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houbin/alarm
|
userOnline/src/push_msg_queue.h
|
<gh_stars>0
#ifndef PUSH_MSG_QUEUE_H_
#define PUSH_MSG_QUEUE_H_
#include <string>
#include "mutex.h"
#include "cond.h"
#include "thread.h"
#include "list"
#include "context.h"
#include <map>
using namespace std;
using namespace util;
class WaitFinishPushMsgQueue;
extern WaitFinishPushMsgQueue g_wait_finish_push_msg_queue;
struct PushMsg
{
int push_mid;
string guid;
string push_msg;
Context *ct;
};
class WaitFinishPushMsgQueue
{
private:
Mutex queue_mutex_;
map<int, PushMsg> wait_finish_msg_queue_;
public:
WaitFinishPushMsgQueue();
~WaitFinishPushMsgQueue();
int SubmitWaitFinishPushMsg(int push_mid, PushMsg push_msg);
int FinishPushMsg(int push_mid, int ret);
};
class PushMsgQueue : public Thread
{
private:
Mutex queue_mutex_;
Cond queue_cond_;
list<PushMsg> push_msg_queue_;
bool stop_;
public:
PushMsgQueue();
~PushMsgQueue();
int SubmitMsg(PushMsg &push_msg);
int Start();
void *Entry();
int Stop();
};
#endif
|
houbin/alarm
|
userOnline/src/init_configure.h
|
<reponame>houbin/alarm<filename>userOnline/src/init_configure.h
/*
* init_log4cxx.h
*
* Created on: 2012-9-12
* Author: yaowei
*/
#ifndef INIT_LOG4CXX_H_
#define INIT_LOG4CXX_H_
#include <string>
class CInitConfig {
public:
CInitConfig();
virtual ~CInitConfig();
public:
void InitLog4cxx(const std::string& project_name);
bool LoadConfiguration(const std::string& project_name);
void SetConfigFilePath(const std::string& config_file_path) {config_file_path_ = config_file_path;};
private:
std::string config_file_path_;
};
#endif /* INIT_LOG4CXX_H_ */
|
houbin/alarm
|
deviceOnline/src/redis_opt.h
|
<filename>deviceOnline/src/redis_opt.h
/*
* CRedisOpt.h
*
* Created on: 2012-11-5
* Author: yaowei
*/
#ifndef CREDISOPT_H_
#define CREDISOPT_H_
#include <set>
#include <hiredis/hiredis.h>
#include "defines.h"
class CRedisOpt {
public:
CRedisOpt();
virtual ~CRedisOpt();
void SetRedisContext(redisContext* conn) { conn_ = conn;}
bool SelectDB(int db_num);
/* string 类型操作 */
bool Set(const std::string& key, const std::string& value);
bool Set(const std::string& key, const int value);
bool Set(const std::string& key, const long value);
bool Get(const std::string& key, std::string& value);
bool MGet(const std::vector<std::string>& vec_key, const std::string& extend_keyname, std::vector<std::string>& vec_value);
bool Incr(const std::string& key);
/* list 类型操作 */
bool LPush(const std::string& key, const std::vector<std::string>& vec_value);
bool LPush(const std::string& key, const std::string& value);
bool RPush(const std::string& key, const std::string& value);
bool LPop(const std::string& key);
bool LLen(const std::string& key, int& len);
bool LRange(const std::string& key, std::vector<std::string>& vec_value);
/* set 类型操作 */
bool SAdd(const std::string& key, const std::vector<std::string>& vec_value);
bool SAdd(const std::string& key, const std::string& value);
bool SAdd(const std::string& key, const std::set<std::string>& set_value);
bool SMembers(const std::string& key, std::vector<std::string>& vec_value);
/* map 类型操作 */
bool Hset(const std::string& key, const std::string& field, const std::string& value);
bool Hset(const std::string& key, const std::string& field, const int value);
bool Hget(const std::string& key, const std::string& field, std::string& value);
bool Hdel(const std::string& key, const std::string& field);
bool Hvals(const std::string& key, std::vector<std::string>& vec_value);
bool HLen(const std::string& key, int& len);
bool Del(const std::string& key);
bool Expire(const std::string& key, const int sec);
bool Exists(const std::string& key);
// need version of redis not lower than 2.8.
// The newest stable version the better.
bool Scan(long long cursor, std::vector<std::string> &vec_keys, long long &next_cursor);
bool Hscan(long long cursor, std::vector<std::string> &vec_keys, long long &next_cursor);
private:
void SafeFreeReplyObject(redisReply *reply)
{
if(reply)
{
freeReplyObject(reply);
reply = NULL;
}
}
void SafeFreeRedisContext(redisContext *conn)
{
if(conn)
{
redisFree(conn);
conn = NULL;
}
}
redisContext *conn_;
redisReply *reply_;
};
#endif /* CCACHED_H_ */
|
houbin/alarm
|
util/http_client.h
|
#ifndef HTTP_CLIENT_H_
#define HTTP_CLIENT_H_
#include <string>
#include <list>
#include <evhttp.h>
#include <event2/event.h>
#include <event2/http.h>
#include <event2/bufferevent.h>
#include "cond.h"
#include "mutex.h"
#include "thread.h"
#include "context.h"
#include "defines.h"
using namespace std;
using namespace util;
extern int g_http_client_mid;
class SendMsg
{
public:
string url_;
string msg_info_;
Context *ct_;
SendMsg(string url, string msg_info, Context *ct = NULL) : url_(url), msg_info_(msg_info) {}
~SendMsg() {}
};
class HttpClient : public Thread
{
public:
HttpClient();
~HttpClient();
int SubmitMsg(SendMsg msg);
int Init();
int Start();
void *Entry();
int Stop();
int ParseUrl(string url, string &scheme, string &host, int &port, string &uri);
int MakeHttpReq(SendMsg send_msg, struct evhttp_request **req);
private:
// 需要发送的消息，如上下线消息
Mutex mutex_;
Cond cond_;
list<SendMsg> dispatch_queue_;
bool stop_;
struct event_base *base_;
};
#endif
|
houbin/alarm
|
deviceOnline/src/local_transport.h
|
<filename>deviceOnline/src/local_transport.h
/*
* local_transport.h
*
* Created on: Mar 7, 2013
* Author: yaowei
*/
#ifndef LOCAL_TRANSPORT_H_
#define LOCAL_TRANSPORT_H_
#include <string>
#include "defines.h"
#include "context.h"
#include <boost/thread.hpp>
#include "libjson/_internal/Source/JSONNode.h"
class PushMsgRespContext : public util::Context
{
private:
int recv_sfd_;
int recv_cnt_;
JSONNode param_node_;
public:
PushMsgRespContext(int recv_sfd, int recv_cnt);
~PushMsgRespContext();
int SetParamNode(JSONNode ¶m_node);
void Finish(int ret);
};
class CLocalTransport
{
public:
static CLocalTransport* GetInstance();
void SetupLocalTransport();
private:
bool InitLocalListenSocket(evutil_socket_t& listen_socket);
void CreateThreadForListenLocal(void *(*func)(void *), void *arg);
static void *ReadLibevent(void *arg);
static void AcceptCb(evutil_socket_t listen_socket, short event, void* arg);
static void ReadCb(struct bufferevent *bev, void *arg);
static void ErrorCb(struct bufferevent *bev, short event, void *arg);
static void HandleMsg(LOCAL_REV_DATA *ptr_data, std::string reply_msg_str);
private:
evutil_socket_t sfd_;
static CLocalTransport* local_transport_ptr_;
struct event_base *main_base_;
struct event *local_listen_event_;
evutil_socket_t local_listen_socket_;
static std::map<int, int> map_logic_sfd_; //连接分发进程的业务进程sfd-->业务进程标识
static boost::mutex mutex_;
};
#endif /* LOCAL_TRANSPORT_H_ */
|
houbin/alarm
|
voice_server/util/env.h
|
#ifndef UTIL_ENV_H_
#define UTIL_ENV_H_
#include <stdint.h>
#include "slice.h"
namespace util
{
// copy from leveldb
// A file abstraction for sequentail writing. The implementation
// must provide buffering since callers may append fragments
// at a time to the file
class WritableFile
{
public:
WritableFile() {};
virtual ~WritableFile() { }
virtual int32_t Append(const Slice& data) = 0;
virtual int32_t Close() = 0;
virtual int32_t Flush() = 0;
virtual int32_t Sync() = 0;
private:
WritableFile(const WritableFile&);
void operator=(const WritableFile&);
};
}
#endif
|
houbin/alarm
|
voice_server/util/thread.h
|
<filename>voice_server/util/thread.h
#ifndef UTIL_THREAD_H_
#define UTIL_THREAD_H_
#include <pthread.h>
namespace util
{
class Thread
{
private:
pthread_t thread_id_;
public:
Thread();
virtual ~Thread();
bool IsStarted() const;
void Create(size_t stack_size = 0);
int Join(void **ret = 0);
int Detach();
int Kill(int sig);
virtual void* Entry() = 0;
static void *EntryWrap(void *arg);
};
}
#endif
|
houbin/alarm
|
deviceOnline/src/push_msg_queue.h
|
<reponame>houbin/alarm
#ifndef PUSH_MSG_QUEUE_
#define PUSH_MSG_QUEUE_
#include <string>
#include "mutex.h"
#include "cond.h"
#include "thread.h"
#include "list"
#include "context.h"
#include <map>
#include "libjson/_internal/Source/JSONNode.h"
using namespace std;
using namespace util;
class WaitFinishPushMsgQueue;
extern WaitFinishPushMsgQueue g_wait_finish_push_msg_queue;
struct PushMsg
{
int push_cnt; //推送出去的消息号
string dev_id;
string push_msg;
Context *ct;
};
class WaitFinishPushMsgQueue
{
private:
Mutex queue_mutex_;
map<int, PushMsg> wait_finish_msg_queue_;
public:
WaitFinishPushMsgQueue();
~WaitFinishPushMsgQueue();
int SubmitWaitFinishPushMsg(int push_cnt, PushMsg push_msg);
int FinishPushMsg(int push_cnt, int ret, JSONNode ¶m_node);
};
class PushMsgQueue : public Thread
{
private:
Mutex queue_mutex_;
Cond queue_cond_;
list<PushMsg> push_msg_queue_;
bool stop_;
public:
PushMsgQueue();
~PushMsgQueue();
int SubmitMsg(PushMsg &push_msg);
int Start();
void *Entry();
int Stop();
};
#endif
|
houbin/alarm
|
public/redis_key.h
|
#ifndef REDIS_KEY_H
#define REDIS_KEY_H
#include <string>
enum DB_NUMBER
{
SESSION = 0,
STATUS = 2,
REDIS_DEVICE_INFO = 6,
REDIS_CLIENT_INFO = 7
};
#define REDIS_FIELD_FD "fd"
#define REDIS_FIELD_PUBLIC_ADDR "public_addr"
#define REDIS_FIELD_PRIVATE_ADDR "private_addr"
#define REDIS_FIELD_DEV_IP "dev_ip"
static inline std::string int2str(int v)
{
std::stringstream ss;
ss << v;
return ss.str();
}
#define ONLINE_FLAG ":onlineflag"
inline std::string RedisKeyUserOnlineFlag(const std::string& username)
{ return username + std::string(ONLINE_FLAG);}
#define CLIENT_LOGIN_INFO ":loginclientinfo"
#define KEY_LOGIN_PLATFORM ":platform"
#define KEY_MOBILE_ID ":moblieid"
#define KEY_LANGUAGE_TYPE ":langt"
#define KEY_ALARM_FLAG ":alarm"
inline std::string RedisKeyClientLoginInfo(const std::string& username)
{ return username + std::string(CLIENT_LOGIN_INFO);}
#define ONLINE_SERVER_INFO ":s_info"
#define KEY_ONLINE_SERVER_NO ":s_no"
#define KEY_ONLINE_SERVER_FD ":s_fd"
#define KEY_ONLINE_SERVER_FD_ID ":s_fd_id"
inline std::string RedisKeyUserOnlineServerInfo(const std::string& username)
{ return username + std::string(ONLINE_SERVER_INFO);}
#define REDIS_DEVICE_LIST ":devicelist"
inline std::string RedisKeyDevicelist(const std::string& username)
{ return username + std::string(REDIS_DEVICE_LIST);}
#define ONLINE_FLAG ":onlineflag"
inline std::string RedisKeyDeviceOnlineFlag(const std::string& device_guid)
{ return device_guid + std::string(ONLINE_FLAG);}
#define ONLINE_SERVER_INFO ":s_info"
#define KEY_ONLINE_SERVER_NO ":s_no"
#define KEY_ONLINE_SERVER_FD ":s_fd"
#define KEY_ONLINE_SERVER_FD_ID ":s_fd_id"
inline std::string RedisKeyDeviceOnlineServerInfo(const std::string& device_guid)
{ return device_guid + std::string(ONLINE_SERVER_INFO);}
#define REDIS_GROUP_ID(id) id + std::string(":groupid")
inline std::string RedisKeySfd2Device(const int server_no, const int sfd)
{return int2str(server_no) + std::string("&") +int2str(sfd);}
#define REDIS_KEY_DEVICE_CHANGE ":dc"
inline std::string RedisKeyDeviceChange(const std::string& device_guid)
{ return device_guid + std::string(REDIS_KEY_DEVICE_CHANGE);}
#define REDIS_ALL_DEVICES_RELATED_USER ":adru"
inline std::string RedisKeyAllDevicesRelatedUser(const std::string& username)
{ return username + std::string(REDIS_ALL_DEVICES_RELATED_USER);}
inline std::string RedisKeyDeviceHumiture(const std::string& device_guid, const std::string& timestamp)
{ return device_guid + std::string("&") + timestamp; }
#define REDIS_HASH_FEILD_TEMPERATURE "temperature"
#define REDIS_HASH_FEILD_HUMIDNESS "humidity"
#define REDIS_LATEST_HUMITURE_KEY ":latesthumiturekey"
inline std::string RedisKeyLatestDeviceHumitureKey(const std::string& device_guid)
{ return device_guid + std::string(REDIS_LATEST_HUMITURE_KEY); }
inline std::string RedisKeyDeviceApConfFlag(const std::string& device_guid)
{ return device_guid + std::string(":apconf"); }
#define REDIS_DEVICE_USER_KEY ":deviceuser"
inline std::string RedisKeyDeviceUserKey(const std::string& device_guid)
{ return device_guid + std::string(REDIS_DEVICE_USER_KEY); }
#endif
|
houbin/alarm
|
voice_server/src/worker.h
|
<gh_stars>0
#ifndef TCP_SERVER_WORKER_H_
#define TCP_SERVER_WORKER_H_
#include <deque>
#include "../util/thread.h"
#include "global.h"
using namespace util;
using namespace std;
enum
{
D_TIMEOUT,
D_CLOSE,
D_ERROR
};
struct ConnectionInfo;
class Master;
class Dispatcher;
class Worker : public Thread
{
public:
Worker(int i, uint32_t worker_conn_count, int read_timeout, int write_timeout, Master *master);
~Worker();
int32_t Init();
int32_t Start();
void *Entry();
void Wait();
void Shutdown();
int GetId();
int GetNotifiedWFd();
void RecvNotifiedCb(int fd, short event, void *arg);
int32_t PutConnInfo(ConnectionInfo *conn_info);
string GetDataProtocol();
Dispatcher* GetDispatcher();
private:
int id_;
struct event_base *base_;
int notified_wfd_;
int notified_rfd_;
struct event *notified_event_;
uint32_t worker_conn_count_;
uint32_t current_conn_count_;
int read_timeout_;
int write_timeout_;
Master *master_;
Mutex conn_info_queue_mutex_;
deque<ConnectionInfo*> conn_info_queue_;
};
#endif
|
houbin/alarm
|
userOnline/src/logic_opt.h
|
/*
* message_opt.h
*
* Created on: Mar 18, 2013
* Author: yaowei
*/
#ifndef MESSAGE_OPT_H_
#define MESSAGE_OPT_H_
#include "defines.h"
#include "redis_opt.h"
#include "../../public/message.h"
#include "../../public/user_interface_defines.h"
using namespace std;
class CJsonOpt;
class CRedisOpt;
class CLogicOpt
{
public:
explicit CLogicOpt(conn* c);
virtual ~CLogicOpt();
void StartLogicOpt(const std::string& message);
int CheckSessionId(string guid);
static int SetGuidFdCache(std::string guid, int fd);
static int GetGuidFdFromCache(std::string guid, int &fd);
static int RemoveGuidFdFromCache(std::string guid);
private:
int UserBeacon();
int HandlePushMsgResp();
private:
CJsonOpt* jsonOpt_ptr_;
int result_;
conn* conn_;
std::string responseToClient_;
};
#endif /* MESSAGE_OPT_H_ */
|
houbin/alarm
|
public/message.h
|
#ifndef MESSAGE_H
#define MESSAGE_H
#define TOKEN_LENGTH 5
#define TOKEN_STR "@<PASSWORD>"
/* JK(JSON KEY) */
#define PROTO_VERSION "1.0"
#define JK_MESSAGE_ID "mid"
#define JK_CLIENT_TYPE "ct"
#define JK_PROTO_VERSION "pv"
#define JK_PARAM "param"
#define JK_ID "id"
#define JK_LOGIC_PROCESS_TYPE "lpt"
#define JK_RESULT "rt"
#define JK_CLINET_SFD "cfd"
#define JK_CLINET_SFD_ID "cfdid"
#define JK_SOFT_VERSION "softver"
#define JK_SOFT_VERSION_ADDR "softveraddr"
#define JK_SOFT_VERSION_DESP "softverdesp"
#define JK_SESSION_ID "sid"
#define JK_CUSTOM_TYPE "custom_type"
#define JK_USERNAME "username"
#define JK_NEW_USERNAME "newusername"
#define JK_PASSWORD "password"
#define JK_NEW_PASSWORD "<PASSWORD>"
#define JK_PEER_USERNAME "pusername"
#define JK_MAIL_OR_PHONE "mop"
#define JK_MAIL "mail"
#define JK_PHONE "phone"
#define JK_NICKNAME "nkname"
#define JK_USER_OTHER_INFO "uoi"
#define JK_SECURITY_MAIL "sm"
#define JK_CLIENT_LOGIN_INFO "cli"
#define JK_CLIENT_LOGIN_PLATFORM "clp"
#define JK_LOGIN_MOBILE_ID "lmi"
#define JK_FEEDBACK "fb"
#define JK_LANGUAGE_TYPE "langt"
#define JK_TERMINAL_TYPE "tt"
#define JK_USER_ONLINE_STATUS "uls"
#define JK_IM_SERVER_NO "isn"
#define JK_RELAY_MESSAGE "rm"
#define JK_RELAY_MESSAGE_GUID "rmg"
#define JK_RELAY_MESSAGE_TIMESTAMP "rmt"
#define JK_CUSTOM_STRING "cs"
/*从IM服务器发送到转发服务器的消息类型，是请求中转的消息 还是 中转消息的发送结果（用于确认是否删除消息队列中的已存储消息）*/
#define JK_P2RELAY_MESSAGE_TYPE "p2rmt"
#define JK_ONLINE_SERVER_NO "osn"
#define JK_ONLINE_SERVER_FD "osf"
#define JK_ONLINE_SERVER_FD_ID "osfi"
#define JK_CREATE_TIME "ct"
#define JK_PUSH_MESSAGE_TYPE "pmt"
#define JK_OPTION "option"
#define JK_CUSTOM_STRING "cs"
#define JK_ACCOUNT_LIVE_INFO "ali"
#define JK_ALARM_FLAG "af"
#define JK_CLIENT_VERSION "cv"
#define JK_UPDATE_FILE_INFO "ufi"
#define JK_FILE_VERSION "fv"
#define JK_FILE_URL "fu"
#define JK_FILE_SIZE "fs"
#define JK_FILE_DESCRIPTION "fd"
#define JK_FILE_CHECKSUM "fc"
/* 自动更新 */
#define JK_APP_CURRENT_VERSION "crtver"
#define JK_APP_VERSION "appver"
#define JK_APP_VERSION_FULL "appfullver"
#define JK_APP_VERSION_URL "appverurl"
#define JK_APP_VERSION_DESC "appverdesc"
#define JK_APP_CLIENT_TYPE "appclit"
/* 设备服务相关 */
#define JK_DEVICES_CHANGE "dc"
#define JK_DEVICE_INFO "dinfo"
#define JK_DEVICE_LIST "dlist"
#define JK_SERVER_TYPE "srvtype"
#define JK_DEVICE_GUID "dguid"
#define JK_DEVICE_TYPE "dtype"
#define JK_DEVICE_SUB_TYPE "dstype"
#define JK_DEVICE_SUB_TYPE_INT "dstypeint"
#define JK_DEVICE_USERNAME "dusername"
#define JK_DEVICE_PASSWORD "<PASSWORD>"
#define JK_DEVICE_NAME "dname"
#define JK_DEVICE_IP "dip"
#define JK_DEVICE_PORT "dport"
#define JK_DEVICE_NET_STATE "dnst"
#define JK_NET_STORAGE_SWITCH "netss"
#define JK_TF_STORAGE_SWITCH "tfss"
#define JK_ALARM_SWITCH "aswitch"
#define JK_ALARM_VIDEO_FTP "avftp"
#define JK_ALARM_SNAP_FTP "asnapftp"
#define JK_ALARM_FTP_ACC "aftpacc"
#define JK_ALARM_FTP_PWD "<PASSWORD>"
#define JK_ALARM_TIME "atime"
#define JK_PIC_FTP_BIG "dpicb"
#define JK_PIC_FTP_SMALL "dpics"
#define JK_PIC_FTP_ACC "dpicacc"
#define JK_PIC_FTP_PWD "<PASSWORD>"
#define JK_PIC_UPLOAD_TIMEING "dpicut"
#define JK_VIDEO_FLUENCY "dvfluency"
#define JK_VIDEO_LINK_TYPE "dvlt"
#define JK_DEVICE_VIDEO_USERNAME "dvusername"
#define JK_DEVICE_VIDEO_PASSWORD "<PASSWORD>"
#define JK_DEVICE_VIDEO_IP "dvip"
#define JK_DEVICE_VIDEO_PORT "dvport"
#define JK_DEVICE_VIDEO_TCP "dvtcp"
#define JK_DEVICE_SOFT_VERSION "dsv"
#define JK_DEVICE_BABY_MODE "dbbm"
#define JK_DEVICE_FULL_ALARM_MODE "dfam"
#define JK_DEVICE_RESET_FLAG "drf"
#define JK_DEVICE_VERIFY "dverify"
#define JK_DEVICE_CHANNEL_SUM "dcs"
#define JK_DEVICE_CHANNEL_NO "dcn"
#define JK_DEVICE_CHANNEL_NAME "dcname"
#define JK_CHANNEL_LIST "clist"
#define JK_DEVICE_WIFI_FLAG "dwifi"
#define JK_DEVICE_RELATION_NUM "drn"
#define JK_DEVICE_NAME_RESULT "dnamers"
#define JK_NET_STORAGE_SWITCH_RESULT "netssrs"
#define JK_TF_STORAGE_SWITCH_RESULT "tfssrs"
#define JK_ALARM_SWITCH_RESULT "aswitchrs"
#define JK_ALARM_VIDEO_FTP_RESULT "avftprs"
#define JK_ALARM_SNAP_FTP_RESULT "asnapftprs"
#define JK_ALARM_FTP_ACC_RESULT "aftpaccrs"
#define JK_ALARM_FTP_PWD_RESULT "<PASSWORD>"
#define JK_ALARM_TIME_RESULT "atimers"
#define JK_PIC_FTP_BIG_RESULT "dpicbrs"
#define JK_PIC_FTP_SMALL_RESULT "dpicsrs"
#define JK_PIC_FTP_ACC_RESULT "dpicaccrs"
#define JK_PIC_FTP_PWD_RESULT "<PASSWORD>"
#define JK_PIC_UPLOAD_TIMEING_RESULT "dpicutrs"
#define JK_VIDEO_FLUENCY_RESULT "dvfluencyrs"
#define JK_DEVICE_BABY_MODE_RESULT "dbbmrs"
#define JK_DEVICE_FULL_ALARM_MODE_RESULT "dfamrs"
#define JK_DEVICE_HUMITURE_FLAG "dhflag"
#define JK_DEVICE_TEMPERATURE "dtem"
#define JK_DEVICE_HUMIDNESS "dhum"
#define JK_DEVICE_TIMESTAMP "dts"
#define JK_DEVICE_HUMITURE_LIST "dhlist"
#define JK_DEVICE_HUMITURE_DATE "dhdate"
#define JK_DEVICE_HUMITURE_HOUR "dhour"
#define JK_DEVICE_HUMITURE_NUM "dhnum"
#define JK_DEVICE_ENV_SCORE "descore" // 综合环境健康指数评分
#define JK_DEVICE_HUMITURE_SCORE "dhscore" // 温湿度评分
#define JK_DEVICE_HUMITURE_TOP "dhtop"
#define JK_DEVICE_HUMITURE_LAST_SCORE "dhlscore"
#define JK_DEVICE_HUMITURE_LAST_TOP "dhltop"
#define JK_DEVICE_HUMITURE_RATIO "dhratio"
#define JK_DEVICE_HUMITURE_ASSESSMENT "dhass"
#define JK_DEVICES_ONLINE_STATUS "dsls"
#define JK_DEVICE_IM_ONLINE_STATUS "dimols"
#define JK_ONLINE_STATUS "ols"
#define JK_DEVICES_PIC "dspic"
#define JK_DEMO_POINT_SERVER "dps"
#define JK_DEVICE_BIND_TYPE "dbt"
// 设备升级
#define JK_UPGRADE_FILE_VERSION "ufver"
#define JK_UPGRADE_FILE_URL "ufurl"
#define JK_UPGRADE_FILE_DESCRIPTION "ufdes"
#define JK_UPGRADE_FILE_SIZE "ufsize"
#define JK_UPGRADE_FILE_CHECKSUM "ufc"
#define JK_UPGRADE_DOWNLOAD_STEP "udstep"
#define JK_UPGRADE_WRITE_STEP "uwstep"
// 设备报警
#define JK_ALARM_GUID "aguid"
#define JK_ALARM_SOLUTION "asln"
#define JK_ALARM_MESSAGE_TYPE "amt"
#define JK_ALARM_STATUS "astatus"
#define JK_ALARM_TYPE "atype"
#define JK_ALARM_PIC "apic"
#define JK_ALARM_PIC_SIZE "apicsz"
#define JK_ALARM_VIDEO "avd"
#define JK_ALARM_VIDEO_SZIE "avdsz"
#define JK_ALARM_MESSAGE "amsg"
#define JK_ALARM_TIMESTAMP "ats"
#define JK_ALARM_TIMESTAMP_STR "atss"
#define JK_ALARM_INDEX_START "aistart"
#define JK_ALARM_INDEX_STOP "aistop"
#define JK_ALARM_INFO "ainfo"
#define JK_ALARM_ERROR "aerror"
//设备报警-FTP模式
#define JK_ALARM_FTP_GUID "aguid"
#define JK_ALARM_FTP_MESSAGE_TYPE "amt"
#define JK_ALARM_FTP_DEVICE_GUID "dguid"
#define JK_ALARM_FTP_TIMESTAMP "ats"
#define JK_ALARM_FTP_DEVICE_NAME "dname"
#define JK_ALARM_FTP_CHANNEL_NO "dcn"
#define JK_ALARM_FTP_TYPE "atype"
#define JK_ALARM_FTP_PIC "apic"
#define JK_ALARM_FTP_PIC_SIZE "apicsz"
#define JK_ALARM_FTP_VIDEO "avd"
#define JK_ALARM_FTP_VIDEO_SZIE "avdsz"
// 报警在线推送
#define JK_ALARM_SEND_ACCOUNT "accountname"
#define JK_ALARM_SEND_GUID "alarmguid"
#define JK_ALARM_SEND_CLOUDNUM "cloudnum"
#define JK_ALARM_SEND_CLOUDNAME "cloudname"
#define JK_ALARM_SEND_CLOUDCHN "cloudchn"
#define JK_ALARM_SEND_ALARMTYPE "alarmtype"
#define JK_ALARM_SEND_ALARMLEVEL "alarmlevel"
#define JK_ALARM_SEND_ALARMTIME "alarmtime"
#define JK_ALARM_SEND_PICURL "picurl"
#define JK_ALARM_SEND_VIDEOURL "videourl"
// 广告平台
#define JK_PRODUCT_TYPE "prot"
#define JK_AD_VERSION "adver"
#define JK_AD_INFO "adinfo"
#define JK_AD_NO "adno"
#define JK_AD_URL "adurl"
#define JK_AD_LINK "adl"
#define JK_AD_URL_EN "adurlen"
#define JK_AD_LINK_EN "adlen"
#define JK_AD_URL_ZHT "adurlzht"
#define JK_AD_LINK_ZHT "adlzht"
#define JK_PORTAL_VERSION "porver"
#define JK_PORTAL "por"
#define JK_PORTAL_EN "poren"
#define JK_PORTAL_ZHT "porzht"
#define JK_PORTAL_SIZE "psize"
#define JK_PUB_INDEX_START "pistart"
#define JK_PUB_COUNT "pcount"
#define JK_PUB_TIME "ptime"
#define JK_PUB_INFO "pinfo"
#define JK_PUB_LIST "plist"
// 增值服务
#define JK_STREAMING_MEDIA_SERVER "smsrv"
#define JK_STREAMING_MEDIA_TIME "smt"
#define JK_STREAMING_MEDIA_CHANNELS "smcs"
#define JK_STREAMING_MEDIA_FLAG "sm"
#define JK_STREAMING_MEDIA_SHARE "sms"
#define JK_CLOUD_STORAGE_FLAG "csf"
#define JK_CLOUD_STORAGE_TIME "cst"
#define JK_CLOUD_STORAGE_CHANNELS "cscs"
#define JK_CLOUD_STORAGE_HOST "cshost"
#define JK_CLOUD_STORAGE_ID "csid"
#define JK_CLOUD_STORAGE_KEY "cskey"
#define JK_CLOUD_STORAGE_SPACE "csspace"
#define JK_CLOUD_STORAGE_TYPE "cstype"
#define JK_SHARED_SERVER "ssrv"
#define JK_SHARE_CHANNELS "scs"
#define JK_RTMP_PORT "rtmp"
#define JK_HLS_PORT "hls"
#define JK_STREAMING_MEDIA_SUPPORT "smspt"
#define JK_CLOUD_STORAGE_SUPPORT "csspt"
#define JK_CLOUD_STORAGE_RESULT "csrs"
/* 报警服务器的消息类型 */
typedef enum alarm_client_messageid
{
MID_RESPONSE_PUSHALARM = 1000, /* 告警服务器向客户端推送报警信息 */
MID_REQUEST_ALARMPICURL = 1001, /* 客户端获取报警图片的url地址 */
MID_RESPONSE_ALARMPICURL = 1002, /* 服务器向客户端发送报警图片的url地址 */
MID_REQUEST_ALARMVIDEOURL = 1003, /* 客户端获取报警视频的url地址 */
MID_RESPONSE_ALARMVIDEOURL = 1004, /* 服务器向客户端发送报警视频的url地址 */
MID_REQUEST_ALARMHISTORY = 1005, /* 客户端获取报警的历史记录 */
MID_RESPONSE_ALARMHISTORY = 1006, /* 服务器向客户端发送报警的历史记录 */
MID_REQUEST_REMOVEALARM = 1007, /* 客户端发送删除报警信息 */
MID_RESPONSE_REMOVEALARM = 1008, /* 服务器向客户端发发送删除报警信息的结果 */
MID_RESPONSE_PUSHALARMCOUNT = 1009 /* 告警服务器向客户端推送某一时间段的报警条数 */
} alarm_client_messageid_t;
/** Message Type */
enum AccountSystemMessageType
{
IS_USER_EXIST = 1000,
IS_USER_EXIST_RESPONSE = 1001,
USER_REGISTER = 1002,
USER_REGISTER_RESPONSE = 1003,
LOGIN = 1004,
LOGIN_RESPONSE = 1005,
LOGOUT = 1006,
LOGOUT_RESPONSE = 1007,
MODIFY_USERPASS = 1008,
MODIFY_USERPASS_RESPONSE = 1009,
RESET_PASSWORD_NOSESSION = 1010,
RESET_PASSWORD_NOSESSION_RESPONSE = 1011,
SEND_FEEDBACK_TO_MAIL = 1012,
SEND_FEEDBACK_TO_MAIL_RESPONSE = 1013,
SEND_RESET_PASSWORD_MAIL = 1014,
SEND_RESET_PASSWORD_MAIL_RESPONSE = 1015,
GET_USER_DETAIL_INFO = 1016,
GET_USER_DETAIL_INFO_RESPONSE = 1017,
VERIFY_USERPASS = 1018,
VERIFY_USERPASS_RESPONSE = 1019,
GET_ALARM_FLAG = 1020,
GET_ALARM_FLAG_RESPONSE = 1021,
SET_ALARM_FLAG = 1022,
SET_ALARM_FLAG_RESPONSE = 1023,
BIND_MAIL_OR_PHONE = 1024,
BIND_MAIL_OR_PHONE_RESPONSE = 1025,
REPORT_CLIENT_PLATFORM_INFO = 1026,
REPORT_CLIENT_PLATFORM_INFO_RESPONSE = 1027,
RESET_USERNAME_PASSWORD = <PASSWORD>,
RESET_USERNAME_PASSWORD_RESPONSE = 1029,
JUDGE_USER_PASSWORD_STRENGTH = 1030,
JUDGE_USER_PASSWORD_STRENGTH_RESPONSE = 1031,
RESET_PASSWORD_BY_MOBILE = 1032,
RESET_PASSWORD_BY_MOBILE_RESPONSE = 1033,
SET_ACCOUNT_INFO = 1034,
SET_ACCOUNT_INFO_RESPONSE = 1035,
GET_ACCOUNT_INFO = 1036,
GET_ACCOUNT_INFO_RESPONSE = 1037,
GET_ACCOUNT_MAILPHONE_NOSESSEION = 1038,
GET_ACCOUNT_MAILPHONE_NOSESSEION_RESPONSE = 1039,
RESET_PASSWORD=<PASSWORD>,
RESET_PASSWORD_RESPONSE=1041
};
enum AutoUpdateSystemMessageType
{
GET_SOFT_VERSION = 5000,
GET_SOFT_VERSION_RESPONSE = 5001,
};
enum IMServerMessageType
{
USER_ONLINE = 3000,
USER_ONLINE_RESPONSE = 3001,
GET_LIVE_STATUS = 3002,
GET_LIVE_STATUS_RESPONSE = 3003,
SET_ONLINE_STATUS = 3004,
SET_ONLINE_STATUS_RESPONSE = 3005,
PUSH_DEVICE_MODIFY_INFO = 3006,
PUSH_DEVICE_MODIFY_INFO_RESPONSE = 3007,
PUSH_DEVICE_UPDATE_CMD = 3012,
PUSH_DEVICE_UPDATE_CMD_RESPONSE = 3013,
PUSH_DEVICE_CANCEL_CMD = 3014,
PUSH_DEVICE_CANCEL_CMD_RESPONSE = 3015,
GET_UPDATE_DOWNLOAD_STEP = 3016,
GET_UPDATE_DOWNLOAD_STEP_RESPONSE = 3017,
GET_UPDATE_WRITE_STEP = 3018,
GET_UPDATE_WRITE_STEP_RESPONSE = 3019,
PUSH_DEVICE_REBOOT_CMD = 3020,
PUSH_DEVICE_REBOOT_CMD_RESPONSE = 3021,
PUSH_DEVICE_MODIFY_PASSWORD = 3022,
PUSH_DEVICE_MODIFY_PASSWORD_RESPONSE = 3023,
PUSH_STREAMINGMEDIA_OPEN = 3024,
PUSH_STREAMINGMEDIA_OPEN_RESPONSE = 3025,
PUSH_STREAMINGMEDIA_CLOSE = 3026,
PUSH_STREAMINGMEDIA_CLOSE_RESPONSE = 3027,
PUSH_SHARE_OPEN = 3028,
PUSH_SHARE_OPEN_RESPONSE = 3029,
PUSH_SHARE_CLOSE = 3030,
PUSH_SHARE_CLOSE_RESPONSE = 3031,
PUSH_DEV_USER_OFFLINE = 3032,
PUSH_DEV_USER_OFFLINE_RESPONSE = 3033,
PUSH_CLOUD_STORAGE_OPEN = 3034,
PUSH_CLOUD_STORAGE_OPEN_RESPONSE = 3035,
};
enum P2RelayMessageType
{
HEATBEAT_DETECT = 4000,
HEATBEAT_DETECT_RESPONSE = 4001,
};
enum AlarmMsgType
{
GET_ALARM_INFO = 6000,
GET_ALARM_INFO_RESPONSE = 6001,
DEL_ALARM_INFO = 6002,
DEL_ALARM_INFO_RESPONSE = 6003,
CLEAN_ALARM_INFO = 6004,
CLEAN_ALARM_INFO_RESPONSE = 6005,
};
enum IM2RelayMessageType
{
NOTIFY_OFFLINE = 4300,
RELAY_NOTIFY_OFFLINE = 4301,
RELAY_DEVICE_MODIFY_INFO = 4302,
RELAY_DEVICE_MODIFY_RESULT = 4303,
RELAY_DEVICE_UPDATE_CMD = 4304,
RELAY_DEVICE_UPDATE_CMD_RESULT = 4305,
RELAY_DEVICE_CANCEL_CMD = 4306,
RELAY_DEVICE_CANCEL_CMD_RESULT = 4307,
RELAY_GET_DEVICE_UPDATE_STEP = 4308,
RELAY_GET_DEVICE_UPDATE_STEP_RESULT = 4309,
RELAY_DEVICE_REBOOT_CMD = 4310,
RELAY_DEVICE_REBOOT_CMD_RESULT = 4311,
RELAY_DEVICE_MODIFY_PASSWORD = <PASSWORD>,
RELAY_DEVICE_MODIFY_PASSWORD_RESULT = 4313,
RELAY_STREAMINGMEDIA_OPEN = 4314,
RELAY_STREAMINGMEDIA_CLOSE = 4315,
RELAY_SHARE_OPEN = 4316,
RELAY_SHARE_CLOSE = 4317,
RELAY_CLOUDSTORAGE_OPEN = 4318,
RELAY_CLOUDSTORAGE_CLOSE = 4319,
RELAY_DEV_USER_ONLINE = 4320,
RELAY_DEV_USER_OFFLINE = 4321,
RELAY_CLOUD_STORAGE_OPEN = 4322,
};
enum Alarm2RelayMessageType
{
GET_ACCOUNT_LIVE_INFO = 4600,
GET_ACCOUNT_LIVE_INFO_RESPONSE = 4601,
SEND_MESSAGE_TO_USER = 4602,
SEND_MESSAGE_TO_USER_RESPONSE = 4603,
RELAY_ALARM_MESSAGE = 4604,
RELAY_ALARM_MESSAGE_RESPONSE = 4605,
};
/** 设备基础信息服务 */
enum MessageType_DeviceInfo
{
DEVICE_REGISTER = 2001,
DEVICE_REGISTER_RESPONSE = 2002,
GET_USER_DEVICES = 2003,
GET_USER_DEVICES_RESPONSE = 2004,
GET_DEVICE_INFO = 2005,
GET_DEVICE_INFO_RESPONSE = 2006,
MODIFY_DEVICE_CONF_INFO = 2007,
MODIFY_DEVICE_CONF_INFO_RESPONSE = 2008,
GET_DEVICE_ONLINE_STATE = 2009,
GET_DEVICE_ONLINE_STATE_RESPONSE = 2010,
GET_DEVICE_PIC = 2011,
GET_DEVICE_PIC_RESPONSE = 2012,
MODIFY_DEVICE_INFO_VIDEO_LINK = 2013,
MODIFY_DEVICE_INFO_VIDEO_LINK_RESPONSE = 2014,
USER_BIND_DEVICE = 2015,
USER_BIND_DEVICE_RESPONSE = 2016,
USER_REMOVE_BIND_DEVICE = 2017,
USER_REMOVE_BIND_DEVICE_RESPONSE = 2018,
GET_USER_DEVICE_INFO = 2019,
GET_USER_DEVICE_INFO_RESPONSE = 2020,
GET_DEVICE_HUMITURE_STAT = 2021,
GET_DEVICE_HUMITURE_STAT_RESPONSE = 2022,
GET_DEVICE_HUMITURE_ONTIME = 2023,
GET_DEVICE_HUMITURE_ONTIME_RESPONSE = 2024,
GET_USER_DEVICES_STATUS_INFO = 2025,
GET_USER_DEVICES_STATUS_INFO_RESPONSE = 2026,
GET_DEVICE_HUMITURE_SCORE = 2027,
GET_DEVICE_HUMITURE_SCORE_RESPONSE = 2028,
GET_DEVICE_USERNAMES = 2029,
GET_DEVICE_USERNAMES_RESPONSE = 2030,
MODIFY_DEVICE_INFO_ADVANCED = 2031,
MODIFY_DEVICE_INFO_ADVANCED_RESPONSE = 2032,
GET_DEVICE_UPDATE_INFO = 2033,
GET_DEVICE_UPDATE_INFO_RESPONSE = 2034,
MODIFY_DEVICE_PASSWORD = <PASSWORD>,
MODIFY_DEVICE_PASSWORD_RESPONSE = 2036,
DEVICE_SHARE = 2037,
DEVICE_SHARE_RESPONSE = 2038,
ADD_DEVICE_CHANNEL = 2039,
ADD_DEVICE_CHANNEL_RESPONSE = 2040,
DELETE_DEVICE_CHANNEL = 2041,
DELETE_DEVICE_CHANNEL_RESPONSE = 2042,
GET_DEVICE_CHANNEL = 2043,
GET_DEVICE_CHANNEL_RESPONSE = 2044,
MODIFY_DEVICE_CHANNEL_NAME = 2045,
MODIFY_DEVICE_CHANNEL_NAME_RESPONSE = 2046,
GET_DEVICE_RELATION_NUM = 2047,
GET_DEVICE_RELATION_NUM_RESPONSE = 2048,
MODIFY_DEVICE_WIFI_FLAG = 2047,
MODIFY_DEVICE_WIFI_FLAG_RESPONSE = 2048,
SET_AP_CONF_FLAG = 2049,
SET_AP_CONF_FLAG_RESPONSE = 2050,
GET_USER_CHANNELS = 2049,
GET_USER_CHANNELS_RESPONSE = 2050,
CHECK_DEVICE_BIND_STATE = 2051,
CHECK_DEVICE_BIND_STATE_RESPONSE = 2052,
REPORT_DEVICE_CLOUDSEE_ONLINE = 2053,
REPORT_DEVICE_CLOUDSEE_ONLINE_RESPONSE = 2054,
REPORT_DEVICE_RESET = 2055,
REPORT_DEVICE_RESET_RESPONSE = 2056,
GET_DEMO_POINT = 2057,
GET_DEMO_POINT_RESPONSE = 2058,
GET_DEMO_POINT_SERVER = 2059,
GET_DEMO_POINT_SERVER_RESPONSE = 2060,
};
/** 设备在线服务 */
enum MessageType_DeviceOnline
{
DEVICE_ONLINE = 2201,
DEVICE_ONLINE_RESPONSE = 2202,
DEVICE_HEARTBEAT = 2203,
DEVICE_HEARTBEAT_RESPONSE = 2204,
DEVICE_OFFLINE = 2205,
DEVICE_OFFLINE_RESPONSE = 2206,
DEVICE_REPORT_HUMITURE = 2207,
DEVICE_REPORT_HUMITURE_RESPONSE = 2208,
PUSH_DEVICE_MODIFY_RESULT = 2209,
PUSH_DEVICE_MODIFY_RESULT_RESPONSE = 2210,
PUSH_DEVICE_UPDATE_CMD_RESULT = 2211,
PUSH_DEVICE_UPDATE_CMD_RESULT_RESPONSE = 2212,
PUSH_DEVICE_CANCEL_CMD_RESULT = 2213,
PUSH_DEVICE_CANCEL_CMD_RESULT_RESPONSE = 2214,
GET_DEVICE_UPDATE_STEP_RESULT = 2215,
GET_DEVICE_UPDATE_STEP_RESULT_RESPONSE = 2216,
PUSH_DEVICE_MODIFY_PASSWORD_RESULT = 2217,
PUSH_DEVICE_MODIFY_PASSWORD_RESULT_RESPONSE = 2218,
PUSH_ALARM_MESSAGE = 2219,
PUSH_ALARM_MESSAGE_RESPONSE = 2220,
PUSH_ALARM_MESSAGE_FTP = 2221,
PUSH_ALARM_MESSAGE_FTP_RESPONSE = 2222,
PUSH_ALARM_MESSAGE_CLOUD = 2223,
PUSH_ALARM_MESSAGE_CLOUD_RESPONSE = 2224,
DEVICE_REGISTER_ONLINE = 2225,
DEVICE_REGISTER_ONLINE_RESPONSE = 2226,
PUSH_CLOUD_STORAGE_OPEN_RESULT = 2227,
PUSH_CLOUD_STORAGE_OPEN_RESULT_RESPONSE = 2228,
};
enum MessageType_ADPublishSys
{
GET_AD_INFO = 5500,
GET_AD_INFO_RESPONSE = 5501,
GET_PORTAL = 5502,
GET_PORTAL_RESPONSE = 5503,
GET_PUBLISH_INFO = 5504,
GET_PUBLISH_INFO_RESPONSE = 5505,
};
enum MessageType_VAS
{
STREAMING_MEDIA_OPEN = 5200,
STREAMING_MEDIA_OPEN_RESPONSE = 5201,
STREAMING_MEDIA_SHARE = 5202,
STREAMING_MEDIA_SHARE_RESPONSE = 5203,
GET_DEVICE_VAS_INFO = 5204,
GET_DEVICE_VAS_INFO_RESPONSE = 5205,
CLOUD_STORAGE_OPEN = 5206,
CLOUD_STORAGE_OPEN_RESPONSE = 5207,
GET_CLOUD_STORAGE_INFO = 5208,
GET_CLOUD_STORAGE_INFO_RESPONSE = 5209,
GET_VAS_SUPPORT = 5210,
GET_VAS_SUPPORT_RESPONSE = 5211,
};
// add by houbin
enum MessageType_LoadReport
{
LOAD_REPORT_REQ = 3000,
LOAD_REPORT_RES = 3001,
LOAD_SERVER_LIST_REQ = 3002,
LOAD_SERVER_LIST_RES = 3003
};
enum TcpConnectFlag
{
SHORT_CONNECTION,
PERSIST_CONNECTION,
};
enum LogicProcessType
{
ACCOUNT_BUSINESS_PROCESS = 0,
DEV_INFO_PRO = 1,
ALARM_PROCESS = 2,
UPDATE_PROCESS = 4,
DEV_INFO_HOMECLOUD = 5,
IM_SERVER_DIRECT = 6,
IM_SERVER_RELAY = 7,
IM_SERVER_RELAY_REQUEST = 8,
IM_DEV_DIRECT = 9,
ALARM_SERVER_RELAY = 10,
ALARM_INFO_PROCESS = 11,
};
/* ============= 联网报警自定义 =========== */
/*
* key of json
*/
// 联网报警新定义的消息共有格式
#define JK_MESSAGE_TYPE "method"
#define JK_METHOD "method"
#define JK_LOGIN "login"
#define JK_SET_PHONEID "set_phoneid"
// 上报负载信息
#define JK_SERVICE_TYPE "service_type"
#define JK_LOAD_NUMBER "load_number"
#define JK_CLIENT_TYPE "ct"
#define JK_PARAM "param"
#define JK_NETGATE_LIST "list"
#define JK_ONLINESRV_LIST "list_online"
#define JK_SERVER_IP "server_host"
#define JK_SERVER_PORT "server_port"
#define JK_ID "id"
#define JK_USER "user"
#define JK_PWD "<PASSWORD>"
#define JK_PHONE_ID "phone_id"
#define JK_SESSION "session"
// 设备上线
#define JK_SEND_CNT "sentcnt"
#define JK_DEV_ID "dev_id"
#define JK_ERROR "error"
#define JK_ERRORCODE "errorcode"
#define JK_STATE "state"
#define JK_TIME "time"
#define JK_TM_STR "tm"
#define JK_AUTH_DATA "data"
// 用户上线
#define JK_SESSION "session"
// 语音转发服务器
#define JK_CLIENT_IP "client_ip"
#define JK_DEV_IP "dev_ip"
#define JK_IP "ip"
#define JK_PORT "port"
/*
* value of json
*/
#define METHOD_GET_SERVERS "get_servers"
#define METHOD_ON_GET_SERVERS "on_get_servers"
#define METHOD_KEEP_ONLINE "keep_online"
#define METHOD_PUSH_MSG "push_msg"
#define METHOD_ON_PUSH_MSG "on_push_msg"
#define METHOD_DEVICE_STATE_NOTICE "device_state_notice"
#define METHOD_DEVICE_LOGIN "login"
#define METHOD_ON_DEVICE_LOGIN "on_login"
#define METHOD_SET_STREAMSERVER_ADDR "set_streamserver_addr"
#define METHOD_GET_DEV_IP "get_dev_ip"
#define METHOD_ON_GET_DEV_IP "on_get_dev_ip"
#define METHOD_LOGOUT "logout"
#define METHOD_ON_LOGOUT "on_logout"
#define METHOD_GET_VOICESERVER_ADDR "get_voiceserver_addr"
#define METHOD_ON_GET_VOICESERVER_ADDR "on_get_voiceserver_addr"
enum ClientType
{
CLIENT_TYPE_DEV = 1,
CLIENT_TYPE_PC = 2,
CLIENT_TYPE_APP = 3
};
enum ServerType
{
SERVER_NETGATE=1,
SERVER_ONLINE=2
};
#endif
|
DevCodeOne/damnflags
|
include/config.h
|
<reponame>DevCodeOne/damnflags<filename>include/config.h<gh_stars>0
#pragma once
#include <optional>
#include <regex>
#include <string>
#include <vector>
#include <nlohmann/json.hpp>
#include "filesys.h"
// TODO do proper caching instead of reading the json every time
class config {
public:
static std::optional<config> load_config(const fs::path &config_path);
static std::optional<config> create_config(const nlohmann::json &conf);
static config create_empty_config();
static bool is_config_valid(const nlohmann::json &conf);
static std::string default_config();
config &project_root(const fs::path &path);
config &compilation_database_path(const fs::path &path);
config &get_flags_from(const std::string &value);
config &whitelist_regex(const std::vector<std::string> ®ex);
config &blacklist_regex(const std::vector<std::string> ®ex);
std::optional<fs::path> project_root() const;
std::optional<fs::path> compilation_database_path() const;
std::optional<std::string> get_flags_from() const;
std::vector<std::string> whitelist_patterns() const;
std::vector<std::string> blacklist_patterns() const;
const std::vector<std::regex> &prepared_blacklist_patterns() const;
const std::vector<std::regex> &prepared_whitelist_patterns() const;
private:
config(const nlohmann::json &conf);
void update_patterns();
std::string load_variables(const std::string &pattern) const;
static inline constexpr char project_root_key[] = "project_root";
static inline constexpr char compilation_database_path_key[] = "compdb_path";
static inline constexpr char whitelist_patterns_key[] = "whitelist_patterns";
static inline constexpr char blacklist_patterns_key[] = "blacklist_patterns";
static inline constexpr char get_flags_from_key[] = "get_flags_from";
nlohmann::json m_conf{};
std::vector<std::regex> m_prepared_blacklist{};
std::vector<std::regex> m_prepared_whitelist{};
static inline constexpr char _default_config[] = R"(
{
"project_root": "${working_dir}",
"get_flags_from" : "${project_root}/src/main.cpp",
"whitelist_patterns" : ["${project_root}/src", "${project_root}/include", "${project_root}/build/compile_commands.json"]
}
)";
};
|
DevCodeOne/damnflags
|
include/utils.h
|
#pragma once
#include <algorithm>
#include <sstream>
#include <string>
#include <string_view>
#include <utility>
#include <vector>
#include "filesys.h"
template<typename T>
bool matches_extension(const fs::path &path, T begin, T end) {
if (!path.has_extension()) {
return false;
}
return std::find(begin, end, path.extension().c_str()) != end;
}
bool is_source_file(const fs::path &path);
bool is_header_file(const fs::path &path);
std::vector<std::string> split_command(const std::string &command_line);
void replace_pattern_with(std::string &str, std::string_view to_replace, std::string_view replace_with);
|
DevCodeOne/damnflags
|
include/workspace.h
|
#pragma once
// clang-format off
#define POSIX_C_SOURCE 200809L
#include <unistd.h>
#include <sys/inotify.h>
#include <sys/select.h>
#include <cstdint>
// clang-format off
#include <bitset>
#include <functional>
#include <map>
#include <optional>
#include <set>
#include "compilation_database.h"
#include "config.h"
#include "filesys.h"
enum struct workspace_events : uint32_t {
accessed = IN_ACCESS,
attribute_changed = IN_ATTRIB,
closed_write = IN_CLOSE_WRITE,
closed_nowrite = IN_CLOSE_NOWRITE,
created = IN_CREATE,
deleted = IN_DELETE,
deleted_self = IN_DELETE_SELF,
modified = IN_MODIFY,
moved_self = IN_MOVE_SELF,
moved_from = IN_MOVED_FROM,
moved_to = IN_MOVED_TO,
opened = IN_OPEN
};
bool operator&(const workspace_events &lhs, const workspace_events &rhs);
class workspace_event final {
public:
workspace_event(workspace_events event_mask, const fs::path &path);
workspace_events event_mask() const;
const fs::path &affected_path() const;
private:
std::optional<int> directory_watch() const;
workspace_event &directory_watch(int watch);
const workspace_events m_event_mask;
const fs::path m_affected_path;
std::optional<int> m_directory_watch{};
friend class workspace;
};
class workspace final {
public:
using handler_type = std::function<void(workspace &workspace_instance, const workspace_event &event)>;
static std::optional<workspace> discover_project(const fs::path &project_path, const std::optional<config> &conf = {});
static bool is_relevant_file(const fs::path &file, const config &conf);
workspace(const workspace &other) = delete;
workspace(workspace &&other);
~workspace();
workspace &operator=(const workspace &other) = delete;
workspace &operator=(workspace &&other) = default;
void swap(workspace &other);
void compilation_database_is_dirty();
bool check_for_updates();
const fs::path project_root() const;
const fs::path compilation_database_path() const;
private:
workspace(int notify_fd,
std::map<int, fs::path> directory_watches, const config &conf);
void update_compilation_database();
void populate_relevant_files();
void inotify_handler();
void send_event(uint32_t mask, const fs::path &affected_path, int directory_watch);
static void default_handler(workspace &workspace_instance, const workspace_event &event);
bool is_relevant_file(const fs::path &file) const;
config m_config;
std::vector<handler_type> m_event_handlers;
std::map<int, fs::path> m_directory_watches;
std::set<fs::path> m_relevant_files;
int m_notify_fd = 0;
bool m_dirty_compilation_database = true;
std::optional<compilation_database> m_compilation_database;
};
|
DevCodeOne/damnflags
|
include/logger.h
|
#pragma once
#include <memory>
#include <mutex>
#include <optional>
#include "spdlog/spdlog.h"
#include "filesys.h"
class logger_configuration final {
public:
logger_configuration() = default;
logger_configuration &should_log_to_console(bool value);
logger_configuration &log_path(const fs::path &value);
bool should_log_to_console() const;
const fs::path &log_path() const;
private:
bool m_should_log_to_console = false;
fs::path m_log_path;
};
class logger final {
public:
static std::shared_ptr<logger> instance(std::optional<logger_configuration> config = {});
void log_info(const std::string &info);
void log_warning(const std::string &warn);
void log_error(const std::string &error);
private:
logger(const logger_configuration &configuration);
std::shared_ptr<spdlog::logger> m_logger_instance = nullptr;
static inline std::shared_ptr<logger> _instance;
static inline std::mutex _instance_mutex;
};
|
DevCodeOne/damnflags
|
include/filesys.h
|
<reponame>DevCodeOne/damnflags<filename>include/filesys.h
#pragma once
#if __has_include("filesystem")
#include <filesystem>
namespace fs = std::filesystem;
#elif __has_include("experimental/filesystem")
#include <experimental/filesystem>
namespace fs = std::experimental::filesystem;
#endif
|
DevCodeOne/damnflags
|
include/compilation_database.h
|
<gh_stars>0
#pragma once
#include <optional>
#include <set>
#include <spdlog/spdlog.h>
#include <nlohmann/json.hpp>
#include "config.h"
#include "filesys.h"
// TODO Merge compilation databases if multiple ones are available
class compilation_database final {
public:
static constexpr inline char database_name[] = "compile_commands.json";
// TODO std::vector<fs::path> as argument for multiple compilation databases
static std::optional<compilation_database> read_from(const fs::path &path);
void swap(compilation_database &other) noexcept;
bool write_to(const fs::path &compilation_database) const;
bool add_missing_files(const std::set<fs::path> &relevant_files, const config &conf);
const nlohmann::json &database() const;
private:
compilation_database(nlohmann::json database);
nlohmann::json m_database;
};
|
SLongofono/EECS678_Scheduler
|
src/queuetest.c
|
/** @file queuetest.c
*/
#include <stdio.h>
#include <stdlib.h>
#include "libpriqueue/libpriqueue.h"
int compare1(const void * a, const void * b)
{
return ( *(int*)a - *(int*)b );
}
int compare2(const void * a, const void * b)
{
return ( *(int*)b - *(int*)a );
}
int compare3(const void *a, const void *b){
return -1;
}
int main()
{
priqueue_t q, q2, q3;
priqueue_init(&q, compare1);
priqueue_init(&q2, compare2);
priqueue_init(&q3, compare3);
/* Pupulate some data... */
int *values = malloc(100 * sizeof(int));
int i;
for (i = 0; i < 100; i++)
values[i] = i;
/* Add 5 values, 3 unique. */
priqueue_offer(&q, &values[12]);
priqueue_offer(&q, &values[13]);
priqueue_offer(&q, &values[14]);
priqueue_offer(&q, &values[12]);
priqueue_offer(&q, &values[12]);
printf("Total elements: %d (expected 5).\n", priqueue_size(&q));
int val = *((int *)priqueue_poll(&q));
printf("Top element: %d (expected 12).\n", val);
printf("Total elements: %d (expected 4).\n", priqueue_size(&q));
int values_removed = priqueue_remove(&q, &values[12]);
printf("Elements removed: %d (expected 2).\n", values_removed);
printf("Total elements: %d (expected 2).\n", priqueue_size(&q));
priqueue_offer(&q, &values[10]);
priqueue_offer(&q, &values[30]);
priqueue_offer(&q, &values[20]);
priqueue_offer(&q2, &values[10]);
priqueue_offer(&q2, &values[30]);
priqueue_offer(&q2, &values[20]);
printf("Elements in order queue (expected 10 13 14 20 30): ");
for (i = 0; i < priqueue_size(&q); i++)
printf("%d ", *((int *)priqueue_at(&q, i)) );
printf("\n");
printf("Elements in reverse order queue (expected 30 20 10): ");
for (i = 0; i < priqueue_size(&q2); i++)
printf("%d ", *((int *)priqueue_at(&q2, i)) );
printf("\n");
/* NEW TESTS */
printf("\n\nBEGINNING NEW TESTS\n\n");
for(int j = 0; j<10; ++j){
priqueue_poll(&q);
}
for(int j = 0; j<10; ++j){
priqueue_poll(&q2);
}
// Create queue of 1's and 9's
for(int j = 0; j<11; ++j){
if(j < 5){
priqueue_offer(&q, &values[1]);
}
else{
priqueue_offer(&q, &values[9]);
}
}
// Remove middle and replace by a 5
priqueue_remove_at(&q, 5);
priqueue_offer(&q, &values[5]);
priqueue_peek(&q2);
priqueue_poll(&q2);
priqueue_remove_at(&q2, 16);
priqueue_remove(&q2, &values[1]);
printf("Size of first queue: %d\n", priqueue_size(&q));
printf("Elements in order queue (expected 1 1 1 1 1 5 9 9 9 9 9): ");
for (i = 0; i < priqueue_size(&q); i++)
printf("%d ", *((int *)priqueue_at(&q, i)) );
printf("\n");
int * temp;
temp = (int *)priqueue_remove_at(&q, 1);
printf("Removed element %d from position %d\n", *temp, 1);
temp = (int*)priqueue_remove_at(&q, priqueue_size(&q)-1);
printf("Removed element %d from position %d\n", *temp, priqueue_size(&q));
printf("Elements in order queue (expected 1 1 1 1 5 9 9 9 9): ");
for (i = 0; i < priqueue_size(&q); i++)
printf("%d ", *((int *)priqueue_at(&q, i)) );
printf("\n");
printf("Elements in second queue (expected none): ");
for (i = 0; i < priqueue_size(&q2); i++)
printf("%d ", *((int *)priqueue_at(&q2, i)) );
printf("\n");
printf("\n");
priqueue_destroy(&q2);
priqueue_destroy(&q);
free(values);
return 0;
}
|
SLongofono/EECS678_Scheduler
|
src/libscheduler/libscheduler.h
|
<reponame>SLongofono/EECS678_Scheduler
/** @file libscheduler.h
*/
#ifndef LIBSCHEDULER_H_
#define LIBSCHEDULER_H_
/**
Constants which represent the different scheduling algorithms
*/
typedef enum {FCFS = 0, SJF, PSJF, PRI, PPRI, RR} scheme_t;
void scheduler_start_up (int cores, scheme_t scheme);
int scheduler_new_job (int job_number, int time, int running_time, int priority);
int scheduler_job_finished (int core_id, int job_number, int time);
int scheduler_quantum_expired (int core_id, int time);
float scheduler_average_turnaround_time();
float scheduler_average_waiting_time ();
float scheduler_average_response_time ();
void scheduler_clean_up ();
void scheduler_show_queue ();
#endif /* LIBSCHEDULER_H_ */
|
SLongofono/EECS678_Scheduler
|
src/libpriqueue/libpriqueue.c
|
<reponame>SLongofono/EECS678_Scheduler<gh_stars>0
/** @file libpriqueue.c
*/
#include <stdlib.h>
#include <stdio.h>
#include "libpriqueue.h"
#define DEBUG 0
void print_q(priqueue_t *q){
node_t* temp = q->front;
printf("Queue contents: ");
while(temp != NULL){
printf("%d ", *(int*)temp->value);
temp = temp->next;
}
}
/**
Initializes the priqueue_t data structure.
Assumtions
- You may assume this function will only be called once per instance of priqueue_t
- You may assume this function will be the first function called using an instance of priqueue_t.
@param q a pointer to an instance of the priqueue_t data structure
@param comparer a function pointer that compares two elements.
See also @ref comparer-page
*/
void priqueue_init(priqueue_t *q, int(*comparer)(const void *, const void *))
{
if(DEBUG){
printf("Init queue...\n");
}
q->size = 0;
q->front = NULL;
q->back = NULL;
q->compare = comparer;
if(DEBUG){
printf("Done init queue...\n");
}
}
/**
Inserts the specified element into this priority queue.
@param q a pointer to an instance of the priqueue_t data structure
@param ptr a pointer to the data to be inserted into the priority queue
@return The zero-based index where ptr is stored in the priority queue, where 0 indicates that ptr was stored at the front of the priority queue.
*/
int priqueue_offer(priqueue_t *q, void *ptr)
{
if(DEBUG){
printf("Adding a value...\n");
}
int insertion_point = 0;
if(0 == q->size){
if(DEBUG){
printf("No previous vals, adding to front...\n");
}
// Allocate some space on heap
node_t *temp = malloc(sizeof(node_t));
q->front = temp;
// Update front/back ptrs
q->back = q->front;
// Fill in given data for the node
q->front->value = ptr;
q->front->next = NULL;
// Update size
q->size++;
}
else{
node_t *temp = q->front;
node_t *prev = NULL;
if(DEBUG){
printf("Searching for correct position for new value %d...\n", *(int*)ptr);
}
// Two compares in use:
// c1(a,b) -> a-b (lowest takes priority)
// c2(a,b) -> b-a (highest takes priority)
while(NULL != temp && 0 >= q->compare(temp->value, ptr)){
// proceed until we reach something that has lower
// priority or the end
if(DEBUG){
printf("%d has higher priority than %d...\n", *(int*)temp->value, *(int*)ptr);
}
prev = temp;
temp = temp->next;
insertion_point++;
}
if(NULL == temp){
// case we hit the end
temp = malloc(sizeof(node_t));
q->back->next = temp;
temp->next = NULL;
temp->value = ptr;
q->size++;
q->back = temp;
if(DEBUG){
printf("Added %d to back\n", *(int*)q->back->value);
}
}
else{
// case insert a new value
node_t *temp2 = malloc(sizeof(node_t));
temp2->value = ptr;
if(q->front == temp){
q->front = temp2;
temp2->next = temp;
}
else{
temp2->next = temp;
prev->next = temp2;
}
q->size++;
if(DEBUG){
printf("Added %d to position %d\n", *(int*)temp2->value, insertion_point);
}
}
if(DEBUG){
print_q(q);
}
}
return insertion_point;
}
/**
Retrieves, but does not remove, the head of this queue, returning NULL if
this queue is empty.
@note The returned value must be freed
@param q a pointer to an instance of the priqueue_t data structure
@return pointer to element at the head of the queue
@return NULL if the queue is empty
*/
void *priqueue_peek(priqueue_t *q)
{
if(0 == q->size){
return NULL;
}
else{
//node_t* temp = malloc(sizeof(node_t));
//temp->next = NULL;
//temp->value = q->front->value;
return q->front->value;
}
}
/**
Retrieves and removes the head of this queue, or NULL if this queue
is empty.
@note The returned element must be freed properly
@param q a pointer to an instance of the priqueue_t data structure
@return the head of this queue
@return NULL if this queue is empty
*/
void *priqueue_poll(priqueue_t *q)
{
if(0 == q->size){
if(DEBUG){
printf("No elements to remove...\n");
}
return NULL;
}
else if(1 == q->size){
if(DEBUG){
printf("Removing %d from front of queue...\n", *(int*)q->front->value);
print_q(q);
}
//node_t* temp = q->front;
void *ret = q->front->value;
free(q->front);
q->front = NULL;
q->back = NULL;
q->size--;
if(DEBUG){
print_q(q);
//printf("\n\nPlease remember to free this...\n\n");
}
return ret;
}
else{
if(DEBUG){
printf("Removing %d from front of queue...\n", *(int*)q->front->value);
print_q(q);
}
node_t* temp = q->front;
void *ret = q->front->value;
q->front = q->front->next;
free(temp);
q->size--;
if(DEBUG){
print_q(q);
//printf("\n\nPlease remember to free this...\n\n");
}
return ret;
}
}
/**
Returns the element at the specified position in this list, or NULL if
the queue does not contain an index'th element.
@note The item remains in the queue - this behavior was not explicitly stated,
but through trial and error it appears that this is the intended behavior
@param q a pointer to an instance of the priqueue_t data structure
@param index position of retrieved element
@return the index'th element in the queue
@return NULL if the queue does not contain the index'th element
*/
void *priqueue_at(priqueue_t *q, int index)
{
// Check size
if(index > q->size){
printf("INVALID SIZE\n");
}
else{
// Locate the element
int count = 0;
node_t * temp = q->front;
while(count < index && NULL != temp ){
temp = temp->next;
count++;
}
if(NULL != temp){
if(DEBUG){
printf("Found element %d at position %d\n", *(int*)temp->value, count);
}
return (void *)temp->value;
}
}
return NULL;
}
/**
Removes all instances of ptr from the queue.
This function should not use the comparer function, but check if the
data contained in each element of the queue is equal (==) to ptr.
@param q a pointer to an instance of the priqueue_t data structure
@param ptr address of element to be removed
@return the number of entries removed
*/
int priqueue_remove(priqueue_t *q, void *ptr)
{
node_t* temp = q->front;
node_t* prev = NULL;
int removed = 0;
while(NULL != temp){
if(temp->value == ptr){
// Remove
if(DEBUG){
printf("Destroying match for %d\n", *(int*)ptr);
print_q(q);
printf("\n\nFREEING!\n\n");
}
if(1 == q->size){
free(temp);
q->front = NULL;
q->back = NULL;
}
else if(temp == q->front){
prev = temp;
temp = temp->next;
q->front = temp;
free(prev);
prev = NULL;
}
else if(temp == q->back){
free(temp);
temp = NULL;
q->back = prev;
q->back->next=NULL;
}
else{
node_t* destroy = temp;
temp = temp->next;
free(destroy);
prev->next = temp;
}
removed++;
q->size--;
if(DEBUG){
print_q(q);
}
}
else{
if(DEBUG){
printf("%d does not match pattern %d, moving on...\n", *(int*)temp->value, *(int*)ptr);
}
prev = temp;
temp = temp->next;
}
}
return removed;
}
/**
Removes the specified index from the queue, moving later elements up
a spot in the queue to fill the gap.
@param q a pointer to an instance of the priqueue_t data structure
@param index position of element to be removed
@return the element removed from the queue
@return NULL if the specified index does not exist
*/
void *priqueue_remove_at(priqueue_t *q, int index)
{
if(NULL == q || 0 == q->size || q->size < index ){
return NULL;
}
int count = 0;
void *ret = NULL;
node_t *temp = q->front;
node_t * prev = NULL;
while(count != index){
prev = temp;
temp = temp->next;
count++;
}
if(1 == q->size){ // Case exactly one
ret = (void *)temp->value;
q->front = NULL;
q->back = NULL;
}
else if(temp == q->back){ // Case remove from back
prev->next = NULL;
q->back = prev;
ret = (void *)temp->value;
}
else if(temp == q->front){ // Case remove from front
q->front = temp->next;
ret = (void*)temp->value;
}
else{ // Case remove from middle
prev->next = temp->next;
ret = (void*)temp->value;
}
free(temp);
q->size--;
return ret;
}
/**
Returns the number of elements in the queue.
@param q a pointer to an instance of the priqueue_t data structure
@return the number of elements in the queue
*/
int priqueue_size(priqueue_t *q)
{
return q->size;
}
/**
Destroys and frees all the memory associated with q.
@param q a pointer to an instance of the priqueue_t data structure
*/
void priqueue_destroy(priqueue_t *q)
{
node_t *temp;
while(q->front != NULL){
temp = q->front->next;
free(q->front);
q->front = temp;
q->size--;
}
assert(0 == q->size);
q->front = NULL;
q->back = NULL;
}
|
SLongofono/EECS678_Scheduler
|
src/libpriqueue/libpriqueue.h
|
/** @file libpriqueue.h
*/
#ifndef LIBPRIQUEUE_H_
#define LIBPRIQUEUE_H_
#include <assert.h>
/**
* Node data structure
*/
typedef struct node_t{
void *value;
struct node_t *next;
} node_t;
/**
* Priority queue data structure
*/
typedef struct _priqueue_t
{
node_t *front;
node_t * back;
int size;
int (*compare)(const void *, const void *);
} priqueue_t;
/**
* @brief Initializer for a priority queue element, called once immediately
* after creating it.
*
* @param q A pointer to an instance of the priqueue_t type
* @param comparer A function pointer to be used when comparing this
* pidqueue_t type.
*/
void priqueue_init (priqueue_t *q, int(*comparer)(const void *, const void *));
/**
* @brief Inserts the value at the given address into this queue, and returns
* the value of the index it was inserted at.
*/
int priqueue_offer (priqueue_t *q, void *ptr);
/**
* @brief Returns the value of the frontmost element in the queue
*/
void * priqueue_peek (priqueue_t *q);
/**
* @brief Removes and returns the frontmost element in the queue, or returns
* NULL if the queue is empty
*/
void * priqueue_poll (priqueue_t *q);
/**
* @brief Return the element at the specified index, or NULL if no such
* element exists
*/
void * priqueue_at (priqueue_t *q, int index);
/**
* @brief Remove all elements with the given value at ptr
*/
int priqueue_remove (priqueue_t *q, void *ptr);
/**
* @brief Remove the element at the given index,
*/
void * priqueue_remove_at(priqueue_t *q, int index);
/**
* @brief Get the number of elements in this queue
*/
int priqueue_size (priqueue_t *q);
/**
* @brief Destructor for the priority queue
*/
void priqueue_destroy (priqueue_t *q);
#endif /* LIBPQUEUE_H_ */
|
SLongofono/EECS678_Scheduler
|
src/simulator.c
|
/*
* CS 241
* The University of Illinois
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <assert.h>
#include "libscheduler/libscheduler.h"
typedef struct _simulator_job_list_t
{
int job_id, arrival_time, run_time, priority;
int core_id, arrived;
} simulator_job_list_t;
void print_usage(char *program_name)
{
fprintf(stderr, "Usage: %s -c <cores> -s <scheme> <input file>\n", program_name);
fprintf(stderr, " %s -c 2 -s fcfs examples/proc1.csv\n", program_name);
fprintf(stderr, "\n");
fprintf(stderr, "Acceptable schemes are: fcfs, sjf, psjf, pri, ppri, rr#\n");
}
int set_active_job(int job_id, int core_id, simulator_job_list_t *jobs, int active_jobs)
{
int i;
for (i = 0; i < active_jobs; i++)
{
if (jobs[i].job_id == job_id && jobs[i].arrived)
{
jobs[i].core_id = core_id;
return 1;
}
}
return 0;
}
void print_available_jobs(simulator_job_list_t *jobs, int active_jobs)
{
printf("Active jobs are: ");
int i, first = 1;
for (i = 0; i < active_jobs; i++)
{
if (jobs[i].arrived)
{
if (first)
{
printf("%d", jobs[i].job_id);
first = 0;
}
else
printf(", %d", jobs[i].job_id);
}
}
if (!first)
printf("\n");
}
void print_available_cores(int cores)
{
printf("Active cores are: ");
int i;
for (i = 0; i < cores; i++)
{
if (i == cores - 1)
printf("%d\n", i);
else
printf("%d, ", i);
}
}
int main(int argc, char **argv)
{
int c;
int cores = 0, scheme = -1, quantum = 0;
char *file_name;
/*
* Parse command line options.
*/
while ((c = getopt(argc, argv, "c:s:")) != -1)
{
switch (c)
{
case 'c':
cores = atoi(optarg);
if (cores <= 0)
{
fprintf(stderr, "Option -c <cores> require a positive number.\n");
print_usage(argv[0]);
return 1;
}
break;
case 's':
if (strcasecmp(optarg, "FCFS") == 0) { scheme = FCFS; }
else if (strcasecmp(optarg, "SJF") == 0) { scheme = SJF; }
else if (strcasecmp(optarg, "PSJF") == 0) { scheme = PSJF; }
else if (strcasecmp(optarg, "PRI") == 0) { scheme = PRI; }
else if (strcasecmp(optarg, "PPRI") == 0) { scheme = PPRI; }
else if (strncasecmp(optarg, "RR", 2) == 0)
{
scheme = RR;
quantum = atoi(optarg + 2);
if (quantum <= 0)
{
fprintf(stderr, "Option -s <scheme> requires a positive number for the quantum of RR. (Eg: -s RR2)\n");
print_usage(argv[0]);
return 1;
}
}
break;
case '?':
print_usage(argv[0]);
return 1;
default:
printf("...\n");
break;
}
}
if (cores == 0)
{
fprintf(stderr, "Required option -c <cores> is not present.\n");
print_usage(argv[0]);
return 1;
}
if (scheme == -1)
{
fprintf(stderr, "Required option -s <scheme> is not present.\n");
print_usage(argv[0]);
return 1;
}
if (optind == argc - 1)
file_name = argv[optind];
else
{
fprintf(stderr, "A single input file is required.\n");
print_usage(argv[0]);
return 1;
}
/*
* Open the file, read the file, and populate the jobs data structure.
*/
FILE *file = fopen(file_name, "r");
if (file == NULL)
{
fprintf(stderr, "Unable to open file \"%s\".\n", file_name);
return 2;
}
int job_id = 0;
int jobs_ct = 10;
simulator_job_list_t* jobs = malloc(jobs_ct * sizeof(simulator_job_list_t));
char line[1024 + 1];
fgets(line, 1024, file); // Ignore the first (header) line
while (fgets(line, 1024, file) != NULL)
{
char *arrival_time = strtok(line, ",");
char *run_time = strtok(NULL, ",");
char *priority = strtok(NULL, ",");
if (arrival_time != NULL && run_time != NULL && priority != NULL)
{
if (job_id == jobs_ct)
{
jobs_ct *= 2;
jobs = realloc(jobs, jobs_ct * sizeof(simulator_job_list_t));
if (!jobs)
{
fprintf(stderr, "Out of memory.\n");
return 2;
}
}
jobs[job_id].job_id = job_id;
jobs[job_id].arrival_time = atoi(arrival_time);
jobs[job_id].run_time = atoi(run_time);
jobs[job_id].priority = atoi(priority);
jobs[job_id].core_id = -1;
jobs[job_id].arrived = 0;
job_id++;
}
else
{
fprintf(stderr, "Illegal file format.\n");
return 2;
}
}
fclose(file);
/*
* Run the simulation.
*/
printf("Loaded %d core(s) and %d job(s) using ", cores, job_id);
if (scheme == FCFS) { printf("First Come First Served (FCFS)"); }
else if (scheme == SJF) { printf("Non-preemptive Shortest Job First (SJF)"); }
else if (scheme == PSJF) { printf("Preemptive Shortest Job First (PSJF)"); }
else if (scheme == PRI) { printf("Non-preemptive Priority (PRI)"); }
else if (scheme == PPRI) { printf("Preemptive Priority (PPRI)"); }
else if (scheme == RR) { printf("Round Robin (RR) with a quantum of %d", quantum); }
printf(" scheduling...\n\n");
scheduler_start_up(cores, scheme);
int time = 0, i, j;
int active_jobs = job_id, jobs_alive = 0;
int *quantum_clock = malloc(cores * sizeof(int));
char **core_timing_diagram = malloc(cores * sizeof(char *));
int core_timing_diagram_size = 1024;
for (i = 0; i < cores; i++)
{
quantum_clock[i] = -1;
core_timing_diagram[i] = malloc(core_timing_diagram_size + 1);
core_timing_diagram[i][0] = '\0';
}
while (active_jobs > 0)
{
printf("=== [TIME %d] ===\n", time);
/*
* 1. Check if any jobs finished in the last time unit.
*/
for (i = 0; i < active_jobs; i++)
{
if (jobs[i].run_time == 0)
{
// Notify the scheduler has finished
int job_id = jobs[i].job_id;
int core_id = jobs[i].core_id;
int new_job_id = scheduler_job_finished(jobs[i].core_id, jobs[i].job_id, time);
if (scheme == RR)
quantum_clock[jobs[i].core_id] = quantum;
// Delete the finished jobs, decrease the number of active jobs
if (i != active_jobs - 1)
memcpy(&jobs[i], &jobs[active_jobs - 1], sizeof(simulator_job_list_t));
active_jobs--;
jobs_alive--;
i--;
// Set the new job
if ( new_job_id != -1 && !set_active_job(new_job_id, core_id, jobs, active_jobs) )
{
printf("The scheduler_job_finished() selected an invalid job (job_id == %d).\n", new_job_id);
print_available_jobs(jobs, active_jobs);
return 3;
}
else
{
printf("Job %d, running on core %d, finished. Core %d is now running job %d.\n", job_id, core_id, core_id, new_job_id);
printf(" Queue: "); scheduler_show_queue(); printf("\n\n");
}
}
}
/*
* Check to see if we finished our last job. (If we don't check here, we would run an extra time unit that will be totally idle.)
*/
if (active_jobs == 0)
break;
/*
* 2. Check of any quantums expired in the last time unit.
*/
if (scheme == RR)
{
for (i = 0; i < cores; i++)
{
if (quantum_clock[i] == 0)
{
for (j = 0; j < active_jobs; j++)
{
if (jobs[j].core_id == i)
{
// Notify the scheduler the quantum has expired
int core_id = jobs[j].core_id;
int old_job_id = jobs[j].job_id;
int new_job_id = scheduler_quantum_expired(jobs[j].core_id, time);
jobs[j].core_id = -1;
quantum_clock[core_id] = quantum;
// Set the new job
if ( new_job_id != -1 && !set_active_job(new_job_id, core_id, jobs, active_jobs) )
{
printf("The scheduler_quantum_expired() selected an invalid job (job_id == %d).\n", new_job_id);
print_available_jobs(jobs, active_jobs);
return 3;
}
else
{
printf("Job %d, running on core %d, had its quantum expire. Core %d is now running job %d.\n", old_job_id, core_id, core_id, new_job_id);
printf(" Queue: "); scheduler_show_queue(); printf("\n\n");
}
break;
}
}
}
}
}
/*
* 3. Check for any new jobs that arrive in this time unit
*/
for (i = 0; i < active_jobs; i++)
{
if (jobs[i].arrival_time == time)
{
int new_job_core_id = scheduler_new_job(jobs[i].job_id, time, jobs[i].run_time, jobs[i].priority);
jobs[i].arrived = 1;
jobs_alive++;
if (new_job_core_id >= 0 && new_job_core_id < cores)
{
printf("A new job, job %d (running time=%d, priority=%d), arrived. Job %d is now running on core %d.\n",
jobs[i].job_id, jobs[i].run_time, jobs[i].priority, jobs[i].job_id, new_job_core_id);
printf(" Queue: "); scheduler_show_queue(); printf("\n\n");
// Find if anyone is currently using the core.
for (j = 0; j < active_jobs; j++)
if (jobs[j].core_id == new_job_core_id)
jobs[j].core_id = -1;
// Assign the core to the new job
jobs[i].core_id = new_job_core_id;
if (scheme == RR)
quantum_clock[new_job_core_id] = quantum;
}
else if (new_job_core_id == -1)
{
printf("A new job, job %d (running time=%d, priority=%d), arrived. Job %d is set to idle (-1).\n",
jobs[i].job_id, jobs[i].run_time, jobs[i].priority, jobs[i].job_id);
printf(" Queue: "); scheduler_show_queue(); printf("\n\n");
}
else
{
printf("The scheduler_new_job() selected an invalid core (core_id == %d).\n", new_job_core_id);
print_available_cores(cores);
return 3;
}
}
}
/*
* 4. Run the time unit.
*/
char time_string[cores][11];
int cores_working = 0;
for (i = 0; i < cores; i++)
time_string[i][0] = '\0';
for (i = 0; i < active_jobs; i++)
{
if (jobs[i].core_id != -1)
{
cores_working++;
jobs[i].run_time--;
quantum_clock[jobs[i].core_id]--;
assert(time_string[jobs[i].core_id][0] == '\0');
if (jobs[i].job_id < 10)
sprintf(time_string[jobs[i].core_id], "%d", jobs[i].job_id);
else if (jobs[i].job_id < 10 + 26)
sprintf(time_string[jobs[i].core_id], "%c", jobs[i].job_id - 10 + 'a');
else if (jobs[i].job_id < 10 + 26 + 26)
sprintf(time_string[jobs[i].core_id], "%c", jobs[i].job_id - 10 - 26 + 'A');
else
snprintf(time_string[jobs[i].core_id], 10, "(%d)", jobs[i].job_id);
}
}
for (i = 0; i < cores; i++)
{
// If the core is idle, print a '-'
if (time_string[i][0] == '\0')
strcpy(time_string[i], "-");
// Ensure we have enough memory
while (strlen(core_timing_diagram[i]) + strlen(time_string[i]) >= (unsigned int)core_timing_diagram_size)
{
core_timing_diagram_size *= 2;
for (j = 0; j < cores; j++)
{
core_timing_diagram[j] = realloc(core_timing_diagram[j], core_timing_diagram_size + 1);
if (core_timing_diagram[j] == NULL)
{
fprintf(stderr, "Out of memory.\n");
return 3;
}
}
}
strcat( core_timing_diagram[i], time_string[i] );
}
/*
* 5. Print data!
*/
printf("At the end of time unit %d...\n", time);
for (i = 0; i < cores; i++)
printf(" Core %2d: %s\n", i, core_timing_diagram[i]);
printf("\n");
printf(" Queue: ");
scheduler_show_queue();
printf("\n");
printf("\n");
/*
* 6. Sanity Checking
*
* - If there's a job alive (needing to be ran) and all CPUs are idle, the scheduler failed to schedule properly.
*/
if (jobs_alive > 0 && cores_working == 0)
{
printf("All cores are idle and at least one job remains unscheduled.\n");
print_available_jobs(jobs, active_jobs);
return 3;
}
/*
* 7. Increase time
*/
time++;
}
printf("FINAL TIMING DIAGRAM:\n");
for (i = 0; i < cores; i++)
printf(" Core %2d: %s\n", i, core_timing_diagram[i]);
printf("\n");
printf("Average Waiting Time: %.2f\n", scheduler_average_waiting_time());
printf("Average Turnaround Time: %.2f\n", scheduler_average_turnaround_time());
printf("Average Response Time: %.2f\n", scheduler_average_response_time());
scheduler_clean_up();
free(quantum_clock);
for (i=0; i < cores; i++)
free(core_timing_diagram[i]);
free(core_timing_diagram);
free(jobs);
return 0;
}
|
SLongofono/EECS678_Scheduler
|
src/libscheduler/libscheduler.c
|
/** @file libscheduler.c
*
* @author <NAME>
*
* created 03/20/2017
*
* modified 03/29/2017
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "libscheduler.h"
#include "../libpriqueue/libpriqueue.h"
#define DEBUG 0
// Global ready queue
priqueue_t *ready_q;
// Track busy cores
int *active_core;
int NUM_CORES;
// Keep track of scheme
scheme_t policy;
/**
Stores information making up a job to be scheduled and statistics required
for the scheduler and its helper functions.
*/
typedef struct _job_t{
// Contains in order: uuid, arrival, burst, priority, runtime, end,
// last active time, latency
int value[8];
// Negative if unassigned, otherwise the integer corresponding to the
// core in active_core
int core;
// Flag for completion
int finished;
// Tracks special order for RR scheduling
int RR_order;
} job_t;
void print_queue(){
job_t * curr;
for(int i=0; i<priqueue_size(ready_q); ++i){
curr = (job_t*)priqueue_at(ready_q, i);
if(curr->finished){
printf("X%dX ", curr->value[0]);
}
else{
printf("%d(%d) ", curr->value[0], curr->value[3]);
}
}
printf("\n");
}
/** @brief Computes and updates time metrics for the job given
*
* @param job A pointer to the job to update
* @param time An integer representing the current time unit
*/
void update_running_time(job_t * job, int time){
int new_running_time = 0;
// Additional running time is current time less last active
// time, or 0 if this job has not run yet
// If this job has already been active...
if(0 <= job->value[6]){
if(DEBUG){
printf("Computing new run time as %d - %d...\n", time, job->value[6]);
}
new_running_time = time - job->value[6];
}
// Update last active time
job->value[6] = time;
if(DEBUG){
printf("Job %d running time incremented from %d to %d\n", job->value[0], job->value[4], job->value[4]+new_running_time);
printf("Job %d last active time updated to %d\n", job->value[0], job->value[6]);
}
job->value[4] += new_running_time;
}
/**
* @brief Computes and updates the latency of the given job
*
* @param job A pointer to the job to update
* @param time An integer representing the current time unit
*/
void update_latency_time(job_t* job, int time){
// If we haven't already set it...
if(0 > job->value[7]){
job->value[7] = time - job->value[1];
if(DEBUG){
printf("Job %d latency updated to %d\n", job->value[0], job->value[7]);
}
}
}
/**
* @brief Computes and updates time metrics for the job given
*
* @param job A pointer to the job to update
* @param time An integer representing the current time unit
*/
void update_time(int time){
job_t *curr_job;
for(int i = 0; i<priqueue_size(ready_q); ++i){
curr_job = (job_t*)priqueue_at(ready_q, i);
assert(NULL != curr_job);
// if active or just ended
if(0 <= curr_job->core){
update_running_time(curr_job, time);
update_latency_time(curr_job, time);
}
else if(time == curr_job->value[5]){
update_running_time(curr_job, time);
}
if(DEBUG){
printf("Time updated, job %d\n", curr_job->value[0]);
}
}
}
/**
* @brief fetches the currently running job to be preempted by the job passed in, or NULL if none exist
*
* @param job A job_t to compare against existing jobs, the preempting job
*
* @return A job to be preempted, or NULL if none exists
*/
job_t* get_preempt_job(job_t *current_job){
// To accurately judge which needs to be preempted, we need to look
// from the back of the list forward
job_t *running_job;
for(int i = priqueue_size(ready_q)-1; i>=0; --i){
running_job = (job_t*)priqueue_at(ready_q, i);
// If the job is running
if(0 <= running_job->core){
//and the job passed in trumps it
if(0 >= ready_q->compare(current_job, running_job)){
return running_job;
}
}
}
return NULL;
}
/**
* @brief Returns the integer corresponding to the lowest free core
*
* @return The lowest non-negative integer which corresponds to a free core,
* or -1 if no cores are free.
*
*/
int get_idle_core(){
int lowest = 9000;
for(int i = 0; i<NUM_CORES; ++i){
if(0 > active_core[i] && i < lowest){
lowest = i;
}
}
return lowest;
}
/**
* @brief Given a job number, locates and returns the job with that number
* from the ready queue
*
* @param job_number The job number of the job to fetch (guaranteed unique)
*
* @return a pointer the job with the job number passed in, or NULL
* if no such job exists.
*/
job_t * get_job(int job_number){
if(DEBUG){
printf("In get job, looking for %d...\n", job_number);
}
job_t* result = NULL;
job_t *current_job;
for(int i = 0; i<priqueue_size(ready_q); ++i){
current_job = (job_t*)priqueue_at(ready_q, i);
if(job_number == current_job->value[0]){
result = current_job;
if(DEBUG){
printf("Found job %d!\n", current_job->value[0]);
}
break;
}
else{
if(DEBUG){
printf("Job %d does not match %d\n", current_job->value[0], job_number);
}
}
}
return result;
}
/**
* @brief Associates a job with a core and vice versa
*
* @param core An integer representing the index into the active_core global
* array of cores
* @param job A pointer to a job to be updated to the given core
*
* Dies if anything is amiss
*/
void update_core(int core, job_t * job){
if(DEBUG){
printf("Updating core %d with job %d...\n", core, job->value[0]);
}
if(core > NUM_CORES){
printf("[ Error ]\t\tTried to update nonexistent core...\n");
assert(0);
}
// Update job
job->core = core;
if(DEBUG){
printf("Job %d core set to %d\n", job->value[0], core);
}
// Update cores and return success
active_core[core] = job->value[0];
return;
}
/*
* Functions for comparison of jobs under different scheduling policies
*
* @param j1 A pointer to a job, given as a void *
* @param j2 A pointer to a job, given as a void *
*
* @return An integer which is negative if the j2 takes precedence over j1,
* zero if equal, or positive if j1 takes precedence
*
* Note: The priqueue class behaves as such:
* compare(a,b):
* return 1 if a < b
* else -1
*
* Thus all functions need to return accordingly, positive return
* if the first parameter takes precedence, negative otherwise
*/
// Round robin comparison
int comparison_RR(const void *j1, const void *j2){
// Always return -1 so that this queue behaves like a FIFO
return -1;
}
// First come, first serve comparison
int comparison_FCFS(const void *j1, const void *j2){
job_t *this;
job_t *that;
this = (job_t*)j1;
that = (job_t*)j2;
// currently running jobs take precedence
if(0 > this->core && 0 <= that->core){
return 1;
}
else if(0 > that->core && 0 <= this->core ){
return -1;
}
else{
// Otherwise, evaluate them based on arrival
// Since we are guaranteed unique arrival times, simply subtract them.
// If the latter came sooner than the former, the result will be
// positive.
if(DEBUG){
printf("Job %d arrived at time %d\n", this->value[0], this->value[1]);
printf("job %d arrived at time %d\n", that->value[0], that->value[1]);
printf("Job %d came %d seconds before job %d...\n", this->value[0], that->value[1]-this->value[1], that->value[0]);
}
return (this->value[1] - that->value[1]);
}
}
// Shortest job first comparison
int comparison_SJF(const void *j1, const void *j2){
job_t *this;
job_t *that;
int t1, t2;
this = (job_t *)j1;
that = (job_t *)j2;
// currently running jobs take precedence
if(0 > this->core && 0 <= that->core){
return 1;
}
else if(0 > that->core && 0 <= this->core ){
return -1;
}
else{
// Compute running time remaining, defined as the burst time minus the
// running time.
t1 = this->value[2] - this->value[4];
t2 = that->value[2] - that->value[4];
// If the remaining time is equal, compare the arrival times per the
// rubric
if(t2 == t1){
// This result will be positive if the latter job arrived first
return (this->value[1] - that->value[1]);
}
// This result will be positive if this job has a longer running
// time remaining.
return (t1-t2);
}
}
// Priority comparison
int comparison_PRI(const void *j1, const void *j2){
job_t *this;
job_t *that;
this = (job_t*)j1;
that = (job_t*)j2;
// currently running jobs take precedence
if(0 > this->core && 0 <= that->core){
return 1;
}
else if(0 > that->core && 0 <= this->core ){
return -1;
}
else{
// Otherwise, evaluate them based on priority, then arrival
if(this->value[3] == that->value[3]){
// Since we are guaranteed unique arrival times, simply subtract them.
// If the latter came sooner than the former, the result will be
// positive.
if(DEBUG){
printf("Job %d arrived at time %d\n", this->value[0], this->value[1]);
printf("job %d arrived at time %d\n", that->value[0], that->value[1]);
printf("Job %d came %d seconds before job %d...\n", this->value[0], that->value[1]-this->value[1], that->value[0]);
}
return (this->value[1] - that->value[1]);
}
else{
if(DEBUG){
printf("Job %d has priority %d\n", this->value[0], this->value[3]);
printf("Job %d has priority %d\n", that->value[0], that->value[3]);
printf("Returning %d...\n", this->value[3]-that->value[3]);
}
// Positive if the former is higher priority
return (this->value[3] - that->value[3]);
}
}
}
// Preemptive priority comparison
int comparison_PPRI(const void *j1, const void *j2){
job_t *this;
job_t *that;
this = (job_t*)j1;
that = (job_t*)j2;
// Evaluate them based on priority, then arrival
if(this->value[3] == that->value[3]){
// Since we are guaranteed unique arrival times, simply subtract them.
// If the latter came sooner than the former, the result will be
// positive.
if(DEBUG){
printf("Job %d arrived at time %d\n", this->value[0], this->value[1]);
printf("job %d arrived at time %d\n", that->value[0], that->value[1]);
printf("Job %d came %d seconds before job %d...\n", this->value[0], that->value[1]-this->value[1], that->value[0]);
}
return (this->value[1] - that->value[1]);
}
else{
if(DEBUG){
printf("Job %d has priority %d\n", this->value[0], this->value[3]);
printf("Job %d has priority %d\n", that->value[0], that->value[3]);
printf("Returning %d...\n", this->value[3]-that->value[3]);
}
// Positive if the former is higher priority
// Note that this is exactly backwards wrt what we discussed
// in class and most Linux systems.
return (this->value[3] - that->value[3]);
}
}
// Preemptive shortest job first comparion
int comparison_PSJF(const void *j1, const void *j2){
job_t *this;
job_t *that;
int t1, t2;
this = (job_t *)j1;
that = (job_t *)j2;
// Compute running time remaining, defined as the burst time minus the
// running time.
t1 = this->value[2] - this->value[4];
t2 = that->value[2] - that->value[4];
// If the remaining time is equal, compare the arrival times per the
// rubric
if(t2 == t1){
if(DEBUG){
printf("Both jobs have %d time remaining\n", t1);
printf("Job %d arrived at time %d\n", this->value[0], this->value[1]);
printf("job %d arrived at time %d\n", that->value[0], that->value[1]);
printf("Job %d came %d seconds before job %d...\n", this->value[0], that->value[1]-this->value[1], that->value[0]);
}
// This result will be positive if the latter job arrived first
return (this->value[1] - that->value[1]);
}
else{
if(DEBUG){
printf("Job %d has remaining time %d\n", this->value[0], t1);
printf("Job %d has remaining time %d\n", that->value[0], t2);
printf("Returning %d...\n", t1-t2);
}
}
// This result will be positive if this job has a longer running
// time remaining.
return (t1-t2);
}
/**
* @brief Determines the next job to be scheduled for non-preemptive schemes
*
* @param new_job An artifact from earlier versions that I was too lazy to
* remove
*
* @param time An integer representing the current time
*
* NOTE: This method schedules and updates everything blindly, plan
* accordingly. Relies on the ready queue being sorted by precedence.
*/
void next_job_no_preempt(job_t* new_job, int time){
job_t* next_job = NULL;
int length = priqueue_size(ready_q);
int found;
if(0 < length){
// If not empty, search through the queue
// Everything should be sorted by arrival automatically by
// priqueue_offer
int idle = get_idle_core();
while(9000 != idle){
found = 0;
for(int i = 0; i<length; ++i){
next_job = (job_t*)priqueue_at(ready_q, i);
// If the current job is not finished..
if(next_job->finished != 1){
if(DEBUG){
printf("Job %d is not finished(%d)...\n", next_job->value[0], next_job->finished);
}
// and it is not already running...
if(0 > next_job->core){
if(DEBUG){
printf("and not running, it will be the next job...\n");
}
found = 1;
break;
}
else{
if(DEBUG){
printf("Job %d is running, moving on...\n", next_job->value[0]);
}
}
}
else{
if(DEBUG){
printf("Job %d is finished, moving on...\n", next_job->value[0]);
}
}
}
if(found){
if(DEBUG){
printf("Updating core %d, currently running: %d\n", idle, active_core[idle]);
}
update_core(idle, next_job);
if(DEBUG){
printf("Core %d is now running job %d\n", idle, active_core[idle]);
}
// Update last active time to next time cycle
next_job->value[6] = time;
idle = get_idle_core();
}
else{
if(DEBUG){
printf("No valid jobs found to schedule\n");
}
break;
}
}// End while
}// End if(0 < length)
}
/**
* @brief Determines the next job to be scheduled for preemptive schemes
*
* @param new_job An artifact from earlier versions that I was too lazy to
* remove
*
* @param time An integer representing the current time
*
* NOTE: This method schedules and updates everything blindly, plan
* accordingly. Relies on the ready queue being sorted by precedence.
*/
void next_job_preempt(job_t *new_job, int time){
job_t *next_job;
next_job = NULL;
int length = priqueue_size(ready_q);
if(length > 0){
for(int i = 0; i<length; ++i){
next_job = (job_t *)priqueue_at(ready_q, i);
// If the current job is not finished..
if(next_job->finished != 1){
if(DEBUG){
printf("Job %d is not finished...\n", next_job->value[0]);
}
// and it is not already running...
if(0 > next_job->core){
if(DEBUG){
printf("and not running, checking for free cores...\n");
}
// If an idle core exists, assign this
// job to that core
int idle = get_idle_core();
if(9000 != idle){
if(DEBUG){
printf("An idle core exists to be scheduled...\n");
printf("Updating core %d, currently running: %d\n", idle, active_core[idle]);
}
update_core(idle, next_job);
if(DEBUG){
printf("Core %d is now running job %d\n", idle, active_core[idle]);
}
}
else{
// Otherwise, check if any of the jobs
// existing jobs should be preempted
// printf("No idle cores available, checking for preemption...\n");
// To preserve priority, find
// the least important task
job_t *old_job = get_preempt_job(next_job);
if(NULL != old_job){
// Preempt the job
int core = old_job->core;
// update its time
update_running_time(old_job, time);
// Reset its core
old_job->core = -1;
// Reset its active
// time to ensure
// proper running time
// accounting
old_job->value[6] = -1;
// If the job has yet
// to run, reset its
// latency
if(0 == old_job->value[4]){
old_job->value[7] = -1;
}
if(DEBUG){
printf("Job %d will preempt job %d on core %d...\n", next_job->value[0], old_job->value[0], core);
printf("Updating core %d, currently running: %d\n", core, active_core[core]);
}
update_core(core, next_job);
if(DEBUG){
printf("Core %d is now running job %d\n", core, active_core[core]);
}
}
else if(DEBUG){
printf("No preemptable jobs found...\n");
}
}// End else
}// End if (0 < next_job->core)
}
else if(DEBUG){
printf("Job %d is finished, moving on...\n", next_job->value[0]);
}
}// End for
} // End if(length > 0)
}
/**
* @brief Special snowflake method to find the next job for a Round robin
* scheme
*
* @param new_job An artifact from a previous version that I was too lazy to
* remove.
*
* @param time An integer representing the current time
*
* See notes
*/
void next_job_RR(job_t *new_job, int time){
// Main idea:
// Since the new jobs are never run right away, there is no need to
// make this more complicated. New jobs are simply added to the
// back of the list. The next job is always at the front, the first
// job which is not finished and not already running.
//
// In the event of a quantum timer expiring, simply move that one to
// the back and update the time. When a job finishes, mark it as
// such and leave it be.
job_t* next_job = NULL;
int length = priqueue_size(ready_q);
int found;
if(0 < length){
// If not empty, search through the queue
// Everything should be sorted by arrival automatically by
// priqueue_offer
int idle = get_idle_core();
while(9000 != idle){
found = 0;
for(int i = 0; i<length; ++i){
next_job = (job_t*)priqueue_at(ready_q, i);
if(NULL == next_job){
printf("SOMETHING IS VERY WRONG...\n");
printf("currently inspecting index %d\n", i);
printf("core %d is idle\n", idle);
printf("Priqueue has %d elements\n", priqueue_size(ready_q));
assert(0);
}
// If the current job is not finished..
if(next_job->finished != 1){
if(DEBUG){
printf("Job %d is not finished(%d)...\n", next_job->value[0], next_job->finished);
}
// and it is not already running...
if(0 > next_job->core){
if(DEBUG){
printf("and not running, it will be the next job...\n");
}
found = 1;
break;
}
else if(DEBUG){
printf("Job %d is running, moving on...\n", next_job->value[0]);
}
}
else if(DEBUG){
printf("Job %d is finished, moving on...\n", next_job->value[0]);
}
}
if(found){
if(DEBUG){
printf("Updating core %d, currently running: %d\n", idle, active_core[idle]);
}
update_core(idle, next_job);
if(DEBUG){
printf("Core %d is now running job %d\n", idle, active_core[idle]);
}
// Update last active time to next time cycle
next_job->value[6] = time;
idle = get_idle_core();
}
else{
if(DEBUG){
printf("No valid jobs found to schedule\n");
}
break;
}
}// End while
}// End if(0 < length)
}
/**
Initalizes the scheduler.
Assumptions:
- You may assume this will be the first scheduler function called.
- You may assume this function will be called once once.
- You may assume that cores is a positive, non-zero number.
- You may assume that scheme is a valid scheduling scheme.
@param cores the number of cores that is available by the scheduler. These
cores will be known as core(id=0), core(id=1), ..., core(id=cores-1).
@param scheme the scheduling scheme that should be used. This value will
be one of the six enum values of scheme_t
*/
void scheduler_start_up(int cores, scheme_t scheme){
// Set up global core tracker, initialized to zeros
active_core = (int *)malloc(cores*sizeof(int));
for(int i = 0; i<cores; ++i){
active_core[i] = -1;
}
NUM_CORES = cores;
// Set up global ready queue on the heap
ready_q = (priqueue_t *)malloc(sizeof(priqueue_t));
policy = scheme;
switch(policy){
case FCFS:
priqueue_init(ready_q, comparison_FCFS);
break;
case SJF:
priqueue_init(ready_q, comparison_SJF);
break;
case PSJF:
priqueue_init(ready_q, comparison_PSJF);
break;
case PRI:
priqueue_init(ready_q, comparison_PRI);
break;
case PPRI:
priqueue_init(ready_q, comparison_PPRI);
break;
default:
// Round robin
priqueue_init(ready_q, comparison_RR);
break;
}
if(DEBUG){
printf("Created new queue with %d elements\n", priqueue_size(ready_q));
printf("Cores:\t");
for(int i = 0; i<NUM_CORES; i++){printf("%d ", active_core[i]);}
printf("\n");
}
}
/**
Called when a new job arrives.
If multiple cores are idle, the job should be assigned to the core with the
lowest id.
If the job arriving should be scheduled to run during the next
time cycle, return the zero-based index of the core the job should be
scheduled on. If another job is already running on the core specified,
this will preempt the currently running job.
Assumptions:
- You may assume that every job wil have a unique arrival time.
NOTES: Here, we need to determine if we need to change anything, and update
everything on this end for execution immediately.
@param job_number a globally unique identification number of the job arriving.
@param time the current time of the simulator.
@param running_time the total number of time units this job will run before
it will be finished.
@param priority the priority of the job. (The lower the value, the higher the
priority.)
@return index of core job should be scheduled on
@return -1 if no scheduling changes should be made.
*/
int scheduler_new_job(int job_number, int time, int running_time, int priority){
// Create and initialize job
job_t* daJob = (job_t*)malloc(sizeof(job_t));
daJob->value[0] = job_number; // UUID
daJob->value[1] = time; // Arrival time
daJob->value[2] = running_time; // Burst
daJob->value[3] = priority; // Priority
daJob->value[4] = 0; // Cumulative running time
daJob->value[5] = 0; // End time
daJob->value[6] = -1; // Last active time
daJob->value[7] = -1; // Scheduling latency
daJob->core = -1; // Active core
daJob->finished = 0; // Complete/Incomplete
if(DEBUG){
print_queue();
}
// Add the new Job to the back of the queue
int status = priqueue_offer(ready_q, daJob);
if(DEBUG){
print_queue();
printf("Inserted new job at position %d\n", status);
printf("Current ready queue size is: %d\n", priqueue_size(ready_q));
}
// Determine and set up for the next round of jobs. It is assumed
// that by this point, all inactive jobs have been destroyed, and that
// this method call is the last step before the next execution
// interval, per the instructions.
//
// Each of the methods below acts accordingly, updating all known jobs
// to their correct cores and statuses.
switch(policy){
case RR:
next_job_RR(daJob, time);
break;
case PPRI:
case PSJF:
next_job_preempt(daJob, time);
break;
case SJF:
case PRI:
case FCFS:
next_job_no_preempt(daJob, time);
break;
}
// Update time for all jobs
update_time(time);
// The job in question will have its core already assigned
return get_job(job_number)->core;
}
/**
Called when a job has completed execution.
The core_id, job_number and time parameters are provided for convenience. You
may be able to calculate the values with your own data structure.
If any job should be scheduled to run on the core free'd up by the
finished job, return the job_number of the job that should be scheduled to
run on core core_id.
NOTES: Here, we need to find the enxt job, and commit the changes on
this end. There may be several such calls due to the way the
simulator is written.
@param core_id the zero-based index of the core where the job was located.
@param job_number a globally unique identification number of the job.
@param time the current time of the simulator.
@return job_number of the job that should be scheduled to run on core core_id
@return -1 if core should remain idle.
*/
int scheduler_job_finished(int core_id, int job_number, int time){
job_t* curr_job;
// Find and update the job in question
curr_job = get_job(job_number);
if(DEBUG){
printf("Job finished: %d\n", curr_job->value[0]);
}
// Update ended time
curr_job->value[5] = time;
// Mark complete
curr_job->finished = 1;
// Hacky hack
// Need to ensure that final jobs do not influence new job placement
// in preemptive priority scheme. By setting this to maximum
// priority, the new job will always make it past the the finished
// jobs and compare to at least one incomplete job.
curr_job->value[3] = 0;
if(DEBUG){
printf("Freeing core %d, currently running job %d...\n", core_id, active_core[core_id]);
}
// Free the core for downstream helpers
active_core[core_id] = -1;
curr_job->core = -1;
// Update everything
switch(policy){
case FCFS:
case PRI:
case SJF:
next_job_no_preempt(NULL, time);
break;
case PSJF:
case PPRI:
next_job_preempt(NULL, time);
break;
default:
next_job_RR(NULL, time);
}
// Hacky hack
curr_job->finished = 0;
// Update time for all jobs
update_time(time);
// end Hacky hack
curr_job->finished = 1;
// return the next item to run on the core in question, or -1 if idle
return active_core[core_id];
}
/**
When the scheme is set to RR, called when the quantum timer has expired
on a core.
If any job should be scheduled to run on the core free'd up by
the quantum expiration, return the job_number of the job that should be
scheduled to run on core core_id.
NOTE - not in the rubric, but there is some ill-defined behavior:
If no other jobs exist, a job should not be preempted at all.
@param core_id the zero-based index of the core where the quantum has expired.
@param time the current time of the simulator.
@return job_number of the job that should be scheduled on core cord_id
@return -1 if core should remain idle
*/
int scheduler_quantum_expired(int core_id, int time){
if(DEBUG){
printf("Quantum time expired for core %d\n", core_id);
}
scheduler_show_queue();
job_t * current_job;
int position = -1;
int no_other_jobs = 0;
// Find the currently running job
int current_job_number = active_core[core_id];
assert(current_job_number >= 0);
// Verify that it exists...
current_job = (job_t*)get_job(current_job_number);
assert(NULL!=current_job);
// Review each job to find the position of the current job,
// and to determine if there are any jobs besides the currently running job
for(int i = 0; i<priqueue_size(ready_q); ++i){
current_job = priqueue_at(ready_q, i);
if(active_core[core_id] == current_job->value[0]){
// Mark position of currently running job
position = i;
}
else{
if(!current_job->finished){
// and not already running...
if(0 > current_job->core){
no_other_jobs = 1;
}
}
}
}
assert(position >= 0);
// If there are no other active jobs, there is nothing to do
if(!no_other_jobs){
return current_job_number;
}
if(DEBUG){
printf("Removing running job %d at position %d, current size is %d...\n", active_core[core_id], position, priqueue_size(ready_q));
}
current_job = (job_t*)priqueue_remove_at(ready_q, position);
if(DEBUG){
printf("Job %d removed, current size is %d, updating metrics...\n", current_job->value[0], priqueue_size(ready_q));
}
if(current_job->value[0] != active_core[core_id]){
printf("Sanity check failed in quantum expired...\n");
printf("The job removed %d does not match the expected job %d\n", current_job->value[0], active_core[core_id]);
assert(0);
}
active_core[core_id] = -1;
// update its time
update_running_time(current_job, time);
if(DEBUG){
printf("Time updated, checking job again...\n");
printf("Old job %d is OK...\n", current_job->value[0]);
}
// Reset its core
current_job->core = -1;
// Reset its active time to ensure proper running time accounting
current_job->value[6] = -1;
// If the job has yet to run, reset its latency
if(0 == current_job->value[4]){
current_job->value[7] = -1;
}
if(DEBUG){
printf("Adding old job to back of queue...\n");
}
// Add the old job to the back of the queue
priqueue_offer(ready_q, current_job);
if(DEBUG){
printf("Checking that the job is in fact in the queue...\n");
}
int sanity_check = current_job->value[0];
current_job = (job_t *)get_job(sanity_check);
if(NULL == current_job){
printf("get_job returned NULL, The job was not properly inserted...\n");
assert(0);
}
if(DEBUG){
printf("The job is in the queue\n");
printf("Scheduling next job...\n");
}
// Call to schedule the next job to run
next_job_RR(NULL, time);
if(DEBUG){
printf("Updating time...\n");
}
// Update time
update_time(time);
if(DEBUG){
printf("Done with quantum expired...\n");
print_queue();
}
return active_core[core_id];
}
/**
Returns the average waiting time of all jobs scheduled by your scheduler.
Assumptions:
- This function will only be called after all scheduling is complete (all
jobs that have arrived will have finished and no new jobs will arrive).
@return the average waiting time of all jobs scheduled.
*/
float scheduler_average_waiting_time(){
job_t * current_job;
int sum = 0;
for(int i = 0; i<priqueue_size(ready_q); ++i){
current_job = (job_t *)priqueue_at(ready_q, i);
int total, waiting;
total = current_job->value[5] - current_job->value[1];
waiting = total - current_job->value[2];
if(DEBUG){
printf("Job %d waited %d time units\n", current_job->value[0], waiting);
}
// waiting time is total time less running time
sum += waiting;
}
return (1.0 * sum)/priqueue_size(ready_q);
}
/**
Returns the average turnaround time of all jobs scheduled by your scheduler.
"turnaround time" is the total amount of time required to complete the process.
This is the sum of the waiting time and the running time, or equivalently the
time from arrival to completion.
Assumptions:
- This function will only be called after all scheduling is complete (all
jobs that have arrived will have finished and no new jobs will arrive).
@return the average turnaround time of all jobs scheduled.
*/
float scheduler_average_turnaround_time(){
int time = 0;
job_t *current_job;
for(int i = 0; i<priqueue_size(ready_q); ++i){
current_job = (job_t*)priqueue_at(ready_q, i);
if(DEBUG){
printf("Job %d took a total of %d time units\n", current_job->value[0], current_job->value[5]-current_job->value[1]);
}
// Add in total time (end-start)
time += (current_job->value[5] - current_job->value[1]);
}
return (1.0 * time)/priqueue_size(ready_q);
}
/**
Returns the average response time of all jobs scheduled by your scheduler.
"Response time" is what everyone else calls "scheduling latency"
Assumptions:
- This function will only be called after all scheduling is complete (all
jobs that have arrived will have finished and no new jobs will arrive).
@return the average response time of all jobs scheduled.
*/
float scheduler_average_response_time(){
int time = 0;
job_t *current_job;
for(int i = 0; i<priqueue_size(ready_q); ++i){
current_job = (job_t*)priqueue_at(ready_q, i);
if(DEBUG){
printf("Job %d had latency of %d time units\n", current_job->value[0], current_job->value[7]);
}
time += current_job->value[7];
}
return (1.0 * time)/priqueue_size(ready_q);
}
/**
Free any memory associated with your scheduler.
Assumptions:
- This function will be the last function called in your library.
*/
void scheduler_clean_up(){
job_t * curr;
while(0 < priqueue_size(ready_q)){
curr = (job_t*)priqueue_poll(ready_q);
free(curr->value);
}
curr = NULL;
priqueue_destroy(ready_q);
free(ready_q);
free(active_core);
}
/**
This function may print out any debugging information you choose. This
function will be called by the simulator after every call the simulator
makes to your scheduler.
In our provided output, we have implemented this function to list the jobs in
the order they are to be scheduled. Furthermore, we have also listed the
current state of the job (either running on a given core or idle).
For example, if we have a non-preemptive algorithm and job(id=4) has began
running, job(id=2) arrives with a higher priority, and job(id=1) arrives with
a lower priority, the output in our sample output will be:
2(-1) 4(0) 1(-1)
This function is not required and will not be graded. You may leave it
blank if you do not find it useful.
#### NOTE NOTE NOTE ####
This function is also not called with arguments, even though the *included* signature
clearly takes arguments. This means if you try to use the parameter, assuming it
is there, you are going to have a bad time. I will seriously punch the original
authors of this code in the face if I ever meet them. I shouldn't have to go
through their code to look for intentionally inserted errors.
*/
void scheduler_show_queue(priqueue_t* q){
if(DEBUG){
printf("\n");
for(int i=0; i<priqueue_size(ready_q); ++i){
job_t *daJob = (job_t*)priqueue_at(ready_q, i);
printf("\tJob %d:\tArrived:\t%d\tBurst:\t\t%d\tPriority:\t%d\tCore:\t%d\tRunning:\t%d\tComplete:\t%d\n", daJob->value[0], daJob->value[1], daJob->value[2], daJob->value[3], daJob->core, (daJob->core>=0)?1:0, daJob->finished);
printf("\t \tLast active:\t%d\tRuntime:\t%d\n", daJob->value[6], daJob->value[4]);
}
}
}
|
rodhan/STSOData
|
Template/Framework/NSURL+MobilePlatform.h
|
<filename>Template/Framework/NSURL+MobilePlatform.h
//
// NSURL+MobilePlatform.h
// Template
//
// Created by Stadelman, Stan on 11/14/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <Foundation/Foundation.h>
@interface NSURL (MobilePlatform)
@property (nonatomic, copy) NSString *appId;
/*
helper constructor for handling the output of MAFLogonRegistrationContext
*/
-(NSURL *)initWithHost:(NSString *)host port:(int)port protocol:(BOOL)isSecure appId:(NSString *)appId;
/*
base constructor... could be changed slightly, depending on the interface of how configurations are acquired
BaseURL string should be: <protocol>://<host>:<port>
*/
-(NSURL *)initWithBaseURLString:(NSString *)urlString appId:(NSString *)appId;
/*
protocol://host:port/appId/
*/
-(NSURL *)applicationURL;
/*
protocol://host:port/clientlogs
*/
-(NSURL *)clientLogsURL;
/*
protocol://host:port/btx
*/
-(NSURL *)btxURL;
/*
protocol://host:port/clientusage
*/
-(NSURL *)clientUsageURL;
@end
|
rodhan/STSOData
|
Template/Framework/OfflineStore.h
|
//
// OfflineStore.h
// TravelAgency_RKT
//
// Created by <NAME> 8/11/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import "SODataOfflineStore.h"
#import "SODataStore.h"
#import "SODataStoreSync.h"
#import "SODataStoreAsync.h"
#import "ODataStore.h"
@interface OfflineStore : SODataOfflineStore <ODataStore, SODataStore, SODataStoreSync, SODataStoreAsync>
@end
|
rodhan/STSOData
|
Template/Framework/LogonHandler+Usage.h
|
//
// LogonHandler+Usage.h
// TravelAgency_RKT
//
// Created by <NAME> on 7/22/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import "LogonHandler.h"
@interface LogonHandler (Usage)
-(void)startUsageCollection;
@end
|
rodhan/STSOData
|
Template/Framework/LogonHandler+E2ETrace.h
|
<gh_stars>1-10
//
// LogonHandler+E2ETrace.h
// TravelAgency_RKT
//
// Created by <NAME> on 7/18/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import "LogonHandler.h"
#import "SAPE2ETraceManager.h"
@class SupportabilityUploader;
@interface LogonHandler (E2ETrace)
-(SupportabilityUploader *)configuredUploader;
-(void)startTrace;
-(void)endAndUploadTrace;
@end
|
rodhan/STSOData
|
Template/Framework/OnlineStore.h
|
<gh_stars>1-10
//
// OnlineStore.h
// Template
//
// Created by Stadelman, Stan on 8/4/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import "SODataOnlineStore.h"
#import "SODataStore.h"
#import "SODataStoreSync.h"
#import "SODataStoreAsync.h"
#import "ODataStore.h"
@interface OnlineStore : SODataOnlineStore <ODataStore, SODataStore, SODataStoreSync, SODataStoreAsync>
@end
|
rodhan/STSOData
|
Template/FlightDetailsCell.h
|
<filename>Template/FlightDetailsCell.h
//
// FlightDetailsCell.h
// Template
//
// Created by Stadelman, Stan on 9/18/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface FlightDetailsCell : UITableViewCell
@property (weak, nonatomic) IBOutlet UILabel *flightNumberLabel;
@property (weak, nonatomic) IBOutlet UILabel *descriptionLabel;
@property (weak, nonatomic) IBOutlet UILabel *departureTimeLabel;
@property (weak, nonatomic) IBOutlet UILabel *arrivalTimeLabel;
@property (weak, nonatomic) IBOutlet UILabel *departureDateLabel;
@property (weak, nonatomic) IBOutlet UILabel *arrivalDateLabel;
@end
|
rodhan/STSOData
|
Template/TravelDetailsCell.h
|
<gh_stars>1-10
//
// TravelDetailsCell.h
// SMP3ODataAPI
//
// Created by <NAME> 6/5/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface TravelDetailsCell : UITableViewCell
@property (weak, nonatomic) IBOutlet UILabel *passengerCount;
@property (weak, nonatomic) IBOutlet UILabel *ticketCost;
@property (weak, nonatomic) IBOutlet UILabel *taxesCost;
@end
|
rodhan/STSOData
|
Template/Framework/NSDate+STSOData.h
|
//
// NSDate+STSOData.h
// SMP3ODataAPI
//
// Created by <NAME> 8/12/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import <Foundation/Foundation.h>
#import "SODataDuration.h"
@interface NSDate (STSOData)
-(NSString *)dateToODataStringWithFormat:(NSString *)dateFormat;
+(NSDate *)dateFromODataString:(NSString *)oDataString dateFormat:(NSString *)dateFormat;
+(NSDate *)dateFromODataDurationComponents:(SODataDuration *)durationComponents inTimeZone:(NSTimeZone *)timeZone;
@end
|
rodhan/STSOData
|
Template/Framework/SampleModelClasses/FlightSample.h
|
//
// FlightSample.h
// Template
//
// Created by Stadelman, Stan on 9/16/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
@class FlightDetailsSample;
@interface FlightSample : NSObject
@property (nonatomic, strong) NSString *carrid;
@property (nonatomic, strong) NSString *connid;
@property (nonatomic, strong) NSDate *fldate;
@property (nonatomic, strong) FlightDetailsSample *flightDetails;
@property (nonatomic, strong) NSNumber *PRICE;
@property (nonatomic, strong) NSString *CURRENCY;
@property (nonatomic, strong) NSString *PLANETYPE;
@property (nonatomic, strong) NSNumber *SEATSMAX;
@property (nonatomic, strong) NSNumber *SEATSOCC;
@property (nonatomic, strong) NSNumber *PAYMENTSUM;
@property (nonatomic, strong) NSNumber *SEATSMAX_B;
@property (nonatomic, strong) NSNumber *SEATSOCC_B;
@property (nonatomic, strong) NSNumber *SEATSMAX_F;
@property (nonatomic, strong) NSNumber *SEATSOCC_F;
-(NSDate *)timeZoneAccurateDepartureDate;
-(NSDate *)timeZoneVariableArrivalDate; // set timeZone through NSDateFormatter
@end
|
rodhan/STSOData
|
Template/TotalPriceCell.h
|
//
// TotalPriceCell.h
// SMP3ODataAPI
//
// Created by <NAME> 6/5/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface TotalPriceCell : UITableViewCell
@property (weak, nonatomic) IBOutlet UILabel *totalPrice;
@end
|
rodhan/STSOData
|
Template/ReviewItinerary.h
|
<reponame>rodhan/STSOData<gh_stars>1-10
//
// ReviewItinerary.h
// Template
//
// Created by Stadelman, Stan on 9/19/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
@class FlightSearchForm;
@interface ReviewItinerary : UITableViewController
@property (nonatomic, weak) FlightSearchForm *searchForm;
@end
|
rodhan/STSOData
|
Template/Framework/DataController.h
|
<gh_stars>1-10
//
// DataController.h
// Template
//
// Created by Stadelman, Stan on 3/7/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <Foundation/Foundation.h>
#import "ODataStore.h"
#import "SODataStore.h"
#import "SODataStoreSync.h"
#import "SODataStoreAsync.h"
#import "Framework-Constants.h"
@interface DataController : NSObject
@property (nonatomic, assign) WorkingModes workingMode;
@property (nonatomic, strong) id<ODataStore, SODataStore, SODataStoreAsync, SODataStoreSync>localStore;
@property (nonatomic, strong) id<ODataStore, SODataStore, SODataStoreAsync, SODataStoreSync>networkStore;
@property (nonatomic, strong) NSArray *definingRequests;
+ (instancetype)shared;
- (void) loadWorkingMode;
//- (void) switchWorkingMode:(WorkingModes)workingMode;
- (void) scheduleRequestForResource:(NSString *)resourcePath withMode:(SODataRequestModes)mode withEntity:(id<SODataEntity>)entity withCompletion:(void(^)(NSArray *entities, id<SODataRequestExecution>requestExecution, NSError *error))completion;
/* MODEL PROPERTIES HERE FOR THE SAMPLE ONLY--IMPLEMENT MODEL PROPERTIES IN YOUR OWN FILE */
@property (nonatomic, strong) NSArray *bookingsWithExpandSample;
@property (nonatomic, strong) NSArray *travelAgenciesSample;
/* MODEL PROPERTIES SHOULD BE IN MODEL FILE */
@end
|
rodhan/STSOData
|
Template/Framework/Framework-Constants.h
|
<filename>Template/Framework/Framework-Constants.h<gh_stars>0
//
// Framework-Constants.h
// Template
//
// Created by Stadelman, Stan on 8/19/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#ifndef Template_Framework_Constants_h
#define Template_Framework_Constants_h
#define kStoreOpenFinished @"com.sap.sdk.store.open.finished"
#define kStoreOpenDelegateFinished @"com.sap.sdk.store.open.delegate.finished"
#define kRequestFinished @"com.sap.sdk.request.finished"
#define kRequestDelegateFinished @"com.sap.sdk.request.delegate.finished"
#define kLogonFinished @"com.sap.sdk.logon.finished"
#define kOnlineStoreConfigured @"com.sap.sdk.store.online.configured"
#define kOfflineStoreConfigured @"com.sap.sdk.store.offline.configured"
#define kStoreConfigured @"com.sap.sdk.store.configured"
#define kFlushDelegateFinished @"com.sap.sdk.store.flush.delegate.finished"
#define kRefreshDelegateFinished @"com.sap.sdk.store.refresh.delegate.finished"
#define kFlushDelegateFailed @"com.sap.sdk.store.flush.delegate.failed"
#define kRefreshDelegateFailed @"com.sap.sdk.store.refresh.delegate.failed"
#pragma mark - Logger Constants
#define LOG_ONLINESTORE @"com.sap.sdk.log.store.online"
#define LOG_OFFLINESTORE @"com.sap.sdk.log.store.offline"
#define LOG_ODATAREQUEST @"com.sap.sdk.log.sodatarequest"
#define LOG_LOGUPLOAD @"com.sap.sdk.log.logupload"
typedef NS_ENUM(NSInteger, WorkingModes) {
WorkingModeUnset,
WorkingModeOnline,
WorkingModeOffline,
WorkingModeMixed
};
#endif
|
rodhan/STSOData
|
Template/EditTravelAgency.h
|
//
// EditTravelAgency.h
// Template
//
// Created by Stadelman, Stan on 12/2/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
#import "TravelAgencySample.h"
@interface EditTravelAgency : UITableViewController
@property (nonatomic, strong) TravelAgencySample *agency;
@end
|
rodhan/STSOData
|
Template/FlightSearchResultsCell.h
|
<filename>Template/FlightSearchResultsCell.h
//
// FlightSearchResultsCell.h
// Template
//
// Created by Stadelman, Stan on 9/19/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface FlightSearchResultsCell : UITableViewCell
@property (strong, nonatomic) IBOutlet UILabel *departureTimeLabel;
@property (strong, nonatomic) IBOutlet UILabel *arrivalTimeLabel;
@property (strong, nonatomic) IBOutlet UILabel *descriptionLabel;
@property (weak, nonatomic) IBOutlet UILabel *priceLabel;
@end
|
rodhan/STSOData
|
Template/MilesExplanationCell.h
|
<filename>Template/MilesExplanationCell.h
//
// MilesExplanationCell.h
// SMP3ODataAPI
//
// Created by <NAME> 6/6/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface MilesExplanationCell : UITableViewCell
@property (weak, nonatomic) IBOutlet UILabel *descriptionLabel;
@end
|
rodhan/STSOData
|
Template/App-Specific-Constants.h
|
//
// App-Specific-Constants.h
// Template
//
// Created by Stadelman, Stan on 8/19/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
static NSString * const kTravelAgencyCollection = @"TravelagencyCollection";
static NSString * const kTravelAgencyID = @"agencynum";
static NSString * const kTravelAgencyName = @"NAME";
static NSString * const kTravelAgencyStreet = @"STREET";
static NSString * const kTravelAgencyCity = @"CITY";
static NSString * const kTravelAgencyRegion = @"REGION";
static NSString * const kTravelAgencyPostalCode = @"POSTCODE";
static NSString * const kTravelAgencyCountry = @"COUNTRY";
static NSString * const kTravelAgencyTelephoneNumber = @"TELEPHONE";
static NSString * const kTravelAgencyURL = @"URL";
#define kODataDateFormat @"yyyy-MM-dd'T'hh:mm:ss"
|
rodhan/STSOData
|
Template/SODataOfflineStoreOptions+READAPI.h
|
<gh_stars>1-10
//
// SODataOfflineStoreOptions+READAPI.h
// Template
//
// Created by Stadelman, Stan on 10/27/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import "SODataOfflineStoreOptions.h"
@interface SODataOfflineStoreOptions (READAPI)
@end
|
rodhan/STSOData
|
Template/Framework/SampleModelClasses/TravelAgencySample.h
|
//
// TravelAgencySample.h
// Template
//
// Created by Stadelman, Stan on 12/2/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <Foundation/Foundation.h>
#import "SODataEntity.h"
@interface TravelAgencySample : NSObject
@property (nonatomic, strong) NSString *agencynum;
@property (nonatomic, strong) NSString *NAME;
@property (nonatomic, strong) NSString *STREET;
@property (nonatomic, strong) NSString *POSTBOX;
@property (nonatomic, strong) NSString *POSTCODE;
@property (nonatomic, strong) NSString *CITY;
@property (nonatomic, strong) NSString *COUNTRY;
@property (nonatomic, strong) NSString *REGION;
@property (nonatomic, strong) NSString *TELEPHONE;
@property (nonatomic, strong) NSString *URL;
@property (nonatomic, strong) NSString *LANGU;
@property (nonatomic, strong) NSString *CURRENCY;
@property (nonatomic, strong) NSString *mimeType;
/*
Since the TravelAgencies are CREATE/UPDATE/DELETE-enabled, it is most convenient to also have access to the underlying SODataEntity.
I don't bother to store the SODataEntity for the READ-only model objects.
*/
@property (nonatomic, strong) id<SODataEntity> entity;
-(id<SODataEntity>)modifiedEntity;
@end
|
rodhan/STSOData
|
Template/Framework/DataController+CUDRequests.h
|
<filename>Template/Framework/DataController+CUDRequests.h
//
// DataController+CUDRequests.h
// TravelAgency_RKT
//
// Created by <NAME> on 8/12/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import "DataController.h"
#import "SODataEntity.h"
@class SODataEntityDefault;
@interface DataController (CUDRequests)
-(void)updateEntity:(id<SODataEntity>) entity withCompletion:(void(^)(BOOL success))completion;
-(void)deleteEntity:(id<SODataEntity>) entity withCompletion:(void(^)(BOOL success))completion;
-(void)createEntity:(id<SODataEntity>) entity inCollection:(NSString *)collection withCompletion:(void(^)(BOOL success, SODataEntityDefault *newEntity))completion;
@end
|
rodhan/STSOData
|
Template/Framework/LogonHandler+Logging.h
|
//
// LogonHandler+Logging.h
// TravelAgency_RKT
//
// Created by <NAME> on 8/12/14.
// Copyright (c) 2014 SAP. All rights reserved.
//
#import "LogonHandler.h"
#import "SAPClientLogManager.h"
@interface LogonHandler (Logging)
- (void) setupLogging;
- (void) uploadLogs;
@end
|
rodhan/STSOData
|
Template/HomeScreen.h
|
//
// HomeScreen.h
// Template
//
// Created by Stadelman, Stan on 9/19/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface HomeScreen : UIViewController
@end
|
rodhan/STSOData
|
Template/AppDelegate.h
|
//
// AppDelegate.h
// Template
//
// Created by Stadelman, Stan on 8/4/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
#import "NSURL+MobilePlatform.h"
@interface AppDelegate : UIResponder <UIApplicationDelegate>
@property (strong, nonatomic) UIWindow *window;
@property (nonatomic, strong) NSURL *baseURL;
@end
|
rodhan/STSOData
|
Template/Framework/SampleModelClasses/BookingSample.h
|
<filename>Template/Framework/SampleModelClasses/BookingSample.h<gh_stars>1-10
//
// BookingSample.h
// Template
//
// Created by Stadelman, Stan on 9/22/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
@class FlightSample;
@interface BookingSample : NSObject
@property (nonatomic, strong) NSString *carrid;
@property (nonatomic, strong) NSString *connid;
@property (nonatomic, strong) NSDate *fldate;
@property (nonatomic, strong) NSString *bookid;
@property (nonatomic, strong) NSString *CUSTOMID;
@property (nonatomic, strong) NSString *CUSTTYPE;
@property (nonatomic, strong) NSString *SMOKER;
@property (nonatomic, strong) NSString *WUNIT;
@property (nonatomic, strong) NSNumber *LUGGWEIGHT;
@property (nonatomic, strong) NSString *INVOICE;
@property (nonatomic, strong) NSString *CLASS;
@property (nonatomic, strong) NSNumber *FORCURAM;
@property (nonatomic, strong) NSString *FORCURKEY;
@property (nonatomic, strong) NSNumber *LOCCURAM;
@property (nonatomic, strong) NSString *LOCCURKEY;
@property (nonatomic, strong) NSDate *ORDER_DATE;
@property (nonatomic, strong) NSString *COUNTER;
@property (nonatomic, strong) NSString *AGENCYNUM;
@property (nonatomic, strong) NSString *CANCELLED;
@property (nonatomic, strong) NSString *RESERVED;
@property (nonatomic, strong) NSString *PASSNAME;
@property (nonatomic, strong) NSString *PASSFORM;
@property (nonatomic, strong) NSDate *PASSBIRTH;
@property (nonatomic, strong) FlightSample *bookedFlight;
@end
|
rodhan/STSOData
|
Template/Framework/LogonHandler.h
|
<reponame>rodhan/STSOData
//
// LogonHandler
//
//
//
// Copyright (c) 2013 RIG. All rights reserved.
//
#import <Foundation/Foundation.h>
#import "MAFLogonNGPublicAPI.h"
#import "MAFLogonUIViewManager.h"
#import "MAFLogonNGDelegate.h"
#import "HttpConversationManager.h"
#import "MAFLogonRegistrationData.h"
#import "SODataOfflineStoreOptions.h"
#import "NSURL+MobilePlatform.h"
#import "SAPClientLogManager.h"
@interface LogonHandler : NSObject <MAFLogonNGDelegate>
@property (strong, nonatomic) MAFLogonUIViewManager *logonUIViewManager;
@property (strong, nonatomic) NSObject<MAFLogonNGPublicAPI> *logonManager;
@property (strong, nonatomic) HttpConversationManager* httpConvManager;
@property (strong, nonatomic) MAFLogonRegistrationData *data;
@property (strong, nonatomic) NSURL *baseURL;
- (SODataOfflineStoreOptions *)options;
@property (strong, nonatomic) id<SAPClientLogManager>logManager;
@property (nonatomic, assign) BOOL collectUsageData;
+(instancetype)shared;
@end
|
rodhan/STSOData
|
Template/Framework/ODataStore.h
|
//
// ODataStore.h
// Template
//
// Created by Stadelman, Stan on 8/20/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <Foundation/Foundation.h>
@protocol ODataStore <NSObject>
@required
- (void) openStoreWithCompletion:(void(^)(BOOL success))completion;
@optional
- (void) flushAndRefresh:(void(^)(BOOL success))completion;
@end
|
rodhan/STSOData
|
Template/Framework/SampleModelClasses/FlightDetailsSample.h
|
<gh_stars>0
//
// FlightDetailsSample.h
// Template
//
// Created by Stadelman, Stan on 9/16/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
@class SODataDuration;
@interface FlightDetailsSample : NSObject
@property (nonatomic, strong) NSString *countryFrom;
@property (nonatomic, strong) NSString *cityFrom;
@property (nonatomic, strong) NSString *airportFrom;
@property (nonatomic, strong) NSString *countryTo;
@property (nonatomic, strong) NSString *airportTo;
@property (nonatomic, assign) NSNumber *flightTime;
@property (nonatomic, strong) SODataDuration *departureTime;
@property (nonatomic, strong) SODataDuration *arrivalTime;
@property (nonatomic, strong) NSNumber *distance;
@property (nonatomic, strong) NSNumber *distanceUnit;
@property (nonatomic, strong) NSNumber *flightType;
@property (nonatomic, strong) NSNumber *period;
@end
|
rodhan/STSOData
|
Template/TravelAgencyCell.h
|
<filename>Template/TravelAgencyCell.h
//
// TravelAgencyCell.h
// Template
//
// Created by Stadelman, Stan on 12/2/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface TravelAgencyCell : UITableViewCell
@property (weak, nonatomic) IBOutlet UILabel *agencyName;
@property (weak, nonatomic) IBOutlet UILabel *agencyPhone;
@property (weak, nonatomic) IBOutlet UILabel *agencyStreetCityState;
@property (weak, nonatomic) IBOutlet UILabel *agencyCountryPostcode;
@property (weak, nonatomic) IBOutlet UILabel *agencyURL;
@end
|
rodhan/STSOData
|
Template/FlightSearchResults.h
|
<reponame>rodhan/STSOData<gh_stars>1-10
//
// FlightSearchResults.h
// Template
//
// Created by Stadelman, Stan on 9/19/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
@class FlightSearchForm;
typedef NS_ENUM(NSInteger, FlightDirection) {
Departing,
Returning
};
@interface FlightSearchResults : UITableViewController <UITableViewDataSource, UITableViewDelegate>
@property (nonatomic, weak) FlightSearchForm *searchForm;
@property (nonatomic, assign) FlightDirection direction;
@property (nonatomic, strong) NSMutableDictionary *searchResults;
- (void)searchAvailableFlights:(NSDictionary *)searchParameters;
@end
|
rodhan/STSOData
|
Template/FlightSearchForm.h
|
//
// FlightSearchForm.h
// Template
//
// Created by Stadelman, Stan on 9/19/14.
// Copyright (c) 2014 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
@class FlightSample;
@interface FlightSearchForm : UITableViewController
@property (nonatomic, strong) NSDate *departureDate;
@property (nonatomic, strong) NSDate *returnDate;
@property (nonatomic, strong) NSString *departureAirportCity;
@property (nonatomic, strong) NSString *returnAirportCity;
@property (nonatomic, strong) NSNumber *numPassengers;
@property (nonatomic, strong) NSString *classPreference;
@property (nonatomic, strong) NSNumber *minPrice;
@property (nonatomic, strong) NSNumber *maxPrice;
@property (nonatomic, strong) FlightSample *selectedDepartureFlight;
@property (nonatomic, strong) FlightSample *selectedReturnFlight;
@end
|
rapinto/LocalNotificationManager
|
Classes/LocalNotificationManager.h
|
<reponame>rapinto/LocalNotificationManager
//
// LocalNotificationManager.h
// Pong
//
// Created by Ades on 11/09/2015.
// Copyright (c) 2015 Ades. All rights reserved.
//
#import <Foundation/Foundation.h>
@interface LocalNotificationManager : NSObject
+ (void)registerLocalNotifications;
+ (void)schedulLocalNotification:(UILocalNotification*)localNotification
withKey:(NSString*)notificationKey;
+ (void)cancelScheduledLocalNotificationWithKey:(NSString*)notificationKey;
@end
|
martha9010/arduino-lorawan
|
src/Arduino_LoRaWAN.h
|
/*
Module: Arduino_LoRaWAN.h
Function:
The base class for arduino-lmic-based LoRaWAN nodes.
Copyright notice:
See LICENSE file accompanying this project.
Author:
<NAME>, MCCI Corporation October 2016
*/
#ifndef _ARDUINO_LORAWAN_H_ /* prevent multiple includes */
#define _ARDUINO_LORAWAN_H_
#include <cstdint>
#include <Arduino.h>
#ifndef _MCCIADK_ENV_H_
# include <mcciadk_env.h>
#endif
#include <cstring>
#include <arduino_lmic_hal_configuration.h>
/// \brief construct Arduino LoRaWAN semantic version
#define ARDUINO_LORAWAN_VERSION_CALC(major, minor, patch, local) \
(((major) << 24u) | ((minor) << 16u) | ((patch) << 8u) | (local))
/// \brief library semantic version
/// \note local "0" is *greater than* any local non-zero; use
/// \ref ARDUINO_LORAWAN_VERSION_COMPARE_LT() to compare relative versions.
///
#define ARDUINO_LORAWAN_VERSION \
ARDUINO_LORAWAN_VERSION_CALC(0, 9, 0, 0) /* v0.9.0 */
#define ARDUINO_LORAWAN_VERSION_GET_MAJOR(v) \
(((v) >> 24u) & 0xFFu)
#define ARDUINO_LORAWAN_VERSION_GET_MINOR(v) \
(((v) >> 16u) & 0xFFu)
#define ARDUINO_LORAWAN_VERSION_GET_PATCH(v) \
(((v) >> 8u) & 0xFFu)
#define ARDUINO_LORAWAN_VERSION_GET_LOCAL(v) \
((v) & 0xFFu)
/// \brief convert a semantic version to an integer.
#define ARDUINO_LORAWAN_VERSION_TO_INT(v) \
(((v) & 0xFFFFFF00u) | (((v) - 1) & 0xFFu))
/// \brief compare two semantic versions
/// \return \c true if \b a is less than \b b (as a semantic version).
#define ARDUINO_LORAWAN_VERSION_COMPARE_LT(a, b) \
(ARDUINO_LORAWAN_VERSION_TO_INT(a) < ARDUINO_LORAWAN_VERSION_TO_INT(b))
/// \brief compare two semantic versions
/// \return \c true if \b a is greater than \b b (as a semantic version).
#define ARDUINO_LORAWAN_VERSION_COMPARE_GT(a, b) \
(ARDUINO_LORAWAN_VERSION_TO_INT(a) > ARDUINO_LORAWAN_VERSION_TO_INT(b))
class Arduino_LoRaWAN;
/*
|| You can use this for declaring event functions...
|| or use a lambda if you're bold; but remember, no
|| captures in that case. Yes, we're *not* using one
|| of the several thousand C++ ways of doing this;
|| we're using C-compatible callbacks.
*/
MCCIADK_BEGIN_DECLS
typedef void ARDUINO_LORAWAN_EVENT_FN(void *, uint32_t);
MCCIADK_END_DECLS
namespace Arduino_LMIC {
// return the country code
constexpr uint16_t kCountryCode(char c1, char c2)
{
return (c1 < 'A' || c1 > 'Z' || c2 < 'A' || c2 > 'Z')
? 0
: ((c1 << 8) | c1);
}
} // namespace Arduino_LMIC
class Arduino_LoRaWAN
{
public:
/*
|| the internal LMIC wrapper
*/
class cLMIC; /* forward reference, see Arduino_LoRaWAN_lmic.h */
/*
|| the event logger
*/
class cEventLog; /* forward reference, see Arduino_LoRaWAN_EventLog.h */
/*
|| debug things
*/
enum {
LOG_BASIC = 1 << 0,
LOG_ERRORS = 1 << 1,
LOG_VERBOSE = 1 << 2,
};
// We must replicate the C structure from
// "lmic.h" inside the class. Otherwise we'd
// need to have all of lmic.h in scope everywhere,
// which could cause naming clashes.
using lmic_pinmap = Arduino_LMIC::HalPinmap_t;
// the networks that we support
enum class NetworkID_t : std::uint32_t
{
TheThingsNetwork,
Actility,
Helium,
machineQ,
Senet,
Senra,
Swisscom,
ChirpStack,
Generic
};
// change network code to text
static constexpr const char * NetworkID_t_GetName(NetworkID_t net)
{
return (net == NetworkID_t::TheThingsNetwork) ? "The Things Network" :
(net == NetworkID_t::Actility) ? "Actility" :
(net == NetworkID_t::Helium) ? "Helium" :
(net == NetworkID_t::machineQ) ? "machineQ" :
(net == NetworkID_t::Senet) ? "Senet" :
(net == NetworkID_t::Senra) ? "Senra" :
(net == NetworkID_t::Swisscom) ? "Swisscom" :
(net == NetworkID_t::ChirpStack) ? "ChirpStack" :
(net == NetworkID_t::Generic) ? "Generic" :
"<<unknown network>>"
;
}
/*
|| provisioning things:
*/
// the provisioning styles.
enum class ProvisioningStyle
{
kNone, kABP, kOTAA
};
// information provided for ABP provisioning
struct AbpProvisioningInfo
{
uint8_t NwkSKey[16];
uint8_t AppSKey[16];
uint32_t DevAddr;
uint32_t NetID;
uint32_t FCntUp;
uint32_t FCntDown;
};
// information provided for OTAA provisioning
struct OtaaProvisioningInfo
{
uint8_t AppKey[16];
uint8_t DevEUI[8];
uint8_t AppEUI[8];
};
// the provisioning blob.
struct ProvisioningInfo
{
ProvisioningStyle Style;
AbpProvisioningInfo AbpInfo;
OtaaProvisioningInfo OtaaInfo;
};
struct ProvisioningTable
{
const ProvisioningInfo *pInfo;
unsigned nInfo;
};
// US-like regions use a 72-bit mask of enabled channels.
// CN474-like regions use a 96-bit mask of enabled channels.
// EU-like regions use a a table of 16 frequencies with
// 100-Hz resolution (at 24 bits, that's 48 bytes)
// In this encoding, we use zeros to represent disabled channels
struct SessionChannelMask_Header
{
enum eMaskKind : uint8_t { kEUlike = 0, kUSlike = 1 };
uint8_t Tag; ///< discriminator, eMaskKind.
uint8_t Size; ///< size of SessionChannelMask, in bytes
};
template <uint32_t a_nCh>
struct SessionChannelMask_US_like
{
static constexpr uint32_t nCh = a_nCh;
static_assert(
1 <= a_nCh && a_nCh <= 96,
"number of channels must be in [1..96]"
);
// the fields
SessionChannelMask_Header Header; ///< the common header
uint8_t ChannelMap[2 * ((nCh + 15) / 16)]; ///< the channel enable mask
uint8_t ChannelShuffleMap[2 * ((nCh + 15) / 16)]; ///< the channel shuffle mask;
/// a multiple of 16 bits to match
/// the LMIC.
// the methods
bool isEnabled(unsigned iCh) const
{
if (iCh < nCh)
{
return this->ChannelMap[iCh / 8] & (1 << (iCh & 7));
}
else
return false;
}
void clearAll()
{
for (auto i = 0u; i < (nCh + 7) / 8; ++i)
{
this->ChannelMap[i] = 0;
this->ChannelShuffleMap[i] = 0;
}
}
// change enable state of indicated channel
// and return previous state.
bool enable(unsigned iCh, bool fEnable)
{
if (iCh < nCh)
{
auto pByte = this->ChannelMap + iCh/8;
uint8_t mask = 1 << (iCh & 7);
auto v = *pByte;
bool fResult = (v & mask) != 0;
if (fEnable)
*pByte = uint8_t(v | mask);
else
*pByte = uint8_t(v & ~mask);
return fResult;
}
else
return false;
}
};
///
/// \brief "band" data for rate limiting in an EU-like configuration
///
struct SessionChannelBand
{
// the fields
uint16_t txDutyDenom; ///< duty cycle limitation: 1/txDutyDenom
uint8_t txPower; ///< maximum TX power, this band
uint8_t lastChannel; ///< last used channel in this band
uint32_t ostimeAvail; ///< when will it be available relative to
/// GPStime in ostime_t ticks.
};
///
/// \brief session data for channels in an EU-like configuration
///
/// \param a_nCh specifies the number of channels this class instance
/// should handle. Must be in 1..16.
///
/// \param a_nBands specifies the maximum number of bands to be supported.
///
template <uint32_t a_nCh = 16, uint32_t a_nBands = 4>
struct SessionChannelMask_EU_like
{
/// \brief number of channels declared for this class instance
static constexpr uint32_t nCh = a_nCh;
static_assert(
1 <= a_nCh && a_nCh <= 16,
"number of channels must be in [1..16]"
);
/// \brief number of bands declared for this class instance
static constexpr uint32_t nBands = a_nBands;
static_assert(
1 <= a_nBands && a_nBands <= 4,
"number of channels must be in [1..4]"
);
// the fields
SessionChannelMask_Header Header; ///< the header
uint32_t ChannelBands; ///< band number for each channel
uint16_t ChannelMap; ///< mask of enabled channels, one bit per channel
uint16_t ChannelShuffleMap; ///< the channel re-use shuffle bitmap
uint16_t ChannelDrMap[nCh]; ///< data rates for each channel
uint8_t UplinkFreq[nCh * 3]; ///< packed downlink frequencies for each channel (100 Hz units)
uint8_t DownlinkFreq[nCh * 3]; ///< packed uplink frequencies for each channel.
SessionChannelBand Bands[nBands]; ///< band limiting info
// useful methods
///
/// \brief set the band number for a given channel
///
/// \param [in] ch channel
/// \param [in] band band (in 0..3)
///
void setBand(unsigned ch, unsigned band)
{
uint32_t mask = 0x3 << (2 * ch);
uint32_t v = band << (2 * ch);
this->ChannelBands ^= (this->ChannelBands ^ v) & mask;
}
///
/// \brief get the band for a given channel
///
/// \param [in] ch channel
///
/// \return band number, in 0..3.
///
uint32_t getBand(unsigned ch) const
{
return (this->ChannelBands >> (2 * ch)) & 0x3u;
}
/// \brief return the recorded frequency of a given channel in Hz from a given table
uint32_t getFrequency(const uint8_t (&freq)[nCh * 3], unsigned iCh) const
{
if (iCh > nCh)
return 0;
else
{
auto const chPtr = freq + iCh * 3;
return (uint32_t(chPtr[0] << 16) |
uint32_t(chPtr[1] << 8) |
uint32_t(chPtr[2])) * 100;
}
}
///
/// \brief record the frequency of a given channel.
/// \param [in] freq packed table of frequencies
/// \param [in] iCh channel index
/// \param [in] freq frequency in Hertz
///
/// \return true if channel number and frequency were valid,
/// false otherwise.
///
bool setFrequency(uint8_t (&freq)[nCh * 3], unsigned iCh, uint32_t frequency)
{
if (iCh > nCh)
return false;
const uint32_t reducedFreq = frequency / 100;
if (reducedFreq > 0xFFFFFFu)
return false;
auto const chPtr = freq + iCh * 3;
chPtr[0] = uint8_t(reducedFreq >> 16);
chPtr[1] = uint8_t(reducedFreq >> 8);
chPtr[2] = uint8_t(reducedFreq);
}
/// \brief clear all entries in the channel table.
void clearAll()
{
this->ChannelMap = 0;
this->ChannelShuffleMap = 0;
std::memset(this->ChannelDrMap, 0, sizeof(this->ChannelDrMap));
std::memset(this->UplinkFreq, 0, sizeof(this->UplinkFreq));
std::memset(this->DownlinkFreq, 0, sizeof(this->DownlinkFreq));
}
};
typedef union SessionChannelMask_u
{
SessionChannelMask_Header Header;
SessionChannelMask_EU_like<16> EUlike;
SessionChannelMask_US_like<64 + 8> USlike;
SessionChannelMask_US_like<96> CNlike;
} SessionChannelMask;
/// \brief discriminate SessionInfo variants
enum SessionInfoTag : uint8_t
{
kSessionInfoTag_Null = 0x00, ///< indicates that there's no info.
kSessionInfoTag_V1 = 0x01, ///< indicates the V1 structure
kSessionInfoTag_V2 = 0x02, ///< indicates the V1 structure
};
/// \brief Header for SessionInfo; allows versioning.
struct SessionInfoHeader
{
SessionInfoTag Tag; // the discriminator
uint8_t Size; // size of the overall structure
};
/// \brief Version 1 of session info.
/// We send this up after a join.
struct SessionInfoV1
{
// to ensure packing, we just repeat the header.
SessionInfoTag Tag; // kSessionInfoTag_V1
uint8_t Size; // sizeof(SessionInfoV1)
uint8_t Rsv2; // reserved
uint8_t Rsv3; // reserved
uint32_t NetID; // the network ID
uint32_t DevAddr; // device address
uint8_t NwkSKey[16]; // network session key
uint8_t AppSKey[16]; // app session key
uint32_t FCntUp; // uplink frame count
uint32_t FCntDown; // downlink frame count
};
/// \brief Version 2 of session info; used in conjunction with.
/// `SessionState`. Omits duplicated info.
struct SessionInfoV2
{
// to ensure packing, we just repeat the header.
uint8_t Tag; // kSessionInfoTag_V1
uint8_t Size; // sizeof(SessionInfoV1)
uint8_t Rsv2; // reserved
uint8_t Rsv3; // reserved
uint32_t NetID; // the network ID
uint32_t DevAddr; // device address
uint8_t NwkSKey[16]; // network session key
uint8_t AppSKey[16]; // app session key
};
/// \brief information about the current session.
///
/// \details
/// This structure is stored persistently if
/// possible, and represents the result of a join. We allow for
/// versioning, primarily so that (if we
/// choose) we can accommodate older versions and very simple
/// storage schemes.
///
/// Older versions of Arduino_LoRaWAN sent version 1 at join,
/// including the frame counts. Newer versions send version 2
/// at join, followed by a SessionState message (which includes
/// the frame counts).
///
/// \see SessionState
///
typedef union SessionInfo_u
{
/// the header, same for all versions
SessionInfoHeader Header;
/// the V1 form used through v0.8 of the Arduino_LoraWAN.
SessionInfoV1 V1;
/// SessionInfo::V2 is used as v0.9 of the Arduino_LoRaWAN,
/// in conjunction with the SessionState message
SessionInfoV2 V2;
} SessionInfo;
/// \brief discriminate SessionState variants
enum SessionStateTag : uint8_t
{
kSessionStateTag_Null = 0x00, ///< indicates that there's no info.
kSessionStateTag_V1 = 0x01, ///< indicates the V1 structure
};
///
/// \brief Session state information
///
/// \details
/// Arduino_LoRaWAN sends this whenever the underlying state might
/// have changed (in particular, after each EV_TXCOMPLETE). The client
/// may store this in non-volatile storage in order to allow for
/// power interruption. This is not necessarily a complete image of
/// MAC state, but is reasonably comprehensive.
///
/// This should be taken as an opaque blob by most clients.
///
struct SessionStateHeader
{
SessionStateTag Tag; ///< versioning info
uint8_t Size; ///< size of embedded data
};
///
/// \brief the first version of SessionState
///
struct SessionStateV1
{
// to ensure packing, we just repeat the header.
SessionStateTag Tag; ///< kSessionStateTag_V1
uint8_t Size; ///< sizeof(SessionStateV1)
uint8_t Region; ///< selected region.
uint8_t LinkDR; ///< Current link DR (per [1.0.2] 5.2)
// above 4 entries make one uint32_t.
// keep uint32_t values together for alignment
uint32_t FCntUp; ///< uplink frame count
uint32_t FCntDown; ///< downlink frame count
uint32_t gpsTime; ///< if non-zero, "as-of" time.
uint32_t globalAvail; ///< osticks to global avail time.
uint32_t Rx2Frequency; ///< RX2 Frequency (in Hz)
uint32_t PingFrequency; ///< class B: ping frequency
// next, the uint16_t values, again for alignment
uint16_t Country; ///< Country code
int16_t LinkIntegrity; ///< the link-integrity counter.
// finally, the uint8_t values
uint8_t TxPower; ///< Current TX power (per LinkADR)
uint8_t Redundancy; ///< NbTrans (in bits 3:0)
uint8_t DutyCycle; ///< Duty cycle (per [1.0.2] 5.3)
uint8_t Rx1DRoffset; ///< RX1 datarate offset
uint8_t Rx2DataRate; ///< RX2 data rate
uint8_t RxDelay; ///< RX window delay
uint8_t TxParam; ///< saved TX param
uint8_t BeaconChannel; ///< class B: beacon channel.
uint8_t PingDr; ///< class B: ping datarate
uint8_t MacRxParamAns; ///< saved LMIC.dn2Ans
uint8_t MacDlChannelAns;///< saved LMIC.macDlChannelAns
uint8_t MacRxTimingSetupAns; ///< saved LMIC.macRxTimingSetupAns;
// at the very end
SessionChannelMask Channels; ///< info about the enabled channels
};
static_assert(sizeof(SessionStateV1) < 256, "SessionStateV1 is too large");
typedef union SessionState_u
{
SessionStateHeader Header;
SessionStateV1 V1;
} SessionState;
/*
|| the constructor.
*/
Arduino_LoRaWAN();
/*
|| the begin function. Call this to start things -- the constructor
|| does not!
*/
bool begin(const Arduino_LMIC::HalPinmap_t *pPinmap);
bool begin(const Arduino_LMIC::HalPinmap_t &pinmap) { return this->begin(&pinmap); };
bool begin(void);
/*
|| the function to call from your loop()
*/
void loop(void);
/*
|| Reset the LMIC
*/
void Reset(void);
/*
|| Shutdown the LMIC
*/
void Shutdown(void);
/*
|| Registering listeners... returns true for
|| success.
*/
bool RegisterListener(ARDUINO_LORAWAN_EVENT_FN *, void *);
/*
|| Dispatch an event to all listeners
*/
void DispatchEvent(uint32_t);
uint32_t GetDebugMask() { return this->m_ulDebugMask; }
uint32_t SetDebugMask(uint32_t ulNewMask)
{
const uint32_t ulOldMask = this->m_ulDebugMask;
this->m_ulDebugMask = ulNewMask;
return ulOldMask;
}
void LogPrintf(
const char *fmt,
...
) __attribute__((__format__(__printf__, 2, 3)));
/* format counts start with 2 for non-static C++ member fns */
/*
|| we only support a single instance, but we don't name it. During
|| begin processing, we register, then we can find it.
*/
static Arduino_LoRaWAN *GetInstance()
{
return Arduino_LoRaWAN::pLoRaWAN;
}
// return the region string to the buffer
const char *GetRegionString(char *pBuf, size_t sizeBuf) const;
// return the region code
enum class Region : uint8_t
{
unknown = 0,
eu868 = 1,
us915,
cn783,
eu433,
au915,
cn490,
as923,
kr920,
in866,
};
Region GetRegion(void) const;
enum class CountryCode : uint16_t
{
none = 0,
JP = Arduino_LMIC::kCountryCode('J', 'P'),
};
CountryCode GetCountryCode() const;
virtual NetworkID_t GetNetworkID() const = 0;
virtual const char *GetNetworkName() const = 0;
bool GetTxReady() const;
typedef void SendBufferCbFn(void *pCtx, bool fSuccess);
bool SendBuffer(
const uint8_t *pBuffer,
size_t nBuffer,
SendBufferCbFn *pDoneFn = nullptr,
void *pCtx = nullptr,
bool fConfirmed = false,
uint8_t port = 1
);
typedef void ReceivePortBufferCbFn(
void *pCtx,
uint8_t uPort,
const uint8_t *pBuffer,
size_t nBuffer
);
void SetReceiveBufferBufferCb(
ReceivePortBufferCbFn *pReceivePortBufferFn,
void *pCtx = nullptr
)
{
this->m_pReceiveBufferFn = pReceivePortBufferFn;
this->m_pReceiveBufferCtx = pCtx;
}
bool GetDevEUI(
uint8_t *pBuf
);
bool GetAppEUI(
uint8_t *pBuf
);
bool GetAppKey(
uint8_t *pBuf
);
// return true iff network seems to be provisioned. Make
// it virtual so it can be overridden if needed.
virtual bool IsProvisioned(void)
{
switch (this->GetProvisioningStyle())
{
case ProvisioningStyle::kABP:
return this->GetAbpProvisioningInfo(nullptr);
case ProvisioningStyle::kOTAA:
return this->GetOtaaProvisioningInfo(nullptr);
case ProvisioningStyle::kNone:
default:
return false;
}
}
// Enable (or disable) link-check mode, which generates uplink ADR
// requests and causes automatic rejoin if the network seems not
// to be responding. Without this, downlink ADR settings are
// honored, but the device will never try to rejoin.
bool SetLinkCheckMode(bool fEnable);
// Data about the currently pending transmit.
struct SendBufferData_t
{
Arduino_LoRaWAN *pSelf;
SendBufferCbFn *pDoneFn;
void *pDoneCtx;
bool fTxPending;
};
protected:
/// \brief client-provided method for region initialization.
///
/// \details
/// NetBeginRegionInit is called after LMIC reset.
/// The client must provide this. Normally it's provided by
/// the network-specific derived class.
///
virtual void NetBeginRegionInit() = 0;
/// \brief notify client about network join.
///
/// \details
/// you may have a \c NetJoin() function.
/// if not, the base function does nothing.
virtual void NetJoin(void)
{ /* NOTHING */ };
/// \brief request client to check whether RX data is available.
///
/// \details
/// You may have a \c NetRxComplete() function; this is called
/// when receive data *may* be available.
/// If not, the base class function calls \c this->m_pReceiveBufferFn
/// if and only if receive data actually is available.
///
virtual void NetRxComplete(void);
/// \brief notify client that transmission has completed.
/// you may have a NetTxComplete() function.
/// if not, the base function does nothing.
virtual void NetTxComplete(void)
{ /* NOTHING */ };
/// \brief return the configured provisioning style.
///
/// you should provide a function that returns the provisioning
/// style from stable storage; if you don't yet have provisioning
/// info, return ProvisioningStyle::kNone
virtual ProvisioningStyle GetProvisioningStyle(void)
{
return ProvisioningStyle::kOTAA;
}
/// \brief return ABP provisioning info.
///
/// Your sketch (or something outside the Arduino_LoRaWAN library)
/// should provide a function that returns provisioning info from
/// persistent storage. Called during initialization. If this returns
/// false, OTAA will be forced. If this returns true (as it should for
/// a saved session), then a call with a non-null pointer will get the
/// filled-in provisioning info.
virtual bool GetAbpProvisioningInfo(
AbpProvisioningInfo *pProvisioningInfo
)
{
// if not provided, default zeros buf and returns false.
if (pProvisioningInfo)
{
memset(
pProvisioningInfo,
0,
sizeof(*pProvisioningInfo)
);
}
return false;
}
/// \brief return OTAA provisioning info.
///
/// you should provide a function that returns
/// OTAA provisioning info from persistent storage. Only called
/// if you return ProvisioningStyle::kOtaa to GetProvisioningStyle().
///
virtual bool GetOtaaProvisioningInfo(
OtaaProvisioningInfo *pProvisioningInfo
)
{
// if not provided, default zeros buf and returns false.
if (pProvisioningInfo)
{
memset(
pProvisioningInfo,
0,
sizeof(*pProvisioningInfo)
);
}
return false;
}
/// \brief Return saved session info (keys)
///
/// if you have persistent storage, you should provide a function
/// that gets the saved session info from persistent storage, or
/// indicate that there isn't a valid saved session. Note that
/// the saved info is opaque to the higher level.
///
/// \return true if \p sessionInfo was filled in, false otherwise.
///
virtual bool GetSavedSessionInfo(
SessionInfo &sessionInfo,
uint8_t *pExtraSessionInfo,
size_t nExtraSessionInfo,
size_t *pnExtraSessionActual
)
{
// if not provided, default zeros buf and returns false.
memset(&sessionInfo, 0, sizeof(sessionInfo));
if (pExtraSessionInfo)
{
memset(pExtraSessionInfo, 0, nExtraSessionInfo);
}
if (pnExtraSessionActual)
{
*pnExtraSessionActual = 0;
}
return false;
}
/// \brief save session info (after join)
///
/// \details
/// if you have persistent storage, you should provide a function that
/// saves session info to persistent storage. This will be called
/// after a successful join.
///
virtual void NetSaveSessionInfo(
const SessionInfo &SessionInfo,
const uint8_t *pExtraSessionInfo,
size_t nExtraSessionInfo
)
{
// default: do nothing.
}
/// \brief get the session state
///
/// \return true if a valid session state was found.
virtual bool NetGetSessionState(
SessionState &State
)
{
// default: not implemented.
return false;
}
/// \brief save the session state
///
/// If not provided, the default does nothing.
///
virtual void NetSaveSessionState(
const SessionState &State
)
{
// default: do nothing.
}
/// \brief return true if verbose logging is enabled.
bool LogVerbose()
{
return (this->m_ulDebugMask & LOG_VERBOSE) != 0;
}
uint32_t m_ulDebugMask;
private:
SendBufferData_t m_SendBufferData;
ReceivePortBufferCbFn *m_pReceiveBufferFn;
void *m_pReceiveBufferCtx;
// this is a 'global' -- it gives us a way to bootstrap
// back into C++ from the LMIC code.
static Arduino_LoRaWAN *pLoRaWAN;
void StandardEventProcessor(
uint32_t ev
);
struct Listener
{
ARDUINO_LORAWAN_EVENT_FN *pEventFn;
void *pContext;
void ReportEvent(uint32_t ev)
{
this->pEventFn(this->pContext, ev);
}
};
Listener m_RegisteredListeners[4];
uint32_t m_nRegisteredListeners;
///
/// \brief Update the downlink frame counter.
/// \param [in] newFCntDown the most recently observed downlink counter.
///
/// \details
/// To save effort for the client, we want to avoid upcalls for changes
/// in the downlink count unless it really seems to have changed.
/// Since the LMIC code is not really obvious as to which events
/// update the downlink count, we simply call this on every event, and
/// watch for changes.
///
void UpdateFCntDown(uint32_t newFCntDown)
{
if (this->m_savedSessionState.Header.Tag == kSessionStateTag_V1 &&
this->m_savedSessionState.V1.FCntDown == newFCntDown)
return;
this->SaveSessionState();
}
/// \brief Internal routine for saving state after join
void SaveSessionInfo();
/// \brief Internal routine to save session state as appropriate
void SaveSessionState();
///
/// \brief build session state object
///
/// \param [in] State reference to the session state object to be initialized.
///
void BuildSessionState(SessionState &State) const;
///
/// \brief apply session state data to current LMIC session
///
/// \param [in] State
bool ApplySessionState(const SessionState &State);
///
/// \brief get session state and apply to the LMIC
///
/// \return true if valid session state was found and applied.
///
bool RestoreSessionState();
/// \brief the internal copy of the session state, used to
/// reduce the number of saves to a minimum. It's initially
/// marked as "not valid".
SessionState m_savedSessionState { .Header = { .Tag = kSessionStateTag_Null } };
};
/****************************************************************************\
|
| Eventually this will get removed for "free" builds. But if you build
| in the Arduino environment, this is going to get hard to override.
|
\****************************************************************************/
#if MCCIADK_DEBUG || 1
# define ARDUINO_LORAWAN_PRINTF(a_check, a_fmt, ...) \
do { \
if (this->a_check()) \
{ \
this->LogPrintf(a_fmt, ## __VA_ARGS__); \
} \
} while (0)
#else
# define ARDUINO_LORAWAN_PRINTF(a_check, a_fmt, ...) \
do { ; } while (0)
#endif
/**** end of Arduino_LoRaWAN.h ****/
#endif /* _ARDUINO_LORAWAN_H_ */
|
KellyCoder/YKPlaceholderView
|
YKPlaceholderView/EmptyPlaceholder/EmptyPlaceholderView.h
|
//
// EmptyPlaceholderView.h
// ComponentDemo
//
// Created by Kevin on 2021/5/11.
//
#import <UIKit/UIKit.h>
NS_ASSUME_NONNULL_BEGIN
typedef void(^EmptyOverlayClicked)(void);
@interface EmptyPlaceholderView : UIView
/** 按钮点击回调 */
@property (nonatomic,copy) EmptyOverlayClicked emptyOverlayClicked;
+ (instancetype)loadXibView;
@end
NS_ASSUME_NONNULL_END
|
KellyCoder/YKPlaceholderView
|
YKPlaceholderView/EmptyPlaceholder/YKPlaceholderHeader.h
|
//
// YKPlaceholderHeader.h
// ComponentDemo
//
// Created by Kevin on 2021/5/11.
//
#ifndef YKPlaceholderHeader_h
#define YKPlaceholderHeader_h
#import "EmptyPlaceholderView.h"
#import "UITableView+Placeholder.h"
#import "UICollectionView+Placeholder.h"
#endif /* YKPlaceholderHeader_h */
|
KellyCoder/YKPlaceholderView
|
YKPlaceholderView/EmptyPlaceholder/UITableView+Placeholder.h
|
//
// UITableView+Placeholder.h
// ComponentDemo
//
// Created by Kevin on 2021/5/11.
//
#import <UIKit/UIKit.h>
NS_ASSUME_NONNULL_BEGIN
@protocol YKTableViewPlaceholderDelegate <NSObject>
@required
/// 无数据占位视图
- (UIView *)yk_makePlaceholderView;
@optional
/// 占位视图显示时,是否可滚动
- (BOOL)yk_enableScrollWhenPlaceholderViewShowing;
@end
@interface UITableView (Placeholder)
- (void)yk_reloadData;
@end
NS_ASSUME_NONNULL_END
|
KellyCoder/YKPlaceholderView
|
YKPlaceholderView/EmptyPlaceholder/UICollectionView+Placeholder.h
|
<gh_stars>1-10
//
// UICollectionView+Placeholder.h
// ComponentDemo
//
// Created by Kevin on 2021/5/11.
//
#import <UIKit/UIKit.h>
NS_ASSUME_NONNULL_BEGIN
@protocol YKCollectionViewPlaceholderDelegate <NSObject>
@required
/// 无数据占位视图
- (UIView *)yk_makePlaceholderView;
@optional
/// 占位视图显示时,是否可滚动
- (BOOL)yk_enableScrollWhenPlaceholderViewShowing;
@end
@interface UICollectionView (Placeholder)
- (void)yk_reloadData;
@end
NS_ASSUME_NONNULL_END
|
gaelfoppolo/SwiftPrecision
|
SwiftPrecisionFramework/SwiftPrecisionFramework.h
|
//
// SwiftPrecisionFramework.h
// SwiftPrecisionFramework
//
// Created by Gaël on 22/09/2018.
// Copyright © 2018 <NAME>. All rights reserved.
//
#import <UIKit/UIKit.h>
//! Project version number for SwiftPrecisionFramework.
FOUNDATION_EXPORT double SwiftPrecisionFrameworkVersionNumber;
//! Project version string for SwiftPrecisionFramework.
FOUNDATION_EXPORT const unsigned char SwiftPrecisionFrameworkVersionString[];
// In this header, you should import all the public headers of your framework using statements like #import <SwiftPrecisionFramework/PublicHeader.h>
|
schneiderlo/ppmlib
|
ppmlib/types.h
|
<reponame>schneiderlo/ppmlib
#ifndef PPM_TYPES_H
#define PPM_TYPES_H
namespace ppm {
using color_t = unsigned char;
struct Color {
color_t r;
color_t g;
color_t b;
};
} // namespace ppm
#endif // PPM_TYPES_H
|
schneiderlo/ppmlib
|
ppmlib/ppm.h
|
<filename>ppmlib/ppm.h
#ifndef PPM_PPM_H
#define PPM_PPM_H
#include <iostream>
#include <vector>
#include "ppmlib/color.h"
#include "ppmlib/types.h"
namespace ppm {
class PPM {
public:
PPM() = default;
PPM(const size_t width, const size_t height, const Color& fill_value);
// Read an image from a stream.
void read(std::istream& is);
// Write the image to an output stream.
void write(std::ostream& os) const;
size_t width() const;
size_t height() const;
Color at(const size_t i, const size_t j) const;
Color& at(const size_t i, const size_t j);
private:
// The color of the image.
//
// They are stored in row-major order.
std::vector<std::vector<Color>> data_;
// Maximum value for each color.
constexpr static color_t max_value_ = 255;
};
[[nodiscard]] PPM read_image(const std::string& path);
void write_image(const PPM& src, const std::string& path);
} // namespace ppm
#endif // PPM_COLOR_H
|
schneiderlo/ppmlib
|
ppmlib/color.h
|
#ifndef PPM_COLOR_H
#define PPM_COLOR_H
#include <iostream>
#include "ppmlib/types.h"
namespace ppm {
// Read a color from a stream.
//
// The beginning of the stream should be of the form "23 233 55". Where 23
// represents the red channel, 233 the green channel and 55 the blue channel.
[[nodiscard]] Color read(std::istream& is);
// Write a Color to an output stream.
void write(std::ostream& os, const Color& color);
} // namespace ppm
#endif // PPM_COLOR_H
|
dfranx/glsl-parser
|
util.h
|
<gh_stars>1-10
#ifndef UTIL_H
#define UTIL_H
#include <stdarg.h> // va_list
#include <vector>
namespace glsl {
// An implementation of std::find
template <typename I, typename T>
static inline I find(I first, I last, const T &value) {
for (; first != last; ++first)
if (*first == value)
return first;
return last;
}
// An implementation of vasprintf
int allocvfmt(char **str, const char *fmt, va_list vp);
// An implementation of vsprintf
int allocfmt(char **str, const char *fmt, ...);
// a tiny wrapper around std::vector so you can provide your own
/*
template <typename T>
struct vector {
size_t size() const { return m_data.size(); }
bool empty() const { return m_data.empty(); }
const T& operator[](size_t index) const { return m_data[index]; }
T& operator[](size_t index) { return m_data[index]; }
T* begin() { return &m_data[0]; }
T* end() { return &m_data[size()]; }
const T* begin() const { return &m_data[0]; }
const T* end() const { return &m_data[size()]; }
void insert(T *at, const T& value = T()) { m_data.insert(m_data.begin() + size_t(at - begin()), value); }
void insert(T *at, const T *beg, const T *end) { m_data.insert(m_data.begin() + size_t(at - begin()), beg, end); }
void push_back(const T &value) { m_data.push_back(value); }
void reserve(size_t size) { m_data.reserve(size); }
T* erase(T *position) { return &*m_data.erase(m_data.begin() + size_t(position - begin())); }
T* erase(T *first, T *last) { return &*m_data.erase(m_data.begin() + size_t(first - begin()), m_data.begin() + size_t(last - begin())); }
void pop_back() { m_data.pop_back(); }
T &front() { return *begin(); }
const T &front() const { return *begin(); }
T &back() { return *(end() - 1); }
const T& back() const { return *(end() - 1); }
void resize(size_t size) { m_data.resize(size); }
private:
std::vector<T> m_data;
};
*/
template <typename T>
using vector = std::vector<T>;
}
#endif
|
pxcland/MV
|
mv.h
|
<filename>mv.h
/* -----------------------------------------------------------------------------
* MV - A Matrix Vector Mathematics Library
* Performs common and useful mathematical operations used in 3D graphics.
* C89 Compliant
* Compiled with: gcc -std=c89 -pedantic -Wall
* www.setsunasoft.com
*
*
* Copyright 2017 <NAME>
*
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
* ----------------------------------------------------------------------------- */
#ifndef MV_H
#define MV_H
#ifdef _MSC_VER
#define _CRT_SECURE_NO_WARNINGS
#endif
#include <math.h>
#include <memory.h>
#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Vector Data Types */
typedef float MVvec2[2];
typedef float MVvec3[3];
typedef float MVvec4[4];
/* Matrix Data Types - Matrices are column major! */
typedef float MVmat2[4];
typedef float MVmat3[9];
typedef float MVmat4[16];
/* Useful constants */
#define MV_PI (3.14159265359f)
#define MV_2PI (6.28318530718f)
#define MV_PIDIV2 (1.57079632679f)
#define MV_PIDIV4 (0.78539816340f)
#define MV_PIDIV180 (0.01745329252f)
#define MV_PIDIV180I (57.2957795131f) /* Inverse of pi/180 */
/* Convert radians and degrees */
#define mvDegToRad(x) ((x) * MV_PIDIV180)
#define mvRadToDeg(x) ((x) * MV_PIDIV180I)
/* ------------------------------------------------------------------- */
/* ---------------------- Vector Operations -------------------------- */
/* ------------------------------------------------------------------- */
/* ATTENTION!! */
/* Functions which take a destination with a type of void* or float* */
/* don't protect against writing out of bounds. For example, copying */
/* an MVvec4 to an MVvec2 will overwrite 2 extra floats of whatever. */
/* set vector */
#define mvVecSet2(v, x, y) v[0] = x; v[1] = y;
#define mvVecSet3(v, x, y, z) v[0] = x; v[1] = y; v[2] = z;
#define mvVecSet4(v, x, y, z, w) v[0] = x; v[1] = y; v[2] = z; v[3] = w;
/* copy vector */
void mvVecCopy2(void* dst, const void* src) { memcpy(dst, src, sizeof(MVvec2)); }
void mvVecCopy3(void* dst, const void* src) { memcpy(dst, src, sizeof(MVvec3)); }
void mvVecCopy4(void* dst, const void* src) { memcpy(dst, src, sizeof(MVvec4)); }
/* vector addition and subtraction: r = a +/- b */
void mvVecAdd2(float* r, const float* a, const float* b) { r[0] = a[0] + b[0]; r[1] = a[1] + b[1]; }
void mvVecAdd3(float* r, const float* a, const float* b) { r[0] = a[0] + b[0]; r[1] = a[1] + b[1]; r[2] = a[2] + b[2]; }
void mvVecAdd4(float* r, const float* a, const float* b) { r[0] = a[0] + b[0]; r[1] = a[1] + b[1]; r[2] = a[2] + b[2]; r[3] = a[3] + b[3]; }
void mvVecSub2(float* r, const float* a, const float* b) { r[0] = a[0] + b[0]; r[1] = a[1] + b[1]; }
void mvVecSub3(float* r, const float* a, const float* b) { r[0] = a[0] + b[0]; r[1] = a[1] + b[1]; r[2] = a[2] + b[2]; }
void mvVecSub4(float* r, const float* a, const float* b) { r[0] = a[0] + b[0]; r[1] = a[1] + b[1]; r[2] = a[2] + b[2]; r[3] = a[3] + b[3]; }
/* scale vector by factor */
void mvVecScale2(float* v, float factor) { v[0] *= factor; v[1] *= factor; }
void mvVecScale3(float* v, float factor) { v[0] *= factor; v[1] *= factor; v[2] *= factor;}
void mvVecScale4(float* v, float factor) { v[0] *= factor; v[1] *= factor; v[2] *= factor; v[3] *= factor; }
/* cross product */
void mvVecCrossProduct(float* r, const float* a, const float* b)
{
r[0] = (a[1] * b[2]) - (b[1] * a[2]);
r[1] = (-a[0] * b[2]) + (b[0] * a[2]);
r[2] = (a[0] * b[1]) - (b[0] * a[1]);
}
/* scalar product */
float mvVecScalarProduct2(const float* a, const float* b) { return (a[0] * b[0]) + (a[1] * b[1]); }
float mvVecScalarProduct3(const float* a, const float* b) { return (a[0] * b[0]) + (a[1] * b[1]) + (a[2] * b[2]); }
float mvVecScalarProduct4(const float* a, const float* b) { return (a[0] * b[0]) + (a[1] * b[1]) + (a[2] * b[2]) + (a[3] * b[3]); }
/* vector length */
float mvVecLength2(const float* v) { return (float)sqrt((v[0] * v[0]) + (v[1] * v[1])); }
float mvVecLength3(const float* v) { return (float)sqrt((v[0] * v[0]) + (v[1] * v[1]) + (v[2] * v[2])); }
/* angle between two vectors */
float mvVecAngleBetween2(const float* a, const float* b)
{
return (float)acos( ((a[0] * b[0]) + (a[1] * b[1])) / (sqrt((a[0] * a[0]) + (a[1] * a[1])) * sqrt((b[0] * b[0]) + (b[1] * b[1]))));
}
float mvVecAngleBetween3(const float* a, const float* b)
{
return (float)acos( ((a[0] * b[0]) + (a[1] * b[1]) + (a[2] * b[2])) / (sqrt((a[0] * a[0]) + (a[1] * a[1]) + (a[2] * a[2])) * sqrt((b[0] * b[0]) + (b[1] * b[1]) + (b[2] * b[2]))));
}
/* normalize vector*/
void mvVecNormalize2(float* v)
{
float length = (float)sqrt((v[0] * v[0]) + (v[1] * v[1]));
v[0] /= length;
v[1] /= length;
}
void mvVecNormalize3(float* v)
{
float length = (float)sqrt((v[0] * v[0]) + (v[1] * v[1]) + (v[2] * v[2]));
v[0] /= length;
v[1] /= length;
v[2] /= length;
}
void mvVecNormalize4(float* v)
{
float length = (float)sqrt((v[0] * v[0]) + (v[1] * v[1]) + (v[2] * v[2]) + (v[3] * v[3]));
v[0] /= length;
v[1] /= length;
v[2] /= length;
v[3] /= length;
}
/* distance between vectors */
float mvVecDistanceBetween2(const float* a, const float* b)
{
float tmp1 = a[0] - b[0];
float tmp2 = a[1] - b[1];
return (float)sqrt((tmp1 * tmp1) + (tmp2 * tmp2));
}
float mvVecDistanceBetween3(const float* a, const float* b)
{
float tmp1 = a[0] - b[0];
float tmp2 = a[1] - b[1];
float tmp3 = a[2] - b[2];
return (float)sqrt((tmp1 * tmp1) + (tmp2 * tmp2) + (tmp3 * tmp3));
}
/* get unit normal vector of a plane from 3 points that lie on the plane */
void mvVecUnitNormalFromPlane(void* r, const float* a, const float* b, const float* c)
{
MVvec3 ab, ac;
mvVecSub3(ab, b, a);
mvVecSub3(ac, c, a);
mvVecCrossProduct(r, ab, ac);
mvVecNormalize3(r);
}
/* ------------------------------------------------------------------- */
/* ---------------------- Matrix Operations -------------------------- */
/* ------------------------------------------------------------------- */
/* copy matrix */
void mvMatCopy2(void* dst, const void* src) { memcpy(dst, src, sizeof(MVmat2)); }
void mvMatCopy3(void* dst, const void* src) { memcpy(dst, src, sizeof(MVmat3)); }
void mvMatCopy4(void* dst, const void* src) { memcpy(dst, src, sizeof(MVmat4)); }
/* load m with identity matrix */
void mvMatLoadIdentity2(MVmat2 m)
{
MVmat2 tmp = {1.0f, 0.0f,
0.0f, 1.0f};
memcpy(m, tmp, sizeof(MVmat2));
}
void mvMatLoadIdentity3(MVmat3 m)
{
MVmat3 tmp = {1.0f, 0.0f, 0.0f,
0.0f, 1.0f, 0.0f,
0.0f, 0.0f, 1.0f};
memcpy(m, tmp, sizeof(MVmat3));
}
void mvMatLoadIdentity4(MVmat4 m)
{
MVmat4 tmp = {1.0f, 0.0f, 0.0f, 0.0f,
0.0f, 1.0f, 0.0f, 0.0f,
0.0f, 0.0f, 1.0f, 0.0f,
0.0f, 0.0f, 0.0f, 1.0f};
memcpy(m, tmp, sizeof(MVmat4));
}
/* set a column of the matrix from vector src */
void mvMatSetCol2(MVmat2 m, const float* src, int col) { memcpy(m + (2*col), src, sizeof(MVvec2)); }
void mvMatSetCol3(MVmat3 m, const float* src, int col) { memcpy(m + (3*col), src, sizeof(MVvec3)); }
void mvMatSetCol4(MVmat4 m, const float* src, int col) { memcpy(m + (4*col), src, sizeof(MVvec4)); }
/* get column from matrix into vector */
void mvMatGetCol2(float* v, const float* src, int col) { memcpy(v, src + (2*col), sizeof(MVvec2)); }
void mvMatGetCol3(float* v, const float* src, int col) { memcpy(v, src + (3*col), sizeof(MVvec3)); }
void mvMatGetCol4(float* v, const float* src, int col) { memcpy(v, src + (4*col), sizeof(MVvec4)); }
/* get rotation matrix from 4x4 matrix */
void mvMatGetRotation(MVmat3 dst, const MVmat4 src)
{
memcpy(dst, src, sizeof(float) * 3); /* X axis */
memcpy(dst + 3, src + 4, sizeof(float) * 3); /* Y */
memcpy(dst + 6, src + 8, sizeof(float) * 3); /* Z */
}
/* set rotation submatrix in a 4x4 matrix */
void mvMatSetRotation(MVmat4 dst, const MVmat3 src)
{
memcpy(dst, src, sizeof(float) * 3); /* X axis */
memcpy(dst + 4, src + 3, sizeof(float) * 3); /* Y */
memcpy(dst + 8, src + 6, sizeof(float) * 3); /* Z */
}
/* Get translation vector from 4x4 matrix */
void mvMatGetTrans3(float* dst, const MVmat4 src) { memcpy(dst, src + 12, sizeof(MVvec3)); }
void mvMatGetTrans4(float* dst, const MVmat4 src) { memcpy(dst, src + 12, sizeof(MVvec4)); }
/* Set translation vector in 4x4 matrix */
void mvMatSetTrans3(MVmat4 dst, const float* src) { memcpy(dst + 12, src, sizeof(MVvec3)); }
void mvMatSetTrans4(MVmat4 dst, const float* src) { memcpy(dst + 12, src, sizeof(MVvec4)); }
/* Matrix multiplication */
void mvMatMultiply2(float* r, const float* a, const float* b)
{
MVmat2 tmp;
tmp[0] = a[0]*b[0] + a[2]*b[1];
tmp[1] = a[1]*b[0] + a[3]*b[1];
tmp[2] = a[0]*b[2] + a[2]*b[3];
tmp[3] = a[1]*b[2] + a[3]*b[3];
memcpy(r, tmp, sizeof(MVmat2));
}
void mvMatMultiply3(float* r, const float* a, const float* b)
{
MVmat3 tmp;
int i, j;
for(i = 0; i < 3; i++)
for(j = 0; j < 3; j++)
tmp[(j*3)+i] = (a[0+i] * b[(j*3)]) + (a[3+i] * b[(j*3)+1]) + (a[6+i] * b[(j*3)+2]);
memcpy(r, tmp, sizeof(MVmat3));
}
void mvMatMultiply4(float* r, const float* a, const float* b)
{
MVmat4 tmp;
int i, j;
for(i = 0; i < 4; i++)
for(j = 0; j < 4; j++)
tmp[(j*4)+i] = (a[0+i] * b[(j*4)]) + (a[4+i] * b[(j*4)+1]) + (a[8+i] * b[(j*4)+2]) + (a[12+i] * b[(j*4)+3]);
memcpy(r, tmp, sizeof(MVmat4));
}
/* scale matrix */
void mvMatScale2(float* r, float factor)
{
int i;
for(i = 0; i < 4; i++)
r[i] *= factor;
}
void mvMatScale3(float* r, float factor)
{
int i;
for(i = 0; i < 9; i++)
r[i] *= factor;
}
void mvMatScale4(float* r, float factor)
{
int i;
for(i = 0; i < 16; i++)
r[i] *= factor;
}
/* Create scaling matrix */
void mvMatCreateScale3(MVmat3 m, float x, float y, float z)
{
MVmat3 tmp = {0.0f};
tmp[0] = x;
tmp[4] = y;
tmp[8] = z;
memcpy(m, tmp, sizeof(MVmat3));
}
void mvMatCreateScale4(MVmat4 m, float x, float y, float z)
{
MVmat4 tmp = {0.0f};
tmp[0] = x;
tmp[5] = y;
tmp[10] = z;
tmp[15] = 1.0f;
memcpy(m, tmp, sizeof(MVmat4));
}
/* Create rotation matrix */
void mvMatCreateRotation3(MVmat3 m, float angle, float xAxis, float yAxis, float zAxis)
{
float x, y, z;
float c = (float)cos(angle);
float s = (float)sin(angle);
float t = 1.0f - (float)cos(angle);
/* Get normalized axis */
MVvec3 axis;
axis[0] = xAxis; axis[1] = yAxis; axis[2] = zAxis;
mvVecNormalize3(axis);
x = axis[0]; y = axis[1]; z = axis[2];
m[0] = (x*x*t)+c; m[3] = (t*x*y)-(s*z); m[6] = (t*x*z)+(s*y);
m[1] = (t*x*y)+(s*z); m[4] = (t*y*y)+c; m[7] = (t*y*z)-(s*x);
m[2] = (t*x*z)-(s*y); m[5] = (t*y*z)+(s*x); m[8] = (t*z*z)+c;
}
void mvMatCreateRotation4(MVmat4 m, float angle, float xAxis, float yAxis, float zAxis)
{
float x, y, z;
float c = (float)cos(angle);
float s = (float)sin(angle);
float t = 1.0f - (float)cos(angle);
/* Get normalized axis */
MVvec3 axis;
axis[0] = xAxis; axis[1] = yAxis; axis[2] = zAxis;
mvVecNormalize3(axis);
x = axis[0]; y = axis[1]; z = axis[2];
m[0] = (x*x*t)+c; m[4] = (t*x*y)-(s*z); m[8] = (t*x*z)+(s*y); m[12] = 0.0f;
m[1] = (t*x*y)+(s*z); m[5] = (t*y*y)+c; m[9] = (t*y*z)-(s*x); m[13] = 0.0f;
m[2] = (t*x*z)-(s*y); m[6] = (t*y*z)+(s*x); m[10] = (t*z*z)+c; m[14] = 0.0f;
m[3] = 0.0f; m[7] = 0.0f; m[11] = 0.0f; m[15] = 1.0f;
}
/* rotate matrix */
void mvRotate(MVmat4 m, float angle, float x, float y, float z)
{
MVmat3 rot, tmp;
mvMatGetRotation(tmp, m);
mvMatCreateRotation3(rot, angle, x, y, z);
mvMatMultiply3(tmp, tmp, rot);
mvMatSetRotation(m, tmp);
}
/* translate matrix */
void mvTranslate(MVmat4 m, float x, float y, float z) { m[12] += x; m[13] += y; m[14] += z; }
/* scale matrix */
void mvScale(MVmat4 m, float x, float y, float z)
{
MVmat4 tmp;
mvMatCreateScale4(tmp, x, y, z);
mvMatMultiply4(tmp, m, tmp);
memcpy(m, tmp, sizeof(MVmat4));
}
/* multiply vector by matrix */
void mvMatVecMultiply2(float* r, const float* m, const float* v)
{
MVvec2 tmp;
memcpy(tmp, v, sizeof(MVvec2));
tmp[0] = m[0]*v[0] + m[2]*v[1];
tmp[1] = m[1]*v[0] + m[3]*v[1];
memcpy(r, tmp, sizeof(MVvec2));
}
void mvMatVecMultiply3(float* r, const float* m, const float* v)
{
MVvec3 tmp;
memcpy(tmp, v, sizeof(MVvec3));
tmp[0] = m[0]*v[0] + m[3]*v[1] + m[6]*v[2];
tmp[1] = m[1]*v[0] + m[4]*v[1] + m[7]*v[2];
tmp[2] = m[2]*v[0] + m[5]*v[1] + m[8]*v[2];
memcpy(r, tmp, sizeof(MVvec3));
}
void mvMatVecMultiply4(float* r, const float* m, const float* v)
{
MVvec4 tmp;
memcpy(tmp, v, sizeof(MVvec4));
tmp[0] = m[0]*v[0] + m[4]*v[1] + m[8]*v[2] + m[12]*v[3];
tmp[1] = m[1]*v[0] + m[5]*v[1] + m[9]*v[2] + m[13]*v[3];
tmp[2] = m[2]*v[0] + m[6]*v[1] + m[10]*v[2] + m[14]*v[3];
tmp[3] = m[3]*v[0] + m[7]*v[1] + m[11]*v[2] + m[15]*v[3];
memcpy(r, tmp, sizeof(MVvec4));
}
/* Generate orthographic projection matrix */
void mvMatCreateOrthographic(MVmat4 m, float left, float right, float bottom, float top, float zNear, float zFar)
{
MVmat4 tmp = {0.0f};
tmp[0] = 2.0f/(right-left);
tmp[5] = 2.0f/(top-bottom);
tmp[10] = -2.0f/(zFar-zNear);
tmp[12] = -(right+left)/(right-left);
tmp[13] = -(top+bottom)/(top-bottom);
tmp[14] = -(zFar+zNear)/(zFar-zNear);
tmp[15] = 1.0f;
memcpy(m, tmp, sizeof(MVmat4));
}
/* Multiply specified matrix with an orthographic projection matrix */
void mvOrtho(MVmat4 m, float left, float right, float bottom, float top, float zNear, float zFar)
{
MVmat4 tmp;
mvMatCreateOrthographic(tmp, left, right, bottom, top, zNear, zFar);
mvMatMultiply4(tmp, m, tmp);
memcpy(m, tmp, sizeof(MVmat4));
}
/* create perspective projection matrix */
void mvMatCreatePerspective(MVmat4 m, float left, float right, float bottom, float top, float zNear, float zFar)
{
MVmat4 tmp = {0.0f};
tmp[0] = (2.0f*zNear)/(right-left);
tmp[5] = (2.0f*zNear)/(top-bottom);
tmp[8] = (right+left)/(right-left);
tmp[9] = (top+bottom)/(top-bottom);
tmp[10] = -(zFar+zNear)/(zFar-zNear);
tmp[11] = -1.0f;
tmp[14] = -(2.0f*zFar*zNear)/(zFar-zNear);
memcpy(m, tmp, sizeof(MVmat4));
}
/* multiply current matrix by perspective projection matrix */
void mvFrustum(MVmat4 m, float left, float right, float bottom, float top, float zNear, float zFar)
{
MVmat4 tmp;
mvMatCreatePerspective(tmp, left, right, bottom, top, zNear, zFar);
mvMatMultiply4(tmp, m, tmp);
memcpy(m, tmp, sizeof(MVmat4));
}
/* multiply current matrix by perspective projection matrix - angle in radians */
void mvPerspective(MVmat4 m, float fovyRadians, float aspect, float zNear, float zFar)
{
float y, x;
y = zNear * (float)tan(fovyRadians / 2.0f);
x = y * aspect;
mvFrustum(m, -x, x, -y, y, zNear, zFar);
}
/* ------------------------------------------------------------------- */
/* ---------------------- Stack Operations --------------------------- */
/* ------------------------------------------------------------------- */
#define MV_STACK_SIZE 32
typedef struct _MVstack
{
MVmat4 matrix[MV_STACK_SIZE];
int top;
} MVstack;
void mvPushMatrix(MVstack* s, const MVmat4 m)
{
s->top++;
memcpy(&(s->matrix[MV_STACK_SIZE - s->top]), m, sizeof(MVmat4));
}
void mvPopMatrix(MVstack* s, MVmat4 m)
{
memcpy(m, &(s->matrix[MV_STACK_SIZE - s->top]), sizeof(MVmat4));
s->top--;
}
void mvPeekMatrix(MVstack* s, MVmat4 m)
{
memcpy(m, &(s->matrix[MV_STACK_SIZE - s->top]), sizeof(MVmat4));
}
int mvGetCurrentStackDepth(MVstack* s)
{
return s->top;
}
/* ------------------------------------------------------------------- */
/* ---------------------- Console Output ----------------------------- */
/* ------------------------------------------------------------------- */
/* print an n dimension vector */
void mvVecPrint(const float* v, int dim)
{
int i;
if(dim < 1 || dim > 4)
{
puts("mvVecPrint() : invalid dimension; must be 2, 3, or 4.");
return;
}
printf("<");
for(i = 0; i < dim; i++)
{
printf(" %.2f ", v[i]);
}
puts(">");
}
/* print an nxn matrix */
void mvMatPrint(const float* m, int dim)
{
int i, j;
if(dim < 2 || dim > 4)
{
puts("mvVecPrint() : invalid dimension; must be 3 or 4");
return;
}
puts("--------------------------------");
for(i = 0; i < dim; i++)
{
for(j = 0; j < dim; j++)
{
printf(" %.2f\t", m[(j*dim)+i]);
}
putchar('\n');
}
puts("--------------------------------");
}
#ifdef __cplusplus
}
#endif
#endif
|
Jchuk99/PyLidar
|
app/pylidar/PyLidar.h
|
#pragma once
#include <stdio.h>
#include <stdlib.h>
#include <signal.h>
#include <string.h>
#include <rplidar.h>
#ifndef _countof
#define _countof(_Array) (int)(sizeof(_Array) / sizeof(_Array[0]))
#endif
typedef struct LidarScan
{
double** data;
int size;
}LidarScan;
using namespace sl;
class PyLidar
{
protected:
// For setting scanmodes
std::vector<LidarScanMode> myscanModes;
sl_lidar_response_device_info_t devinfo;
LidarScanMode myScanMode;
ILidarDriver* _drv = NULL;
IChannel* _channel = NULL;
// some parameters to be set
const char* _port;
float frequency = 0.0;
bool connectSuccess = false;
// create a buffer to hold the scanned data
rplidar_response_measurement_node_hq_t nodes[8192];
bool checkRPLIDARHealth(ILidarDriver* drv)
{
u_result op_result;
rplidar_response_device_health_t healthinfo;
op_result = drv->getHealth(healthinfo);
if (SL_IS_OK(op_result)) {
printf("%d\n", healthinfo.status);
if (healthinfo.status == RPLIDAR_STATUS_ERROR) {
//printf("Error1\n");
// enable the following code if you want rplidar to be reboot by software
// drv->reset();
return false;
}
else {
return true;
}
}
else {
//fprintf(stderr, "Error, cannot retrieve the lidar health code: %x\n", op_result);
//printf("Error2\n");
return false;
}
}
public:
int _baud_rate;
// Create the constructor: Here the driver will be created.
PyLidar(const char* my_port = "/dev/ttyUSB0", int baud_rate = 115200);
~PyLidar();
// Setup connection to the rplidar.
// Connect Lidar
void connectlidar(void);
void disconnectlidar(void);
// destroy driver
void destroydriver(void);
bool isConnected(void);
// rest lidar, return true if succeed
bool reset(unsigned int timeout);
// A wrapper code for the checkhealth status
bool checkhealth(void);
float getFrequency(void);
sl_lidar_response_device_info_t getDeviceInfo(void);
// stopping the motor
void stopmotor(void);
// starts the motor
void startmotor(int my_scanmode = 2);
/*
* This function will be used in fetching the scan data
* The output is a vector of vectors.
* */
std::vector<std::vector<double>> get_scan_as_vectors(bool filter_quality = false);
double ** get_scan_as_pointers(bool filter_quality = false);
/*
* This function will be used in fetching the scan data
* The output is a vector of vectors.
* */
std::vector<std::vector<double>> get_scan_as_xy(bool filter_quality = false);
double** get_scan_as_xy_pointers(bool filter_quality = false);
};
|
ddiakopoulos/sculpting-and-simulations-sample
|
code/deformation.h
|
<gh_stars>1-10
// Copyright(c) Facebook, Inc. and its affiliates.
// All rights reserved.
//
// This source code is licensed under the BSD - style license found in the
// LICENSE file in the root directory of this source tree.
#pragma once
#ifdef __cplusplus
#pragma once
#define INLINE inline
INLINE float min(float a, float b) { return a < b ? a : b; };
INLINE float max(float a, float b) { return a > b ? a : b; };
INLINE int min(int a, int b) { return a < b ? a : b; };
INLINE int max(int a, int b) { return a > b ? a : b; };
#include "glslmathforcpp.h"
#else
// otherwise this assumes GLSL, which defines min()/max()
#define INLINE
struct quat { float r, i, j, k; };
#endif
struct Pose
{
vec3 position;
quat orientation;
float scale;
float time;
};
struct Motion
{
vec3 origin;
vec3 linearVelocity;
vec3 angularVelocity;
float scaleFactor;
float time;
float dt;
};
struct Deformation
{
vec3 origin;
vec3 linearVelocity;
mat3x3 rotationTensor;
mat3x3 strainTensor;
mat3x3 displacementGradientTensor;
float time;
float dt;
};
struct Kelvinlet
{
vec3 origin;
vec3 linearVelocity;
vec3 forceVector;
mat3x3 twistForceMatrix;
mat3x3 scaleForceMatrix;
float time;
float dt;
float radius;
float stiffness;
float compressibility;
};
#include "kelvinlets.h"
#include "nonelastic.h"
// The code below is meant to be run on the CPU
// It does not need to be computed per-vertex
#ifdef __cplusplus
INLINE Motion buildMotion(Pose start, Pose end);
INLINE Deformation buildDeformation(Motion motion);
INLINE Kelvinlet buildKelvinlet(Deformation deformation, float stiffness, float compressibilty, float radius);
INLINE mat3x3 skewSymmetric(vec3 a)
{
// This assumes mat3x3's constructor takes three column vectors
// e.g. the zeroth column is (0, a.z, -a.y). When reading this,
// you should transpose the vec3's and see them as columns.
return mat3x3
{
vec3( 0, a.z, -a.y),
vec3(-a.z, 0, a.x),
vec3( a.y, -a.x, 0)
};
}
INLINE mat3x3 identityMat3x3()
{
return mat3x3
{
vec3(1, 0, 0),
vec3(0, 1, 0),
vec3(0, 0, 1)
};
}
INLINE Motion buildMotion(Pose start, Pose end)
{
Motion motion;
quat rotation = end.orientation * inverse(start.orientation);
vec3 axis;
float angle;
rotation.toAxisAngle(axis, angle);
if (angle == 0.0f)
{
axis = vec3(1, 0, 0);
angle = 0.0f;
}
vec3 t = end.position - start.position;
vec3 r = axis * angle;
float s = end.scale / start.scale;
float dt = end.time - start.time;
motion.origin = start.position;
motion.linearVelocity = t / dt;
motion.angularVelocity = r / dt;
motion.scaleFactor = s;
motion.time = start.time;
motion.dt = dt;
return motion;
}
INLINE Deformation buildDeformation(Motion motion)
{
Deformation deformation;
deformation.origin = motion.origin;
deformation.linearVelocity = motion.linearVelocity;
deformation.rotationTensor = skewSymmetric(motion.angularVelocity);
deformation.strainTensor = identityMat3x3() * log(pow(motion.scaleFactor, 1/motion.dt));
deformation.displacementGradientTensor = deformation.rotationTensor + deformation.strainTensor;
deformation.time = motion.time;
deformation.dt = motion.dt;
return deformation;
}
INLINE Kelvinlet buildKelvinlet(Deformation deformation, float stiffness, float compressibility, float radius)
{
Kelvinlet kelvinlet;
// Compressibility of 0.5 causes divide by 0 in Kelvinlets equation for scale,
// so use 0.0 (also done in KEvaluate() function)
float scaleCompressibility = 0.0f;
kelvinlet.origin = deformation.origin;
kelvinlet.linearVelocity = deformation.linearVelocity;
kelvinlet.forceVector = deformation.linearVelocity * KTranslationCalibrationFactor(radius, compressibility);
kelvinlet.twistForceMatrix = deformation.rotationTensor * KTwistCalibrationFactor(radius, compressibility);
kelvinlet.scaleForceMatrix = deformation.strainTensor * KScaleCalibrationFactor(radius, scaleCompressibility);
kelvinlet.time = deformation.time;
kelvinlet.dt = deformation.dt;
kelvinlet.radius = radius;
kelvinlet.stiffness = stiffness;
kelvinlet.compressibility = compressibility;
return kelvinlet;
}
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/usbd_composite .c
|
#include <string.h>
#include "usb_common.h"
#include "usbd.h"
#include "usbd_cdc.h"
#include "usbd_hid.h"
#include "usbd_msc.h"
#include "usbd_composite.h"
static struct usbd_t *handle = NULL;
static uint32_t composite_standard_request_to_intf_handler(struct usbd_t *h)
{
switch(handle->setup.index)
{
case USBD_MSC_IF_IDX:
msc_standard_request_to_intf_handler(h);
break;
case USBD_CDC_CIF_IDX:
cdc_standard_request_to_intf_handler(h);
break;
case USBD_HID0_IF_IDX:
case USBD_HID1_IF_IDX:
case USBD_HID2_IF_IDX:
hid_standard_request_to_intf_handler(h);
break;
}
return CH_OK;
}
static uint32_t composite_class_request_handler(struct usbd_t *h)
{
switch(handle->setup.index)
{
case USBD_MSC_IF_IDX:
msc_class_request_handler(h);
break;
case USBD_CDC_CIF_IDX:
cdc_class_request_handler(h);
break;
case USBD_HID0_IF_IDX:
case USBD_HID1_IF_IDX:
case USBD_HID2_IF_IDX:
hid_class_request_handler(h);
break;
}
return CH_OK;
}
static uint32_t composite_data_ep_handler(uint8_t ep, uint8_t dir)
{
hid_data_ep_handler(ep, dir);
cdc_data_ep_handler(ep, dir);
msc_data_ep_handler(ep, dir);
return CH_OK;
}
uint32_t composite_setup_out_data_received_handler(uint8_t *buf, uint32_t len)
{
switch(handle->setup.index)
{
case USBD_CDC_CIF_IDX:
case USBD_CDC_DIF_IDX:
cdc_setup_out_data_received(buf, len);
break;
}
return CH_OK;
}
void usbd_composite_init(struct usbd_t *h, uint32_t option)
{
handle = h;
uint8_t *p;
struct uconfig_descriptor *uconfiguration_descriptor;
desc_t d;
get_descriptor_data("configuration_descriptor", &d);
uconfiguration_descriptor = (struct uconfig_descriptor *)d.buf;
uconfiguration_descriptor->bLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->type = USB_DESC_TYPE_CONFIGURATION;
uconfiguration_descriptor->wTotalLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->bNumInterfaces = 0;
uconfiguration_descriptor->bConfigurationValue = 1;
uconfiguration_descriptor->iConfiguration = 0;
uconfiguration_descriptor->bmAttributes = 0x80;
uconfiguration_descriptor->MaxPower = 0x32;
/* add configuation data */
p = uconfiguration_descriptor->data;
if(option & USBD_USE_MSC)
{
uconfiguration_descriptor->bNumInterfaces++;
get_descriptor_data("msc_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
}
if(option & USBD_USE_CDC)
{
uconfiguration_descriptor->bNumInterfaces += 2;
get_descriptor_data("cdc_acm_iad_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
get_descriptor_data("cdc_acm_if0", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
get_descriptor_data("cdc_acm_if1", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
}
if(option & USBD_USE_HID0)
{
uconfiguration_descriptor->bNumInterfaces++;
get_descriptor_data("hid0_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
}
if(option & USBD_USE_HID1)
{
uconfiguration_descriptor->bNumInterfaces++;
get_descriptor_data("hid1_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
}
if(option & USBD_USE_HID2)
{
uconfiguration_descriptor->bNumInterfaces++;
get_descriptor_data("hid2_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
}
/* install descriptor */
get_descriptor_data("device_descriptor", &d);
struct udevice_descriptor* device_desc = (struct udevice_descriptor*)d.buf;
device_desc->bDeviceClass = USB_CLASS_MISC;
device_desc->bDeviceSubClass = 0x02;
device_desc->bDeviceProtocol = 0x01;
/* install class callback */
handle->class_request_handler = composite_class_request_handler;
handle->standard_request_to_intf_handler = composite_standard_request_to_intf_handler;
handle->setup_out_data_received_handler = composite_setup_out_data_received_handler;
handle->data_ep_handler = composite_data_ep_handler;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/test/usbd_cdc_test.c
|
#include "usbd_cdc.h"
/* host need device's line_coding config */
uint32_t get_line_coding(struct ucdc_line_coding *line_coding)
{
line_coding->dwDTERate = 115200;
line_coding->bCharFormat = 2;
USBD_TRACE("get_line_coding, baud:%d\r\n", line_coding->dwDTERate);
return CH_OK;
}
/* device need to implment host's config */
uint32_t set_line_coding(struct ucdc_line_coding *line_coding)
{
USBD_TRACE("set line coding:%d\r\n", line_coding->dwDTERate);
return CH_OK;
}
uint32_t cdc_data_received(uint8_t *buf, uint32_t len)
{
printf("cdc_data_received %d\r\n", len);
return CH_OK;
}
struct usbd_cdc_callback_t cdc_cb =
{
get_line_coding,
set_line_coding,
cdc_data_received,
};
void usbd_cdc_test(struct usbd_t *h)
{
usbd_cdc_set_cb(&cdc_cb);
usbd_cdc_init(h);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/ctimer.c
|
<reponame>yandld/lpc_uart_server
/**
******************************************************************************
* @file ctimer.c
* @author YANDLD
* @version V3.0.0
* @date 2016.5.28
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "ctimer.h"
#include "common.h"
static uint32_t fac_us = 0;
CTIMER_Type* const CTIMERBases[] = CTIMER_BASE_PTRS;
static const IRQn_Type CTIMER_IRQTbl[] = CTIMER_IRQS;
static void CTIMER_EnableAllClocks(void)
{
SYSCON->ASYNCAPBCTRL |= SYSCON_ASYNCAPBCTRL_ENABLE_MASK;
SYSCON->AHBCLKCTRL[1] |= SYSCON_AHBCLKCTRL_CTIMER0_MASK | SYSCON_AHBCLKCTRL_CTIMER1_MASK | SYSCON_AHBCLKCTRL_CTIMER2_MASK;
ASYNC_SYSCON->ASYNCAPBCLKCTRL |= ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK | ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK;
}
void CTIMER_PWM_Init(uint32_t instance, uint32_t pwm_chl, uint32_t freq)
{
uint32_t period;
CTIMER_Type *CTIMERx = CTIMERBases[instance];
/* enable clock */
CTIMER_EnableAllClocks();
/* Setup the cimer mode and count select */
CTIMERx->CTCR = CTIMER_CTCR_CTMODE(0);
CTIMERx->PR = 0;
CTIMERx->PWMC |= (1U << pwm_chl);
CTIMERx->MCR = CTIMER_MCR_MR3R_MASK;
LIB_TRACE("PWM input clock after prescaler:%d\r\n", (GetClock(kCoreClock)/(CTIMERx->PR + 1)));
period = ((GetClock(kCoreClock)/(CTIMERx->PR + 1)) / freq) - 1;
CTIMERx->MR[3] = period;
LIB_TRACE("PWM MR[3](perdiod):%d\r\n", CTIMERx->MR[3]);
/* initial duty */
CTIMERx->MR[pwm_chl] = period/2;
/* clear IT flags */
CTIMERx->IR = 0xFF;
CTIMERx->TCR |= CTIMER_TCR_CEN_MASK;
}
void CTIMER_PWM_SetDuty(uint32_t instance, uint32_t pwm_chl, uint32_t duty)
{
CTIMERBases[instance]->MR[pwm_chl] = (CTIMERBases[instance]->MR[3] * (10000 - duty)) / 10000;
}
void CTIMER_TC_Init(uint32_t instance, uint32_t us)
{
CTIMER_Type *CTIMERx = CTIMERBases[instance];
/* enable clock */
CTIMER_EnableAllClocks();
/* Setup the cimer mode and count select */
CTIMERx->CTCR = CTIMER_CTCR_CTMODE(0);
/* clear IT flags */
CTIMERx->IR = 0xFF;
/* reset on match */
CTIMERx->MCR = CTIMER_MCR_MR0R_MASK;
/* prescale value */
CTIMERx->PR = 0;
fac_us = GetClock(kCoreClock) / (CTIMERx->PR + 1);
fac_us /= 1000000;
LIB_TRACE("CTIMER TC fac_us:%d\r\n", fac_us);
/* match value */
CTIMERx->MR[0] = us * fac_us;
CTIMER_Start(instance);
}
void CTIMER_CAP_Init(uint32_t instance, uint32_t chl)
{
CTIMER_Type *CTIMERx = CTIMERBases[instance];
/* enable clock */
CTIMER_EnableAllClocks();
/* Setup the cimer mode and count select */
CTIMERx->CTCR = CTIMER_CTCR_CTMODE(2) | CTIMER_CTCR_CINSEL(chl);
/* clear IT flags */
CTIMERx->IR = 0xFF;
/* prescale value */
CTIMERx->PR = 0;
fac_us = GetClock(kCoreClock) / (CTIMERx->PR + 1);
fac_us /= 1000000;
CTIMERx->PR = 0;
CTIMERx->TC = 0;
CTIMER_Start(instance);
}
void CTIMER_Stop(uint32_t instance)
{
CTIMERBases[instance]->TCR &= ~CTIMER_TCR_CEN_MASK;
}
void CTIMER_Start(uint32_t instance)
{
CTIMERBases[instance]->TCR |= CTIMER_TCR_CEN_MASK;
}
void CTIMER_TC_SetIntMode(uint32_t instance, uint32_t chl, bool val)
{
switch(chl)
{
case HW_CTIMER_CH0:
(val)?(CTIMERBases[instance]->MCR |= CTIMER_MCR_MR0I_MASK):(CTIMERBases[instance]->MCR &= ~CTIMER_MCR_MR0I_MASK);
break;
case HW_CTIMER_CH1:
(val)?(CTIMERBases[instance]->MCR |= CTIMER_MCR_MR1I_MASK):(CTIMERBases[instance]->MCR &= ~CTIMER_MCR_MR1I_MASK);
break;
case HW_CTIMER_CH2:
(val)?(CTIMERBases[instance]->MCR |= CTIMER_MCR_MR2I_MASK):(CTIMERBases[instance]->MCR &= ~CTIMER_MCR_MR2I_MASK);
break;
case HW_CTIMER_CH3:
(val)?(CTIMERBases[instance]->MCR |= CTIMER_MCR_MR3I_MASK):(CTIMERBases[instance]->MCR &= ~CTIMER_MCR_MR3I_MASK);
break;
default:
break;
}
NVIC_EnableIRQ(CTIMER_IRQTbl[instance]);
}
/*
mode: HW_CTIMER_CAP_INT_EVT_RE: generate interrupt: 0->1
mode: HW_CTIMER_CAP_INT_EVT_FE: generate interrupt: 1->0
mode: HW_CTIMER_CAP_INT_EVT_ALL: any edge
*/
void CIMER_CAP_SetITandLoadMode(uint32_t instance, uint32_t chl, uint32_t mode)
{
switch(chl)
{
case HW_CTIMER_CH0:
(HW_CTIMER_CAP_INT_EVT_FE)?(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP0FE_MASK):(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP0RE_MASK);
break;
case HW_CTIMER_CH1:
(HW_CTIMER_CAP_INT_EVT_FE)?(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP1FE_MASK):(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP1RE_MASK);
break;
case HW_CTIMER_CH2:
(HW_CTIMER_CAP_INT_EVT_FE)?(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP2FE_MASK):(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP2RE_MASK);
break;
case HW_CTIMER_CH3:
(HW_CTIMER_CAP_INT_EVT_FE)?(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP3FE_MASK):(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP3RE_MASK);
break;
default:
break;
}
}
void CTIMER_CAP_SetIntMode(uint32_t instance, uint32_t chl, bool val)
{
switch(chl)
{
case HW_CTIMER_CH0:
(val)?(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP0I_MASK):(CTIMERBases[instance]->CCR &= ~CTIMER_CCR_CAP0I_MASK);
break;
case HW_CTIMER_CH1:
(val)?(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP1I_MASK):(CTIMERBases[instance]->CCR &= ~CTIMER_CCR_CAP1I_MASK);
break;
case HW_CTIMER_CH2:
(val)?(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP2I_MASK):(CTIMERBases[instance]->CCR &= ~CTIMER_CCR_CAP2I_MASK);
break;
case HW_CTIMER_CH3:
(val)?(CTIMERBases[instance]->CCR |= CTIMER_CCR_CAP3I_MASK):(CTIMERBases[instance]->CCR &= ~CTIMER_CCR_CAP3I_MASK);
break;
default:
break;
}
NVIC_EnableIRQ(CTIMER_IRQTbl[instance]);
}
void CTIMER_SetCounter(uint32_t instance, uint32_t val)
{
CTIMERBases[instance]->TC = val;
}
uint32_t CTIMER_GetCounter(uint32_t instance)
{
return CTIMERBases[instance]->TC;
}
uint32_t CTIMER_GetCAPCounter(uint32_t instance, uint32_t chl)
{
uint32_t CR;
CR = CTIMERBases[instance]->CR[chl];
return CR;
}
void CTIMER_SetTimerClearEvt(uint32_t instance, uint32_t chl, uint32_t mode, bool val)
{
(val)?(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_ENCC_MASK):(CTIMERBases[instance]->CTCR &= ~CTIMER_CTCR_ENCC_MASK);
CTIMERBases[instance]->CTCR &= ~CTIMER_CTCR_SELCC_MASK;
switch(chl)
{
case HW_CTIMER_CH0:
(HW_CTIMER_CAP_INT_EVT_FE)?(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_SELCC(1)):(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_SELCC(0));
break;
case HW_CTIMER_CH1:
(HW_CTIMER_CAP_INT_EVT_FE)?(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_SELCC(3)):(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_SELCC(2));
break;
case HW_CTIMER_CH2:
(HW_CTIMER_CAP_INT_EVT_FE)?(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_SELCC(5)):(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_SELCC(4));
break;
case HW_CTIMER_CH3:
(HW_CTIMER_CAP_INT_EVT_FE)?(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_SELCC(7)):(CTIMERBases[instance]->CTCR |= CTIMER_CTCR_SELCC(6));
break;
default:
break;
}
}
void CTIMER_IRQHandler(uint32_t instance)
{
CTIMERBases[instance]->IR |= CTIMER_IR_MR0INT_MASK;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/src/system_SKEAZ1284.c
|
<filename>mcu_source/Libraries/startup/src/system_SKEAZ1284.c
/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: MKE06P80M48SF0RM, Rev. 1, Dec 2013
** Version: rev. 1.2, 2014-01-10
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2014 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2013-07-30)
** Initial version.
** - rev. 1.1 (2013-10-29)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 1.2 (2014-01-10)
** CAN module: corrected address of TSIDR1 register.
** CAN module: corrected name of MSCAN_TDLR bit DLC to TDLC.
** FTM0 module: added access macro for EXTTRIG register.
** NVIC module: registers access macros improved.
** SCB module: unused bits removed, mask, shift macros improved.
** Defines of interrupt vectors aligned to RM.
**
** ###################################################################
*/
/*!
* @file SKEAZ1284
* @version 1.2
* @date 2014-01-10
* @brief Device specific configuration file for SKEAZ1284 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "SKEAZ1284.h"
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Internal Clock Source (ICS) in FLL Engaged Internal (FEI) mode
Default part configuration.
Reference clock source for ICS module is the slow internal clock source 32.768kHz
Core clock = 20.97MHz, BusClock = 20.97MHz
1 ... Internal Clock Source (ICS) in FLL Engaged External (FEE) mode
Maximum achievable clock frequency configuration.
Reference clock source for ICS module is an external 8MHz crystal
Core clock = 40MHz, BusClock = 20MHz
2 ... Internal Clock Source (ICS) in Bypassed Low Power Internal (FBILP) mode
Core clock/Bus clock derived directly from an internal clock 32.769kHz with no multiplication
The clock settings is ready for Very Low Power Run mode.
Core clock = 32.769kHz, BusClock = 32.769kHz
3 ... Internal Clock Source (ICS) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from the external 8MHz crystal
The clock settings is ready for Very Low Power Run mode.
Core clock = 8MHz, BusClock = 8MHz
4 ... Internal Clock Source (ICS) in FLL Engaged External (FBE) mode
Maximum achievable clock frequency configuration.
Reference clock source for ICS module is an external 12MHz crystal
Core clock = 12MHz, BusClock = 12MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_CLK_HZ 32768u /* Value of the internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_CLK_HZ 32768u /* Value of the internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 40000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_CLK_HZ 32768u /* Value of the internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_CLK_HZ 32768u /* Value of the internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 4) */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if (DISABLE_WDOG)
/* WDOG->TOVAL: TOVAL=0xE803 */
WDOG->TOVAL = WDOG_TOVAL_TOVAL(0xE803); /* Timeout value */
WDOG->CS2 = WDOG_CS2_CLK(0x01); /* 1-kHz clock source */
/* WDOG->CS1: EN=0,INT=0,UPDATE=1,TST=0,DBG=0,WAIT=1,STOP=1 */
WDOG->CS1 = WDOG_CS1_UPDATE_MASK |
WDOG_CS1_TST(0x00) |
WDOG_CS1_WAIT_MASK |
WDOG_CS1_STOP_MASK;
#endif /* (DISABLE_WDOG) */
#if (CLOCK_SETUP == 0)
/* ICS->C2: BDIV|=1 */
ICS->C2 |= ICS_C2_BDIV(0x01); /* Update system prescalers */
SIM->CLKDIV = SIM_CLKDIV_OUTDIV1(0x00); /* Update system prescalers */
/* Switch to FEI Mode */
/* ICS_C1: CLKS=0,RDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
ICS->C1 = ICS_C1_CLKS(0x00) |
ICS_C1_RDIV(0x00) |
ICS_C1_IREFS_MASK |
ICS_C1_IRCLKEN_MASK;
/* ICS->C2: BDIV=1,LP=0 */
ICS->C2 = (uint8_t)((ICS->C2 & (uint8_t)~(uint8_t)(
ICS_C2_BDIV(0x06) |
ICS_C2_LP_MASK
)) | (uint8_t)(
ICS_C2_BDIV(0x01)
));
OSC->CR = 0x00U;
while((ICS->S & ICS_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((ICS->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 1)
SIM->CLKDIV = SIM_CLKDIV_OUTDIV1(0x00) | SIM_CLKDIV_OUTDIV2(0x01); /* Update system prescalers */
/* Switch to FEE Mode */
/* ICS->C2: BDIV=0,LP=0 */
ICS->C2 &= (uint8_t)~(uint8_t)((ICS_C2_BDIV(0x07) | ICS_C2_LP_MASK));
OSC->CR = (OSC_CR_OSCEN_MASK | OSC_CR_OSCOS_MASK | OSC_CR_RANGE_MASK);
/* ICS->C1: CLKS=0,RDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
ICS->C1 = (ICS_C1_CLKS(0x00) | ICS_C1_RDIV(0x03) | ICS_C1_IRCLKEN_MASK);
while((ICS->S & ICS_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((ICS->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 2)
SIM->CLKDIV = SIM_CLKDIV_OUTDIV1(0x00); /* Update system prescalers */
/* Switch to FBI Mode */
/* ICS->C1: CLKS=1,RDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
ICS->C1 = ICS_C1_CLKS(0x01) |
ICS_C1_RDIV(0x00) |
ICS_C1_IREFS_MASK |
ICS_C1_IRCLKEN_MASK;
/* ICS->C2: BDIV=0,LP=0 */
ICS->C2 &= (uint8_t)~(uint8_t)((ICS_C2_BDIV(0x07) | ICS_C2_LP_MASK));
OSC->CR = 0x00U;
while((ICS->S & ICS_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((ICS->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as ICS output */
}
/* Switch to BLPI Mode */
/* ICS->C2: BDIV=0,LP=1 */
ICS->C2 = (uint8_t)((ICS->C2 & (uint8_t)~(uint8_t)(
ICS_C2_BDIV(0x07)
)) | (uint8_t)(
ICS_C2_LP_MASK
));
while((ICS->S & ICS_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
#elif (CLOCK_SETUP == 3)
SIM->CLKDIV = SIM_CLKDIV_OUTDIV1(0x00); /* Update system prescalers */
/* Switch to FBE Mode */
/* ICS->C2: BDIV=0,LP=0 */
ICS->C2 &= (uint8_t)~(uint8_t)((ICS_C2_BDIV(0x07) | ICS_C2_LP_MASK));
OSC->CR = (OSC_CR_OSCEN_MASK | OSC_CR_OSCOS_MASK | OSC_CR_RANGE_MASK);
/* ICS->C1: CLKS=2,RDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
ICS->C1 = (ICS_C1_CLKS(0x02) | ICS_C1_RDIV(0x03) | ICS_C1_IRCLKEN_MASK);
while((ICS->S & ICS_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((ICS->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as ICS output */
}
/* Switch to BLPE Mode */
/* ICS->C2: BDIV=0,LP=1 */
ICS->C2 = (uint8_t)((ICS->C2 & (uint8_t)~(uint8_t)(
ICS_C2_BDIV(0x07)
)) | (uint8_t)(
ICS_C2_LP_MASK
));
while((ICS->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as ICS output */
}
#endif
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t ICSOUTClock; /* Variable to store output clock frequency of the ICS module */
uint8_t Divider;
if ((ICS->C1 & ICS_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL is selected */
if ((ICS->C1 & ICS_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
ICSOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives ICS clock */
Divider = (uint8_t)(1u << ((ICS->C1 & ICS_C1_RDIV_MASK) >> ICS_C1_RDIV_SHIFT));
ICSOUTClock = (ICSOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((OSC->CR & OSC_CR_RANGE_MASK) != 0x0u) {
ICSOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
}
} else {
ICSOUTClock = CPU_INT_CLK_HZ; /* The internal reference clock is selected */
}
ICSOUTClock *= 1280u; /* Apply 1280 FLL multiplier */
} else if ((ICS->C1 & ICS_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
ICSOUTClock = CPU_INT_CLK_HZ;
} else if ((ICS->C1 & ICS_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
ICSOUTClock = CPU_XTAL_CLK_HZ;
} else {
/* Reserved value */
return;
}
ICSOUTClock = ICSOUTClock >> ((ICS->C2 & ICS_C2_BDIV_MASK) >> ICS_C2_BDIV_SHIFT);
SystemCoreClock = (ICSOUTClock / (1u + ((SIM->CLKDIV & SIM_CLKDIV_OUTDIV1_MASK) >> SIM_CLKDIV_OUTDIV1_SHIFT)));
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/bsp/lpc546xx/drv_pin.c
|
<filename>mcu_source/Libraries/utilities/rtthread/bsp/lpc546xx/drv_pin.c<gh_stars>1-10
#include <rthw.h>
#include <rtthread.h>
#include "common.h"
#include "gpio.h"
#include <rtdevice.h>
#include <drivers/pin.h>
static void _pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
{
uint32_t instance;
instance = (pin & 0xFF00) >> 8;
switch(mode)
{
case PIN_MODE_OUTPUT:
GPIO_Init(instance, pin & 0xFF, kGPIO_OPPH);
break;
case PIN_MODE_INPUT:
GPIO_Init(instance, pin & 0xFF, kGPIO_IFT);
GPIO_AddIntToSocket(instance, pin & 0xFF, 0);
GPIO_SetIntMode(0, kGPIO_Int_FE, true);
break;
case PIN_MODE_INPUT_PULLUP:
GPIO_Init(instance, pin & 0xFF, kGPIO_IPU);
GPIO_AddIntToSocket(instance, pin & 0xFF, 0);
GPIO_SetIntMode(0, kGPIO_Int_FE, true);
break;
}
}
static void _pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
{
uint32_t instance;
instance = (pin & 0xFF00) >> 8;
GPIO_PinWrite(instance, pin & 0xFF, value);
}
static int _pin_read(struct rt_device *device, rt_base_t pin)
{
uint32_t instance;
instance = (pin & 0xFF00) >> 8;
return GPIO_PinRead(instance, pin & 0xFF);
}
static const struct rt_pin_ops _ops =
{
_pin_mode,
_pin_write,
_pin_read,
};
int rt_hw_pin_init(const char *name)
{
return rt_device_pin_register(name, &_ops, RT_NULL);
}
void PIN_INT0_IRQHandler(void)
{
volatile uint32_t IST = PINT->IST;
PINT->IST = IST;
rt_device_t dev;
dev = rt_device_find("gpio");
if(dev && dev->rx_indicate)
{
dev->rx_indicate(dev, IST);
}
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/bsp/lpc546xx/drv_uart.c
|
/*
* File : serial.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2006-03-13 bernard first version
* 2012-05-15 lgnq modified according bernard's implementation.
* 2012-05-28 bernard code cleanup
* 2012-11-23 bernard fix compiler warning.
* 2013-02-20 bernard use RT_SERIAL_RB_BUFSZ to define
* the size of ring buffer.
*/
#include <rtthread.h>
#include <string.h>
#include "common.h"
#include "uart.h"
#include "dma.h"
#include <rtdevice.h>
#define HW_LPC546XX_UART_CNT (10)
/* LP546xx uart driver */
struct lpc546xx_uart
{
uint8_t instance;
USART_Type *USARTx;
DMA_ChlSetup_t tx_setup;
};
struct lpc546xx_uart uart[HW_LPC546XX_UART_CNT];
struct rt_serial_device serial[HW_LPC546XX_UART_CNT];
static rt_err_t lpc546xx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct lpc546xx_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct lpc546xx_uart *)serial->parent.user_data;
switch (cfg->data_bits)
{
case DATA_BITS_8:
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_1:
break;
}
switch (cfg->parity)
{
case PARITY_NONE:
break;
}
UART_Init(uart->instance, cfg->baud_rate);
if(serial->parent.flag & RT_DEVICE_FLAG_DMA_TX)
{
uart->tx_setup.isPeriph = true;
uart->tx_setup.dataWidth = 1;
uart->tx_setup.sAddrInc = 1;
uart->tx_setup.dAddrInc = 0;
switch(uart->instance)
{
case 4:
uart->tx_setup.chl = DMAREQ_FLEXCOMM4_TX;
uart->tx_setup.dAddr = (uint32_t)(&(USART4->FIFOWR));
break;
case 0:
uart->tx_setup.chl = DMAREQ_FLEXCOMM0_TX;
uart->tx_setup.dAddr = (uint32_t)(&(USART0->FIFOWR));
break;
default:
printf("lpc546xx_configure error instance%d\r\n", uart->instance);
break;
}
DMA_SetupChl(&uart->tx_setup);
DMA_SetChlIntMode(uart->tx_setup.chl, true);
UART_SetDMAMode(uart->instance, kUART_DMATx, true);
}
return RT_EOK;
}
static rt_err_t lpc546xx_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct lpc546xx_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct lpc546xx_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
UART_SetIntMode(uart->instance, kUART_IntRx, false);
break;
case RT_DEVICE_CTRL_SET_INT:;
UART_SetIntMode(uart->instance, kUART_IntRx, true);
break;
}
return RT_EOK;
}
static int lpc546xx_putc(struct rt_serial_device *serial, char c)
{
struct lpc546xx_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct lpc546xx_uart *)serial->parent.user_data;
UART_PutChar(uart->instance, c);
return 1;
}
static int lpc546xx_getc(struct rt_serial_device *serial)
{
uint8_t ch;
struct lpc546xx_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct lpc546xx_uart *)serial->parent.user_data;
if(UART_GetChar(uart->instance, &ch) == RT_EOK)
{
return ch;
}
return -1;
}
static rt_size_t lpc546xx_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
struct lpc546xx_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct lpc546xx_uart *)serial->parent.user_data;
if(direction == RT_SERIAL_DMA_TX)
{
uart->tx_setup.transferCnt = size;
uart->tx_setup.sAddr = (uint32_t)buf;
DMA_SetupChl(&uart->tx_setup);
DMA_SWTrigger(uart->tx_setup.chl);
}
return size;
}
static const struct rt_uart_ops lpc546xx_uart_ops =
{
lpc546xx_configure,
lpc546xx_control,
lpc546xx_putc,
lpc546xx_getc,
lpc546xx_dma_transmit,
};
static void uart_isr(struct rt_serial_device *serial)
{
struct lpc546xx_uart *uart = (struct lpc546xx_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
if(uart->USARTx->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
}
void FLEXCOMM0_IRQHandler(void)
{
rt_interrupt_enter();
uart_isr(&serial[0]);
rt_interrupt_leave();
}
void FLEXCOMM1_IRQHandler(void)
{
rt_interrupt_enter();
uart_isr(&serial[1]);
rt_interrupt_leave();
}
void FLEXCOMM2_IRQHandler(void)
{
rt_interrupt_enter();
uart_isr(&serial[2]);
rt_interrupt_leave();
}
void FLEXCOMM3_IRQHandler(void)
{
rt_interrupt_enter();
uart_isr(&serial[3]);
rt_interrupt_leave();
}
void FLEXCOMM4_IRQHandler(void)
{
rt_interrupt_enter();
uart_isr(&serial[4]);
rt_interrupt_leave();
}
void FLEXCOMM5_IRQHandler(void)
{
rt_interrupt_enter();
uart_isr(&serial[5]);
rt_interrupt_leave();
}
//void DMA0_IRQHandler(void)
//{
// rt_interrupt_enter();
//
// int i;
// static volatile uint32_t INTA;
//
// INTA = DMA0->COMMON[0].INTA;
// DMA0->COMMON[0].INTA = DMA0->COMMON[0].INTA;
//
// if(INTA & (1 << DMAREQ_FLEXCOMM4_TX))
// {
// rt_hw_serial_isr(&serial[4], RT_SERIAL_EVENT_TX_DMADONE);
// }
//
// rt_interrupt_leave();
//}
int rt_hw_uart_init(const char *name)
{
uint32_t instance;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
static USART_Type* const uart_instance_table[] = USART_BASE_PTRS;
sscanf(name, "uart%d", &instance);
uart[instance].USARTx = uart_instance_table[instance];
uart[instance].instance = instance;
serial[instance].ops = &lpc546xx_uart_ops;
serial[instance].config = config;
/* register device */
rt_hw_serial_register(&serial[instance], name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_TX, &uart[instance]);
return 0;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/examples/master402/motor_control.c
|
<reponame>yandld/lpc_uart_server
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include <math.h>
#include <rtthread.h>
#include <rtdevice.h>
#ifdef RT_USING_FINSH
#include <finsh.h>
#endif
#include "canfestival.h"
#include "timers_driver.h"
#include "master402_od.h"
#include "master402_canopen.h"
#define SYNC_DELAY rt_thread_delay(RT_TICK_PER_SECOND/50)
#define PROFILE_POSITION_MODE 1
#define ENCODER_RES (2500 * 4)
void servo_on(uint8_t nodeId)
{
UNS32 speed;
speed = ENCODER_RES * 30;
modes_of_operation_6060 = PROFILE_POSITION_MODE;
profile_velocity_6081 = speed;
target_position_607a = 0;
control_word_6040 = 0x06;
SYNC_DELAY;
control_word_6040 = 0x0f;
}
#ifdef RT_USING_FINSH
FINSH_FUNCTION_EXPORT(servo_on, set servo on);
#endif
void relative_move(int32_t position, int32_t speed)
{
target_position_607a = position;
profile_velocity_6081 = speed;
control_word_6040 = 0x6f;
SYNC_DELAY;
control_word_6040 = 0x7f;
}
#ifdef RT_USING_FINSH
FINSH_FUNCTION_EXPORT_ALIAS(relative_move, relmove, relative move);
#endif
void motorstate(void)
{
rt_kprintf("ControlWord 0x%0X\n", control_word_6040);
rt_kprintf("StatusWord 0x%0X\n", status_word_6041);
rt_kprintf("current position %d\n", position_actual_value_6063);
rt_kprintf("current speed %d\n", velocity_actual_value_606c);
}
#ifdef RT_USING_FINSH
FINSH_FUNCTION_EXPORT(motorstate, print motor state);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/drivers/include/drivers/rt_sensor.h
|
<filename>mcu_source/Libraries/utilities/rtthread/components/drivers/include/drivers/rt_sensor.h
#ifndef __CH_RT_SENSOR_H__
#define __CH_RT_SENSOR_H__
#include <stdint.h>
//#define RT_SENSOR_CTRL_GET_ID (0)
//#define RT_SENSOR_CTRL_GET_INFO (1)
//#define RT_SENSOR_CTRL_SET_RANGE (2)
//#define RT_SENSOR_CTRL_SET_ODR (3)
//#define RT_SENSOR_CTRL_SET_MODE (4)
//#define RT_SENSOR_CTRL_SET_POWER (5)
//#define RT_SENSOR_CTRL_SELF_TEST (6)
//#define RT_SENSOR_CTRL_SET_BW (8)
#define RT_SENSOR_POS_ACC (0)
#define RT_SENSOR_POS_GYR (1)
#define RT_SENSOR_POS_MAG (2)
#define RT_SENSOR_POS_GYR_TEMPERATURE (3)
#define RT_SENSOR_POS_ACC_FIFO (9)
#define RT_SENSOR_POS_GYR_FIFO (10)
#define RT_SENSOR_POS_MAG_FIFO (11)
#define RT_SENSOR_POS_PRS (14)
#define RT_SENSOR_POS_PRS_TEMPERATURE (15)
#define RT_SENSOR_POS_ACC_BW (20)
#define RT_SENSOR_POS_ACC_RG (21)
#define RT_SENSOR_POS_GYR_BW (22)
#define RT_SENSOR_POS_GYR_RG (23)
#define RT_SENSOR_POS_MAG_BW (24)
#define RT_SENSOR_POS_MAG_RG (25)
#define RT_SENSOR_POS_ACC_CLEAR_FIFO (27)
#define RT_SENSOR_POS_GYR_CLEAR_FIFO (28)
#define RT_SENSOR_POS_ACC_WM_FIFO_INT (29)
#define RT_SENSOR_POS_GYR_WM_FIFO_INT (30)
#define RT_SENSOR_POS_CUSTOM (255)
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/usbd_cdc.c
|
#include <string.h>
#include "usb_common.h"
#include "usbd.h"
#include "usbd_cdc.h"
struct ucdc_t
{
struct usbd_t *h;
struct usbd_cdc_callback_t *cb;
struct ucdc_line_coding line_coding;
};
static struct ucdc_t cdc;
uint32_t cdc_standard_request_to_intf_handler(struct usbd_t *h)
{
if(h->setup.request == USB_REQ_SET_INTERFACE)
{
USBD_TRACE("CDC USB_REQ_SET_INTERFACE\r\n");
usbd_status_in_stage();
}
return CH_OK;
}
uint32_t cdc_class_request_handler(struct usbd_t *h)
{
switch(h->setup.request)
{
case 0x21: /* get line coding */
if(cdc.cb && cdc.cb->get_line_coding)
{
cdc.cb->get_line_coding(&cdc.line_coding);
begin_data_in_stage((uint8_t*)&cdc.line_coding, sizeof(struct ucdc_line_coding));
}
break;
case 0x22: /* set control line state */
if(cdc.cb && cdc.cb->set_control_line_serial_state)
{
cdc.cb->set_control_line_serial_state(h->setup.value & 0x01);
}
usbd_status_in_stage();
USBD_TRACE("set control line state 0x%X\r\n", h->setup.value);
break;
case 0x20:
USBD_TRACE("set line coding\r\n");
break;
default:
USBD_TRACE("unknown class request from cdc\r\n");
break;
}
return CH_OK;
}
uint32_t cdc_setup_out_data_received(uint8_t *buf, uint32_t len)
{
return cdc.cb->set_line_coding((struct ucdc_line_coding *)buf);
}
static uint8_t cdc_out_buf[CDC_EP_SIZE];
/* the maxium len cannot reach MAX_EPSIZE */
uint32_t usbd_cdc_send(uint8_t *buf, uint32_t len)
{
usbd_ep_write(USBD_CDC_ACM_EP_BULKIN, buf, len);
return CH_OK;
}
uint32_t cdc_data_ep_handler(uint8_t ep, uint8_t dir)
{
uint32_t size;
if(dir == 1) /* in transfer */
{
if(ep == USBD_CDC_ACM_EP_BULKIN)
{
USBD_TRACE("CDC EP:%d IN TOKEN\r\n", ep);
if(cdc.cb && cdc.cb->send_notify)
{
cdc.cb->send_notify();
}
}
}
else /* out transfer */
{
if(ep == USBD_CDC_ACM_EP_BULKOUT)
{
size = usbd_ep_read(ep, cdc_out_buf);
if(cdc.cb && cdc.cb->recv_handler)
{
cdc.cb->recv_handler(cdc_out_buf, size);
}
}
}
return CH_OK;
}
void usbd_cdc_set_cb(struct usbd_cdc_callback_t *cb)
{
cdc.cb = cb;
}
void usbd_cdc_init(struct usbd_t *h)
{
cdc.h = h;
uint8_t *p;
struct uconfig_descriptor *uconfiguration_descriptor;
desc_t d;
get_descriptor_data("configuration_descriptor", &d);
uconfiguration_descriptor = (struct uconfig_descriptor *)d.buf;
uconfiguration_descriptor->bLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->type = USB_DESC_TYPE_CONFIGURATION;
uconfiguration_descriptor->wTotalLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->bNumInterfaces = 2;
uconfiguration_descriptor->bConfigurationValue = 1;
uconfiguration_descriptor->iConfiguration = 0;
uconfiguration_descriptor->bmAttributes = 0x80;
uconfiguration_descriptor->MaxPower = 0x32;
/* add configuation data */
p = uconfiguration_descriptor->data;
get_descriptor_data("cdc_acm_if0", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
get_descriptor_data("cdc_acm_if1", &d);
memcpy(p, d.buf, d.len);
uconfiguration_descriptor->wTotalLength += d.len;
/* install descriptor */
get_descriptor_data("device_descriptor", &d);
struct udevice_descriptor* device_desc = (struct udevice_descriptor*)d.buf;
device_desc->bDeviceClass = USB_CLASS_CDC;
/* install class callback */
cdc.h->class_request_handler = cdc_class_request_handler;
cdc.h->standard_request_to_intf_handler = cdc_standard_request_to_intf_handler;
cdc.h->setup_out_data_received_handler = cdc_setup_out_data_received;
cdc.h->data_ep_handler = cdc_data_ep_handler;
cdc.h->vender_request_handler = NULL;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/src/pdo.c
|
/*
This file is part of CanFestival, a library implementing CanOpen
Stack.
Copyright (C): <NAME> and <NAME>
See COPYING file for copyrights details.
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA
*/
#include "pdo.h"
#include "objacces.h"
#include "canfestival.h"
#include "sysdep.h"
/*!
** @file pdo.c
** @author <NAME> and <NAME>
** @date Tue Jun 5 09:32:32 2007
**
** @brief
**
**
*/
/*!
**
**
** @param d
** @param numPdo The PDO index
** @param pdo pointer to can message to be filled
**
** @return
**/
UNS8 buildPDO (CO_Data * d, UNS8 numPdo, Message * pdo)
{
const indextable *TPDO_com = d->objdict + d->firstIndex->PDO_TRS + numPdo;
const indextable *TPDO_map = d->objdict + d->firstIndex->PDO_TRS_MAP + numPdo;
UNS8 prp_j = 0x00;
UNS32 offset = 0x00000000;
const UNS8 *pMappingCount = (UNS8 *) TPDO_map->pSubindex[0].pObject;
pdo->cob_id = (UNS16) UNS16_LE(*(UNS32*)TPDO_com->pSubindex[1].pObject & 0x7FF);
pdo->rtr = NOT_A_REQUEST;
MSG_WAR (0x3009, " PDO CobId is : ",
*(UNS32 *) TPDO_com->pSubindex[1].pObject);
MSG_WAR (0x300D, " Number of objects mapped : ", *pMappingCount);
do
{
UNS8 dataType; /* Unused */
UNS8 tmp[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* temporary space to hold bits */
/* pointer fo the var which holds the mapping parameter of an mapping entry */
UNS32 *pMappingParameter =
(UNS32 *) TPDO_map->pSubindex[prp_j + 1].pObject;
UNS16 index = (UNS16) ((*pMappingParameter) >> 16);
UNS32 Size = (UNS32) (*pMappingParameter & (UNS32) 0x000000FF); /* Size in bits */
/* get variable only if Size != 0 and Size is lower than remaining bits in the PDO */
if (Size && ((offset + Size) <= 64))
{
UNS32 ByteSize = 1 + ((Size - 1) >> 3); /*1->8 => 1 ; 9->16 => 2, ... */
UNS8 subIndex =
(UNS8) (((*pMappingParameter) >> (UNS8) 8) & (UNS32) 0x000000FF);
MSG_WAR (0x300F, " got mapping parameter : ", *pMappingParameter);
MSG_WAR (0x3050, " at index : ", TPDO_map->index);
MSG_WAR (0x3051, " sub-index : ", prp_j + 1);
if (getODentry (d, index, subIndex, tmp, &ByteSize, &dataType, 0) !=
OD_SUCCESSFUL)
{
MSG_ERR (0x1013,
" Couldn't find mapped variable at index-subindex-size : ",
(UNS32) (*pMappingParameter));
return 0xFF;
}
/* copy bit per bit in little endian */
CopyBits ((UNS8) Size, ((UNS8 *) tmp), 0, 0,
(UNS8 *) & pdo->data[offset >> 3], (UNS8)(offset % 8), 0);
offset += Size;
}
prp_j++;
}
while (prp_j < *pMappingCount);
pdo->len = (UNS8)(1 + ((offset - 1) >> 3));
MSG_WAR (0x3015, " End scan mapped variable", 0);
return 0;
}
/*!
**
**
** @param d
** @param RPDOIndex
**
** @return
**/
UNS8
sendPDOrequest (CO_Data * d, UNS16 RPDOIndex)
{
UNS32 *pwCobId;
UNS16 offset = d->firstIndex->PDO_RCV;
UNS16 lastIndex = d->lastIndex->PDO_RCV;
if (!d->CurrentCommunicationState.csPDO)
{
return 0;
}
/* Sending the request only if the cobid have been found on the PDO
receive */
/* part dictionary */
MSG_WAR (0x3930, "sendPDOrequest RPDO Index : ", RPDOIndex);
if (offset && RPDOIndex >= 0x1400)
{
offset += RPDOIndex - 0x1400;
if (offset <= lastIndex)
{
/* get the CobId */
pwCobId = d->objdict[offset].pSubindex[1].pObject;
MSG_WAR (0x3930, "sendPDOrequest cobId is : ", *pwCobId);
{
Message pdo;
pdo.cob_id = UNS16_LE(((unsigned short)*pwCobId));
pdo.rtr = REQUEST;
pdo.len = 0;
return canSend (d->canHandle, &pdo);
}
}
}
MSG_ERR (0x1931, "sendPDOrequest : RPDO Index not found : ", RPDOIndex);
return 0xFF;
}
/*!
**
**
** @param d
** @param m
**
** @return
**/
UNS8
proceedPDO (CO_Data * d, Message * m)
{
UNS8 numPdo;
UNS8 numMap; /* Number of the mapped varable */
UNS8 *pMappingCount = NULL; /* count of mapped objects... */
/* pointer to the var which is mapped to a pdo... */
/* void * pMappedAppObject = NULL; */
/* pointer fo the var which holds the mapping parameter of an
mapping entry */
UNS32 *pMappingParameter = NULL;
UNS8 *pTransmissionType = NULL; /* pointer to the transmission
type */
UNS32 *pwCobId = NULL;
UNS8 Size;
UNS8 offset;
UNS8 status;
UNS32 objDict;
UNS16 offsetObjdict;
UNS16 lastIndex;
status = state2;
MSG_WAR (0x3935, "proceedPDO, cobID : ", (UNS16_LE(m->cob_id) & 0x7ff));
offset = 0x00;
numPdo = 0;
numMap = 0;
if ((*m).rtr == NOT_A_REQUEST)
{
offsetObjdict = d->firstIndex->PDO_RCV;
lastIndex = d->lastIndex->PDO_RCV;
if (offsetObjdict)
while (offsetObjdict <= lastIndex)
{
switch (status)
{
case state2:
pwCobId = d->objdict[offsetObjdict].pSubindex[1].pObject;
if (*pwCobId == UNS16_LE(m->cob_id))
{
/* The cobId is recognized */
status = state4;
MSG_WAR (0x3936, "cobId found at index ",
0x1400 + numPdo);
break;
}
else
{
/* received cobId does not match */
numPdo++;
offsetObjdict++;
status = state2;
break;
}
case state4: /* Get Mapped Objects Number */
/* The cobId of the message received has been found in the
dictionnary. */
offsetObjdict = d->firstIndex->PDO_RCV_MAP;
lastIndex = d->lastIndex->PDO_RCV_MAP;
pMappingCount =
(UNS8 *) (d->objdict + offsetObjdict +
numPdo)->pSubindex[0].pObject;
numMap = 0;
while (numMap < *pMappingCount)
{
UNS8 tmp[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
UNS32 ByteSize;
pMappingParameter =
(UNS32 *) (d->objdict + offsetObjdict +
numPdo)->pSubindex[numMap + 1].pObject;
if (pMappingParameter == NULL)
{
MSG_ERR (0x1937, "Couldn't get mapping parameter : ",
numMap + 1);
return 0xFF;
}
/* Get the addresse of the mapped variable. */
/* detail of *pMappingParameter : */
/* The 16 hight bits contains the index, the medium 8 bits
contains the subindex, */
/* and the lower 8 bits contains the size of the mapped
variable. */
Size = (UNS8) (*pMappingParameter & (UNS32) 0x000000FF);
/* set variable only if Size != 0 and
* Size is lower than remaining bits in the PDO */
if (Size && ((offset + Size) <= (m->len << 3)))
{
/* copy bit per bit in little endian */
CopyBits (Size, (UNS8 *) & m->data[offset >> 3],
offset % 8, 0, ((UNS8 *) tmp), 0, 0);
/*1->8 => 1 ; 9->16 =>2, ... */
ByteSize = (UNS32)(1 + ((Size - 1) >> 3));
objDict =
setODentry (d, (UNS16) ((*pMappingParameter) >> 16),
(UNS8) (((*pMappingParameter) >> 8) &
0xFF), tmp, &ByteSize, 0);
if (objDict != OD_SUCCESSFUL)
{
MSG_ERR (0x1938,
"error accessing to the mapped var : ",
numMap + 1);
MSG_WAR (0x2939, " Mapped at index : ",
(*pMappingParameter) >> 16);
MSG_WAR (0x2940, " subindex : ",
((*pMappingParameter) >> 8) & 0xFF);
return 0xFF;
}
MSG_WAR (0x3942,
"Variable updated by PDO cobid : ",
UNS16_LE(m->cob_id));
MSG_WAR (0x3943, " Mapped at index : ",
(*pMappingParameter) >> 16);
MSG_WAR (0x3944, " subindex : ",
((*pMappingParameter) >> 8) & 0xFF);
offset += Size;
}
numMap++;
} /* end loop while on mapped variables */
if (d->RxPDO_EventTimers)
{
TIMEVAL EventTimerDuration = *(UNS16 *)d->objdict[offsetObjdict].pSubindex[5].pObject;
if(EventTimerDuration){
DelAlarm (d->RxPDO_EventTimers[numPdo]);
d->RxPDO_EventTimers[numPdo] = SetAlarm (d, numPdo, d->RxPDO_EventTimers_Handler,
MS_TO_TIMEVAL (EventTimerDuration), 0);
}
}
return 0;
} /* end switch status */
} /* end while */
} /* end if Donnees */
else if ((*m).rtr == REQUEST)
{
MSG_WAR (0x3946, "Receive a PDO request cobId : ", UNS16_LE(m->cob_id));
status = state1;
offsetObjdict = d->firstIndex->PDO_TRS;
lastIndex = d->lastIndex->PDO_TRS;
if (offsetObjdict)
while (offsetObjdict <= lastIndex)
{
/* study of all PDO stored in the objects dictionary */
switch (status)
{
case state1: /* check the CobId */
/* get CobId of the dictionary which match to the received PDO
*/
pwCobId =
(d->objdict +
offsetObjdict)->pSubindex[1].pObject;
if (*pwCobId == UNS16_LE(m->cob_id))
{
status = state4;
break;
}
else
{
numPdo++;
offsetObjdict++;
}
status = state1;
break;
case state4: /* check transmission type */
pTransmissionType =
(UNS8 *) d->objdict[offsetObjdict].pSubindex[2].pObject;
/* If PDO is to be sampled and send on RTR, do it */
if ((*pTransmissionType == TRANS_RTR))
{
status = state5;
break;
}
/* RTR_SYNC means data prepared at SYNC, transmitted on RTR */
else if ((*pTransmissionType == TRANS_RTR_SYNC))
{
if (d->PDO_status[numPdo].
transmit_type_parameter & PDO_RTR_SYNC_READY)
{
/*Data ready, just send */
canSend (d->canHandle,
&d->PDO_status[numPdo].last_message);
return 0;
}
else
{
/* if SYNC did never occur, transmit current data */
/* DS301 do not tell what to do in such a case... */
MSG_ERR (0x1947,
"Not ready RTR_SYNC TPDO send current data : ",
UNS16_LE(m->cob_id));
status = state5;
}
break;
}
else if ((*pTransmissionType == TRANS_EVENT_PROFILE) ||
(*pTransmissionType == TRANS_EVENT_SPECIFIC))
{
/* Zap all timers and inhibit flag */
d->PDO_status[numPdo].event_timer =
DelAlarm (d->PDO_status[numPdo].event_timer);
d->PDO_status[numPdo].inhibit_timer =
DelAlarm (d->PDO_status[numPdo].inhibit_timer);
d->PDO_status[numPdo].transmit_type_parameter &=
~PDO_INHIBITED;
/* Call PDOEventTimerAlarm for this TPDO,
* this will trigger emission et reset timers */
PDOEventTimerAlarm (d, numPdo);
return 0;
}
else
{
/* The requested PDO is not to send on request. So, does
nothing. */
MSG_WAR (0x2947, "PDO is not to send on request : ",
UNS16_LE(m->cob_id));
return 0xFF;
}
case state5: /* build and send requested PDO */
{
Message pdo;
if (buildPDO (d, numPdo, &pdo))
{
MSG_ERR (0x1948, " Couldn't build TPDO number : ", numPdo);
return 0xFF;
}
canSend (d->canHandle, &pdo);
return 0;
}
} /* end switch status */
} /* end while */
} /* end if Requete */
return 0;
}
/*!
**
**
** @param NbBits
** @param SrcByteIndex
** @param SrcBitIndex
** @param SrcBigEndian
** @param DestByteIndex
** @param DestBitIndex
** @param DestBigEndian
**/
void
CopyBits (UNS8 NbBits, UNS8 * SrcByteIndex, UNS8 SrcBitIndex,
UNS8 SrcBigEndian, UNS8 * DestByteIndex, UNS8 DestBitIndex,
UNS8 DestBigEndian)
{
/* This loop copy as many bits that it can each time, crossing */
/* successively bytes */
// boundaries from LSB to MSB.
while (NbBits > 0)
{
/* Bit missalignement between src and dest */
INTEGER8 Vect = DestBitIndex - SrcBitIndex;
/* We can now get src and align it to dest */
UNS8 Aligned =
(UNS8)(Vect > 0 ? *SrcByteIndex << Vect : *SrcByteIndex >> -Vect);
/* Compute the nb of bit we will be able to copy */
UNS8 BoudaryLimit = (Vect > 0 ? 8 - DestBitIndex : 8 - SrcBitIndex);
UNS8 BitsToCopy = BoudaryLimit > NbBits ? NbBits : BoudaryLimit;
/* Create a mask that will serve in: */
UNS8 Mask = (UNS8)
((0xff << (DestBitIndex + BitsToCopy)) |
(0xff >> (8 - DestBitIndex)));
/* - Filtering src */
UNS8 Filtered = (UNS8)(Aligned & ~Mask);
/* - and erase bits where we write, preserve where we don't */
*DestByteIndex &= Mask;
/* Then write. */
*DestByteIndex |= Filtered;
/*Compute next time cursors for src */
if ((SrcBitIndex += BitsToCopy) > 7) /* cross boundary ? */
{
SrcBitIndex = 0; /* First bit */
SrcByteIndex += (SrcBigEndian ? -1 : 1); /* Next byte */
}
/*Compute next time cursors for dest */
if ((DestBitIndex += BitsToCopy) > 7)
{
DestBitIndex = 0; /* First bit */
DestByteIndex += (DestBigEndian ? -1 : 1); /* Next byte */
}
/*And decrement counter. */
NbBits -= BitsToCopy;
}
}
static void sendPdo(CO_Data * d, UNS32 pdoNum, Message * pdo)
{
/*store_as_last_message */
d->PDO_status[pdoNum].last_message = *pdo;
MSG_WAR (0x396D, "sendPDO cobId :", UNS16_LE(pdo->cob_id));
MSG_WAR (0x396E, " Nb octets : ", pdo->len);
canSend (d->canHandle, pdo);
}
/*!
**
**
** @param d
**
** @return
**/
UNS8
sendPDOevent (CO_Data * d)
{
/* Calls _sendPDOevent specifying it is not a sync event */
return _sendPDOevent (d, 0);
}
UNS8
sendOnePDOevent (CO_Data * d, UNS8 pdoNum)
{
UNS16 offsetObjdict;
Message pdo;
if (!d->CurrentCommunicationState.csPDO ||
(d->PDO_status[pdoNum].transmit_type_parameter & PDO_INHIBITED))
{
return 0;
}
offsetObjdict = (UNS16) (d->firstIndex->PDO_TRS + pdoNum);
if (*(UNS32 *) d->objdict[offsetObjdict].pSubindex[1].pObject & 0x80000000)
{
return 0;
}
MSG_WAR (0x3968, " PDO is on EVENT. Trans type : ",
*((UNS8 *) d->objdict[offsetObjdict].pSubindex[2].pObject));
memset(&pdo, 0, sizeof(pdo));
if (buildPDO (d, pdoNum, &pdo))
{
MSG_ERR (0x3907, " Couldn't build TPDO number : ",
pdoNum);
return 0;
}
/*
changed by yandld: disable compared with last data
if (d->PDO_status[pdoNum].last_message.cob_id == pdo.cob_id
&& d->PDO_status[pdoNum].last_message.len == pdo.len
&& memcmp(d->PDO_status[pdoNum].last_message.data,
pdo.data, 8) == 0
)
*/
/*Compare new and old PDO */
if (d->PDO_status[pdoNum].last_message.cob_id == pdo.cob_id
&& d->PDO_status[pdoNum].last_message.len == pdo.len
)
{
/* No changes -> go to next pdo */
return 0;
}
else
{
TIMEVAL EventTimerDuration;
TIMEVAL InhibitTimerDuration;
MSG_WAR (0x306A, "Changes TPDO number : ", pdoNum);
/* Changes detected -> transmit message */
EventTimerDuration =
*(UNS16 *) d->objdict[offsetObjdict].pSubindex[5].
pObject;
InhibitTimerDuration =
*(UNS16 *) d->objdict[offsetObjdict].pSubindex[3].
pObject;
/* Start both event_timer and inhibit_timer */
if (EventTimerDuration)
{
DelAlarm (d->PDO_status[pdoNum].event_timer);
d->PDO_status[pdoNum].event_timer =
SetAlarm (d, pdoNum, &PDOEventTimerAlarm,
MS_TO_TIMEVAL (EventTimerDuration), 0);
}
if (InhibitTimerDuration)
{
DelAlarm (d->PDO_status[pdoNum].inhibit_timer);
d->PDO_status[pdoNum].inhibit_timer =
SetAlarm (d, pdoNum, &PDOInhibitTimerAlarm,
US_TO_TIMEVAL (InhibitTimerDuration *
100), 0);
/* and inhibit TPDO */
d->PDO_status[pdoNum].transmit_type_parameter |=
PDO_INHIBITED;
}
sendPdo(d, pdoNum, &pdo);
}
return 1;
}
void
PDOEventTimerAlarm (CO_Data * d, UNS32 pdoNum)
{
/* This is needed to avoid deletion of re-attribuated timer */
d->PDO_status[pdoNum].event_timer = TIMER_NONE;
/* force emission of PDO by artificially changing last emitted */
d->PDO_status[pdoNum].last_message.cob_id = 0;
sendOnePDOevent (d, (UNS8) pdoNum);
}
void
PDOInhibitTimerAlarm (CO_Data * d, UNS32 pdoNum)
{
/* This is needed to avoid deletion of re-attribuated timer */
d->PDO_status[pdoNum].inhibit_timer = TIMER_NONE;
/* Remove inhibit flag */
d->PDO_status[pdoNum].transmit_type_parameter &= ~PDO_INHIBITED;
sendOnePDOevent (d, (UNS8) pdoNum);
}
void
_RxPDO_EventTimers_Handler(CO_Data *d, UNS32 pdoNum)
{
(void)d;
(void)pdoNum;
}
/*!
**
**
** @param d
** @param isSyncEvent
**
** @return
**/
UNS8
_sendPDOevent (CO_Data * d, UNS8 isSyncEvent)
{
UNS8 pdoNum = 0x00; /* number of the actual processed pdo-nr. */
UNS8 *pTransmissionType = NULL;
UNS8 status = state3;
UNS16 offsetObjdict = d->firstIndex->PDO_TRS;
UNS16 offsetObjdictMap = d->firstIndex->PDO_TRS_MAP;
UNS16 lastIndex = d->lastIndex->PDO_TRS;
if (!d->CurrentCommunicationState.csPDO)
{
return 0;
}
/* study all PDO stored in the objects dictionary */
if (offsetObjdict)
{
Message pdo;/* = Message_Initializer;*/
memset(&pdo, 0, sizeof(pdo));
while (offsetObjdict <= lastIndex)
{
switch (status)
{
case state3:
if ( /* bSubCount always 5 with objdictedit -> check disabled */
/*d->objdict[offsetObjdict].bSubCount < 5 ||*/
/* check if TPDO is not valid */
*(UNS32 *) d->objdict[offsetObjdict].pSubindex[1].
pObject & 0x80000000)
{
MSG_WAR (0x3960, "Not a valid PDO ", 0x1800 + pdoNum);
/*Go next TPDO */
status = state11;
break;
}
/* get the PDO transmission type */
pTransmissionType =
(UNS8 *) d->objdict[offsetObjdict].pSubindex[2].pObject;
MSG_WAR (0x3962, "Reading PDO at index : ", 0x1800 + pdoNum);
/* check if transmission type is SYNCRONOUS */
/* message transmited every n SYNC with n=TransmissionType */
if (isSyncEvent &&
(*pTransmissionType >= TRANS_SYNC_MIN) &&
(*pTransmissionType <= TRANS_SYNC_MAX) &&
(++d->PDO_status[pdoNum].transmit_type_parameter ==
*pTransmissionType))
{
/*Reset count of SYNC */
d->PDO_status[pdoNum].transmit_type_parameter = 0;
MSG_WAR (0x3964, " PDO is on SYNCHRO. Trans type : ",
*pTransmissionType);
memset(&pdo, 0, sizeof(pdo));
/*{
Message msg_init = Message_Initializer;
pdo = msg_init;
}*/
if (buildPDO (d, pdoNum, &pdo))
{
MSG_ERR (0x1906, " Couldn't build TPDO number : ",
pdoNum);
status = state11;
break;
}
status = state5;
/* If transmission RTR, with data sampled on SYNC */
}
else if (isSyncEvent && (*pTransmissionType == TRANS_RTR_SYNC))
{
if (buildPDO
(d, pdoNum, &d->PDO_status[pdoNum].last_message))
{
MSG_ERR (0x1966, " Couldn't build TPDO number : ",
pdoNum);
d->PDO_status[pdoNum].transmit_type_parameter &=
~PDO_RTR_SYNC_READY;
}
else
{
d->PDO_status[pdoNum].transmit_type_parameter |=
PDO_RTR_SYNC_READY;
}
status = state11;
break;
/* If transmission on Event and not inhibited, check for changes */
}
else
if ( (isSyncEvent && (*pTransmissionType == TRANS_SYNC_ACYCLIC))
||
(!isSyncEvent && (*pTransmissionType == TRANS_EVENT_PROFILE || *pTransmissionType == TRANS_EVENT_SPECIFIC)
&& !(d->PDO_status[pdoNum].transmit_type_parameter & PDO_INHIBITED)))
{
sendOnePDOevent(d, pdoNum);
status = state11;
}
else
{
MSG_WAR (0x306C,
" PDO is not on EVENT or synchro or not at this SYNC. Trans type : ",
*pTransmissionType);
status = state11;
}
break;
case state5: /*Send the pdo */
sendPdo(d, pdoNum, &pdo);
status = state11;
break;
case state11: /*Go to next TPDO */
pdoNum++;
offsetObjdict++;
offsetObjdictMap++;
MSG_WAR (0x3970, "next pdo index : ", pdoNum);
status = state3;
break;
default:
MSG_ERR (0x1972, "Unknown state has been reached :", status);
return 0xFF;
} /* end switch case */
} /* end while */
}
return 0;
}
/*!
**
**
** @param d
** @param OD_entry
** @param bSubindex
** @return always 0
**/
UNS32
TPDO_Communication_Parameter_Callback (CO_Data * d,
const indextable * OD_entry,
UNS8 bSubindex)
{
/* If PDO are actives */
if (d->CurrentCommunicationState.csPDO)
switch (bSubindex)
{
case 2: /* Changed transmition type */
case 3: /* Changed inhibit time */
case 5: /* Changed event time */
{
const indextable *TPDO_com = d->objdict + d->firstIndex->PDO_TRS;
UNS8 numPdo = (UNS8) (OD_entry - TPDO_com); /* number of the actual processed pdo-nr. */
/* Zap all timers and inhibit flag */
d->PDO_status[numPdo].event_timer =
DelAlarm (d->PDO_status[numPdo].event_timer);
d->PDO_status[numPdo].inhibit_timer =
DelAlarm (d->PDO_status[numPdo].inhibit_timer);
d->PDO_status[numPdo].transmit_type_parameter = 0;
/* Call PDOEventTimerAlarm for this TPDO, this will trigger emission et reset timers */
PDOEventTimerAlarm (d, numPdo);
return 0;
}
default: /* other subindex are ignored */
break;
}
return 0;
}
void
PDOInit (CO_Data * d)
{
/* For each TPDO mapping parameters */
UNS16 pdoIndex = 0x1800; /* OD index of TDPO */
UNS16 offsetObjdict = d->firstIndex->PDO_TRS;
UNS16 lastIndex = d->lastIndex->PDO_TRS;
if (offsetObjdict)
while (offsetObjdict <= lastIndex)
{
/* Assign callbacks to sensible TPDO mapping subindexes */
UNS32 errorCode;
const indextable *ptrTable = (*d->scanIndexOD)(d, pdoIndex, &errorCode);
if (errorCode == OD_SUCCESSFUL)
{
/*Assign callbacks to corresponding subindex */
/* Transmission type */
ptrTable->pSubindex[2].callback = &TPDO_Communication_Parameter_Callback;
/* Inhibit time */
ptrTable->pSubindex[3].callback = &TPDO_Communication_Parameter_Callback;
/* Event timer */
ptrTable->pSubindex[5].callback = &TPDO_Communication_Parameter_Callback;
}
pdoIndex++;
offsetObjdict++;
}
/* Trigger a non-sync event */
_sendPDOevent (d, 0);
}
void
PDOStop (CO_Data * d)
{
/* For each TPDO mapping parameters */
UNS8 pdoNum = 0x00; /* number of the actual processed pdo-nr. */
UNS16 offsetObjdict = d->firstIndex->PDO_TRS;
UNS16 lastIndex = d->lastIndex->PDO_TRS;
if (offsetObjdict)
while (offsetObjdict <= lastIndex)
{
/* Delete TPDO timers */
d->PDO_status[pdoNum].event_timer =
DelAlarm (d->PDO_status[pdoNum].event_timer);
d->PDO_status[pdoNum].inhibit_timer =
DelAlarm (d->PDO_status[pdoNum].inhibit_timer);
/* Reset transmit type parameter */
d->PDO_status[pdoNum].transmit_type_parameter = 0;
d->PDO_status[pdoNum].last_message.cob_id = 0;
pdoNum++;
offsetObjdict++;
}
}
void
PDOEnable (CO_Data * d, UNS8 pdoNum)
{
UNS16 offsetObjdict;
if(!d->firstIndex->PDO_TRS)
return;
offsetObjdict = (UNS16) (d->firstIndex->PDO_TRS + pdoNum);
*(UNS32 *) d->objdict[offsetObjdict].pSubindex[1].pObject &= ~0x80000000;
}
void
PDODisable (CO_Data * d, UNS8 pdoNum)
{
UNS16 offsetObjdict;
if(!d->firstIndex->PDO_TRS)
return;
offsetObjdict = (UNS16) (d->firstIndex->PDO_TRS + pdoNum);
*(UNS32 *) d->objdict[offsetObjdict].pSubindex[1].pObject |= 0x80000000;
}
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/main.c
|
#include <stdio.h>
#include <string.h>
#include <rthw.h>
#include <stdlib.h>
#include "common.h"
#include "gpio.h"
#include "syscon.h"
#include "shell.h"
#include "dma.h"
#include "uart.h"
#include "rtthread.h"
#define LOG_TAG "example"
#define LOG_LVL LOG_LVL_DBG
#include "ulog.h"
int rt_hw_uart_init(const char *name);
void rt_usbd_init(void);
void serial_tx_thread_entey(void* parameter);
void usb_data_in_thread_entry(void* parameter);
void usb_ctl_in_thread_entry(void* parameter);
void serial_rx_thread_entry(void* parameter);
void thread_led_entry(void* parameter);
void uart_dma_test_thread_entry(void* parameter);
void cpu_usage_init(void);
void init_thread_entry(void* parameter)
{
int i;
rt_thread_t tid;
cpu_usage_init();
rt_show_version();
// LOG_I("ResetCause:0x%08X", GetResetCause());
// LOG_I("kCoreClock:%dHz", GetClock(kCoreClock));
// LOG_I("kFROHfClock:%dHz", GetClock(kFROHfClock));
// LOG_I("kFROLfClock:%dHz", GetClock(kFROLfClock));
// rt_hw_uart_init("uart4");
//
// rt_device_t u = rt_device_find("uart4");
// rt_device_open(u, RT_DEVICE_FLAG_DMA_TX | RT_DEVICE_OFLAG_RDWR);
// rt_device_write(u, 0, "1234567890 ", 10);
// rt_device_write(u, 0, "1234567890 ", 10);
//
// while(1)
// {
// rt_thread_delay(1);
// }
rt_usbd_init();
DMA_Init();
/* loopback */
for(i=1; i<10; i++)
{
UART_Init(i, 115200);
UART_SetDMAMode(i, kUART_DMARx, true);
}
tid = rt_thread_create("serial_tx", serial_tx_thread_entey, RT_NULL, 256, 11, 20);
rt_thread_startup(tid);
rt_thread_delay(10);
tid = rt_thread_create("usb_data_in", usb_data_in_thread_entry, RT_NULL, 512, 9, 20);
rt_thread_startup(tid);
tid = rt_thread_create("usb_ctl_in", usb_ctl_in_thread_entry, RT_NULL, 512, 16, 20);
rt_thread_startup(tid);
tid = rt_thread_create("serial_rx", serial_rx_thread_entry, RT_NULL, 256, 12, 20);
rt_thread_startup(tid);
tid = rt_thread_create("serial_rx", thread_led_entry, RT_NULL, 256, 19, 20);
rt_thread_startup(tid);
// tid = rt_thread_create("test", uart_dma_test_thread_entry, RT_NULL, 512, 11, 20);
// rt_thread_startup(tid);
while(1)
{
rt_thread_delay(100);
}
}
void rt_application_init(void* parameter)
{
rt_thread_t tid;
/* FC0 */
SetPinMux(HW_GPIO0, 29, 1); /* UART0 RX */
SetPinMux(HW_GPIO0, 30, 1); /* UART0 TX */
/* FC1 */
SetPinMux(HW_GPIO1, 11, 2);
SetPinMux(HW_GPIO1, 10, 2);
SetPinMux(HW_GPIO0, 13, 1);
SetPinMux(HW_GPIO0, 14, 1);
/* FC2 */
SetPinMux(HW_GPIO1, 25, 1);
SetPinMux(HW_GPIO1, 24, 1);
SetPinMux(HW_GPIO1, 26, 1);
SetPinMux(HW_GPIO1, 27, 1);
/* FC3 */
SetPinMux(HW_GPIO0, 2, 1);
SetPinMux(HW_GPIO0, 3, 1);
SetPinMux(HW_GPIO0, 1, 2);
SetPinMux(HW_GPIO0, 7, 1);
/* FC4 */
SetPinMux(HW_GPIO3, 27, 3);
SetPinMux(HW_GPIO3, 26, 3);
SetPinMux(HW_GPIO3, 28, 3);
SetPinMux(HW_GPIO3, 39, 3);
/* FC5 */
SetPinMux(HW_GPIO2, 13, 5);
SetPinMux(HW_GPIO2, 12, 5);
SetPinMux(HW_GPIO2, 14, 5);
SetPinMux(HW_GPIO2, 15, 5);
/* FC6 */
SetPinMux(HW_GPIO4, 3, 2);
SetPinMux(HW_GPIO4, 2, 2);
SetPinMux(HW_GPIO4, 0, 2);
//SetPinMux(HW_GPIO0, 3, 1);
/* FC7 */
SetPinMux(HW_GPIO2, 20, 3);
SetPinMux(HW_GPIO2, 19, 3);
SetPinMux(HW_GPIO1, 21, 1);
SetPinMux(HW_GPIO1, 20, 1);
/* FC8 */
SetPinMux(HW_GPIO3, 16, 1);
SetPinMux(HW_GPIO3, 17, 1);
SetPinMux(HW_GPIO3, 4, 3);
SetPinMux(HW_GPIO3, 5, 3);
/* FC9 */
SetPinMux(HW_GPIO3, 3, 2);
SetPinMux(HW_GPIO3, 2, 2);
SetPinMux(HW_GPIO3, 30, 1);
SetPinMux(HW_GPIO3, 31, 1);
rt_hw_uart_init("uart0");
rt_console_set_device("uart0");
rt_components_board_init();
rt_components_init();
tid = rt_thread_create("init", init_thread_entry, RT_NULL, 512, 5, 20);
rt_thread_startup(tid);
}
int main(void)
{
SetFROClock(96*1000*1000, true);
SetupSystemPLL(kPLLSrcCLKIN, 180*1000*1000);
rt_hw_interrupt_disable();
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND - 1);
rt_system_timer_init();
rt_system_scheduler_init();
rt_device_init_all();
rt_system_timer_thread_init();
rt_thread_idle_init();
rt_system_heap_init((void*)0x20000000, (void*)(0x10000 + 0x20000000));
rt_application_init(RT_NULL);
rt_system_scheduler_start();
while(1)
{
DelayMs(500);
}
}
void SysTick_Handler(void)
{
rt_interrupt_enter();
rt_tick_increase();
rt_interrupt_leave();
}
void DelayMs(uint32_t ms)
{
rt_thread_delay(rt_tick_from_millisecond(ms));
}
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t delta;
us = us * (SysTick->LOAD/(1000000/RT_TICK_PER_SECOND));
delta = SysTick->VAL;
while (delta - SysTick->VAL< us);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/examples/master402/canopen_callback.h
|
<reponame>yandld/lpc_uart_server<gh_stars>1-10
#include "data.h"
void master402_heartbeatError(CO_Data* d, UNS8 heartbeatID);
void master402_initialisation(CO_Data* d);
void master402_preOperational(CO_Data* d);
void master402_operational(CO_Data* d);
void master402_stopped(CO_Data* d);
void master402_post_sync(CO_Data* d);
void master402_post_TPDO(CO_Data* d);
void master402_storeODSubIndex(CO_Data* d, UNS16 wIndex, UNS8 bSubindex);
void master402_post_emcy(CO_Data* d, UNS8 nodeID, UNS16 errCode, UNS8 errReg, const UNS8 errSpec[5]);
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/mesh_cmd.c
|
#include <rtthread.h>
#include "common.h"
#include "uart.h"
#include "uart_bridge.h"
#include "usbd.h"
#ifdef FINSH_USING_MSH
#include <finsh.h>
static int reboot(int argc, char** argv)
{
NVIC_SystemReset();
return 0;
}
MSH_CMD_EXPORT(reboot, reboot);
static int cpuinfo(int argc, char** argv)
{
uint32_t clock;
rt_kprintf("LPC54606\r\n");
clock = GetClock(kCoreClock);
rt_kprintf("CoreClock:%dHz\r\n", clock);
uint32_t tick = rt_tick_get();
rt_kprintf("tick:%d, time:%ds\r\n", tick, tick/RT_TICK_PER_SECOND);
return 0;
}
MSH_CMD_EXPORT(cpuinfo, cpuinfo);
static int uloop(int argc, char** argv)
{
int i, instance, val;
rt_kprintf("uloop\r\n");
if(argc == 1)
{
for(i=0; i<10; i++)
{
rt_kprintf("uart%d loop:%d\r\n", i, UART_GetLoopbackMode(i));
}
}
if(argc == 3)
{
instance = strtoul(argv[1], NULL, NULL);
val = strtoul(argv[2], NULL, NULL);
UART_SetLoopbackMode(instance, val);
rt_kprintf("set: uart%d loop:%d\r\n", instance, UART_GetLoopbackMode(instance));
}
return 0;
}
MSH_CMD_EXPORT(uloop, set uart loopback mode);
extern uart_bridge_t bridge[10];
extern stat_t stat;
static int ustat(int argc, char** argv)
{
int i;
rt_kprintf("uart stat\r\n");
if(argc == 2)
{
for(i=0; i<10; i++)
{
bridge[i].tx_sum = 0;
bridge[i].rx_sum = 0;
bridge[i].rx_dma_sum = 0;
}
}
for(i=0; i<10; i++)
{
rt_kprintf("uart[%d] down:%d up:%d rx_dma:%d tbuf:%d rbuf:%d\r\n", i, bridge[i].tx_sum, bridge[i].rx_sum, bridge[i].rx_dma_sum, bridge_uart_tx_get_free(i), bridge_uart_rx_get_free(i));
}
rt_kprintf("total out:%d B/s\r\n", stat.total_out_speed);
rt_kprintf("total in:%d B/s\r\n", stat.total_in_speed);
return 0;
}
MSH_CMD_EXPORT(ustat, uart stat info);
static int epsend(int argc, char** argv)
{
uint8_t ep = strtoul(argv[1], NULL, NULL);
uint8_t data = strtoul(argv[2], NULL, NULL);
rt_kprintf("ep%d send :0x%X\r\n", ep, data);
uint8_t buf[4];
buf[0] = 13;
buf[1] = data;
buf[2] = 0;
buf[3] = 0;
usbd_ep_write(2, buf, sizeof(buf));
return 0;
}
MSH_CMD_EXPORT(epsend, send ep data);
static int test_uart_tx(int argc, char** argv)
{
uint8_t chl = strtoul(argv[1], NULL, NULL);
bridge_uart_send(chl, "123456", 6);
}
MSH_CMD_EXPORT(test_uart_tx, test uart tx send);
static int led(int argc, char** argv)
{
uint8_t idx = strtoul(argv[1], NULL, NULL);
uint8_t val = strtoul(argv[2], NULL, NULL);
set_led(idx, val);
}
MSH_CMD_EXPORT(led, test led);
#define CPU_USAGE_CALC_TICK 10
#define CPU_USAGE_LOOP 100
static rt_uint8_t cpu_usage_major = 0, cpu_usage_minor= 0;
static rt_uint32_t total_count = 0;
static void cpu_usage_idle_hook()
{
rt_tick_t tick;
rt_uint32_t count;
volatile rt_uint32_t loop;
if (total_count == 0)
{
/* get total count */
rt_enter_critical();
tick = rt_tick_get();
while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK)
{
total_count ++;
loop = 0;
while (loop < CPU_USAGE_LOOP) loop ++;
}
rt_exit_critical();
}
count = 0;
/* get CPU usage */
tick = rt_tick_get();
while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK)
{
count ++;
loop = 0;
while (loop < CPU_USAGE_LOOP) loop ++;
}
/* calculate major and minor */
if (count < total_count)
{
count = total_count - count;
cpu_usage_major = (count * 100) / total_count;
cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count;
}
else
{
total_count = count;
/* no CPU usage */
cpu_usage_major = 0;
cpu_usage_minor = 0;
}
}
void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor)
{
RT_ASSERT(major != RT_NULL);
RT_ASSERT(minor != RT_NULL);
*major = cpu_usage_major;
*minor = cpu_usage_minor;
}
static int cpu(int argc, char** argv)
{
printf("%-16s%d.%d%%\r\n", "cpu ", cpu_usage_major, cpu_usage_minor);
return 0;
}
MSH_CMD_EXPORT(cpu, cpu usage);
void cpu_usage_init(void)
{
/* set idle thread hook */
rt_thread_idle_sethook(cpu_usage_idle_hook);
}
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/inc/usbd_cp210x.h
|
<filename>mcu_source/Libraries/utilities/chusb/inc/usbd_cp210x.h<gh_stars>1-10
#ifndef __USBD_CP210X_SERIAL_H_
#define __USBD_CP210X_SERIAL_H_
#include <stdint.h>
#include <usbd.h>
#include <usb_common.h>
/* Config request codes */
#define CP210X_IFC_ENABLE 0x00
#define CP210X_SET_BAUDDIV 0x01
#define CP210X_GET_BAUDDIV 0x02
#define CP210X_SET_LINE_CTL 0x03
#define CP210X_GET_LINE_CTL 0x04
#define CP210X_SET_BREAK 0x05
#define CP210X_IMM_CHAR 0x06
#define CP210X_SET_MHS 0x07
#define CP210X_GET_MDMSTS 0x08
#define CP210X_SET_XON 0x09
#define CP210X_SET_XOFF 0x0A
#define CP210X_SET_EVENTMASK 0x0B
#define CP210X_GET_EVENTMASK 0x0C
#define CP210X_SET_CHAR 0x0D
#define CP210X_GET_CHARS 0x0E
#define CP210X_GET_PROPS 0x0F
#define CP210X_GET_COMM_STATUS 0x10
#define CP210X_RESET 0x11
#define CP210X_PURGE 0x12
#define CP210X_SET_FLOW 0x13
#define CP210X_GET_FLOW 0x14
#define CP210X_EMBED_EVENTS 0x15
#define CP210X_GET_EVENTSTATE 0x16
#define CP210X_SET_CHARS 0x19
#define CP210X_GET_BAUDRATE 0x1D
#define CP210X_SET_BAUDRATE 0x1E
#define CP210X_VENDOR_SPECIFIC 0xFF
typedef struct
{
uint16_t wLength;
uint16_t bcdVersion;
uint32_t ulServiceMask;
uint32_t _reserved8;
uint32_t ulMaxTxQueue;
uint32_t ulMaxRxQueue;
uint32_t ulMaxBaud;
uint32_t ulProvSubType;
uint32_t ulProvCapabilities;
uint32_t ulSettableParams;
uint32_t ulSettableBaud;
uint16_t wSettableData;
uint16_t _reserved42;
uint32_t ulCurrentTxQueue;
uint32_t ulCurrentRxQueue;
uint32_t _reserved52;
uint32_t _reserved56;
uint16_t uniProvName[15];
}cp210x_cpr_t;
__packed typedef struct
{
uint32_t ulErrors;
uint32_t ulHoldReasons;
uint32_t ulAmountInInQueue;
uint32_t ulAmountInOutQueue;
uint8_t bEofReceived;
uint8_t bWaitForImmediate;
uint8_t bReserved;
} cp210x_ssr_t;
struct usbd_cp210x_callback_t
{
uint32_t (*get_line_coding)(struct ucdc_line_coding *line_coding);
uint32_t (*set_line_coding)(struct ucdc_line_coding *line_coding);
uint32_t (*set_control_line_serial_state)(uint8_t val);
uint32_t (*recv_handler)(uint8_t *buf, uint32_t len);
uint32_t (*send_notify)(void);
};
void usbd_vsc_cp210x_init(struct usbd_t *h);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/HAL_device.h
|
/**************************************************************************//**
* @file HAL_device.h
* @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion
* microcontroller devices
*
* This is a convenience header file for defining the part number on the
* build command line, instead of specifying the part specific header file.
*
* Example: Add "-MM32F103xCxE_o" to your build options, to define part
* Add "#include "HAL_device.h" to your source files
*
*
* @version 1.0.1
*
*
*****************************************************************************/
#ifndef __HAL_device_H
#define __HAL_device_H
#include "MM32F103xCxE_o.h"
#include "system_MM32F103xCxE_o.h"
#endif /* __HAL_device_H */
/*-------------------------(C) COPYRIGHT 2018 MindMotion ----------------------*/
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/LPC84x.h
|
<filename>mcu_source/Libraries/startup/inc/LPC84x.h
// Attention please!
// This is the header file for the LPC84x product family only.
/****************************************************************************
* $Id:: LPC84x.h 6437 2012-10-31 11:06:06Z dep00694 $
* Project: NXP LPC8xx software example
*
* Description:
* CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
* NXP LPC800 Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*
* modified by ARM 24.04.2017
****************************************************************************/
#ifndef __LPC84x_H__
#define __LPC84x_H__
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
This file defines all structures and symbols for LPC8xx:
- Registers and bitfields
- peripheral base address
- PIO definitions
@{
*/
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
Configuration of the Cortex-M0+ Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** LPC84x Specific Interrupt Numbers ********************************************************/
SPI0_IRQn = 0, /*!< SPI0 */
SPI1_IRQn = 1, /*!< SPI1 */
DAC0_IRQn = 2, /*!< DAC0 Interrupt */
UART0_IRQn = 3, /*!< USART0 */
UART1_IRQn = 4, /*!< USART1 */
UART2_IRQn = 5, /*!< USART2 */
FAIM_IRQn = 6, /*!< FAIM Interrupt */
I2C1_IRQn = 7, /*!< I2C1 */
I2C0_IRQn = 8, /*!< I2C0 */
SCT_IRQn = 9, /*!< SCT */
MRT_IRQn = 10, /*!< MRT */
CMP_IRQn = 11, /*!< Analog Comparator */
WDT_IRQn = 12, /*!< WDT */
BOD_IRQn = 13, /*!< BOD */
FLASH_IRQn = 14, /*!< FLASH */
WKT_IRQn = 15, /*!< WKT Interrupt */
ADC_SEQA_IRQn = 16, /*!< ADC Seq. A */
ADC_SEQB_IRQn = 17, /*!< ADC Seq. B */
ADC_THCMP_IRQn = 18, /*!< ADC Thresh Comp */
ADC_OVR_IRQn = 19, /*!< ADC overrun */
DMA_IRQn = 20, /*!< DMA */
I2C2_IRQn = 21, /*!< I2C2 */
I2C3_IRQn = 22, /*!< I2C3 */
CTIMER0_IRQn = 23, /*!< Timer 0 Interrupt */
PININT0_IRQn = 24, /*!< External Interrupt 0 */
PININT1_IRQn = 25, /*!< External Interrupt 1 */
PININT2_IRQn = 26, /*!< External Interrupt 2 */
PININT3_IRQn = 27, /*!< External Interrupt 3 */
PININT4_IRQn = 28, /*!< External Interrupt 4 */
PININT5_IRQn = 29, /*!< External Interrupt 5 shared slot with DAC1 */
PININT6_IRQn = 30, /*!< External Interrupt 6 shared slot with UART3 */
PININT7_IRQn = 31, /*!< External Interrupt 7 shared slot with UART4 */
} IRQn_Type;
#define DAC1_IRQn PININT5_IRQn // Pin int. 5 shared slot with DAC1
#define UART3_IRQn PININT6_IRQn // Pin int. 6 shared slot with UART3
#define UART4_IRQn PININT7_IRQn // Pin int. 7 shared slot with UART4
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0PLUS_REV 0x0001
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/*@}*/ /* end of group LPC8xx_CMSIS */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
#include "system_LPC8xx.h" /* System Header */
/* ARM 24.04.2017 */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
# warning Not supported compiler type
#endif
/******************************************************************************/
/* Device Specific Peripheral Registers structures */
/******************************************************************************/
//------------- System Control (SYSCON) --------------------------------------
typedef struct
{
__IO uint32_t SYSMEMREMAP ; ///< (0x000) System memory remap
__IO uint32_t RESERVED0[1] ; ///< (0x004)
__IO uint32_t SYSPLLCTRL ; ///< (0x008) System PLL control
__I uint32_t SYSPLLSTAT ; ///< (0x00C) System PLL status
__IO uint32_t RESERVED1[4] ; ///< (0x010 - 0x01C)
__IO uint32_t SYSOSCCTRL ; ///< (0x020) System oscillator control
__IO uint32_t WDTOSCCTRL ; ///< (0x024) Watchdog oscillator control
__IO uint32_t FROOSCCTRL ; ///< (0x028) FRO oscillator control
__IO uint32_t RESERVED2[1] ; ///< (0x02C)
__IO uint32_t FRODIRECTCLKUEN ; ///< (0x030) FRO direct clock source update
__IO uint32_t RESERVED3[1] ; ///< (0x034)
__IO uint32_t SYSRSTSTAT ; ///< (0x038) System reset status 0
__IO uint32_t FAIMCTRL ; ///< (0x03C) FAIM row protect control 0xFF
__IO uint32_t SYSPLLCLKSEL ; ///< (0x040) System PLL clock source select 0
__IO uint32_t SYSPLLCLKUEN ; ///< (0x044) System PLL clock source update
__IO uint32_t MAINCLKPLLSEL ; ///< (0x048) Main clock pll source select 0
__IO uint32_t MAINCLKPLLUEN ; ///< (0x04C) Main clock pll source update enable
__IO uint32_t MAINCLKSEL ; ///< (0x050) Main clock source select
__IO uint32_t MAINCLKUEN ; ///< (0x054) Main clock source update enable
__IO uint32_t SYSAHBCLKDIV ; ///< (0x058) System clock divider
__IO uint32_t RESERVED4[1] ; ///< (0x05C)
__IO uint32_t RESERVED4a[1] ; ///< (0x060)
__IO uint32_t ADCCLKSEL ; ///< (0x064) ADC clock source select
__IO uint32_t ADCCLKDIV ; ///< (0x068) ADC clock divider
__IO uint32_t SCTCLKSEL ; ///< (0x06C) SCT clock source select
__IO uint32_t SCTCLKDIV ; ///< (0x070) SCT clock divider
__IO uint32_t EXTCLKSEL ; ///< (0x074) External clock source select
__IO uint32_t RESERVED5[2] ; ///< (0x078 - 0x07C)
union {
__IO uint32_t SYSAHBCLKCTRL[2] ;
struct {
__IO uint32_t SYSAHBCLKCTRL0 ; ///< (0x080) System clock group 0 control
__IO uint32_t SYSAHBCLKCTRL1 ; ///< (0x084) System clock group 1 control
};
};
union {
__IO uint32_t PRESETCTRL[2] ;
struct {
__IO uint32_t PRESETCTRL0 ; ///< (0x088) Peripheral reset group 0 control
__IO uint32_t PRESETCTRL1 ; ///< (0x08C) Peripheral reset group 1 control
};
};
union {
__IO uint32_t FCLKSEL[11] ;
struct {
__IO uint32_t UART0CLKSEL ; ///< (0x090) FCLK0 clock source select
__IO uint32_t UART1CLKSEL ; ///< (0x094) FCLK1 clock source select
__IO uint32_t UART2CLKSEL ; ///< (0x098) FCLK2 clock source select
__IO uint32_t UART3CLKSEL ; ///< (0x09C) FCLK3 clock source select
__IO uint32_t UART4CLKSEL ; ///< (0x0A0) FCLK4 clock source select
__IO uint32_t I2C0CLKSEL ; ///< (0x0A4) FCLK5 clock source select
__IO uint32_t I2C1CLKSEL ; ///< (0x0A8) FCLK6 clock source select
__IO uint32_t I2C2CLKSEL ; ///< (0x0AC) FCLK7 clock source select
__IO uint32_t I2C3CLKSEL ; ///< (0x0B0) FCLK8 clock source select
__IO uint32_t SPI0CLKSEL ; ///< (0x0B4) FCLK9 clock source select
__IO uint32_t SPI1CLKSEL ; ///< (0x0B8) FCLK10 clock source select
};
};
__IO uint32_t RESERVED6[1] ; ///< (0x0BC)
__IO uint32_t EFLASHREFCLKDIV ; ///< (0x0C0) EFLASH reference clock divider
__IO uint32_t FAIMREFCLKDIV ; ///< (0x0C4) FAIM reference clock divider
__IO uint32_t RESERVED7[2] ; ///< (0x0C8 - 0x0CC)
__IO uint32_t FRG0DIV ; ///< (0x0D0) Fractional generator divider value
__IO uint32_t FRG0MULT ; ///< (0x0D4) Fractional generator multiplier value
__IO uint32_t FRG0CLKSEL ; ///< (0x0D8) FRG0 clock source select
__IO uint32_t RESERVED8[1] ; ///< (0x0DC)
__IO uint32_t FRG1DIV ; ///< (0x0E0) Fractional generator divider value
__IO uint32_t FRG1MULT ; ///< (0x0E4) Fractional generator multiplier value
__IO uint32_t FRG1CLKSEL ; ///< (0x0E8) FRG1 clock source select
__IO uint32_t RESERVED9[1] ; ///< (0x0EC)
__IO uint32_t CLKOUTSEL ; ///< (0x0F0) CLKOUT clock source select
__IO uint32_t CLKOUTDIV ; ///< (0x0F4) CLKOUT clock divider
__IO uint32_t RESERVED10[1] ; ///< (0x0F8)
__IO uint32_t EXTTRACECMD ; ///< (0x0FC) External trace buffer command
__I uint32_t PIOPORCAP0 ; ///< (0x100) POR captured PIO0 status 0
__I uint32_t PIOPORCAP1 ; ///< (0x104) POR captured PIO1 status 0
__IO uint32_t RESERVED11[11] ; ///< (0x108 - 0x130)
__IO uint32_t IOCONCLKDIV6 ; ///< (0x134) Peripheral clock 6 to the IOCON block for programmable glitch filter
__IO uint32_t IOCONCLKDIV5 ; ///< (0x138) Peripheral clock 5 to the IOCON block for programmable glitch filter
__IO uint32_t IOCONCLKDIV4 ; ///< (0x13C) Peripheral clock 4 to the IOCON block for programmable glitch filter
__IO uint32_t IOCONCLKDIV3 ; ///< (0x140) Peripheral clock 3 to the IOCON block for programmable glitch filter
__IO uint32_t IOCONCLKDIV2 ; ///< (0x144) Peripheral clock 2 to the IOCON block for programmable glitch filter
__IO uint32_t IOCONCLKDIV1 ; ///< (0x148) Peripheral clock 1 to the IOCON block for programmable glitch filter
__IO uint32_t IOCONCLKDIV0 ; ///< (0x14C) Peripheral clock 0 to the IOCON block for programmable glitch filter
__IO uint32_t BODCTRL ; ///< (0x150) Brown-Out Detect
__IO uint32_t SYSTCKCAL ; ///< (0x154) System tick counter calibration
__IO uint32_t RESERVED12[6] ; ///< (0x158 - 0x16C)
__IO uint32_t IRQLATENCY ; ///< (0x170) IRQ delay. Allows trade-off between interrupt latency and determinism.
__IO uint32_t NMISRC ; ///< (0x174) NMI Source Control
union {
__IO uint32_t PINTSEL[8] ;
struct {
__IO uint32_t PINTSEL0 ; ///< (0x178) GPIO Pin Interrupt Select 0
__IO uint32_t PINTSEL1 ; ///< (0x17C) GPIO Pin Interrupt Select 1
__IO uint32_t PINTSEL2 ; ///< (0x180) GPIO Pin Interrupt Select 2
__IO uint32_t PINTSEL3 ; ///< (0x184) GPIO Pin Interrupt Select 3
__IO uint32_t PINTSEL4 ; ///< (0x188) GPIO Pin Interrupt Select 4
__IO uint32_t PINTSEL5 ; ///< (0x18C) GPIO Pin Interrupt Select 5
__IO uint32_t PINTSEL6 ; ///< (0x190) GPIO Pin Interrupt Select 6
__IO uint32_t PINTSEL7 ; ///< (0x194) GPIO Pin Interrupt Select 7
};
};
__IO uint32_t RESERVED13[27] ; ///< (0x198 - 0x200)
__IO uint32_t STARTERP0 ; ///< (0x204) Start logic 0 pin wake-up enable
__IO uint32_t RESERVED14[3] ; ///< (0x208 - 0x210)
__IO uint32_t STARTERP1 ; ///< (0x214) Start logic 1 interrupt wake-up enable
__IO uint32_t RESERVED15[6] ; ///< (0x218 - 0x22C)
__IO uint32_t PDSLEEPCFG ; ///< (0x230) Power-down states in deep-sleep mode
__IO uint32_t PDAWAKECFG ; ///< (0x234) Power-down states for wake-up from deep-sleep
__IO uint32_t PDRUNCFG ; ///< (0x238) Power configuration
__IO uint32_t RESERVED16[111] ; ///< (0x23C - 0x3F4)
__I uint32_t DEVICE_ID ; ///< (0x3F8) Device ID
} LPC_SYSCON_TypeDef;
// ---------------- IOCON ----------------
typedef struct {
__IO uint32_t PIO0_17; // 0x00
__IO uint32_t PIO0_13; // 0x04
__IO uint32_t PIO0_12; // 0x08
__IO uint32_t PIO0_5; // 0x0C
__IO uint32_t PIO0_4; // 0x10
__IO uint32_t PIO0_3; // 0x14
__IO uint32_t PIO0_2; // 0x18
__IO uint32_t PIO0_11; // 0x1C
__IO uint32_t PIO0_10; // 0x20
__IO uint32_t PIO0_16; // 0x24
__IO uint32_t PIO0_15; // 0x28
__IO uint32_t PIO0_1; // 0x2C
__IO uint32_t Reserved0; // 0x30
__IO uint32_t PIO0_9; // 0x34
__IO uint32_t PIO0_8; // 0x38
__IO uint32_t PIO0_7; // 0x3C
__IO uint32_t PIO0_6; // 0x40
__IO uint32_t PIO0_0; // 0x44
__IO uint32_t PIO0_14; // 0x48
__IO uint32_t Reserved1; // 0x4C
__IO uint32_t PIO0_28; // 0x50
__IO uint32_t PIO0_27; // 0x54
__IO uint32_t PIO0_26; // 0x58
__IO uint32_t PIO0_25; // 0x5C
__IO uint32_t PIO0_24; // 0x60
__IO uint32_t PIO0_23; // 0x64
__IO uint32_t PIO0_22; // 0x68
__IO uint32_t PIO0_21; // 0x6C
__IO uint32_t PIO0_20; // 0x70
__IO uint32_t PIO0_19; // 0x74
__IO uint32_t PIO0_18; // 0x78
__IO uint32_t PIO1_8; // 0x7C
__IO uint32_t PIO1_9; // 0x80
__IO uint32_t PIO1_12; // 0x84
__IO uint32_t PIO1_13; // 0x88
__IO uint32_t PIO0_31; // 0x8C
__IO uint32_t PIO1_0; // 0x90
__IO uint32_t PIO1_1; // 0x94
__IO uint32_t PIO1_2; // 0x98
__IO uint32_t PIO1_14; // 0x9C
__IO uint32_t PIO1_15; // 0xA0
__IO uint32_t PIO1_3; // 0xA4
__IO uint32_t PIO1_4; // 0xA8
__IO uint32_t PIO1_5; // 0xAC
__IO uint32_t PIO1_16; // 0xB0
__IO uint32_t PIO1_17; // 0xB4
__IO uint32_t PIO1_6; // 0xB8
__IO uint32_t PIO1_18; // 0xBC
__IO uint32_t PIO1_19; // 0xC0
__IO uint32_t PIO1_7; // 0xC4
__IO uint32_t PIO0_29; // 0xC8
__IO uint32_t PIO0_30; // 0xCC
__IO uint32_t PIO1_20; // 0xD0
__IO uint32_t PIO1_21; // 0xD4
__IO uint32_t PIO1_11; // 0xD8
__IO uint32_t PIO1_10; // 0xDC
} LPC_IOCON_TypeDef;
// ================================================================================
// ================ FLASHCTRL ================
// ================================================================================
typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
__I uint32_t RESERVED0[4];
__IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
__I uint32_t RESERVED1[3];
__IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
__IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
__I uint32_t RESERVED2;
__I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */
} LPC_FLASHCTRL_TypeDef;
//------------- Power Management Unit (PMU) --------------------------
typedef struct
{
__IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
__IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
__IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
__IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
__IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
__IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
} LPC_PMU_TypeDef;
//------------- Switch Matrix (SWM) --------------------------
typedef struct
{
union {
__IO uint32_t PINASSIGN[15];
struct {
__IO uint32_t PINASSIGN0; // 0x000
__IO uint32_t PINASSIGN1; // 0x004
__IO uint32_t PINASSIGN2; // 0x008
__IO uint32_t PINASSIGN3; // 0x00C
__IO uint32_t PINASSIGN4; // 0x010
__IO uint32_t PINASSIGN5; // 0x014
__IO uint32_t PINASSIGN6; // 0x018
__IO uint32_t PINASSIGN7; // 0x01C
__IO uint32_t PINASSIGN8; // 0x020
__IO uint32_t PINASSIGN9; // 0x024
__IO uint32_t PINASSIGN10; // 0x028
__IO uint32_t PINASSIGN11; // 0x02C
__IO uint32_t PINASSIGN12; // 0x030
__IO uint32_t PINASSIGN13; // 0x034
__IO uint32_t PINASSIGN14; // 0x038
};
};
__I uint32_t Reserved0[97]; // 0x03C - 0x1BC
__IO uint32_t PINENABLE0; // 0x1C0
__IO uint32_t PINENABLE1; // 0x1C4
} LPC_SWM_TypeDef;
// ------------------------------------------------------------------------------------------------
// ----- General Purpose I/O (GPIO) -----
// ------------------------------------------------------------------------------------------------
typedef struct {
__IO uint8_t B0[32]; // 0x00 - 0x1F Byte pin registers P0.0 - P0.31
__IO uint8_t B1[32]; // 0x20 - 0x3F Byte pin registers P1.0 - P1.31
__I uint8_t Reserved0[4032]; // 0x40 - 0xFFF
__IO uint32_t W0[32]; // 0x1000 - 0x107C Word pin registers P0.0 - P0.31
__IO uint32_t W1[32]; // 0x1080 - 0x10FC Word pin registers P1.0 - P1.31
__I uint32_t Reserved1[960]; // 0x1100 - 0x1FFC (960d = 0x3c0)
union {
__IO uint32_t DIR[2]; // 0x2000 - 0x2004
struct {
__IO uint32_t DIR0; // 0x2000
__IO uint32_t DIR1; // 0x2004
};
};
__I uint32_t Reserved2[30]; // 0x2008 - 0x207C
union {
__IO uint32_t MASK[2]; // 0x2080 - 0x2084
struct {
__IO uint32_t MASK0; // 0x2080
__IO uint32_t MASK1; // 0x2084
};
};
__I uint32_t Reserved3[30]; // 0x2088 - 0x20FC
union {
__IO uint32_t PIN[2]; // 0x2100 - 0x2104
struct {
__IO uint32_t PIN0; // 0x2100
__IO uint32_t PIN1; // 0x2104
};
};
__I uint32_t Reserved4[30]; // 0x2108 - 0x217C
union {
__IO uint32_t MPIN[2]; // 0x22180 - 0x2184
struct {
__IO uint32_t MPIN0; // 0x2180
__IO uint32_t MPIN1; // 0x2184
};
};
__I uint32_t Reserved5[30]; // 0x2188 - 0x21FC
union {
__IO uint32_t SET[2]; // 0x2200 -0x2204
struct {
__IO uint32_t SET0; // 0x2200
__IO uint32_t SET1; // 0x2204
};
};
__I uint32_t Reserved6[30]; // 0x2208 - 0x227C
union {
__O uint32_t CLR[2]; // 0x2280 - 0x2284
struct {
__O uint32_t CLR0; // 0x2280
__O uint32_t CLR1; // 0x2284
};
};
__I uint32_t Reserved7[30]; // 0x2288 - 0x22FC
union {
__O uint32_t NOT[2]; // 0x2300 - 0x2304
struct {
__O uint32_t NOT0; // 0x2300
__O uint32_t NOT1; // 0x2304
};
};
__I uint32_t Reserved8[30]; // 0x2308 - 0x237C
union {
__O uint32_t DIRSET[2]; // 0x2380 - 0x2384
struct {
__O uint32_t DIRSET0; // 0x2380
__O uint32_t DIRSET1; // 0x2384
};
};
__I uint32_t Reserved9[30]; // 0x2388 - 0x23FC
union {
__O uint32_t DIRCLR[2]; // 0x2400 - 0x2404
struct {
__O uint32_t DIRCLR0; // 0x2400
__O uint32_t DIRCLR1; // 0x2404
};
};
__I uint32_t Reserved10[30]; // 0x2408 - 0x247C
union {
__O uint32_t DIRNOT[2]; // 0x2480 - 0x2484
struct {
__O uint32_t DIRNOT0; // 0x2480
__O uint32_t DIRNOT1; // 0x2484
};
};
} LPC_GPIO_PORT_TypeDef;
// ------------------------------------------------------------------------------------------------
// ----- Pin Interrupts and Pattern Match (PIN_INT) -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
__IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
__IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
__IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
__IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
__IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
} LPC_PIN_INT_TypeDef;
//------------- CRC Engine (CRC) -----------------------------------------
typedef struct
{
__IO uint32_t MODE;
__IO uint32_t SEED;
union {
__I uint32_t SUM;
__O uint32_t WR_DATA;
};
} LPC_CRC_TypeDef;
//------------- Comparator (CMP) --------------------------------------------------
typedef struct { /*!< (@ 0x40024000) CMP Structure */
__IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
__IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
} LPC_CMP_TypeDef;
//------------- Self Wakeup Timer (WKT) --------------------------------------------------
typedef struct { /*!< (@ 0x40028000) WKT Structure */
__IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
uint32_t Reserved[2];
__IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
} LPC_WKT_TypeDef;
//------------- Multi-Rate Timer(MRT) --------------------------------------------------
typedef struct {
__IO uint32_t INTVAL;
__IO uint32_t TIMER;
__IO uint32_t CTRL;
__IO uint32_t STAT;
} MRT_Channel_cfg_Type;
typedef struct {
MRT_Channel_cfg_Type Channel[4];
uint32_t Reserved0[45]; // Address offsets = 0x40 - 0xF0
__IO uint32_t IDLE_CH;
__IO uint32_t IRQ_FLAG;
} LPC_MRT_TypeDef;
//------------- Universal Asynchronous Receiver Transmitter (USART) -----------
typedef struct
{
__IO uint32_t CFG;
__IO uint32_t CTL;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR;
__I uint32_t RXDAT;
__I uint32_t RXDATSTAT;
__IO uint32_t TXDAT;
__IO uint32_t BRG;
__I uint32_t INTSTAT;
__IO uint32_t OSR;
__IO uint32_t ADDR;
} LPC_USART_TypeDef;
//------------- SPI -----------------------
typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t DLY;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR; /* 0x10 */
__I uint32_t RXDAT;
__IO uint32_t TXDATCTL;
__IO uint32_t TXDAT;
__IO uint32_t TXCTL; /* 0x20 */
__IO uint32_t DIV;
__I uint32_t INTSTAT;
} LPC_SPI_TypeDef;
//------------- Inter-Integrated Circuit (I2C) -------------------------------
typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR;
__IO uint32_t TIMEOUT; /* 0x10 */
union {
__IO uint32_t CLKDIV;
__IO uint32_t DIV;
};
__IO uint32_t INTSTAT;
uint32_t Reserved0[1];
__IO uint32_t MSTCTL; /* 0x20 */
__IO uint32_t MSTTIME;
__IO uint32_t MSTDAT;
uint32_t Reserved1[5];
__IO uint32_t SLVCTL; /* 0x40 */
__IO uint32_t SLVDAT;
__IO uint32_t SLVADR0;
__IO uint32_t SLVADR1;
__IO uint32_t SLVADR2; /* 0x50 */
__IO uint32_t SLVADR3;
__IO uint32_t SLVQUAL0;
uint32_t Reserved2[9];
__I uint32_t MONRXDAT; /* 0x80 */
} LPC_I2C_TypeDef;
// ================================================================================
// == SCT
// ================================================================================
#define CONFIG_SCT_nEV (8) // Number of events
#define CONFIG_SCT_nRG (8) // Number of match/compare registers
#define CONFIG_SCT_nOU (7) // Number of outputs
typedef struct {
__IO uint32_t CONFIG; // 0x0
union {
__IO uint32_t CTRL; // 0x4
struct {
__IO uint16_t CTRL_L;
__IO uint16_t CTRL_H;
};
};
union {
__IO uint32_t LIMIT; // 0x8
struct {
__IO uint16_t LIMIT_L;
__IO uint16_t LIMIT_H;
};
};
union {
__IO uint32_t HALT; // 0xc
struct {
__IO uint16_t HALT_L;
__IO uint16_t HALT_H;
};
};
union {
__IO uint32_t STOP; // 0x10
struct {
__IO uint16_t STOP_L;
__IO uint16_t STOP_H;
};
};
union {
__IO uint32_t START; // 0x14
struct {
__IO uint16_t START_L;
__IO uint16_t START_H;
};
};
uint32_t RESERVED1[10];
union {
__IO uint32_t COUNT; // 0x40
struct {
__IO uint16_t COUNT_L;
__IO uint16_t COUNT_H;
};
};
union {
__IO uint32_t STATE; // 0x44
struct {
__IO uint16_t STATE_L;
__IO uint16_t STATE_H;
};
};
__I uint32_t INPUT; // 0x48
union {
__IO uint32_t REGMODE; // 0x4c
struct {
__IO uint16_t REGMODE_L;
__IO uint16_t REGMODE_H;
};
};
__IO uint32_t OUTPUT; // 0x50
__IO uint32_t OUTPUTDIRCTRL; // 0x54
__IO uint32_t RES; // 0x58
__IO uint32_t DMAREQ0; // 0x5c
__IO uint32_t DMAREQ1; // 0x60
uint32_t RESERVED2[35]; // 0x64 - 0xec
__IO uint32_t EVEN; // 0xf0
__IO uint32_t EVFLAG; // 0xf4
__IO uint32_t CONEN; // 0xf8
__IO uint32_t CONFLAG; // 0xfc
union { // Match / Capture 0x100 - 0x13c
__IO union {
uint32_t U; // MATCH[i].U Unified 32-bit register
struct {
uint16_t L; // MATCH[i].L Access to L value
uint16_t H; // MATCH[i].H Access to H value
};
} MATCH[CONFIG_SCT_nRG];
__I union {
uint32_t U; // CAP[i].U Unified 32-bit register
struct {
uint16_t L; // CAP[i].L Access to L value
uint16_t H; // CAP[i].H Access to H value
};
} CAP[CONFIG_SCT_nRG];
};
uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; // ...-0x17C reserved
union {
__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; // 0x180-... Match Value L counter
__I uint16_t CAP_L[CONFIG_SCT_nRG]; // 0x180-... Capture Value L counter
};
uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; // ...-0x1BE reserved
union {
__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; // 0x1C0-... Match Value H counter
__I uint16_t CAP_H[CONFIG_SCT_nRG]; // 0x1C0-... Capture Value H counter
};
uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; // ...-0x1FE reserved
union {
__IO union { // 0x200-... Match Reload / Capture Control value
uint32_t U; // MATCHREL[i].U Unified 32-bit register
struct {
uint16_t L; // MATCHREL[i].L Access to L value
uint16_t H; // MATCHREL[i].H Access to H value
};
} MATCHREL[CONFIG_SCT_nRG];
__IO union {
uint32_t U; // CAPCTRL[i].U Unified 32-bit register
struct {
uint16_t L; // CAPCTRL[i].L Access to L value
uint16_t H; // SCTCAPCTRL[i].H Access to H value
};
} CAPCTRL[CONFIG_SCT_nRG];
};
uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; // ...-0x27C reserved
union {
__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; // 0x280-... Match Reload value L counter
__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; // 0x280-... Capture Control value L counter
};
uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; // ...-0x2BE reserved
union {
__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; // 0x2C0-... Match Reload value H counter
__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; // 0x2C0-... Capture Control value H counter
};
uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; // ...-0x2FE reserved
__IO struct { // 0x300-0x3FC EVENT[i].STATE / EVENT[i].CTRL
uint32_t STATE;
uint32_t CTRL;
} EVENT[CONFIG_SCT_nEV];
uint32_t RESERVED9[128 - (2 * CONFIG_SCT_nEV)]; // ...-0x4FC reserved
__IO struct { // 0x500-0x57C OUT[n].SET / OUT[n].CLR
uint32_t SET; // Output n Set Register
uint32_t CLR; // Output n Clear Register
} OUT[CONFIG_SCT_nOU];
uint32_t RESERVED10[((0x300 / 4) - 1) - (2 * CONFIG_SCT_nOU)]; // ...-0x7F8 reserved
__I uint32_t MODULECONTENT; // 0x7FC Module Content
} LPC_SCT_TypeDef;
//------------------- Standard Counter/Timer (CTIMER) ---------------------
typedef struct {
__IO uint32_t IR; // 0x00
__IO uint32_t TCR; // 0x04
__IO uint32_t TC; // 0x08
__IO uint32_t PR; // 0x0C
__IO uint32_t PC; // 0x10
__IO uint32_t MCR; // 0x14
__IO uint32_t MR[4]; // 0x18 - 0x24
__IO uint32_t CCR; // 0x28
__IO uint32_t CR[4]; // 0x2C - 0x38
__IO uint32_t EMR; // 0x3C
__I uint32_t RESERVED0[12]; // 0x40 - 0x6C
__IO uint32_t CTCR; // 0x70
__IO uint32_t PWMC; // 0x74
} LPC_TIMER_TypeDef;
//------------- Widowed Watchdog Timer (WWDT) -----------------------------------------
typedef struct
{
__IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
__IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
__O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
__I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
__IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
__IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
} LPC_WWDT_TypeDef;
//-------------------------------------------------------------------------
// Input multiplexing and DMA trigger multiplexing (INPUT MUX, DMA TRIGMUX)
//-------------------------------------------------------------------------
typedef struct {
__IO uint32_t DMA_INMUX_INMUX0; // 0x0
__IO uint32_t DMA_INMUX_INMUX1; // 0x4
__I uint32_t Preserved[6]; // 0x8 - 0x1C
__IO uint32_t SCT0_INMUX0; // 0x20
__IO uint32_t SCT0_INMUX1; // 0x24
__IO uint32_t SCT0_INMUX2; // 0x28
__IO uint32_t SCT0_INMUX3; // 0x2C
__I uint32_t Severed[4]; // 0x30 - 0x3C
__IO uint32_t DMA_ITRIG_INMUX0; // 0x40
__IO uint32_t DMA_ITRIG_INMUX1; // 0x44
__IO uint32_t DMA_ITRIG_INMUX2; // 0x48
__IO uint32_t DMA_ITRIG_INMUX3; // 0x4C
__IO uint32_t DMA_ITRIG_INMUX4; // 0x50
__IO uint32_t DMA_ITRIG_INMUX5; // 0x54
__IO uint32_t DMA_ITRIG_INMUX6; // 0x58
__IO uint32_t DMA_ITRIG_INMUX7; // 0x5C
__IO uint32_t DMA_ITRIG_INMUX8; // 0x60
__IO uint32_t DMA_ITRIG_INMUX9; // 0x64
__IO uint32_t DMA_ITRIG_INMUX10; // 0x68
__IO uint32_t DMA_ITRIG_INMUX11; // 0x6C
__IO uint32_t DMA_ITRIG_INMUX12; // 0x70
__IO uint32_t DMA_ITRIG_INMUX13; // 0x74
__IO uint32_t DMA_ITRIG_INMUX14; // 0x78
__IO uint32_t DMA_ITRIG_INMUX15; // 0x7C
__IO uint32_t DMA_ITRIG_INMUX16; // 0x80
__IO uint32_t DMA_ITRIG_INMUX17; // 0x84
__IO uint32_t DMA_ITRIG_INMUX18; // 0x88
__IO uint32_t DMA_ITRIG_INMUX19; // 0x8C
__IO uint32_t DMA_ITRIG_INMUX20; // 0x90
__IO uint32_t DMA_ITRIG_INMUX21; // 0x94
__IO uint32_t DMA_ITRIG_INMUX22; // 0x98
__IO uint32_t DMA_ITRIG_INMUX23; // 0x9C
__IO uint32_t DMA_ITRIG_INMUX24; // 0xA0
} LPC_INMUX_TRIGMUX_TypeDef;
//------------- ADC -----------------------------------------
typedef struct {
__IO uint32_t CTRL; // 0x0
uint32_t RESERVED0; // 0x4
__IO uint32_t SEQA_CTRL; // 0x8
__IO uint32_t SEQB_CTRL; // 0xC
__IO uint32_t SEQA_GDAT; // 0x10
__IO uint32_t SEQB_GDAT; // 0x14
uint32_t RESERVED1[2]; // 0x18 - 0x1C
__IO uint32_t DAT[12]; // 0x20 - 0x4C
__IO uint32_t THR0_LOW; // 0x50
__IO uint32_t THR1_LOW; // 0x54
__IO uint32_t THR0_HIGH; // 0x58
__IO uint32_t THR1_HIGH; // 0x5C
__IO uint32_t CHAN_THRSEL; // 0x60
__IO uint32_t INTEN; // 0x64
__IO uint32_t FLAGS; // 0x68
__IO uint32_t TRM; // 0x6C
} LPC_ADC_TypeDef;
//------------- DMA -----------------------------------------
#define NUM_DMA_CHANNELS 25
typedef struct {
__IO uint32_t CFG;
__I uint32_t CTLSTAT;
__IO uint32_t XFERCFG;
__I uint32_t RESERVED;
} LPC_DMA_CHANNEL_T;
typedef struct {
__IO uint32_t CTRL; // 0x0
__I uint32_t INTSTAT; // 0x4
__IO uint32_t SRAMBASE; // 0x8
__I uint32_t Reserved0[5]; // 0x10 - 0x1C
__IO uint32_t ENABLESET0; // 0x20
__I uint32_t Reserved1; // 0x24
__O uint32_t ENABLECLR0; // 0x28
__I uint32_t Reserved2; // 0x2C
__I uint32_t ACTIVE0; // 0x30
__I uint32_t Reserved3; // 0x34
__I uint32_t BUSY0; // 0x38
__I uint32_t Reserved4; // 0x3C
__IO uint32_t ERRINT0; // 0x40
__I uint32_t Reserved5; // 0x44
__IO uint32_t INTENSET0; // 0x48
__I uint32_t Reserved6; // 0x4C
__O uint32_t INTENCLR0; // 0x50
__I uint32_t Reserved7; // 0x54
__IO uint32_t INTA0; // 0x58
__I uint32_t Reserved8; // 0x5C
__IO uint32_t INTB0; // 0x60
__I uint32_t Reserved9; // 0x64
__O uint32_t SETVALID0; // 0x68
__I uint32_t Reserved10; // 0x6C
__O uint32_t SETTRIG0; // 0x70
__I uint32_t Reserved11; // 0x74
__O uint32_t ABORT0; // 0x78
__I uint32_t Absolutely_Nothing[225]; // 0x7C - 0x3FC
LPC_DMA_CHANNEL_T CHANNEL[NUM_DMA_CHANNELS]; // 0x400 - 0xThe_End
} LPC_DMA_TypeDef;
//------------- DAC ----------------
typedef struct {
__IO uint32_t CR; // 0x00
__IO uint32_t CTRL; // 0x04
__IO uint32_t CNTVAL; // 0x08
} LPC_DAC_TypeDef;
//------------------------ FAIM Controller -------------------------
typedef struct {
__IO uint32_t EECMD; // 0x00
__I uint32_t Reserved0; // 0x04
__IO uint32_t EERWSTATE; // 0x08
__IO uint32_t EEPAUTOPROG; // 0x0C
__IO uint32_t EEWSTATE; // 0x10
__IO uint32_t EECLKDIV; // 0x14
__IO uint32_t EEPWRDWN; // 0x18
__IO uint32_t EEMSSTART; // 0x20
__IO uint32_t EEMSSTOP; // 0x24
__I uint32_t EEMSDATASIG; // 0x28
__I uint32_t EEMSPARSIG; // 0x2C
__IO uint32_t EEFEATURE; // 0x30
__I uint32_t EESTATUS; // 0x34
__IO uint32_t ECCRSTERRCNT; // 0x38
__I uint32_t ECCERRCNT; // 0x3C
__I uint32_t Reserved1[5]; // 0x40 - 0x50
__IO uint32_t EECLKDIV1; // 0x54
__IO uint32_t EECLKDIV2; // 0x58
__I uint32_t Reserved2[5]; // 0x5C - 0x6C
__O uint32_t EEADDR; // 0x70
__I uint32_t Reserved3[3]; // 0x74 - 0x7C
__O uint32_t EEWDATA; // 0x80
__I uint32_t Reserved4; // 0x84
__I uint32_t EERDATA; // 0x88
} LPC_FAIMCTRL_TypeDef;
/* ARM 24.04.2017 */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
// Base addresses
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_ROM_BASE (0x1FFF0000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_AHB_BASE (0x50000000UL)
// APB0 peripherals
#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
#define LPC_FAIMCTRL_BASE (LPC_APB0_BASE + 0x10000)
#define LPC_DAC0_BASE (LPC_APB0_BASE + 0x14000)
#define LPC_DAC1_BASE (LPC_APB0_BASE + 0x18000)
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
// (LPC_APB0_BASE + 0x28000)
#define LPC_INMUX_TRIGMUX_BASE (LPC_APB0_BASE + 0x2C000)
#define LPC_I2C2_BASE (LPC_APB0_BASE + 0x30000)
#define LPC_I2C3_BASE (LPC_APB0_BASE + 0x34000)
#define LPC_CTIMER0_BASE (LPC_APB0_BASE + 0x38000)
// (LPC_APB0_BASE + 0x38000)
#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x50000)
#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x54000)
#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
// (LPC_APB0_BASE + 0x60000)
#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
#define LPC_USART3_BASE (LPC_APB0_BASE + 0x70000)
#define LPC_USART4_BASE (LPC_APB0_BASE + 0x74000)
// AHB peripherals
#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
#define LPC_DMA_BASE (LPC_AHB_BASE + 0x08000)
#define LPC_MTB_SFR_BASE (LPC_AHB_BASE + 0x0C000)
#define LPC_FAIM_BASE (LPC_AHB_BASE + 0x10000)
#define LPC_GPIO_PORT_BASE (0xA0000000)
#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
/******************************************************************************/
/* Peripheral declarations */
/******************************************************************************/
#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
#define LPC_FAIMCTRL ((LPC_FAIMCTRL_TypeDef *) LPC_FAIMCTRL_BASE)
#define LPC_DAC0 ((LPC_DAC_TypeDef *) LPC_DAC0_BASE )
#define LPC_DAC1 ((LPC_DAC_TypeDef *) LPC_DAC1_BASE )
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
#define LPC_INMUX_TRIGMUX ((LPC_INMUX_TRIGMUX_TypeDef *) LPC_INMUX_TRIGMUX_BASE)
#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
#define LPC_I2C3 ((LPC_I2C_TypeDef *) LPC_I2C3_BASE )
#define LPC_CTIMER0 ((LPC_TIMER_TypeDef *) LPC_CTIMER0_BASE )
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
#define LPC_USART3 ((LPC_USART_TypeDef *) LPC_USART3_BASE )
#define LPC_USART4 ((LPC_USART_TypeDef *) LPC_USART4_BASE )
#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
#define LPC_SCT0 ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
#define LPC_DMA ((LPC_DMA_TypeDef *) LPC_DMA_BASE )
#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
///////////////////////////////////////////////////////////////////////////////
// Other chip-specific macro definitions (a.k.a. the chip.h section)
///////////////////////////////////////////////////////////////////////////////
// ACMP_I-to-IOCON mapping
#define ACMP_I1_PORT PIO0_0
#define ACMP_I2_PORT PIO0_1
#define ACMP_I3_PORT PIO0_14
#define ACMP_I4_PORT PIO0_23
#define ACMP_I5_PORT PIO0_30
#ifdef __cplusplus
}
#endif
#endif /* __LPC84x_H__ */
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/MM32F103xCxE_o.h
|
<gh_stars>1-10
/**
******************************************************************************
* @file MM32F103xCxE_o.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for MM32F103xCxE_o High Density, Medium
* Density and Low Density devices.
* @version V1.0.0
* @date 2018/09/17
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup MM32F103xCxE_o
* @{
*/
#ifndef __MM32F103xCxE_o_H
#define __MM32F103xCxE_o_H
/** @addtogroup Library_configuration_section
* @{
*/
#if !defined USE_STDPERIPH_DRIVER
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_STDPERIPH_DRIVER*/
#endif
/**
* @brief In the following line adjust the value of External High Speed oscillator (HSE)
used in your application
*/
#define HSE_Value ((uint32_t)8000000L) /*!< Value of the External oscillator in Hz*/
#define HSE_VALUE HSE_Value
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value
*/
#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
#define HSE_STARTUP_TIMEOUT HSEStartUp_TimeOut
#define HSI_Value_Pll_ON ((uint32_t)48000000/4) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE_PLL_ON HSI_Value_Pll_ON
#define HSI_Value_Pll_OFF ((uint32_t)48000000/6) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE_PLL_OFF HSI_Value_Pll_OFF
/*!< [31:16] MM32F103xCxE_o Standard Peripheral Library main version */
#define __MM32F103xCxE_o_STDPERIPH_VERSION_MAIN (0x01)
/*!< [15:8] MM32F103xCxE_o Standard Peripheral Library sub1 version */
#define __MM32F103xCxE_o_STDPERIPH_VERSION_SUB1 (0x00)
/*!< [7:0] MM32F103xCxE_o Standard Peripheral Library sub2 version */
#define __MM32F103xCxE_o_STDPERIPH_VERSION_SUB2 (0x00)
/*!< MM32F103xCxE_o Standard Peripheral Library version number */
#define __MM32F103xCxE_o_STDPERIPH_VERSION ((__MM32F103xCxE_o_STDPERIPH_VERSION_MAIN << 16)\
| (__MM32F103xCxE_o_STDPERIPH_VERSION_SUB1 << 8)\
| __MM32F103xCxE_o_STDPERIPH_VERSION_SUB2)
/**
* @}
*/
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
#define __MPU_PRESENT 0 /*!< MM32F103xCxE_o does not provide a MPU present or not */
#define __NVIC_PRIO_BITS 4 /*!< MM32F103xCxE_o uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/*!< Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** MM32F103xCxE_o CM3 specific Interrupt Numbers *********************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMPER_IRQn = 2, /*!< Tamper Interrupt */
RTC_IRQn = 3, /*!< RTC global Interrupt */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_CRS_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_IRQn = 18, /*!< ADC1 et ADC2 global Interrupt */
CAN1_RX_IRQn = 21, /*!< CAN1 RX1 Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C2_IRQn = 33, /*!< I2C2 Event Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
UART1_IRQn = 37, /*!< UART1 global Interrupt */
UART2_IRQn = 38, /*!< UART2 global Interrupt */
UART3_IRQn = 39, /*!< UART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USB_WKUP_IRQn = 42, /*!< USB WakeUp from suspend through EXTI Line Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
SDIO_IRQn = 49, /* SDIO */
TIM5_IRQn = 50, /* TIM5 */
SPI3_IRQn = 51, /* SPI3 */
UART4_IRQn = 52, /* UART4 */
UART5_IRQn = 53, /* UART5 */
TIM6_IRQn = 54, /* TIM6 */
TIM7_IRQn = 55, /* TIM7 */
DMA2_Channel1_IRQn = 56, /* DMA2 Channel 1 */
DMA2_Channel2_IRQn = 57, /* DMA2 Channel 2 */
DMA2_Channel3_IRQn = 58, /* DMA2 Channel 3 */
DMA2_Channel4_IRQn = 59, /* DMA2 Channel 4 */
DMA2_Channel5_IRQn = 60, /* DMA2 Channel 5 */
ETHERNET_MAC_IRQn = 61, /* Ethernet */
COMP1_2_IRQn = 64, /* COMP1,COMP2 */
USB_OTG_FS_IRQn = 67, /* USB_FS */
UART6_IRQn = 71, /* UART6 */
AES_IRQn = 79, /* AES */
TRNG_IRQn = 80, /* TRNG */
UART7_IRQn = 82, /* UART7 */
UART8_IRQn = 83, /* UART8 */
} IRQn_Type;
/**
* @}
*/
#include <core_cm3.h>
#include <stdint.h>
/** @addtogroup Exported_types
* @{
*/
/*!< MM32F103xCxE_o Standard Peripheral Library old types (maintained for legacy prupose) */
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef const int32_t sc32; /*!< Read Only */
typedef const int16_t sc16; /*!< Read Only */
typedef const int8_t sc8; /*!< Read Only */
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32; /*!< Read Only */
typedef __I int16_t vsc16; /*!< Read Only */
typedef __I int8_t vsc8; /*!< Read Only */
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef const uint32_t uc32; /*!< Read Only */
typedef const uint16_t uc16; /*!< Read Only */
typedef const uint8_t uc8; /*!< Read Only */
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __I uint32_t vuc32; /*!< Read Only */
typedef __I uint16_t vuc16; /*!< Read Only */
typedef __I uint8_t vuc8; /*!< Read Only */
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define SETnBIT(VALUE,BITs) ((VALUE) |= (1<<BITs))
#define RSTnBIT(VALUE,BITs) ((VALUE) &= ~(1<<BITs))
/**
* @}
*/
typedef struct
{
__IO uint32_t SHCSR; //0XE000DE24
__IO uint8_t MFSR; //0XE000DE28
__IO uint8_t BFSR; //0XE000DE29
__IO uint16_t UFSR; //0XE000DE2A
__IO uint32_t HFSR; //0XE000DE2C
__IO uint32_t DFSR; //0XE000DE30
__IO uint32_t MMAR; //0XE000DE34
__IO uint32_t BFAR; //0XE000DE38
} HARD_FAULT_TypeDef;
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ADDATA;
__IO uint32_t ADCFG;
__IO uint32_t ADCR;
__IO uint32_t ADCHS;
__IO uint32_t ADCMPR;
__IO uint32_t ADSTA;
__IO uint32_t ADDR0;
__IO uint32_t ADDR1;
__IO uint32_t ADDR2;
__IO uint32_t ADDR3;
__IO uint32_t ADDR4;
__IO uint32_t ADDR5;
__IO uint32_t ADDR6;
__IO uint32_t ADDR7;
__IO uint32_t ADDR8;
// __IO uint32_t ADDR9;
// __IO uint32_t ADDR10;
// __IO uint32_t ADDR11;
// __IO uint32_t ADDR12;
// __IO uint32_t ADDR13;
// __IO uint32_t ADDR14;
// __IO uint32_t ADDR15;
} ADC_TypeDef;
/**
* @brief Backup Registers
*/
typedef struct
{
__IO uint32_t RESERVED0;//0x24
__IO uint16_t DR1;//0x28
__IO uint16_t RESERVED1;
__IO uint16_t DR2;
__IO uint16_t RESERVED2;
__IO uint16_t DR3;
__IO uint16_t RESERVED3;
__IO uint16_t DR4;
__IO uint16_t RESERVED4;
__IO uint16_t DR5;
__IO uint16_t RESERVED5;
__IO uint16_t DR6;
__IO uint16_t RESERVED6;
__IO uint16_t DR7;
__IO uint16_t RESERVED7;
__IO uint16_t DR8;
__IO uint16_t RESERVED8;
__IO uint16_t DR9;
__IO uint16_t RESERVED9;
__IO uint16_t DR10;
__IO uint16_t RESERVED10;
__IO uint16_t RTCCR;
__IO uint16_t RESERVED11;
__IO uint16_t CR;
__IO uint16_t RESERVED12;
__IO uint16_t CSR;
__IO uint16_t RESERVED13;
__IO uint16_t DR11;
__IO uint16_t RESERVED14;
__IO uint16_t DR12;
__IO uint16_t RESERVED15;
__IO uint16_t DR13;
__IO uint16_t RESERVED16;
__IO uint16_t DR14;
__IO uint16_t RESERVED17;
__IO uint16_t DR15;
__IO uint16_t RESERVED18;
__IO uint16_t DR16;
__IO uint16_t RESERVED19;
__IO uint16_t DR17;
__IO uint16_t RESERVED20;
__IO uint16_t DR18;
__IO uint16_t RESERVED21;
__IO uint16_t DR19;
__IO uint16_t RESERVED22;
__IO uint16_t DR20;
__IO uint16_t RESERVED23;
} BKP_TypeDef;
/**
* @brief CAN basic
*/
typedef struct
{
__IO uint32_t CR; //0x00
__IO uint32_t CMR; //0x04
__IO uint32_t SR; //0x08
__IO uint32_t IR; //0x0c
__IO uint32_t ACR; //0x10
__IO uint32_t AMR; //0x14
__IO uint32_t BTR0; //0x18
__IO uint32_t BTR1; //0x1C
__IO uint32_t RESERVED0; //0x20
__IO uint32_t RESERVED1; //0x24
__IO uint32_t TXID0; //0x28
__IO uint32_t TXID1; //0x2c
__IO uint32_t TXDR0; //0x30
__IO uint32_t TXDR1; //0x34
__IO uint32_t TXDR2; //0x38
__IO uint32_t TXDR3; //0x3c
__IO uint32_t TXDR4; //0x40
__IO uint32_t TXDR5; //0x44
__IO uint32_t TXDR6; //0x48
__IO uint32_t TXDR7; //0x4c
__IO uint32_t RXID0; //0x50
__IO uint32_t RXID1; //0x54
__IO uint32_t RXDR0; //0x58
__IO uint32_t RXDR1; //0x5C
__IO uint32_t RXDR2; //0x60
__IO uint32_t RXDR3; //0x64
__IO uint32_t RXDR4; //0x68
__IO uint32_t RXDR5; //0x6c
__IO uint32_t RXDR6; //0x70
__IO uint32_t RXDR7; //0x74
__IO uint32_t RESERVED2; //0x78
__IO uint32_t CDR; //0x7c
} CAN_TypeDef;
/**
* @brief CAN Peli
*/
#define ACR0 FF
#define ACR1 ID0
#define ACR2 ID1
#define ACR3 DATA0
#define AMR0 DATA1
#define AMR1 DATA2
#define AMR2 DATA3
#define AMR3 DATA4
typedef struct
{
__IO uint32_t MOD; //0x00
__IO uint32_t CMR; //0x04
__IO uint32_t SR; //0x08
__IO uint32_t IR; //0x0c
__IO uint32_t IER; //0x10
__IO uint32_t RESERVED0; //0x14
__IO uint32_t BTR0; //0x18
__IO uint32_t BTR1; //0x1C
__IO uint32_t RESERVED1; //0x20
__IO uint32_t RESERVED2; //0x24
__IO uint32_t RESERVED3; //0x28
__IO uint32_t ALC; //0x2c
__IO uint32_t ECC; //0x30
__IO uint32_t EWLR; //0x34
__IO uint32_t RXERR; //0x38
__IO uint32_t TXERR; //0x3c
__IO uint32_t FF; //0x40
__IO uint32_t ID0; //0x44
__IO uint32_t ID1; //0x48
__IO uint32_t DATA0; //0x4c
__IO uint32_t DATA1; //0x50
__IO uint32_t DATA2; //0x54
__IO uint32_t DATA3; //0x58
__IO uint32_t DATA4; //0x5C
__IO uint32_t DATA5; //0x60
__IO uint32_t DATA6; //0x64
__IO uint32_t DATA7; //0x68
__IO uint32_t DATA8; //0x6c
__IO uint32_t DATA9; //0x70
__IO uint32_t RMC;
__IO uint32_t RBSA;
__IO uint32_t CDR; //0x7c
} CAN_Peli_TypeDef;
/**
* @}
*/
typedef struct
{
__IO uint32_t CCR;
__IO uint32_t SR;
__IO uint32_t IRQMASKR;
__IO uint32_t IRQSTATR;
__IO uint32_t RESERVED0;
__IO uint32_t CSHR;
__IO uint32_t CSMR;
} CACHE_TypeDef;
/**
* @brief COMP
*/
typedef struct
{
__IO uint32_t COMP_CSR1;
__IO uint32_t COMP_CSR2;
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR;
__IO uint16_t IDR;
__IO uint16_t RESERVED0;
__IO uint32_t CR;
} CRC_TypeDef;
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CFGR;
__IO uint32_t ISR;
__IO uint32_t ICR;
} CRS_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE;
__IO uint32_t CR;
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR;
__IO uint32_t IFCR;
} DMA_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR;
__IO uint32_t EMR;
__IO uint32_t RTSR;
__IO uint32_t FTSR;
__IO uint32_t SWIER;
__IO uint32_t PR;
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR;
__IO uint32_t KEYR;
__IO uint32_t OPTKEYR;
__IO uint32_t SR;
__IO uint32_t CR;
__IO uint32_t AR;
__IO uint32_t RESERVED;
__IO uint32_t OBR;
__IO uint32_t WRP0R;
__IO uint32_t WRP1R;
__IO uint32_t WRP2R;
__IO uint32_t WRP3R;
__IO uint32_t RESERVED0;
__IO uint32_t RESERVED1;
__IO uint32_t RESERVED2;
__IO uint32_t RESERVED3;
__IO uint32_t SECUKEY0R;
__IO uint32_t SECUKEY1R;
// __IO uint32_t RESERVED4;
// __IO uint32_t RESERVED5;
// __IO uint32_t EEPKEYR;
} FLASH_TypeDef;
/**
* @brief Option Bytes Registers
*/
typedef struct
{
__IO uint16_t RDP;
__IO uint16_t USER;
__IO uint16_t Data0;
__IO uint16_t Data1;
__IO uint16_t WRP0;
__IO uint16_t WRP1;
__IO uint16_t WRP2;
__IO uint16_t WRP3;
} OB_TypeDef;
/**
* @brief General Purpose IO
*/
typedef struct
{
__IO uint32_t CRL;
__IO uint32_t CRH;
__IO uint32_t IDR;
__IO uint32_t ODR;
__IO uint32_t BSRR;
__IO uint32_t BRR;
__IO uint32_t LCKR;
__IO uint32_t RESERVED0;
__IO uint32_t AFRL;
__IO uint32_t AFRH;
} GPIO_TypeDef;
/**
* @brief SysTem Configuration
*/
typedef struct
{
__IO uint32_t CFGR; /*!< SYSCFG configuration register , Address offset: 0x00 */
__IO uint32_t RESERVED0;
__IO uint32_t EXTICR[4];
} SYSCFG_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint16_t IC_CON;
__IO uint16_t RESERVED0;
__IO uint16_t IC_TAR;
__IO uint16_t RESERVED1;
__IO uint16_t IC_SAR;
__IO uint16_t RESERVED2;
// __IO uint16_t IC_HS_MADDR;
__IO uint32_t RESERVED3;
__IO uint16_t IC_DATA_CMD;
__IO uint16_t RESERVED4;
__IO uint16_t IC_SS_SCL_HCNT;
__IO uint16_t RESERVED5;
__IO uint16_t IC_SS_SCL_LCNT;
__IO uint16_t RESERVED6;
__IO uint16_t IC_FS_SCL_HCNT;
__IO uint16_t RESERVED7;
__IO uint16_t IC_FS_SCL_LCNT;
__IO uint16_t RESERVED8;
// __IO uint16_t IC_HS_SCL_HCNT;
__IO uint32_t RESERVED9;
// __IO uint16_t IC_HS_SCL_LCNT;
__IO uint32_t RESERVED10;
__IO uint16_t IC_INTR_STAT;
__IO uint16_t RESERVED11;
__IO uint16_t IC_INTR_MASK;
__IO uint16_t RESERVED12;
__IO uint16_t IC_RAW_INTR_STAT;
__IO uint16_t RESERVED13;
__IO uint16_t IC_RX_TL;
__IO uint16_t RESERVED14;
__IO uint16_t IC_TX_TL;
__IO uint16_t RESERVED15;
__IO uint16_t IC_CLR_INTR;
__IO uint16_t RESERVED16;
__IO uint16_t IC_CLR_RX_UNDER;
__IO uint16_t RESERVED17;
__IO uint16_t IC_CLR_RX_OVER;
__IO uint16_t RESERVED18;
__IO uint16_t IC_CLR_TX_OVER;
__IO uint16_t RESERVED19;
__IO uint16_t IC_CLR_RD_REQ;
__IO uint16_t RESERVED20;
__IO uint16_t IC_CLR_TX_ABRT;
__IO uint16_t RESERVED21;
__IO uint16_t IC_CLR_RX_DONE;
__IO uint16_t RESERVED22;
__IO uint16_t IC_CLR_ACTIVITY;
__IO uint16_t RESERVED23;
__IO uint16_t IC_CLR_STOP_DET;
__IO uint16_t RESERVED24;
__IO uint16_t IC_CLR_START_DET;
__IO uint16_t RESERVED25;
__IO uint16_t IC_CLR_GEN_CALL;
__IO uint16_t RESERVED26;
__IO uint16_t IC_ENABLE;
__IO uint16_t RESERVED27;
__IO uint16_t IC_STATUS;
__IO uint16_t RESERVED28;
__IO uint16_t IC_TXFLR;
__IO uint16_t RESERVED29;
__IO uint16_t IC_RXFLR;
__IO uint16_t RESERVED30;
__IO uint16_t IC_SDA_HOLD;
__IO uint16_t RESERVED31;
__IO uint32_t RESERVED32;
__IO uint32_t RESERVED33;
__IO uint16_t IC_DMA_CR;
__IO uint16_t RESERVED34;
__IO uint32_t RESERVED35;
__IO uint32_t RESERVED36;
// __IO uint16_t IC_DMA_TDLR;
// __IO uint16_t IC_DMA_RDLR;
__IO uint16_t IC_SDA_SETUP;
__IO uint16_t RESERVED37;
__IO uint16_t IC_ACK_GENERAL_CALL;
__IO uint16_t RESERVED38;
// __IO uint32_t IC_FS_SPKLEN;
// __IO uint32_t IC_HS_SPKLEN;
// __IO uint16_t IC_CLR_RESTART_DET;
// __IO uint16_t RESERVED28;
// __IO uint32_t IC_COMP_PARAM_1;
// __IO uint32_t IC_COMP_VERSION;
// __IO uint32_t IC_COMP_TYPE;
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR;
__IO uint32_t PR;
__IO uint32_t RLR;
__IO uint32_t SR;
__IO uint32_t CTRL;
} IWDG_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CSR;
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CFGR;
__IO uint32_t CIR;
__IO uint32_t AHB3RSTR;
__IO uint32_t AHB2RSTR;
__IO uint32_t AHB1RSTR;
__IO uint32_t APB2RSTR;
__IO uint32_t APB1RSTR;
__IO uint32_t AHB3ENR;
__IO uint32_t AHB2ENR;
__IO uint32_t AHB1ENR;
__IO uint32_t APB2ENR;
__IO uint32_t APB1ENR;
__IO uint32_t BDCR;
__IO uint32_t CSR;
__IO uint32_t SYSCFGR;
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint16_t CRH;
__IO uint16_t RESERVED0;
__IO uint16_t CRL;
__IO uint16_t RESERVED1;
__IO uint16_t PRLH;
__IO uint16_t RESERVED2;
__IO uint16_t PRLL;
__IO uint16_t RESERVED3;
__IO uint16_t DIVH;
__IO uint16_t RESERVED4;
__IO uint16_t DIVL;
__IO uint16_t RESERVED5;
__IO uint16_t CNTH;
__IO uint16_t RESERVED6;
__IO uint16_t CNTL;
__IO uint16_t RESERVED7;
__IO uint16_t ALRH;
__IO uint16_t RESERVED8;
__IO uint16_t ALRL;
__IO uint16_t RESERVED9;
} RTC_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
#define NSSR SCSR
#define EXTCTL EXTSCR
typedef struct
{
__IO uint32_t TXREG; //0
__IO uint32_t RXREG; //4
__IO uint16_t CSTAT; //8
__IO uint16_t RESERVED0;
__IO uint16_t INTSTAT; //c
__IO uint16_t RESERVED1;
__IO uint16_t INTEN; //10
__IO uint16_t RESERVED2;
__IO uint16_t INTCLR; //14
__IO uint16_t RESERVED3;
__IO uint16_t GCTL; //18
__IO uint16_t RESERVED4;
__IO uint16_t CCTL; //1c
__IO uint16_t RESERVED5;
__IO uint16_t SPBRG; //20
__IO uint16_t RESERVED6;
__IO uint16_t RXDNR; //24
__IO uint16_t RESERVED7;
__IO uint16_t SCSR; //28
__IO uint16_t RESERVED8;
__IO uint16_t EXTSCR; //2c
__IO uint16_t RESERVED9;
} SPI_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint16_t CR1;
__IO uint16_t RESERVED0;
__IO uint16_t CR2;
__IO uint16_t RESERVED1;
__IO uint16_t SMCR;
__IO uint16_t RESERVED2;
__IO uint16_t DIER;
__IO uint16_t RESERVED3;
__IO uint16_t SR;
__IO uint16_t RESERVED4;
__IO uint16_t EGR;
__IO uint16_t RESERVED5;
__IO uint16_t CCMR1;
__IO uint16_t RESERVED6;
__IO uint16_t CCMR2;
__IO uint16_t RESERVED7;
__IO uint16_t CCER;
__IO uint16_t RESERVED8;
__IO uint32_t CNT; //16->32bit
__IO uint16_t PSC;
__IO uint16_t RESERVED10;
__IO uint32_t ARR; //16->32bit
__IO uint16_t RCR;
__IO uint16_t RESERVED12;
__IO uint32_t CCR1; //16->32bit
__IO uint32_t CCR2; //16->32bit
__IO uint32_t CCR3; //16->32bit
__IO uint32_t CCR4; //16->32bit
__IO uint32_t BDTR;
__IO uint16_t DCR;
__IO uint16_t RESERVED18;
__IO uint16_t DMAR;
__IO uint16_t RESERVED19;
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
#define RXADDR RXADD
typedef struct
{
__IO uint32_t TDR;
__IO uint32_t RDR;
__IO uint32_t CSR;
__IO uint32_t ISR;
__IO uint32_t IER;
__IO uint32_t ICR;
__IO uint32_t GCR;
__IO uint32_t CCR;
__IO uint32_t BRR;
__IO uint32_t FRA;
__IO uint32_t RXADD;
__IO uint32_t RXMASK;
__IO uint32_t SCR;
} UART_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CFR;
__IO uint32_t SR;
} WWDG_TypeDef;
//???chend:no document,not check
/**
* @brief QSPI
*/
typedef struct
{
__IO uint32_t INST_READ;
__IO uint32_t INST_SET;
__IO uint32_t SPEC;
__IO uint32_t CLKGEN;
__IO uint32_t DATA_ADDR;
__IO uint32_t ENCRYPT;
__IO uint32_t CHECKDATA;
__IO uint32_t DATAPRO;
__IO uint32_t DATAOPEN;
} QSPI_TypeDef;
/**
* @brief FSMC
*/
#define SSCONR SCONR
#define SCSLR0 SCSLR0_LOW
#define SCSLR1 SCSLR1_LOW
#define SCSLR2 SCSLR2_LOW
#define SCSLR3 SCSLR3_LOW
#define SCSLR4 SCSLR4_LOW
#define SCSLR5 SCSLR5_LOW
#define SCSLR6 SCSLR6_LOW
#define SCSLR7 SCSLR7_LOW
typedef struct
{
__IO uint32_t SSCONR; //0
__IO uint32_t STMG0R; //4
__IO uint32_t STMG1R; //8
__IO uint32_t SCTLR; //c
__IO uint32_t SREFR; //10
__IO uint32_t SCSLR0_LOW; //14
__IO uint32_t SCSLR1_LOW; //18
__IO uint32_t SCSLR2_LOW; //1c
__IO uint32_t SCSLR3_LOW; //20
__IO uint32_t SCSLR4_LOW; //24
__IO uint32_t SCSLR5_LOW; //28
__IO uint32_t SCSLR6_LOW; //2c
__IO uint32_t SCSLR7_LOW; //30
__IO uint32_t RESERVED0; //34
__IO uint32_t RESERVED1; //38
__IO uint32_t RESERVED2; //3c
__IO uint32_t RESERVED3; //40
__IO uint32_t RESERVED4; //44
__IO uint32_t RESERVED5; //48
__IO uint32_t RESERVED6; //4c
__IO uint32_t RESERVED7; //50
__IO uint32_t SMSKR0; //54
__IO uint32_t SMSKR1; //58
__IO uint32_t SMSKR2; //5c
__IO uint32_t SMSKR3; //60
__IO uint32_t SMSKR4; //64
__IO uint32_t SMSKR5; //68
__IO uint32_t SMSKR6; //6c
__IO uint32_t SMSKR7; //70
__IO uint32_t CSALIAS0_LOW; //74
__IO uint32_t CSALIAS1_LOW; //78
__IO uint32_t RESERVED8; //7c
__IO uint32_t RESERVED9; //80
__IO uint32_t CSREMAP0_LOW; //84
__IO uint32_t CSREMAP1_LOW; //88
__IO uint32_t RESERVED10; //8c
__IO uint32_t RESERVED11; //90
__IO uint32_t SMTMGR_SET0; //94
__IO uint32_t SMTMGR_SET1; //98
__IO uint32_t SMTMGR_SET2; //9c
__IO uint32_t FLASH_TRPDR; //a0
__IO uint32_t SMCTLR; //a4
__IO uint32_t RESERVED17; //a8
__IO uint32_t EXN_MODE_REG; //ac
} FSMC_TypeDef;
/**
* @brief TRNG
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t SR;
__IO uint32_t IER;
__IO uint32_t DR;
__IO uint32_t NONCE_SEED1;
__IO uint32_t NONCE_SEED2;
__IO uint32_t NONCE_SEED3;
} TRNG_TypeDef;
/**
* @brief AES
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t SR;
__IO uint32_t DINR;
__IO uint32_t DOUTR;
__IO uint32_t KEYR0;
__IO uint32_t KEYR1;
__IO uint32_t KEYR2;
__IO uint32_t KEYR3;
__IO uint32_t IVR0;
__IO uint32_t IVR1;
__IO uint32_t IVR2;
__IO uint32_t IVR3;
__IO uint32_t KEYR4;
__IO uint32_t KEYR5;
__IO uint32_t KEYR6;
__IO uint32_t KEYR7;
} AES_TypeDef;
/**
* @brief USB_OTG_FS
*/
typedef struct
{
__IO uint32_t PER_ID; //0x00
__IO uint32_t ID_COMP;
__IO uint32_t REV;
__IO uint32_t ADD_INFO;
__IO uint32_t OTG_INT_STAT; //0x10
__IO uint32_t OTG_INT_EN; //0x14
__IO uint32_t OTG_STATUS; //0x18
__IO uint32_t OTG_CTRL; //0x1c
__IO uint32_t RESERVED1; //0x20
__IO uint32_t RESERVED2; //0x24
__IO uint32_t RESERVED3; //0x28
__IO uint32_t RESERVED4; //0x2c
__IO uint32_t RESERVED5; //0x30
__IO uint32_t RESERVED6; //0x34
__IO uint32_t RESERVED7; //0x38
__IO uint32_t RESERVED8; //0x3c
__IO uint32_t RESERVED9; //0x40
__IO uint32_t RESERVED10; //0x44
__IO uint32_t RESERVED11; //0x48
__IO uint32_t RESERVED12; //0x4c
__IO uint32_t RESERVED13; //0x50
__IO uint32_t RESERVED14; //0x54
__IO uint32_t RESERVED15; //0x58
__IO uint32_t RESERVED16; //0x5c
__IO uint32_t RESERVED17; //0x60
__IO uint32_t RESERVED18; //0x64
__IO uint32_t RESERVED19; //0x68
__IO uint32_t RESERVED20; //0x6c
__IO uint32_t RESERVED21; //0x70
__IO uint32_t RESERVED22; //0x74
__IO uint32_t RESERVED23; //0x78
__IO uint32_t RESERVED24; //0x7c
__IO uint32_t INT_STAT; //0x80
__IO uint32_t INT_ENB;
__IO uint32_t ERR_STAT;
__IO uint32_t ERR_ENB;
__IO uint32_t STAT; //0x90
__IO uint32_t CTL;
__IO uint32_t ADDR;
__IO uint32_t BDT_PAGE_01;
__IO uint32_t FRM_NUML; //0xa0
__IO uint32_t FRM_NUMH;
__IO uint32_t TOKEN;
__IO uint32_t SOF_THLD;
__IO uint32_t BDT_PAGE_02; //0xb0
__IO uint32_t BDT_PAGE_03; //0xb4
__IO uint32_t RESERVED25; //0xb8
__IO uint32_t RESERVED26; //0xbc
__IO uint32_t EP_CTL0; //0xc0
__IO uint32_t EP_CTL1; //0xc4
__IO uint32_t EP_CTL2; //0xc8
__IO uint32_t EP_CTL3; //0xcc
__IO uint32_t EP_CTL4; //0xd0
__IO uint32_t EP_CTL5; //0xd4
__IO uint32_t EP_CTL6; //0xd8
__IO uint32_t EP_CTL7; //0xdc
__IO uint32_t EP_CTL8; //0xe0
__IO uint32_t EP_CTL9; //0xe4
__IO uint32_t EP_CTL10; //0xe8
__IO uint32_t EP_CTL11; //0xec
__IO uint32_t EP_CTL12; //0xf0
__IO uint32_t EP_CTL13; //0xf4
__IO uint32_t EP_CTL14; //0xf8
__IO uint32_t EP_CTL15; //0xfc
} USB_OTG_FS_TypeDef;
typedef struct
{
__IO uint32_t FORMAT;
__IO uint32_t ADRESS;
} BDT_DATA_TypeDef;
typedef struct
{
BDT_DATA_TypeDef RX_BUF[2];
BDT_DATA_TypeDef TX_BUF[2];
} USB_OTG_BDT_TypeDef;
/**
* @brief SDIO
*/
typedef struct
{
__IO uint32_t MMC_CTRL;
__IO uint32_t MMC_IO;
__IO uint32_t MMC_BYTECNTL;
__IO uint32_t MMC_TR_BLOCKCNT;
__IO uint32_t MMC_CRCCTL;
__IO uint32_t CMD_CRC;
__IO uint32_t DAT_CRCL;
__IO uint32_t DAT_CRCH;
__IO uint32_t MMC_PORT;
__IO uint32_t MMC_INT_MASK;
__IO uint32_t CLR_MMC_INT;
__IO uint32_t MMC_CARDSEL;
__IO uint32_t MMC_SIG;
__IO uint32_t MMC_IO_MBCTL;
__IO uint32_t MMC_BLOCKCNT;
__IO uint32_t MMC_TIMEOUTCNT;
__IO uint32_t CMD_BUF0;
__IO uint32_t CMD_BUF1;
__IO uint32_t CMD_BUF2;
__IO uint32_t CMD_BUF3;
__IO uint32_t CMD_BUF4;
__IO uint32_t CMD_BUF5;
__IO uint32_t CMD_BUF6;
__IO uint32_t CMD_BUF7;
__IO uint32_t CMD_BUF8;
__IO uint32_t CMD_BUF9;
__IO uint32_t CMD_BUF10;
__IO uint32_t CMD_BUF11;
__IO uint32_t CMD_BUF12;
__IO uint32_t CMD_BUF13;
__IO uint32_t CMD_BUF14;
__IO uint32_t CMD_BUF15;
__IO uint32_t BUF_CTL;
__IO uint32_t RESERVED[31];
__IO uint32_t DATA_BUF0;
__IO uint32_t DATA_BUF1;
__IO uint32_t DATA_BUF2;
__IO uint32_t DATA_BUF3;
__IO uint32_t DATA_BUF4;
} SDIO_TypeDef;
/**
* @brief Ethernet MAC
*/
typedef struct
{
__IO uint32_t MACCR; //0X0000
__IO uint32_t MACFFR; //0X0004
__IO uint32_t MACHTHR; //0X0008
__IO uint32_t MACHTLR; //0X000C
__IO uint32_t MACMIIAR; //0X0010
__IO uint32_t MACMIIDR; //0x0014
__IO uint32_t MACFCR; //0x0018
__IO uint32_t MACVLANTR; //0x001C
__IO uint32_t RESERVED0[2]; //0x0020 ~ 0x0024
__IO uint32_t MACRWUFFR; //0x0028
__IO uint32_t MACPMTCSR; //0x002C
//__IO uint32_t MACSR; //0x0030
//__IO uint32_t MACIMR; //0x0034
__IO uint32_t RESERVED1[4]; //0x0030 ~ 0x003C
__IO uint32_t MACA0HR; //0x0040
__IO uint32_t MACA0LR; //0x0044
__IO uint32_t MACA1HR; //0x0048
__IO uint32_t MACA1LR; //0x004C
__IO uint32_t MACA2HR; //0x0050
__IO uint32_t MACA2LR; //0x0054
__IO uint32_t MACA3HR; //0x0058
__IO uint32_t MACA3LR; //0x005C
__IO uint32_t MACA4HR; //0x0060
__IO uint32_t MACA4LR; //0x0064
__IO uint32_t MACA5HR; //0x0068
__IO uint32_t MACA5LR; //0x006C
__IO uint32_t MACA6HR; //0x0070
__IO uint32_t MACA6LR; //0x0074
__IO uint32_t MACA7HR; //0x0078
__IO uint32_t MACA7LR; //0x007C
__IO uint32_t MACA8HR; //0x0080
__IO uint32_t MACA8LR; //0x0084
__IO uint32_t MACA9HR; //0x0088
__IO uint32_t MACA9LR; //0x008C
__IO uint32_t MACA10HR; //0x0090
__IO uint32_t MACA10LR; //0x0094
__IO uint32_t MACA11HR; //0x0098
__IO uint32_t MACA11LR; //0x009C
__IO uint32_t MACA12HR; //0x00A0
__IO uint32_t MACA12LR; //0x00A4
__IO uint32_t MACA13HR; //0x00A8
__IO uint32_t MACA13LR; //0x00AC
__IO uint32_t MACA14HR; //0x00B0
__IO uint32_t MACA14LR; //0x00B4
__IO uint32_t MACA15HR; //0x00B8
__IO uint32_t MACA15LR; //0x00BC
__IO uint32_t MACANCR; //0x00C0
__IO uint32_t MACANSR; //0x00C4
__IO uint32_t MACANAR; //0x00C8
__IO uint32_t MACANLPAR; //0x00CC
__IO uint32_t MACANER; //0x00D0
__IO uint32_t MACTBIER; //0x00D4
__IO uint32_t MACMIISR; //0x00D8
__IO uint32_t RESERVED2[9]; //0x00DC ~ 0x00FC
__IO uint32_t MMCCR; //0x0100
__IO uint32_t MMCRIR; //0x0104
__IO uint32_t MMCTIR; //0x0108
__IO uint32_t MMCRIMR; //0x010C
__IO uint32_t MMCTIMR; //0x0110
__IO uint32_t RESERVED3[14]; //0x0114 ~ 0x0148
__IO uint32_t MMCTGFSCCR; //0x014C
__IO uint32_t MMCTGFMSCCR; //0x0150
__IO uint32_t RESERVED4[5]; //0x0154 ~ 0x0164
__IO uint32_t MMCTGFCR; //0x0168
__IO uint32_t RESERVED5[10]; //0x016C ~ 0x0190
__IO uint32_t MMCRFCECR; //0x0194
__IO uint32_t MMCRFAECR; //0x0198
__IO uint32_t RESERVED6[10]; //0x019C ~ 0x01C0
__IO uint32_t MMCRGUFCR; //0x01C4
}ETH_MAC_TypeDef;
/**
* @brief Ethernet DMA
*/
typedef struct
{
__IO uint32_t DMABMR; //0x1000
__IO uint32_t DMATPDR; //0x1004
__IO uint32_t DMARPDR; //0x1008
__IO uint32_t DMARDLAR; //0x100C
__IO uint32_t DMATDLAR; //0x1010
__IO uint32_t DMASR; //0x1014
__IO uint32_t DMAOMR; //0x1018
__IO uint32_t DMAIER; //0x101C
__IO uint32_t DMAMFBOCR; //0x1020
__IO uint32_t RESERVED10[9]; //0x1024 ~ 0x1044
__IO uint32_t DMACHTDR; //0x1048
__IO uint32_t DMACHRDR; //0x104C
__IO uint32_t DMACHTBAR; //0x1050
__IO uint32_t DMACHRBAR; //0x1054
} ETH_DMA_TypeDef;
/**
* @}
*/
#define HARD_FAULT_MM ((HARD_FAULT_TypeDef*)0xE000DE24)
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
#define SECURITY_MEM_BASE ((uint32_t)0x1FFE1000) /*!< Special security memory base address */
#define PROTECT_BYTE_R_BASE ((uint32_t)0x1FFE0000) /*!< Protect byte register base address */
#define EEPROM_BASE ((uint32_t)0x08100000) /*!< EEPROM base address in the alias region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000)
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define BKP_BASE (APB1PERIPH_BASE + 0x2800 + 0x24)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define UART2_BASE (APB1PERIPH_BASE + 0x4400)
#define UART3_BASE (APB1PERIPH_BASE + 0x4800)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define CRS_BASE (APB1PERIPH_BASE + 0x6C00)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
#define COMP_BASE (APB2PERIPH_BASE + 0x001C)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
#define UART1_BASE (APB2PERIPH_BASE + 0x3800)
#define UART6_BASE (APB2PERIPH_BASE + 0x3C00)
#define CACHE_BASE (APB2PERIPH_BASE + 0x6000)
#define SDIO_BASE (0x40018000)
#define DMA1_BASE (AHB1PERIPH_BASE + 0x0000)
#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x0008)
#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x001C)
#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x0030)
#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x0044)
#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x0058)
#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x006C)
#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x0080)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400)
#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x0408)
#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x041C)
#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x0430)
#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x0444)
#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x0458)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000) /*!< Flash registers base address */
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
#define ETH_MAC_BASE (AHB1PERIPH_BASE + 0x8000)
#define ETH_DMA_BASE (AHB1PERIPH_BASE + 0x9000)
#define GPIOA_BASE (0x48000000)
#define GPIOB_BASE (0x48000400)
#define GPIOC_BASE (0x48000800)
#define GPIOD_BASE (0x48000C00)
#define GPIOE_BASE (0x48001000)
#define USB_OTG_FS_BASE (0x50000000)
#define AES_BASE (0x50060000)
#define TRNG_BASE (0x50060800)
#define FSMC_BANK1_ADDR (0x60000000)
#define FSMC_BANK2_ADDR (0x64000000)
#define FSMC_BANK3_ADDR (0x68000000)
#define FSMC_BANK4_ADDR (0x6c000000)
#define FSMC_R_BASE (0xA0000000)
#define QSPI_R_BASE (0xA0001000)
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define BKP ((BKP_TypeDef *) BKP_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define UART2 ((UART_TypeDef *) UART2_BASE)
#define UART3 ((UART_TypeDef *) UART3_BASE)
#define UART4 ((UART_TypeDef *) UART4_BASE)
#define UART5 ((UART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define CAN1_BASIC ((CAN_TypeDef *) CAN1_BASE)
#define CAN1_PELI ((CAN_Peli_TypeDef *) CAN1_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define UART7 ((UART_TypeDef *) UART7_BASE)
#define UART8 ((UART_TypeDef *) UART8_BASE)
#define COMP ((COMP_TypeDef *) COMP_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define UART1 ((UART_TypeDef *) UART1_BASE)
#define UART6 ((UART_TypeDef *) UART6_BASE)
#define CACHE ((CACHE_TypeDef*) CACHE_BASE)
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define ETH_MAC ((ETH_MAC_TypeDef *) ETH_MAC_BASE)
#define ETH_DMA ((ETH_DMA_TypeDef *) ETH_DMA_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define USB_OTG_FS ((USB_OTG_FS_TypeDef *) USB_OTG_FS_BASE)
#define AES ((AES_TypeDef *) AES_BASE)
#define TRNG ((TRNG_TypeDef *) TRNG_BASE)
#define FSMC ((FSMC_TypeDef *) FSMC_BASE)
#define QSPI ((QSPI_TypeDef *) QSPI_R_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
#define PWR_CR_PLS ((uint16_t)0x1E00) /*!< PLS[3:0] bits (PVD Level Selection) */
#define PWR_CR_PLS_0 ((uint16_t)0x0200) /*!< Bit 0 */
#define PWR_CR_PLS_1 ((uint16_t)0x0400) /*!< Bit 1 */
#define PWR_CR_PLS_2 ((uint16_t)0x0800) /*!< Bit 2 */
#define PWR_CR_PLS_3 ((uint16_t)0x1000) /*!< Bit 3 */
/*!< PVD level configuration */
#define PWR_CR_PLS_1V8 ((uint16_t)0x0000) /*!< PVD level 1.8V */
#define PWR_CR_PLS_2V1 ((uint16_t)0x0200) /*!< PVD level 2.1V */
#define PWR_CR_PLS_2V4 ((uint16_t)0x0400) /*!< PVD level 2.4V */
#define PWR_CR_PLS_2V7 ((uint16_t)0x0600) /*!< PVD level 2.7V */
#define PWR_CR_PLS_3V0 ((uint16_t)0x0800) /*!< PVD level 3.0V */
#define PWR_CR_PLS_3V3 ((uint16_t)0x0A00) /*!< PVD level 3.3V */
#define PWR_CR_PLS_3V6 ((uint16_t)0x0C00) /*!< PVD level 3.6V */
#define PWR_CR_PLS_3V9 ((uint16_t)0x0E00) /*!< PVD level 3.9V */
#define PWR_CR_PLS_4V2 ((uint16_t)0x1000) /*!< PVD level 4.2V */
#define PWR_CR_PLS_4V5 ((uint16_t)0x1200) /*!< PVD level 4.5V */
#define PWR_CR_PLS_4V8 ((uint16_t)0x1400) /*!< PVD level 4.8V */
#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
/******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
/******************************************************************************/
/* */
/* Backup registers */
/* */
/******************************************************************************/
/******************* Bit definition for BKP_DR1 register ********************/
#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR2 register ********************/
#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR3 register ********************/
#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR4 register ********************/
#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR5 register ********************/
#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR6 register ********************/
#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR7 register ********************/
#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR8 register ********************/
#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR9 register ********************/
#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************* Bit definition for BKP_DR10 register *******************/
#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
/****************** Bit definition for BKP_RTCCR register *******************/
#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
/******************** Bit definition for BKP_CR register ********************/
#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
/******************* Bit definition for BKP_CSR register ********************/
#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
#define RCC_CR_HSITMPEN ((uint32_t)0x00000004) /*!< Internal High Speed clock trimming */
#define RCC_CR_HSICAL ((uint32_t)0x0000FE00) /*!< Internal High Speed clock Calibration */
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
#define RCC_CR_PLLDN ((uint32_t)0xFC000000) /*!< PLLDN[5:0] bits */
#define RCC_CR_PLLDN_0 ((uint32_t)0x04000000) /*!< Bit 0 */
#define RCC_CR_PLLDN_1 ((uint32_t)0x08000000) /*!< Bit 1 */
#define RCC_CR_PLLDN_2 ((uint32_t)0x10000000) /*!< Bit 2 */
#define RCC_CR_PLLDN_3 ((uint32_t)0x20000000) /*!< Bit 3 */
#define RCC_CR_PLLDN_4 ((uint32_t)0x40000000) /*!< Bit 4 */
#define RCC_CR_PLLDN_5 ((uint32_t)0x80000000) /*!< Bit 5 */
#define RCC_CR_PLLDM ((uint32_t)0x00700000) /*!< PLLDM[2:0] bits */
#define RCC_CR_PLLDM_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define RCC_CR_PLLDM_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define RCC_CR_PLLDM_2 ((uint32_t)0x00400000) /*!< Bit 2 */
/******************* Bit definition for RCC_CFGR register *******************/
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
/*!< SW configuration */
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
#define RCC_CFGR_SW_LSI ((uint32_t)0x00000003) /*!< LSI selected as system clock */
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
/*!< SWS configuration */
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
#define RCC_CFGR_SWS_LSI ((uint32_t)0x0000000C) /*!< LSI used as system clock */
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
#define RCC_CFGR_CKOFF_SFT ((uint32_t)0x00004000) /*!< Clock off control bit in STOP mode */
#define RCC_CFGR_CLK48MSEL ((uint32_t)0x00008000) /*!< 48M clock source of USB */
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
#define RCC_CFGR_USBPRE ((uint32_t)0x00C00000) /*!< USB prescaler BIT[1:0] */
#define RCC_CFGR_USBPRE_0 ((uint32_t)0x00400000) /*!< Bit 0 */
#define RCC_CFGR_USBPRE_1 ((uint32_t)0x00800000) /*!< Bit 1 */
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
/*!< MCO configuration */
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) //
#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000)
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected */
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< Internal 48 MHz RC oscillator clock selected */
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< External 1-25 MHz oscillator clock selected */
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected*/
/*!<****************** Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
/****************** Bit definition for RCC_AHB3RSTR register ******************/
#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001) /*!< FSMC reset */
#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002) /*!< QSPI reset */
/****************** Bit definition for RCC_AHB2RSTR register ******************/
#define RCC_AHB2RSTR_AESRST ((uint32_t)0x00000010) /*!< AES reset */
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) /*!< RNG reset */
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) /*!< OTGFS reset */
/****************** Bit definition for RCC_AHB1RSTR register ******************/
#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIOA reset */
#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIOB reset */
#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIOC reset */
#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIOD reset */
#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIOE reset */
#define RCC_AHB1RSTR_SDIORST ((uint32_t)0x00000400) /*!< SDIO reset */
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) /*!< DMA1 reset */
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) /*!< DMA2 reset */
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) /*!< ETHMAC reset */
/***************** Bit definition for RCC_APB2RSTR register *****************/
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) /*!< Timer 1 reset */
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) /*!< Timer 8 reset */
#define RCC_APB2RSTR_UART1RST ((uint32_t)0x00000010) /*!< U ART1 reset */
#define RCC_APB2RSTR_UART6RST ((uint32_t)0x00000020) /*!< U ART6 reset */
#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000100) /*!< ADC 1 interface reset */
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) /*!< SYSCFG reset */
#define RCC_APB2RSTR_COMPRST ((uint32_t)0x00008000) /*!< COMP reset */
/***************** Bit definition for RCC_APB1RSTR register *****************/
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
#define RCC_APB1RSTR_UART2RST ((uint32_t)0x00020000) /*!< UART 2 reset */
#define RCC_APB1RSTR_UART3RST ((uint32_t)0x00040000) /*!< UART 3 reset */
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
#define RCC_APB1RSTR_CRSRST ((uint32_t)0x01000000) /*!< CRS reset */
#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000) /*!< UART 7 reset */
#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000) /*!< UART 8 reset */
/****************** Bit definition for RCC_AHB3ENR register ******************/
#define RCC_AHB3RSTR_FSMCEN ((uint32_t)0x00000001) /*!< FSMC clock enable */
#define RCC_AHB3RSTR_QSPIEN ((uint32_t)0x00000002) /*!< QSPI clock enable */
/****************** Bit definition for RCC_AHB2ENR register ******************/
#define RCC_AHB2RSTR_AESEN ((uint32_t)0x00000010) /*!< AES clock enable */
#define RCC_AHB2RSTR_RNGEN ((uint32_t)0x00000040) /*!< RNG clock enable */
#define RCC_AHB2RSTR_OTGFSEN ((uint32_t)0x00000080) /*!< OTGFS clock enable */
/****************** Bit definition for RCC_AHB1ENR register ******************/
#define RCC_AHB1RSTR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIOA clock enable */
#define RCC_AHB1RSTR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIOB clock enable */
#define RCC_AHB1RSTR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIOC clock enable */
#define RCC_AHB1RSTR_GPIODEN ((uint32_t)0x00000008) /*!< GPIOD clock enable */
#define RCC_AHB1RSTR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIOE clock enable */
#define RCC_AHB1RSTR_SDIOEN ((uint32_t)0x00000400) /*!< SDIO clock enable */
#define RCC_AHB1RSTR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
#define RCC_AHB1RSTR_FLASHEN ((uint32_t)0x00002000) /*!< FLASH clock enable */
#define RCC_AHB1RSTR_SRAMEN ((uint32_t)0x00004000) /*!< FLASH clock enable */
#define RCC_AHB1RSTR_DMA1EN ((uint32_t)0x00200000) /*!< DMA1 clock enable */
#define RCC_AHB1RSTR_DMA2EN ((uint32_t)0x00400000) /*!< DMA2 clock enable */
#define RCC_AHB1RSTR_ETHMACEN ((uint32_t)0x02000000) /*!< ETHMAC clock enable */
/****************** Bit definition for RCC_APB2ENR register *****************/
#define RCC_APB2RSTR_TIM1EN ((uint32_t)0x00000001) /*!< Timer 1 clock enable */
#define RCC_APB2RSTR_TIM8EN ((uint32_t)0x00000002) /*!< Timer 8 clock enable */
#define RCC_APB2RSTR_UART1EN ((uint32_t)0x00000010) /*!< UART1 clock enable */
#define RCC_APB2RSTR_UART6EN ((uint32_t)0x00000020) /*!< UART6 clock enable */
#define RCC_APB2RSTR_ADC1EN ((uint32_t)0x00000100) /*!< ADC 1 interface clock enable */
#define RCC_APB2RSTR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
#define RCC_APB2RSTR_SYSCFGEN ((uint32_t)0x00004000) /*!< SYSCFG clock enable */
#define RCC_APB2RSTR_COMPEN ((uint32_t)0x00008000) /*!< COMP clock enable */
/***************** Bit definition for RCC_APB1ENR register ******************/
#define RCC_APB1RSTR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
#define RCC_APB1RSTR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
#define RCC_APB1RSTR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
#define RCC_APB1RSTR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
#define RCC_APB1RSTR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
#define RCC_APB1RSTR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
#define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
#define RCC_APB1RSTR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
#define RCC_APB1RSTR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
#define RCC_APB1RSTR_UART2EN ((uint32_t)0x00020000) /*!< UART 2 clock enable */
#define RCC_APB1RSTR_UART3EN ((uint32_t)0x00040000) /*!< UART 3 clock enable */
#define RCC_APB1RSTR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
#define RCC_APB1RSTR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
#define RCC_APB1RSTR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
#define RCC_APB1RSTR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
#define RCC_APB1RSTR_CRSEN ((uint32_t)0x01000000) /*!< CRS clock enable */
#define RCC_APB1RSTR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
#define RCC_APB1RSTR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
#define RCC_APB1RSTR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
#define RCC_APB1RSTR_UART7EN ((uint32_t)0x40000000) /*!< UART 7 clock enable */
#define RCC_APB1RSTR_UART8EN ((uint32_t)0x80000000) /*!< UART 8 clock enable */
/******************* Bit definition for RCC_BDCR register *******************/
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
/*!< BDCR_RTCSEL configuration */
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
/******************* Bit definition for RCC_CSR register ********************/
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
/******************* Bit definition for RCC_SYSCFG register ********************/
#define RCC_SYSCFG_PROG_CHECK_EN ((uint32_t)0x00000001) /*!< Program check enable */
#define RCC_SYSCFG_SECTOR_1K_CFG ((uint32_t)0x00000002) /*!< Page size when FLASH page is erased */
#define RCC_SYSCFG_DATA_PREFETCH ((uint32_t)0x00000004) /*!< DATA prefetch module enabled */
#define RCC_SYSCFG_PAD_OSC_TRIM ((uint32_t)0x00001F00) /*!< External crystal calibration value */
#define RCC_SYSCFG_QSPI_CLKP_DIV ((uint32_t)0x007F0000) /*!< QSPI_CLKP_DIV[22:16] bits (QSPI clock prescaler) */
#define RCC_SYSCFG_QSPI_CLKP_DIV_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_SYSCFG_QSPI_CLKP_DIV_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define RCC_SYSCFG_QSPI_CLKP_DIV_2 ((uint32_t)0x00040000) /*!< Bit 2 */
#define RCC_SYSCFG_QSPI_CLKP_DIV_3 ((uint32_t)0x00080000) /*!< Bit 3 */
/*!< QSPI clock prescaler configuration */
#define RCC_SYSCFG_QSPI_CLKP_DIV2 ((uint32_t)0x00000000) /*!< CLK divided by 2 */
#define RCC_SYSCFG_QSPI_CLKP_DIV4 ((uint32_t)0x00010000) /*!< CLK divided by 4 */
#define RCC_SYSCFG_QSPI_CLKP_DIV6 ((uint32_t)0x00020000) /*!< CLK divided by 6 */
#define RCC_SYSCFG_QSPI_CLKP_DIV8 ((uint32_t)0x00030000) /*!< CLK divided by 8 */
#define RCC_SYSCFG_QSPI_BYPASS ((uint32_t)0x00800000) /*!< QSPI bypass control bit */
#define RCC_SYSCFG_DBUF_EN ((uint32_t)0x80000000) /*!< DATA prefetch module status bit */
/******************************************************************************/
/* */
/* General Purpose and Alternate Function IO */
/* */
/******************************************************************************/
/******************* Bit definition for GPIO_CRL register *******************/
#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
/******************* Bit definition for GPIO_CRH register *******************/
#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
/*!<****************** Bit definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
/******************* Bit definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
/****************** Bit definition for GPIO_BSRR register *******************/
#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
/******************* Bit definition for GPIO_BRR register *******************/
#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
/****************** Bit definition for GPIO_LCKR register *******************/
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
/****************** Bit definition for GPIO_AFRL register *******************/
#define GPIO_AFRL_AFR ((uint32_t)0xFFFFFFFF) /*!< Port x alternate function bits */
#define GPIO_AFRL_AFR0 ((uint32_t)0x0000000F) /*!< AFR0[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRL_AFR0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define GPIO_AFRL_AFR0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define GPIO_AFRL_AFR0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define GPIO_AFRL_AFR0_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define GPIO_AFRL_AFR1 ((uint32_t)0x000000F0) /*!< AFR1[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRL_AFR1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define GPIO_AFRL_AFR1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define GPIO_AFRL_AFR1_2 ((uint32_t)0x00000040) /*!< Bit 2 */
#define GPIO_AFRL_AFR1_3 ((uint32_t)0x00000080) /*!< Bit 3 */
#define GPIO_AFRL_AFR2 ((uint32_t)0x00000F00) /*!< AFR2[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRL_AFR2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define GPIO_AFRL_AFR2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define GPIO_AFRL_AFR2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define GPIO_AFRL_AFR2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
#define GPIO_AFRL_AFR3 ((uint32_t)0x0000F000) /*!< AFR3[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRL_AFR3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define GPIO_AFRL_AFR3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define GPIO_AFRL_AFR3_2 ((uint32_t)0x00004000) /*!< Bit 2 */
#define GPIO_AFRL_AFR3_3 ((uint32_t)0x00008000) /*!< Bit 3 */
#define GPIO_AFRL_AFR4 ((uint32_t)0x000F0000) /*!< AFR4[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRL_AFR4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define GPIO_AFRL_AFR4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define GPIO_AFRL_AFR4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
#define GPIO_AFRL_AFR4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
#define GPIO_AFRL_AFR5 ((uint32_t)0x00F00000) /*!< AFR5[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRL_AFR5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define GPIO_AFRL_AFR5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define GPIO_AFRL_AFR5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
#define GPIO_AFRL_AFR5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
#define GPIO_AFRL_AFR6 ((uint32_t)0x0F000000) /*!< AFR6[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRL_AFR6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define GPIO_AFRL_AFR6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define GPIO_AFRL_AFR6_2 ((uint32_t)0x04000000) /*!< Bit 2 */
#define GPIO_AFRL_AFR6_3 ((uint32_t)0x08000000) /*!< Bit 3 */
#define GPIO_AFRL_AFR7 ((uint32_t)0xF0000000) /*!< AFR7[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRL_AFR7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
#define GPIO_AFRL_AFR7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
#define GPIO_AFRL_AFR7_2 ((uint32_t)0x40000000) /*!< Bit 2 */
#define GPIO_AFRL_AFR7_3 ((uint32_t)0x80000000) /*!< Bit 3 */
/****************** Bit definition for GPIO_AFRH register *******************/
#define GPIO_AFRH_AFR ((uint32_t)0xFFFFFFFF) /*!< Port x alternate function bits */
#define GPIO_AFRH_AFR8 ((uint32_t)0x0000000F) /*!< AFR8[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRH_AFR8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define GPIO_AFRH_AFR8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define GPIO_AFRH_AFR8_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define GPIO_AFRH_AFR8_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define GPIO_AFRH_AFR9 ((uint32_t)0x000000F0) /*!< AFR9[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRH_AFR9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define GPIO_AFRH_AFR9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define GPIO_AFRH_AFR9_2 ((uint32_t)0x00000040) /*!< Bit 2 */
#define GPIO_AFRH_AFR9_3 ((uint32_t)0x00000080) /*!< Bit 3 */
#define GPIO_AFRH_AFR10 ((uint32_t)0x00000F00) /*!< AFR10[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRH_AFR10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define GPIO_AFRH_AFR10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define GPIO_AFRH_AFR10_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define GPIO_AFRH_AFR10_3 ((uint32_t)0x00000800) /*!< Bit 3 */
#define GPIO_AFRH_AFR11 ((uint32_t)0x0000F000) /*!< AFR11[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRH_AFR11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define GPIO_AFRH_AFR11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define GPIO_AFRH_AFR11_2 ((uint32_t)0x00004000) /*!< Bit 2 */
#define GPIO_AFRH_AFR11_3 ((uint32_t)0x00008000) /*!< Bit 3 */
#define GPIO_AFRH_AFR12 ((uint32_t)0x000F0000) /*!< AFR12[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRH_AFR12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define GPIO_AFRH_AFR12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define GPIO_AFRH_AFR12_2 ((uint32_t)0x00040000) /*!< Bit 2 */
#define GPIO_AFRH_AFR12_3 ((uint32_t)0x00080000) /*!< Bit 3 */
#define GPIO_AFRH_AFR13 ((uint32_t)0x00F00000) /*!< AFR13[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRH_AFR13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define GPIO_AFRH_AFR13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define GPIO_AFRH_AFR13_2 ((uint32_t)0x00400000) /*!< Bit 2 */
#define GPIO_AFRH_AFR13_3 ((uint32_t)0x00800000) /*!< Bit 3 */
#define GPIO_AFRH_AFR14 ((uint32_t)0x0F000000) /*!< AFR14[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRH_AFR14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define GPIO_AFRH_AFR14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define GPIO_AFRH_AFR14_2 ((uint32_t)0x04000000) /*!< Bit 2 */
#define GPIO_AFRH_AFR14_3 ((uint32_t)0x08000000) /*!< Bit 3 */
#define GPIO_AFRH_AFR15 ((uint32_t)0xF0000000) /*!< AFR15[3:0] bits (Port x alternate function bits, pin 0) */
#define GPIO_AFRH_AFR15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
#define GPIO_AFRH_AFR15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
#define GPIO_AFRH_AFR15_2 ((uint32_t)0x40000000) /*!< Bit 2 */
#define GPIO_AFRH_AFR15_3 ((uint32_t)0x80000000) /*!< Bit 3 */
/*----------------------------------------------------------------------------*/
/******************************************************************************/
/* */
/* SystemTick */
/* */
/******************************************************************************/
/***************** Bit definition for SysTick_CTRL register *****************/
#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
/***************** Bit definition for SysTick_LOAD register *****************/
#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
/***************** Bit definition for SysTick_VAL register ******************/
#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
/***************** Bit definition for SysTick_CALIB register ****************/
#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
/******************************************************************************/
/* */
/* Nested Vectored Interrupt Controller */
/* */
/******************************************************************************/
/****************** Bit definition for NVIC_ISER register *******************/
#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
/****************** Bit definition for NVIC_ICER register *******************/
#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
/****************** Bit definition for NVIC_ISPR register *******************/
#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
/****************** Bit definition for NVIC_ICPR register *******************/
#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
/****************** Bit definition for NVIC_IABR register *******************/
#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
/****************** Bit definition for NVIC_PRI0 register *******************/
#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
/****************** Bit definition for NVIC_PRI1 register *******************/
#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
/****************** Bit definition for NVIC_PRI2 register *******************/
#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
/****************** Bit definition for NVIC_PRI3 register *******************/
#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
/****************** Bit definition for NVIC_PRI4 register *******************/
#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
/****************** Bit definition for NVIC_PRI5 register *******************/
#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
/****************** Bit definition for NVIC_PRI6 register *******************/
#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
/****************** Bit definition for NVIC_PRI7 register *******************/
#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
/****************** Bit definition for NVIC_PRI8 register *******************/
#define NVIC_IPR7_PRI_32 ((uint32_t)0x000000FF) /*!< Priority of interrupt 32 */
#define NVIC_IPR7_PRI_33 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 33 */
#define NVIC_IPR7_PRI_34 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 34 */
#define NVIC_IPR7_PRI_35 ((uint32_t)0xFF000000) /*!< Priority of interrupt 35 */
/****************** Bit definition for NVIC_PRI9 register *******************/
#define NVIC_IPR7_PRI_36 ((uint32_t)0x000000FF) /*!< Priority of interrupt 36 */
#define NVIC_IPR7_PRI_37 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 37 */
#define NVIC_IPR7_PRI_38 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 38 */
#define NVIC_IPR7_PRI_39 ((uint32_t)0xFF000000) /*!< Priority of interrupt 39 */
/****************** Bit definition for NVIC_PRI10 register *******************/
#define NVIC_IPR7_PRI_40 ((uint32_t)0x000000FF) /*!< Priority of interrupt 40 */
#define NVIC_IPR7_PRI_41 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 41 */
#define NVIC_IPR7_PRI_42 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 42 */
#define NVIC_IPR7_PRI_43 ((uint32_t)0xFF000000) /*!< Priority of interrupt 43 */
/****************** Bit definition for NVIC_PRI11 register *******************/
#define NVIC_IPR7_PRI_44 ((uint32_t)0x000000FF) /*!< Priority of interrupt 44 */
#define NVIC_IPR7_PRI_45 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 45 */
#define NVIC_IPR7_PRI_46 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 46 */
#define NVIC_IPR7_PRI_47 ((uint32_t)0xFF000000) /*!< Priority of interrupt 47 */
/****************** Bit definition for SCB_CPUID register *******************/
#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
/******************* Bit definition for SCB_ICSR register *******************/
#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
/******************* Bit definition for SCB_VTOR register *******************/
#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
/*!<***************** Bit definition for SCB_AIRCR register *******************/
#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
/* prority group configuration */
#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
/******************* Bit definition for SCB_SCR register ********************/
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
/******************** Bit definition for SCB_CCR register *******************/
#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
/******************* Bit definition for SCB_SHPR register ********************/
#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
/****************** Bit definition for SCB_SHCSR register *******************/
#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
/******************* Bit definition for SCB_CFSR register *******************/
/*!< MFSR */
#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
/*!< BFSR */
#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
/*!< UFSR */
#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
/******************* Bit definition for SCB_HFSR register *******************/
#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
/******************* Bit definition for SCB_DFSR register *******************/
#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
/******************* Bit definition for SCB_MMFAR register ******************/
#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
/******************* Bit definition for SCB_BFAR register *******************/
#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
/******************* Bit definition for SCB_afsr register *******************/
#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
// #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
// #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
// #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
// #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
// #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
// #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
// #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
// #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
// #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
// #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Trigger request occurred on the external interrupt line 18 */
// #define EXTI_PR_PR19 ((uint32_t)0x00080000)
// #define EXTI_PR_PR20 ((uint32_t)0x00100000)
/******************************************************************************/
/* */
/* DMA Controller */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for DMA_CCR1 register *******************/
#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
/******************* Bit definition for DMA_CCR2 register *******************/
#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
/******************* Bit definition for DMA_CCR3 register *******************/
#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
/*!<****************** Bit definition for DMA_CCR4 register *******************/
#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */
#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */
#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
/****************** Bit definition for DMA_CCR5 register *******************/
#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */
#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */
#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
/******************* Bit definition for DMA_CCR6 register *******************/
#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */
#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */
#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
/******************* Bit definition for DMA_CCR7 register *******************/
#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */
#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */
#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
/******************* Bit definition for DMA_CCR8 register *******************/
#define DMA_CCR8_EN ((uint16_t)0x0001) /*!<Channel enable */
#define DMA_CCR8_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
#define DMA_CCR8_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
#define DMA_CCR8_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
#define DMA_CCR8_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
#define DMA_CCR8_CIRC ((uint16_t)0x0020) /*!<Circular mode */
#define DMA_CCR8_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
#define DMA_CCR8_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
#define DMA_CCR8_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR8_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define DMA_CCR8_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define DMA_CCR8_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
#define DMA_CCR8_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define DMA_CCR8_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define DMA_CCR8_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
#define DMA_CCR8_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define DMA_CCR8_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define DMA_CCR8_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
/****************** Bit definition for DMA_CNDTR1 register ******************/
#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR2 register ******************/
#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR3 register ******************/
#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR4 register ******************/
#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR5 register ******************/
#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR6 register ******************/
#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR7 register ******************/
#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR8 register ******************/
#define DMA_CNDTR8_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
/****************** Bit definition for DMA_CPAR1 register *******************/
#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
/****************** Bit definition for DMA_CPAR2 register *******************/
#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
/****************** Bit definition for DMA_CPAR3 register *******************/
#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
/****************** Bit definition for DMA_CPAR4 register *******************/
#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
/****************** Bit definition for DMA_CPAR5 register *******************/
#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
/****************** Bit definition for DMA_CPAR6 register *******************/
#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
/****************** Bit definition for DMA_CPAR7 register *******************/
#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
/****************** Bit definition for DMA_CPAR8 register *******************/
#define DMA_CPAR8_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
/****************** Bit definition for DMA_CMAR1 register *******************/
#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
/****************** Bit definition for DMA_CMAR2 register *******************/
#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
/****************** Bit definition for DMA_CMAR3 register *******************/
#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
/****************** Bit definition for DMA_CMAR4 register *******************/
#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
/****************** Bit definition for DMA_CMAR5 register *******************/
#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
/****************** Bit definition for DMA_CMAR6 register *******************/
#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
/****************** Bit definition for DMA_CMAR7 register *******************/
#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
/****************** Bit definition for DMA_CMAR8 register *******************/
#define DMA_CMAR8_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/******************** Bit definition for ADDATA register ********************/
#define ADDATA_DATA ((uint32_t)0x00000FFF) /*!<ADC 12bit convert data */
#define ADDATA_CHANNELSEL ((uint32_t)0x00070000) /*!<CHANNELSEL[19:16] (ADC current channel convert data) */
#define ADDATA_CHANNELSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define ADDATA_CHANNELSEL_1 ((uint32_t)0x00020000) /*!<Bit 1*/
#define ADDATA_CHANNELSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define ADDATA_CHANNELSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define ADDATA_OVERRUN ((uint32_t)0x00100000) /*!<ADC data will be cover */
#define ADDATA_VALID ((uint32_t)0x00200000) /*!<ADC data[11:0] is valid*/
/******************** Bit definition for ADCFG register ********************/
#define ADCFG_ADEN ((uint32_t)0x00000001) /*!<ADC convert enable */
#define ADCFG_ADWEN ((uint32_t)0x00000002) /*!<ADC window compare enable */
#define ADCFG_TVSEN ((uint32_t)0x00000004) /*!<ADC sensor enable */
#define ADCFG_ADCPRE ((uint32_t)0x00000070)
#define ADCFG_ADCPRE_2 ((uint32_t)0x00000000) /*!<ADC preclk 2 */
#define ADCFG_ADCPRE_4 ((uint32_t)0x00000010) /*!<ADC preclk 4 */
#define ADCFG_ADCPRE_6 ((uint32_t)0x00000020) /*!<ADC preclk 6 */
#define ADCFG_ADCPRE_8 ((uint32_t)0x00000030) /*!<ADC preclk 8 */
#define ADCFG_ADCPRE_10 ((uint32_t)0x00000040) /*!<ADC preclk 10 */
#define ADCFG_ADCPRE_12 ((uint32_t)0x00000050) /*!<ADC preclk 12 */
#define ADCFG_ADCPRE_14 ((uint32_t)0x00000060) /*!<ADC preclk 14 */
#define ADCFG_ADCPRE_16 ((uint32_t)0x00000070) /*!<ADC preclk 16 */
#define ADCFG_RSLTCTL ((uint32_t)0x00000380)
#define ADCFG_RSLTCTL_0 ((uint32_t)0x00000080)
#define ADCFG_RSLTCTL_1 ((uint32_t)0x00000100)
#define ADCFG_RSLTCTL_2 ((uint32_t)0x00000200)
#define ADCFG_SAMCTL ((uint32_t)0x00001C00)
#define ADCFG_SAMCTL_0 ((uint32_t)0x00000400)
#define ADCFG_SAMCTL_1 ((uint32_t)0x00000800)
#define ADCFG_SAMCTL_2 ((uint32_t)0x00001000)
/******************** Bit definition for ADCR register ********************/
#define ADCR_ADIE ((uint32_t)0x00000001) /*!<ADC interrupt enable */
#define ADCR_ADWIE ((uint32_t)0x00000002) /*!<ADC window compare interrupt enable */
#define ADCR_TRGEN ((uint32_t)0x00000004) /*!<extranal trigger single start AD convert */
#define ADCR_DMAEN ((uint32_t)0x00000008) /*!<ADC DMA enable */
#define ADCR_TRGSEL ((uint32_t)0x00000070) /*!<TRGSEL[6:4] ADC1 external trigger source select */
#define ADCR_TRGSEL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define ADCR_TRGSEL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define ADCR_TRGSEL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define ADCR_ADST ((uint32_t)0x00000100) /*!<ADC start convert data */
#define ADCR_ADMD ((uint32_t)0x00000600)
#define ADCR_ADMD_SINGLE ((uint32_t)0x00000000) /*!<ADC single convert mode */
#define ADCR_ADMD_PERIOD ((uint32_t)0x00000200) /*!<ADC single period convert mode */
#define ADCR_ADMD_CONTINUE ((uint32_t)0x00000400) /*!<ADC continue scan convert mode */
#define ADCR_ALIGN ((uint32_t)0x00000800)
#define ADCR_ALIGN_LEFT ((uint32_t)0x00000800) /*!<ADC data left align */
#define ADCR_ALIGN_RIGHT ((uint32_t)0x00000000) /*!<ADC data right align */
#define ADCR_CMPCH ((uint32_t)0x0000F000) /*!<CMPCH[15:12] ADC window compare channel0 convert data */
#define ADCR_CMPCH_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define ADCR_CMPCH_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define ADCR_CMPCH_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define ADCR_CMPCH_3 ((uint32_t)0x00008000) /*!<Bit 3 */
/******************** Bit definition for ADCHS register ********************/
#define ADCHS_CHEN0 ((uint32_t)0x00000001) /*!<ADC channel0 enable */
#define ADCHS_CHEN1 ((uint32_t)0x00000002) /*!<ADC channel1 enable */
#define ADCHS_CHEN2 ((uint32_t)0x00000004) /*!<ADC channel2 enable */
#define ADCHS_CHEN3 ((uint32_t)0x00000008) /*!<ADC channel3 enable */
#define ADCHS_CHEN4 ((uint32_t)0x00000010) /*!<ADC channel4 enable */
#define ADCHS_CHEN5 ((uint32_t)0x00000020) /*!<ADC channel5 enable */
#define ADCHS_CHEN6 ((uint32_t)0x00000040) /*!<ADC channel6 enable */
// #define ADCHS_CHEN7 ((uint32_t)0x00000080) /*!<ADC channel7 enable */
#define ADCHS_CHENTS ((uint32_t)0x00000080) /*!<ADC voltage sensor enable */
#define ADCHS_CHENVS ((uint32_t)0x00000100) /*!<ADC temperature sensor enable */
/******************** Bit definition for ADCMPR register ********************/
#define ADCMPR_CMPLDATA ((uint32_t)0x00000FFF) /*!<ADC 12bit window compare DOWN LEVEL DATA*/
#define ADCMPR_CMPHDATA ((uint32_t)0x0FFF0000) /*!<ADC 12bit window compare UP LEVEL DATA*/
/******************** Bit definition for ADSTA register ********************/
#define ADSTA_ADIF ((uint32_t)0x00000001) /*!<ADC convert complete flag*/
#define ADSTA_ADWIF ((uint32_t)0x00000002) /*!<ADC compare flag*/
#define ADSTA_BUSY ((uint32_t)0x00000004) /*!<ADC busy flag*/
#define ADSTA_CHANNEL ((uint32_t)0x000001F0) /*!<CHANNEL[8:4] ADC current channel*/
#define ADSTA_CHANNEL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define ADSTA_CHANNEL_1 ((uint32_t)0x00000020) /*!<Bit 1*/
#define ADSTA_CHANNEL_2 ((uint32_t)0x00000040) /*!<Bit 2*/
#define ADSTA_CHANNEL_3 ((uint32_t)0x00000080) /*!<Bit 3*/
#define ADSTA_CHANNEL_4 ((uint32_t)0x00000100) /*!<Bit 4*/
#define ADSTA_VALID ((uint32_t)0x0001FE00) /*!<VALID[16:9] ADC channel0 valid flag*/
#define ADSTA_VALID_0 ((uint32_t)0x00000200) /*!<Bit 0*/
#define ADSTA_VALID_1 ((uint32_t)0x00000400) /*!<Bit 1*/
#define ADSTA_VALID_2 ((uint32_t)0x00000800) /*!<Bit 2*/
#define ADSTA_VALID_3 ((uint32_t)0x00001000) /*!<Bit 3*/
#define ADSTA_VALID_4 ((uint32_t)0x00002000) /*!<Bit 4*/
#define ADSTA_VALID_5 ((uint32_t)0x00004000) /*!<Bit 5*/
#define ADSTA_VALID_6 ((uint32_t)0x00008000) /*!<Bit 6*/
#define ADSTA_VALID_7 ((uint32_t)0x00010000) /*!<Bit 7*/
#define ADSTA_OVERRUN ((uint32_t)0x1FF00000) /*!<OVERRUN[28:20] ADC channel0 data covered flag*/
#define ADSTA_OVERRUN_0 ((uint32_t)0x00100000) /*!<Bit 0*/
#define ADSTA_OVERRUN_1 ((uint32_t)0x00200000) /*!<Bit 1*/
#define ADSTA_OVERRUN_2 ((uint32_t)0x00400000) /*!<Bit 2*/
#define ADSTA_OVERRUN_3 ((uint32_t)0x00800000) /*!<Bit 3*/
#define ADSTA_OVERRUN_4 ((uint32_t)0x01000000) /*!<Bit 4*/
#define ADSTA_OVERRUN_5 ((uint32_t)0x02000000) /*!<Bit 5*/
#define ADSTA_OVERRUN_6 ((uint32_t)0x04000000) /*!<Bit 6*/
#define ADSTA_OVERRUN_7 ((uint32_t)0x08000000) /*!<Bit 7*/
#define ADSTA_OVERRUN_8 ((uint32_t)0x10000000) /*!<Bit 8*/
/******************** Bit definition for ADDR0~ADDR8 register ********************/
#define ADDR_DATA ((uint32_t)0x00000FFF) /*!<ADC channel convert data */
#define ADDR_OVERRUN ((uint32_t)0x00100000) /*!<ADC data covered flag */
#define ADDR_VALID ((uint32_t)0x00200000) /*!<ADC data valid flag*/
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
/****************** Bit definition for TIM_CCMR1 register (Output capture) *******************/
#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
#define TIM_BDTR_DOE ((uint32_t)0x00010000) /*!<Direct output enable */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Real-Time Clock */
/* */
/******************************************************************************/
/******************* Bit definition for RTC_CRH register ********************/
#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */
#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */
#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */
/******************* Bit definition for RTC_CRL register ********************/
#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */
#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */
#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */
#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */
#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */
#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */
/******************* Bit definition for RTC_PRLH register *******************/
#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */
/******************* Bit definition for RTC_PRLL register *******************/
#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */
/******************* Bit definition for RTC_DIVH register *******************/
#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */
/******************* Bit definition for RTC_DIVL register *******************/
#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */
/******************* Bit definition for RTC_CNTH register *******************/
#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */
/******************* Bit definition for RTC_CNTL register *******************/
#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */
/******************* Bit definition for RTC_ALRH register *******************/
#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */
/******************* Bit definition for RTC_ALRL register *******************/
#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
/******************* Bit definition for IWDG_CTRL register ********************/
#define IWDG_CTRL_IRQ_SEL ((uint8_t)0x01)
#define IWDG_CTRL_IRQ_CLR ((uint8_t)0x02)
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 ((uint8_t)0x01) /*!<Bit 0 */
#define WWDG_CR_T_1 ((uint8_t)0x02) /*!<Bit 1 */
#define WWDG_CR_T_2 ((uint8_t)0x04) /*!<Bit 2 */
#define WWDG_CR_T_3 ((uint8_t)0x08) /*!<Bit 3 */
#define WWDG_CR_T_4 ((uint8_t)0x10) /*!<Bit 4 */
#define WWDG_CR_T_5 ((uint8_t)0x20) /*!<Bit 5 */
#define WWDG_CR_T_6 ((uint8_t)0x40) /*!<Bit 6 */
#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 ((uint16_t)0x0080) /*!<Bit 0 */
#define WWDG_CFR_WDGTB_1 ((uint16_t)0x0100) /*!<Bit 1 */
#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
/******************************************************************************/
/* */
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
/******************* Bit definition for SPI_TXREG register ********************/
#define SPI_TXREG_TXREG ((uint32_t)0xFFFFFFFF)
/******************* Bit definition for SPI_RXREG register ********************/
#define SPI_RXREG_RXREG ((uint32_t)0xFFFFFFFF)
/******************* Bit definition for SPI_CSTAT register ********************/
#define SPI_CSTAT_TXEPT ((uint8_t)0x01)
#define SPI_CSTAT_RXAVL ((uint8_t)0x02)
#define SPI_CSTAT_TXFULL ((uint8_t)0x04)
#define SPI_CSTAT_RXAVL_4BYTE ((uint8_t)0x08)
/******************* Bit definition for SPI_INTSTAT register ********************/
#define SPI_INTSTAT_TX_INTF ((uint16_t)0x0001)
#define SPI_INTSTAT_RX_INTF ((uint16_t)0x0002)
#define SPI_INTSTAT_UNDERRUN_INTF ((uint16_t)0x0004)
#define SPI_INTSTAT_RXOERR_INTF ((uint16_t)0x0008)
#define SPI_INTSTAT_RXMATCH_INTF ((uint16_t)0x0010)
#define SPI_INTSTAT_RXFULL_INTF ((uint16_t)0x0020)
#define SPI_INTSTAT_TXEPT_INTF ((uint16_t)0x0040)
/******************* Bit definition for SPI_INTEN register ********************/
#define SPI_INTEN_TX_IEN ((uint16_t)0x0001)
#define SPI_INTEN_RX_IEN ((uint16_t)0x0002)
#define SPI_INTEN_UNDERRUN_IEN ((uint16_t)0x0004)
#define SPI_INTEN_RXOERR_IEN ((uint16_t)0x0008)
#define SPI_INTEN_RXMATCH_IEN ((uint16_t)0x0010)
#define SPI_INTEN_RXFULL_IEN ((uint16_t)0x0020)
#define SPI_INTEN_TXEPT_IEN ((uint16_t)0x0040)
/******************* Bit definition for SPI_INTCLR register ********************/
#define SPI_INTCLR_TX_ICLR ((uint16_t)0x0001)
#define SPI_INTCLR_RX_ICLR ((uint16_t)0x0002)
#define SPI_INTCLR_UNDERRUN_ICLR ((uint16_t)0x0004)
#define SPI_INTCLR_RXOERR_ICLR ((uint16_t)0x0008)
#define SPI_INTCLR_RXMATCH_ICLR ((uint16_t)0x0010)
#define SPI_INTCLR_RXFULL_ICLR ((uint16_t)0x0020)
#define SPI_INTCLR_TXEPT_ICLR ((uint16_t)0x0040)
/******************* Bit definition for SPI_GCTL register ********************/
#define SPI_GCTL_SPIEN ((uint16_t)0x0001)
#define SPI_GCTL_INT_EN ((uint16_t)0x0002)
#define SPI_GCTL_MM ((uint16_t)0x0004)
#define SPI_GCTL_TXEN ((uint16_t)0x0008)
#define SPI_GCTL_RXEN ((uint16_t)0x0010)
#define SPI_GCTL_RXTLF ((uint16_t)0x0060)
#define SPI_GCTL_TXTLF ((uint16_t)0x0180)
#define SPI_GCTL_DMAEN ((uint16_t)0x0200)
#define SPI_GCTL_NSS_SEL ((uint16_t)0x0400)
#define SPI_GCTL_DATA_SEL ((uint16_t)0x0800)
/******************* Bit definition for SPI_CCTL register ********************/
#define SPI_CCTL_CPHA ((uint16_t)0x0001)
#define SPI_CCTL_CPOL ((uint16_t)0x0002)
#define SPI_CCTL_LSBFE ((uint16_t)0x0004)
#define SPI_CCTL_SPILEN ((uint16_t)0x0008)
#define SPI_CCTL_RXEDGE ((uint16_t)0x0010)
#define SPI_CCTL_TXEDGE ((uint16_t)0x0020)
/******************* Bit definition for SPI_SPBRG register ********************/
#define SPI_SPBRG_SPBRG ((uint16_t)0xFFFF)
/******************* Bit definition for SPI_RXDNR register ********************/
#define SPI_RXDNR_RXDNR ((uint16_t)0xFFFF)
/******************* Bit definition for SPI_NSSR register ********************/
#define SPI_NSSR_NSS ((uint8_t)0x01)
/******************* Bit definition for SPI_EXTCTL register ********************/
#define SPI_EXTCTL_EXTLEN ((uint8_t)0x1F)
#define SPI_EXTCTL_EXTLEN_0 ((uint8_t)0x01)
#define SPI_EXTCTL_EXTLEN_1 ((uint8_t)0x02)
#define SPI_EXTCTL_EXTLEN_2 ((uint8_t)0x04)
#define SPI_EXTCTL_EXTLEN_3 ((uint8_t)0x08)
#define SPI_EXTCTL_EXTLEN_4 ((uint8_t)0x10)
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CON register ********************/
#define I2C_CON_MASTER_MODE ((uint16_t)0x0001)
#define I2C_CON_SPEED ((uint16_t)0x0006)
#define I2C_CON_SPEED_0 ((uint16_t)0x0002)
#define I2C_CON_SPEED_1 ((uint16_t)0x0004)
#define I2C_CON_10BITADDR_SLAVE ((uint16_t)0x0008)
#define I2C_CON_10BITADDR_MASTER ((uint16_t)0x0010)
#define I2C_CON_RESTART_EN ((uint16_t)0x0020)
#define I2C_CON_SLAVE_DISABLE ((uint16_t)0x0040)
#define I2C_CON_STOP_DET_IFADDRESSED ((uint16_t)0x0080)
#define I2C_CON_TX_EMPTY_CTRL ((uint16_t)0x0100)
/******************* Bit definition for I2C_TAR register ********************/
#define I2C_TAR_TAR ((uint16_t)0x03FF)
#define I2C_TAR_TAR_0 ((uint16_t)0x0001)
#define I2C_TAR_TAR_1 ((uint16_t)0x0002)
#define I2C_TAR_TAR_2 ((uint16_t)0x0004)
#define I2C_TAR_TAR_3 ((uint16_t)0x0008)
#define I2C_TAR_TAR_4 ((uint16_t)0x0010)
#define I2C_TAR_TAR_5 ((uint16_t)0x0020)
#define I2C_TAR_TAR_6 ((uint16_t)0x0040)
#define I2C_TAR_TAR_7 ((uint16_t)0x0080)
#define I2C_TAR_TAR_8 ((uint16_t)0x0100)
#define I2C_TAR_TAR_9 ((uint16_t)0x0200)
#define I2C_TAR_GC_OR_START ((uint16_t)0x0400)
#define I2C_TAR_SPECIAL ((uint16_t)0x0800)
/******************* Bit definition for I2C_SAR register ********************/
#define I2C_SAR_SAR ((uint16_t)0x03FF)
///******************* Bit definition for I2C_HS_MADDR register ********************/
//#define I2C_HS_MADDR ((uint16_t)0x0007)
/******************* Bit definition for I2C_DATA_CMD register ********************/
#define I2C_DATA_CMD_DAT ((uint16_t)0x00FF)
#define I2C_DATA_CMD_DAT_0 ((uint16_t)0x0001)
#define I2C_DATA_CMD_DAT_1 ((uint16_t)0x0002)
#define I2C_DATA_CMD_DAT_2 ((uint16_t)0x0004)
#define I2C_DATA_CMD_DAT_3 ((uint16_t)0x0008)
#define I2C_DATA_CMD_DAT_4 ((uint16_t)0x0010)
#define I2C_DATA_CMD_DAT_5 ((uint16_t)0x0020)
#define I2C_DATA_CMD_DAT_6 ((uint16_t)0x0040)
#define I2C_DATA_CMD_DAT_7 ((uint16_t)0x0080)
#define I2C_DATA_CMD_STOP ((uint16_t)0x0200)
#define I2C_DATA_CMD_RESTART ((uint16_t)0x0400)
/******************* Bit definition for I2C_SS_SCL_HCNT register ********************/
#define I2C_SS_SCL_HCNT ((uint16_t)0xFFFF)
/******************* Bit definition for I2C_SS_SCL_LCNT register ********************/
#define I2C_SS_SCL_LCNT ((uint16_t)0xFFFF)
/******************* Bit definition for I2C_FS_SCL_HCNT register ********************/
#define I2C_FS_SCL_HCNT ((uint16_t)0xFFFF)
/******************* Bit definition for I2C_FS_SCL_LCNT register ********************/
#define I2C_FS_SCL_LCNT ((uint16_t)0xFFFF)
/******************* Bit definition for I2C_FS_SCL_HCNT register ********************/
#define I2C_HS_SCL_HCNT ((uint16_t)0xFFFF)
/******************* Bit definition for I2C_FS_SCL_LCNT register ********************/
#define I2C_HS_SCL_LCNT ((uint16_t)0xFFFF)
/******************* Bit definition for I2C_INTR_STAT register ********************/
#define I2C_INTR_STAT_RX_UNDER ((uint16_t)0x0001)
#define I2C_INTR_STAT_RX_OVER ((uint16_t)0x0002)
#define I2C_INTR_STAT_RX_FULL ((uint16_t)0x0004)
#define I2C_INTR_STAT_TX_OVER ((uint16_t)0x0008)
#define I2C_INTR_STAT_TX_EMPTY ((uint16_t)0x0010)
#define I2C_INTR_STAT_RX_REQ ((uint16_t)0x0020)
#define I2C_INTR_STAT_TX_ABRT ((uint16_t)0x0040)
#define I2C_INTR_STAT_RX_DONE ((uint16_t)0x0080)
#define I2C_INTR_STAT_ACTIVITY ((uint16_t)0x0100)
#define I2C_INTR_STAT_STOP_DET ((uint16_t)0x0200)
#define I2C_INTR_STAT_START_DET ((uint16_t)0x0400)
#define I2C_INTR_STAT_GEN_CALL ((uint16_t)0x0800)
#define I2C_INTR_STAT_RESTART_DET ((uint16_t)0x1000)
#define I2C_INTR_STAT_MST_ON_HOLD ((uint16_t)0x2000)
/******************* Bit definition for I2C_INTR_MASK register ********************/
#define I2C_INTR_MASK_RX_UNDER ((uint16_t)0x0001)
#define I2C_INTR_MASK_RX_OVER ((uint16_t)0x0002)
#define I2C_INTR_MASK_RX_FULL ((uint16_t)0x0004)
#define I2C_INTR_MASK_TX_OVER ((uint16_t)0x0008)
#define I2C_INTR_MASK_TX_EMPTY ((uint16_t)0x0010)
#define I2C_INTR_MASK_RX_REQ ((uint16_t)0x0020)
#define I2C_INTR_MASK_TX_ABRT ((uint16_t)0x0040)
#define I2C_INTR_MASK_RX_DONE ((uint16_t)0x0080)
#define I2C_INTR_MASK_ACTIVITY ((uint16_t)0x0100)
#define I2C_INTR_MASK_STOP_DET ((uint16_t)0x0200)
#define I2C_INTR_MASK_START_DET ((uint16_t)0x0400)
#define I2C_INTR_MASK_GEN_CALL ((uint16_t)0x0800)
//#define I2C_INTR_MASK_RESTART_DET ((uint16_t)0x1000)
//#define I2C_INTR_MASK_MST_ON_HOLD ((uint16_t)0x2000)
/******************* Bit definition for I2C_RAW_INTR_STAT register ********************/
#define I2C_RAW_INTR_MASK_RX_UNDER ((uint16_t)0x0001)
#define I2C_RAW_INTR_MASK_RX_OVER ((uint16_t)0x0002)
#define I2C_RAW_INTR_MASK_RX_FULL ((uint16_t)0x0004)
#define I2C_RAW_INTR_MASK_TX_OVER ((uint16_t)0x0008)
#define I2C_RAW_INTR_MASK_TX_EMPTY ((uint16_t)0x0010)
#define I2C_RAW_INTR_MASK_RX_REQ ((uint16_t)0x0020)
#define I2C_RAW_INTR_MASK_TX_ABRT ((uint16_t)0x0040)
#define I2C_RAW_INTR_MASK_RX_DONE ((uint16_t)0x0080)
#define I2C_RAW_INTR_MASK_ACTIVITY ((uint16_t)0x0100)
#define I2C_RAW_INTR_MASK_STOP_DET ((uint16_t)0x0200)
#define I2C_RAW_INTR_MASK_START_DET ((uint16_t)0x0400)
#define I2C_RAW_INTR_MASK_GEN_CALL ((uint16_t)0x0800)
//#define I2C_RAW_INTR_MASK_RESTART_DET ((uint16_t)0x1000)
//#define I2C_RAW_INTR_MASK_MST_ON_HOLD ((uint16_t)0x2000)
/******************* Bit definition for I2C_RX_TL register ********************/
#define I2C_RX_TL ((uint16_t)0x00FF)
/******************* Bit definition for I2C_TX_TL register ********************/
#define I2C_TX_TL ((uint16_t)0x00FF)
/******************* Bit definition for I2C_CLR_INTR register ********************/
#define I2C_CLR_INTR ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_RX_UNDER register ********************/
#define I2C_CLR_RX_UNDER ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_RX_OVER register ********************/
#define I2C_CLR_RX_OVER ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_TX_OVER register ********************/
#define I2C_CLR_TX_OVER ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_RD_REQ register ********************/
#define I2C_CLR_RD_REQ ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_TX_ABRT register ********************/
#define I2C_CLR_TX_ABRT ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_RX_DONE register ********************/
#define I2C_CLR_RX_DONE ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_ACTIVITY register ********************/
#define I2C_CLR_ACTIVITY ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_STOP_DET register ********************/
#define I2C_CLR_STOP_DET ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_START_DET register ********************/
#define I2C_CLR_START_DET ((uint16_t)0x0001)
/******************* Bit definition for I2C_CLR_GEN_CALL register ********************/
#define I2C_CLR_GEN_CALL ((uint16_t)0x0001)
/******************* Bit definition for I2C_ENABLE register ********************/
#define I2C_ENABLE_ENABLE ((uint16_t)0x0001)
#define I2C_ENABLE_ABORT ((uint16_t)0x0002)
/******************* Bit definition for I2C_STATUS register ********************/
#define I2C_STATUS_ACTIVITY ((uint16_t)0x0001)
#define I2C_STATUS_TFNF ((uint16_t)0x0002)
#define I2C_STATUS_TFE ((uint16_t)0x0004)
#define I2C_STATUS_RFNE ((uint16_t)0x0008)
#define I2C_STATUS_RFF ((uint16_t)0x0010)
#define I2C_STATUS_MST_ACTIVITY ((uint16_t)0x0020)
#define I2C_STATUS_SLV_ACTIVITY ((uint16_t)0x0040)
/******************* Bit definition for I2C_TXFLR register ********************/
#define I2C_TXFLR ((uint16_t)0x0003)
#define I2C_TXFLR_0 ((uint16_t)0x0001)
#define I2C_TXFLR_1 ((uint16_t)0x0002)
/******************* Bit definition for I2C_RXFLR register ********************/
#define I2C_RXFLR ((uint16_t)0x0003)
#define I2C_RXFLR_0 ((uint16_t)0x0001)
#define I2C_RXFLR_1 ((uint16_t)0x0002)
/******************* Bit definition for I2C_SDA_HOLD register ********************/
#define I2C_SDA_TX_HOLD ((uint32_t)0x0000FFFF)
#define I2C_SDA_RX_HOLD ((uint32_t)0x00FF0000)
/******************* Bit definition for I2C_DMA_CR register ********************/
#define I2C_DMA_CR_RDMAE ((uint16_t)0x0001)
#define I2C_DMA_CR_TDMAE ((uint16_t)0x0002)
/******************* Bit definition for I2C_SDA_SET_UP register ********************/
#define I2C_SDA_SETUP ((uint16_t)0x00FF)
/******************* Bit definition for I2C_ACK_GENERAL_CALL register ********************/
#define I2C_ACK_GENERAL_CALL ((uint16_t)0x0001)
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter */
/* */
/******************************************************************************/
/******************* Bit definition for UART_TDR register *******************/
#define UART_TDR_TXREG ((uint16_t)0x00FF)
/******************* Bit definition for UART_RDR register *******************/
#define UART_RDR_RXREG ((uint16_t)0x00FF)
/******************* Bit definition for UART_CSR register *******************/
#define UART_CSR_TXC ((uint16_t)0x0001)
#define UART_CSR_RXAVL ((uint16_t)0x0002)
#define UART_CSR_TXFULL ((uint16_t)0x0004)
#define UART_CSR_TXBUF_EMPTY ((uint16_t)0x0008)
/******************* Bit definition for UART_ISR register *******************/
#define UART_ISR_TX_INTF ((uint16_t)0x0001)
#define UART_ISR_RX_INTF ((uint16_t)0x0002)
#define UART_ISR_RX_TXC_INTF ((uint16_t)0x0004)
#define UART_ISR_RXOERR_INTF ((uint16_t)0x0008)
#define UART_ISR_RXPERR_INTF ((uint16_t)0x0010)
#define UART_ISR_RXFERR_INTF ((uint16_t)0x0020)
#define UART_ISR_RXBRK_INTF ((uint16_t)0x0040)
#define UART_ISR_TXBRK_INTF ((uint16_t)0x0080)
#define UART_ISR_RXB8_INTF ((uint16_t)0x0100)
/******************* Bit definition for UART_IER register *******************/
#define UART_IER_TXIEN ((uint16_t)0x0001)
#define UART_IER_RXIEN ((uint16_t)0x0002)
#define UART_IER_TXC_IEN ((uint16_t)0x0004)
#define UART_IER_RXOERREN ((uint16_t)0x0008)
#define UART_IER_RXPERREN ((uint16_t)0x0010)
#define UART_IER_RXFERREN ((uint16_t)0x0020)
#define UART_IER_RXBRKEN ((uint16_t)0x0040)
#define UART_IER_TXBRK_IEN ((uint16_t)0x0080)
#define UART_IER_RXB8_IEN ((uint16_t)0x0100)
/******************* Bit definition for UART_ICR register *******************/
#define UART_ICR_TXICLR ((uint16_t)0x0001)
#define UART_ICR_RXICLR ((uint16_t)0x0002)
#define UART_ICR_TXC_CLR ((uint16_t)0x0004)
#define UART_ICR_RXOERRCLR ((uint16_t)0x0008)
#define UART_ICR_RXPERRCLR ((uint16_t)0x0010)
#define UART_ICR_RXFERRCLR ((uint16_t)0x0020)
#define UART_ICR_RXBRKCLR ((uint16_t)0x0040)
#define UART_ICR_TXBRK_CLR ((uint16_t)0x0080)
#define UART_ICR_RXB8_CLR ((uint16_t)0x0100)
/******************* Bit definition for UART_GCR register *******************/
#define UART_GCR_UARTEN ((uint16_t)0x0001)
#define UART_GCR_DMAMODE ((uint16_t)0x0002)
#define UART_GCR_AUTOFLOWEN ((uint16_t)0x0004)
#define UART_GCR_RXEN ((uint16_t)0x0008)
#define UART_GCR_TXEN ((uint16_t)0x0010)
/******************* Bit definition for UART_CCR register *******************/
#define UART_CCR_PEN ((uint16_t)0x0001)
#define UART_CCR_PSEL ((uint16_t)0x0002)
#define UART_CCR_SPB0 ((uint16_t)0x0004)
#define UART_CCR_BRK ((uint16_t)0x0008)
#define UART_CCR_CHAR ((uint16_t)0x0030)
#define UART_CCR_CHAR_0 ((uint16_t)0x0010)
#define UART_CCR_CHAR_1 ((uint16_t)0x0020)
#define UART_CCR_SPB1 ((uint16_t)0x0040)
#define UART_CCR_B8RXD ((uint16_t)0x0080)
#define UART_CCR_B8TXD ((uint16_t)0x0100)
#define UART_CCR_B8POL ((uint16_t)0x0200)
#define UART_CCR_B8TOG ((uint16_t)0x0400)
#define UART_CCR_B8EN ((uint16_t)0x0800)
#define UART_CCR_RWU ((uint16_t)0x1000)
#define UART_CCR_WAKE ((uint16_t)0x2000)
/******************* Bit definition for UART_BRR register *******************/
#define UART_BRR_SPBRG ((uint16_t)0xFFFF)
/******************* Bit definition for UART_FRA register *******************/
#define UART_FRA_DIV_Fraction ((uint16_t)0x000F)
#define UART_FRA_DIV_Fraction_0 ((uint16_t)0x0001)
#define UART_FRA_DIV_Fraction_1 ((uint16_t)0x0002)
#define UART_FRA_DIV_Fraction_2 ((uint16_t)0x0004)
#define UART_FRA_DIV_Fraction_3 ((uint16_t)0x0008)
/******************* Bit definition for UART_RXADDR register *******************/
#define UART_RXADDR_RXADDR ((uint16_t)0x00FF)
#define UART_RXADDR_RXADDR_0 ((uint16_t)0x0001)
#define UART_RXADDR_RXADDR_1 ((uint16_t)0x0002)
#define UART_RXADDR_RXADDR_2 ((uint16_t)0x0004)
#define UART_RXADDR_RXADDR_3 ((uint16_t)0x0008)
#define UART_RXADDR_RXADDR_4 ((uint16_t)0x0010)
#define UART_RXADDR_RXADDR_5 ((uint16_t)0x0020)
#define UART_RXADDR_RXADDR_6 ((uint16_t)0x0040)
#define UART_RXADDR_RXADDR_7 ((uint16_t)0x0080)
/******************* Bit definition for UART_RXMASK register *******************/
#define UART_RXMASK_RXMASK ((uint16_t)0x00FF)
#define UART_RXMASK_RXMASK_0 ((uint16_t)0x0001)
#define UART_RXMASK_RXMASK_1 ((uint16_t)0x0002)
#define UART_RXMASK_RXMASK_2 ((uint16_t)0x0004)
#define UART_RXMASK_RXMASK_3 ((uint16_t)0x0008)
#define UART_RXMASK_RXMASK_4 ((uint16_t)0x0010)
#define UART_RXMASK_RXMASK_5 ((uint16_t)0x0020)
#define UART_RXMASK_RXMASK_6 ((uint16_t)0x0040)
#define UART_RXMASK_RXMASK_7 ((uint16_t)0x0080)
/******************* Bit definition for UART_SCR register *******************/
#define UART_SCR_SCEN ((uint16_t)0x0001)
#define UART_SCR_SCAEN ((uint16_t)0x0002)
#define UART_SCR_NACK ((uint16_t)0x0004)
#define UART_SCR_SCFCNT ((uint16_t)0x0FF0)
#define UART_SCR_SCFCNT_0 ((uint16_t)0x0010)
#define UART_SCR_SCFCNT_1 ((uint16_t)0x0020)
#define UART_SCR_SCFCNT_2 ((uint16_t)0x0040)
#define UART_SCR_SCFCNT_3 ((uint16_t)0x0080)
#define UART_SCR_SCFCNT_4 ((uint16_t)0x0100)
#define UART_SCR_SCFCNT_5 ((uint16_t)0x0200)
#define UART_SCR_SCFCNT_6 ((uint16_t)0x0400)
#define UART_SCR_SCFCNT_7 ((uint16_t)0x0800)
#define UART_SCR_HDSEL ((uint16_t)0x1000)
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/**************** Bit definition for DBGMCU_IDCODE register *****************/
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0xFFFFFFFF) /*!<Device Identifier */
/****************** Bit definition for DBGMCU_CR register *******************/
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */
#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */
#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */
#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */
#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */
#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */
/******************************************************************************/
/* */
/* FLASH and Option Bytes Registers */
/* */
/******************************************************************************/
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY ((uint8_t)0x07) /*!<LATENCY[2:0] bits (Latency) */
#define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /*!<Bit 0 */
#define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /*!<Bit 0 */
#define FLASH_ACR_LATENCY_2 ((uint8_t)0x04) /*!<Bit 1 */
#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */
#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */
#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */
/****************** Bit definition for FLASH_KEYR register ******************/
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */
/***************** Bit definition for FLASH_OPTKEYR register ****************/
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */
/****************** Bit definition for FLASH_SR register *******************/
#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */
#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */
#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */
#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */
/******************* Bit definition for FLASH_CR register *******************/
#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */
#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */
#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */
#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */
#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */
#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */
#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */
#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */
#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */
#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */
#define FLASH_CR_EEPWRE ((uint16_t)0x1000)
/******************* Bit definition for FLASH_AR register *******************/
#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */
/****************** Bit definition for FLASH_OBR register *******************/
#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
#define FLASH_OBR_neeprom_erase_unlockrdpt ((uint16_t)0x0020)
#define FLASH_OBR_Data0 ((uint32_t)0x0003FC00)
#define FLASH_OBR_Data1 ((uint32_t)0x03FC0000)
/****************** Bit definition for FLASH_WRP0R register ******************/
#define FLASH_WRP0R_WRP ((uint32_t)0xFFFFFFFF) /*!<*/
/****************** Bit definition for FLASH_WRP1R register ******************/
#define FLASH_WRP1R_WRP ((uint32_t)0xFFFFFFFF) /*!<*/
/****************** Bit definition for FLASH_WRP2R register ******************/
#define FLASH_WRP2R_WRP ((uint32_t)0xFFFFFFFF) /*!<*/
/****************** Bit definition for FLASH_WRP3R register ******************/
#define FLASH_WRP3R_WRP ((uint32_t)0xFFFFFFFF) /*!<*/
/****************** Bit definition for FLASH_SECUKEY0R register ******************/
#define FLASH_SECUKEY0R_SECU_KEY ((uint32_t)0xFFFFFFFF) /*!<*/
/****************** Bit definition for FLASH_SECUKEY1R register ******************/
#define FLASH_SECUKEY1R_SECU_KEY ((uint32_t)0xFFFFFFFF) /*!<*/
/*----------------------------------------------------------------------------*/
/******************************************************************************/
/* */
/* CAN Registers and bits */
/* */
/******************************************************************************/
/*!<common registers */
/******************* Bit definition for CAN_CMR register *******************/
#define CAN_CMR_TR ((uint16_t)0x0001)
#define CAN_CMR_AT ((uint16_t)0x0002)
#define CAN_CMR_RRB ((uint16_t)0x0004)
#define CAN_CMR_CDO ((uint16_t)0x0008)
#define CAN_CMR_GTS ((uint16_t)0x0010)
/******************* Bit definition for CAN_SR register *******************/
#define CAN_SR_RBS ((uint16_t)0x0001)
#define CAN_SR_DOS ((uint16_t)0x0002)
#define CAN_SR_TBS ((uint16_t)0x0004)
#define CAN_SR_TCS ((uint16_t)0x0008)
#define CAN_SR_RS ((uint16_t)0x0010)
#define CAN_SR_TS ((uint16_t)0x0020)
#define CAN_SR_ES ((uint16_t)0x0040)
#define CAN_SR_BS ((uint16_t)0x0080)
/******************* Bit definition for CAN_IR register *******************/
#define CAN_IR_RI ((uint16_t)0x0001)
#define CAN_IR_TI ((uint16_t)0x0002)
#define CAN_IR_EI ((uint16_t)0x0004)
#define CAN_IR_DOI ((uint16_t)0x0008)
#define CAN_IR_EPI ((uint16_t)0x0020) /*PeliCAN*/
#define CAN_IR_ALI ((uint16_t)0x0040) /*PeliCAN*/
#define CAN_IR_BIE ((uint16_t)0x0080) /*PeliCAN*/
/******************* Bit definition for CAN_BTR0 register *******************/
#define CAN_BTR0_BRP ((uint16_t)0x003F)
#define CAN_BTR0_BRP_0 ((uint16_t)0x0001)
#define CAN_BTR0_BRP_1 ((uint16_t)0x0002)
#define CAN_BTR0_BRP_2 ((uint16_t)0x0004)
#define CAN_BTR0_BRP_3 ((uint16_t)0x0008)
#define CAN_BTR0_BRP_4 ((uint16_t)0x0010)
#define CAN_BTR0_BRP_5 ((uint16_t)0x0020)
#define CAN_BTR0_SJW ((uint16_t)0x00C0)
#define CAN_BTR0_SJW_0 ((uint16_t)0x0040)
#define CAN_BTR0_SJW_1 ((uint16_t)0x0080)
/******************* Bit definition for CAN_BTR1 register *******************/
#define CAN_BTR1_SAM ((uint16_t)0x0080)
#define CAN_BTR1_TSEG1 ((uint16_t)0x000F)
#define CAN_BTR1_TSEG1_0 ((uint16_t)0x0001)
#define CAN_BTR1_TSEG1_1 ((uint16_t)0x0002)
#define CAN_BTR1_TSEG1_2 ((uint16_t)0x0004)
#define CAN_BTR1_TSEG1_3 ((uint16_t)0x0008)
#define CAN_BTR1_TSEG2 ((uint16_t)0x0070)
#define CAN_BTR1_TSEG2_0 ((uint16_t)0x0010)
#define CAN_BTR1_TSEG2_1 ((uint16_t)0x0020)
#define CAN_BTR1_TSEG2_2 ((uint16_t)0x0040)
/******************* Bit definition for CAN_CDR register *******************/
#define CAN_CDR_MODE ((uint16_t)0x0080)
/*!<BasicCAN registers */
/******************* Bit definition for CAN_CR register *******************/
#define CAN_CR_RR ((uint16_t)0x0001)
#define CAN_CR_RIE ((uint16_t)0x0002)
#define CAN_CR_TIE ((uint16_t)0x0004)
#define CAN_CR_EIE ((uint16_t)0x0008)
#define CAN_CR_OIE ((uint16_t)0x0010)
/******************* Bit definition for CAN_ACR register *******************/
#define CAN_ACR_AC ((uint16_t)0x00FF)
#define CAN_ACR_AC_0 ((uint16_t)0x0001)
#define CAN_ACR_AC_1 ((uint16_t)0x0002)
#define CAN_ACR_AC_2 ((uint16_t)0x0004)
#define CAN_ACR_AC_3 ((uint16_t)0x0008)
#define CAN_ACR_AC_4 ((uint16_t)0x0010)
#define CAN_ACR_AC_5 ((uint16_t)0x0020)
#define CAN_ACR_AC_6 ((uint16_t)0x0040)
#define CAN_ACR_AC_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_AMR register *******************/
#define CAN_AMR_AM ((uint16_t)0x00FF)
#define CAN_AMR_AM_0 ((uint16_t)0x0001)
#define CAN_AMR_AM_1 ((uint16_t)0x0002)
#define CAN_AMR_AM_2 ((uint16_t)0x0004)
#define CAN_AMR_AM_3 ((uint16_t)0x0008)
#define CAN_AMR_AM_4 ((uint16_t)0x0010)
#define CAN_AMR_AM_5 ((uint16_t)0x0020)
#define CAN_AMR_AM_6 ((uint16_t)0x0040)
#define CAN_AMR_AM_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_TXID0 register *******************/
#define CAN_TXID0_ID ((uint16_t)0x00FF)
#define CAN_TXID0_ID_3 ((uint16_t)0x0001)
#define CAN_TXID0_ID_4 ((uint16_t)0x0002)
#define CAN_TXID0_ID_5 ((uint16_t)0x0004)
#define CAN_TXID0_ID_6 ((uint16_t)0x0008)
#define CAN_TXID0_ID_7 ((uint16_t)0x0010)
#define CAN_TXID0_ID_8 ((uint16_t)0x0020)
#define CAN_TXID0_ID_9 ((uint16_t)0x0040)
#define CAN_TXID0_ID_10 ((uint16_t)0x0080)
/******************* Bit definition for CAN_TXID1 register *******************/
#define CAN_TXID1_DLC ((uint16_t)0x000F)
#define CAN_TXID1_DLC_0 ((uint16_t)0x0001)
#define CAN_TXID1_DLC_1 ((uint16_t)0x0002)
#define CAN_TXID1_DLC_2 ((uint16_t)0x0004)
#define CAN_TXID1_DLC_3 ((uint16_t)0x0008)
#define CAN_TXID1_RTR ((uint16_t)0x0010)
#define CAN_TXID1_ID ((uint16_t)0x00E0)
#define CAN_TXID1_ID_0 ((uint16_t)0x0020)
#define CAN_TXID1_ID_1 ((uint16_t)0x0040)
#define CAN_TXID1_ID_2 ((uint16_t)0x0080)
/******************* Bit definition for CAN_TXDR0 register *******************/
#define CAN_TXDR0 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXDR1 register *******************/
#define CAN_TXDR1 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXDR2 register *******************/
#define CAN_TXDR2 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXDR3 register *******************/
#define CAN_TXDR3 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXDR4 register *******************/
#define CAN_TXDR4 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXDR5 register *******************/
#define CAN_TXDR5 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXDR6 register *******************/
#define CAN_TXDR6 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXDR7 register *******************/
#define CAN_TXDR7 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXID1 register *******************/
#define CAN_RXID1_ID ((uint16_t)0x00FF)
#define CAN_RXID1_ID_3 ((uint16_t)0x0001)
#define CAN_RXID1_ID_4 ((uint16_t)0x0002)
#define CAN_RXID1_ID_5 ((uint16_t)0x0004)
#define CAN_RXID1_ID_6 ((uint16_t)0x0008)
#define CAN_RXID1_ID_7 ((uint16_t)0x0010)
#define CAN_RXID1_ID_8 ((uint16_t)0x0020)
#define CAN_RXID1_ID_9 ((uint16_t)0x0040)
#define CAN_RXID1_ID_10 ((uint16_t)0x0080)
/******************* Bit definition for CAN_RXID2 register *******************/
#define CAN_RXID2_RTR ((uint16_t)0x0010)
#define CAN_RXID2_DLC ((uint16_t)0x000F)
#define CAN_RXID2_DLC_0 ((uint16_t)0x0001)
#define CAN_RXID2_DLC_1 ((uint16_t)0x0002)
#define CAN_RXID2_DLC_2 ((uint16_t)0x0004)
#define CAN_RXID2_DLC_3 ((uint16_t)0x0008)
#define CAN_RXID2_ID ((uint16_t)0x00E0)
#define CAN_RXID2_ID_0 ((uint16_t)0x0020)
#define CAN_RXID2_ID_1 ((uint16_t)0x0040)
#define CAN_RXID2_ID_2 ((uint16_t)0x0080)
/******************* Bit definition for CAN_RXDR0 register *******************/
#define CAN_RXDR0 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXDR1 register *******************/
#define CAN_RXDR1 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXDR2 register *******************/
#define CAN_RXDR2 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXDR3 register *******************/
#define CAN_RXDR3 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXDR4 register *******************/
#define CAN_RXDR4 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXDR5 register *******************/
#define CAN_RXDR5 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXDR6 register *******************/
#define CAN_RXDR6 ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXDR7 register *******************/
#define CAN_RXDR7 ((uint16_t)0x00FF)
/*!<PeliCAN registers */
/******************* Bit definition for CAN_MOD register *******************/
#define CAN_MOD_RM ((uint16_t)0x0001)
#define CAN_MOD_LOM ((uint16_t)0x0002)
#define CAN_MOD_STM ((uint16_t)0x0004)
#define CAN_MOD_AFM ((uint16_t)0x0008)
/******************* Bit definition for CAN_IER register *******************/
#define CAN_IER_RIE ((uint16_t)0x0001)
#define CAN_IER_TIE ((uint16_t)0x0002)
#define CAN_IER_EIE ((uint16_t)0x0004)
#define CAN_IER_DOIE ((uint16_t)0x0008)
#define CAN_IER_WUIE ((uint16_t)0x0010)
#define CAN_IER_EPIE ((uint16_t)0x0020)
#define CAN_IER_ALIE ((uint16_t)0x0040)
#define CAN_IER_BEIE ((uint16_t)0x0080)
/******************* Bit definition for CAN_ALC register *******************/
#define CAN_ALC_BITNO ((uint16_t)0x001F)
#define CAN_ALC_BITNO_0 ((uint16_t)0x0001)
#define CAN_ALC_BITNO_1 ((uint16_t)0x0002)
#define CAN_ALC_BITNO_2 ((uint16_t)0x0004)
#define CAN_ALC_BITNO_3 ((uint16_t)0x0008)
#define CAN_ALC_BITNO_4 ((uint16_t)0x0010)
/******************* Bit definition for CAN_ECC register *******************/
#define CAN_ECC_SEG ((uint16_t)0x001F)
#define CAN_ECC_SEG_0 ((uint16_t)0x0001)
#define CAN_ECC_SEG_1 ((uint16_t)0x0002)
#define CAN_ECC_SEG_2 ((uint16_t)0x0004)
#define CAN_ECC_SEG_3 ((uint16_t)0x0008)
#define CAN_ECC_SEG_4 ((uint16_t)0x0010)
#define CAN_ECC_DIR ((uint16_t)0x0020)
#define CAN_ECC_ERRC ((uint16_t)0x00C0)
#define CAN_ECC_ERRC_0 ((uint16_t)0x0040)
#define CAN_ECC_ERRC_1 ((uint16_t)0x0080)
/******************* Bit definition for CAN_EWLR register *******************/
#define CAN_EWLR_EWL ((uint16_t)0x00FF)
/******************* Bit definition for CAN_RXERR register *******************/
#define CAN_RXERR_RXERR ((uint16_t)0x00FF)
/******************* Bit definition for CAN_TXERR register *******************/
#define CAN_TXERR_TXERR ((uint16_t)0x00FF)
/******************* Bit definition for CAN_FF register *******************/
#define CAN_SFF_DLC ((uint16_t)0x000F)
#define CAN_SFF_DLC_0 ((uint16_t)0x0001)
#define CAN_SFF_DLC_1 ((uint16_t)0x0002)
#define CAN_SFF_DLC_2 ((uint16_t)0x0004)
#define CAN_SFF_DLC_3 ((uint16_t)0x0008)
#define CAN_SFF_RTR ((uint16_t)0x0040)
#define CAN_SFF_FF ((uint16_t)0x0080)
/******************* Bit definition for CAN_ACR0 register *******************/
#define CAN_ACR0_AC ((uint16_t)0x00FF)
#define CAN_ACR0_AC_0 ((uint16_t)0x0001)
#define CAN_ACR0_AC_1 ((uint16_t)0x0002)
#define CAN_ACR0_AC_2 ((uint16_t)0x0004)
#define CAN_ACR0_AC_3 ((uint16_t)0x0008)
#define CAN_ACR0_AC_4 ((uint16_t)0x0010)
#define CAN_ACR0_AC_5 ((uint16_t)0x0020)
#define CAN_ACR0_AC_6 ((uint16_t)0x0040)
#define CAN_ACR0_AC_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_ACR1 register *******************/
#define CAN_ACR1_AC ((uint16_t)0x00FF)
#define CAN_ACR1_AC_0 ((uint16_t)0x0001)
#define CAN_ACR1_AC_1 ((uint16_t)0x0002)
#define CAN_ACR1_AC_2 ((uint16_t)0x0004)
#define CAN_ACR1_AC_3 ((uint16_t)0x0008)
#define CAN_ACR1_AC_4 ((uint16_t)0x0010)
#define CAN_ACR1_AC_5 ((uint16_t)0x0020)
#define CAN_ACR1_AC_6 ((uint16_t)0x0040)
#define CAN_ACR1_AC_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_ACR2 register *******************/
#define CAN_ACR2_AC ((uint16_t)0x00FF)
#define CAN_ACR2_AC_0 ((uint16_t)0x0001)
#define CAN_ACR2_AC_1 ((uint16_t)0x0002)
#define CAN_ACR2_AC_2 ((uint16_t)0x0004)
#define CAN_ACR2_AC_3 ((uint16_t)0x0008)
#define CAN_ACR2_AC_4 ((uint16_t)0x0010)
#define CAN_ACR2_AC_5 ((uint16_t)0x0020)
#define CAN_ACR2_AC_6 ((uint16_t)0x0040)
#define CAN_ACR2_AC_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_ACR3 register *******************/
#define CAN_ACR3_AC ((uint16_t)0x00FF)
#define CAN_ACR3_AC_0 ((uint16_t)0x0001)
#define CAN_ACR3_AC_1 ((uint16_t)0x0002)
#define CAN_ACR3_AC_2 ((uint16_t)0x0004)
#define CAN_ACR3_AC_3 ((uint16_t)0x0008)
#define CAN_ACR3_AC_4 ((uint16_t)0x0010)
#define CAN_ACR3_AC_5 ((uint16_t)0x0020)
#define CAN_ACR3_AC_6 ((uint16_t)0x0040)
#define CAN_ACR3_AC_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_AMR0 register *******************/
#define CAN_AMR0_AM ((uint16_t)0x00FF)
#define CAN_AMR0_AM_0 ((uint16_t)0x0001)
#define CAN_AMR0_AM_1 ((uint16_t)0x0002)
#define CAN_AMR0_AM_2 ((uint16_t)0x0004)
#define CAN_AMR0_AM_3 ((uint16_t)0x0008)
#define CAN_AMR0_AM_4 ((uint16_t)0x0010)
#define CAN_AMR0_AM_5 ((uint16_t)0x0020)
#define CAN_AMR0_AM_6 ((uint16_t)0x0040)
#define CAN_AMR0_AM_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_AMR1 register *******************/
#define CAN_AMR1_AM ((uint16_t)0x00FF)
#define CAN_AMR1_AM_0 ((uint16_t)0x0001)
#define CAN_AMR1_AM_1 ((uint16_t)0x0002)
#define CAN_AMR1_AM_2 ((uint16_t)0x0004)
#define CAN_AMR1_AM_3 ((uint16_t)0x0008)
#define CAN_AMR1_AM_4 ((uint16_t)0x0010)
#define CAN_AMR1_AM_5 ((uint16_t)0x0020)
#define CAN_AMR1_AM_6 ((uint16_t)0x0040)
#define CAN_AMR1_AM_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_AMR2 register *******************/
#define CAN_AMR2_AM ((uint16_t)0x00FF)
#define CAN_AMR2_AM_0 ((uint16_t)0x0001)
#define CAN_AMR2_AM_1 ((uint16_t)0x0002)
#define CAN_AMR2_AM_2 ((uint16_t)0x0004)
#define CAN_AMR2_AM_3 ((uint16_t)0x0008)
#define CAN_AMR2_AM_4 ((uint16_t)0x0010)
#define CAN_AMR2_AM_5 ((uint16_t)0x0020)
#define CAN_AMR2_AM_6 ((uint16_t)0x0040)
#define CAN_AMR2_AM_7 ((uint16_t)0x0080)
/******************* Bit definition for CAN_AMR3 register *******************/
#define CAN_AMR3_AM ((uint16_t)0x00FF)
#define CAN_AMR3_AM_0 ((uint16_t)0x0001)
#define CAN_AMR3_AM_1 ((uint16_t)0x0002)
#define CAN_AMR3_AM_2 ((uint16_t)0x0004)
#define CAN_AMR3_AM_3 ((uint16_t)0x0008)
#define CAN_AMR3_AM_4 ((uint16_t)0x0010)
#define CAN_AMR3_AM_5 ((uint16_t)0x0020)
#define CAN_AMR3_AM_6 ((uint16_t)0x0040)
#define CAN_AMR3_AM_7 ((uint16_t)0x0080)
/******************************************************************************/
/* */
/* Advanced Encryption Standard (AES) */
/* */
/******************************************************************************/
/******************* Bit definition for AES_CR register *********************/
#define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */
#define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */
#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */
#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */
#define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */
#define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */
#define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */
#define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */
#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */
#define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */
#define AES_CR_CCFIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */
#define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
#define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */
#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */
#define AES_CR_KSIZE ((uint32_t)0x000C0000)
#define AES_CR_KSIZE_0 ((uint32_t)0x00040000)
#define AES_CR_KSIZE_1 ((uint32_t)0x00080000)
#define AES_CR_FBSEL ((uint32_t)0x00300000)
#define AES_CR_FBSEL_0 ((uint32_t)0x00100000)
#define AES_CR_FBSEL_1 ((uint32_t)0x00200000)
/******************* Bit definition for AES_SR register *********************/
#define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */
#define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */
#define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */
/******************* Bit definition for AES_DINR register *******************/
#define AES_DINR ((uint32_t)0xFFFFFFFF) /*!< AES Data Input Register */
/******************* Bit definition for AES_DOUTR register ******************/
#define AES_DOUTR ((uint32_t)0xFFFFFFFF) /*!< AES Data Output Register */
/******************* Bit definition for AES_KEYR0 register ******************/
#define AES_KEYR0 ((uint32_t)0xFFFFFFFF) /*!< AES Key Register 0 */
/******************* Bit definition for AES_KEYR1 register ******************/
#define AES_KEYR1 ((uint32_t)0xFFFFFFFF) /*!< AES Key Register 1 */
/******************* Bit definition for AES_KEYR2 register ******************/
#define AES_KEYR2 ((uint32_t)0xFFFFFFFF) /*!< AES Key Register 2 */
/******************* Bit definition for AES_KEYR3 register ******************/
#define AES_KEYR3 ((uint32_t)0xFFFFFFFF) /*!< AES Key Register 3 */
/******************* Bit definition for AES_IVR0 register *******************/
#define AES_IVR0 ((uint32_t)0xFFFFFFFF) /*!< AES Initialization Vector Register 0 */
/******************* Bit definition for AES_IVR1 register *******************/
#define AES_IVR1 ((uint32_t)0xFFFFFFFF) /*!< AES Initialization Vector Register 1 */
/******************* Bit definition for AES_IVR2 register *******************/
#define AES_IVR2 ((uint32_t)0xFFFFFFFF) /*!< AES Initialization Vector Register 2 */
/******************* Bit definition for AES_IVR3 register *******************/
#define AES_IVR3 ((uint32_t)0xFFFFFFFF) /*!< AES Initialization Vector Register 3 */
/******************************************************************************/
/* */
/* Ethernet MAC Registers bits definitions */
/* */
/******************************************************************************/
/* Bit definition for Ethernet MAC Control Register register */
#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 =< r <2^k */
#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
/* Bit definition for Ethernet MAC Frame Filter Register */
#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
/* Bit definition for Ethernet MAC Hash Table High Register */
#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
/* Bit definition for Ethernet MAC Hash Table Low Register */
#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
/* Bit definition for Ethernet MAC MII Address Register */
#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
/* Bit definition for Ethernet MAC MII Data Register */
#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
/* Bit definition for Ethernet MAC Flow Control Register */
#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
/* Bit definition for Ethernet MAC VLAN Tag Register */
#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
RSVD - Filter1 Command - RSVD - Filter0 Command
Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
/* Bit definition for Ethernet MAC PMT Control and Status Register */
#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
/* Bit definition for Ethernet MAC Status Register */
#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
/* Bit definition for Ethernet MAC Interrupt Mask Register */
#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
/* Bit definition for Ethernet MAC Address0 High Register */
#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
/* Bit definition for Ethernet MAC Address0 Low Register */
#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
/* Bit definition for Ethernet MAC Address1 High Register */
#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
/* Bit definition for Ethernet MAC Address1 Low Register */
#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
/* Bit definition for Ethernet MAC Address2 High Register */
#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
/* Bit definition for Ethernet MAC Address2 Low Register */
#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
/* Bit definition for Ethernet MAC Address3 High Register */
#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
/* Bit definition for Ethernet MAC Address3 Low Register */
#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
/******************************************************************************/
/* Ethernet MMC Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet MMC Contol Register */
#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
/* Bit definition for Ethernet MMC Receive Interrupt Register */
#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmit Interrupt Register */
#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
/******************************************************************************/
/* Ethernet PTP Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
/* Bit definition for Ethernet PTP Sub-Second Increment Register */
#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
/* Bit definition for Ethernet PTP Time Stamp High Register */
#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
/* Bit definition for Ethernet PTP Time Stamp Low Register */
#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
/* Bit definition for Ethernet PTP Time Stamp High Update Register */
#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
/* Bit definition for Ethernet PTP Time Stamp Addend Register */
#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
/* Bit definition for Ethernet PTP Target Time High Register */
#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
/* Bit definition for Ethernet PTP Target Time Low Register */
#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
/* Bit definition for Ethernet PTP Time Stamp Status Register */
#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet DMA Bus Mode Register */
#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
/* Bit definition for Ethernet DMA Receive Poll Demand Register */
#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
/* Bit definition for Ethernet DMA Status Register */
#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
/* combination with EBS[2:0] for GetFlagStatus function */
#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
/* Bit definition for Ethernet DMA Operation Mode Register */
#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
/* Bit definition for Ethernet DMA Interrupt Enable Register */
#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
/**
* @}
*/
/**
* @}
*/
#ifdef USE_STDPERIPH_DRIVER
#include "HAL_conf.h"
#endif
/** @addtogroup Exported_macro
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK)))
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval : None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
/**
* @}
*/
#endif /* __MM32F103xCxE_o_H */
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2018 MindMotion ----------------------*/
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/config/rtconfig.h
|
<filename>mcu_source/Project/Internal/lpc54018_uart_server/src/config/rtconfig.h
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
#define RT_NAME_MAX 16
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_MAX 64
#define RT_TICK_PER_SECOND 1000
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_DEBUG
#define RT_USING_COMPONENTS_INIT
#define RT_DEBUG_INIT 1
//#define RT_USING_MODULE
#define RT_USING_HWTIMER
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define IDLE_THREAD_STACK_SIZE 512
/* Using Software Timer */
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
/* SECTION: IPC */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Using Dynamic Heap Management */
#define RT_USING_HEAP
#define RT_USING_MEMPOOL
//#define RT_USING_MEMHEAP_AS_HEAP
/* Using Small MM */
#define RT_USING_SMALL_MEM
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_USING_SPI
#define RT_USING_I2C
//#define RT_I2C_BIT_DEBUG
//#define RT_I2C_DEBUG
#define RT_USING_I2C_BITOPS
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 255
/* SECTION: finsh, a C-Express shell */
#define RT_USING_FINSH
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define FINSH_CMD_SIZE 120
#define RT_USING_ULOG
#define ULOG_BACKEND_USING_CONSOLE
#define ULOG_OUTPUT_TIME
#define ULOG_OUTPUT_THREAD_NAME
#define ULOG_OUTPUT_LVL LOG_LVL_DBG
/* Using symbol table */
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_THREAD_STACK_SIZE (1024*3)
/* SECTION: device filesystem */
//#define RT_USING_DFS
//#define RT_USING_DFS_ROMFS
#define RT_USING_DFS_ELMFAT
#define RT_DFS_ELM_WORD_ACCESS
#define DFS_USING_WORKDIR
/* Reentrancy (thread safe) of the FatFs module. */
#define RT_DFS_ELM_REENTRANT
/* Number of volumes (logical drives) to be used. */
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_MAX_LFN 255
/* Maximum sector size to be handled. */
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
//#define RT_USING_DFS_NFS
#define RT_NFS_HOST_EXPORT "10.193.32.65:/"
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 8
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
//#define RT_USING_LWIP
/* LwIP uses RT-Thread Memory Management */
//#define RT_LWIP_USING_RT_MEM
#define RT_LWIP_ICMP
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_DNS
#define RT_LWIP_DEBUG
#define RT_LWIP_DHCP
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 16
#define RT_LWIP_PBUF_NUM 32
#define RT_LWIP_PBUF_POOL_BUFSIZE (256 + 7)
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 0
#define RT_LWIP_IPADDR3 201
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 0
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 5
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 1048
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 6
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_ETHTHREAD_STACKSIZE 1048
/* TCP sender buffer space */
#define RT_LWIP_TCP_SND_BUF (12*1024)
/* TCP receive window. */
#define RT_LWIP_TCP_WND (2*1024)
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/bsp/lpc546xx/drv_hwtimer.c
|
<reponame>yandld/lpc_uart_server
/*
* File : drv_hwtimer.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2015-09-02 heyuanjie87 the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "common.h"
#include "ctimer.h"
#ifdef RT_USING_HWTIMER
//static void NVIC_Configuration(void)
//{
// NVIC_EnableIRQ(TIMER0_IRQn);
//}
static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state)
{
if (state == 1)
{
CTIMER_TC_Init(HW_CTIMER0, 1000*1000);
CTIMER_Stop(HW_CTIMER0);
CTIMER_TC_SetIntMode(HW_CTIMER0, HW_CTIMER_CH0, true);
}
}
static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
{
CTIMER_TC_Init(HW_CTIMER0, t);
return RT_EOK;
}
static void timer_stop(rt_hwtimer_t *timer)
{
// LPC_TIM_TypeDef *tim;
// tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
// TIM_Cmd(tim, DISABLE);
}
static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
{
// LPC_TIM_TypeDef *tim;
rt_err_t err = RT_EOK;
// tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
// switch (cmd)
// {
// case HWTIMER_CTRL_FREQ_SET:
// {
// uint32_t clk;
// uint32_t pre;
// clk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
// pre = clk / *((uint32_t*)arg) - 1;
// tim->PR = pre;
// }
// break;
// default:
// {
// err = -RT_ENOSYS;
// }
// break;
// }
return err;
}
static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
{
return CTIMER_GetCounter(0);
}
static const struct rt_hwtimer_info _info =
{
1000000, /* the maximum count frequency can be set */
2000, /* the minimum count frequency can be set */
0xFFFFFF, /* the maximum counter value */
HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */
};
static const struct rt_hwtimer_ops _ops =
{
timer_init,
timer_start,
timer_stop,
timer_counter_get,
timer_ctrl,
};
static rt_hwtimer_t _timer0;
int rt_hw_hwtimer_init(void)
{
_timer0.info = &_info;
_timer0.ops = &_ops;
rt_device_hwtimer_register(&_timer0, "timer0", NULL);
return 0;
}
void CTIMER0_IRQHandler(void)
{
CTIMER0->IR = CTIMER_IR_MR0INT_MASK;
rt_device_hwtimer_isr(&_timer0);
}
//INIT_BOARD_EXPORT(lpc_hwtimer_init);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/MKL28Z7.h
|
<filename>mcu_source/Libraries/startup/inc/MKL28Z7.h
/*
** ###################################################################
** Processors: MKL28Z512VDC7
** MKL28Z512VLH7
** MKL28Z512VLL7
** MKL28Z512VMP7
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL28SINGLERM, Rev. 0, June 1, 2015
** Version: rev. 1.12, 2015-06-03
** Build: b150603
**
** Abstract:
** CMSIS Peripheral Access Layer for MKL28Z7
**
** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2014-12-29)
** Initial version.
** - rev. 1.1 (2015-03-19)
** Make array for registers in XRDC, PCC and TRGMUX
** - rev. 1.2 (2015-03-20)
** Add vector table for intmux0
** Add IRQS for SCG, RCM, DAC, TSI
** - rev. 1.3 (2015-03-26)
** Update FGPIO and GPIO
** Update IRQ for LPIT
** - rev. 1.4 (2015-04-08)
** Group channel registers for LPIT
** - rev. 1.5 (2015-04-15)
** Group channel registers for INTMUX
** - rev. 1.6 (2015-05-06)
** Correct FOPT reset value
** Correct vector table size
** Remove parts with 256K flash size
** - rev. 1.7 (2015-05-08)
** Reduce register for XRDC
** - rev. 1.8 (2015-05-12)
** Add CMP
** DMAMUX channel count to 8
** Add PIDR for GPIO/FGPIO
** Rename PIT to LPIT in PCC
** SCG, USB register update
** SIM, TRGMUX1, TRNG, TSTMR0/1 base address update
** Add KEY related macros for WDOG
** - rev. 1.9 (2015-05-16)
** Add IRQS
** - rev. 1.10 (2015-05-30)
** Remove MTB1, MCM1 and MMDVSQ1
** - rev. 1.11 (2015-06-01)
** Remove registers for modules which are not available on single in PCC and TRGMUX
** - rev. 1.12 (2015-06-03)
** Bit 31 of TRGMUX changed to RW from RO
**
** ###################################################################
*/
/*!
* @file MKL28Z7.h
* @version 1.12
* @date 2015-06-03
* @brief CMSIS Peripheral Access Layer for MKL28Z7
*
* CMSIS Peripheral Access Layer for MKL28Z7
*/
/* ----------------------------------------------------------------------------
-- MCU activation
---------------------------------------------------------------------------- */
/* Prevention from multiple including the same memory map */
#if !defined(MKL28Z7_H_) /* Check if memory map has not been already included */
#define MKL28Z7_H_
#define MCU_MKL28Z7
/* Check if another memory map has not been also included */
#if (defined(MCU_ACTIVE))
#error MKL28Z7 memory map: There is already included another memory map. Only one memory map can be included.
#endif /* (defined(MCU_ACTIVE)) */
#define MCU_ACTIVE
#include <stdint.h>
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0100u
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x000Cu
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 80 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
/* Device specific interrupts */
DMA0_04_IRQn = 0, /**< DMA0 channel 0/4 transfer complete */
DMA0_15_IRQn = 1, /**< DMA0 channel 1/5 transfer complete */
DMA0_26_IRQn = 2, /**< DMA0 channel 2/6 transfer complete */
DMA0_37_IRQn = 3, /**< DMA0 channel 3/7 transfer complete */
CTI0_DMA0_Error_IRQn = 4, /**< CTI0 or DMA0 error */
FLEXIO0_IRQn = 5, /**< FLEXIO0 */
TPM0_IRQn = 6, /**< TPM0 single interrupt vector for all sources */
TPM1_IRQn = 7, /**< TPM1 single interrupt vector for all sources */
TPM2_IRQn = 8, /**< TPM2 single interrupt vector for all sources */
LPIT0_IRQn = 9, /**< LPIT0 interrupt */
LPSPI0_IRQn = 10, /**< LPSPI0 single interrupt vector for all sources */
LPSPI1_IRQn = 11, /**< LPSPI1 single interrupt vector for all sources */
LPUART0_IRQn = 12, /**< LPUART0 status and error */
LPUART1_IRQn = 13, /**< LPUART1 status and error */
LPI2C0_IRQn = 14, /**< LPI2C0 interrupt */
LPI2C1_IRQn = 15, /**< LPI2C1 interrupt */
Reserved32_IRQn = 16, /**< Reserved interrupt */
PORTA_IRQn = 17, /**< PORTA Pin detect */
PORTB_IRQn = 18, /**< PORTB Pin detect */
PORTC_IRQn = 19, /**< PORTC Pin detect */
PORTD_IRQn = 20, /**< PORTD Pin detect */
PORTE_IRQn = 21, /**< PORTE Pin detect */
LLWU0_IRQn = 22, /**< Low leakage wakeup 0 */
I2S0_IRQn = 23, /**< I2S0 interrupt */
USB0_IRQn = 24, /**< USB0 interrupt */
ADC0_IRQn = 25, /**< ADC0 interrupt */
LPTMR0_IRQn = 26, /**< LPTMR0 interrupt */
RTC_Seconds_IRQn = 27, /**< RTC seconds */
INTMUX0_0_IRQn = 28, /**< INTMUX0 channel 0 interrupt */
INTMUX0_1_IRQn = 29, /**< INTMUX0 channel 1 interrupt */
INTMUX0_2_IRQn = 30, /**< INTMUX0 channel 2 interrupt */
INTMUX0_3_IRQn = 31, /**< INTMUX0 channel 3 interrupt */
LPTMR1_IRQn = 32, /**< LPTMR1 interrupt (INTMUX source IRQ0) */
Reserved49_IRQn = 33, /**< Reserved interrupt */
Reserved50_IRQn = 34, /**< Reserved interrupt */
Reserved51_IRQn = 35, /**< Reserved interrupt */
LPSPI2_IRQn = 36, /**< LPSPI2 single interrupt vector for all sources (INTMUX source IRQ4) */
LPUART2_IRQn = 37, /**< LPUART2 status and error (INTMUX source IRQ5) */
EMVSIM0_IRQn = 38, /**< EMVSIM0 interrupt (INTMUX source IRQ6) */
LPI2C2_IRQn = 39, /**< LPI2C2 interrupt (INTMUX source IRQ7) */
TSI0_IRQn = 40, /**< TSI0 interrupt (INTMUX source IRQ8) */
PMC_IRQn = 41, /**< PMC interrupt (INTMUX source IRQ9) */
FTFA_IRQn = 42, /**< FTFA interrupt (INTMUX source IRQ10) */
SCG_IRQn = 43, /**< SCG interrupt (INTMUX source IRQ11) */
WDOG0_IRQn = 44, /**< WDOG0 interrupt (INTMUX source IRQ12) */
DAC0_IRQn = 45, /**< DAC0 interrupt (INTMUX source IRQ13) */
TRNG_IRQn = 46, /**< TRNG interrupt (INTMUX source IRQ14) */
RCM_IRQn = 47, /**< RCM interrupt (INTMUX source IRQ15) */
CMP0_IRQn = 48, /**< CMP0 interrupt (INTMUX source IRQ16) */
CMP1_IRQn = 49, /**< CMP1 interrupt (INTMUX source IRQ17) */
RTC_Alarm_IRQn = 50, /**< RTC Alarm interrupt (INTMUX source IRQ18) */
Reserved67_IRQn = 51, /**< Reserved interrupt */
Reserved68_IRQn = 52, /**< Reserved interrupt */
Reserved69_IRQn = 53, /**< Reserved interrupt */
Reserved70_IRQn = 54, /**< Reserved interrupt */
Reserved71_IRQn = 55, /**< Reserved interrupt */
Reserved72_IRQn = 56, /**< Reserved interrupt */
Reserved73_IRQn = 57, /**< Reserved interrupt */
Reserved74_IRQn = 58, /**< Reserved interrupt */
Reserved75_IRQn = 59, /**< Reserved interrupt */
Reserved76_IRQn = 60, /**< Reserved interrupt */
Reserved77_IRQn = 61, /**< Reserved interrupt */
Reserved78_IRQn = 62, /**< Reserved interrupt */
Reserved79_IRQn = 63 /**< Reserved interrupt */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M0 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm0plus.h" /* Core Peripheral Access Layer */
#include "system_MKL28Z7.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
__IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
__I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
__IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
__IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
__IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
__IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
__IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
__IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
__IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
__IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
__IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
__IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
__IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
__IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
__IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
__IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
uint8_t RESERVED_0[4];
__IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
__IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
__IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
__IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
} ADC_Type, *ADC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register accessors */
#define ADC_SC1_REG(base,index) ((base)->SC1[index])
#define ADC_SC1_COUNT 2
#define ADC_CFG1_REG(base) ((base)->CFG1)
#define ADC_CFG2_REG(base) ((base)->CFG2)
#define ADC_R_REG(base,index) ((base)->R[index])
#define ADC_R_COUNT 2
#define ADC_CV1_REG(base) ((base)->CV1)
#define ADC_CV2_REG(base) ((base)->CV2)
#define ADC_SC2_REG(base) ((base)->SC2)
#define ADC_SC3_REG(base) ((base)->SC3)
#define ADC_OFS_REG(base) ((base)->OFS)
#define ADC_PG_REG(base) ((base)->PG)
#define ADC_MG_REG(base) ((base)->MG)
#define ADC_CLPD_REG(base) ((base)->CLPD)
#define ADC_CLPS_REG(base) ((base)->CLPS)
#define ADC_CLP4_REG(base) ((base)->CLP4)
#define ADC_CLP3_REG(base) ((base)->CLP3)
#define ADC_CLP2_REG(base) ((base)->CLP2)
#define ADC_CLP1_REG(base) ((base)->CLP1)
#define ADC_CLP0_REG(base) ((base)->CLP0)
#define ADC_CLMD_REG(base) ((base)->CLMD)
#define ADC_CLMS_REG(base) ((base)->CLMS)
#define ADC_CLM4_REG(base) ((base)->CLM4)
#define ADC_CLM3_REG(base) ((base)->CLM3)
#define ADC_CLM2_REG(base) ((base)->CLM2)
#define ADC_CLM1_REG(base) ((base)->CLM1)
#define ADC_CLM0_REG(base) ((base)->CLM0)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH_WIDTH 5
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK 0x20u
#define ADC_SC1_DIFF_SHIFT 5
#define ADC_SC1_DIFF_WIDTH 1
#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_AIEN_WIDTH 1
#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
#define ADC_SC1_COCO_WIDTH 1
#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK_WIDTH 2
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE_WIDTH 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADLSMP_WIDTH 1
#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV_WIDTH 2
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
#define ADC_CFG1_ADLPC_WIDTH 1
#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS_WIDTH 2
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADHSC_WIDTH 1
#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_ADACKEN_WIDTH 1
#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
#define ADC_CFG2_MUXSEL_WIDTH 1
#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D_WIDTH 16
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV_WIDTH 16
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV_WIDTH 16
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL_WIDTH 2
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK 0x4u
#define ADC_SC2_DMAEN_SHIFT 2
#define ADC_SC2_DMAEN_WIDTH 1
#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACREN_WIDTH 1
#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFGT_WIDTH 1
#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ACFE_WIDTH 1
#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADTRG_WIDTH 1
#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
#define ADC_SC2_ADACT_WIDTH 1
#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS_WIDTH 2
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_AVGE_WIDTH 1
#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_ADCO_WIDTH 1
#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CALF_WIDTH 1
#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
#define ADC_SC3_CAL_WIDTH 1
#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
#define ADC_OFS_OFS_WIDTH 16
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
/* PG Bit Fields */
#define ADC_PG_PG_MASK 0xFFFFu
#define ADC_PG_PG_SHIFT 0
#define ADC_PG_PG_WIDTH 16
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
/* MG Bit Fields */
#define ADC_MG_MG_MASK 0xFFFFu
#define ADC_MG_MG_SHIFT 0
#define ADC_MG_MG_WIDTH 16
#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
/* CLPD Bit Fields */
#define ADC_CLPD_CLPD_MASK 0x3Fu
#define ADC_CLPD_CLPD_SHIFT 0
#define ADC_CLPD_CLPD_WIDTH 6
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
/* CLPS Bit Fields */
#define ADC_CLPS_CLPS_MASK 0x3Fu
#define ADC_CLPS_CLPS_SHIFT 0
#define ADC_CLPS_CLPS_WIDTH 6
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
/* CLP4 Bit Fields */
#define ADC_CLP4_CLP4_MASK 0x3FFu
#define ADC_CLP4_CLP4_SHIFT 0
#define ADC_CLP4_CLP4_WIDTH 10
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
/* CLP3 Bit Fields */
#define ADC_CLP3_CLP3_MASK 0x1FFu
#define ADC_CLP3_CLP3_SHIFT 0
#define ADC_CLP3_CLP3_WIDTH 9
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
/* CLP2 Bit Fields */
#define ADC_CLP2_CLP2_MASK 0xFFu
#define ADC_CLP2_CLP2_SHIFT 0
#define ADC_CLP2_CLP2_WIDTH 8
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
/* CLP1 Bit Fields */
#define ADC_CLP1_CLP1_MASK 0x7Fu
#define ADC_CLP1_CLP1_SHIFT 0
#define ADC_CLP1_CLP1_WIDTH 7
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
/* CLP0 Bit Fields */
#define ADC_CLP0_CLP0_MASK 0x3Fu
#define ADC_CLP0_CLP0_SHIFT 0
#define ADC_CLP0_CLP0_WIDTH 6
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
/* CLMD Bit Fields */
#define ADC_CLMD_CLMD_MASK 0x3Fu
#define ADC_CLMD_CLMD_SHIFT 0
#define ADC_CLMD_CLMD_WIDTH 6
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
/* CLMS Bit Fields */
#define ADC_CLMS_CLMS_MASK 0x3Fu
#define ADC_CLMS_CLMS_SHIFT 0
#define ADC_CLMS_CLMS_WIDTH 6
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
/* CLM4 Bit Fields */
#define ADC_CLM4_CLM4_MASK 0x3FFu
#define ADC_CLM4_CLM4_SHIFT 0
#define ADC_CLM4_CLM4_WIDTH 10
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
/* CLM3 Bit Fields */
#define ADC_CLM3_CLM3_MASK 0x1FFu
#define ADC_CLM3_CLM3_SHIFT 0
#define ADC_CLM3_CLM3_WIDTH 9
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
/* CLM2 Bit Fields */
#define ADC_CLM2_CLM2_MASK 0xFFu
#define ADC_CLM2_CLM2_SHIFT 0
#define ADC_CLM2_CLM2_WIDTH 8
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
/* CLM1 Bit Fields */
#define ADC_CLM1_CLM1_MASK 0x7Fu
#define ADC_CLM1_CLM1_SHIFT 0
#define ADC_CLM1_CLM1_WIDTH 7
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
/* CLM0 Bit Fields */
#define ADC_CLM0_CLM0_MASK 0x3Fu
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0_WIDTH 6
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE (0x40066000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
#define ADC0_BASE_PTR (ADC0)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { ADC0_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { ADC0 }
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register instance definitions */
/* ADC0 */
#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
#define ADC0_RA ADC_R_REG(ADC0,0)
#define ADC0_RB ADC_R_REG(ADC0,1)
#define ADC0_CV1 ADC_CV1_REG(ADC0)
#define ADC0_CV2 ADC_CV2_REG(ADC0)
#define ADC0_SC2 ADC_SC2_REG(ADC0)
#define ADC0_SC3 ADC_SC3_REG(ADC0)
#define ADC0_OFS ADC_OFS_REG(ADC0)
#define ADC0_PG ADC_PG_REG(ADC0)
#define ADC0_MG ADC_MG_REG(ADC0)
#define ADC0_CLPD ADC_CLPD_REG(ADC0)
#define ADC0_CLPS ADC_CLPS_REG(ADC0)
#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
#define ADC0_CLMD ADC_CLMD_REG(ADC0)
#define ADC0_CLMS ADC_CLMS_REG(ADC0)
#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
/* ADC - Register array accessors */
#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
#define ADC0_R(index) ADC_R_REG(ADC0,index)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
* @{
*/
/** CAU - Register Layout Typedef */
typedef struct {
__O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
uint8_t RESERVED_0[2048];
__O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
__O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
__O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
uint8_t RESERVED_1[20];
__I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
__I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
__I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
uint8_t RESERVED_2[20];
__O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
__O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
__O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
uint8_t RESERVED_3[20];
__O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
__O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
__O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
uint8_t RESERVED_4[84];
__O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
__O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
__O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
uint8_t RESERVED_5[20];
__O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
__O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
__O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
uint8_t RESERVED_6[276];
__O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
__O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
__O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
uint8_t RESERVED_7[20];
__O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
__O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
__O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
} CAU_Type, *CAU_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CAU - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
* @{
*/
/* CAU - Register accessors */
#define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
#define CAU_DIRECT_COUNT 16
#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
#define CAU_LDR_CA_COUNT 9
#define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
#define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
#define CAU_STR_CA_COUNT 9
#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
#define CAU_ADR_CA_COUNT 9
#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
#define CAU_RADR_CA_COUNT 9
#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
#define CAU_XOR_CA_COUNT 9
#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
#define CAU_ROTL_CA_COUNT 9
#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
#define CAU_AESC_CA_COUNT 9
#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
#define CAU_AESIC_CA_COUNT 9
/*!
* @}
*/ /* end of group CAU_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CAU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAU_Register_Masks CAU Register Masks
* @{
*/
/* DIRECT Bit Fields */
#define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT0_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT0_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
#define CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT1_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT1_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
#define CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT2_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT2_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
#define CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT3_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT3_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
#define CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT4_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT4_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
#define CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT5_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT5_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
#define CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT6_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT6_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
#define CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT7_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT7_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
#define CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT8_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT8_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
#define CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT9_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT9_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
#define CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT10_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT10_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
#define CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT11_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT11_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
#define CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT12_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT12_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
#define CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT13_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT13_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
#define CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT14_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT14_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
#define CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu
#define CAU_DIRECT_CAU_DIRECT15_SHIFT 0
#define CAU_DIRECT_CAU_DIRECT15_WIDTH 32
#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
/* LDR_CASR Bit Fields */
#define CAU_LDR_CASR_IC_MASK 0x1u
#define CAU_LDR_CASR_IC_SHIFT 0
#define CAU_LDR_CASR_IC_WIDTH 1
#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_IC_SHIFT))&CAU_LDR_CASR_IC_MASK)
#define CAU_LDR_CASR_DPE_MASK 0x2u
#define CAU_LDR_CASR_DPE_SHIFT 1
#define CAU_LDR_CASR_DPE_WIDTH 1
#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_DPE_SHIFT))&CAU_LDR_CASR_DPE_MASK)
#define CAU_LDR_CASR_VER_MASK 0xF0000000u
#define CAU_LDR_CASR_VER_SHIFT 28
#define CAU_LDR_CASR_VER_WIDTH 4
#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
/* LDR_CAA Bit Fields */
#define CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu
#define CAU_LDR_CAA_ACC_SHIFT 0
#define CAU_LDR_CAA_ACC_WIDTH 32
#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
/* LDR_CA Bit Fields */
#define CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA0_SHIFT 0
#define CAU_LDR_CA_CA0_WIDTH 32
#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
#define CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA1_SHIFT 0
#define CAU_LDR_CA_CA1_WIDTH 32
#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
#define CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA2_SHIFT 0
#define CAU_LDR_CA_CA2_WIDTH 32
#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
#define CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA3_SHIFT 0
#define CAU_LDR_CA_CA3_WIDTH 32
#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
#define CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA4_SHIFT 0
#define CAU_LDR_CA_CA4_WIDTH 32
#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
#define CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA5_SHIFT 0
#define CAU_LDR_CA_CA5_WIDTH 32
#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
#define CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA6_SHIFT 0
#define CAU_LDR_CA_CA6_WIDTH 32
#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
#define CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA7_SHIFT 0
#define CAU_LDR_CA_CA7_WIDTH 32
#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
#define CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu
#define CAU_LDR_CA_CA8_SHIFT 0
#define CAU_LDR_CA_CA8_WIDTH 32
#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
/* STR_CASR Bit Fields */
#define CAU_STR_CASR_IC_MASK 0x1u
#define CAU_STR_CASR_IC_SHIFT 0
#define CAU_STR_CASR_IC_WIDTH 1
#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_IC_SHIFT))&CAU_STR_CASR_IC_MASK)
#define CAU_STR_CASR_DPE_MASK 0x2u
#define CAU_STR_CASR_DPE_SHIFT 1
#define CAU_STR_CASR_DPE_WIDTH 1
#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_DPE_SHIFT))&CAU_STR_CASR_DPE_MASK)
#define CAU_STR_CASR_VER_MASK 0xF0000000u
#define CAU_STR_CASR_VER_SHIFT 28
#define CAU_STR_CASR_VER_WIDTH 4
#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
/* STR_CAA Bit Fields */
#define CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu
#define CAU_STR_CAA_ACC_SHIFT 0
#define CAU_STR_CAA_ACC_WIDTH 32
#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
/* STR_CA Bit Fields */
#define CAU_STR_CA_CA0_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA0_SHIFT 0
#define CAU_STR_CA_CA0_WIDTH 32
#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
#define CAU_STR_CA_CA1_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA1_SHIFT 0
#define CAU_STR_CA_CA1_WIDTH 32
#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
#define CAU_STR_CA_CA2_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA2_SHIFT 0
#define CAU_STR_CA_CA2_WIDTH 32
#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
#define CAU_STR_CA_CA3_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA3_SHIFT 0
#define CAU_STR_CA_CA3_WIDTH 32
#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
#define CAU_STR_CA_CA4_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA4_SHIFT 0
#define CAU_STR_CA_CA4_WIDTH 32
#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
#define CAU_STR_CA_CA5_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA5_SHIFT 0
#define CAU_STR_CA_CA5_WIDTH 32
#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
#define CAU_STR_CA_CA6_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA6_SHIFT 0
#define CAU_STR_CA_CA6_WIDTH 32
#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
#define CAU_STR_CA_CA7_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA7_SHIFT 0
#define CAU_STR_CA_CA7_WIDTH 32
#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
#define CAU_STR_CA_CA8_MASK 0xFFFFFFFFu
#define CAU_STR_CA_CA8_SHIFT 0
#define CAU_STR_CA_CA8_WIDTH 32
#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
/* ADR_CASR Bit Fields */
#define CAU_ADR_CASR_IC_MASK 0x1u
#define CAU_ADR_CASR_IC_SHIFT 0
#define CAU_ADR_CASR_IC_WIDTH 1
#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_IC_SHIFT))&CAU_ADR_CASR_IC_MASK)
#define CAU_ADR_CASR_DPE_MASK 0x2u
#define CAU_ADR_CASR_DPE_SHIFT 1
#define CAU_ADR_CASR_DPE_WIDTH 1
#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_DPE_SHIFT))&CAU_ADR_CASR_DPE_MASK)
#define CAU_ADR_CASR_VER_MASK 0xF0000000u
#define CAU_ADR_CASR_VER_SHIFT 28
#define CAU_ADR_CASR_VER_WIDTH 4
#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
/* ADR_CAA Bit Fields */
#define CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu
#define CAU_ADR_CAA_ACC_SHIFT 0
#define CAU_ADR_CAA_ACC_WIDTH 32
#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
/* ADR_CA Bit Fields */
#define CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA0_SHIFT 0
#define CAU_ADR_CA_CA0_WIDTH 32
#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
#define CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA1_SHIFT 0
#define CAU_ADR_CA_CA1_WIDTH 32
#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
#define CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA2_SHIFT 0
#define CAU_ADR_CA_CA2_WIDTH 32
#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
#define CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA3_SHIFT 0
#define CAU_ADR_CA_CA3_WIDTH 32
#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
#define CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA4_SHIFT 0
#define CAU_ADR_CA_CA4_WIDTH 32
#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
#define CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA5_SHIFT 0
#define CAU_ADR_CA_CA5_WIDTH 32
#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
#define CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA6_SHIFT 0
#define CAU_ADR_CA_CA6_WIDTH 32
#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
#define CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA7_SHIFT 0
#define CAU_ADR_CA_CA7_WIDTH 32
#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
#define CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu
#define CAU_ADR_CA_CA8_SHIFT 0
#define CAU_ADR_CA_CA8_WIDTH 32
#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
/* RADR_CASR Bit Fields */
#define CAU_RADR_CASR_IC_MASK 0x1u
#define CAU_RADR_CASR_IC_SHIFT 0
#define CAU_RADR_CASR_IC_WIDTH 1
#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_IC_SHIFT))&CAU_RADR_CASR_IC_MASK)
#define CAU_RADR_CASR_DPE_MASK 0x2u
#define CAU_RADR_CASR_DPE_SHIFT 1
#define CAU_RADR_CASR_DPE_WIDTH 1
#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_DPE_SHIFT))&CAU_RADR_CASR_DPE_MASK)
#define CAU_RADR_CASR_VER_MASK 0xF0000000u
#define CAU_RADR_CASR_VER_SHIFT 28
#define CAU_RADR_CASR_VER_WIDTH 4
#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
/* RADR_CAA Bit Fields */
#define CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu
#define CAU_RADR_CAA_ACC_SHIFT 0
#define CAU_RADR_CAA_ACC_WIDTH 32
#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
/* RADR_CA Bit Fields */
#define CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA0_SHIFT 0
#define CAU_RADR_CA_CA0_WIDTH 32
#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
#define CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA1_SHIFT 0
#define CAU_RADR_CA_CA1_WIDTH 32
#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
#define CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA2_SHIFT 0
#define CAU_RADR_CA_CA2_WIDTH 32
#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
#define CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA3_SHIFT 0
#define CAU_RADR_CA_CA3_WIDTH 32
#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
#define CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA4_SHIFT 0
#define CAU_RADR_CA_CA4_WIDTH 32
#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
#define CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA5_SHIFT 0
#define CAU_RADR_CA_CA5_WIDTH 32
#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
#define CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA6_SHIFT 0
#define CAU_RADR_CA_CA6_WIDTH 32
#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
#define CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA7_SHIFT 0
#define CAU_RADR_CA_CA7_WIDTH 32
#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
#define CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu
#define CAU_RADR_CA_CA8_SHIFT 0
#define CAU_RADR_CA_CA8_WIDTH 32
#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
/* XOR_CASR Bit Fields */
#define CAU_XOR_CASR_IC_MASK 0x1u
#define CAU_XOR_CASR_IC_SHIFT 0
#define CAU_XOR_CASR_IC_WIDTH 1
#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_IC_SHIFT))&CAU_XOR_CASR_IC_MASK)
#define CAU_XOR_CASR_DPE_MASK 0x2u
#define CAU_XOR_CASR_DPE_SHIFT 1
#define CAU_XOR_CASR_DPE_WIDTH 1
#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_DPE_SHIFT))&CAU_XOR_CASR_DPE_MASK)
#define CAU_XOR_CASR_VER_MASK 0xF0000000u
#define CAU_XOR_CASR_VER_SHIFT 28
#define CAU_XOR_CASR_VER_WIDTH 4
#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
/* XOR_CAA Bit Fields */
#define CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu
#define CAU_XOR_CAA_ACC_SHIFT 0
#define CAU_XOR_CAA_ACC_WIDTH 32
#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
/* XOR_CA Bit Fields */
#define CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA0_SHIFT 0
#define CAU_XOR_CA_CA0_WIDTH 32
#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
#define CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA1_SHIFT 0
#define CAU_XOR_CA_CA1_WIDTH 32
#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
#define CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA2_SHIFT 0
#define CAU_XOR_CA_CA2_WIDTH 32
#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
#define CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA3_SHIFT 0
#define CAU_XOR_CA_CA3_WIDTH 32
#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
#define CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA4_SHIFT 0
#define CAU_XOR_CA_CA4_WIDTH 32
#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
#define CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA5_SHIFT 0
#define CAU_XOR_CA_CA5_WIDTH 32
#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
#define CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA6_SHIFT 0
#define CAU_XOR_CA_CA6_WIDTH 32
#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
#define CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA7_SHIFT 0
#define CAU_XOR_CA_CA7_WIDTH 32
#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
#define CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu
#define CAU_XOR_CA_CA8_SHIFT 0
#define CAU_XOR_CA_CA8_WIDTH 32
#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
/* ROTL_CASR Bit Fields */
#define CAU_ROTL_CASR_IC_MASK 0x1u
#define CAU_ROTL_CASR_IC_SHIFT 0
#define CAU_ROTL_CASR_IC_WIDTH 1
#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_IC_SHIFT))&CAU_ROTL_CASR_IC_MASK)
#define CAU_ROTL_CASR_DPE_MASK 0x2u
#define CAU_ROTL_CASR_DPE_SHIFT 1
#define CAU_ROTL_CASR_DPE_WIDTH 1
#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_DPE_SHIFT))&CAU_ROTL_CASR_DPE_MASK)
#define CAU_ROTL_CASR_VER_MASK 0xF0000000u
#define CAU_ROTL_CASR_VER_SHIFT 28
#define CAU_ROTL_CASR_VER_WIDTH 4
#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
/* ROTL_CAA Bit Fields */
#define CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu
#define CAU_ROTL_CAA_ACC_SHIFT 0
#define CAU_ROTL_CAA_ACC_WIDTH 32
#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
/* ROTL_CA Bit Fields */
#define CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA0_SHIFT 0
#define CAU_ROTL_CA_CA0_WIDTH 32
#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
#define CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA1_SHIFT 0
#define CAU_ROTL_CA_CA1_WIDTH 32
#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
#define CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA2_SHIFT 0
#define CAU_ROTL_CA_CA2_WIDTH 32
#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
#define CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA3_SHIFT 0
#define CAU_ROTL_CA_CA3_WIDTH 32
#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
#define CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA4_SHIFT 0
#define CAU_ROTL_CA_CA4_WIDTH 32
#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
#define CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA5_SHIFT 0
#define CAU_ROTL_CA_CA5_WIDTH 32
#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
#define CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA6_SHIFT 0
#define CAU_ROTL_CA_CA6_WIDTH 32
#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
#define CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA7_SHIFT 0
#define CAU_ROTL_CA_CA7_WIDTH 32
#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
#define CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu
#define CAU_ROTL_CA_CA8_SHIFT 0
#define CAU_ROTL_CA_CA8_WIDTH 32
#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
/* AESC_CASR Bit Fields */
#define CAU_AESC_CASR_IC_MASK 0x1u
#define CAU_AESC_CASR_IC_SHIFT 0
#define CAU_AESC_CASR_IC_WIDTH 1
#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_IC_SHIFT))&CAU_AESC_CASR_IC_MASK)
#define CAU_AESC_CASR_DPE_MASK 0x2u
#define CAU_AESC_CASR_DPE_SHIFT 1
#define CAU_AESC_CASR_DPE_WIDTH 1
#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_DPE_SHIFT))&CAU_AESC_CASR_DPE_MASK)
#define CAU_AESC_CASR_VER_MASK 0xF0000000u
#define CAU_AESC_CASR_VER_SHIFT 28
#define CAU_AESC_CASR_VER_WIDTH 4
#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
/* AESC_CAA Bit Fields */
#define CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu
#define CAU_AESC_CAA_ACC_SHIFT 0
#define CAU_AESC_CAA_ACC_WIDTH 32
#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
/* AESC_CA Bit Fields */
#define CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA0_SHIFT 0
#define CAU_AESC_CA_CA0_WIDTH 32
#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
#define CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA1_SHIFT 0
#define CAU_AESC_CA_CA1_WIDTH 32
#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
#define CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA2_SHIFT 0
#define CAU_AESC_CA_CA2_WIDTH 32
#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
#define CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA3_SHIFT 0
#define CAU_AESC_CA_CA3_WIDTH 32
#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
#define CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA4_SHIFT 0
#define CAU_AESC_CA_CA4_WIDTH 32
#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
#define CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA5_SHIFT 0
#define CAU_AESC_CA_CA5_WIDTH 32
#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
#define CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA6_SHIFT 0
#define CAU_AESC_CA_CA6_WIDTH 32
#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
#define CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA7_SHIFT 0
#define CAU_AESC_CA_CA7_WIDTH 32
#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
#define CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu
#define CAU_AESC_CA_CA8_SHIFT 0
#define CAU_AESC_CA_CA8_WIDTH 32
#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
/* AESIC_CASR Bit Fields */
#define CAU_AESIC_CASR_IC_MASK 0x1u
#define CAU_AESIC_CASR_IC_SHIFT 0
#define CAU_AESIC_CASR_IC_WIDTH 1
#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_IC_SHIFT))&CAU_AESIC_CASR_IC_MASK)
#define CAU_AESIC_CASR_DPE_MASK 0x2u
#define CAU_AESIC_CASR_DPE_SHIFT 1
#define CAU_AESIC_CASR_DPE_WIDTH 1
#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_DPE_SHIFT))&CAU_AESIC_CASR_DPE_MASK)
#define CAU_AESIC_CASR_VER_MASK 0xF0000000u
#define CAU_AESIC_CASR_VER_SHIFT 28
#define CAU_AESIC_CASR_VER_WIDTH 4
#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
/* AESIC_CAA Bit Fields */
#define CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu
#define CAU_AESIC_CAA_ACC_SHIFT 0
#define CAU_AESIC_CAA_ACC_WIDTH 32
#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
/* AESIC_CA Bit Fields */
#define CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA0_SHIFT 0
#define CAU_AESIC_CA_CA0_WIDTH 32
#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
#define CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA1_SHIFT 0
#define CAU_AESIC_CA_CA1_WIDTH 32
#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
#define CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA2_SHIFT 0
#define CAU_AESIC_CA_CA2_WIDTH 32
#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
#define CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA3_SHIFT 0
#define CAU_AESIC_CA_CA3_WIDTH 32
#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
#define CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA4_SHIFT 0
#define CAU_AESIC_CA_CA4_WIDTH 32
#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
#define CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA5_SHIFT 0
#define CAU_AESIC_CA_CA5_WIDTH 32
#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
#define CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA6_SHIFT 0
#define CAU_AESIC_CA_CA6_WIDTH 32
#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
#define CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA7_SHIFT 0
#define CAU_AESIC_CA_CA7_WIDTH 32
#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
#define CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu
#define CAU_AESIC_CA_CA8_SHIFT 0
#define CAU_AESIC_CA_CA8_WIDTH 32
#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
/*!
* @}
*/ /* end of group CAU_Register_Masks */
/* CAU - Peripheral instance base addresses */
/** Peripheral CAU0 base address */
#define CAU0_BASE (0xF0005000u)
/** Peripheral CAU0 base pointer */
#define CAU0 ((CAU_Type *)CAU0_BASE)
#define CAU0_BASE_PTR (CAU0)
/** Array initializer of CAU peripheral base addresses */
#define CAU_BASE_ADDRS { CAU0_BASE }
/** Array initializer of CAU peripheral base pointers */
#define CAU_BASE_PTRS { CAU0 }
/* ----------------------------------------------------------------------------
-- CAU - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
* @{
*/
/* CAU - Register instance definitions */
/* CAU0 */
#define CAU_DIRECT0 CAU_DIRECT_REG(CAU0,0)
#define CAU_DIRECT1 CAU_DIRECT_REG(CAU0,1)
#define CAU_DIRECT2 CAU_DIRECT_REG(CAU0,2)
#define CAU_DIRECT3 CAU_DIRECT_REG(CAU0,3)
#define CAU_DIRECT4 CAU_DIRECT_REG(CAU0,4)
#define CAU_DIRECT5 CAU_DIRECT_REG(CAU0,5)
#define CAU_DIRECT6 CAU_DIRECT_REG(CAU0,6)
#define CAU_DIRECT7 CAU_DIRECT_REG(CAU0,7)
#define CAU_DIRECT8 CAU_DIRECT_REG(CAU0,8)
#define CAU_DIRECT9 CAU_DIRECT_REG(CAU0,9)
#define CAU_DIRECT10 CAU_DIRECT_REG(CAU0,10)
#define CAU_DIRECT11 CAU_DIRECT_REG(CAU0,11)
#define CAU_DIRECT12 CAU_DIRECT_REG(CAU0,12)
#define CAU_DIRECT13 CAU_DIRECT_REG(CAU0,13)
#define CAU_DIRECT14 CAU_DIRECT_REG(CAU0,14)
#define CAU_DIRECT15 CAU_DIRECT_REG(CAU0,15)
#define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU0)
#define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU0)
#define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU0,0)
#define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU0,1)
#define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU0,2)
#define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU0,3)
#define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU0,4)
#define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU0,5)
#define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU0,6)
#define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU0,7)
#define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU0,8)
#define CAU_STR_CASR CAU_STR_CASR_REG(CAU0)
#define CAU_STR_CAA CAU_STR_CAA_REG(CAU0)
#define CAU_STR_CA0 CAU_STR_CA_REG(CAU0,0)
#define CAU_STR_CA1 CAU_STR_CA_REG(CAU0,1)
#define CAU_STR_CA2 CAU_STR_CA_REG(CAU0,2)
#define CAU_STR_CA3 CAU_STR_CA_REG(CAU0,3)
#define CAU_STR_CA4 CAU_STR_CA_REG(CAU0,4)
#define CAU_STR_CA5 CAU_STR_CA_REG(CAU0,5)
#define CAU_STR_CA6 CAU_STR_CA_REG(CAU0,6)
#define CAU_STR_CA7 CAU_STR_CA_REG(CAU0,7)
#define CAU_STR_CA8 CAU_STR_CA_REG(CAU0,8)
#define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU0)
#define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU0)
#define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU0,0)
#define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU0,1)
#define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU0,2)
#define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU0,3)
#define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU0,4)
#define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU0,5)
#define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU0,6)
#define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU0,7)
#define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU0,8)
#define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU0)
#define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU0)
#define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU0,0)
#define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU0,1)
#define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU0,2)
#define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU0,3)
#define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU0,4)
#define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU0,5)
#define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU0,6)
#define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU0,7)
#define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU0,8)
#define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU0)
#define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU0)
#define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU0,0)
#define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU0,1)
#define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU0,2)
#define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU0,3)
#define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU0,4)
#define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU0,5)
#define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU0,6)
#define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU0,7)
#define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU0,8)
#define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU0)
#define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU0)
#define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU0,0)
#define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU0,1)
#define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU0,2)
#define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU0,3)
#define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU0,4)
#define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU0,5)
#define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU0,6)
#define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU0,7)
#define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU0,8)
#define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU0)
#define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU0)
#define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU0,0)
#define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU0,1)
#define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU0,2)
#define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU0,3)
#define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU0,4)
#define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU0,5)
#define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU0,6)
#define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU0,7)
#define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU0,8)
#define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU0)
#define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU0)
#define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU0,0)
#define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU0,1)
#define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU0,2)
#define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU0,3)
#define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU0,4)
#define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU0,5)
#define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU0,6)
#define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU0,7)
#define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU0,8)
/* CAU - Register array accessors */
#define CAU0_DIRECT(index) CAU_DIRECT_REG(CAU0,index)
#define CAU0_LDR_CA(index) CAU_LDR_CA_REG(CAU0,index)
#define CAU0_STR_CA(index) CAU_STR_CA_REG(CAU0,index)
#define CAU0_ADR_CA(index) CAU_ADR_CA_REG(CAU0,index)
#define CAU0_RADR_CA(index) CAU_RADR_CA_REG(CAU0,index)
#define CAU0_XOR_CA(index) CAU_XOR_CA_REG(CAU0,index)
#define CAU0_ROTL_CA(index) CAU_ROTL_CA_REG(CAU0,index)
#define CAU0_AESC_CA(index) CAU_AESC_CA_REG(CAU0,index)
#define CAU0_AESIC_CA(index) CAU_AESIC_CA_REG(CAU0,index)
/*!
* @}
*/ /* end of group CAU_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CAU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Register Layout Typedef */
typedef struct {
__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} CMP_Type, *CMP_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register accessors */
#define CMP_CR0_REG(base) ((base)->CR0)
#define CMP_CR1_REG(base) ((base)->CR1)
#define CMP_FPR_REG(base) ((base)->FPR)
#define CMP_SCR_REG(base) ((base)->SCR)
#define CMP_DACCR_REG(base) ((base)->DACCR)
#define CMP_MUXCR_REG(base) ((base)->MUXCR)
/*!
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/* CR0 Bit Fields */
#define CMP_CR0_HYSTCTR_MASK 0x3u
#define CMP_CR0_HYSTCTR_SHIFT 0
#define CMP_CR0_HYSTCTR_WIDTH 2
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK 0x70u
#define CMP_CR0_FILTER_CNT_SHIFT 4
#define CMP_CR0_FILTER_CNT_WIDTH 3
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
/* CR1 Bit Fields */
#define CMP_CR1_EN_MASK 0x1u
#define CMP_CR1_EN_SHIFT 0
#define CMP_CR1_EN_WIDTH 1
#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
#define CMP_CR1_OPE_MASK 0x2u
#define CMP_CR1_OPE_SHIFT 1
#define CMP_CR1_OPE_WIDTH 1
#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
#define CMP_CR1_COS_MASK 0x4u
#define CMP_CR1_COS_SHIFT 2
#define CMP_CR1_COS_WIDTH 1
#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
#define CMP_CR1_INV_MASK 0x8u
#define CMP_CR1_INV_SHIFT 3
#define CMP_CR1_INV_WIDTH 1
#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
#define CMP_CR1_PMODE_MASK 0x10u
#define CMP_CR1_PMODE_SHIFT 4
#define CMP_CR1_PMODE_WIDTH 1
#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
#define CMP_CR1_TRIGM_MASK 0x20u
#define CMP_CR1_TRIGM_SHIFT 5
#define CMP_CR1_TRIGM_WIDTH 1
#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_TRIGM_SHIFT))&CMP_CR1_TRIGM_MASK)
#define CMP_CR1_WE_MASK 0x40u
#define CMP_CR1_WE_SHIFT 6
#define CMP_CR1_WE_WIDTH 1
#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
#define CMP_CR1_SE_MASK 0x80u
#define CMP_CR1_SE_SHIFT 7
#define CMP_CR1_SE_WIDTH 1
#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
/* FPR Bit Fields */
#define CMP_FPR_FILT_PER_MASK 0xFFu
#define CMP_FPR_FILT_PER_SHIFT 0
#define CMP_FPR_FILT_PER_WIDTH 8
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
/* SCR Bit Fields */
#define CMP_SCR_COUT_MASK 0x1u
#define CMP_SCR_COUT_SHIFT 0
#define CMP_SCR_COUT_WIDTH 1
#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
#define CMP_SCR_CFF_MASK 0x2u
#define CMP_SCR_CFF_SHIFT 1
#define CMP_SCR_CFF_WIDTH 1
#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
#define CMP_SCR_CFR_MASK 0x4u
#define CMP_SCR_CFR_SHIFT 2
#define CMP_SCR_CFR_WIDTH 1
#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
#define CMP_SCR_IEF_MASK 0x8u
#define CMP_SCR_IEF_SHIFT 3
#define CMP_SCR_IEF_WIDTH 1
#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
#define CMP_SCR_IER_MASK 0x10u
#define CMP_SCR_IER_SHIFT 4
#define CMP_SCR_IER_WIDTH 1
#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
#define CMP_SCR_DMAEN_MASK 0x40u
#define CMP_SCR_DMAEN_SHIFT 6
#define CMP_SCR_DMAEN_WIDTH 1
#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
/* DACCR Bit Fields */
#define CMP_DACCR_VOSEL_MASK 0x3Fu
#define CMP_DACCR_VOSEL_SHIFT 0
#define CMP_DACCR_VOSEL_WIDTH 6
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK 0x40u
#define CMP_DACCR_VRSEL_SHIFT 6
#define CMP_DACCR_VRSEL_WIDTH 1
#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
#define CMP_DACCR_DACEN_MASK 0x80u
#define CMP_DACCR_DACEN_SHIFT 7
#define CMP_DACCR_DACEN_WIDTH 1
#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
/* MUXCR Bit Fields */
#define CMP_MUXCR_MSEL_MASK 0x7u
#define CMP_MUXCR_MSEL_SHIFT 0
#define CMP_MUXCR_MSEL_WIDTH 3
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK 0x38u
#define CMP_MUXCR_PSEL_SHIFT 3
#define CMP_MUXCR_PSEL_WIDTH 3
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
#define CMP_MUXCR_PSTM_MASK 0x80u
#define CMP_MUXCR_PSTM_SHIFT 7
#define CMP_MUXCR_PSTM_WIDTH 1
#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base address */
#define CMP0_BASE (0x4006E000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
#define CMP0_BASE_PTR (CMP0)
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x400EF000u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
#define CMP1_BASE_PTR (CMP1)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS { CMP0, CMP1 }
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register instance definitions */
/* CMP0 */
#define CMP0_CR0 CMP_CR0_REG(CMP0)
#define CMP0_CR1 CMP_CR1_REG(CMP0)
#define CMP0_FPR CMP_FPR_REG(CMP0)
#define CMP0_SCR CMP_SCR_REG(CMP0)
#define CMP0_DACCR CMP_DACCR_REG(CMP0)
#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
/* CMP1 */
#define CMP1_CR0 CMP_CR0_REG(CMP1)
#define CMP1_CR1 CMP_CR1_REG(CMP1)
#define CMP1_FPR CMP_FPR_REG(CMP1)
#define CMP1_SCR CMP_SCR_REG(CMP1)
#define CMP1_DACCR CMP_DACCR_REG(CMP1)
#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
/*!
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
* @{
*/
/** CRC - Register Layout Typedef */
typedef struct {
union { /* offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
__IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
} ACCESS16BIT;
__IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
__IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
__IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
__IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
} ACCESS8BIT;
};
union { /* offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
__IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
} GPOLY_ACCESS16BIT;
__IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
__IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
__IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
__IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
} GPOLY_ACCESS8BIT;
};
union { /* offset: 0x8 */
__IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
struct { /* offset: 0x8 */
uint8_t RESERVED_0[3];
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
} CRC_Type, *CRC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CRC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
* @{
*/
/* CRC - Register accessors */
#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
#define CRC_DATA_REG(base) ((base)->DATA)
#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
#define CRC_GPOLY_REG(base) ((base)->GPOLY)
#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
#define CRC_CTRL_REG(base) ((base)->CTRL)
#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
/*!
* @}
*/ /* end of group CRC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/* DATAL Bit Fields */
#define CRC_DATAL_DATAL_MASK 0xFFFFu
#define CRC_DATAL_DATAL_SHIFT 0
#define CRC_DATAL_DATAL_WIDTH 16
#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
/* DATAH Bit Fields */
#define CRC_DATAH_DATAH_MASK 0xFFFFu
#define CRC_DATAH_DATAH_SHIFT 0
#define CRC_DATAH_DATAH_WIDTH 16
#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
/* DATA Bit Fields */
#define CRC_DATA_LL_MASK 0xFFu
#define CRC_DATA_LL_SHIFT 0
#define CRC_DATA_LL_WIDTH 8
#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
#define CRC_DATA_LU_MASK 0xFF00u
#define CRC_DATA_LU_SHIFT 8
#define CRC_DATA_LU_WIDTH 8
#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
#define CRC_DATA_HL_MASK 0xFF0000u
#define CRC_DATA_HL_SHIFT 16
#define CRC_DATA_HL_WIDTH 8
#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
#define CRC_DATA_HU_MASK 0xFF000000u
#define CRC_DATA_HU_SHIFT 24
#define CRC_DATA_HU_WIDTH 8
#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
/* DATALL Bit Fields */
#define CRC_DATALL_DATALL_MASK 0xFFu
#define CRC_DATALL_DATALL_SHIFT 0
#define CRC_DATALL_DATALL_WIDTH 8
#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
/* DATALU Bit Fields */
#define CRC_DATALU_DATALU_MASK 0xFFu
#define CRC_DATALU_DATALU_SHIFT 0
#define CRC_DATALU_DATALU_WIDTH 8
#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
/* DATAHL Bit Fields */
#define CRC_DATAHL_DATAHL_MASK 0xFFu
#define CRC_DATAHL_DATAHL_SHIFT 0
#define CRC_DATAHL_DATAHL_WIDTH 8
#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
/* DATAHU Bit Fields */
#define CRC_DATAHU_DATAHU_MASK 0xFFu
#define CRC_DATAHU_DATAHU_SHIFT 0
#define CRC_DATAHU_DATAHU_WIDTH 8
#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
/* GPOLYL Bit Fields */
#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
#define CRC_GPOLYL_GPOLYL_SHIFT 0
#define CRC_GPOLYL_GPOLYL_WIDTH 16
#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
/* GPOLYH Bit Fields */
#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
#define CRC_GPOLYH_GPOLYH_SHIFT 0
#define CRC_GPOLYH_GPOLYH_WIDTH 16
#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
/* GPOLY Bit Fields */
#define CRC_GPOLY_LOW_MASK 0xFFFFu
#define CRC_GPOLY_LOW_SHIFT 0
#define CRC_GPOLY_LOW_WIDTH 16
#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
#define CRC_GPOLY_HIGH_SHIFT 16
#define CRC_GPOLY_HIGH_WIDTH 16
#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
/* GPOLYLL Bit Fields */
#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
#define CRC_GPOLYLL_GPOLYLL_WIDTH 8
#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
/* GPOLYLU Bit Fields */
#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
#define CRC_GPOLYLU_GPOLYLU_WIDTH 8
#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
/* GPOLYHL Bit Fields */
#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
#define CRC_GPOLYHL_GPOLYHL_WIDTH 8
#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
/* GPOLYHU Bit Fields */
#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
#define CRC_GPOLYHU_GPOLYHU_WIDTH 8
#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
/* CTRL Bit Fields */
#define CRC_CTRL_TCRC_MASK 0x1000000u
#define CRC_CTRL_TCRC_SHIFT 24
#define CRC_CTRL_TCRC_WIDTH 1
#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
#define CRC_CTRL_WAS_MASK 0x2000000u
#define CRC_CTRL_WAS_SHIFT 25
#define CRC_CTRL_WAS_WIDTH 1
#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
#define CRC_CTRL_FXOR_MASK 0x4000000u
#define CRC_CTRL_FXOR_SHIFT 26
#define CRC_CTRL_FXOR_WIDTH 1
#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
#define CRC_CTRL_TOTR_MASK 0x30000000u
#define CRC_CTRL_TOTR_SHIFT 28
#define CRC_CTRL_TOTR_WIDTH 2
#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
#define CRC_CTRL_TOT_MASK 0xC0000000u
#define CRC_CTRL_TOT_SHIFT 30
#define CRC_CTRL_TOT_WIDTH 2
#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
/* CTRLHU Bit Fields */
#define CRC_CTRLHU_TCRC_MASK 0x1u
#define CRC_CTRLHU_TCRC_SHIFT 0
#define CRC_CTRLHU_TCRC_WIDTH 1
#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
#define CRC_CTRLHU_WAS_MASK 0x2u
#define CRC_CTRLHU_WAS_SHIFT 1
#define CRC_CTRLHU_WAS_WIDTH 1
#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
#define CRC_CTRLHU_FXOR_MASK 0x4u
#define CRC_CTRLHU_FXOR_SHIFT 2
#define CRC_CTRLHU_FXOR_WIDTH 1
#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
#define CRC_CTRLHU_TOTR_MASK 0x30u
#define CRC_CTRLHU_TOTR_SHIFT 4
#define CRC_CTRLHU_TOTR_WIDTH 2
#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
#define CRC_CTRLHU_TOT_MASK 0xC0u
#define CRC_CTRLHU_TOT_SHIFT 6
#define CRC_CTRLHU_TOT_WIDTH 2
#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
/*!
* @}
*/ /* end of group CRC_Register_Masks */
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base address */
#define CRC_BASE (0x40078000u)
/** Peripheral CRC base pointer */
#define CRC0 ((CRC_Type *)CRC_BASE)
#define CRC_BASE_PTR (CRC0)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS { CRC_BASE }
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS { CRC0 }
/* ----------------------------------------------------------------------------
-- CRC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
* @{
*/
/* CRC - Register instance definitions */
/* CRC */
#define CRC_DATA CRC_DATA_REG(CRC0)
#define CRC_DATAL CRC_DATAL_REG(CRC0)
#define CRC_DATALL CRC_DATALL_REG(CRC0)
#define CRC_DATALU CRC_DATALU_REG(CRC0)
#define CRC_DATAH CRC_DATAH_REG(CRC0)
#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
#define CRC_CTRL CRC_CTRL_REG(CRC0)
#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
/*!
* @}
*/ /* end of group CRC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DAC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
* @{
*/
/** DAC - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x2 */
__IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
__IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
} DAT[16];
__IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
} DAC_Type, *DAC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DAC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
* @{
*/
/* DAC - Register accessors */
#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
#define DAC_DATL_COUNT 16
#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
#define DAC_DATH_COUNT 16
#define DAC_SR_REG(base) ((base)->SR)
#define DAC_C0_REG(base) ((base)->C0)
#define DAC_C1_REG(base) ((base)->C1)
#define DAC_C2_REG(base) ((base)->C2)
/*!
* @}
*/ /* end of group DAC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/* DATL Bit Fields */
#define DAC_DATL_DATA0_MASK 0xFFu
#define DAC_DATL_DATA0_SHIFT 0
#define DAC_DATL_DATA0_WIDTH 8
#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
/* DATH Bit Fields */
#define DAC_DATH_DATA1_MASK 0xFu
#define DAC_DATH_DATA1_SHIFT 0
#define DAC_DATH_DATA1_WIDTH 4
#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
/* SR Bit Fields */
#define DAC_SR_DACBFRPBF_MASK 0x1u
#define DAC_SR_DACBFRPBF_SHIFT 0
#define DAC_SR_DACBFRPBF_WIDTH 1
#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
#define DAC_SR_DACBFRPTF_MASK 0x2u
#define DAC_SR_DACBFRPTF_SHIFT 1
#define DAC_SR_DACBFRPTF_WIDTH 1
#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
#define DAC_SR_DACBFWMF_MASK 0x4u
#define DAC_SR_DACBFWMF_SHIFT 2
#define DAC_SR_DACBFWMF_WIDTH 1
#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
/* C0 Bit Fields */
#define DAC_C0_DACBBIEN_MASK 0x1u
#define DAC_C0_DACBBIEN_SHIFT 0
#define DAC_C0_DACBBIEN_WIDTH 1
#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
#define DAC_C0_DACBTIEN_MASK 0x2u
#define DAC_C0_DACBTIEN_SHIFT 1
#define DAC_C0_DACBTIEN_WIDTH 1
#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
#define DAC_C0_DACBWIEN_MASK 0x4u
#define DAC_C0_DACBWIEN_SHIFT 2
#define DAC_C0_DACBWIEN_WIDTH 1
#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
#define DAC_C0_LPEN_MASK 0x8u
#define DAC_C0_LPEN_SHIFT 3
#define DAC_C0_LPEN_WIDTH 1
#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
#define DAC_C0_DACSWTRG_MASK 0x10u
#define DAC_C0_DACSWTRG_SHIFT 4
#define DAC_C0_DACSWTRG_WIDTH 1
#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
#define DAC_C0_DACTRGSEL_MASK 0x20u
#define DAC_C0_DACTRGSEL_SHIFT 5
#define DAC_C0_DACTRGSEL_WIDTH 1
#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
#define DAC_C0_DACRFS_MASK 0x40u
#define DAC_C0_DACRFS_SHIFT 6
#define DAC_C0_DACRFS_WIDTH 1
#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
#define DAC_C0_DACEN_MASK 0x80u
#define DAC_C0_DACEN_SHIFT 7
#define DAC_C0_DACEN_WIDTH 1
#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
/* C1 Bit Fields */
#define DAC_C1_DACBFEN_MASK 0x1u
#define DAC_C1_DACBFEN_SHIFT 0
#define DAC_C1_DACBFEN_WIDTH 1
#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
#define DAC_C1_DACBFMD_MASK 0x6u
#define DAC_C1_DACBFMD_SHIFT 1
#define DAC_C1_DACBFMD_WIDTH 2
#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
#define DAC_C1_DACBFWM_MASK 0x18u
#define DAC_C1_DACBFWM_SHIFT 3
#define DAC_C1_DACBFWM_WIDTH 2
#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
#define DAC_C1_DMAEN_MASK 0x80u
#define DAC_C1_DMAEN_SHIFT 7
#define DAC_C1_DMAEN_WIDTH 1
#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
/* C2 Bit Fields */
#define DAC_C2_DACBFUP_MASK 0xFu
#define DAC_C2_DACBFUP_SHIFT 0
#define DAC_C2_DACBFUP_WIDTH 4
#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
#define DAC_C2_DACBFRP_MASK 0xF0u
#define DAC_C2_DACBFRP_SHIFT 4
#define DAC_C2_DACBFRP_WIDTH 4
#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
/*!
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base address */
#define DAC0_BASE (0x4006A000u)
/** Peripheral DAC0 base pointer */
#define DAC0 ((DAC_Type *)DAC0_BASE)
#define DAC0_BASE_PTR (DAC0)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS { DAC0_BASE }
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASE_PTRS { DAC0 }
/* ----------------------------------------------------------------------------
-- DAC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
* @{
*/
/* DAC - Register instance definitions */
/* DAC0 */
#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
#define DAC0_SR DAC_SR_REG(DAC0)
#define DAC0_C0 DAC_C0_REG(DAC0)
#define DAC0_C1 DAC_C1_REG(DAC0)
#define DAC0_C2 DAC_C2_REG(DAC0)
/* DAC - Register array accessors */
#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
/*!
* @}
*/ /* end of group DAC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< Control Register, offset: 0x0 */
__I uint32_t ES; /**< Error Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
uint8_t RESERVED_1[4];
__IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
__O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
__O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
__O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
__O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
uint8_t RESERVED_2[4];
__IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
uint8_t RESERVED_3[4];
__IO uint32_t ERR; /**< Error Register, offset: 0x2C */
uint8_t RESERVED_4[4];
__I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
uint8_t RESERVED_5[12];
__IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
uint8_t RESERVED_6[184];
__IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
__IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
__IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
__IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
__IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
__IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
__IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
__IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
uint8_t RESERVED_7[3832];
struct { /* offset: 0x1000, array step: 0x20 */
__IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
};
__IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
__IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
union { /* offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
};
__IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
union { /* offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[8];
} DMA_Type, *DMA_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DMA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
* @{
*/
/* DMA - Register accessors */
#define DMA_CR_REG(base) ((base)->CR)
#define DMA_ES_REG(base) ((base)->ES)
#define DMA_ERQ_REG(base) ((base)->ERQ)
#define DMA_EEI_REG(base) ((base)->EEI)
#define DMA_CEEI_REG(base) ((base)->CEEI)
#define DMA_SEEI_REG(base) ((base)->SEEI)
#define DMA_CERQ_REG(base) ((base)->CERQ)
#define DMA_SERQ_REG(base) ((base)->SERQ)
#define DMA_CDNE_REG(base) ((base)->CDNE)
#define DMA_SSRT_REG(base) ((base)->SSRT)
#define DMA_CERR_REG(base) ((base)->CERR)
#define DMA_CINT_REG(base) ((base)->CINT)
#define DMA_INT_REG(base) ((base)->INT)
#define DMA_ERR_REG(base) ((base)->ERR)
#define DMA_HRS_REG(base) ((base)->HRS)
#define DMA_EARS_REG(base) ((base)->EARS)
#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
#define DMA_SADDR_COUNT 8
#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
#define DMA_SOFF_COUNT 8
#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
#define DMA_ATTR_COUNT 8
#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
#define DMA_NBYTES_MLNO_COUNT 8
#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
#define DMA_NBYTES_MLOFFNO_COUNT 8
#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
#define DMA_NBYTES_MLOFFYES_COUNT 8
#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
#define DMA_SLAST_COUNT 8
#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
#define DMA_DADDR_COUNT 8
#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
#define DMA_DOFF_COUNT 8
#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
#define DMA_CITER_ELINKNO_COUNT 8
#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
#define DMA_CITER_ELINKYES_COUNT 8
#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
#define DMA_DLAST_SGA_COUNT 8
#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
#define DMA_CSR_COUNT 8
#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
#define DMA_BITER_ELINKNO_COUNT 8
#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
#define DMA_BITER_ELINKYES_COUNT 8
/*!
* @}
*/ /* end of group DMA_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/* CR Bit Fields */
#define DMA_CR_EDBG_MASK 0x2u
#define DMA_CR_EDBG_SHIFT 1
#define DMA_CR_EDBG_WIDTH 1
#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
#define DMA_CR_ERCA_MASK 0x4u
#define DMA_CR_ERCA_SHIFT 2
#define DMA_CR_ERCA_WIDTH 1
#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
#define DMA_CR_HOE_MASK 0x10u
#define DMA_CR_HOE_SHIFT 4
#define DMA_CR_HOE_WIDTH 1
#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
#define DMA_CR_HALT_MASK 0x20u
#define DMA_CR_HALT_SHIFT 5
#define DMA_CR_HALT_WIDTH 1
#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
#define DMA_CR_CLM_MASK 0x40u
#define DMA_CR_CLM_SHIFT 6
#define DMA_CR_CLM_WIDTH 1
#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
#define DMA_CR_EMLM_MASK 0x80u
#define DMA_CR_EMLM_SHIFT 7
#define DMA_CR_EMLM_WIDTH 1
#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
#define DMA_CR_ECX_MASK 0x10000u
#define DMA_CR_ECX_SHIFT 16
#define DMA_CR_ECX_WIDTH 1
#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
#define DMA_CR_CX_MASK 0x20000u
#define DMA_CR_CX_SHIFT 17
#define DMA_CR_CX_WIDTH 1
#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
#define DMA_CR_ACTIVE_MASK 0x80000000u
#define DMA_CR_ACTIVE_SHIFT 31
#define DMA_CR_ACTIVE_WIDTH 1
#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ACTIVE_SHIFT))&DMA_CR_ACTIVE_MASK)
/* ES Bit Fields */
#define DMA_ES_DBE_MASK 0x1u
#define DMA_ES_DBE_SHIFT 0
#define DMA_ES_DBE_WIDTH 1
#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
#define DMA_ES_SBE_MASK 0x2u
#define DMA_ES_SBE_SHIFT 1
#define DMA_ES_SBE_WIDTH 1
#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
#define DMA_ES_SGE_MASK 0x4u
#define DMA_ES_SGE_SHIFT 2
#define DMA_ES_SGE_WIDTH 1
#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
#define DMA_ES_NCE_MASK 0x8u
#define DMA_ES_NCE_SHIFT 3
#define DMA_ES_NCE_WIDTH 1
#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
#define DMA_ES_DOE_MASK 0x10u
#define DMA_ES_DOE_SHIFT 4
#define DMA_ES_DOE_WIDTH 1
#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
#define DMA_ES_DAE_MASK 0x20u
#define DMA_ES_DAE_SHIFT 5
#define DMA_ES_DAE_WIDTH 1
#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
#define DMA_ES_SOE_MASK 0x40u
#define DMA_ES_SOE_SHIFT 6
#define DMA_ES_SOE_WIDTH 1
#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
#define DMA_ES_SAE_MASK 0x80u
#define DMA_ES_SAE_SHIFT 7
#define DMA_ES_SAE_WIDTH 1
#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
#define DMA_ES_ERRCHN_MASK 0x700u
#define DMA_ES_ERRCHN_SHIFT 8
#define DMA_ES_ERRCHN_WIDTH 3
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK 0x4000u
#define DMA_ES_CPE_SHIFT 14
#define DMA_ES_CPE_WIDTH 1
#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
#define DMA_ES_ECX_MASK 0x10000u
#define DMA_ES_ECX_SHIFT 16
#define DMA_ES_ECX_WIDTH 1
#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
#define DMA_ES_VLD_MASK 0x80000000u
#define DMA_ES_VLD_SHIFT 31
#define DMA_ES_VLD_WIDTH 1
#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
/* ERQ Bit Fields */
#define DMA_ERQ_ERQ0_MASK 0x1u
#define DMA_ERQ_ERQ0_SHIFT 0
#define DMA_ERQ_ERQ0_WIDTH 1
#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
#define DMA_ERQ_ERQ1_MASK 0x2u
#define DMA_ERQ_ERQ1_SHIFT 1
#define DMA_ERQ_ERQ1_WIDTH 1
#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
#define DMA_ERQ_ERQ2_MASK 0x4u
#define DMA_ERQ_ERQ2_SHIFT 2
#define DMA_ERQ_ERQ2_WIDTH 1
#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
#define DMA_ERQ_ERQ3_MASK 0x8u
#define DMA_ERQ_ERQ3_SHIFT 3
#define DMA_ERQ_ERQ3_WIDTH 1
#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
#define DMA_ERQ_ERQ4_MASK 0x10u
#define DMA_ERQ_ERQ4_SHIFT 4
#define DMA_ERQ_ERQ4_WIDTH 1
#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
#define DMA_ERQ_ERQ5_MASK 0x20u
#define DMA_ERQ_ERQ5_SHIFT 5
#define DMA_ERQ_ERQ5_WIDTH 1
#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
#define DMA_ERQ_ERQ6_MASK 0x40u
#define DMA_ERQ_ERQ6_SHIFT 6
#define DMA_ERQ_ERQ6_WIDTH 1
#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
#define DMA_ERQ_ERQ7_MASK 0x80u
#define DMA_ERQ_ERQ7_SHIFT 7
#define DMA_ERQ_ERQ7_WIDTH 1
#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
/* EEI Bit Fields */
#define DMA_EEI_EEI0_MASK 0x1u
#define DMA_EEI_EEI0_SHIFT 0
#define DMA_EEI_EEI0_WIDTH 1
#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
#define DMA_EEI_EEI1_MASK 0x2u
#define DMA_EEI_EEI1_SHIFT 1
#define DMA_EEI_EEI1_WIDTH 1
#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
#define DMA_EEI_EEI2_MASK 0x4u
#define DMA_EEI_EEI2_SHIFT 2
#define DMA_EEI_EEI2_WIDTH 1
#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
#define DMA_EEI_EEI3_MASK 0x8u
#define DMA_EEI_EEI3_SHIFT 3
#define DMA_EEI_EEI3_WIDTH 1
#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
#define DMA_EEI_EEI4_MASK 0x10u
#define DMA_EEI_EEI4_SHIFT 4
#define DMA_EEI_EEI4_WIDTH 1
#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
#define DMA_EEI_EEI5_MASK 0x20u
#define DMA_EEI_EEI5_SHIFT 5
#define DMA_EEI_EEI5_WIDTH 1
#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
#define DMA_EEI_EEI6_MASK 0x40u
#define DMA_EEI_EEI6_SHIFT 6
#define DMA_EEI_EEI6_WIDTH 1
#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
#define DMA_EEI_EEI7_MASK 0x80u
#define DMA_EEI_EEI7_SHIFT 7
#define DMA_EEI_EEI7_WIDTH 1
#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
/* CEEI Bit Fields */
#define DMA_CEEI_CEEI_MASK 0x7u
#define DMA_CEEI_CEEI_SHIFT 0
#define DMA_CEEI_CEEI_WIDTH 3
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK 0x40u
#define DMA_CEEI_CAEE_SHIFT 6
#define DMA_CEEI_CAEE_WIDTH 1
#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
#define DMA_CEEI_NOP_MASK 0x80u
#define DMA_CEEI_NOP_SHIFT 7
#define DMA_CEEI_NOP_WIDTH 1
#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
/* SEEI Bit Fields */
#define DMA_SEEI_SEEI_MASK 0x7u
#define DMA_SEEI_SEEI_SHIFT 0
#define DMA_SEEI_SEEI_WIDTH 3
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK 0x40u
#define DMA_SEEI_SAEE_SHIFT 6
#define DMA_SEEI_SAEE_WIDTH 1
#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
#define DMA_SEEI_NOP_MASK 0x80u
#define DMA_SEEI_NOP_SHIFT 7
#define DMA_SEEI_NOP_WIDTH 1
#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
/* CERQ Bit Fields */
#define DMA_CERQ_CERQ_MASK 0x7u
#define DMA_CERQ_CERQ_SHIFT 0
#define DMA_CERQ_CERQ_WIDTH 3
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK 0x40u
#define DMA_CERQ_CAER_SHIFT 6
#define DMA_CERQ_CAER_WIDTH 1
#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
#define DMA_CERQ_NOP_MASK 0x80u
#define DMA_CERQ_NOP_SHIFT 7
#define DMA_CERQ_NOP_WIDTH 1
#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
/* SERQ Bit Fields */
#define DMA_SERQ_SERQ_MASK 0x7u
#define DMA_SERQ_SERQ_SHIFT 0
#define DMA_SERQ_SERQ_WIDTH 3
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK 0x40u
#define DMA_SERQ_SAER_SHIFT 6
#define DMA_SERQ_SAER_WIDTH 1
#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
#define DMA_SERQ_NOP_MASK 0x80u
#define DMA_SERQ_NOP_SHIFT 7
#define DMA_SERQ_NOP_WIDTH 1
#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
/* CDNE Bit Fields */
#define DMA_CDNE_CDNE_MASK 0x7u
#define DMA_CDNE_CDNE_SHIFT 0
#define DMA_CDNE_CDNE_WIDTH 3
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK 0x40u
#define DMA_CDNE_CADN_SHIFT 6
#define DMA_CDNE_CADN_WIDTH 1
#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
#define DMA_CDNE_NOP_MASK 0x80u
#define DMA_CDNE_NOP_SHIFT 7
#define DMA_CDNE_NOP_WIDTH 1
#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
/* SSRT Bit Fields */
#define DMA_SSRT_SSRT_MASK 0x7u
#define DMA_SSRT_SSRT_SHIFT 0
#define DMA_SSRT_SSRT_WIDTH 3
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK 0x40u
#define DMA_SSRT_SAST_SHIFT 6
#define DMA_SSRT_SAST_WIDTH 1
#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
#define DMA_SSRT_NOP_MASK 0x80u
#define DMA_SSRT_NOP_SHIFT 7
#define DMA_SSRT_NOP_WIDTH 1
#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
/* CERR Bit Fields */
#define DMA_CERR_CERR_MASK 0x7u
#define DMA_CERR_CERR_SHIFT 0
#define DMA_CERR_CERR_WIDTH 3
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK 0x40u
#define DMA_CERR_CAEI_SHIFT 6
#define DMA_CERR_CAEI_WIDTH 1
#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
#define DMA_CERR_NOP_MASK 0x80u
#define DMA_CERR_NOP_SHIFT 7
#define DMA_CERR_NOP_WIDTH 1
#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
/* CINT Bit Fields */
#define DMA_CINT_CINT_MASK 0x7u
#define DMA_CINT_CINT_SHIFT 0
#define DMA_CINT_CINT_WIDTH 3
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK 0x40u
#define DMA_CINT_CAIR_SHIFT 6
#define DMA_CINT_CAIR_WIDTH 1
#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
#define DMA_CINT_NOP_MASK 0x80u
#define DMA_CINT_NOP_SHIFT 7
#define DMA_CINT_NOP_WIDTH 1
#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
/* INT Bit Fields */
#define DMA_INT_INT0_MASK 0x1u
#define DMA_INT_INT0_SHIFT 0
#define DMA_INT_INT0_WIDTH 1
#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
#define DMA_INT_INT1_MASK 0x2u
#define DMA_INT_INT1_SHIFT 1
#define DMA_INT_INT1_WIDTH 1
#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
#define DMA_INT_INT2_MASK 0x4u
#define DMA_INT_INT2_SHIFT 2
#define DMA_INT_INT2_WIDTH 1
#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
#define DMA_INT_INT3_MASK 0x8u
#define DMA_INT_INT3_SHIFT 3
#define DMA_INT_INT3_WIDTH 1
#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
#define DMA_INT_INT4_MASK 0x10u
#define DMA_INT_INT4_SHIFT 4
#define DMA_INT_INT4_WIDTH 1
#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
#define DMA_INT_INT5_MASK 0x20u
#define DMA_INT_INT5_SHIFT 5
#define DMA_INT_INT5_WIDTH 1
#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
#define DMA_INT_INT6_MASK 0x40u
#define DMA_INT_INT6_SHIFT 6
#define DMA_INT_INT6_WIDTH 1
#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
#define DMA_INT_INT7_MASK 0x80u
#define DMA_INT_INT7_SHIFT 7
#define DMA_INT_INT7_WIDTH 1
#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
/* ERR Bit Fields */
#define DMA_ERR_ERR0_MASK 0x1u
#define DMA_ERR_ERR0_SHIFT 0
#define DMA_ERR_ERR0_WIDTH 1
#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
#define DMA_ERR_ERR1_MASK 0x2u
#define DMA_ERR_ERR1_SHIFT 1
#define DMA_ERR_ERR1_WIDTH 1
#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
#define DMA_ERR_ERR2_MASK 0x4u
#define DMA_ERR_ERR2_SHIFT 2
#define DMA_ERR_ERR2_WIDTH 1
#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
#define DMA_ERR_ERR3_MASK 0x8u
#define DMA_ERR_ERR3_SHIFT 3
#define DMA_ERR_ERR3_WIDTH 1
#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
#define DMA_ERR_ERR4_MASK 0x10u
#define DMA_ERR_ERR4_SHIFT 4
#define DMA_ERR_ERR4_WIDTH 1
#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
#define DMA_ERR_ERR5_MASK 0x20u
#define DMA_ERR_ERR5_SHIFT 5
#define DMA_ERR_ERR5_WIDTH 1
#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
#define DMA_ERR_ERR6_MASK 0x40u
#define DMA_ERR_ERR6_SHIFT 6
#define DMA_ERR_ERR6_WIDTH 1
#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
#define DMA_ERR_ERR7_MASK 0x80u
#define DMA_ERR_ERR7_SHIFT 7
#define DMA_ERR_ERR7_WIDTH 1
#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
/* HRS Bit Fields */
#define DMA_HRS_HRS0_MASK 0x1u
#define DMA_HRS_HRS0_SHIFT 0
#define DMA_HRS_HRS0_WIDTH 1
#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
#define DMA_HRS_HRS1_MASK 0x2u
#define DMA_HRS_HRS1_SHIFT 1
#define DMA_HRS_HRS1_WIDTH 1
#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
#define DMA_HRS_HRS2_MASK 0x4u
#define DMA_HRS_HRS2_SHIFT 2
#define DMA_HRS_HRS2_WIDTH 1
#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
#define DMA_HRS_HRS3_MASK 0x8u
#define DMA_HRS_HRS3_SHIFT 3
#define DMA_HRS_HRS3_WIDTH 1
#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
#define DMA_HRS_HRS4_MASK 0x10u
#define DMA_HRS_HRS4_SHIFT 4
#define DMA_HRS_HRS4_WIDTH 1
#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
#define DMA_HRS_HRS5_MASK 0x20u
#define DMA_HRS_HRS5_SHIFT 5
#define DMA_HRS_HRS5_WIDTH 1
#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
#define DMA_HRS_HRS6_MASK 0x40u
#define DMA_HRS_HRS6_SHIFT 6
#define DMA_HRS_HRS6_WIDTH 1
#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
#define DMA_HRS_HRS7_MASK 0x80u
#define DMA_HRS_HRS7_SHIFT 7
#define DMA_HRS_HRS7_WIDTH 1
#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
/* EARS Bit Fields */
#define DMA_EARS_EDREQ_0_MASK 0x1u
#define DMA_EARS_EDREQ_0_SHIFT 0
#define DMA_EARS_EDREQ_0_WIDTH 1
#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
#define DMA_EARS_EDREQ_1_MASK 0x2u
#define DMA_EARS_EDREQ_1_SHIFT 1
#define DMA_EARS_EDREQ_1_WIDTH 1
#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
#define DMA_EARS_EDREQ_2_MASK 0x4u
#define DMA_EARS_EDREQ_2_SHIFT 2
#define DMA_EARS_EDREQ_2_WIDTH 1
#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
#define DMA_EARS_EDREQ_3_MASK 0x8u
#define DMA_EARS_EDREQ_3_SHIFT 3
#define DMA_EARS_EDREQ_3_WIDTH 1
#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
#define DMA_EARS_EDREQ_4_MASK 0x10u
#define DMA_EARS_EDREQ_4_SHIFT 4
#define DMA_EARS_EDREQ_4_WIDTH 1
#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
#define DMA_EARS_EDREQ_5_MASK 0x20u
#define DMA_EARS_EDREQ_5_SHIFT 5
#define DMA_EARS_EDREQ_5_WIDTH 1
#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
#define DMA_EARS_EDREQ_6_MASK 0x40u
#define DMA_EARS_EDREQ_6_SHIFT 6
#define DMA_EARS_EDREQ_6_WIDTH 1
#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
#define DMA_EARS_EDREQ_7_MASK 0x80u
#define DMA_EARS_EDREQ_7_SHIFT 7
#define DMA_EARS_EDREQ_7_WIDTH 1
#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
/* DCHPRI3 Bit Fields */
#define DMA_DCHPRI3_CHPRI_MASK 0x7u
#define DMA_DCHPRI3_CHPRI_SHIFT 0
#define DMA_DCHPRI3_CHPRI_WIDTH 3
#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
#define DMA_DCHPRI3_DPA_MASK 0x40u
#define DMA_DCHPRI3_DPA_SHIFT 6
#define DMA_DCHPRI3_DPA_WIDTH 1
#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
#define DMA_DCHPRI3_ECP_MASK 0x80u
#define DMA_DCHPRI3_ECP_SHIFT 7
#define DMA_DCHPRI3_ECP_WIDTH 1
#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
/* DCHPRI2 Bit Fields */
#define DMA_DCHPRI2_CHPRI_MASK 0x7u
#define DMA_DCHPRI2_CHPRI_SHIFT 0
#define DMA_DCHPRI2_CHPRI_WIDTH 3
#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
#define DMA_DCHPRI2_DPA_MASK 0x40u
#define DMA_DCHPRI2_DPA_SHIFT 6
#define DMA_DCHPRI2_DPA_WIDTH 1
#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
#define DMA_DCHPRI2_ECP_MASK 0x80u
#define DMA_DCHPRI2_ECP_SHIFT 7
#define DMA_DCHPRI2_ECP_WIDTH 1
#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
/* DCHPRI1 Bit Fields */
#define DMA_DCHPRI1_CHPRI_MASK 0x7u
#define DMA_DCHPRI1_CHPRI_SHIFT 0
#define DMA_DCHPRI1_CHPRI_WIDTH 3
#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
#define DMA_DCHPRI1_DPA_MASK 0x40u
#define DMA_DCHPRI1_DPA_SHIFT 6
#define DMA_DCHPRI1_DPA_WIDTH 1
#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
#define DMA_DCHPRI1_ECP_MASK 0x80u
#define DMA_DCHPRI1_ECP_SHIFT 7
#define DMA_DCHPRI1_ECP_WIDTH 1
#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
/* DCHPRI0 Bit Fields */
#define DMA_DCHPRI0_CHPRI_MASK 0x7u
#define DMA_DCHPRI0_CHPRI_SHIFT 0
#define DMA_DCHPRI0_CHPRI_WIDTH 3
#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
#define DMA_DCHPRI0_DPA_MASK 0x40u
#define DMA_DCHPRI0_DPA_SHIFT 6
#define DMA_DCHPRI0_DPA_WIDTH 1
#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
#define DMA_DCHPRI0_ECP_MASK 0x80u
#define DMA_DCHPRI0_ECP_SHIFT 7
#define DMA_DCHPRI0_ECP_WIDTH 1
#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
/* DCHPRI7 Bit Fields */
#define DMA_DCHPRI7_CHPRI_MASK 0x7u
#define DMA_DCHPRI7_CHPRI_SHIFT 0
#define DMA_DCHPRI7_CHPRI_WIDTH 3
#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
#define DMA_DCHPRI7_DPA_MASK 0x40u
#define DMA_DCHPRI7_DPA_SHIFT 6
#define DMA_DCHPRI7_DPA_WIDTH 1
#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
#define DMA_DCHPRI7_ECP_MASK 0x80u
#define DMA_DCHPRI7_ECP_SHIFT 7
#define DMA_DCHPRI7_ECP_WIDTH 1
#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
/* DCHPRI6 Bit Fields */
#define DMA_DCHPRI6_CHPRI_MASK 0x7u
#define DMA_DCHPRI6_CHPRI_SHIFT 0
#define DMA_DCHPRI6_CHPRI_WIDTH 3
#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
#define DMA_DCHPRI6_DPA_MASK 0x40u
#define DMA_DCHPRI6_DPA_SHIFT 6
#define DMA_DCHPRI6_DPA_WIDTH 1
#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
#define DMA_DCHPRI6_ECP_MASK 0x80u
#define DMA_DCHPRI6_ECP_SHIFT 7
#define DMA_DCHPRI6_ECP_WIDTH 1
#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
/* DCHPRI5 Bit Fields */
#define DMA_DCHPRI5_CHPRI_MASK 0x7u
#define DMA_DCHPRI5_CHPRI_SHIFT 0
#define DMA_DCHPRI5_CHPRI_WIDTH 3
#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
#define DMA_DCHPRI5_DPA_MASK 0x40u
#define DMA_DCHPRI5_DPA_SHIFT 6
#define DMA_DCHPRI5_DPA_WIDTH 1
#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
#define DMA_DCHPRI5_ECP_MASK 0x80u
#define DMA_DCHPRI5_ECP_SHIFT 7
#define DMA_DCHPRI5_ECP_WIDTH 1
#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
/* DCHPRI4 Bit Fields */
#define DMA_DCHPRI4_CHPRI_MASK 0x7u
#define DMA_DCHPRI4_CHPRI_SHIFT 0
#define DMA_DCHPRI4_CHPRI_WIDTH 3
#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
#define DMA_DCHPRI4_DPA_MASK 0x40u
#define DMA_DCHPRI4_DPA_SHIFT 6
#define DMA_DCHPRI4_DPA_WIDTH 1
#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
#define DMA_DCHPRI4_ECP_MASK 0x80u
#define DMA_DCHPRI4_ECP_SHIFT 7
#define DMA_DCHPRI4_ECP_WIDTH 1
#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
/* SADDR Bit Fields */
#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
#define DMA_SADDR_SADDR_SHIFT 0
#define DMA_SADDR_SADDR_WIDTH 32
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
/* SOFF Bit Fields */
#define DMA_SOFF_SOFF_MASK 0xFFFFu
#define DMA_SOFF_SOFF_SHIFT 0
#define DMA_SOFF_SOFF_WIDTH 16
#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
/* ATTR Bit Fields */
#define DMA_ATTR_DSIZE_MASK 0x7u
#define DMA_ATTR_DSIZE_SHIFT 0
#define DMA_ATTR_DSIZE_WIDTH 3
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
#define DMA_ATTR_DMOD_MASK 0xF8u
#define DMA_ATTR_DMOD_SHIFT 3
#define DMA_ATTR_DMOD_WIDTH 5
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
#define DMA_ATTR_SSIZE_MASK 0x700u
#define DMA_ATTR_SSIZE_SHIFT 8
#define DMA_ATTR_SSIZE_WIDTH 3
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
#define DMA_ATTR_SMOD_MASK 0xF800u
#define DMA_ATTR_SMOD_SHIFT 11
#define DMA_ATTR_SMOD_WIDTH 5
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
/* NBYTES_MLNO Bit Fields */
#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
#define DMA_NBYTES_MLNO_NBYTES_WIDTH 32
#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
/* NBYTES_MLOFFNO Bit Fields */
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH 30
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH 1
#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH 1
#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
/* NBYTES_MLOFFYES Bit Fields */
#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH 10
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH 20
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH 1
#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH 1
#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
/* SLAST Bit Fields */
#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
#define DMA_SLAST_SLAST_SHIFT 0
#define DMA_SLAST_SLAST_WIDTH 32
#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
/* DADDR Bit Fields */
#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
#define DMA_DADDR_DADDR_SHIFT 0
#define DMA_DADDR_DADDR_WIDTH 32
#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
/* DOFF Bit Fields */
#define DMA_DOFF_DOFF_MASK 0xFFFFu
#define DMA_DOFF_DOFF_SHIFT 0
#define DMA_DOFF_DOFF_WIDTH 16
#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
/* CITER_ELINKNO Bit Fields */
#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
#define DMA_CITER_ELINKNO_CITER_SHIFT 0
#define DMA_CITER_ELINKNO_CITER_WIDTH 15
#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
#define DMA_CITER_ELINKNO_ELINK_WIDTH 1
#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
/* CITER_ELINKYES Bit Fields */
#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
#define DMA_CITER_ELINKYES_CITER_SHIFT 0
#define DMA_CITER_ELINKYES_CITER_WIDTH 9
#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
#define DMA_CITER_ELINKYES_LINKCH_MASK 0xE00u
#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
#define DMA_CITER_ELINKYES_LINKCH_WIDTH 3
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
#define DMA_CITER_ELINKYES_ELINK_WIDTH 1
#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
/* DLAST_SGA Bit Fields */
#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
#define DMA_DLAST_SGA_DLASTSGA_WIDTH 32
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
/* CSR Bit Fields */
#define DMA_CSR_START_MASK 0x1u
#define DMA_CSR_START_SHIFT 0
#define DMA_CSR_START_WIDTH 1
#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
#define DMA_CSR_INTMAJOR_MASK 0x2u
#define DMA_CSR_INTMAJOR_SHIFT 1
#define DMA_CSR_INTMAJOR_WIDTH 1
#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
#define DMA_CSR_INTHALF_MASK 0x4u
#define DMA_CSR_INTHALF_SHIFT 2
#define DMA_CSR_INTHALF_WIDTH 1
#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
#define DMA_CSR_DREQ_MASK 0x8u
#define DMA_CSR_DREQ_SHIFT 3
#define DMA_CSR_DREQ_WIDTH 1
#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
#define DMA_CSR_ESG_MASK 0x10u
#define DMA_CSR_ESG_SHIFT 4
#define DMA_CSR_ESG_WIDTH 1
#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
#define DMA_CSR_MAJORELINK_MASK 0x20u
#define DMA_CSR_MAJORELINK_SHIFT 5
#define DMA_CSR_MAJORELINK_WIDTH 1
#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
#define DMA_CSR_ACTIVE_MASK 0x40u
#define DMA_CSR_ACTIVE_SHIFT 6
#define DMA_CSR_ACTIVE_WIDTH 1
#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
#define DMA_CSR_DONE_MASK 0x80u
#define DMA_CSR_DONE_SHIFT 7
#define DMA_CSR_DONE_WIDTH 1
#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
#define DMA_CSR_MAJORLINKCH_MASK 0x700u
#define DMA_CSR_MAJORLINKCH_SHIFT 8
#define DMA_CSR_MAJORLINKCH_WIDTH 3
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
#define DMA_CSR_BWC_MASK 0xC000u
#define DMA_CSR_BWC_SHIFT 14
#define DMA_CSR_BWC_WIDTH 2
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
/* BITER_ELINKNO Bit Fields */
#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
#define DMA_BITER_ELINKNO_BITER_SHIFT 0
#define DMA_BITER_ELINKNO_BITER_WIDTH 15
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
#define DMA_BITER_ELINKNO_ELINK_WIDTH 1
#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
/* BITER_ELINKYES Bit Fields */
#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
#define DMA_BITER_ELINKYES_BITER_SHIFT 0
#define DMA_BITER_ELINKYES_BITER_WIDTH 9
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
#define DMA_BITER_ELINKYES_LINKCH_MASK 0xE00u
#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
#define DMA_BITER_ELINKYES_LINKCH_WIDTH 3
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
#define DMA_BITER_ELINKYES_ELINK_WIDTH 1
#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
/*!
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral DMA0 base address */
#define DMA0_BASE (0x40008000u)
/** Peripheral DMA0 base pointer */
#define DMA0 ((DMA_Type *)DMA0_BASE)
#define DMA0_BASE_PTR (DMA0)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { DMA0_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { DMA0 }
/* ----------------------------------------------------------------------------
-- DMA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
* @{
*/
/* DMA - Register instance definitions */
/* DMA0 */
#define DMA0_CR DMA_CR_REG(DMA0)
#define DMA0_ES DMA_ES_REG(DMA0)
#define DMA0_ERQ DMA_ERQ_REG(DMA0)
#define DMA0_EEI DMA_EEI_REG(DMA0)
#define DMA0_CEEI DMA_CEEI_REG(DMA0)
#define DMA0_SEEI DMA_SEEI_REG(DMA0)
#define DMA0_CERQ DMA_CERQ_REG(DMA0)
#define DMA0_SERQ DMA_SERQ_REG(DMA0)
#define DMA0_CDNE DMA_CDNE_REG(DMA0)
#define DMA0_SSRT DMA_SSRT_REG(DMA0)
#define DMA0_CERR DMA_CERR_REG(DMA0)
#define DMA0_CINT DMA_CINT_REG(DMA0)
#define DMA0_INT DMA_INT_REG(DMA0)
#define DMA0_ERR DMA_ERR_REG(DMA0)
#define DMA0_HRS DMA_HRS_REG(DMA0)
#define DMA0_EARS DMA_EARS_REG(DMA0)
#define DMA0_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
#define DMA0_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
#define DMA0_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
#define DMA0_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
#define DMA0_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
#define DMA0_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
#define DMA0_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
#define DMA0_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
#define DMA0_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
#define DMA0_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
#define DMA0_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
#define DMA0_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
#define DMA0_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
#define DMA0_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
#define DMA0_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
#define DMA0_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
#define DMA0_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
#define DMA0_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
#define DMA0_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
#define DMA0_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
#define DMA0_TCD0_CSR DMA_CSR_REG(DMA0,0)
#define DMA0_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
#define DMA0_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
#define DMA0_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
#define DMA0_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
#define DMA0_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
#define DMA0_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
#define DMA0_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
#define DMA0_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
#define DMA0_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
#define DMA0_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
#define DMA0_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
#define DMA0_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
#define DMA0_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
#define DMA0_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
#define DMA0_TCD1_CSR DMA_CSR_REG(DMA0,1)
#define DMA0_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
#define DMA0_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
#define DMA0_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
#define DMA0_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
#define DMA0_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
#define DMA0_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
#define DMA0_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
#define DMA0_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
#define DMA0_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
#define DMA0_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
#define DMA0_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
#define DMA0_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
#define DMA0_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
#define DMA0_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
#define DMA0_TCD2_CSR DMA_CSR_REG(DMA0,2)
#define DMA0_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
#define DMA0_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
#define DMA0_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
#define DMA0_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
#define DMA0_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
#define DMA0_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
#define DMA0_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
#define DMA0_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
#define DMA0_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
#define DMA0_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
#define DMA0_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
#define DMA0_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
#define DMA0_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
#define DMA0_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
#define DMA0_TCD3_CSR DMA_CSR_REG(DMA0,3)
#define DMA0_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
#define DMA0_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
#define DMA0_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
#define DMA0_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
#define DMA0_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
#define DMA0_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
#define DMA0_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
#define DMA0_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
#define DMA0_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
#define DMA0_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
#define DMA0_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
#define DMA0_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
#define DMA0_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
#define DMA0_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
#define DMA0_TCD4_CSR DMA_CSR_REG(DMA0,4)
#define DMA0_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
#define DMA0_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
#define DMA0_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
#define DMA0_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
#define DMA0_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
#define DMA0_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
#define DMA0_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
#define DMA0_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
#define DMA0_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
#define DMA0_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
#define DMA0_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
#define DMA0_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
#define DMA0_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
#define DMA0_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
#define DMA0_TCD5_CSR DMA_CSR_REG(DMA0,5)
#define DMA0_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
#define DMA0_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
#define DMA0_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
#define DMA0_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
#define DMA0_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
#define DMA0_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
#define DMA0_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
#define DMA0_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
#define DMA0_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
#define DMA0_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
#define DMA0_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
#define DMA0_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
#define DMA0_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
#define DMA0_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
#define DMA0_TCD6_CSR DMA_CSR_REG(DMA0,6)
#define DMA0_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
#define DMA0_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
#define DMA0_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
#define DMA0_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
#define DMA0_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
#define DMA0_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
#define DMA0_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
#define DMA0_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
#define DMA0_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
#define DMA0_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
#define DMA0_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
#define DMA0_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
#define DMA0_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
#define DMA0_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
#define DMA0_TCD7_CSR DMA_CSR_REG(DMA0,7)
#define DMA0_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
#define DMA0_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
/* DMA - Register array accessors */
#define DMA0_SADDR(index) DMA_SADDR_REG(DMA0,index)
#define DMA0_SOFF(index) DMA_SOFF_REG(DMA0,index)
#define DMA0_ATTR(index) DMA_ATTR_REG(DMA0,index)
#define DMA0_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
#define DMA0_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
#define DMA0_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
#define DMA0_SLAST(index) DMA_SLAST_REG(DMA0,index)
#define DMA0_DADDR(index) DMA_DADDR_REG(DMA0,index)
#define DMA0_DOFF(index) DMA_DOFF_REG(DMA0,index)
#define DMA0_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
#define DMA0_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
#define DMA0_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
#define DMA0_CSR(index) DMA_CSR_REG(DMA0,index)
#define DMA0_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
#define DMA0_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
/*!
* @}
*/ /* end of group DMA_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMAMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
* @{
*/
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint8_t CHCFG[8]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
} DMAMUX_Type, *DMAMUX_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DMAMUX - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
* @{
*/
/* DMAMUX - Register accessors */
#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
#define DMAMUX_CHCFG_COUNT 8
/*!
* @}
*/ /* end of group DMAMUX_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
/* CHCFG Bit Fields */
#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
#define DMAMUX_CHCFG_SOURCE_SHIFT 0
#define DMAMUX_CHCFG_SOURCE_WIDTH 6
#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
#define DMAMUX_CHCFG_TRIG_MASK 0x40u
#define DMAMUX_CHCFG_TRIG_SHIFT 6
#define DMAMUX_CHCFG_TRIG_WIDTH 1
#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
#define DMAMUX_CHCFG_ENBL_MASK 0x80u
#define DMAMUX_CHCFG_ENBL_SHIFT 7
#define DMAMUX_CHCFG_ENBL_WIDTH 1
#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
/*!
* @}
*/ /* end of group DMAMUX_Register_Masks */
/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX0 base address */
#define DMAMUX0_BASE (0x40021000u)
/** Peripheral DMAMUX0 base pointer */
#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
#define DMAMUX0_BASE_PTR (DMAMUX0)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS { DMAMUX0 }
/* ----------------------------------------------------------------------------
-- DMAMUX - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
* @{
*/
/* DMAMUX - Register instance definitions */
/* DMAMUX0 */
#define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0)
#define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1)
#define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2)
#define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3)
#define DMAMUX0_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX0,4)
#define DMAMUX0_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX0,5)
#define DMAMUX0_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX0,6)
#define DMAMUX0_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX0,7)
/* DMAMUX - Register array accessors */
#define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index)
/*!
* @}
*/ /* end of group DMAMUX_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EMVSIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
* @{
*/
/** EMVSIM - Register Layout Typedef */
typedef struct {
__I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */
__IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */
__IO uint32_t CTRL; /**< Control Register, offset: 0x10 */
__IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */
__IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */
__IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */
__IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */
__IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */
__IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */
__I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */
__IO uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */
__IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */
__IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */
__IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */
__IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */
__IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
__IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
} EMVSIM_Type, *EMVSIM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- EMVSIM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup EMVSIM_Register_Accessor_Macros EMVSIM - Register accessor macros
* @{
*/
/* EMVSIM - Register accessors */
#define EMVSIM_VER_ID_REG(base) ((base)->VER_ID)
#define EMVSIM_PARAM_REG(base) ((base)->PARAM)
#define EMVSIM_CLKCFG_REG(base) ((base)->CLKCFG)
#define EMVSIM_DIVISOR_REG(base) ((base)->DIVISOR)
#define EMVSIM_CTRL_REG(base) ((base)->CTRL)
#define EMVSIM_INT_MASK_REG(base) ((base)->INT_MASK)
#define EMVSIM_RX_THD_REG(base) ((base)->RX_THD)
#define EMVSIM_TX_THD_REG(base) ((base)->TX_THD)
#define EMVSIM_RX_STATUS_REG(base) ((base)->RX_STATUS)
#define EMVSIM_TX_STATUS_REG(base) ((base)->TX_STATUS)
#define EMVSIM_PCSR_REG(base) ((base)->PCSR)
#define EMVSIM_RX_BUF_REG(base) ((base)->RX_BUF)
#define EMVSIM_TX_BUF_REG(base) ((base)->TX_BUF)
#define EMVSIM_TX_GETU_REG(base) ((base)->TX_GETU)
#define EMVSIM_CWT_VAL_REG(base) ((base)->CWT_VAL)
#define EMVSIM_BWT_VAL_REG(base) ((base)->BWT_VAL)
#define EMVSIM_BGT_VAL_REG(base) ((base)->BGT_VAL)
#define EMVSIM_GPCNT0_VAL_REG(base) ((base)->GPCNT0_VAL)
#define EMVSIM_GPCNT1_VAL_REG(base) ((base)->GPCNT1_VAL)
/*!
* @}
*/ /* end of group EMVSIM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- EMVSIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
* @{
*/
/* VER_ID Bit Fields */
#define EMVSIM_VER_ID_VER_MASK 0xFFFFFFFFu
#define EMVSIM_VER_ID_VER_SHIFT 0
#define EMVSIM_VER_ID_VER_WIDTH 32
#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_VER_ID_VER_SHIFT))&EMVSIM_VER_ID_VER_MASK)
/* PARAM Bit Fields */
#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK 0xFFu
#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT 0
#define EMVSIM_PARAM_RX_FIFO_DEPTH_WIDTH 8
#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT))&EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK 0xFF00u
#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT 8
#define EMVSIM_PARAM_TX_FIFO_DEPTH_WIDTH 8
#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT))&EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
/* CLKCFG Bit Fields */
#define EMVSIM_CLKCFG_CLK_PRSC_MASK 0xFFu
#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT 0
#define EMVSIM_CLKCFG_CLK_PRSC_WIDTH 8
#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_CLK_PRSC_SHIFT))&EMVSIM_CLKCFG_CLK_PRSC_MASK)
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK 0x300u
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT 8
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_WIDTH 2
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT))&EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK 0xC00u
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT 10
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_WIDTH 2
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT))&EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
/* DIVISOR Bit Fields */
#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK 0x1FFu
#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT 0
#define EMVSIM_DIVISOR_DIVISOR_VALUE_WIDTH 9
#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT))&EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
/* CTRL Bit Fields */
#define EMVSIM_CTRL_IC_MASK 0x1u
#define EMVSIM_CTRL_IC_SHIFT 0
#define EMVSIM_CTRL_IC_WIDTH 1
#define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_IC_SHIFT))&EMVSIM_CTRL_IC_MASK)
#define EMVSIM_CTRL_ICM_MASK 0x2u
#define EMVSIM_CTRL_ICM_SHIFT 1
#define EMVSIM_CTRL_ICM_WIDTH 1
#define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_ICM_SHIFT))&EMVSIM_CTRL_ICM_MASK)
#define EMVSIM_CTRL_ANACK_MASK 0x4u
#define EMVSIM_CTRL_ANACK_SHIFT 2
#define EMVSIM_CTRL_ANACK_WIDTH 1
#define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_ANACK_SHIFT))&EMVSIM_CTRL_ANACK_MASK)
#define EMVSIM_CTRL_ONACK_MASK 0x8u
#define EMVSIM_CTRL_ONACK_SHIFT 3
#define EMVSIM_CTRL_ONACK_WIDTH 1
#define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_ONACK_SHIFT))&EMVSIM_CTRL_ONACK_MASK)
#define EMVSIM_CTRL_FLSH_RX_MASK 0x100u
#define EMVSIM_CTRL_FLSH_RX_SHIFT 8
#define EMVSIM_CTRL_FLSH_RX_WIDTH 1
#define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_FLSH_RX_SHIFT))&EMVSIM_CTRL_FLSH_RX_MASK)
#define EMVSIM_CTRL_FLSH_TX_MASK 0x200u
#define EMVSIM_CTRL_FLSH_TX_SHIFT 9
#define EMVSIM_CTRL_FLSH_TX_WIDTH 1
#define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_FLSH_TX_SHIFT))&EMVSIM_CTRL_FLSH_TX_MASK)
#define EMVSIM_CTRL_SW_RST_MASK 0x400u
#define EMVSIM_CTRL_SW_RST_SHIFT 10
#define EMVSIM_CTRL_SW_RST_WIDTH 1
#define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_SW_RST_SHIFT))&EMVSIM_CTRL_SW_RST_MASK)
#define EMVSIM_CTRL_KILL_CLOCKS_MASK 0x800u
#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT 11
#define EMVSIM_CTRL_KILL_CLOCKS_WIDTH 1
#define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_KILL_CLOCKS_SHIFT))&EMVSIM_CTRL_KILL_CLOCKS_MASK)
#define EMVSIM_CTRL_DOZE_EN_MASK 0x1000u
#define EMVSIM_CTRL_DOZE_EN_SHIFT 12
#define EMVSIM_CTRL_DOZE_EN_WIDTH 1
#define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_DOZE_EN_SHIFT))&EMVSIM_CTRL_DOZE_EN_MASK)
#define EMVSIM_CTRL_STOP_EN_MASK 0x2000u
#define EMVSIM_CTRL_STOP_EN_SHIFT 13
#define EMVSIM_CTRL_STOP_EN_WIDTH 1
#define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_STOP_EN_SHIFT))&EMVSIM_CTRL_STOP_EN_MASK)
#define EMVSIM_CTRL_RCV_EN_MASK 0x10000u
#define EMVSIM_CTRL_RCV_EN_SHIFT 16
#define EMVSIM_CTRL_RCV_EN_WIDTH 1
#define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_RCV_EN_SHIFT))&EMVSIM_CTRL_RCV_EN_MASK)
#define EMVSIM_CTRL_XMT_EN_MASK 0x20000u
#define EMVSIM_CTRL_XMT_EN_SHIFT 17
#define EMVSIM_CTRL_XMT_EN_WIDTH 1
#define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_XMT_EN_SHIFT))&EMVSIM_CTRL_XMT_EN_MASK)
#define EMVSIM_CTRL_RCVR_11_MASK 0x40000u
#define EMVSIM_CTRL_RCVR_11_SHIFT 18
#define EMVSIM_CTRL_RCVR_11_WIDTH 1
#define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_RCVR_11_SHIFT))&EMVSIM_CTRL_RCVR_11_MASK)
#define EMVSIM_CTRL_RX_DMA_EN_MASK 0x80000u
#define EMVSIM_CTRL_RX_DMA_EN_SHIFT 19
#define EMVSIM_CTRL_RX_DMA_EN_WIDTH 1
#define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_RX_DMA_EN_SHIFT))&EMVSIM_CTRL_RX_DMA_EN_MASK)
#define EMVSIM_CTRL_TX_DMA_EN_MASK 0x100000u
#define EMVSIM_CTRL_TX_DMA_EN_SHIFT 20
#define EMVSIM_CTRL_TX_DMA_EN_WIDTH 1
#define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_TX_DMA_EN_SHIFT))&EMVSIM_CTRL_TX_DMA_EN_MASK)
#define EMVSIM_CTRL_INV_CRC_VAL_MASK 0x1000000u
#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT 24
#define EMVSIM_CTRL_INV_CRC_VAL_WIDTH 1
#define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_INV_CRC_VAL_SHIFT))&EMVSIM_CTRL_INV_CRC_VAL_MASK)
#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK 0x2000000u
#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT 25
#define EMVSIM_CTRL_CRC_OUT_FLIP_WIDTH 1
#define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT))&EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
#define EMVSIM_CTRL_CRC_IN_FLIP_MASK 0x4000000u
#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT 26
#define EMVSIM_CTRL_CRC_IN_FLIP_WIDTH 1
#define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_CRC_IN_FLIP_SHIFT))&EMVSIM_CTRL_CRC_IN_FLIP_MASK)
#define EMVSIM_CTRL_CWT_EN_MASK 0x8000000u
#define EMVSIM_CTRL_CWT_EN_SHIFT 27
#define EMVSIM_CTRL_CWT_EN_WIDTH 1
#define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_CWT_EN_SHIFT))&EMVSIM_CTRL_CWT_EN_MASK)
#define EMVSIM_CTRL_LRC_EN_MASK 0x10000000u
#define EMVSIM_CTRL_LRC_EN_SHIFT 28
#define EMVSIM_CTRL_LRC_EN_WIDTH 1
#define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_LRC_EN_SHIFT))&EMVSIM_CTRL_LRC_EN_MASK)
#define EMVSIM_CTRL_CRC_EN_MASK 0x20000000u
#define EMVSIM_CTRL_CRC_EN_SHIFT 29
#define EMVSIM_CTRL_CRC_EN_WIDTH 1
#define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_CRC_EN_SHIFT))&EMVSIM_CTRL_CRC_EN_MASK)
#define EMVSIM_CTRL_XMT_CRC_LRC_MASK 0x40000000u
#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT 30
#define EMVSIM_CTRL_XMT_CRC_LRC_WIDTH 1
#define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_XMT_CRC_LRC_SHIFT))&EMVSIM_CTRL_XMT_CRC_LRC_MASK)
#define EMVSIM_CTRL_BWT_EN_MASK 0x80000000u
#define EMVSIM_CTRL_BWT_EN_SHIFT 31
#define EMVSIM_CTRL_BWT_EN_WIDTH 1
#define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CTRL_BWT_EN_SHIFT))&EMVSIM_CTRL_BWT_EN_MASK)
/* INT_MASK Bit Fields */
#define EMVSIM_INT_MASK_RDT_IM_MASK 0x1u
#define EMVSIM_INT_MASK_RDT_IM_SHIFT 0
#define EMVSIM_INT_MASK_RDT_IM_WIDTH 1
#define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_RDT_IM_SHIFT))&EMVSIM_INT_MASK_RDT_IM_MASK)
#define EMVSIM_INT_MASK_TC_IM_MASK 0x2u
#define EMVSIM_INT_MASK_TC_IM_SHIFT 1
#define EMVSIM_INT_MASK_TC_IM_WIDTH 1
#define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_TC_IM_SHIFT))&EMVSIM_INT_MASK_TC_IM_MASK)
#define EMVSIM_INT_MASK_RFO_IM_MASK 0x4u
#define EMVSIM_INT_MASK_RFO_IM_SHIFT 2
#define EMVSIM_INT_MASK_RFO_IM_WIDTH 1
#define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_RFO_IM_SHIFT))&EMVSIM_INT_MASK_RFO_IM_MASK)
#define EMVSIM_INT_MASK_ETC_IM_MASK 0x8u
#define EMVSIM_INT_MASK_ETC_IM_SHIFT 3
#define EMVSIM_INT_MASK_ETC_IM_WIDTH 1
#define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_ETC_IM_SHIFT))&EMVSIM_INT_MASK_ETC_IM_MASK)
#define EMVSIM_INT_MASK_TFE_IM_MASK 0x10u
#define EMVSIM_INT_MASK_TFE_IM_SHIFT 4
#define EMVSIM_INT_MASK_TFE_IM_WIDTH 1
#define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_TFE_IM_SHIFT))&EMVSIM_INT_MASK_TFE_IM_MASK)
#define EMVSIM_INT_MASK_TNACK_IM_MASK 0x20u
#define EMVSIM_INT_MASK_TNACK_IM_SHIFT 5
#define EMVSIM_INT_MASK_TNACK_IM_WIDTH 1
#define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_TNACK_IM_SHIFT))&EMVSIM_INT_MASK_TNACK_IM_MASK)
#define EMVSIM_INT_MASK_TFF_IM_MASK 0x40u
#define EMVSIM_INT_MASK_TFF_IM_SHIFT 6
#define EMVSIM_INT_MASK_TFF_IM_WIDTH 1
#define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_TFF_IM_SHIFT))&EMVSIM_INT_MASK_TFF_IM_MASK)
#define EMVSIM_INT_MASK_TDT_IM_MASK 0x80u
#define EMVSIM_INT_MASK_TDT_IM_SHIFT 7
#define EMVSIM_INT_MASK_TDT_IM_WIDTH 1
#define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_TDT_IM_SHIFT))&EMVSIM_INT_MASK_TDT_IM_MASK)
#define EMVSIM_INT_MASK_GPCNT0_IM_MASK 0x100u
#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT 8
#define EMVSIM_INT_MASK_GPCNT0_IM_WIDTH 1
#define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_GPCNT0_IM_SHIFT))&EMVSIM_INT_MASK_GPCNT0_IM_MASK)
#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK 0x200u
#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT 9
#define EMVSIM_INT_MASK_CWT_ERR_IM_WIDTH 1
#define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT))&EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_RNACK_IM_MASK 0x400u
#define EMVSIM_INT_MASK_RNACK_IM_SHIFT 10
#define EMVSIM_INT_MASK_RNACK_IM_WIDTH 1
#define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_RNACK_IM_SHIFT))&EMVSIM_INT_MASK_RNACK_IM_MASK)
#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK 0x800u
#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT 11
#define EMVSIM_INT_MASK_BWT_ERR_IM_WIDTH 1
#define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT))&EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK 0x1000u
#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT 12
#define EMVSIM_INT_MASK_BGT_ERR_IM_WIDTH 1
#define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT))&EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_GPCNT1_IM_MASK 0x2000u
#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT 13
#define EMVSIM_INT_MASK_GPCNT1_IM_WIDTH 1
#define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_GPCNT1_IM_SHIFT))&EMVSIM_INT_MASK_GPCNT1_IM_MASK)
#define EMVSIM_INT_MASK_RX_DATA_IM_MASK 0x4000u
#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT 14
#define EMVSIM_INT_MASK_RX_DATA_IM_WIDTH 1
#define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_RX_DATA_IM_SHIFT))&EMVSIM_INT_MASK_RX_DATA_IM_MASK)
#define EMVSIM_INT_MASK_PEF_IM_MASK 0x8000u
#define EMVSIM_INT_MASK_PEF_IM_SHIFT 15
#define EMVSIM_INT_MASK_PEF_IM_WIDTH 1
#define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_INT_MASK_PEF_IM_SHIFT))&EMVSIM_INT_MASK_PEF_IM_MASK)
/* RX_THD Bit Fields */
#define EMVSIM_RX_THD_RDT_MASK 0xFu
#define EMVSIM_RX_THD_RDT_SHIFT 0
#define EMVSIM_RX_THD_RDT_WIDTH 4
#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_THD_RDT_SHIFT))&EMVSIM_RX_THD_RDT_MASK)
#define EMVSIM_RX_THD_RNCK_THD_MASK 0xF00u
#define EMVSIM_RX_THD_RNCK_THD_SHIFT 8
#define EMVSIM_RX_THD_RNCK_THD_WIDTH 4
#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_THD_RNCK_THD_SHIFT))&EMVSIM_RX_THD_RNCK_THD_MASK)
/* TX_THD Bit Fields */
#define EMVSIM_TX_THD_TDT_MASK 0xFu
#define EMVSIM_TX_THD_TDT_SHIFT 0
#define EMVSIM_TX_THD_TDT_WIDTH 4
#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_THD_TDT_SHIFT))&EMVSIM_TX_THD_TDT_MASK)
#define EMVSIM_TX_THD_TNCK_THD_MASK 0xF00u
#define EMVSIM_TX_THD_TNCK_THD_SHIFT 8
#define EMVSIM_TX_THD_TNCK_THD_WIDTH 4
#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_THD_TNCK_THD_SHIFT))&EMVSIM_TX_THD_TNCK_THD_MASK)
/* RX_STATUS Bit Fields */
#define EMVSIM_RX_STATUS_RFO_MASK 0x1u
#define EMVSIM_RX_STATUS_RFO_SHIFT 0
#define EMVSIM_RX_STATUS_RFO_WIDTH 1
#define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RFO_SHIFT))&EMVSIM_RX_STATUS_RFO_MASK)
#define EMVSIM_RX_STATUS_RX_DATA_MASK 0x10u
#define EMVSIM_RX_STATUS_RX_DATA_SHIFT 4
#define EMVSIM_RX_STATUS_RX_DATA_WIDTH 1
#define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RX_DATA_SHIFT))&EMVSIM_RX_STATUS_RX_DATA_MASK)
#define EMVSIM_RX_STATUS_RDTF_MASK 0x20u
#define EMVSIM_RX_STATUS_RDTF_SHIFT 5
#define EMVSIM_RX_STATUS_RDTF_WIDTH 1
#define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RDTF_SHIFT))&EMVSIM_RX_STATUS_RDTF_MASK)
#define EMVSIM_RX_STATUS_LRC_OK_MASK 0x40u
#define EMVSIM_RX_STATUS_LRC_OK_SHIFT 6
#define EMVSIM_RX_STATUS_LRC_OK_WIDTH 1
#define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_LRC_OK_SHIFT))&EMVSIM_RX_STATUS_LRC_OK_MASK)
#define EMVSIM_RX_STATUS_CRC_OK_MASK 0x80u
#define EMVSIM_RX_STATUS_CRC_OK_SHIFT 7
#define EMVSIM_RX_STATUS_CRC_OK_WIDTH 1
#define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_CRC_OK_SHIFT))&EMVSIM_RX_STATUS_CRC_OK_MASK)
#define EMVSIM_RX_STATUS_CWT_ERR_MASK 0x100u
#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT 8
#define EMVSIM_RX_STATUS_CWT_ERR_WIDTH 1
#define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_CWT_ERR_SHIFT))&EMVSIM_RX_STATUS_CWT_ERR_MASK)
#define EMVSIM_RX_STATUS_RTE_MASK 0x200u
#define EMVSIM_RX_STATUS_RTE_SHIFT 9
#define EMVSIM_RX_STATUS_RTE_WIDTH 1
#define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RTE_SHIFT))&EMVSIM_RX_STATUS_RTE_MASK)
#define EMVSIM_RX_STATUS_BWT_ERR_MASK 0x400u
#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT 10
#define EMVSIM_RX_STATUS_BWT_ERR_WIDTH 1
#define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_BWT_ERR_SHIFT))&EMVSIM_RX_STATUS_BWT_ERR_MASK)
#define EMVSIM_RX_STATUS_BGT_ERR_MASK 0x800u
#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT 11
#define EMVSIM_RX_STATUS_BGT_ERR_WIDTH 1
#define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_BGT_ERR_SHIFT))&EMVSIM_RX_STATUS_BGT_ERR_MASK)
#define EMVSIM_RX_STATUS_PEF_MASK 0x1000u
#define EMVSIM_RX_STATUS_PEF_SHIFT 12
#define EMVSIM_RX_STATUS_PEF_WIDTH 1
#define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_PEF_SHIFT))&EMVSIM_RX_STATUS_PEF_MASK)
#define EMVSIM_RX_STATUS_FEF_MASK 0x2000u
#define EMVSIM_RX_STATUS_FEF_SHIFT 13
#define EMVSIM_RX_STATUS_FEF_WIDTH 1
#define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_FEF_SHIFT))&EMVSIM_RX_STATUS_FEF_MASK)
#define EMVSIM_RX_STATUS_RX_WPTR_MASK 0x30000u
#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT 16
#define EMVSIM_RX_STATUS_RX_WPTR_WIDTH 2
#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RX_WPTR_SHIFT))&EMVSIM_RX_STATUS_RX_WPTR_MASK)
#define EMVSIM_RX_STATUS_RX_CNT_MASK 0x1C00000u
#define EMVSIM_RX_STATUS_RX_CNT_SHIFT 22
#define EMVSIM_RX_STATUS_RX_CNT_WIDTH 3
#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RX_CNT_SHIFT))&EMVSIM_RX_STATUS_RX_CNT_MASK)
/* TX_STATUS Bit Fields */
#define EMVSIM_TX_STATUS_TNTE_MASK 0x1u
#define EMVSIM_TX_STATUS_TNTE_SHIFT 0
#define EMVSIM_TX_STATUS_TNTE_WIDTH 1
#define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TNTE_SHIFT))&EMVSIM_TX_STATUS_TNTE_MASK)
#define EMVSIM_TX_STATUS_TFE_MASK 0x8u
#define EMVSIM_TX_STATUS_TFE_SHIFT 3
#define EMVSIM_TX_STATUS_TFE_WIDTH 1
#define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TFE_SHIFT))&EMVSIM_TX_STATUS_TFE_MASK)
#define EMVSIM_TX_STATUS_ETCF_MASK 0x10u
#define EMVSIM_TX_STATUS_ETCF_SHIFT 4
#define EMVSIM_TX_STATUS_ETCF_WIDTH 1
#define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_ETCF_SHIFT))&EMVSIM_TX_STATUS_ETCF_MASK)
#define EMVSIM_TX_STATUS_TCF_MASK 0x20u
#define EMVSIM_TX_STATUS_TCF_SHIFT 5
#define EMVSIM_TX_STATUS_TCF_WIDTH 1
#define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TCF_SHIFT))&EMVSIM_TX_STATUS_TCF_MASK)
#define EMVSIM_TX_STATUS_TFF_MASK 0x40u
#define EMVSIM_TX_STATUS_TFF_SHIFT 6
#define EMVSIM_TX_STATUS_TFF_WIDTH 1
#define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TFF_SHIFT))&EMVSIM_TX_STATUS_TFF_MASK)
#define EMVSIM_TX_STATUS_TDTF_MASK 0x80u
#define EMVSIM_TX_STATUS_TDTF_SHIFT 7
#define EMVSIM_TX_STATUS_TDTF_WIDTH 1
#define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TDTF_SHIFT))&EMVSIM_TX_STATUS_TDTF_MASK)
#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK 0x100u
#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT 8
#define EMVSIM_TX_STATUS_GPCNT0_TO_WIDTH 1
#define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT))&EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK 0x200u
#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT 9
#define EMVSIM_TX_STATUS_GPCNT1_TO_WIDTH 1
#define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT))&EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
#define EMVSIM_TX_STATUS_TX_RPTR_MASK 0x30000u
#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT 16
#define EMVSIM_TX_STATUS_TX_RPTR_WIDTH 2
#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TX_RPTR_SHIFT))&EMVSIM_TX_STATUS_TX_RPTR_MASK)
#define EMVSIM_TX_STATUS_TX_CNT_MASK 0x1C00000u
#define EMVSIM_TX_STATUS_TX_CNT_SHIFT 22
#define EMVSIM_TX_STATUS_TX_CNT_WIDTH 3
#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TX_CNT_SHIFT))&EMVSIM_TX_STATUS_TX_CNT_MASK)
/* PCSR Bit Fields */
#define EMVSIM_PCSR_SAPD_MASK 0x1u
#define EMVSIM_PCSR_SAPD_SHIFT 0
#define EMVSIM_PCSR_SAPD_WIDTH 1
#define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SAPD_SHIFT))&EMVSIM_PCSR_SAPD_MASK)
#define EMVSIM_PCSR_SVCC_EN_MASK 0x2u
#define EMVSIM_PCSR_SVCC_EN_SHIFT 1
#define EMVSIM_PCSR_SVCC_EN_WIDTH 1
#define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SVCC_EN_SHIFT))&EMVSIM_PCSR_SVCC_EN_MASK)
#define EMVSIM_PCSR_VCCENP_MASK 0x4u
#define EMVSIM_PCSR_VCCENP_SHIFT 2
#define EMVSIM_PCSR_VCCENP_WIDTH 1
#define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_VCCENP_SHIFT))&EMVSIM_PCSR_VCCENP_MASK)
#define EMVSIM_PCSR_SRST_MASK 0x8u
#define EMVSIM_PCSR_SRST_SHIFT 3
#define EMVSIM_PCSR_SRST_WIDTH 1
#define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SRST_SHIFT))&EMVSIM_PCSR_SRST_MASK)
#define EMVSIM_PCSR_SCEN_MASK 0x10u
#define EMVSIM_PCSR_SCEN_SHIFT 4
#define EMVSIM_PCSR_SCEN_WIDTH 1
#define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SCEN_SHIFT))&EMVSIM_PCSR_SCEN_MASK)
#define EMVSIM_PCSR_SCSP_MASK 0x20u
#define EMVSIM_PCSR_SCSP_SHIFT 5
#define EMVSIM_PCSR_SCSP_WIDTH 1
#define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SCSP_SHIFT))&EMVSIM_PCSR_SCSP_MASK)
#define EMVSIM_PCSR_SPD_MASK 0x80u
#define EMVSIM_PCSR_SPD_SHIFT 7
#define EMVSIM_PCSR_SPD_WIDTH 1
#define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SPD_SHIFT))&EMVSIM_PCSR_SPD_MASK)
#define EMVSIM_PCSR_SPDIM_MASK 0x1000000u
#define EMVSIM_PCSR_SPDIM_SHIFT 24
#define EMVSIM_PCSR_SPDIM_WIDTH 1
#define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SPDIM_SHIFT))&EMVSIM_PCSR_SPDIM_MASK)
#define EMVSIM_PCSR_SPDIF_MASK 0x2000000u
#define EMVSIM_PCSR_SPDIF_SHIFT 25
#define EMVSIM_PCSR_SPDIF_WIDTH 1
#define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SPDIF_SHIFT))&EMVSIM_PCSR_SPDIF_MASK)
#define EMVSIM_PCSR_SPDP_MASK 0x4000000u
#define EMVSIM_PCSR_SPDP_SHIFT 26
#define EMVSIM_PCSR_SPDP_WIDTH 1
#define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SPDP_SHIFT))&EMVSIM_PCSR_SPDP_MASK)
#define EMVSIM_PCSR_SPDES_MASK 0x8000000u
#define EMVSIM_PCSR_SPDES_SHIFT 27
#define EMVSIM_PCSR_SPDES_WIDTH 1
#define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PCSR_SPDES_SHIFT))&EMVSIM_PCSR_SPDES_MASK)
/* RX_BUF Bit Fields */
#define EMVSIM_RX_BUF_RX_BYTE_MASK 0xFFu
#define EMVSIM_RX_BUF_RX_BYTE_SHIFT 0
#define EMVSIM_RX_BUF_RX_BYTE_WIDTH 8
#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_BUF_RX_BYTE_SHIFT))&EMVSIM_RX_BUF_RX_BYTE_MASK)
/* TX_BUF Bit Fields */
#define EMVSIM_TX_BUF_TX_BYTE_MASK 0xFFu
#define EMVSIM_TX_BUF_TX_BYTE_SHIFT 0
#define EMVSIM_TX_BUF_TX_BYTE_WIDTH 8
#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_BUF_TX_BYTE_SHIFT))&EMVSIM_TX_BUF_TX_BYTE_MASK)
/* TX_GETU Bit Fields */
#define EMVSIM_TX_GETU_GETU_MASK 0xFFu
#define EMVSIM_TX_GETU_GETU_SHIFT 0
#define EMVSIM_TX_GETU_GETU_WIDTH 8
#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_GETU_GETU_SHIFT))&EMVSIM_TX_GETU_GETU_MASK)
/* CWT_VAL Bit Fields */
#define EMVSIM_CWT_VAL_CWT_MASK 0xFFFFu
#define EMVSIM_CWT_VAL_CWT_SHIFT 0
#define EMVSIM_CWT_VAL_CWT_WIDTH 16
#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CWT_VAL_CWT_SHIFT))&EMVSIM_CWT_VAL_CWT_MASK)
/* BWT_VAL Bit Fields */
#define EMVSIM_BWT_VAL_BWT_MASK 0xFFFFFFFFu
#define EMVSIM_BWT_VAL_BWT_SHIFT 0
#define EMVSIM_BWT_VAL_BWT_WIDTH 32
#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_BWT_VAL_BWT_SHIFT))&EMVSIM_BWT_VAL_BWT_MASK)
/* BGT_VAL Bit Fields */
#define EMVSIM_BGT_VAL_BGT_MASK 0xFFFFu
#define EMVSIM_BGT_VAL_BGT_SHIFT 0
#define EMVSIM_BGT_VAL_BGT_WIDTH 16
#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_BGT_VAL_BGT_SHIFT))&EMVSIM_BGT_VAL_BGT_MASK)
/* GPCNT0_VAL Bit Fields */
#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK 0xFFFFu
#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT 0
#define EMVSIM_GPCNT0_VAL_GPCNT0_WIDTH 16
#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT))&EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
/* GPCNT1_VAL Bit Fields */
#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK 0xFFFFu
#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT 0
#define EMVSIM_GPCNT1_VAL_GPCNT1_WIDTH 16
#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT))&EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/*!
* @}
*/ /* end of group EMVSIM_Register_Masks */
/* EMVSIM - Peripheral instance base addresses */
/** Peripheral EMVSIM0 base address */
#define EMVSIM0_BASE (0x4004E000u)
/** Peripheral EMVSIM0 base pointer */
#define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE)
#define EMVSIM0_BASE_PTR (EMVSIM0)
/** Array initializer of EMVSIM peripheral base addresses */
#define EMVSIM_BASE_ADDRS { EMVSIM0_BASE }
/** Array initializer of EMVSIM peripheral base pointers */
#define EMVSIM_BASE_PTRS { EMVSIM0 }
/* ----------------------------------------------------------------------------
-- EMVSIM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup EMVSIM_Register_Accessor_Macros EMVSIM - Register accessor macros
* @{
*/
/* EMVSIM - Register instance definitions */
/* EMVSIM0 */
#define EMVSIM0_VER_ID EMVSIM_VER_ID_REG(EMVSIM0)
#define EMVSIM0_PARAM EMVSIM_PARAM_REG(EMVSIM0)
#define EMVSIM0_CLKCFG EMVSIM_CLKCFG_REG(EMVSIM0)
#define EMVSIM0_DIVISOR EMVSIM_DIVISOR_REG(EMVSIM0)
#define EMVSIM0_CTRL EMVSIM_CTRL_REG(EMVSIM0)
#define EMVSIM0_INT_MASK EMVSIM_INT_MASK_REG(EMVSIM0)
#define EMVSIM0_RX_THD EMVSIM_RX_THD_REG(EMVSIM0)
#define EMVSIM0_TX_THD EMVSIM_TX_THD_REG(EMVSIM0)
#define EMVSIM0_RX_STATUS EMVSIM_RX_STATUS_REG(EMVSIM0)
#define EMVSIM0_TX_STATUS EMVSIM_TX_STATUS_REG(EMVSIM0)
#define EMVSIM0_PCSR EMVSIM_PCSR_REG(EMVSIM0)
#define EMVSIM0_RX_BUF EMVSIM_RX_BUF_REG(EMVSIM0)
#define EMVSIM0_TX_BUF EMVSIM_TX_BUF_REG(EMVSIM0)
#define EMVSIM0_TX_GETU EMVSIM_TX_GETU_REG(EMVSIM0)
#define EMVSIM0_CWT_VAL EMVSIM_CWT_VAL_REG(EMVSIM0)
#define EMVSIM0_BWT_VAL EMVSIM_BWT_VAL_REG(EMVSIM0)
#define EMVSIM0_BGT_VAL EMVSIM_BGT_VAL_REG(EMVSIM0)
#define EMVSIM0_GPCNT0_VAL EMVSIM_GPCNT0_VAL_REG(EMVSIM0)
#define EMVSIM0_GPCNT1_VAL EMVSIM_GPCNT1_VAL_REG(EMVSIM0)
/*!
* @}
*/ /* end of group EMVSIM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group EMVSIM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FGPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
* @{
*/
/** FGPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} FGPIO_Type, *FGPIO_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FGPIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros
* @{
*/
/* FGPIO - Register accessors */
#define FGPIO_PDOR_REG(base) ((base)->PDOR)
#define FGPIO_PSOR_REG(base) ((base)->PSOR)
#define FGPIO_PCOR_REG(base) ((base)->PCOR)
#define FGPIO_PTOR_REG(base) ((base)->PTOR)
#define FGPIO_PDIR_REG(base) ((base)->PDIR)
#define FGPIO_PDDR_REG(base) ((base)->PDDR)
/*!
* @}
*/ /* end of group FGPIO_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FGPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
* @{
*/
/* PDOR Bit Fields */
#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
#define FGPIO_PDOR_PDO_SHIFT 0
#define FGPIO_PDOR_PDO_WIDTH 32
#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
/* PSOR Bit Fields */
#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
#define FGPIO_PSOR_PTSO_SHIFT 0
#define FGPIO_PSOR_PTSO_WIDTH 32
#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
/* PCOR Bit Fields */
#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
#define FGPIO_PCOR_PTCO_SHIFT 0
#define FGPIO_PCOR_PTCO_WIDTH 32
#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
/* PTOR Bit Fields */
#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
#define FGPIO_PTOR_PTTO_SHIFT 0
#define FGPIO_PTOR_PTTO_WIDTH 32
#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
/* PDIR Bit Fields */
#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
#define FGPIO_PDIR_PDI_SHIFT 0
#define FGPIO_PDIR_PDI_WIDTH 32
#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
/* PDDR Bit Fields */
#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
#define FGPIO_PDDR_PDD_SHIFT 0
#define FGPIO_PDDR_PDD_WIDTH 32
#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group FGPIO_Register_Masks */
/* FGPIO - Peripheral instance base addresses */
/** Peripheral FGPIOA base address */
#define FGPIOA_BASE (0xF8000000u)
/** Peripheral FGPIOA base pointer */
#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
#define FGPIOA_BASE_PTR (FGPIOA)
/** Array initializer of FGPIO peripheral base addresses */
#define FGPIO_BASE_ADDRS { FGPIOA_BASE }
/** Array initializer of FGPIO peripheral base pointers */
#define FGPIO_BASE_PTRS { FGPIOA }
/* ----------------------------------------------------------------------------
-- FGPIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros
* @{
*/
/* FGPIO - Register instance definitions */
/* FGPIOA */
#define FGPIOA_PDOR FGPIO_PDOR_REG(FGPIOA)
#define FGPIOA_PSOR FGPIO_PSOR_REG(FGPIOA)
#define FGPIOA_PCOR FGPIO_PCOR_REG(FGPIOA)
#define FGPIOA_PTOR FGPIO_PTOR_REG(FGPIOA)
#define FGPIOA_PDIR FGPIO_PDIR_REG(FGPIOA)
#define FGPIOA_PDDR FGPIO_PDDR_REG(FGPIOA)
/*!
* @}
*/ /* end of group FGPIO_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group FGPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
* @{
*/
/** FLEXIO - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
__I uint32_t PIN; /**< Pin State Register, offset: 0xC */
__IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
__IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
__IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
uint8_t RESERVED_0[4];
__IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
__IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
__IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
uint8_t RESERVED_1[4];
__IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
uint8_t RESERVED_2[12];
__IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
uint8_t RESERVED_3[60];
__IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_4[96];
__IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_5[224];
__IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_6[96];
__IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
uint8_t RESERVED_7[96];
__IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
uint8_t RESERVED_8[96];
__IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
uint8_t RESERVED_9[96];
__IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
uint8_t RESERVED_10[96];
__IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
uint8_t RESERVED_11[96];
__IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
uint8_t RESERVED_12[352];
__IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
uint8_t RESERVED_13[96];
__IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
uint8_t RESERVED_14[96];
__IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
} FLEXIO_Type, *FLEXIO_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FLEXIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
* @{
*/
/* FLEXIO - Register accessors */
#define FLEXIO_VERID_REG(base) ((base)->VERID)
#define FLEXIO_PARAM_REG(base) ((base)->PARAM)
#define FLEXIO_CTRL_REG(base) ((base)->CTRL)
#define FLEXIO_PIN_REG(base) ((base)->PIN)
#define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT)
#define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR)
#define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT)
#define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN)
#define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN)
#define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN)
#define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN)
#define FLEXIO_SHIFTSTATE_REG(base) ((base)->SHIFTSTATE)
#define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index])
#define FLEXIO_SHIFTCTL_COUNT 8
#define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index])
#define FLEXIO_SHIFTCFG_COUNT 8
#define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index])
#define FLEXIO_SHIFTBUF_COUNT 8
#define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index])
#define FLEXIO_SHIFTBUFBIS_COUNT 8
#define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index])
#define FLEXIO_SHIFTBUFBYS_COUNT 8
#define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index])
#define FLEXIO_SHIFTBUFBBS_COUNT 8
#define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index])
#define FLEXIO_TIMCTL_COUNT 8
#define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index])
#define FLEXIO_TIMCFG_COUNT 8
#define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index])
#define FLEXIO_TIMCMP_COUNT 8
#define FLEXIO_SHIFTBUFNBS_REG(base,index) ((base)->SHIFTBUFNBS[index])
#define FLEXIO_SHIFTBUFNBS_COUNT 8
#define FLEXIO_SHIFTBUFHWS_REG(base,index) ((base)->SHIFTBUFHWS[index])
#define FLEXIO_SHIFTBUFHWS_COUNT 8
#define FLEXIO_SHIFTBUFNIS_REG(base,index) ((base)->SHIFTBUFNIS[index])
#define FLEXIO_SHIFTBUFNIS_COUNT 8
/*!
* @}
*/ /* end of group FLEXIO_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FLEXIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
* @{
*/
/* VERID Bit Fields */
#define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
#define FLEXIO_VERID_FEATURE_SHIFT 0
#define FLEXIO_VERID_FEATURE_WIDTH 16
#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
#define FLEXIO_VERID_MINOR_MASK 0xFF0000u
#define FLEXIO_VERID_MINOR_SHIFT 16
#define FLEXIO_VERID_MINOR_WIDTH 8
#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
#define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
#define FLEXIO_VERID_MAJOR_SHIFT 24
#define FLEXIO_VERID_MAJOR_WIDTH 8
#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
#define FLEXIO_PARAM_SHIFTER_SHIFT 0
#define FLEXIO_PARAM_SHIFTER_WIDTH 8
#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
#define FLEXIO_PARAM_TIMER_MASK 0xFF00u
#define FLEXIO_PARAM_TIMER_SHIFT 8
#define FLEXIO_PARAM_TIMER_WIDTH 8
#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
#define FLEXIO_PARAM_PIN_MASK 0xFF0000u
#define FLEXIO_PARAM_PIN_SHIFT 16
#define FLEXIO_PARAM_PIN_WIDTH 8
#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
#define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
#define FLEXIO_PARAM_TRIGGER_SHIFT 24
#define FLEXIO_PARAM_TRIGGER_WIDTH 8
#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
/* CTRL Bit Fields */
#define FLEXIO_CTRL_FLEXEN_MASK 0x1u
#define FLEXIO_CTRL_FLEXEN_SHIFT 0
#define FLEXIO_CTRL_FLEXEN_WIDTH 1
#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
#define FLEXIO_CTRL_SWRST_MASK 0x2u
#define FLEXIO_CTRL_SWRST_SHIFT 1
#define FLEXIO_CTRL_SWRST_WIDTH 1
#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
#define FLEXIO_CTRL_FASTACC_MASK 0x4u
#define FLEXIO_CTRL_FASTACC_SHIFT 2
#define FLEXIO_CTRL_FASTACC_WIDTH 1
#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
#define FLEXIO_CTRL_DBGE_MASK 0x40000000u
#define FLEXIO_CTRL_DBGE_SHIFT 30
#define FLEXIO_CTRL_DBGE_WIDTH 1
#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
#define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
#define FLEXIO_CTRL_DOZEN_SHIFT 31
#define FLEXIO_CTRL_DOZEN_WIDTH 1
#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
/* PIN Bit Fields */
#define FLEXIO_PIN_PDI_MASK 0xFFFFFFFFu
#define FLEXIO_PIN_PDI_SHIFT 0
#define FLEXIO_PIN_PDI_WIDTH 32
#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PIN_PDI_SHIFT))&FLEXIO_PIN_PDI_MASK)
/* SHIFTSTAT Bit Fields */
#define FLEXIO_SHIFTSTAT_SSF_MASK 0xFFu
#define FLEXIO_SHIFTSTAT_SSF_SHIFT 0
#define FLEXIO_SHIFTSTAT_SSF_WIDTH 8
#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
/* SHIFTERR Bit Fields */
#define FLEXIO_SHIFTERR_SEF_MASK 0xFFu
#define FLEXIO_SHIFTERR_SEF_SHIFT 0
#define FLEXIO_SHIFTERR_SEF_WIDTH 8
#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
/* TIMSTAT Bit Fields */
#define FLEXIO_TIMSTAT_TSF_MASK 0xFFu
#define FLEXIO_TIMSTAT_TSF_SHIFT 0
#define FLEXIO_TIMSTAT_TSF_WIDTH 8
#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
/* SHIFTSIEN Bit Fields */
#define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFFu
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0
#define FLEXIO_SHIFTSIEN_SSIE_WIDTH 8
#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
/* SHIFTEIEN Bit Fields */
#define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFFu
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0
#define FLEXIO_SHIFTEIEN_SEIE_WIDTH 8
#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
/* TIMIEN Bit Fields */
#define FLEXIO_TIMIEN_TEIE_MASK 0xFFu
#define FLEXIO_TIMIEN_TEIE_SHIFT 0
#define FLEXIO_TIMIEN_TEIE_WIDTH 8
#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
/* SHIFTSDEN Bit Fields */
#define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFFu
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0
#define FLEXIO_SHIFTSDEN_SSDE_WIDTH 8
#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
/* SHIFTSTATE Bit Fields */
#define FLEXIO_SHIFTSTATE_STATE_MASK 0x7u
#define FLEXIO_SHIFTSTATE_STATE_SHIFT 0
#define FLEXIO_SHIFTSTATE_STATE_WIDTH 3
#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTATE_STATE_SHIFT))&FLEXIO_SHIFTSTATE_STATE_MASK)
/* SHIFTCTL Bit Fields */
#define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
#define FLEXIO_SHIFTCTL_SMOD_SHIFT 0
#define FLEXIO_SHIFTCTL_SMOD_WIDTH 3
#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
#define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7
#define FLEXIO_SHIFTCTL_PINPOL_WIDTH 1
#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
#define FLEXIO_SHIFTCTL_PINSEL_MASK 0x1F00u
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8
#define FLEXIO_SHIFTCTL_PINSEL_WIDTH 5
#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
#define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16
#define FLEXIO_SHIFTCTL_PINCFG_WIDTH 2
#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
#define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23
#define FLEXIO_SHIFTCTL_TIMPOL_WIDTH 1
#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x7000000u
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24
#define FLEXIO_SHIFTCTL_TIMSEL_WIDTH 3
#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
/* SHIFTCFG Bit Fields */
#define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
#define FLEXIO_SHIFTCFG_SSTART_SHIFT 0
#define FLEXIO_SHIFTCFG_SSTART_WIDTH 2
#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
#define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4
#define FLEXIO_SHIFTCFG_SSTOP_WIDTH 2
#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
#define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
#define FLEXIO_SHIFTCFG_INSRC_SHIFT 8
#define FLEXIO_SHIFTCFG_INSRC_WIDTH 1
#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
#define FLEXIO_SHIFTCFG_PWIDTH_MASK 0x1F0000u
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT 16
#define FLEXIO_SHIFTCFG_PWIDTH_WIDTH 5
#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_PWIDTH_SHIFT))&FLEXIO_SHIFTCFG_PWIDTH_MASK)
/* SHIFTBUF Bit Fields */
#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0
#define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH 32
#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/* SHIFTBUFBIS Bit Fields */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH 32
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/* SHIFTBUFBYS Bit Fields */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH 32
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/* SHIFTBUFBBS Bit Fields */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH 32
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/* TIMCTL Bit Fields */
#define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
#define FLEXIO_TIMCTL_TIMOD_SHIFT 0
#define FLEXIO_TIMCTL_TIMOD_WIDTH 2
#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
#define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
#define FLEXIO_TIMCTL_PINPOL_SHIFT 7
#define FLEXIO_TIMCTL_PINPOL_WIDTH 1
#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
#define FLEXIO_TIMCTL_PINSEL_MASK 0x1F00u
#define FLEXIO_TIMCTL_PINSEL_SHIFT 8
#define FLEXIO_TIMCTL_PINSEL_WIDTH 5
#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
#define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
#define FLEXIO_TIMCTL_PINCFG_SHIFT 16
#define FLEXIO_TIMCTL_PINCFG_WIDTH 2
#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
#define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
#define FLEXIO_TIMCTL_TRGSRC_SHIFT 22
#define FLEXIO_TIMCTL_TRGSRC_WIDTH 1
#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
#define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
#define FLEXIO_TIMCTL_TRGPOL_SHIFT 23
#define FLEXIO_TIMCTL_TRGPOL_WIDTH 1
#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
#define FLEXIO_TIMCTL_TRGSEL_MASK 0x3F000000u
#define FLEXIO_TIMCTL_TRGSEL_SHIFT 24
#define FLEXIO_TIMCTL_TRGSEL_WIDTH 6
#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
/* TIMCFG Bit Fields */
#define FLEXIO_TIMCFG_TSTART_MASK 0x2u
#define FLEXIO_TIMCFG_TSTART_SHIFT 1
#define FLEXIO_TIMCFG_TSTART_WIDTH 1
#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
#define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
#define FLEXIO_TIMCFG_TSTOP_SHIFT 4
#define FLEXIO_TIMCFG_TSTOP_WIDTH 2
#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
#define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
#define FLEXIO_TIMCFG_TIMENA_SHIFT 8
#define FLEXIO_TIMCFG_TIMENA_WIDTH 3
#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
#define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
#define FLEXIO_TIMCFG_TIMDIS_SHIFT 12
#define FLEXIO_TIMCFG_TIMDIS_WIDTH 3
#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
#define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
#define FLEXIO_TIMCFG_TIMRST_SHIFT 16
#define FLEXIO_TIMCFG_TIMRST_WIDTH 3
#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
#define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
#define FLEXIO_TIMCFG_TIMDEC_SHIFT 20
#define FLEXIO_TIMCFG_TIMDEC_WIDTH 2
#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
#define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
#define FLEXIO_TIMCFG_TIMOUT_SHIFT 24
#define FLEXIO_TIMCFG_TIMOUT_WIDTH 2
#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
/* TIMCMP Bit Fields */
#define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
#define FLEXIO_TIMCMP_CMP_SHIFT 0
#define FLEXIO_TIMCMP_CMP_WIDTH 16
#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
/* SHIFTBUFNBS Bit Fields */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT 0
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_WIDTH 32
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT))&FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
/* SHIFTBUFHWS Bit Fields */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT 0
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_WIDTH 32
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT))&FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
/* SHIFTBUFNIS Bit Fields */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT 0
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_WIDTH 32
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT))&FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
/*!
* @}
*/ /* end of group FLEXIO_Register_Masks */
/* FLEXIO - Peripheral instance base addresses */
/** Peripheral FLEXIO0 base address */
#define FLEXIO0_BASE (0x400CA000u)
/** Peripheral FLEXIO0 base pointer */
#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
#define FLEXIO0_BASE_PTR (FLEXIO0)
/** Array initializer of FLEXIO peripheral base addresses */
#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE }
/** Array initializer of FLEXIO peripheral base pointers */
#define FLEXIO_BASE_PTRS { FLEXIO0 }
/* ----------------------------------------------------------------------------
-- FLEXIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
* @{
*/
/* FLEXIO - Register instance definitions */
/* FLEXIO0 */
#define FLEXIO0_VERID FLEXIO_VERID_REG(FLEXIO0)
#define FLEXIO0_PARAM FLEXIO_PARAM_REG(FLEXIO0)
#define FLEXIO0_CTRL FLEXIO_CTRL_REG(FLEXIO0)
#define FLEXIO0_PIN FLEXIO_PIN_REG(FLEXIO0)
#define FLEXIO0_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO0)
#define FLEXIO0_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO0)
#define FLEXIO0_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO0)
#define FLEXIO0_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO0)
#define FLEXIO0_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO0)
#define FLEXIO0_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO0)
#define FLEXIO0_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO0)
#define FLEXIO0_SHIFTSTATE FLEXIO_SHIFTSTATE_REG(FLEXIO0)
#define FLEXIO0_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTCTL4 FLEXIO_SHIFTCTL_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTCTL5 FLEXIO_SHIFTCTL_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTCTL6 FLEXIO_SHIFTCTL_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTCTL7 FLEXIO_SHIFTCTL_REG(FLEXIO0,7)
#define FLEXIO0_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTCFG4 FLEXIO_SHIFTCFG_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTCFG5 FLEXIO_SHIFTCFG_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTCFG6 FLEXIO_SHIFTCFG_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTCFG7 FLEXIO_SHIFTCFG_REG(FLEXIO0,7)
#define FLEXIO0_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTBUF4 FLEXIO_SHIFTBUF_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTBUF5 FLEXIO_SHIFTBUF_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTBUF6 FLEXIO_SHIFTBUF_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTBUF7 FLEXIO_SHIFTBUF_REG(FLEXIO0,7)
#define FLEXIO0_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTBUFBIS4 FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTBUFBIS5 FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTBUFBIS6 FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTBUFBIS7 FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,7)
#define FLEXIO0_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTBUFBYS4 FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTBUFBYS5 FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTBUFBYS6 FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTBUFBYS7 FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,7)
#define FLEXIO0_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTBUFBBS4 FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTBUFBBS5 FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTBUFBBS6 FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTBUFBBS7 FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,7)
#define FLEXIO0_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO0,0)
#define FLEXIO0_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO0,1)
#define FLEXIO0_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO0,2)
#define FLEXIO0_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO0,3)
#define FLEXIO0_TIMCTL4 FLEXIO_TIMCTL_REG(FLEXIO0,4)
#define FLEXIO0_TIMCTL5 FLEXIO_TIMCTL_REG(FLEXIO0,5)
#define FLEXIO0_TIMCTL6 FLEXIO_TIMCTL_REG(FLEXIO0,6)
#define FLEXIO0_TIMCTL7 FLEXIO_TIMCTL_REG(FLEXIO0,7)
#define FLEXIO0_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO0,0)
#define FLEXIO0_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO0,1)
#define FLEXIO0_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO0,2)
#define FLEXIO0_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO0,3)
#define FLEXIO0_TIMCFG4 FLEXIO_TIMCFG_REG(FLEXIO0,4)
#define FLEXIO0_TIMCFG5 FLEXIO_TIMCFG_REG(FLEXIO0,5)
#define FLEXIO0_TIMCFG6 FLEXIO_TIMCFG_REG(FLEXIO0,6)
#define FLEXIO0_TIMCFG7 FLEXIO_TIMCFG_REG(FLEXIO0,7)
#define FLEXIO0_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO0,0)
#define FLEXIO0_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO0,1)
#define FLEXIO0_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO0,2)
#define FLEXIO0_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO0,3)
#define FLEXIO0_TIMCMP4 FLEXIO_TIMCMP_REG(FLEXIO0,4)
#define FLEXIO0_TIMCMP5 FLEXIO_TIMCMP_REG(FLEXIO0,5)
#define FLEXIO0_TIMCMP6 FLEXIO_TIMCMP_REG(FLEXIO0,6)
#define FLEXIO0_TIMCMP7 FLEXIO_TIMCMP_REG(FLEXIO0,7)
#define FLEXIO0_SHIFTBUFNBS0 FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTBUFNBS1 FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTBUFNBS2 FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTBUFNBS3 FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTBUFNBS4 FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTBUFNBS5 FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTBUFNBS6 FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTBUFNBS7 FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,7)
#define FLEXIO0_SHIFTBUFHWS0 FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTBUFHWS1 FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTBUFHWS2 FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTBUFHWS3 FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTBUFHWS4 FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTBUFHWS5 FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTBUFHWS6 FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTBUFHWS7 FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,7)
#define FLEXIO0_SHIFTBUFNIS0 FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,0)
#define FLEXIO0_SHIFTBUFNIS1 FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,1)
#define FLEXIO0_SHIFTBUFNIS2 FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,2)
#define FLEXIO0_SHIFTBUFNIS3 FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,3)
#define FLEXIO0_SHIFTBUFNIS4 FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,4)
#define FLEXIO0_SHIFTBUFNIS5 FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,5)
#define FLEXIO0_SHIFTBUFNIS6 FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,6)
#define FLEXIO0_SHIFTBUFNIS7 FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,7)
/* FLEXIO - Register array accessors */
#define FLEXIO0_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO0,index)
#define FLEXIO0_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO0,index)
#define FLEXIO0_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO0,index)
#define FLEXIO0_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO0,index)
#define FLEXIO0_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO0,index)
#define FLEXIO0_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO0,index)
#define FLEXIO0_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO0,index)
#define FLEXIO0_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO0,index)
#define FLEXIO0_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO0,index)
#define FLEXIO0_SHIFTBUFNBS(index) FLEXIO_SHIFTBUFNBS_REG(FLEXIO0,index)
#define FLEXIO0_SHIFTBUFHWS(index) FLEXIO_SHIFTBUFHWS_REG(FLEXIO0,index)
#define FLEXIO0_SHIFTBUFNIS(index) FLEXIO_SHIFTBUFNIS_REG(FLEXIO0,index)
/*!
* @}
*/ /* end of group FLEXIO_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group FLEXIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FTFA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
* @{
*/
/** FTFA - Register Layout Typedef */
typedef struct {
__IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
__IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
__I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
__I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
__IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
__IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
__IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
__IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
__IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
__IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
__IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
__IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
__IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
__IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
__IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
__IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
__IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
__IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
__IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
__IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
uint8_t RESERVED_0[4];
__I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
__I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
__I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
__I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
__I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
__I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
__I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
__I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
__I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
__I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
__I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
__I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
__I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
__I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
__I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
__I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
__I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
uint8_t RESERVED_1[2];
__I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
} FTFA_Type, *FTFA_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FTFA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
* @{
*/
/* FTFA - Register accessors */
#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
#define FTFA_FSEC_REG(base) ((base)->FSEC)
#define FTFA_FOPT_REG(base) ((base)->FOPT)
#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
#define FTFA_XACCH3_REG(base) ((base)->XACCH3)
#define FTFA_XACCH2_REG(base) ((base)->XACCH2)
#define FTFA_XACCH1_REG(base) ((base)->XACCH1)
#define FTFA_XACCH0_REG(base) ((base)->XACCH0)
#define FTFA_XACCL3_REG(base) ((base)->XACCL3)
#define FTFA_XACCL2_REG(base) ((base)->XACCL2)
#define FTFA_XACCL1_REG(base) ((base)->XACCL1)
#define FTFA_XACCL0_REG(base) ((base)->XACCL0)
#define FTFA_SACCH3_REG(base) ((base)->SACCH3)
#define FTFA_SACCH2_REG(base) ((base)->SACCH2)
#define FTFA_SACCH1_REG(base) ((base)->SACCH1)
#define FTFA_SACCH0_REG(base) ((base)->SACCH0)
#define FTFA_SACCL3_REG(base) ((base)->SACCL3)
#define FTFA_SACCL2_REG(base) ((base)->SACCL2)
#define FTFA_SACCL1_REG(base) ((base)->SACCL1)
#define FTFA_SACCL0_REG(base) ((base)->SACCL0)
#define FTFA_FACSS_REG(base) ((base)->FACSS)
#define FTFA_FACSN_REG(base) ((base)->FACSN)
/*!
* @}
*/ /* end of group FTFA_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FTFA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Masks FTFA Register Masks
* @{
*/
/* FSTAT Bit Fields */
#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
#define FTFA_FSTAT_MGSTAT0_SHIFT 0
#define FTFA_FSTAT_MGSTAT0_WIDTH 1
#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_MGSTAT0_SHIFT))&FTFA_FSTAT_MGSTAT0_MASK)
#define FTFA_FSTAT_FPVIOL_MASK 0x10u
#define FTFA_FSTAT_FPVIOL_SHIFT 4
#define FTFA_FSTAT_FPVIOL_WIDTH 1
#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_FPVIOL_SHIFT))&FTFA_FSTAT_FPVIOL_MASK)
#define FTFA_FSTAT_ACCERR_MASK 0x20u
#define FTFA_FSTAT_ACCERR_SHIFT 5
#define FTFA_FSTAT_ACCERR_WIDTH 1
#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_ACCERR_SHIFT))&FTFA_FSTAT_ACCERR_MASK)
#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
#define FTFA_FSTAT_RDCOLERR_SHIFT 6
#define FTFA_FSTAT_RDCOLERR_WIDTH 1
#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_RDCOLERR_SHIFT))&FTFA_FSTAT_RDCOLERR_MASK)
#define FTFA_FSTAT_CCIF_MASK 0x80u
#define FTFA_FSTAT_CCIF_SHIFT 7
#define FTFA_FSTAT_CCIF_WIDTH 1
#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_CCIF_SHIFT))&FTFA_FSTAT_CCIF_MASK)
/* FCNFG Bit Fields */
#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
#define FTFA_FCNFG_ERSSUSP_SHIFT 4
#define FTFA_FCNFG_ERSSUSP_WIDTH 1
#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSSUSP_SHIFT))&FTFA_FCNFG_ERSSUSP_MASK)
#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
#define FTFA_FCNFG_ERSAREQ_SHIFT 5
#define FTFA_FCNFG_ERSAREQ_WIDTH 1
#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSAREQ_SHIFT))&FTFA_FCNFG_ERSAREQ_MASK)
#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
#define FTFA_FCNFG_RDCOLLIE_WIDTH 1
#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_RDCOLLIE_SHIFT))&FTFA_FCNFG_RDCOLLIE_MASK)
#define FTFA_FCNFG_CCIE_MASK 0x80u
#define FTFA_FCNFG_CCIE_SHIFT 7
#define FTFA_FCNFG_CCIE_WIDTH 1
#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_CCIE_SHIFT))&FTFA_FCNFG_CCIE_MASK)
/* FSEC Bit Fields */
#define FTFA_FSEC_SEC_MASK 0x3u
#define FTFA_FSEC_SEC_SHIFT 0
#define FTFA_FSEC_SEC_WIDTH 2
#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
#define FTFA_FSEC_FSLACC_MASK 0xCu
#define FTFA_FSEC_FSLACC_SHIFT 2
#define FTFA_FSEC_FSLACC_WIDTH 2
#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
#define FTFA_FSEC_MEEN_MASK 0x30u
#define FTFA_FSEC_MEEN_SHIFT 4
#define FTFA_FSEC_MEEN_WIDTH 2
#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
#define FTFA_FSEC_KEYEN_MASK 0xC0u
#define FTFA_FSEC_KEYEN_SHIFT 6
#define FTFA_FSEC_KEYEN_WIDTH 2
#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
/* FOPT Bit Fields */
#define FTFA_FOPT_OPT_MASK 0xFFu
#define FTFA_FOPT_OPT_SHIFT 0
#define FTFA_FOPT_OPT_WIDTH 8
#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
/* FCCOB3 Bit Fields */
#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
#define FTFA_FCCOB3_CCOBn_SHIFT 0
#define FTFA_FCCOB3_CCOBn_WIDTH 8
#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
/* FCCOB2 Bit Fields */
#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
#define FTFA_FCCOB2_CCOBn_SHIFT 0
#define FTFA_FCCOB2_CCOBn_WIDTH 8
#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
/* FCCOB1 Bit Fields */
#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
#define FTFA_FCCOB1_CCOBn_SHIFT 0
#define FTFA_FCCOB1_CCOBn_WIDTH 8
#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
/* FCCOB0 Bit Fields */
#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
#define FTFA_FCCOB0_CCOBn_SHIFT 0
#define FTFA_FCCOB0_CCOBn_WIDTH 8
#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
/* FCCOB7 Bit Fields */
#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
#define FTFA_FCCOB7_CCOBn_SHIFT 0
#define FTFA_FCCOB7_CCOBn_WIDTH 8
#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
/* FCCOB6 Bit Fields */
#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
#define FTFA_FCCOB6_CCOBn_SHIFT 0
#define FTFA_FCCOB6_CCOBn_WIDTH 8
#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
/* FCCOB5 Bit Fields */
#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
#define FTFA_FCCOB5_CCOBn_SHIFT 0
#define FTFA_FCCOB5_CCOBn_WIDTH 8
#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
/* FCCOB4 Bit Fields */
#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
#define FTFA_FCCOB4_CCOBn_SHIFT 0
#define FTFA_FCCOB4_CCOBn_WIDTH 8
#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
/* FCCOBB Bit Fields */
#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
#define FTFA_FCCOBB_CCOBn_SHIFT 0
#define FTFA_FCCOBB_CCOBn_WIDTH 8
#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
/* FCCOBA Bit Fields */
#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
#define FTFA_FCCOBA_CCOBn_SHIFT 0
#define FTFA_FCCOBA_CCOBn_WIDTH 8
#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
/* FCCOB9 Bit Fields */
#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
#define FTFA_FCCOB9_CCOBn_SHIFT 0
#define FTFA_FCCOB9_CCOBn_WIDTH 8
#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
/* FCCOB8 Bit Fields */
#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
#define FTFA_FCCOB8_CCOBn_SHIFT 0
#define FTFA_FCCOB8_CCOBn_WIDTH 8
#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
/* FPROT3 Bit Fields */
#define FTFA_FPROT3_PROT_MASK 0xFFu
#define FTFA_FPROT3_PROT_SHIFT 0
#define FTFA_FPROT3_PROT_WIDTH 8
#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
/* FPROT2 Bit Fields */
#define FTFA_FPROT2_PROT_MASK 0xFFu
#define FTFA_FPROT2_PROT_SHIFT 0
#define FTFA_FPROT2_PROT_WIDTH 8
#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
/* FPROT1 Bit Fields */
#define FTFA_FPROT1_PROT_MASK 0xFFu
#define FTFA_FPROT1_PROT_SHIFT 0
#define FTFA_FPROT1_PROT_WIDTH 8
#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
/* FPROT0 Bit Fields */
#define FTFA_FPROT0_PROT_MASK 0xFFu
#define FTFA_FPROT0_PROT_SHIFT 0
#define FTFA_FPROT0_PROT_WIDTH 8
#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
/* XACCH3 Bit Fields */
#define FTFA_XACCH3_XA_MASK 0xFFu
#define FTFA_XACCH3_XA_SHIFT 0
#define FTFA_XACCH3_XA_WIDTH 8
#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
/* XACCH2 Bit Fields */
#define FTFA_XACCH2_XA_MASK 0xFFu
#define FTFA_XACCH2_XA_SHIFT 0
#define FTFA_XACCH2_XA_WIDTH 8
#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
/* XACCH1 Bit Fields */
#define FTFA_XACCH1_XA_MASK 0xFFu
#define FTFA_XACCH1_XA_SHIFT 0
#define FTFA_XACCH1_XA_WIDTH 8
#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
/* XACCH0 Bit Fields */
#define FTFA_XACCH0_XA_MASK 0xFFu
#define FTFA_XACCH0_XA_SHIFT 0
#define FTFA_XACCH0_XA_WIDTH 8
#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
/* XACCL3 Bit Fields */
#define FTFA_XACCL3_XA_MASK 0xFFu
#define FTFA_XACCL3_XA_SHIFT 0
#define FTFA_XACCL3_XA_WIDTH 8
#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
/* XACCL2 Bit Fields */
#define FTFA_XACCL2_XA_MASK 0xFFu
#define FTFA_XACCL2_XA_SHIFT 0
#define FTFA_XACCL2_XA_WIDTH 8
#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
/* XACCL1 Bit Fields */
#define FTFA_XACCL1_XA_MASK 0xFFu
#define FTFA_XACCL1_XA_SHIFT 0
#define FTFA_XACCL1_XA_WIDTH 8
#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
/* XACCL0 Bit Fields */
#define FTFA_XACCL0_XA_MASK 0xFFu
#define FTFA_XACCL0_XA_SHIFT 0
#define FTFA_XACCL0_XA_WIDTH 8
#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
/* SACCH3 Bit Fields */
#define FTFA_SACCH3_SA_MASK 0xFFu
#define FTFA_SACCH3_SA_SHIFT 0
#define FTFA_SACCH3_SA_WIDTH 8
#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
/* SACCH2 Bit Fields */
#define FTFA_SACCH2_SA_MASK 0xFFu
#define FTFA_SACCH2_SA_SHIFT 0
#define FTFA_SACCH2_SA_WIDTH 8
#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
/* SACCH1 Bit Fields */
#define FTFA_SACCH1_SA_MASK 0xFFu
#define FTFA_SACCH1_SA_SHIFT 0
#define FTFA_SACCH1_SA_WIDTH 8
#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
/* SACCH0 Bit Fields */
#define FTFA_SACCH0_SA_MASK 0xFFu
#define FTFA_SACCH0_SA_SHIFT 0
#define FTFA_SACCH0_SA_WIDTH 8
#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
/* SACCL3 Bit Fields */
#define FTFA_SACCL3_SA_MASK 0xFFu
#define FTFA_SACCL3_SA_SHIFT 0
#define FTFA_SACCL3_SA_WIDTH 8
#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
/* SACCL2 Bit Fields */
#define FTFA_SACCL2_SA_MASK 0xFFu
#define FTFA_SACCL2_SA_SHIFT 0
#define FTFA_SACCL2_SA_WIDTH 8
#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
/* SACCL1 Bit Fields */
#define FTFA_SACCL1_SA_MASK 0xFFu
#define FTFA_SACCL1_SA_SHIFT 0
#define FTFA_SACCL1_SA_WIDTH 8
#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
/* SACCL0 Bit Fields */
#define FTFA_SACCL0_SA_MASK 0xFFu
#define FTFA_SACCL0_SA_SHIFT 0
#define FTFA_SACCL0_SA_WIDTH 8
#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
/* FACSS Bit Fields */
#define FTFA_FACSS_SGSIZE_MASK 0xFFu
#define FTFA_FACSS_SGSIZE_SHIFT 0
#define FTFA_FACSS_SGSIZE_WIDTH 8
#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
/* FACSN Bit Fields */
#define FTFA_FACSN_NUMSG_MASK 0xFFu
#define FTFA_FACSN_NUMSG_SHIFT 0
#define FTFA_FACSN_NUMSG_WIDTH 8
#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
/*!
* @}
*/ /* end of group FTFA_Register_Masks */
/* FTFA - Peripheral instance base addresses */
/** Peripheral FTFA base address */
#define FTFA_BASE (0x40020000u)
/** Peripheral FTFA base pointer */
#define FTFA ((FTFA_Type *)FTFA_BASE)
#define FTFA_BASE_PTR (FTFA)
/** Array initializer of FTFA peripheral base addresses */
#define FTFA_BASE_ADDRS { FTFA_BASE }
/** Array initializer of FTFA peripheral base pointers */
#define FTFA_BASE_PTRS { FTFA }
/* ----------------------------------------------------------------------------
-- FTFA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
* @{
*/
/* FTFA - Register instance definitions */
/* FTFA */
#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
#define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
#define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
#define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
#define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
#define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
#define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
#define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
#define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
#define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
#define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
#define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
#define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
#define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
#define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
#define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
#define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
#define FTFA_FACSS FTFA_FACSS_REG(FTFA)
#define FTFA_FACSN FTFA_FACSN_REG(FTFA)
/*!
* @}
*/ /* end of group FTFA_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group FTFA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} GPIO_Type, *GPIO_MemMapPtr;
/* ----------------------------------------------------------------------------
-- GPIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
* @{
*/
/* GPIO - Register accessors */
#define GPIO_PDOR_REG(base) ((base)->PDOR)
#define GPIO_PSOR_REG(base) ((base)->PSOR)
#define GPIO_PCOR_REG(base) ((base)->PCOR)
#define GPIO_PTOR_REG(base) ((base)->PTOR)
#define GPIO_PDIR_REG(base) ((base)->PDIR)
#define GPIO_PDDR_REG(base) ((base)->PDDR)
/*!
* @}
*/ /* end of group GPIO_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/* PDOR Bit Fields */
#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
#define GPIO_PDOR_PDO_SHIFT 0
#define GPIO_PDOR_PDO_WIDTH 32
#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
/* PSOR Bit Fields */
#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
#define GPIO_PSOR_PTSO_SHIFT 0
#define GPIO_PSOR_PTSO_WIDTH 32
#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
/* PCOR Bit Fields */
#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
#define GPIO_PCOR_PTCO_SHIFT 0
#define GPIO_PCOR_PTCO_WIDTH 32
#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
/* PTOR Bit Fields */
#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
#define GPIO_PTOR_PTTO_SHIFT 0
#define GPIO_PTOR_PTTO_WIDTH 32
#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
/* PDIR Bit Fields */
#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
#define GPIO_PDIR_PDI_SHIFT 0
#define GPIO_PDIR_PDI_WIDTH 32
#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
/* PDDR Bit Fields */
#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
#define GPIO_PDDR_PDD_SHIFT 0
#define GPIO_PDDR_PDD_WIDTH 32
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIOA base address */
#define GPIOA_BASE (0x4000F000u)
/** Peripheral GPIOA base pointer */
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
#define GPIOA_BASE_PTR (GPIOA)
/** Peripheral GPIOB base address */
#define GPIOB_BASE (0x4000F040u)
/** Peripheral GPIOB base pointer */
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
#define GPIOB_BASE_PTR (GPIOB)
/** Peripheral GPIOC base address */
#define GPIOC_BASE (0x4000F080u)
/** Peripheral GPIOC base pointer */
#define GPIOC ((GPIO_Type *)GPIOC_BASE)
#define GPIOC_BASE_PTR (GPIOC)
/** Peripheral GPIOD base address */
#define GPIOD_BASE (0x4000F0C0u)
/** Peripheral GPIOD base pointer */
#define GPIOD ((GPIO_Type *)GPIOD_BASE)
#define GPIOD_BASE_PTR (GPIOD)
/** Peripheral GPIOE base address */
#define GPIOE_BASE (0x4000F100u)
/** Peripheral GPIOE base pointer */
#define GPIOE ((GPIO_Type *)GPIOE_BASE)
#define GPIOE_BASE_PTR (GPIOE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
/* ----------------------------------------------------------------------------
-- GPIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
* @{
*/
/* GPIO - Register instance definitions */
/* GPIOA */
#define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
#define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
#define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
#define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
#define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
#define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
/* GPIOB */
#define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
#define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
#define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
#define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
#define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
#define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
/* GPIOC */
#define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
#define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
#define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
#define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
#define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
#define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
/* GPIOD */
#define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
#define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
#define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
#define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
#define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
#define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
/* GPIOE */
#define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
#define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
#define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
#define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
#define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
#define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
/*!
* @}
*/ /* end of group GPIO_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2S Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
* @{
*/
/** I2S - Register Layout Typedef */
typedef struct {
__IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
__IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
__IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
__IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
__IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
__IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
uint8_t RESERVED_0[8];
__O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_1[28];
__I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
uint8_t RESERVED_2[28];
__IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
uint8_t RESERVED_3[28];
__IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
__IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
__IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
__IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
__IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
__IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
uint8_t RESERVED_4[8];
__I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
uint8_t RESERVED_5[28];
__I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_6[28];
__IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
} I2S_Type, *I2S_MemMapPtr;
/* ----------------------------------------------------------------------------
-- I2S - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
* @{
*/
/* I2S - Register accessors */
#define I2S_TCSR_REG(base) ((base)->TCSR)
#define I2S_TCR1_REG(base) ((base)->TCR1)
#define I2S_TCR2_REG(base) ((base)->TCR2)
#define I2S_TCR3_REG(base) ((base)->TCR3)
#define I2S_TCR4_REG(base) ((base)->TCR4)
#define I2S_TCR5_REG(base) ((base)->TCR5)
#define I2S_TDR_REG(base,index) ((base)->TDR[index])
#define I2S_TDR_COUNT 1
#define I2S_TFR_REG(base,index) ((base)->TFR[index])
#define I2S_TFR_COUNT 1
#define I2S_TMR_REG(base) ((base)->TMR)
#define I2S_RCSR_REG(base) ((base)->RCSR)
#define I2S_RCR1_REG(base) ((base)->RCR1)
#define I2S_RCR2_REG(base) ((base)->RCR2)
#define I2S_RCR3_REG(base) ((base)->RCR3)
#define I2S_RCR4_REG(base) ((base)->RCR4)
#define I2S_RCR5_REG(base) ((base)->RCR5)
#define I2S_RDR_REG(base,index) ((base)->RDR[index])
#define I2S_RDR_COUNT 1
#define I2S_RFR_REG(base,index) ((base)->RFR[index])
#define I2S_RFR_COUNT 1
#define I2S_RMR_REG(base) ((base)->RMR)
/*!
* @}
*/ /* end of group I2S_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- I2S Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Masks I2S Register Masks
* @{
*/
/* TCSR Bit Fields */
#define I2S_TCSR_FRDE_MASK 0x1u
#define I2S_TCSR_FRDE_SHIFT 0
#define I2S_TCSR_FRDE_WIDTH 1
#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
#define I2S_TCSR_FWDE_MASK 0x2u
#define I2S_TCSR_FWDE_SHIFT 1
#define I2S_TCSR_FWDE_WIDTH 1
#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
#define I2S_TCSR_FRIE_MASK 0x100u
#define I2S_TCSR_FRIE_SHIFT 8
#define I2S_TCSR_FRIE_WIDTH 1
#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
#define I2S_TCSR_FWIE_MASK 0x200u
#define I2S_TCSR_FWIE_SHIFT 9
#define I2S_TCSR_FWIE_WIDTH 1
#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
#define I2S_TCSR_FEIE_MASK 0x400u
#define I2S_TCSR_FEIE_SHIFT 10
#define I2S_TCSR_FEIE_WIDTH 1
#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
#define I2S_TCSR_SEIE_MASK 0x800u
#define I2S_TCSR_SEIE_SHIFT 11
#define I2S_TCSR_SEIE_WIDTH 1
#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
#define I2S_TCSR_WSIE_MASK 0x1000u
#define I2S_TCSR_WSIE_SHIFT 12
#define I2S_TCSR_WSIE_WIDTH 1
#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
#define I2S_TCSR_FRF_MASK 0x10000u
#define I2S_TCSR_FRF_SHIFT 16
#define I2S_TCSR_FRF_WIDTH 1
#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
#define I2S_TCSR_FWF_MASK 0x20000u
#define I2S_TCSR_FWF_SHIFT 17
#define I2S_TCSR_FWF_WIDTH 1
#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
#define I2S_TCSR_FEF_MASK 0x40000u
#define I2S_TCSR_FEF_SHIFT 18
#define I2S_TCSR_FEF_WIDTH 1
#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
#define I2S_TCSR_SEF_MASK 0x80000u
#define I2S_TCSR_SEF_SHIFT 19
#define I2S_TCSR_SEF_WIDTH 1
#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
#define I2S_TCSR_WSF_MASK 0x100000u
#define I2S_TCSR_WSF_SHIFT 20
#define I2S_TCSR_WSF_WIDTH 1
#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
#define I2S_TCSR_SR_MASK 0x1000000u
#define I2S_TCSR_SR_SHIFT 24
#define I2S_TCSR_SR_WIDTH 1
#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
#define I2S_TCSR_FR_MASK 0x2000000u
#define I2S_TCSR_FR_SHIFT 25
#define I2S_TCSR_FR_WIDTH 1
#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
#define I2S_TCSR_BCE_MASK 0x10000000u
#define I2S_TCSR_BCE_SHIFT 28
#define I2S_TCSR_BCE_WIDTH 1
#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
#define I2S_TCSR_DBGE_MASK 0x20000000u
#define I2S_TCSR_DBGE_SHIFT 29
#define I2S_TCSR_DBGE_WIDTH 1
#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
#define I2S_TCSR_STOPE_MASK 0x40000000u
#define I2S_TCSR_STOPE_SHIFT 30
#define I2S_TCSR_STOPE_WIDTH 1
#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
#define I2S_TCSR_TE_MASK 0x80000000u
#define I2S_TCSR_TE_SHIFT 31
#define I2S_TCSR_TE_WIDTH 1
#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
/* TCR1 Bit Fields */
#define I2S_TCR1_TFW_MASK 0x3u
#define I2S_TCR1_TFW_SHIFT 0
#define I2S_TCR1_TFW_WIDTH 2
#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
/* TCR2 Bit Fields */
#define I2S_TCR2_DIV_MASK 0xFFu
#define I2S_TCR2_DIV_SHIFT 0
#define I2S_TCR2_DIV_WIDTH 8
#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
#define I2S_TCR2_BCD_MASK 0x1000000u
#define I2S_TCR2_BCD_SHIFT 24
#define I2S_TCR2_BCD_WIDTH 1
#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
#define I2S_TCR2_BCP_MASK 0x2000000u
#define I2S_TCR2_BCP_SHIFT 25
#define I2S_TCR2_BCP_WIDTH 1
#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
#define I2S_TCR2_MSEL_MASK 0xC000000u
#define I2S_TCR2_MSEL_SHIFT 26
#define I2S_TCR2_MSEL_WIDTH 2
#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
#define I2S_TCR2_BCI_MASK 0x10000000u
#define I2S_TCR2_BCI_SHIFT 28
#define I2S_TCR2_BCI_WIDTH 1
#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
#define I2S_TCR2_BCS_MASK 0x20000000u
#define I2S_TCR2_BCS_SHIFT 29
#define I2S_TCR2_BCS_WIDTH 1
#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
#define I2S_TCR2_SYNC_MASK 0xC0000000u
#define I2S_TCR2_SYNC_SHIFT 30
#define I2S_TCR2_SYNC_WIDTH 2
#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
/* TCR3 Bit Fields */
#define I2S_TCR3_WDFL_MASK 0xFu
#define I2S_TCR3_WDFL_SHIFT 0
#define I2S_TCR3_WDFL_WIDTH 4
#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
#define I2S_TCR3_TCE_MASK 0x10000u
#define I2S_TCR3_TCE_SHIFT 16
#define I2S_TCR3_TCE_WIDTH 1
#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
/* TCR4 Bit Fields */
#define I2S_TCR4_FSD_MASK 0x1u
#define I2S_TCR4_FSD_SHIFT 0
#define I2S_TCR4_FSD_WIDTH 1
#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
#define I2S_TCR4_FSP_MASK 0x2u
#define I2S_TCR4_FSP_SHIFT 1
#define I2S_TCR4_FSP_WIDTH 1
#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
#define I2S_TCR4_ONDEM_MASK 0x4u
#define I2S_TCR4_ONDEM_SHIFT 2
#define I2S_TCR4_ONDEM_WIDTH 1
#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_ONDEM_SHIFT))&I2S_TCR4_ONDEM_MASK)
#define I2S_TCR4_FSE_MASK 0x8u
#define I2S_TCR4_FSE_SHIFT 3
#define I2S_TCR4_FSE_WIDTH 1
#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
#define I2S_TCR4_MF_MASK 0x10u
#define I2S_TCR4_MF_SHIFT 4
#define I2S_TCR4_MF_WIDTH 1
#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
#define I2S_TCR4_SYWD_MASK 0x1F00u
#define I2S_TCR4_SYWD_SHIFT 8
#define I2S_TCR4_SYWD_WIDTH 5
#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
#define I2S_TCR4_FRSZ_MASK 0xF0000u
#define I2S_TCR4_FRSZ_SHIFT 16
#define I2S_TCR4_FRSZ_WIDTH 4
#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
#define I2S_TCR4_FPACK_MASK 0x3000000u
#define I2S_TCR4_FPACK_SHIFT 24
#define I2S_TCR4_FPACK_WIDTH 2
#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
#define I2S_TCR4_FCONT_MASK 0x10000000u
#define I2S_TCR4_FCONT_SHIFT 28
#define I2S_TCR4_FCONT_WIDTH 1
#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FCONT_SHIFT))&I2S_TCR4_FCONT_MASK)
/* TCR5 Bit Fields */
#define I2S_TCR5_FBT_MASK 0x1F00u
#define I2S_TCR5_FBT_SHIFT 8
#define I2S_TCR5_FBT_WIDTH 5
#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
#define I2S_TCR5_W0W_MASK 0x1F0000u
#define I2S_TCR5_W0W_SHIFT 16
#define I2S_TCR5_W0W_WIDTH 5
#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
#define I2S_TCR5_WNW_MASK 0x1F000000u
#define I2S_TCR5_WNW_SHIFT 24
#define I2S_TCR5_WNW_WIDTH 5
#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
/* TDR Bit Fields */
#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
#define I2S_TDR_TDR_SHIFT 0
#define I2S_TDR_TDR_WIDTH 32
#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
/* TFR Bit Fields */
#define I2S_TFR_RFP_MASK 0x7u
#define I2S_TFR_RFP_SHIFT 0
#define I2S_TFR_RFP_WIDTH 3
#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
#define I2S_TFR_WFP_MASK 0x70000u
#define I2S_TFR_WFP_SHIFT 16
#define I2S_TFR_WFP_WIDTH 3
#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
/* TMR Bit Fields */
#define I2S_TMR_TWM_MASK 0xFFFFu
#define I2S_TMR_TWM_SHIFT 0
#define I2S_TMR_TWM_WIDTH 16
#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
/* RCSR Bit Fields */
#define I2S_RCSR_FRDE_MASK 0x1u
#define I2S_RCSR_FRDE_SHIFT 0
#define I2S_RCSR_FRDE_WIDTH 1
#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
#define I2S_RCSR_FWDE_MASK 0x2u
#define I2S_RCSR_FWDE_SHIFT 1
#define I2S_RCSR_FWDE_WIDTH 1
#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
#define I2S_RCSR_FRIE_MASK 0x100u
#define I2S_RCSR_FRIE_SHIFT 8
#define I2S_RCSR_FRIE_WIDTH 1
#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
#define I2S_RCSR_FWIE_MASK 0x200u
#define I2S_RCSR_FWIE_SHIFT 9
#define I2S_RCSR_FWIE_WIDTH 1
#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
#define I2S_RCSR_FEIE_MASK 0x400u
#define I2S_RCSR_FEIE_SHIFT 10
#define I2S_RCSR_FEIE_WIDTH 1
#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
#define I2S_RCSR_SEIE_MASK 0x800u
#define I2S_RCSR_SEIE_SHIFT 11
#define I2S_RCSR_SEIE_WIDTH 1
#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
#define I2S_RCSR_WSIE_MASK 0x1000u
#define I2S_RCSR_WSIE_SHIFT 12
#define I2S_RCSR_WSIE_WIDTH 1
#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
#define I2S_RCSR_FRF_MASK 0x10000u
#define I2S_RCSR_FRF_SHIFT 16
#define I2S_RCSR_FRF_WIDTH 1
#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
#define I2S_RCSR_FWF_MASK 0x20000u
#define I2S_RCSR_FWF_SHIFT 17
#define I2S_RCSR_FWF_WIDTH 1
#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
#define I2S_RCSR_FEF_MASK 0x40000u
#define I2S_RCSR_FEF_SHIFT 18
#define I2S_RCSR_FEF_WIDTH 1
#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
#define I2S_RCSR_SEF_MASK 0x80000u
#define I2S_RCSR_SEF_SHIFT 19
#define I2S_RCSR_SEF_WIDTH 1
#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
#define I2S_RCSR_WSF_MASK 0x100000u
#define I2S_RCSR_WSF_SHIFT 20
#define I2S_RCSR_WSF_WIDTH 1
#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
#define I2S_RCSR_SR_MASK 0x1000000u
#define I2S_RCSR_SR_SHIFT 24
#define I2S_RCSR_SR_WIDTH 1
#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
#define I2S_RCSR_FR_MASK 0x2000000u
#define I2S_RCSR_FR_SHIFT 25
#define I2S_RCSR_FR_WIDTH 1
#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
#define I2S_RCSR_BCE_MASK 0x10000000u
#define I2S_RCSR_BCE_SHIFT 28
#define I2S_RCSR_BCE_WIDTH 1
#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
#define I2S_RCSR_DBGE_MASK 0x20000000u
#define I2S_RCSR_DBGE_SHIFT 29
#define I2S_RCSR_DBGE_WIDTH 1
#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
#define I2S_RCSR_STOPE_MASK 0x40000000u
#define I2S_RCSR_STOPE_SHIFT 30
#define I2S_RCSR_STOPE_WIDTH 1
#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
#define I2S_RCSR_RE_MASK 0x80000000u
#define I2S_RCSR_RE_SHIFT 31
#define I2S_RCSR_RE_WIDTH 1
#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
/* RCR1 Bit Fields */
#define I2S_RCR1_RFW_MASK 0x3u
#define I2S_RCR1_RFW_SHIFT 0
#define I2S_RCR1_RFW_WIDTH 2
#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
/* RCR2 Bit Fields */
#define I2S_RCR2_DIV_MASK 0xFFu
#define I2S_RCR2_DIV_SHIFT 0
#define I2S_RCR2_DIV_WIDTH 8
#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
#define I2S_RCR2_BCD_MASK 0x1000000u
#define I2S_RCR2_BCD_SHIFT 24
#define I2S_RCR2_BCD_WIDTH 1
#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
#define I2S_RCR2_BCP_MASK 0x2000000u
#define I2S_RCR2_BCP_SHIFT 25
#define I2S_RCR2_BCP_WIDTH 1
#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
#define I2S_RCR2_MSEL_MASK 0xC000000u
#define I2S_RCR2_MSEL_SHIFT 26
#define I2S_RCR2_MSEL_WIDTH 2
#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
#define I2S_RCR2_BCI_MASK 0x10000000u
#define I2S_RCR2_BCI_SHIFT 28
#define I2S_RCR2_BCI_WIDTH 1
#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
#define I2S_RCR2_BCS_MASK 0x20000000u
#define I2S_RCR2_BCS_SHIFT 29
#define I2S_RCR2_BCS_WIDTH 1
#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
#define I2S_RCR2_SYNC_MASK 0xC0000000u
#define I2S_RCR2_SYNC_SHIFT 30
#define I2S_RCR2_SYNC_WIDTH 2
#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
/* RCR3 Bit Fields */
#define I2S_RCR3_WDFL_MASK 0xFu
#define I2S_RCR3_WDFL_SHIFT 0
#define I2S_RCR3_WDFL_WIDTH 4
#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
#define I2S_RCR3_RCE_MASK 0x10000u
#define I2S_RCR3_RCE_SHIFT 16
#define I2S_RCR3_RCE_WIDTH 1
#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
/* RCR4 Bit Fields */
#define I2S_RCR4_FSD_MASK 0x1u
#define I2S_RCR4_FSD_SHIFT 0
#define I2S_RCR4_FSD_WIDTH 1
#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
#define I2S_RCR4_FSP_MASK 0x2u
#define I2S_RCR4_FSP_SHIFT 1
#define I2S_RCR4_FSP_WIDTH 1
#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
#define I2S_RCR4_ONDEM_MASK 0x4u
#define I2S_RCR4_ONDEM_SHIFT 2
#define I2S_RCR4_ONDEM_WIDTH 1
#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_ONDEM_SHIFT))&I2S_RCR4_ONDEM_MASK)
#define I2S_RCR4_FSE_MASK 0x8u
#define I2S_RCR4_FSE_SHIFT 3
#define I2S_RCR4_FSE_WIDTH 1
#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
#define I2S_RCR4_MF_MASK 0x10u
#define I2S_RCR4_MF_SHIFT 4
#define I2S_RCR4_MF_WIDTH 1
#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
#define I2S_RCR4_SYWD_MASK 0x1F00u
#define I2S_RCR4_SYWD_SHIFT 8
#define I2S_RCR4_SYWD_WIDTH 5
#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
#define I2S_RCR4_FRSZ_MASK 0xF0000u
#define I2S_RCR4_FRSZ_SHIFT 16
#define I2S_RCR4_FRSZ_WIDTH 4
#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
#define I2S_RCR4_FPACK_MASK 0x3000000u
#define I2S_RCR4_FPACK_SHIFT 24
#define I2S_RCR4_FPACK_WIDTH 2
#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
#define I2S_RCR4_FCONT_MASK 0x10000000u
#define I2S_RCR4_FCONT_SHIFT 28
#define I2S_RCR4_FCONT_WIDTH 1
#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FCONT_SHIFT))&I2S_RCR4_FCONT_MASK)
/* RCR5 Bit Fields */
#define I2S_RCR5_FBT_MASK 0x1F00u
#define I2S_RCR5_FBT_SHIFT 8
#define I2S_RCR5_FBT_WIDTH 5
#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
#define I2S_RCR5_W0W_MASK 0x1F0000u
#define I2S_RCR5_W0W_SHIFT 16
#define I2S_RCR5_W0W_WIDTH 5
#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
#define I2S_RCR5_WNW_MASK 0x1F000000u
#define I2S_RCR5_WNW_SHIFT 24
#define I2S_RCR5_WNW_WIDTH 5
#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
/* RDR Bit Fields */
#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
#define I2S_RDR_RDR_SHIFT 0
#define I2S_RDR_RDR_WIDTH 32
#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
/* RFR Bit Fields */
#define I2S_RFR_RFP_MASK 0x7u
#define I2S_RFR_RFP_SHIFT 0
#define I2S_RFR_RFP_WIDTH 3
#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
#define I2S_RFR_WFP_MASK 0x70000u
#define I2S_RFR_WFP_SHIFT 16
#define I2S_RFR_WFP_WIDTH 3
#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
/* RMR Bit Fields */
#define I2S_RMR_RWM_MASK 0xFFFFu
#define I2S_RMR_RWM_SHIFT 0
#define I2S_RMR_RWM_WIDTH 16
#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
/*!
* @}
*/ /* end of group I2S_Register_Masks */
/* I2S - Peripheral instance base addresses */
/** Peripheral I2S0 base address */
#define I2S0_BASE (0x4004C000u)
/** Peripheral I2S0 base pointer */
#define I2S0 ((I2S_Type *)I2S0_BASE)
#define I2S0_BASE_PTR (I2S0)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { I2S0_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS { I2S0 }
/* ----------------------------------------------------------------------------
-- I2S - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
* @{
*/
/* I2S - Register instance definitions */
/* I2S0 */
#define I2S0_TCSR I2S_TCSR_REG(I2S0)
#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
#define I2S0_TMR I2S_TMR_REG(I2S0)
#define I2S0_RCSR I2S_RCSR_REG(I2S0)
#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
#define I2S0_RMR I2S_RMR_REG(I2S0)
/* I2S - Register array accessors */
#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
/*!
* @}
*/ /* end of group I2S_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- INTMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
* @{
*/
/** INTMUX - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x40 */
__IO uint32_t CHn_CSR; /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
__I uint32_t CHn_VEC; /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
uint8_t RESERVED_0[8];
__IO uint32_t CHn_IER_31_0; /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
uint8_t RESERVED_1[12];
__I uint32_t CHn_IPR_31_0; /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
uint8_t RESERVED_2[28];
} CHANNEL[4];
} INTMUX_Type, *INTMUX_MemMapPtr;
/* ----------------------------------------------------------------------------
-- INTMUX - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTMUX_Register_Accessor_Macros INTMUX - Register accessor macros
* @{
*/
/* INTMUX - Register accessors */
#define INTMUX_CHn_CSR_REG(base,index) ((base)->CHANNEL[index].CHn_CSR)
#define INTMUX_CHn_CSR_COUNT 4
#define INTMUX_CHn_VEC_REG(base,index) ((base)->CHANNEL[index].CHn_VEC)
#define INTMUX_CHn_VEC_COUNT 4
#define INTMUX_CHn_IER_31_0_REG(base,index) ((base)->CHANNEL[index].CHn_IER_31_0)
#define INTMUX_CHn_IER_31_0_COUNT 4
#define INTMUX_CHn_IPR_31_0_REG(base,index) ((base)->CHANNEL[index].CHn_IPR_31_0)
#define INTMUX_CHn_IPR_31_0_COUNT 4
/*!
* @}
*/ /* end of group INTMUX_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- INTMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTMUX_Register_Masks INTMUX Register Masks
* @{
*/
/* CHn_CSR Bit Fields */
#define INTMUX_CHn_CSR_RST_MASK 0x1u
#define INTMUX_CHn_CSR_RST_SHIFT 0
#define INTMUX_CHn_CSR_RST_WIDTH 1
#define INTMUX_CHn_CSR_RST(x) (((uint32_t)(((uint32_t)(x))<<INTMUX_CHn_CSR_RST_SHIFT))&INTMUX_CHn_CSR_RST_MASK)
#define INTMUX_CHn_CSR_AND_MASK 0x2u
#define INTMUX_CHn_CSR_AND_SHIFT 1
#define INTMUX_CHn_CSR_AND_WIDTH 1
#define INTMUX_CHn_CSR_AND(x) (((uint32_t)(((uint32_t)(x))<<INTMUX_CHn_CSR_AND_SHIFT))&INTMUX_CHn_CSR_AND_MASK)
#define INTMUX_CHn_CSR_IRQN_MASK 0x30u
#define INTMUX_CHn_CSR_IRQN_SHIFT 4
#define INTMUX_CHn_CSR_IRQN_WIDTH 2
#define INTMUX_CHn_CSR_IRQN(x) (((uint32_t)(((uint32_t)(x))<<INTMUX_CHn_CSR_IRQN_SHIFT))&INTMUX_CHn_CSR_IRQN_MASK)
#define INTMUX_CHn_CSR_CHIN_MASK 0xF00u
#define INTMUX_CHn_CSR_CHIN_SHIFT 8
#define INTMUX_CHn_CSR_CHIN_WIDTH 4
#define INTMUX_CHn_CSR_CHIN(x) (((uint32_t)(((uint32_t)(x))<<INTMUX_CHn_CSR_CHIN_SHIFT))&INTMUX_CHn_CSR_CHIN_MASK)
#define INTMUX_CHn_CSR_IRQP_MASK 0x80000000u
#define INTMUX_CHn_CSR_IRQP_SHIFT 31
#define INTMUX_CHn_CSR_IRQP_WIDTH 1
#define INTMUX_CHn_CSR_IRQP(x) (((uint32_t)(((uint32_t)(x))<<INTMUX_CHn_CSR_IRQP_SHIFT))&INTMUX_CHn_CSR_IRQP_MASK)
/* CHn_VEC Bit Fields */
#define INTMUX_CHn_VEC_VECN_MASK 0x3FFCu
#define INTMUX_CHn_VEC_VECN_SHIFT 2
#define INTMUX_CHn_VEC_VECN_WIDTH 12
#define INTMUX_CHn_VEC_VECN(x) (((uint32_t)(((uint32_t)(x))<<INTMUX_CHn_VEC_VECN_SHIFT))&INTMUX_CHn_VEC_VECN_MASK)
/* CHn_IER_31_0 Bit Fields */
#define INTMUX_CHn_IER_31_0_INTE_MASK 0xFFFFFFFFu
#define INTMUX_CHn_IER_31_0_INTE_SHIFT 0
#define INTMUX_CHn_IER_31_0_INTE_WIDTH 32
#define INTMUX_CHn_IER_31_0_INTE(x) (((uint32_t)(((uint32_t)(x))<<INTMUX_CHn_IER_31_0_INTE_SHIFT))&INTMUX_CHn_IER_31_0_INTE_MASK)
/* CHn_IPR_31_0 Bit Fields */
#define INTMUX_CHn_IPR_31_0_INTP_MASK 0xFFFFFFFFu
#define INTMUX_CHn_IPR_31_0_INTP_SHIFT 0
#define INTMUX_CHn_IPR_31_0_INTP_WIDTH 32
#define INTMUX_CHn_IPR_31_0_INTP(x) (((uint32_t)(((uint32_t)(x))<<INTMUX_CHn_IPR_31_0_INTP_SHIFT))&INTMUX_CHn_IPR_31_0_INTP_MASK)
/*!
* @}
*/ /* end of group INTMUX_Register_Masks */
/* INTMUX - Peripheral instance base addresses */
/** Peripheral INTMUX0 base address */
#define INTMUX0_BASE (0x40024000u)
/** Peripheral INTMUX0 base pointer */
#define INTMUX0 ((INTMUX_Type *)INTMUX0_BASE)
#define INTMUX0_BASE_PTR (INTMUX0)
/** Array initializer of INTMUX peripheral base addresses */
#define INTMUX_BASE_ADDRS { INTMUX0_BASE }
/** Array initializer of INTMUX peripheral base pointers */
#define INTMUX_BASE_PTRS { INTMUX0 }
/* ----------------------------------------------------------------------------
-- INTMUX - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTMUX_Register_Accessor_Macros INTMUX - Register accessor macros
* @{
*/
/* INTMUX - Register instance definitions */
/* INTMUX0 */
#define INTMUX0_CH0_CSR INTMUX_CHn_CSR_REG(INTMUX0,0)
#define INTMUX0_CH0_VEC INTMUX_CHn_VEC_REG(INTMUX0,0)
#define INTMUX0_CH0_IER_31_0 INTMUX_CHn_IER_31_0_REG(INTMUX0,0)
#define INTMUX0_CH0_IPR_31_0 INTMUX_CHn_IPR_31_0_REG(INTMUX0,0)
#define INTMUX0_CH1_CSR INTMUX_CHn_CSR_REG(INTMUX0,1)
#define INTMUX0_CH1_VEC INTMUX_CHn_VEC_REG(INTMUX0,1)
#define INTMUX0_CH1_IER_31_0 INTMUX_CHn_IER_31_0_REG(INTMUX0,1)
#define INTMUX0_CH1_IPR_31_0 INTMUX_CHn_IPR_31_0_REG(INTMUX0,1)
#define INTMUX0_CH2_CSR INTMUX_CHn_CSR_REG(INTMUX0,2)
#define INTMUX0_CH2_VEC INTMUX_CHn_VEC_REG(INTMUX0,2)
#define INTMUX0_CH2_IER_31_0 INTMUX_CHn_IER_31_0_REG(INTMUX0,2)
#define INTMUX0_CH2_IPR_31_0 INTMUX_CHn_IPR_31_0_REG(INTMUX0,2)
#define INTMUX0_CH3_CSR INTMUX_CHn_CSR_REG(INTMUX0,3)
#define INTMUX0_CH3_VEC INTMUX_CHn_VEC_REG(INTMUX0,3)
#define INTMUX0_CH3_IER_31_0 INTMUX_CHn_IER_31_0_REG(INTMUX0,3)
#define INTMUX0_CH3_IPR_31_0 INTMUX_CHn_IPR_31_0_REG(INTMUX0,3)
/* INTMUX - Register array accessors */
#define INTMUX0_CHn_CSR(index) INTMUX_CHn_CSR_REG(INTMUX0,index)
#define INTMUX0_CHn_VEC(index) INTMUX_CHn_VEC_REG(INTMUX0,index)
#define INTMUX0_CHn_IER_31_0(index) INTMUX_CHn_IER_31_0_REG(INTMUX0,index)
#define INTMUX0_CHn_IPR_31_0(index) INTMUX_CHn_IPR_31_0_REG(INTMUX0,index)
/*!
* @}
*/ /* end of group INTMUX_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group INTMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LLWU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
* @{
*/
/** LLWU - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x8 */
__IO uint32_t PE2; /**< LLWU Pin Enable 2 register, offset: 0xC */
uint8_t RESERVED_0[8];
__IO uint32_t ME; /**< LLWU Module Interrupt Enable register, offset: 0x18 */
__IO uint32_t DE; /**< LLWU Module DMA Enable register, offset: 0x1C */
__IO uint32_t PF; /**< LLWU Pin Flag register, offset: 0x20 */
uint8_t RESERVED_1[4];
__I uint32_t MF; /**< LLWU Module Interrupt Flag register, offset: 0x28 */
uint8_t RESERVED_2[4];
__IO uint32_t FILT; /**< LLWU Pin Filter register, offset: 0x30 */
} LLWU_Type, *LLWU_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LLWU - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
* @{
*/
/* LLWU - Register accessors */
#define LLWU_VERID_REG(base) ((base)->VERID)
#define LLWU_PARAM_REG(base) ((base)->PARAM)
#define LLWU_PE1_REG(base) ((base)->PE1)
#define LLWU_PE2_REG(base) ((base)->PE2)
#define LLWU_ME_REG(base) ((base)->ME)
#define LLWU_DE_REG(base) ((base)->DE)
#define LLWU_PF_REG(base) ((base)->PF)
#define LLWU_MF_REG(base) ((base)->MF)
#define LLWU_FILT_REG(base) ((base)->FILT)
/*!
* @}
*/ /* end of group LLWU_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Masks LLWU Register Masks
* @{
*/
/* VERID Bit Fields */
#define LLWU_VERID_FEATURE_MASK 0xFFFFu
#define LLWU_VERID_FEATURE_SHIFT 0
#define LLWU_VERID_FEATURE_WIDTH 16
#define LLWU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LLWU_VERID_FEATURE_SHIFT))&LLWU_VERID_FEATURE_MASK)
#define LLWU_VERID_MINOR_MASK 0xFF0000u
#define LLWU_VERID_MINOR_SHIFT 16
#define LLWU_VERID_MINOR_WIDTH 8
#define LLWU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LLWU_VERID_MINOR_SHIFT))&LLWU_VERID_MINOR_MASK)
#define LLWU_VERID_MAJOR_MASK 0xFF000000u
#define LLWU_VERID_MAJOR_SHIFT 24
#define LLWU_VERID_MAJOR_WIDTH 8
#define LLWU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LLWU_VERID_MAJOR_SHIFT))&LLWU_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define LLWU_PARAM_FILTERS_MASK 0xFFu
#define LLWU_PARAM_FILTERS_SHIFT 0
#define LLWU_PARAM_FILTERS_WIDTH 8
#define LLWU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PARAM_FILTERS_SHIFT))&LLWU_PARAM_FILTERS_MASK)
#define LLWU_PARAM_DMAS_MASK 0xFF00u
#define LLWU_PARAM_DMAS_SHIFT 8
#define LLWU_PARAM_DMAS_WIDTH 8
#define LLWU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PARAM_DMAS_SHIFT))&LLWU_PARAM_DMAS_MASK)
#define LLWU_PARAM_MODULES_MASK 0xFF0000u
#define LLWU_PARAM_MODULES_SHIFT 16
#define LLWU_PARAM_MODULES_WIDTH 8
#define LLWU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PARAM_MODULES_SHIFT))&LLWU_PARAM_MODULES_MASK)
#define LLWU_PARAM_PINS_MASK 0xFF000000u
#define LLWU_PARAM_PINS_SHIFT 24
#define LLWU_PARAM_PINS_WIDTH 8
#define LLWU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PARAM_PINS_SHIFT))&LLWU_PARAM_PINS_MASK)
/* PE1 Bit Fields */
#define LLWU_PE1_WUPE0_MASK 0x3u
#define LLWU_PE1_WUPE0_SHIFT 0
#define LLWU_PE1_WUPE0_WIDTH 2
#define LLWU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
#define LLWU_PE1_WUPE1_MASK 0xCu
#define LLWU_PE1_WUPE1_SHIFT 2
#define LLWU_PE1_WUPE1_WIDTH 2
#define LLWU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
#define LLWU_PE1_WUPE2_MASK 0x30u
#define LLWU_PE1_WUPE2_SHIFT 4
#define LLWU_PE1_WUPE2_WIDTH 2
#define LLWU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
#define LLWU_PE1_WUPE3_MASK 0xC0u
#define LLWU_PE1_WUPE3_SHIFT 6
#define LLWU_PE1_WUPE3_WIDTH 2
#define LLWU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
#define LLWU_PE1_WUPE4_MASK 0x300u
#define LLWU_PE1_WUPE4_SHIFT 8
#define LLWU_PE1_WUPE4_WIDTH 2
#define LLWU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE4_SHIFT))&LLWU_PE1_WUPE4_MASK)
#define LLWU_PE1_WUPE5_MASK 0xC00u
#define LLWU_PE1_WUPE5_SHIFT 10
#define LLWU_PE1_WUPE5_WIDTH 2
#define LLWU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE5_SHIFT))&LLWU_PE1_WUPE5_MASK)
#define LLWU_PE1_WUPE6_MASK 0x3000u
#define LLWU_PE1_WUPE6_SHIFT 12
#define LLWU_PE1_WUPE6_WIDTH 2
#define LLWU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE6_SHIFT))&LLWU_PE1_WUPE6_MASK)
#define LLWU_PE1_WUPE7_MASK 0xC000u
#define LLWU_PE1_WUPE7_SHIFT 14
#define LLWU_PE1_WUPE7_WIDTH 2
#define LLWU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE7_SHIFT))&LLWU_PE1_WUPE7_MASK)
#define LLWU_PE1_WUPE8_MASK 0x30000u
#define LLWU_PE1_WUPE8_SHIFT 16
#define LLWU_PE1_WUPE8_WIDTH 2
#define LLWU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE8_SHIFT))&LLWU_PE1_WUPE8_MASK)
#define LLWU_PE1_WUPE9_MASK 0xC0000u
#define LLWU_PE1_WUPE9_SHIFT 18
#define LLWU_PE1_WUPE9_WIDTH 2
#define LLWU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE9_SHIFT))&LLWU_PE1_WUPE9_MASK)
#define LLWU_PE1_WUPE10_MASK 0x300000u
#define LLWU_PE1_WUPE10_SHIFT 20
#define LLWU_PE1_WUPE10_WIDTH 2
#define LLWU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE10_SHIFT))&LLWU_PE1_WUPE10_MASK)
#define LLWU_PE1_WUPE11_MASK 0xC00000u
#define LLWU_PE1_WUPE11_SHIFT 22
#define LLWU_PE1_WUPE11_WIDTH 2
#define LLWU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE11_SHIFT))&LLWU_PE1_WUPE11_MASK)
#define LLWU_PE1_WUPE12_MASK 0x3000000u
#define LLWU_PE1_WUPE12_SHIFT 24
#define LLWU_PE1_WUPE12_WIDTH 2
#define LLWU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE12_SHIFT))&LLWU_PE1_WUPE12_MASK)
#define LLWU_PE1_WUPE13_MASK 0xC000000u
#define LLWU_PE1_WUPE13_SHIFT 26
#define LLWU_PE1_WUPE13_WIDTH 2
#define LLWU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE13_SHIFT))&LLWU_PE1_WUPE13_MASK)
#define LLWU_PE1_WUPE14_MASK 0x30000000u
#define LLWU_PE1_WUPE14_SHIFT 28
#define LLWU_PE1_WUPE14_WIDTH 2
#define LLWU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE14_SHIFT))&LLWU_PE1_WUPE14_MASK)
#define LLWU_PE1_WUPE15_MASK 0xC0000000u
#define LLWU_PE1_WUPE15_SHIFT 30
#define LLWU_PE1_WUPE15_WIDTH 2
#define LLWU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE1_WUPE15_SHIFT))&LLWU_PE1_WUPE15_MASK)
/* PE2 Bit Fields */
#define LLWU_PE2_WUPE16_MASK 0x3u
#define LLWU_PE2_WUPE16_SHIFT 0
#define LLWU_PE2_WUPE16_WIDTH 2
#define LLWU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE16_SHIFT))&LLWU_PE2_WUPE16_MASK)
#define LLWU_PE2_WUPE17_MASK 0xCu
#define LLWU_PE2_WUPE17_SHIFT 2
#define LLWU_PE2_WUPE17_WIDTH 2
#define LLWU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE17_SHIFT))&LLWU_PE2_WUPE17_MASK)
#define LLWU_PE2_WUPE18_MASK 0x30u
#define LLWU_PE2_WUPE18_SHIFT 4
#define LLWU_PE2_WUPE18_WIDTH 2
#define LLWU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE18_SHIFT))&LLWU_PE2_WUPE18_MASK)
#define LLWU_PE2_WUPE19_MASK 0xC0u
#define LLWU_PE2_WUPE19_SHIFT 6
#define LLWU_PE2_WUPE19_WIDTH 2
#define LLWU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE19_SHIFT))&LLWU_PE2_WUPE19_MASK)
#define LLWU_PE2_WUPE20_MASK 0x300u
#define LLWU_PE2_WUPE20_SHIFT 8
#define LLWU_PE2_WUPE20_WIDTH 2
#define LLWU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE20_SHIFT))&LLWU_PE2_WUPE20_MASK)
#define LLWU_PE2_WUPE21_MASK 0xC00u
#define LLWU_PE2_WUPE21_SHIFT 10
#define LLWU_PE2_WUPE21_WIDTH 2
#define LLWU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE21_SHIFT))&LLWU_PE2_WUPE21_MASK)
#define LLWU_PE2_WUPE22_MASK 0x3000u
#define LLWU_PE2_WUPE22_SHIFT 12
#define LLWU_PE2_WUPE22_WIDTH 2
#define LLWU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE22_SHIFT))&LLWU_PE2_WUPE22_MASK)
#define LLWU_PE2_WUPE23_MASK 0xC000u
#define LLWU_PE2_WUPE23_SHIFT 14
#define LLWU_PE2_WUPE23_WIDTH 2
#define LLWU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE23_SHIFT))&LLWU_PE2_WUPE23_MASK)
#define LLWU_PE2_WUPE24_MASK 0x30000u
#define LLWU_PE2_WUPE24_SHIFT 16
#define LLWU_PE2_WUPE24_WIDTH 2
#define LLWU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE24_SHIFT))&LLWU_PE2_WUPE24_MASK)
#define LLWU_PE2_WUPE25_MASK 0xC0000u
#define LLWU_PE2_WUPE25_SHIFT 18
#define LLWU_PE2_WUPE25_WIDTH 2
#define LLWU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE25_SHIFT))&LLWU_PE2_WUPE25_MASK)
#define LLWU_PE2_WUPE26_MASK 0x300000u
#define LLWU_PE2_WUPE26_SHIFT 20
#define LLWU_PE2_WUPE26_WIDTH 2
#define LLWU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE26_SHIFT))&LLWU_PE2_WUPE26_MASK)
#define LLWU_PE2_WUPE27_MASK 0xC00000u
#define LLWU_PE2_WUPE27_SHIFT 22
#define LLWU_PE2_WUPE27_WIDTH 2
#define LLWU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE27_SHIFT))&LLWU_PE2_WUPE27_MASK)
#define LLWU_PE2_WUPE28_MASK 0x3000000u
#define LLWU_PE2_WUPE28_SHIFT 24
#define LLWU_PE2_WUPE28_WIDTH 2
#define LLWU_PE2_WUPE28(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE28_SHIFT))&LLWU_PE2_WUPE28_MASK)
#define LLWU_PE2_WUPE29_MASK 0xC000000u
#define LLWU_PE2_WUPE29_SHIFT 26
#define LLWU_PE2_WUPE29_WIDTH 2
#define LLWU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE29_SHIFT))&LLWU_PE2_WUPE29_MASK)
#define LLWU_PE2_WUPE30_MASK 0x30000000u
#define LLWU_PE2_WUPE30_SHIFT 28
#define LLWU_PE2_WUPE30_WIDTH 2
#define LLWU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE30_SHIFT))&LLWU_PE2_WUPE30_MASK)
#define LLWU_PE2_WUPE31_MASK 0xC0000000u
#define LLWU_PE2_WUPE31_SHIFT 30
#define LLWU_PE2_WUPE31_WIDTH 2
#define LLWU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PE2_WUPE31_SHIFT))&LLWU_PE2_WUPE31_MASK)
/* ME Bit Fields */
#define LLWU_ME_WUME0_MASK 0x1u
#define LLWU_ME_WUME0_SHIFT 0
#define LLWU_ME_WUME0_WIDTH 1
#define LLWU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
#define LLWU_ME_WUME1_MASK 0x2u
#define LLWU_ME_WUME1_SHIFT 1
#define LLWU_ME_WUME1_WIDTH 1
#define LLWU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
#define LLWU_ME_WUME2_MASK 0x4u
#define LLWU_ME_WUME2_SHIFT 2
#define LLWU_ME_WUME2_WIDTH 1
#define LLWU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
#define LLWU_ME_WUME3_MASK 0x8u
#define LLWU_ME_WUME3_SHIFT 3
#define LLWU_ME_WUME3_WIDTH 1
#define LLWU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
#define LLWU_ME_WUME4_MASK 0x10u
#define LLWU_ME_WUME4_SHIFT 4
#define LLWU_ME_WUME4_WIDTH 1
#define LLWU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
#define LLWU_ME_WUME5_MASK 0x20u
#define LLWU_ME_WUME5_SHIFT 5
#define LLWU_ME_WUME5_WIDTH 1
#define LLWU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
#define LLWU_ME_WUME6_MASK 0x40u
#define LLWU_ME_WUME6_SHIFT 6
#define LLWU_ME_WUME6_WIDTH 1
#define LLWU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
#define LLWU_ME_WUME7_MASK 0x80u
#define LLWU_ME_WUME7_SHIFT 7
#define LLWU_ME_WUME7_WIDTH 1
#define LLWU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
/* DE Bit Fields */
#define LLWU_DE_WUDE0_MASK 0x1u
#define LLWU_DE_WUDE0_SHIFT 0
#define LLWU_DE_WUDE0_WIDTH 1
#define LLWU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x))<<LLWU_DE_WUDE0_SHIFT))&LLWU_DE_WUDE0_MASK)
#define LLWU_DE_WUDE1_MASK 0x2u
#define LLWU_DE_WUDE1_SHIFT 1
#define LLWU_DE_WUDE1_WIDTH 1
#define LLWU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x))<<LLWU_DE_WUDE1_SHIFT))&LLWU_DE_WUDE1_MASK)
#define LLWU_DE_WUDE2_MASK 0x4u
#define LLWU_DE_WUDE2_SHIFT 2
#define LLWU_DE_WUDE2_WIDTH 1
#define LLWU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x))<<LLWU_DE_WUDE2_SHIFT))&LLWU_DE_WUDE2_MASK)
#define LLWU_DE_WUDE3_MASK 0x8u
#define LLWU_DE_WUDE3_SHIFT 3
#define LLWU_DE_WUDE3_WIDTH 1
#define LLWU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x))<<LLWU_DE_WUDE3_SHIFT))&LLWU_DE_WUDE3_MASK)
#define LLWU_DE_WUDE4_MASK 0x10u
#define LLWU_DE_WUDE4_SHIFT 4
#define LLWU_DE_WUDE4_WIDTH 1
#define LLWU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x))<<LLWU_DE_WUDE4_SHIFT))&LLWU_DE_WUDE4_MASK)
#define LLWU_DE_WUDE5_MASK 0x20u
#define LLWU_DE_WUDE5_SHIFT 5
#define LLWU_DE_WUDE5_WIDTH 1
#define LLWU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x))<<LLWU_DE_WUDE5_SHIFT))&LLWU_DE_WUDE5_MASK)
#define LLWU_DE_WUDE6_MASK 0x40u
#define LLWU_DE_WUDE6_SHIFT 6
#define LLWU_DE_WUDE6_WIDTH 1
#define LLWU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x))<<LLWU_DE_WUDE6_SHIFT))&LLWU_DE_WUDE6_MASK)
#define LLWU_DE_WUDE7_MASK 0x80u
#define LLWU_DE_WUDE7_SHIFT 7
#define LLWU_DE_WUDE7_WIDTH 1
#define LLWU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x))<<LLWU_DE_WUDE7_SHIFT))&LLWU_DE_WUDE7_MASK)
/* PF Bit Fields */
#define LLWU_PF_WUF0_MASK 0x1u
#define LLWU_PF_WUF0_SHIFT 0
#define LLWU_PF_WUF0_WIDTH 1
#define LLWU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF0_SHIFT))&LLWU_PF_WUF0_MASK)
#define LLWU_PF_WUF1_MASK 0x2u
#define LLWU_PF_WUF1_SHIFT 1
#define LLWU_PF_WUF1_WIDTH 1
#define LLWU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF1_SHIFT))&LLWU_PF_WUF1_MASK)
#define LLWU_PF_WUF2_MASK 0x4u
#define LLWU_PF_WUF2_SHIFT 2
#define LLWU_PF_WUF2_WIDTH 1
#define LLWU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF2_SHIFT))&LLWU_PF_WUF2_MASK)
#define LLWU_PF_WUF3_MASK 0x8u
#define LLWU_PF_WUF3_SHIFT 3
#define LLWU_PF_WUF3_WIDTH 1
#define LLWU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF3_SHIFT))&LLWU_PF_WUF3_MASK)
#define LLWU_PF_WUF4_MASK 0x10u
#define LLWU_PF_WUF4_SHIFT 4
#define LLWU_PF_WUF4_WIDTH 1
#define LLWU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF4_SHIFT))&LLWU_PF_WUF4_MASK)
#define LLWU_PF_WUF5_MASK 0x20u
#define LLWU_PF_WUF5_SHIFT 5
#define LLWU_PF_WUF5_WIDTH 1
#define LLWU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF5_SHIFT))&LLWU_PF_WUF5_MASK)
#define LLWU_PF_WUF6_MASK 0x40u
#define LLWU_PF_WUF6_SHIFT 6
#define LLWU_PF_WUF6_WIDTH 1
#define LLWU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF6_SHIFT))&LLWU_PF_WUF6_MASK)
#define LLWU_PF_WUF7_MASK 0x80u
#define LLWU_PF_WUF7_SHIFT 7
#define LLWU_PF_WUF7_WIDTH 1
#define LLWU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF7_SHIFT))&LLWU_PF_WUF7_MASK)
#define LLWU_PF_WUF8_MASK 0x100u
#define LLWU_PF_WUF8_SHIFT 8
#define LLWU_PF_WUF8_WIDTH 1
#define LLWU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF8_SHIFT))&LLWU_PF_WUF8_MASK)
#define LLWU_PF_WUF9_MASK 0x200u
#define LLWU_PF_WUF9_SHIFT 9
#define LLWU_PF_WUF9_WIDTH 1
#define LLWU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF9_SHIFT))&LLWU_PF_WUF9_MASK)
#define LLWU_PF_WUF10_MASK 0x400u
#define LLWU_PF_WUF10_SHIFT 10
#define LLWU_PF_WUF10_WIDTH 1
#define LLWU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF10_SHIFT))&LLWU_PF_WUF10_MASK)
#define LLWU_PF_WUF11_MASK 0x800u
#define LLWU_PF_WUF11_SHIFT 11
#define LLWU_PF_WUF11_WIDTH 1
#define LLWU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF11_SHIFT))&LLWU_PF_WUF11_MASK)
#define LLWU_PF_WUF12_MASK 0x1000u
#define LLWU_PF_WUF12_SHIFT 12
#define LLWU_PF_WUF12_WIDTH 1
#define LLWU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF12_SHIFT))&LLWU_PF_WUF12_MASK)
#define LLWU_PF_WUF13_MASK 0x2000u
#define LLWU_PF_WUF13_SHIFT 13
#define LLWU_PF_WUF13_WIDTH 1
#define LLWU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF13_SHIFT))&LLWU_PF_WUF13_MASK)
#define LLWU_PF_WUF14_MASK 0x4000u
#define LLWU_PF_WUF14_SHIFT 14
#define LLWU_PF_WUF14_WIDTH 1
#define LLWU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF14_SHIFT))&LLWU_PF_WUF14_MASK)
#define LLWU_PF_WUF15_MASK 0x8000u
#define LLWU_PF_WUF15_SHIFT 15
#define LLWU_PF_WUF15_WIDTH 1
#define LLWU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF15_SHIFT))&LLWU_PF_WUF15_MASK)
#define LLWU_PF_WUF16_MASK 0x10000u
#define LLWU_PF_WUF16_SHIFT 16
#define LLWU_PF_WUF16_WIDTH 1
#define LLWU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF16_SHIFT))&LLWU_PF_WUF16_MASK)
#define LLWU_PF_WUF17_MASK 0x20000u
#define LLWU_PF_WUF17_SHIFT 17
#define LLWU_PF_WUF17_WIDTH 1
#define LLWU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF17_SHIFT))&LLWU_PF_WUF17_MASK)
#define LLWU_PF_WUF18_MASK 0x40000u
#define LLWU_PF_WUF18_SHIFT 18
#define LLWU_PF_WUF18_WIDTH 1
#define LLWU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF18_SHIFT))&LLWU_PF_WUF18_MASK)
#define LLWU_PF_WUF19_MASK 0x80000u
#define LLWU_PF_WUF19_SHIFT 19
#define LLWU_PF_WUF19_WIDTH 1
#define LLWU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF19_SHIFT))&LLWU_PF_WUF19_MASK)
#define LLWU_PF_WUF20_MASK 0x100000u
#define LLWU_PF_WUF20_SHIFT 20
#define LLWU_PF_WUF20_WIDTH 1
#define LLWU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF20_SHIFT))&LLWU_PF_WUF20_MASK)
#define LLWU_PF_WUF21_MASK 0x200000u
#define LLWU_PF_WUF21_SHIFT 21
#define LLWU_PF_WUF21_WIDTH 1
#define LLWU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF21_SHIFT))&LLWU_PF_WUF21_MASK)
#define LLWU_PF_WUF22_MASK 0x400000u
#define LLWU_PF_WUF22_SHIFT 22
#define LLWU_PF_WUF22_WIDTH 1
#define LLWU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF22_SHIFT))&LLWU_PF_WUF22_MASK)
#define LLWU_PF_WUF23_MASK 0x800000u
#define LLWU_PF_WUF23_SHIFT 23
#define LLWU_PF_WUF23_WIDTH 1
#define LLWU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF23_SHIFT))&LLWU_PF_WUF23_MASK)
#define LLWU_PF_WUF24_MASK 0x1000000u
#define LLWU_PF_WUF24_SHIFT 24
#define LLWU_PF_WUF24_WIDTH 1
#define LLWU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF24_SHIFT))&LLWU_PF_WUF24_MASK)
#define LLWU_PF_WUF25_MASK 0x2000000u
#define LLWU_PF_WUF25_SHIFT 25
#define LLWU_PF_WUF25_WIDTH 1
#define LLWU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF25_SHIFT))&LLWU_PF_WUF25_MASK)
#define LLWU_PF_WUF26_MASK 0x4000000u
#define LLWU_PF_WUF26_SHIFT 26
#define LLWU_PF_WUF26_WIDTH 1
#define LLWU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF26_SHIFT))&LLWU_PF_WUF26_MASK)
#define LLWU_PF_WUF27_MASK 0x8000000u
#define LLWU_PF_WUF27_SHIFT 27
#define LLWU_PF_WUF27_WIDTH 1
#define LLWU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF27_SHIFT))&LLWU_PF_WUF27_MASK)
#define LLWU_PF_WUF28_MASK 0x10000000u
#define LLWU_PF_WUF28_SHIFT 28
#define LLWU_PF_WUF28_WIDTH 1
#define LLWU_PF_WUF28(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF28_SHIFT))&LLWU_PF_WUF28_MASK)
#define LLWU_PF_WUF29_MASK 0x20000000u
#define LLWU_PF_WUF29_SHIFT 29
#define LLWU_PF_WUF29_WIDTH 1
#define LLWU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF29_SHIFT))&LLWU_PF_WUF29_MASK)
#define LLWU_PF_WUF30_MASK 0x40000000u
#define LLWU_PF_WUF30_SHIFT 30
#define LLWU_PF_WUF30_WIDTH 1
#define LLWU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF30_SHIFT))&LLWU_PF_WUF30_MASK)
#define LLWU_PF_WUF31_MASK 0x80000000u
#define LLWU_PF_WUF31_SHIFT 31
#define LLWU_PF_WUF31_WIDTH 1
#define LLWU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x))<<LLWU_PF_WUF31_SHIFT))&LLWU_PF_WUF31_MASK)
/* MF Bit Fields */
#define LLWU_MF_MWUF0_MASK 0x1u
#define LLWU_MF_MWUF0_SHIFT 0
#define LLWU_MF_MWUF0_WIDTH 1
#define LLWU_MF_MWUF0(x) (((uint32_t)(((uint32_t)(x))<<LLWU_MF_MWUF0_SHIFT))&LLWU_MF_MWUF0_MASK)
#define LLWU_MF_MWUF1_MASK 0x2u
#define LLWU_MF_MWUF1_SHIFT 1
#define LLWU_MF_MWUF1_WIDTH 1
#define LLWU_MF_MWUF1(x) (((uint32_t)(((uint32_t)(x))<<LLWU_MF_MWUF1_SHIFT))&LLWU_MF_MWUF1_MASK)
#define LLWU_MF_MWUF2_MASK 0x4u
#define LLWU_MF_MWUF2_SHIFT 2
#define LLWU_MF_MWUF2_WIDTH 1
#define LLWU_MF_MWUF2(x) (((uint32_t)(((uint32_t)(x))<<LLWU_MF_MWUF2_SHIFT))&LLWU_MF_MWUF2_MASK)
#define LLWU_MF_MWUF3_MASK 0x8u
#define LLWU_MF_MWUF3_SHIFT 3
#define LLWU_MF_MWUF3_WIDTH 1
#define LLWU_MF_MWUF3(x) (((uint32_t)(((uint32_t)(x))<<LLWU_MF_MWUF3_SHIFT))&LLWU_MF_MWUF3_MASK)
#define LLWU_MF_MWUF4_MASK 0x10u
#define LLWU_MF_MWUF4_SHIFT 4
#define LLWU_MF_MWUF4_WIDTH 1
#define LLWU_MF_MWUF4(x) (((uint32_t)(((uint32_t)(x))<<LLWU_MF_MWUF4_SHIFT))&LLWU_MF_MWUF4_MASK)
#define LLWU_MF_MWUF5_MASK 0x20u
#define LLWU_MF_MWUF5_SHIFT 5
#define LLWU_MF_MWUF5_WIDTH 1
#define LLWU_MF_MWUF5(x) (((uint32_t)(((uint32_t)(x))<<LLWU_MF_MWUF5_SHIFT))&LLWU_MF_MWUF5_MASK)
#define LLWU_MF_MWUF6_MASK 0x40u
#define LLWU_MF_MWUF6_SHIFT 6
#define LLWU_MF_MWUF6_WIDTH 1
#define LLWU_MF_MWUF6(x) (((uint32_t)(((uint32_t)(x))<<LLWU_MF_MWUF6_SHIFT))&LLWU_MF_MWUF6_MASK)
#define LLWU_MF_MWUF7_MASK 0x80u
#define LLWU_MF_MWUF7_SHIFT 7
#define LLWU_MF_MWUF7_WIDTH 1
#define LLWU_MF_MWUF7(x) (((uint32_t)(((uint32_t)(x))<<LLWU_MF_MWUF7_SHIFT))&LLWU_MF_MWUF7_MASK)
/* FILT Bit Fields */
#define LLWU_FILT_FILTSEL1_MASK 0x1Fu
#define LLWU_FILT_FILTSEL1_SHIFT 0
#define LLWU_FILT_FILTSEL1_WIDTH 5
#define LLWU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTSEL1_SHIFT))&LLWU_FILT_FILTSEL1_MASK)
#define LLWU_FILT_FILTE1_MASK 0x60u
#define LLWU_FILT_FILTE1_SHIFT 5
#define LLWU_FILT_FILTE1_WIDTH 2
#define LLWU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTE1_SHIFT))&LLWU_FILT_FILTE1_MASK)
#define LLWU_FILT_FILTF1_MASK 0x80u
#define LLWU_FILT_FILTF1_SHIFT 7
#define LLWU_FILT_FILTF1_WIDTH 1
#define LLWU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTF1_SHIFT))&LLWU_FILT_FILTF1_MASK)
#define LLWU_FILT_FILTSEL2_MASK 0x1F00u
#define LLWU_FILT_FILTSEL2_SHIFT 8
#define LLWU_FILT_FILTSEL2_WIDTH 5
#define LLWU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTSEL2_SHIFT))&LLWU_FILT_FILTSEL2_MASK)
#define LLWU_FILT_FILTE2_MASK 0x6000u
#define LLWU_FILT_FILTE2_SHIFT 13
#define LLWU_FILT_FILTE2_WIDTH 2
#define LLWU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTE2_SHIFT))&LLWU_FILT_FILTE2_MASK)
#define LLWU_FILT_FILTF2_MASK 0x8000u
#define LLWU_FILT_FILTF2_SHIFT 15
#define LLWU_FILT_FILTF2_WIDTH 1
#define LLWU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTF2_SHIFT))&LLWU_FILT_FILTF2_MASK)
#define LLWU_FILT_FILTSEL3_MASK 0x1F0000u
#define LLWU_FILT_FILTSEL3_SHIFT 16
#define LLWU_FILT_FILTSEL3_WIDTH 5
#define LLWU_FILT_FILTSEL3(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTSEL3_SHIFT))&LLWU_FILT_FILTSEL3_MASK)
#define LLWU_FILT_FILTE3_MASK 0x600000u
#define LLWU_FILT_FILTE3_SHIFT 21
#define LLWU_FILT_FILTE3_WIDTH 2
#define LLWU_FILT_FILTE3(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTE3_SHIFT))&LLWU_FILT_FILTE3_MASK)
#define LLWU_FILT_FILTF3_MASK 0x800000u
#define LLWU_FILT_FILTF3_SHIFT 23
#define LLWU_FILT_FILTF3_WIDTH 1
#define LLWU_FILT_FILTF3(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTF3_SHIFT))&LLWU_FILT_FILTF3_MASK)
#define LLWU_FILT_FILTSEL4_MASK 0x1F000000u
#define LLWU_FILT_FILTSEL4_SHIFT 24
#define LLWU_FILT_FILTSEL4_WIDTH 5
#define LLWU_FILT_FILTSEL4(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTSEL4_SHIFT))&LLWU_FILT_FILTSEL4_MASK)
#define LLWU_FILT_FILTE4_MASK 0x60000000u
#define LLWU_FILT_FILTE4_SHIFT 29
#define LLWU_FILT_FILTE4_WIDTH 2
#define LLWU_FILT_FILTE4(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTE4_SHIFT))&LLWU_FILT_FILTE4_MASK)
#define LLWU_FILT_FILTF4_MASK 0x80000000u
#define LLWU_FILT_FILTF4_SHIFT 31
#define LLWU_FILT_FILTF4_WIDTH 1
#define LLWU_FILT_FILTF4(x) (((uint32_t)(((uint32_t)(x))<<LLWU_FILT_FILTF4_SHIFT))&LLWU_FILT_FILTF4_MASK)
/*!
* @}
*/ /* end of group LLWU_Register_Masks */
/* LLWU - Peripheral instance base addresses */
/** Peripheral LLWU0 base address */
#define LLWU0_BASE (0x40061000u)
/** Peripheral LLWU0 base pointer */
#define LLWU0 ((LLWU_Type *)LLWU0_BASE)
#define LLWU0_BASE_PTR (LLWU0)
/** Array initializer of LLWU peripheral base addresses */
#define LLWU_BASE_ADDRS { LLWU0_BASE }
/** Array initializer of LLWU peripheral base pointers */
#define LLWU_BASE_PTRS { LLWU0 }
/* ----------------------------------------------------------------------------
-- LLWU - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
* @{
*/
/* LLWU - Register instance definitions */
/* LLWU0 */
#define LLWU0_VERID LLWU_VERID_REG(LLWU0)
#define LLWU0_PARAM LLWU_PARAM_REG(LLWU0)
#define LLWU0_PE1 LLWU_PE1_REG(LLWU0)
#define LLWU0_PE2 LLWU_PE2_REG(LLWU0)
#define LLWU0_ME LLWU_ME_REG(LLWU0)
#define LLWU0_DE LLWU_DE_REG(LLWU0)
#define LLWU0_PF LLWU_PF_REG(LLWU0)
#define LLWU0_MF LLWU_MF_REG(LLWU0)
#define LLWU0_FILT LLWU_FILT_REG(LLWU0)
/*!
* @}
*/ /* end of group LLWU_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPI2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
* @{
*/
/** LPI2C - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */
__IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */
__IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */
__IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */
__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */
__IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */
__IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */
__IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */
uint8_t RESERVED_1[16];
__IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */
uint8_t RESERVED_2[4];
__IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */
uint8_t RESERVED_3[4];
__IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */
uint8_t RESERVED_4[4];
__IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */
__I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */
__O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */
uint8_t RESERVED_5[12];
__I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */
uint8_t RESERVED_6[156];
__IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */
__IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */
__IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */
__IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */
uint8_t RESERVED_7[4];
__IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */
__IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */
uint8_t RESERVED_8[20];
__IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */
uint8_t RESERVED_9[12];
__I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */
__IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */
uint8_t RESERVED_10[8];
__O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */
uint8_t RESERVED_11[12];
__I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */
} LPI2C_Type, *LPI2C_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPI2C - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Accessor_Macros LPI2C - Register accessor macros
* @{
*/
/* LPI2C - Register accessors */
#define LPI2C_VERID_REG(base) ((base)->VERID)
#define LPI2C_PARAM_REG(base) ((base)->PARAM)
#define LPI2C_MCR_REG(base) ((base)->MCR)
#define LPI2C_MSR_REG(base) ((base)->MSR)
#define LPI2C_MIER_REG(base) ((base)->MIER)
#define LPI2C_MDER_REG(base) ((base)->MDER)
#define LPI2C_MCFGR0_REG(base) ((base)->MCFGR0)
#define LPI2C_MCFGR1_REG(base) ((base)->MCFGR1)
#define LPI2C_MCFGR2_REG(base) ((base)->MCFGR2)
#define LPI2C_MCFGR3_REG(base) ((base)->MCFGR3)
#define LPI2C_MDMR_REG(base) ((base)->MDMR)
#define LPI2C_MCCR0_REG(base) ((base)->MCCR0)
#define LPI2C_MCCR1_REG(base) ((base)->MCCR1)
#define LPI2C_MFCR_REG(base) ((base)->MFCR)
#define LPI2C_MFSR_REG(base) ((base)->MFSR)
#define LPI2C_MTDR_REG(base) ((base)->MTDR)
#define LPI2C_MRDR_REG(base) ((base)->MRDR)
#define LPI2C_SCR_REG(base) ((base)->SCR)
#define LPI2C_SSR_REG(base) ((base)->SSR)
#define LPI2C_SIER_REG(base) ((base)->SIER)
#define LPI2C_SDER_REG(base) ((base)->SDER)
#define LPI2C_SCFGR1_REG(base) ((base)->SCFGR1)
#define LPI2C_SCFGR2_REG(base) ((base)->SCFGR2)
#define LPI2C_SAMR_REG(base) ((base)->SAMR)
#define LPI2C_SASR_REG(base) ((base)->SASR)
#define LPI2C_STAR_REG(base) ((base)->STAR)
#define LPI2C_STDR_REG(base) ((base)->STDR)
#define LPI2C_SRDR_REG(base) ((base)->SRDR)
/*!
* @}
*/ /* end of group LPI2C_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPI2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Masks LPI2C Register Masks
* @{
*/
/* VERID Bit Fields */
#define LPI2C_VERID_FEATURE_MASK 0xFFFFu
#define LPI2C_VERID_FEATURE_SHIFT 0
#define LPI2C_VERID_FEATURE_WIDTH 16
#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_FEATURE_SHIFT))&LPI2C_VERID_FEATURE_MASK)
#define LPI2C_VERID_MINOR_MASK 0xFF0000u
#define LPI2C_VERID_MINOR_SHIFT 16
#define LPI2C_VERID_MINOR_WIDTH 8
#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MINOR_SHIFT))&LPI2C_VERID_MINOR_MASK)
#define LPI2C_VERID_MAJOR_MASK 0xFF000000u
#define LPI2C_VERID_MAJOR_SHIFT 24
#define LPI2C_VERID_MAJOR_WIDTH 8
#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MAJOR_SHIFT))&LPI2C_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define LPI2C_PARAM_MTXFIFO_MASK 0xFu
#define LPI2C_PARAM_MTXFIFO_SHIFT 0
#define LPI2C_PARAM_MTXFIFO_WIDTH 4
#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MTXFIFO_SHIFT))&LPI2C_PARAM_MTXFIFO_MASK)
#define LPI2C_PARAM_MRXFIFO_MASK 0xF00u
#define LPI2C_PARAM_MRXFIFO_SHIFT 8
#define LPI2C_PARAM_MRXFIFO_WIDTH 4
#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MRXFIFO_SHIFT))&LPI2C_PARAM_MRXFIFO_MASK)
/* MCR Bit Fields */
#define LPI2C_MCR_MEN_MASK 0x1u
#define LPI2C_MCR_MEN_SHIFT 0
#define LPI2C_MCR_MEN_WIDTH 1
#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_MEN_SHIFT))&LPI2C_MCR_MEN_MASK)
#define LPI2C_MCR_RST_MASK 0x2u
#define LPI2C_MCR_RST_SHIFT 1
#define LPI2C_MCR_RST_WIDTH 1
#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RST_SHIFT))&LPI2C_MCR_RST_MASK)
#define LPI2C_MCR_DOZEN_MASK 0x4u
#define LPI2C_MCR_DOZEN_SHIFT 2
#define LPI2C_MCR_DOZEN_WIDTH 1
#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DOZEN_SHIFT))&LPI2C_MCR_DOZEN_MASK)
#define LPI2C_MCR_DBGEN_MASK 0x8u
#define LPI2C_MCR_DBGEN_SHIFT 3
#define LPI2C_MCR_DBGEN_WIDTH 1
#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DBGEN_SHIFT))&LPI2C_MCR_DBGEN_MASK)
#define LPI2C_MCR_RTF_MASK 0x100u
#define LPI2C_MCR_RTF_SHIFT 8
#define LPI2C_MCR_RTF_WIDTH 1
#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RTF_SHIFT))&LPI2C_MCR_RTF_MASK)
#define LPI2C_MCR_RRF_MASK 0x200u
#define LPI2C_MCR_RRF_SHIFT 9
#define LPI2C_MCR_RRF_WIDTH 1
#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RRF_SHIFT))&LPI2C_MCR_RRF_MASK)
/* MSR Bit Fields */
#define LPI2C_MSR_TDF_MASK 0x1u
#define LPI2C_MSR_TDF_SHIFT 0
#define LPI2C_MSR_TDF_WIDTH 1
#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_TDF_SHIFT))&LPI2C_MSR_TDF_MASK)
#define LPI2C_MSR_RDF_MASK 0x2u
#define LPI2C_MSR_RDF_SHIFT 1
#define LPI2C_MSR_RDF_WIDTH 1
#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_RDF_SHIFT))&LPI2C_MSR_RDF_MASK)
#define LPI2C_MSR_EPF_MASK 0x100u
#define LPI2C_MSR_EPF_SHIFT 8
#define LPI2C_MSR_EPF_WIDTH 1
#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_EPF_SHIFT))&LPI2C_MSR_EPF_MASK)
#define LPI2C_MSR_SDF_MASK 0x200u
#define LPI2C_MSR_SDF_SHIFT 9
#define LPI2C_MSR_SDF_WIDTH 1
#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_SDF_SHIFT))&LPI2C_MSR_SDF_MASK)
#define LPI2C_MSR_NDF_MASK 0x400u
#define LPI2C_MSR_NDF_SHIFT 10
#define LPI2C_MSR_NDF_WIDTH 1
#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_NDF_SHIFT))&LPI2C_MSR_NDF_MASK)
#define LPI2C_MSR_ALF_MASK 0x800u
#define LPI2C_MSR_ALF_SHIFT 11
#define LPI2C_MSR_ALF_WIDTH 1
#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_ALF_SHIFT))&LPI2C_MSR_ALF_MASK)
#define LPI2C_MSR_FEF_MASK 0x1000u
#define LPI2C_MSR_FEF_SHIFT 12
#define LPI2C_MSR_FEF_WIDTH 1
#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_FEF_SHIFT))&LPI2C_MSR_FEF_MASK)
#define LPI2C_MSR_PLTF_MASK 0x2000u
#define LPI2C_MSR_PLTF_SHIFT 13
#define LPI2C_MSR_PLTF_WIDTH 1
#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_PLTF_SHIFT))&LPI2C_MSR_PLTF_MASK)
#define LPI2C_MSR_DMF_MASK 0x4000u
#define LPI2C_MSR_DMF_SHIFT 14
#define LPI2C_MSR_DMF_WIDTH 1
#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_DMF_SHIFT))&LPI2C_MSR_DMF_MASK)
#define LPI2C_MSR_MBF_MASK 0x1000000u
#define LPI2C_MSR_MBF_SHIFT 24
#define LPI2C_MSR_MBF_WIDTH 1
#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_MBF_SHIFT))&LPI2C_MSR_MBF_MASK)
#define LPI2C_MSR_BBF_MASK 0x2000000u
#define LPI2C_MSR_BBF_SHIFT 25
#define LPI2C_MSR_BBF_WIDTH 1
#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_BBF_SHIFT))&LPI2C_MSR_BBF_MASK)
/* MIER Bit Fields */
#define LPI2C_MIER_TDIE_MASK 0x1u
#define LPI2C_MIER_TDIE_SHIFT 0
#define LPI2C_MIER_TDIE_WIDTH 1
#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_TDIE_SHIFT))&LPI2C_MIER_TDIE_MASK)
#define LPI2C_MIER_RDIE_MASK 0x2u
#define LPI2C_MIER_RDIE_SHIFT 1
#define LPI2C_MIER_RDIE_WIDTH 1
#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_RDIE_SHIFT))&LPI2C_MIER_RDIE_MASK)
#define LPI2C_MIER_EPIE_MASK 0x100u
#define LPI2C_MIER_EPIE_SHIFT 8
#define LPI2C_MIER_EPIE_WIDTH 1
#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_EPIE_SHIFT))&LPI2C_MIER_EPIE_MASK)
#define LPI2C_MIER_SDIE_MASK 0x200u
#define LPI2C_MIER_SDIE_SHIFT 9
#define LPI2C_MIER_SDIE_WIDTH 1
#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_SDIE_SHIFT))&LPI2C_MIER_SDIE_MASK)
#define LPI2C_MIER_NDIE_MASK 0x400u
#define LPI2C_MIER_NDIE_SHIFT 10
#define LPI2C_MIER_NDIE_WIDTH 1
#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_NDIE_SHIFT))&LPI2C_MIER_NDIE_MASK)
#define LPI2C_MIER_ALIE_MASK 0x800u
#define LPI2C_MIER_ALIE_SHIFT 11
#define LPI2C_MIER_ALIE_WIDTH 1
#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_ALIE_SHIFT))&LPI2C_MIER_ALIE_MASK)
#define LPI2C_MIER_FEIE_MASK 0x1000u
#define LPI2C_MIER_FEIE_SHIFT 12
#define LPI2C_MIER_FEIE_WIDTH 1
#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_FEIE_SHIFT))&LPI2C_MIER_FEIE_MASK)
#define LPI2C_MIER_PLTIE_MASK 0x2000u
#define LPI2C_MIER_PLTIE_SHIFT 13
#define LPI2C_MIER_PLTIE_WIDTH 1
#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_PLTIE_SHIFT))&LPI2C_MIER_PLTIE_MASK)
#define LPI2C_MIER_DMIE_MASK 0x4000u
#define LPI2C_MIER_DMIE_SHIFT 14
#define LPI2C_MIER_DMIE_WIDTH 1
#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_DMIE_SHIFT))&LPI2C_MIER_DMIE_MASK)
/* MDER Bit Fields */
#define LPI2C_MDER_TDDE_MASK 0x1u
#define LPI2C_MDER_TDDE_SHIFT 0
#define LPI2C_MDER_TDDE_WIDTH 1
#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_TDDE_SHIFT))&LPI2C_MDER_TDDE_MASK)
#define LPI2C_MDER_RDDE_MASK 0x2u
#define LPI2C_MDER_RDDE_SHIFT 1
#define LPI2C_MDER_RDDE_WIDTH 1
#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_RDDE_SHIFT))&LPI2C_MDER_RDDE_MASK)
/* MCFGR0 Bit Fields */
#define LPI2C_MCFGR0_HREN_MASK 0x1u
#define LPI2C_MCFGR0_HREN_SHIFT 0
#define LPI2C_MCFGR0_HREN_WIDTH 1
#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HREN_SHIFT))&LPI2C_MCFGR0_HREN_MASK)
#define LPI2C_MCFGR0_HRPOL_MASK 0x2u
#define LPI2C_MCFGR0_HRPOL_SHIFT 1
#define LPI2C_MCFGR0_HRPOL_WIDTH 1
#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRPOL_SHIFT))&LPI2C_MCFGR0_HRPOL_MASK)
#define LPI2C_MCFGR0_HRSEL_MASK 0x4u
#define LPI2C_MCFGR0_HRSEL_SHIFT 2
#define LPI2C_MCFGR0_HRSEL_WIDTH 1
#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRSEL_SHIFT))&LPI2C_MCFGR0_HRSEL_MASK)
#define LPI2C_MCFGR0_CIRFIFO_MASK 0x100u
#define LPI2C_MCFGR0_CIRFIFO_SHIFT 8
#define LPI2C_MCFGR0_CIRFIFO_WIDTH 1
#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_CIRFIFO_SHIFT))&LPI2C_MCFGR0_CIRFIFO_MASK)
#define LPI2C_MCFGR0_RDMO_MASK 0x200u
#define LPI2C_MCFGR0_RDMO_SHIFT 9
#define LPI2C_MCFGR0_RDMO_WIDTH 1
#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_RDMO_SHIFT))&LPI2C_MCFGR0_RDMO_MASK)
/* MCFGR1 Bit Fields */
#define LPI2C_MCFGR1_PRESCALE_MASK 0x7u
#define LPI2C_MCFGR1_PRESCALE_SHIFT 0
#define LPI2C_MCFGR1_PRESCALE_WIDTH 3
#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PRESCALE_SHIFT))&LPI2C_MCFGR1_PRESCALE_MASK)
#define LPI2C_MCFGR1_AUTOSTOP_MASK 0x100u
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT 8
#define LPI2C_MCFGR1_AUTOSTOP_WIDTH 1
#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_AUTOSTOP_SHIFT))&LPI2C_MCFGR1_AUTOSTOP_MASK)
#define LPI2C_MCFGR1_IGNACK_MASK 0x200u
#define LPI2C_MCFGR1_IGNACK_SHIFT 9
#define LPI2C_MCFGR1_IGNACK_WIDTH 1
#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_IGNACK_SHIFT))&LPI2C_MCFGR1_IGNACK_MASK)
#define LPI2C_MCFGR1_TIMECFG_MASK 0x400u
#define LPI2C_MCFGR1_TIMECFG_SHIFT 10
#define LPI2C_MCFGR1_TIMECFG_WIDTH 1
#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_TIMECFG_SHIFT))&LPI2C_MCFGR1_TIMECFG_MASK)
#define LPI2C_MCFGR1_MATCFG_MASK 0x70000u
#define LPI2C_MCFGR1_MATCFG_SHIFT 16
#define LPI2C_MCFGR1_MATCFG_WIDTH 3
#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_MATCFG_SHIFT))&LPI2C_MCFGR1_MATCFG_MASK)
#define LPI2C_MCFGR1_PINCFG_MASK 0x7000000u
#define LPI2C_MCFGR1_PINCFG_SHIFT 24
#define LPI2C_MCFGR1_PINCFG_WIDTH 3
#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PINCFG_SHIFT))&LPI2C_MCFGR1_PINCFG_MASK)
/* MCFGR2 Bit Fields */
#define LPI2C_MCFGR2_BUSIDLE_MASK 0xFFFu
#define LPI2C_MCFGR2_BUSIDLE_SHIFT 0
#define LPI2C_MCFGR2_BUSIDLE_WIDTH 12
#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_BUSIDLE_SHIFT))&LPI2C_MCFGR2_BUSIDLE_MASK)
#define LPI2C_MCFGR2_FILTSCL_MASK 0xF0000u
#define LPI2C_MCFGR2_FILTSCL_SHIFT 16
#define LPI2C_MCFGR2_FILTSCL_WIDTH 4
#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSCL_SHIFT))&LPI2C_MCFGR2_FILTSCL_MASK)
#define LPI2C_MCFGR2_FILTSDA_MASK 0xF000000u
#define LPI2C_MCFGR2_FILTSDA_SHIFT 24
#define LPI2C_MCFGR2_FILTSDA_WIDTH 4
#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSDA_SHIFT))&LPI2C_MCFGR2_FILTSDA_MASK)
/* MCFGR3 Bit Fields */
#define LPI2C_MCFGR3_PINLOW_MASK 0xFFF00u
#define LPI2C_MCFGR3_PINLOW_SHIFT 8
#define LPI2C_MCFGR3_PINLOW_WIDTH 12
#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR3_PINLOW_SHIFT))&LPI2C_MCFGR3_PINLOW_MASK)
/* MDMR Bit Fields */
#define LPI2C_MDMR_MATCH0_MASK 0xFFu
#define LPI2C_MDMR_MATCH0_SHIFT 0
#define LPI2C_MDMR_MATCH0_WIDTH 8
#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH0_SHIFT))&LPI2C_MDMR_MATCH0_MASK)
#define LPI2C_MDMR_MATCH1_MASK 0xFF0000u
#define LPI2C_MDMR_MATCH1_SHIFT 16
#define LPI2C_MDMR_MATCH1_WIDTH 8
#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH1_SHIFT))&LPI2C_MDMR_MATCH1_MASK)
/* MCCR0 Bit Fields */
#define LPI2C_MCCR0_CLKLO_MASK 0x3Fu
#define LPI2C_MCCR0_CLKLO_SHIFT 0
#define LPI2C_MCCR0_CLKLO_WIDTH 6
#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKLO_SHIFT))&LPI2C_MCCR0_CLKLO_MASK)
#define LPI2C_MCCR0_CLKHI_MASK 0x3F00u
#define LPI2C_MCCR0_CLKHI_SHIFT 8
#define LPI2C_MCCR0_CLKHI_WIDTH 6
#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKHI_SHIFT))&LPI2C_MCCR0_CLKHI_MASK)
#define LPI2C_MCCR0_SETHOLD_MASK 0x3F0000u
#define LPI2C_MCCR0_SETHOLD_SHIFT 16
#define LPI2C_MCCR0_SETHOLD_WIDTH 6
#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_SETHOLD_SHIFT))&LPI2C_MCCR0_SETHOLD_MASK)
#define LPI2C_MCCR0_DATAVD_MASK 0x3F000000u
#define LPI2C_MCCR0_DATAVD_SHIFT 24
#define LPI2C_MCCR0_DATAVD_WIDTH 6
#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_DATAVD_SHIFT))&LPI2C_MCCR0_DATAVD_MASK)
/* MCCR1 Bit Fields */
#define LPI2C_MCCR1_CLKLO_MASK 0x3Fu
#define LPI2C_MCCR1_CLKLO_SHIFT 0
#define LPI2C_MCCR1_CLKLO_WIDTH 6
#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKLO_SHIFT))&LPI2C_MCCR1_CLKLO_MASK)
#define LPI2C_MCCR1_CLKHI_MASK 0x3F00u
#define LPI2C_MCCR1_CLKHI_SHIFT 8
#define LPI2C_MCCR1_CLKHI_WIDTH 6
#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKHI_SHIFT))&LPI2C_MCCR1_CLKHI_MASK)
#define LPI2C_MCCR1_SETHOLD_MASK 0x3F0000u
#define LPI2C_MCCR1_SETHOLD_SHIFT 16
#define LPI2C_MCCR1_SETHOLD_WIDTH 6
#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_SETHOLD_SHIFT))&LPI2C_MCCR1_SETHOLD_MASK)
#define LPI2C_MCCR1_DATAVD_MASK 0x3F000000u
#define LPI2C_MCCR1_DATAVD_SHIFT 24
#define LPI2C_MCCR1_DATAVD_WIDTH 6
#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_DATAVD_SHIFT))&LPI2C_MCCR1_DATAVD_MASK)
/* MFCR Bit Fields */
#define LPI2C_MFCR_TXWATER_MASK 0xFFu
#define LPI2C_MFCR_TXWATER_SHIFT 0
#define LPI2C_MFCR_TXWATER_WIDTH 8
#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_TXWATER_SHIFT))&LPI2C_MFCR_TXWATER_MASK)
#define LPI2C_MFCR_RXWATER_MASK 0xFF0000u
#define LPI2C_MFCR_RXWATER_SHIFT 16
#define LPI2C_MFCR_RXWATER_WIDTH 8
#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_RXWATER_SHIFT))&LPI2C_MFCR_RXWATER_MASK)
/* MFSR Bit Fields */
#define LPI2C_MFSR_TXCOUNT_MASK 0xFFu
#define LPI2C_MFSR_TXCOUNT_SHIFT 0
#define LPI2C_MFSR_TXCOUNT_WIDTH 8
#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_TXCOUNT_SHIFT))&LPI2C_MFSR_TXCOUNT_MASK)
#define LPI2C_MFSR_RXCOUNT_MASK 0xFF0000u
#define LPI2C_MFSR_RXCOUNT_SHIFT 16
#define LPI2C_MFSR_RXCOUNT_WIDTH 8
#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_RXCOUNT_SHIFT))&LPI2C_MFSR_RXCOUNT_MASK)
/* MTDR Bit Fields */
#define LPI2C_MTDR_DATA_MASK 0xFFu
#define LPI2C_MTDR_DATA_SHIFT 0
#define LPI2C_MTDR_DATA_WIDTH 8
#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_DATA_SHIFT))&LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_MASK 0x700u
#define LPI2C_MTDR_CMD_SHIFT 8
#define LPI2C_MTDR_CMD_WIDTH 3
#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_CMD_SHIFT))&LPI2C_MTDR_CMD_MASK)
/* MRDR Bit Fields */
#define LPI2C_MRDR_DATA_MASK 0xFFu
#define LPI2C_MRDR_DATA_SHIFT 0
#define LPI2C_MRDR_DATA_WIDTH 8
#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_DATA_SHIFT))&LPI2C_MRDR_DATA_MASK)
#define LPI2C_MRDR_RXEMPTY_MASK 0x4000u
#define LPI2C_MRDR_RXEMPTY_SHIFT 14
#define LPI2C_MRDR_RXEMPTY_WIDTH 1
#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_RXEMPTY_SHIFT))&LPI2C_MRDR_RXEMPTY_MASK)
/* SCR Bit Fields */
#define LPI2C_SCR_SEN_MASK 0x1u
#define LPI2C_SCR_SEN_SHIFT 0
#define LPI2C_SCR_SEN_WIDTH 1
#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_SEN_SHIFT))&LPI2C_SCR_SEN_MASK)
#define LPI2C_SCR_RST_MASK 0x2u
#define LPI2C_SCR_RST_SHIFT 1
#define LPI2C_SCR_RST_WIDTH 1
#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RST_SHIFT))&LPI2C_SCR_RST_MASK)
#define LPI2C_SCR_FILTEN_MASK 0x10u
#define LPI2C_SCR_FILTEN_SHIFT 4
#define LPI2C_SCR_FILTEN_WIDTH 1
#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTEN_SHIFT))&LPI2C_SCR_FILTEN_MASK)
#define LPI2C_SCR_FILTDZ_MASK 0x20u
#define LPI2C_SCR_FILTDZ_SHIFT 5
#define LPI2C_SCR_FILTDZ_WIDTH 1
#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTDZ_SHIFT))&LPI2C_SCR_FILTDZ_MASK)
#define LPI2C_SCR_RTF_MASK 0x100u
#define LPI2C_SCR_RTF_SHIFT 8
#define LPI2C_SCR_RTF_WIDTH 1
#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RTF_SHIFT))&LPI2C_SCR_RTF_MASK)
#define LPI2C_SCR_RRF_MASK 0x200u
#define LPI2C_SCR_RRF_SHIFT 9
#define LPI2C_SCR_RRF_WIDTH 1
#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RRF_SHIFT))&LPI2C_SCR_RRF_MASK)
/* SSR Bit Fields */
#define LPI2C_SSR_TDF_MASK 0x1u
#define LPI2C_SSR_TDF_SHIFT 0
#define LPI2C_SSR_TDF_WIDTH 1
#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TDF_SHIFT))&LPI2C_SSR_TDF_MASK)
#define LPI2C_SSR_RDF_MASK 0x2u
#define LPI2C_SSR_RDF_SHIFT 1
#define LPI2C_SSR_RDF_WIDTH 1
#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RDF_SHIFT))&LPI2C_SSR_RDF_MASK)
#define LPI2C_SSR_AVF_MASK 0x4u
#define LPI2C_SSR_AVF_SHIFT 2
#define LPI2C_SSR_AVF_WIDTH 1
#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AVF_SHIFT))&LPI2C_SSR_AVF_MASK)
#define LPI2C_SSR_TAF_MASK 0x8u
#define LPI2C_SSR_TAF_SHIFT 3
#define LPI2C_SSR_TAF_WIDTH 1
#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TAF_SHIFT))&LPI2C_SSR_TAF_MASK)
#define LPI2C_SSR_RSF_MASK 0x100u
#define LPI2C_SSR_RSF_SHIFT 8
#define LPI2C_SSR_RSF_WIDTH 1
#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RSF_SHIFT))&LPI2C_SSR_RSF_MASK)
#define LPI2C_SSR_SDF_MASK 0x200u
#define LPI2C_SSR_SDF_SHIFT 9
#define LPI2C_SSR_SDF_WIDTH 1
#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SDF_SHIFT))&LPI2C_SSR_SDF_MASK)
#define LPI2C_SSR_BEF_MASK 0x400u
#define LPI2C_SSR_BEF_SHIFT 10
#define LPI2C_SSR_BEF_WIDTH 1
#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BEF_SHIFT))&LPI2C_SSR_BEF_MASK)
#define LPI2C_SSR_FEF_MASK 0x800u
#define LPI2C_SSR_FEF_SHIFT 11
#define LPI2C_SSR_FEF_WIDTH 1
#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_FEF_SHIFT))&LPI2C_SSR_FEF_MASK)
#define LPI2C_SSR_AM0F_MASK 0x1000u
#define LPI2C_SSR_AM0F_SHIFT 12
#define LPI2C_SSR_AM0F_WIDTH 1
#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM0F_SHIFT))&LPI2C_SSR_AM0F_MASK)
#define LPI2C_SSR_AM1F_MASK 0x2000u
#define LPI2C_SSR_AM1F_SHIFT 13
#define LPI2C_SSR_AM1F_WIDTH 1
#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM1F_SHIFT))&LPI2C_SSR_AM1F_MASK)
#define LPI2C_SSR_GCF_MASK 0x4000u
#define LPI2C_SSR_GCF_SHIFT 14
#define LPI2C_SSR_GCF_WIDTH 1
#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_GCF_SHIFT))&LPI2C_SSR_GCF_MASK)
#define LPI2C_SSR_SARF_MASK 0x8000u
#define LPI2C_SSR_SARF_SHIFT 15
#define LPI2C_SSR_SARF_WIDTH 1
#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SARF_SHIFT))&LPI2C_SSR_SARF_MASK)
#define LPI2C_SSR_SBF_MASK 0x1000000u
#define LPI2C_SSR_SBF_SHIFT 24
#define LPI2C_SSR_SBF_WIDTH 1
#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SBF_SHIFT))&LPI2C_SSR_SBF_MASK)
#define LPI2C_SSR_BBF_MASK 0x2000000u
#define LPI2C_SSR_BBF_SHIFT 25
#define LPI2C_SSR_BBF_WIDTH 1
#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BBF_SHIFT))&LPI2C_SSR_BBF_MASK)
/* SIER Bit Fields */
#define LPI2C_SIER_TDIE_MASK 0x1u
#define LPI2C_SIER_TDIE_SHIFT 0
#define LPI2C_SIER_TDIE_WIDTH 1
#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TDIE_SHIFT))&LPI2C_SIER_TDIE_MASK)
#define LPI2C_SIER_RDIE_MASK 0x2u
#define LPI2C_SIER_RDIE_SHIFT 1
#define LPI2C_SIER_RDIE_WIDTH 1
#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RDIE_SHIFT))&LPI2C_SIER_RDIE_MASK)
#define LPI2C_SIER_AVIE_MASK 0x4u
#define LPI2C_SIER_AVIE_SHIFT 2
#define LPI2C_SIER_AVIE_WIDTH 1
#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AVIE_SHIFT))&LPI2C_SIER_AVIE_MASK)
#define LPI2C_SIER_TAIE_MASK 0x8u
#define LPI2C_SIER_TAIE_SHIFT 3
#define LPI2C_SIER_TAIE_WIDTH 1
#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TAIE_SHIFT))&LPI2C_SIER_TAIE_MASK)
#define LPI2C_SIER_RSIE_MASK 0x100u
#define LPI2C_SIER_RSIE_SHIFT 8
#define LPI2C_SIER_RSIE_WIDTH 1
#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RSIE_SHIFT))&LPI2C_SIER_RSIE_MASK)
#define LPI2C_SIER_SDIE_MASK 0x200u
#define LPI2C_SIER_SDIE_SHIFT 9
#define LPI2C_SIER_SDIE_WIDTH 1
#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SDIE_SHIFT))&LPI2C_SIER_SDIE_MASK)
#define LPI2C_SIER_BEIE_MASK 0x400u
#define LPI2C_SIER_BEIE_SHIFT 10
#define LPI2C_SIER_BEIE_WIDTH 1
#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_BEIE_SHIFT))&LPI2C_SIER_BEIE_MASK)
#define LPI2C_SIER_FEIE_MASK 0x800u
#define LPI2C_SIER_FEIE_SHIFT 11
#define LPI2C_SIER_FEIE_WIDTH 1
#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_FEIE_SHIFT))&LPI2C_SIER_FEIE_MASK)
#define LPI2C_SIER_AM0IE_MASK 0x1000u
#define LPI2C_SIER_AM0IE_SHIFT 12
#define LPI2C_SIER_AM0IE_WIDTH 1
#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM0IE_SHIFT))&LPI2C_SIER_AM0IE_MASK)
#define LPI2C_SIER_AM1F_MASK 0x2000u
#define LPI2C_SIER_AM1F_SHIFT 13
#define LPI2C_SIER_AM1F_WIDTH 1
#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM1F_SHIFT))&LPI2C_SIER_AM1F_MASK)
#define LPI2C_SIER_GCIE_MASK 0x4000u
#define LPI2C_SIER_GCIE_SHIFT 14
#define LPI2C_SIER_GCIE_WIDTH 1
#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_GCIE_SHIFT))&LPI2C_SIER_GCIE_MASK)
#define LPI2C_SIER_SARIE_MASK 0x8000u
#define LPI2C_SIER_SARIE_SHIFT 15
#define LPI2C_SIER_SARIE_WIDTH 1
#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SARIE_SHIFT))&LPI2C_SIER_SARIE_MASK)
/* SDER Bit Fields */
#define LPI2C_SDER_TDDE_MASK 0x1u
#define LPI2C_SDER_TDDE_SHIFT 0
#define LPI2C_SDER_TDDE_WIDTH 1
#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_TDDE_SHIFT))&LPI2C_SDER_TDDE_MASK)
#define LPI2C_SDER_RDDE_MASK 0x2u
#define LPI2C_SDER_RDDE_SHIFT 1
#define LPI2C_SDER_RDDE_WIDTH 1
#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_RDDE_SHIFT))&LPI2C_SDER_RDDE_MASK)
#define LPI2C_SDER_AVDE_MASK 0x4u
#define LPI2C_SDER_AVDE_SHIFT 2
#define LPI2C_SDER_AVDE_WIDTH 1
#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_AVDE_SHIFT))&LPI2C_SDER_AVDE_MASK)
/* SCFGR1 Bit Fields */
#define LPI2C_SCFGR1_ADRSTALL_MASK 0x1u
#define LPI2C_SCFGR1_ADRSTALL_SHIFT 0
#define LPI2C_SCFGR1_ADRSTALL_WIDTH 1
#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADRSTALL_SHIFT))&LPI2C_SCFGR1_ADRSTALL_MASK)
#define LPI2C_SCFGR1_RXSTALL_MASK 0x2u
#define LPI2C_SCFGR1_RXSTALL_SHIFT 1
#define LPI2C_SCFGR1_RXSTALL_WIDTH 1
#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXSTALL_SHIFT))&LPI2C_SCFGR1_RXSTALL_MASK)
#define LPI2C_SCFGR1_TXDSTALL_MASK 0x4u
#define LPI2C_SCFGR1_TXDSTALL_SHIFT 2
#define LPI2C_SCFGR1_TXDSTALL_WIDTH 1
#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXDSTALL_SHIFT))&LPI2C_SCFGR1_TXDSTALL_MASK)
#define LPI2C_SCFGR1_ACKSTALL_MASK 0x8u
#define LPI2C_SCFGR1_ACKSTALL_SHIFT 3
#define LPI2C_SCFGR1_ACKSTALL_WIDTH 1
#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ACKSTALL_SHIFT))&LPI2C_SCFGR1_ACKSTALL_MASK)
#define LPI2C_SCFGR1_GCEN_MASK 0x100u
#define LPI2C_SCFGR1_GCEN_SHIFT 8
#define LPI2C_SCFGR1_GCEN_WIDTH 1
#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_GCEN_SHIFT))&LPI2C_SCFGR1_GCEN_MASK)
#define LPI2C_SCFGR1_SAEN_MASK 0x200u
#define LPI2C_SCFGR1_SAEN_SHIFT 9
#define LPI2C_SCFGR1_SAEN_WIDTH 1
#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_SAEN_SHIFT))&LPI2C_SCFGR1_SAEN_MASK)
#define LPI2C_SCFGR1_TXCFG_MASK 0x400u
#define LPI2C_SCFGR1_TXCFG_SHIFT 10
#define LPI2C_SCFGR1_TXCFG_WIDTH 1
#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXCFG_SHIFT))&LPI2C_SCFGR1_TXCFG_MASK)
#define LPI2C_SCFGR1_RXCFG_MASK 0x800u
#define LPI2C_SCFGR1_RXCFG_SHIFT 11
#define LPI2C_SCFGR1_RXCFG_WIDTH 1
#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXCFG_SHIFT))&LPI2C_SCFGR1_RXCFG_MASK)
#define LPI2C_SCFGR1_IGNACK_MASK 0x1000u
#define LPI2C_SCFGR1_IGNACK_SHIFT 12
#define LPI2C_SCFGR1_IGNACK_WIDTH 1
#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_IGNACK_SHIFT))&LPI2C_SCFGR1_IGNACK_MASK)
#define LPI2C_SCFGR1_HSMEN_MASK 0x2000u
#define LPI2C_SCFGR1_HSMEN_SHIFT 13
#define LPI2C_SCFGR1_HSMEN_WIDTH 1
#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_HSMEN_SHIFT))&LPI2C_SCFGR1_HSMEN_MASK)
#define LPI2C_SCFGR1_ADDRCFG_MASK 0x70000u
#define LPI2C_SCFGR1_ADDRCFG_SHIFT 16
#define LPI2C_SCFGR1_ADDRCFG_WIDTH 3
#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADDRCFG_SHIFT))&LPI2C_SCFGR1_ADDRCFG_MASK)
/* SCFGR2 Bit Fields */
#define LPI2C_SCFGR2_CLKHOLD_MASK 0xFu
#define LPI2C_SCFGR2_CLKHOLD_SHIFT 0
#define LPI2C_SCFGR2_CLKHOLD_WIDTH 4
#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_CLKHOLD_SHIFT))&LPI2C_SCFGR2_CLKHOLD_MASK)
#define LPI2C_SCFGR2_DATAVD_MASK 0x3F00u
#define LPI2C_SCFGR2_DATAVD_SHIFT 8
#define LPI2C_SCFGR2_DATAVD_WIDTH 6
#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_DATAVD_SHIFT))&LPI2C_SCFGR2_DATAVD_MASK)
#define LPI2C_SCFGR2_FILTSCL_MASK 0xF0000u
#define LPI2C_SCFGR2_FILTSCL_SHIFT 16
#define LPI2C_SCFGR2_FILTSCL_WIDTH 4
#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSCL_SHIFT))&LPI2C_SCFGR2_FILTSCL_MASK)
#define LPI2C_SCFGR2_FILTSDA_MASK 0xF000000u
#define LPI2C_SCFGR2_FILTSDA_SHIFT 24
#define LPI2C_SCFGR2_FILTSDA_WIDTH 4
#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSDA_SHIFT))&LPI2C_SCFGR2_FILTSDA_MASK)
/* SAMR Bit Fields */
#define LPI2C_SAMR_ADDR0_MASK 0x7FEu
#define LPI2C_SAMR_ADDR0_SHIFT 1
#define LPI2C_SAMR_ADDR0_WIDTH 10
#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR0_SHIFT))&LPI2C_SAMR_ADDR0_MASK)
#define LPI2C_SAMR_ADDR1_MASK 0x7FE0000u
#define LPI2C_SAMR_ADDR1_SHIFT 17
#define LPI2C_SAMR_ADDR1_WIDTH 10
#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR1_SHIFT))&LPI2C_SAMR_ADDR1_MASK)
/* SASR Bit Fields */
#define LPI2C_SASR_RADDR_MASK 0x7FFu
#define LPI2C_SASR_RADDR_SHIFT 0
#define LPI2C_SASR_RADDR_WIDTH 11
#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_RADDR_SHIFT))&LPI2C_SASR_RADDR_MASK)
#define LPI2C_SASR_ANV_MASK 0x4000u
#define LPI2C_SASR_ANV_SHIFT 14
#define LPI2C_SASR_ANV_WIDTH 1
#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_ANV_SHIFT))&LPI2C_SASR_ANV_MASK)
/* STAR Bit Fields */
#define LPI2C_STAR_TXNACK_MASK 0x1u
#define LPI2C_STAR_TXNACK_SHIFT 0
#define LPI2C_STAR_TXNACK_WIDTH 1
#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STAR_TXNACK_SHIFT))&LPI2C_STAR_TXNACK_MASK)
/* STDR Bit Fields */
#define LPI2C_STDR_DATA_MASK 0xFFu
#define LPI2C_STDR_DATA_SHIFT 0
#define LPI2C_STDR_DATA_WIDTH 8
#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STDR_DATA_SHIFT))&LPI2C_STDR_DATA_MASK)
/* SRDR Bit Fields */
#define LPI2C_SRDR_DATA_MASK 0xFFu
#define LPI2C_SRDR_DATA_SHIFT 0
#define LPI2C_SRDR_DATA_WIDTH 8
#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_DATA_SHIFT))&LPI2C_SRDR_DATA_MASK)
#define LPI2C_SRDR_RXEMPTY_MASK 0x4000u
#define LPI2C_SRDR_RXEMPTY_SHIFT 14
#define LPI2C_SRDR_RXEMPTY_WIDTH 1
#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_RXEMPTY_SHIFT))&LPI2C_SRDR_RXEMPTY_MASK)
#define LPI2C_SRDR_SOF_MASK 0x8000u
#define LPI2C_SRDR_SOF_SHIFT 15
#define LPI2C_SRDR_SOF_WIDTH 1
#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_SOF_SHIFT))&LPI2C_SRDR_SOF_MASK)
/*!
* @}
*/ /* end of group LPI2C_Register_Masks */
/* LPI2C - Peripheral instance base addresses */
/** Peripheral LPI2C0 base address */
#define LPI2C0_BASE (0x400C0000u)
/** Peripheral LPI2C0 base pointer */
#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
#define LPI2C0_BASE_PTR (LPI2C0)
/** Peripheral LPI2C1 base address */
#define LPI2C1_BASE (0x400C1000u)
/** Peripheral LPI2C1 base pointer */
#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
#define LPI2C1_BASE_PTR (LPI2C1)
/** Peripheral LPI2C2 base address */
#define LPI2C2_BASE (0x40042000u)
/** Peripheral LPI2C2 base pointer */
#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
#define LPI2C2_BASE_PTR (LPI2C2)
/** Array initializer of LPI2C peripheral base addresses */
#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE }
/** Array initializer of LPI2C peripheral base pointers */
#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2 }
/* ----------------------------------------------------------------------------
-- LPI2C - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Accessor_Macros LPI2C - Register accessor macros
* @{
*/
/* LPI2C - Register instance definitions */
/* LPI2C0 */
#define LPI2C0_VERID LPI2C_VERID_REG(LPI2C0)
#define LPI2C0_PARAM LPI2C_PARAM_REG(LPI2C0)
#define LPI2C0_MCR LPI2C_MCR_REG(LPI2C0)
#define LPI2C0_MSR LPI2C_MSR_REG(LPI2C0)
#define LPI2C0_MIER LPI2C_MIER_REG(LPI2C0)
#define LPI2C0_MDER LPI2C_MDER_REG(LPI2C0)
#define LPI2C0_MCFGR0 LPI2C_MCFGR0_REG(LPI2C0)
#define LPI2C0_MCFGR1 LPI2C_MCFGR1_REG(LPI2C0)
#define LPI2C0_MCFGR2 LPI2C_MCFGR2_REG(LPI2C0)
#define LPI2C0_MCFGR3 LPI2C_MCFGR3_REG(LPI2C0)
#define LPI2C0_MDMR LPI2C_MDMR_REG(LPI2C0)
#define LPI2C0_MCCR0 LPI2C_MCCR0_REG(LPI2C0)
#define LPI2C0_MCCR1 LPI2C_MCCR1_REG(LPI2C0)
#define LPI2C0_MFCR LPI2C_MFCR_REG(LPI2C0)
#define LPI2C0_MFSR LPI2C_MFSR_REG(LPI2C0)
#define LPI2C0_MTDR LPI2C_MTDR_REG(LPI2C0)
#define LPI2C0_MRDR LPI2C_MRDR_REG(LPI2C0)
#define LPI2C0_SCR LPI2C_SCR_REG(LPI2C0)
#define LPI2C0_SSR LPI2C_SSR_REG(LPI2C0)
#define LPI2C0_SIER LPI2C_SIER_REG(LPI2C0)
#define LPI2C0_SDER LPI2C_SDER_REG(LPI2C0)
#define LPI2C0_SCFGR1 LPI2C_SCFGR1_REG(LPI2C0)
#define LPI2C0_SCFGR2 LPI2C_SCFGR2_REG(LPI2C0)
#define LPI2C0_SAMR LPI2C_SAMR_REG(LPI2C0)
#define LPI2C0_SASR LPI2C_SASR_REG(LPI2C0)
#define LPI2C0_STAR LPI2C_STAR_REG(LPI2C0)
#define LPI2C0_STDR LPI2C_STDR_REG(LPI2C0)
#define LPI2C0_SRDR LPI2C_SRDR_REG(LPI2C0)
/* LPI2C1 */
#define LPI2C1_VERID LPI2C_VERID_REG(LPI2C1)
#define LPI2C1_PARAM LPI2C_PARAM_REG(LPI2C1)
#define LPI2C1_MCR LPI2C_MCR_REG(LPI2C1)
#define LPI2C1_MSR LPI2C_MSR_REG(LPI2C1)
#define LPI2C1_MIER LPI2C_MIER_REG(LPI2C1)
#define LPI2C1_MDER LPI2C_MDER_REG(LPI2C1)
#define LPI2C1_MCFGR0 LPI2C_MCFGR0_REG(LPI2C1)
#define LPI2C1_MCFGR1 LPI2C_MCFGR1_REG(LPI2C1)
#define LPI2C1_MCFGR2 LPI2C_MCFGR2_REG(LPI2C1)
#define LPI2C1_MCFGR3 LPI2C_MCFGR3_REG(LPI2C1)
#define LPI2C1_MDMR LPI2C_MDMR_REG(LPI2C1)
#define LPI2C1_MCCR0 LPI2C_MCCR0_REG(LPI2C1)
#define LPI2C1_MCCR1 LPI2C_MCCR1_REG(LPI2C1)
#define LPI2C1_MFCR LPI2C_MFCR_REG(LPI2C1)
#define LPI2C1_MFSR LPI2C_MFSR_REG(LPI2C1)
#define LPI2C1_MTDR LPI2C_MTDR_REG(LPI2C1)
#define LPI2C1_MRDR LPI2C_MRDR_REG(LPI2C1)
#define LPI2C1_SCR LPI2C_SCR_REG(LPI2C1)
#define LPI2C1_SSR LPI2C_SSR_REG(LPI2C1)
#define LPI2C1_SIER LPI2C_SIER_REG(LPI2C1)
#define LPI2C1_SDER LPI2C_SDER_REG(LPI2C1)
#define LPI2C1_SCFGR1 LPI2C_SCFGR1_REG(LPI2C1)
#define LPI2C1_SCFGR2 LPI2C_SCFGR2_REG(LPI2C1)
#define LPI2C1_SAMR LPI2C_SAMR_REG(LPI2C1)
#define LPI2C1_SASR LPI2C_SASR_REG(LPI2C1)
#define LPI2C1_STAR LPI2C_STAR_REG(LPI2C1)
#define LPI2C1_STDR LPI2C_STDR_REG(LPI2C1)
#define LPI2C1_SRDR LPI2C_SRDR_REG(LPI2C1)
/* LPI2C2 */
#define LPI2C2_VERID LPI2C_VERID_REG(LPI2C2)
#define LPI2C2_PARAM LPI2C_PARAM_REG(LPI2C2)
#define LPI2C2_MCR LPI2C_MCR_REG(LPI2C2)
#define LPI2C2_MSR LPI2C_MSR_REG(LPI2C2)
#define LPI2C2_MIER LPI2C_MIER_REG(LPI2C2)
#define LPI2C2_MDER LPI2C_MDER_REG(LPI2C2)
#define LPI2C2_MCFGR0 LPI2C_MCFGR0_REG(LPI2C2)
#define LPI2C2_MCFGR1 LPI2C_MCFGR1_REG(LPI2C2)
#define LPI2C2_MCFGR2 LPI2C_MCFGR2_REG(LPI2C2)
#define LPI2C2_MCFGR3 LPI2C_MCFGR3_REG(LPI2C2)
#define LPI2C2_MDMR LPI2C_MDMR_REG(LPI2C2)
#define LPI2C2_MCCR0 LPI2C_MCCR0_REG(LPI2C2)
#define LPI2C2_MCCR1 LPI2C_MCCR1_REG(LPI2C2)
#define LPI2C2_MFCR LPI2C_MFCR_REG(LPI2C2)
#define LPI2C2_MFSR LPI2C_MFSR_REG(LPI2C2)
#define LPI2C2_MTDR LPI2C_MTDR_REG(LPI2C2)
#define LPI2C2_MRDR LPI2C_MRDR_REG(LPI2C2)
#define LPI2C2_SCR LPI2C_SCR_REG(LPI2C2)
#define LPI2C2_SSR LPI2C_SSR_REG(LPI2C2)
#define LPI2C2_SIER LPI2C_SIER_REG(LPI2C2)
#define LPI2C2_SDER LPI2C_SDER_REG(LPI2C2)
#define LPI2C2_SCFGR1 LPI2C_SCFGR1_REG(LPI2C2)
#define LPI2C2_SCFGR2 LPI2C_SCFGR2_REG(LPI2C2)
#define LPI2C2_SAMR LPI2C_SAMR_REG(LPI2C2)
#define LPI2C2_SASR LPI2C_SASR_REG(LPI2C2)
#define LPI2C2_STAR LPI2C_STAR_REG(LPI2C2)
#define LPI2C2_STDR LPI2C_STDR_REG(LPI2C2)
#define LPI2C2_SRDR LPI2C_SRDR_REG(LPI2C2)
/*!
* @}
*/ /* end of group LPI2C_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LPI2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPIT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
* @{
*/
/** LPIT - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */
__IO uint32_t MSR; /**< Module Status Register, offset: 0xC */
__IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */
__IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */
__IO uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */
uint8_t RESERVED_0[4];
struct { /* offset: 0x20, array step: 0x10 */
__IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */
__I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */
uint8_t RESERVED_0[4];
} CHANNEL[4];
} LPIT_Type, *LPIT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPIT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPIT_Register_Accessor_Macros LPIT - Register accessor macros
* @{
*/
/* LPIT - Register accessors */
#define LPIT_VERID_REG(base) ((base)->VERID)
#define LPIT_PARAM_REG(base) ((base)->PARAM)
#define LPIT_MCR_REG(base) ((base)->MCR)
#define LPIT_MSR_REG(base) ((base)->MSR)
#define LPIT_MIER_REG(base) ((base)->MIER)
#define LPIT_SETTEN_REG(base) ((base)->SETTEN)
#define LPIT_CLRTEN_REG(base) ((base)->CLRTEN)
#define LPIT_TVAL_REG(base,index) ((base)->CHANNEL[index].TVAL)
#define LPIT_TVAL_COUNT 4
#define LPIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
#define LPIT_CVAL_COUNT 4
#define LPIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
#define LPIT_TCTRL_COUNT 4
/*!
* @}
*/ /* end of group LPIT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPIT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPIT_Register_Masks LPIT Register Masks
* @{
*/
/* VERID Bit Fields */
#define LPIT_VERID_FEATURE_MASK 0xFFFFu
#define LPIT_VERID_FEATURE_SHIFT 0
#define LPIT_VERID_FEATURE_WIDTH 16
#define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_FEATURE_SHIFT))&LPIT_VERID_FEATURE_MASK)
#define LPIT_VERID_MINOR_MASK 0xFF0000u
#define LPIT_VERID_MINOR_SHIFT 16
#define LPIT_VERID_MINOR_WIDTH 8
#define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MINOR_SHIFT))&LPIT_VERID_MINOR_MASK)
#define LPIT_VERID_MAJOR_MASK 0xFF000000u
#define LPIT_VERID_MAJOR_SHIFT 24
#define LPIT_VERID_MAJOR_WIDTH 8
#define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MAJOR_SHIFT))&LPIT_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define LPIT_PARAM_CHANNEL_MASK 0xFFu
#define LPIT_PARAM_CHANNEL_SHIFT 0
#define LPIT_PARAM_CHANNEL_WIDTH 8
#define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_CHANNEL_SHIFT))&LPIT_PARAM_CHANNEL_MASK)
#define LPIT_PARAM_EXT_TRIG_MASK 0xFF00u
#define LPIT_PARAM_EXT_TRIG_SHIFT 8
#define LPIT_PARAM_EXT_TRIG_WIDTH 8
#define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_EXT_TRIG_SHIFT))&LPIT_PARAM_EXT_TRIG_MASK)
/* MCR Bit Fields */
#define LPIT_MCR_M_CEN_MASK 0x1u
#define LPIT_MCR_M_CEN_SHIFT 0
#define LPIT_MCR_M_CEN_WIDTH 1
#define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_M_CEN_SHIFT))&LPIT_MCR_M_CEN_MASK)
#define LPIT_MCR_SW_RST_MASK 0x2u
#define LPIT_MCR_SW_RST_SHIFT 1
#define LPIT_MCR_SW_RST_WIDTH 1
#define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_SW_RST_SHIFT))&LPIT_MCR_SW_RST_MASK)
#define LPIT_MCR_DOZE_EN_MASK 0x4u
#define LPIT_MCR_DOZE_EN_SHIFT 2
#define LPIT_MCR_DOZE_EN_WIDTH 1
#define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DOZE_EN_SHIFT))&LPIT_MCR_DOZE_EN_MASK)
#define LPIT_MCR_DBG_EN_MASK 0x8u
#define LPIT_MCR_DBG_EN_SHIFT 3
#define LPIT_MCR_DBG_EN_WIDTH 1
#define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DBG_EN_SHIFT))&LPIT_MCR_DBG_EN_MASK)
/* MSR Bit Fields */
#define LPIT_MSR_TIF0_MASK 0x1u
#define LPIT_MSR_TIF0_SHIFT 0
#define LPIT_MSR_TIF0_WIDTH 1
#define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF0_SHIFT))&LPIT_MSR_TIF0_MASK)
#define LPIT_MSR_TIF1_MASK 0x2u
#define LPIT_MSR_TIF1_SHIFT 1
#define LPIT_MSR_TIF1_WIDTH 1
#define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF1_SHIFT))&LPIT_MSR_TIF1_MASK)
#define LPIT_MSR_TIF2_MASK 0x4u
#define LPIT_MSR_TIF2_SHIFT 2
#define LPIT_MSR_TIF2_WIDTH 1
#define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF2_SHIFT))&LPIT_MSR_TIF2_MASK)
#define LPIT_MSR_TIF3_MASK 0x8u
#define LPIT_MSR_TIF3_SHIFT 3
#define LPIT_MSR_TIF3_WIDTH 1
#define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF3_SHIFT))&LPIT_MSR_TIF3_MASK)
/* MIER Bit Fields */
#define LPIT_MIER_TIE0_MASK 0x1u
#define LPIT_MIER_TIE0_SHIFT 0
#define LPIT_MIER_TIE0_WIDTH 1
#define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE0_SHIFT))&LPIT_MIER_TIE0_MASK)
#define LPIT_MIER_TIE1_MASK 0x2u
#define LPIT_MIER_TIE1_SHIFT 1
#define LPIT_MIER_TIE1_WIDTH 1
#define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE1_SHIFT))&LPIT_MIER_TIE1_MASK)
#define LPIT_MIER_TIE2_MASK 0x4u
#define LPIT_MIER_TIE2_SHIFT 2
#define LPIT_MIER_TIE2_WIDTH 1
#define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE2_SHIFT))&LPIT_MIER_TIE2_MASK)
#define LPIT_MIER_TIE3_MASK 0x8u
#define LPIT_MIER_TIE3_SHIFT 3
#define LPIT_MIER_TIE3_WIDTH 1
#define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE3_SHIFT))&LPIT_MIER_TIE3_MASK)
/* SETTEN Bit Fields */
#define LPIT_SETTEN_SET_T_EN_0_MASK 0x1u
#define LPIT_SETTEN_SET_T_EN_0_SHIFT 0
#define LPIT_SETTEN_SET_T_EN_0_WIDTH 1
#define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_0_SHIFT))&LPIT_SETTEN_SET_T_EN_0_MASK)
#define LPIT_SETTEN_SET_T_EN_1_MASK 0x2u
#define LPIT_SETTEN_SET_T_EN_1_SHIFT 1
#define LPIT_SETTEN_SET_T_EN_1_WIDTH 1
#define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_1_SHIFT))&LPIT_SETTEN_SET_T_EN_1_MASK)
#define LPIT_SETTEN_SET_T_EN_2_MASK 0x4u
#define LPIT_SETTEN_SET_T_EN_2_SHIFT 2
#define LPIT_SETTEN_SET_T_EN_2_WIDTH 1
#define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_2_SHIFT))&LPIT_SETTEN_SET_T_EN_2_MASK)
#define LPIT_SETTEN_SET_T_EN_3_MASK 0x8u
#define LPIT_SETTEN_SET_T_EN_3_SHIFT 3
#define LPIT_SETTEN_SET_T_EN_3_WIDTH 1
#define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_3_SHIFT))&LPIT_SETTEN_SET_T_EN_3_MASK)
/* CLRTEN Bit Fields */
#define LPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT 0
#define LPIT_CLRTEN_CLR_T_EN_0_WIDTH 1
#define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_0_SHIFT))&LPIT_CLRTEN_CLR_T_EN_0_MASK)
#define LPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT 1
#define LPIT_CLRTEN_CLR_T_EN_1_WIDTH 1
#define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_1_SHIFT))&LPIT_CLRTEN_CLR_T_EN_1_MASK)
#define LPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT 2
#define LPIT_CLRTEN_CLR_T_EN_2_WIDTH 1
#define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_2_SHIFT))&LPIT_CLRTEN_CLR_T_EN_2_MASK)
#define LPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT 3
#define LPIT_CLRTEN_CLR_T_EN_3_WIDTH 1
#define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_3_SHIFT))&LPIT_CLRTEN_CLR_T_EN_3_MASK)
/* TVAL Bit Fields */
#define LPIT_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
#define LPIT_TVAL_TMR_VAL_SHIFT 0
#define LPIT_TVAL_TMR_VAL_WIDTH 32
#define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TVAL_TMR_VAL_SHIFT))&LPIT_TVAL_TMR_VAL_MASK)
/* CVAL Bit Fields */
#define LPIT_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
#define LPIT_CVAL_TMR_CUR_VAL_SHIFT 0
#define LPIT_CVAL_TMR_CUR_VAL_WIDTH 32
#define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CVAL_TMR_CUR_VAL_SHIFT))&LPIT_CVAL_TMR_CUR_VAL_MASK)
/* TCTRL Bit Fields */
#define LPIT_TCTRL_T_EN_MASK 0x1u
#define LPIT_TCTRL_T_EN_SHIFT 0
#define LPIT_TCTRL_T_EN_WIDTH 1
#define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TCTRL_T_EN_SHIFT))&LPIT_TCTRL_T_EN_MASK)
#define LPIT_TCTRL_CHAIN_MASK 0x2u
#define LPIT_TCTRL_CHAIN_SHIFT 1
#define LPIT_TCTRL_CHAIN_WIDTH 1
#define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TCTRL_CHAIN_SHIFT))&LPIT_TCTRL_CHAIN_MASK)
#define LPIT_TCTRL_MODE_MASK 0xCu
#define LPIT_TCTRL_MODE_SHIFT 2
#define LPIT_TCTRL_MODE_WIDTH 2
#define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TCTRL_MODE_SHIFT))&LPIT_TCTRL_MODE_MASK)
#define LPIT_TCTRL_TSOT_MASK 0x10000u
#define LPIT_TCTRL_TSOT_SHIFT 16
#define LPIT_TCTRL_TSOT_WIDTH 1
#define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TCTRL_TSOT_SHIFT))&LPIT_TCTRL_TSOT_MASK)
#define LPIT_TCTRL_TSOI_MASK 0x20000u
#define LPIT_TCTRL_TSOI_SHIFT 17
#define LPIT_TCTRL_TSOI_WIDTH 1
#define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TCTRL_TSOI_SHIFT))&LPIT_TCTRL_TSOI_MASK)
#define LPIT_TCTRL_TROT_MASK 0x40000u
#define LPIT_TCTRL_TROT_SHIFT 18
#define LPIT_TCTRL_TROT_WIDTH 1
#define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TCTRL_TROT_SHIFT))&LPIT_TCTRL_TROT_MASK)
#define LPIT_TCTRL_TRG_SRC_MASK 0x800000u
#define LPIT_TCTRL_TRG_SRC_SHIFT 23
#define LPIT_TCTRL_TRG_SRC_WIDTH 1
#define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TCTRL_TRG_SRC_SHIFT))&LPIT_TCTRL_TRG_SRC_MASK)
#define LPIT_TCTRL_TRG_SEL_MASK 0xF000000u
#define LPIT_TCTRL_TRG_SEL_SHIFT 24
#define LPIT_TCTRL_TRG_SEL_WIDTH 4
#define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TCTRL_TRG_SEL_SHIFT))&LPIT_TCTRL_TRG_SEL_MASK)
/*!
* @}
*/ /* end of group LPIT_Register_Masks */
/* LPIT - Peripheral instance base addresses */
/** Peripheral LPIT0 base address */
#define LPIT0_BASE (0x40030000u)
/** Peripheral LPIT0 base pointer */
#define LPIT0 ((LPIT_Type *)LPIT0_BASE)
#define LPIT0_BASE_PTR (LPIT0)
/** Array initializer of LPIT peripheral base addresses */
#define LPIT_BASE_ADDRS { LPIT0_BASE }
/** Array initializer of LPIT peripheral base pointers */
#define LPIT_BASE_PTRS { LPIT0 }
/* ----------------------------------------------------------------------------
-- LPIT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPIT_Register_Accessor_Macros LPIT - Register accessor macros
* @{
*/
/* LPIT - Register instance definitions */
/* LPIT0 */
#define LPIT0_VERID LPIT_VERID_REG(LPIT0)
#define LPIT0_PARAM LPIT_PARAM_REG(LPIT0)
#define LPIT0_MCR LPIT_MCR_REG(LPIT0)
#define LPIT0_MSR LPIT_MSR_REG(LPIT0)
#define LPIT0_MIER LPIT_MIER_REG(LPIT0)
#define LPIT0_SETTEN LPIT_SETTEN_REG(LPIT0)
#define LPIT0_CLRTEN LPIT_CLRTEN_REG(LPIT0)
#define LPIT0_TVAL0 LPIT_TVAL_REG(LPIT0,0)
#define LPIT0_CVAL0 LPIT_CVAL_REG(LPIT0,0)
#define LPIT0_TCTRL0 LPIT_TCTRL_REG(LPIT0,0)
#define LPIT0_TVAL1 LPIT_TVAL_REG(LPIT0,1)
#define LPIT0_CVAL1 LPIT_CVAL_REG(LPIT0,1)
#define LPIT0_TCTRL1 LPIT_TCTRL_REG(LPIT0,1)
#define LPIT0_TVAL2 LPIT_TVAL_REG(LPIT0,2)
#define LPIT0_CVAL2 LPIT_CVAL_REG(LPIT0,2)
#define LPIT0_TCTRL2 LPIT_TCTRL_REG(LPIT0,2)
#define LPIT0_TVAL3 LPIT_TVAL_REG(LPIT0,3)
#define LPIT0_CVAL3 LPIT_CVAL_REG(LPIT0,3)
#define LPIT0_TCTRL3 LPIT_TCTRL_REG(LPIT0,3)
/* LPIT - Register array accessors */
#define LPIT0_TVAL(index) LPIT_TVAL_REG(LPIT0,index)
#define LPIT0_CVAL(index) LPIT_CVAL_REG(LPIT0,index)
#define LPIT0_TCTRL(index) LPIT_TCTRL_REG(LPIT0,index)
/*!
* @}
*/ /* end of group LPIT_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LPIT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
* @{
*/
/** LPSPI - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t CR; /**< Control Register, offset: 0x10 */
__IO uint32_t SR; /**< Status Register, offset: 0x14 */
__IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */
__IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */
__IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */
__IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */
uint8_t RESERVED_1[8];
__IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */
__IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */
uint8_t RESERVED_2[8];
__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */
uint8_t RESERVED_3[20];
__IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */
__I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */
__IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */
__O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */
uint8_t RESERVED_4[8];
__I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */
__I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */
} LPSPI_Type, *LPSPI_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPSPI - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Register_Accessor_Macros LPSPI - Register accessor macros
* @{
*/
/* LPSPI - Register accessors */
#define LPSPI_VERID_REG(base) ((base)->VERID)
#define LPSPI_PARAM_REG(base) ((base)->PARAM)
#define LPSPI_CR_REG(base) ((base)->CR)
#define LPSPI_SR_REG(base) ((base)->SR)
#define LPSPI_IER_REG(base) ((base)->IER)
#define LPSPI_DER_REG(base) ((base)->DER)
#define LPSPI_CFGR0_REG(base) ((base)->CFGR0)
#define LPSPI_CFGR1_REG(base) ((base)->CFGR1)
#define LPSPI_DMR0_REG(base) ((base)->DMR0)
#define LPSPI_DMR1_REG(base) ((base)->DMR1)
#define LPSPI_CCR_REG(base) ((base)->CCR)
#define LPSPI_FCR_REG(base) ((base)->FCR)
#define LPSPI_FSR_REG(base) ((base)->FSR)
#define LPSPI_TCR_REG(base) ((base)->TCR)
#define LPSPI_TDR_REG(base) ((base)->TDR)
#define LPSPI_RSR_REG(base) ((base)->RSR)
#define LPSPI_RDR_REG(base) ((base)->RDR)
/*!
* @}
*/ /* end of group LPSPI_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Register_Masks LPSPI Register Masks
* @{
*/
/* VERID Bit Fields */
#define LPSPI_VERID_FEATURE_MASK 0xFFFFu
#define LPSPI_VERID_FEATURE_SHIFT 0
#define LPSPI_VERID_FEATURE_WIDTH 16
#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_FEATURE_SHIFT))&LPSPI_VERID_FEATURE_MASK)
#define LPSPI_VERID_MINOR_MASK 0xFF0000u
#define LPSPI_VERID_MINOR_SHIFT 16
#define LPSPI_VERID_MINOR_WIDTH 8
#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MINOR_SHIFT))&LPSPI_VERID_MINOR_MASK)
#define LPSPI_VERID_MAJOR_MASK 0xFF000000u
#define LPSPI_VERID_MAJOR_SHIFT 24
#define LPSPI_VERID_MAJOR_WIDTH 8
#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MAJOR_SHIFT))&LPSPI_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define LPSPI_PARAM_TXFIFO_MASK 0xFFu
#define LPSPI_PARAM_TXFIFO_SHIFT 0
#define LPSPI_PARAM_TXFIFO_WIDTH 8
#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_TXFIFO_SHIFT))&LPSPI_PARAM_TXFIFO_MASK)
#define LPSPI_PARAM_RXFIFO_MASK 0xFF00u
#define LPSPI_PARAM_RXFIFO_SHIFT 8
#define LPSPI_PARAM_RXFIFO_WIDTH 8
#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_RXFIFO_SHIFT))&LPSPI_PARAM_RXFIFO_MASK)
/* CR Bit Fields */
#define LPSPI_CR_MEN_MASK 0x1u
#define LPSPI_CR_MEN_SHIFT 0
#define LPSPI_CR_MEN_WIDTH 1
#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_MEN_SHIFT))&LPSPI_CR_MEN_MASK)
#define LPSPI_CR_RST_MASK 0x2u
#define LPSPI_CR_RST_SHIFT 1
#define LPSPI_CR_RST_WIDTH 1
#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RST_SHIFT))&LPSPI_CR_RST_MASK)
#define LPSPI_CR_DOZEN_MASK 0x4u
#define LPSPI_CR_DOZEN_SHIFT 2
#define LPSPI_CR_DOZEN_WIDTH 1
#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DOZEN_SHIFT))&LPSPI_CR_DOZEN_MASK)
#define LPSPI_CR_DBGEN_MASK 0x8u
#define LPSPI_CR_DBGEN_SHIFT 3
#define LPSPI_CR_DBGEN_WIDTH 1
#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DBGEN_SHIFT))&LPSPI_CR_DBGEN_MASK)
#define LPSPI_CR_RTF_MASK 0x100u
#define LPSPI_CR_RTF_SHIFT 8
#define LPSPI_CR_RTF_WIDTH 1
#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RTF_SHIFT))&LPSPI_CR_RTF_MASK)
#define LPSPI_CR_RRF_MASK 0x200u
#define LPSPI_CR_RRF_SHIFT 9
#define LPSPI_CR_RRF_WIDTH 1
#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RRF_SHIFT))&LPSPI_CR_RRF_MASK)
/* SR Bit Fields */
#define LPSPI_SR_TDF_MASK 0x1u
#define LPSPI_SR_TDF_SHIFT 0
#define LPSPI_SR_TDF_WIDTH 1
#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TDF_SHIFT))&LPSPI_SR_TDF_MASK)
#define LPSPI_SR_RDF_MASK 0x2u
#define LPSPI_SR_RDF_SHIFT 1
#define LPSPI_SR_RDF_WIDTH 1
#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_RDF_SHIFT))&LPSPI_SR_RDF_MASK)
#define LPSPI_SR_WCF_MASK 0x100u
#define LPSPI_SR_WCF_SHIFT 8
#define LPSPI_SR_WCF_WIDTH 1
#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_WCF_SHIFT))&LPSPI_SR_WCF_MASK)
#define LPSPI_SR_FCF_MASK 0x200u
#define LPSPI_SR_FCF_SHIFT 9
#define LPSPI_SR_FCF_WIDTH 1
#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_FCF_SHIFT))&LPSPI_SR_FCF_MASK)
#define LPSPI_SR_TCF_MASK 0x400u
#define LPSPI_SR_TCF_SHIFT 10
#define LPSPI_SR_TCF_WIDTH 1
#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TCF_SHIFT))&LPSPI_SR_TCF_MASK)
#define LPSPI_SR_TEF_MASK 0x800u
#define LPSPI_SR_TEF_SHIFT 11
#define LPSPI_SR_TEF_WIDTH 1
#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TEF_SHIFT))&LPSPI_SR_TEF_MASK)
#define LPSPI_SR_REF_MASK 0x1000u
#define LPSPI_SR_REF_SHIFT 12
#define LPSPI_SR_REF_WIDTH 1
#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_REF_SHIFT))&LPSPI_SR_REF_MASK)
#define LPSPI_SR_DMF_MASK 0x2000u
#define LPSPI_SR_DMF_SHIFT 13
#define LPSPI_SR_DMF_WIDTH 1
#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_DMF_SHIFT))&LPSPI_SR_DMF_MASK)
#define LPSPI_SR_MBF_MASK 0x1000000u
#define LPSPI_SR_MBF_SHIFT 24
#define LPSPI_SR_MBF_WIDTH 1
#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_MBF_SHIFT))&LPSPI_SR_MBF_MASK)
/* IER Bit Fields */
#define LPSPI_IER_TDIE_MASK 0x1u
#define LPSPI_IER_TDIE_SHIFT 0
#define LPSPI_IER_TDIE_WIDTH 1
#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TDIE_SHIFT))&LPSPI_IER_TDIE_MASK)
#define LPSPI_IER_RDIE_MASK 0x2u
#define LPSPI_IER_RDIE_SHIFT 1
#define LPSPI_IER_RDIE_WIDTH 1
#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_RDIE_SHIFT))&LPSPI_IER_RDIE_MASK)
#define LPSPI_IER_WCIE_MASK 0x100u
#define LPSPI_IER_WCIE_SHIFT 8
#define LPSPI_IER_WCIE_WIDTH 1
#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_WCIE_SHIFT))&LPSPI_IER_WCIE_MASK)
#define LPSPI_IER_FCIE_MASK 0x200u
#define LPSPI_IER_FCIE_SHIFT 9
#define LPSPI_IER_FCIE_WIDTH 1
#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_FCIE_SHIFT))&LPSPI_IER_FCIE_MASK)
#define LPSPI_IER_TCIE_MASK 0x400u
#define LPSPI_IER_TCIE_SHIFT 10
#define LPSPI_IER_TCIE_WIDTH 1
#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TCIE_SHIFT))&LPSPI_IER_TCIE_MASK)
#define LPSPI_IER_TEIE_MASK 0x800u
#define LPSPI_IER_TEIE_SHIFT 11
#define LPSPI_IER_TEIE_WIDTH 1
#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TEIE_SHIFT))&LPSPI_IER_TEIE_MASK)
#define LPSPI_IER_REIE_MASK 0x1000u
#define LPSPI_IER_REIE_SHIFT 12
#define LPSPI_IER_REIE_WIDTH 1
#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_REIE_SHIFT))&LPSPI_IER_REIE_MASK)
#define LPSPI_IER_DMIE_MASK 0x2000u
#define LPSPI_IER_DMIE_SHIFT 13
#define LPSPI_IER_DMIE_WIDTH 1
#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_DMIE_SHIFT))&LPSPI_IER_DMIE_MASK)
/* DER Bit Fields */
#define LPSPI_DER_TDDE_MASK 0x1u
#define LPSPI_DER_TDDE_SHIFT 0
#define LPSPI_DER_TDDE_WIDTH 1
#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_TDDE_SHIFT))&LPSPI_DER_TDDE_MASK)
#define LPSPI_DER_RDDE_MASK 0x2u
#define LPSPI_DER_RDDE_SHIFT 1
#define LPSPI_DER_RDDE_WIDTH 1
#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_RDDE_SHIFT))&LPSPI_DER_RDDE_MASK)
/* CFGR0 Bit Fields */
#define LPSPI_CFGR0_HREN_MASK 0x1u
#define LPSPI_CFGR0_HREN_SHIFT 0
#define LPSPI_CFGR0_HREN_WIDTH 1
#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HREN_SHIFT))&LPSPI_CFGR0_HREN_MASK)
#define LPSPI_CFGR0_HRPOL_MASK 0x2u
#define LPSPI_CFGR0_HRPOL_SHIFT 1
#define LPSPI_CFGR0_HRPOL_WIDTH 1
#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRPOL_SHIFT))&LPSPI_CFGR0_HRPOL_MASK)
#define LPSPI_CFGR0_HRSEL_MASK 0x4u
#define LPSPI_CFGR0_HRSEL_SHIFT 2
#define LPSPI_CFGR0_HRSEL_WIDTH 1
#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRSEL_SHIFT))&LPSPI_CFGR0_HRSEL_MASK)
#define LPSPI_CFGR0_CIRFIFO_MASK 0x100u
#define LPSPI_CFGR0_CIRFIFO_SHIFT 8
#define LPSPI_CFGR0_CIRFIFO_WIDTH 1
#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_CIRFIFO_SHIFT))&LPSPI_CFGR0_CIRFIFO_MASK)
#define LPSPI_CFGR0_RDMO_MASK 0x200u
#define LPSPI_CFGR0_RDMO_SHIFT 9
#define LPSPI_CFGR0_RDMO_WIDTH 1
#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_RDMO_SHIFT))&LPSPI_CFGR0_RDMO_MASK)
/* CFGR1 Bit Fields */
#define LPSPI_CFGR1_MASTER_MASK 0x1u
#define LPSPI_CFGR1_MASTER_SHIFT 0
#define LPSPI_CFGR1_MASTER_WIDTH 1
#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MASTER_SHIFT))&LPSPI_CFGR1_MASTER_MASK)
#define LPSPI_CFGR1_SAMPLE_MASK 0x2u
#define LPSPI_CFGR1_SAMPLE_SHIFT 1
#define LPSPI_CFGR1_SAMPLE_WIDTH 1
#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_SAMPLE_SHIFT))&LPSPI_CFGR1_SAMPLE_MASK)
#define LPSPI_CFGR1_AUTOPCS_MASK 0x4u
#define LPSPI_CFGR1_AUTOPCS_SHIFT 2
#define LPSPI_CFGR1_AUTOPCS_WIDTH 1
#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_AUTOPCS_SHIFT))&LPSPI_CFGR1_AUTOPCS_MASK)
#define LPSPI_CFGR1_NOSTALL_MASK 0x8u
#define LPSPI_CFGR1_NOSTALL_SHIFT 3
#define LPSPI_CFGR1_NOSTALL_WIDTH 1
#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_NOSTALL_SHIFT))&LPSPI_CFGR1_NOSTALL_MASK)
#define LPSPI_CFGR1_PCSPOL_MASK 0xF00u
#define LPSPI_CFGR1_PCSPOL_SHIFT 8
#define LPSPI_CFGR1_PCSPOL_WIDTH 4
#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSPOL_SHIFT))&LPSPI_CFGR1_PCSPOL_MASK)
#define LPSPI_CFGR1_MATCFG_MASK 0x70000u
#define LPSPI_CFGR1_MATCFG_SHIFT 16
#define LPSPI_CFGR1_MATCFG_WIDTH 3
#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MATCFG_SHIFT))&LPSPI_CFGR1_MATCFG_MASK)
#define LPSPI_CFGR1_PINCFG_MASK 0x3000000u
#define LPSPI_CFGR1_PINCFG_SHIFT 24
#define LPSPI_CFGR1_PINCFG_WIDTH 2
#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PINCFG_SHIFT))&LPSPI_CFGR1_PINCFG_MASK)
#define LPSPI_CFGR1_OUTCFG_MASK 0x4000000u
#define LPSPI_CFGR1_OUTCFG_SHIFT 26
#define LPSPI_CFGR1_OUTCFG_WIDTH 1
#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_OUTCFG_SHIFT))&LPSPI_CFGR1_OUTCFG_MASK)
#define LPSPI_CFGR1_PCSCFG_MASK 0x8000000u
#define LPSPI_CFGR1_PCSCFG_SHIFT 27
#define LPSPI_CFGR1_PCSCFG_WIDTH 1
#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSCFG_SHIFT))&LPSPI_CFGR1_PCSCFG_MASK)
/* DMR0 Bit Fields */
#define LPSPI_DMR0_MATCH0_MASK 0xFFFFFFFFu
#define LPSPI_DMR0_MATCH0_SHIFT 0
#define LPSPI_DMR0_MATCH0_WIDTH 32
#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR0_MATCH0_SHIFT))&LPSPI_DMR0_MATCH0_MASK)
/* DMR1 Bit Fields */
#define LPSPI_DMR1_MATCH1_MASK 0xFFFFFFFFu
#define LPSPI_DMR1_MATCH1_SHIFT 0
#define LPSPI_DMR1_MATCH1_WIDTH 32
#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR1_MATCH1_SHIFT))&LPSPI_DMR1_MATCH1_MASK)
/* CCR Bit Fields */
#define LPSPI_CCR_SCKDIV_MASK 0xFFu
#define LPSPI_CCR_SCKDIV_SHIFT 0
#define LPSPI_CCR_SCKDIV_WIDTH 8
#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKDIV_SHIFT))&LPSPI_CCR_SCKDIV_MASK)
#define LPSPI_CCR_DBT_MASK 0xFF00u
#define LPSPI_CCR_DBT_SHIFT 8
#define LPSPI_CCR_DBT_WIDTH 8
#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_DBT_SHIFT))&LPSPI_CCR_DBT_MASK)
#define LPSPI_CCR_PCSSCK_MASK 0xFF0000u
#define LPSPI_CCR_PCSSCK_SHIFT 16
#define LPSPI_CCR_PCSSCK_WIDTH 8
#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_PCSSCK_SHIFT))&LPSPI_CCR_PCSSCK_MASK)
#define LPSPI_CCR_SCKPCS_MASK 0xFF000000u
#define LPSPI_CCR_SCKPCS_SHIFT 24
#define LPSPI_CCR_SCKPCS_WIDTH 8
#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKPCS_SHIFT))&LPSPI_CCR_SCKPCS_MASK)
/* FCR Bit Fields */
#define LPSPI_FCR_TXWATER_MASK 0xFFu
#define LPSPI_FCR_TXWATER_SHIFT 0
#define LPSPI_FCR_TXWATER_WIDTH 8
#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_TXWATER_SHIFT))&LPSPI_FCR_TXWATER_MASK)
#define LPSPI_FCR_RXWATER_MASK 0xFF0000u
#define LPSPI_FCR_RXWATER_SHIFT 16
#define LPSPI_FCR_RXWATER_WIDTH 8
#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_RXWATER_SHIFT))&LPSPI_FCR_RXWATER_MASK)
/* FSR Bit Fields */
#define LPSPI_FSR_TXCOUNT_MASK 0xFFu
#define LPSPI_FSR_TXCOUNT_SHIFT 0
#define LPSPI_FSR_TXCOUNT_WIDTH 8
#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_TXCOUNT_SHIFT))&LPSPI_FSR_TXCOUNT_MASK)
#define LPSPI_FSR_RXCOUNT_MASK 0xFF0000u
#define LPSPI_FSR_RXCOUNT_SHIFT 16
#define LPSPI_FSR_RXCOUNT_WIDTH 8
#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_RXCOUNT_SHIFT))&LPSPI_FSR_RXCOUNT_MASK)
/* TCR Bit Fields */
#define LPSPI_TCR_FRAMESZ_MASK 0xFFFu
#define LPSPI_TCR_FRAMESZ_SHIFT 0
#define LPSPI_TCR_FRAMESZ_WIDTH 12
#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_FRAMESZ_SHIFT))&LPSPI_TCR_FRAMESZ_MASK)
#define LPSPI_TCR_WIDTH_MASK 0x30000u
#define LPSPI_TCR_WIDTH_SHIFT 16
#define LPSPI_TCR_WIDTH_WIDTH 2
#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_WIDTH_SHIFT))&LPSPI_TCR_WIDTH_MASK)
#define LPSPI_TCR_TXMSK_MASK 0x40000u
#define LPSPI_TCR_TXMSK_SHIFT 18
#define LPSPI_TCR_TXMSK_WIDTH 1
#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_TXMSK_SHIFT))&LPSPI_TCR_TXMSK_MASK)
#define LPSPI_TCR_RXMSK_MASK 0x80000u
#define LPSPI_TCR_RXMSK_SHIFT 19
#define LPSPI_TCR_RXMSK_WIDTH 1
#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_RXMSK_SHIFT))&LPSPI_TCR_RXMSK_MASK)
#define LPSPI_TCR_CONTC_MASK 0x100000u
#define LPSPI_TCR_CONTC_SHIFT 20
#define LPSPI_TCR_CONTC_WIDTH 1
#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONTC_SHIFT))&LPSPI_TCR_CONTC_MASK)
#define LPSPI_TCR_CONT_MASK 0x200000u
#define LPSPI_TCR_CONT_SHIFT 21
#define LPSPI_TCR_CONT_WIDTH 1
#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONT_SHIFT))&LPSPI_TCR_CONT_MASK)
#define LPSPI_TCR_BYSW_MASK 0x400000u
#define LPSPI_TCR_BYSW_SHIFT 22
#define LPSPI_TCR_BYSW_WIDTH 1
#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_BYSW_SHIFT))&LPSPI_TCR_BYSW_MASK)
#define LPSPI_TCR_LSBF_MASK 0x800000u
#define LPSPI_TCR_LSBF_SHIFT 23
#define LPSPI_TCR_LSBF_WIDTH 1
#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_LSBF_SHIFT))&LPSPI_TCR_LSBF_MASK)
#define LPSPI_TCR_PCS_MASK 0x3000000u
#define LPSPI_TCR_PCS_SHIFT 24
#define LPSPI_TCR_PCS_WIDTH 2
#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PCS_SHIFT))&LPSPI_TCR_PCS_MASK)
#define LPSPI_TCR_PRESCALE_MASK 0x38000000u
#define LPSPI_TCR_PRESCALE_SHIFT 27
#define LPSPI_TCR_PRESCALE_WIDTH 3
#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PRESCALE_SHIFT))&LPSPI_TCR_PRESCALE_MASK)
#define LPSPI_TCR_CPHA_MASK 0x40000000u
#define LPSPI_TCR_CPHA_SHIFT 30
#define LPSPI_TCR_CPHA_WIDTH 1
#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPHA_SHIFT))&LPSPI_TCR_CPHA_MASK)
#define LPSPI_TCR_CPOL_MASK 0x80000000u
#define LPSPI_TCR_CPOL_SHIFT 31
#define LPSPI_TCR_CPOL_WIDTH 1
#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPOL_SHIFT))&LPSPI_TCR_CPOL_MASK)
/* TDR Bit Fields */
#define LPSPI_TDR_DATA_MASK 0xFFFFFFFFu
#define LPSPI_TDR_DATA_SHIFT 0
#define LPSPI_TDR_DATA_WIDTH 32
#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TDR_DATA_SHIFT))&LPSPI_TDR_DATA_MASK)
/* RSR Bit Fields */
#define LPSPI_RSR_SOF_MASK 0x1u
#define LPSPI_RSR_SOF_SHIFT 0
#define LPSPI_RSR_SOF_WIDTH 1
#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_SOF_SHIFT))&LPSPI_RSR_SOF_MASK)
#define LPSPI_RSR_RXEMPTY_MASK 0x2u
#define LPSPI_RSR_RXEMPTY_SHIFT 1
#define LPSPI_RSR_RXEMPTY_WIDTH 1
#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_RXEMPTY_SHIFT))&LPSPI_RSR_RXEMPTY_MASK)
/* RDR Bit Fields */
#define LPSPI_RDR_DATA_MASK 0xFFFFFFFFu
#define LPSPI_RDR_DATA_SHIFT 0
#define LPSPI_RDR_DATA_WIDTH 32
#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RDR_DATA_SHIFT))&LPSPI_RDR_DATA_MASK)
/*!
* @}
*/ /* end of group LPSPI_Register_Masks */
/* LPSPI - Peripheral instance base addresses */
/** Peripheral LPSPI0 base address */
#define LPSPI0_BASE (0x400BC000u)
/** Peripheral LPSPI0 base pointer */
#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
#define LPSPI0_BASE_PTR (LPSPI0)
/** Peripheral LPSPI1 base address */
#define LPSPI1_BASE (0x400BD000u)
/** Peripheral LPSPI1 base pointer */
#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
#define LPSPI1_BASE_PTR (LPSPI1)
/** Peripheral LPSPI2 base address */
#define LPSPI2_BASE (0x4003E000u)
/** Peripheral LPSPI2 base pointer */
#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
#define LPSPI2_BASE_PTR (LPSPI2)
/** Array initializer of LPSPI peripheral base addresses */
#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE }
/** Array initializer of LPSPI peripheral base pointers */
#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2 }
/* ----------------------------------------------------------------------------
-- LPSPI - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Register_Accessor_Macros LPSPI - Register accessor macros
* @{
*/
/* LPSPI - Register instance definitions */
/* LPSPI0 */
#define LPSPI0_VERID LPSPI_VERID_REG(LPSPI0)
#define LPSPI0_PARAM LPSPI_PARAM_REG(LPSPI0)
#define LPSPI0_CR LPSPI_CR_REG(LPSPI0)
#define LPSPI0_SR LPSPI_SR_REG(LPSPI0)
#define LPSPI0_IER LPSPI_IER_REG(LPSPI0)
#define LPSPI0_DER LPSPI_DER_REG(LPSPI0)
#define LPSPI0_CFGR0 LPSPI_CFGR0_REG(LPSPI0)
#define LPSPI0_CFGR1 LPSPI_CFGR1_REG(LPSPI0)
#define LPSPI0_DMR0 LPSPI_DMR0_REG(LPSPI0)
#define LPSPI0_DMR1 LPSPI_DMR1_REG(LPSPI0)
#define LPSPI0_CCR LPSPI_CCR_REG(LPSPI0)
#define LPSPI0_FCR LPSPI_FCR_REG(LPSPI0)
#define LPSPI0_FSR LPSPI_FSR_REG(LPSPI0)
#define LPSPI0_TCR LPSPI_TCR_REG(LPSPI0)
#define LPSPI0_TDR LPSPI_TDR_REG(LPSPI0)
#define LPSPI0_RSR LPSPI_RSR_REG(LPSPI0)
#define LPSPI0_RDR LPSPI_RDR_REG(LPSPI0)
/* LPSPI1 */
#define LPSPI1_VERID LPSPI_VERID_REG(LPSPI1)
#define LPSPI1_PARAM LPSPI_PARAM_REG(LPSPI1)
#define LPSPI1_CR LPSPI_CR_REG(LPSPI1)
#define LPSPI1_SR LPSPI_SR_REG(LPSPI1)
#define LPSPI1_IER LPSPI_IER_REG(LPSPI1)
#define LPSPI1_DER LPSPI_DER_REG(LPSPI1)
#define LPSPI1_CFGR0 LPSPI_CFGR0_REG(LPSPI1)
#define LPSPI1_CFGR1 LPSPI_CFGR1_REG(LPSPI1)
#define LPSPI1_DMR0 LPSPI_DMR0_REG(LPSPI1)
#define LPSPI1_DMR1 LPSPI_DMR1_REG(LPSPI1)
#define LPSPI1_CCR LPSPI_CCR_REG(LPSPI1)
#define LPSPI1_FCR LPSPI_FCR_REG(LPSPI1)
#define LPSPI1_FSR LPSPI_FSR_REG(LPSPI1)
#define LPSPI1_TCR LPSPI_TCR_REG(LPSPI1)
#define LPSPI1_TDR LPSPI_TDR_REG(LPSPI1)
#define LPSPI1_RSR LPSPI_RSR_REG(LPSPI1)
#define LPSPI1_RDR LPSPI_RDR_REG(LPSPI1)
/* LPSPI2 */
#define LPSPI2_VERID LPSPI_VERID_REG(LPSPI2)
#define LPSPI2_PARAM LPSPI_PARAM_REG(LPSPI2)
#define LPSPI2_CR LPSPI_CR_REG(LPSPI2)
#define LPSPI2_SR LPSPI_SR_REG(LPSPI2)
#define LPSPI2_IER LPSPI_IER_REG(LPSPI2)
#define LPSPI2_DER LPSPI_DER_REG(LPSPI2)
#define LPSPI2_CFGR0 LPSPI_CFGR0_REG(LPSPI2)
#define LPSPI2_CFGR1 LPSPI_CFGR1_REG(LPSPI2)
#define LPSPI2_DMR0 LPSPI_DMR0_REG(LPSPI2)
#define LPSPI2_DMR1 LPSPI_DMR1_REG(LPSPI2)
#define LPSPI2_CCR LPSPI_CCR_REG(LPSPI2)
#define LPSPI2_FCR LPSPI_FCR_REG(LPSPI2)
#define LPSPI2_FSR LPSPI_FSR_REG(LPSPI2)
#define LPSPI2_TCR LPSPI_TCR_REG(LPSPI2)
#define LPSPI2_TDR LPSPI_TDR_REG(LPSPI2)
#define LPSPI2_RSR LPSPI_RSR_REG(LPSPI2)
#define LPSPI2_RDR LPSPI_RDR_REG(LPSPI2)
/*!
* @}
*/ /* end of group LPSPI_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LPSPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPTMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
* @{
*/
/** LPTMR - Register Layout Typedef */
typedef struct {
__IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
__IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
} LPTMR_Type, *LPTMR_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPTMR - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
* @{
*/
/* LPTMR - Register accessors */
#define LPTMR_CSR_REG(base) ((base)->CSR)
#define LPTMR_PSR_REG(base) ((base)->PSR)
#define LPTMR_CMR_REG(base) ((base)->CMR)
#define LPTMR_CNR_REG(base) ((base)->CNR)
/*!
* @}
*/ /* end of group LPTMR_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
* @{
*/
/* CSR Bit Fields */
#define LPTMR_CSR_TEN_MASK 0x1u
#define LPTMR_CSR_TEN_SHIFT 0
#define LPTMR_CSR_TEN_WIDTH 1
#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
#define LPTMR_CSR_TMS_MASK 0x2u
#define LPTMR_CSR_TMS_SHIFT 1
#define LPTMR_CSR_TMS_WIDTH 1
#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
#define LPTMR_CSR_TFC_MASK 0x4u
#define LPTMR_CSR_TFC_SHIFT 2
#define LPTMR_CSR_TFC_WIDTH 1
#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
#define LPTMR_CSR_TPP_MASK 0x8u
#define LPTMR_CSR_TPP_SHIFT 3
#define LPTMR_CSR_TPP_WIDTH 1
#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
#define LPTMR_CSR_TPS_MASK 0x30u
#define LPTMR_CSR_TPS_SHIFT 4
#define LPTMR_CSR_TPS_WIDTH 2
#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
#define LPTMR_CSR_TIE_MASK 0x40u
#define LPTMR_CSR_TIE_SHIFT 6
#define LPTMR_CSR_TIE_WIDTH 1
#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
#define LPTMR_CSR_TCF_MASK 0x80u
#define LPTMR_CSR_TCF_SHIFT 7
#define LPTMR_CSR_TCF_WIDTH 1
#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
#define LPTMR_CSR_TDRE_MASK 0x100u
#define LPTMR_CSR_TDRE_SHIFT 8
#define LPTMR_CSR_TDRE_WIDTH 1
#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TDRE_SHIFT))&LPTMR_CSR_TDRE_MASK)
/* PSR Bit Fields */
#define LPTMR_PSR_PCS_MASK 0x3u
#define LPTMR_PSR_PCS_SHIFT 0
#define LPTMR_PSR_PCS_WIDTH 2
#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
#define LPTMR_PSR_PBYP_MASK 0x4u
#define LPTMR_PSR_PBYP_SHIFT 2
#define LPTMR_PSR_PBYP_WIDTH 1
#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
#define LPTMR_PSR_PRESCALE_MASK 0x78u
#define LPTMR_PSR_PRESCALE_SHIFT 3
#define LPTMR_PSR_PRESCALE_WIDTH 4
#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
/* CMR Bit Fields */
#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
#define LPTMR_CMR_COMPARE_SHIFT 0
#define LPTMR_CMR_COMPARE_WIDTH 16
#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
/* CNR Bit Fields */
#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
#define LPTMR_CNR_COUNTER_SHIFT 0
#define LPTMR_CNR_COUNTER_WIDTH 16
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
/*!
* @}
*/ /* end of group LPTMR_Register_Masks */
/* LPTMR - Peripheral instance base addresses */
/** Peripheral LPTMR0 base address */
#define LPTMR0_BASE (0x40034000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
#define LPTMR0_BASE_PTR (LPTMR0)
/** Peripheral LPTMR1 base address */
#define LPTMR1_BASE (0x400B5000u)
/** Peripheral LPTMR1 base pointer */
#define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE)
#define LPTMR1_BASE_PTR (LPTMR1)
/** Array initializer of LPTMR peripheral base addresses */
#define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE }
/** Array initializer of LPTMR peripheral base pointers */
#define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 }
/* ----------------------------------------------------------------------------
-- LPTMR - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
* @{
*/
/* LPTMR - Register instance definitions */
/* LPTMR0 */
#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
/* LPTMR1 */
#define LPTMR1_CSR LPTMR_CSR_REG(LPTMR1)
#define LPTMR1_PSR LPTMR_PSR_REG(LPTMR1)
#define LPTMR1_CMR LPTMR_CMR_REG(LPTMR1)
#define LPTMR1_CNR LPTMR_CNR_REG(LPTMR1)
/*!
* @}
*/ /* end of group LPTMR_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPUART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
* @{
*/
/** LPUART - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */
__IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */
__IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */
__IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */
__IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */
__IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */
__IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */
__IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */
} LPUART_Type, *LPUART_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPUART - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
* @{
*/
/* LPUART - Register accessors */
#define LPUART_VERID_REG(base) ((base)->VERID)
#define LPUART_PARAM_REG(base) ((base)->PARAM)
#define LPUART_GLOBAL_REG(base) ((base)->GLOBAL)
#define LPUART_PINCFG_REG(base) ((base)->PINCFG)
#define LPUART_BAUD_REG(base) ((base)->BAUD)
#define LPUART_STAT_REG(base) ((base)->STAT)
#define LPUART_CTRL_REG(base) ((base)->CTRL)
#define LPUART_DATA_REG(base) ((base)->DATA)
#define LPUART_MATCH_REG(base) ((base)->MATCH)
#define LPUART_MODIR_REG(base) ((base)->MODIR)
#define LPUART_FIFO_REG(base) ((base)->FIFO)
#define LPUART_WATER_REG(base) ((base)->WATER)
/*!
* @}
*/ /* end of group LPUART_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPUART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Masks LPUART Register Masks
* @{
*/
/* VERID Bit Fields */
#define LPUART_VERID_FEATURE_MASK 0xFFFFu
#define LPUART_VERID_FEATURE_SHIFT 0
#define LPUART_VERID_FEATURE_WIDTH 16
#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_FEATURE_SHIFT))&LPUART_VERID_FEATURE_MASK)
#define LPUART_VERID_MINOR_MASK 0xFF0000u
#define LPUART_VERID_MINOR_SHIFT 16
#define LPUART_VERID_MINOR_WIDTH 8
#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MINOR_SHIFT))&LPUART_VERID_MINOR_MASK)
#define LPUART_VERID_MAJOR_MASK 0xFF000000u
#define LPUART_VERID_MAJOR_SHIFT 24
#define LPUART_VERID_MAJOR_WIDTH 8
#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MAJOR_SHIFT))&LPUART_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define LPUART_PARAM_TXFIFO_MASK 0xFFu
#define LPUART_PARAM_TXFIFO_SHIFT 0
#define LPUART_PARAM_TXFIFO_WIDTH 8
#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_TXFIFO_SHIFT))&LPUART_PARAM_TXFIFO_MASK)
#define LPUART_PARAM_RXFIFO_MASK 0xFF00u
#define LPUART_PARAM_RXFIFO_SHIFT 8
#define LPUART_PARAM_RXFIFO_WIDTH 8
#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_RXFIFO_SHIFT))&LPUART_PARAM_RXFIFO_MASK)
/* GLOBAL Bit Fields */
#define LPUART_GLOBAL_RST_MASK 0x2u
#define LPUART_GLOBAL_RST_SHIFT 1
#define LPUART_GLOBAL_RST_WIDTH 1
#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x))<<LPUART_GLOBAL_RST_SHIFT))&LPUART_GLOBAL_RST_MASK)
/* PINCFG Bit Fields */
#define LPUART_PINCFG_TRGSEL_MASK 0x3u
#define LPUART_PINCFG_TRGSEL_SHIFT 0
#define LPUART_PINCFG_TRGSEL_WIDTH 2
#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PINCFG_TRGSEL_SHIFT))&LPUART_PINCFG_TRGSEL_MASK)
/* BAUD Bit Fields */
#define LPUART_BAUD_SBR_MASK 0x1FFFu
#define LPUART_BAUD_SBR_SHIFT 0
#define LPUART_BAUD_SBR_WIDTH 13
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
#define LPUART_BAUD_SBNS_MASK 0x2000u
#define LPUART_BAUD_SBNS_SHIFT 13
#define LPUART_BAUD_SBNS_WIDTH 1
#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
#define LPUART_BAUD_RXEDGIE_SHIFT 14
#define LPUART_BAUD_RXEDGIE_WIDTH 1
#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
#define LPUART_BAUD_LBKDIE_MASK 0x8000u
#define LPUART_BAUD_LBKDIE_SHIFT 15
#define LPUART_BAUD_LBKDIE_WIDTH 1
#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
#define LPUART_BAUD_RESYNCDIS_SHIFT 16
#define LPUART_BAUD_RESYNCDIS_WIDTH 1
#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
#define LPUART_BAUD_BOTHEDGE_SHIFT 17
#define LPUART_BAUD_BOTHEDGE_WIDTH 1
#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
#define LPUART_BAUD_MATCFG_MASK 0xC0000u
#define LPUART_BAUD_MATCFG_SHIFT 18
#define LPUART_BAUD_MATCFG_WIDTH 2
#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
#define LPUART_BAUD_RDMAE_MASK 0x200000u
#define LPUART_BAUD_RDMAE_SHIFT 21
#define LPUART_BAUD_RDMAE_WIDTH 1
#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
#define LPUART_BAUD_TDMAE_MASK 0x800000u
#define LPUART_BAUD_TDMAE_SHIFT 23
#define LPUART_BAUD_TDMAE_WIDTH 1
#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
#define LPUART_BAUD_OSR_MASK 0x1F000000u
#define LPUART_BAUD_OSR_SHIFT 24
#define LPUART_BAUD_OSR_WIDTH 5
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
#define LPUART_BAUD_M10_MASK 0x20000000u
#define LPUART_BAUD_M10_SHIFT 29
#define LPUART_BAUD_M10_WIDTH 1
#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
#define LPUART_BAUD_MAEN2_MASK 0x40000000u
#define LPUART_BAUD_MAEN2_SHIFT 30
#define LPUART_BAUD_MAEN2_WIDTH 1
#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
#define LPUART_BAUD_MAEN1_MASK 0x80000000u
#define LPUART_BAUD_MAEN1_SHIFT 31
#define LPUART_BAUD_MAEN1_WIDTH 1
#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
/* STAT Bit Fields */
#define LPUART_STAT_MA2F_MASK 0x4000u
#define LPUART_STAT_MA2F_SHIFT 14
#define LPUART_STAT_MA2F_WIDTH 1
#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
#define LPUART_STAT_MA1F_MASK 0x8000u
#define LPUART_STAT_MA1F_SHIFT 15
#define LPUART_STAT_MA1F_WIDTH 1
#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
#define LPUART_STAT_PF_MASK 0x10000u
#define LPUART_STAT_PF_SHIFT 16
#define LPUART_STAT_PF_WIDTH 1
#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
#define LPUART_STAT_FE_MASK 0x20000u
#define LPUART_STAT_FE_SHIFT 17
#define LPUART_STAT_FE_WIDTH 1
#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
#define LPUART_STAT_NF_MASK 0x40000u
#define LPUART_STAT_NF_SHIFT 18
#define LPUART_STAT_NF_WIDTH 1
#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
#define LPUART_STAT_OR_MASK 0x80000u
#define LPUART_STAT_OR_SHIFT 19
#define LPUART_STAT_OR_WIDTH 1
#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
#define LPUART_STAT_IDLE_MASK 0x100000u
#define LPUART_STAT_IDLE_SHIFT 20
#define LPUART_STAT_IDLE_WIDTH 1
#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
#define LPUART_STAT_RDRF_MASK 0x200000u
#define LPUART_STAT_RDRF_SHIFT 21
#define LPUART_STAT_RDRF_WIDTH 1
#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
#define LPUART_STAT_TC_MASK 0x400000u
#define LPUART_STAT_TC_SHIFT 22
#define LPUART_STAT_TC_WIDTH 1
#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
#define LPUART_STAT_TDRE_MASK 0x800000u
#define LPUART_STAT_TDRE_SHIFT 23
#define LPUART_STAT_TDRE_WIDTH 1
#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
#define LPUART_STAT_RAF_MASK 0x1000000u
#define LPUART_STAT_RAF_SHIFT 24
#define LPUART_STAT_RAF_WIDTH 1
#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
#define LPUART_STAT_LBKDE_MASK 0x2000000u
#define LPUART_STAT_LBKDE_SHIFT 25
#define LPUART_STAT_LBKDE_WIDTH 1
#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
#define LPUART_STAT_BRK13_MASK 0x4000000u
#define LPUART_STAT_BRK13_SHIFT 26
#define LPUART_STAT_BRK13_WIDTH 1
#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
#define LPUART_STAT_RWUID_MASK 0x8000000u
#define LPUART_STAT_RWUID_SHIFT 27
#define LPUART_STAT_RWUID_WIDTH 1
#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
#define LPUART_STAT_RXINV_MASK 0x10000000u
#define LPUART_STAT_RXINV_SHIFT 28
#define LPUART_STAT_RXINV_WIDTH 1
#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
#define LPUART_STAT_MSBF_MASK 0x20000000u
#define LPUART_STAT_MSBF_SHIFT 29
#define LPUART_STAT_MSBF_WIDTH 1
#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
#define LPUART_STAT_RXEDGIF_SHIFT 30
#define LPUART_STAT_RXEDGIF_WIDTH 1
#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
#define LPUART_STAT_LBKDIF_MASK 0x80000000u
#define LPUART_STAT_LBKDIF_SHIFT 31
#define LPUART_STAT_LBKDIF_WIDTH 1
#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
/* CTRL Bit Fields */
#define LPUART_CTRL_PT_MASK 0x1u
#define LPUART_CTRL_PT_SHIFT 0
#define LPUART_CTRL_PT_WIDTH 1
#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
#define LPUART_CTRL_PE_MASK 0x2u
#define LPUART_CTRL_PE_SHIFT 1
#define LPUART_CTRL_PE_WIDTH 1
#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
#define LPUART_CTRL_ILT_MASK 0x4u
#define LPUART_CTRL_ILT_SHIFT 2
#define LPUART_CTRL_ILT_WIDTH 1
#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
#define LPUART_CTRL_WAKE_MASK 0x8u
#define LPUART_CTRL_WAKE_SHIFT 3
#define LPUART_CTRL_WAKE_WIDTH 1
#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
#define LPUART_CTRL_M_MASK 0x10u
#define LPUART_CTRL_M_SHIFT 4
#define LPUART_CTRL_M_WIDTH 1
#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
#define LPUART_CTRL_RSRC_MASK 0x20u
#define LPUART_CTRL_RSRC_SHIFT 5
#define LPUART_CTRL_RSRC_WIDTH 1
#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
#define LPUART_CTRL_DOZEEN_MASK 0x40u
#define LPUART_CTRL_DOZEEN_SHIFT 6
#define LPUART_CTRL_DOZEEN_WIDTH 1
#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
#define LPUART_CTRL_LOOPS_MASK 0x80u
#define LPUART_CTRL_LOOPS_SHIFT 7
#define LPUART_CTRL_LOOPS_WIDTH 1
#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
#define LPUART_CTRL_IDLECFG_MASK 0x700u
#define LPUART_CTRL_IDLECFG_SHIFT 8
#define LPUART_CTRL_IDLECFG_WIDTH 3
#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
#define LPUART_CTRL_MA2IE_MASK 0x4000u
#define LPUART_CTRL_MA2IE_SHIFT 14
#define LPUART_CTRL_MA2IE_WIDTH 1
#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
#define LPUART_CTRL_MA1IE_MASK 0x8000u
#define LPUART_CTRL_MA1IE_SHIFT 15
#define LPUART_CTRL_MA1IE_WIDTH 1
#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
#define LPUART_CTRL_SBK_MASK 0x10000u
#define LPUART_CTRL_SBK_SHIFT 16
#define LPUART_CTRL_SBK_WIDTH 1
#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
#define LPUART_CTRL_RWU_MASK 0x20000u
#define LPUART_CTRL_RWU_SHIFT 17
#define LPUART_CTRL_RWU_WIDTH 1
#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
#define LPUART_CTRL_RE_MASK 0x40000u
#define LPUART_CTRL_RE_SHIFT 18
#define LPUART_CTRL_RE_WIDTH 1
#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
#define LPUART_CTRL_TE_MASK 0x80000u
#define LPUART_CTRL_TE_SHIFT 19
#define LPUART_CTRL_TE_WIDTH 1
#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
#define LPUART_CTRL_ILIE_MASK 0x100000u
#define LPUART_CTRL_ILIE_SHIFT 20
#define LPUART_CTRL_ILIE_WIDTH 1
#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
#define LPUART_CTRL_RIE_MASK 0x200000u
#define LPUART_CTRL_RIE_SHIFT 21
#define LPUART_CTRL_RIE_WIDTH 1
#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
#define LPUART_CTRL_TCIE_MASK 0x400000u
#define LPUART_CTRL_TCIE_SHIFT 22
#define LPUART_CTRL_TCIE_WIDTH 1
#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
#define LPUART_CTRL_TIE_MASK 0x800000u
#define LPUART_CTRL_TIE_SHIFT 23
#define LPUART_CTRL_TIE_WIDTH 1
#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
#define LPUART_CTRL_PEIE_MASK 0x1000000u
#define LPUART_CTRL_PEIE_SHIFT 24
#define LPUART_CTRL_PEIE_WIDTH 1
#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
#define LPUART_CTRL_FEIE_MASK 0x2000000u
#define LPUART_CTRL_FEIE_SHIFT 25
#define LPUART_CTRL_FEIE_WIDTH 1
#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
#define LPUART_CTRL_NEIE_MASK 0x4000000u
#define LPUART_CTRL_NEIE_SHIFT 26
#define LPUART_CTRL_NEIE_WIDTH 1
#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
#define LPUART_CTRL_ORIE_MASK 0x8000000u
#define LPUART_CTRL_ORIE_SHIFT 27
#define LPUART_CTRL_ORIE_WIDTH 1
#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
#define LPUART_CTRL_TXINV_MASK 0x10000000u
#define LPUART_CTRL_TXINV_SHIFT 28
#define LPUART_CTRL_TXINV_WIDTH 1
#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
#define LPUART_CTRL_TXDIR_MASK 0x20000000u
#define LPUART_CTRL_TXDIR_SHIFT 29
#define LPUART_CTRL_TXDIR_WIDTH 1
#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
#define LPUART_CTRL_R9T8_MASK 0x40000000u
#define LPUART_CTRL_R9T8_SHIFT 30
#define LPUART_CTRL_R9T8_WIDTH 1
#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
#define LPUART_CTRL_R8T9_MASK 0x80000000u
#define LPUART_CTRL_R8T9_SHIFT 31
#define LPUART_CTRL_R8T9_WIDTH 1
#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
/* DATA Bit Fields */
#define LPUART_DATA_R0T0_MASK 0x1u
#define LPUART_DATA_R0T0_SHIFT 0
#define LPUART_DATA_R0T0_WIDTH 1
#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
#define LPUART_DATA_R1T1_MASK 0x2u
#define LPUART_DATA_R1T1_SHIFT 1
#define LPUART_DATA_R1T1_WIDTH 1
#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
#define LPUART_DATA_R2T2_MASK 0x4u
#define LPUART_DATA_R2T2_SHIFT 2
#define LPUART_DATA_R2T2_WIDTH 1
#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
#define LPUART_DATA_R3T3_MASK 0x8u
#define LPUART_DATA_R3T3_SHIFT 3
#define LPUART_DATA_R3T3_WIDTH 1
#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
#define LPUART_DATA_R4T4_MASK 0x10u
#define LPUART_DATA_R4T4_SHIFT 4
#define LPUART_DATA_R4T4_WIDTH 1
#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
#define LPUART_DATA_R5T5_MASK 0x20u
#define LPUART_DATA_R5T5_SHIFT 5
#define LPUART_DATA_R5T5_WIDTH 1
#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
#define LPUART_DATA_R6T6_MASK 0x40u
#define LPUART_DATA_R6T6_SHIFT 6
#define LPUART_DATA_R6T6_WIDTH 1
#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
#define LPUART_DATA_R7T7_MASK 0x80u
#define LPUART_DATA_R7T7_SHIFT 7
#define LPUART_DATA_R7T7_WIDTH 1
#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
#define LPUART_DATA_R8T8_MASK 0x100u
#define LPUART_DATA_R8T8_SHIFT 8
#define LPUART_DATA_R8T8_WIDTH 1
#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
#define LPUART_DATA_R9T9_MASK 0x200u
#define LPUART_DATA_R9T9_SHIFT 9
#define LPUART_DATA_R9T9_WIDTH 1
#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
#define LPUART_DATA_IDLINE_MASK 0x800u
#define LPUART_DATA_IDLINE_SHIFT 11
#define LPUART_DATA_IDLINE_WIDTH 1
#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
#define LPUART_DATA_RXEMPT_MASK 0x1000u
#define LPUART_DATA_RXEMPT_SHIFT 12
#define LPUART_DATA_RXEMPT_WIDTH 1
#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
#define LPUART_DATA_FRETSC_MASK 0x2000u
#define LPUART_DATA_FRETSC_SHIFT 13
#define LPUART_DATA_FRETSC_WIDTH 1
#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
#define LPUART_DATA_PARITYE_MASK 0x4000u
#define LPUART_DATA_PARITYE_SHIFT 14
#define LPUART_DATA_PARITYE_WIDTH 1
#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
#define LPUART_DATA_NOISY_MASK 0x8000u
#define LPUART_DATA_NOISY_SHIFT 15
#define LPUART_DATA_NOISY_WIDTH 1
#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
/* MATCH Bit Fields */
#define LPUART_MATCH_MA1_MASK 0x3FFu
#define LPUART_MATCH_MA1_SHIFT 0
#define LPUART_MATCH_MA1_WIDTH 10
#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
#define LPUART_MATCH_MA2_MASK 0x3FF0000u
#define LPUART_MATCH_MA2_SHIFT 16
#define LPUART_MATCH_MA2_WIDTH 10
#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
/* MODIR Bit Fields */
#define LPUART_MODIR_TXCTSE_MASK 0x1u
#define LPUART_MODIR_TXCTSE_SHIFT 0
#define LPUART_MODIR_TXCTSE_WIDTH 1
#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
#define LPUART_MODIR_TXRTSE_MASK 0x2u
#define LPUART_MODIR_TXRTSE_SHIFT 1
#define LPUART_MODIR_TXRTSE_WIDTH 1
#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
#define LPUART_MODIR_TXRTSPOL_MASK 0x4u
#define LPUART_MODIR_TXRTSPOL_SHIFT 2
#define LPUART_MODIR_TXRTSPOL_WIDTH 1
#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
#define LPUART_MODIR_RXRTSE_MASK 0x8u
#define LPUART_MODIR_RXRTSE_SHIFT 3
#define LPUART_MODIR_RXRTSE_WIDTH 1
#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
#define LPUART_MODIR_TXCTSC_MASK 0x10u
#define LPUART_MODIR_TXCTSC_SHIFT 4
#define LPUART_MODIR_TXCTSC_WIDTH 1
#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
#define LPUART_MODIR_TXCTSSRC_MASK 0x20u
#define LPUART_MODIR_TXCTSSRC_SHIFT 5
#define LPUART_MODIR_TXCTSSRC_WIDTH 1
#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
#define LPUART_MODIR_RTSWATER_MASK 0xFF00u
#define LPUART_MODIR_RTSWATER_SHIFT 8
#define LPUART_MODIR_RTSWATER_WIDTH 8
#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RTSWATER_SHIFT))&LPUART_MODIR_RTSWATER_MASK)
#define LPUART_MODIR_TNP_MASK 0x30000u
#define LPUART_MODIR_TNP_SHIFT 16
#define LPUART_MODIR_TNP_WIDTH 2
#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
#define LPUART_MODIR_IREN_MASK 0x40000u
#define LPUART_MODIR_IREN_SHIFT 18
#define LPUART_MODIR_IREN_WIDTH 1
#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
/* FIFO Bit Fields */
#define LPUART_FIFO_RXFIFOSIZE_MASK 0x7u
#define LPUART_FIFO_RXFIFOSIZE_SHIFT 0
#define LPUART_FIFO_RXFIFOSIZE_WIDTH 3
#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFIFOSIZE_SHIFT))&LPUART_FIFO_RXFIFOSIZE_MASK)
#define LPUART_FIFO_RXFE_MASK 0x8u
#define LPUART_FIFO_RXFE_SHIFT 3
#define LPUART_FIFO_RXFE_WIDTH 1
#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFE_SHIFT))&LPUART_FIFO_RXFE_MASK)
#define LPUART_FIFO_TXFIFOSIZE_MASK 0x70u
#define LPUART_FIFO_TXFIFOSIZE_SHIFT 4
#define LPUART_FIFO_TXFIFOSIZE_WIDTH 3
#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFIFOSIZE_SHIFT))&LPUART_FIFO_TXFIFOSIZE_MASK)
#define LPUART_FIFO_TXFE_MASK 0x80u
#define LPUART_FIFO_TXFE_SHIFT 7
#define LPUART_FIFO_TXFE_WIDTH 1
#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFE_SHIFT))&LPUART_FIFO_TXFE_MASK)
#define LPUART_FIFO_RXUFE_MASK 0x100u
#define LPUART_FIFO_RXUFE_SHIFT 8
#define LPUART_FIFO_RXUFE_WIDTH 1
#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUFE_SHIFT))&LPUART_FIFO_RXUFE_MASK)
#define LPUART_FIFO_TXOFE_MASK 0x200u
#define LPUART_FIFO_TXOFE_SHIFT 9
#define LPUART_FIFO_TXOFE_WIDTH 1
#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOFE_SHIFT))&LPUART_FIFO_TXOFE_MASK)
#define LPUART_FIFO_RXIDEN_MASK 0x1C00u
#define LPUART_FIFO_RXIDEN_SHIFT 10
#define LPUART_FIFO_RXIDEN_WIDTH 3
#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXIDEN_SHIFT))&LPUART_FIFO_RXIDEN_MASK)
#define LPUART_FIFO_RXFLUSH_MASK 0x4000u
#define LPUART_FIFO_RXFLUSH_SHIFT 14
#define LPUART_FIFO_RXFLUSH_WIDTH 1
#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFLUSH_SHIFT))&LPUART_FIFO_RXFLUSH_MASK)
#define LPUART_FIFO_TXFLUSH_MASK 0x8000u
#define LPUART_FIFO_TXFLUSH_SHIFT 15
#define LPUART_FIFO_TXFLUSH_WIDTH 1
#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFLUSH_SHIFT))&LPUART_FIFO_TXFLUSH_MASK)
#define LPUART_FIFO_RXUF_MASK 0x10000u
#define LPUART_FIFO_RXUF_SHIFT 16
#define LPUART_FIFO_RXUF_WIDTH 1
#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUF_SHIFT))&LPUART_FIFO_RXUF_MASK)
#define LPUART_FIFO_TXOF_MASK 0x20000u
#define LPUART_FIFO_TXOF_SHIFT 17
#define LPUART_FIFO_TXOF_WIDTH 1
#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOF_SHIFT))&LPUART_FIFO_TXOF_MASK)
#define LPUART_FIFO_RXEMPT_MASK 0x400000u
#define LPUART_FIFO_RXEMPT_SHIFT 22
#define LPUART_FIFO_RXEMPT_WIDTH 1
#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXEMPT_SHIFT))&LPUART_FIFO_RXEMPT_MASK)
#define LPUART_FIFO_TXEMPT_MASK 0x800000u
#define LPUART_FIFO_TXEMPT_SHIFT 23
#define LPUART_FIFO_TXEMPT_WIDTH 1
#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXEMPT_SHIFT))&LPUART_FIFO_TXEMPT_MASK)
/* WATER Bit Fields */
#define LPUART_WATER_TXWATER_MASK 0xFFu
#define LPUART_WATER_TXWATER_SHIFT 0
#define LPUART_WATER_TXWATER_WIDTH 8
#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXWATER_SHIFT))&LPUART_WATER_TXWATER_MASK)
#define LPUART_WATER_TXCOUNT_MASK 0xFF00u
#define LPUART_WATER_TXCOUNT_SHIFT 8
#define LPUART_WATER_TXCOUNT_WIDTH 8
#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXCOUNT_SHIFT))&LPUART_WATER_TXCOUNT_MASK)
#define LPUART_WATER_RXWATER_MASK 0xFF0000u
#define LPUART_WATER_RXWATER_SHIFT 16
#define LPUART_WATER_RXWATER_WIDTH 8
#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXWATER_SHIFT))&LPUART_WATER_RXWATER_MASK)
#define LPUART_WATER_RXCOUNT_MASK 0xFF000000u
#define LPUART_WATER_RXCOUNT_SHIFT 24
#define LPUART_WATER_RXCOUNT_WIDTH 8
#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXCOUNT_SHIFT))&LPUART_WATER_RXCOUNT_MASK)
/*!
* @}
*/ /* end of group LPUART_Register_Masks */
/* LPUART - Peripheral instance base addresses */
/** Peripheral LPUART0 base address */
#define LPUART0_BASE (0x400C4000u)
/** Peripheral LPUART0 base pointer */
#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
#define LPUART0_BASE_PTR (LPUART0)
/** Peripheral LPUART1 base address */
#define LPUART1_BASE (0x400C5000u)
/** Peripheral LPUART1 base pointer */
#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
#define LPUART1_BASE_PTR (LPUART1)
/** Peripheral LPUART2 base address */
#define LPUART2_BASE (0x40046000u)
/** Peripheral LPUART2 base pointer */
#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
#define LPUART2_BASE_PTR (LPUART2)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 }
/* ----------------------------------------------------------------------------
-- LPUART - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
* @{
*/
/* LPUART - Register instance definitions */
/* LPUART0 */
#define LPUART0_VERID LPUART_VERID_REG(LPUART0)
#define LPUART0_PARAM LPUART_PARAM_REG(LPUART0)
#define LPUART0_GLOBAL LPUART_GLOBAL_REG(LPUART0)
#define LPUART0_PINCFG LPUART_PINCFG_REG(LPUART0)
#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
#define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
#define LPUART0_FIFO LPUART_FIFO_REG(LPUART0)
#define LPUART0_WATER LPUART_WATER_REG(LPUART0)
/* LPUART1 */
#define LPUART1_VERID LPUART_VERID_REG(LPUART1)
#define LPUART1_PARAM LPUART_PARAM_REG(LPUART1)
#define LPUART1_GLOBAL LPUART_GLOBAL_REG(LPUART1)
#define LPUART1_PINCFG LPUART_PINCFG_REG(LPUART1)
#define LPUART1_BAUD LPUART_BAUD_REG(LPUART1)
#define LPUART1_STAT LPUART_STAT_REG(LPUART1)
#define LPUART1_CTRL LPUART_CTRL_REG(LPUART1)
#define LPUART1_DATA LPUART_DATA_REG(LPUART1)
#define LPUART1_MATCH LPUART_MATCH_REG(LPUART1)
#define LPUART1_MODIR LPUART_MODIR_REG(LPUART1)
#define LPUART1_FIFO LPUART_FIFO_REG(LPUART1)
#define LPUART1_WATER LPUART_WATER_REG(LPUART1)
/* LPUART2 */
#define LPUART2_VERID LPUART_VERID_REG(LPUART2)
#define LPUART2_PARAM LPUART_PARAM_REG(LPUART2)
#define LPUART2_GLOBAL LPUART_GLOBAL_REG(LPUART2)
#define LPUART2_PINCFG LPUART_PINCFG_REG(LPUART2)
#define LPUART2_BAUD LPUART_BAUD_REG(LPUART2)
#define LPUART2_STAT LPUART_STAT_REG(LPUART2)
#define LPUART2_CTRL LPUART_CTRL_REG(LPUART2)
#define LPUART2_DATA LPUART_DATA_REG(LPUART2)
#define LPUART2_MATCH LPUART_MATCH_REG(LPUART2)
#define LPUART2_MODIR LPUART_MODIR_REG(LPUART2)
#define LPUART2_FIFO LPUART_FIFO_REG(LPUART2)
#define LPUART2_WATER LPUART_WATER_REG(LPUART2)
/*!
* @}
*/ /* end of group LPUART_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LPUART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
* @{
*/
/** MCM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
__I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
__IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
uint8_t RESERVED_1[48];
__IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
} MCM_Type, *MCM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
* @{
*/
/* MCM - Register accessors */
#define MCM_PLASC_REG(base) ((base)->PLASC)
#define MCM_PLAMC_REG(base) ((base)->PLAMC)
#define MCM_PLACR_REG(base) ((base)->PLACR)
#define MCM_CPO_REG(base) ((base)->CPO)
/*!
* @}
*/ /* end of group MCM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Masks MCM Register Masks
* @{
*/
/* PLASC Bit Fields */
#define MCM_PLASC_ASC_MASK 0xFFu
#define MCM_PLASC_ASC_SHIFT 0
#define MCM_PLASC_ASC_WIDTH 8
#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
/* PLAMC Bit Fields */
#define MCM_PLAMC_AMC_MASK 0xFFu
#define MCM_PLAMC_AMC_SHIFT 0
#define MCM_PLAMC_AMC_WIDTH 8
#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
/* PLACR Bit Fields */
#define MCM_PLACR_MMCAU_MASK 0x100u
#define MCM_PLACR_MMCAU_SHIFT 8
#define MCM_PLACR_MMCAU_WIDTH 1
#define MCM_PLACR_MMCAU(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_MMCAU_SHIFT))&MCM_PLACR_MMCAU_MASK)
#define MCM_PLACR_ARB_MASK 0x200u
#define MCM_PLACR_ARB_SHIFT 9
#define MCM_PLACR_ARB_WIDTH 1
#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ARB_SHIFT))&MCM_PLACR_ARB_MASK)
#define MCM_PLACR_CFCC_MASK 0x400u
#define MCM_PLACR_CFCC_SHIFT 10
#define MCM_PLACR_CFCC_WIDTH 1
#define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_CFCC_SHIFT))&MCM_PLACR_CFCC_MASK)
#define MCM_PLACR_DFCDA_MASK 0x800u
#define MCM_PLACR_DFCDA_SHIFT 11
#define MCM_PLACR_DFCDA_WIDTH 1
#define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCDA_SHIFT))&MCM_PLACR_DFCDA_MASK)
#define MCM_PLACR_DFCIC_MASK 0x1000u
#define MCM_PLACR_DFCIC_SHIFT 12
#define MCM_PLACR_DFCIC_WIDTH 1
#define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCIC_SHIFT))&MCM_PLACR_DFCIC_MASK)
#define MCM_PLACR_DFCC_MASK 0x2000u
#define MCM_PLACR_DFCC_SHIFT 13
#define MCM_PLACR_DFCC_WIDTH 1
#define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCC_SHIFT))&MCM_PLACR_DFCC_MASK)
#define MCM_PLACR_EFDS_MASK 0x4000u
#define MCM_PLACR_EFDS_SHIFT 14
#define MCM_PLACR_EFDS_WIDTH 1
#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_EFDS_SHIFT))&MCM_PLACR_EFDS_MASK)
#define MCM_PLACR_DFCS_MASK 0x8000u
#define MCM_PLACR_DFCS_SHIFT 15
#define MCM_PLACR_DFCS_WIDTH 1
#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCS_SHIFT))&MCM_PLACR_DFCS_MASK)
#define MCM_PLACR_ESFC_MASK 0x10000u
#define MCM_PLACR_ESFC_SHIFT 16
#define MCM_PLACR_ESFC_WIDTH 1
#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ESFC_SHIFT))&MCM_PLACR_ESFC_MASK)
/* CPO Bit Fields */
#define MCM_CPO_CPOREQ_MASK 0x1u
#define MCM_CPO_CPOREQ_SHIFT 0
#define MCM_CPO_CPOREQ_WIDTH 1
#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
#define MCM_CPO_CPOACK_MASK 0x2u
#define MCM_CPO_CPOACK_SHIFT 1
#define MCM_CPO_CPOACK_WIDTH 1
#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
#define MCM_CPO_CPOWOI_MASK 0x4u
#define MCM_CPO_CPOWOI_SHIFT 2
#define MCM_CPO_CPOWOI_WIDTH 1
#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
/*!
* @}
*/ /* end of group MCM_Register_Masks */
/* MCM - Peripheral instance base addresses */
/** Peripheral MCM0 base address */
#define MCM0_BASE (0xF0003000u)
/** Peripheral MCM0 base pointer */
#define MCM0 ((MCM_Type *)MCM0_BASE)
#define MCM0_BASE_PTR (MCM0)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS { MCM0_BASE }
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASE_PTRS { MCM0 }
/* ----------------------------------------------------------------------------
-- MCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
* @{
*/
/* MCM - Register instance definitions */
/* MCM0 */
#define MCM0_PLASC MCM_PLASC_REG(MCM0)
#define MCM0_PLAMC MCM_PLAMC_REG(MCM0)
#define MCM0_PLACR MCM_PLACR_REG(MCM0)
#define MCM0_CPO MCM_CPO_REG(MCM0)
/*!
* @}
*/ /* end of group MCM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MMDVSQ Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer
* @{
*/
/** MMDVSQ - Register Layout Typedef */
typedef struct {
__IO uint32_t DEND; /**< Dividend Register, offset: 0x0 */
__IO uint32_t DSOR; /**< Divisor Register, offset: 0x4 */
__IO uint32_t CSR; /**< Control/Status Register, offset: 0x8 */
__IO uint32_t RES; /**< Result Register, offset: 0xC */
__IO uint32_t RCND; /**< Radicand Register, offset: 0x10 */
} MMDVSQ_Type, *MMDVSQ_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MMDVSQ - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MMDVSQ_Register_Accessor_Macros MMDVSQ - Register accessor macros
* @{
*/
/* MMDVSQ - Register accessors */
#define MMDVSQ_DEND_REG(base) ((base)->DEND)
#define MMDVSQ_DSOR_REG(base) ((base)->DSOR)
#define MMDVSQ_CSR_REG(base) ((base)->CSR)
#define MMDVSQ_RES_REG(base) ((base)->RES)
#define MMDVSQ_RCND_REG(base) ((base)->RCND)
/*!
* @}
*/ /* end of group MMDVSQ_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MMDVSQ Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks
* @{
*/
/* DEND Bit Fields */
#define MMDVSQ_DEND_DIVIDEND_MASK 0xFFFFFFFFu
#define MMDVSQ_DEND_DIVIDEND_SHIFT 0
#define MMDVSQ_DEND_DIVIDEND_WIDTH 32
#define MMDVSQ_DEND_DIVIDEND(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_DEND_DIVIDEND_SHIFT))&MMDVSQ_DEND_DIVIDEND_MASK)
/* DSOR Bit Fields */
#define MMDVSQ_DSOR_DIVISOR_MASK 0xFFFFFFFFu
#define MMDVSQ_DSOR_DIVISOR_SHIFT 0
#define MMDVSQ_DSOR_DIVISOR_WIDTH 32
#define MMDVSQ_DSOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_DSOR_DIVISOR_SHIFT))&MMDVSQ_DSOR_DIVISOR_MASK)
/* CSR Bit Fields */
#define MMDVSQ_CSR_SRT_MASK 0x1u
#define MMDVSQ_CSR_SRT_SHIFT 0
#define MMDVSQ_CSR_SRT_WIDTH 1
#define MMDVSQ_CSR_SRT(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_SRT_SHIFT))&MMDVSQ_CSR_SRT_MASK)
#define MMDVSQ_CSR_USGN_MASK 0x2u
#define MMDVSQ_CSR_USGN_SHIFT 1
#define MMDVSQ_CSR_USGN_WIDTH 1
#define MMDVSQ_CSR_USGN(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_USGN_SHIFT))&MMDVSQ_CSR_USGN_MASK)
#define MMDVSQ_CSR_REM_MASK 0x4u
#define MMDVSQ_CSR_REM_SHIFT 2
#define MMDVSQ_CSR_REM_WIDTH 1
#define MMDVSQ_CSR_REM(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_REM_SHIFT))&MMDVSQ_CSR_REM_MASK)
#define MMDVSQ_CSR_DZE_MASK 0x8u
#define MMDVSQ_CSR_DZE_SHIFT 3
#define MMDVSQ_CSR_DZE_WIDTH 1
#define MMDVSQ_CSR_DZE(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_DZE_SHIFT))&MMDVSQ_CSR_DZE_MASK)
#define MMDVSQ_CSR_DZ_MASK 0x10u
#define MMDVSQ_CSR_DZ_SHIFT 4
#define MMDVSQ_CSR_DZ_WIDTH 1
#define MMDVSQ_CSR_DZ(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_DZ_SHIFT))&MMDVSQ_CSR_DZ_MASK)
#define MMDVSQ_CSR_DFS_MASK 0x20u
#define MMDVSQ_CSR_DFS_SHIFT 5
#define MMDVSQ_CSR_DFS_WIDTH 1
#define MMDVSQ_CSR_DFS(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_DFS_SHIFT))&MMDVSQ_CSR_DFS_MASK)
#define MMDVSQ_CSR_SQRT_MASK 0x20000000u
#define MMDVSQ_CSR_SQRT_SHIFT 29
#define MMDVSQ_CSR_SQRT_WIDTH 1
#define MMDVSQ_CSR_SQRT(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_SQRT_SHIFT))&MMDVSQ_CSR_SQRT_MASK)
#define MMDVSQ_CSR_DIV_MASK 0x40000000u
#define MMDVSQ_CSR_DIV_SHIFT 30
#define MMDVSQ_CSR_DIV_WIDTH 1
#define MMDVSQ_CSR_DIV(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_DIV_SHIFT))&MMDVSQ_CSR_DIV_MASK)
#define MMDVSQ_CSR_BUSY_MASK 0x80000000u
#define MMDVSQ_CSR_BUSY_SHIFT 31
#define MMDVSQ_CSR_BUSY_WIDTH 1
#define MMDVSQ_CSR_BUSY(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_CSR_BUSY_SHIFT))&MMDVSQ_CSR_BUSY_MASK)
/* RES Bit Fields */
#define MMDVSQ_RES_RESULT_MASK 0xFFFFFFFFu
#define MMDVSQ_RES_RESULT_SHIFT 0
#define MMDVSQ_RES_RESULT_WIDTH 32
#define MMDVSQ_RES_RESULT(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_RES_RESULT_SHIFT))&MMDVSQ_RES_RESULT_MASK)
/* RCND Bit Fields */
#define MMDVSQ_RCND_RADICAND_MASK 0xFFFFFFFFu
#define MMDVSQ_RCND_RADICAND_SHIFT 0
#define MMDVSQ_RCND_RADICAND_WIDTH 32
#define MMDVSQ_RCND_RADICAND(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_RCND_RADICAND_SHIFT))&MMDVSQ_RCND_RADICAND_MASK)
/*!
* @}
*/ /* end of group MMDVSQ_Register_Masks */
/* MMDVSQ - Peripheral instance base addresses */
/** Peripheral MMDVSQ0 base address */
#define MMDVSQ0_BASE (0xF0004000u)
/** Peripheral MMDVSQ0 base pointer */
#define MMDVSQ0 ((MMDVSQ_Type *)MMDVSQ0_BASE)
#define MMDVSQ0_BASE_PTR (MMDVSQ0)
/** Array initializer of MMDVSQ peripheral base addresses */
#define MMDVSQ_BASE_ADDRS { MMDVSQ0_BASE }
/** Array initializer of MMDVSQ peripheral base pointers */
#define MMDVSQ_BASE_PTRS { MMDVSQ0 }
/* ----------------------------------------------------------------------------
-- MMDVSQ - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MMDVSQ_Register_Accessor_Macros MMDVSQ - Register accessor macros
* @{
*/
/* MMDVSQ - Register instance definitions */
/* MMDVSQ0 */
#define MMDVSQ0_DEND MMDVSQ_DEND_REG(MMDVSQ0)
#define MMDVSQ0_DSOR MMDVSQ_DSOR_REG(MMDVSQ0)
#define MMDVSQ0_CSR MMDVSQ_CSR_REG(MMDVSQ0)
#define MMDVSQ0_RES MMDVSQ_RES_REG(MMDVSQ0)
#define MMDVSQ0_RCND MMDVSQ_RCND_REG(MMDVSQ0)
/*!
* @}
*/ /* end of group MMDVSQ_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group MMDVSQ_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MSCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer
* @{
*/
/** MSCM - Register Layout Typedef */
typedef struct {
__I uint32_t CPxTYPE; /**< Processor X Type Register, offset: 0x0 */
__I uint32_t CPxNUM; /**< Processor X Number Register, offset: 0x4 */
__I uint32_t CPxMASTER; /**< Processor X Master Register, offset: 0x8 */
__I uint32_t CPxCOUNT; /**< Processor X Count Register, offset: 0xC */
__I uint32_t CPxCFG[4]; /**< Processor X Configuration Register, array offset: 0x10, array step: 0x4 */
__I uint32_t CP0TYPE; /**< Processor 0 Type Register, offset: 0x20 */
__I uint32_t CP0NUM; /**< Processor 0 Number Register, offset: 0x24 */
__I uint32_t CP0MASTER; /**< Processor 0 Master Register, offset: 0x28 */
__I uint32_t CP0COUNT; /**< Processor 0 Count Register, offset: 0x2C */
__I uint32_t CP0CFG[4]; /**< Processor 0 Configuration Register, array offset: 0x30, array step: 0x4 */
uint8_t RESERVED_0[960];
__I uint32_t OCMDR[3]; /**< On-Chip Memory Descriptor Register, array offset: 0x400, array step: 0x4 */
} MSCM_Type, *MSCM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MSCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MSCM_Register_Accessor_Macros MSCM - Register accessor macros
* @{
*/
/* MSCM - Register accessors */
#define MSCM_CPxTYPE_REG(base) ((base)->CPxTYPE)
#define MSCM_CPxNUM_REG(base) ((base)->CPxNUM)
#define MSCM_CPxMASTER_REG(base) ((base)->CPxMASTER)
#define MSCM_CPxCOUNT_REG(base) ((base)->CPxCOUNT)
#define MSCM_CPxCFG_REG(base,index) ((base)->CPxCFG[index])
#define MSCM_CPxCFG_COUNT 4
#define MSCM_CP0TYPE_REG(base) ((base)->CP0TYPE)
#define MSCM_CP0NUM_REG(base) ((base)->CP0NUM)
#define MSCM_CP0MASTER_REG(base) ((base)->CP0MASTER)
#define MSCM_CP0COUNT_REG(base) ((base)->CP0COUNT)
#define MSCM_CP0CFG_REG(base,index) ((base)->CP0CFG[index])
#define MSCM_CP0CFG_COUNT 4
#define MSCM_OCMDR_REG(base,index) ((base)->OCMDR[index])
#define MSCM_OCMDR_COUNT 3
/*!
* @}
*/ /* end of group MSCM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MSCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MSCM_Register_Masks MSCM Register Masks
* @{
*/
/* CPxTYPE Bit Fields */
#define MSCM_CPxTYPE_RYPZ_MASK 0xFFu
#define MSCM_CPxTYPE_RYPZ_SHIFT 0
#define MSCM_CPxTYPE_RYPZ_WIDTH 8
#define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_RYPZ_SHIFT))&MSCM_CPxTYPE_RYPZ_MASK)
#define MSCM_CPxTYPE_PERSONALITY_MASK 0xFFFFFF00u
#define MSCM_CPxTYPE_PERSONALITY_SHIFT 8
#define MSCM_CPxTYPE_PERSONALITY_WIDTH 24
#define MSCM_CPxTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_PERSONALITY_SHIFT))&MSCM_CPxTYPE_PERSONALITY_MASK)
/* CPxNUM Bit Fields */
#define MSCM_CPxNUM_CPN_MASK 0x1u
#define MSCM_CPxNUM_CPN_SHIFT 0
#define MSCM_CPxNUM_CPN_WIDTH 1
#define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxNUM_CPN_SHIFT))&MSCM_CPxNUM_CPN_MASK)
/* CPxMASTER Bit Fields */
#define MSCM_CPxMASTER_PPN_MASK 0x3Fu
#define MSCM_CPxMASTER_PPN_SHIFT 0
#define MSCM_CPxMASTER_PPN_WIDTH 6
#define MSCM_CPxMASTER_PPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxMASTER_PPN_SHIFT))&MSCM_CPxMASTER_PPN_MASK)
/* CPxCOUNT Bit Fields */
#define MSCM_CPxCOUNT_PCNT_MASK 0x3u
#define MSCM_CPxCOUNT_PCNT_SHIFT 0
#define MSCM_CPxCOUNT_PCNT_WIDTH 2
#define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCOUNT_PCNT_SHIFT))&MSCM_CPxCOUNT_PCNT_MASK)
/* CPxCFG Bit Fields */
#define MSCM_CPxCFG_DCWY_MASK 0xFFu
#define MSCM_CPxCFG_DCWY_SHIFT 0
#define MSCM_CPxCFG_DCWY_WIDTH 8
#define MSCM_CPxCFG_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG_DCWY_SHIFT))&MSCM_CPxCFG_DCWY_MASK)
#define MSCM_CPxCFG_DCSZ_MASK 0xFF00u
#define MSCM_CPxCFG_DCSZ_SHIFT 8
#define MSCM_CPxCFG_DCSZ_WIDTH 8
#define MSCM_CPxCFG_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG_DCSZ_SHIFT))&MSCM_CPxCFG_DCSZ_MASK)
#define MSCM_CPxCFG_ICWY_MASK 0xFF0000u
#define MSCM_CPxCFG_ICWY_SHIFT 16
#define MSCM_CPxCFG_ICWY_WIDTH 8
#define MSCM_CPxCFG_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG_ICWY_SHIFT))&MSCM_CPxCFG_ICWY_MASK)
#define MSCM_CPxCFG_ICSZ_MASK 0xFF000000u
#define MSCM_CPxCFG_ICSZ_SHIFT 24
#define MSCM_CPxCFG_ICSZ_WIDTH 8
#define MSCM_CPxCFG_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG_ICSZ_SHIFT))&MSCM_CPxCFG_ICSZ_MASK)
/* CP0TYPE Bit Fields */
#define MSCM_CP0TYPE_RYPZ_MASK 0xFFu
#define MSCM_CP0TYPE_RYPZ_SHIFT 0
#define MSCM_CP0TYPE_RYPZ_WIDTH 8
#define MSCM_CP0TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_RYPZ_SHIFT))&MSCM_CP0TYPE_RYPZ_MASK)
#define MSCM_CP0TYPE_PERSONALITY_MASK 0xFFFFFF00u
#define MSCM_CP0TYPE_PERSONALITY_SHIFT 8
#define MSCM_CP0TYPE_PERSONALITY_WIDTH 24
#define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_PERSONALITY_SHIFT))&MSCM_CP0TYPE_PERSONALITY_MASK)
/* CP0NUM Bit Fields */
#define MSCM_CP0NUM_CPN_MASK 0x1u
#define MSCM_CP0NUM_CPN_SHIFT 0
#define MSCM_CP0NUM_CPN_WIDTH 1
#define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0NUM_CPN_SHIFT))&MSCM_CP0NUM_CPN_MASK)
/* CP0MASTER Bit Fields */
#define MSCM_CP0MASTER_PPN_MASK 0x3Fu
#define MSCM_CP0MASTER_PPN_SHIFT 0
#define MSCM_CP0MASTER_PPN_WIDTH 6
#define MSCM_CP0MASTER_PPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0MASTER_PPN_SHIFT))&MSCM_CP0MASTER_PPN_MASK)
/* CP0COUNT Bit Fields */
#define MSCM_CP0COUNT_PCNT_MASK 0x3u
#define MSCM_CP0COUNT_PCNT_SHIFT 0
#define MSCM_CP0COUNT_PCNT_WIDTH 2
#define MSCM_CP0COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0COUNT_PCNT_SHIFT))&MSCM_CP0COUNT_PCNT_MASK)
/* CP0CFG Bit Fields */
#define MSCM_CP0CFG_DCWY_MASK 0xFFu
#define MSCM_CP0CFG_DCWY_SHIFT 0
#define MSCM_CP0CFG_DCWY_WIDTH 8
#define MSCM_CP0CFG_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG_DCWY_SHIFT))&MSCM_CP0CFG_DCWY_MASK)
#define MSCM_CP0CFG_DCSZ_MASK 0xFF00u
#define MSCM_CP0CFG_DCSZ_SHIFT 8
#define MSCM_CP0CFG_DCSZ_WIDTH 8
#define MSCM_CP0CFG_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG_DCSZ_SHIFT))&MSCM_CP0CFG_DCSZ_MASK)
#define MSCM_CP0CFG_ICWY_MASK 0xFF0000u
#define MSCM_CP0CFG_ICWY_SHIFT 16
#define MSCM_CP0CFG_ICWY_WIDTH 8
#define MSCM_CP0CFG_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG_ICWY_SHIFT))&MSCM_CP0CFG_ICWY_MASK)
#define MSCM_CP0CFG_ICSZ_MASK 0xFF000000u
#define MSCM_CP0CFG_ICSZ_SHIFT 24
#define MSCM_CP0CFG_ICSZ_WIDTH 8
#define MSCM_CP0CFG_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG_ICSZ_SHIFT))&MSCM_CP0CFG_ICSZ_MASK)
/* OCMDR Bit Fields */
#define MSCM_OCMDR_OCMPU_MASK 0x1000u
#define MSCM_OCMDR_OCMPU_SHIFT 12
#define MSCM_OCMDR_OCMPU_WIDTH 1
#define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMPU_SHIFT))&MSCM_OCMDR_OCMPU_MASK)
#define MSCM_OCMDR_OCMT_MASK 0xE000u
#define MSCM_OCMDR_OCMT_SHIFT 13
#define MSCM_OCMDR_OCMT_WIDTH 3
#define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMT_SHIFT))&MSCM_OCMDR_OCMT_MASK)
#define MSCM_OCMDR_RO_MASK 0x10000u
#define MSCM_OCMDR_RO_SHIFT 16
#define MSCM_OCMDR_RO_WIDTH 1
#define MSCM_OCMDR_RO(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_RO_SHIFT))&MSCM_OCMDR_RO_MASK)
#define MSCM_OCMDR_OCMW_MASK 0xE0000u
#define MSCM_OCMDR_OCMW_SHIFT 17
#define MSCM_OCMDR_OCMW_WIDTH 3
#define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMW_SHIFT))&MSCM_OCMDR_OCMW_MASK)
#define MSCM_OCMDR_OCMSZ_MASK 0xF000000u
#define MSCM_OCMDR_OCMSZ_SHIFT 24
#define MSCM_OCMDR_OCMSZ_WIDTH 4
#define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZ_SHIFT))&MSCM_OCMDR_OCMSZ_MASK)
#define MSCM_OCMDR_OCMSZH_MASK 0x10000000u
#define MSCM_OCMDR_OCMSZH_SHIFT 28
#define MSCM_OCMDR_OCMSZH_WIDTH 1
#define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZH_SHIFT))&MSCM_OCMDR_OCMSZH_MASK)
#define MSCM_OCMDR_V_MASK 0x80000000u
#define MSCM_OCMDR_V_SHIFT 31
#define MSCM_OCMDR_V_WIDTH 1
#define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_V_SHIFT))&MSCM_OCMDR_V_MASK)
/*!
* @}
*/ /* end of group MSCM_Register_Masks */
/* MSCM - Peripheral instance base addresses */
/** Peripheral MSCM base address */
#define MSCM_BASE (0x40001000u)
/** Peripheral MSCM base pointer */
#define MSCM ((MSCM_Type *)MSCM_BASE)
#define MSCM_BASE_PTR (MSCM)
/** Array initializer of MSCM peripheral base addresses */
#define MSCM_BASE_ADDRS { MSCM_BASE }
/** Array initializer of MSCM peripheral base pointers */
#define MSCM_BASE_PTRS { MSCM }
/* ----------------------------------------------------------------------------
-- MSCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MSCM_Register_Accessor_Macros MSCM - Register accessor macros
* @{
*/
/* MSCM - Register instance definitions */
/* MSCM */
#define MSCM_CPxTYPE MSCM_CPxTYPE_REG(MSCM)
#define MSCM_CPxNUM MSCM_CPxNUM_REG(MSCM)
#define MSCM_CPxMASTER MSCM_CPxMASTER_REG(MSCM)
#define MSCM_CPxCOUNT MSCM_CPxCOUNT_REG(MSCM)
#define MSCM_CPxCFG0 MSCM_CPxCFG_REG(MSCM,0)
#define MSCM_CPxCFG1 MSCM_CPxCFG_REG(MSCM,1)
#define MSCM_CPxCFG2 MSCM_CPxCFG_REG(MSCM,2)
#define MSCM_CPxCFG3 MSCM_CPxCFG_REG(MSCM,3)
#define MSCM_CP0TYPE MSCM_CP0TYPE_REG(MSCM)
#define MSCM_CP0NUM MSCM_CP0NUM_REG(MSCM)
#define MSCM_CP0MASTER MSCM_CP0MASTER_REG(MSCM)
#define MSCM_CP0COUNT MSCM_CP0COUNT_REG(MSCM)
#define MSCM_CP0CFG0 MSCM_CP0CFG_REG(MSCM,0)
#define MSCM_CP0CFG1 MSCM_CP0CFG_REG(MSCM,1)
#define MSCM_CP0CFG2 MSCM_CP0CFG_REG(MSCM,2)
#define MSCM_CP0CFG3 MSCM_CP0CFG_REG(MSCM,3)
#define MSCM_OCMDR0 MSCM_OCMDR_REG(MSCM,0)
#define MSCM_OCMDR1 MSCM_OCMDR_REG(MSCM,1)
#define MSCM_OCMDR2 MSCM_OCMDR_REG(MSCM,2)
/* MSCM - Register array accessors */
#define MSCM_CPxCFG(index) MSCM_CPxCFG_REG(MSCM,index)
#define MSCM_CP0CFG(index) MSCM_CP0CFG_REG(MSCM,index)
#define MSCM_OCMDR(index) MSCM_OCMDR_REG(MSCM,index)
/*!
* @}
*/ /* end of group MSCM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group MSCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MTB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
* @{
*/
/** MTB - Register Layout Typedef */
typedef struct {
__IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
__IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
__IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
__I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
uint8_t RESERVED_0[3824];
__I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
uint8_t RESERVED_1[156];
__I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
__I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
uint8_t RESERVED_2[8];
__I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
__I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
__I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
__I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
uint8_t RESERVED_3[8];
__I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
__I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
__I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
} MTB_Type, *MTB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MTB - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
* @{
*/
/* MTB - Register accessors */
#define MTB_POSITION_REG(base) ((base)->POSITION)
#define MTB_MASTER_REG(base) ((base)->MASTER)
#define MTB_FLOW_REG(base) ((base)->FLOW)
#define MTB_BASE_REG(base) ((base)->BASE)
#define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
#define MTB_TAGSET_REG(base) ((base)->TAGSET)
#define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
#define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
#define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
#define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
#define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
#define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
#define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
#define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
#define MTB_PERIPHID_COUNT 8
#define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
#define MTB_COMPID_COUNT 4
/*!
* @}
*/ /* end of group MTB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MTB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Register_Masks MTB Register Masks
* @{
*/
/* POSITION Bit Fields */
#define MTB_POSITION_WRAP_MASK 0x4u
#define MTB_POSITION_WRAP_SHIFT 2
#define MTB_POSITION_WRAP_WIDTH 1
#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_WRAP_SHIFT))&MTB_POSITION_WRAP_MASK)
#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
#define MTB_POSITION_POINTER_SHIFT 3
#define MTB_POSITION_POINTER_WIDTH 29
#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
/* MASTER Bit Fields */
#define MTB_MASTER_MASK_MASK 0x1Fu
#define MTB_MASTER_MASK_SHIFT 0
#define MTB_MASTER_MASK_WIDTH 5
#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
#define MTB_MASTER_TSTARTEN_MASK 0x20u
#define MTB_MASTER_TSTARTEN_SHIFT 5
#define MTB_MASTER_TSTARTEN_WIDTH 1
#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_TSTARTEN_SHIFT))&MTB_MASTER_TSTARTEN_MASK)
#define MTB_MASTER_TSTOPEN_MASK 0x40u
#define MTB_MASTER_TSTOPEN_SHIFT 6
#define MTB_MASTER_TSTOPEN_WIDTH 1
#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_TSTOPEN_SHIFT))&MTB_MASTER_TSTOPEN_MASK)
#define MTB_MASTER_SFRWPRIV_MASK 0x80u
#define MTB_MASTER_SFRWPRIV_SHIFT 7
#define MTB_MASTER_SFRWPRIV_WIDTH 1
#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_SFRWPRIV_SHIFT))&MTB_MASTER_SFRWPRIV_MASK)
#define MTB_MASTER_RAMPRIV_MASK 0x100u
#define MTB_MASTER_RAMPRIV_SHIFT 8
#define MTB_MASTER_RAMPRIV_WIDTH 1
#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_RAMPRIV_SHIFT))&MTB_MASTER_RAMPRIV_MASK)
#define MTB_MASTER_HALTREQ_MASK 0x200u
#define MTB_MASTER_HALTREQ_SHIFT 9
#define MTB_MASTER_HALTREQ_WIDTH 1
#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_HALTREQ_SHIFT))&MTB_MASTER_HALTREQ_MASK)
#define MTB_MASTER_EN_MASK 0x80000000u
#define MTB_MASTER_EN_SHIFT 31
#define MTB_MASTER_EN_WIDTH 1
#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_EN_SHIFT))&MTB_MASTER_EN_MASK)
/* FLOW Bit Fields */
#define MTB_FLOW_AUTOSTOP_MASK 0x1u
#define MTB_FLOW_AUTOSTOP_SHIFT 0
#define MTB_FLOW_AUTOSTOP_WIDTH 1
#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_AUTOSTOP_SHIFT))&MTB_FLOW_AUTOSTOP_MASK)
#define MTB_FLOW_AUTOHALT_MASK 0x2u
#define MTB_FLOW_AUTOHALT_SHIFT 1
#define MTB_FLOW_AUTOHALT_WIDTH 1
#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_AUTOHALT_SHIFT))&MTB_FLOW_AUTOHALT_MASK)
#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
#define MTB_FLOW_WATERMARK_SHIFT 3
#define MTB_FLOW_WATERMARK_WIDTH 29
#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
/* BASE Bit Fields */
#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
#define MTB_BASE_BASEADDR_SHIFT 0
#define MTB_BASE_BASEADDR_WIDTH 32
#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
/* MODECTRL Bit Fields */
#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
#define MTB_MODECTRL_MODECTRL_SHIFT 0
#define MTB_MODECTRL_MODECTRL_WIDTH 32
#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
/* TAGSET Bit Fields */
#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
#define MTB_TAGSET_TAGSET_SHIFT 0
#define MTB_TAGSET_TAGSET_WIDTH 32
#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
/* TAGCLEAR Bit Fields */
#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
#define MTB_TAGCLEAR_TAGCLEAR_WIDTH 32
#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
/* LOCKACCESS Bit Fields */
#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
#define MTB_LOCKACCESS_LOCKACCESS_WIDTH 32
#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
/* LOCKSTAT Bit Fields */
#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
#define MTB_LOCKSTAT_LOCKSTAT_WIDTH 32
#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
/* AUTHSTAT Bit Fields */
#define MTB_AUTHSTAT_BIT0_MASK 0x1u
#define MTB_AUTHSTAT_BIT0_SHIFT 0
#define MTB_AUTHSTAT_BIT0_WIDTH 1
#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT0_SHIFT))&MTB_AUTHSTAT_BIT0_MASK)
#define MTB_AUTHSTAT_BIT1_MASK 0x2u
#define MTB_AUTHSTAT_BIT1_SHIFT 1
#define MTB_AUTHSTAT_BIT1_WIDTH 1
#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT1_SHIFT))&MTB_AUTHSTAT_BIT1_MASK)
#define MTB_AUTHSTAT_BIT2_MASK 0x4u
#define MTB_AUTHSTAT_BIT2_SHIFT 2
#define MTB_AUTHSTAT_BIT2_WIDTH 1
#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT2_SHIFT))&MTB_AUTHSTAT_BIT2_MASK)
#define MTB_AUTHSTAT_BIT3_MASK 0x8u
#define MTB_AUTHSTAT_BIT3_SHIFT 3
#define MTB_AUTHSTAT_BIT3_WIDTH 1
#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT3_SHIFT))&MTB_AUTHSTAT_BIT3_MASK)
/* DEVICEARCH Bit Fields */
#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
#define MTB_DEVICEARCH_DEVICEARCH_WIDTH 32
#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
/* DEVICECFG Bit Fields */
#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
#define MTB_DEVICECFG_DEVICECFG_WIDTH 32
#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
/* DEVICETYPID Bit Fields */
#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
#define MTB_DEVICETYPID_DEVICETYPID_WIDTH 32
#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
/* PERIPHID Bit Fields */
#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
#define MTB_PERIPHID_PERIPHID_SHIFT 0
#define MTB_PERIPHID_PERIPHID_WIDTH 32
#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
/* COMPID Bit Fields */
#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
#define MTB_COMPID_COMPID_SHIFT 0
#define MTB_COMPID_COMPID_WIDTH 32
#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
/*!
* @}
*/ /* end of group MTB_Register_Masks */
/* MTB - Peripheral instance base addresses */
/** Peripheral MTB0 base address */
#define MTB0_BASE (0xF0000000u)
/** Peripheral MTB0 base pointer */
#define MTB0 ((MTB_Type *)MTB0_BASE)
#define MTB0_BASE_PTR (MTB0)
/** Array initializer of MTB peripheral base addresses */
#define MTB_BASE_ADDRS { MTB0_BASE }
/** Array initializer of MTB peripheral base pointers */
#define MTB_BASE_PTRS { MTB0 }
/* ----------------------------------------------------------------------------
-- MTB - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
* @{
*/
/* MTB - Register instance definitions */
/* MTB0 */
#define MTB0_POSITION MTB_POSITION_REG(MTB0)
#define MTB0_MASTER MTB_MASTER_REG(MTB0)
#define MTB0_FLOW MTB_FLOW_REG(MTB0)
#define MTB0_BASEr MTB_BASE_REG(MTB0)
#define MTB0_MODECTRL MTB_MODECTRL_REG(MTB0)
#define MTB0_TAGSET MTB_TAGSET_REG(MTB0)
#define MTB0_TAGCLEAR MTB_TAGCLEAR_REG(MTB0)
#define MTB0_LOCKACCESS MTB_LOCKACCESS_REG(MTB0)
#define MTB0_LOCKSTAT MTB_LOCKSTAT_REG(MTB0)
#define MTB0_AUTHSTAT MTB_AUTHSTAT_REG(MTB0)
#define MTB0_DEVICEARCH MTB_DEVICEARCH_REG(MTB0)
#define MTB0_DEVICECFG MTB_DEVICECFG_REG(MTB0)
#define MTB0_DEVICETYPID MTB_DEVICETYPID_REG(MTB0)
#define MTB0_PERIPHID4 MTB_PERIPHID_REG(MTB0,0)
#define MTB0_PERIPHID5 MTB_PERIPHID_REG(MTB0,1)
#define MTB0_PERIPHID6 MTB_PERIPHID_REG(MTB0,2)
#define MTB0_PERIPHID7 MTB_PERIPHID_REG(MTB0,3)
#define MTB0_PERIPHID0 MTB_PERIPHID_REG(MTB0,4)
#define MTB0_PERIPHID1 MTB_PERIPHID_REG(MTB0,5)
#define MTB0_PERIPHID2 MTB_PERIPHID_REG(MTB0,6)
#define MTB0_PERIPHID3 MTB_PERIPHID_REG(MTB0,7)
#define MTB0_COMPID0 MTB_COMPID_REG(MTB0,0)
#define MTB0_COMPID1 MTB_COMPID_REG(MTB0,1)
#define MTB0_COMPID2 MTB_COMPID_REG(MTB0,2)
#define MTB0_COMPID3 MTB_COMPID_REG(MTB0,3)
/* MTB - Register array accessors */
#define MTB0_PERIPHID(index) MTB_PERIPHID_REG(MTB0,index)
#define MTB0_COMPID(index) MTB_COMPID_REG(MTB0,index)
/*!
* @}
*/ /* end of group MTB_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group MTB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- NV Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
* @{
*/
/** NV - Register Layout Typedef */
typedef struct {
__I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
__I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
__I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
__I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
__I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
__I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
__I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
__I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
__I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
__I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
__I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
__I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
__I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
} NV_Type, *NV_MemMapPtr;
/* ----------------------------------------------------------------------------
-- NV - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
* @{
*/
/* NV - Register accessors */
#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
#define NV_FPROT3_REG(base) ((base)->FPROT3)
#define NV_FPROT2_REG(base) ((base)->FPROT2)
#define NV_FPROT1_REG(base) ((base)->FPROT1)
#define NV_FPROT0_REG(base) ((base)->FPROT0)
#define NV_FSEC_REG(base) ((base)->FSEC)
#define NV_FOPT_REG(base) ((base)->FOPT)
/*!
* @}
*/ /* end of group NV_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- NV Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Masks NV Register Masks
* @{
*/
/* BACKKEY3 Bit Fields */
#define NV_BACKKEY3_KEY_MASK 0xFFu
#define NV_BACKKEY3_KEY_SHIFT 0
#define NV_BACKKEY3_KEY_WIDTH 8
#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
/* BACKKEY2 Bit Fields */
#define NV_BACKKEY2_KEY_MASK 0xFFu
#define NV_BACKKEY2_KEY_SHIFT 0
#define NV_BACKKEY2_KEY_WIDTH 8
#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
/* BACKKEY1 Bit Fields */
#define NV_BACKKEY1_KEY_MASK 0xFFu
#define NV_BACKKEY1_KEY_SHIFT 0
#define NV_BACKKEY1_KEY_WIDTH 8
#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
/* BACKKEY0 Bit Fields */
#define NV_BACKKEY0_KEY_MASK 0xFFu
#define NV_BACKKEY0_KEY_SHIFT 0
#define NV_BACKKEY0_KEY_WIDTH 8
#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
/* BACKKEY7 Bit Fields */
#define NV_BACKKEY7_KEY_MASK 0xFFu
#define NV_BACKKEY7_KEY_SHIFT 0
#define NV_BACKKEY7_KEY_WIDTH 8
#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
/* BACKKEY6 Bit Fields */
#define NV_BACKKEY6_KEY_MASK 0xFFu
#define NV_BACKKEY6_KEY_SHIFT 0
#define NV_BACKKEY6_KEY_WIDTH 8
#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
/* BACKKEY5 Bit Fields */
#define NV_BACKKEY5_KEY_MASK 0xFFu
#define NV_BACKKEY5_KEY_SHIFT 0
#define NV_BACKKEY5_KEY_WIDTH 8
#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
/* BACKKEY4 Bit Fields */
#define NV_BACKKEY4_KEY_MASK 0xFFu
#define NV_BACKKEY4_KEY_SHIFT 0
#define NV_BACKKEY4_KEY_WIDTH 8
#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
/* FPROT3 Bit Fields */
#define NV_FPROT3_PROT_MASK 0xFFu
#define NV_FPROT3_PROT_SHIFT 0
#define NV_FPROT3_PROT_WIDTH 8
#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
/* FPROT2 Bit Fields */
#define NV_FPROT2_PROT_MASK 0xFFu
#define NV_FPROT2_PROT_SHIFT 0
#define NV_FPROT2_PROT_WIDTH 8
#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
/* FPROT1 Bit Fields */
#define NV_FPROT1_PROT_MASK 0xFFu
#define NV_FPROT1_PROT_SHIFT 0
#define NV_FPROT1_PROT_WIDTH 8
#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
/* FPROT0 Bit Fields */
#define NV_FPROT0_PROT_MASK 0xFFu
#define NV_FPROT0_PROT_SHIFT 0
#define NV_FPROT0_PROT_WIDTH 8
#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
/* FSEC Bit Fields */
#define NV_FSEC_SEC_MASK 0x3u
#define NV_FSEC_SEC_SHIFT 0
#define NV_FSEC_SEC_WIDTH 2
#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
#define NV_FSEC_FSLACC_MASK 0xCu
#define NV_FSEC_FSLACC_SHIFT 2
#define NV_FSEC_FSLACC_WIDTH 2
#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
#define NV_FSEC_MEEN_MASK 0x30u
#define NV_FSEC_MEEN_SHIFT 4
#define NV_FSEC_MEEN_WIDTH 2
#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
#define NV_FSEC_KEYEN_MASK 0xC0u
#define NV_FSEC_KEYEN_SHIFT 6
#define NV_FSEC_KEYEN_WIDTH 2
#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
/* FOPT Bit Fields */
#define NV_FOPT_LPBOOT0_MASK 0x1u
#define NV_FOPT_LPBOOT0_SHIFT 0
#define NV_FOPT_LPBOOT0_WIDTH 1
#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT0_SHIFT))&NV_FOPT_LPBOOT0_MASK)
#define NV_FOPT_BOOTPIN_OPT_MASK 0x2u
#define NV_FOPT_BOOTPIN_OPT_SHIFT 1
#define NV_FOPT_BOOTPIN_OPT_WIDTH 1
#define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTPIN_OPT_SHIFT))&NV_FOPT_BOOTPIN_OPT_MASK)
#define NV_FOPT_NMI_DIS_MASK 0x4u
#define NV_FOPT_NMI_DIS_SHIFT 2
#define NV_FOPT_NMI_DIS_WIDTH 1
#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_NMI_DIS_SHIFT))&NV_FOPT_NMI_DIS_MASK)
#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
#define NV_FOPT_RESET_PIN_CFG_WIDTH 1
#define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_RESET_PIN_CFG_SHIFT))&NV_FOPT_RESET_PIN_CFG_MASK)
#define NV_FOPT_LPBOOT1_MASK 0x10u
#define NV_FOPT_LPBOOT1_SHIFT 4
#define NV_FOPT_LPBOOT1_WIDTH 1
#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT1_SHIFT))&NV_FOPT_LPBOOT1_MASK)
#define NV_FOPT_FAST_INIT_MASK 0x20u
#define NV_FOPT_FAST_INIT_SHIFT 5
#define NV_FOPT_FAST_INIT_WIDTH 1
#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_FAST_INIT_SHIFT))&NV_FOPT_FAST_INIT_MASK)
#define NV_FOPT_BOOTSRC_SEL_MASK 0xC0u
#define NV_FOPT_BOOTSRC_SEL_SHIFT 6
#define NV_FOPT_BOOTSRC_SEL_WIDTH 2
#define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK)
/*!
* @}
*/ /* end of group NV_Register_Masks */
/* NV - Peripheral instance base addresses */
/** Peripheral FTFA_FlashConfig base address */
#define FTFA_FlashConfig_BASE (0x400u)
/** Peripheral FTFA_FlashConfig base pointer */
#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
/** Array initializer of NV peripheral base addresses */
#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
/** Array initializer of NV peripheral base pointers */
#define NV_BASE_PTRS { FTFA_FlashConfig }
/* ----------------------------------------------------------------------------
-- NV - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
* @{
*/
/* NV - Register instance definitions */
/* FTFA_FlashConfig */
#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
/*!
* @}
*/ /* end of group NV_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PCC0 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC0_Peripheral_Access_Layer PCC0 Peripheral Access Layer
* @{
*/
/** PCC0 - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[32];
__IO uint32_t PCC_DMA0; /**< PCC_DMA0 Register, offset: 0x20 */
uint8_t RESERVED_1[92];
__IO uint32_t PCC_FLASH; /**< PCC_FLASH Register, offset: 0x80 */
__IO uint32_t PCC_DMAMUX0; /**< PCC_DMAMUX0 Register, offset: 0x84 */
uint8_t RESERVED_2[8];
__IO uint32_t PCC_INTMUX0; /**< PCC_INTMUX0 Register, offset: 0x90 */
uint8_t RESERVED_3[36];
__IO uint32_t PCC_TPM2; /**< PCC_TPM2 Register, offset: 0xB8 */
uint8_t RESERVED_4[4];
__IO uint32_t PCC_LPIT0; /**< PCC_LPIT0 Register, offset: 0xC0 */
uint8_t RESERVED_5[12];
__IO uint32_t PCC_LPTMR0; /**< PCC_LPTMR0 Register, offset: 0xD0 */
uint8_t RESERVED_6[12];
__IO uint32_t PCC_RTC; /**< PCC_RTC Register, offset: 0xE0 */
uint8_t RESERVED_7[20];
__IO uint32_t PCC_LPSPI2; /**< PCC_LPSPI2 Register, offset: 0xF8 */
uint8_t RESERVED_8[12];
__IO uint32_t PCC_LPI2C2; /**< PCC_LPI2C2 Register, offset: 0x108 */
uint8_t RESERVED_9[12];
__IO uint32_t PCC_LPUART2; /**< PCC_LPUART2 Register, offset: 0x118 */
uint8_t RESERVED_10[20];
__IO uint32_t PCC_SAI0; /**< PCC_SAI0 Register, offset: 0x130 */
uint8_t RESERVED_11[4];
__IO uint32_t PCC_EVMSIM0; /**< PCC_EVMSIM0 Register, offset: 0x138 */
uint8_t RESERVED_12[24];
__IO uint32_t PCC_USB0FS; /**< PCC_USB0FS Register, offset: 0x154 */
uint8_t RESERVED_13[16];
__IO uint32_t PCC_PORTA; /**< PCC_PORTA Register, offset: 0x168 */
__IO uint32_t PCC_PORTB; /**< PCC_PORTB Register, offset: 0x16C */
__IO uint32_t PCC_PORTC; /**< PCC_PORTC Register, offset: 0x170 */
__IO uint32_t PCC_PORTD; /**< PCC_PORTD Register, offset: 0x174 */
__IO uint32_t PCC_PORTE; /**< PCC_PORTE Register, offset: 0x178 */
uint8_t RESERVED_14[12];
__IO uint32_t PCC_TSI0; /**< PCC_TSI0 Register, offset: 0x188 */
uint8_t RESERVED_15[12];
__IO uint32_t PCC_ADC0; /**< PCC_ADC0 Register, offset: 0x198 */
uint8_t RESERVED_16[12];
__IO uint32_t PCC_DAC0; /**< PCC_DAC0 Register, offset: 0x1A8 */
uint8_t RESERVED_17[12];
__IO uint32_t PCC_CMP0; /**< PCC_CMP0 Register, offset: 0x1B8 */
uint8_t RESERVED_18[12];
__IO uint32_t PCC_VREF; /**< PCC_VREF Register, offset: 0x1C8 */
uint8_t RESERVED_19[20];
__IO uint32_t PCC_CRC; /**< PCC_CRC Register, offset: 0x1E0 */
} PCC0_Type, *PCC0_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PCC0 - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC0_Register_Accessor_Macros PCC0 - Register accessor macros
* @{
*/
/* PCC0 - Register accessors */
#define PCC0_PCC_DMA0_REG(base) ((base)->PCC_DMA0)
#define PCC0_PCC_FLASH_REG(base) ((base)->PCC_FLASH)
#define PCC0_PCC_DMAMUX0_REG(base) ((base)->PCC_DMAMUX0)
#define PCC0_PCC_INTMUX0_REG(base) ((base)->PCC_INTMUX0)
#define PCC0_PCC_TPM2_REG(base) ((base)->PCC_TPM2)
#define PCC0_PCC_LPIT0_REG(base) ((base)->PCC_LPIT0)
#define PCC0_PCC_LPTMR0_REG(base) ((base)->PCC_LPTMR0)
#define PCC0_PCC_RTC_REG(base) ((base)->PCC_RTC)
#define PCC0_PCC_LPSPI2_REG(base) ((base)->PCC_LPSPI2)
#define PCC0_PCC_LPI2C2_REG(base) ((base)->PCC_LPI2C2)
#define PCC0_PCC_LPUART2_REG(base) ((base)->PCC_LPUART2)
#define PCC0_PCC_SAI0_REG(base) ((base)->PCC_SAI0)
#define PCC0_PCC_EVMSIM0_REG(base) ((base)->PCC_EVMSIM0)
#define PCC0_PCC_USB0FS_REG(base) ((base)->PCC_USB0FS)
#define PCC0_PCC_PORTA_REG(base) ((base)->PCC_PORTA)
#define PCC0_PCC_PORTB_REG(base) ((base)->PCC_PORTB)
#define PCC0_PCC_PORTC_REG(base) ((base)->PCC_PORTC)
#define PCC0_PCC_PORTD_REG(base) ((base)->PCC_PORTD)
#define PCC0_PCC_PORTE_REG(base) ((base)->PCC_PORTE)
#define PCC0_PCC_TSI0_REG(base) ((base)->PCC_TSI0)
#define PCC0_PCC_ADC0_REG(base) ((base)->PCC_ADC0)
#define PCC0_PCC_DAC0_REG(base) ((base)->PCC_DAC0)
#define PCC0_PCC_CMP0_REG(base) ((base)->PCC_CMP0)
#define PCC0_PCC_VREF_REG(base) ((base)->PCC_VREF)
#define PCC0_PCC_CRC_REG(base) ((base)->PCC_CRC)
/*!
* @}
*/ /* end of group PCC0_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PCC0 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC0_Register_Masks PCC0 Register Masks
* @{
*/
/* PCC_DMA0 Bit Fields */
#define PCC0_PCC_DMA0_INUSE_MASK 0x20000000u
#define PCC0_PCC_DMA0_INUSE_SHIFT 29
#define PCC0_PCC_DMA0_INUSE_WIDTH 1
#define PCC0_PCC_DMA0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DMA0_INUSE_SHIFT))&PCC0_PCC_DMA0_INUSE_MASK)
#define PCC0_PCC_DMA0_CGC_MASK 0x40000000u
#define PCC0_PCC_DMA0_CGC_SHIFT 30
#define PCC0_PCC_DMA0_CGC_WIDTH 1
#define PCC0_PCC_DMA0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DMA0_CGC_SHIFT))&PCC0_PCC_DMA0_CGC_MASK)
#define PCC0_PCC_DMA0_PR_MASK 0x80000000u
#define PCC0_PCC_DMA0_PR_SHIFT 31
#define PCC0_PCC_DMA0_PR_WIDTH 1
#define PCC0_PCC_DMA0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DMA0_PR_SHIFT))&PCC0_PCC_DMA0_PR_MASK)
/* PCC_FLASH Bit Fields */
#define PCC0_PCC_FLASH_INUSE_MASK 0x20000000u
#define PCC0_PCC_FLASH_INUSE_SHIFT 29
#define PCC0_PCC_FLASH_INUSE_WIDTH 1
#define PCC0_PCC_FLASH_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_FLASH_INUSE_SHIFT))&PCC0_PCC_FLASH_INUSE_MASK)
#define PCC0_PCC_FLASH_CGC_MASK 0x40000000u
#define PCC0_PCC_FLASH_CGC_SHIFT 30
#define PCC0_PCC_FLASH_CGC_WIDTH 1
#define PCC0_PCC_FLASH_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_FLASH_CGC_SHIFT))&PCC0_PCC_FLASH_CGC_MASK)
#define PCC0_PCC_FLASH_PR_MASK 0x80000000u
#define PCC0_PCC_FLASH_PR_SHIFT 31
#define PCC0_PCC_FLASH_PR_WIDTH 1
#define PCC0_PCC_FLASH_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_FLASH_PR_SHIFT))&PCC0_PCC_FLASH_PR_MASK)
/* PCC_DMAMUX0 Bit Fields */
#define PCC0_PCC_DMAMUX0_INUSE_MASK 0x20000000u
#define PCC0_PCC_DMAMUX0_INUSE_SHIFT 29
#define PCC0_PCC_DMAMUX0_INUSE_WIDTH 1
#define PCC0_PCC_DMAMUX0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DMAMUX0_INUSE_SHIFT))&PCC0_PCC_DMAMUX0_INUSE_MASK)
#define PCC0_PCC_DMAMUX0_CGC_MASK 0x40000000u
#define PCC0_PCC_DMAMUX0_CGC_SHIFT 30
#define PCC0_PCC_DMAMUX0_CGC_WIDTH 1
#define PCC0_PCC_DMAMUX0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DMAMUX0_CGC_SHIFT))&PCC0_PCC_DMAMUX0_CGC_MASK)
#define PCC0_PCC_DMAMUX0_PR_MASK 0x80000000u
#define PCC0_PCC_DMAMUX0_PR_SHIFT 31
#define PCC0_PCC_DMAMUX0_PR_WIDTH 1
#define PCC0_PCC_DMAMUX0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DMAMUX0_PR_SHIFT))&PCC0_PCC_DMAMUX0_PR_MASK)
/* PCC_INTMUX0 Bit Fields */
#define PCC0_PCC_INTMUX0_INUSE_MASK 0x20000000u
#define PCC0_PCC_INTMUX0_INUSE_SHIFT 29
#define PCC0_PCC_INTMUX0_INUSE_WIDTH 1
#define PCC0_PCC_INTMUX0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_INTMUX0_INUSE_SHIFT))&PCC0_PCC_INTMUX0_INUSE_MASK)
#define PCC0_PCC_INTMUX0_CGC_MASK 0x40000000u
#define PCC0_PCC_INTMUX0_CGC_SHIFT 30
#define PCC0_PCC_INTMUX0_CGC_WIDTH 1
#define PCC0_PCC_INTMUX0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_INTMUX0_CGC_SHIFT))&PCC0_PCC_INTMUX0_CGC_MASK)
#define PCC0_PCC_INTMUX0_PR_MASK 0x80000000u
#define PCC0_PCC_INTMUX0_PR_SHIFT 31
#define PCC0_PCC_INTMUX0_PR_WIDTH 1
#define PCC0_PCC_INTMUX0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_INTMUX0_PR_SHIFT))&PCC0_PCC_INTMUX0_PR_MASK)
/* PCC_TPM2 Bit Fields */
#define PCC0_PCC_TPM2_PCS_MASK 0x7000000u
#define PCC0_PCC_TPM2_PCS_SHIFT 24
#define PCC0_PCC_TPM2_PCS_WIDTH 3
#define PCC0_PCC_TPM2_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_TPM2_PCS_SHIFT))&PCC0_PCC_TPM2_PCS_MASK)
#define PCC0_PCC_TPM2_INUSE_MASK 0x20000000u
#define PCC0_PCC_TPM2_INUSE_SHIFT 29
#define PCC0_PCC_TPM2_INUSE_WIDTH 1
#define PCC0_PCC_TPM2_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_TPM2_INUSE_SHIFT))&PCC0_PCC_TPM2_INUSE_MASK)
#define PCC0_PCC_TPM2_CGC_MASK 0x40000000u
#define PCC0_PCC_TPM2_CGC_SHIFT 30
#define PCC0_PCC_TPM2_CGC_WIDTH 1
#define PCC0_PCC_TPM2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_TPM2_CGC_SHIFT))&PCC0_PCC_TPM2_CGC_MASK)
#define PCC0_PCC_TPM2_PR_MASK 0x80000000u
#define PCC0_PCC_TPM2_PR_SHIFT 31
#define PCC0_PCC_TPM2_PR_WIDTH 1
#define PCC0_PCC_TPM2_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_TPM2_PR_SHIFT))&PCC0_PCC_TPM2_PR_MASK)
/* PCC_LPIT0 Bit Fields */
#define PCC0_PCC_LPIT0_PCS_MASK 0x7000000u
#define PCC0_PCC_LPIT0_PCS_SHIFT 24
#define PCC0_PCC_LPIT0_PCS_WIDTH 3
#define PCC0_PCC_LPIT0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPIT0_PCS_SHIFT))&PCC0_PCC_LPIT0_PCS_MASK)
#define PCC0_PCC_LPIT0_INUSE_MASK 0x20000000u
#define PCC0_PCC_LPIT0_INUSE_SHIFT 29
#define PCC0_PCC_LPIT0_INUSE_WIDTH 1
#define PCC0_PCC_LPIT0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPIT0_INUSE_SHIFT))&PCC0_PCC_LPIT0_INUSE_MASK)
#define PCC0_PCC_LPIT0_CGC_MASK 0x40000000u
#define PCC0_PCC_LPIT0_CGC_SHIFT 30
#define PCC0_PCC_LPIT0_CGC_WIDTH 1
#define PCC0_PCC_LPIT0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPIT0_CGC_SHIFT))&PCC0_PCC_LPIT0_CGC_MASK)
#define PCC0_PCC_LPIT0_PR_MASK 0x80000000u
#define PCC0_PCC_LPIT0_PR_SHIFT 31
#define PCC0_PCC_LPIT0_PR_WIDTH 1
#define PCC0_PCC_LPIT0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPIT0_PR_SHIFT))&PCC0_PCC_LPIT0_PR_MASK)
/* PCC_LPTMR0 Bit Fields */
#define PCC0_PCC_LPTMR0_INUSE_MASK 0x20000000u
#define PCC0_PCC_LPTMR0_INUSE_SHIFT 29
#define PCC0_PCC_LPTMR0_INUSE_WIDTH 1
#define PCC0_PCC_LPTMR0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPTMR0_INUSE_SHIFT))&PCC0_PCC_LPTMR0_INUSE_MASK)
#define PCC0_PCC_LPTMR0_CGC_MASK 0x40000000u
#define PCC0_PCC_LPTMR0_CGC_SHIFT 30
#define PCC0_PCC_LPTMR0_CGC_WIDTH 1
#define PCC0_PCC_LPTMR0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPTMR0_CGC_SHIFT))&PCC0_PCC_LPTMR0_CGC_MASK)
#define PCC0_PCC_LPTMR0_PR_MASK 0x80000000u
#define PCC0_PCC_LPTMR0_PR_SHIFT 31
#define PCC0_PCC_LPTMR0_PR_WIDTH 1
#define PCC0_PCC_LPTMR0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPTMR0_PR_SHIFT))&PCC0_PCC_LPTMR0_PR_MASK)
/* PCC_RTC Bit Fields */
#define PCC0_PCC_RTC_INUSE_MASK 0x20000000u
#define PCC0_PCC_RTC_INUSE_SHIFT 29
#define PCC0_PCC_RTC_INUSE_WIDTH 1
#define PCC0_PCC_RTC_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_RTC_INUSE_SHIFT))&PCC0_PCC_RTC_INUSE_MASK)
#define PCC0_PCC_RTC_CGC_MASK 0x40000000u
#define PCC0_PCC_RTC_CGC_SHIFT 30
#define PCC0_PCC_RTC_CGC_WIDTH 1
#define PCC0_PCC_RTC_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_RTC_CGC_SHIFT))&PCC0_PCC_RTC_CGC_MASK)
#define PCC0_PCC_RTC_PR_MASK 0x80000000u
#define PCC0_PCC_RTC_PR_SHIFT 31
#define PCC0_PCC_RTC_PR_WIDTH 1
#define PCC0_PCC_RTC_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_RTC_PR_SHIFT))&PCC0_PCC_RTC_PR_MASK)
/* PCC_LPSPI2 Bit Fields */
#define PCC0_PCC_LPSPI2_PCS_MASK 0x7000000u
#define PCC0_PCC_LPSPI2_PCS_SHIFT 24
#define PCC0_PCC_LPSPI2_PCS_WIDTH 3
#define PCC0_PCC_LPSPI2_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPSPI2_PCS_SHIFT))&PCC0_PCC_LPSPI2_PCS_MASK)
#define PCC0_PCC_LPSPI2_INUSE_MASK 0x20000000u
#define PCC0_PCC_LPSPI2_INUSE_SHIFT 29
#define PCC0_PCC_LPSPI2_INUSE_WIDTH 1
#define PCC0_PCC_LPSPI2_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPSPI2_INUSE_SHIFT))&PCC0_PCC_LPSPI2_INUSE_MASK)
#define PCC0_PCC_LPSPI2_CGC_MASK 0x40000000u
#define PCC0_PCC_LPSPI2_CGC_SHIFT 30
#define PCC0_PCC_LPSPI2_CGC_WIDTH 1
#define PCC0_PCC_LPSPI2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPSPI2_CGC_SHIFT))&PCC0_PCC_LPSPI2_CGC_MASK)
#define PCC0_PCC_LPSPI2_PR_MASK 0x80000000u
#define PCC0_PCC_LPSPI2_PR_SHIFT 31
#define PCC0_PCC_LPSPI2_PR_WIDTH 1
#define PCC0_PCC_LPSPI2_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPSPI2_PR_SHIFT))&PCC0_PCC_LPSPI2_PR_MASK)
/* PCC_LPI2C2 Bit Fields */
#define PCC0_PCC_LPI2C2_PCS_MASK 0x7000000u
#define PCC0_PCC_LPI2C2_PCS_SHIFT 24
#define PCC0_PCC_LPI2C2_PCS_WIDTH 3
#define PCC0_PCC_LPI2C2_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPI2C2_PCS_SHIFT))&PCC0_PCC_LPI2C2_PCS_MASK)
#define PCC0_PCC_LPI2C2_INUSE_MASK 0x20000000u
#define PCC0_PCC_LPI2C2_INUSE_SHIFT 29
#define PCC0_PCC_LPI2C2_INUSE_WIDTH 1
#define PCC0_PCC_LPI2C2_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPI2C2_INUSE_SHIFT))&PCC0_PCC_LPI2C2_INUSE_MASK)
#define PCC0_PCC_LPI2C2_CGC_MASK 0x40000000u
#define PCC0_PCC_LPI2C2_CGC_SHIFT 30
#define PCC0_PCC_LPI2C2_CGC_WIDTH 1
#define PCC0_PCC_LPI2C2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPI2C2_CGC_SHIFT))&PCC0_PCC_LPI2C2_CGC_MASK)
#define PCC0_PCC_LPI2C2_PR_MASK 0x80000000u
#define PCC0_PCC_LPI2C2_PR_SHIFT 31
#define PCC0_PCC_LPI2C2_PR_WIDTH 1
#define PCC0_PCC_LPI2C2_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPI2C2_PR_SHIFT))&PCC0_PCC_LPI2C2_PR_MASK)
/* PCC_LPUART2 Bit Fields */
#define PCC0_PCC_LPUART2_PCS_MASK 0x7000000u
#define PCC0_PCC_LPUART2_PCS_SHIFT 24
#define PCC0_PCC_LPUART2_PCS_WIDTH 3
#define PCC0_PCC_LPUART2_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPUART2_PCS_SHIFT))&PCC0_PCC_LPUART2_PCS_MASK)
#define PCC0_PCC_LPUART2_INUSE_MASK 0x20000000u
#define PCC0_PCC_LPUART2_INUSE_SHIFT 29
#define PCC0_PCC_LPUART2_INUSE_WIDTH 1
#define PCC0_PCC_LPUART2_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPUART2_INUSE_SHIFT))&PCC0_PCC_LPUART2_INUSE_MASK)
#define PCC0_PCC_LPUART2_CGC_MASK 0x40000000u
#define PCC0_PCC_LPUART2_CGC_SHIFT 30
#define PCC0_PCC_LPUART2_CGC_WIDTH 1
#define PCC0_PCC_LPUART2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPUART2_CGC_SHIFT))&PCC0_PCC_LPUART2_CGC_MASK)
#define PCC0_PCC_LPUART2_PR_MASK 0x80000000u
#define PCC0_PCC_LPUART2_PR_SHIFT 31
#define PCC0_PCC_LPUART2_PR_WIDTH 1
#define PCC0_PCC_LPUART2_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_LPUART2_PR_SHIFT))&PCC0_PCC_LPUART2_PR_MASK)
/* PCC_SAI0 Bit Fields */
#define PCC0_PCC_SAI0_PCS_MASK 0x7000000u
#define PCC0_PCC_SAI0_PCS_SHIFT 24
#define PCC0_PCC_SAI0_PCS_WIDTH 3
#define PCC0_PCC_SAI0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_SAI0_PCS_SHIFT))&PCC0_PCC_SAI0_PCS_MASK)
#define PCC0_PCC_SAI0_INUSE_MASK 0x20000000u
#define PCC0_PCC_SAI0_INUSE_SHIFT 29
#define PCC0_PCC_SAI0_INUSE_WIDTH 1
#define PCC0_PCC_SAI0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_SAI0_INUSE_SHIFT))&PCC0_PCC_SAI0_INUSE_MASK)
#define PCC0_PCC_SAI0_CGC_MASK 0x40000000u
#define PCC0_PCC_SAI0_CGC_SHIFT 30
#define PCC0_PCC_SAI0_CGC_WIDTH 1
#define PCC0_PCC_SAI0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_SAI0_CGC_SHIFT))&PCC0_PCC_SAI0_CGC_MASK)
#define PCC0_PCC_SAI0_PR_MASK 0x80000000u
#define PCC0_PCC_SAI0_PR_SHIFT 31
#define PCC0_PCC_SAI0_PR_WIDTH 1
#define PCC0_PCC_SAI0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_SAI0_PR_SHIFT))&PCC0_PCC_SAI0_PR_MASK)
/* PCC_EVMSIM0 Bit Fields */
#define PCC0_PCC_EVMSIM0_PCS_MASK 0x7000000u
#define PCC0_PCC_EVMSIM0_PCS_SHIFT 24
#define PCC0_PCC_EVMSIM0_PCS_WIDTH 3
#define PCC0_PCC_EVMSIM0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_EVMSIM0_PCS_SHIFT))&PCC0_PCC_EVMSIM0_PCS_MASK)
#define PCC0_PCC_EVMSIM0_INUSE_MASK 0x20000000u
#define PCC0_PCC_EVMSIM0_INUSE_SHIFT 29
#define PCC0_PCC_EVMSIM0_INUSE_WIDTH 1
#define PCC0_PCC_EVMSIM0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_EVMSIM0_INUSE_SHIFT))&PCC0_PCC_EVMSIM0_INUSE_MASK)
#define PCC0_PCC_EVMSIM0_CGC_MASK 0x40000000u
#define PCC0_PCC_EVMSIM0_CGC_SHIFT 30
#define PCC0_PCC_EVMSIM0_CGC_WIDTH 1
#define PCC0_PCC_EVMSIM0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_EVMSIM0_CGC_SHIFT))&PCC0_PCC_EVMSIM0_CGC_MASK)
#define PCC0_PCC_EVMSIM0_PR_MASK 0x80000000u
#define PCC0_PCC_EVMSIM0_PR_SHIFT 31
#define PCC0_PCC_EVMSIM0_PR_WIDTH 1
#define PCC0_PCC_EVMSIM0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_EVMSIM0_PR_SHIFT))&PCC0_PCC_EVMSIM0_PR_MASK)
/* PCC_USB0FS Bit Fields */
#define PCC0_PCC_USB0FS_PCD_MASK 0x7u
#define PCC0_PCC_USB0FS_PCD_SHIFT 0
#define PCC0_PCC_USB0FS_PCD_WIDTH 3
#define PCC0_PCC_USB0FS_PCD(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_USB0FS_PCD_SHIFT))&PCC0_PCC_USB0FS_PCD_MASK)
#define PCC0_PCC_USB0FS_FRAC_MASK 0x8u
#define PCC0_PCC_USB0FS_FRAC_SHIFT 3
#define PCC0_PCC_USB0FS_FRAC_WIDTH 1
#define PCC0_PCC_USB0FS_FRAC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_USB0FS_FRAC_SHIFT))&PCC0_PCC_USB0FS_FRAC_MASK)
#define PCC0_PCC_USB0FS_PCS_MASK 0x7000000u
#define PCC0_PCC_USB0FS_PCS_SHIFT 24
#define PCC0_PCC_USB0FS_PCS_WIDTH 3
#define PCC0_PCC_USB0FS_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_USB0FS_PCS_SHIFT))&PCC0_PCC_USB0FS_PCS_MASK)
#define PCC0_PCC_USB0FS_INUSE_MASK 0x20000000u
#define PCC0_PCC_USB0FS_INUSE_SHIFT 29
#define PCC0_PCC_USB0FS_INUSE_WIDTH 1
#define PCC0_PCC_USB0FS_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_USB0FS_INUSE_SHIFT))&PCC0_PCC_USB0FS_INUSE_MASK)
#define PCC0_PCC_USB0FS_CGC_MASK 0x40000000u
#define PCC0_PCC_USB0FS_CGC_SHIFT 30
#define PCC0_PCC_USB0FS_CGC_WIDTH 1
#define PCC0_PCC_USB0FS_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_USB0FS_CGC_SHIFT))&PCC0_PCC_USB0FS_CGC_MASK)
#define PCC0_PCC_USB0FS_PR_MASK 0x80000000u
#define PCC0_PCC_USB0FS_PR_SHIFT 31
#define PCC0_PCC_USB0FS_PR_WIDTH 1
#define PCC0_PCC_USB0FS_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_USB0FS_PR_SHIFT))&PCC0_PCC_USB0FS_PR_MASK)
/* PCC_PORTA Bit Fields */
#define PCC0_PCC_PORTA_INUSE_MASK 0x20000000u
#define PCC0_PCC_PORTA_INUSE_SHIFT 29
#define PCC0_PCC_PORTA_INUSE_WIDTH 1
#define PCC0_PCC_PORTA_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTA_INUSE_SHIFT))&PCC0_PCC_PORTA_INUSE_MASK)
#define PCC0_PCC_PORTA_CGC_MASK 0x40000000u
#define PCC0_PCC_PORTA_CGC_SHIFT 30
#define PCC0_PCC_PORTA_CGC_WIDTH 1
#define PCC0_PCC_PORTA_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTA_CGC_SHIFT))&PCC0_PCC_PORTA_CGC_MASK)
#define PCC0_PCC_PORTA_PR_MASK 0x80000000u
#define PCC0_PCC_PORTA_PR_SHIFT 31
#define PCC0_PCC_PORTA_PR_WIDTH 1
#define PCC0_PCC_PORTA_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTA_PR_SHIFT))&PCC0_PCC_PORTA_PR_MASK)
/* PCC_PORTB Bit Fields */
#define PCC0_PCC_PORTB_INUSE_MASK 0x20000000u
#define PCC0_PCC_PORTB_INUSE_SHIFT 29
#define PCC0_PCC_PORTB_INUSE_WIDTH 1
#define PCC0_PCC_PORTB_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTB_INUSE_SHIFT))&PCC0_PCC_PORTB_INUSE_MASK)
#define PCC0_PCC_PORTB_CGC_MASK 0x40000000u
#define PCC0_PCC_PORTB_CGC_SHIFT 30
#define PCC0_PCC_PORTB_CGC_WIDTH 1
#define PCC0_PCC_PORTB_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTB_CGC_SHIFT))&PCC0_PCC_PORTB_CGC_MASK)
#define PCC0_PCC_PORTB_PR_MASK 0x80000000u
#define PCC0_PCC_PORTB_PR_SHIFT 31
#define PCC0_PCC_PORTB_PR_WIDTH 1
#define PCC0_PCC_PORTB_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTB_PR_SHIFT))&PCC0_PCC_PORTB_PR_MASK)
/* PCC_PORTC Bit Fields */
#define PCC0_PCC_PORTC_INUSE_MASK 0x20000000u
#define PCC0_PCC_PORTC_INUSE_SHIFT 29
#define PCC0_PCC_PORTC_INUSE_WIDTH 1
#define PCC0_PCC_PORTC_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTC_INUSE_SHIFT))&PCC0_PCC_PORTC_INUSE_MASK)
#define PCC0_PCC_PORTC_CGC_MASK 0x40000000u
#define PCC0_PCC_PORTC_CGC_SHIFT 30
#define PCC0_PCC_PORTC_CGC_WIDTH 1
#define PCC0_PCC_PORTC_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTC_CGC_SHIFT))&PCC0_PCC_PORTC_CGC_MASK)
#define PCC0_PCC_PORTC_PR_MASK 0x80000000u
#define PCC0_PCC_PORTC_PR_SHIFT 31
#define PCC0_PCC_PORTC_PR_WIDTH 1
#define PCC0_PCC_PORTC_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTC_PR_SHIFT))&PCC0_PCC_PORTC_PR_MASK)
/* PCC_PORTD Bit Fields */
#define PCC0_PCC_PORTD_INUSE_MASK 0x20000000u
#define PCC0_PCC_PORTD_INUSE_SHIFT 29
#define PCC0_PCC_PORTD_INUSE_WIDTH 1
#define PCC0_PCC_PORTD_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTD_INUSE_SHIFT))&PCC0_PCC_PORTD_INUSE_MASK)
#define PCC0_PCC_PORTD_CGC_MASK 0x40000000u
#define PCC0_PCC_PORTD_CGC_SHIFT 30
#define PCC0_PCC_PORTD_CGC_WIDTH 1
#define PCC0_PCC_PORTD_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTD_CGC_SHIFT))&PCC0_PCC_PORTD_CGC_MASK)
#define PCC0_PCC_PORTD_PR_MASK 0x80000000u
#define PCC0_PCC_PORTD_PR_SHIFT 31
#define PCC0_PCC_PORTD_PR_WIDTH 1
#define PCC0_PCC_PORTD_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTD_PR_SHIFT))&PCC0_PCC_PORTD_PR_MASK)
/* PCC_PORTE Bit Fields */
#define PCC0_PCC_PORTE_INUSE_MASK 0x20000000u
#define PCC0_PCC_PORTE_INUSE_SHIFT 29
#define PCC0_PCC_PORTE_INUSE_WIDTH 1
#define PCC0_PCC_PORTE_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTE_INUSE_SHIFT))&PCC0_PCC_PORTE_INUSE_MASK)
#define PCC0_PCC_PORTE_CGC_MASK 0x40000000u
#define PCC0_PCC_PORTE_CGC_SHIFT 30
#define PCC0_PCC_PORTE_CGC_WIDTH 1
#define PCC0_PCC_PORTE_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTE_CGC_SHIFT))&PCC0_PCC_PORTE_CGC_MASK)
#define PCC0_PCC_PORTE_PR_MASK 0x80000000u
#define PCC0_PCC_PORTE_PR_SHIFT 31
#define PCC0_PCC_PORTE_PR_WIDTH 1
#define PCC0_PCC_PORTE_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_PORTE_PR_SHIFT))&PCC0_PCC_PORTE_PR_MASK)
/* PCC_TSI0 Bit Fields */
#define PCC0_PCC_TSI0_INUSE_MASK 0x20000000u
#define PCC0_PCC_TSI0_INUSE_SHIFT 29
#define PCC0_PCC_TSI0_INUSE_WIDTH 1
#define PCC0_PCC_TSI0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_TSI0_INUSE_SHIFT))&PCC0_PCC_TSI0_INUSE_MASK)
#define PCC0_PCC_TSI0_CGC_MASK 0x40000000u
#define PCC0_PCC_TSI0_CGC_SHIFT 30
#define PCC0_PCC_TSI0_CGC_WIDTH 1
#define PCC0_PCC_TSI0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_TSI0_CGC_SHIFT))&PCC0_PCC_TSI0_CGC_MASK)
#define PCC0_PCC_TSI0_PR_MASK 0x80000000u
#define PCC0_PCC_TSI0_PR_SHIFT 31
#define PCC0_PCC_TSI0_PR_WIDTH 1
#define PCC0_PCC_TSI0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_TSI0_PR_SHIFT))&PCC0_PCC_TSI0_PR_MASK)
/* PCC_ADC0 Bit Fields */
#define PCC0_PCC_ADC0_PCS_MASK 0x7000000u
#define PCC0_PCC_ADC0_PCS_SHIFT 24
#define PCC0_PCC_ADC0_PCS_WIDTH 3
#define PCC0_PCC_ADC0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_ADC0_PCS_SHIFT))&PCC0_PCC_ADC0_PCS_MASK)
#define PCC0_PCC_ADC0_INUSE_MASK 0x20000000u
#define PCC0_PCC_ADC0_INUSE_SHIFT 29
#define PCC0_PCC_ADC0_INUSE_WIDTH 1
#define PCC0_PCC_ADC0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_ADC0_INUSE_SHIFT))&PCC0_PCC_ADC0_INUSE_MASK)
#define PCC0_PCC_ADC0_CGC_MASK 0x40000000u
#define PCC0_PCC_ADC0_CGC_SHIFT 30
#define PCC0_PCC_ADC0_CGC_WIDTH 1
#define PCC0_PCC_ADC0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_ADC0_CGC_SHIFT))&PCC0_PCC_ADC0_CGC_MASK)
#define PCC0_PCC_ADC0_PR_MASK 0x80000000u
#define PCC0_PCC_ADC0_PR_SHIFT 31
#define PCC0_PCC_ADC0_PR_WIDTH 1
#define PCC0_PCC_ADC0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_ADC0_PR_SHIFT))&PCC0_PCC_ADC0_PR_MASK)
/* PCC_DAC0 Bit Fields */
#define PCC0_PCC_DAC0_INUSE_MASK 0x20000000u
#define PCC0_PCC_DAC0_INUSE_SHIFT 29
#define PCC0_PCC_DAC0_INUSE_WIDTH 1
#define PCC0_PCC_DAC0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DAC0_INUSE_SHIFT))&PCC0_PCC_DAC0_INUSE_MASK)
#define PCC0_PCC_DAC0_CGC_MASK 0x40000000u
#define PCC0_PCC_DAC0_CGC_SHIFT 30
#define PCC0_PCC_DAC0_CGC_WIDTH 1
#define PCC0_PCC_DAC0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DAC0_CGC_SHIFT))&PCC0_PCC_DAC0_CGC_MASK)
#define PCC0_PCC_DAC0_PR_MASK 0x80000000u
#define PCC0_PCC_DAC0_PR_SHIFT 31
#define PCC0_PCC_DAC0_PR_WIDTH 1
#define PCC0_PCC_DAC0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_DAC0_PR_SHIFT))&PCC0_PCC_DAC0_PR_MASK)
/* PCC_CMP0 Bit Fields */
#define PCC0_PCC_CMP0_INUSE_MASK 0x20000000u
#define PCC0_PCC_CMP0_INUSE_SHIFT 29
#define PCC0_PCC_CMP0_INUSE_WIDTH 1
#define PCC0_PCC_CMP0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_CMP0_INUSE_SHIFT))&PCC0_PCC_CMP0_INUSE_MASK)
#define PCC0_PCC_CMP0_CGC_MASK 0x40000000u
#define PCC0_PCC_CMP0_CGC_SHIFT 30
#define PCC0_PCC_CMP0_CGC_WIDTH 1
#define PCC0_PCC_CMP0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_CMP0_CGC_SHIFT))&PCC0_PCC_CMP0_CGC_MASK)
#define PCC0_PCC_CMP0_PR_MASK 0x80000000u
#define PCC0_PCC_CMP0_PR_SHIFT 31
#define PCC0_PCC_CMP0_PR_WIDTH 1
#define PCC0_PCC_CMP0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_CMP0_PR_SHIFT))&PCC0_PCC_CMP0_PR_MASK)
/* PCC_VREF Bit Fields */
#define PCC0_PCC_VREF_INUSE_MASK 0x20000000u
#define PCC0_PCC_VREF_INUSE_SHIFT 29
#define PCC0_PCC_VREF_INUSE_WIDTH 1
#define PCC0_PCC_VREF_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_VREF_INUSE_SHIFT))&PCC0_PCC_VREF_INUSE_MASK)
#define PCC0_PCC_VREF_CGC_MASK 0x40000000u
#define PCC0_PCC_VREF_CGC_SHIFT 30
#define PCC0_PCC_VREF_CGC_WIDTH 1
#define PCC0_PCC_VREF_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_VREF_CGC_SHIFT))&PCC0_PCC_VREF_CGC_MASK)
#define PCC0_PCC_VREF_PR_MASK 0x80000000u
#define PCC0_PCC_VREF_PR_SHIFT 31
#define PCC0_PCC_VREF_PR_WIDTH 1
#define PCC0_PCC_VREF_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_VREF_PR_SHIFT))&PCC0_PCC_VREF_PR_MASK)
/* PCC_CRC Bit Fields */
#define PCC0_PCC_CRC_INUSE_MASK 0x20000000u
#define PCC0_PCC_CRC_INUSE_SHIFT 29
#define PCC0_PCC_CRC_INUSE_WIDTH 1
#define PCC0_PCC_CRC_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_CRC_INUSE_SHIFT))&PCC0_PCC_CRC_INUSE_MASK)
#define PCC0_PCC_CRC_CGC_MASK 0x40000000u
#define PCC0_PCC_CRC_CGC_SHIFT 30
#define PCC0_PCC_CRC_CGC_WIDTH 1
#define PCC0_PCC_CRC_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_CRC_CGC_SHIFT))&PCC0_PCC_CRC_CGC_MASK)
#define PCC0_PCC_CRC_PR_MASK 0x80000000u
#define PCC0_PCC_CRC_PR_SHIFT 31
#define PCC0_PCC_CRC_PR_WIDTH 1
#define PCC0_PCC_CRC_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC0_PCC_CRC_PR_SHIFT))&PCC0_PCC_CRC_PR_MASK)
/*!
* @}
*/ /* end of group PCC0_Register_Masks */
/* PCC0 - Peripheral instance base addresses */
/** Peripheral PCC0 base address */
#define PCC0_BASE (0x4007A000u)
/** Peripheral PCC0 base pointer */
#define PCC0 ((PCC0_Type *)PCC0_BASE)
#define PCC0_BASE_PTR (PCC0)
/** Array initializer of PCC0 peripheral base addresses */
#define PCC0_BASE_ADDRS { PCC0_BASE }
/** Array initializer of PCC0 peripheral base pointers */
#define PCC0_BASE_PTRS { PCC0 }
/* ----------------------------------------------------------------------------
-- PCC0 - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC0_Register_Accessor_Macros PCC0 - Register accessor macros
* @{
*/
/* PCC0 - Register instance definitions */
/* PCC0 */
#define PCC_PCC_DMA0 PCC0_PCC_DMA0_REG(PCC0)
#define PCC_PCC_FLASH PCC0_PCC_FLASH_REG(PCC0)
#define PCC_PCC_DMAMUX0 PCC0_PCC_DMAMUX0_REG(PCC0)
#define PCC_PCC_INTMUX0 PCC0_PCC_INTMUX0_REG(PCC0)
#define PCC_PCC_TPM2 PCC0_PCC_TPM2_REG(PCC0)
#define PCC_PCC_LPIT0 PCC0_PCC_LPIT0_REG(PCC0)
#define PCC_PCC_LPTMR0 PCC0_PCC_LPTMR0_REG(PCC0)
#define PCC_PCC_RTC PCC0_PCC_RTC_REG(PCC0)
#define PCC_PCC_LPSPI2 PCC0_PCC_LPSPI2_REG(PCC0)
#define PCC_PCC_LPI2C2 PCC0_PCC_LPI2C2_REG(PCC0)
#define PCC_PCC_LPUART2 PCC0_PCC_LPUART2_REG(PCC0)
#define PCC_PCC_SAI0 PCC0_PCC_SAI0_REG(PCC0)
#define PCC_PCC_EVMSIM0 PCC0_PCC_EVMSIM0_REG(PCC0)
#define PCC_PCC_USB0FS PCC0_PCC_USB0FS_REG(PCC0)
#define PCC_PCC_PORTA PCC0_PCC_PORTA_REG(PCC0)
#define PCC_PCC_PORTB PCC0_PCC_PORTB_REG(PCC0)
#define PCC_PCC_PORTC PCC0_PCC_PORTC_REG(PCC0)
#define PCC_PCC_PORTD PCC0_PCC_PORTD_REG(PCC0)
#define PCC_PCC_PORTE PCC0_PCC_PORTE_REG(PCC0)
#define PCC_PCC_TSI0 PCC0_PCC_TSI0_REG(PCC0)
#define PCC_PCC_ADC0 PCC0_PCC_ADC0_REG(PCC0)
#define PCC_PCC_DAC0 PCC0_PCC_DAC0_REG(PCC0)
#define PCC_PCC_CMP0 PCC0_PCC_CMP0_REG(PCC0)
#define PCC_PCC_VREF PCC0_PCC_VREF_REG(PCC0)
#define PCC_PCC_CRC PCC0_PCC_CRC_REG(PCC0)
/*!
* @}
*/ /* end of group PCC0_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group PCC0_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PCC1 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC1_Peripheral_Access_Layer PCC1 Peripheral Access Layer
* @{
*/
/** PCC1 - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[148];
__IO uint32_t PCC_TRNG; /**< PCC_TRNG Register, offset: 0x94 */
uint8_t RESERVED_1[24];
__IO uint32_t PCC_TPM0; /**< PCC_TPM0 Register, offset: 0xB0 */
__IO uint32_t PCC_TPM1; /**< PCC_TPM1 Register, offset: 0xB4 */
uint8_t RESERVED_2[28];
__IO uint32_t PCC_LPTMR1; /**< PCC_LPTMR1 Register, offset: 0xD4 */
uint8_t RESERVED_3[24];
__IO uint32_t PCC_LPSPI0; /**< PCC_LPSPI0 Register, offset: 0xF0 */
__IO uint32_t PCC_LPSPI1; /**< PCC_LPSPI1 Register, offset: 0xF4 */
uint8_t RESERVED_4[8];
__IO uint32_t PCC_LPI2C0; /**< PCC_LPI2C0 Register, offset: 0x100 */
__IO uint32_t PCC_LPI2C1; /**< PCC_LPI2C1 Register, offset: 0x104 */
uint8_t RESERVED_5[8];
__IO uint32_t PCC_LPUART0; /**< PCC_LPUART0 Register, offset: 0x110 */
__IO uint32_t PCC_LPUART1; /**< PCC_LPUART1 Register, offset: 0x114 */
uint8_t RESERVED_6[16];
__IO uint32_t PCC_FLEXIO0; /**< PCC_FLEXIO0 Register, offset: 0x128 */
uint8_t RESERVED_7[144];
__IO uint32_t PCC_CMP1; /**< PCC_CMP1 Register, offset: 0x1BC */
} PCC1_Type, *PCC1_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PCC1 - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC1_Register_Accessor_Macros PCC1 - Register accessor macros
* @{
*/
/* PCC1 - Register accessors */
#define PCC1_PCC_TRNG_REG(base) ((base)->PCC_TRNG)
#define PCC1_PCC_TPM0_REG(base) ((base)->PCC_TPM0)
#define PCC1_PCC_TPM1_REG(base) ((base)->PCC_TPM1)
#define PCC1_PCC_LPTMR1_REG(base) ((base)->PCC_LPTMR1)
#define PCC1_PCC_LPSPI0_REG(base) ((base)->PCC_LPSPI0)
#define PCC1_PCC_LPSPI1_REG(base) ((base)->PCC_LPSPI1)
#define PCC1_PCC_LPI2C0_REG(base) ((base)->PCC_LPI2C0)
#define PCC1_PCC_LPI2C1_REG(base) ((base)->PCC_LPI2C1)
#define PCC1_PCC_LPUART0_REG(base) ((base)->PCC_LPUART0)
#define PCC1_PCC_LPUART1_REG(base) ((base)->PCC_LPUART1)
#define PCC1_PCC_FLEXIO0_REG(base) ((base)->PCC_FLEXIO0)
#define PCC1_PCC_CMP1_REG(base) ((base)->PCC_CMP1)
/*!
* @}
*/ /* end of group PCC1_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PCC1 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC1_Register_Masks PCC1 Register Masks
* @{
*/
/* PCC_TRNG Bit Fields */
#define PCC1_PCC_TRNG_INUSE_MASK 0x20000000u
#define PCC1_PCC_TRNG_INUSE_SHIFT 29
#define PCC1_PCC_TRNG_INUSE_WIDTH 1
#define PCC1_PCC_TRNG_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TRNG_INUSE_SHIFT))&PCC1_PCC_TRNG_INUSE_MASK)
#define PCC1_PCC_TRNG_CGC_MASK 0x40000000u
#define PCC1_PCC_TRNG_CGC_SHIFT 30
#define PCC1_PCC_TRNG_CGC_WIDTH 1
#define PCC1_PCC_TRNG_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TRNG_CGC_SHIFT))&PCC1_PCC_TRNG_CGC_MASK)
#define PCC1_PCC_TRNG_PR_MASK 0x80000000u
#define PCC1_PCC_TRNG_PR_SHIFT 31
#define PCC1_PCC_TRNG_PR_WIDTH 1
#define PCC1_PCC_TRNG_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TRNG_PR_SHIFT))&PCC1_PCC_TRNG_PR_MASK)
/* PCC_TPM0 Bit Fields */
#define PCC1_PCC_TPM0_PCS_MASK 0x7000000u
#define PCC1_PCC_TPM0_PCS_SHIFT 24
#define PCC1_PCC_TPM0_PCS_WIDTH 3
#define PCC1_PCC_TPM0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TPM0_PCS_SHIFT))&PCC1_PCC_TPM0_PCS_MASK)
#define PCC1_PCC_TPM0_INUSE_MASK 0x20000000u
#define PCC1_PCC_TPM0_INUSE_SHIFT 29
#define PCC1_PCC_TPM0_INUSE_WIDTH 1
#define PCC1_PCC_TPM0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TPM0_INUSE_SHIFT))&PCC1_PCC_TPM0_INUSE_MASK)
#define PCC1_PCC_TPM0_CGC_MASK 0x40000000u
#define PCC1_PCC_TPM0_CGC_SHIFT 30
#define PCC1_PCC_TPM0_CGC_WIDTH 1
#define PCC1_PCC_TPM0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TPM0_CGC_SHIFT))&PCC1_PCC_TPM0_CGC_MASK)
#define PCC1_PCC_TPM0_PR_MASK 0x80000000u
#define PCC1_PCC_TPM0_PR_SHIFT 31
#define PCC1_PCC_TPM0_PR_WIDTH 1
#define PCC1_PCC_TPM0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TPM0_PR_SHIFT))&PCC1_PCC_TPM0_PR_MASK)
/* PCC_TPM1 Bit Fields */
#define PCC1_PCC_TPM1_PCS_MASK 0x7000000u
#define PCC1_PCC_TPM1_PCS_SHIFT 24
#define PCC1_PCC_TPM1_PCS_WIDTH 3
#define PCC1_PCC_TPM1_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TPM1_PCS_SHIFT))&PCC1_PCC_TPM1_PCS_MASK)
#define PCC1_PCC_TPM1_INUSE_MASK 0x20000000u
#define PCC1_PCC_TPM1_INUSE_SHIFT 29
#define PCC1_PCC_TPM1_INUSE_WIDTH 1
#define PCC1_PCC_TPM1_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TPM1_INUSE_SHIFT))&PCC1_PCC_TPM1_INUSE_MASK)
#define PCC1_PCC_TPM1_CGC_MASK 0x40000000u
#define PCC1_PCC_TPM1_CGC_SHIFT 30
#define PCC1_PCC_TPM1_CGC_WIDTH 1
#define PCC1_PCC_TPM1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TPM1_CGC_SHIFT))&PCC1_PCC_TPM1_CGC_MASK)
#define PCC1_PCC_TPM1_PR_MASK 0x80000000u
#define PCC1_PCC_TPM1_PR_SHIFT 31
#define PCC1_PCC_TPM1_PR_WIDTH 1
#define PCC1_PCC_TPM1_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_TPM1_PR_SHIFT))&PCC1_PCC_TPM1_PR_MASK)
/* PCC_LPTMR1 Bit Fields */
#define PCC1_PCC_LPTMR1_INUSE_MASK 0x20000000u
#define PCC1_PCC_LPTMR1_INUSE_SHIFT 29
#define PCC1_PCC_LPTMR1_INUSE_WIDTH 1
#define PCC1_PCC_LPTMR1_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPTMR1_INUSE_SHIFT))&PCC1_PCC_LPTMR1_INUSE_MASK)
#define PCC1_PCC_LPTMR1_CGC_MASK 0x40000000u
#define PCC1_PCC_LPTMR1_CGC_SHIFT 30
#define PCC1_PCC_LPTMR1_CGC_WIDTH 1
#define PCC1_PCC_LPTMR1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPTMR1_CGC_SHIFT))&PCC1_PCC_LPTMR1_CGC_MASK)
#define PCC1_PCC_LPTMR1_PR_MASK 0x80000000u
#define PCC1_PCC_LPTMR1_PR_SHIFT 31
#define PCC1_PCC_LPTMR1_PR_WIDTH 1
#define PCC1_PCC_LPTMR1_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPTMR1_PR_SHIFT))&PCC1_PCC_LPTMR1_PR_MASK)
/* PCC_LPSPI0 Bit Fields */
#define PCC1_PCC_LPSPI0_PCS_MASK 0x7000000u
#define PCC1_PCC_LPSPI0_PCS_SHIFT 24
#define PCC1_PCC_LPSPI0_PCS_WIDTH 3
#define PCC1_PCC_LPSPI0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPSPI0_PCS_SHIFT))&PCC1_PCC_LPSPI0_PCS_MASK)
#define PCC1_PCC_LPSPI0_INUSE_MASK 0x20000000u
#define PCC1_PCC_LPSPI0_INUSE_SHIFT 29
#define PCC1_PCC_LPSPI0_INUSE_WIDTH 1
#define PCC1_PCC_LPSPI0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPSPI0_INUSE_SHIFT))&PCC1_PCC_LPSPI0_INUSE_MASK)
#define PCC1_PCC_LPSPI0_CGC_MASK 0x40000000u
#define PCC1_PCC_LPSPI0_CGC_SHIFT 30
#define PCC1_PCC_LPSPI0_CGC_WIDTH 1
#define PCC1_PCC_LPSPI0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPSPI0_CGC_SHIFT))&PCC1_PCC_LPSPI0_CGC_MASK)
#define PCC1_PCC_LPSPI0_PR_MASK 0x80000000u
#define PCC1_PCC_LPSPI0_PR_SHIFT 31
#define PCC1_PCC_LPSPI0_PR_WIDTH 1
#define PCC1_PCC_LPSPI0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPSPI0_PR_SHIFT))&PCC1_PCC_LPSPI0_PR_MASK)
/* PCC_LPSPI1 Bit Fields */
#define PCC1_PCC_LPSPI1_PCS_MASK 0x7000000u
#define PCC1_PCC_LPSPI1_PCS_SHIFT 24
#define PCC1_PCC_LPSPI1_PCS_WIDTH 3
#define PCC1_PCC_LPSPI1_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPSPI1_PCS_SHIFT))&PCC1_PCC_LPSPI1_PCS_MASK)
#define PCC1_PCC_LPSPI1_INUSE_MASK 0x20000000u
#define PCC1_PCC_LPSPI1_INUSE_SHIFT 29
#define PCC1_PCC_LPSPI1_INUSE_WIDTH 1
#define PCC1_PCC_LPSPI1_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPSPI1_INUSE_SHIFT))&PCC1_PCC_LPSPI1_INUSE_MASK)
#define PCC1_PCC_LPSPI1_CGC_MASK 0x40000000u
#define PCC1_PCC_LPSPI1_CGC_SHIFT 30
#define PCC1_PCC_LPSPI1_CGC_WIDTH 1
#define PCC1_PCC_LPSPI1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPSPI1_CGC_SHIFT))&PCC1_PCC_LPSPI1_CGC_MASK)
#define PCC1_PCC_LPSPI1_PR_MASK 0x80000000u
#define PCC1_PCC_LPSPI1_PR_SHIFT 31
#define PCC1_PCC_LPSPI1_PR_WIDTH 1
#define PCC1_PCC_LPSPI1_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPSPI1_PR_SHIFT))&PCC1_PCC_LPSPI1_PR_MASK)
/* PCC_LPI2C0 Bit Fields */
#define PCC1_PCC_LPI2C0_PCS_MASK 0x7000000u
#define PCC1_PCC_LPI2C0_PCS_SHIFT 24
#define PCC1_PCC_LPI2C0_PCS_WIDTH 3
#define PCC1_PCC_LPI2C0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPI2C0_PCS_SHIFT))&PCC1_PCC_LPI2C0_PCS_MASK)
#define PCC1_PCC_LPI2C0_INUSE_MASK 0x20000000u
#define PCC1_PCC_LPI2C0_INUSE_SHIFT 29
#define PCC1_PCC_LPI2C0_INUSE_WIDTH 1
#define PCC1_PCC_LPI2C0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPI2C0_INUSE_SHIFT))&PCC1_PCC_LPI2C0_INUSE_MASK)
#define PCC1_PCC_LPI2C0_CGC_MASK 0x40000000u
#define PCC1_PCC_LPI2C0_CGC_SHIFT 30
#define PCC1_PCC_LPI2C0_CGC_WIDTH 1
#define PCC1_PCC_LPI2C0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPI2C0_CGC_SHIFT))&PCC1_PCC_LPI2C0_CGC_MASK)
#define PCC1_PCC_LPI2C0_PR_MASK 0x80000000u
#define PCC1_PCC_LPI2C0_PR_SHIFT 31
#define PCC1_PCC_LPI2C0_PR_WIDTH 1
#define PCC1_PCC_LPI2C0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPI2C0_PR_SHIFT))&PCC1_PCC_LPI2C0_PR_MASK)
/* PCC_LPI2C1 Bit Fields */
#define PCC1_PCC_LPI2C1_PCS_MASK 0x7000000u
#define PCC1_PCC_LPI2C1_PCS_SHIFT 24
#define PCC1_PCC_LPI2C1_PCS_WIDTH 3
#define PCC1_PCC_LPI2C1_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPI2C1_PCS_SHIFT))&PCC1_PCC_LPI2C1_PCS_MASK)
#define PCC1_PCC_LPI2C1_INUSE_MASK 0x20000000u
#define PCC1_PCC_LPI2C1_INUSE_SHIFT 29
#define PCC1_PCC_LPI2C1_INUSE_WIDTH 1
#define PCC1_PCC_LPI2C1_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPI2C1_INUSE_SHIFT))&PCC1_PCC_LPI2C1_INUSE_MASK)
#define PCC1_PCC_LPI2C1_CGC_MASK 0x40000000u
#define PCC1_PCC_LPI2C1_CGC_SHIFT 30
#define PCC1_PCC_LPI2C1_CGC_WIDTH 1
#define PCC1_PCC_LPI2C1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPI2C1_CGC_SHIFT))&PCC1_PCC_LPI2C1_CGC_MASK)
#define PCC1_PCC_LPI2C1_PR_MASK 0x80000000u
#define PCC1_PCC_LPI2C1_PR_SHIFT 31
#define PCC1_PCC_LPI2C1_PR_WIDTH 1
#define PCC1_PCC_LPI2C1_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPI2C1_PR_SHIFT))&PCC1_PCC_LPI2C1_PR_MASK)
/* PCC_LPUART0 Bit Fields */
#define PCC1_PCC_LPUART0_PCS_MASK 0x7000000u
#define PCC1_PCC_LPUART0_PCS_SHIFT 24
#define PCC1_PCC_LPUART0_PCS_WIDTH 3
#define PCC1_PCC_LPUART0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPUART0_PCS_SHIFT))&PCC1_PCC_LPUART0_PCS_MASK)
#define PCC1_PCC_LPUART0_INUSE_MASK 0x20000000u
#define PCC1_PCC_LPUART0_INUSE_SHIFT 29
#define PCC1_PCC_LPUART0_INUSE_WIDTH 1
#define PCC1_PCC_LPUART0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPUART0_INUSE_SHIFT))&PCC1_PCC_LPUART0_INUSE_MASK)
#define PCC1_PCC_LPUART0_CGC_MASK 0x40000000u
#define PCC1_PCC_LPUART0_CGC_SHIFT 30
#define PCC1_PCC_LPUART0_CGC_WIDTH 1
#define PCC1_PCC_LPUART0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPUART0_CGC_SHIFT))&PCC1_PCC_LPUART0_CGC_MASK)
#define PCC1_PCC_LPUART0_PR_MASK 0x80000000u
#define PCC1_PCC_LPUART0_PR_SHIFT 31
#define PCC1_PCC_LPUART0_PR_WIDTH 1
#define PCC1_PCC_LPUART0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPUART0_PR_SHIFT))&PCC1_PCC_LPUART0_PR_MASK)
/* PCC_LPUART1 Bit Fields */
#define PCC1_PCC_LPUART1_PCS_MASK 0x7000000u
#define PCC1_PCC_LPUART1_PCS_SHIFT 24
#define PCC1_PCC_LPUART1_PCS_WIDTH 3
#define PCC1_PCC_LPUART1_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPUART1_PCS_SHIFT))&PCC1_PCC_LPUART1_PCS_MASK)
#define PCC1_PCC_LPUART1_INUSE_MASK 0x20000000u
#define PCC1_PCC_LPUART1_INUSE_SHIFT 29
#define PCC1_PCC_LPUART1_INUSE_WIDTH 1
#define PCC1_PCC_LPUART1_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPUART1_INUSE_SHIFT))&PCC1_PCC_LPUART1_INUSE_MASK)
#define PCC1_PCC_LPUART1_CGC_MASK 0x40000000u
#define PCC1_PCC_LPUART1_CGC_SHIFT 30
#define PCC1_PCC_LPUART1_CGC_WIDTH 1
#define PCC1_PCC_LPUART1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPUART1_CGC_SHIFT))&PCC1_PCC_LPUART1_CGC_MASK)
#define PCC1_PCC_LPUART1_PR_MASK 0x80000000u
#define PCC1_PCC_LPUART1_PR_SHIFT 31
#define PCC1_PCC_LPUART1_PR_WIDTH 1
#define PCC1_PCC_LPUART1_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_LPUART1_PR_SHIFT))&PCC1_PCC_LPUART1_PR_MASK)
/* PCC_FLEXIO0 Bit Fields */
#define PCC1_PCC_FLEXIO0_PCS_MASK 0x7000000u
#define PCC1_PCC_FLEXIO0_PCS_SHIFT 24
#define PCC1_PCC_FLEXIO0_PCS_WIDTH 3
#define PCC1_PCC_FLEXIO0_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_FLEXIO0_PCS_SHIFT))&PCC1_PCC_FLEXIO0_PCS_MASK)
#define PCC1_PCC_FLEXIO0_INUSE_MASK 0x20000000u
#define PCC1_PCC_FLEXIO0_INUSE_SHIFT 29
#define PCC1_PCC_FLEXIO0_INUSE_WIDTH 1
#define PCC1_PCC_FLEXIO0_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_FLEXIO0_INUSE_SHIFT))&PCC1_PCC_FLEXIO0_INUSE_MASK)
#define PCC1_PCC_FLEXIO0_CGC_MASK 0x40000000u
#define PCC1_PCC_FLEXIO0_CGC_SHIFT 30
#define PCC1_PCC_FLEXIO0_CGC_WIDTH 1
#define PCC1_PCC_FLEXIO0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_FLEXIO0_CGC_SHIFT))&PCC1_PCC_FLEXIO0_CGC_MASK)
#define PCC1_PCC_FLEXIO0_PR_MASK 0x80000000u
#define PCC1_PCC_FLEXIO0_PR_SHIFT 31
#define PCC1_PCC_FLEXIO0_PR_WIDTH 1
#define PCC1_PCC_FLEXIO0_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_FLEXIO0_PR_SHIFT))&PCC1_PCC_FLEXIO0_PR_MASK)
/* PCC_CMP1 Bit Fields */
#define PCC1_PCC_CMP1_INUSE_MASK 0x20000000u
#define PCC1_PCC_CMP1_INUSE_SHIFT 29
#define PCC1_PCC_CMP1_INUSE_WIDTH 1
#define PCC1_PCC_CMP1_INUSE(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_CMP1_INUSE_SHIFT))&PCC1_PCC_CMP1_INUSE_MASK)
#define PCC1_PCC_CMP1_CGC_MASK 0x40000000u
#define PCC1_PCC_CMP1_CGC_SHIFT 30
#define PCC1_PCC_CMP1_CGC_WIDTH 1
#define PCC1_PCC_CMP1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_CMP1_CGC_SHIFT))&PCC1_PCC_CMP1_CGC_MASK)
#define PCC1_PCC_CMP1_PR_MASK 0x80000000u
#define PCC1_PCC_CMP1_PR_SHIFT 31
#define PCC1_PCC_CMP1_PR_WIDTH 1
#define PCC1_PCC_CMP1_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC1_PCC_CMP1_PR_SHIFT))&PCC1_PCC_CMP1_PR_MASK)
/*!
* @}
*/ /* end of group PCC1_Register_Masks */
/* PCC1 - Peripheral instance base addresses */
/** Peripheral PCC1 base address */
#define PCC1_BASE (0x400FA000u)
/** Peripheral PCC1 base pointer */
#define PCC1 ((PCC1_Type *)PCC1_BASE)
#define PCC1_BASE_PTR (PCC1)
/** Array initializer of PCC1 peripheral base addresses */
#define PCC1_BASE_ADDRS { PCC1_BASE }
/** Array initializer of PCC1 peripheral base pointers */
#define PCC1_BASE_PTRS { PCC1 }
/* ----------------------------------------------------------------------------
-- PCC1 - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC1_Register_Accessor_Macros PCC1 - Register accessor macros
* @{
*/
/* PCC1 - Register instance definitions */
/* PCC1 */
#define PCC_PCC_TRNG PCC1_PCC_TRNG_REG(PCC1)
#define PCC_PCC_TPM0 PCC1_PCC_TPM0_REG(PCC1)
#define PCC_PCC_TPM1 PCC1_PCC_TPM1_REG(PCC1)
#define PCC_PCC_LPTMR1 PCC1_PCC_LPTMR1_REG(PCC1)
#define PCC_PCC_LPSPI0 PCC1_PCC_LPSPI0_REG(PCC1)
#define PCC_PCC_LPSPI1 PCC1_PCC_LPSPI1_REG(PCC1)
#define PCC_PCC_LPI2C0 PCC1_PCC_LPI2C0_REG(PCC1)
#define PCC_PCC_LPI2C1 PCC1_PCC_LPI2C1_REG(PCC1)
#define PCC_PCC_LPUART0 PCC1_PCC_LPUART0_REG(PCC1)
#define PCC_PCC_LPUART1 PCC1_PCC_LPUART1_REG(PCC1)
#define PCC_PCC_FLEXIO0 PCC1_PCC_FLEXIO0_REG(PCC1)
#define PCC_PCC_CMP1 PCC1_PCC_CMP1_REG(PCC1)
/*!
* @}
*/ /* end of group PCC1_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group PCC1_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
* @{
*/
/** PMC - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter register, offset: 0x4 */
__IO uint32_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x8 */
__IO uint32_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0xC */
__IO uint32_t REGSC; /**< Regulator Status And Control register, offset: 0x10 */
uint8_t RESERVED_0[32];
__IO uint32_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0x34 */
} PMC_Type, *PMC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
* @{
*/
/* PMC - Register accessors */
#define PMC_VERID_REG(base) ((base)->VERID)
#define PMC_PARAM_REG(base) ((base)->PARAM)
#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
#define PMC_REGSC_REG(base) ((base)->REGSC)
#define PMC_HVDSC1_REG(base) ((base)->HVDSC1)
/*!
* @}
*/ /* end of group PMC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Masks PMC Register Masks
* @{
*/
/* VERID Bit Fields */
#define PMC_VERID_FEATURE_MASK 0xFFFFu
#define PMC_VERID_FEATURE_SHIFT 0
#define PMC_VERID_FEATURE_WIDTH 16
#define PMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<PMC_VERID_FEATURE_SHIFT))&PMC_VERID_FEATURE_MASK)
#define PMC_VERID_MINOR_MASK 0xFF0000u
#define PMC_VERID_MINOR_SHIFT 16
#define PMC_VERID_MINOR_WIDTH 8
#define PMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<PMC_VERID_MINOR_SHIFT))&PMC_VERID_MINOR_MASK)
#define PMC_VERID_MAJOR_MASK 0xFF000000u
#define PMC_VERID_MAJOR_SHIFT 24
#define PMC_VERID_MAJOR_WIDTH 8
#define PMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<PMC_VERID_MAJOR_SHIFT))&PMC_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define PMC_PARAM_VLPOE_MASK 0x1u
#define PMC_PARAM_VLPOE_SHIFT 0
#define PMC_PARAM_VLPOE_WIDTH 1
#define PMC_PARAM_VLPOE(x) (((uint32_t)(((uint32_t)(x))<<PMC_PARAM_VLPOE_SHIFT))&PMC_PARAM_VLPOE_MASK)
#define PMC_PARAM_HVDE_MASK 0x2u
#define PMC_PARAM_HVDE_SHIFT 1
#define PMC_PARAM_HVDE_WIDTH 1
#define PMC_PARAM_HVDE(x) (((uint32_t)(((uint32_t)(x))<<PMC_PARAM_HVDE_SHIFT))&PMC_PARAM_HVDE_MASK)
/* LVDSC1 Bit Fields */
#define PMC_LVDSC1_LVDV_MASK 0x3u
#define PMC_LVDSC1_LVDV_SHIFT 0
#define PMC_LVDSC1_LVDV_WIDTH 2
#define PMC_LVDSC1_LVDV(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
#define PMC_LVDSC1_LVDRE_MASK 0x10u
#define PMC_LVDSC1_LVDRE_SHIFT 4
#define PMC_LVDSC1_LVDRE_WIDTH 1
#define PMC_LVDSC1_LVDRE(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
#define PMC_LVDSC1_LVDIE_MASK 0x20u
#define PMC_LVDSC1_LVDIE_SHIFT 5
#define PMC_LVDSC1_LVDIE_WIDTH 1
#define PMC_LVDSC1_LVDIE(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
#define PMC_LVDSC1_LVDACK_MASK 0x40u
#define PMC_LVDSC1_LVDACK_SHIFT 6
#define PMC_LVDSC1_LVDACK_WIDTH 1
#define PMC_LVDSC1_LVDACK(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
#define PMC_LVDSC1_LVDF_MASK 0x80u
#define PMC_LVDSC1_LVDF_SHIFT 7
#define PMC_LVDSC1_LVDF_WIDTH 1
#define PMC_LVDSC1_LVDF(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
/* LVDSC2 Bit Fields */
#define PMC_LVDSC2_LVWV_MASK 0x3u
#define PMC_LVDSC2_LVWV_SHIFT 0
#define PMC_LVDSC2_LVWV_WIDTH 2
#define PMC_LVDSC2_LVWV(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
#define PMC_LVDSC2_LVWIE_MASK 0x20u
#define PMC_LVDSC2_LVWIE_SHIFT 5
#define PMC_LVDSC2_LVWIE_WIDTH 1
#define PMC_LVDSC2_LVWIE(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
#define PMC_LVDSC2_LVWACK_MASK 0x40u
#define PMC_LVDSC2_LVWACK_SHIFT 6
#define PMC_LVDSC2_LVWACK_WIDTH 1
#define PMC_LVDSC2_LVWACK(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
#define PMC_LVDSC2_LVWF_MASK 0x80u
#define PMC_LVDSC2_LVWF_SHIFT 7
#define PMC_LVDSC2_LVWF_WIDTH 1
#define PMC_LVDSC2_LVWF(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
/* REGSC Bit Fields */
#define PMC_REGSC_BGBE_MASK 0x1u
#define PMC_REGSC_BGBE_SHIFT 0
#define PMC_REGSC_BGBE_WIDTH 1
#define PMC_REGSC_BGBE(x) (((uint32_t)(((uint32_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
#define PMC_REGSC_REGONS_MASK 0x4u
#define PMC_REGSC_REGONS_SHIFT 2
#define PMC_REGSC_REGONS_WIDTH 1
#define PMC_REGSC_REGONS(x) (((uint32_t)(((uint32_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
#define PMC_REGSC_ACKISO_MASK 0x8u
#define PMC_REGSC_ACKISO_SHIFT 3
#define PMC_REGSC_ACKISO_WIDTH 1
#define PMC_REGSC_ACKISO(x) (((uint32_t)(((uint32_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
#define PMC_REGSC_BGEN_MASK 0x10u
#define PMC_REGSC_BGEN_SHIFT 4
#define PMC_REGSC_BGEN_WIDTH 1
#define PMC_REGSC_BGEN(x) (((uint32_t)(((uint32_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
#define PMC_REGSC_VLPO_MASK 0x40u
#define PMC_REGSC_VLPO_SHIFT 6
#define PMC_REGSC_VLPO_WIDTH 1
#define PMC_REGSC_VLPO(x) (((uint32_t)(((uint32_t)(x))<<PMC_REGSC_VLPO_SHIFT))&PMC_REGSC_VLPO_MASK)
/* HVDSC1 Bit Fields */
#define PMC_HVDSC1_HVDV_MASK 0x1u
#define PMC_HVDSC1_HVDV_SHIFT 0
#define PMC_HVDSC1_HVDV_WIDTH 1
#define PMC_HVDSC1_HVDV(x) (((uint32_t)(((uint32_t)(x))<<PMC_HVDSC1_HVDV_SHIFT))&PMC_HVDSC1_HVDV_MASK)
#define PMC_HVDSC1_HVDRE_MASK 0x10u
#define PMC_HVDSC1_HVDRE_SHIFT 4
#define PMC_HVDSC1_HVDRE_WIDTH 1
#define PMC_HVDSC1_HVDRE(x) (((uint32_t)(((uint32_t)(x))<<PMC_HVDSC1_HVDRE_SHIFT))&PMC_HVDSC1_HVDRE_MASK)
#define PMC_HVDSC1_HVDIE_MASK 0x20u
#define PMC_HVDSC1_HVDIE_SHIFT 5
#define PMC_HVDSC1_HVDIE_WIDTH 1
#define PMC_HVDSC1_HVDIE(x) (((uint32_t)(((uint32_t)(x))<<PMC_HVDSC1_HVDIE_SHIFT))&PMC_HVDSC1_HVDIE_MASK)
#define PMC_HVDSC1_HVDACK_MASK 0x40u
#define PMC_HVDSC1_HVDACK_SHIFT 6
#define PMC_HVDSC1_HVDACK_WIDTH 1
#define PMC_HVDSC1_HVDACK(x) (((uint32_t)(((uint32_t)(x))<<PMC_HVDSC1_HVDACK_SHIFT))&PMC_HVDSC1_HVDACK_MASK)
#define PMC_HVDSC1_HVDF_MASK 0x80u
#define PMC_HVDSC1_HVDF_SHIFT 7
#define PMC_HVDSC1_HVDF_WIDTH 1
#define PMC_HVDSC1_HVDF(x) (((uint32_t)(((uint32_t)(x))<<PMC_HVDSC1_HVDF_SHIFT))&PMC_HVDSC1_HVDF_MASK)
/*!
* @}
*/ /* end of group PMC_Register_Masks */
/* PMC - Peripheral instance base addresses */
/** Peripheral PMC base address */
#define PMC_BASE (0x4007D000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
#define PMC_BASE_PTR (PMC)
/** Array initializer of PMC peripheral base addresses */
#define PMC_BASE_ADDRS { PMC_BASE }
/** Array initializer of PMC peripheral base pointers */
#define PMC_BASE_PTRS { PMC }
/* ----------------------------------------------------------------------------
-- PMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
* @{
*/
/* PMC - Register instance definitions */
/* PMC */
#define PMC_VERID PMC_VERID_REG(PMC)
#define PMC_PARAM PMC_PARAM_REG(PMC)
#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
#define PMC_REGSC PMC_REGSC_REG(PMC)
#define PMC_HVDSC1 PMC_HVDSC1_REG(PMC)
/*!
* @}
*/ /* end of group PMC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PORT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
* @{
*/
/** PORT - Register Layout Typedef */
typedef struct {
__IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */
__O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */
uint8_t RESERVED_0[16];
__IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
__IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
__IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
__IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} PORT_Type, *PORT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PORT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
* @{
*/
/* PORT - Register accessors */
#define PORT_PCR_REG(base,index) ((base)->PCR[index])
#define PORT_PCR_COUNT 32
#define PORT_GPCLR_REG(base) ((base)->GPCLR)
#define PORT_GPCHR_REG(base) ((base)->GPCHR)
#define PORT_GICLR_REG(base) ((base)->GICLR)
#define PORT_GICHR_REG(base) ((base)->GICHR)
#define PORT_ISFR_REG(base) ((base)->ISFR)
#define PORT_DFER_REG(base) ((base)->DFER)
#define PORT_DFCR_REG(base) ((base)->DFCR)
#define PORT_DFWR_REG(base) ((base)->DFWR)
/*!
* @}
*/ /* end of group PORT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PORT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Masks PORT Register Masks
* @{
*/
/* PCR Bit Fields */
#define PORT_PCR_PS_MASK 0x1u
#define PORT_PCR_PS_SHIFT 0
#define PORT_PCR_PS_WIDTH 1
#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
#define PORT_PCR_PE_MASK 0x2u
#define PORT_PCR_PE_SHIFT 1
#define PORT_PCR_PE_WIDTH 1
#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
#define PORT_PCR_SRE_MASK 0x4u
#define PORT_PCR_SRE_SHIFT 2
#define PORT_PCR_SRE_WIDTH 1
#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
#define PORT_PCR_PFE_MASK 0x10u
#define PORT_PCR_PFE_SHIFT 4
#define PORT_PCR_PFE_WIDTH 1
#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
#define PORT_PCR_ODE_MASK 0x20u
#define PORT_PCR_ODE_SHIFT 5
#define PORT_PCR_ODE_WIDTH 1
#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
#define PORT_PCR_DSE_MASK 0x40u
#define PORT_PCR_DSE_SHIFT 6
#define PORT_PCR_DSE_WIDTH 1
#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
#define PORT_PCR_MUX_MASK 0x700u
#define PORT_PCR_MUX_SHIFT 8
#define PORT_PCR_MUX_WIDTH 3
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
#define PORT_PCR_IRQC_MASK 0xF0000u
#define PORT_PCR_IRQC_SHIFT 16
#define PORT_PCR_IRQC_WIDTH 4
#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
#define PORT_PCR_ISF_MASK 0x1000000u
#define PORT_PCR_ISF_SHIFT 24
#define PORT_PCR_ISF_WIDTH 1
#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
/* GPCLR Bit Fields */
#define PORT_GPCLR_GPWD_MASK 0xFFFFu
#define PORT_GPCLR_GPWD_SHIFT 0
#define PORT_GPCLR_GPWD_WIDTH 16
#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCLR_GPWE_SHIFT 16
#define PORT_GPCLR_GPWE_WIDTH 16
#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
/* GPCHR Bit Fields */
#define PORT_GPCHR_GPWD_MASK 0xFFFFu
#define PORT_GPCHR_GPWD_SHIFT 0
#define PORT_GPCHR_GPWD_WIDTH 16
#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCHR_GPWE_SHIFT 16
#define PORT_GPCHR_GPWE_WIDTH 16
#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
/* GICLR Bit Fields */
#define PORT_GICLR_GIWE_MASK 0xFFFFu
#define PORT_GICLR_GIWE_SHIFT 0
#define PORT_GICLR_GIWE_WIDTH 16
#define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWE_SHIFT))&PORT_GICLR_GIWE_MASK)
#define PORT_GICLR_GIWD_MASK 0xFFFF0000u
#define PORT_GICLR_GIWD_SHIFT 16
#define PORT_GICLR_GIWD_WIDTH 16
#define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWD_SHIFT))&PORT_GICLR_GIWD_MASK)
/* GICHR Bit Fields */
#define PORT_GICHR_GIWE_MASK 0xFFFFu
#define PORT_GICHR_GIWE_SHIFT 0
#define PORT_GICHR_GIWE_WIDTH 16
#define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWE_SHIFT))&PORT_GICHR_GIWE_MASK)
#define PORT_GICHR_GIWD_MASK 0xFFFF0000u
#define PORT_GICHR_GIWD_SHIFT 16
#define PORT_GICHR_GIWD_WIDTH 16
#define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWD_SHIFT))&PORT_GICHR_GIWD_MASK)
/* ISFR Bit Fields */
#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
#define PORT_ISFR_ISF_SHIFT 0
#define PORT_ISFR_ISF_WIDTH 32
#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
/* DFER Bit Fields */
#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
#define PORT_DFER_DFE_SHIFT 0
#define PORT_DFER_DFE_WIDTH 32
#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
/* DFCR Bit Fields */
#define PORT_DFCR_CS_MASK 0x1u
#define PORT_DFCR_CS_SHIFT 0
#define PORT_DFCR_CS_WIDTH 1
#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
/* DFWR Bit Fields */
#define PORT_DFWR_FILT_MASK 0x1Fu
#define PORT_DFWR_FILT_SHIFT 0
#define PORT_DFWR_FILT_WIDTH 5
#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
/*!
* @}
*/ /* end of group PORT_Register_Masks */
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base address */
#define PORTA_BASE (0x4005A000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
#define PORTA_BASE_PTR (PORTA)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4005B000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
#define PORTB_BASE_PTR (PORTB)
/** Peripheral PORTC base address */
#define PORTC_BASE (0x4005C000u)
/** Peripheral PORTC base pointer */
#define PORTC ((PORT_Type *)PORTC_BASE)
#define PORTC_BASE_PTR (PORTC)
/** Peripheral PORTD base address */
#define PORTD_BASE (0x4005D000u)
/** Peripheral PORTD base pointer */
#define PORTD ((PORT_Type *)PORTD_BASE)
#define PORTD_BASE_PTR (PORTD)
/** Peripheral PORTE base address */
#define PORTE_BASE (0x4005E000u)
/** Peripheral PORTE base pointer */
#define PORTE ((PORT_Type *)PORTE_BASE)
#define PORTE_BASE_PTR (PORTE)
/** Array initializer of PORT peripheral base addresses */
#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
/** Array initializer of PORT peripheral base pointers */
#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
/* ----------------------------------------------------------------------------
-- PORT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
* @{
*/
/* PORT - Register instance definitions */
/* PORTA */
#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
#define PORTA_GICLR PORT_GICLR_REG(PORTA)
#define PORTA_GICHR PORT_GICHR_REG(PORTA)
#define PORTA_ISFR PORT_ISFR_REG(PORTA)
#define PORTA_DFER PORT_DFER_REG(PORTA)
#define PORTA_DFCR PORT_DFCR_REG(PORTA)
#define PORTA_DFWR PORT_DFWR_REG(PORTA)
/* PORTB */
#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
#define PORTB_GICLR PORT_GICLR_REG(PORTB)
#define PORTB_GICHR PORT_GICHR_REG(PORTB)
#define PORTB_ISFR PORT_ISFR_REG(PORTB)
#define PORTB_DFER PORT_DFER_REG(PORTB)
#define PORTB_DFCR PORT_DFCR_REG(PORTB)
#define PORTB_DFWR PORT_DFWR_REG(PORTB)
/* PORTC */
#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
#define PORTC_GICLR PORT_GICLR_REG(PORTC)
#define PORTC_GICHR PORT_GICHR_REG(PORTC)
#define PORTC_ISFR PORT_ISFR_REG(PORTC)
#define PORTC_DFER PORT_DFER_REG(PORTC)
#define PORTC_DFCR PORT_DFCR_REG(PORTC)
#define PORTC_DFWR PORT_DFWR_REG(PORTC)
/* PORTD */
#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
#define PORTD_GICLR PORT_GICLR_REG(PORTD)
#define PORTD_GICHR PORT_GICHR_REG(PORTD)
#define PORTD_ISFR PORT_ISFR_REG(PORTD)
#define PORTD_DFER PORT_DFER_REG(PORTD)
#define PORTD_DFCR PORT_DFCR_REG(PORTD)
#define PORTD_DFWR PORT_DFWR_REG(PORTD)
/* PORTE */
#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
#define PORTE_GICLR PORT_GICLR_REG(PORTE)
#define PORTE_GICHR PORT_GICHR_REG(PORTE)
#define PORTE_ISFR PORT_ISFR_REG(PORTE)
#define PORTE_DFER PORT_DFER_REG(PORTE)
#define PORTE_DFCR PORT_DFCR_REG(PORTE)
#define PORTE_DFWR PORT_DFWR_REG(PORTE)
/* PORT - Register array accessors */
#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
/*!
* @}
*/ /* end of group PORT_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
* @{
*/
/** RCM - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__I uint32_t SRS; /**< System Reset Status Register, offset: 0x8 */
__IO uint32_t RPC; /**< Reset Pin Control register, offset: 0xC */
__IO uint32_t MR; /**< Mode Register, offset: 0x10 */
__IO uint32_t FM; /**< Force Mode Register, offset: 0x14 */
__IO uint32_t SSRS; /**< Sticky System Reset Status Register, offset: 0x18 */
__IO uint32_t SRIE; /**< System Reset Interrupt Enable Register, offset: 0x1C */
} RCM_Type, *RCM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
* @{
*/
/* RCM - Register accessors */
#define RCM_VERID_REG(base) ((base)->VERID)
#define RCM_PARAM_REG(base) ((base)->PARAM)
#define RCM_SRS_REG(base) ((base)->SRS)
#define RCM_RPC_REG(base) ((base)->RPC)
#define RCM_MR_REG(base) ((base)->MR)
#define RCM_FM_REG(base) ((base)->FM)
#define RCM_SSRS_REG(base) ((base)->SSRS)
#define RCM_SRIE_REG(base) ((base)->SRIE)
/*!
* @}
*/ /* end of group RCM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Masks RCM Register Masks
* @{
*/
/* VERID Bit Fields */
#define RCM_VERID_FEATURE_MASK 0xFFFFu
#define RCM_VERID_FEATURE_SHIFT 0
#define RCM_VERID_FEATURE_WIDTH 16
#define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_FEATURE_SHIFT))&RCM_VERID_FEATURE_MASK)
#define RCM_VERID_MINOR_MASK 0xFF0000u
#define RCM_VERID_MINOR_SHIFT 16
#define RCM_VERID_MINOR_WIDTH 8
#define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MINOR_SHIFT))&RCM_VERID_MINOR_MASK)
#define RCM_VERID_MAJOR_MASK 0xFF000000u
#define RCM_VERID_MAJOR_SHIFT 24
#define RCM_VERID_MAJOR_WIDTH 8
#define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MAJOR_SHIFT))&RCM_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define RCM_PARAM_RSTSRC_MASK 0xFFFFFFFFu
#define RCM_PARAM_RSTSRC_SHIFT 0
#define RCM_PARAM_RSTSRC_WIDTH 32
#define RCM_PARAM_RSTSRC(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_RSTSRC_SHIFT))&RCM_PARAM_RSTSRC_MASK)
/* SRS Bit Fields */
#define RCM_SRS_WAKEUP_MASK 0x1u
#define RCM_SRS_WAKEUP_SHIFT 0
#define RCM_SRS_WAKEUP_WIDTH 1
#define RCM_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_WAKEUP_SHIFT))&RCM_SRS_WAKEUP_MASK)
#define RCM_SRS_LVD_MASK 0x2u
#define RCM_SRS_LVD_SHIFT 1
#define RCM_SRS_LVD_WIDTH 1
#define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LVD_SHIFT))&RCM_SRS_LVD_MASK)
#define RCM_SRS_LOC_MASK 0x4u
#define RCM_SRS_LOC_SHIFT 2
#define RCM_SRS_LOC_WIDTH 1
#define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOC_SHIFT))&RCM_SRS_LOC_MASK)
#define RCM_SRS_LOL_MASK 0x8u
#define RCM_SRS_LOL_SHIFT 3
#define RCM_SRS_LOL_WIDTH 1
#define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOL_SHIFT))&RCM_SRS_LOL_MASK)
#define RCM_SRS_WDOG_MASK 0x20u
#define RCM_SRS_WDOG_SHIFT 5
#define RCM_SRS_WDOG_WIDTH 1
#define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_WDOG_SHIFT))&RCM_SRS_WDOG_MASK)
#define RCM_SRS_PIN_MASK 0x40u
#define RCM_SRS_PIN_SHIFT 6
#define RCM_SRS_PIN_WIDTH 1
#define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_PIN_SHIFT))&RCM_SRS_PIN_MASK)
#define RCM_SRS_POR_MASK 0x80u
#define RCM_SRS_POR_SHIFT 7
#define RCM_SRS_POR_WIDTH 1
#define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_POR_SHIFT))&RCM_SRS_POR_MASK)
#define RCM_SRS_LOCKUP_MASK 0x200u
#define RCM_SRS_LOCKUP_SHIFT 9
#define RCM_SRS_LOCKUP_WIDTH 1
#define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOCKUP_SHIFT))&RCM_SRS_LOCKUP_MASK)
#define RCM_SRS_SW_MASK 0x400u
#define RCM_SRS_SW_SHIFT 10
#define RCM_SRS_SW_WIDTH 1
#define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SW_SHIFT))&RCM_SRS_SW_MASK)
#define RCM_SRS_MDM_AP_MASK 0x800u
#define RCM_SRS_MDM_AP_SHIFT 11
#define RCM_SRS_MDM_AP_WIDTH 1
#define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_MDM_AP_SHIFT))&RCM_SRS_MDM_AP_MASK)
#define RCM_SRS_SACKERR_MASK 0x2000u
#define RCM_SRS_SACKERR_SHIFT 13
#define RCM_SRS_SACKERR_WIDTH 1
#define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SACKERR_SHIFT))&RCM_SRS_SACKERR_MASK)
/* RPC Bit Fields */
#define RCM_RPC_RSTFLTSRW_MASK 0x3u
#define RCM_RPC_RSTFLTSRW_SHIFT 0
#define RCM_RPC_RSTFLTSRW_WIDTH 2
#define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSRW_SHIFT))&RCM_RPC_RSTFLTSRW_MASK)
#define RCM_RPC_RSTFLTSS_MASK 0x4u
#define RCM_RPC_RSTFLTSS_SHIFT 2
#define RCM_RPC_RSTFLTSS_WIDTH 1
#define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSS_SHIFT))&RCM_RPC_RSTFLTSS_MASK)
#define RCM_RPC_RSTFLTSEL_MASK 0x1F00u
#define RCM_RPC_RSTFLTSEL_SHIFT 8
#define RCM_RPC_RSTFLTSEL_WIDTH 5
#define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSEL_SHIFT))&RCM_RPC_RSTFLTSEL_MASK)
/* MR Bit Fields */
#define RCM_MR_BOOTROM_MASK 0x6u
#define RCM_MR_BOOTROM_SHIFT 1
#define RCM_MR_BOOTROM_WIDTH 2
#define RCM_MR_BOOTROM(x) (((uint32_t)(((uint32_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK)
/* FM Bit Fields */
#define RCM_FM_FORCEROM_MASK 0x6u
#define RCM_FM_FORCEROM_SHIFT 1
#define RCM_FM_FORCEROM_WIDTH 2
#define RCM_FM_FORCEROM(x) (((uint32_t)(((uint32_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK)
/* SSRS Bit Fields */
#define RCM_SSRS_SWAKEUP_MASK 0x1u
#define RCM_SSRS_SWAKEUP_SHIFT 0
#define RCM_SSRS_SWAKEUP_WIDTH 1
#define RCM_SSRS_SWAKEUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SWAKEUP_SHIFT))&RCM_SSRS_SWAKEUP_MASK)
#define RCM_SSRS_SLVD_MASK 0x2u
#define RCM_SSRS_SLVD_SHIFT 1
#define RCM_SSRS_SLVD_WIDTH 1
#define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLVD_SHIFT))&RCM_SSRS_SLVD_MASK)
#define RCM_SSRS_SLOC_MASK 0x4u
#define RCM_SSRS_SLOC_SHIFT 2
#define RCM_SSRS_SLOC_WIDTH 1
#define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOC_SHIFT))&RCM_SSRS_SLOC_MASK)
#define RCM_SSRS_SLOL_MASK 0x8u
#define RCM_SSRS_SLOL_SHIFT 3
#define RCM_SSRS_SLOL_WIDTH 1
#define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOL_SHIFT))&RCM_SSRS_SLOL_MASK)
#define RCM_SSRS_SWDOG_MASK 0x20u
#define RCM_SSRS_SWDOG_SHIFT 5
#define RCM_SSRS_SWDOG_WIDTH 1
#define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SWDOG_SHIFT))&RCM_SSRS_SWDOG_MASK)
#define RCM_SSRS_SPIN_MASK 0x40u
#define RCM_SSRS_SPIN_SHIFT 6
#define RCM_SSRS_SPIN_WIDTH 1
#define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPIN_SHIFT))&RCM_SSRS_SPIN_MASK)
#define RCM_SSRS_SPOR_MASK 0x80u
#define RCM_SSRS_SPOR_SHIFT 7
#define RCM_SSRS_SPOR_WIDTH 1
#define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPOR_SHIFT))&RCM_SSRS_SPOR_MASK)
#define RCM_SSRS_SLOCKUP_MASK 0x200u
#define RCM_SSRS_SLOCKUP_SHIFT 9
#define RCM_SSRS_SLOCKUP_WIDTH 1
#define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOCKUP_SHIFT))&RCM_SSRS_SLOCKUP_MASK)
#define RCM_SSRS_SSW_MASK 0x400u
#define RCM_SSRS_SSW_SHIFT 10
#define RCM_SSRS_SSW_WIDTH 1
#define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSW_SHIFT))&RCM_SSRS_SSW_MASK)
#define RCM_SSRS_SSACKERR_MASK 0x2000u
#define RCM_SSRS_SSACKERR_SHIFT 13
#define RCM_SSRS_SSACKERR_WIDTH 1
#define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSACKERR_SHIFT))&RCM_SSRS_SSACKERR_MASK)
/* SRIE Bit Fields */
#define RCM_SRIE_DELAY_MASK 0x3u
#define RCM_SRIE_DELAY_SHIFT 0
#define RCM_SRIE_DELAY_WIDTH 2
#define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_DELAY_SHIFT))&RCM_SRIE_DELAY_MASK)
#define RCM_SRIE_LOC_MASK 0x4u
#define RCM_SRIE_LOC_SHIFT 2
#define RCM_SRIE_LOC_WIDTH 1
#define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOC_SHIFT))&RCM_SRIE_LOC_MASK)
#define RCM_SRIE_LOL_MASK 0x8u
#define RCM_SRIE_LOL_SHIFT 3
#define RCM_SRIE_LOL_WIDTH 1
#define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOL_SHIFT))&RCM_SRIE_LOL_MASK)
#define RCM_SRIE_WDOG_MASK 0x20u
#define RCM_SRIE_WDOG_SHIFT 5
#define RCM_SRIE_WDOG_WIDTH 1
#define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_WDOG_SHIFT))&RCM_SRIE_WDOG_MASK)
#define RCM_SRIE_PIN_MASK 0x40u
#define RCM_SRIE_PIN_SHIFT 6
#define RCM_SRIE_PIN_WIDTH 1
#define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_PIN_SHIFT))&RCM_SRIE_PIN_MASK)
#define RCM_SRIE_GIE_MASK 0x80u
#define RCM_SRIE_GIE_SHIFT 7
#define RCM_SRIE_GIE_WIDTH 1
#define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_GIE_SHIFT))&RCM_SRIE_GIE_MASK)
#define RCM_SRIE_LOCKUP_MASK 0x200u
#define RCM_SRIE_LOCKUP_SHIFT 9
#define RCM_SRIE_LOCKUP_WIDTH 1
#define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOCKUP_SHIFT))&RCM_SRIE_LOCKUP_MASK)
#define RCM_SRIE_SW_MASK 0x400u
#define RCM_SRIE_SW_SHIFT 10
#define RCM_SRIE_SW_WIDTH 1
#define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SW_SHIFT))&RCM_SRIE_SW_MASK)
#define RCM_SRIE_SACKERR_MASK 0x2000u
#define RCM_SRIE_SACKERR_SHIFT 13
#define RCM_SRIE_SACKERR_WIDTH 1
#define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SACKERR_SHIFT))&RCM_SRIE_SACKERR_MASK)
/*!
* @}
*/ /* end of group RCM_Register_Masks */
/* RCM - Peripheral instance base addresses */
/** Peripheral RCM base address */
#define RCM_BASE (0x4007F000u)
/** Peripheral RCM base pointer */
#define RCM ((RCM_Type *)RCM_BASE)
#define RCM_BASE_PTR (RCM)
/** Array initializer of RCM peripheral base addresses */
#define RCM_BASE_ADDRS { RCM_BASE }
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASE_PTRS { RCM }
/* ----------------------------------------------------------------------------
-- RCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
* @{
*/
/* RCM - Register instance definitions */
/* RCM */
#define RCM_VERID RCM_VERID_REG(RCM)
#define RCM_PARAM RCM_PARAM_REG(RCM)
#define RCM_SRS RCM_SRS_REG(RCM)
#define RCM_RPC RCM_RPC_REG(RCM)
#define RCM_MR RCM_MR_REG(RCM)
#define RCM_FM RCM_FM_REG(RCM)
#define RCM_SSRS RCM_SSRS_REG(RCM)
#define RCM_SRIE RCM_SRIE_REG(RCM)
/*!
* @}
*/ /* end of group RCM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RTC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
* @{
*/
/** RTC - Register Layout Typedef */
typedef struct {
__IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
__IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
__IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
__IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
__IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
__IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
__IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
} RTC_Type, *RTC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RTC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
* @{
*/
/* RTC - Register accessors */
#define RTC_TSR_REG(base) ((base)->TSR)
#define RTC_TPR_REG(base) ((base)->TPR)
#define RTC_TAR_REG(base) ((base)->TAR)
#define RTC_TCR_REG(base) ((base)->TCR)
#define RTC_CR_REG(base) ((base)->CR)
#define RTC_SR_REG(base) ((base)->SR)
#define RTC_LR_REG(base) ((base)->LR)
#define RTC_IER_REG(base) ((base)->IER)
/*!
* @}
*/ /* end of group RTC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RTC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Masks RTC Register Masks
* @{
*/
/* TSR Bit Fields */
#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
#define RTC_TSR_TSR_SHIFT 0
#define RTC_TSR_TSR_WIDTH 32
#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
/* TPR Bit Fields */
#define RTC_TPR_TPR_MASK 0xFFFFu
#define RTC_TPR_TPR_SHIFT 0
#define RTC_TPR_TPR_WIDTH 16
#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
/* TAR Bit Fields */
#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
#define RTC_TAR_TAR_SHIFT 0
#define RTC_TAR_TAR_WIDTH 32
#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
/* TCR Bit Fields */
#define RTC_TCR_TCR_MASK 0xFFu
#define RTC_TCR_TCR_SHIFT 0
#define RTC_TCR_TCR_WIDTH 8
#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
#define RTC_TCR_CIR_MASK 0xFF00u
#define RTC_TCR_CIR_SHIFT 8
#define RTC_TCR_CIR_WIDTH 8
#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
#define RTC_TCR_TCV_MASK 0xFF0000u
#define RTC_TCR_TCV_SHIFT 16
#define RTC_TCR_TCV_WIDTH 8
#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
#define RTC_TCR_CIC_MASK 0xFF000000u
#define RTC_TCR_CIC_SHIFT 24
#define RTC_TCR_CIC_WIDTH 8
#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
/* CR Bit Fields */
#define RTC_CR_SWR_MASK 0x1u
#define RTC_CR_SWR_SHIFT 0
#define RTC_CR_SWR_WIDTH 1
#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
#define RTC_CR_WPE_MASK 0x2u
#define RTC_CR_WPE_SHIFT 1
#define RTC_CR_WPE_WIDTH 1
#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
#define RTC_CR_SUP_MASK 0x4u
#define RTC_CR_SUP_SHIFT 2
#define RTC_CR_SUP_WIDTH 1
#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
#define RTC_CR_UM_MASK 0x8u
#define RTC_CR_UM_SHIFT 3
#define RTC_CR_UM_WIDTH 1
#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
#define RTC_CR_WPS_MASK 0x10u
#define RTC_CR_WPS_SHIFT 4
#define RTC_CR_WPS_WIDTH 1
#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
#define RTC_CR_CPS_MASK 0x20u
#define RTC_CR_CPS_SHIFT 5
#define RTC_CR_CPS_WIDTH 1
#define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPS_SHIFT))&RTC_CR_CPS_MASK)
#define RTC_CR_LPOS_MASK 0x80u
#define RTC_CR_LPOS_SHIFT 7
#define RTC_CR_LPOS_WIDTH 1
#define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_LPOS_SHIFT))&RTC_CR_LPOS_MASK)
#define RTC_CR_OSCE_MASK 0x100u
#define RTC_CR_OSCE_SHIFT 8
#define RTC_CR_OSCE_WIDTH 1
#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
#define RTC_CR_CLKO_MASK 0x200u
#define RTC_CR_CLKO_SHIFT 9
#define RTC_CR_CLKO_WIDTH 1
#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
#define RTC_CR_SC16P_MASK 0x400u
#define RTC_CR_SC16P_SHIFT 10
#define RTC_CR_SC16P_WIDTH 1
#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
#define RTC_CR_SC8P_MASK 0x800u
#define RTC_CR_SC8P_SHIFT 11
#define RTC_CR_SC8P_WIDTH 1
#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
#define RTC_CR_SC4P_MASK 0x1000u
#define RTC_CR_SC4P_SHIFT 12
#define RTC_CR_SC4P_WIDTH 1
#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
#define RTC_CR_SC2P_MASK 0x2000u
#define RTC_CR_SC2P_SHIFT 13
#define RTC_CR_SC2P_WIDTH 1
#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
#define RTC_CR_CPE_MASK 0x3000000u
#define RTC_CR_CPE_SHIFT 24
#define RTC_CR_CPE_WIDTH 2
#define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPE_SHIFT))&RTC_CR_CPE_MASK)
/* SR Bit Fields */
#define RTC_SR_TIF_MASK 0x1u
#define RTC_SR_TIF_SHIFT 0
#define RTC_SR_TIF_WIDTH 1
#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
#define RTC_SR_TOF_MASK 0x2u
#define RTC_SR_TOF_SHIFT 1
#define RTC_SR_TOF_WIDTH 1
#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
#define RTC_SR_TAF_MASK 0x4u
#define RTC_SR_TAF_SHIFT 2
#define RTC_SR_TAF_WIDTH 1
#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
#define RTC_SR_TCE_MASK 0x10u
#define RTC_SR_TCE_SHIFT 4
#define RTC_SR_TCE_WIDTH 1
#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
/* LR Bit Fields */
#define RTC_LR_TCL_MASK 0x8u
#define RTC_LR_TCL_SHIFT 3
#define RTC_LR_TCL_WIDTH 1
#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
#define RTC_LR_CRL_MASK 0x10u
#define RTC_LR_CRL_SHIFT 4
#define RTC_LR_CRL_WIDTH 1
#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
#define RTC_LR_SRL_MASK 0x20u
#define RTC_LR_SRL_SHIFT 5
#define RTC_LR_SRL_WIDTH 1
#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
#define RTC_LR_LRL_MASK 0x40u
#define RTC_LR_LRL_SHIFT 6
#define RTC_LR_LRL_WIDTH 1
#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
/* IER Bit Fields */
#define RTC_IER_TIIE_MASK 0x1u
#define RTC_IER_TIIE_SHIFT 0
#define RTC_IER_TIIE_WIDTH 1
#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
#define RTC_IER_TOIE_MASK 0x2u
#define RTC_IER_TOIE_SHIFT 1
#define RTC_IER_TOIE_WIDTH 1
#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
#define RTC_IER_TAIE_MASK 0x4u
#define RTC_IER_TAIE_SHIFT 2
#define RTC_IER_TAIE_WIDTH 1
#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
#define RTC_IER_TSIE_MASK 0x10u
#define RTC_IER_TSIE_SHIFT 4
#define RTC_IER_TSIE_WIDTH 1
#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
#define RTC_IER_WPON_MASK 0x80u
#define RTC_IER_WPON_SHIFT 7
#define RTC_IER_WPON_WIDTH 1
#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
#define RTC_IER_TSIC_MASK 0x70000u
#define RTC_IER_TSIC_SHIFT 16
#define RTC_IER_TSIC_WIDTH 3
#define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIC_SHIFT))&RTC_IER_TSIC_MASK)
/*!
* @}
*/ /* end of group RTC_Register_Masks */
/* RTC - Peripheral instance base addresses */
/** Peripheral RTC base address */
#define RTC_BASE (0x40038000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
#define RTC_BASE_PTR (RTC)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS { RTC_BASE }
/** Array initializer of RTC peripheral base pointers */
#define RTC_BASE_PTRS { RTC }
/* ----------------------------------------------------------------------------
-- RTC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
* @{
*/
/* RTC - Register instance definitions */
/* RTC */
#define RTC_TSR RTC_TSR_REG(RTC)
#define RTC_TPR RTC_TPR_REG(RTC)
#define RTC_TAR RTC_TAR_REG(RTC)
#define RTC_TCR RTC_TCR_REG(RTC)
#define RTC_CR RTC_CR_REG(RTC)
#define RTC_SR RTC_SR_REG(RTC)
#define RTC_LR RTC_LR_REG(RTC)
#define RTC_IER RTC_IER_REG(RTC)
/*!
* @}
*/ /* end of group RTC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SCG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
* @{
*/
/** SCG - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */
__IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */
__IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */
__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */
__IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */
uint8_t RESERVED_1[220];
__IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */
__IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */
__IO uint32_t SOSCCFG; /**< System Oscillator Configuration Register, offset: 0x108 */
uint8_t RESERVED_2[244];
__IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */
__IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */
__IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */
uint8_t RESERVED_3[244];
__IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */
__IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */
__IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */
__IO uint32_t FIRCTCFG; /**< Fast IRC Trim Configuration Register, offset: 0x30C */
uint8_t RESERVED_4[8];
__IO uint32_t FIRCSTAT; /**< Fast IRC Status Register, offset: 0x318 */
uint8_t RESERVED_5[740];
__IO uint32_t SPLLCSR; /**< System PLL Control Status Register, offset: 0x600 */
__IO uint32_t SPLLDIV; /**< System PLL Divide Register, offset: 0x604 */
__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0x608 */
} SCG_Type, *SCG_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SCG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SCG_Register_Accessor_Macros SCG - Register accessor macros
* @{
*/
/* SCG - Register accessors */
#define SCG_VERID_REG(base) ((base)->VERID)
#define SCG_PARAM_REG(base) ((base)->PARAM)
#define SCG_CSR_REG(base) ((base)->CSR)
#define SCG_RCCR_REG(base) ((base)->RCCR)
#define SCG_VCCR_REG(base) ((base)->VCCR)
#define SCG_HCCR_REG(base) ((base)->HCCR)
#define SCG_CLKOUTCNFG_REG(base) ((base)->CLKOUTCNFG)
#define SCG_SOSCCSR_REG(base) ((base)->SOSCCSR)
#define SCG_SOSCDIV_REG(base) ((base)->SOSCDIV)
#define SCG_SOSCCFG_REG(base) ((base)->SOSCCFG)
#define SCG_SIRCCSR_REG(base) ((base)->SIRCCSR)
#define SCG_SIRCDIV_REG(base) ((base)->SIRCDIV)
#define SCG_SIRCCFG_REG(base) ((base)->SIRCCFG)
#define SCG_FIRCCSR_REG(base) ((base)->FIRCCSR)
#define SCG_FIRCDIV_REG(base) ((base)->FIRCDIV)
#define SCG_FIRCCFG_REG(base) ((base)->FIRCCFG)
#define SCG_FIRCTCFG_REG(base) ((base)->FIRCTCFG)
#define SCG_FIRCSTAT_REG(base) ((base)->FIRCSTAT)
#define SCG_SPLLCSR_REG(base) ((base)->SPLLCSR)
#define SCG_SPLLDIV_REG(base) ((base)->SPLLDIV)
#define SCG_SPLLCFG_REG(base) ((base)->SPLLCFG)
/*!
* @}
*/ /* end of group SCG_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SCG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SCG_Register_Masks SCG Register Masks
* @{
*/
/* VERID Bit Fields */
#define SCG_VERID_VERSION_MASK 0xFFFFFFFFu
#define SCG_VERID_VERSION_SHIFT 0
#define SCG_VERID_VERSION_WIDTH 32
#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x))<<SCG_VERID_VERSION_SHIFT))&SCG_VERID_VERSION_MASK)
/* PARAM Bit Fields */
#define SCG_PARAM_CLKPRES_MASK 0xFFu
#define SCG_PARAM_CLKPRES_SHIFT 0
#define SCG_PARAM_CLKPRES_WIDTH 8
#define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_CLKPRES_SHIFT))&SCG_PARAM_CLKPRES_MASK)
#define SCG_PARAM_DIVPRES_MASK 0xF8000000u
#define SCG_PARAM_DIVPRES_SHIFT 27
#define SCG_PARAM_DIVPRES_WIDTH 5
#define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_DIVPRES_SHIFT))&SCG_PARAM_DIVPRES_MASK)
/* CSR Bit Fields */
#define SCG_CSR_DIVSLOW_MASK 0xFu
#define SCG_CSR_DIVSLOW_SHIFT 0
#define SCG_CSR_DIVSLOW_WIDTH 4
#define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVSLOW_SHIFT))&SCG_CSR_DIVSLOW_MASK)
#define SCG_CSR_DIVCORE_MASK 0xF0000u
#define SCG_CSR_DIVCORE_SHIFT 16
#define SCG_CSR_DIVCORE_WIDTH 4
#define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVCORE_SHIFT))&SCG_CSR_DIVCORE_MASK)
#define SCG_CSR_SCS_MASK 0xF000000u
#define SCG_CSR_SCS_SHIFT 24
#define SCG_CSR_SCS_WIDTH 4
#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_SCS_SHIFT))&SCG_CSR_SCS_MASK)
/* RCCR Bit Fields */
#define SCG_RCCR_DIVSLOW_MASK 0xFu
#define SCG_RCCR_DIVSLOW_SHIFT 0
#define SCG_RCCR_DIVSLOW_WIDTH 4
#define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVSLOW_SHIFT))&SCG_RCCR_DIVSLOW_MASK)
#define SCG_RCCR_DIVCORE_MASK 0xF0000u
#define SCG_RCCR_DIVCORE_SHIFT 16
#define SCG_RCCR_DIVCORE_WIDTH 4
#define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVCORE_SHIFT))&SCG_RCCR_DIVCORE_MASK)
#define SCG_RCCR_SCS_MASK 0xF000000u
#define SCG_RCCR_SCS_SHIFT 24
#define SCG_RCCR_SCS_WIDTH 4
#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_SCS_SHIFT))&SCG_RCCR_SCS_MASK)
/* VCCR Bit Fields */
#define SCG_VCCR_DIVSLOW_MASK 0xFu
#define SCG_VCCR_DIVSLOW_SHIFT 0
#define SCG_VCCR_DIVSLOW_WIDTH 4
#define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVSLOW_SHIFT))&SCG_VCCR_DIVSLOW_MASK)
#define SCG_VCCR_DIVCORE_MASK 0xF0000u
#define SCG_VCCR_DIVCORE_SHIFT 16
#define SCG_VCCR_DIVCORE_WIDTH 4
#define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVCORE_SHIFT))&SCG_VCCR_DIVCORE_MASK)
#define SCG_VCCR_SCS_MASK 0xF000000u
#define SCG_VCCR_SCS_SHIFT 24
#define SCG_VCCR_SCS_WIDTH 4
#define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_SCS_SHIFT))&SCG_VCCR_SCS_MASK)
/* HCCR Bit Fields */
#define SCG_HCCR_DIVSLOW_MASK 0xFu
#define SCG_HCCR_DIVSLOW_SHIFT 0
#define SCG_HCCR_DIVSLOW_WIDTH 4
#define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVSLOW_SHIFT))&SCG_HCCR_DIVSLOW_MASK)
#define SCG_HCCR_DIVCORE_MASK 0xF0000u
#define SCG_HCCR_DIVCORE_SHIFT 16
#define SCG_HCCR_DIVCORE_WIDTH 4
#define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVCORE_SHIFT))&SCG_HCCR_DIVCORE_MASK)
#define SCG_HCCR_SCS_MASK 0xF000000u
#define SCG_HCCR_SCS_SHIFT 24
#define SCG_HCCR_SCS_WIDTH 4
#define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_SCS_SHIFT))&SCG_HCCR_SCS_MASK)
/* CLKOUTCNFG Bit Fields */
#define SCG_CLKOUTCNFG_CLKOUTSEL_MASK 0xF000000u
#define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT 24
#define SCG_CLKOUTCNFG_CLKOUTSEL_WIDTH 4
#define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT))&SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
/* SOSCCSR Bit Fields */
#define SCG_SOSCCSR_SOSCEN_MASK 0x1u
#define SCG_SOSCCSR_SOSCEN_SHIFT 0
#define SCG_SOSCCSR_SOSCEN_WIDTH 1
#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCEN_SHIFT))&SCG_SOSCCSR_SOSCEN_MASK)
#define SCG_SOSCCSR_SOSCSTEN_MASK 0x2u
#define SCG_SOSCCSR_SOSCSTEN_SHIFT 1
#define SCG_SOSCCSR_SOSCSTEN_WIDTH 1
#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCSTEN_SHIFT))&SCG_SOSCCSR_SOSCSTEN_MASK)
#define SCG_SOSCCSR_SOSCLPEN_MASK 0x4u
#define SCG_SOSCCSR_SOSCLPEN_SHIFT 2
#define SCG_SOSCCSR_SOSCLPEN_WIDTH 1
#define SCG_SOSCCSR_SOSCLPEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCLPEN_SHIFT))&SCG_SOSCCSR_SOSCLPEN_MASK)
#define SCG_SOSCCSR_SOSCERCLKEN_MASK 0x8u
#define SCG_SOSCCSR_SOSCERCLKEN_SHIFT 3
#define SCG_SOSCCSR_SOSCERCLKEN_WIDTH 1
#define SCG_SOSCCSR_SOSCERCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCERCLKEN_SHIFT))&SCG_SOSCCSR_SOSCERCLKEN_MASK)
#define SCG_SOSCCSR_SOSCCM_MASK 0x10000u
#define SCG_SOSCCSR_SOSCCM_SHIFT 16
#define SCG_SOSCCSR_SOSCCM_WIDTH 1
#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCM_SHIFT))&SCG_SOSCCSR_SOSCCM_MASK)
#define SCG_SOSCCSR_SOSCCMRE_MASK 0x20000u
#define SCG_SOSCCSR_SOSCCMRE_SHIFT 17
#define SCG_SOSCCSR_SOSCCMRE_WIDTH 1
#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCMRE_SHIFT))&SCG_SOSCCSR_SOSCCMRE_MASK)
#define SCG_SOSCCSR_LK_MASK 0x800000u
#define SCG_SOSCCSR_LK_SHIFT 23
#define SCG_SOSCCSR_LK_WIDTH 1
#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_LK_SHIFT))&SCG_SOSCCSR_LK_MASK)
#define SCG_SOSCCSR_SOSCVLD_MASK 0x1000000u
#define SCG_SOSCCSR_SOSCVLD_SHIFT 24
#define SCG_SOSCCSR_SOSCVLD_WIDTH 1
#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCVLD_SHIFT))&SCG_SOSCCSR_SOSCVLD_MASK)
#define SCG_SOSCCSR_SOSCSEL_MASK 0x2000000u
#define SCG_SOSCCSR_SOSCSEL_SHIFT 25
#define SCG_SOSCCSR_SOSCSEL_WIDTH 1
#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCSEL_SHIFT))&SCG_SOSCCSR_SOSCSEL_MASK)
#define SCG_SOSCCSR_SOSCERR_MASK 0x4000000u
#define SCG_SOSCCSR_SOSCERR_SHIFT 26
#define SCG_SOSCCSR_SOSCERR_WIDTH 1
#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCERR_SHIFT))&SCG_SOSCCSR_SOSCERR_MASK)
/* SOSCDIV Bit Fields */
#define SCG_SOSCDIV_SOSCDIV1_MASK 0x7u
#define SCG_SOSCDIV_SOSCDIV1_SHIFT 0
#define SCG_SOSCDIV_SOSCDIV1_WIDTH 3
#define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV1_SHIFT))&SCG_SOSCDIV_SOSCDIV1_MASK)
#define SCG_SOSCDIV_SOSCDIV2_MASK 0x700u
#define SCG_SOSCDIV_SOSCDIV2_SHIFT 8
#define SCG_SOSCDIV_SOSCDIV2_WIDTH 3
#define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV2_SHIFT))&SCG_SOSCDIV_SOSCDIV2_MASK)
#define SCG_SOSCDIV_SOSCDIV3_MASK 0x70000u
#define SCG_SOSCDIV_SOSCDIV3_SHIFT 16
#define SCG_SOSCDIV_SOSCDIV3_WIDTH 3
#define SCG_SOSCDIV_SOSCDIV3(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV3_SHIFT))&SCG_SOSCDIV_SOSCDIV3_MASK)
/* SOSCCFG Bit Fields */
#define SCG_SOSCCFG_EREFS_MASK 0x4u
#define SCG_SOSCCFG_EREFS_SHIFT 2
#define SCG_SOSCCFG_EREFS_WIDTH 1
#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_EREFS_SHIFT))&SCG_SOSCCFG_EREFS_MASK)
#define SCG_SOSCCFG_HGO_MASK 0x8u
#define SCG_SOSCCFG_HGO_SHIFT 3
#define SCG_SOSCCFG_HGO_WIDTH 1
#define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_HGO_SHIFT))&SCG_SOSCCFG_HGO_MASK)
#define SCG_SOSCCFG_RANGE_MASK 0x30u
#define SCG_SOSCCFG_RANGE_SHIFT 4
#define SCG_SOSCCFG_RANGE_WIDTH 2
#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_RANGE_SHIFT))&SCG_SOSCCFG_RANGE_MASK)
#define SCG_SOSCCFG_SC16P_MASK 0x100u
#define SCG_SOSCCFG_SC16P_SHIFT 8
#define SCG_SOSCCFG_SC16P_WIDTH 1
#define SCG_SOSCCFG_SC16P(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_SC16P_SHIFT))&SCG_SOSCCFG_SC16P_MASK)
#define SCG_SOSCCFG_SC8P_MASK 0x200u
#define SCG_SOSCCFG_SC8P_SHIFT 9
#define SCG_SOSCCFG_SC8P_WIDTH 1
#define SCG_SOSCCFG_SC8P(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_SC8P_SHIFT))&SCG_SOSCCFG_SC8P_MASK)
#define SCG_SOSCCFG_SC4P_MASK 0x400u
#define SCG_SOSCCFG_SC4P_SHIFT 10
#define SCG_SOSCCFG_SC4P_WIDTH 1
#define SCG_SOSCCFG_SC4P(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_SC4P_SHIFT))&SCG_SOSCCFG_SC4P_MASK)
#define SCG_SOSCCFG_SC2P_MASK 0x800u
#define SCG_SOSCCFG_SC2P_SHIFT 11
#define SCG_SOSCCFG_SC2P_WIDTH 1
#define SCG_SOSCCFG_SC2P(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_SC2P_SHIFT))&SCG_SOSCCFG_SC2P_MASK)
/* SIRCCSR Bit Fields */
#define SCG_SIRCCSR_SIRCEN_MASK 0x1u
#define SCG_SIRCCSR_SIRCEN_SHIFT 0
#define SCG_SIRCCSR_SIRCEN_WIDTH 1
#define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCEN_SHIFT))&SCG_SIRCCSR_SIRCEN_MASK)
#define SCG_SIRCCSR_SIRCSTEN_MASK 0x2u
#define SCG_SIRCCSR_SIRCSTEN_SHIFT 1
#define SCG_SIRCCSR_SIRCSTEN_WIDTH 1
#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSTEN_SHIFT))&SCG_SIRCCSR_SIRCSTEN_MASK)
#define SCG_SIRCCSR_SIRCLPEN_MASK 0x4u
#define SCG_SIRCCSR_SIRCLPEN_SHIFT 2
#define SCG_SIRCCSR_SIRCLPEN_WIDTH 1
#define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCLPEN_SHIFT))&SCG_SIRCCSR_SIRCLPEN_MASK)
#define SCG_SIRCCSR_LK_MASK 0x800000u
#define SCG_SIRCCSR_LK_SHIFT 23
#define SCG_SIRCCSR_LK_WIDTH 1
#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_LK_SHIFT))&SCG_SIRCCSR_LK_MASK)
#define SCG_SIRCCSR_SIRCVLD_MASK 0x1000000u
#define SCG_SIRCCSR_SIRCVLD_SHIFT 24
#define SCG_SIRCCSR_SIRCVLD_WIDTH 1
#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCVLD_SHIFT))&SCG_SIRCCSR_SIRCVLD_MASK)
#define SCG_SIRCCSR_SIRCSEL_MASK 0x2000000u
#define SCG_SIRCCSR_SIRCSEL_SHIFT 25
#define SCG_SIRCCSR_SIRCSEL_WIDTH 1
#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSEL_SHIFT))&SCG_SIRCCSR_SIRCSEL_MASK)
/* SIRCDIV Bit Fields */
#define SCG_SIRCDIV_SIRCDIV1_MASK 0x7u
#define SCG_SIRCDIV_SIRCDIV1_SHIFT 0
#define SCG_SIRCDIV_SIRCDIV1_WIDTH 3
#define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV1_SHIFT))&SCG_SIRCDIV_SIRCDIV1_MASK)
#define SCG_SIRCDIV_SIRCDIV2_MASK 0x700u
#define SCG_SIRCDIV_SIRCDIV2_SHIFT 8
#define SCG_SIRCDIV_SIRCDIV2_WIDTH 3
#define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV2_SHIFT))&SCG_SIRCDIV_SIRCDIV2_MASK)
#define SCG_SIRCDIV_SIRCDIV3_MASK 0x70000u
#define SCG_SIRCDIV_SIRCDIV3_SHIFT 16
#define SCG_SIRCDIV_SIRCDIV3_WIDTH 3
#define SCG_SIRCDIV_SIRCDIV3(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV3_SHIFT))&SCG_SIRCDIV_SIRCDIV3_MASK)
/* SIRCCFG Bit Fields */
#define SCG_SIRCCFG_RANGE_MASK 0x1u
#define SCG_SIRCCFG_RANGE_SHIFT 0
#define SCG_SIRCCFG_RANGE_WIDTH 1
#define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCFG_RANGE_SHIFT))&SCG_SIRCCFG_RANGE_MASK)
/* FIRCCSR Bit Fields */
#define SCG_FIRCCSR_FIRCEN_MASK 0x1u
#define SCG_FIRCCSR_FIRCEN_SHIFT 0
#define SCG_FIRCCSR_FIRCEN_WIDTH 1
#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCEN_SHIFT))&SCG_FIRCCSR_FIRCEN_MASK)
#define SCG_FIRCCSR_FIRCSTEN_MASK 0x2u
#define SCG_FIRCCSR_FIRCSTEN_SHIFT 1
#define SCG_FIRCCSR_FIRCSTEN_WIDTH 1
#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCSTEN_SHIFT))&SCG_FIRCCSR_FIRCSTEN_MASK)
#define SCG_FIRCCSR_FIRCREGOFF_MASK 0x4u
#define SCG_FIRCCSR_FIRCREGOFF_SHIFT 2
#define SCG_FIRCCSR_FIRCREGOFF_WIDTH 1
#define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCREGOFF_SHIFT))&SCG_FIRCCSR_FIRCREGOFF_MASK)
#define SCG_FIRCCSR_FIRCLPEN_MASK 0x8u
#define SCG_FIRCCSR_FIRCLPEN_SHIFT 3
#define SCG_FIRCCSR_FIRCLPEN_WIDTH 1
#define SCG_FIRCCSR_FIRCLPEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCLPEN_SHIFT))&SCG_FIRCCSR_FIRCLPEN_MASK)
#define SCG_FIRCCSR_FIRCTREN_MASK 0x100u
#define SCG_FIRCCSR_FIRCTREN_SHIFT 8
#define SCG_FIRCCSR_FIRCTREN_WIDTH 1
#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCTREN_SHIFT))&SCG_FIRCCSR_FIRCTREN_MASK)
#define SCG_FIRCCSR_FIRCTRUP_MASK 0x200u
#define SCG_FIRCCSR_FIRCTRUP_SHIFT 9
#define SCG_FIRCCSR_FIRCTRUP_WIDTH 1
#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCTRUP_SHIFT))&SCG_FIRCCSR_FIRCTRUP_MASK)
#define SCG_FIRCCSR_LK_MASK 0x800000u
#define SCG_FIRCCSR_LK_SHIFT 23
#define SCG_FIRCCSR_LK_WIDTH 1
#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_LK_SHIFT))&SCG_FIRCCSR_LK_MASK)
#define SCG_FIRCCSR_FIRCVLD_MASK 0x1000000u
#define SCG_FIRCCSR_FIRCVLD_SHIFT 24
#define SCG_FIRCCSR_FIRCVLD_WIDTH 1
#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCVLD_SHIFT))&SCG_FIRCCSR_FIRCVLD_MASK)
#define SCG_FIRCCSR_FIRCSEL_MASK 0x2000000u
#define SCG_FIRCCSR_FIRCSEL_SHIFT 25
#define SCG_FIRCCSR_FIRCSEL_WIDTH 1
#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCSEL_SHIFT))&SCG_FIRCCSR_FIRCSEL_MASK)
#define SCG_FIRCCSR_FIRCERR_MASK 0x4000000u
#define SCG_FIRCCSR_FIRCERR_SHIFT 26
#define SCG_FIRCCSR_FIRCERR_WIDTH 1
#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCERR_SHIFT))&SCG_FIRCCSR_FIRCERR_MASK)
/* FIRCDIV Bit Fields */
#define SCG_FIRCDIV_FIRCDIV1_MASK 0x7u
#define SCG_FIRCDIV_FIRCDIV1_SHIFT 0
#define SCG_FIRCDIV_FIRCDIV1_WIDTH 3
#define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV1_SHIFT))&SCG_FIRCDIV_FIRCDIV1_MASK)
#define SCG_FIRCDIV_FIRCDIV2_MASK 0x700u
#define SCG_FIRCDIV_FIRCDIV2_SHIFT 8
#define SCG_FIRCDIV_FIRCDIV2_WIDTH 3
#define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV2_SHIFT))&SCG_FIRCDIV_FIRCDIV2_MASK)
#define SCG_FIRCDIV_FIRCDIV3_MASK 0x70000u
#define SCG_FIRCDIV_FIRCDIV3_SHIFT 16
#define SCG_FIRCDIV_FIRCDIV3_WIDTH 3
#define SCG_FIRCDIV_FIRCDIV3(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV3_SHIFT))&SCG_FIRCDIV_FIRCDIV3_MASK)
/* FIRCCFG Bit Fields */
#define SCG_FIRCCFG_RANGE_MASK 0x3u
#define SCG_FIRCCFG_RANGE_SHIFT 0
#define SCG_FIRCCFG_RANGE_WIDTH 2
#define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCFG_RANGE_SHIFT))&SCG_FIRCCFG_RANGE_MASK)
/* FIRCTCFG Bit Fields */
#define SCG_FIRCTCFG_TRIMSRC_MASK 0x3u
#define SCG_FIRCTCFG_TRIMSRC_SHIFT 0
#define SCG_FIRCTCFG_TRIMSRC_WIDTH 2
#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCTCFG_TRIMSRC_SHIFT))&SCG_FIRCTCFG_TRIMSRC_MASK)
#define SCG_FIRCTCFG_TRIMDIV_MASK 0x700u
#define SCG_FIRCTCFG_TRIMDIV_SHIFT 8
#define SCG_FIRCTCFG_TRIMDIV_WIDTH 3
#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCTCFG_TRIMDIV_SHIFT))&SCG_FIRCTCFG_TRIMDIV_MASK)
/* FIRCSTAT Bit Fields */
#define SCG_FIRCSTAT_TRIMFINE_MASK 0x7Fu
#define SCG_FIRCSTAT_TRIMFINE_SHIFT 0
#define SCG_FIRCSTAT_TRIMFINE_WIDTH 7
#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCSTAT_TRIMFINE_SHIFT))&SCG_FIRCSTAT_TRIMFINE_MASK)
#define SCG_FIRCSTAT_TRIMCOAR_MASK 0xFF00u
#define SCG_FIRCSTAT_TRIMCOAR_SHIFT 8
#define SCG_FIRCSTAT_TRIMCOAR_WIDTH 8
#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCSTAT_TRIMCOAR_SHIFT))&SCG_FIRCSTAT_TRIMCOAR_MASK)
/* SPLLCSR Bit Fields */
#define SCG_SPLLCSR_SPLLEN_MASK 0x1u
#define SCG_SPLLCSR_SPLLEN_SHIFT 0
#define SCG_SPLLCSR_SPLLEN_WIDTH 1
#define SCG_SPLLCSR_SPLLEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLEN_SHIFT))&SCG_SPLLCSR_SPLLEN_MASK)
#define SCG_SPLLCSR_SPLLSTEN_MASK 0x2u
#define SCG_SPLLCSR_SPLLSTEN_SHIFT 1
#define SCG_SPLLCSR_SPLLSTEN_WIDTH 1
#define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLSTEN_SHIFT))&SCG_SPLLCSR_SPLLSTEN_MASK)
#define SCG_SPLLCSR_SPLLCM_MASK 0x10000u
#define SCG_SPLLCSR_SPLLCM_SHIFT 16
#define SCG_SPLLCSR_SPLLCM_WIDTH 1
#define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLCM_SHIFT))&SCG_SPLLCSR_SPLLCM_MASK)
#define SCG_SPLLCSR_SPLLCMRE_MASK 0x20000u
#define SCG_SPLLCSR_SPLLCMRE_SHIFT 17
#define SCG_SPLLCSR_SPLLCMRE_WIDTH 1
#define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLCMRE_SHIFT))&SCG_SPLLCSR_SPLLCMRE_MASK)
#define SCG_SPLLCSR_LK_MASK 0x800000u
#define SCG_SPLLCSR_LK_SHIFT 23
#define SCG_SPLLCSR_LK_WIDTH 1
#define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_LK_SHIFT))&SCG_SPLLCSR_LK_MASK)
#define SCG_SPLLCSR_SPLLVLD_MASK 0x1000000u
#define SCG_SPLLCSR_SPLLVLD_SHIFT 24
#define SCG_SPLLCSR_SPLLVLD_WIDTH 1
#define SCG_SPLLCSR_SPLLVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLVLD_SHIFT))&SCG_SPLLCSR_SPLLVLD_MASK)
#define SCG_SPLLCSR_SPLLSEL_MASK 0x2000000u
#define SCG_SPLLCSR_SPLLSEL_SHIFT 25
#define SCG_SPLLCSR_SPLLSEL_WIDTH 1
#define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLSEL_SHIFT))&SCG_SPLLCSR_SPLLSEL_MASK)
#define SCG_SPLLCSR_SPLLERR_MASK 0x4000000u
#define SCG_SPLLCSR_SPLLERR_SHIFT 26
#define SCG_SPLLCSR_SPLLERR_WIDTH 1
#define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLERR_SHIFT))&SCG_SPLLCSR_SPLLERR_MASK)
/* SPLLDIV Bit Fields */
#define SCG_SPLLDIV_SPLLDIV1_MASK 0x7u
#define SCG_SPLLDIV_SPLLDIV1_SHIFT 0
#define SCG_SPLLDIV_SPLLDIV1_WIDTH 3
#define SCG_SPLLDIV_SPLLDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV1_SHIFT))&SCG_SPLLDIV_SPLLDIV1_MASK)
#define SCG_SPLLDIV_SPLLDIV2_MASK 0x700u
#define SCG_SPLLDIV_SPLLDIV2_SHIFT 8
#define SCG_SPLLDIV_SPLLDIV2_WIDTH 3
#define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV2_SHIFT))&SCG_SPLLDIV_SPLLDIV2_MASK)
#define SCG_SPLLDIV_SPLLDIV3_MASK 0x70000u
#define SCG_SPLLDIV_SPLLDIV3_SHIFT 16
#define SCG_SPLLDIV_SPLLDIV3_WIDTH 3
#define SCG_SPLLDIV_SPLLDIV3(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV3_SHIFT))&SCG_SPLLDIV_SPLLDIV3_MASK)
/* SPLLCFG Bit Fields */
#define SCG_SPLLCFG_SOURCE_MASK 0x1u
#define SCG_SPLLCFG_SOURCE_SHIFT 0
#define SCG_SPLLCFG_SOURCE_WIDTH 1
#define SCG_SPLLCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_SOURCE_SHIFT))&SCG_SPLLCFG_SOURCE_MASK)
#define SCG_SPLLCFG_PREDIV_MASK 0x700u
#define SCG_SPLLCFG_PREDIV_SHIFT 8
#define SCG_SPLLCFG_PREDIV_WIDTH 3
#define SCG_SPLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_PREDIV_SHIFT))&SCG_SPLLCFG_PREDIV_MASK)
#define SCG_SPLLCFG_MULT_MASK 0x1F0000u
#define SCG_SPLLCFG_MULT_SHIFT 16
#define SCG_SPLLCFG_MULT_WIDTH 5
#define SCG_SPLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_MULT_SHIFT))&SCG_SPLLCFG_MULT_MASK)
/*!
* @}
*/ /* end of group SCG_Register_Masks */
/* SCG - Peripheral instance base addresses */
/** Peripheral SCG base address */
#define SCG_BASE (0x4007B000u)
/** Peripheral SCG base pointer */
#define SCG ((SCG_Type *)SCG_BASE)
#define SCG_BASE_PTR (SCG)
/** Array initializer of SCG peripheral base addresses */
#define SCG_BASE_ADDRS { SCG_BASE }
/** Array initializer of SCG peripheral base pointers */
#define SCG_BASE_PTRS { SCG }
/* ----------------------------------------------------------------------------
-- SCG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SCG_Register_Accessor_Macros SCG - Register accessor macros
* @{
*/
/* SCG - Register instance definitions */
/* SCG */
#define SCG_VERID SCG_VERID_REG(SCG)
#define SCG_PARAM SCG_PARAM_REG(SCG)
#define SCG_CSR SCG_CSR_REG(SCG)
#define SCG_RCCR SCG_RCCR_REG(SCG)
#define SCG_VCCR SCG_VCCR_REG(SCG)
#define SCG_HCCR SCG_HCCR_REG(SCG)
#define SCG_CLKOUTCNFG SCG_CLKOUTCNFG_REG(SCG)
#define SCG_SOSCCSR SCG_SOSCCSR_REG(SCG)
#define SCG_SOSCDIV SCG_SOSCDIV_REG(SCG)
#define SCG_SOSCCFG SCG_SOSCCFG_REG(SCG)
#define SCG_SIRCCSR SCG_SIRCCSR_REG(SCG)
#define SCG_SIRCDIV SCG_SIRCDIV_REG(SCG)
#define SCG_SIRCCFG SCG_SIRCCFG_REG(SCG)
#define SCG_FIRCCSR SCG_FIRCCSR_REG(SCG)
#define SCG_FIRCDIV SCG_FIRCDIV_REG(SCG)
#define SCG_FIRCCFG SCG_FIRCCFG_REG(SCG)
#define SCG_FIRCTCFG SCG_FIRCTCFG_REG(SCG)
#define SCG_FIRCSTAT SCG_FIRCSTAT_REG(SCG)
#define SCG_SPLLCSR SCG_SPLLCSR_REG(SCG)
#define SCG_SPLLDIV SCG_SPLLDIV_REG(SCG)
#define SCG_SPLLCFG SCG_SPLLCFG_REG(SCG)
/*!
* @}
*/ /* end of group SCG_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group SCG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
* @{
*/
/** SIM - Register Layout Typedef */
typedef struct {
__IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
__IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
uint8_t RESERVED_0[4124];
__I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint8_t RESERVED_1[36];
__IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
__I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
uint8_t RESERVED_2[4];
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
} SIM_Type, *SIM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SIM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
* @{
*/
/* SIM - Register accessors */
#define SIM_SOPT1_REG(base) ((base)->SOPT1)
#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
#define SIM_SDID_REG(base) ((base)->SDID)
#define SIM_FCFG1_REG(base) ((base)->FCFG1)
#define SIM_FCFG2_REG(base) ((base)->FCFG2)
#define SIM_UIDMH_REG(base) ((base)->UIDMH)
#define SIM_UIDML_REG(base) ((base)->UIDML)
#define SIM_UIDL_REG(base) ((base)->UIDL)
/*!
* @}
*/ /* end of group SIM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Masks SIM Register Masks
* @{
*/
/* SOPT1 Bit Fields */
#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
#define SIM_SOPT1_USBVSTBY_SHIFT 29
#define SIM_SOPT1_USBVSTBY_WIDTH 1
#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
#define SIM_SOPT1_USBSSTBY_SHIFT 30
#define SIM_SOPT1_USBSSTBY_WIDTH 1
#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
#define SIM_SOPT1_USBREGEN_SHIFT 31
#define SIM_SOPT1_USBREGEN_WIDTH 1
#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
/* SOPT1CFG Bit Fields */
#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
#define SIM_SOPT1CFG_URWE_SHIFT 24
#define SIM_SOPT1CFG_URWE_WIDTH 1
#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
#define SIM_SOPT1CFG_UVSWE_SHIFT 25
#define SIM_SOPT1CFG_UVSWE_WIDTH 1
#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
#define SIM_SOPT1CFG_USSWE_SHIFT 26
#define SIM_SOPT1CFG_USSWE_WIDTH 1
#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
/* SDID Bit Fields */
#define SIM_SDID_PINID_MASK 0xFu
#define SIM_SDID_PINID_SHIFT 0
#define SIM_SDID_PINID_WIDTH 4
#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
#define SIM_SDID_KEYATT_MASK 0x70u
#define SIM_SDID_KEYATT_SHIFT 4
#define SIM_SDID_KEYATT_WIDTH 3
#define SIM_SDID_KEYATT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_KEYATT_SHIFT))&SIM_SDID_KEYATT_MASK)
#define SIM_SDID_DIEID_MASK 0xF80u
#define SIM_SDID_DIEID_SHIFT 7
#define SIM_SDID_DIEID_WIDTH 5
#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
#define SIM_SDID_REVID_MASK 0xF000u
#define SIM_SDID_REVID_SHIFT 12
#define SIM_SDID_REVID_WIDTH 4
#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
#define SIM_SDID_SRAMSIZE_SHIFT 16
#define SIM_SDID_SRAMSIZE_WIDTH 4
#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
#define SIM_SDID_SERIESID_MASK 0xF00000u
#define SIM_SDID_SERIESID_SHIFT 20
#define SIM_SDID_SERIESID_WIDTH 4
#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
#define SIM_SDID_SUBFAMID_MASK 0xF000000u
#define SIM_SDID_SUBFAMID_SHIFT 24
#define SIM_SDID_SUBFAMID_WIDTH 4
#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
#define SIM_SDID_FAMID_MASK 0xF0000000u
#define SIM_SDID_FAMID_SHIFT 28
#define SIM_SDID_FAMID_WIDTH 4
#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
/* FCFG1 Bit Fields */
#define SIM_FCFG1_FLASHDIS_MASK 0x1u
#define SIM_FCFG1_FLASHDIS_SHIFT 0
#define SIM_FCFG1_FLASHDIS_WIDTH 1
#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
#define SIM_FCFG1_FLASHDOZE_SHIFT 1
#define SIM_FCFG1_FLASHDOZE_WIDTH 1
#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
#define SIM_FCFG1_PFSIZE_SHIFT 24
#define SIM_FCFG1_PFSIZE_WIDTH 4
#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
/* FCFG2 Bit Fields */
#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
#define SIM_FCFG2_MAXADDR1_SHIFT 16
#define SIM_FCFG2_MAXADDR1_WIDTH 7
#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
#define SIM_FCFG2_MAXADDR0_SHIFT 24
#define SIM_FCFG2_MAXADDR0_WIDTH 7
#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
/* UIDMH Bit Fields */
#define SIM_UIDMH_UID_MASK 0xFFFFu
#define SIM_UIDMH_UID_SHIFT 0
#define SIM_UIDMH_UID_WIDTH 16
#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
/* UIDML Bit Fields */
#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
#define SIM_UIDML_UID_SHIFT 0
#define SIM_UIDML_UID_WIDTH 32
#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
/* UIDL Bit Fields */
#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
#define SIM_UIDL_UID_SHIFT 0
#define SIM_UIDL_UID_WIDTH 32
#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
/*!
* @}
*/ /* end of group SIM_Register_Masks */
/* SIM - Peripheral instance base addresses */
/** Peripheral SIM base address */
#define SIM_BASE (0x40074000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
#define SIM_BASE_PTR (SIM)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS { SIM_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS { SIM }
/* ----------------------------------------------------------------------------
-- SIM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
* @{
*/
/* SIM - Register instance definitions */
/* SIM */
#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
#define SIM_SDID SIM_SDID_REG(SIM)
#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
#define SIM_UIDMH SIM_UIDMH_REG(SIM)
#define SIM_UIDML SIM_UIDML_REG(SIM)
#define SIM_UIDL SIM_UIDL_REG(SIM)
/*!
* @}
*/ /* end of group SIM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
* @{
*/
/** SMC - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< SMC Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< SMC Parameter Register, offset: 0x4 */
__IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */
__IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */
__IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
__I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */
} SMC_Type, *SMC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
* @{
*/
/* SMC - Register accessors */
#define SMC_VERID_REG(base) ((base)->VERID)
#define SMC_PARAM_REG(base) ((base)->PARAM)
#define SMC_PMPROT_REG(base) ((base)->PMPROT)
#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
/*!
* @}
*/ /* end of group SMC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Masks SMC Register Masks
* @{
*/
/* VERID Bit Fields */
#define SMC_VERID_FEATURE_MASK 0xFFFFu
#define SMC_VERID_FEATURE_SHIFT 0
#define SMC_VERID_FEATURE_WIDTH 16
#define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_FEATURE_SHIFT))&SMC_VERID_FEATURE_MASK)
#define SMC_VERID_MINOR_MASK 0xFF0000u
#define SMC_VERID_MINOR_SHIFT 16
#define SMC_VERID_MINOR_WIDTH 8
#define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MINOR_SHIFT))&SMC_VERID_MINOR_MASK)
#define SMC_VERID_MAJOR_MASK 0xFF000000u
#define SMC_VERID_MAJOR_SHIFT 24
#define SMC_VERID_MAJOR_WIDTH 8
#define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MAJOR_SHIFT))&SMC_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define SMC_PARAM_EHSRUN_MASK 0x1u
#define SMC_PARAM_EHSRUN_SHIFT 0
#define SMC_PARAM_EHSRUN_WIDTH 1
#define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EHSRUN_SHIFT))&SMC_PARAM_EHSRUN_MASK)
#define SMC_PARAM_ELLS_MASK 0x8u
#define SMC_PARAM_ELLS_SHIFT 3
#define SMC_PARAM_ELLS_WIDTH 1
#define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS_SHIFT))&SMC_PARAM_ELLS_MASK)
#define SMC_PARAM_ELLS2_MASK 0x20u
#define SMC_PARAM_ELLS2_SHIFT 5
#define SMC_PARAM_ELLS2_WIDTH 1
#define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS2_SHIFT))&SMC_PARAM_ELLS2_MASK)
#define SMC_PARAM_EVLLS0_MASK 0x40u
#define SMC_PARAM_EVLLS0_SHIFT 6
#define SMC_PARAM_EVLLS0_WIDTH 1
#define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EVLLS0_SHIFT))&SMC_PARAM_EVLLS0_MASK)
/* PMPROT Bit Fields */
#define SMC_PMPROT_AVLLS_MASK 0x2u
#define SMC_PMPROT_AVLLS_SHIFT 1
#define SMC_PMPROT_AVLLS_WIDTH 1
#define SMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
#define SMC_PMPROT_ALLS_MASK 0x8u
#define SMC_PMPROT_ALLS_SHIFT 3
#define SMC_PMPROT_ALLS_WIDTH 1
#define SMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
#define SMC_PMPROT_AVLP_MASK 0x20u
#define SMC_PMPROT_AVLP_SHIFT 5
#define SMC_PMPROT_AVLP_WIDTH 1
#define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
#define SMC_PMPROT_AHSRUN_MASK 0x80u
#define SMC_PMPROT_AHSRUN_SHIFT 7
#define SMC_PMPROT_AHSRUN_WIDTH 1
#define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AHSRUN_SHIFT))&SMC_PMPROT_AHSRUN_MASK)
/* PMCTRL Bit Fields */
#define SMC_PMCTRL_STOPM_MASK 0x7u
#define SMC_PMCTRL_STOPM_SHIFT 0
#define SMC_PMCTRL_STOPM_WIDTH 3
#define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
#define SMC_PMCTRL_STOPA_MASK 0x8u
#define SMC_PMCTRL_STOPA_SHIFT 3
#define SMC_PMCTRL_STOPA_WIDTH 1
#define SMC_PMCTRL_STOPA(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
#define SMC_PMCTRL_RUNM_MASK 0x60u
#define SMC_PMCTRL_RUNM_SHIFT 5
#define SMC_PMCTRL_RUNM_WIDTH 2
#define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
/* STOPCTRL Bit Fields */
#define SMC_STOPCTRL_LLSM_MASK 0x7u
#define SMC_STOPCTRL_LLSM_SHIFT 0
#define SMC_STOPCTRL_LLSM_WIDTH 3
#define SMC_STOPCTRL_LLSM(x) (((uint32_t)(((uint32_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
#define SMC_STOPCTRL_LPOPO_MASK 0x8u
#define SMC_STOPCTRL_LPOPO_SHIFT 3
#define SMC_STOPCTRL_LPOPO_WIDTH 1
#define SMC_STOPCTRL_LPOPO(x) (((uint32_t)(((uint32_t)(x))<<SMC_STOPCTRL_LPOPO_SHIFT))&SMC_STOPCTRL_LPOPO_MASK)
#define SMC_STOPCTRL_PORPO_MASK 0x20u
#define SMC_STOPCTRL_PORPO_SHIFT 5
#define SMC_STOPCTRL_PORPO_WIDTH 1
#define SMC_STOPCTRL_PORPO(x) (((uint32_t)(((uint32_t)(x))<<SMC_STOPCTRL_PORPO_SHIFT))&SMC_STOPCTRL_PORPO_MASK)
#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
#define SMC_STOPCTRL_PSTOPO_SHIFT 6
#define SMC_STOPCTRL_PSTOPO_WIDTH 2
#define SMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
/* PMSTAT Bit Fields */
#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
#define SMC_PMSTAT_PMSTAT_SHIFT 0
#define SMC_PMSTAT_PMSTAT_WIDTH 8
#define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
/*!
* @}
*/ /* end of group SMC_Register_Masks */
/* SMC - Peripheral instance base addresses */
/** Peripheral SMC base address */
#define SMC_BASE (0x4007E000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
#define SMC_BASE_PTR (SMC)
/** Array initializer of SMC peripheral base addresses */
#define SMC_BASE_ADDRS { SMC_BASE }
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASE_PTRS { SMC }
/* ----------------------------------------------------------------------------
-- SMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
* @{
*/
/* SMC - Register instance definitions */
/* SMC */
#define SMC_VERID SMC_VERID_REG(SMC)
#define SMC_PARAM SMC_PARAM_REG(SMC)
#define SMC_PMPROT SMC_PMPROT_REG(SMC)
#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
/*!
* @}
*/ /* end of group SMC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TPM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
* @{
*/
/** TPM - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t GLOBAL; /**< TPM Global Register, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t SC; /**< Status and Control, offset: 0x10 */
__IO uint32_t CNT; /**< Counter, offset: 0x14 */
__IO uint32_t MOD; /**< Modulo, offset: 0x18 */
__IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */
struct { /* offset: 0x20, array step: 0x8 */
__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
} CONTROLS[6];
uint8_t RESERVED_1[20];
__IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
uint8_t RESERVED_2[4];
__IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */
__IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
uint8_t RESERVED_3[4];
__IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
uint8_t RESERVED_4[4];
__IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
__IO uint32_t CONF; /**< Configuration, offset: 0x84 */
} TPM_Type, *TPM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TPM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
* @{
*/
/* TPM - Register accessors */
#define TPM_VERID_REG(base) ((base)->VERID)
#define TPM_PARAM_REG(base) ((base)->PARAM)
#define TPM_GLOBAL_REG(base) ((base)->GLOBAL)
#define TPM_SC_REG(base) ((base)->SC)
#define TPM_CNT_REG(base) ((base)->CNT)
#define TPM_MOD_REG(base) ((base)->MOD)
#define TPM_STATUS_REG(base) ((base)->STATUS)
#define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
#define TPM_CnSC_COUNT 6
#define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
#define TPM_CnV_COUNT 6
#define TPM_COMBINE_REG(base) ((base)->COMBINE)
#define TPM_TRIG_REG(base) ((base)->TRIG)
#define TPM_POL_REG(base) ((base)->POL)
#define TPM_FILTER_REG(base) ((base)->FILTER)
#define TPM_QDCTRL_REG(base) ((base)->QDCTRL)
#define TPM_CONF_REG(base) ((base)->CONF)
/*!
* @}
*/ /* end of group TPM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TPM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Register_Masks TPM Register Masks
* @{
*/
/* VERID Bit Fields */
#define TPM_VERID_FEATURE_MASK 0xFFFFu
#define TPM_VERID_FEATURE_SHIFT 0
#define TPM_VERID_FEATURE_WIDTH 16
#define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<TPM_VERID_FEATURE_SHIFT))&TPM_VERID_FEATURE_MASK)
#define TPM_VERID_MINOR_MASK 0xFF0000u
#define TPM_VERID_MINOR_SHIFT 16
#define TPM_VERID_MINOR_WIDTH 8
#define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<TPM_VERID_MINOR_SHIFT))&TPM_VERID_MINOR_MASK)
#define TPM_VERID_MAJOR_MASK 0xFF000000u
#define TPM_VERID_MAJOR_SHIFT 24
#define TPM_VERID_MAJOR_WIDTH 8
#define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<TPM_VERID_MAJOR_SHIFT))&TPM_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define TPM_PARAM_CHAN_MASK 0xFFu
#define TPM_PARAM_CHAN_SHIFT 0
#define TPM_PARAM_CHAN_WIDTH 8
#define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_CHAN_SHIFT))&TPM_PARAM_CHAN_MASK)
#define TPM_PARAM_TRIG_MASK 0xFF00u
#define TPM_PARAM_TRIG_SHIFT 8
#define TPM_PARAM_TRIG_WIDTH 8
#define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_TRIG_SHIFT))&TPM_PARAM_TRIG_MASK)
#define TPM_PARAM_WIDTH_MASK 0xFF0000u
#define TPM_PARAM_WIDTH_SHIFT 16
#define TPM_PARAM_WIDTH_WIDTH 8
#define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_WIDTH_SHIFT))&TPM_PARAM_WIDTH_MASK)
/* GLOBAL Bit Fields */
#define TPM_GLOBAL_RST_MASK 0x2u
#define TPM_GLOBAL_RST_SHIFT 1
#define TPM_GLOBAL_RST_WIDTH 1
#define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x))<<TPM_GLOBAL_RST_SHIFT))&TPM_GLOBAL_RST_MASK)
/* SC Bit Fields */
#define TPM_SC_PS_MASK 0x7u
#define TPM_SC_PS_SHIFT 0
#define TPM_SC_PS_WIDTH 3
#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
#define TPM_SC_CMOD_MASK 0x18u
#define TPM_SC_CMOD_SHIFT 3
#define TPM_SC_CMOD_WIDTH 2
#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
#define TPM_SC_CPWMS_MASK 0x20u
#define TPM_SC_CPWMS_SHIFT 5
#define TPM_SC_CPWMS_WIDTH 1
#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CPWMS_SHIFT))&TPM_SC_CPWMS_MASK)
#define TPM_SC_TOIE_MASK 0x40u
#define TPM_SC_TOIE_SHIFT 6
#define TPM_SC_TOIE_WIDTH 1
#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOIE_SHIFT))&TPM_SC_TOIE_MASK)
#define TPM_SC_TOF_MASK 0x80u
#define TPM_SC_TOF_SHIFT 7
#define TPM_SC_TOF_WIDTH 1
#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOF_SHIFT))&TPM_SC_TOF_MASK)
#define TPM_SC_DMA_MASK 0x100u
#define TPM_SC_DMA_SHIFT 8
#define TPM_SC_DMA_WIDTH 1
#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_DMA_SHIFT))&TPM_SC_DMA_MASK)
/* CNT Bit Fields */
#define TPM_CNT_COUNT_MASK 0xFFFFu
#define TPM_CNT_COUNT_SHIFT 0
#define TPM_CNT_COUNT_WIDTH 16
#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
/* MOD Bit Fields */
#define TPM_MOD_MOD_MASK 0xFFFFu
#define TPM_MOD_MOD_SHIFT 0
#define TPM_MOD_MOD_WIDTH 16
#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
/* STATUS Bit Fields */
#define TPM_STATUS_CH0F_MASK 0x1u
#define TPM_STATUS_CH0F_SHIFT 0
#define TPM_STATUS_CH0F_WIDTH 1
#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH0F_SHIFT))&TPM_STATUS_CH0F_MASK)
#define TPM_STATUS_CH1F_MASK 0x2u
#define TPM_STATUS_CH1F_SHIFT 1
#define TPM_STATUS_CH1F_WIDTH 1
#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH1F_SHIFT))&TPM_STATUS_CH1F_MASK)
#define TPM_STATUS_CH2F_MASK 0x4u
#define TPM_STATUS_CH2F_SHIFT 2
#define TPM_STATUS_CH2F_WIDTH 1
#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH2F_SHIFT))&TPM_STATUS_CH2F_MASK)
#define TPM_STATUS_CH3F_MASK 0x8u
#define TPM_STATUS_CH3F_SHIFT 3
#define TPM_STATUS_CH3F_WIDTH 1
#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH3F_SHIFT))&TPM_STATUS_CH3F_MASK)
#define TPM_STATUS_CH4F_MASK 0x10u
#define TPM_STATUS_CH4F_SHIFT 4
#define TPM_STATUS_CH4F_WIDTH 1
#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH4F_SHIFT))&TPM_STATUS_CH4F_MASK)
#define TPM_STATUS_CH5F_MASK 0x20u
#define TPM_STATUS_CH5F_SHIFT 5
#define TPM_STATUS_CH5F_WIDTH 1
#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH5F_SHIFT))&TPM_STATUS_CH5F_MASK)
#define TPM_STATUS_TOF_MASK 0x100u
#define TPM_STATUS_TOF_SHIFT 8
#define TPM_STATUS_TOF_WIDTH 1
#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_TOF_SHIFT))&TPM_STATUS_TOF_MASK)
/* CnSC Bit Fields */
#define TPM_CnSC_DMA_MASK 0x1u
#define TPM_CnSC_DMA_SHIFT 0
#define TPM_CnSC_DMA_WIDTH 1
#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_DMA_SHIFT))&TPM_CnSC_DMA_MASK)
#define TPM_CnSC_ELSA_MASK 0x4u
#define TPM_CnSC_ELSA_SHIFT 2
#define TPM_CnSC_ELSA_WIDTH 1
#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSA_SHIFT))&TPM_CnSC_ELSA_MASK)
#define TPM_CnSC_ELSB_MASK 0x8u
#define TPM_CnSC_ELSB_SHIFT 3
#define TPM_CnSC_ELSB_WIDTH 1
#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSB_SHIFT))&TPM_CnSC_ELSB_MASK)
#define TPM_CnSC_MSA_MASK 0x10u
#define TPM_CnSC_MSA_SHIFT 4
#define TPM_CnSC_MSA_WIDTH 1
#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSA_SHIFT))&TPM_CnSC_MSA_MASK)
#define TPM_CnSC_MSB_MASK 0x20u
#define TPM_CnSC_MSB_SHIFT 5
#define TPM_CnSC_MSB_WIDTH 1
#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSB_SHIFT))&TPM_CnSC_MSB_MASK)
#define TPM_CnSC_CHIE_MASK 0x40u
#define TPM_CnSC_CHIE_SHIFT 6
#define TPM_CnSC_CHIE_WIDTH 1
#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHIE_SHIFT))&TPM_CnSC_CHIE_MASK)
#define TPM_CnSC_CHF_MASK 0x80u
#define TPM_CnSC_CHF_SHIFT 7
#define TPM_CnSC_CHF_WIDTH 1
#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHF_SHIFT))&TPM_CnSC_CHF_MASK)
/* CnV Bit Fields */
#define TPM_CnV_VAL_MASK 0xFFFFu
#define TPM_CnV_VAL_SHIFT 0
#define TPM_CnV_VAL_WIDTH 16
#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
/* COMBINE Bit Fields */
#define TPM_COMBINE_COMBINE0_MASK 0x1u
#define TPM_COMBINE_COMBINE0_SHIFT 0
#define TPM_COMBINE_COMBINE0_WIDTH 1
#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE0_SHIFT))&TPM_COMBINE_COMBINE0_MASK)
#define TPM_COMBINE_COMSWAP0_MASK 0x2u
#define TPM_COMBINE_COMSWAP0_SHIFT 1
#define TPM_COMBINE_COMSWAP0_WIDTH 1
#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP0_SHIFT))&TPM_COMBINE_COMSWAP0_MASK)
#define TPM_COMBINE_COMBINE1_MASK 0x100u
#define TPM_COMBINE_COMBINE1_SHIFT 8
#define TPM_COMBINE_COMBINE1_WIDTH 1
#define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE1_SHIFT))&TPM_COMBINE_COMBINE1_MASK)
#define TPM_COMBINE_COMSWAP1_MASK 0x200u
#define TPM_COMBINE_COMSWAP1_SHIFT 9
#define TPM_COMBINE_COMSWAP1_WIDTH 1
#define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP1_SHIFT))&TPM_COMBINE_COMSWAP1_MASK)
#define TPM_COMBINE_COMBINE2_MASK 0x10000u
#define TPM_COMBINE_COMBINE2_SHIFT 16
#define TPM_COMBINE_COMBINE2_WIDTH 1
#define TPM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE2_SHIFT))&TPM_COMBINE_COMBINE2_MASK)
#define TPM_COMBINE_COMSWAP2_MASK 0x20000u
#define TPM_COMBINE_COMSWAP2_SHIFT 17
#define TPM_COMBINE_COMSWAP2_WIDTH 1
#define TPM_COMBINE_COMSWAP2(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP2_SHIFT))&TPM_COMBINE_COMSWAP2_MASK)
/* TRIG Bit Fields */
#define TPM_TRIG_TRIG0_MASK 0x1u
#define TPM_TRIG_TRIG0_SHIFT 0
#define TPM_TRIG_TRIG0_WIDTH 1
#define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG0_SHIFT))&TPM_TRIG_TRIG0_MASK)
#define TPM_TRIG_TRIG1_MASK 0x2u
#define TPM_TRIG_TRIG1_SHIFT 1
#define TPM_TRIG_TRIG1_WIDTH 1
#define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG1_SHIFT))&TPM_TRIG_TRIG1_MASK)
#define TPM_TRIG_TRIG2_MASK 0x4u
#define TPM_TRIG_TRIG2_SHIFT 2
#define TPM_TRIG_TRIG2_WIDTH 1
#define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG2_SHIFT))&TPM_TRIG_TRIG2_MASK)
#define TPM_TRIG_TRIG3_MASK 0x8u
#define TPM_TRIG_TRIG3_SHIFT 3
#define TPM_TRIG_TRIG3_WIDTH 1
#define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG3_SHIFT))&TPM_TRIG_TRIG3_MASK)
#define TPM_TRIG_TRIG4_MASK 0x10u
#define TPM_TRIG_TRIG4_SHIFT 4
#define TPM_TRIG_TRIG4_WIDTH 1
#define TPM_TRIG_TRIG4(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG4_SHIFT))&TPM_TRIG_TRIG4_MASK)
#define TPM_TRIG_TRIG5_MASK 0x20u
#define TPM_TRIG_TRIG5_SHIFT 5
#define TPM_TRIG_TRIG5_WIDTH 1
#define TPM_TRIG_TRIG5(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG5_SHIFT))&TPM_TRIG_TRIG5_MASK)
/* POL Bit Fields */
#define TPM_POL_POL0_MASK 0x1u
#define TPM_POL_POL0_SHIFT 0
#define TPM_POL_POL0_WIDTH 1
#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL0_SHIFT))&TPM_POL_POL0_MASK)
#define TPM_POL_POL1_MASK 0x2u
#define TPM_POL_POL1_SHIFT 1
#define TPM_POL_POL1_WIDTH 1
#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL1_SHIFT))&TPM_POL_POL1_MASK)
#define TPM_POL_POL2_MASK 0x4u
#define TPM_POL_POL2_SHIFT 2
#define TPM_POL_POL2_WIDTH 1
#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL2_SHIFT))&TPM_POL_POL2_MASK)
#define TPM_POL_POL3_MASK 0x8u
#define TPM_POL_POL3_SHIFT 3
#define TPM_POL_POL3_WIDTH 1
#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL3_SHIFT))&TPM_POL_POL3_MASK)
#define TPM_POL_POL4_MASK 0x10u
#define TPM_POL_POL4_SHIFT 4
#define TPM_POL_POL4_WIDTH 1
#define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL4_SHIFT))&TPM_POL_POL4_MASK)
#define TPM_POL_POL5_MASK 0x20u
#define TPM_POL_POL5_SHIFT 5
#define TPM_POL_POL5_WIDTH 1
#define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL5_SHIFT))&TPM_POL_POL5_MASK)
/* FILTER Bit Fields */
#define TPM_FILTER_CH0FVAL_MASK 0xFu
#define TPM_FILTER_CH0FVAL_SHIFT 0
#define TPM_FILTER_CH0FVAL_WIDTH 4
#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH0FVAL_SHIFT))&TPM_FILTER_CH0FVAL_MASK)
#define TPM_FILTER_CH1FVAL_MASK 0xF0u
#define TPM_FILTER_CH1FVAL_SHIFT 4
#define TPM_FILTER_CH1FVAL_WIDTH 4
#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH1FVAL_SHIFT))&TPM_FILTER_CH1FVAL_MASK)
#define TPM_FILTER_CH2FVAL_MASK 0xF00u
#define TPM_FILTER_CH2FVAL_SHIFT 8
#define TPM_FILTER_CH2FVAL_WIDTH 4
#define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH2FVAL_SHIFT))&TPM_FILTER_CH2FVAL_MASK)
#define TPM_FILTER_CH3FVAL_MASK 0xF000u
#define TPM_FILTER_CH3FVAL_SHIFT 12
#define TPM_FILTER_CH3FVAL_WIDTH 4
#define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH3FVAL_SHIFT))&TPM_FILTER_CH3FVAL_MASK)
#define TPM_FILTER_CH4FVAL_MASK 0xF0000u
#define TPM_FILTER_CH4FVAL_SHIFT 16
#define TPM_FILTER_CH4FVAL_WIDTH 4
#define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH4FVAL_SHIFT))&TPM_FILTER_CH4FVAL_MASK)
#define TPM_FILTER_CH5FVAL_MASK 0xF00000u
#define TPM_FILTER_CH5FVAL_SHIFT 20
#define TPM_FILTER_CH5FVAL_WIDTH 4
#define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH5FVAL_SHIFT))&TPM_FILTER_CH5FVAL_MASK)
/* QDCTRL Bit Fields */
#define TPM_QDCTRL_QUADEN_MASK 0x1u
#define TPM_QDCTRL_QUADEN_SHIFT 0
#define TPM_QDCTRL_QUADEN_WIDTH 1
#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADEN_SHIFT))&TPM_QDCTRL_QUADEN_MASK)
#define TPM_QDCTRL_TOFDIR_MASK 0x2u
#define TPM_QDCTRL_TOFDIR_SHIFT 1
#define TPM_QDCTRL_TOFDIR_WIDTH 1
#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_TOFDIR_SHIFT))&TPM_QDCTRL_TOFDIR_MASK)
#define TPM_QDCTRL_QUADIR_MASK 0x4u
#define TPM_QDCTRL_QUADIR_SHIFT 2
#define TPM_QDCTRL_QUADIR_WIDTH 1
#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADIR_SHIFT))&TPM_QDCTRL_QUADIR_MASK)
#define TPM_QDCTRL_QUADMODE_MASK 0x8u
#define TPM_QDCTRL_QUADMODE_SHIFT 3
#define TPM_QDCTRL_QUADMODE_WIDTH 1
#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADMODE_SHIFT))&TPM_QDCTRL_QUADMODE_MASK)
/* CONF Bit Fields */
#define TPM_CONF_DOZEEN_MASK 0x20u
#define TPM_CONF_DOZEEN_SHIFT 5
#define TPM_CONF_DOZEEN_WIDTH 1
#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DOZEEN_SHIFT))&TPM_CONF_DOZEEN_MASK)
#define TPM_CONF_DBGMODE_MASK 0xC0u
#define TPM_CONF_DBGMODE_SHIFT 6
#define TPM_CONF_DBGMODE_WIDTH 2
#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
#define TPM_CONF_GTBSYNC_MASK 0x100u
#define TPM_CONF_GTBSYNC_SHIFT 8
#define TPM_CONF_GTBSYNC_WIDTH 1
#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBSYNC_SHIFT))&TPM_CONF_GTBSYNC_MASK)
#define TPM_CONF_GTBEEN_MASK 0x200u
#define TPM_CONF_GTBEEN_SHIFT 9
#define TPM_CONF_GTBEEN_WIDTH 1
#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBEEN_SHIFT))&TPM_CONF_GTBEEN_MASK)
#define TPM_CONF_CSOT_MASK 0x10000u
#define TPM_CONF_CSOT_SHIFT 16
#define TPM_CONF_CSOT_WIDTH 1
#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOT_SHIFT))&TPM_CONF_CSOT_MASK)
#define TPM_CONF_CSOO_MASK 0x20000u
#define TPM_CONF_CSOO_SHIFT 17
#define TPM_CONF_CSOO_WIDTH 1
#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOO_SHIFT))&TPM_CONF_CSOO_MASK)
#define TPM_CONF_CROT_MASK 0x40000u
#define TPM_CONF_CROT_SHIFT 18
#define TPM_CONF_CROT_WIDTH 1
#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CROT_SHIFT))&TPM_CONF_CROT_MASK)
#define TPM_CONF_CPOT_MASK 0x80000u
#define TPM_CONF_CPOT_SHIFT 19
#define TPM_CONF_CPOT_WIDTH 1
#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CPOT_SHIFT))&TPM_CONF_CPOT_MASK)
#define TPM_CONF_TRGPOL_MASK 0x400000u
#define TPM_CONF_TRGPOL_SHIFT 22
#define TPM_CONF_TRGPOL_WIDTH 1
#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGPOL_SHIFT))&TPM_CONF_TRGPOL_MASK)
#define TPM_CONF_TRGSRC_MASK 0x800000u
#define TPM_CONF_TRGSRC_SHIFT 23
#define TPM_CONF_TRGSRC_WIDTH 1
#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSRC_SHIFT))&TPM_CONF_TRGSRC_MASK)
#define TPM_CONF_TRGSEL_MASK 0xF000000u
#define TPM_CONF_TRGSEL_SHIFT 24
#define TPM_CONF_TRGSEL_WIDTH 4
#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
/*!
* @}
*/ /* end of group TPM_Register_Masks */
/* TPM - Peripheral instance base addresses */
/** Peripheral TPM0 base address */
#define TPM0_BASE (0x400AC000u)
/** Peripheral TPM0 base pointer */
#define TPM0 ((TPM_Type *)TPM0_BASE)
#define TPM0_BASE_PTR (TPM0)
/** Peripheral TPM1 base address */
#define TPM1_BASE (0x400AD000u)
/** Peripheral TPM1 base pointer */
#define TPM1 ((TPM_Type *)TPM1_BASE)
#define TPM1_BASE_PTR (TPM1)
/** Peripheral TPM2 base address */
#define TPM2_BASE (0x4002E000u)
/** Peripheral TPM2 base pointer */
#define TPM2 ((TPM_Type *)TPM2_BASE)
#define TPM2_BASE_PTR (TPM2)
/** Array initializer of TPM peripheral base addresses */
#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
/** Array initializer of TPM peripheral base pointers */
#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
/* ----------------------------------------------------------------------------
-- TPM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
* @{
*/
/* TPM - Register instance definitions */
/* TPM0 */
#define TPM0_VERID TPM_VERID_REG(TPM0)
#define TPM0_PARAM TPM_PARAM_REG(TPM0)
#define TPM0_GLOBAL TPM_GLOBAL_REG(TPM0)
#define TPM0_SC TPM_SC_REG(TPM0)
#define TPM0_CNT TPM_CNT_REG(TPM0)
#define TPM0_MOD TPM_MOD_REG(TPM0)
#define TPM0_STATUS TPM_STATUS_REG(TPM0)
#define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
#define TPM0_C0V TPM_CnV_REG(TPM0,0)
#define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
#define TPM0_C1V TPM_CnV_REG(TPM0,1)
#define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
#define TPM0_C2V TPM_CnV_REG(TPM0,2)
#define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
#define TPM0_C3V TPM_CnV_REG(TPM0,3)
#define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
#define TPM0_C4V TPM_CnV_REG(TPM0,4)
#define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
#define TPM0_C5V TPM_CnV_REG(TPM0,5)
#define TPM0_COMBINE TPM_COMBINE_REG(TPM0)
#define TPM0_TRIG TPM_TRIG_REG(TPM0)
#define TPM0_POL TPM_POL_REG(TPM0)
#define TPM0_FILTER TPM_FILTER_REG(TPM0)
#define TPM0_QDCTRL TPM_QDCTRL_REG(TPM0)
#define TPM0_CONF TPM_CONF_REG(TPM0)
/* TPM1 */
#define TPM1_VERID TPM_VERID_REG(TPM1)
#define TPM1_PARAM TPM_PARAM_REG(TPM1)
#define TPM1_GLOBAL TPM_GLOBAL_REG(TPM1)
#define TPM1_SC TPM_SC_REG(TPM1)
#define TPM1_CNT TPM_CNT_REG(TPM1)
#define TPM1_MOD TPM_MOD_REG(TPM1)
#define TPM1_STATUS TPM_STATUS_REG(TPM1)
#define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
#define TPM1_C0V TPM_CnV_REG(TPM1,0)
#define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
#define TPM1_C1V TPM_CnV_REG(TPM1,1)
#define TPM1_COMBINE TPM_COMBINE_REG(TPM1)
#define TPM1_TRIG TPM_TRIG_REG(TPM1)
#define TPM1_POL TPM_POL_REG(TPM1)
#define TPM1_FILTER TPM_FILTER_REG(TPM1)
#define TPM1_QDCTRL TPM_QDCTRL_REG(TPM1)
#define TPM1_CONF TPM_CONF_REG(TPM1)
/* TPM2 */
#define TPM2_VERID TPM_VERID_REG(TPM2)
#define TPM2_PARAM TPM_PARAM_REG(TPM2)
#define TPM2_GLOBAL TPM_GLOBAL_REG(TPM2)
#define TPM2_SC TPM_SC_REG(TPM2)
#define TPM2_CNT TPM_CNT_REG(TPM2)
#define TPM2_MOD TPM_MOD_REG(TPM2)
#define TPM2_STATUS TPM_STATUS_REG(TPM2)
#define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
#define TPM2_C0V TPM_CnV_REG(TPM2,0)
#define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
#define TPM2_C1V TPM_CnV_REG(TPM2,1)
#define TPM2_COMBINE TPM_COMBINE_REG(TPM2)
#define TPM2_TRIG TPM_TRIG_REG(TPM2)
#define TPM2_POL TPM_POL_REG(TPM2)
#define TPM2_FILTER TPM_FILTER_REG(TPM2)
#define TPM2_QDCTRL TPM_QDCTRL_REG(TPM2)
#define TPM2_CONF TPM_CONF_REG(TPM2)
/* TPM - Register array accessors */
#define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
#define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
#define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
#define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
#define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
#define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
/*!
* @}
*/ /* end of group TPM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group TPM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TRGMUX0 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX0_Peripheral_Access_Layer TRGMUX0 Peripheral Access Layer
* @{
*/
/** TRGMUX0 - Register Layout Typedef */
typedef struct {
__IO uint32_t TRGMUX_DMAMUX0; /**< TRGMUX TRGCFG Register, offset: 0x0 */
__IO uint32_t TRGMUX_LPIT0; /**< TRGMUX TRGCFG Register, offset: 0x4 */
__IO uint32_t TRGMUX_TPM2; /**< TRGMUX TRGCFG Register, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t TRGMUX_ADC0; /**< TRGMUX TRGCFG Register, offset: 0x10 */
__IO uint32_t TRGMUX_LPUART2; /**< TRGMUX TRGCFG Register, offset: 0x14 */
uint8_t RESERVED_1[4];
__IO uint32_t TRGMUX_LPI2C2; /**< TRGMUX TRGCFG Register, offset: 0x1C */
uint8_t RESERVED_2[4];
__IO uint32_t TRGMUX_LPSPI2; /**< TRGMUX TRGCFG Register, offset: 0x24 */
uint8_t RESERVED_3[4];
__IO uint32_t TRGMUX_CMP0; /**< TRGMUX TRGCFG Register, offset: 0x2C */
__IO uint32_t TRGMUX_CMP1; /**< TRGMUX TRGCFG Register, offset: 0x30 */
__IO uint32_t TRGMUX_DAC0; /**< TRGMUX TRGCFG Register, offset: 0x34 */
} TRGMUX0_Type, *TRGMUX0_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TRGMUX0 - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX0_Register_Accessor_Macros TRGMUX0 - Register accessor macros
* @{
*/
/* TRGMUX0 - Register accessors */
#define TRGMUX0_TRGMUX_DMAMUX0_REG(base) ((base)->TRGMUX_DMAMUX0)
#define TRGMUX0_TRGMUX_LPIT0_REG(base) ((base)->TRGMUX_LPIT0)
#define TRGMUX0_TRGMUX_TPM2_REG(base) ((base)->TRGMUX_TPM2)
#define TRGMUX0_TRGMUX_ADC0_REG(base) ((base)->TRGMUX_ADC0)
#define TRGMUX0_TRGMUX_LPUART2_REG(base) ((base)->TRGMUX_LPUART2)
#define TRGMUX0_TRGMUX_LPI2C2_REG(base) ((base)->TRGMUX_LPI2C2)
#define TRGMUX0_TRGMUX_LPSPI2_REG(base) ((base)->TRGMUX_LPSPI2)
#define TRGMUX0_TRGMUX_CMP0_REG(base) ((base)->TRGMUX_CMP0)
#define TRGMUX0_TRGMUX_CMP1_REG(base) ((base)->TRGMUX_CMP1)
#define TRGMUX0_TRGMUX_DAC0_REG(base) ((base)->TRGMUX_DAC0)
/*!
* @}
*/ /* end of group TRGMUX0_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TRGMUX0 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX0_Register_Masks TRGMUX0 Register Masks
* @{
*/
/* TRGMUX_DMAMUX0 Bit Fields */
#define TRGMUX0_TRGMUX_DMAMUX0_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_DMAMUX0_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_DMAMUX0_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_DMAMUX0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_DMAMUX0_SEL0_SHIFT))&TRGMUX0_TRGMUX_DMAMUX0_SEL0_MASK)
#define TRGMUX0_TRGMUX_DMAMUX0_SEL1_MASK 0x3F00u
#define TRGMUX0_TRGMUX_DMAMUX0_SEL1_SHIFT 8
#define TRGMUX0_TRGMUX_DMAMUX0_SEL1_WIDTH 6
#define TRGMUX0_TRGMUX_DMAMUX0_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_DMAMUX0_SEL1_SHIFT))&TRGMUX0_TRGMUX_DMAMUX0_SEL1_MASK)
#define TRGMUX0_TRGMUX_DMAMUX0_SEL2_MASK 0x3F0000u
#define TRGMUX0_TRGMUX_DMAMUX0_SEL2_SHIFT 16
#define TRGMUX0_TRGMUX_DMAMUX0_SEL2_WIDTH 6
#define TRGMUX0_TRGMUX_DMAMUX0_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_DMAMUX0_SEL2_SHIFT))&TRGMUX0_TRGMUX_DMAMUX0_SEL2_MASK)
#define TRGMUX0_TRGMUX_DMAMUX0_SEL3_MASK 0x3F000000u
#define TRGMUX0_TRGMUX_DMAMUX0_SEL3_SHIFT 24
#define TRGMUX0_TRGMUX_DMAMUX0_SEL3_WIDTH 6
#define TRGMUX0_TRGMUX_DMAMUX0_SEL3(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_DMAMUX0_SEL3_SHIFT))&TRGMUX0_TRGMUX_DMAMUX0_SEL3_MASK)
#define TRGMUX0_TRGMUX_DMAMUX0_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_DMAMUX0_LK_SHIFT 31
#define TRGMUX0_TRGMUX_DMAMUX0_LK_WIDTH 1
#define TRGMUX0_TRGMUX_DMAMUX0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_DMAMUX0_LK_SHIFT))&TRGMUX0_TRGMUX_DMAMUX0_LK_MASK)
/* TRGMUX_LPIT0 Bit Fields */
#define TRGMUX0_TRGMUX_LPIT0_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_LPIT0_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_LPIT0_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_LPIT0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPIT0_SEL0_SHIFT))&TRGMUX0_TRGMUX_LPIT0_SEL0_MASK)
#define TRGMUX0_TRGMUX_LPIT0_SEL1_MASK 0x3F00u
#define TRGMUX0_TRGMUX_LPIT0_SEL1_SHIFT 8
#define TRGMUX0_TRGMUX_LPIT0_SEL1_WIDTH 6
#define TRGMUX0_TRGMUX_LPIT0_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPIT0_SEL1_SHIFT))&TRGMUX0_TRGMUX_LPIT0_SEL1_MASK)
#define TRGMUX0_TRGMUX_LPIT0_SEL2_MASK 0x3F0000u
#define TRGMUX0_TRGMUX_LPIT0_SEL2_SHIFT 16
#define TRGMUX0_TRGMUX_LPIT0_SEL2_WIDTH 6
#define TRGMUX0_TRGMUX_LPIT0_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPIT0_SEL2_SHIFT))&TRGMUX0_TRGMUX_LPIT0_SEL2_MASK)
#define TRGMUX0_TRGMUX_LPIT0_SEL3_MASK 0x3F000000u
#define TRGMUX0_TRGMUX_LPIT0_SEL3_SHIFT 24
#define TRGMUX0_TRGMUX_LPIT0_SEL3_WIDTH 6
#define TRGMUX0_TRGMUX_LPIT0_SEL3(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPIT0_SEL3_SHIFT))&TRGMUX0_TRGMUX_LPIT0_SEL3_MASK)
#define TRGMUX0_TRGMUX_LPIT0_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_LPIT0_LK_SHIFT 31
#define TRGMUX0_TRGMUX_LPIT0_LK_WIDTH 1
#define TRGMUX0_TRGMUX_LPIT0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPIT0_LK_SHIFT))&TRGMUX0_TRGMUX_LPIT0_LK_MASK)
/* TRGMUX_TPM2 Bit Fields */
#define TRGMUX0_TRGMUX_TPM2_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_TPM2_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_TPM2_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_TPM2_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_TPM2_SEL0_SHIFT))&TRGMUX0_TRGMUX_TPM2_SEL0_MASK)
#define TRGMUX0_TRGMUX_TPM2_SEL1_MASK 0x3F00u
#define TRGMUX0_TRGMUX_TPM2_SEL1_SHIFT 8
#define TRGMUX0_TRGMUX_TPM2_SEL1_WIDTH 6
#define TRGMUX0_TRGMUX_TPM2_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_TPM2_SEL1_SHIFT))&TRGMUX0_TRGMUX_TPM2_SEL1_MASK)
#define TRGMUX0_TRGMUX_TPM2_SEL2_MASK 0x3F0000u
#define TRGMUX0_TRGMUX_TPM2_SEL2_SHIFT 16
#define TRGMUX0_TRGMUX_TPM2_SEL2_WIDTH 6
#define TRGMUX0_TRGMUX_TPM2_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_TPM2_SEL2_SHIFT))&TRGMUX0_TRGMUX_TPM2_SEL2_MASK)
#define TRGMUX0_TRGMUX_TPM2_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_TPM2_LK_SHIFT 31
#define TRGMUX0_TRGMUX_TPM2_LK_WIDTH 1
#define TRGMUX0_TRGMUX_TPM2_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_TPM2_LK_SHIFT))&TRGMUX0_TRGMUX_TPM2_LK_MASK)
/* TRGMUX_ADC0 Bit Fields */
#define TRGMUX0_TRGMUX_ADC0_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_ADC0_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_ADC0_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_ADC0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_ADC0_SEL0_SHIFT))&TRGMUX0_TRGMUX_ADC0_SEL0_MASK)
#define TRGMUX0_TRGMUX_ADC0_SEL1_MASK 0x3F00u
#define TRGMUX0_TRGMUX_ADC0_SEL1_SHIFT 8
#define TRGMUX0_TRGMUX_ADC0_SEL1_WIDTH 6
#define TRGMUX0_TRGMUX_ADC0_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_ADC0_SEL1_SHIFT))&TRGMUX0_TRGMUX_ADC0_SEL1_MASK)
#define TRGMUX0_TRGMUX_ADC0_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_ADC0_LK_SHIFT 31
#define TRGMUX0_TRGMUX_ADC0_LK_WIDTH 1
#define TRGMUX0_TRGMUX_ADC0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_ADC0_LK_SHIFT))&TRGMUX0_TRGMUX_ADC0_LK_MASK)
/* TRGMUX_LPUART2 Bit Fields */
#define TRGMUX0_TRGMUX_LPUART2_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_LPUART2_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_LPUART2_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_LPUART2_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPUART2_SEL0_SHIFT))&TRGMUX0_TRGMUX_LPUART2_SEL0_MASK)
#define TRGMUX0_TRGMUX_LPUART2_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_LPUART2_LK_SHIFT 31
#define TRGMUX0_TRGMUX_LPUART2_LK_WIDTH 1
#define TRGMUX0_TRGMUX_LPUART2_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPUART2_LK_SHIFT))&TRGMUX0_TRGMUX_LPUART2_LK_MASK)
/* TRGMUX_LPI2C2 Bit Fields */
#define TRGMUX0_TRGMUX_LPI2C2_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_LPI2C2_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_LPI2C2_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_LPI2C2_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPI2C2_SEL0_SHIFT))&TRGMUX0_TRGMUX_LPI2C2_SEL0_MASK)
#define TRGMUX0_TRGMUX_LPI2C2_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_LPI2C2_LK_SHIFT 31
#define TRGMUX0_TRGMUX_LPI2C2_LK_WIDTH 1
#define TRGMUX0_TRGMUX_LPI2C2_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPI2C2_LK_SHIFT))&TRGMUX0_TRGMUX_LPI2C2_LK_MASK)
/* TRGMUX_LPSPI2 Bit Fields */
#define TRGMUX0_TRGMUX_LPSPI2_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_LPSPI2_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_LPSPI2_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_LPSPI2_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPSPI2_SEL0_SHIFT))&TRGMUX0_TRGMUX_LPSPI2_SEL0_MASK)
#define TRGMUX0_TRGMUX_LPSPI2_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_LPSPI2_LK_SHIFT 31
#define TRGMUX0_TRGMUX_LPSPI2_LK_WIDTH 1
#define TRGMUX0_TRGMUX_LPSPI2_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_LPSPI2_LK_SHIFT))&TRGMUX0_TRGMUX_LPSPI2_LK_MASK)
/* TRGMUX_CMP0 Bit Fields */
#define TRGMUX0_TRGMUX_CMP0_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_CMP0_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_CMP0_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_CMP0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_CMP0_SEL0_SHIFT))&TRGMUX0_TRGMUX_CMP0_SEL0_MASK)
#define TRGMUX0_TRGMUX_CMP0_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_CMP0_LK_SHIFT 31
#define TRGMUX0_TRGMUX_CMP0_LK_WIDTH 1
#define TRGMUX0_TRGMUX_CMP0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_CMP0_LK_SHIFT))&TRGMUX0_TRGMUX_CMP0_LK_MASK)
/* TRGMUX_CMP1 Bit Fields */
#define TRGMUX0_TRGMUX_CMP1_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_CMP1_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_CMP1_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_CMP1_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_CMP1_SEL0_SHIFT))&TRGMUX0_TRGMUX_CMP1_SEL0_MASK)
#define TRGMUX0_TRGMUX_CMP1_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_CMP1_LK_SHIFT 31
#define TRGMUX0_TRGMUX_CMP1_LK_WIDTH 1
#define TRGMUX0_TRGMUX_CMP1_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_CMP1_LK_SHIFT))&TRGMUX0_TRGMUX_CMP1_LK_MASK)
/* TRGMUX_DAC0 Bit Fields */
#define TRGMUX0_TRGMUX_DAC0_SEL0_MASK 0x3Fu
#define TRGMUX0_TRGMUX_DAC0_SEL0_SHIFT 0
#define TRGMUX0_TRGMUX_DAC0_SEL0_WIDTH 6
#define TRGMUX0_TRGMUX_DAC0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_DAC0_SEL0_SHIFT))&TRGMUX0_TRGMUX_DAC0_SEL0_MASK)
#define TRGMUX0_TRGMUX_DAC0_LK_MASK 0x80000000u
#define TRGMUX0_TRGMUX_DAC0_LK_SHIFT 31
#define TRGMUX0_TRGMUX_DAC0_LK_WIDTH 1
#define TRGMUX0_TRGMUX_DAC0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX0_TRGMUX_DAC0_LK_SHIFT))&TRGMUX0_TRGMUX_DAC0_LK_MASK)
/*!
* @}
*/ /* end of group TRGMUX0_Register_Masks */
/* TRGMUX0 - Peripheral instance base addresses */
/** Peripheral TRGMUX0 base address */
#define TRGMUX0_BASE (0x40027000u)
/** Peripheral TRGMUX0 base pointer */
#define TRGMUX0 ((TRGMUX0_Type *)TRGMUX0_BASE)
#define TRGMUX0_BASE_PTR (TRGMUX0)
/** Array initializer of TRGMUX0 peripheral base addresses */
#define TRGMUX0_BASE_ADDRS { TRGMUX0_BASE }
/** Array initializer of TRGMUX0 peripheral base pointers */
#define TRGMUX0_BASE_PTRS { TRGMUX0 }
/* ----------------------------------------------------------------------------
-- TRGMUX0 - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX0_Register_Accessor_Macros TRGMUX0 - Register accessor macros
* @{
*/
/* TRGMUX0 - Register instance definitions */
/* TRGMUX0 */
#define TRGMUX_TRGMUX_DMAMUX0 TRGMUX0_TRGMUX_DMAMUX0_REG(TRGMUX0)
#define TRGMUX_TRGMUX_LPIT0 TRGMUX0_TRGMUX_LPIT0_REG(TRGMUX0)
#define TRGMUX_TRGMUX_TPM2 TRGMUX0_TRGMUX_TPM2_REG(TRGMUX0)
#define TRGMUX_TRGMUX_ADC0 TRGMUX0_TRGMUX_ADC0_REG(TRGMUX0)
#define TRGMUX_TRGMUX_LPUART2 TRGMUX0_TRGMUX_LPUART2_REG(TRGMUX0)
#define TRGMUX_TRGMUX_LPI2C2 TRGMUX0_TRGMUX_LPI2C2_REG(TRGMUX0)
#define TRGMUX_TRGMUX_LPSPI2 TRGMUX0_TRGMUX_LPSPI2_REG(TRGMUX0)
#define TRGMUX_TRGMUX_CMP0 TRGMUX0_TRGMUX_CMP0_REG(TRGMUX0)
#define TRGMUX_TRGMUX_CMP1 TRGMUX0_TRGMUX_CMP1_REG(TRGMUX0)
#define TRGMUX_TRGMUX_DAC0 TRGMUX0_TRGMUX_DAC0_REG(TRGMUX0)
/*!
* @}
*/ /* end of group TRGMUX0_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group TRGMUX0_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TRGMUX1 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX1_Peripheral_Access_Layer TRGMUX1 Peripheral Access Layer
* @{
*/
/** TRGMUX1 - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__IO uint32_t TRGMUX_TPM0; /**< TRGMUX TRGCFG Register, offset: 0x8 */
__IO uint32_t TRGMUX_TPM1; /**< TRGMUX TRGCFG Register, offset: 0xC */
__IO uint32_t TRGMUX_FLEXIO0; /**< TRGMUX TRGCFG Register, offset: 0x10 */
__IO uint32_t TRGMUX_LPUART0; /**< TRGMUX TRGCFG Register, offset: 0x14 */
__IO uint32_t TRGMUX_LPUART1; /**< TRGMUX TRGCFG Register, offset: 0x18 */
__IO uint32_t TRGMUX_LPI2C0; /**< TRGMUX TRGCFG Register, offset: 0x1C */
__IO uint32_t TRGMUX_LPI2C1; /**< TRGMUX TRGCFG Register, offset: 0x20 */
__IO uint32_t TRGMUX_LPSPI0; /**< TRGMUX TRGCFG Register, offset: 0x24 */
__IO uint32_t TRGMUX_LPSPI1; /**< TRGMUX TRGCFG Register, offset: 0x28 */
} TRGMUX1_Type, *TRGMUX1_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TRGMUX1 - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX1_Register_Accessor_Macros TRGMUX1 - Register accessor macros
* @{
*/
/* TRGMUX1 - Register accessors */
#define TRGMUX1_TRGMUX_TPM0_REG(base) ((base)->TRGMUX_TPM0)
#define TRGMUX1_TRGMUX_TPM1_REG(base) ((base)->TRGMUX_TPM1)
#define TRGMUX1_TRGMUX_FLEXIO0_REG(base) ((base)->TRGMUX_FLEXIO0)
#define TRGMUX1_TRGMUX_LPUART0_REG(base) ((base)->TRGMUX_LPUART0)
#define TRGMUX1_TRGMUX_LPUART1_REG(base) ((base)->TRGMUX_LPUART1)
#define TRGMUX1_TRGMUX_LPI2C0_REG(base) ((base)->TRGMUX_LPI2C0)
#define TRGMUX1_TRGMUX_LPI2C1_REG(base) ((base)->TRGMUX_LPI2C1)
#define TRGMUX1_TRGMUX_LPSPI0_REG(base) ((base)->TRGMUX_LPSPI0)
#define TRGMUX1_TRGMUX_LPSPI1_REG(base) ((base)->TRGMUX_LPSPI1)
/*!
* @}
*/ /* end of group TRGMUX1_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TRGMUX1 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX1_Register_Masks TRGMUX1 Register Masks
* @{
*/
/* TRGMUX_TPM0 Bit Fields */
#define TRGMUX1_TRGMUX_TPM0_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_TPM0_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_TPM0_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_TPM0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_TPM0_SEL0_SHIFT))&TRGMUX1_TRGMUX_TPM0_SEL0_MASK)
#define TRGMUX1_TRGMUX_TPM0_SEL1_MASK 0x3F00u
#define TRGMUX1_TRGMUX_TPM0_SEL1_SHIFT 8
#define TRGMUX1_TRGMUX_TPM0_SEL1_WIDTH 6
#define TRGMUX1_TRGMUX_TPM0_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_TPM0_SEL1_SHIFT))&TRGMUX1_TRGMUX_TPM0_SEL1_MASK)
#define TRGMUX1_TRGMUX_TPM0_SEL2_MASK 0x3F0000u
#define TRGMUX1_TRGMUX_TPM0_SEL2_SHIFT 16
#define TRGMUX1_TRGMUX_TPM0_SEL2_WIDTH 6
#define TRGMUX1_TRGMUX_TPM0_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_TPM0_SEL2_SHIFT))&TRGMUX1_TRGMUX_TPM0_SEL2_MASK)
#define TRGMUX1_TRGMUX_TPM0_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_TPM0_LK_SHIFT 31
#define TRGMUX1_TRGMUX_TPM0_LK_WIDTH 1
#define TRGMUX1_TRGMUX_TPM0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_TPM0_LK_SHIFT))&TRGMUX1_TRGMUX_TPM0_LK_MASK)
/* TRGMUX_TPM1 Bit Fields */
#define TRGMUX1_TRGMUX_TPM1_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_TPM1_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_TPM1_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_TPM1_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_TPM1_SEL0_SHIFT))&TRGMUX1_TRGMUX_TPM1_SEL0_MASK)
#define TRGMUX1_TRGMUX_TPM1_SEL1_MASK 0x3F00u
#define TRGMUX1_TRGMUX_TPM1_SEL1_SHIFT 8
#define TRGMUX1_TRGMUX_TPM1_SEL1_WIDTH 6
#define TRGMUX1_TRGMUX_TPM1_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_TPM1_SEL1_SHIFT))&TRGMUX1_TRGMUX_TPM1_SEL1_MASK)
#define TRGMUX1_TRGMUX_TPM1_SEL2_MASK 0x3F0000u
#define TRGMUX1_TRGMUX_TPM1_SEL2_SHIFT 16
#define TRGMUX1_TRGMUX_TPM1_SEL2_WIDTH 6
#define TRGMUX1_TRGMUX_TPM1_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_TPM1_SEL2_SHIFT))&TRGMUX1_TRGMUX_TPM1_SEL2_MASK)
#define TRGMUX1_TRGMUX_TPM1_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_TPM1_LK_SHIFT 31
#define TRGMUX1_TRGMUX_TPM1_LK_WIDTH 1
#define TRGMUX1_TRGMUX_TPM1_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_TPM1_LK_SHIFT))&TRGMUX1_TRGMUX_TPM1_LK_MASK)
/* TRGMUX_FLEXIO0 Bit Fields */
#define TRGMUX1_TRGMUX_FLEXIO0_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_FLEXIO0_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_FLEXIO0_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_FLEXIO0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_FLEXIO0_SEL0_SHIFT))&TRGMUX1_TRGMUX_FLEXIO0_SEL0_MASK)
#define TRGMUX1_TRGMUX_FLEXIO0_SEL1_MASK 0x3F00u
#define TRGMUX1_TRGMUX_FLEXIO0_SEL1_SHIFT 8
#define TRGMUX1_TRGMUX_FLEXIO0_SEL1_WIDTH 6
#define TRGMUX1_TRGMUX_FLEXIO0_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_FLEXIO0_SEL1_SHIFT))&TRGMUX1_TRGMUX_FLEXIO0_SEL1_MASK)
#define TRGMUX1_TRGMUX_FLEXIO0_SEL2_MASK 0x3F0000u
#define TRGMUX1_TRGMUX_FLEXIO0_SEL2_SHIFT 16
#define TRGMUX1_TRGMUX_FLEXIO0_SEL2_WIDTH 6
#define TRGMUX1_TRGMUX_FLEXIO0_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_FLEXIO0_SEL2_SHIFT))&TRGMUX1_TRGMUX_FLEXIO0_SEL2_MASK)
#define TRGMUX1_TRGMUX_FLEXIO0_SEL3_MASK 0x3F000000u
#define TRGMUX1_TRGMUX_FLEXIO0_SEL3_SHIFT 24
#define TRGMUX1_TRGMUX_FLEXIO0_SEL3_WIDTH 6
#define TRGMUX1_TRGMUX_FLEXIO0_SEL3(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_FLEXIO0_SEL3_SHIFT))&TRGMUX1_TRGMUX_FLEXIO0_SEL3_MASK)
#define TRGMUX1_TRGMUX_FLEXIO0_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_FLEXIO0_LK_SHIFT 31
#define TRGMUX1_TRGMUX_FLEXIO0_LK_WIDTH 1
#define TRGMUX1_TRGMUX_FLEXIO0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_FLEXIO0_LK_SHIFT))&TRGMUX1_TRGMUX_FLEXIO0_LK_MASK)
/* TRGMUX_LPUART0 Bit Fields */
#define TRGMUX1_TRGMUX_LPUART0_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_LPUART0_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_LPUART0_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_LPUART0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPUART0_SEL0_SHIFT))&TRGMUX1_TRGMUX_LPUART0_SEL0_MASK)
#define TRGMUX1_TRGMUX_LPUART0_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_LPUART0_LK_SHIFT 31
#define TRGMUX1_TRGMUX_LPUART0_LK_WIDTH 1
#define TRGMUX1_TRGMUX_LPUART0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPUART0_LK_SHIFT))&TRGMUX1_TRGMUX_LPUART0_LK_MASK)
/* TRGMUX_LPUART1 Bit Fields */
#define TRGMUX1_TRGMUX_LPUART1_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_LPUART1_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_LPUART1_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_LPUART1_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPUART1_SEL0_SHIFT))&TRGMUX1_TRGMUX_LPUART1_SEL0_MASK)
#define TRGMUX1_TRGMUX_LPUART1_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_LPUART1_LK_SHIFT 31
#define TRGMUX1_TRGMUX_LPUART1_LK_WIDTH 1
#define TRGMUX1_TRGMUX_LPUART1_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPUART1_LK_SHIFT))&TRGMUX1_TRGMUX_LPUART1_LK_MASK)
/* TRGMUX_LPI2C0 Bit Fields */
#define TRGMUX1_TRGMUX_LPI2C0_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_LPI2C0_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_LPI2C0_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_LPI2C0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPI2C0_SEL0_SHIFT))&TRGMUX1_TRGMUX_LPI2C0_SEL0_MASK)
#define TRGMUX1_TRGMUX_LPI2C0_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_LPI2C0_LK_SHIFT 31
#define TRGMUX1_TRGMUX_LPI2C0_LK_WIDTH 1
#define TRGMUX1_TRGMUX_LPI2C0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPI2C0_LK_SHIFT))&TRGMUX1_TRGMUX_LPI2C0_LK_MASK)
/* TRGMUX_LPI2C1 Bit Fields */
#define TRGMUX1_TRGMUX_LPI2C1_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_LPI2C1_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_LPI2C1_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_LPI2C1_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPI2C1_SEL0_SHIFT))&TRGMUX1_TRGMUX_LPI2C1_SEL0_MASK)
#define TRGMUX1_TRGMUX_LPI2C1_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_LPI2C1_LK_SHIFT 31
#define TRGMUX1_TRGMUX_LPI2C1_LK_WIDTH 1
#define TRGMUX1_TRGMUX_LPI2C1_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPI2C1_LK_SHIFT))&TRGMUX1_TRGMUX_LPI2C1_LK_MASK)
/* TRGMUX_LPSPI0 Bit Fields */
#define TRGMUX1_TRGMUX_LPSPI0_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_LPSPI0_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_LPSPI0_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_LPSPI0_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPSPI0_SEL0_SHIFT))&TRGMUX1_TRGMUX_LPSPI0_SEL0_MASK)
#define TRGMUX1_TRGMUX_LPSPI0_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_LPSPI0_LK_SHIFT 31
#define TRGMUX1_TRGMUX_LPSPI0_LK_WIDTH 1
#define TRGMUX1_TRGMUX_LPSPI0_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPSPI0_LK_SHIFT))&TRGMUX1_TRGMUX_LPSPI0_LK_MASK)
/* TRGMUX_LPSPI1 Bit Fields */
#define TRGMUX1_TRGMUX_LPSPI1_SEL0_MASK 0x3Fu
#define TRGMUX1_TRGMUX_LPSPI1_SEL0_SHIFT 0
#define TRGMUX1_TRGMUX_LPSPI1_SEL0_WIDTH 6
#define TRGMUX1_TRGMUX_LPSPI1_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPSPI1_SEL0_SHIFT))&TRGMUX1_TRGMUX_LPSPI1_SEL0_MASK)
#define TRGMUX1_TRGMUX_LPSPI1_LK_MASK 0x80000000u
#define TRGMUX1_TRGMUX_LPSPI1_LK_SHIFT 31
#define TRGMUX1_TRGMUX_LPSPI1_LK_WIDTH 1
#define TRGMUX1_TRGMUX_LPSPI1_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX1_TRGMUX_LPSPI1_LK_SHIFT))&TRGMUX1_TRGMUX_LPSPI1_LK_MASK)
/*!
* @}
*/ /* end of group TRGMUX1_Register_Masks */
/* TRGMUX1 - Peripheral instance base addresses */
/** Peripheral TRGMUX1 base address */
#define TRGMUX1_BASE (0x400A7000u)
/** Peripheral TRGMUX1 base pointer */
#define TRGMUX1 ((TRGMUX1_Type *)TRGMUX1_BASE)
#define TRGMUX1_BASE_PTR (TRGMUX1)
/** Array initializer of TRGMUX1 peripheral base addresses */
#define TRGMUX1_BASE_ADDRS { TRGMUX1_BASE }
/** Array initializer of TRGMUX1 peripheral base pointers */
#define TRGMUX1_BASE_PTRS { TRGMUX1 }
/* ----------------------------------------------------------------------------
-- TRGMUX1 - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX1_Register_Accessor_Macros TRGMUX1 - Register accessor macros
* @{
*/
/* TRGMUX1 - Register instance definitions */
/* TRGMUX1 */
#define TRGMUX_TRGMUX_TPM0 TRGMUX1_TRGMUX_TPM0_REG(TRGMUX1)
#define TRGMUX_TRGMUX_TPM1 TRGMUX1_TRGMUX_TPM1_REG(TRGMUX1)
#define TRGMUX_TRGMUX_FLEXIO0 TRGMUX1_TRGMUX_FLEXIO0_REG(TRGMUX1)
#define TRGMUX_TRGMUX_LPUART0 TRGMUX1_TRGMUX_LPUART0_REG(TRGMUX1)
#define TRGMUX_TRGMUX_LPUART1 TRGMUX1_TRGMUX_LPUART1_REG(TRGMUX1)
#define TRGMUX_TRGMUX_LPI2C0 TRGMUX1_TRGMUX_LPI2C0_REG(TRGMUX1)
#define TRGMUX_TRGMUX_LPI2C1 TRGMUX1_TRGMUX_LPI2C1_REG(TRGMUX1)
#define TRGMUX_TRGMUX_LPSPI0 TRGMUX1_TRGMUX_LPSPI0_REG(TRGMUX1)
#define TRGMUX_TRGMUX_LPSPI1 TRGMUX1_TRGMUX_LPSPI1_REG(TRGMUX1)
/*!
* @}
*/ /* end of group TRGMUX1_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group TRGMUX1_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TRNG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
* @{
*/
/** TRNG - Register Layout Typedef */
typedef struct {
__IO uint32_t RTMCTL; /**< RNG Miscellaneous Control Register, offset: 0x0 */
__IO uint32_t RTSCMISC; /**< RNG Statistical Check Miscellaneous Register, offset: 0x4 */
__IO uint32_t RTPKRRNG; /**< RNG Poker Range Register, offset: 0x8 */
union { /* offset: 0xC */
__IO uint32_t RTPKRMAX; /**< RNG Poker Maximum Limit Register, offset: 0xC */
__I uint32_t RTPKRSQ; /**< RNG Poker Square Calculation Result Register, offset: 0xC */
};
__IO uint32_t RTSDCTL; /**< RNG Seed Control Register, offset: 0x10 */
union { /* offset: 0x14 */
__IO uint32_t RTSBLIM; /**< RNG Sparse Bit Limit Register, offset: 0x14 */
__I uint32_t RTTOTSAM; /**< RNG Total Samples Register, offset: 0x14 */
};
__IO uint32_t RTFRQMIN; /**< RNG Frequency Count Minimum Limit Register, offset: 0x18 */
union { /* offset: 0x1C */
__I uint32_t RTFRQCNT; /**< RNG Frequency Count Register, offset: 0x1C */
__IO uint32_t RTFRQMAX; /**< RNG Frequency Count Maximum Limit Register, offset: 0x1C */
};
union { /* offset: 0x20 */
__I uint32_t RTSCMC; /**< RNG Statistical Check Monobit Count Register, offset: 0x20 */
__IO uint32_t RTSCML; /**< RNG Statistical Check Monobit Limit Register, offset: 0x20 */
};
union { /* offset: 0x24 */
__I uint32_t RTSCR1C; /**< RNG Statistical Check Run Length 1 Count Register, offset: 0x24 */
__IO uint32_t RTSCR1L; /**< RNG Statistical Check Run Length 1 Limit Register, offset: 0x24 */
};
union { /* offset: 0x28 */
__I uint32_t RTSCR2C; /**< RNG Statistical Check Run Length 2 Count Register, offset: 0x28 */
__IO uint32_t RTSCR2L; /**< RNG Statistical Check Run Length 2 Limit Register, offset: 0x28 */
};
union { /* offset: 0x2C */
__I uint32_t RTSCR3C; /**< RNG Statistical Check Run Length 3 Count Register, offset: 0x2C */
__IO uint32_t RTSCR3L; /**< RNG Statistical Check Run Length 3 Limit Register, offset: 0x2C */
};
union { /* offset: 0x30 */
__I uint32_t RTSCR4C; /**< RNG Statistical Check Run Length 4 Count Register, offset: 0x30 */
__IO uint32_t RTSCR4L; /**< RNG Statistical Check Run Length 4 Limit Register, offset: 0x30 */
};
union { /* offset: 0x34 */
__I uint32_t RTSCR5C; /**< RNG Statistical Check Run Length 5 Count Register, offset: 0x34 */
__IO uint32_t RTSCR5L; /**< RNG Statistical Check Run Length 5 Limit Register, offset: 0x34 */
};
union { /* offset: 0x38 */
__I uint32_t RTSCR6PC; /**< RNG Statistical Check Run Length 6+ Count Register, offset: 0x38 */
__IO uint32_t RTSCR6PL; /**< RNG Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
};
__I uint32_t RTSTATUS; /**< RNG Status Register, offset: 0x3C */
__I uint32_t RTENT0; /**< RNG TRNG Entropy Read Register, offset: 0x40 */
__I uint32_t RTENT1; /**< RNG TRNG Entropy Read Register, offset: 0x44 */
__I uint32_t RTENT2; /**< RNG TRNG Entropy Read Register, offset: 0x48 */
__I uint32_t RTENT3; /**< RNG TRNG Entropy Read Register, offset: 0x4C */
__I uint32_t RTENT4; /**< RNG TRNG Entropy Read Register, offset: 0x50 */
__I uint32_t RTENT5; /**< RNG TRNG Entropy Read Register, offset: 0x54 */
__I uint32_t RTENT6; /**< RNG TRNG Entropy Read Register, offset: 0x58 */
__I uint32_t RTENT7; /**< RNG TRNG Entropy Read Register, offset: 0x5C */
__I uint32_t RTENT8; /**< RNG TRNG Entropy Read Register, offset: 0x60 */
__I uint32_t RTENT9; /**< RNG TRNG Entropy Read Register, offset: 0x64 */
__I uint32_t RTENT10; /**< RNG TRNG Entropy Read Register, offset: 0x68 */
__I uint32_t RTENT11; /**< RNG TRNG Entropy Read Register, offset: 0x6C */
__I uint32_t RTENT12; /**< RNG TRNG Entropy Read Register, offset: 0x70 */
__I uint32_t RTENT13; /**< RNG TRNG Entropy Read Register, offset: 0x74 */
__I uint32_t RTENT14; /**< RNG TRNG Entropy Read Register, offset: 0x78 */
__I uint32_t RTENT15; /**< RNG TRNG Entropy Read Register, offset: 0x7C */
__I uint32_t RTPKRCNT10; /**< RNG Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
__I uint32_t RTPKRCNT32; /**< RNG Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
__I uint32_t RTPKRCNT54; /**< RNG Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
__I uint32_t RTPKRCNT76; /**< RNG Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
__I uint32_t RTPKRCNT98; /**< RNG Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
__I uint32_t RTPKRCNTBA; /**< RNG Statistical Check Poker Count B and A Register, offset: 0x94 */
__I uint32_t RTPKRCNTDC; /**< RNG Statistical Check Poker Count D and C Register, offset: 0x98 */
__I uint32_t RTPKRCNTFE; /**< RNG Statistical Check Poker Count F and E Register, offset: 0x9C */
__IO uint32_t SA_TRNG_SEC_CFG; /**< RNG Security Configuration Register, offset: 0xA0 */
__IO uint32_t SA_TRNG_INT_CTRL; /**< RNG Interrupt Control Register, offset: 0xA4 */
__IO uint32_t SA_TRNG_INT_MASK; /**< RNG Mask Register, offset: 0xA8 */
__IO uint32_t SA_TRNG_INT_STATUS; /**< RNG Interrupt Status Register, offset: 0xAC */
uint8_t RESERVED_0[64];
__I uint32_t SA_TRNG_VID1; /**< RNG Version ID Register (MS), offset: 0xF0 */
__I uint32_t SA_TRNG_VID2; /**< RNG Version ID Register (LS), offset: 0xF4 */
} TRNG_Type, *TRNG_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TRNG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Register_Accessor_Macros TRNG - Register accessor macros
* @{
*/
/* TRNG - Register accessors */
#define TRNG_RTMCTL_REG(base) ((base)->RTMCTL)
#define TRNG_RTSCMISC_REG(base) ((base)->RTSCMISC)
#define TRNG_RTPKRRNG_REG(base) ((base)->RTPKRRNG)
#define TRNG_RTPKRMAX_REG(base) ((base)->RTPKRMAX)
#define TRNG_RTPKRSQ_REG(base) ((base)->RTPKRSQ)
#define TRNG_RTSDCTL_REG(base) ((base)->RTSDCTL)
#define TRNG_RTSBLIM_REG(base) ((base)->RTSBLIM)
#define TRNG_RTTOTSAM_REG(base) ((base)->RTTOTSAM)
#define TRNG_RTFRQMIN_REG(base) ((base)->RTFRQMIN)
#define TRNG_RTFRQCNT_REG(base) ((base)->RTFRQCNT)
#define TRNG_RTFRQMAX_REG(base) ((base)->RTFRQMAX)
#define TRNG_RTSCMC_REG(base) ((base)->RTSCMC)
#define TRNG_RTSCML_REG(base) ((base)->RTSCML)
#define TRNG_RTSCR1C_REG(base) ((base)->RTSCR1C)
#define TRNG_RTSCR1L_REG(base) ((base)->RTSCR1L)
#define TRNG_RTSCR2C_REG(base) ((base)->RTSCR2C)
#define TRNG_RTSCR2L_REG(base) ((base)->RTSCR2L)
#define TRNG_RTSCR3C_REG(base) ((base)->RTSCR3C)
#define TRNG_RTSCR3L_REG(base) ((base)->RTSCR3L)
#define TRNG_RTSCR4C_REG(base) ((base)->RTSCR4C)
#define TRNG_RTSCR4L_REG(base) ((base)->RTSCR4L)
#define TRNG_RTSCR5C_REG(base) ((base)->RTSCR5C)
#define TRNG_RTSCR5L_REG(base) ((base)->RTSCR5L)
#define TRNG_RTSCR6PC_REG(base) ((base)->RTSCR6PC)
#define TRNG_RTSCR6PL_REG(base) ((base)->RTSCR6PL)
#define TRNG_RTSTATUS_REG(base) ((base)->RTSTATUS)
#define TRNG_RTENT0_REG(base) ((base)->RTENT0)
#define TRNG_RTENT1_REG(base) ((base)->RTENT1)
#define TRNG_RTENT2_REG(base) ((base)->RTENT2)
#define TRNG_RTENT3_REG(base) ((base)->RTENT3)
#define TRNG_RTENT4_REG(base) ((base)->RTENT4)
#define TRNG_RTENT5_REG(base) ((base)->RTENT5)
#define TRNG_RTENT6_REG(base) ((base)->RTENT6)
#define TRNG_RTENT7_REG(base) ((base)->RTENT7)
#define TRNG_RTENT8_REG(base) ((base)->RTENT8)
#define TRNG_RTENT9_REG(base) ((base)->RTENT9)
#define TRNG_RTENT10_REG(base) ((base)->RTENT10)
#define TRNG_RTENT11_REG(base) ((base)->RTENT11)
#define TRNG_RTENT12_REG(base) ((base)->RTENT12)
#define TRNG_RTENT13_REG(base) ((base)->RTENT13)
#define TRNG_RTENT14_REG(base) ((base)->RTENT14)
#define TRNG_RTENT15_REG(base) ((base)->RTENT15)
#define TRNG_RTPKRCNT10_REG(base) ((base)->RTPKRCNT10)
#define TRNG_RTPKRCNT32_REG(base) ((base)->RTPKRCNT32)
#define TRNG_RTPKRCNT54_REG(base) ((base)->RTPKRCNT54)
#define TRNG_RTPKRCNT76_REG(base) ((base)->RTPKRCNT76)
#define TRNG_RTPKRCNT98_REG(base) ((base)->RTPKRCNT98)
#define TRNG_RTPKRCNTBA_REG(base) ((base)->RTPKRCNTBA)
#define TRNG_RTPKRCNTDC_REG(base) ((base)->RTPKRCNTDC)
#define TRNG_RTPKRCNTFE_REG(base) ((base)->RTPKRCNTFE)
#define TRNG_SA_TRNG_SEC_CFG_REG(base) ((base)->SA_TRNG_SEC_CFG)
#define TRNG_SA_TRNG_INT_CTRL_REG(base) ((base)->SA_TRNG_INT_CTRL)
#define TRNG_SA_TRNG_INT_MASK_REG(base) ((base)->SA_TRNG_INT_MASK)
#define TRNG_SA_TRNG_INT_STATUS_REG(base) ((base)->SA_TRNG_INT_STATUS)
#define TRNG_SA_TRNG_VID1_REG(base) ((base)->SA_TRNG_VID1)
#define TRNG_SA_TRNG_VID2_REG(base) ((base)->SA_TRNG_VID2)
/*!
* @}
*/ /* end of group TRNG_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TRNG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Register_Masks TRNG Register Masks
* @{
*/
/* RTMCTL Bit Fields */
#define TRNG_RTMCTL_SAMP_MODE_MASK 0x3u
#define TRNG_RTMCTL_SAMP_MODE_SHIFT 0
#define TRNG_RTMCTL_SAMP_MODE_WIDTH 2
#define TRNG_RTMCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_SAMP_MODE_SHIFT))&TRNG_RTMCTL_SAMP_MODE_MASK)
#define TRNG_RTMCTL_OSC_DIV_MASK 0xCu
#define TRNG_RTMCTL_OSC_DIV_SHIFT 2
#define TRNG_RTMCTL_OSC_DIV_WIDTH 2
#define TRNG_RTMCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_OSC_DIV_SHIFT))&TRNG_RTMCTL_OSC_DIV_MASK)
#define TRNG_RTMCTL_UNUSED_MASK 0x10u
#define TRNG_RTMCTL_UNUSED_SHIFT 4
#define TRNG_RTMCTL_UNUSED_WIDTH 1
#define TRNG_RTMCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_UNUSED_SHIFT))&TRNG_RTMCTL_UNUSED_MASK)
#define TRNG_RTMCTL_TRNG_ACC_MASK 0x20u
#define TRNG_RTMCTL_TRNG_ACC_SHIFT 5
#define TRNG_RTMCTL_TRNG_ACC_WIDTH 1
#define TRNG_RTMCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_TRNG_ACC_SHIFT))&TRNG_RTMCTL_TRNG_ACC_MASK)
#define TRNG_RTMCTL_RST_DEF_MASK 0x40u
#define TRNG_RTMCTL_RST_DEF_SHIFT 6
#define TRNG_RTMCTL_RST_DEF_WIDTH 1
#define TRNG_RTMCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_RST_DEF_SHIFT))&TRNG_RTMCTL_RST_DEF_MASK)
#define TRNG_RTMCTL_FOR_SCLK_MASK 0x80u
#define TRNG_RTMCTL_FOR_SCLK_SHIFT 7
#define TRNG_RTMCTL_FOR_SCLK_WIDTH 1
#define TRNG_RTMCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_FOR_SCLK_SHIFT))&TRNG_RTMCTL_FOR_SCLK_MASK)
#define TRNG_RTMCTL_FCT_FAIL_MASK 0x100u
#define TRNG_RTMCTL_FCT_FAIL_SHIFT 8
#define TRNG_RTMCTL_FCT_FAIL_WIDTH 1
#define TRNG_RTMCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_FCT_FAIL_SHIFT))&TRNG_RTMCTL_FCT_FAIL_MASK)
#define TRNG_RTMCTL_FCT_VAL_MASK 0x200u
#define TRNG_RTMCTL_FCT_VAL_SHIFT 9
#define TRNG_RTMCTL_FCT_VAL_WIDTH 1
#define TRNG_RTMCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_FCT_VAL_SHIFT))&TRNG_RTMCTL_FCT_VAL_MASK)
#define TRNG_RTMCTL_ENT_VAL_MASK 0x400u
#define TRNG_RTMCTL_ENT_VAL_SHIFT 10
#define TRNG_RTMCTL_ENT_VAL_WIDTH 1
#define TRNG_RTMCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_ENT_VAL_SHIFT))&TRNG_RTMCTL_ENT_VAL_MASK)
#define TRNG_RTMCTL_TST_OUT_MASK 0x800u
#define TRNG_RTMCTL_TST_OUT_SHIFT 11
#define TRNG_RTMCTL_TST_OUT_WIDTH 1
#define TRNG_RTMCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_TST_OUT_SHIFT))&TRNG_RTMCTL_TST_OUT_MASK)
#define TRNG_RTMCTL_ERR_MASK 0x1000u
#define TRNG_RTMCTL_ERR_SHIFT 12
#define TRNG_RTMCTL_ERR_WIDTH 1
#define TRNG_RTMCTL_ERR(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_ERR_SHIFT))&TRNG_RTMCTL_ERR_MASK)
#define TRNG_RTMCTL_TSTOP_OK_MASK 0x2000u
#define TRNG_RTMCTL_TSTOP_OK_SHIFT 13
#define TRNG_RTMCTL_TSTOP_OK_WIDTH 1
#define TRNG_RTMCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_TSTOP_OK_SHIFT))&TRNG_RTMCTL_TSTOP_OK_MASK)
#define TRNG_RTMCTL_PRGM_MASK 0x10000u
#define TRNG_RTMCTL_PRGM_SHIFT 16
#define TRNG_RTMCTL_PRGM_WIDTH 1
#define TRNG_RTMCTL_PRGM(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTMCTL_PRGM_SHIFT))&TRNG_RTMCTL_PRGM_MASK)
/* RTSCMISC Bit Fields */
#define TRNG_RTSCMISC_LRUN_MAX_MASK 0xFFu
#define TRNG_RTSCMISC_LRUN_MAX_SHIFT 0
#define TRNG_RTSCMISC_LRUN_MAX_WIDTH 8
#define TRNG_RTSCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCMISC_LRUN_MAX_SHIFT))&TRNG_RTSCMISC_LRUN_MAX_MASK)
#define TRNG_RTSCMISC_RTY_CT_MASK 0xF0000u
#define TRNG_RTSCMISC_RTY_CT_SHIFT 16
#define TRNG_RTSCMISC_RTY_CT_WIDTH 4
#define TRNG_RTSCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCMISC_RTY_CT_SHIFT))&TRNG_RTSCMISC_RTY_CT_MASK)
/* RTPKRRNG Bit Fields */
#define TRNG_RTPKRRNG_PKR_RNG_MASK 0xFFFFu
#define TRNG_RTPKRRNG_PKR_RNG_SHIFT 0
#define TRNG_RTPKRRNG_PKR_RNG_WIDTH 16
#define TRNG_RTPKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRRNG_PKR_RNG_SHIFT))&TRNG_RTPKRRNG_PKR_RNG_MASK)
/* RTPKRMAX Bit Fields */
#define TRNG_RTPKRMAX_PKR_MAX_MASK 0xFFFFFFu
#define TRNG_RTPKRMAX_PKR_MAX_SHIFT 0
#define TRNG_RTPKRMAX_PKR_MAX_WIDTH 24
#define TRNG_RTPKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRMAX_PKR_MAX_SHIFT))&TRNG_RTPKRMAX_PKR_MAX_MASK)
/* RTPKRSQ Bit Fields */
#define TRNG_RTPKRSQ_PKR_SQ_MASK 0xFFFFFFu
#define TRNG_RTPKRSQ_PKR_SQ_SHIFT 0
#define TRNG_RTPKRSQ_PKR_SQ_WIDTH 24
#define TRNG_RTPKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRSQ_PKR_SQ_SHIFT))&TRNG_RTPKRSQ_PKR_SQ_MASK)
/* RTSDCTL Bit Fields */
#define TRNG_RTSDCTL_SAMP_SIZE_MASK 0xFFFFu
#define TRNG_RTSDCTL_SAMP_SIZE_SHIFT 0
#define TRNG_RTSDCTL_SAMP_SIZE_WIDTH 16
#define TRNG_RTSDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSDCTL_SAMP_SIZE_SHIFT))&TRNG_RTSDCTL_SAMP_SIZE_MASK)
#define TRNG_RTSDCTL_ENT_DLY_MASK 0xFFFF0000u
#define TRNG_RTSDCTL_ENT_DLY_SHIFT 16
#define TRNG_RTSDCTL_ENT_DLY_WIDTH 16
#define TRNG_RTSDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSDCTL_ENT_DLY_SHIFT))&TRNG_RTSDCTL_ENT_DLY_MASK)
/* RTSBLIM Bit Fields */
#define TRNG_RTSBLIM_SB_LIM_MASK 0x3FFu
#define TRNG_RTSBLIM_SB_LIM_SHIFT 0
#define TRNG_RTSBLIM_SB_LIM_WIDTH 10
#define TRNG_RTSBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSBLIM_SB_LIM_SHIFT))&TRNG_RTSBLIM_SB_LIM_MASK)
/* RTTOTSAM Bit Fields */
#define TRNG_RTTOTSAM_TOT_SAM_MASK 0xFFFFFu
#define TRNG_RTTOTSAM_TOT_SAM_SHIFT 0
#define TRNG_RTTOTSAM_TOT_SAM_WIDTH 20
#define TRNG_RTTOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTTOTSAM_TOT_SAM_SHIFT))&TRNG_RTTOTSAM_TOT_SAM_MASK)
/* RTFRQMIN Bit Fields */
#define TRNG_RTFRQMIN_FRQ_MIN_MASK 0x3FFFFFu
#define TRNG_RTFRQMIN_FRQ_MIN_SHIFT 0
#define TRNG_RTFRQMIN_FRQ_MIN_WIDTH 22
#define TRNG_RTFRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTFRQMIN_FRQ_MIN_SHIFT))&TRNG_RTFRQMIN_FRQ_MIN_MASK)
/* RTFRQCNT Bit Fields */
#define TRNG_RTFRQCNT_FRQ_CT_MASK 0x3FFFFFu
#define TRNG_RTFRQCNT_FRQ_CT_SHIFT 0
#define TRNG_RTFRQCNT_FRQ_CT_WIDTH 22
#define TRNG_RTFRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTFRQCNT_FRQ_CT_SHIFT))&TRNG_RTFRQCNT_FRQ_CT_MASK)
/* RTFRQMAX Bit Fields */
#define TRNG_RTFRQMAX_FRQ_MAX_MASK 0x3FFFFFu
#define TRNG_RTFRQMAX_FRQ_MAX_SHIFT 0
#define TRNG_RTFRQMAX_FRQ_MAX_WIDTH 22
#define TRNG_RTFRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTFRQMAX_FRQ_MAX_SHIFT))&TRNG_RTFRQMAX_FRQ_MAX_MASK)
/* RTSCMC Bit Fields */
#define TRNG_RTSCMC_MONO_CT_MASK 0xFFFFu
#define TRNG_RTSCMC_MONO_CT_SHIFT 0
#define TRNG_RTSCMC_MONO_CT_WIDTH 16
#define TRNG_RTSCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCMC_MONO_CT_SHIFT))&TRNG_RTSCMC_MONO_CT_MASK)
/* RTSCML Bit Fields */
#define TRNG_RTSCML_MONO_MAX_MASK 0xFFFFu
#define TRNG_RTSCML_MONO_MAX_SHIFT 0
#define TRNG_RTSCML_MONO_MAX_WIDTH 16
#define TRNG_RTSCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCML_MONO_MAX_SHIFT))&TRNG_RTSCML_MONO_MAX_MASK)
#define TRNG_RTSCML_MONO_RNG_MASK 0xFFFF0000u
#define TRNG_RTSCML_MONO_RNG_SHIFT 16
#define TRNG_RTSCML_MONO_RNG_WIDTH 16
#define TRNG_RTSCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCML_MONO_RNG_SHIFT))&TRNG_RTSCML_MONO_RNG_MASK)
/* RTSCR1C Bit Fields */
#define TRNG_RTSCR1C_R1_0_CT_MASK 0x7FFFu
#define TRNG_RTSCR1C_R1_0_CT_SHIFT 0
#define TRNG_RTSCR1C_R1_0_CT_WIDTH 15
#define TRNG_RTSCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR1C_R1_0_CT_SHIFT))&TRNG_RTSCR1C_R1_0_CT_MASK)
#define TRNG_RTSCR1C_R1_1_CT_MASK 0x7FFF0000u
#define TRNG_RTSCR1C_R1_1_CT_SHIFT 16
#define TRNG_RTSCR1C_R1_1_CT_WIDTH 15
#define TRNG_RTSCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR1C_R1_1_CT_SHIFT))&TRNG_RTSCR1C_R1_1_CT_MASK)
/* RTSCR1L Bit Fields */
#define TRNG_RTSCR1L_RUN1_MAX_MASK 0x7FFFu
#define TRNG_RTSCR1L_RUN1_MAX_SHIFT 0
#define TRNG_RTSCR1L_RUN1_MAX_WIDTH 15
#define TRNG_RTSCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR1L_RUN1_MAX_SHIFT))&TRNG_RTSCR1L_RUN1_MAX_MASK)
#define TRNG_RTSCR1L_RUN1_RNG_MASK 0x7FFF0000u
#define TRNG_RTSCR1L_RUN1_RNG_SHIFT 16
#define TRNG_RTSCR1L_RUN1_RNG_WIDTH 15
#define TRNG_RTSCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR1L_RUN1_RNG_SHIFT))&TRNG_RTSCR1L_RUN1_RNG_MASK)
/* RTSCR2C Bit Fields */
#define TRNG_RTSCR2C_R2_0_CT_MASK 0x3FFFu
#define TRNG_RTSCR2C_R2_0_CT_SHIFT 0
#define TRNG_RTSCR2C_R2_0_CT_WIDTH 14
#define TRNG_RTSCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR2C_R2_0_CT_SHIFT))&TRNG_RTSCR2C_R2_0_CT_MASK)
#define TRNG_RTSCR2C_R2_1_CT_MASK 0x3FFF0000u
#define TRNG_RTSCR2C_R2_1_CT_SHIFT 16
#define TRNG_RTSCR2C_R2_1_CT_WIDTH 14
#define TRNG_RTSCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR2C_R2_1_CT_SHIFT))&TRNG_RTSCR2C_R2_1_CT_MASK)
/* RTSCR2L Bit Fields */
#define TRNG_RTSCR2L_RUN2_MAX_MASK 0x3FFFu
#define TRNG_RTSCR2L_RUN2_MAX_SHIFT 0
#define TRNG_RTSCR2L_RUN2_MAX_WIDTH 14
#define TRNG_RTSCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR2L_RUN2_MAX_SHIFT))&TRNG_RTSCR2L_RUN2_MAX_MASK)
#define TRNG_RTSCR2L_RUN2_RNG_MASK 0x3FFF0000u
#define TRNG_RTSCR2L_RUN2_RNG_SHIFT 16
#define TRNG_RTSCR2L_RUN2_RNG_WIDTH 14
#define TRNG_RTSCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR2L_RUN2_RNG_SHIFT))&TRNG_RTSCR2L_RUN2_RNG_MASK)
/* RTSCR3C Bit Fields */
#define TRNG_RTSCR3C_R3_0_CT_MASK 0x1FFFu
#define TRNG_RTSCR3C_R3_0_CT_SHIFT 0
#define TRNG_RTSCR3C_R3_0_CT_WIDTH 13
#define TRNG_RTSCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR3C_R3_0_CT_SHIFT))&TRNG_RTSCR3C_R3_0_CT_MASK)
#define TRNG_RTSCR3C_R3_1_CT_MASK 0x1FFF0000u
#define TRNG_RTSCR3C_R3_1_CT_SHIFT 16
#define TRNG_RTSCR3C_R3_1_CT_WIDTH 13
#define TRNG_RTSCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR3C_R3_1_CT_SHIFT))&TRNG_RTSCR3C_R3_1_CT_MASK)
/* RTSCR3L Bit Fields */
#define TRNG_RTSCR3L_RUN3_MAX_MASK 0x1FFFu
#define TRNG_RTSCR3L_RUN3_MAX_SHIFT 0
#define TRNG_RTSCR3L_RUN3_MAX_WIDTH 13
#define TRNG_RTSCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR3L_RUN3_MAX_SHIFT))&TRNG_RTSCR3L_RUN3_MAX_MASK)
#define TRNG_RTSCR3L_RUN3_RNG_MASK 0x1FFF0000u
#define TRNG_RTSCR3L_RUN3_RNG_SHIFT 16
#define TRNG_RTSCR3L_RUN3_RNG_WIDTH 13
#define TRNG_RTSCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR3L_RUN3_RNG_SHIFT))&TRNG_RTSCR3L_RUN3_RNG_MASK)
/* RTSCR4C Bit Fields */
#define TRNG_RTSCR4C_R4_0_CT_MASK 0xFFFu
#define TRNG_RTSCR4C_R4_0_CT_SHIFT 0
#define TRNG_RTSCR4C_R4_0_CT_WIDTH 12
#define TRNG_RTSCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR4C_R4_0_CT_SHIFT))&TRNG_RTSCR4C_R4_0_CT_MASK)
#define TRNG_RTSCR4C_R4_1_CT_MASK 0xFFF0000u
#define TRNG_RTSCR4C_R4_1_CT_SHIFT 16
#define TRNG_RTSCR4C_R4_1_CT_WIDTH 12
#define TRNG_RTSCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR4C_R4_1_CT_SHIFT))&TRNG_RTSCR4C_R4_1_CT_MASK)
/* RTSCR4L Bit Fields */
#define TRNG_RTSCR4L_RUN4_MAX_MASK 0xFFFu
#define TRNG_RTSCR4L_RUN4_MAX_SHIFT 0
#define TRNG_RTSCR4L_RUN4_MAX_WIDTH 12
#define TRNG_RTSCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR4L_RUN4_MAX_SHIFT))&TRNG_RTSCR4L_RUN4_MAX_MASK)
#define TRNG_RTSCR4L_RUN4_RNG_MASK 0xFFF0000u
#define TRNG_RTSCR4L_RUN4_RNG_SHIFT 16
#define TRNG_RTSCR4L_RUN4_RNG_WIDTH 12
#define TRNG_RTSCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR4L_RUN4_RNG_SHIFT))&TRNG_RTSCR4L_RUN4_RNG_MASK)
/* RTSCR5C Bit Fields */
#define TRNG_RTSCR5C_R5_0_CT_MASK 0x7FFu
#define TRNG_RTSCR5C_R5_0_CT_SHIFT 0
#define TRNG_RTSCR5C_R5_0_CT_WIDTH 11
#define TRNG_RTSCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR5C_R5_0_CT_SHIFT))&TRNG_RTSCR5C_R5_0_CT_MASK)
#define TRNG_RTSCR5C_R5_1_CT_MASK 0x7FF0000u
#define TRNG_RTSCR5C_R5_1_CT_SHIFT 16
#define TRNG_RTSCR5C_R5_1_CT_WIDTH 11
#define TRNG_RTSCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR5C_R5_1_CT_SHIFT))&TRNG_RTSCR5C_R5_1_CT_MASK)
/* RTSCR5L Bit Fields */
#define TRNG_RTSCR5L_RUN5_MAX_MASK 0x7FFu
#define TRNG_RTSCR5L_RUN5_MAX_SHIFT 0
#define TRNG_RTSCR5L_RUN5_MAX_WIDTH 11
#define TRNG_RTSCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR5L_RUN5_MAX_SHIFT))&TRNG_RTSCR5L_RUN5_MAX_MASK)
#define TRNG_RTSCR5L_RUN5_RNG_MASK 0x7FF0000u
#define TRNG_RTSCR5L_RUN5_RNG_SHIFT 16
#define TRNG_RTSCR5L_RUN5_RNG_WIDTH 11
#define TRNG_RTSCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR5L_RUN5_RNG_SHIFT))&TRNG_RTSCR5L_RUN5_RNG_MASK)
/* RTSCR6PC Bit Fields */
#define TRNG_RTSCR6PC_R6P_0_CT_MASK 0x7FFu
#define TRNG_RTSCR6PC_R6P_0_CT_SHIFT 0
#define TRNG_RTSCR6PC_R6P_0_CT_WIDTH 11
#define TRNG_RTSCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR6PC_R6P_0_CT_SHIFT))&TRNG_RTSCR6PC_R6P_0_CT_MASK)
#define TRNG_RTSCR6PC_R6P_1_CT_MASK 0x7FF0000u
#define TRNG_RTSCR6PC_R6P_1_CT_SHIFT 16
#define TRNG_RTSCR6PC_R6P_1_CT_WIDTH 11
#define TRNG_RTSCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR6PC_R6P_1_CT_SHIFT))&TRNG_RTSCR6PC_R6P_1_CT_MASK)
/* RTSCR6PL Bit Fields */
#define TRNG_RTSCR6PL_RUN6P_MAX_MASK 0x7FFu
#define TRNG_RTSCR6PL_RUN6P_MAX_SHIFT 0
#define TRNG_RTSCR6PL_RUN6P_MAX_WIDTH 11
#define TRNG_RTSCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR6PL_RUN6P_MAX_SHIFT))&TRNG_RTSCR6PL_RUN6P_MAX_MASK)
#define TRNG_RTSCR6PL_RUN6P_RNG_MASK 0x7FF0000u
#define TRNG_RTSCR6PL_RUN6P_RNG_SHIFT 16
#define TRNG_RTSCR6PL_RUN6P_RNG_WIDTH 11
#define TRNG_RTSCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSCR6PL_RUN6P_RNG_SHIFT))&TRNG_RTSCR6PL_RUN6P_RNG_MASK)
/* RTSTATUS Bit Fields */
#define TRNG_RTSTATUS_TF1BR0_MASK 0x1u
#define TRNG_RTSTATUS_TF1BR0_SHIFT 0
#define TRNG_RTSTATUS_TF1BR0_WIDTH 1
#define TRNG_RTSTATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF1BR0_SHIFT))&TRNG_RTSTATUS_TF1BR0_MASK)
#define TRNG_RTSTATUS_TF1BR1_MASK 0x2u
#define TRNG_RTSTATUS_TF1BR1_SHIFT 1
#define TRNG_RTSTATUS_TF1BR1_WIDTH 1
#define TRNG_RTSTATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF1BR1_SHIFT))&TRNG_RTSTATUS_TF1BR1_MASK)
#define TRNG_RTSTATUS_TF2BR0_MASK 0x4u
#define TRNG_RTSTATUS_TF2BR0_SHIFT 2
#define TRNG_RTSTATUS_TF2BR0_WIDTH 1
#define TRNG_RTSTATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF2BR0_SHIFT))&TRNG_RTSTATUS_TF2BR0_MASK)
#define TRNG_RTSTATUS_TF2BR1_MASK 0x8u
#define TRNG_RTSTATUS_TF2BR1_SHIFT 3
#define TRNG_RTSTATUS_TF2BR1_WIDTH 1
#define TRNG_RTSTATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF2BR1_SHIFT))&TRNG_RTSTATUS_TF2BR1_MASK)
#define TRNG_RTSTATUS_TF3BR0_MASK 0x10u
#define TRNG_RTSTATUS_TF3BR0_SHIFT 4
#define TRNG_RTSTATUS_TF3BR0_WIDTH 1
#define TRNG_RTSTATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF3BR0_SHIFT))&TRNG_RTSTATUS_TF3BR0_MASK)
#define TRNG_RTSTATUS_TF3BR1_MASK 0x20u
#define TRNG_RTSTATUS_TF3BR1_SHIFT 5
#define TRNG_RTSTATUS_TF3BR1_WIDTH 1
#define TRNG_RTSTATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF3BR1_SHIFT))&TRNG_RTSTATUS_TF3BR1_MASK)
#define TRNG_RTSTATUS_TF4BR0_MASK 0x40u
#define TRNG_RTSTATUS_TF4BR0_SHIFT 6
#define TRNG_RTSTATUS_TF4BR0_WIDTH 1
#define TRNG_RTSTATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF4BR0_SHIFT))&TRNG_RTSTATUS_TF4BR0_MASK)
#define TRNG_RTSTATUS_TF4BR1_MASK 0x80u
#define TRNG_RTSTATUS_TF4BR1_SHIFT 7
#define TRNG_RTSTATUS_TF4BR1_WIDTH 1
#define TRNG_RTSTATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF4BR1_SHIFT))&TRNG_RTSTATUS_TF4BR1_MASK)
#define TRNG_RTSTATUS_TF5BR0_MASK 0x100u
#define TRNG_RTSTATUS_TF5BR0_SHIFT 8
#define TRNG_RTSTATUS_TF5BR0_WIDTH 1
#define TRNG_RTSTATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF5BR0_SHIFT))&TRNG_RTSTATUS_TF5BR0_MASK)
#define TRNG_RTSTATUS_TF5BR1_MASK 0x200u
#define TRNG_RTSTATUS_TF5BR1_SHIFT 9
#define TRNG_RTSTATUS_TF5BR1_WIDTH 1
#define TRNG_RTSTATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF5BR1_SHIFT))&TRNG_RTSTATUS_TF5BR1_MASK)
#define TRNG_RTSTATUS_TF6PBR0_MASK 0x400u
#define TRNG_RTSTATUS_TF6PBR0_SHIFT 10
#define TRNG_RTSTATUS_TF6PBR0_WIDTH 1
#define TRNG_RTSTATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF6PBR0_SHIFT))&TRNG_RTSTATUS_TF6PBR0_MASK)
#define TRNG_RTSTATUS_TF6PBR1_MASK 0x800u
#define TRNG_RTSTATUS_TF6PBR1_SHIFT 11
#define TRNG_RTSTATUS_TF6PBR1_WIDTH 1
#define TRNG_RTSTATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TF6PBR1_SHIFT))&TRNG_RTSTATUS_TF6PBR1_MASK)
#define TRNG_RTSTATUS_TFSB_MASK 0x1000u
#define TRNG_RTSTATUS_TFSB_SHIFT 12
#define TRNG_RTSTATUS_TFSB_WIDTH 1
#define TRNG_RTSTATUS_TFSB(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TFSB_SHIFT))&TRNG_RTSTATUS_TFSB_MASK)
#define TRNG_RTSTATUS_TFLR_MASK 0x2000u
#define TRNG_RTSTATUS_TFLR_SHIFT 13
#define TRNG_RTSTATUS_TFLR_WIDTH 1
#define TRNG_RTSTATUS_TFLR(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TFLR_SHIFT))&TRNG_RTSTATUS_TFLR_MASK)
#define TRNG_RTSTATUS_TFP_MASK 0x4000u
#define TRNG_RTSTATUS_TFP_SHIFT 14
#define TRNG_RTSTATUS_TFP_WIDTH 1
#define TRNG_RTSTATUS_TFP(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TFP_SHIFT))&TRNG_RTSTATUS_TFP_MASK)
#define TRNG_RTSTATUS_TFMB_MASK 0x8000u
#define TRNG_RTSTATUS_TFMB_SHIFT 15
#define TRNG_RTSTATUS_TFMB_WIDTH 1
#define TRNG_RTSTATUS_TFMB(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_TFMB_SHIFT))&TRNG_RTSTATUS_TFMB_MASK)
#define TRNG_RTSTATUS_RETRY_CT_MASK 0xF0000u
#define TRNG_RTSTATUS_RETRY_CT_SHIFT 16
#define TRNG_RTSTATUS_RETRY_CT_WIDTH 4
#define TRNG_RTSTATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTSTATUS_RETRY_CT_SHIFT))&TRNG_RTSTATUS_RETRY_CT_MASK)
/* RTENT0 Bit Fields */
#define TRNG_RTENT0_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT0_ENT_SHIFT 0
#define TRNG_RTENT0_ENT_WIDTH 32
#define TRNG_RTENT0_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT0_ENT_SHIFT))&TRNG_RTENT0_ENT_MASK)
/* RTENT1 Bit Fields */
#define TRNG_RTENT1_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT1_ENT_SHIFT 0
#define TRNG_RTENT1_ENT_WIDTH 32
#define TRNG_RTENT1_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT1_ENT_SHIFT))&TRNG_RTENT1_ENT_MASK)
/* RTENT2 Bit Fields */
#define TRNG_RTENT2_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT2_ENT_SHIFT 0
#define TRNG_RTENT2_ENT_WIDTH 32
#define TRNG_RTENT2_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT2_ENT_SHIFT))&TRNG_RTENT2_ENT_MASK)
/* RTENT3 Bit Fields */
#define TRNG_RTENT3_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT3_ENT_SHIFT 0
#define TRNG_RTENT3_ENT_WIDTH 32
#define TRNG_RTENT3_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT3_ENT_SHIFT))&TRNG_RTENT3_ENT_MASK)
/* RTENT4 Bit Fields */
#define TRNG_RTENT4_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT4_ENT_SHIFT 0
#define TRNG_RTENT4_ENT_WIDTH 32
#define TRNG_RTENT4_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT4_ENT_SHIFT))&TRNG_RTENT4_ENT_MASK)
/* RTENT5 Bit Fields */
#define TRNG_RTENT5_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT5_ENT_SHIFT 0
#define TRNG_RTENT5_ENT_WIDTH 32
#define TRNG_RTENT5_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT5_ENT_SHIFT))&TRNG_RTENT5_ENT_MASK)
/* RTENT6 Bit Fields */
#define TRNG_RTENT6_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT6_ENT_SHIFT 0
#define TRNG_RTENT6_ENT_WIDTH 32
#define TRNG_RTENT6_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT6_ENT_SHIFT))&TRNG_RTENT6_ENT_MASK)
/* RTENT7 Bit Fields */
#define TRNG_RTENT7_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT7_ENT_SHIFT 0
#define TRNG_RTENT7_ENT_WIDTH 32
#define TRNG_RTENT7_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT7_ENT_SHIFT))&TRNG_RTENT7_ENT_MASK)
/* RTENT8 Bit Fields */
#define TRNG_RTENT8_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT8_ENT_SHIFT 0
#define TRNG_RTENT8_ENT_WIDTH 32
#define TRNG_RTENT8_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT8_ENT_SHIFT))&TRNG_RTENT8_ENT_MASK)
/* RTENT9 Bit Fields */
#define TRNG_RTENT9_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT9_ENT_SHIFT 0
#define TRNG_RTENT9_ENT_WIDTH 32
#define TRNG_RTENT9_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT9_ENT_SHIFT))&TRNG_RTENT9_ENT_MASK)
/* RTENT10 Bit Fields */
#define TRNG_RTENT10_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT10_ENT_SHIFT 0
#define TRNG_RTENT10_ENT_WIDTH 32
#define TRNG_RTENT10_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT10_ENT_SHIFT))&TRNG_RTENT10_ENT_MASK)
/* RTENT11 Bit Fields */
#define TRNG_RTENT11_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT11_ENT_SHIFT 0
#define TRNG_RTENT11_ENT_WIDTH 32
#define TRNG_RTENT11_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT11_ENT_SHIFT))&TRNG_RTENT11_ENT_MASK)
/* RTENT12 Bit Fields */
#define TRNG_RTENT12_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT12_ENT_SHIFT 0
#define TRNG_RTENT12_ENT_WIDTH 32
#define TRNG_RTENT12_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT12_ENT_SHIFT))&TRNG_RTENT12_ENT_MASK)
/* RTENT13 Bit Fields */
#define TRNG_RTENT13_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT13_ENT_SHIFT 0
#define TRNG_RTENT13_ENT_WIDTH 32
#define TRNG_RTENT13_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT13_ENT_SHIFT))&TRNG_RTENT13_ENT_MASK)
/* RTENT14 Bit Fields */
#define TRNG_RTENT14_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT14_ENT_SHIFT 0
#define TRNG_RTENT14_ENT_WIDTH 32
#define TRNG_RTENT14_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT14_ENT_SHIFT))&TRNG_RTENT14_ENT_MASK)
/* RTENT15 Bit Fields */
#define TRNG_RTENT15_ENT_MASK 0xFFFFFFFFu
#define TRNG_RTENT15_ENT_SHIFT 0
#define TRNG_RTENT15_ENT_WIDTH 32
#define TRNG_RTENT15_ENT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTENT15_ENT_SHIFT))&TRNG_RTENT15_ENT_MASK)
/* RTPKRCNT10 Bit Fields */
#define TRNG_RTPKRCNT10_PKR_0_CT_MASK 0xFFFFu
#define TRNG_RTPKRCNT10_PKR_0_CT_SHIFT 0
#define TRNG_RTPKRCNT10_PKR_0_CT_WIDTH 16
#define TRNG_RTPKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT10_PKR_0_CT_SHIFT))&TRNG_RTPKRCNT10_PKR_0_CT_MASK)
#define TRNG_RTPKRCNT10_PKR_1_CT_MASK 0xFFFF0000u
#define TRNG_RTPKRCNT10_PKR_1_CT_SHIFT 16
#define TRNG_RTPKRCNT10_PKR_1_CT_WIDTH 16
#define TRNG_RTPKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT10_PKR_1_CT_SHIFT))&TRNG_RTPKRCNT10_PKR_1_CT_MASK)
/* RTPKRCNT32 Bit Fields */
#define TRNG_RTPKRCNT32_PKR_2_CT_MASK 0xFFFFu
#define TRNG_RTPKRCNT32_PKR_2_CT_SHIFT 0
#define TRNG_RTPKRCNT32_PKR_2_CT_WIDTH 16
#define TRNG_RTPKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT32_PKR_2_CT_SHIFT))&TRNG_RTPKRCNT32_PKR_2_CT_MASK)
#define TRNG_RTPKRCNT32_PKR_3_CT_MASK 0xFFFF0000u
#define TRNG_RTPKRCNT32_PKR_3_CT_SHIFT 16
#define TRNG_RTPKRCNT32_PKR_3_CT_WIDTH 16
#define TRNG_RTPKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT32_PKR_3_CT_SHIFT))&TRNG_RTPKRCNT32_PKR_3_CT_MASK)
/* RTPKRCNT54 Bit Fields */
#define TRNG_RTPKRCNT54_PKR_4_CT_MASK 0xFFFFu
#define TRNG_RTPKRCNT54_PKR_4_CT_SHIFT 0
#define TRNG_RTPKRCNT54_PKR_4_CT_WIDTH 16
#define TRNG_RTPKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT54_PKR_4_CT_SHIFT))&TRNG_RTPKRCNT54_PKR_4_CT_MASK)
#define TRNG_RTPKRCNT54_PKR_5_CT_MASK 0xFFFF0000u
#define TRNG_RTPKRCNT54_PKR_5_CT_SHIFT 16
#define TRNG_RTPKRCNT54_PKR_5_CT_WIDTH 16
#define TRNG_RTPKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT54_PKR_5_CT_SHIFT))&TRNG_RTPKRCNT54_PKR_5_CT_MASK)
/* RTPKRCNT76 Bit Fields */
#define TRNG_RTPKRCNT76_PKR_6_CT_MASK 0xFFFFu
#define TRNG_RTPKRCNT76_PKR_6_CT_SHIFT 0
#define TRNG_RTPKRCNT76_PKR_6_CT_WIDTH 16
#define TRNG_RTPKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT76_PKR_6_CT_SHIFT))&TRNG_RTPKRCNT76_PKR_6_CT_MASK)
#define TRNG_RTPKRCNT76_PKR_7_CT_MASK 0xFFFF0000u
#define TRNG_RTPKRCNT76_PKR_7_CT_SHIFT 16
#define TRNG_RTPKRCNT76_PKR_7_CT_WIDTH 16
#define TRNG_RTPKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT76_PKR_7_CT_SHIFT))&TRNG_RTPKRCNT76_PKR_7_CT_MASK)
/* RTPKRCNT98 Bit Fields */
#define TRNG_RTPKRCNT98_PKR_8_CT_MASK 0xFFFFu
#define TRNG_RTPKRCNT98_PKR_8_CT_SHIFT 0
#define TRNG_RTPKRCNT98_PKR_8_CT_WIDTH 16
#define TRNG_RTPKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT98_PKR_8_CT_SHIFT))&TRNG_RTPKRCNT98_PKR_8_CT_MASK)
#define TRNG_RTPKRCNT98_PKR_9_CT_MASK 0xFFFF0000u
#define TRNG_RTPKRCNT98_PKR_9_CT_SHIFT 16
#define TRNG_RTPKRCNT98_PKR_9_CT_WIDTH 16
#define TRNG_RTPKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNT98_PKR_9_CT_SHIFT))&TRNG_RTPKRCNT98_PKR_9_CT_MASK)
/* RTPKRCNTBA Bit Fields */
#define TRNG_RTPKRCNTBA_PKR_A_CT_MASK 0xFFFFu
#define TRNG_RTPKRCNTBA_PKR_A_CT_SHIFT 0
#define TRNG_RTPKRCNTBA_PKR_A_CT_WIDTH 16
#define TRNG_RTPKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNTBA_PKR_A_CT_SHIFT))&TRNG_RTPKRCNTBA_PKR_A_CT_MASK)
#define TRNG_RTPKRCNTBA_PKR_B_CT_MASK 0xFFFF0000u
#define TRNG_RTPKRCNTBA_PKR_B_CT_SHIFT 16
#define TRNG_RTPKRCNTBA_PKR_B_CT_WIDTH 16
#define TRNG_RTPKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNTBA_PKR_B_CT_SHIFT))&TRNG_RTPKRCNTBA_PKR_B_CT_MASK)
/* RTPKRCNTDC Bit Fields */
#define TRNG_RTPKRCNTDC_PKR_C_CT_MASK 0xFFFFu
#define TRNG_RTPKRCNTDC_PKR_C_CT_SHIFT 0
#define TRNG_RTPKRCNTDC_PKR_C_CT_WIDTH 16
#define TRNG_RTPKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNTDC_PKR_C_CT_SHIFT))&TRNG_RTPKRCNTDC_PKR_C_CT_MASK)
#define TRNG_RTPKRCNTDC_PKR_D_CT_MASK 0xFFFF0000u
#define TRNG_RTPKRCNTDC_PKR_D_CT_SHIFT 16
#define TRNG_RTPKRCNTDC_PKR_D_CT_WIDTH 16
#define TRNG_RTPKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNTDC_PKR_D_CT_SHIFT))&TRNG_RTPKRCNTDC_PKR_D_CT_MASK)
/* RTPKRCNTFE Bit Fields */
#define TRNG_RTPKRCNTFE_PKR_E_CT_MASK 0xFFFFu
#define TRNG_RTPKRCNTFE_PKR_E_CT_SHIFT 0
#define TRNG_RTPKRCNTFE_PKR_E_CT_WIDTH 16
#define TRNG_RTPKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNTFE_PKR_E_CT_SHIFT))&TRNG_RTPKRCNTFE_PKR_E_CT_MASK)
#define TRNG_RTPKRCNTFE_PKR_F_CT_MASK 0xFFFF0000u
#define TRNG_RTPKRCNTFE_PKR_F_CT_SHIFT 16
#define TRNG_RTPKRCNTFE_PKR_F_CT_WIDTH 16
#define TRNG_RTPKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_RTPKRCNTFE_PKR_F_CT_SHIFT))&TRNG_RTPKRCNTFE_PKR_F_CT_MASK)
/* SA_TRNG_SEC_CFG Bit Fields */
#define TRNG_SA_TRNG_SEC_CFG_SH0_MASK 0x1u
#define TRNG_SA_TRNG_SEC_CFG_SH0_SHIFT 0
#define TRNG_SA_TRNG_SEC_CFG_SH0_WIDTH 1
#define TRNG_SA_TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_SEC_CFG_SH0_SHIFT))&TRNG_SA_TRNG_SEC_CFG_SH0_MASK)
#define TRNG_SA_TRNG_SEC_CFG_NO_PRGM_MASK 0x2u
#define TRNG_SA_TRNG_SEC_CFG_NO_PRGM_SHIFT 1
#define TRNG_SA_TRNG_SEC_CFG_NO_PRGM_WIDTH 1
#define TRNG_SA_TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_SEC_CFG_NO_PRGM_SHIFT))&TRNG_SA_TRNG_SEC_CFG_NO_PRGM_MASK)
#define TRNG_SA_TRNG_SEC_CFG_SK_VAL_MASK 0x4u
#define TRNG_SA_TRNG_SEC_CFG_SK_VAL_SHIFT 2
#define TRNG_SA_TRNG_SEC_CFG_SK_VAL_WIDTH 1
#define TRNG_SA_TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_SEC_CFG_SK_VAL_SHIFT))&TRNG_SA_TRNG_SEC_CFG_SK_VAL_MASK)
/* SA_TRNG_INT_CTRL Bit Fields */
#define TRNG_SA_TRNG_INT_CTRL_HW_ERR_MASK 0x1u
#define TRNG_SA_TRNG_INT_CTRL_HW_ERR_SHIFT 0
#define TRNG_SA_TRNG_INT_CTRL_HW_ERR_WIDTH 1
#define TRNG_SA_TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_CTRL_HW_ERR_SHIFT))&TRNG_SA_TRNG_INT_CTRL_HW_ERR_MASK)
#define TRNG_SA_TRNG_INT_CTRL_ENT_VAL_MASK 0x2u
#define TRNG_SA_TRNG_INT_CTRL_ENT_VAL_SHIFT 1
#define TRNG_SA_TRNG_INT_CTRL_ENT_VAL_WIDTH 1
#define TRNG_SA_TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_CTRL_ENT_VAL_SHIFT))&TRNG_SA_TRNG_INT_CTRL_ENT_VAL_MASK)
#define TRNG_SA_TRNG_INT_CTRL_FRQ_CT_FAIL_MASK 0x4u
#define TRNG_SA_TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT 2
#define TRNG_SA_TRNG_INT_CTRL_FRQ_CT_FAIL_WIDTH 1
#define TRNG_SA_TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT))&TRNG_SA_TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
#define TRNG_SA_TRNG_INT_CTRL_UNUSED_MASK 0xFFFFFFF8u
#define TRNG_SA_TRNG_INT_CTRL_UNUSED_SHIFT 3
#define TRNG_SA_TRNG_INT_CTRL_UNUSED_WIDTH 29
#define TRNG_SA_TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_CTRL_UNUSED_SHIFT))&TRNG_SA_TRNG_INT_CTRL_UNUSED_MASK)
/* SA_TRNG_INT_MASK Bit Fields */
#define TRNG_SA_TRNG_INT_MASK_HW_ERR_MASK 0x1u
#define TRNG_SA_TRNG_INT_MASK_HW_ERR_SHIFT 0
#define TRNG_SA_TRNG_INT_MASK_HW_ERR_WIDTH 1
#define TRNG_SA_TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_MASK_HW_ERR_SHIFT))&TRNG_SA_TRNG_INT_MASK_HW_ERR_MASK)
#define TRNG_SA_TRNG_INT_MASK_ENT_VAL_MASK 0x2u
#define TRNG_SA_TRNG_INT_MASK_ENT_VAL_SHIFT 1
#define TRNG_SA_TRNG_INT_MASK_ENT_VAL_WIDTH 1
#define TRNG_SA_TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_MASK_ENT_VAL_SHIFT))&TRNG_SA_TRNG_INT_MASK_ENT_VAL_MASK)
#define TRNG_SA_TRNG_INT_MASK_FRQ_CT_FAIL_MASK 0x4u
#define TRNG_SA_TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT 2
#define TRNG_SA_TRNG_INT_MASK_FRQ_CT_FAIL_WIDTH 1
#define TRNG_SA_TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT))&TRNG_SA_TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
/* SA_TRNG_INT_STATUS Bit Fields */
#define TRNG_SA_TRNG_INT_STATUS_HW_ERR_MASK 0x1u
#define TRNG_SA_TRNG_INT_STATUS_HW_ERR_SHIFT 0
#define TRNG_SA_TRNG_INT_STATUS_HW_ERR_WIDTH 1
#define TRNG_SA_TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_STATUS_HW_ERR_SHIFT))&TRNG_SA_TRNG_INT_STATUS_HW_ERR_MASK)
#define TRNG_SA_TRNG_INT_STATUS_ENT_VAL_MASK 0x2u
#define TRNG_SA_TRNG_INT_STATUS_ENT_VAL_SHIFT 1
#define TRNG_SA_TRNG_INT_STATUS_ENT_VAL_WIDTH 1
#define TRNG_SA_TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_STATUS_ENT_VAL_SHIFT))&TRNG_SA_TRNG_INT_STATUS_ENT_VAL_MASK)
#define TRNG_SA_TRNG_INT_STATUS_FRQ_CT_FAIL_MASK 0x4u
#define TRNG_SA_TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT 2
#define TRNG_SA_TRNG_INT_STATUS_FRQ_CT_FAIL_WIDTH 1
#define TRNG_SA_TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT))&TRNG_SA_TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
/* SA_TRNG_VID1 Bit Fields */
#define TRNG_SA_TRNG_VID1_RNG_MIN_REV_MASK 0xFFu
#define TRNG_SA_TRNG_VID1_RNG_MIN_REV_SHIFT 0
#define TRNG_SA_TRNG_VID1_RNG_MIN_REV_WIDTH 8
#define TRNG_SA_TRNG_VID1_RNG_MIN_REV(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_VID1_RNG_MIN_REV_SHIFT))&TRNG_SA_TRNG_VID1_RNG_MIN_REV_MASK)
#define TRNG_SA_TRNG_VID1_RNG_MAJ_REV_MASK 0xFF00u
#define TRNG_SA_TRNG_VID1_RNG_MAJ_REV_SHIFT 8
#define TRNG_SA_TRNG_VID1_RNG_MAJ_REV_WIDTH 8
#define TRNG_SA_TRNG_VID1_RNG_MAJ_REV(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_VID1_RNG_MAJ_REV_SHIFT))&TRNG_SA_TRNG_VID1_RNG_MAJ_REV_MASK)
#define TRNG_SA_TRNG_VID1_RNG_IP_ID_MASK 0xFFFF0000u
#define TRNG_SA_TRNG_VID1_RNG_IP_ID_SHIFT 16
#define TRNG_SA_TRNG_VID1_RNG_IP_ID_WIDTH 16
#define TRNG_SA_TRNG_VID1_RNG_IP_ID(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_VID1_RNG_IP_ID_SHIFT))&TRNG_SA_TRNG_VID1_RNG_IP_ID_MASK)
/* SA_TRNG_VID2 Bit Fields */
#define TRNG_SA_TRNG_VID2_RNG_CONFIG_OPT_MASK 0xFFu
#define TRNG_SA_TRNG_VID2_RNG_CONFIG_OPT_SHIFT 0
#define TRNG_SA_TRNG_VID2_RNG_CONFIG_OPT_WIDTH 8
#define TRNG_SA_TRNG_VID2_RNG_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_VID2_RNG_CONFIG_OPT_SHIFT))&TRNG_SA_TRNG_VID2_RNG_CONFIG_OPT_MASK)
#define TRNG_SA_TRNG_VID2_RNG_ECO_REV_MASK 0xFF00u
#define TRNG_SA_TRNG_VID2_RNG_ECO_REV_SHIFT 8
#define TRNG_SA_TRNG_VID2_RNG_ECO_REV_WIDTH 8
#define TRNG_SA_TRNG_VID2_RNG_ECO_REV(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_VID2_RNG_ECO_REV_SHIFT))&TRNG_SA_TRNG_VID2_RNG_ECO_REV_MASK)
#define TRNG_SA_TRNG_VID2_RNG_INTG_OPT_MASK 0xFF0000u
#define TRNG_SA_TRNG_VID2_RNG_INTG_OPT_SHIFT 16
#define TRNG_SA_TRNG_VID2_RNG_INTG_OPT_WIDTH 8
#define TRNG_SA_TRNG_VID2_RNG_INTG_OPT(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_VID2_RNG_INTG_OPT_SHIFT))&TRNG_SA_TRNG_VID2_RNG_INTG_OPT_MASK)
#define TRNG_SA_TRNG_VID2_RNG_ERA_MASK 0xFF000000u
#define TRNG_SA_TRNG_VID2_RNG_ERA_SHIFT 24
#define TRNG_SA_TRNG_VID2_RNG_ERA_WIDTH 8
#define TRNG_SA_TRNG_VID2_RNG_ERA(x) (((uint32_t)(((uint32_t)(x))<<TRNG_SA_TRNG_VID2_RNG_ERA_SHIFT))&TRNG_SA_TRNG_VID2_RNG_ERA_MASK)
/*!
* @}
*/ /* end of group TRNG_Register_Masks */
/* TRNG - Peripheral instance base addresses */
/** Peripheral TRNG base address */
#define TRNG_BASE (0x400A5000u)
/** Peripheral TRNG base pointer */
#define TRNG ((TRNG_Type *)TRNG_BASE)
#define TRNG_BASE_PTR (TRNG)
/** Array initializer of TRNG peripheral base addresses */
#define TRNG_BASE_ADDRS { TRNG_BASE }
/** Array initializer of TRNG peripheral base pointers */
#define TRNG_BASE_PTRS { TRNG }
/* ----------------------------------------------------------------------------
-- TRNG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Register_Accessor_Macros TRNG - Register accessor macros
* @{
*/
/* TRNG - Register instance definitions */
/* TRNG */
#define TRNG_RTMCTL TRNG_RTMCTL_REG(TRNG)
#define TRNG_RTSCMISC TRNG_RTSCMISC_REG(TRNG)
#define TRNG_RTPKRRNG TRNG_RTPKRRNG_REG(TRNG)
#define TRNG_RTPKRMAX TRNG_RTPKRMAX_REG(TRNG)
#define TRNG_RTPKRSQ TRNG_RTPKRSQ_REG(TRNG)
#define TRNG_RTSDCTL TRNG_RTSDCTL_REG(TRNG)
#define TRNG_RTSBLIM TRNG_RTSBLIM_REG(TRNG)
#define TRNG_RTTOTSAM TRNG_RTTOTSAM_REG(TRNG)
#define TRNG_RTFRQMIN TRNG_RTFRQMIN_REG(TRNG)
#define TRNG_RTFRQCNT TRNG_RTFRQCNT_REG(TRNG)
#define TRNG_RTFRQMAX TRNG_RTFRQMAX_REG(TRNG)
#define TRNG_RTSCMC TRNG_RTSCMC_REG(TRNG)
#define TRNG_RTSCML TRNG_RTSCML_REG(TRNG)
#define TRNG_RTSCR1C TRNG_RTSCR1C_REG(TRNG)
#define TRNG_RTSCR1L TRNG_RTSCR1L_REG(TRNG)
#define TRNG_RTSCR2C TRNG_RTSCR2C_REG(TRNG)
#define TRNG_RTSCR2L TRNG_RTSCR2L_REG(TRNG)
#define TRNG_RTSCR3C TRNG_RTSCR3C_REG(TRNG)
#define TRNG_RTSCR3L TRNG_RTSCR3L_REG(TRNG)
#define TRNG_RTSCR4C TRNG_RTSCR4C_REG(TRNG)
#define TRNG_RTSCR4L TRNG_RTSCR4L_REG(TRNG)
#define TRNG_RTSCR5C TRNG_RTSCR5C_REG(TRNG)
#define TRNG_RTSCR5L TRNG_RTSCR5L_REG(TRNG)
#define TRNG_RTSCR6PC TRNG_RTSCR6PC_REG(TRNG)
#define TRNG_RTSCR6PL TRNG_RTSCR6PL_REG(TRNG)
#define TRNG_RTSTATUS TRNG_RTSTATUS_REG(TRNG)
#define TRNG_RTENT0 TRNG_RTENT0_REG(TRNG)
#define TRNG_RTENT1 TRNG_RTENT1_REG(TRNG)
#define TRNG_RTENT2 TRNG_RTENT2_REG(TRNG)
#define TRNG_RTENT3 TRNG_RTENT3_REG(TRNG)
#define TRNG_RTENT4 TRNG_RTENT4_REG(TRNG)
#define TRNG_RTENT5 TRNG_RTENT5_REG(TRNG)
#define TRNG_RTENT6 TRNG_RTENT6_REG(TRNG)
#define TRNG_RTENT7 TRNG_RTENT7_REG(TRNG)
#define TRNG_RTENT8 TRNG_RTENT8_REG(TRNG)
#define TRNG_RTENT9 TRNG_RTENT9_REG(TRNG)
#define TRNG_RTENT10 TRNG_RTENT10_REG(TRNG)
#define TRNG_RTENT11 TRNG_RTENT11_REG(TRNG)
#define TRNG_RTENT12 TRNG_RTENT12_REG(TRNG)
#define TRNG_RTENT13 TRNG_RTENT13_REG(TRNG)
#define TRNG_RTENT14 TRNG_RTENT14_REG(TRNG)
#define TRNG_RTENT15 TRNG_RTENT15_REG(TRNG)
#define TRNG_RTPKRCNT10 TRNG_RTPKRCNT10_REG(TRNG)
#define TRNG_RTPKRCNT32 TRNG_RTPKRCNT32_REG(TRNG)
#define TRNG_RTPKRCNT54 TRNG_RTPKRCNT54_REG(TRNG)
#define TRNG_RTPKRCNT76 TRNG_RTPKRCNT76_REG(TRNG)
#define TRNG_RTPKRCNT98 TRNG_RTPKRCNT98_REG(TRNG)
#define TRNG_RTPKRCNTBA TRNG_RTPKRCNTBA_REG(TRNG)
#define TRNG_RTPKRCNTDC TRNG_RTPKRCNTDC_REG(TRNG)
#define TRNG_RTPKRCNTFE TRNG_RTPKRCNTFE_REG(TRNG)
#define TRNG_SA_TRNG_SEC_CFG TRNG_SA_TRNG_SEC_CFG_REG(TRNG)
#define TRNG_SA_TRNG_INT_CTRL TRNG_SA_TRNG_INT_CTRL_REG(TRNG)
#define TRNG_SA_TRNG_INT_MASK TRNG_SA_TRNG_INT_MASK_REG(TRNG)
#define TRNG_SA_TRNG_INT_STATUS TRNG_SA_TRNG_INT_STATUS_REG(TRNG)
#define TRNG_SA_TRNG_VID1 TRNG_SA_TRNG_VID1_REG(TRNG)
#define TRNG_SA_TRNG_VID2 TRNG_SA_TRNG_VID2_REG(TRNG)
/*!
* @}
*/ /* end of group TRNG_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group TRNG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TSI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
* @{
*/
/** TSI - Register Layout Typedef */
typedef struct {
__IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
__IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
__IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
} TSI_Type, *TSI_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TSI - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
* @{
*/
/* TSI - Register accessors */
#define TSI_GENCS_REG(base) ((base)->GENCS)
#define TSI_DATA_REG(base) ((base)->DATA)
#define TSI_TSHD_REG(base) ((base)->TSHD)
/*!
* @}
*/ /* end of group TSI_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TSI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSI_Register_Masks TSI Register Masks
* @{
*/
/* GENCS Bit Fields */
#define TSI_GENCS_EOSDMEO_MASK 0x1u
#define TSI_GENCS_EOSDMEO_SHIFT 0
#define TSI_GENCS_EOSDMEO_WIDTH 1
#define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EOSDMEO_SHIFT))&TSI_GENCS_EOSDMEO_MASK)
#define TSI_GENCS_CURSW_MASK 0x2u
#define TSI_GENCS_CURSW_SHIFT 1
#define TSI_GENCS_CURSW_WIDTH 1
#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_CURSW_SHIFT))&TSI_GENCS_CURSW_MASK)
#define TSI_GENCS_EOSF_MASK 0x4u
#define TSI_GENCS_EOSF_SHIFT 2
#define TSI_GENCS_EOSF_WIDTH 1
#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EOSF_SHIFT))&TSI_GENCS_EOSF_MASK)
#define TSI_GENCS_SCNIP_MASK 0x8u
#define TSI_GENCS_SCNIP_SHIFT 3
#define TSI_GENCS_SCNIP_WIDTH 1
#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_SCNIP_SHIFT))&TSI_GENCS_SCNIP_MASK)
#define TSI_GENCS_STM_MASK 0x10u
#define TSI_GENCS_STM_SHIFT 4
#define TSI_GENCS_STM_WIDTH 1
#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_STM_SHIFT))&TSI_GENCS_STM_MASK)
#define TSI_GENCS_STPE_MASK 0x20u
#define TSI_GENCS_STPE_SHIFT 5
#define TSI_GENCS_STPE_WIDTH 1
#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_STPE_SHIFT))&TSI_GENCS_STPE_MASK)
#define TSI_GENCS_TSIIEN_MASK 0x40u
#define TSI_GENCS_TSIIEN_SHIFT 6
#define TSI_GENCS_TSIIEN_WIDTH 1
#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_TSIIEN_SHIFT))&TSI_GENCS_TSIIEN_MASK)
#define TSI_GENCS_TSIEN_MASK 0x80u
#define TSI_GENCS_TSIEN_SHIFT 7
#define TSI_GENCS_TSIEN_WIDTH 1
#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_TSIEN_SHIFT))&TSI_GENCS_TSIEN_MASK)
#define TSI_GENCS_NSCN_MASK 0x1F00u
#define TSI_GENCS_NSCN_SHIFT 8
#define TSI_GENCS_NSCN_WIDTH 5
#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
#define TSI_GENCS_PS_MASK 0xE000u
#define TSI_GENCS_PS_SHIFT 13
#define TSI_GENCS_PS_WIDTH 3
#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
#define TSI_GENCS_EXTCHRG_MASK 0x70000u
#define TSI_GENCS_EXTCHRG_SHIFT 16
#define TSI_GENCS_EXTCHRG_WIDTH 3
#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
#define TSI_GENCS_DVOLT_MASK 0x180000u
#define TSI_GENCS_DVOLT_SHIFT 19
#define TSI_GENCS_DVOLT_WIDTH 2
#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
#define TSI_GENCS_REFCHRG_MASK 0xE00000u
#define TSI_GENCS_REFCHRG_SHIFT 21
#define TSI_GENCS_REFCHRG_WIDTH 3
#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
#define TSI_GENCS_MODE_MASK 0xF000000u
#define TSI_GENCS_MODE_SHIFT 24
#define TSI_GENCS_MODE_WIDTH 4
#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
#define TSI_GENCS_ESOR_MASK 0x10000000u
#define TSI_GENCS_ESOR_SHIFT 28
#define TSI_GENCS_ESOR_WIDTH 1
#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_ESOR_SHIFT))&TSI_GENCS_ESOR_MASK)
#define TSI_GENCS_OUTRGF_MASK 0x80000000u
#define TSI_GENCS_OUTRGF_SHIFT 31
#define TSI_GENCS_OUTRGF_WIDTH 1
#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_OUTRGF_SHIFT))&TSI_GENCS_OUTRGF_MASK)
/* DATA Bit Fields */
#define TSI_DATA_TSICNT_MASK 0xFFFFu
#define TSI_DATA_TSICNT_SHIFT 0
#define TSI_DATA_TSICNT_WIDTH 16
#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
#define TSI_DATA_SWTS_MASK 0x400000u
#define TSI_DATA_SWTS_SHIFT 22
#define TSI_DATA_SWTS_WIDTH 1
#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_SWTS_SHIFT))&TSI_DATA_SWTS_MASK)
#define TSI_DATA_DMAEN_MASK 0x800000u
#define TSI_DATA_DMAEN_SHIFT 23
#define TSI_DATA_DMAEN_WIDTH 1
#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_DMAEN_SHIFT))&TSI_DATA_DMAEN_MASK)
#define TSI_DATA_TSICH_MASK 0xF0000000u
#define TSI_DATA_TSICH_SHIFT 28
#define TSI_DATA_TSICH_WIDTH 4
#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
/* TSHD Bit Fields */
#define TSI_TSHD_THRESL_MASK 0xFFFFu
#define TSI_TSHD_THRESL_SHIFT 0
#define TSI_TSHD_THRESL_WIDTH 16
#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
#define TSI_TSHD_THRESH_SHIFT 16
#define TSI_TSHD_THRESH_WIDTH 16
#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
/*!
* @}
*/ /* end of group TSI_Register_Masks */
/* TSI - Peripheral instance base addresses */
/** Peripheral TSI0 base address */
#define TSI0_BASE (0x40062000u)
/** Peripheral TSI0 base pointer */
#define TSI0 ((TSI_Type *)TSI0_BASE)
#define TSI0_BASE_PTR (TSI0)
/** Array initializer of TSI peripheral base addresses */
#define TSI_BASE_ADDRS { TSI0_BASE }
/** Array initializer of TSI peripheral base pointers */
#define TSI_BASE_PTRS { TSI0 }
/* ----------------------------------------------------------------------------
-- TSI - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
* @{
*/
/* TSI - Register instance definitions */
/* TSI0 */
#define TSI0_GENCS TSI_GENCS_REG(TSI0)
#define TSI0_DATA TSI_DATA_REG(TSI0)
#define TSI0_TSHD TSI_TSHD_REG(TSI0)
/*!
* @}
*/ /* end of group TSI_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group TSI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TSTMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
* @{
*/
/** TSTMR - Register Layout Typedef */
typedef struct {
__I uint32_t L; /**< Time Stamp Timer Register Low, offset: 0x0 */
__I uint32_t H; /**< Time Stamp Timer Register High, offset: 0x4 */
} TSTMR_Type, *TSTMR_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TSTMR - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSTMR_Register_Accessor_Macros TSTMR - Register accessor macros
* @{
*/
/* TSTMR - Register accessors */
#define TSTMR_L_REG(base) ((base)->L)
#define TSTMR_H_REG(base) ((base)->H)
/*!
* @}
*/ /* end of group TSTMR_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TSTMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSTMR_Register_Masks TSTMR Register Masks
* @{
*/
/* L Bit Fields */
#define TSTMR_L_VALUE_MASK 0xFFFFFFFFu
#define TSTMR_L_VALUE_SHIFT 0
#define TSTMR_L_VALUE_WIDTH 32
#define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TSTMR_L_VALUE_SHIFT))&TSTMR_L_VALUE_MASK)
/* H Bit Fields */
#define TSTMR_H_VALUE_MASK 0xFFFFFFu
#define TSTMR_H_VALUE_SHIFT 0
#define TSTMR_H_VALUE_WIDTH 24
#define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TSTMR_H_VALUE_SHIFT))&TSTMR_H_VALUE_MASK)
/*!
* @}
*/ /* end of group TSTMR_Register_Masks */
/* TSTMR - Peripheral instance base addresses */
/** Peripheral TSTMR0 base address */
#define TSTMR0_BASE (0x400750F0u)
/** Peripheral TSTMR0 base pointer */
#define TSTMR0 ((TSTMR_Type *)TSTMR0_BASE)
#define TSTMR0_BASE_PTR (TSTMR0)
/** Peripheral TSTMR1 base address */
#define TSTMR1_BASE (0x400F50F0u)
/** Peripheral TSTMR1 base pointer */
#define TSTMR1 ((TSTMR_Type *)TSTMR1_BASE)
#define TSTMR1_BASE_PTR (TSTMR1)
/** Array initializer of TSTMR peripheral base addresses */
#define TSTMR_BASE_ADDRS { TSTMR0_BASE, TSTMR1_BASE }
/** Array initializer of TSTMR peripheral base pointers */
#define TSTMR_BASE_PTRS { TSTMR0, TSTMR1 }
/* ----------------------------------------------------------------------------
-- TSTMR - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSTMR_Register_Accessor_Macros TSTMR - Register accessor macros
* @{
*/
/* TSTMR - Register instance definitions */
/* TSTMR0 */
#define TSTMR0_L TSTMR_L_REG(TSTMR0)
#define TSTMR0_H TSTMR_H_REG(TSTMR0)
/* TSTMR1 */
#define TSTMR1_L TSTMR_L_REG(TSTMR1)
#define TSTMR1_H TSTMR_H_REG(TSTMR1)
/*!
* @}
*/ /* end of group TSTMR_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group TSTMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
* @{
*/
/** USB - Register Layout Typedef */
typedef struct {
__I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
uint8_t RESERVED_0[3];
__I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
uint8_t RESERVED_1[3];
__I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
uint8_t RESERVED_2[3];
__I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
uint8_t RESERVED_3[3];
__IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
uint8_t RESERVED_4[3];
__IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
uint8_t RESERVED_5[3];
__IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
uint8_t RESERVED_6[3];
__IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
uint8_t RESERVED_7[99];
__IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
uint8_t RESERVED_8[3];
__IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
uint8_t RESERVED_9[3];
__IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
uint8_t RESERVED_10[3];
__IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
uint8_t RESERVED_11[3];
__I uint8_t STAT; /**< Status register, offset: 0x90 */
uint8_t RESERVED_12[3];
__IO uint8_t CTL; /**< Control register, offset: 0x94 */
uint8_t RESERVED_13[3];
__IO uint8_t ADDR; /**< Address register, offset: 0x98 */
uint8_t RESERVED_14[3];
__IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
uint8_t RESERVED_15[3];
__IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
uint8_t RESERVED_16[3];
__IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
uint8_t RESERVED_17[3];
__IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
uint8_t RESERVED_18[3];
__IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
uint8_t RESERVED_19[3];
__IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
uint8_t RESERVED_20[3];
__IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
uint8_t RESERVED_21[11];
struct { /* offset: 0xC0, array step: 0x4 */
__IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_0[3];
} ENDPOINT[16];
__IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
uint8_t RESERVED_22[3];
__I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
uint8_t RESERVED_23[3];
__IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
uint8_t RESERVED_24[3];
__IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
uint8_t RESERVED_25[7];
__IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
uint8_t RESERVED_26[15];
__IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive mode control, offset: 0x124 */
uint8_t RESERVED_27[3];
__IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive mode wakeup control, offset: 0x128 */
uint8_t RESERVED_28[3];
__IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */
uint8_t RESERVED_29[19];
__IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
uint8_t RESERVED_30[3];
__IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
uint8_t RESERVED_31[15];
__IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
uint8_t RESERVED_32[7];
__IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
} USB_Type, *USB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- USB - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
* @{
*/
/* USB - Register accessors */
#define USB_PERID_REG(base) ((base)->PERID)
#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
#define USB_REV_REG(base) ((base)->REV)
#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
#define USB_OTGICR_REG(base) ((base)->OTGICR)
#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
#define USB_ISTAT_REG(base) ((base)->ISTAT)
#define USB_INTEN_REG(base) ((base)->INTEN)
#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
#define USB_ERREN_REG(base) ((base)->ERREN)
#define USB_STAT_REG(base) ((base)->STAT)
#define USB_CTL_REG(base) ((base)->CTL)
#define USB_ADDR_REG(base) ((base)->ADDR)
#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
#define USB_TOKEN_REG(base) ((base)->TOKEN)
#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
#define USB_ENDPT_COUNT 16
#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
#define USB_CONTROL_REG(base) ((base)->CONTROL)
#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
#define USB_KEEP_ALIVE_CTRL_REG(base) ((base)->KEEP_ALIVE_CTRL)
#define USB_KEEP_ALIVE_WKCTRL_REG(base) ((base)->KEEP_ALIVE_WKCTRL)
#define USB_MISCCTRL_REG(base) ((base)->MISCCTRL)
#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
/*!
* @}
*/ /* end of group USB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- USB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
/* PERID Bit Fields */
#define USB_PERID_ID_MASK 0x3Fu
#define USB_PERID_ID_SHIFT 0
#define USB_PERID_ID_WIDTH 6
#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
/* IDCOMP Bit Fields */
#define USB_IDCOMP_NID_MASK 0x3Fu
#define USB_IDCOMP_NID_SHIFT 0
#define USB_IDCOMP_NID_WIDTH 6
#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
/* REV Bit Fields */
#define USB_REV_REV_MASK 0xFFu
#define USB_REV_REV_SHIFT 0
#define USB_REV_REV_WIDTH 8
#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
/* ADDINFO Bit Fields */
#define USB_ADDINFO_IEHOST_MASK 0x1u
#define USB_ADDINFO_IEHOST_SHIFT 0
#define USB_ADDINFO_IEHOST_WIDTH 1
#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
/* OTGISTAT Bit Fields */
#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
#define USB_OTGISTAT_AVBUSCHG_WIDTH 1
#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
#define USB_OTGISTAT_B_SESS_CHG_WIDTH 1
#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
#define USB_OTGISTAT_SESSVLDCHG_WIDTH 1
#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH 1
#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
#define USB_OTGISTAT_ONEMSEC_SHIFT 6
#define USB_OTGISTAT_ONEMSEC_WIDTH 1
#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
#define USB_OTGISTAT_IDCHG_MASK 0x80u
#define USB_OTGISTAT_IDCHG_SHIFT 7
#define USB_OTGISTAT_IDCHG_WIDTH 1
#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
/* OTGICR Bit Fields */
#define USB_OTGICR_AVBUSEN_MASK 0x1u
#define USB_OTGICR_AVBUSEN_SHIFT 0
#define USB_OTGICR_AVBUSEN_WIDTH 1
#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
#define USB_OTGICR_BSESSEN_MASK 0x4u
#define USB_OTGICR_BSESSEN_SHIFT 2
#define USB_OTGICR_BSESSEN_WIDTH 1
#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
#define USB_OTGICR_SESSVLDEN_MASK 0x8u
#define USB_OTGICR_SESSVLDEN_SHIFT 3
#define USB_OTGICR_SESSVLDEN_WIDTH 1
#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
#define USB_OTGICR_LINESTATEEN_MASK 0x20u
#define USB_OTGICR_LINESTATEEN_SHIFT 5
#define USB_OTGICR_LINESTATEEN_WIDTH 1
#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
#define USB_OTGICR_ONEMSECEN_MASK 0x40u
#define USB_OTGICR_ONEMSECEN_SHIFT 6
#define USB_OTGICR_ONEMSECEN_WIDTH 1
#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
#define USB_OTGICR_IDEN_MASK 0x80u
#define USB_OTGICR_IDEN_SHIFT 7
#define USB_OTGICR_IDEN_WIDTH 1
#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
/* OTGSTAT Bit Fields */
#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
#define USB_OTGSTAT_AVBUSVLD_WIDTH 1
#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
#define USB_OTGSTAT_BSESSEND_MASK 0x4u
#define USB_OTGSTAT_BSESSEND_SHIFT 2
#define USB_OTGSTAT_BSESSEND_WIDTH 1
#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
#define USB_OTGSTAT_SESS_VLD_SHIFT 3
#define USB_OTGSTAT_SESS_VLD_WIDTH 1
#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
#define USB_OTGSTAT_LINESTATESTABLE_WIDTH 1
#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
#define USB_OTGSTAT_ONEMSECEN_WIDTH 1
#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
#define USB_OTGSTAT_ID_MASK 0x80u
#define USB_OTGSTAT_ID_SHIFT 7
#define USB_OTGSTAT_ID_WIDTH 1
#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
/* OTGCTL Bit Fields */
#define USB_OTGCTL_OTGEN_MASK 0x4u
#define USB_OTGCTL_OTGEN_SHIFT 2
#define USB_OTGCTL_OTGEN_WIDTH 1
#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
#define USB_OTGCTL_DMLOW_MASK 0x10u
#define USB_OTGCTL_DMLOW_SHIFT 4
#define USB_OTGCTL_DMLOW_WIDTH 1
#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
#define USB_OTGCTL_DPLOW_MASK 0x20u
#define USB_OTGCTL_DPLOW_SHIFT 5
#define USB_OTGCTL_DPLOW_WIDTH 1
#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
#define USB_OTGCTL_DPHIGH_MASK 0x80u
#define USB_OTGCTL_DPHIGH_SHIFT 7
#define USB_OTGCTL_DPHIGH_WIDTH 1
#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
/* ISTAT Bit Fields */
#define USB_ISTAT_USBRST_MASK 0x1u
#define USB_ISTAT_USBRST_SHIFT 0
#define USB_ISTAT_USBRST_WIDTH 1
#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
#define USB_ISTAT_ERROR_MASK 0x2u
#define USB_ISTAT_ERROR_SHIFT 1
#define USB_ISTAT_ERROR_WIDTH 1
#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
#define USB_ISTAT_SOFTOK_MASK 0x4u
#define USB_ISTAT_SOFTOK_SHIFT 2
#define USB_ISTAT_SOFTOK_WIDTH 1
#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
#define USB_ISTAT_TOKDNE_MASK 0x8u
#define USB_ISTAT_TOKDNE_SHIFT 3
#define USB_ISTAT_TOKDNE_WIDTH 1
#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
#define USB_ISTAT_SLEEP_MASK 0x10u
#define USB_ISTAT_SLEEP_SHIFT 4
#define USB_ISTAT_SLEEP_WIDTH 1
#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
#define USB_ISTAT_RESUME_MASK 0x20u
#define USB_ISTAT_RESUME_SHIFT 5
#define USB_ISTAT_RESUME_WIDTH 1
#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
#define USB_ISTAT_ATTACH_MASK 0x40u
#define USB_ISTAT_ATTACH_SHIFT 6
#define USB_ISTAT_ATTACH_WIDTH 1
#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
#define USB_ISTAT_STALL_MASK 0x80u
#define USB_ISTAT_STALL_SHIFT 7
#define USB_ISTAT_STALL_WIDTH 1
#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
/* INTEN Bit Fields */
#define USB_INTEN_USBRSTEN_MASK 0x1u
#define USB_INTEN_USBRSTEN_SHIFT 0
#define USB_INTEN_USBRSTEN_WIDTH 1
#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
#define USB_INTEN_ERROREN_MASK 0x2u
#define USB_INTEN_ERROREN_SHIFT 1
#define USB_INTEN_ERROREN_WIDTH 1
#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
#define USB_INTEN_SOFTOKEN_MASK 0x4u
#define USB_INTEN_SOFTOKEN_SHIFT 2
#define USB_INTEN_SOFTOKEN_WIDTH 1
#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
#define USB_INTEN_TOKDNEEN_MASK 0x8u
#define USB_INTEN_TOKDNEEN_SHIFT 3
#define USB_INTEN_TOKDNEEN_WIDTH 1
#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
#define USB_INTEN_SLEEPEN_MASK 0x10u
#define USB_INTEN_SLEEPEN_SHIFT 4
#define USB_INTEN_SLEEPEN_WIDTH 1
#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
#define USB_INTEN_RESUMEEN_MASK 0x20u
#define USB_INTEN_RESUMEEN_SHIFT 5
#define USB_INTEN_RESUMEEN_WIDTH 1
#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
#define USB_INTEN_ATTACHEN_MASK 0x40u
#define USB_INTEN_ATTACHEN_SHIFT 6
#define USB_INTEN_ATTACHEN_WIDTH 1
#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
#define USB_INTEN_STALLEN_MASK 0x80u
#define USB_INTEN_STALLEN_SHIFT 7
#define USB_INTEN_STALLEN_WIDTH 1
#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
/* ERRSTAT Bit Fields */
#define USB_ERRSTAT_PIDERR_MASK 0x1u
#define USB_ERRSTAT_PIDERR_SHIFT 0
#define USB_ERRSTAT_PIDERR_WIDTH 1
#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
#define USB_ERRSTAT_CRC5EOF_SHIFT 1
#define USB_ERRSTAT_CRC5EOF_WIDTH 1
#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
#define USB_ERRSTAT_CRC16_MASK 0x4u
#define USB_ERRSTAT_CRC16_SHIFT 2
#define USB_ERRSTAT_CRC16_WIDTH 1
#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
#define USB_ERRSTAT_DFN8_MASK 0x8u
#define USB_ERRSTAT_DFN8_SHIFT 3
#define USB_ERRSTAT_DFN8_WIDTH 1
#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
#define USB_ERRSTAT_BTOERR_MASK 0x10u
#define USB_ERRSTAT_BTOERR_SHIFT 4
#define USB_ERRSTAT_BTOERR_WIDTH 1
#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
#define USB_ERRSTAT_DMAERR_MASK 0x20u
#define USB_ERRSTAT_DMAERR_SHIFT 5
#define USB_ERRSTAT_DMAERR_WIDTH 1
#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
#define USB_ERRSTAT_OWNERR_MASK 0x40u
#define USB_ERRSTAT_OWNERR_SHIFT 6
#define USB_ERRSTAT_OWNERR_WIDTH 1
#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_OWNERR_SHIFT))&USB_ERRSTAT_OWNERR_MASK)
#define USB_ERRSTAT_BTSERR_MASK 0x80u
#define USB_ERRSTAT_BTSERR_SHIFT 7
#define USB_ERRSTAT_BTSERR_WIDTH 1
#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
/* ERREN Bit Fields */
#define USB_ERREN_PIDERREN_MASK 0x1u
#define USB_ERREN_PIDERREN_SHIFT 0
#define USB_ERREN_PIDERREN_WIDTH 1
#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
#define USB_ERREN_CRC5EOFEN_MASK 0x2u
#define USB_ERREN_CRC5EOFEN_SHIFT 1
#define USB_ERREN_CRC5EOFEN_WIDTH 1
#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
#define USB_ERREN_CRC16EN_MASK 0x4u
#define USB_ERREN_CRC16EN_SHIFT 2
#define USB_ERREN_CRC16EN_WIDTH 1
#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
#define USB_ERREN_DFN8EN_MASK 0x8u
#define USB_ERREN_DFN8EN_SHIFT 3
#define USB_ERREN_DFN8EN_WIDTH 1
#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
#define USB_ERREN_BTOERREN_MASK 0x10u
#define USB_ERREN_BTOERREN_SHIFT 4
#define USB_ERREN_BTOERREN_WIDTH 1
#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
#define USB_ERREN_DMAERREN_MASK 0x20u
#define USB_ERREN_DMAERREN_SHIFT 5
#define USB_ERREN_DMAERREN_WIDTH 1
#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
#define USB_ERREN_OWNERREN_MASK 0x40u
#define USB_ERREN_OWNERREN_SHIFT 6
#define USB_ERREN_OWNERREN_WIDTH 1
#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_OWNERREN_SHIFT))&USB_ERREN_OWNERREN_MASK)
#define USB_ERREN_BTSERREN_MASK 0x80u
#define USB_ERREN_BTSERREN_SHIFT 7
#define USB_ERREN_BTSERREN_WIDTH 1
#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
/* STAT Bit Fields */
#define USB_STAT_ODD_MASK 0x4u
#define USB_STAT_ODD_SHIFT 2
#define USB_STAT_ODD_WIDTH 1
#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
#define USB_STAT_TX_MASK 0x8u
#define USB_STAT_TX_SHIFT 3
#define USB_STAT_TX_WIDTH 1
#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
#define USB_STAT_ENDP_MASK 0xF0u
#define USB_STAT_ENDP_SHIFT 4
#define USB_STAT_ENDP_WIDTH 4
#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
/* CTL Bit Fields */
#define USB_CTL_USBENSOFEN_MASK 0x1u
#define USB_CTL_USBENSOFEN_SHIFT 0
#define USB_CTL_USBENSOFEN_WIDTH 1
#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
#define USB_CTL_ODDRST_MASK 0x2u
#define USB_CTL_ODDRST_SHIFT 1
#define USB_CTL_ODDRST_WIDTH 1
#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
#define USB_CTL_RESUME_MASK 0x4u
#define USB_CTL_RESUME_SHIFT 2
#define USB_CTL_RESUME_WIDTH 1
#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
#define USB_CTL_HOSTMODEEN_MASK 0x8u
#define USB_CTL_HOSTMODEEN_SHIFT 3
#define USB_CTL_HOSTMODEEN_WIDTH 1
#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
#define USB_CTL_RESET_MASK 0x10u
#define USB_CTL_RESET_SHIFT 4
#define USB_CTL_RESET_WIDTH 1
#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH 1
#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
#define USB_CTL_SE0_MASK 0x40u
#define USB_CTL_SE0_SHIFT 6
#define USB_CTL_SE0_WIDTH 1
#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
#define USB_CTL_JSTATE_MASK 0x80u
#define USB_CTL_JSTATE_SHIFT 7
#define USB_CTL_JSTATE_WIDTH 1
#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
/* ADDR Bit Fields */
#define USB_ADDR_ADDR_MASK 0x7Fu
#define USB_ADDR_ADDR_SHIFT 0
#define USB_ADDR_ADDR_WIDTH 7
#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
#define USB_ADDR_LSEN_MASK 0x80u
#define USB_ADDR_LSEN_SHIFT 7
#define USB_ADDR_LSEN_WIDTH 1
#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
/* BDTPAGE1 Bit Fields */
#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
#define USB_BDTPAGE1_BDTBA_SHIFT 1
#define USB_BDTPAGE1_BDTBA_WIDTH 7
#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
/* FRMNUML Bit Fields */
#define USB_FRMNUML_FRM_MASK 0xFFu
#define USB_FRMNUML_FRM_SHIFT 0
#define USB_FRMNUML_FRM_WIDTH 8
#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
/* FRMNUMH Bit Fields */
#define USB_FRMNUMH_FRM_MASK 0x7u
#define USB_FRMNUMH_FRM_SHIFT 0
#define USB_FRMNUMH_FRM_WIDTH 3
#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
/* TOKEN Bit Fields */
#define USB_TOKEN_TOKENENDPT_MASK 0xFu
#define USB_TOKEN_TOKENENDPT_SHIFT 0
#define USB_TOKEN_TOKENENDPT_WIDTH 4
#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
#define USB_TOKEN_TOKENPID_MASK 0xF0u
#define USB_TOKEN_TOKENPID_SHIFT 4
#define USB_TOKEN_TOKENPID_WIDTH 4
#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
/* SOFTHLD Bit Fields */
#define USB_SOFTHLD_CNT_MASK 0xFFu
#define USB_SOFTHLD_CNT_SHIFT 0
#define USB_SOFTHLD_CNT_WIDTH 8
#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
/* BDTPAGE2 Bit Fields */
#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
#define USB_BDTPAGE2_BDTBA_SHIFT 0
#define USB_BDTPAGE2_BDTBA_WIDTH 8
#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
/* BDTPAGE3 Bit Fields */
#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
#define USB_BDTPAGE3_BDTBA_SHIFT 0
#define USB_BDTPAGE3_BDTBA_WIDTH 8
#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
/* ENDPT Bit Fields */
#define USB_ENDPT_EPHSHK_MASK 0x1u
#define USB_ENDPT_EPHSHK_SHIFT 0
#define USB_ENDPT_EPHSHK_WIDTH 1
#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
#define USB_ENDPT_EPSTALL_MASK 0x2u
#define USB_ENDPT_EPSTALL_SHIFT 1
#define USB_ENDPT_EPSTALL_WIDTH 1
#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
#define USB_ENDPT_EPTXEN_MASK 0x4u
#define USB_ENDPT_EPTXEN_SHIFT 2
#define USB_ENDPT_EPTXEN_WIDTH 1
#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
#define USB_ENDPT_EPRXEN_MASK 0x8u
#define USB_ENDPT_EPRXEN_SHIFT 3
#define USB_ENDPT_EPRXEN_WIDTH 1
#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
#define USB_ENDPT_EPCTLDIS_MASK 0x10u
#define USB_ENDPT_EPCTLDIS_SHIFT 4
#define USB_ENDPT_EPCTLDIS_WIDTH 1
#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
#define USB_ENDPT_RETRYDIS_MASK 0x40u
#define USB_ENDPT_RETRYDIS_SHIFT 6
#define USB_ENDPT_RETRYDIS_WIDTH 1
#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
#define USB_ENDPT_HOSTWOHUB_SHIFT 7
#define USB_ENDPT_HOSTWOHUB_WIDTH 1
#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
/* USBCTRL Bit Fields */
#define USB_USBCTRL_UARTSEL_MASK 0x10u
#define USB_USBCTRL_UARTSEL_SHIFT 4
#define USB_USBCTRL_UARTSEL_WIDTH 1
#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_UARTSEL_SHIFT))&USB_USBCTRL_UARTSEL_MASK)
#define USB_USBCTRL_UARTCHLS_MASK 0x20u
#define USB_USBCTRL_UARTCHLS_SHIFT 5
#define USB_USBCTRL_UARTCHLS_WIDTH 1
#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_UARTCHLS_SHIFT))&USB_USBCTRL_UARTCHLS_MASK)
#define USB_USBCTRL_PDE_MASK 0x40u
#define USB_USBCTRL_PDE_SHIFT 6
#define USB_USBCTRL_PDE_WIDTH 1
#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
#define USB_USBCTRL_SUSP_MASK 0x80u
#define USB_USBCTRL_SUSP_SHIFT 7
#define USB_USBCTRL_SUSP_WIDTH 1
#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
/* OBSERVE Bit Fields */
#define USB_OBSERVE_DMPD_MASK 0x10u
#define USB_OBSERVE_DMPD_SHIFT 4
#define USB_OBSERVE_DMPD_WIDTH 1
#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
#define USB_OBSERVE_DPPD_MASK 0x40u
#define USB_OBSERVE_DPPD_SHIFT 6
#define USB_OBSERVE_DPPD_WIDTH 1
#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
#define USB_OBSERVE_DPPU_MASK 0x80u
#define USB_OBSERVE_DPPU_SHIFT 7
#define USB_OBSERVE_DPPU_WIDTH 1
#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
/* CONTROL Bit Fields */
#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
#define USB_CONTROL_DPPULLUPNONOTG_WIDTH 1
#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
/* USBTRC0 Bit Fields */
#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
#define USB_USBTRC0_USB_RESUME_INT_WIDTH 1
#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
#define USB_USBTRC0_SYNC_DET_MASK 0x2u
#define USB_USBTRC0_SYNC_DET_SHIFT 1
#define USB_USBTRC0_SYNC_DET_WIDTH 1
#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH 1
#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
#define USB_USBTRC0_VREDG_DET_MASK 0x8u
#define USB_USBTRC0_VREDG_DET_SHIFT 3
#define USB_USBTRC0_VREDG_DET_WIDTH 1
#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_VREDG_DET_SHIFT))&USB_USBTRC0_VREDG_DET_MASK)
#define USB_USBTRC0_VFEDG_DET_MASK 0x10u
#define USB_USBTRC0_VFEDG_DET_SHIFT 4
#define USB_USBTRC0_VFEDG_DET_WIDTH 1
#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_VFEDG_DET_SHIFT))&USB_USBTRC0_VFEDG_DET_MASK)
#define USB_USBTRC0_USBRESMEN_MASK 0x20u
#define USB_USBTRC0_USBRESMEN_SHIFT 5
#define USB_USBTRC0_USBRESMEN_WIDTH 1
#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
#define USB_USBTRC0_USBRESET_MASK 0x80u
#define USB_USBTRC0_USBRESET_SHIFT 7
#define USB_USBTRC0_USBRESET_WIDTH 1
#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
/* USBFRMADJUST Bit Fields */
#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
#define USB_USBFRMADJUST_ADJ_SHIFT 0
#define USB_USBFRMADJUST_ADJ_WIDTH 8
#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
/* KEEP_ALIVE_CTRL Bit Fields */
#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK 0x1u
#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT 0
#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_WIDTH 1
#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT))&USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK)
#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK 0x2u
#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT 1
#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_WIDTH 1
#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT))&USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK)
#define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_MASK 0x8u
#define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_SHIFT 3
#define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_WIDTH 1
#define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_SHIFT))&USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_MASK)
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK 0x10u
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT 4
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_WIDTH 1
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT))&USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK)
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK 0x80u
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT 7
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_WIDTH 1
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x))<<USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT))&USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK)
/* KEEP_ALIVE_WKCTRL Bit Fields */
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK 0xFu
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT 0
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_WIDTH 4
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x))<<USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT))&USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK 0xF0u
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT 4
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_WIDTH 4
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT))&USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK)
/* MISCCTRL Bit Fields */
#define USB_MISCCTRL_SOFDYNTHLD_MASK 0x1u
#define USB_MISCCTRL_SOFDYNTHLD_SHIFT 0
#define USB_MISCCTRL_SOFDYNTHLD_WIDTH 1
#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_SOFDYNTHLD_SHIFT))&USB_MISCCTRL_SOFDYNTHLD_MASK)
#define USB_MISCCTRL_SOFBUSSET_MASK 0x2u
#define USB_MISCCTRL_SOFBUSSET_SHIFT 1
#define USB_MISCCTRL_SOFBUSSET_WIDTH 1
#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_SOFBUSSET_SHIFT))&USB_MISCCTRL_SOFBUSSET_MASK)
#define USB_MISCCTRL_OWNERRISODIS_MASK 0x4u
#define USB_MISCCTRL_OWNERRISODIS_SHIFT 2
#define USB_MISCCTRL_OWNERRISODIS_WIDTH 1
#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_OWNERRISODIS_SHIFT))&USB_MISCCTRL_OWNERRISODIS_MASK)
#define USB_MISCCTRL_VREDG_EN_MASK 0x8u
#define USB_MISCCTRL_VREDG_EN_SHIFT 3
#define USB_MISCCTRL_VREDG_EN_WIDTH 1
#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_VREDG_EN_SHIFT))&USB_MISCCTRL_VREDG_EN_MASK)
#define USB_MISCCTRL_VFEDG_EN_MASK 0x10u
#define USB_MISCCTRL_VFEDG_EN_SHIFT 4
#define USB_MISCCTRL_VFEDG_EN_WIDTH 1
#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_VFEDG_EN_SHIFT))&USB_MISCCTRL_VFEDG_EN_MASK)
/* CLK_RECOVER_CTRL Bit Fields */
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
/* CLK_RECOVER_IRC_EN Bit Fields */
#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH 1
#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH 1
#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
/* CLK_RECOVER_INT_EN Bit Fields */
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_WIDTH 1
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT))&USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
/* CLK_RECOVER_INT_STATUS Bit Fields */
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
/*!
* @}
*/ /* end of group USB_Register_Masks */
/* USB - Peripheral instance base addresses */
/** Peripheral USB0 base address */
#define USB0_BASE (0x40055000u)
/** Peripheral USB0 base pointer */
#define USB0 ((USB_Type *)USB0_BASE)
#define USB0_BASE_PTR (USB0)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { USB0_BASE }
/** Array initializer of USB peripheral base pointers */
#define USB_BASE_PTRS { USB0 }
/* ----------------------------------------------------------------------------
-- USB - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
* @{
*/
/* USB - Register instance definitions */
/* USB0 */
#define USB0_PERID USB_PERID_REG(USB0)
#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
#define USB0_REV USB_REV_REG(USB0)
#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
#define USB0_OTGICR USB_OTGICR_REG(USB0)
#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
#define USB0_ISTAT USB_ISTAT_REG(USB0)
#define USB0_INTEN USB_INTEN_REG(USB0)
#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
#define USB0_ERREN USB_ERREN_REG(USB0)
#define USB0_STAT USB_STAT_REG(USB0)
#define USB0_CTL USB_CTL_REG(USB0)
#define USB0_ADDR USB_ADDR_REG(USB0)
#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
#define USB0_TOKEN USB_TOKEN_REG(USB0)
#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
#define USB0_CONTROL USB_CONTROL_REG(USB0)
#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
#define USB0_KEEP_ALIVE_CTRL USB_KEEP_ALIVE_CTRL_REG(USB0)
#define USB0_KEEP_ALIVE_WKCTRL USB_KEEP_ALIVE_WKCTRL_REG(USB0)
#define USB0_MISCCTRL USB_MISCCTRL_REG(USB0)
#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
#define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
/* USB - Register array accessors */
#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
/*!
* @}
*/ /* end of group USB_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VREF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
* @{
*/
/** VREF - Register Layout Typedef */
typedef struct {
__IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
__IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
__IO uint8_t TRM1; /**< VREF Trim Register 1, offset: 0x2 */
__IO uint8_t TRM2; /**< VREF Trim Register 2, offset: 0x3 */
__IO uint8_t TRM3; /**< VREF Trim Register 3, offset: 0x4 */
__IO uint8_t TRM4; /**< VREF Trim Register 4, offset: 0x5 */
} VREF_Type, *VREF_MemMapPtr;
/* ----------------------------------------------------------------------------
-- VREF - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
* @{
*/
/* VREF - Register accessors */
#define VREF_TRM_REG(base) ((base)->TRM)
#define VREF_SC_REG(base) ((base)->SC)
#define VREF_TRM1_REG(base) ((base)->TRM1)
#define VREF_TRM2_REG(base) ((base)->TRM2)
#define VREF_TRM3_REG(base) ((base)->TRM3)
#define VREF_TRM4_REG(base) ((base)->TRM4)
/*!
* @}
*/ /* end of group VREF_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- VREF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VREF_Register_Masks VREF Register Masks
* @{
*/
/* TRM Bit Fields */
#define VREF_TRM_TRIM_MASK 0x3Fu
#define VREF_TRM_TRIM_SHIFT 0
#define VREF_TRM_TRIM_WIDTH 6
#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
#define VREF_TRM_CHOPEN_MASK 0x40u
#define VREF_TRM_CHOPEN_SHIFT 6
#define VREF_TRM_CHOPEN_WIDTH 1
#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
#define VREF_TRM_FLIP_MASK 0x80u
#define VREF_TRM_FLIP_SHIFT 7
#define VREF_TRM_FLIP_WIDTH 1
#define VREF_TRM_FLIP(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_FLIP_SHIFT))&VREF_TRM_FLIP_MASK)
/* SC Bit Fields */
#define VREF_SC_MODE_LV_MASK 0x3u
#define VREF_SC_MODE_LV_SHIFT 0
#define VREF_SC_MODE_LV_WIDTH 2
#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
#define VREF_SC_VREFST_MASK 0x4u
#define VREF_SC_VREFST_SHIFT 2
#define VREF_SC_VREFST_WIDTH 1
#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
#define VREF_SC_TMUXEN_MASK 0x8u
#define VREF_SC_TMUXEN_SHIFT 3
#define VREF_SC_TMUXEN_WIDTH 1
#define VREF_SC_TMUXEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_TMUXEN_SHIFT))&VREF_SC_TMUXEN_MASK)
#define VREF_SC_TRESEN_MASK 0x10u
#define VREF_SC_TRESEN_SHIFT 4
#define VREF_SC_TRESEN_WIDTH 1
#define VREF_SC_TRESEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_TRESEN_SHIFT))&VREF_SC_TRESEN_MASK)
#define VREF_SC_ICOMPEN_MASK 0x20u
#define VREF_SC_ICOMPEN_SHIFT 5
#define VREF_SC_ICOMPEN_WIDTH 1
#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
#define VREF_SC_REGEN_MASK 0x40u
#define VREF_SC_REGEN_SHIFT 6
#define VREF_SC_REGEN_WIDTH 1
#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
#define VREF_SC_VREFEN_MASK 0x80u
#define VREF_SC_VREFEN_SHIFT 7
#define VREF_SC_VREFEN_WIDTH 1
#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
/* TRM1 Bit Fields */
#define VREF_TRM1_BPLSB_MASK 0xFu
#define VREF_TRM1_BPLSB_SHIFT 0
#define VREF_TRM1_BPLSB_WIDTH 4
#define VREF_TRM1_BPLSB(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM1_BPLSB_SHIFT))&VREF_TRM1_BPLSB_MASK)
#define VREF_TRM1_BPMSB_MASK 0xE0u
#define VREF_TRM1_BPMSB_SHIFT 5
#define VREF_TRM1_BPMSB_WIDTH 3
#define VREF_TRM1_BPMSB(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM1_BPMSB_SHIFT))&VREF_TRM1_BPMSB_MASK)
/* TRM2 Bit Fields */
#define VREF_TRM2_COMPLSB_MASK 0x7u
#define VREF_TRM2_COMPLSB_SHIFT 0
#define VREF_TRM2_COMPLSB_WIDTH 3
#define VREF_TRM2_COMPLSB(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM2_COMPLSB_SHIFT))&VREF_TRM2_COMPLSB_MASK)
#define VREF_TRM2_COMPMSB_MASK 0xE0u
#define VREF_TRM2_COMPMSB_SHIFT 5
#define VREF_TRM2_COMPMSB_WIDTH 3
#define VREF_TRM2_COMPMSB(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM2_COMPMSB_SHIFT))&VREF_TRM2_COMPMSB_MASK)
/* TRM3 Bit Fields */
#define VREF_TRM3_CHOPOSCTRM_MASK 0xFu
#define VREF_TRM3_CHOPOSCTRM_SHIFT 0
#define VREF_TRM3_CHOPOSCTRM_WIDTH 4
#define VREF_TRM3_CHOPOSCTRM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM3_CHOPOSCTRM_SHIFT))&VREF_TRM3_CHOPOSCTRM_MASK)
/* TRM4 Bit Fields */
#define VREF_TRM4_TRIM2V1_MASK 0x3Fu
#define VREF_TRM4_TRIM2V1_SHIFT 0
#define VREF_TRM4_TRIM2V1_WIDTH 6
#define VREF_TRM4_TRIM2V1(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM4_TRIM2V1_SHIFT))&VREF_TRM4_TRIM2V1_MASK)
#define VREF_TRM4_VREF2V1_EN_MASK 0x80u
#define VREF_TRM4_VREF2V1_EN_SHIFT 7
#define VREF_TRM4_VREF2V1_EN_WIDTH 1
#define VREF_TRM4_VREF2V1_EN(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM4_VREF2V1_EN_SHIFT))&VREF_TRM4_VREF2V1_EN_MASK)
/*!
* @}
*/ /* end of group VREF_Register_Masks */
/* VREF - Peripheral instance base addresses */
/** Peripheral VREF base address */
#define VREF_BASE (0x40072000u)
/** Peripheral VREF base pointer */
#define VREF ((VREF_Type *)VREF_BASE)
#define VREF_BASE_PTR (VREF)
/** Array initializer of VREF peripheral base addresses */
#define VREF_BASE_ADDRS { VREF_BASE }
/** Array initializer of VREF peripheral base pointers */
#define VREF_BASE_PTRS { VREF }
/* ----------------------------------------------------------------------------
-- VREF - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
* @{
*/
/* VREF - Register instance definitions */
/* VREF */
#define VREF_TRM VREF_TRM_REG(VREF)
#define VREF_SC VREF_SC_REG(VREF)
#define VREF_TRM1 VREF_TRM1_REG(VREF)
#define VREF_TRM2 VREF_TRM2_REG(VREF)
#define VREF_TRM3 VREF_TRM3_REG(VREF)
#define VREF_TRM4 VREF_TRM4_REG(VREF)
/*!
* @}
*/ /* end of group VREF_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group VREF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- WDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
* @{
*/
/** WDOG - Register Layout Typedef */
typedef struct {
__IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */
__IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */
__IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */
__IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */
} WDOG_Type, *WDOG_MemMapPtr;
/* ----------------------------------------------------------------------------
-- WDOG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
* @{
*/
/* WDOG - Register accessors */
#define WDOG_CS_REG(base) ((base)->CS)
#define WDOG_CNT_REG(base) ((base)->CNT)
#define WDOG_TOVAL_REG(base) ((base)->TOVAL)
#define WDOG_WIN_REG(base) ((base)->WIN)
/*!
* @}
*/ /* end of group WDOG_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/* CS Bit Fields */
#define WDOG_CS_STOP_MASK 0x1u
#define WDOG_CS_STOP_SHIFT 0
#define WDOG_CS_STOP_WIDTH 1
#define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_STOP_SHIFT))&WDOG_CS_STOP_MASK)
#define WDOG_CS_WAIT_MASK 0x2u
#define WDOG_CS_WAIT_SHIFT 1
#define WDOG_CS_WAIT_WIDTH 1
#define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WAIT_SHIFT))&WDOG_CS_WAIT_MASK)
#define WDOG_CS_DBG_MASK 0x4u
#define WDOG_CS_DBG_SHIFT 2
#define WDOG_CS_DBG_WIDTH 1
#define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_DBG_SHIFT))&WDOG_CS_DBG_MASK)
#define WDOG_CS_TST_MASK 0x18u
#define WDOG_CS_TST_SHIFT 3
#define WDOG_CS_TST_WIDTH 2
#define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_TST_SHIFT))&WDOG_CS_TST_MASK)
#define WDOG_CS_UPDATE_MASK 0x20u
#define WDOG_CS_UPDATE_SHIFT 5
#define WDOG_CS_UPDATE_WIDTH 1
#define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_UPDATE_SHIFT))&WDOG_CS_UPDATE_MASK)
#define WDOG_CS_INT_MASK 0x40u
#define WDOG_CS_INT_SHIFT 6
#define WDOG_CS_INT_WIDTH 1
#define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_INT_SHIFT))&WDOG_CS_INT_MASK)
#define WDOG_CS_EN_MASK 0x80u
#define WDOG_CS_EN_SHIFT 7
#define WDOG_CS_EN_WIDTH 1
#define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_EN_SHIFT))&WDOG_CS_EN_MASK)
#define WDOG_CS_CLK_MASK 0x300u
#define WDOG_CS_CLK_SHIFT 8
#define WDOG_CS_CLK_WIDTH 2
#define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CLK_SHIFT))&WDOG_CS_CLK_MASK)
#define WDOG_CS_PRES_MASK 0x1000u
#define WDOG_CS_PRES_SHIFT 12
#define WDOG_CS_PRES_WIDTH 1
#define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_PRES_SHIFT))&WDOG_CS_PRES_MASK)
#define WDOG_CS_FLG_MASK 0x4000u
#define WDOG_CS_FLG_SHIFT 14
#define WDOG_CS_FLG_WIDTH 1
#define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_FLG_SHIFT))&WDOG_CS_FLG_MASK)
#define WDOG_CS_WIN_MASK 0x8000u
#define WDOG_CS_WIN_SHIFT 15
#define WDOG_CS_WIN_WIDTH 1
#define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WIN_SHIFT))&WDOG_CS_WIN_MASK)
/* CNT Bit Fields */
#define WDOG_CNT_CNTLOW_MASK 0xFFu
#define WDOG_CNT_CNTLOW_SHIFT 0
#define WDOG_CNT_CNTLOW_WIDTH 8
#define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTLOW_SHIFT))&WDOG_CNT_CNTLOW_MASK)
#define WDOG_CNT_CNTHIGH_MASK 0xFF00u
#define WDOG_CNT_CNTHIGH_SHIFT 8
#define WDOG_CNT_CNTHIGH_WIDTH 8
#define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTHIGH_SHIFT))&WDOG_CNT_CNTHIGH_MASK)
/* TOVAL Bit Fields */
#define WDOG_TOVAL_TOVALLOW_MASK 0xFFu
#define WDOG_TOVAL_TOVALLOW_SHIFT 0
#define WDOG_TOVAL_TOVALLOW_WIDTH 8
#define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALLOW_SHIFT))&WDOG_TOVAL_TOVALLOW_MASK)
#define WDOG_TOVAL_TOVALHIGH_MASK 0xFF00u
#define WDOG_TOVAL_TOVALHIGH_SHIFT 8
#define WDOG_TOVAL_TOVALHIGH_WIDTH 8
#define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALHIGH_SHIFT))&WDOG_TOVAL_TOVALHIGH_MASK)
/* WIN Bit Fields */
#define WDOG_WIN_WINLOW_MASK 0xFFu
#define WDOG_WIN_WINLOW_SHIFT 0
#define WDOG_WIN_WINLOW_WIDTH 8
#define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINLOW_SHIFT))&WDOG_WIN_WINLOW_MASK)
#define WDOG_WIN_WINHIGH_MASK 0xFF00u
#define WDOG_WIN_WINHIGH_SHIFT 8
#define WDOG_WIN_WINHIGH_WIDTH 8
#define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINHIGH_SHIFT))&WDOG_WIN_WINHIGH_MASK)
/*!
* @}
*/ /* end of group WDOG_Register_Masks */
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG0 base address */
#define WDOG0_BASE (0x40076000u)
/** Peripheral WDOG0 base pointer */
#define WDOG0 ((WDOG_Type *)WDOG0_BASE)
#define WDOG0_BASE_PTR (WDOG0)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { WDOG0_BASE }
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS { WDOG0 }
/* ----------------------------------------------------------------------------
-- WDOG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
* @{
*/
/* WDOG - Register instance definitions */
/* WDOG0 */
#define WDOG0_CS WDOG_CS_REG(WDOG0)
#define WDOG0_CNT WDOG_CNT_REG(WDOG0)
#define WDOG0_TOVAL WDOG_TOVAL_REG(WDOG0)
#define WDOG0_WIN WDOG_WIN_REG(WDOG0)
/*!
* @}
*/ /* end of group WDOG_Register_Accessor_Macros */
#define WDOG_UPDATE_KEY (<KEY>)
#define WDOG_REFRESH_KEY (<KEY>)
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma pop
#elif defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- Backward Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
* @{
*/
#define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK
#define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT
#define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x)
#define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK
#define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT
#define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x)
#define ADC_BASES ADC_BASE_PTRS
#define CMP_BASES CMP_BASE_PTRS
#define DAC_BASES DAC_BASE_PTRS
#define DMA_BASES DMA_BASE_PTRS
#define DMAMUX_BASES DMAMUX_BASE_PTRS
#define FGPIO_BASES FGPIO_BASE_PTRS
#define GPIO_BASES GPIO_BASE_PTRS
#define FTFA_BASES FTFA_BASE_PTRS
#define I2S_BASES I2S_BASE_PTRS
#define LLWU_BASES LLWU_BASE_PTRS
#define LPTMR_BASES LPTMR_BASE_PTRS
#define MCM_BASES MCM_BASE_PTRS
#define MTB_BASES MTB_BASE_PTRS
#define MTBDWT_BASES MTBDWT_BASE_PTRS
#define NV_BASES NV_BASES
#define OSC_BASES OSC_BASE_PTRS
#define LPIT_BASES LPIT_BASE_PTRS
#define PMC_BASES PMC_BASE_PTRS
#define PORT_BASES PORT_BASE_PTRS
#define RCM_BASES RCM_BASE_PTRS
#define ROM_BASES ROM_BASE_PTRS
#define RTC_BASES RTC_BASE_PTRS
#define SIM_BASES SIM_BASE_PTRS
#define SMC_BASES SMC_BASE_PTRS
#define LPI2C_BASES LPI2C_BASE_PTRS
#define LPSPI_BASES LPSPI_BASE_PTRS
#define TPM_BASES TPM_BASE_PTRS
#define TSI_BASES TSI_BASE_PTRS
#define LPUART_BASES LPUART_BASE_PTRS
#define FPTA_BASE FGPIOA_BASE
#define FPTA FGPIOA
#define PTA_BASE GPIOA_BASE
#define PTA GPIOA
#define PTB_BASE GPIOB_BASE
#define PTB GPIOB
#define PTC_BASE GPIOC_BASE
#define PTC GPIOC
#define PTD_BASE GPIOD_BASE
#define PTD GPIOD
#define PTE_BASE GPIOE_BASE
#define PTE GPIOE
#define I2C_FLT_STOPIE_MASK This_symbol_has_been_deprecated
#define I2C_FLT_STOPIE_SHIFT This_symbol_has_been_deprecated
#define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK
#define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT
#define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x)
#define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK
#define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT
#define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x)
#define LPTimer_IRQn LPTMR0_IRQn
#define LPTimer_IRQHandler LPTMR0_IRQHandler
/*!
* @}
*/ /* end of group Backward_Compatibility_Symbols */
#else /* #if !defined(MKL28Z7_H_) */
/* There is already included the same memory map. Check if it is compatible (has the same major version) */
#if (MCU_MEM_MAP_VERSION != 0x0100u)
#if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
#warning There are included two not compatible versions of memory maps. Please check possible differences.
#endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
#endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
#endif /* #if !defined(MKL28Z7_H_) */
/* MKL28Z7.h, eof. */
|
yandld/lpc_uart_server
|
kernel_driver/lpc54xxx.c
|
<reponame>yandld/lpc_uart_server<gh_stars>1-10
// SPDX-License-Identifier: GPL-2.0+
/*
* LPC USB-10 ports Serial Converters
*
* Copyright 2018 by NXP International
*
* Shamelessly based on DIGI driver
*
*
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/tty_driver.h>
#include <linux/tty_flip.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/uaccess.h>
#include <linux/usb.h>
#include <linux/wait.h>
#include <linux/sched/signal.h>
#include <linux/usb/serial.h>
#include <linux/types.h>
/* Defines */
#define DRIVER_AUTHOR "<NAME> <<EMAIL>>"
#define DRIVER_DESC "NXP usb-10 Serial Converter driver"
/* when the number of the have send data is greater than the macro below */
/* we should enquire the device whether can send data */
#define LPC_MAX_SEND_NUM 512
/* port output buffer length -- must be <= transfer buffer length - 3 */
/* so we can be sure to send the full buffer in one urb */
#define LPC_OUT_BUF_SIZE 128
/* retry timeout while sleeping */
#define LPC_RETRY_TIMEOUT (HZ/10)
/* timeout while waiting for tty output to drain in close */
/* this delay is used twice in close, so the total delay could */
/* be twice this value */
#define LPC_CLOSE_TIMEOUT (5*HZ)
/* LPC USB Defines */
/* ids */
#define LPC_VENDOR_ID 0x1FC9
#define LPC_10_ID 0xEA60
/* commands
* "INB": can be used on the in-band endpoint
* "OOB": can be used on the out-of-band endpoint
*/
#define LPC_CMD_SET_BAUD_RATE 0 /* INB, OOB */
#define LPC_CMD_SET_WORD_SIZE 1 /* INB, OOB */
#define LPC_CMD_SET_PARITY 2 /* INB, OOB */
#define LPC_CMD_SET_STOP_BITS 3 /* INB, OOB */
#define LPC_CMD_SET_INPUT_FLOW_CONTROL 4 /* INB, OOB */
#define LPC_CMD_SET_OUTPUT_FLOW_CONTROL 5 /* INB, OOB */
#define LPC_CMD_SET_DTR_SIGNAL 6 /* INB, OOB */
#define LPC_CMD_SET_RTS_SIGNAL 7 /* INB, OOB */
#define LPC_CMD_READ_INPUT_SIGNALS 8 /* OOB */
#define LPC_CMD_IFLUSH_FIFO 9 /* OOB */
#define LPC_CMD_RECEIVE_ENABLE 10 /* INB, OOB */
#define LPC_CMD_BREAK_CONTROL 11 /* INB, OOB */
#define LPC_CMD_LOCAL_LOOPBACK 12 /* INB, OOB */
#define LPC_CMD_TRANSMIT_IDLE 13 /* INB, OOB */
#define LPC_CMD_READ_UART_REGISTER 14 /* OOB */
#define LPC_CMD_WRITE_UART_REGISTER 15 /* INB, OOB */
#define LPC_CMD_AND_UART_REGISTER 16 /* INB, OOB */
#define LPC_CMD_OR_UART_REGISTER 17 /* INB, OOB */
#define LPC_CMD_SEND_DATA 18 /* INB */
#define LPC_CMD_RECEIVE_DATA 19 /* INB */
#define LPC_CMD_RECEIVE_DISABLE 20 /* INB */
#define LPC_CMD_GET_PORT_TYPE 21 /* OOB */
#define LPC_CMD_TRANSMIT_FULL 22 /* OOB */
/* baud rates */
#define LPC_BAUD_50 0
#define LPC_BAUD_75 1
#define LPC_BAUD_110 2
#define LPC_BAUD_150 3
#define LPC_BAUD_200 4
#define LPC_BAUD_300 5
#define LPC_BAUD_600 6
#define LPC_BAUD_1200 7
#define LPC_BAUD_1800 8
#define LPC_BAUD_2400 9
#define LPC_BAUD_4800 10
#define LPC_BAUD_7200 11
#define LPC_BAUD_9600 12
#define LPC_BAUD_14400 13
#define LPC_BAUD_19200 14
#define LPC_BAUD_28800 15
#define LPC_BAUD_38400 16
#define LPC_BAUD_57600 17
#define LPC_BAUD_76800 18
#define LPC_BAUD_115200 19
#define LPC_BAUD_153600 20
#define LPC_BAUD_230400 21
#define LPC_BAUD_460800 22
/* arguments */
#define LPC_WORD_SIZE_5 0
#define LPC_WORD_SIZE_6 1
#define LPC_WORD_SIZE_7 2
#define LPC_WORD_SIZE_8 3
#define LPC_PARITY_NONE 0
#define LPC_PARITY_ODD 1
#define LPC_PARITY_EVEN 2
#define LPC_PARITY_MARK 3
#define LPC_PARITY_SPACE 4
#define LPC_STOP_BITS_1 0
#define LPC_STOP_BITS_2 1
#define LPC_INPUT_FLOW_CONTROL_XON_XOFF 1
#define LPC_INPUT_FLOW_CONTROL_RTS 2
#define LPC_INPUT_FLOW_CONTROL_DTR 4
#define LPC_OUTPUT_FLOW_CONTROL_XON_XOFF 1
#define LPC_OUTPUT_FLOW_CONTROL_CTS 2
#define LPC_OUTPUT_FLOW_CONTROL_DSR 4
#define LPC_DTR_INACTIVE 0
#define LPC_DTR_ACTIVE 1
#define LPC_DTR_INPUT_FLOW_CONTROL 2
#define LPC_RTS_INACTIVE 0
#define LPC_RTS_ACTIVE 1
#define LPC_RTS_INPUT_FLOW_CONTROL 2
#define LPC_RTS_TOGGLE 3
#define LPC_FLUSH_TX 1
#define LPC_FLUSH_RX 2
#define LPC_RESUME_TX 4 /* clears xoff condition */
#define LPC_TRANSMIT_NOT_IDLE 0
#define LPC_TRANSMIT_IDLE 1
#define LPC_DISABLE 0
#define LPC_ENABLE 1
#define LPC_DEASSERT 0
#define LPC_ASSERT 1
/* in band status codes */
#define LPC_OVERRUN_ERROR 4
#define LPC_PARITY_ERROR 8
#define LPC_FRAMING_ERROR 16
#define LPC_BREAK_ERROR 32
/* out of band status */
#define LPC_NO_ERROR 0
#define LPC_BAD_FIRST_PARAMETER 1
#define LPC_BAD_SECOND_PARAMETER 2
#define LPC_INVALID_LINE 3
#define LPC_INVALID_OPCODE 4
/* input signals */
#define LPC_READ_INPUT_SIGNALS_SLOT 1
#define LPC_READ_INPUT_SIGNALS_ERR 2
#define LPC_READ_INPUT_SIGNALS_BUSY 4
#define LPC_READ_INPUT_SIGNALS_PE 8
#define LPC_READ_INPUT_SIGNALS_CTS 16
#define LPC_READ_INPUT_SIGNALS_DSR 32
#define LPC_READ_INPUT_SIGNALS_RI 64
#define LPC_READ_INPUT_SIGNALS_DCD 128
/* usb serial port configuration information */
#define NUM_PORTS 10
#define NUM_BULK_IN 11
#define NUM_BULK_OUT 11
#define REAL_NUM_BULK_IN 2
#define REAL_NUM_BULK_OUT 2
/* Structures */
struct lpc_serial {
spinlock_t lpcs_serial_lock;
struct usb_serial_port *lpcs_oob_port; /* out-of-band port */
int lpcs_oob_port_num; /* index of out-of-band port */
int lpcs_device_started;
};
struct lpc_port {
spinlock_t lpcp_port_lock;
bool is_loopback;
int lpcp_port_num;
int lpcp_out_buf_len;
unsigned char lpcp_out_buf[LPC_OUT_BUF_SIZE];
int lpcp_write_urb_in_use;
unsigned int lpcp_modem_signals;
int lpcp_transmit_idle;
wait_queue_head_t lpcp_transmit_idle_wait;
wait_queue_head_t lpcp_transmit_is_full;
int lpcp_threshold_num;
unsigned long long lpcp_download_num;
unsigned long long lpcp_upload_num;
int lpcp_throttled;
int lpcp_throttle_restart;
wait_queue_head_t lpcp_flush_wait;
wait_queue_head_t lpcp_close_wait; /* wait queue for close */
struct work_struct lpcp_wakeup_work;
struct usb_serial_port *lpcp_port;
};
/* Local Function Declarations */
static void lpc_wakeup_write_lock(struct work_struct *work);
static int lpc_write_oob_command(struct usb_serial_port *port,unsigned char *buf, int count, int interruptible);
static int lpc_write_inb_command(struct usb_serial_port *port,unsigned char *buf, int count, unsigned long timeout);
static int lpc_set_modem_signals(struct usb_serial_port *port,unsigned int modem_signals, int interruptible);
static int lpc_transmit_idle(struct usb_serial_port *port,unsigned long timeout);
static void lpc_rx_throttle(struct tty_struct *tty);
static void lpc_rx_unthrottle(struct tty_struct *tty);
static void lpc_set_termios(struct tty_struct *tty,struct usb_serial_port *port, struct ktermios *old_termios);
static void lpc_break_ctl(struct tty_struct *tty, int break_state);
static int lpc_tiocmget(struct tty_struct *tty);
static int lpc_tiocmset(struct tty_struct *tty, unsigned int set,unsigned int clear);
static int lpc_write(struct tty_struct *tty, struct usb_serial_port *port,const unsigned char *buf, int count);
static void lpc_write_bulk_callback(struct urb *urb);
static int lpc_write_room(struct tty_struct *tty);
static int lpc_chars_in_buffer(struct tty_struct *tty);
static int lpc_open(struct tty_struct *tty, struct usb_serial_port *port);
static void lpc_close(struct usb_serial_port *port);
static void lpc_dtr_rts(struct usb_serial_port *port, int on);
static int lpc_startup_device(struct usb_serial *serial);
static int lpc_startup(struct usb_serial *serial);
static void lpc_disconnect(struct usb_serial *serial);
static void lpc_release(struct usb_serial *serial);
static int lpc_port_probe(struct usb_serial_port *port);
static int lpc_port_remove(struct usb_serial_port *port);
static void lpc_read_bulk_callback(struct urb *urb);
static int lpc_read_inb_callback(struct urb *urb);
static int lpc_read_oob_callback(struct urb *urb);
static int lpc_probe(struct usb_serial *serial,const struct usb_device_id *id);
static int lpc_calc_num_ports(struct usb_serial *serial,struct usb_serial_endpoints *epds);
static const struct usb_device_id id_table_10[] = {
{ USB_DEVICE(LPC_VENDOR_ID, LPC_10_ID) },
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, id_table_10);
/* device info needed for the lpc serial converter */
static struct usb_serial_driver lpc_10_port_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "LPC54XXX",
},
.description = "LPC54XXX 10 port USB adapter",
.id_table = id_table_10,
.num_ports = NUM_PORTS,
.num_bulk_in = NUM_BULK_IN,
.num_bulk_out = NUM_BULK_OUT,
.bulk_in_size = 256,
.bulk_out_size = 256,
.probe = lpc_probe,
.calc_num_ports = lpc_calc_num_ports,
.open = lpc_open,
.close = lpc_close,
.dtr_rts = lpc_dtr_rts,
.write = lpc_write,
.write_room = lpc_write_room,
.write_bulk_callback = lpc_write_bulk_callback,
.read_bulk_callback = lpc_read_bulk_callback,
.chars_in_buffer = lpc_chars_in_buffer,
.throttle = lpc_rx_throttle,
.unthrottle = lpc_rx_unthrottle,
.set_termios = lpc_set_termios,
.break_ctl = lpc_break_ctl,
.tiocmget = lpc_tiocmget,
.tiocmset = lpc_tiocmset,
.attach = lpc_startup,
.disconnect = lpc_disconnect,
.release = lpc_release,
.port_probe = lpc_port_probe,
.port_remove = lpc_port_remove,
};
static struct usb_serial_driver * const serial_drivers[] = {
&lpc_10_port_driver, NULL
};
/* Functions */
static ssize_t loopback_show(struct device *dev, struct device_attribute *attr, char *buf)
{
bool val;
unsigned long flags = 0;
struct usb_serial_port *port = to_usb_serial_port(dev);
struct lpc_port *priv = usb_get_serial_port_data(port);
spin_lock_irqsave(&priv->lpcp_port_lock,flags);
val = priv->is_loopback;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return sprintf(buf, "%u\n", val);
}
static ssize_t loopback_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
{
bool val;
int ret;
int index = 0;
unsigned char oob_command[4];
unsigned long flags = 0;
struct usb_serial_port *port = to_usb_serial_port(dev);
struct lpc_port *priv = usb_get_serial_port_data(port);
index = port->port_number;
ret = strtobool(buf, &val);
if (ret < 0)
return ret;
spin_lock_irqsave(&priv->lpcp_port_lock,flags);
priv->is_loopback = val;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
dev_warn(&port->dev, "-----loopback is = %d\n", val);
/* decide the current port whether in loopback mode */
oob_command[0] = LPC_CMD_LOCAL_LOOPBACK;
oob_command[1] = index;
oob_command[2] = val;
oob_command[3] = 0;
ret = lpc_write_oob_command(port, oob_command, 4, 1);
if(ret)
{
dev_warn(&port->dev, "lpc_write: write oob failed, ret=%d\n", ret);
return ret;
}
return count;
}
static DEVICE_ATTR_RW(loopback);
static ssize_t port_number_show(struct device *dev,struct device_attribute *attr, char *buf)
{
struct usb_serial_port *port = to_usb_serial_port(dev);
return sprintf(buf, "%u\n", port->port_number);
}
static DEVICE_ATTR_RO(port_number);
static ssize_t send_bytes_show(struct device *dev,struct device_attribute *attr, char *buf)
{
unsigned long long send_num = 0;
unsigned long flags = 0;
struct usb_serial_port *port = to_usb_serial_port(dev);
struct lpc_port *priv = usb_get_serial_port_data(port);
spin_lock_irqsave(&priv->lpcp_port_lock,flags);
send_num = priv->lpcp_download_num;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return sprintf(buf, "%llu\n", send_num);
}
static DEVICE_ATTR_RO(send_bytes);
static ssize_t recv_bytes_show(struct device *dev,struct device_attribute *attr, char *buf)
{
unsigned long long recv_num = 0;
unsigned long flags = 0;
struct usb_serial_port *port = to_usb_serial_port(dev);
struct lpc_port *priv = usb_get_serial_port_data(port);
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
recv_num = priv->lpcp_upload_num;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return sprintf(buf, "%llu\n", recv_num);
}
static DEVICE_ATTR_RO(recv_bytes);
static struct attribute *usb_serial_port_attrs[] = {
&dev_attr_port_number.attr,
&dev_attr_send_bytes.attr,
&dev_attr_recv_bytes.attr,
&dev_attr_loopback.attr,
NULL
};
ATTRIBUTE_GROUPS(usb_serial_port);
static void set_endpoints(struct usb_serial *serial,struct usb_serial_endpoints *epds)
{
struct usb_endpoint_descriptor *epd_bulk_in_data = epds->bulk_in[0];
struct usb_endpoint_descriptor *epd_bulk_in_oob = epds->bulk_in[1];
struct usb_endpoint_descriptor *epd_bulk_out_data = epds->bulk_out[0];
struct usb_endpoint_descriptor *epd_bulk_out_oob = epds->bulk_out[1];
unsigned int i;
for (i = 1; i < epds->num_bulk_in; ++i) {
if(i != (epds->num_bulk_in - 1))
{
epds->bulk_in[i] = epd_bulk_in_data;
epds->bulk_out[i] = epd_bulk_out_data;
}
else
{
epds->bulk_in[i] = epd_bulk_in_oob;
epds->bulk_out[i] = epd_bulk_out_oob;
}
}
}
static int lpc_probe(struct usb_serial *serial,const struct usb_device_id *id)
{
struct usb_serial_driver *driver = serial->type;
driver->num_bulk_in = REAL_NUM_BULK_IN;
driver->num_bulk_out = REAL_NUM_BULK_OUT;
return 0;
}
static int lpc_calc_num_ports(struct usb_serial *serial,struct usb_serial_endpoints *epds)
{
struct usb_serial_driver *driver = serial->type;
int num_ports;
driver->num_bulk_in = NUM_BULK_IN;
driver->num_bulk_out = NUM_BULK_OUT;
epds->num_bulk_in = driver->num_bulk_in;
epds->num_bulk_out = driver->num_bulk_out;
num_ports = driver->num_ports;
set_endpoints(serial,epds);
return num_ports;
}
/*
* Cond Wait Interruptible Timeout Irqrestore
*
* Do spin_unlock_irqrestore and interruptible_sleep_on_timeout
* so that wake ups are not lost if they occur between the unlock
* and the sleep. In other words, spin_unlock_irqrestore and
* interruptible_sleep_on_timeout are "atomic" with respect to
* wake ups. This is used to implement condition variables.
*
* interruptible_sleep_on_timeout is deprecated and has been replaced
* with the equivalent code.
*/
static long cond_wait_interruptible_timeout_irqrestore(
wait_queue_head_t *q, long timeout,
spinlock_t *lock, unsigned long flags)
__releases(lock)
{
DEFINE_WAIT(wait);
prepare_to_wait(q, &wait, TASK_INTERRUPTIBLE);
spin_unlock_irqrestore(lock, flags);
timeout = schedule_timeout(timeout);
finish_wait(q, &wait);
return timeout;
}
/*
* lpc Wakeup Write
*
* Wake up port, line discipline, and tty processes sleeping
* on writes.
*/
static void lpc_wakeup_write_lock(struct work_struct *work)
{
struct lpc_port *priv =
container_of(work, struct lpc_port, lpcp_wakeup_work);
struct usb_serial_port *port = priv->lpcp_port;
unsigned long flags;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
tty_port_tty_wakeup(&port->port);
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
}
/*
* lpc Write OOB Command
*
* Write commands on the out of band port. Commands are 4
* bytes each, multiple commands can be sent at once, and
* no command will be split across USB packets. Returns 0
* if successful, -EINTR if interrupted while sleeping and
* the interruptible flag is true, or a negative error
* returned by usb_submit_urb.
*/
static int lpc_write_oob_command(struct usb_serial_port *port,
unsigned char *buf, int count, int interruptible)
{
int ret = 0;
int len;
struct usb_serial_port *oob_port = (struct usb_serial_port *)((struct lpc_serial *)(usb_get_serial_data(port->serial)))->lpcs_oob_port;
struct lpc_port *oob_priv = usb_get_serial_port_data(oob_port);
unsigned long flags = 0;
dev_dbg(&port->dev,
"lpc_write_oob_command: TOP: port=%d, count=%d\n",
oob_priv->lpcp_port_num, count);
spin_lock_irqsave(&oob_priv->lpcp_port_lock, flags);
while (count > 0) {
while (oob_priv->lpcp_write_urb_in_use) {
cond_wait_interruptible_timeout_irqrestore(
&oob_port->write_wait, LPC_RETRY_TIMEOUT,
&oob_priv->lpcp_port_lock, flags);
if (interruptible && signal_pending(current))
return -EINTR;
spin_lock_irqsave(&oob_priv->lpcp_port_lock, flags);
}
/* len must be a multiple of 4, so commands are not split */
len = min(count, oob_port->bulk_out_size);
if (len > 4)
len &= ~3;
memcpy(oob_port->write_urb->transfer_buffer, buf, len);
oob_port->write_urb->transfer_buffer_length = len;
ret = usb_submit_urb(oob_port->write_urb, GFP_ATOMIC);
if (ret == 0) {
oob_priv->lpcp_write_urb_in_use = 1;
count -= len;
buf += len;
}
}
spin_unlock_irqrestore(&oob_priv->lpcp_port_lock, flags);
if (ret)
dev_err(&port->dev, "%s: usb_submit_urb failed, ret=%d\n",
__func__, ret);
return ret;
}
/*
* lpc Write In Band Command
*
* Write commands on the given port. Commands are 4
* bytes each, multiple commands can be sent at once, and
* no command will be split across USB packets. If timeout
* is non-zero, write in band command will return after
* waiting unsuccessfully for the URB status to clear for
* timeout ticks. Returns 0 if successful, or a negative
* error returned by lpc_write.
*/
static int lpc_write_inb_command(struct usb_serial_port *port,
unsigned char *buf, int count, unsigned long timeout)
{
int ret = 0;
int len;
int index = port->port_number;
struct lpc_port *priv = usb_get_serial_port_data(port);
unsigned char *data = port->write_urb->transfer_buffer;
unsigned long flags = 0;
dev_dbg(&port->dev, "lpc_write_inb_command: TOP: port=%d, count=%d\n",
priv->lpcp_port_num, count);
if (timeout)
timeout += jiffies;
else
timeout = ULONG_MAX;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
while (count > 0 && ret == 0) {
while (priv->lpcp_write_urb_in_use &&
time_before(jiffies, timeout)) {
cond_wait_interruptible_timeout_irqrestore(
&port->write_wait, LPC_RETRY_TIMEOUT,
&priv->lpcp_port_lock, flags);
if (signal_pending(current))
return -EINTR;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
}
/* len must be a multiple of 4 and small enough to */
/* guarantee the write will send buffered data first, */
/* so commands are in order with data and not split */
len = min(count, port->bulk_out_size-3-priv->lpcp_out_buf_len);
if (len > 4)
len &= ~3;
/* write any buffered data first */
if (priv->lpcp_out_buf_len > 0) {
data[0] = LPC_CMD_SEND_DATA;
data[1] = index;
data[2] = priv->lpcp_out_buf_len;
memcpy(data + 3, priv->lpcp_out_buf,
priv->lpcp_out_buf_len);
memcpy(data + 3 + priv->lpcp_out_buf_len, buf, len);
port->write_urb->transfer_buffer_length
= priv->lpcp_out_buf_len + 3 + len;
} else {
memcpy(data, buf, len);
port->write_urb->transfer_buffer_length = len;
}
ret = usb_submit_urb(port->write_urb, GFP_ATOMIC);
if (ret == 0) {
priv->lpcp_write_urb_in_use = 1;
priv->lpcp_out_buf_len = 0;
count -= len;
buf += len;
}
}
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
if (ret)
dev_err(&port->dev,
"%s: usb_submit_urb failed, ret=%d, port=%d\n",
__func__, ret, priv->lpcp_port_num);
return ret;
}
/*
* lpc Set Modem Signals
*
* Sets or clears DTR and RTS on the port, according to the
* modem_signals argument. Use TIOCM_DTR and TIOCM_RTS flags
* for the modem_signals argument. Returns 0 if successful,
* -EINTR if interrupted while sleeping, or a non-zero error
* returned by usb_submit_urb.
*/
static int lpc_set_modem_signals(struct usb_serial_port *port,
unsigned int modem_signals, int interruptible)
{
int ret;
struct lpc_port *port_priv = usb_get_serial_port_data(port);
struct usb_serial_port *oob_port = (struct usb_serial_port *) ((struct lpc_serial *)(usb_get_serial_data(port->serial)))->lpcs_oob_port;
struct lpc_port *oob_priv = usb_get_serial_port_data(oob_port);
unsigned char *data = oob_port->write_urb->transfer_buffer;
unsigned long flags = 0;
dev_dbg(&port->dev,
"lpc_set_modem_signals: TOP: port=%d, modem_signals=0x%x\n",
port_priv->lpcp_port_num, modem_signals);
spin_lock_irqsave(&oob_priv->lpcp_port_lock, flags);
spin_lock(&port_priv->lpcp_port_lock);
while (oob_priv->lpcp_write_urb_in_use) {
spin_unlock(&port_priv->lpcp_port_lock);
cond_wait_interruptible_timeout_irqrestore(
&oob_port->write_wait, LPC_RETRY_TIMEOUT,
&oob_priv->lpcp_port_lock, flags);
if (interruptible && signal_pending(current))
return -EINTR;
spin_lock_irqsave(&oob_priv->lpcp_port_lock, flags);
spin_lock(&port_priv->lpcp_port_lock);
}
data[0] = LPC_CMD_SET_DTR_SIGNAL;
data[1] = port_priv->lpcp_port_num;
data[2] = (modem_signals & TIOCM_DTR) ?
LPC_DTR_ACTIVE : LPC_DTR_INACTIVE;
data[3] = 0;
data[4] = LPC_CMD_SET_RTS_SIGNAL;
data[5] = port_priv->lpcp_port_num;
data[6] = (modem_signals & TIOCM_RTS) ?
LPC_RTS_ACTIVE : LPC_RTS_INACTIVE;
data[7] = 0;
oob_port->write_urb->transfer_buffer_length = 8;
ret = usb_submit_urb(oob_port->write_urb, GFP_ATOMIC);
if (ret == 0) {
oob_priv->lpcp_write_urb_in_use = 1;
port_priv->lpcp_modem_signals =
(port_priv->lpcp_modem_signals&~(TIOCM_DTR|TIOCM_RTS))
| (modem_signals&(TIOCM_DTR|TIOCM_RTS));
}
spin_unlock(&port_priv->lpcp_port_lock);
spin_unlock_irqrestore(&oob_priv->lpcp_port_lock, flags);
if (ret)
dev_err(&port->dev, "%s: usb_submit_urb failed, ret=%d\n",
__func__, ret);
return ret;
}
/*
* lpc Transmit Idle
*
* lpc transmit idle waits, up to timeout ticks, for the transmitter
* to go idle. It returns 0 if successful or a negative error.
*
* There are race conditions here if more than one process is calling
* lpc_transmit_idle on the same port at the same time. However, this
* is only called from close, and only one process can be in close on a
* port at a time, so its ok.
*/
static int lpc_transmit_idle(struct usb_serial_port *port,
unsigned long timeout)
{
int ret;
unsigned char buf[2];
struct lpc_port *priv = usb_get_serial_port_data(port);
unsigned long flags = 0;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
priv->lpcp_transmit_idle = 0;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
buf[0] = LPC_CMD_TRANSMIT_IDLE;
buf[1] = 0;
timeout += jiffies;
ret = lpc_write_inb_command(port, buf, 2, timeout - jiffies);
if (ret != 0)
return ret;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
while (time_before(jiffies, timeout) && !priv->lpcp_transmit_idle) {
cond_wait_interruptible_timeout_irqrestore(
&priv->lpcp_transmit_idle_wait, LPC_RETRY_TIMEOUT,
&priv->lpcp_port_lock, flags);
if (signal_pending(current))
return -EINTR;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
}
priv->lpcp_transmit_idle = 0;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return 0;
}
static void lpc_rx_throttle(struct tty_struct *tty)
{
unsigned long flags;
struct usb_serial_port *port = tty->driver_data;
struct lpc_port *priv = usb_get_serial_port_data(port);
/* stop receiving characters by not resubmitting the read urb */
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
priv->lpcp_throttled = 1;
priv->lpcp_throttle_restart = 0;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
}
static void lpc_rx_unthrottle(struct tty_struct *tty)
{
int ret = 0;
unsigned long flags;
struct usb_serial_port *port = tty->driver_data;
struct lpc_port *priv = usb_get_serial_port_data(port);
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
/* restart read chain */
if (priv->lpcp_throttle_restart){
ret = usb_submit_urb(port->read_urb, GFP_ATOMIC);
}
/* turn throttle off */
priv->lpcp_throttled = 0;
priv->lpcp_throttle_restart = 0;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
if (ret)
dev_err(&port->dev,
"%s: usb_submit_urb failed, ret=%d, port=%d\n",
__func__, ret, priv->lpcp_port_num);
}
static void lpc_set_termios(struct tty_struct *tty,
struct usb_serial_port *port, struct ktermios *old_termios)
{
struct lpc_port *priv = usb_get_serial_port_data(port);
struct device *dev = &port->dev;
unsigned int iflag = tty->termios.c_iflag;
unsigned int cflag = tty->termios.c_cflag;
unsigned int old_iflag = old_termios->c_iflag;
unsigned int old_cflag = old_termios->c_cflag;
unsigned char buf[32];
unsigned int modem_signals;
int arg, ret;
int i = 0;
speed_t baud;
dev_dbg(dev,
"lpc_set_termios: TOP: port=%d, iflag=0x%x, old_iflag=0x%x, cflag=0x%x, old_cflag=0x%x\n",
priv->lpcp_port_num, iflag, old_iflag, cflag, old_cflag);
/* set baud rate */
baud = tty_get_baud_rate(tty);
if (baud != tty_termios_baud_rate(old_termios)) {
arg = -1;
/* reassert DTR and (maybe) RTS on transition from B0 */
if ((old_cflag & CBAUD) == B0) {
/* don't set RTS if using hardware flow control */
/* and throttling input */
modem_signals = TIOCM_DTR;
if (!C_CRTSCTS(tty) || !tty_throttled(tty))
modem_signals |= TIOCM_RTS;
lpc_set_modem_signals(port, modem_signals, 1);
}
switch (baud) {
/* drop DTR and RTS on transition to B0 */
case 0: lpc_set_modem_signals(port, 0, 1); break;
case 50: arg = LPC_BAUD_50; break;
case 75: arg = LPC_BAUD_75; break;
case 110: arg = LPC_BAUD_110; break;
case 150: arg = LPC_BAUD_150; break;
case 200: arg = LPC_BAUD_200; break;
case 300: arg = LPC_BAUD_300; break;
case 600: arg = LPC_BAUD_600; break;
case 1200: arg = LPC_BAUD_1200; break;
case 1800: arg = LPC_BAUD_1800; break;
case 2400: arg = LPC_BAUD_2400; break;
case 4800: arg = LPC_BAUD_4800; break;
case 9600: arg = LPC_BAUD_9600; break;
case 19200: arg = LPC_BAUD_19200; break;
case 38400: arg = LPC_BAUD_38400; break;
case 57600: arg = LPC_BAUD_57600; break;
case 115200: arg = LPC_BAUD_115200; break;
case 230400: arg = LPC_BAUD_230400; break;
case 460800: arg = LPC_BAUD_460800; break;
default:
arg = LPC_BAUD_9600;
baud = 9600;
break;
}
if (arg != -1) {
buf[i++] = LPC_CMD_SET_BAUD_RATE;
buf[i++] = priv->lpcp_port_num;
buf[i++] = arg;
buf[i++] = 0;
}
}
/* set parity */
tty->termios.c_cflag &= ~CMSPAR;
if ((cflag&(PARENB|PARODD)) != (old_cflag&(PARENB|PARODD))) {
if (cflag&PARENB) {
if (cflag&PARODD)
arg = LPC_PARITY_ODD;
else
arg = LPC_PARITY_EVEN;
} else {
arg = LPC_PARITY_NONE;
}
buf[i++] = LPC_CMD_SET_PARITY;
buf[i++] = priv->lpcp_port_num;
buf[i++] = arg;
buf[i++] = 0;
}
/* set word size */
if ((cflag&CSIZE) != (old_cflag&CSIZE)) {
arg = -1;
switch (cflag&CSIZE) {
case CS5: arg = LPC_WORD_SIZE_5; break;
case CS6: arg = LPC_WORD_SIZE_6; break;
case CS7: arg = LPC_WORD_SIZE_7; break;
case CS8: arg = LPC_WORD_SIZE_8; break;
default:
dev_dbg(dev,
"lpc_set_termios: can't handle word size %d\n",
(cflag&CSIZE));
break;
}
if (arg != -1) {
buf[i++] = LPC_CMD_SET_WORD_SIZE;
buf[i++] = priv->lpcp_port_num;
buf[i++] = arg;
buf[i++] = 0;
}
}
/* set stop bits */
if ((cflag&CSTOPB) != (old_cflag&CSTOPB)) {
if ((cflag&CSTOPB))
arg = LPC_STOP_BITS_2;
else
arg = LPC_STOP_BITS_1;
buf[i++] = LPC_CMD_SET_STOP_BITS;
buf[i++] = priv->lpcp_port_num;
buf[i++] = arg;
buf[i++] = 0;
}
/* set input flow control */
if ((iflag&IXOFF) != (old_iflag&IXOFF)
|| (cflag&CRTSCTS) != (old_cflag&CRTSCTS)) {
arg = 0;
if (iflag&IXOFF)
arg |= LPC_INPUT_FLOW_CONTROL_XON_XOFF;
else
arg &= ~LPC_INPUT_FLOW_CONTROL_XON_XOFF;
if (cflag&CRTSCTS) {
arg |= LPC_INPUT_FLOW_CONTROL_RTS;
/* On USB-4 it is necessary to assert RTS prior */
/* to selecting RTS input flow control. */
buf[i++] = LPC_CMD_SET_RTS_SIGNAL;
buf[i++] = priv->lpcp_port_num;
buf[i++] = LPC_RTS_ACTIVE;
buf[i++] = 0;
} else {
arg &= ~LPC_INPUT_FLOW_CONTROL_RTS;
}
buf[i++] = LPC_CMD_SET_INPUT_FLOW_CONTROL;
buf[i++] = priv->lpcp_port_num;
buf[i++] = arg;
buf[i++] = 0;
}
/* set output flow control */
if ((iflag & IXON) != (old_iflag & IXON)
|| (cflag & CRTSCTS) != (old_cflag & CRTSCTS)) {
arg = 0;
if (iflag & IXON)
arg |= LPC_OUTPUT_FLOW_CONTROL_XON_XOFF;
else
arg &= ~LPC_OUTPUT_FLOW_CONTROL_XON_XOFF;
if (cflag & CRTSCTS) {
arg |= LPC_OUTPUT_FLOW_CONTROL_CTS;
} else {
arg &= ~LPC_OUTPUT_FLOW_CONTROL_CTS;
}
buf[i++] = LPC_CMD_SET_OUTPUT_FLOW_CONTROL;
buf[i++] = priv->lpcp_port_num;
buf[i++] = arg;
buf[i++] = 0;
}
/* set receive enable/disable */
if ((cflag & CREAD) != (old_cflag & CREAD)) {
if (cflag & CREAD)
arg = LPC_ENABLE;
else
arg = LPC_DISABLE;
buf[i++] = LPC_CMD_RECEIVE_ENABLE;
buf[i++] = priv->lpcp_port_num;
buf[i++] = arg;
buf[i++] = 0;
}
ret = lpc_write_oob_command(port, buf, i, 1);
if (ret != 0)
dev_dbg(dev, "lpc_set_termios: write oob failed, ret=%d\n", ret);
tty_encode_baud_rate(tty, baud, baud);
}
static void lpc_break_ctl(struct tty_struct *tty, int break_state)
{
struct usb_serial_port *port = tty->driver_data;
unsigned char buf[4];
buf[0] = LPC_CMD_BREAK_CONTROL;
buf[1] = 2; /* length */
buf[2] = break_state ? 1 : 0;
buf[3] = 0; /* pad */
lpc_write_inb_command(port, buf, 4, 0);
}
static int lpc_tiocmget(struct tty_struct *tty)
{
struct usb_serial_port *port = tty->driver_data;
struct lpc_port *priv = usb_get_serial_port_data(port);
unsigned int val;
unsigned long flags;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
val = priv->lpcp_modem_signals;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return val;
}
static int lpc_tiocmset(struct tty_struct *tty,
unsigned int set, unsigned int clear)
{
struct usb_serial_port *port = tty->driver_data;
struct lpc_port *priv = usb_get_serial_port_data(port);
unsigned int val;
unsigned long flags;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
val = (priv->lpcp_modem_signals & ~clear) | set;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return lpc_set_modem_signals(port, val, 1);
}
static int lpc_write(struct tty_struct *tty, struct usb_serial_port *port,
const unsigned char *buf, int count)
{
int ret, data_len, new_len;
int index = port->port_number;
struct lpc_port *priv = usb_get_serial_port_data(port);
unsigned char *data = port->write_urb->transfer_buffer;
unsigned long flags = 0;
unsigned char oob_command[4];
dev_dbg(&port->dev,
"lpc_write: TOP: port=%d, count=%d, in_interrupt=%ld\n",
priv->lpcp_port_num, count, in_interrupt());
/* copy user data (which can sleep) before getting spin lock */
count = min(count, port->bulk_out_size-3);
count = min(253, count);
/* be sure only one write proceeds at a time */
/* there are races on the port private buffer */
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
/* wait for urb status clear to submit another urb */
if (priv->lpcp_write_urb_in_use) {
/* buffer data if count is 1 (probably put_char) if possible */
if (count == 1 && priv->lpcp_out_buf_len < LPC_OUT_BUF_SIZE) {
priv->lpcp_out_buf[priv->lpcp_out_buf_len++] = *buf;
new_len = 1;
} else {
new_len = 0;
}
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return new_len;
}
/* be sure current port can receive data */
if(priv->lpcp_threshold_num > LPC_MAX_SEND_NUM){
oob_command[0] = LPC_CMD_TRANSMIT_FULL;
oob_command[1] = index;
oob_command[2] = 0;
oob_command[3] = 0;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
ret = lpc_write_oob_command(port, oob_command, 4, 1);
if(ret)
{
dev_warn(&port->dev, "lpc_write: write oob failed, ret=%d\n", ret);
return ret;
}
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
cond_wait_interruptible_timeout_irqrestore(&priv->lpcp_transmit_is_full,
LPC_RETRY_TIMEOUT,&priv->lpcp_port_lock, flags);
if (signal_pending(current))
return -EINTR;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
priv->lpcp_threshold_num = 0;
}
/* allow space for any buffered data and for new data, up to */
/* transfer buffer size - 3 (for command, channel, length bytes) */
new_len = min(count, port->bulk_out_size-3-priv->lpcp_out_buf_len);
data_len = new_len + priv->lpcp_out_buf_len;
priv->lpcp_threshold_num += data_len;
priv->lpcp_download_num += data_len;
if (data_len == 0) {
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return 0;
}
port->write_urb->transfer_buffer_length = data_len+3;
*data++ = LPC_CMD_SEND_DATA;
*data++ = (unsigned char)index;
*data++ = data_len;
/* copy in buffered data first */
memcpy(data, priv->lpcp_out_buf, priv->lpcp_out_buf_len);
data += priv->lpcp_out_buf_len;
/* copy in new data */
memcpy(data, buf, new_len);
ret = usb_submit_urb(port->write_urb, GFP_ATOMIC);
if (ret == 0) {
priv->lpcp_write_urb_in_use = 1;
ret = new_len;
priv->lpcp_out_buf_len = 0;
}
/* return length of new data written, or error */
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
if (ret < 0)
dev_err_console(port,
"%s: usb_submit_urb failed, ret=%d, port=%d\n",
__func__, ret, priv->lpcp_port_num);
dev_dbg(&port->dev, "lpc_write: returning %d\n", ret);
return ret;
}
static void lpc_write_bulk_callback(struct urb *urb)
{
struct usb_serial_port *port = urb->context;
int index = port->port_number ;
struct usb_serial *serial;
struct lpc_port *priv;
struct lpc_serial *serial_priv;
unsigned long flags;
int ret = 0;
int status = urb->status;
/* port and serial sanity check */
if (port == NULL || (priv = usb_get_serial_port_data(port)) == NULL) {
pr_err("%s: port or port->private is NULL, status=%d\n",
__func__, status);
return;
}
serial = port->serial;
if (serial == NULL || (serial_priv = usb_get_serial_data(serial)) == NULL) {
dev_err(&port->dev,
"%s: serial or serial->private is NULL, status=%d\n",
__func__, status);
return;
}
/* handle oob callback */
if (priv->lpcp_port_num == serial_priv->lpcs_oob_port_num) {
dev_dbg(&port->dev, "lpc_write_bulk_callback: oob callback\n");
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
priv->lpcp_write_urb_in_use = 0;
wake_up_interruptible(&port->write_wait);
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
return;
}
/* try to send any buffered data on this port */
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
priv->lpcp_write_urb_in_use = 0;
if (priv->lpcp_out_buf_len > 0) {
*((unsigned char *)(port->write_urb->transfer_buffer))
= (unsigned char)LPC_CMD_SEND_DATA;
*((unsigned char *)(port->write_urb->transfer_buffer) + 1)
= (unsigned char)index;
*((unsigned char *)(port->write_urb->transfer_buffer) + 2)
= (unsigned char)priv->lpcp_out_buf_len;
port->write_urb->transfer_buffer_length =
priv->lpcp_out_buf_len + 3;
memcpy(port->write_urb->transfer_buffer + 3, priv->lpcp_out_buf,
priv->lpcp_out_buf_len);
ret = usb_submit_urb(port->write_urb, GFP_ATOMIC);
if (ret == 0) {
priv->lpcp_write_urb_in_use = 1;
priv->lpcp_out_buf_len = 0;
}
}
/* wake up processes sleeping on writes immediately */
tty_port_tty_wakeup(&port->port);
/* also queue up a wakeup at scheduler time, in case we */
/* lost the race in write_chan(). */
schedule_work(&priv->lpcp_wakeup_work);
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
if (ret && ret != -EPERM)
dev_err_console(port,
"%s: usb_submit_urb failed, ret=%d, port=%d\n",
__func__, ret, priv->lpcp_port_num);
}
static int lpc_write_room(struct tty_struct *tty)
{
struct usb_serial_port *port = tty->driver_data;
struct lpc_port *priv = usb_get_serial_port_data(port);
int room;
unsigned long flags = 0;
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
if (priv->lpcp_write_urb_in_use)
room = 0;
else
room = port->bulk_out_size - 3 - priv->lpcp_out_buf_len;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
dev_dbg(&port->dev, "lpc_write_room: port=%d, room=%d\n", priv->lpcp_port_num, room);
return room;
}
static int lpc_chars_in_buffer(struct tty_struct *tty)
{
struct usb_serial_port *port = tty->driver_data;
struct lpc_port *priv = usb_get_serial_port_data(port);
if (priv->lpcp_write_urb_in_use) {
dev_dbg(&port->dev, "lpc_chars_in_buffer: port=%d, chars=%d\n",
priv->lpcp_port_num, port->bulk_out_size - 3);
/* return(port->bulk_out_size - 2); */
return 256;
} else {
dev_dbg(&port->dev, "lpc_chars_in_buffer: port=%d, chars=%d\n",
priv->lpcp_port_num, priv->lpcp_out_buf_len);
return priv->lpcp_out_buf_len;
}
}
static void lpc_dtr_rts(struct usb_serial_port *port, int on)
{
/* Adjust DTR and RTS */
lpc_set_modem_signals(port, on * (TIOCM_DTR|TIOCM_RTS), 1);
}
static int lpc_open(struct tty_struct *tty, struct usb_serial_port *port)
{
int ret;
unsigned char buf[8];
struct lpc_port *priv = usb_get_serial_port_data(port);
struct ktermios not_termios;
/* be sure the device is started up */
if (lpc_startup_device(port->serial) != 0)
return -ENXIO;
/* read modem signals automatically whenever they change */
buf[0] = LPC_CMD_READ_INPUT_SIGNALS;
buf[1] = priv->lpcp_port_num;
buf[2] = LPC_ENABLE;
buf[3] = 0;
/* flush fifos */
buf[4] = LPC_CMD_IFLUSH_FIFO;
buf[5] = priv->lpcp_port_num;
buf[6] = LPC_FLUSH_TX | LPC_FLUSH_RX;
buf[7] = 0;
ret = lpc_write_oob_command(port, buf, 8, 1);
if (ret != 0)
dev_dbg(&port->dev, "lpc_open: write oob failed, ret=%d\n", ret);
/* set termios settings */
if (tty) {
not_termios.c_cflag = ~tty->termios.c_cflag;
not_termios.c_iflag = ~tty->termios.c_iflag;
lpc_set_termios(tty, port, ¬_termios);
}
return 0;
}
static void lpc_close(struct usb_serial_port *port)
{
DEFINE_WAIT(wait);
int ret;
unsigned char buf[32];
struct lpc_port *priv = usb_get_serial_port_data(port);
mutex_lock(&port->serial->disc_mutex);
/* if disconnected, just clear flags */
if (port->serial->disconnected)
goto exit;
/* FIXME: Transmit idle belongs in the wait_unti_sent path */
lpc_transmit_idle(port, LPC_CLOSE_TIMEOUT);
/* disable input flow control */
buf[0] = LPC_CMD_SET_INPUT_FLOW_CONTROL;
buf[1] = priv->lpcp_port_num;
buf[2] = LPC_DISABLE;
buf[3] = 0;
/* disable output flow control */
buf[4] = LPC_CMD_SET_OUTPUT_FLOW_CONTROL;
buf[5] = priv->lpcp_port_num;
buf[6] = LPC_DISABLE;
buf[7] = 0;
/* disable reading modem signals automatically */
buf[8] = LPC_CMD_READ_INPUT_SIGNALS;
buf[9] = priv->lpcp_port_num;
buf[10] = LPC_DISABLE;
buf[11] = 0;
/* disable receive */
buf[12] = LPC_CMD_RECEIVE_ENABLE;
buf[13] = priv->lpcp_port_num;
buf[14] = LPC_DISABLE;
buf[15] = 0;
/* flush fifos */
buf[16] = LPC_CMD_IFLUSH_FIFO;
buf[17] = priv->lpcp_port_num;
buf[18] = LPC_FLUSH_TX | LPC_FLUSH_RX;
buf[19] = 0;
ret = lpc_write_oob_command(port, buf, 20, 0);
if (ret != 0)
dev_dbg(&port->dev, "lpc_close: write oob failed, ret=%d\n",
ret);
/* wait for final commands on oob port to complete */
prepare_to_wait(&priv->lpcp_flush_wait, &wait,
TASK_INTERRUPTIBLE);
schedule_timeout(LPC_CLOSE_TIMEOUT);
finish_wait(&priv->lpcp_flush_wait, &wait);
/* shutdown any outstanding bulk writes */
usb_kill_urb(port->write_urb);
exit:
spin_lock_irq(&priv->lpcp_port_lock);
priv->lpcp_write_urb_in_use = 0;
wake_up_interruptible(&priv->lpcp_close_wait);
spin_unlock_irq(&priv->lpcp_port_lock);
mutex_unlock(&port->serial->disc_mutex);
}
/*
* lpc Startup Device
*
* Starts reads on all ports. Must be called AFTER startup, with
* urbs initialized. Returns 0 if successful, non-zero error otherwise.
*/
static int lpc_startup_device(struct usb_serial *serial)
{
int i, ret = 0;
struct lpc_serial *serial_priv = usb_get_serial_data(serial);
struct usb_serial_port *port;
/* be sure this happens exactly once */
spin_lock(&serial_priv->lpcs_serial_lock);
if (serial_priv->lpcs_device_started) {
spin_unlock(&serial_priv->lpcs_serial_lock);
return 0;
}
serial_priv->lpcs_device_started = 1;
spin_unlock(&serial_priv->lpcs_serial_lock);
/* start reading from each bulk in endpoint for the device */
/* set USB_DISABLE_SPD flag for write bulk urbs */
for (i = 0; i < serial->type->num_ports + 1; i++) {
port = serial->port[i];
ret = usb_submit_urb(port->read_urb, GFP_KERNEL);
if (ret != 0) {
dev_err(&port->dev,
"%s: usb_submit_urb failed, ret=%d, port=%d\n",
__func__, ret, i);
break;
}
}
return ret;
}
static int lpc_port_init(struct usb_serial_port *port, unsigned port_num)
{
struct lpc_port *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
spin_lock_init(&priv->lpcp_port_lock);
priv->lpcp_port_num = port_num;
init_waitqueue_head(&priv->lpcp_transmit_idle_wait);
init_waitqueue_head(&priv->lpcp_transmit_is_full);
init_waitqueue_head(&priv->lpcp_flush_wait);
init_waitqueue_head(&priv->lpcp_close_wait);
INIT_WORK(&priv->lpcp_wakeup_work, lpc_wakeup_write_lock);
priv->lpcp_port = port;
init_waitqueue_head(&port->write_wait);
usb_set_serial_port_data(port, priv);
return 0;
}
/* add recv_number and send_number attribute to the device ttyUSB */
static void lpc_add_attribute(struct usb_serial *serial)
{
int i;
struct usb_serial_port *port;
for(i = 0; i < serial->num_ports;i++){
port = serial->port[i];
port->dev.groups = usb_serial_port_groups;
}
}
static int lpc_startup(struct usb_serial *serial)
{
struct lpc_serial *serial_priv;
int ret;
lpc_add_attribute(serial);
serial_priv = kzalloc(sizeof(*serial_priv), GFP_KERNEL);
if (!serial_priv)
return -ENOMEM;
spin_lock_init(&serial_priv->lpcs_serial_lock);
serial_priv->lpcs_oob_port_num = serial->type->num_ports;
serial_priv->lpcs_oob_port = serial->port[serial_priv->lpcs_oob_port_num];
ret = lpc_port_init(serial_priv->lpcs_oob_port,
serial_priv->lpcs_oob_port_num);
if (ret) {
kfree(serial_priv);
return ret;
}
usb_set_serial_data(serial, serial_priv);
return 0;
}
static void lpc_disconnect(struct usb_serial *serial)
{
int i;
/* stop reads and writes on all ports */
for (i = 0; i < serial->type->num_ports + 1; i++) {
usb_kill_urb(serial->port[i]->read_urb);
usb_kill_urb(serial->port[i]->write_urb);
}
}
static void lpc_release(struct usb_serial *serial)
{
struct lpc_serial *serial_priv;
struct lpc_port *priv;
serial_priv = usb_get_serial_data(serial);
priv = usb_get_serial_port_data(serial_priv->lpcs_oob_port);
kfree(priv);
kfree(serial_priv);
}
static int lpc_port_probe(struct usb_serial_port *port)
{
return lpc_port_init(port, port->port_number);
}
static int lpc_port_remove(struct usb_serial_port *port)
{
struct lpc_port *priv;
priv = usb_get_serial_port_data(port);
kfree(priv);
return 0;
}
static void lpc_read_bulk_callback(struct urb *urb)
{
struct usb_serial_port *port = urb->context;
struct lpc_port *priv;
struct lpc_serial *serial_priv;
int ret;
int status = urb->status;
/* port sanity check, do not resubmit if port is not valid */
if (port == NULL)
return;
priv = usb_get_serial_port_data(port);
if (priv == NULL) {
dev_err(&port->dev, "%s: port->private is NULL, status=%d\n",
__func__, status);
return;
}
if (port->serial == NULL ||
(serial_priv = usb_get_serial_data(port->serial)) == NULL) {
dev_err(&port->dev, "%s: serial is bad or serial->private "
"is NULL, status=%d\n", __func__, status);
return;
}
/* do not resubmit urb if it has any status error */
if (status) {
dev_err(&port->dev,
"%s: nonzero read bulk status: status=%d, port=%d\n",
__func__, status, priv->lpcp_port_num);
return;
}
/* handle oob or inb callback, do not resubmit if error */
if (priv->lpcp_port_num == serial_priv->lpcs_oob_port_num) {
if (lpc_read_oob_callback(urb) != 0)
return;
} else {
if (lpc_read_inb_callback(urb) != 0)
return;
}
/* continue read */
ret = usb_submit_urb(urb, GFP_ATOMIC);
if (ret != 0 && ret != -EPERM) {
dev_err(&port->dev,
"%s: failed resubmitting urb, ret=%d, port=%d\n",
__func__, ret, priv->lpcp_port_num);
}
}
/*
* lpc Read INB Callback
*
* lpc Read INB Callback handles reads on the in band ports, sending
* the data on to the tty subsystem. When called we know port and
* port->private are not NULL and port->serial has been validated.
* It returns 0 if successful, 1 if successful but the port is
* throttled, and -1 if the sanity checks failed.
*/
static int lpc_read_inb_callback(struct urb *urb)
{
struct usb_serial_port *port = urb->context;
struct usb_serial_port *tmp = port;
struct lpc_port *priv = NULL;
struct usb_serial* serial;
unsigned char *buf = urb->transfer_buffer;
unsigned long flags;
int opcode;
int len;
int index;
unsigned char *data;
int tty_flag, throttled;
/* short/multiple packet check */
if (urb->actual_length < 2) {
dev_warn(&port->dev, "short packet received\n");
return -1;
}
opcode = buf[0];
index = buf[1];
len = buf[2];
serial = port->serial;
port = serial->port[index];
priv = usb_get_serial_port_data(port);
if (urb->actual_length != len + 3) {
dev_err(&port->dev, "malformed packet received: port=%d, opcode=%d, len=%d, actual_length=%u\n",
priv->lpcp_port_num, opcode, len, urb->actual_length);
return -1;
}
if (opcode == LPC_CMD_RECEIVE_DATA && len < 1) {
dev_err(&port->dev, "malformed data packet received\n");
return -1;
}
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
/* check for throttle; if set, do not resubmit read urb */
/* indicate the read chain needs to be restarted on unthrottle */
throttled = priv->lpcp_throttled;
if (throttled){
priv->lpcp_throttle_restart = 1;
/*swap the urb and urb->context*/
tmp->read_urb = port->read_urb;
tmp->read_urb->context = tmp;
urb->context = port;
port->read_urb = urb;
}
/* receive data */
if (opcode == LPC_CMD_RECEIVE_DATA) {
data = &buf[3];
/* get flag from port_status */
tty_flag = 0;
if (len > 0) {
priv->lpcp_upload_num += len;
tty_insert_flip_string_fixed_flag(&port->port, data,
tty_flag, len);
tty_flip_buffer_push(&port->port);
}
}
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
if (opcode == LPC_CMD_RECEIVE_DISABLE)
dev_dbg(&port->dev, "%s: got RECEIVE_DISABLE\n", __func__);
else if (opcode != LPC_CMD_RECEIVE_DATA)
dev_dbg(&port->dev, "%s: unknown opcode: %d\n", __func__, opcode);
return throttled ? 1 : 0;
}
/*
* lpc Read OOB Callback
*
* lpc Read OOB Callback handles reads on the out of band port.
* When called we know port and port->private are not NULL and
* the port->serial is valid. It returns 0 if successful, and
* -1 if the sanity checks failed.
*/
static int lpc_read_oob_callback(struct urb *urb)
{
struct usb_serial_port *port = urb->context;
struct usb_serial *serial = port->serial;
struct tty_struct *tty;
struct lpc_port *priv = usb_get_serial_port_data(port);
unsigned char *buf = urb->transfer_buffer;
int opcode, channel, status, val;
unsigned long flags;
int i;
unsigned int rts;
if (urb->actual_length < 4)
return -1;
/* handle each oob command */
for (i = 0; i < urb->actual_length; i += 4) {
opcode = buf[i];
channel = buf[i + 1];
status = buf[i + 2];
val = buf[i + 3];
dev_dbg(&port->dev, "lpc_read_oob_callback:length=%d, opcode=%d, channel=%d, status=%d, val=%d\n",
urb->actual_length,opcode, channel, status, val);
if (status != 0 || channel >= serial->type->num_ports)
continue;
port = serial->port[channel];
priv = usb_get_serial_port_data(port);
if (priv == NULL)
return -1;
/* check whether receive buffer is full */
if (opcode == LPC_CMD_TRANSMIT_FULL) {
if(status == 0){
wake_up_interruptible(&priv->lpcp_transmit_is_full);
}
return 0;
}
tty = tty_port_tty_get(&port->port);
rts = 0;
if (tty)
rts = C_CRTSCTS(tty);
if (tty && opcode == LPC_CMD_READ_INPUT_SIGNALS) {
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
/* convert from lpc flags to termiox flags */
if (val & LPC_READ_INPUT_SIGNALS_CTS) {
priv->lpcp_modem_signals |= TIOCM_CTS;
/* port must be open to use tty struct */
if (rts)
tty_port_tty_wakeup(&port->port);
} else {
priv->lpcp_modem_signals &= ~TIOCM_CTS;
/* port must be open to use tty struct */
}
if (val & LPC_READ_INPUT_SIGNALS_DSR)
priv->lpcp_modem_signals |= TIOCM_DSR;
else
priv->lpcp_modem_signals &= ~TIOCM_DSR;
if (val & LPC_READ_INPUT_SIGNALS_RI)
priv->lpcp_modem_signals |= TIOCM_RI;
else
priv->lpcp_modem_signals &= ~TIOCM_RI;
if (val & LPC_READ_INPUT_SIGNALS_DCD)
priv->lpcp_modem_signals |= TIOCM_CD;
else
priv->lpcp_modem_signals &= ~TIOCM_CD;
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
} else if (opcode == LPC_CMD_TRANSMIT_IDLE) {
spin_lock_irqsave(&priv->lpcp_port_lock, flags);
priv->lpcp_transmit_idle = 1;
wake_up_interruptible(&priv->lpcp_transmit_idle_wait);
spin_unlock_irqrestore(&priv->lpcp_port_lock, flags);
} else if (opcode == LPC_CMD_IFLUSH_FIFO) {
wake_up_interruptible(&priv->lpcp_flush_wait);
}
tty_kref_put(tty);
}
return 0;
}
module_usb_serial_driver(serial_drivers, id_table_10);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/src/system_MKV10Z7.c
|
/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KV10P48M75RM Rev.2, July 2013
** Version: rev. 1.0, 2013-05-09
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2013-05-09)
** Initial version.
**
** ###################################################################
*/
/*!
* @file MKV10Z7
* @version 1.0
* @date 2013-05-09
* @brief Device specific configuration file for MKV10Z7 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MKV10Z7.h"
#define DISABLE_WDOG 1
#define CLOCK_SETUP 0
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 72MHz, BusClock = 24MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (FEE) mode
Reference clock source for MCG module is an external crystal 10MHz
Core clock = 75MHz, BusClock = 25MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external crystal 10MHz with no multiplication
Core clock = 10MHz, BusClock = 10MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 10000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 10000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 75000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 10000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 10000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 2) */
/* ----------------------------------------------------------------------------
-- Non-volatile IRC user trim field
---------------------------------------------------------------------------- */
#define NON_VOLATILE_IRC_USER_TRIM(offset) (((uint8_t*)0x000003FCu)[offset])
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
int main(void);
void SystemInit (void) {
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
/* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = (uint16_t)0x01D2u;
#endif /* (DISABLE_WDOG) */
#if (CLOCK_SETUP == 0)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV4=2, OUTDIV5EN=1, OUTDIV5=1 */
SIM->CLKDIV1 = (uint32_t)0x00029000UL; /* Update system prescalers */
/* Switch to FEI Mode */
/* MCG->C1: CLKS=0, FRDIV=0, IREFS=1, IRCLKEN=1, IREFSTEN=0 */
MCG->C1 = (uint8_t)0x06U;
/* MCG->C2: LOCRE0=0, FCFTRIM=FCFTRIM_Trim, RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)(((uint8_t)0x40U) & NON_VOLATILE_IRC_USER_TRIM(2));
/* MCG->C3: SCTRIM=SCTRIM_Trim */
MCG->C3 = NON_VOLATILE_IRC_USER_TRIM(3);
/* MCG->C4: DMX32=1, DRST_DRS=2, FCTRIM=FCTRIM_Trim, SCFTRIM=SCFTRIM_Trim */
MCG->C4 = (uint8_t)(((uint8_t)0xC0U) | (uint8_t)(((uint8_t)0x1FU) & NON_VOLATILE_IRC_USER_TRIM(2)));
/* MCG->C6: CME0=0 */
MCG->C6 = (uint8_t)0x00U;
while((uint8_t)(MCG->S & (uint8_t)0x1DU) != (uint8_t)0x10U) { /* Check that IREFST=1, CLKST=0, IRCST=0. */
}
#elif (CLOCK_SETUP == 1)
/* SIM->SCGC5: PORTE=0, PORTD=0, PORTC=0, PORTB=0, PORTA=1, LPTMR=0 */
SIM->SCGC5 = (uint32_t)0x00040380UL; /* Enable clock gate for ports to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV4=2, OUTDIV5EN=1, OUTDIV5=1 */
SIM->CLKDIV1 = (uint32_t)0x00029000UL; /* Update system prescalers */
/* PORTA->PCR18: ISF=1, IRQC=0, MUX=0, DSE=0, PFE=0, SRE=0, PE=0, PS=1 */
PORTA->PCR[18] = (uint32_t)0x01000001UL;
/* PORTA->PCR19: ISF=1, IRQC=0, MUX=0, DSE=0, PFE=0, SRE=0, PE=0, PS=1 */
PORTA->PCR[19] = (uint32_t)0x01000001UL;
/* Switch to FEE Mode */
/* MCG->C2: LOCRE0=0, FCFTRIM=FCFTRIM_Trim, RANGE0=1, HGO0=0, EREFS0=1, LP=0, IRCS=0 */
MCG->C2 = (uint8_t)(((uint8_t)0x40U & NON_VOLATILE_IRC_USER_TRIM(2)) | (uint8_t)0x14U);
/* OSC0->CR: ERCLKEN=1, EREFSTEN=0, SC2P=0, SC4P=0, SC8P=0, SC16P=0 */
OSC0->CR = (uint8_t)0x80U;
while((uint8_t)(MCG->S & (uint8_t)0x02U) != (uint8_t)0x02U) { /* Check that OSCINIT0=1 */
}
/* MCG_C1: CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=1, IREFSTEN=0 */
MCG->C1 = (uint8_t)0x1AU;
while((uint8_t)(MCG->S & (uint8_t)0x1DU) != (uint8_t)0x00U) { /* Check that Check that IREFST=0, CLKST=0, IRCST=0. */
}
/* MCG->C3: SCTRIM=SCTRIM_Trim */
MCG->C3 = NON_VOLATILE_IRC_USER_TRIM(3);
/* MCG->C4: DMX32=0, DRST_DRS=2, FCTRIM=FCTRIM_Trim, SCFTRIM=SCFTRIM_Trim */
MCG->C4 = (uint8_t)(((uint8_t)0x40U) | (uint8_t)(((uint8_t)0x1FU) & NON_VOLATILE_IRC_USER_TRIM(2)));
/* MCG->C6: CME0=0 */
MCG->C6 = (uint8_t)0x00U;
#elif (CLOCK_SETUP == 2)
/* SIM->SCGC5: PORTE=0, PORTD=0, PORTC=0, PORTB=0, PORTA=1, LPTMR=0 */
SIM->SCGC5 = (uint32_t)0x00040380UL; /* Enable clock gate for ports to enable pin routing */
/* PORTA->PCR18: ISF=1, IRQC=0, MUX=0, DSE=0, PFE=0, SRE=0, PE=0, PS=1 */
PORTA->PCR[18] = (uint32_t)0x01000001UL;
/* PORTA->PCR19: ISF=1, IRQC=0, MUX=0, DSE=0, PFE=0, SRE=0, PE=0, PS=1 */
PORTA->PCR[19] = (uint32_t)0x01000001UL;
/* Switch to FEE Mode */
/* MCG->C2: LOCRE0=0, FCFTRIM=FCFTRIM_Trim, RANGE0=1, HGO0=0, EREFS0=1, LP=0, IRCS=0 */
MCG->C2 = (uint8_t)(((uint8_t)0x40U & NON_VOLATILE_IRC_USER_TRIM(2)) | (uint8_t)0x14U);
/* OSC0->CR: ERCLKEN=1, EREFSTEN=0, SC2P=0, SC4P=0, SC8P=0, SC16P=0 */
OSC0->CR = (uint8_t)0x80U;
while((uint8_t)(MCG->S & (uint8_t)0x02U) != (uint8_t)0x02U) { /* Check that OSCINIT0=1 */
}
/* MCG_C1: CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=1, IREFSTEN=1 */
MCG->C1 = (uint8_t)0x9BU;
while((uint8_t)(MCG->S & (uint8_t)0x1DU) != (uint8_t)0x08U) { /* Check that Check that IREFST=0, CLKST=2, IRCST=0. */
}
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV4=0, OUTDIV5EN=1, OUTDIV5=0 */
SIM->CLKDIV1 = (uint32_t)0x00008000UL; /* Update system prescalers */
/* MCG->C2: LOCRE0=0, FCFTRIM=FCFTRIM_Trim, RANGE0=1, HGO0=0, EREFS0=1, LP=1, IRCS=0 */
MCG->C2 = (uint8_t)(((uint8_t)0x40U & NON_VOLATILE_IRC_USER_TRIM(2)) | (uint8_t)0x16U);
while((uint8_t)(MCG->S & (uint8_t)0x01U) != (uint8_t)0x00U) { /* Check that Check that IRCST=0. */
}
#endif /* (CLOCK_SETUP == 2) */
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
switch ((uint8_t)(MCG->C1 & MCG_C1_CLKS_MASK)) {
case 0x00u: /* Output of FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { /* External reference clock is selected */
MCGOUTClock = (uint32_t)((uint32_t)CPU_XTAL_CLK_HZ >> (uint8_t)((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); /* System oscillator drives MCG clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
}; /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
break;
case 0x40u: /* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = (uint32_t)((uint32_t)CPU_INT_FAST_CLK_HZ >> (uint8_t)((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
break;
case 0x80u: /* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ;
break;
default:
return; /* Reserved value */
}
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/vsc/usbd_digi_serial.c
|
<filename>mcu_source/Libraries/utilities/chusb/src/vsc/usbd_digi_serial.c
#include <string.h>
#include "usb_common.h"
#include "usbd.h"
#include "usbd_digi_serial.h"
#include "uart_bridge.h"
#include "uart.h"
#include "ulog.h"
#define DIGI_USBD_VID (0x1FC9)
#define DIGI_USBD_PID (0xEA60)
#define USBD_DIGI_SERIAL_CTL_BULKIN (1)
#define USBD_DIGI_SERIAL_CTL_BULKOUT (1)
#define USBD_DIGI_SERIAL_DATA_BULKIN (2)
#define USBD_DIGI_SERIAL_DATA_BULKOUT (2)
#define DIGI_CMD_SET_BAUD_RATE 0 /* INB, OOB */
#define DIGI_CMD_SET_WORD_SIZE 1 /* INB, OOB */
#define DIGI_CMD_SET_PARITY 2 /* INB, OOB */
#define DIGI_CMD_SET_STOP_BITS 3 /* INB, OOB */
#define DIGI_CMD_SET_INPUT_FLOW_CONTROL 4 /* INB, OOB */
#define DIGI_CMD_SET_OUTPUT_FLOW_CONTROL 5 /* INB, OOB */
#define DIGI_CMD_SET_DTR_SIGNAL 6 /* INB, OOB */
#define DIGI_CMD_SET_RTS_SIGNAL 7 /* INB, OOB */
#define DIGI_CMD_READ_INPUT_SIGNALS 8 /* OOB */
#define DIGI_CMD_IFLUSH_FIFO 9 /* OOB */
#define DIGI_CMD_RECEIVE_ENABLE 10 /* INB, OOB */
#define DIGI_CMD_BREAK_CONTROL 11 /* INB, OOB */
#define DIGI_CMD_LOCAL_LOOPBACK 12 /* INB, OOB */
#define DIGI_CMD_TRANSMIT_IDLE 13 /* INB, OOB */
#define DIGI_CMD_READ_UART_REGISTER 14 /* OOB */
#define DIGI_CMD_WRITE_UART_REGISTER 15 /* INB, OOB */
#define DIGI_CMD_AND_UART_REGISTER 16 /* INB, OOB */
#define DIGI_CMD_OR_UART_REGISTER 17 /* INB, OOB */
#define DIGI_CMD_SEND_DATA 18 /* INB */
#define DIGI_CMD_RECEIVE_DATA 19 /* INB */
#define DIGI_CMD_RECEIVE_DISABLE 20 /* INB */
#define DIGI_CMD_GET_PORT_TYPE 21 /* OOB */
#define DIGI_CMD_GET_BUFFER_STAT 22
/* baud rates */
#define DIGI_BAUD_50 0
#define DIGI_BAUD_75 1
#define DIGI_BAUD_110 2
#define DIGI_BAUD_150 3
#define DIGI_BAUD_200 4
#define DIGI_BAUD_300 5
#define DIGI_BAUD_600 6
#define DIGI_BAUD_1200 7
#define DIGI_BAUD_1800 8
#define DIGI_BAUD_2400 9
#define DIGI_BAUD_4800 10
#define DIGI_BAUD_7200 11
#define DIGI_BAUD_9600 12
#define DIGI_BAUD_14400 13
#define DIGI_BAUD_19200 14
#define DIGI_BAUD_28800 15
#define DIGI_BAUD_38400 16
#define DIGI_BAUD_57600 17
#define DIGI_BAUD_76800 18
#define DIGI_BAUD_115200 19
#define DIGI_BAUD_153600 20
#define DIGI_BAUD_230400 21
#define DIGI_BAUD_460800 22
static uint8_t digi_cdc_out_buf[512];
extern rt_mutex_t usb_lock;
static rt_sem_t dg_out_sem;
extern int usb_report_stat_chl;
extern int usb_ctl_need_report_stat;
extern stat_t stat;
/* msd */
const uint8_t digi_serial_descriptor[] =
{
USB_DESC_LENGTH_INTERFACE,
USB_DESC_TYPE_INTERFACE,
0, /* interfac index */
0x00,
0x04, /* 4 end point */
USB_CLASS_VEND_SPECIFIC,
0x00,
0x00,
USBD_IF_STR_IDX(USBD_MSC_IF_IDX),
/* endpoint descriptor CTL */
0x07,
USB_DESC_TYPE_ENDPOINT,
(0x80 | USBD_DIGI_SERIAL_CTL_BULKIN),
0x02, /* buck */
WBVAL(512),
0,
0x07,
USB_DESC_TYPE_ENDPOINT,
(0x00 | USBD_DIGI_SERIAL_CTL_BULKOUT),
0x02,
WBVAL(512),
0,
/* endpoint descriptor DATA */
0x07,
USB_DESC_TYPE_ENDPOINT,
(0x80 | USBD_DIGI_SERIAL_DATA_BULKIN),
0x02,
WBVAL(512),
0,
0x07,
USB_DESC_TYPE_ENDPOINT,
(0x00 | USBD_DIGI_SERIAL_DATA_BULKOUT),
0x02,
WBVAL(512),
0,
};
/* data handler */
static uint32_t digi_data_ep_handler(uint8_t ep, uint8_t dir)
{
uint8_t digi_cdc_ob_out_buf[128];
uint8_t size, cmd, chl, val;
if(dir == 1) /* in transfer */
{
if(ep == USBD_DIGI_SERIAL_CTL_BULKIN)
{
bridge_uart_usb_data_in_ready();
}
if(ep == USBD_DIGI_SERIAL_DATA_BULKIN)
{
}
}
else /* out transfer */
{
if(ep == USBD_DIGI_SERIAL_DATA_BULKOUT)
{
size = usbd_ep_read(ep, digi_cdc_ob_out_buf);
cmd = digi_cdc_ob_out_buf[0];
chl = digi_cdc_ob_out_buf[1];
val = digi_cdc_ob_out_buf[2];
switch(cmd)
{
case DIGI_CMD_READ_INPUT_SIGNALS:
// LOG_I("CTRLOUT[%d] - DIGI_CMD_READ_INPUT_SIGNALS\r\n", chl);
break;
case DIGI_CMD_SET_INPUT_FLOW_CONTROL:
// LOG_I("CTRLOUT[%d] - DIGI_CMD_SET_INPUT_FLOW_CONTROL\r\n", chl);
break;
case DIGI_CMD_SET_BAUD_RATE:
// LOG_I("CTRLOUT[%d] - DIGI_CMD_SET_BAUD_RATE baud:%d\r\n", chl, val);
switch(val)
{
case DIGI_BAUD_4800:
UART_SetBaudRate(chl, 4800);
break;
case DIGI_BAUD_9600:
UART_SetBaudRate(chl, 9600);
break;
case DIGI_BAUD_38400:
UART_SetBaudRate(chl, 38400);
break;
case DIGI_BAUD_115200:
UART_SetBaudRate(chl, 115200);
break;
default:
LOG_E("un-supported baud rate");
break;
}
break;
case DIGI_CMD_LOCAL_LOOPBACK:
// LOG_I("CTRLOUT[%d] - DIGI_CMD_LOCAL_LOOPBACK val:%d\r\n", chl, val);
UART_SetLoopbackMode(chl, val);
break;
case DIGI_CMD_SET_DTR_SIGNAL:
// LOG_I("CTRLOUT[%d] - DIGI_CMD_SET_DTR_SIGNAL\r\n", chl);
break;
case DIGI_CMD_GET_BUFFER_STAT:
//LOG_I("CTRLOUT[%d] - DIGI_CMD_GET_BUFFER_STAT\r\n", chl);
usb_report_stat_chl = chl;
usb_ctl_need_report_stat = 1;
break;
default:
LOG_E("unknown ctrl out cmd:%d chl:%d\r\n", cmd, chl);
ulog_hexdump("example", 16, digi_cdc_ob_out_buf, size);
break;
}
}
if(ep == USBD_DIGI_SERIAL_CTL_BULKOUT)
{
rt_sem_release(dg_out_sem);
}
}
return 0;
}
void dg_out_thread_entry(void* parameter)
{
uint32_t size, len, free;
uint8_t op_code, chl;
while(1)
{
rt_sem_take(dg_out_sem, RT_WAITING_FOREVER);
/* read data from USB */
size = usbd_ep_read(USBD_DIGI_SERIAL_CTL_BULKOUT, digi_cdc_out_buf);
op_code = digi_cdc_out_buf[0];
chl = digi_cdc_out_buf[1];
len = digi_cdc_out_buf[2];
if(op_code == DIGI_CMD_SEND_DATA)
{
/* get free buffer */
free = bridge_uart_tx_get_free(chl);
while(free < size)
{
free = bridge_uart_tx_get_free(chl);
rt_thread_delay(1);
}
stat.total_out += len;
bridge_uart_send(chl, &digi_cdc_out_buf[3], len);
}
}
}
/* handle vender specfic class request */
static uint32_t digi_vender_request_handler(struct usbd_t *h)
{
LOG_I("digi_vender_request_handler\r\n");
return 0;
}
void usbd_vsc_digi_serial_init(struct usbd_t *h)
{
uint8_t *p;
struct uconfig_descriptor *uconfiguration_descriptor;
desc_t d;
/* make descriptor */
get_descriptor_data("device_descriptor", &d);
struct udevice_descriptor* device_desc = (struct udevice_descriptor*)d.buf;
device_desc->bDeviceClass = USB_CLASS_VEND_SPECIFIC;
device_desc->bDeviceSubClass = 0x00;
device_desc->bDeviceProtocol = 0x00;
/* make configuration descriptor */
get_descriptor_data("configuration_descriptor", &d);
uconfiguration_descriptor = (struct uconfig_descriptor *)d.buf;
uconfiguration_descriptor->bLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->type = USB_DESC_TYPE_CONFIGURATION;
uconfiguration_descriptor->wTotalLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->bNumInterfaces = 1;
uconfiguration_descriptor->bConfigurationValue = 1;
uconfiguration_descriptor->iConfiguration = 0;
uconfiguration_descriptor->bmAttributes = 0x80;
uconfiguration_descriptor->MaxPower = 0x32;
device_desc->idVendor = DIGI_USBD_VID;
device_desc->idProduct = DIGI_USBD_PID;
/* make intf and add to configuation data */
p = uconfiguration_descriptor->data;
d.buf = digi_serial_descriptor;
d.len = sizeof(digi_serial_descriptor);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
h->vender_request_handler = digi_vender_request_handler;
h->data_ep_handler = digi_data_ep_handler;
dg_out_sem = rt_sem_create("dg_out", 0, RT_IPC_FLAG_FIFO);
rt_thread_t tid;
tid = rt_thread_create("dg_out", dg_out_thread_entry, RT_NULL, 256, 6, 20);
rt_thread_startup(tid);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/src/system_QN908XB.c
|
/*
** ###################################################################
** Processors: QN908X
** QN908X
**
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: QN908X User manual Rev. 1.0 16 February 2016
** Version: rev. 1.0, 2016-04-29
** Build: b160525
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2016-04-29)
** Initial version.
**
** ###################################################################
*/
/*!
* @file system_QN908X
* @version 1.0
* @date 2016-04-29
* @brief Device specific configuration file for QN908X (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "QN908XB.h"
extern void *__Vectors;
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/*
* FUNCTION DEFINITIONS
****************************************************************************************
*/
/**
****************************************************************************************
* @brief Setup the microcontroller system.
*****************************************************************************************
*/
void SystemInit(void)
{
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) || (defined(__VFP_FP__) && !defined(__SOFTFP__))
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
SCB->VTOR = (uint32_t)&__Vectors;
/* Disable chip test mode */
*((uint32_t *)0x40000080) &= 0x0FFFFFFF;
/* Disable watchdog timer */
WDT->LOCK = 0x1ACCE551;
WDT->CTRL = 0;
WDT->LOCK = 0;
/* Save power in active mode */
SYSCON->CLK_CTRL = (SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_CGBYPASS_MASK) | SYSCON_CLK_CTRL_CGBYPASS(0U);
/* speed up the startup of XTAL by decrease load cap */
SYSCON->XTAL_CTRL = (SYSCON->XTAL_CTRL &
~(SYSCON_XTAL_CTRL_XTAL_SU_CA_REG_MASK | SYSCON_XTAL_CTRL_XTAL_SU_CB_REG_MASK |
SYSCON_XTAL_CTRL_XTAL_XCUR_BOOST_REG_MASK)) |
SYSCON_XTAL_CTRL_XTAL_SU_CA_REG(0U) | SYSCON_XTAL_CTRL_XTAL_SU_CB_REG(0U) |
SYSCON_XTAL_CTRL_XTAL_XCUR_BOOST_REG_MASK;
/* change crystal load cap to (0.35 * 0x08 + 5) = 7.8pF for DK board, and half of default voltage*/
SYSCON->ANA_CTRL0 = (SYSCON->ANA_CTRL0 & ~(SYSCON_ANA_CTRL0_XTAL_LOAD_CAP_MASK | SYSCON_ANA_CTRL0_XTAL_AMP_MASK)) |
SYSCON_ANA_CTRL0_XTAL_LOAD_CAP(8U) | SYSCON_ANA_CTRL0_XTAL_AMP(2U);
/* Adjust mem & pmu voltage */
/* if VDD_PMU_SET_ULTRA_LOW bit is set, SYSCON_ANA_CTRL1_VDD_MEM_SET_PDM_MASK will be ignored */
SYSCON->ANA_CTRL1 = (SYSCON->ANA_CTRL1 &
~(SYSCON_ANA_CTRL1_VDD_PMU_SET_PDM_MASK | SYSCON_ANA_CTRL1_VDD_PMU_SET_MASK |
SYSCON_ANA_CTRL1_VDD_MEM_SET_PDM_MASK | SYSCON_ANA_CTRL1_VDD_MEM_SET_MASK |
SYSCON_ANA_CTRL1_VDD_PMU_SET_ULTRA_LOW_MASK | SYSCON_ANA_CTRL1_IV_VREG11_SET_MASK |
SYSCON_ANA_CTRL1_DVREG11_SET_DIG_MASK)) |
SYSCON_ANA_CTRL1_VDD_PMU_SET_PDM(3U) | SYSCON_ANA_CTRL1_VDD_PMU_SET(3U) |
SYSCON_ANA_CTRL1_VDD_MEM_SET_PDM(3U) | SYSCON_ANA_CTRL1_VDD_MEM_SET(3U) |
SYSCON_ANA_CTRL1_VDD_PMU_SET_ULTRA_LOW(0U) | SYSCON_ANA_CTRL1_IV_VREG11_SET(2U) |
SYSCON_ANA_CTRL1_DVREG11_SET_DIG(2U);
/* config flash to be powered down during power down mode, this is reset value */
SYSCON->PMU_CTRL2 = SYSCON->PMU_CTRL2 | SYSCON_PMU_CTRL2_FLSH_PDM_DIS_MASK;
/* flatten RX sensitivity across 2402-2480M */
CALIB->RRF1 = (CALIB->RRF1 & ~(CALIB_RRF1_RRF_RX_INCAP1_MASK | CALIB_RRF1_RRF_LOAD_CAP_MASK)) |
CALIB_RRF1_RRF_RX_INCAP1(4U) | CALIB_RRF1_RRF_LOAD_CAP(6U);
/* Sub module clock setting:
* enable Data Path 16/8MHz clock(some of the flash operations need this, too)
* enable BiV clock include RTC BiV register */
SYSCON->CLK_EN = SYSCON_CLK_EN_CLK_DP_EN_MASK | SYSCON_CLK_EN_CLK_BIV_EN_MASK;
/* workaround for bootloader: set pin mux registers to reset value */
SYSCON->PIO_FUNC_CFG[1] = 0x0U;
SYSCON->PIO_FUNC_CFG[2] = 0x0U;
/* workaround for bootloader: bootloader may enable these submodules */
SYSCON->RST_SW_SET = SYSCON_RST_SW_SET_SET_FC0_RST_MASK | SYSCON_RST_SW_SET_SET_FC3_RST_MASK;
SYSCON->RST_SW_CLR = SYSCON_RST_SW_CLR_CLR_FC0_RST_MASK | SYSCON_RST_SW_CLR_CLR_FC3_RST_MASK;
SYSCON->CLK_DIS = SYSCON_CLK_DIS_CLK_FC0_DIS_MASK | SYSCON_CLK_DIS_CLK_FC3_DIS_MASK;
#if defined(CFG_QN908XA)
/* Remove pullup from USB pins */
SYSCON->PIO_PULL_CFG[1] =
SYSCON->PIO_PULL_CFG[1] & ~(SYSCON_PIO_PULL_CFG_PA26_PULL_MASK | SYSCON_PIO_PULL_CFG_PA27_PULL_MASK);
SYSCON->USB_CFG = ((1 << SYSCON_USB_CFG_DPPUEN_B_PHY_POL_SHIFT) | (0 << SYSCON_USB_CFG_DPPUEN_B_PHY_SEL_SHIFT) |
(0 << SYSCON_USB_CFG_USB_VBUS_SHIFT) | (1 << SYSCON_USB_CFG_USB_PHYSTDBY_SHIFT) |
(1 << SYSCON_USB_CFG_USB_PHYSTDBY_WEN_SHIFT));
#endif
/* use close loop mode by default */
CALIB->LO1 = (CALIB->LO1 | (CALIB_LO1_TX_PLLPFD_EN_MASK | CALIB_LO1_RX_PLLPFD_EN_MASK));
/* Wait for XTAL ready */
while (!(SYSCON->SYS_MODE_CTRL & SYSCON_SYS_MODE_CTRL_XTAL_RDY_MASK))
;
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate(void)
{
}
/// @} SYSTEM
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/examples/master402/canopen_callback.c
|
/*
This file is part of CanFestival, a library implementing CanOpen Stack.
Copyright (C): <NAME> and <NAME>
See COPYING file for copyrights details.
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <rtthread.h>
#include "canfestival.h"
#include "master402_od.h"
#include "canopen_callback.h"
#include "master402_canopen.h"
/*****************************************************************************/
void master402_heartbeatError(CO_Data* d, UNS8 heartbeatID)
{
rt_kprintf("heartbeatError %d\n", heartbeatID);
}
void master402_initialisation(CO_Data* d)
{
rt_kprintf("canfestival enter initialisation state\n");
}
void master402_preOperational(CO_Data* d)
{
rt_thread_t tid;
rt_kprintf("canfestival enter preOperational state\n");
tid = rt_thread_create("co_cfg", canopen_start_thread_entry, RT_NULL, 1024, 12, 2);
if(tid == RT_NULL)
{
rt_kprintf("canfestival config thread start failed!\n");
}
else
{
rt_thread_startup(tid);
}
}
void master402_operational(CO_Data* d)
{
rt_kprintf("canfestival enter operational state\n");
}
void master402_stopped(CO_Data* d)
{
rt_kprintf("canfestival enter stop state\n");
}
void master402_post_sync(CO_Data* d)
{
}
void master402_post_TPDO(CO_Data* d)
{
}
void master402_storeODSubIndex(CO_Data* d, UNS16 wIndex, UNS8 bSubindex)
{
/*TODO :
* - call getODEntry for index and subindex,
* - save content to file, database, flash, nvram, ...
*
* To ease flash organisation, index of variable to store
* can be established by scanning d->objdict[d->ObjdictSize]
* for variables to store.
*
* */
rt_kprintf("storeODSubIndex : %4.4x %2.2x\n", wIndex, bSubindex);
}
void master402_post_emcy(CO_Data* d, UNS8 nodeID, UNS16 errCode, UNS8 errReg, const UNS8 errSpec[5])
{
rt_kprintf("received EMCY message. Node: %2.2x ErrorCode: %4.4x ErrorRegister: %2.2x\n", nodeID, errCode, errReg);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/bsp/lpc546xx/drv_usbd_cdc.c
|
#include <rtthread.h>
#include "common.h"
#include "usbd.h"
#include "usbd_cdc.h"
#define CDC_NAME "usbd_cdc"
#define CDC_BUF_SIZE (64)
struct bsp_drv_cdc_device
{
struct rt_device rtdev;
rt_mutex_t lock;
rt_sem_t tx_sem;
rt_mq_t rx_mq;
uint8_t is_line_active;
};
/* device need to implment host's config */
static uint32_t set_line_coding(struct ucdc_line_coding *line_coding)
{
// USBD_TRACE("set line coding:%d\r\n", line_coding->dwDTERate);
return 0;
}
static uint32_t cdc_send_notify(void)
{
struct bsp_drv_cdc_device *cdc_dev = (struct bsp_drv_cdc_device *)rt_device_find(CDC_NAME);
rt_sem_release(cdc_dev->tx_sem);
return 0;
}
static uint32_t cdc_recv_handler(uint8_t *buf, uint32_t len)
{
struct bsp_drv_cdc_device *cdc_dev = (struct bsp_drv_cdc_device *)rt_device_find(CDC_NAME);
if(cdc_dev)
{
for(int i=0; i<len; i++)
{
rt_mq_send(cdc_dev->rx_mq, &buf[i], 1);
}
if(cdc_dev->rtdev.rx_indicate)
{
cdc_dev->rtdev.rx_indicate((rt_device_t)cdc_dev, len);
}
}
return 0;
}
/* host need device's line_coding config */
static uint32_t get_line_coding(struct ucdc_line_coding *line_coding)
{
line_coding->dwDTERate = 115200;
line_coding->bCharFormat = 2;
// USBD_TRACE("get_line_coding, baud:%d\r\n", line_coding->dwDTERate);
return 0;
}
static uint32_t set_control_line_serial_state(uint8_t val)
{
struct bsp_drv_cdc_device *cdc_dev = (struct bsp_drv_cdc_device *)rt_device_find(CDC_NAME);
/* 0:off, 1 on */
cdc_dev->is_line_active = val;
return 0;
}
static struct usbd_cdc_callback_t cdc_cb =
{
get_line_coding,
set_line_coding,
set_control_line_serial_state,
cdc_recv_handler,
cdc_send_notify,
};
static void _lock(struct bsp_drv_cdc_device * dev)
{
rt_mutex_take(dev->lock, RT_WAITING_FOREVER);
}
static void _unlock(struct bsp_drv_cdc_device * dev)
{
rt_mutex_release(dev->lock);
}
static rt_err_t cdc_init (rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t cdc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
int i;
struct bsp_drv_cdc_device * cdc_dev;
cdc_dev = (struct bsp_drv_cdc_device*)dev;
_lock(cdc_dev);
cdc_dev = (struct bsp_drv_cdc_device*)dev;
uint8_t *p = buffer;
for(i=0; i<size; i++)
{
if(rt_mq_recv(cdc_dev->rx_mq, &p[i], 1, 0) != RT_EOK)
{
_unlock(cdc_dev);
return i;
}
}
_unlock(cdc_dev);
return size;
}
static rt_size_t cdc_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
struct bsp_drv_cdc_device *cdc_dev = (struct bsp_drv_cdc_device*)dev;
_lock(cdc_dev);
uint8_t *p = (uint8_t*)buffer;
if(cdc_dev->is_line_active == 1)
{
while(size--)
{
if (*p == '\n' && (dev->open_flag & RT_DEVICE_FLAG_STREAM))
{
uint8_t r = '\r';
if(rt_sem_take(cdc_dev->tx_sem, 1) == RT_EOK)
{
usbd_cdc_send(&r, 1);
}
}
if(rt_sem_take(cdc_dev->tx_sem, 1) == RT_EOK)
{
usbd_cdc_send(p, 1);
}
p++;
}
}
_unlock(cdc_dev);
return size;
}
static rt_err_t cdc_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t cdc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
return RT_EOK;
}
int rt_hw_usbd_cdc_init(const char *name)
{
struct bsp_drv_cdc_device *cdc_dev;
/* already registiered */
if(rt_device_find(name))
{
return -RT_EIO;
}
cdc_dev = rt_malloc(sizeof(struct bsp_drv_cdc_device));
cdc_dev->rtdev.type = RT_Device_Class_Char;
cdc_dev->rtdev.rx_indicate = RT_NULL;
cdc_dev->rtdev.tx_complete = RT_NULL;
cdc_dev->rtdev.init = cdc_init;
cdc_dev->rtdev.open = cdc_open;
cdc_dev->rtdev.close = RT_NULL;
cdc_dev->rtdev.read = cdc_read;
cdc_dev->rtdev.write = cdc_write;
cdc_dev->rtdev.control = cdc_control;
cdc_dev->rtdev.user_data = RT_NULL;
cdc_dev->lock = rt_mutex_create(name, RT_IPC_FLAG_FIFO);
cdc_dev->tx_sem = rt_sem_create(name, 1, RT_IPC_FLAG_FIFO);
cdc_dev->rx_mq = rt_mq_create(name, 1, CDC_BUF_SIZE, RT_IPC_FLAG_FIFO);
usbd_cdc_set_cb(&cdc_cb);
rt_device_register(&cdc_dev->rtdev, name, RT_DEVICE_FLAG_RDWR);
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/inc/usbd_digi_serial.h
|
#ifndef __USBD_DIGI_SERIAL_H_
#define __USBD_DIGI_SERIAL_H_
#include <stdint.h>
#include <usbd.h>
#include <usb_common.h>
void usbd_vsc_digi_serial_init(struct usbd_t *h);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/examples/master402/master402_canopen.h
|
#ifndef __AGV_CANOPEN_H__
#define __AGV_CANOPEN_H__
#define CONTROLLER_NODEID 1
#define SERVO_NODEID 2
#define PDO_TRANSMISSION_TYPE 1
extern CO_Data *OD_Data;
void canopen_start_thread_entry(void *parameter);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/spifi.h
|
/**
******************************************************************************
* @file spifi.h
* @author YANDLD
* @version V3.0.0
* @date 2016.05.31
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_SPIFI_H__
#define __CH_LIB_SPIFI_H__
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/*! @brief SPIFI data direction */
typedef enum _spifi_data_direction
{
kSPIFI_DataInput = 0x0U, /*!< Data input from serial flash. */
kSPIFI_DataOutput = 0x1U /*!< Data output to serial flash. */
} spifi_data_direction_t;
/*! @brief SPIFI command opcode format */
typedef enum _spifi_command_format
{
kSPIFI_CommandAllSerial = 0x0, /*!< All fields of command are serial. */
kSPIFI_CommandDataQuad = 0x1U, /*!< Only data field is dual/quad, others are serial. */
kSPIFI_CommandOpcodeSerial = 0x2U, /*!< Only opcode field is serial, others are quad/dual. */
kSPIFI_CommandAllQuad = 0x3U /*!< All fields of command are dual/quad mode. */
} spifi_command_format_t;
/*! @brief SPIFI command type */
typedef enum _spifi_command_type
{
kSPIFI_CommandOpcodeOnly = 0x1U, /*!< Command only have opcode, no address field */
kSPIFI_CommandOpcodeAddrOneByte = 0x2U, /*!< Command have opcode and also one byte address field */
kSPIFI_CommandOpcodeAddrTwoBytes = 0x3U, /*!< Command have opcode and also two bytes address field */
kSPIFI_CommandOpcodeAddrThreeBytes = 0x4U, /*!< Command have opcode and also three bytes address field. */
kSPIFI_CommandOpcodeAddrFourBytes = 0x5U, /*!< Command have opcode and also four bytes address field */
kSPIFI_CommandNoOpcodeAddrThreeBytes = 0x6U, /*!< Command have no opcode and three bytes address field */
kSPIFI_CommandNoOpcodeAddrFourBytes = 0x7U /*!< Command have no opcode and four bytes address field */
} spifi_command_type_t;
/*! @brief SPIFI command structure */
typedef struct
{
uint16_t dataLen; /*!< How many data bytes are needed in this command. */
spifi_data_direction_t direction; /*!< Data direction of this command. */
uint8_t intermediateBytes; /*!< How many intermediate bytes needed */
spifi_command_format_t format; /*!< Command format */
spifi_command_type_t type; /*!< Command type */
uint8_t opcode; /*!< Command opcode value */
} spifi_command_t;
typedef struct
{
spifi_command_t *cmd;
uint32_t sector_size;
uint32_t page_size;
}qspi_flash_t;
void SPIFI_Init(uint32_t baud);
void SPIFI_SetCmd(spifi_command_t *cmd);
void SPIFI_SetMemoryCmd(spifi_command_t *cmd);
void SPIFI_Reset(void);
#define QSPI_CMD_READ_IDX (0)
#define QSPI_PROGRAM_PAGE_IDX (1)
#define QSPI_GET_STATUS_IDX (2)
#define QSPI_ERASE_SECTOR_IDX (3)
#define QSPI_WRITE_ENABLE_IDX (4)
#define QSPI_WRITE_REGISTER_IDX (5)
#define QSPI_READ_ID_IDX (6)
void QSPI_Init(qspi_flash_t * ctx, uint32_t freq);
uint32_t QSPI_GetDeviceID(qspi_flash_t *ctx);
uint32_t QSPI_WriteSector(qspi_flash_t *ctx, uint32_t addr, uint8_t *buf);
uint32_t QSPI_EraseSector(qspi_flash_t *ctx, uint32_t addr);
uint32_t QSPI_SectorTest(qspi_flash_t *ctx, uint32_t addr, uint8_t *buf);
uint32_t QSPI_WaitFinish(qspi_flash_t *ctx);
uint32_t qspi_flash_test(qspi_flash_t *ctx, uint8_t *test_buf, uint32_t addr, uint32_t len);
void QSPI_Read(qspi_flash_t *ctx, uint32_t addr, uint8_t *buf, uint32_t len);
uint32_t QSPI_WritePage(qspi_flash_t *ctx, uint32_t addr, uint8_t *buf);
void QSPI_SetReadMode(qspi_flash_t *ctx);
#ifdef __cplusplus
}
#endif
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/dma.h
|
/**
******************************************************************************
* @file dma.h
* @author YANDLD
* @version V3.0.0
* @date 2016.05.31
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_DMA_H__
#define __CH_LIB_DMA_H__
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
#define MAX_DMA_CHANNEL (DMA_CHANNEL_XFERCFG_COUNT)
typedef enum {
DMA_CH0, /* DMA Request for channel 0 */
DMA_CH1, /* DMA Request for channel 1 */
DMA_CH2, /* DMA Request for channel 2 */
DMA_CH3, /* DMA Request for channel 3 */
DMA_CH4, /* DMA Request for channel 4 */
DMA_CH5, /* DMA Request for channel 5 */
DMA_CH6, /* DMA Request for channel 6 */
DMA_CH7, /* DMA Request for channel 7 */
DMA_CH8, /* DMA Request for channel 8 */
DMA_CH9, /* DMA Request for channel 9 */
DMA_CH10, /* DMA Request for channel 10 */
DMA_CH11, /* DMA Request for channel 11 */
DMA_CH12, /* DMA Request for channel 12 */
DMA_CH13, /* DMA Request for channel 13 */
DMA_CH14, /* DMA Request for channel 14 */
DMA_CH15, /* DMA Request for channel 15 */
DMA_CH16, /* DMA Request for channel 16 */
DMA_CH17, /* DMA Request for channel 17 */
DMA_CH18, /* DMA Request for channel 18 */
DMA_CH19, /* DMA Request for channel 19 */
/* Alias DMAREQ defines */
DMAREQ_FLEXCOMM0_RX = DMA_CH0, /* DMA Request for flexcomm 0 RX */
DMAREQ_FLEXCOMM0_TX, /* DMA Request for flexcomm 0 TX */
DMAREQ_FLEXCOMM1_RX, /* DMA Request for flexcomm 1 RX */
DMAREQ_FLEXCOMM1_TX, /* DMA Request for flexcomm 1 TX */
DMAREQ_FLEXCOMM2_RX, /* DMA Request for flexcomm 2 RX */
DMAREQ_FLEXCOMM2_TX, /* DMA Request for flexcomm 2 TX */
DMAREQ_FLEXCOMM3_RX, /* DMA Request for flexcomm 3 RX */
DMAREQ_FLEXCOMM3_TX, /* DMA Request for flexcomm 3 TX */
DMAREQ_FLEXCOMM4_RX, /* DMA Request for flexcomm 4 RX */
DMAREQ_FLEXCOMM4_TX, /* DMA Request for flexcomm 4 TX */
DMAREQ_FLEXCOMM5_RX, /* DMA Request for flexcomm 5 RX */
DMAREQ_FLEXCOMM5_TX, /* DMA Request for flexcomm 5 TX */
DMAREQ_FLEXCOMM6_RX, /* DMA Request for flexcomm 6 RX */
DMAREQ_FLEXCOMM6_TX, /* DMA Request for flexcomm 6 TX */
DMAREQ_FLEXCOMM7_RX, /* DMA Request for flexcomm 7 RX */
DMAREQ_FLEXCOMM7_TX, /* DMA Request for flexcomm 7 TX */
DMAREQ_DMIC0, /* DMA Request for Digital MIC-0 */
DMAREQ_DMIC1, /* DMA Request for Digital MIC-1 */
DMAREQ_SPIFI, /* DMA Request for SPIFI controller */
DMAREQ_SHA,
DMAREQ_FLEXCOMM8_RX,
DMAREQ_FLEXCOMM8_TX,
DMAREQ_FLEXCOMM9_RX,
DMAREQ_FLEXCOMM9_TX,
}DMA_Chl_t;
/* DMA channel source/address/next descriptor */
typedef struct
{
uint32_t xfercfg; /*!< Transfer configuration (only used in linked lists and ping-pong configs) */
uint32_t src; /*!< DMA transfer source end address */
uint32_t dest; /*!< DMA transfer desintation end address */
uint32_t next; /*!< Link to next DMA descriptor, must be 16 byte aligned */
} DMA_Desc_t;
typedef struct
{
uint8_t chl;
bool isPeriph;
uint16_t transferCnt; /* numbers of one transfer */
uint16_t dataWidth; /* 1,2 or 4 unit in byte */
uint16_t sAddrInc; /* 0:no increasment, 1: 1 x width, 2: 2 x width, 3: 4 x width */
uint32_t sAddr;
uint16_t dAddrInc;
uint32_t dAddr;
}DMA_ChlSetup_t;
void DMA_Init(void);
void DMA_SetChlIntMode(uint32_t chl, bool val);
void DMA_SWTrigger(uint32_t chl);
void DMA_SetupChl(DMA_ChlSetup_t *setup);
uint32_t DMA_GetTransferCnt(uint8_t chl);
void DMA_SetChlLink(uint8_t chl, DMA_Desc_t *list);
void DMA_CopyDesc(uint8_t ch, DMA_Desc_t *desc);
DMA_Desc_t *DMA_GetDesc(uint8_t ch);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/lcdc.c
|
<filename>mcu_source/Libraries/drivers_lpc/src/lcdc.c
/**
******************************************************************************
* @file lcdc.c
* @author YANDLD
* @version V3.0.0
* @date 2015.6.21
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "common.h"
#include "lcdc.h"
#if defined(LCD)
/*!@brief How many hardware cursors supports. */
#define LCDC_CURSOR_COUNT 4
/*!@brief LCD cursor image bits per pixel. */
#define LCDC_CURSOR_IMG_BPP 2
/*!@brief LCD 32x32 cursor image size in word(32-bit). */
#define LCDC_CURSOR_IMG_32X32_WORDS (32 * 32 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t)))
/*!@brief LCD 64x64 cursor image size in word(32-bit). */
#define LCDC_CURSOR_IMG_64X64_WORDS (64 * 64 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t)))
/*!@brief LCD palette size in words(32-bit). */
#define LCDC_PALETTE_SIZE_WORDS (ARRAY_SIZE(((LCD_Type *)0)->PAL))
static ALIGN(4) const uint8_t CursorDefault32Img0[] = {
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 1. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 2. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 3. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 4. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 5. */
0xAA, 0xAA, 0xAA, 0xFA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 6. */
0xAA, 0xAA, 0xAB, 0xFE, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 7. */
0xAA, 0xAA, 0xAB, 0xFE, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 8. */
0xAA, 0xAA, 0xAB, 0xFE, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 9. */
0xAA, 0xAA, 0xAB, 0xFE, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 10 */
0xAA, 0xAA, 0xAB, 0xFF, 0xEA,
0xAA, 0xAA, 0xAA, /* Line 11. */
0xAA, 0xAA, 0xAB, 0xFF, 0xFF,
0xAA, 0xAA, 0xAA, /* Line 12. */
0xAA, 0xAA, 0xAB, 0xFF, 0xFF,
0xFA, 0xAA, 0xAA, /* Line 13. */
0xAA, 0xAA, 0xAB, 0xFF, 0xFF,
0xFE, 0xAA, 0xAA, /* Line 14. */
0xAA, 0xAB, 0xFB, 0xFF, 0xFF,
0xFF, 0xAA, 0xAA, /* Line 15. */
0xAA, 0xAB, 0xFF, 0xFF, 0xFF,
0xFF, 0xAA, 0xAA, /* Line 16. */
0xAA, 0xAB, 0xFF, 0xFF, 0xFF,
0xFF, 0xAA, 0xAA, /* Line 17. */
0xAA, 0xAA, 0xFF, 0xFF, 0xFF,
0xFF, 0xAA, 0xAA, /* Line 18. */
0xAA, 0xAA, 0xBF, 0xFF, 0xFF,
0xFF, 0xAA, 0xAA, /* Line 19. */
0xAA, 0xAA, 0xBF, 0xFF, 0xFF,
0xFF, 0xAA, 0xAA, /* Line 20. */
0xAA, 0xAA, 0xAF, 0xFF, 0xFF,
0xFF, 0xAA, 0xAA, /* Line 21. */
0xAA, 0xAA, 0xAF, 0xFF, 0xFF,
0xFE, 0xAA, 0xAA, /* Line 22. */
0xAA, 0xAA, 0xAB, 0xFF, 0xFF,
0xFE, 0xAA, 0xAA, /* Line 23. */
0xAA, 0xAA, 0xAB, 0xFF, 0xFF,
0xFE, 0xAA, 0xAA, /* Line 24. */
0xAA, 0xAA, 0xAA, 0xFF, 0xFF,
0xFA, 0xAA, 0xAA, /* Line 25. */
0xAA, 0xAA, 0xAA, 0xFF, 0xFF,
0xFA, 0xAA, 0xAA, /* Line 26. */
0xAA, 0xAA, 0xAA, 0xFF, 0xFF,
0xFA, 0xAA, 0xAA, /* Line 27. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 28. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 29. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 30. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, /* Line 31. */
0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA /* Line 32. */
};
void LCDC_SetIntMode(bool val)
{
LCD->INTMSK = LCD_INTMSK_LNBUIM_MASK;
NVIC_EnableIRQ(LCD_IRQn);
}
void LCDC_GetDefaultConfig(LCDC_Config_t *config)
{
config->ppl = 0U;
config->hsw = 0U;
config->hfp = 0U;
config->hbp = 0U;
config->lpp = 0U;
config->vsw = 0U;
config->vfp = 0U;
config->vbp = 0U;
config->acBiasFreq = 1U;
config->polarityFlags = 0U;
config->enableLineEnd = false;
config->lineEndDelay = 0U;
config->upperPanelAddr = 0U;
config->lowerPanelAddr = 0U;
config->bpp = kLCDC_16BPP565;
config->dataFormat = kLCDC_LittleEndian;
config->swapRedBlue = true;
config->fps = 50;
}
void LCDC_Init(LCDC_Config_t *config)
{
int i;
uint32_t reg, pixel_clk;
SYSCON->AHBCLKCTRL[2] |= SYSCON_AHBCLKCTRL_LCD_MASK;
/*
0x0 Main clock (main_clk).
0x1 LCD external clock input (LCD_CLKIN).
0x2 FRO 96 or 48 MHz (fro_hf).
0x3 None, this may be selected to reduce power when no output is needed.
*/
/* main clock */
SYSCON->LCDCLKSEL = SYSCON_LCDCLKSEL_SEL(0);
pixel_clk = config->fps * (config->hbp + config->hfp + config->ppl) * (config->vbp + config->vfp + config->lpp);
LIB_TRACE("width:%d heigt:%d\r\n", config->ppl, config->lpp);
LIB_TRACE("pixel clk need:%dKHz\r\n", pixel_clk/1000);
LIB_TRACE("lcd: %dx%d\r\n", config->ppl, config->lpp);
/* load a defualt value */
SYSCON->LCDCLKDIV = SYSCON_LCDCLKDIV_DIV_MASK;
for(i=0; i<256; i++)
{
if((ABS((int)GetClock(kCoreClock) / i) - (int)pixel_clk) < (pixel_clk / 10)) /* if reach 10% of accuricy */
{
LIB_TRACE("lcd clock divider found:%d\r\n", i);
SYSCON->LCDCLKDIV = SYSCON_LCDCLKDIV_DIV(i - 1);
break;
}
}
/* Set register CTRL. */
reg = (LCD_CTRL_LCDVCOMP(3) | LCD_CTRL_WATERMARK_MASK);
reg |= (uint32_t)(config->dataFormat) | LCD_CTRL_LCDTFT_MASK | LCD_CTRL_LCDBPP(config->bpp);
if (config->swapRedBlue)
{
reg |= LCD_CTRL_BGR_MASK;
}
/* Configure timing. */
LCD->TIMH = LCD_TIMH_PPL((config->ppl / 16U) - 1U) | LCD_TIMH_HSW(config->hsw - 1U) | LCD_TIMH_HFP(config->hfp - 1U) | LCD_TIMH_HBP(config->hbp - 1U);
LCD->TIMV = LCD_TIMV_LPP(config->lpp - 1U) | LCD_TIMV_VSW(config->vsw - 1U) | LCD_TIMV_VFP(config->vfp - 1U) | LCD_TIMV_VBP(config->vbp - 1U);
LCD->POL = (uint32_t)(config->polarityFlags) | LCD_POL_ACB(config->acBiasFreq - 1U) | LCD_POL_BCD_MASK | LCD_POL_CPL(config->ppl - 1U);
/* Line end configuration. */
if (config->enableLineEnd)
{
LCD->LE = LCD_LE_LED(config->lineEndDelay - 1U) | LCD_LE_LEE_MASK;
}
else
{
LCD->LE = 0U;
}
/* Set panel frame base address. */
LCD->UPBASE = config->upperPanelAddr;
LCD->LPBASE = config->lowerPanelAddr;
LCD->CTRL = reg | LCD_CTRL_LCDPWR_MASK | LCD_CTRL_LCDEN_MASK;
}
void LCDC_CursorSetImage(LCD_Type *base, uint8_t index, const uint32_t *image)
{
uint32_t regStart;
uint32_t i;
uint32_t len;
regStart = index * LCDC_CURSOR_IMG_32X32_WORDS;
len = LCDC_CURSOR_IMG_32X32_WORDS;
for (i = 0U; i < len; i++)
{
base->CRSR_IMG[regStart + i] = image[i];
}
}
void LCDC_CursorInit(void)
{
/* size = 32x32, */
LCD->CRSR_CFG = LCD_CRSR_CFG_CRSRSIZE(0) | LCD_CRSR_CFG_FRAMESYNC_MASK;
/* Set position. */
LCDC_CursorSetPos(0, 0);
/* Palette. */
//LCD->CRSR_PAL0 = ((uint32_t)config->palette0.red << LCD_CRSR_PAL0_RED_SHIFT) | ((uint32_t)config->palette0.blue << LCD_CRSR_PAL0_BLUE_SHIFT) | ((uint32_t)config->palette0.green << LCD_CRSR_PAL0_GREEN_SHIFT);
//LCD->CRSR_PAL1 = ((uint32_t)config->palette1.red << LCD_CRSR_PAL1_RED_SHIFT) | ((uint32_t)config->palette1.blue << LCD_CRSR_PAL1_BLUE_SHIFT) | ((uint32_t)config->palette1.green << LCD_CRSR_PAL1_GREEN_SHIFT);s
LCDC_CursorSetImage(LCD, 0, (const uint32_t *)CursorDefault32Img0);
/* select image 0 */
LCD->CRSR_CTRL = LCD_CRSR_CTRL_CRSRNUM1_0(0);
LCDC_CursorShow(true);
}
void LCDC_CursorSetPos(int32_t x, int32_t y)
{
//LCD->CRSR_CLIP = LCD_CRSR_CLIP_CRSRCLIPX(32/2) | LCD_CRSR_CLIP_CRSRCLIPY(32/2);
LCD->CRSR_XY = LCD_CRSR_XY_CRSRX(x) | LCD_CRSR_XY_CRSRY(y);
}
void LCDC_CursorSelectImage(uint8_t index)
{
LCD->CRSR_CTRL = (LCD->CRSR_CTRL & ~LCD_CRSR_CTRL_CRSRNUM1_0_MASK) | LCD_CRSR_CTRL_CRSRNUM1_0(index);
}
void LCDC_CursorShow(bool val)
{
(val)?(LCD->CRSR_CTRL |= LCD_CRSR_CTRL_CRSRON_MASK):(LCD->CRSR_CTRL &= ~LCD_CRSR_CTRL_CRSRON_MASK);
}
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/ctimer.h
|
<filename>mcu_source/Libraries/drivers_lpc/inc/ctimer.h
/**
******************************************************************************
* @file ctimer.h
* @author YANDLD
* @version V3.0.0
* @date 2016.05.31
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_CTIMER_H__
#define __CH_LIB_CTIMER_H__
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
#define HW_CTIMER0 (0)
#define HW_CTIMER1 (1)
#define HW_CTIMER2 (2)
#define HW_CTIMER3 (3)
#define HW_CTIMER_CH0 (0)
#define HW_CTIMER_CH1 (1)
#define HW_CTIMER_CH2 (2)
#define HW_CTIMER_CH3 (3)
#define HW_CTIMER_CAP_INT_EVT_RE (0)
#define HW_CTIMER_CAP_INT_EVT_FE (1)
#define HW_CTIMER_CAP_INT_EVT_ALL (2)
/* using CTIMER as a normal timer */
void CTIMER_TC_Init(uint32_t instance, uint32_t us);
void CTIMER_TC_SetIntMode(uint32_t instance, uint32_t chl, bool val);
void CTIMER_SetCounter(uint32_t instance, uint32_t val);
uint32_t CTIMER_GetCounter(uint32_t instance);
void CTIMER_Stop(uint32_t instance);
void CTIMER_Start(uint32_t instance);
/* using CTIMER as a PWM */
void CTIMER_PWM_Init(uint32_t instance, uint32_t pwm_chl, uint32_t freq);
void CTIMER_PWM_SetDuty(uint32_t instance, uint32_t pwm_chl, uint32_t duty);
/* CTIMER_CAP API */
void CTIMER_CAP_Init(uint32_t instance, uint32_t chl);
void CIMER_CAP_SetITandLoadMode(uint32_t instance, uint32_t chl, uint32_t mode);
void CTIMER_CAP_SetIntMode(uint32_t instance, uint32_t chl, bool val);
uint32_t CTIMER_GetCAPCounter(uint32_t instance, uint32_t chl);
void CTIMER_SetTimerClearEvt(uint32_t instance, uint32_t chl, uint32_t mode, bool val);
#endif
|
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