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yandld/lpc_uart_server
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mcu_source/Libraries/startup/src/system_MK02F12810.c
|
/*
** ###################################################################
** Processors: MK02FN128VFM10
** MK02FN64VFM10
** MK02FN128VLF10
** MK02FN64VLF10
** MK02FN128VLH10
** MK02FN64VLH10
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K02P64M100SFARM, Rev. 0, February 14, 2014
** Version: rev. 0.1, 2014-02-24
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2014 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 0.1 (2014-02-24)
** Initial version
**
** ###################################################################
*/
/*!
* @file MK02F12810
* @version 0.1
* @date 2014-02-24
* @brief Device specific configuration file for MK02F12810 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MK02F12810.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if (DISABLE_WDOG)
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG->STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
#endif /* (DISABLE_WDOG) */
//#if (CLOCK_SETUP == 0)
// /* SMC_PMPROT: AHSRUN=1,??=0,AVLP=1,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
// SMC_PMPROT = (SMC_PMPROT_AHSRUN_MASK | SMC_PMPROT_AVLP_MASK); /* Setup Power mode protection register */
// /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
// SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
// SIM_CLKDIV1_OUTDIV2(0x00) |
// SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
// /* SIM_SOPT2: PLLFLLSEL&=~1 */
// SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL(0x01)); /* Select FLL as a clock source for various peripherals */
// /* SIM_SOPT1: OSC32KSEL=3 */
// SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
// /* SIM_SCGC5: PORTA=1 */
// SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
// /* PORTA_PCR18: ISF=0,MUX=0 */
// PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
// /* PORTA_PCR19: ISF=0,MUX=0 */
// PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
// /* Switch to FEI Mode */
// /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
// MCG_C1 = MCG_C1_CLKS(0x00) |
// MCG_C1_FRDIV(0x00) |
// MCG_C1_IREFS_MASK |
// MCG_C1_IRCLKEN_MASK;
// /* MCG_C2: LOCRE0=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
// MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
// MCG_C2_LOCRE0_MASK |
// MCG_C2_RANGE(0x01) |
// MCG_C2_HGO_MASK |
// MCG_C2_LP_MASK |
// MCG_C2_IRCS_MASK
// )) | (uint8_t)(
// MCG_C2_RANGE(0x02) |
// MCG_C2_EREFS_MASK
// ));
// /* MCG_C4: DMX32=0,DRST_DRS=0 */
// MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
// /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
// OSC_CR = OSC_CR_ERCLKEN_MASK;
// /* MCG_C7: OSCSEL=0 */
// MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL(0x03));
// while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
// }
// while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
// }
//#elif (CLOCK_SETUP == 1)
// /* SMC_PMPROT: AHSRUN=1,??=0,AVLP=1,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
// SMC_PMPROT = (SMC_PMPROT_AHSRUN_MASK | SMC_PMPROT_AVLP_MASK); /* Setup Power mode protection register */
// /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
// SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
// SIM_CLKDIV1_OUTDIV2(0x01) |
// SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */
// /* SIM_SOPT2: PLLFLLSEL&=~1 */
// SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL(0x01)); /* Select FLL as a clock source for various peripherals */
// /* SIM_SOPT1: OSC32KSEL=3 */
// SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
// /* SIM_SCGC5: PORTA=1 */
// SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
// /* PORTA_PCR18: ISF=0,MUX=0 */
// PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
// /* PORTA_PCR19: ISF=0,MUX=0 */
// PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
// /* Switch to FEI Mode */
// /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
// MCG_C1 = MCG_C1_CLKS(0x00) |
// MCG_C1_FRDIV(0x00) |
// MCG_C1_IREFS_MASK |
// MCG_C1_IRCLKEN_MASK;
// /* MCG_C2: LOCRE0=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
// MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
// MCG_C2_LOCRE0_MASK |
// MCG_C2_RANGE(0x01) |
// MCG_C2_HGO_MASK |
// MCG_C2_LP_MASK |
// MCG_C2_IRCS_MASK
// )) | (uint8_t)(
// MCG_C2_RANGE(0x02) |
// MCG_C2_EREFS_MASK
// ));
// /* MCG_C4: DMX32=0,DRST_DRS=0 */
// MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
// /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
// OSC_CR = OSC_CR_ERCLKEN_MASK;
// /* MCG_C7: OSCSEL=0 */
// MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL(0x03));
// while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
// }
// while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
// }
//#elif (CLOCK_SETUP == 2)
// /* SMC_PMPROT: AHSRUN=1,??=0,AVLP=1,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
// SMC_PMPROT = (SMC_PMPROT_AHSRUN_MASK | SMC_PMPROT_AVLP_MASK); /* Setup Power mode protection register */
// /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,??=0,??=0,??=0,??=0,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
// SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
// SIM_CLKDIV1_OUTDIV2(0x00) |
// SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
// /* SIM_SOPT2: PLLFLLSEL|=1 */
// SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */
// /* SIM_SOPT1: OSC32KSEL=3 */
// SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
// /* SIM_SCGC5: PORTA=1 */
// SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
// /* PORTA_PCR18: ISF=0,MUX=0 */
// PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
// /* PORTA_PCR19: ISF=0,MUX=0 */
// PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
// /* Switch to FEI Mode */
// /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
// MCG_C1 = MCG_C1_CLKS(0x00) |
// MCG_C1_FRDIV(0x00) |
// MCG_C1_IREFS_MASK |
// MCG_C1_IRCLKEN_MASK;
// /* MCG_C2: LOCRE0=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
// MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
// MCG_C2_LOCRE0_MASK |
// MCG_C2_RANGE(0x01) |
// MCG_C2_HGO_MASK |
// MCG_C2_LP_MASK |
// MCG_C2_IRCS_MASK
// )) | (uint8_t)(
// MCG_C2_RANGE(0x02) |
// MCG_C2_EREFS_MASK
// ));
// /* MCG_C4: DMX32=0,DRST_DRS=0 */
// MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
// /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
// OSC_CR = OSC_CR_ERCLKEN_MASK;
// /* MCG_C7: OSCSEL=0 */
// MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL(0x03));
// while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
// }
// while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
// }
//#elif (CLOCK_SETUP == 3)
// /* SMC_PMPROT: AHSRUN=1,??=0,AVLP=1,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
// SMC_PMPROT = (SMC_PMPROT_AHSRUN_MASK | SMC_PMPROT_AVLP_MASK); /* Setup Power mode protection register */
// /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,??=0,??=0,??=0,??=0,OUTDIV4=7,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
// SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x01) |
// SIM_CLKDIV1_OUTDIV2(0x01) |
// SIM_CLKDIV1_OUTDIV4(0x07); /* Update system prescalers */
// /* SIM_SOPT2: PLLFLLSEL|=1 */
// SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */
// /* SIM_SOPT1: OSC32KSEL=3 */
// SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
// /* SIM_SCGC5: PORTA=1 */
// SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
// /* PORTA_PCR18: ISF=0,MUX=0 */
// PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
// /* PORTA_PCR19: ISF=0,MUX=0 */
// PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
// /* Switch to FEI Mode */
// /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
// MCG_C1 = MCG_C1_CLKS(0x00) |
// MCG_C1_FRDIV(0x00) |
// MCG_C1_IREFS_MASK |
// MCG_C1_IRCLKEN_MASK;
// /* MCG_C2: LOCRE0=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
// MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
// MCG_C2_LOCRE0_MASK |
// MCG_C2_RANGE(0x01) |
// MCG_C2_HGO_MASK |
// MCG_C2_LP_MASK |
// MCG_C2_IRCS_MASK
// )) | (uint8_t)(
// MCG_C2_RANGE(0x02) |
// MCG_C2_EREFS_MASK
// ));
// /* MCG_C4: DMX32=0,DRST_DRS=0 */
// MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
// /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
// OSC_CR = OSC_CR_ERCLKEN_MASK;
// /* MCG_C7: OSCSEL=0 */
// MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL(0x03));
// while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
// }
// while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
// }
// #endif
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint16_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00u:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x02u:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
}
if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) {
switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
case MCG_C1_FRDIV(0x07):
Divider = 1536;
break;
case MCG_C1_FRDIV(0x06):
Divider = 1280;
break;
default:
Divider = (uint16_t)(32u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
}
} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) */
Divider = (uint16_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
}
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00u:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x02u:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
}
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/usbd_thread.c
|
#include <rtthread.h>
#include "common.h"
#include "usbd.h"
#include "usbd_cdc.h"
#include "usbd_cp210x.h"
#include "usbd_digi_serial.h"
rt_mq_t msd_mq;
static struct usbd_t usbd;
void USBD_Connect (bool con);
void USBD_Init (void);
//struct ucdc_line_coding coding;
typedef struct
{
uint8_t param;
void (*exec)(uint32_t param);
}msd_msg_t;
///* host need device's line_coding config */
//uint32_t get_line_coding(struct ucdc_line_coding *line_coding)
//{
// rt_memcpy(line_coding, &coding, sizeof(struct ucdc_line_coding));
// USBD_TRACE("get_line_coding, baud:%d\r\n", line_coding->dwDTERate);
// return CH_OK;
//}
///* device need to implment host's config */
//uint32_t set_line_coding(struct ucdc_line_coding *line_coding)
//{
// rt_memcpy(&coding, line_coding, sizeof(struct ucdc_line_coding));
// USBD_TRACE("set line coding:%d\r\n", line_coding->dwDTERate);
// return CH_OK;
//}
//uint32_t cdc_data_received(uint8_t *buf, uint32_t len)
//{
// int i;
// for(i=0; i<len; i++)
// {
// rt_kprintf("%c", buf[i]);
// }
// return CH_OK;
//}
//uint32_t set_control_line_serial_state(uint8_t val)
//{
// printf("set_control_line_serial_state %d\r\n", val);
// return CH_OK;
//}
//uint32_t send_notify(void)
//{
// return CH_OK;
//}
//struct usbd_cdc_callback_t cdc_cb =
//{
// get_line_coding,
// set_line_coding,
// set_control_line_serial_state,
// cdc_data_received,
// send_notify,
//};
void usbd_thread(void* parameter)
{
msd_msg_t msg;
msd_mq = rt_mq_create("mq", sizeof(msd_msg_t), 20, RT_IPC_FLAG_FIFO);
/* VBUS LPC54608 */
IOCON->PIO[0][22] = IOCON_PIO_FUNC(7) | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_MODE(0);
ch_usb_init(&usbd);
// usbd_cdc_set_cb(&cdc_cb);
//usbd_cdc_init(&usbd);
// usbd_vsc_cp210x_init(&usbd);
usbd_vsc_digi_serial_init(&usbd);
USBD_Init();
USBD_Connect(true);
while(1)
{
/* handling usbd sof event */
if(rt_mq_recv(msd_mq, &msg, sizeof(msd_msg_t), RT_WAITING_FOREVER) == RT_EOK)
{
usbd_data_ep_handler(msg.param/2, msg.param % 2);
}
}
}
void rt_usbd_init(void)
{
rt_thread_t tid = rt_thread_create("usbd", usbd_thread, RT_NULL, 1024, 13, 20);
rt_thread_startup(tid);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/src/rtt_canfestival.c
|
<gh_stars>1-10
#include <stdbool.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "canfestival.h"
#include "TaskSlave.h"
#include "timer.h"
#include "gpio.h"
#include "at32_can.h"
#include "chkv.h"
#include "app.h"
#include "common.h"
#include "at32_can.h"
static rt_mq_t cf_mq;
static rt_mutex_t cf_mutex;
#define RTT_CF_DEBUG 0
#if ( RTT_CF_DEBUG == 1 )
#include <stdio.h>
#define RTT_CF_TRACE printf
#else
#define RTT_CF_TRACE(...)
#endif
void _cf_enter_mutex(void)
{
rt_mutex_take(cf_mutex, RT_WAITING_FOREVER);
}
void _cf_exit_mutex(void)
{
rt_mutex_release(cf_mutex);
}
static void _reflash_data(void)
{
ACC[0] = sys.imu.cal_acc[0]*1000;
ACC[1] = sys.imu.cal_acc[1]*1000;
ACC[2] = sys.imu.cal_acc[2]*1000;
GYR[0] = sys.imu.cal_gyr2[0]*10;
GYR[1] = sys.imu.cal_gyr2[1]*10;
GYR[2] = sys.imu.cal_gyr2[2]*10;
EUL[0] = sys.att.eul[0]*100;
EUL[1] = sys.att.eul[1]*100;
EUL[2] = sys.att.eul[2]*100;
QUAT[0] = sys.att.q[0]*10000;
QUAT[1] = sys.att.q[1]*10000;
QUAT[2] = sys.att.q[2]*10000;
QUAT[3] = sys.att.q[3]*10000;
}
static void _dump_msg(char *str, Message *m)
{
int i;
RTT_CF_TRACE("%s id:0x%X, len:%d data:", str, m->cob_id, m->len);
for(i=0; i<m->len; i++)
{
RTT_CF_TRACE("0x%02X ", m->data[i]);
}
RTT_CF_TRACE("\r\n");
}
/* CF can operation interface */
unsigned char canSend(CAN_PORT notused, Message *m)
{
_reflash_data();
_dump_msg("send", m);
CAN_Send(HW_CAN1, m->cob_id, m->data, m->len);
return 0;
}
void canopen_recv_thread_entry(void* parameter)
{
Message msg;
while (1)
{
rt_mq_recv(cf_mq, &msg, sizeof(msg), RT_WAITING_FOREVER);
_dump_msg("rev", &msg);
_cf_enter_mutex();
canDispatch(&TaskSlave_Data, &msg);
_cf_exit_mutex();
/* saveing the key param */
if(NodeID != sys.can_intf.node_id || CAN_BAUD != sys.can_intf.can_baud)
{
sys.can_intf.node_id = NodeID;
sys.can_intf.can_baud = CAN_BAUD;
chkv_write_kv("INF_CAN", (uint8_t*)&sys.can_intf, sizeof(hi_can_intf_t));
chkv_save();
}
}
}
/* CF timer interface: timer need increase every 10 us */
static rt_uint32_t timer_val;
static rt_uint32_t cur_time;
void setTimer(TIMEVAL value)
{
value /= 100;
cur_time = 0;
timer_val = value;
// RTT_CF_TRACE("stimer val:%d\r\n", value);
}
TIMEVAL getElapsedTime(void)
{
return cur_time*100;
}
static void cf_timer_cb(void* parameter)
{
cur_time++;
if(cur_time >= timer_val)
{
_cf_enter_mutex();
TimeDispatch();
_cf_exit_mutex();
cur_time = 0;
}
}
void canopen_system_init(void)
{
rt_thread_t tid;
NodeID = sys.can_intf.node_id;
CAN_BAUD = sys.can_intf.can_baud;
/* CAN */
SetPinMux(HW_GPIOA, 12, 0, 2, 3); /* CAN_TX */
SetPinMux(HW_GPIOA, 11, 0, 2, 0); /* CAN_RX */
CAN_Init(HW_CAN1, CAN_BAUD);
CAN_SetIntMode(HW_CAN1, kCAN_IntRx_FIFO1, 1);
/* let this node id pass */
CAN_SetFilterMaskMode(HW_CAN1, HW_CAN_RX_FT0, NodeID, 0x7F, HW_CAN_RX_FIFO1);
/* let boardcast not id pass */
CAN_SetFilterMaskMode(HW_CAN1, HW_CAN_RX_FT1, 0x00, 0x7F, HW_CAN_RX_FIFO1);
cf_mq = rt_mq_create("cf_mq", sizeof(Message), 4, RT_IPC_FLAG_FIFO);
cf_mutex = rt_mutex_create("cf_mtx", RT_IPC_FLAG_FIFO);
rt_timer_start(rt_timer_create("cf_timer", cf_timer_cb, RT_NULL, rt_tick_from_millisecond(1), RT_TIMER_FLAG_PERIODIC));
tid = rt_thread_create("cf_rev", canopen_recv_thread_entry, RT_NULL, 1024, 28, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
setNodeId(&TaskSlave_Data, NodeID);
setState(&TaskSlave_Data, Initialisation);
setState(&TaskSlave_Data, Pre_operational);
}
void CAN1_RX1_IRQHandler(void)
{
rt_interrupt_enter();
static Message m;
uint8_t isRemote;
uint32_t id;
/* rx fifo fill */
if(CAN1->RF1 & CAN_RF1_RFFU1)
{
CAN1->RF1 = CAN_RF1_RFFU1;
}
/* rx fifo overflow */
if(CAN1->RF1 & CAN_RF1_RFOV1)
{
CAN1->RF1 = CAN_RF1_RFOV1;
}
CAN_Receive(HW_CAN1, HW_CAN_RX_FIFO1, &id, m.data, &m.len, &isRemote);
m.cob_id = id;
rt_mq_send(cf_mq, &m, sizeof(Message));
rt_interrupt_leave();
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/inc/usbd_composite.h
|
<reponame>yandld/lpc_uart_server
#ifndef __USBD_COMPOSITE_H_
#define __USBD_COMPOSITE_H_
#include <stdint.h>
#include <usbd.h>
#include <usbd_cdc.h>
void usbd_composite_init(struct usbd_t *h, uint32_t option);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/emc.h
|
/**
******************************************************************************
* @file emc.h
* @author YANDLD
* @version V3.0.0
* @date 2016.5.29
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_EMC_H__
#define __CH_LIB_EMC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
/*! @brief EMC dynamic read strategy. */
typedef enum
{
kEMC_NoDelay = 0x0U, /*!< No delay. */
kEMC_Cmddelay, /*!< Command delayed strategy, using EMCCLKDELAY. */
kEMC_CmdDelayPulseOneclk, /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */
kEMC_CmddelayPulsetwoclk, /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */
} emc_dynamic_read_t;
/*! @brief EMC dynamic timing/delay configure structure. */
typedef struct
{
emc_dynamic_read_t readConfig; /* Dynamic read strategy. */
uint32_t refreshPeriod_Nanosec; /*!< The refresh period in unit of nanosecond. */
uint32_t tRp_Ns; /*!< Precharge command period in unit of nanosecond. */
uint32_t tRas_Ns; /*!< Active to precharge command period in unit of nanosecond. */
uint32_t tSrex_Ns; /*!< Self-refresh exit time in unit of nanosecond. */
uint32_t tApr_Ns; /*!< Last data out to active command time in unit of nanosecond. */
uint32_t tDal_Ns; /*!< Data-in to active command in unit of nanosecond. */
uint32_t tWr_Ns; /*!< Write recovery time in unit of nanosecond. */
uint32_t tRc_Ns; /*!< Active to active command period in unit of nanosecond. */
uint32_t tRfc_Ns; /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */
uint32_t tXsr_Ns; /*!< Exit self-refresh to active command time in unit of nanosecond. */
uint32_t tRrd_Ns; /*!< Active bank A to active bank B latency in unit of nanosecond. */
uint8_t tMrd_Nclk; /*!< Load mode register to active command time in unit of EMCCLK cycles.*/
} emc_dynamic_timing_config_t;
/*! @brief EMC dynamic memory device. */
typedef enum
{
kEMC_Sdram = 0x0U, /*!< Dynamic memory device: SDRAM. */
kEMC_Lpsdram, /*!< Dynamic memory device: Low-power SDRAM. */
} emc_dynamic_device_t;
/*!
* @brief EMC dynamic memory controller independent chip configuration structure.
* Please take refer to the address mapping table in the RM in EMC chapter when you
* set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table
* according to the bus width/banks/row/colum length for you device.
* Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7)
* and inset the bit 13 with 0.
* for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the
* 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length.
* Set devAddrMap with 0x81.
*/
typedef struct
{
uint8_t chipIndex; /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */
emc_dynamic_device_t dynamicDevice; /*!< All chips shall use the same device setting. mixed use are not supported. */
uint8_t rAS_Nclk; /*!< Active to read/write delay tRCD. */
uint16_t sdramModeReg; /*!< Sdram mode register setting. */
uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */
uint8_t devAddrMap; /*!< dynamic device address mapping, choose the address mapping for your specific device. */
} emc_dynamic_chip_config_t;
void EMC_Init(void);
void SDRAM_Init(emc_dynamic_timing_config_t *dynTiming, emc_dynamic_chip_config_t *config);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/mrt.h
|
<filename>mcu_source/Libraries/drivers_lpc/inc/mrt.h<gh_stars>1-10
/**
******************************************************************************
* @file mrt.h
* @author YANDLD
* @version V3.0.0
* @date 2016.05.31
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_MRT_H__
#define __CH_LIB_MRT_H__
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
//!< hardware instances
#define HW_MRT_CH0 (0x00U)
#define HW_MRT_CH1 (0x01U)
#define HW_MRT_CH2 (0x02U)
void MRT_Init(uint32_t chl, uint32_t us);
void MRT_SetValue(uint8_t chl, uint32_t val);
void MRT_SetTime(uint32_t chl, uint32_t us);
uint32_t MRT_GetTime(uint32_t chl);
uint32_t MRT_GetValue(uint32_t chl);
uint32_t MRT_SetIntMode(uint32_t chl, bool val);
#ifdef __cplusplus
}
#endif
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/mrt.c
|
<gh_stars>1-10
/**
******************************************************************************
* @file mrt.c
* @author YANDLD
* @version V3.0.0
* @date 2016.5.28
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "mrt.h"
#include "common.h"
static uint32_t fac_us;
#if defined(LPC8XX)
typedef struct {
struct {
__IO uint32_t INTVAL;
__I uint32_t TIMER;
__IO uint32_t CTRL;
__IO uint32_t STAT;
}CHANNEL[4];
}MRT_Type;
#endif
#if !defined(MRT_BASE)
#if defined(LPC_MRT_BASE)
#define MRT_BASE LPC_MRT_BASE
#elif defined(MRT0)
#define MRT_BASE MRT0_BASE
#endif
#endif
#define MMRT ((MRT_Type *)MRT_BASE)
void MRT_Init(uint32_t chl, uint32_t us)
{
#if defined(SYSCON_AHBCLKCTRL_MRT_MASK)
SYSCON->AHBCLKCTRL[1] |= SYSCON_AHBCLKCTRL_MRT_MASK;
#else
SYSCON->AHBCLKCTRL[1] |= SYSCON_AHBCLKCTRL_MRT0_MASK;
#endif
/* repect interrupt, disable timer */
MMRT->CHANNEL[chl].CTRL = 0x00000000;
/* get clock */
fac_us = US_TO_COUNT(1, GetClock(kCoreClock));
if(us*fac_us > 0x00FFFFFF)
{
MMRT->CHANNEL[chl].INTVAL = 0x80000000 | 0x00FFFFFF;
LIB_TRACE("MRT overflow:%d%%\r\n", (us*fac_us*100)/0x00FFFFFF);
}
else
{
MMRT->CHANNEL[chl].INTVAL = 0x80000000 | us*fac_us;
}
}
void MRT_SetValue(uint8_t chl, uint32_t val)
{
MMRT->CHANNEL[chl].INTVAL = 0x80000000 | val;
}
uint32_t MRT_GetValue(uint32_t chl)
{
return MMRT->CHANNEL[chl].TIMER & 0x7FFFFFFF;
}
void MRT_SetTime(uint32_t chl, uint32_t us)
{
fac_us = US_TO_COUNT(1, GetClock(kCoreClock));
MMRT->CHANNEL[chl].INTVAL = 0x80000000 | us*fac_us;
}
uint32_t MRT_GetTime(uint32_t chl)
{
return MMRT->CHANNEL[chl].INTVAL/fac_us;
}
uint32_t MRT_SetIntMode(uint32_t chl, bool val)
{
(val)?(MMRT->CHANNEL[chl].CTRL |= MRT_CHANNEL_CTRL_INTEN_MASK):(MMRT->CHANNEL[chl].CTRL &= ~MRT_CHANNEL_CTRL_INTEN_MASK);
NVIC_EnableIRQ(MRT0_IRQn);
return CH_OK;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/lcdc.h
|
/**
******************************************************************************
* @file lcdc.h
* @author YANDLD
* @version V3.0.0
* @date 2016.6.2
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_LPC_LCDC_H__
#define __CH_LIB_LPC_LCDC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
/*!
* @brief LCD bits per pixel.
*/
typedef enum
{
kLCDC_1BPP = 0U, /*!< 1 bpp. */
kLCDC_2BPP = 1U, /*!< 2 bpp. */
kLCDC_4BPP = 2U, /*!< 4 bpp. */
kLCDC_8BPP = 3U, /*!< 8 bpp. */
kLCDC_16BPP = 4U, /*!< 16 bpp. */
kLCDC_24BPP = 5U, /*!< 24 bpp, TFT panel only. */
kLCDC_16BPP565 = 6U, /*!< 16 bpp, 5:6:5 mode. */
kLCDC_12BPP = 7U, /*!< 12 bpp, 4:4:4 mode. */
} lcdc_bpp_t;
/*!
* @brief LCD panel buffer data format.
*/
typedef enum
{
kLCDC_LittleEndian = 0U, /*!< Little endian byte, little endian pixel. */
kLCDC_BigEndian = LCD_CTRL_BEPO_MASK | LCD_CTRL_BEBO_MASK, /*!< Big endian byte, big endian pixel. */
kLCDC_WinCeMode = LCD_CTRL_BEPO_MASK, /*!< little-endian byte, big-endian pixel for Windows CE mode. */
} lcdc_data_format_t;
/*!
* @brief LCD sigal polarity flags.
*/
enum
{
kLCDC_InvertVsyncPolarity = LCD_POL_IVS_MASK, /*!< Invert the VSYNC polarity, set to active low. */
kLCDC_InvertHsyncPolarity = LCD_POL_IHS_MASK, /*!< Invert the HSYNC polarity, set to active low. */
kLCDC_InvertClkPolarity = LCD_POL_IPC_MASK, /*!< Invert the panel clock polarity, set to
drive data on falling edge. */
kLCDC_InvertDePolarity = LCD_POL_IOE_MASK, /*!< Invert the data enable (DE) polarity, set to active low. */
};
typedef struct
{
uint16_t ppl; /*!< Pixels per line, it must could be divided by 16. */
uint8_t hsw; /*!< HSYNC pulse width. */
uint8_t hfp; /*!< Horizontal front porch. */
uint8_t hbp; /*!< Horizontal back porch. */
uint16_t lpp; /*!< Lines per panal. */
uint8_t vsw; /*!< VSYNC pulse width. */
uint8_t vfp; /*!< Vrtical front porch. */
uint8_t vbp; /*!< Vertical back porch. */
uint8_t acBiasFreq; /*!< The number of line clocks between AC bias pin toggling. Only used for STN display. */
uint16_t polarityFlags; /*!< OR'ed value of @ref _lcdc_polarity_flags, used to contol the signal polarity. */
bool enableLineEnd; /*!< Enable line end or not, the line end is a positive pulse with 4 panel clock. */
uint8_t lineEndDelay; /*!< The panel clocks between the last pixel of line and the start of line end. */
uint32_t upperPanelAddr; /*!< LCD upper panel base address, must be double-word(64-bit) align. */
uint32_t lowerPanelAddr; /*!< LCD lower panel base address, must be double-word(64-bit) align. */
lcdc_bpp_t bpp; /*!< LCD bits per pixel. */
lcdc_data_format_t dataFormat; /*!< Data format. */
bool swapRedBlue; /*!< Set true to use BGR format, set false to choose RGB format. */
uint8_t fps;
}LCDC_Config_t;
void LCDC_GetDefaultConfig(LCDC_Config_t *config);
void LCDC_Init(LCDC_Config_t *config);
void LCDC_SetIntMode(bool val);
void LCDC_CursorInit(void);
void LCDC_CursorSetPos(int32_t x, int32_t y);
void LCDC_CursorShow(bool val);
void LCDC_CursorSelectImage(uint8_t index);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/usbd_hid.c
|
<gh_stars>1-10
#include <string.h>
#include "usb_common.h"
#include "usbd.h"
#include "usbd_hid.h"
struct uhid_t
{
struct usbd_t *h; /* usbd handle */
struct usbd_hid_callback_t *cb;
uint8_t out_buf[64];
uint8_t keyboard_in_buf[8];
uint8_t mouse_in_buf[4];
};
static struct uhid_t hid;
uint32_t hid_class_request_handler(struct usbd_t *h)
{
USBD_TRACE("class request:0x%X\r\n", h->setup.request);
if(h->setup.request == 0x0A)
{
/* HID:set idle, do nothing */
USBD_TRACE("reqeust to class: HID set idle\r\n");
usbd_status_in_stage();
}
return CH_OK;
}
uint32_t hid_standard_request_to_intf_handler(struct usbd_t *h)
{
desc_t d;
if(h->setup.request == USB_REQ_GET_DESCRIPTOR)
{
if((h->setup.value >> 8) == USB_DESC_TYPE_REPORT)
{
/* get hid report descriptor class index 0 */
if(h->setup.index == USBD_HID0_IF_IDX)
{
get_descriptor_data("report_descriptor_keyboard", &d);
USBD_TRACE("send key boarad report descrtipor size:%d\r\n", d.len);
begin_data_in_stage((uint8_t*)d.buf, d.len);
}
if(h->setup.index == USBD_HID1_IF_IDX)
{
get_descriptor_data("report_descriptor_mouse", &d);
USBD_TRACE("send mouse report descrtipor size:%d\r\n", d.len);
begin_data_in_stage((uint8_t*)d.buf, d.len);
}
if(h->setup.index == USBD_HID2_IF_IDX)
{
get_descriptor_data("report_descriptor_custom", &d);
USBD_TRACE("send custom report descrtipor size:%d\r\n", d.len);
begin_data_in_stage((uint8_t*)d.buf, d.len);
}
}
}
return CH_OK;
}
uint32_t hid_data_ep_handler(uint8_t ep, uint8_t dir)
{
uint32_t size;
switch(ep)
{
case USBD_HID1_EP_INTIN:
case USBD_HID0_EP_INTIN:
case USBD_HID2_EP_INTIN:
if(hid.cb)
{
if(dir == 1) /* in transfer */
{
hid.cb->data_send_notify(ep);
}
else
{
size = usbd_ep_read(ep, hid.out_buf);
hid.cb->data_received(ep, hid.out_buf, size);
}
}
break;
}
return CH_OK;
}
/*
* Get Mouse Input Report -> MouseInReport
* Parameters: report:
* Byte0.0: 1st Button (Left)
* Byte0.1: 2nd Button (Right)
* Byte0.2: 3rd Button
* Byte1: Relative X Pos
* Byte2: Relative Y Pos
* Byte3: Relative Wheel Pos
* size: report size
* Return Value: None
*/
uint32_t usbd_set_mouse(uint8_t btn, int8_t x, int8_t y, int8_t wheel)
{
uint8_t *p = hid.mouse_in_buf;
p[0] = btn;
p[1] = x;
p[2] = y;
p[3] = wheel;
usbd_ep_write(USBD_HID1_EP_INTIN, hid.mouse_in_buf, 4);
return CH_OK;
}
uint32_t usbd_set_keyboard(uint8_t fun_key, uint8_t key)
{
uint8_t *p = hid.keyboard_in_buf;
p[0] = fun_key;
p[1] = 0x00; /* reserved */
p[2] = key;
p[3] = 0;
p[4] = 0;
p[5] = 0;
p[6] = 0;
p[7] = 0;
usbd_ep_write(USBD_HID0_EP_INTIN, hid.keyboard_in_buf, 8);
return CH_OK;
}
void usbd_hid_set_cb(struct usbd_hid_callback_t *cb)
{
hid.cb = cb;
}
void usbd_hid_init(struct usbd_t *h, uint32_t intf_cnt)
{
hid.h = h;
uint8_t *p;
struct uconfig_descriptor *uconfiguration_descriptor;
desc_t d;
get_descriptor_data("configuration_descriptor", &d);
uconfiguration_descriptor = (struct uconfig_descriptor *)d.buf;
uconfiguration_descriptor->bLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->type = USB_DESC_TYPE_CONFIGURATION;
uconfiguration_descriptor->wTotalLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->bNumInterfaces = intf_cnt; /* hid interface num */
uconfiguration_descriptor->bConfigurationValue = 1;
uconfiguration_descriptor->iConfiguration = 0;
uconfiguration_descriptor->bmAttributes = 0x80;
uconfiguration_descriptor->MaxPower = 0x32;
p = uconfiguration_descriptor->data;
get_descriptor_data("hid0_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
if(intf_cnt == 2)
{
get_descriptor_data("hid1_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
}
if(intf_cnt == 3)
{
get_descriptor_data("hid2_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
}
/* install class callback */
hid.h->class_request_handler = hid_class_request_handler;
hid.h->standard_request_to_intf_handler = hid_standard_request_to_intf_handler;
hid.h->data_ep_handler = hid_data_ep_handler;
hid.h->setup_out_data_received_handler = NULL;
hid.h->vender_request_handler = NULL;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/system_SKEAZ1284.h
|
/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: MKE06P80M48SF0RM, Rev. 1, Dec 2013
** Version: rev. 1.2, 2014-01-10
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2014 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2013-07-30)
** Initial version.
** - rev. 1.1 (2013-10-29)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 1.2 (2014-01-10)
** CAN module: corrected address of TSIDR1 register.
** CAN module: corrected name of MSCAN_TDLR bit DLC to TDLC.
** FTM0 module: added access macro for EXTTRIG register.
** NVIC module: registers access macros improved.
** SCB module: unused bits removed, mask, shift macros improved.
** Defines of interrupt vectors aligned to RM.
**
** ###################################################################
*/
/*!
* @file SKEAZ1284
* @version 1.2
* @date 2014-01-10
* @brief Device specific configuration file for SKEAZ1284 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_SKEAZ1284_H_
#define SYSTEM_SKEAZ1284_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_SKEAZ1284_H_) */
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/uart_dma_test.c
|
#include <rtthread.h>
#include "uart_bridge.h"
#include "common.h"
#include "gpio.h"
#include "uart.h"
#include "dma.h"
void _setup_dma_tx_desc(uint8_t ch, DMA_ChlSetup_t *setup);
void _setup_dma_rx_desc(uint8_t ch, DMA_ChlSetup_t *setup);
uint8_t rx_buf0[128];
DMA_ChlSetup_t rx_dma0;
void uart_dma_test_thread_entry(void* parameter)
{
int sum, len;
printf("uart_dma_test_thread_entry\r\n");
UART_SetLoopbackMode(HW_UART4, false);
UART_SetIntMode(HW_UART4, kUART_IntRx, false);
/* setup rx */
rx_dma0.dAddr = (uint32_t)rx_buf0;
rx_dma0.transferCnt = sizeof(rx_buf0);
_setup_dma_rx_desc(4, &rx_dma0);
// DMA_SetChlIntMode(DMAREQ_FLEXCOMM4_RX, true);
DMA_SWTrigger(DMAREQ_FLEXCOMM4_RX);
sum = 0;
while(1)
{
while(DMA0->COMMON[0].BUSY) {};
DMA0->COMMON[0].ENABLECLR = (1 << DMAREQ_FLEXCOMM4_RX);
len = sizeof(rx_buf0) - DMA_GetTransferCnt(DMAREQ_FLEXCOMM4_RX);
sum += len;
DMA_SetupChl(&rx_dma0);
DMA_SWTrigger(DMAREQ_FLEXCOMM4_RX);
if(len)
{
printf("len:%d sum%d\r\n", len, sum);
}
DelayMs(2);
}
}
void DMA0_IRQHandler(void)
{
int i;
static uint32_t INTA;
INTA = DMA0->COMMON[0].INTA;
/* clear int */
DMA0->COMMON[0].INTA = DMA0->COMMON[0].INTA;
if(INTA & (1 << DMAREQ_FLEXCOMM4_RX))
{
// rx_dma.dAddr = (uint32_t)rx_buf;
// rx_dma.transferCnt = 4;
// _setup_dma_rx_desc(DMAREQ_FLEXCOMM4_RX, &rx_dma);
// DMA_SWTrigger(DMAREQ_FLEXCOMM4_RX);
// printf("%X %X\r\n", rx_buf[0], rx_buf[1]);
}
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/test/usbd_msc_test.c
|
<gh_stars>1-10
#include <string.h>
#include "usbd_msc.h"
extern struct usbd_t usbd;
#define BLOCK_SIZE (512)
#define BLOCK_CNT (100)
uint8_t DiskBuf[BLOCK_SIZE*BLOCK_CNT];
uint32_t msc_read_sector (uint32_t block, uint8_t *buf, uint32_t block_cnt)
{
// printf("r block:%d cnt:%d\r\n", block, block_cnt);
memcpy(buf, DiskBuf + block*BLOCK_SIZE, block_cnt*BLOCK_SIZE);
return 0;
}
uint32_t msc_write_sector(uint32_t block, uint8_t *buf, uint32_t block_cnt)
{
//printf("w block:%d cnt:%d buf:%X\r\n", block, block_cnt, buf);
memcpy(DiskBuf + block*BLOCK_SIZE, buf, BLOCK_SIZE*block_cnt);
return 0;
}
uint32_t msc_get_disk_info(uint32_t *total_block_cnt, uint32_t *block_size)
{
*total_block_cnt = BLOCK_CNT;
*block_size = BLOCK_SIZE;
return 0;
}
struct usbd_msc_callback_t msc_cb =
{
msc_read_sector,
msc_write_sector,
msc_get_disk_info,
};
void usbd_msc_test(struct usbd_t *h)
{
usbd_msc_set_cb(&msc_cb);
usbd_msc_init(h);
}
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/uart_bridge_support.c
|
#include "common.h"
#include "uart.h"
#include "dma.h"
#include "ulog.h"
void _setup_dma_tx_desc(uint8_t ch, DMA_ChlSetup_t *setup)
{
setup->chl = DMAREQ_FLEXCOMM0_RX + ch*2 + 1;
if(ch == 8)
{
setup->chl = DMAREQ_FLEXCOMM8_TX;
}
if(ch == 9)
{
setup->chl = DMAREQ_FLEXCOMM9_TX;
}
setup->isPeriph = true;
setup->dataWidth = 1;
setup->sAddrInc = 1;
setup->dAddrInc = 0;
switch(setup->chl)
{
case DMAREQ_FLEXCOMM0_TX:
setup->dAddr = (uint32_t)(&(USART0->FIFOWR));
break;
case DMAREQ_FLEXCOMM1_TX:
setup->dAddr = (uint32_t)(&(USART1->FIFOWR));
break;
case DMAREQ_FLEXCOMM2_TX:
setup->dAddr = (uint32_t)(&(USART2->FIFOWR));
break;
case DMAREQ_FLEXCOMM3_TX:
setup->dAddr = (uint32_t)(&(USART3->FIFOWR));
break;
case DMAREQ_FLEXCOMM4_TX:
setup->dAddr = (uint32_t)(&(USART4->FIFOWR));
break;
case DMAREQ_FLEXCOMM5_TX:
setup->dAddr = (uint32_t)(&(USART5->FIFOWR));
break;
case DMAREQ_FLEXCOMM6_TX:
setup->dAddr = (uint32_t)(&(USART6->FIFOWR));
break;
case DMAREQ_FLEXCOMM7_TX:
setup->dAddr = (uint32_t)(&(USART7->FIFOWR));
break;
case DMAREQ_FLEXCOMM8_TX:
setup->dAddr = (uint32_t)(&(USART8->FIFOWR));
break;
case DMAREQ_FLEXCOMM9_TX:
setup->dAddr = (uint32_t)(&(USART9->FIFOWR));
break;
default:
LOG_I("_setup_dma_tx_desc failed %d\r\n", setup->chl);
break;
}
DMA_SetupChl(setup);
}
void _setup_dma_rx_desc(uint8_t ch, DMA_ChlSetup_t *setup)
{
setup->chl = DMAREQ_FLEXCOMM0_RX + ch*2;
if(ch == 8)
{
setup->chl = DMAREQ_FLEXCOMM8_RX;
}
if(ch == 9)
{
setup->chl = DMAREQ_FLEXCOMM9_RX;
}
setup->isPeriph = true;
setup->dataWidth = 1;
setup->sAddrInc = 0;
setup->dAddrInc = 1;
switch(setup->chl)
{
case DMAREQ_FLEXCOMM0_RX:
setup->sAddr = (uint32_t)(&(USART0->FIFORD));
break;
case DMAREQ_FLEXCOMM1_RX:
setup->sAddr = (uint32_t)(&(USART1->FIFORD));
break;
case DMAREQ_FLEXCOMM2_RX:
setup->sAddr = (uint32_t)(&(USART2->FIFORD));
break;
case DMAREQ_FLEXCOMM3_RX:
setup->sAddr = (uint32_t)(&(USART3->FIFORD));
break;
case DMAREQ_FLEXCOMM4_RX:
setup->sAddr = (uint32_t)(&(USART4->FIFORD));
break;
case DMAREQ_FLEXCOMM5_RX:
setup->sAddr = (uint32_t)(&(USART5->FIFORD));
break;
case DMAREQ_FLEXCOMM6_RX:
setup->sAddr = (uint32_t)(&(USART6->FIFORD));
break;
case DMAREQ_FLEXCOMM7_RX:
setup->sAddr = (uint32_t)(&(USART7->FIFORD));
break;
case DMAREQ_FLEXCOMM8_RX:
setup->sAddr = (uint32_t)(&(USART8->FIFORD));
break;
case DMAREQ_FLEXCOMM9_RX:
setup->sAddr = (uint32_t)(&(USART9->FIFORD));
break;
default:
LOG_I("_setup_dma_rx_desc failed %d\r\n", ch);
break;
}
DMA_SetupChl(setup);
}
//static void uart_irq_handler(uint8_t chl)
//{
// uint8_t ch;
// if(UART_GetChar(chl, &ch) == CH_OK)
// {
// rt_ringbuffer_put(&bridge[chl].rrb, &ch, 1);
// }
//}
//void FLEXCOMM1_IRQHandler(void)
//{
// uart_irq_handler(1);
//}
//void FLEXCOMM2_IRQHandler(void)
//{
// uart_irq_handler(2);
//}
//void FLEXCOMM3_IRQHandler(void)
//{
// uart_irq_handler(3);
//}
//void FLEXCOMM4_IRQHandler(void)
//{
// uart_irq_handler(4);
//}
//void FLEXCOMM5_IRQHandler(void)
//{
// uart_irq_handler(5);
//}
//void FLEXCOMM6_IRQHandler(void)
//{
// uart_irq_handler(6);
//}
//void FLEXCOMM7_IRQHandler(void)
//{
// uart_irq_handler(7);
//}
//void FLEXCOMM8_IRQHandler(void)
//{
// uart_irq_handler(8);
//}
//void FLEXCOMM9_IRQHandler(void)
//{
// uart_irq_handler(9);
//}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/system_MM32F103xCxE_o.h
|
<gh_stars>1-10
#ifndef __SYSTEM_MM32F103xCxE_o_H__
#define __SYSTEM_MM32F103xCxE_o_H__
extern uint32_t SystemCoreClock;
void SystemInit (void);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/MKS22F25612.h
|
<gh_stars>1-10
/*
** ###################################################################
** Processors: MKS22FN256LH12
** MKS22FN128LH12
** MKS22FN256LL12
** MKS22FN128LL12
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KS22P100M120SF0RM, Rev. 1, Sep. 2015
** Version: rev. 2.0, 2015-10-10
** Build: b151021
**
** Abstract:
** CMSIS Peripheral Access Layer for MKS22F25612
**
** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2015-06-23)
** Initial version.
** - rev. 2.0 (2015-10-10)
** Update according to Rev1 RM, Sep 2015.
**
** ###################################################################
*/
/*!
* @file MKS22F25612.h
* @version 2.0
* @date 2015-10-10
* @brief CMSIS Peripheral Access Layer for MKS22F25612
*
* CMSIS Peripheral Access Layer for MKS22F25612
*/
/* ----------------------------------------------------------------------------
-- MCU activation
---------------------------------------------------------------------------- */
/* Prevention from multiple including the same memory map */
#if !defined(MKS22F25612_H_) /* Check if memory map has not been already included */
#define MKS22F25612_H_
#define MCU_MKS22F25612
/* Check if another memory map has not been also included */
#if (defined(MCU_ACTIVE))
#error MKS22F25612 memory map: There is already included another memory map. Only one memory map can be included.
#endif /* (defined(MCU_ACTIVE)) */
#define MCU_ACTIVE
#include <stdint.h>
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0200u
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
/**
* @brief Macro to calculate address of an aliased word in the peripheral
* bitband area for a peripheral register and bit (bit band region 0x40000000 to
* 0x400FFFFF).
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Address of the aliased word in the peripheral bitband area.
*/
#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 32bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 16bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 8bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 116 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
/* Device specific interrupts */
DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
MCM_IRQn = 17, /**< Normal Interrupt */
FTF_IRQn = 18, /**< FTFA Command complete interrupt */
Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
RNG_IRQn = 23, /**< RNG Interrupt */
LPI2C0_IRQn = 24, /**< LPI2C0 interrupt */
LPI2C1_IRQn = 25, /**< LPI2C1 interrupt */
SPI0_IRQn = 26, /**< SPI0 Interrupt */
SPI1_IRQn = 27, /**< SPI1 Interrupt */
I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */
UART0_RX_TX_IRQn = 31, /**< UART0 Status Sources interrupt */
UART0_ERR_IRQn = 32, /**< UART0 Error Sources interrupt */
UART1_RX_TX_IRQn = 33, /**< UART1 Status Sources interrupt */
UART1_ERR_IRQn = 34, /**< UART1 Error Sources interrupt */
UART2_RX_TX_IRQn = 35, /**< UART2 Status Sources interrupt */
UART2_ERR_IRQn = 36, /**< UART2 Error Sources interrupt */
Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
ADC0_IRQn = 39, /**< ADC0 interrupt */
CMP0_IRQn = 40, /**< CMP0 interrupt */
Reserved57_IRQn = 41, /**< Reserved interrupt 57 */
TPM0_IRQn = 42, /**< TPM0 Timer Overflow and Channels interrupt */
TPM1_IRQn = 43, /**< TPM1 Timer Overflow and Channels interrupt */
TPM2_IRQn = 44, /**< TPM2 Timer Overflow and Channels interrupt */
Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
RTC_IRQn = 46, /**< RTC alarm interrupt */
RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
PDB0_IRQn = 52, /**< PDB0 Interrupt */
USB0_IRQn = 53, /**< USB0 interrupt */
Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
DAC0_IRQn = 56, /**< DAC0 interrupt */
MCG_IRQn = 57, /**< MCG Interrupt */
LPTMR0_IRQn = 58, /**< LPTimer interrupt */
PORTA_IRQn = 59, /**< Port A interrupt */
PORTB_IRQn = 60, /**< Port B interrupt */
PORTC_IRQn = 61, /**< Port C interrupt */
PORTD_IRQn = 62, /**< Port D interrupt */
PORTE_IRQn = 63, /**< Port E interrupt */
SWI_IRQn = 64, /**< Software interrupt */
Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
FLEXIO_IRQn = 70, /**< Flexible IO interrupt */
Reserved87_IRQn = 71, /**< Reserved interrupt 87 */
Reserved88_IRQn = 72, /**< Reserved interrupt 88 */
Reserved89_IRQn = 73, /**< Reserved interrupt 89 */
Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */
CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */
Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
Reserved101_IRQn = 85, /**< Reserved Interrupt 101 */
Reserved102_IRQn = 86, /**< Reserved Interrupt 102 */
Reserved103_IRQn = 87, /**< Reserved Interrupt 103 */
I2S1_Tx_IRQn = 88, /**< I2S1 transmit interrupt */
I2S1_Rx_IRQn = 89, /**< I2S1 receive interrupt */
Reserved106_IRQn = 90, /**< Reserved Interrupt 106 */
Reserved107_IRQn = 91, /**< Reserved Interrupt 107 */
Reserved108_IRQn = 92, /**< Reserved Interrupt 108 */
Reserved109_IRQn = 93, /**< Reserved Interrupt 109 */
CAN1_ORed_Message_buffer_IRQn = 94, /**< CAN0 OR'd message buffers interrupt */
CAN1_Bus_Off_IRQn = 95, /**< CAN1 bus off interrupt */
CAN1_Error_IRQn = 96, /**< CAN1 error interrupt */
CAN1_Tx_Warning_IRQn = 97, /**< CAN1 Tx warning interrupt */
CAN1_Rx_Warning_IRQn = 98, /**< CAN1 Rx warning interrupt */
CAN1_Wake_Up_IRQn = 99 /**< CAN1 wake up interrupt */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M4 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
* @{
*/
#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
#include "core_cm4.h" /* Core Peripheral Access Layer */
#include "system_MKS22F25612.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
__IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
__I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
__IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
__IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
__IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
__IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
__IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
__IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
__IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
__IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
__IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
__IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
__IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
__IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
__IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
__IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
uint8_t RESERVED_0[4];
__IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
__IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
__IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
__IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
} ADC_Type, *ADC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register accessors */
#define ADC_SC1_REG(base,index) ((base)->SC1[index])
#define ADC_SC1_COUNT 2
#define ADC_CFG1_REG(base) ((base)->CFG1)
#define ADC_CFG2_REG(base) ((base)->CFG2)
#define ADC_R_REG(base,index) ((base)->R[index])
#define ADC_R_COUNT 2
#define ADC_CV1_REG(base) ((base)->CV1)
#define ADC_CV2_REG(base) ((base)->CV2)
#define ADC_SC2_REG(base) ((base)->SC2)
#define ADC_SC3_REG(base) ((base)->SC3)
#define ADC_OFS_REG(base) ((base)->OFS)
#define ADC_PG_REG(base) ((base)->PG)
#define ADC_MG_REG(base) ((base)->MG)
#define ADC_CLPD_REG(base) ((base)->CLPD)
#define ADC_CLPS_REG(base) ((base)->CLPS)
#define ADC_CLP4_REG(base) ((base)->CLP4)
#define ADC_CLP3_REG(base) ((base)->CLP3)
#define ADC_CLP2_REG(base) ((base)->CLP2)
#define ADC_CLP1_REG(base) ((base)->CLP1)
#define ADC_CLP0_REG(base) ((base)->CLP0)
#define ADC_CLMD_REG(base) ((base)->CLMD)
#define ADC_CLMS_REG(base) ((base)->CLMS)
#define ADC_CLM4_REG(base) ((base)->CLM4)
#define ADC_CLM3_REG(base) ((base)->CLM3)
#define ADC_CLM2_REG(base) ((base)->CLM2)
#define ADC_CLM1_REG(base) ((base)->CLM1)
#define ADC_CLM0_REG(base) ((base)->CLM0)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH_WIDTH 5
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK 0x20u
#define ADC_SC1_DIFF_SHIFT 5
#define ADC_SC1_DIFF_WIDTH 1
#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_AIEN_WIDTH 1
#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
#define ADC_SC1_COCO_WIDTH 1
#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK_WIDTH 2
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE_WIDTH 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADLSMP_WIDTH 1
#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV_WIDTH 2
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
#define ADC_CFG1_ADLPC_WIDTH 1
#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS_WIDTH 2
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADHSC_WIDTH 1
#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_ADACKEN_WIDTH 1
#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
#define ADC_CFG2_MUXSEL_WIDTH 1
#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D_WIDTH 16
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV_WIDTH 16
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV_WIDTH 16
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL_WIDTH 2
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK 0x4u
#define ADC_SC2_DMAEN_SHIFT 2
#define ADC_SC2_DMAEN_WIDTH 1
#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACREN_WIDTH 1
#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFGT_WIDTH 1
#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ACFE_WIDTH 1
#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADTRG_WIDTH 1
#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
#define ADC_SC2_ADACT_WIDTH 1
#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS_WIDTH 2
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_AVGE_WIDTH 1
#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_ADCO_WIDTH 1
#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CALF_WIDTH 1
#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
#define ADC_SC3_CAL_WIDTH 1
#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
#define ADC_OFS_OFS_WIDTH 16
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
/* PG Bit Fields */
#define ADC_PG_PG_MASK 0xFFFFu
#define ADC_PG_PG_SHIFT 0
#define ADC_PG_PG_WIDTH 16
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
/* MG Bit Fields */
#define ADC_MG_MG_MASK 0xFFFFu
#define ADC_MG_MG_SHIFT 0
#define ADC_MG_MG_WIDTH 16
#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
/* CLPD Bit Fields */
#define ADC_CLPD_CLPD_MASK 0x3Fu
#define ADC_CLPD_CLPD_SHIFT 0
#define ADC_CLPD_CLPD_WIDTH 6
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
/* CLPS Bit Fields */
#define ADC_CLPS_CLPS_MASK 0x3Fu
#define ADC_CLPS_CLPS_SHIFT 0
#define ADC_CLPS_CLPS_WIDTH 6
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
/* CLP4 Bit Fields */
#define ADC_CLP4_CLP4_MASK 0x3FFu
#define ADC_CLP4_CLP4_SHIFT 0
#define ADC_CLP4_CLP4_WIDTH 10
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
/* CLP3 Bit Fields */
#define ADC_CLP3_CLP3_MASK 0x1FFu
#define ADC_CLP3_CLP3_SHIFT 0
#define ADC_CLP3_CLP3_WIDTH 9
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
/* CLP2 Bit Fields */
#define ADC_CLP2_CLP2_MASK 0xFFu
#define ADC_CLP2_CLP2_SHIFT 0
#define ADC_CLP2_CLP2_WIDTH 8
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
/* CLP1 Bit Fields */
#define ADC_CLP1_CLP1_MASK 0x7Fu
#define ADC_CLP1_CLP1_SHIFT 0
#define ADC_CLP1_CLP1_WIDTH 7
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
/* CLP0 Bit Fields */
#define ADC_CLP0_CLP0_MASK 0x3Fu
#define ADC_CLP0_CLP0_SHIFT 0
#define ADC_CLP0_CLP0_WIDTH 6
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
/* CLMD Bit Fields */
#define ADC_CLMD_CLMD_MASK 0x3Fu
#define ADC_CLMD_CLMD_SHIFT 0
#define ADC_CLMD_CLMD_WIDTH 6
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
/* CLMS Bit Fields */
#define ADC_CLMS_CLMS_MASK 0x3Fu
#define ADC_CLMS_CLMS_SHIFT 0
#define ADC_CLMS_CLMS_WIDTH 6
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
/* CLM4 Bit Fields */
#define ADC_CLM4_CLM4_MASK 0x3FFu
#define ADC_CLM4_CLM4_SHIFT 0
#define ADC_CLM4_CLM4_WIDTH 10
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
/* CLM3 Bit Fields */
#define ADC_CLM3_CLM3_MASK 0x1FFu
#define ADC_CLM3_CLM3_SHIFT 0
#define ADC_CLM3_CLM3_WIDTH 9
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
/* CLM2 Bit Fields */
#define ADC_CLM2_CLM2_MASK 0xFFu
#define ADC_CLM2_CLM2_SHIFT 0
#define ADC_CLM2_CLM2_WIDTH 8
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
/* CLM1 Bit Fields */
#define ADC_CLM1_CLM1_MASK 0x7Fu
#define ADC_CLM1_CLM1_SHIFT 0
#define ADC_CLM1_CLM1_WIDTH 7
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
/* CLM0 Bit Fields */
#define ADC_CLM0_CLM0_MASK 0x3Fu
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0_WIDTH 6
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
#define ADC0_BASE_PTR (ADC0)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { ADC0_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { ADC0 }
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register instance definitions */
/* ADC0 */
#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
#define ADC0_RA ADC_R_REG(ADC0,0)
#define ADC0_RB ADC_R_REG(ADC0,1)
#define ADC0_CV1 ADC_CV1_REG(ADC0)
#define ADC0_CV2 ADC_CV2_REG(ADC0)
#define ADC0_SC2 ADC_SC2_REG(ADC0)
#define ADC0_SC3 ADC_SC3_REG(ADC0)
#define ADC0_OFS ADC_OFS_REG(ADC0)
#define ADC0_PG ADC_PG_REG(ADC0)
#define ADC0_MG ADC_MG_REG(ADC0)
#define ADC0_CLPD ADC_CLPD_REG(ADC0)
#define ADC0_CLPS ADC_CLPS_REG(ADC0)
#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
#define ADC0_CLMD ADC_CLMD_REG(ADC0)
#define ADC0_CLMS ADC_CLMS_REG(ADC0)
#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
/* ADC - Register array accessors */
#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
#define ADC0_R(index) ADC_R_REG(ADC0,index)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAN Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
* @{
*/
/** CAN - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
__IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
__IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
__IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
__IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
__IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
__IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
uint8_t RESERVED_1[4];
__IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
uint8_t RESERVED_2[4];
__IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
__IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
__I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
uint8_t RESERVED_3[8];
__I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
__IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
__I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
__IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */
uint8_t RESERVED_4[44];
struct { /* offset: 0x80, array step: 0x10 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
__IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
__IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
} MB[16];
uint8_t RESERVED_5[1792];
__IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
} CAN_Type, *CAN_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CAN - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
* @{
*/
/* CAN - Register accessors */
#define CAN_MCR_REG(base) ((base)->MCR)
#define CAN_CTRL1_REG(base) ((base)->CTRL1)
#define CAN_TIMER_REG(base) ((base)->TIMER)
#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
#define CAN_ECR_REG(base) ((base)->ECR)
#define CAN_ESR1_REG(base) ((base)->ESR1)
#define CAN_IMASK1_REG(base) ((base)->IMASK1)
#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
#define CAN_CTRL2_REG(base) ((base)->CTRL2)
#define CAN_ESR2_REG(base) ((base)->ESR2)
#define CAN_CRCR_REG(base) ((base)->CRCR)
#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
#define CAN_RXFIR_REG(base) ((base)->RXFIR)
#define CAN_CBT_REG(base) ((base)->CBT)
#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
#define CAN_CS_COUNT 16
#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
#define CAN_ID_COUNT 16
#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
#define CAN_WORD0_COUNT 16
#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
#define CAN_WORD1_COUNT 16
#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
#define CAN_RXIMR_COUNT 16
/*!
* @}
*/ /* end of group CAN_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CAN Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Masks CAN Register Masks
* @{
*/
/* MCR Bit Fields */
#define CAN_MCR_MAXMB_MASK 0x7Fu
#define CAN_MCR_MAXMB_SHIFT 0
#define CAN_MCR_MAXMB_WIDTH 7
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK 0x300u
#define CAN_MCR_IDAM_SHIFT 8
#define CAN_MCR_IDAM_WIDTH 2
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
#define CAN_MCR_AEN_MASK 0x1000u
#define CAN_MCR_AEN_SHIFT 12
#define CAN_MCR_AEN_WIDTH 1
#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
#define CAN_MCR_LPRIOEN_MASK 0x2000u
#define CAN_MCR_LPRIOEN_SHIFT 13
#define CAN_MCR_LPRIOEN_WIDTH 1
#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
#define CAN_MCR_DMA_MASK 0x8000u
#define CAN_MCR_DMA_SHIFT 15
#define CAN_MCR_DMA_WIDTH 1
#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DMA_SHIFT))&CAN_MCR_DMA_MASK)
#define CAN_MCR_IRMQ_MASK 0x10000u
#define CAN_MCR_IRMQ_SHIFT 16
#define CAN_MCR_IRMQ_WIDTH 1
#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
#define CAN_MCR_SRXDIS_MASK 0x20000u
#define CAN_MCR_SRXDIS_SHIFT 17
#define CAN_MCR_SRXDIS_WIDTH 1
#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
#define CAN_MCR_DOZE_MASK 0x40000u
#define CAN_MCR_DOZE_SHIFT 18
#define CAN_MCR_DOZE_WIDTH 1
#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DOZE_SHIFT))&CAN_MCR_DOZE_MASK)
#define CAN_MCR_WAKSRC_MASK 0x80000u
#define CAN_MCR_WAKSRC_SHIFT 19
#define CAN_MCR_WAKSRC_WIDTH 1
#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
#define CAN_MCR_LPMACK_MASK 0x100000u
#define CAN_MCR_LPMACK_SHIFT 20
#define CAN_MCR_LPMACK_WIDTH 1
#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
#define CAN_MCR_WRNEN_MASK 0x200000u
#define CAN_MCR_WRNEN_SHIFT 21
#define CAN_MCR_WRNEN_WIDTH 1
#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
#define CAN_MCR_SLFWAK_MASK 0x400000u
#define CAN_MCR_SLFWAK_SHIFT 22
#define CAN_MCR_SLFWAK_WIDTH 1
#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
#define CAN_MCR_SUPV_MASK 0x800000u
#define CAN_MCR_SUPV_SHIFT 23
#define CAN_MCR_SUPV_WIDTH 1
#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
#define CAN_MCR_FRZACK_MASK 0x1000000u
#define CAN_MCR_FRZACK_SHIFT 24
#define CAN_MCR_FRZACK_WIDTH 1
#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
#define CAN_MCR_SOFTRST_MASK 0x2000000u
#define CAN_MCR_SOFTRST_SHIFT 25
#define CAN_MCR_SOFTRST_WIDTH 1
#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
#define CAN_MCR_WAKMSK_MASK 0x4000000u
#define CAN_MCR_WAKMSK_SHIFT 26
#define CAN_MCR_WAKMSK_WIDTH 1
#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
#define CAN_MCR_NOTRDY_MASK 0x8000000u
#define CAN_MCR_NOTRDY_SHIFT 27
#define CAN_MCR_NOTRDY_WIDTH 1
#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
#define CAN_MCR_HALT_MASK 0x10000000u
#define CAN_MCR_HALT_SHIFT 28
#define CAN_MCR_HALT_WIDTH 1
#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
#define CAN_MCR_RFEN_MASK 0x20000000u
#define CAN_MCR_RFEN_SHIFT 29
#define CAN_MCR_RFEN_WIDTH 1
#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
#define CAN_MCR_FRZ_MASK 0x40000000u
#define CAN_MCR_FRZ_SHIFT 30
#define CAN_MCR_FRZ_WIDTH 1
#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
#define CAN_MCR_MDIS_MASK 0x80000000u
#define CAN_MCR_MDIS_SHIFT 31
#define CAN_MCR_MDIS_WIDTH 1
#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
/* CTRL1 Bit Fields */
#define CAN_CTRL1_PROPSEG_MASK 0x7u
#define CAN_CTRL1_PROPSEG_SHIFT 0
#define CAN_CTRL1_PROPSEG_WIDTH 3
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK 0x8u
#define CAN_CTRL1_LOM_SHIFT 3
#define CAN_CTRL1_LOM_WIDTH 1
#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
#define CAN_CTRL1_LBUF_MASK 0x10u
#define CAN_CTRL1_LBUF_SHIFT 4
#define CAN_CTRL1_LBUF_WIDTH 1
#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
#define CAN_CTRL1_TSYN_MASK 0x20u
#define CAN_CTRL1_TSYN_SHIFT 5
#define CAN_CTRL1_TSYN_WIDTH 1
#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
#define CAN_CTRL1_BOFFREC_MASK 0x40u
#define CAN_CTRL1_BOFFREC_SHIFT 6
#define CAN_CTRL1_BOFFREC_WIDTH 1
#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
#define CAN_CTRL1_SMP_MASK 0x80u
#define CAN_CTRL1_SMP_SHIFT 7
#define CAN_CTRL1_SMP_WIDTH 1
#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
#define CAN_CTRL1_RWRNMSK_MASK 0x400u
#define CAN_CTRL1_RWRNMSK_SHIFT 10
#define CAN_CTRL1_RWRNMSK_WIDTH 1
#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
#define CAN_CTRL1_TWRNMSK_MASK 0x800u
#define CAN_CTRL1_TWRNMSK_SHIFT 11
#define CAN_CTRL1_TWRNMSK_WIDTH 1
#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
#define CAN_CTRL1_LPB_MASK 0x1000u
#define CAN_CTRL1_LPB_SHIFT 12
#define CAN_CTRL1_LPB_WIDTH 1
#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
#define CAN_CTRL1_CLKSRC_MASK 0x2000u
#define CAN_CTRL1_CLKSRC_SHIFT 13
#define CAN_CTRL1_CLKSRC_WIDTH 1
#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
#define CAN_CTRL1_ERRMSK_MASK 0x4000u
#define CAN_CTRL1_ERRMSK_SHIFT 14
#define CAN_CTRL1_ERRMSK_WIDTH 1
#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
#define CAN_CTRL1_BOFFMSK_SHIFT 15
#define CAN_CTRL1_BOFFMSK_WIDTH 1
#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
#define CAN_CTRL1_PSEG2_MASK 0x70000u
#define CAN_CTRL1_PSEG2_SHIFT 16
#define CAN_CTRL1_PSEG2_WIDTH 3
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK 0x380000u
#define CAN_CTRL1_PSEG1_SHIFT 19
#define CAN_CTRL1_PSEG1_WIDTH 3
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK 0xC00000u
#define CAN_CTRL1_RJW_SHIFT 22
#define CAN_CTRL1_RJW_WIDTH 2
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
#define CAN_CTRL1_PRESDIV_SHIFT 24
#define CAN_CTRL1_PRESDIV_WIDTH 8
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
/* TIMER Bit Fields */
#define CAN_TIMER_TIMER_MASK 0xFFFFu
#define CAN_TIMER_TIMER_SHIFT 0
#define CAN_TIMER_TIMER_WIDTH 16
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
/* RXMGMASK Bit Fields */
#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
#define CAN_RXMGMASK_MG_SHIFT 0
#define CAN_RXMGMASK_MG_WIDTH 32
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
/* RX14MASK Bit Fields */
#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
#define CAN_RX14MASK_RX14M_SHIFT 0
#define CAN_RX14MASK_RX14M_WIDTH 32
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
/* RX15MASK Bit Fields */
#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
#define CAN_RX15MASK_RX15M_SHIFT 0
#define CAN_RX15MASK_RX15M_WIDTH 32
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
/* ECR Bit Fields */
#define CAN_ECR_TXERRCNT_MASK 0xFFu
#define CAN_ECR_TXERRCNT_SHIFT 0
#define CAN_ECR_TXERRCNT_WIDTH 8
#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK 0xFF00u
#define CAN_ECR_RXERRCNT_SHIFT 8
#define CAN_ECR_RXERRCNT_WIDTH 8
#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
/* ESR1 Bit Fields */
#define CAN_ESR1_WAKINT_MASK 0x1u
#define CAN_ESR1_WAKINT_SHIFT 0
#define CAN_ESR1_WAKINT_WIDTH 1
#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
#define CAN_ESR1_ERRINT_MASK 0x2u
#define CAN_ESR1_ERRINT_SHIFT 1
#define CAN_ESR1_ERRINT_WIDTH 1
#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
#define CAN_ESR1_BOFFINT_MASK 0x4u
#define CAN_ESR1_BOFFINT_SHIFT 2
#define CAN_ESR1_BOFFINT_WIDTH 1
#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
#define CAN_ESR1_RX_MASK 0x8u
#define CAN_ESR1_RX_SHIFT 3
#define CAN_ESR1_RX_WIDTH 1
#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
#define CAN_ESR1_FLTCONF_MASK 0x30u
#define CAN_ESR1_FLTCONF_SHIFT 4
#define CAN_ESR1_FLTCONF_WIDTH 2
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK 0x40u
#define CAN_ESR1_TX_SHIFT 6
#define CAN_ESR1_TX_WIDTH 1
#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
#define CAN_ESR1_IDLE_MASK 0x80u
#define CAN_ESR1_IDLE_SHIFT 7
#define CAN_ESR1_IDLE_WIDTH 1
#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
#define CAN_ESR1_RXWRN_MASK 0x100u
#define CAN_ESR1_RXWRN_SHIFT 8
#define CAN_ESR1_RXWRN_WIDTH 1
#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
#define CAN_ESR1_TXWRN_MASK 0x200u
#define CAN_ESR1_TXWRN_SHIFT 9
#define CAN_ESR1_TXWRN_WIDTH 1
#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
#define CAN_ESR1_STFERR_MASK 0x400u
#define CAN_ESR1_STFERR_SHIFT 10
#define CAN_ESR1_STFERR_WIDTH 1
#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
#define CAN_ESR1_FRMERR_MASK 0x800u
#define CAN_ESR1_FRMERR_SHIFT 11
#define CAN_ESR1_FRMERR_WIDTH 1
#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
#define CAN_ESR1_CRCERR_MASK 0x1000u
#define CAN_ESR1_CRCERR_SHIFT 12
#define CAN_ESR1_CRCERR_WIDTH 1
#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
#define CAN_ESR1_ACKERR_MASK 0x2000u
#define CAN_ESR1_ACKERR_SHIFT 13
#define CAN_ESR1_ACKERR_WIDTH 1
#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
#define CAN_ESR1_BIT0ERR_MASK 0x4000u
#define CAN_ESR1_BIT0ERR_SHIFT 14
#define CAN_ESR1_BIT0ERR_WIDTH 1
#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
#define CAN_ESR1_BIT1ERR_MASK 0x8000u
#define CAN_ESR1_BIT1ERR_SHIFT 15
#define CAN_ESR1_BIT1ERR_WIDTH 1
#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
#define CAN_ESR1_RWRNINT_MASK 0x10000u
#define CAN_ESR1_RWRNINT_SHIFT 16
#define CAN_ESR1_RWRNINT_WIDTH 1
#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
#define CAN_ESR1_TWRNINT_MASK 0x20000u
#define CAN_ESR1_TWRNINT_SHIFT 17
#define CAN_ESR1_TWRNINT_WIDTH 1
#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
#define CAN_ESR1_SYNCH_MASK 0x40000u
#define CAN_ESR1_SYNCH_SHIFT 18
#define CAN_ESR1_SYNCH_WIDTH 1
#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
#define CAN_ESR1_BOFFDONEINT_MASK 0x80000u
#define CAN_ESR1_BOFFDONEINT_SHIFT 19
#define CAN_ESR1_BOFFDONEINT_WIDTH 1
#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFDONEINT_SHIFT))&CAN_ESR1_BOFFDONEINT_MASK)
#define CAN_ESR1_ERROVR_MASK 0x200000u
#define CAN_ESR1_ERROVR_SHIFT 21
#define CAN_ESR1_ERROVR_WIDTH 1
#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERROVR_SHIFT))&CAN_ESR1_ERROVR_MASK)
/* IMASK1 Bit Fields */
#define CAN_IMASK1_BUF31TO0M_MASK 0xFFFFFFFFu
#define CAN_IMASK1_BUF31TO0M_SHIFT 0
#define CAN_IMASK1_BUF31TO0M_WIDTH 32
#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31TO0M_SHIFT))&CAN_IMASK1_BUF31TO0M_MASK)
/* IFLAG1 Bit Fields */
#define CAN_IFLAG1_BUF0I_MASK 0x1u
#define CAN_IFLAG1_BUF0I_SHIFT 0
#define CAN_IFLAG1_BUF0I_WIDTH 1
#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
#define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
#define CAN_IFLAG1_BUF4TO1I_SHIFT 1
#define CAN_IFLAG1_BUF4TO1I_WIDTH 4
#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
#define CAN_IFLAG1_BUF5I_MASK 0x20u
#define CAN_IFLAG1_BUF5I_SHIFT 5
#define CAN_IFLAG1_BUF5I_WIDTH 1
#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
#define CAN_IFLAG1_BUF6I_MASK 0x40u
#define CAN_IFLAG1_BUF6I_SHIFT 6
#define CAN_IFLAG1_BUF6I_WIDTH 1
#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
#define CAN_IFLAG1_BUF7I_MASK 0x80u
#define CAN_IFLAG1_BUF7I_SHIFT 7
#define CAN_IFLAG1_BUF7I_WIDTH 1
#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
#define CAN_IFLAG1_BUF31TO8I_WIDTH 24
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
/* CTRL2 Bit Fields */
#define CAN_CTRL2_EACEN_MASK 0x10000u
#define CAN_CTRL2_EACEN_SHIFT 16
#define CAN_CTRL2_EACEN_WIDTH 1
#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
#define CAN_CTRL2_RRS_MASK 0x20000u
#define CAN_CTRL2_RRS_SHIFT 17
#define CAN_CTRL2_RRS_WIDTH 1
#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
#define CAN_CTRL2_MRP_MASK 0x40000u
#define CAN_CTRL2_MRP_SHIFT 18
#define CAN_CTRL2_MRP_WIDTH 1
#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
#define CAN_CTRL2_TASD_MASK 0xF80000u
#define CAN_CTRL2_TASD_SHIFT 19
#define CAN_CTRL2_TASD_WIDTH 5
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK 0xF000000u
#define CAN_CTRL2_RFFN_SHIFT 24
#define CAN_CTRL2_RFFN_WIDTH 4
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_BOFFDONEMSK_MASK 0x40000000u
#define CAN_CTRL2_BOFFDONEMSK_SHIFT 30
#define CAN_CTRL2_BOFFDONEMSK_WIDTH 1
#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_BOFFDONEMSK_SHIFT))&CAN_CTRL2_BOFFDONEMSK_MASK)
/* ESR2 Bit Fields */
#define CAN_ESR2_IMB_MASK 0x2000u
#define CAN_ESR2_IMB_SHIFT 13
#define CAN_ESR2_IMB_WIDTH 1
#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
#define CAN_ESR2_VPS_MASK 0x4000u
#define CAN_ESR2_VPS_SHIFT 14
#define CAN_ESR2_VPS_WIDTH 1
#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
#define CAN_ESR2_LPTM_MASK 0x7F0000u
#define CAN_ESR2_LPTM_SHIFT 16
#define CAN_ESR2_LPTM_WIDTH 7
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
/* CRCR Bit Fields */
#define CAN_CRCR_TXCRC_MASK 0x7FFFu
#define CAN_CRCR_TXCRC_SHIFT 0
#define CAN_CRCR_TXCRC_WIDTH 15
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK 0x7F0000u
#define CAN_CRCR_MBCRC_SHIFT 16
#define CAN_CRCR_MBCRC_WIDTH 7
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
/* RXFGMASK Bit Fields */
#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
#define CAN_RXFGMASK_FGM_SHIFT 0
#define CAN_RXFGMASK_FGM_WIDTH 32
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
/* RXFIR Bit Fields */
#define CAN_RXFIR_IDHIT_MASK 0x1FFu
#define CAN_RXFIR_IDHIT_SHIFT 0
#define CAN_RXFIR_IDHIT_WIDTH 9
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
/* CBT Bit Fields */
#define CAN_CBT_EPSEG2_MASK 0x1Fu
#define CAN_CBT_EPSEG2_SHIFT 0
#define CAN_CBT_EPSEG2_WIDTH 5
#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG2_SHIFT))&CAN_CBT_EPSEG2_MASK)
#define CAN_CBT_EPSEG1_MASK 0x3E0u
#define CAN_CBT_EPSEG1_SHIFT 5
#define CAN_CBT_EPSEG1_WIDTH 5
#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG1_SHIFT))&CAN_CBT_EPSEG1_MASK)
#define CAN_CBT_EPROPSEG_MASK 0xFC00u
#define CAN_CBT_EPROPSEG_SHIFT 10
#define CAN_CBT_EPROPSEG_WIDTH 6
#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPROPSEG_SHIFT))&CAN_CBT_EPROPSEG_MASK)
#define CAN_CBT_ERJW_MASK 0xF0000u
#define CAN_CBT_ERJW_SHIFT 16
#define CAN_CBT_ERJW_WIDTH 4
#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_ERJW_SHIFT))&CAN_CBT_ERJW_MASK)
#define CAN_CBT_EPRESDIV_MASK 0x7FE00000u
#define CAN_CBT_EPRESDIV_SHIFT 21
#define CAN_CBT_EPRESDIV_WIDTH 10
#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPRESDIV_SHIFT))&CAN_CBT_EPRESDIV_MASK)
#define CAN_CBT_BTF_MASK 0x80000000u
#define CAN_CBT_BTF_SHIFT 31
#define CAN_CBT_BTF_WIDTH 1
#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_BTF_SHIFT))&CAN_CBT_BTF_MASK)
/* CS Bit Fields */
#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
#define CAN_CS_TIME_STAMP_SHIFT 0
#define CAN_CS_TIME_STAMP_WIDTH 16
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK 0xF0000u
#define CAN_CS_DLC_SHIFT 16
#define CAN_CS_DLC_WIDTH 4
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK 0x100000u
#define CAN_CS_RTR_SHIFT 20
#define CAN_CS_RTR_WIDTH 1
#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
#define CAN_CS_IDE_MASK 0x200000u
#define CAN_CS_IDE_SHIFT 21
#define CAN_CS_IDE_WIDTH 1
#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
#define CAN_CS_SRR_MASK 0x400000u
#define CAN_CS_SRR_SHIFT 22
#define CAN_CS_SRR_WIDTH 1
#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
#define CAN_CS_CODE_MASK 0xF000000u
#define CAN_CS_CODE_SHIFT 24
#define CAN_CS_CODE_WIDTH 4
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
/* ID Bit Fields */
#define CAN_ID_EXT_MASK 0x3FFFFu
#define CAN_ID_EXT_SHIFT 0
#define CAN_ID_EXT_WIDTH 18
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK 0x1FFC0000u
#define CAN_ID_STD_SHIFT 18
#define CAN_ID_STD_WIDTH 11
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK 0xE0000000u
#define CAN_ID_PRIO_SHIFT 29
#define CAN_ID_PRIO_WIDTH 3
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
/* WORD0 Bit Fields */
#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
#define CAN_WORD0_DATA_BYTE_3_WIDTH 8
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
#define CAN_WORD0_DATA_BYTE_2_WIDTH 8
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
#define CAN_WORD0_DATA_BYTE_1_WIDTH 8
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
#define CAN_WORD0_DATA_BYTE_0_WIDTH 8
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
/* WORD1 Bit Fields */
#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
#define CAN_WORD1_DATA_BYTE_7_WIDTH 8
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
#define CAN_WORD1_DATA_BYTE_6_WIDTH 8
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
#define CAN_WORD1_DATA_BYTE_5_WIDTH 8
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
#define CAN_WORD1_DATA_BYTE_4_WIDTH 8
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
/* RXIMR Bit Fields */
#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
#define CAN_RXIMR_MI_SHIFT 0
#define CAN_RXIMR_MI_WIDTH 32
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
/*!
* @}
*/ /* end of group CAN_Register_Masks */
/* CAN - Peripheral instance base addresses */
/** Peripheral CAN0 base address */
#define CAN0_BASE (0x40024000u)
/** Peripheral CAN0 base pointer */
#define CAN0 ((CAN_Type *)CAN0_BASE)
#define CAN0_BASE_PTR (CAN0)
/** Peripheral CAN1 base address */
#define CAN1_BASE (0x40025000u)
/** Peripheral CAN1 base pointer */
#define CAN1 ((CAN_Type *)CAN1_BASE)
#define CAN1_BASE_PTR (CAN1)
/** Array initializer of CAN peripheral base addresses */
#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASE_PTRS { CAN0, CAN1 }
/* ----------------------------------------------------------------------------
-- CAN - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
* @{
*/
/* CAN - Register instance definitions */
/* CAN0 */
#define CAN0_MCR CAN_MCR_REG(CAN0)
#define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
#define CAN0_TIMER CAN_TIMER_REG(CAN0)
#define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
#define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
#define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
#define CAN0_ECR CAN_ECR_REG(CAN0)
#define CAN0_ESR1 CAN_ESR1_REG(CAN0)
#define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
#define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
#define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
#define CAN0_ESR2 CAN_ESR2_REG(CAN0)
#define CAN0_CRCR CAN_CRCR_REG(CAN0)
#define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
#define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
#define CAN0_CBT CAN_CBT_REG(CAN0)
#define CAN0_CS0 CAN_CS_REG(CAN0,0)
#define CAN0_ID0 CAN_ID_REG(CAN0,0)
#define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
#define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
#define CAN0_CS1 CAN_CS_REG(CAN0,1)
#define CAN0_ID1 CAN_ID_REG(CAN0,1)
#define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
#define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
#define CAN0_CS2 CAN_CS_REG(CAN0,2)
#define CAN0_ID2 CAN_ID_REG(CAN0,2)
#define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
#define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
#define CAN0_CS3 CAN_CS_REG(CAN0,3)
#define CAN0_ID3 CAN_ID_REG(CAN0,3)
#define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
#define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
#define CAN0_CS4 CAN_CS_REG(CAN0,4)
#define CAN0_ID4 CAN_ID_REG(CAN0,4)
#define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
#define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
#define CAN0_CS5 CAN_CS_REG(CAN0,5)
#define CAN0_ID5 CAN_ID_REG(CAN0,5)
#define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
#define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
#define CAN0_CS6 CAN_CS_REG(CAN0,6)
#define CAN0_ID6 CAN_ID_REG(CAN0,6)
#define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
#define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
#define CAN0_CS7 CAN_CS_REG(CAN0,7)
#define CAN0_ID7 CAN_ID_REG(CAN0,7)
#define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
#define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
#define CAN0_CS8 CAN_CS_REG(CAN0,8)
#define CAN0_ID8 CAN_ID_REG(CAN0,8)
#define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
#define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
#define CAN0_CS9 CAN_CS_REG(CAN0,9)
#define CAN0_ID9 CAN_ID_REG(CAN0,9)
#define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
#define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
#define CAN0_CS10 CAN_CS_REG(CAN0,10)
#define CAN0_ID10 CAN_ID_REG(CAN0,10)
#define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
#define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
#define CAN0_CS11 CAN_CS_REG(CAN0,11)
#define CAN0_ID11 CAN_ID_REG(CAN0,11)
#define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
#define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
#define CAN0_CS12 CAN_CS_REG(CAN0,12)
#define CAN0_ID12 CAN_ID_REG(CAN0,12)
#define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
#define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
#define CAN0_CS13 CAN_CS_REG(CAN0,13)
#define CAN0_ID13 CAN_ID_REG(CAN0,13)
#define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
#define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
#define CAN0_CS14 CAN_CS_REG(CAN0,14)
#define CAN0_ID14 CAN_ID_REG(CAN0,14)
#define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
#define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
#define CAN0_CS15 CAN_CS_REG(CAN0,15)
#define CAN0_ID15 CAN_ID_REG(CAN0,15)
#define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
#define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
#define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
#define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
#define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
#define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
#define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
#define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
#define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
#define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
#define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
#define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
#define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
#define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
#define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
#define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
#define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
#define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
/* CAN1 */
#define CAN1_MCR CAN_MCR_REG(CAN1)
#define CAN1_CTRL1 CAN_CTRL1_REG(CAN1)
#define CAN1_TIMER CAN_TIMER_REG(CAN1)
#define CAN1_RXMGMASK CAN_RXMGMASK_REG(CAN1)
#define CAN1_RX14MASK CAN_RX14MASK_REG(CAN1)
#define CAN1_RX15MASK CAN_RX15MASK_REG(CAN1)
#define CAN1_ECR CAN_ECR_REG(CAN1)
#define CAN1_ESR1 CAN_ESR1_REG(CAN1)
#define CAN1_IMASK1 CAN_IMASK1_REG(CAN1)
#define CAN1_IFLAG1 CAN_IFLAG1_REG(CAN1)
#define CAN1_CTRL2 CAN_CTRL2_REG(CAN1)
#define CAN1_ESR2 CAN_ESR2_REG(CAN1)
#define CAN1_CRCR CAN_CRCR_REG(CAN1)
#define CAN1_RXFGMASK CAN_RXFGMASK_REG(CAN1)
#define CAN1_RXFIR CAN_RXFIR_REG(CAN1)
#define CAN1_CBT CAN_CBT_REG(CAN1)
#define CAN1_CS0 CAN_CS_REG(CAN1,0)
#define CAN1_ID0 CAN_ID_REG(CAN1,0)
#define CAN1_WORD00 CAN_WORD0_REG(CAN1,0)
#define CAN1_WORD10 CAN_WORD1_REG(CAN1,0)
#define CAN1_CS1 CAN_CS_REG(CAN1,1)
#define CAN1_ID1 CAN_ID_REG(CAN1,1)
#define CAN1_WORD01 CAN_WORD0_REG(CAN1,1)
#define CAN1_WORD11 CAN_WORD1_REG(CAN1,1)
#define CAN1_CS2 CAN_CS_REG(CAN1,2)
#define CAN1_ID2 CAN_ID_REG(CAN1,2)
#define CAN1_WORD02 CAN_WORD0_REG(CAN1,2)
#define CAN1_WORD12 CAN_WORD1_REG(CAN1,2)
#define CAN1_CS3 CAN_CS_REG(CAN1,3)
#define CAN1_ID3 CAN_ID_REG(CAN1,3)
#define CAN1_WORD03 CAN_WORD0_REG(CAN1,3)
#define CAN1_WORD13 CAN_WORD1_REG(CAN1,3)
#define CAN1_CS4 CAN_CS_REG(CAN1,4)
#define CAN1_ID4 CAN_ID_REG(CAN1,4)
#define CAN1_WORD04 CAN_WORD0_REG(CAN1,4)
#define CAN1_WORD14 CAN_WORD1_REG(CAN1,4)
#define CAN1_CS5 CAN_CS_REG(CAN1,5)
#define CAN1_ID5 CAN_ID_REG(CAN1,5)
#define CAN1_WORD05 CAN_WORD0_REG(CAN1,5)
#define CAN1_WORD15 CAN_WORD1_REG(CAN1,5)
#define CAN1_CS6 CAN_CS_REG(CAN1,6)
#define CAN1_ID6 CAN_ID_REG(CAN1,6)
#define CAN1_WORD06 CAN_WORD0_REG(CAN1,6)
#define CAN1_WORD16 CAN_WORD1_REG(CAN1,6)
#define CAN1_CS7 CAN_CS_REG(CAN1,7)
#define CAN1_ID7 CAN_ID_REG(CAN1,7)
#define CAN1_WORD07 CAN_WORD0_REG(CAN1,7)
#define CAN1_WORD17 CAN_WORD1_REG(CAN1,7)
#define CAN1_CS8 CAN_CS_REG(CAN1,8)
#define CAN1_ID8 CAN_ID_REG(CAN1,8)
#define CAN1_WORD08 CAN_WORD0_REG(CAN1,8)
#define CAN1_WORD18 CAN_WORD1_REG(CAN1,8)
#define CAN1_CS9 CAN_CS_REG(CAN1,9)
#define CAN1_ID9 CAN_ID_REG(CAN1,9)
#define CAN1_WORD09 CAN_WORD0_REG(CAN1,9)
#define CAN1_WORD19 CAN_WORD1_REG(CAN1,9)
#define CAN1_CS10 CAN_CS_REG(CAN1,10)
#define CAN1_ID10 CAN_ID_REG(CAN1,10)
#define CAN1_WORD010 CAN_WORD0_REG(CAN1,10)
#define CAN1_WORD110 CAN_WORD1_REG(CAN1,10)
#define CAN1_CS11 CAN_CS_REG(CAN1,11)
#define CAN1_ID11 CAN_ID_REG(CAN1,11)
#define CAN1_WORD011 CAN_WORD0_REG(CAN1,11)
#define CAN1_WORD111 CAN_WORD1_REG(CAN1,11)
#define CAN1_CS12 CAN_CS_REG(CAN1,12)
#define CAN1_ID12 CAN_ID_REG(CAN1,12)
#define CAN1_WORD012 CAN_WORD0_REG(CAN1,12)
#define CAN1_WORD112 CAN_WORD1_REG(CAN1,12)
#define CAN1_CS13 CAN_CS_REG(CAN1,13)
#define CAN1_ID13 CAN_ID_REG(CAN1,13)
#define CAN1_WORD013 CAN_WORD0_REG(CAN1,13)
#define CAN1_WORD113 CAN_WORD1_REG(CAN1,13)
#define CAN1_CS14 CAN_CS_REG(CAN1,14)
#define CAN1_ID14 CAN_ID_REG(CAN1,14)
#define CAN1_WORD014 CAN_WORD0_REG(CAN1,14)
#define CAN1_WORD114 CAN_WORD1_REG(CAN1,14)
#define CAN1_CS15 CAN_CS_REG(CAN1,15)
#define CAN1_ID15 CAN_ID_REG(CAN1,15)
#define CAN1_WORD015 CAN_WORD0_REG(CAN1,15)
#define CAN1_WORD115 CAN_WORD1_REG(CAN1,15)
#define CAN1_RXIMR0 CAN_RXIMR_REG(CAN1,0)
#define CAN1_RXIMR1 CAN_RXIMR_REG(CAN1,1)
#define CAN1_RXIMR2 CAN_RXIMR_REG(CAN1,2)
#define CAN1_RXIMR3 CAN_RXIMR_REG(CAN1,3)
#define CAN1_RXIMR4 CAN_RXIMR_REG(CAN1,4)
#define CAN1_RXIMR5 CAN_RXIMR_REG(CAN1,5)
#define CAN1_RXIMR6 CAN_RXIMR_REG(CAN1,6)
#define CAN1_RXIMR7 CAN_RXIMR_REG(CAN1,7)
#define CAN1_RXIMR8 CAN_RXIMR_REG(CAN1,8)
#define CAN1_RXIMR9 CAN_RXIMR_REG(CAN1,9)
#define CAN1_RXIMR10 CAN_RXIMR_REG(CAN1,10)
#define CAN1_RXIMR11 CAN_RXIMR_REG(CAN1,11)
#define CAN1_RXIMR12 CAN_RXIMR_REG(CAN1,12)
#define CAN1_RXIMR13 CAN_RXIMR_REG(CAN1,13)
#define CAN1_RXIMR14 CAN_RXIMR_REG(CAN1,14)
#define CAN1_RXIMR15 CAN_RXIMR_REG(CAN1,15)
/* CAN - Register array accessors */
#define CAN0_CS(index) CAN_CS_REG(CAN0,index)
#define CAN1_CS(index) CAN_CS_REG(CAN1,index)
#define CAN0_ID(index) CAN_ID_REG(CAN0,index)
#define CAN1_ID(index) CAN_ID_REG(CAN1,index)
#define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
#define CAN1_WORD0(index) CAN_WORD0_REG(CAN1,index)
#define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
#define CAN1_WORD1(index) CAN_WORD1_REG(CAN1,index)
#define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
#define CAN1_RXIMR(index) CAN_RXIMR_REG(CAN1,index)
/*!
* @}
*/ /* end of group CAN_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CAN_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Register Layout Typedef */
typedef struct {
__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} CMP_Type, *CMP_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register accessors */
#define CMP_CR0_REG(base) ((base)->CR0)
#define CMP_CR1_REG(base) ((base)->CR1)
#define CMP_FPR_REG(base) ((base)->FPR)
#define CMP_SCR_REG(base) ((base)->SCR)
#define CMP_DACCR_REG(base) ((base)->DACCR)
#define CMP_MUXCR_REG(base) ((base)->MUXCR)
/*!
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/* CR0 Bit Fields */
#define CMP_CR0_HYSTCTR_MASK 0x3u
#define CMP_CR0_HYSTCTR_SHIFT 0
#define CMP_CR0_HYSTCTR_WIDTH 2
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK 0x70u
#define CMP_CR0_FILTER_CNT_SHIFT 4
#define CMP_CR0_FILTER_CNT_WIDTH 3
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
/* CR1 Bit Fields */
#define CMP_CR1_EN_MASK 0x1u
#define CMP_CR1_EN_SHIFT 0
#define CMP_CR1_EN_WIDTH 1
#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
#define CMP_CR1_OPE_MASK 0x2u
#define CMP_CR1_OPE_SHIFT 1
#define CMP_CR1_OPE_WIDTH 1
#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
#define CMP_CR1_COS_MASK 0x4u
#define CMP_CR1_COS_SHIFT 2
#define CMP_CR1_COS_WIDTH 1
#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
#define CMP_CR1_INV_MASK 0x8u
#define CMP_CR1_INV_SHIFT 3
#define CMP_CR1_INV_WIDTH 1
#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
#define CMP_CR1_PMODE_MASK 0x10u
#define CMP_CR1_PMODE_SHIFT 4
#define CMP_CR1_PMODE_WIDTH 1
#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
#define CMP_CR1_TRIGM_MASK 0x20u
#define CMP_CR1_TRIGM_SHIFT 5
#define CMP_CR1_TRIGM_WIDTH 1
#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_TRIGM_SHIFT))&CMP_CR1_TRIGM_MASK)
#define CMP_CR1_WE_MASK 0x40u
#define CMP_CR1_WE_SHIFT 6
#define CMP_CR1_WE_WIDTH 1
#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
#define CMP_CR1_SE_MASK 0x80u
#define CMP_CR1_SE_SHIFT 7
#define CMP_CR1_SE_WIDTH 1
#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
/* FPR Bit Fields */
#define CMP_FPR_FILT_PER_MASK 0xFFu
#define CMP_FPR_FILT_PER_SHIFT 0
#define CMP_FPR_FILT_PER_WIDTH 8
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
/* SCR Bit Fields */
#define CMP_SCR_COUT_MASK 0x1u
#define CMP_SCR_COUT_SHIFT 0
#define CMP_SCR_COUT_WIDTH 1
#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
#define CMP_SCR_CFF_MASK 0x2u
#define CMP_SCR_CFF_SHIFT 1
#define CMP_SCR_CFF_WIDTH 1
#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
#define CMP_SCR_CFR_MASK 0x4u
#define CMP_SCR_CFR_SHIFT 2
#define CMP_SCR_CFR_WIDTH 1
#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
#define CMP_SCR_IEF_MASK 0x8u
#define CMP_SCR_IEF_SHIFT 3
#define CMP_SCR_IEF_WIDTH 1
#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
#define CMP_SCR_IER_MASK 0x10u
#define CMP_SCR_IER_SHIFT 4
#define CMP_SCR_IER_WIDTH 1
#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
#define CMP_SCR_DMAEN_MASK 0x40u
#define CMP_SCR_DMAEN_SHIFT 6
#define CMP_SCR_DMAEN_WIDTH 1
#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
/* DACCR Bit Fields */
#define CMP_DACCR_VOSEL_MASK 0x3Fu
#define CMP_DACCR_VOSEL_SHIFT 0
#define CMP_DACCR_VOSEL_WIDTH 6
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK 0x40u
#define CMP_DACCR_VRSEL_SHIFT 6
#define CMP_DACCR_VRSEL_WIDTH 1
#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
#define CMP_DACCR_DACEN_MASK 0x80u
#define CMP_DACCR_DACEN_SHIFT 7
#define CMP_DACCR_DACEN_WIDTH 1
#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
/* MUXCR Bit Fields */
#define CMP_MUXCR_MSEL_MASK 0x7u
#define CMP_MUXCR_MSEL_SHIFT 0
#define CMP_MUXCR_MSEL_WIDTH 3
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK 0x38u
#define CMP_MUXCR_PSEL_SHIFT 3
#define CMP_MUXCR_PSEL_WIDTH 3
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base address */
#define CMP0_BASE (0x40073000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
#define CMP0_BASE_PTR (CMP0)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { CMP0_BASE }
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS { CMP0 }
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register instance definitions */
/* CMP0 */
#define CMP0_CR0 CMP_CR0_REG(CMP0)
#define CMP0_CR1 CMP_CR1_REG(CMP0)
#define CMP0_FPR CMP_FPR_REG(CMP0)
#define CMP0_SCR CMP_SCR_REG(CMP0)
#define CMP0_DACCR CMP_DACCR_REG(CMP0)
#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
/*!
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
* @{
*/
/** CRC - Register Layout Typedef */
typedef struct {
union { /* offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
__IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
} ACCESS16BIT;
__IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
__IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
__IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
__IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
} ACCESS8BIT;
};
union { /* offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
__IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
} GPOLY_ACCESS16BIT;
__IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
__IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
__IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
__IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
} GPOLY_ACCESS8BIT;
};
union { /* offset: 0x8 */
__IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
struct { /* offset: 0x8 */
uint8_t RESERVED_0[3];
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
} CRC_Type, *CRC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CRC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
* @{
*/
/* CRC - Register accessors */
#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
#define CRC_DATA_REG(base) ((base)->DATA)
#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
#define CRC_GPOLY_REG(base) ((base)->GPOLY)
#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
#define CRC_CTRL_REG(base) ((base)->CTRL)
#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
/*!
* @}
*/ /* end of group CRC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/* DATAL Bit Fields */
#define CRC_DATAL_DATAL_MASK 0xFFFFu
#define CRC_DATAL_DATAL_SHIFT 0
#define CRC_DATAL_DATAL_WIDTH 16
#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
/* DATAH Bit Fields */
#define CRC_DATAH_DATAH_MASK 0xFFFFu
#define CRC_DATAH_DATAH_SHIFT 0
#define CRC_DATAH_DATAH_WIDTH 16
#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
/* DATA Bit Fields */
#define CRC_DATA_LL_MASK 0xFFu
#define CRC_DATA_LL_SHIFT 0
#define CRC_DATA_LL_WIDTH 8
#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
#define CRC_DATA_LU_MASK 0xFF00u
#define CRC_DATA_LU_SHIFT 8
#define CRC_DATA_LU_WIDTH 8
#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
#define CRC_DATA_HL_MASK 0xFF0000u
#define CRC_DATA_HL_SHIFT 16
#define CRC_DATA_HL_WIDTH 8
#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
#define CRC_DATA_HU_MASK 0xFF000000u
#define CRC_DATA_HU_SHIFT 24
#define CRC_DATA_HU_WIDTH 8
#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
/* DATALL Bit Fields */
#define CRC_DATALL_DATALL_MASK 0xFFu
#define CRC_DATALL_DATALL_SHIFT 0
#define CRC_DATALL_DATALL_WIDTH 8
#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
/* DATALU Bit Fields */
#define CRC_DATALU_DATALU_MASK 0xFFu
#define CRC_DATALU_DATALU_SHIFT 0
#define CRC_DATALU_DATALU_WIDTH 8
#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
/* DATAHL Bit Fields */
#define CRC_DATAHL_DATAHL_MASK 0xFFu
#define CRC_DATAHL_DATAHL_SHIFT 0
#define CRC_DATAHL_DATAHL_WIDTH 8
#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
/* DATAHU Bit Fields */
#define CRC_DATAHU_DATAHU_MASK 0xFFu
#define CRC_DATAHU_DATAHU_SHIFT 0
#define CRC_DATAHU_DATAHU_WIDTH 8
#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
/* GPOLYL Bit Fields */
#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
#define CRC_GPOLYL_GPOLYL_SHIFT 0
#define CRC_GPOLYL_GPOLYL_WIDTH 16
#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
/* GPOLYH Bit Fields */
#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
#define CRC_GPOLYH_GPOLYH_SHIFT 0
#define CRC_GPOLYH_GPOLYH_WIDTH 16
#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
/* GPOLY Bit Fields */
#define CRC_GPOLY_LOW_MASK 0xFFFFu
#define CRC_GPOLY_LOW_SHIFT 0
#define CRC_GPOLY_LOW_WIDTH 16
#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
#define CRC_GPOLY_HIGH_SHIFT 16
#define CRC_GPOLY_HIGH_WIDTH 16
#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
/* GPOLYLL Bit Fields */
#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
#define CRC_GPOLYLL_GPOLYLL_WIDTH 8
#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
/* GPOLYLU Bit Fields */
#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
#define CRC_GPOLYLU_GPOLYLU_WIDTH 8
#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
/* GPOLYHL Bit Fields */
#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
#define CRC_GPOLYHL_GPOLYHL_WIDTH 8
#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
/* GPOLYHU Bit Fields */
#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
#define CRC_GPOLYHU_GPOLYHU_WIDTH 8
#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
/* CTRL Bit Fields */
#define CRC_CTRL_TCRC_MASK 0x1000000u
#define CRC_CTRL_TCRC_SHIFT 24
#define CRC_CTRL_TCRC_WIDTH 1
#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
#define CRC_CTRL_WAS_MASK 0x2000000u
#define CRC_CTRL_WAS_SHIFT 25
#define CRC_CTRL_WAS_WIDTH 1
#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
#define CRC_CTRL_FXOR_MASK 0x4000000u
#define CRC_CTRL_FXOR_SHIFT 26
#define CRC_CTRL_FXOR_WIDTH 1
#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
#define CRC_CTRL_TOTR_MASK 0x30000000u
#define CRC_CTRL_TOTR_SHIFT 28
#define CRC_CTRL_TOTR_WIDTH 2
#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
#define CRC_CTRL_TOT_MASK 0xC0000000u
#define CRC_CTRL_TOT_SHIFT 30
#define CRC_CTRL_TOT_WIDTH 2
#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
/* CTRLHU Bit Fields */
#define CRC_CTRLHU_TCRC_MASK 0x1u
#define CRC_CTRLHU_TCRC_SHIFT 0
#define CRC_CTRLHU_TCRC_WIDTH 1
#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
#define CRC_CTRLHU_WAS_MASK 0x2u
#define CRC_CTRLHU_WAS_SHIFT 1
#define CRC_CTRLHU_WAS_WIDTH 1
#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
#define CRC_CTRLHU_FXOR_MASK 0x4u
#define CRC_CTRLHU_FXOR_SHIFT 2
#define CRC_CTRLHU_FXOR_WIDTH 1
#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
#define CRC_CTRLHU_TOTR_MASK 0x30u
#define CRC_CTRLHU_TOTR_SHIFT 4
#define CRC_CTRLHU_TOTR_WIDTH 2
#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
#define CRC_CTRLHU_TOT_MASK 0xC0u
#define CRC_CTRLHU_TOT_SHIFT 6
#define CRC_CTRLHU_TOT_WIDTH 2
#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
/*!
* @}
*/ /* end of group CRC_Register_Masks */
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base address */
#define CRC_BASE (0x40032000u)
/** Peripheral CRC base pointer */
#define CRC0 ((CRC_Type *)CRC_BASE)
#define CRC_BASE_PTR (CRC0)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS { CRC_BASE }
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS { CRC0 }
/* ----------------------------------------------------------------------------
-- CRC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
* @{
*/
/* CRC - Register instance definitions */
/* CRC */
#define CRC_DATA CRC_DATA_REG(CRC0)
#define CRC_DATAL CRC_DATAL_REG(CRC0)
#define CRC_DATALL CRC_DATALL_REG(CRC0)
#define CRC_DATALU CRC_DATALU_REG(CRC0)
#define CRC_DATAH CRC_DATAH_REG(CRC0)
#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
#define CRC_CTRL CRC_CTRL_REG(CRC0)
#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
/*!
* @}
*/ /* end of group CRC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DAC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
* @{
*/
/** DAC - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x2 */
__IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
__IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
} DAT[16];
__IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
} DAC_Type, *DAC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DAC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
* @{
*/
/* DAC - Register accessors */
#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
#define DAC_DATL_COUNT 16
#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
#define DAC_DATH_COUNT 16
#define DAC_SR_REG(base) ((base)->SR)
#define DAC_C0_REG(base) ((base)->C0)
#define DAC_C1_REG(base) ((base)->C1)
#define DAC_C2_REG(base) ((base)->C2)
/*!
* @}
*/ /* end of group DAC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/* DATL Bit Fields */
#define DAC_DATL_DATA0_MASK 0xFFu
#define DAC_DATL_DATA0_SHIFT 0
#define DAC_DATL_DATA0_WIDTH 8
#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
/* DATH Bit Fields */
#define DAC_DATH_DATA1_MASK 0xFu
#define DAC_DATH_DATA1_SHIFT 0
#define DAC_DATH_DATA1_WIDTH 4
#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
/* SR Bit Fields */
#define DAC_SR_DACBFRPBF_MASK 0x1u
#define DAC_SR_DACBFRPBF_SHIFT 0
#define DAC_SR_DACBFRPBF_WIDTH 1
#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
#define DAC_SR_DACBFRPTF_MASK 0x2u
#define DAC_SR_DACBFRPTF_SHIFT 1
#define DAC_SR_DACBFRPTF_WIDTH 1
#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
#define DAC_SR_DACBFWMF_MASK 0x4u
#define DAC_SR_DACBFWMF_SHIFT 2
#define DAC_SR_DACBFWMF_WIDTH 1
#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
/* C0 Bit Fields */
#define DAC_C0_DACBBIEN_MASK 0x1u
#define DAC_C0_DACBBIEN_SHIFT 0
#define DAC_C0_DACBBIEN_WIDTH 1
#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
#define DAC_C0_DACBTIEN_MASK 0x2u
#define DAC_C0_DACBTIEN_SHIFT 1
#define DAC_C0_DACBTIEN_WIDTH 1
#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
#define DAC_C0_DACBWIEN_MASK 0x4u
#define DAC_C0_DACBWIEN_SHIFT 2
#define DAC_C0_DACBWIEN_WIDTH 1
#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
#define DAC_C0_LPEN_MASK 0x8u
#define DAC_C0_LPEN_SHIFT 3
#define DAC_C0_LPEN_WIDTH 1
#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
#define DAC_C0_DACSWTRG_MASK 0x10u
#define DAC_C0_DACSWTRG_SHIFT 4
#define DAC_C0_DACSWTRG_WIDTH 1
#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
#define DAC_C0_DACTRGSEL_MASK 0x20u
#define DAC_C0_DACTRGSEL_SHIFT 5
#define DAC_C0_DACTRGSEL_WIDTH 1
#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
#define DAC_C0_DACRFS_MASK 0x40u
#define DAC_C0_DACRFS_SHIFT 6
#define DAC_C0_DACRFS_WIDTH 1
#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
#define DAC_C0_DACEN_MASK 0x80u
#define DAC_C0_DACEN_SHIFT 7
#define DAC_C0_DACEN_WIDTH 1
#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
/* C1 Bit Fields */
#define DAC_C1_DACBFEN_MASK 0x1u
#define DAC_C1_DACBFEN_SHIFT 0
#define DAC_C1_DACBFEN_WIDTH 1
#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
#define DAC_C1_DACBFMD_MASK 0x6u
#define DAC_C1_DACBFMD_SHIFT 1
#define DAC_C1_DACBFMD_WIDTH 2
#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
#define DAC_C1_DACBFWM_MASK 0x18u
#define DAC_C1_DACBFWM_SHIFT 3
#define DAC_C1_DACBFWM_WIDTH 2
#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
#define DAC_C1_DMAEN_MASK 0x80u
#define DAC_C1_DMAEN_SHIFT 7
#define DAC_C1_DMAEN_WIDTH 1
#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
/* C2 Bit Fields */
#define DAC_C2_DACBFUP_MASK 0xFu
#define DAC_C2_DACBFUP_SHIFT 0
#define DAC_C2_DACBFUP_WIDTH 4
#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
#define DAC_C2_DACBFRP_MASK 0xF0u
#define DAC_C2_DACBFRP_SHIFT 4
#define DAC_C2_DACBFRP_WIDTH 4
#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
/*!
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base address */
#define DAC0_BASE (0x4003F000u)
/** Peripheral DAC0 base pointer */
#define DAC0 ((DAC_Type *)DAC0_BASE)
#define DAC0_BASE_PTR (DAC0)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS { DAC0_BASE }
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASE_PTRS { DAC0 }
/* ----------------------------------------------------------------------------
-- DAC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
* @{
*/
/* DAC - Register instance definitions */
/* DAC0 */
#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
#define DAC0_SR DAC_SR_REG(DAC0)
#define DAC0_C0 DAC_C0_REG(DAC0)
#define DAC0_C1 DAC_C1_REG(DAC0)
#define DAC0_C2 DAC_C2_REG(DAC0)
/* DAC - Register array accessors */
#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
/*!
* @}
*/ /* end of group DAC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< Control Register, offset: 0x0 */
__I uint32_t ES; /**< Error Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
uint8_t RESERVED_1[4];
__IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
__O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
__O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
__O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
__O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
uint8_t RESERVED_2[4];
__IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
uint8_t RESERVED_3[4];
__IO uint32_t ERR; /**< Error Register, offset: 0x2C */
uint8_t RESERVED_4[4];
__I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
uint8_t RESERVED_5[12];
__IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
uint8_t RESERVED_6[184];
__IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
__IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
__IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
__IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
__IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
__IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
__IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
__IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
__IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
__IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
__IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
__IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
__IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
__IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
__IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
__IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
uint8_t RESERVED_7[3824];
struct { /* offset: 0x1000, array step: 0x20 */
__IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
};
__IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
__IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
union { /* offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
};
__IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
union { /* offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[16];
} DMA_Type, *DMA_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DMA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
* @{
*/
/* DMA - Register accessors */
#define DMA_CR_REG(base) ((base)->CR)
#define DMA_ES_REG(base) ((base)->ES)
#define DMA_ERQ_REG(base) ((base)->ERQ)
#define DMA_EEI_REG(base) ((base)->EEI)
#define DMA_CEEI_REG(base) ((base)->CEEI)
#define DMA_SEEI_REG(base) ((base)->SEEI)
#define DMA_CERQ_REG(base) ((base)->CERQ)
#define DMA_SERQ_REG(base) ((base)->SERQ)
#define DMA_CDNE_REG(base) ((base)->CDNE)
#define DMA_SSRT_REG(base) ((base)->SSRT)
#define DMA_CERR_REG(base) ((base)->CERR)
#define DMA_CINT_REG(base) ((base)->CINT)
#define DMA_INT_REG(base) ((base)->INT)
#define DMA_ERR_REG(base) ((base)->ERR)
#define DMA_HRS_REG(base) ((base)->HRS)
#define DMA_EARS_REG(base) ((base)->EARS)
#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
#define DMA_SADDR_COUNT 16
#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
#define DMA_SOFF_COUNT 16
#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
#define DMA_ATTR_COUNT 16
#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
#define DMA_NBYTES_MLNO_COUNT 16
#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
#define DMA_NBYTES_MLOFFNO_COUNT 16
#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
#define DMA_NBYTES_MLOFFYES_COUNT 16
#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
#define DMA_SLAST_COUNT 16
#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
#define DMA_DADDR_COUNT 16
#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
#define DMA_DOFF_COUNT 16
#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
#define DMA_CITER_ELINKNO_COUNT 16
#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
#define DMA_CITER_ELINKYES_COUNT 16
#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
#define DMA_DLAST_SGA_COUNT 16
#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
#define DMA_CSR_COUNT 16
#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
#define DMA_BITER_ELINKNO_COUNT 16
#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
#define DMA_BITER_ELINKYES_COUNT 16
/*!
* @}
*/ /* end of group DMA_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/* CR Bit Fields */
#define DMA_CR_EDBG_MASK 0x2u
#define DMA_CR_EDBG_SHIFT 1
#define DMA_CR_EDBG_WIDTH 1
#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
#define DMA_CR_ERCA_MASK 0x4u
#define DMA_CR_ERCA_SHIFT 2
#define DMA_CR_ERCA_WIDTH 1
#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
#define DMA_CR_HOE_MASK 0x10u
#define DMA_CR_HOE_SHIFT 4
#define DMA_CR_HOE_WIDTH 1
#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
#define DMA_CR_HALT_MASK 0x20u
#define DMA_CR_HALT_SHIFT 5
#define DMA_CR_HALT_WIDTH 1
#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
#define DMA_CR_CLM_MASK 0x40u
#define DMA_CR_CLM_SHIFT 6
#define DMA_CR_CLM_WIDTH 1
#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
#define DMA_CR_EMLM_MASK 0x80u
#define DMA_CR_EMLM_SHIFT 7
#define DMA_CR_EMLM_WIDTH 1
#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
#define DMA_CR_ECX_MASK 0x10000u
#define DMA_CR_ECX_SHIFT 16
#define DMA_CR_ECX_WIDTH 1
#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
#define DMA_CR_CX_MASK 0x20000u
#define DMA_CR_CX_SHIFT 17
#define DMA_CR_CX_WIDTH 1
#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
/* ES Bit Fields */
#define DMA_ES_DBE_MASK 0x1u
#define DMA_ES_DBE_SHIFT 0
#define DMA_ES_DBE_WIDTH 1
#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
#define DMA_ES_SBE_MASK 0x2u
#define DMA_ES_SBE_SHIFT 1
#define DMA_ES_SBE_WIDTH 1
#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
#define DMA_ES_SGE_MASK 0x4u
#define DMA_ES_SGE_SHIFT 2
#define DMA_ES_SGE_WIDTH 1
#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
#define DMA_ES_NCE_MASK 0x8u
#define DMA_ES_NCE_SHIFT 3
#define DMA_ES_NCE_WIDTH 1
#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
#define DMA_ES_DOE_MASK 0x10u
#define DMA_ES_DOE_SHIFT 4
#define DMA_ES_DOE_WIDTH 1
#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
#define DMA_ES_DAE_MASK 0x20u
#define DMA_ES_DAE_SHIFT 5
#define DMA_ES_DAE_WIDTH 1
#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
#define DMA_ES_SOE_MASK 0x40u
#define DMA_ES_SOE_SHIFT 6
#define DMA_ES_SOE_WIDTH 1
#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
#define DMA_ES_SAE_MASK 0x80u
#define DMA_ES_SAE_SHIFT 7
#define DMA_ES_SAE_WIDTH 1
#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
#define DMA_ES_ERRCHN_MASK 0xF00u
#define DMA_ES_ERRCHN_SHIFT 8
#define DMA_ES_ERRCHN_WIDTH 4
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK 0x4000u
#define DMA_ES_CPE_SHIFT 14
#define DMA_ES_CPE_WIDTH 1
#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
#define DMA_ES_ECX_MASK 0x10000u
#define DMA_ES_ECX_SHIFT 16
#define DMA_ES_ECX_WIDTH 1
#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
#define DMA_ES_VLD_MASK 0x80000000u
#define DMA_ES_VLD_SHIFT 31
#define DMA_ES_VLD_WIDTH 1
#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
/* ERQ Bit Fields */
#define DMA_ERQ_ERQ0_MASK 0x1u
#define DMA_ERQ_ERQ0_SHIFT 0
#define DMA_ERQ_ERQ0_WIDTH 1
#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
#define DMA_ERQ_ERQ1_MASK 0x2u
#define DMA_ERQ_ERQ1_SHIFT 1
#define DMA_ERQ_ERQ1_WIDTH 1
#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
#define DMA_ERQ_ERQ2_MASK 0x4u
#define DMA_ERQ_ERQ2_SHIFT 2
#define DMA_ERQ_ERQ2_WIDTH 1
#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
#define DMA_ERQ_ERQ3_MASK 0x8u
#define DMA_ERQ_ERQ3_SHIFT 3
#define DMA_ERQ_ERQ3_WIDTH 1
#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
#define DMA_ERQ_ERQ4_MASK 0x10u
#define DMA_ERQ_ERQ4_SHIFT 4
#define DMA_ERQ_ERQ4_WIDTH 1
#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
#define DMA_ERQ_ERQ5_MASK 0x20u
#define DMA_ERQ_ERQ5_SHIFT 5
#define DMA_ERQ_ERQ5_WIDTH 1
#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
#define DMA_ERQ_ERQ6_MASK 0x40u
#define DMA_ERQ_ERQ6_SHIFT 6
#define DMA_ERQ_ERQ6_WIDTH 1
#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
#define DMA_ERQ_ERQ7_MASK 0x80u
#define DMA_ERQ_ERQ7_SHIFT 7
#define DMA_ERQ_ERQ7_WIDTH 1
#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
#define DMA_ERQ_ERQ8_MASK 0x100u
#define DMA_ERQ_ERQ8_SHIFT 8
#define DMA_ERQ_ERQ8_WIDTH 1
#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
#define DMA_ERQ_ERQ9_MASK 0x200u
#define DMA_ERQ_ERQ9_SHIFT 9
#define DMA_ERQ_ERQ9_WIDTH 1
#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
#define DMA_ERQ_ERQ10_MASK 0x400u
#define DMA_ERQ_ERQ10_SHIFT 10
#define DMA_ERQ_ERQ10_WIDTH 1
#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
#define DMA_ERQ_ERQ11_MASK 0x800u
#define DMA_ERQ_ERQ11_SHIFT 11
#define DMA_ERQ_ERQ11_WIDTH 1
#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
#define DMA_ERQ_ERQ12_MASK 0x1000u
#define DMA_ERQ_ERQ12_SHIFT 12
#define DMA_ERQ_ERQ12_WIDTH 1
#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
#define DMA_ERQ_ERQ13_MASK 0x2000u
#define DMA_ERQ_ERQ13_SHIFT 13
#define DMA_ERQ_ERQ13_WIDTH 1
#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
#define DMA_ERQ_ERQ14_MASK 0x4000u
#define DMA_ERQ_ERQ14_SHIFT 14
#define DMA_ERQ_ERQ14_WIDTH 1
#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
#define DMA_ERQ_ERQ15_MASK 0x8000u
#define DMA_ERQ_ERQ15_SHIFT 15
#define DMA_ERQ_ERQ15_WIDTH 1
#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
/* EEI Bit Fields */
#define DMA_EEI_EEI0_MASK 0x1u
#define DMA_EEI_EEI0_SHIFT 0
#define DMA_EEI_EEI0_WIDTH 1
#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
#define DMA_EEI_EEI1_MASK 0x2u
#define DMA_EEI_EEI1_SHIFT 1
#define DMA_EEI_EEI1_WIDTH 1
#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
#define DMA_EEI_EEI2_MASK 0x4u
#define DMA_EEI_EEI2_SHIFT 2
#define DMA_EEI_EEI2_WIDTH 1
#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
#define DMA_EEI_EEI3_MASK 0x8u
#define DMA_EEI_EEI3_SHIFT 3
#define DMA_EEI_EEI3_WIDTH 1
#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
#define DMA_EEI_EEI4_MASK 0x10u
#define DMA_EEI_EEI4_SHIFT 4
#define DMA_EEI_EEI4_WIDTH 1
#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
#define DMA_EEI_EEI5_MASK 0x20u
#define DMA_EEI_EEI5_SHIFT 5
#define DMA_EEI_EEI5_WIDTH 1
#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
#define DMA_EEI_EEI6_MASK 0x40u
#define DMA_EEI_EEI6_SHIFT 6
#define DMA_EEI_EEI6_WIDTH 1
#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
#define DMA_EEI_EEI7_MASK 0x80u
#define DMA_EEI_EEI7_SHIFT 7
#define DMA_EEI_EEI7_WIDTH 1
#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
#define DMA_EEI_EEI8_MASK 0x100u
#define DMA_EEI_EEI8_SHIFT 8
#define DMA_EEI_EEI8_WIDTH 1
#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
#define DMA_EEI_EEI9_MASK 0x200u
#define DMA_EEI_EEI9_SHIFT 9
#define DMA_EEI_EEI9_WIDTH 1
#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
#define DMA_EEI_EEI10_MASK 0x400u
#define DMA_EEI_EEI10_SHIFT 10
#define DMA_EEI_EEI10_WIDTH 1
#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
#define DMA_EEI_EEI11_MASK 0x800u
#define DMA_EEI_EEI11_SHIFT 11
#define DMA_EEI_EEI11_WIDTH 1
#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
#define DMA_EEI_EEI12_MASK 0x1000u
#define DMA_EEI_EEI12_SHIFT 12
#define DMA_EEI_EEI12_WIDTH 1
#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
#define DMA_EEI_EEI13_MASK 0x2000u
#define DMA_EEI_EEI13_SHIFT 13
#define DMA_EEI_EEI13_WIDTH 1
#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
#define DMA_EEI_EEI14_MASK 0x4000u
#define DMA_EEI_EEI14_SHIFT 14
#define DMA_EEI_EEI14_WIDTH 1
#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
#define DMA_EEI_EEI15_MASK 0x8000u
#define DMA_EEI_EEI15_SHIFT 15
#define DMA_EEI_EEI15_WIDTH 1
#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
/* CEEI Bit Fields */
#define DMA_CEEI_CEEI_MASK 0xFu
#define DMA_CEEI_CEEI_SHIFT 0
#define DMA_CEEI_CEEI_WIDTH 4
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK 0x40u
#define DMA_CEEI_CAEE_SHIFT 6
#define DMA_CEEI_CAEE_WIDTH 1
#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
#define DMA_CEEI_NOP_MASK 0x80u
#define DMA_CEEI_NOP_SHIFT 7
#define DMA_CEEI_NOP_WIDTH 1
#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
/* SEEI Bit Fields */
#define DMA_SEEI_SEEI_MASK 0xFu
#define DMA_SEEI_SEEI_SHIFT 0
#define DMA_SEEI_SEEI_WIDTH 4
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK 0x40u
#define DMA_SEEI_SAEE_SHIFT 6
#define DMA_SEEI_SAEE_WIDTH 1
#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
#define DMA_SEEI_NOP_MASK 0x80u
#define DMA_SEEI_NOP_SHIFT 7
#define DMA_SEEI_NOP_WIDTH 1
#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
/* CERQ Bit Fields */
#define DMA_CERQ_CERQ_MASK 0xFu
#define DMA_CERQ_CERQ_SHIFT 0
#define DMA_CERQ_CERQ_WIDTH 4
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK 0x40u
#define DMA_CERQ_CAER_SHIFT 6
#define DMA_CERQ_CAER_WIDTH 1
#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
#define DMA_CERQ_NOP_MASK 0x80u
#define DMA_CERQ_NOP_SHIFT 7
#define DMA_CERQ_NOP_WIDTH 1
#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
/* SERQ Bit Fields */
#define DMA_SERQ_SERQ_MASK 0xFu
#define DMA_SERQ_SERQ_SHIFT 0
#define DMA_SERQ_SERQ_WIDTH 4
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK 0x40u
#define DMA_SERQ_SAER_SHIFT 6
#define DMA_SERQ_SAER_WIDTH 1
#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
#define DMA_SERQ_NOP_MASK 0x80u
#define DMA_SERQ_NOP_SHIFT 7
#define DMA_SERQ_NOP_WIDTH 1
#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
/* CDNE Bit Fields */
#define DMA_CDNE_CDNE_MASK 0xFu
#define DMA_CDNE_CDNE_SHIFT 0
#define DMA_CDNE_CDNE_WIDTH 4
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK 0x40u
#define DMA_CDNE_CADN_SHIFT 6
#define DMA_CDNE_CADN_WIDTH 1
#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
#define DMA_CDNE_NOP_MASK 0x80u
#define DMA_CDNE_NOP_SHIFT 7
#define DMA_CDNE_NOP_WIDTH 1
#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
/* SSRT Bit Fields */
#define DMA_SSRT_SSRT_MASK 0xFu
#define DMA_SSRT_SSRT_SHIFT 0
#define DMA_SSRT_SSRT_WIDTH 4
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK 0x40u
#define DMA_SSRT_SAST_SHIFT 6
#define DMA_SSRT_SAST_WIDTH 1
#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
#define DMA_SSRT_NOP_MASK 0x80u
#define DMA_SSRT_NOP_SHIFT 7
#define DMA_SSRT_NOP_WIDTH 1
#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
/* CERR Bit Fields */
#define DMA_CERR_CERR_MASK 0xFu
#define DMA_CERR_CERR_SHIFT 0
#define DMA_CERR_CERR_WIDTH 4
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK 0x40u
#define DMA_CERR_CAEI_SHIFT 6
#define DMA_CERR_CAEI_WIDTH 1
#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
#define DMA_CERR_NOP_MASK 0x80u
#define DMA_CERR_NOP_SHIFT 7
#define DMA_CERR_NOP_WIDTH 1
#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
/* CINT Bit Fields */
#define DMA_CINT_CINT_MASK 0xFu
#define DMA_CINT_CINT_SHIFT 0
#define DMA_CINT_CINT_WIDTH 4
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK 0x40u
#define DMA_CINT_CAIR_SHIFT 6
#define DMA_CINT_CAIR_WIDTH 1
#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
#define DMA_CINT_NOP_MASK 0x80u
#define DMA_CINT_NOP_SHIFT 7
#define DMA_CINT_NOP_WIDTH 1
#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
/* INT Bit Fields */
#define DMA_INT_INT0_MASK 0x1u
#define DMA_INT_INT0_SHIFT 0
#define DMA_INT_INT0_WIDTH 1
#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
#define DMA_INT_INT1_MASK 0x2u
#define DMA_INT_INT1_SHIFT 1
#define DMA_INT_INT1_WIDTH 1
#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
#define DMA_INT_INT2_MASK 0x4u
#define DMA_INT_INT2_SHIFT 2
#define DMA_INT_INT2_WIDTH 1
#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
#define DMA_INT_INT3_MASK 0x8u
#define DMA_INT_INT3_SHIFT 3
#define DMA_INT_INT3_WIDTH 1
#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
#define DMA_INT_INT4_MASK 0x10u
#define DMA_INT_INT4_SHIFT 4
#define DMA_INT_INT4_WIDTH 1
#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
#define DMA_INT_INT5_MASK 0x20u
#define DMA_INT_INT5_SHIFT 5
#define DMA_INT_INT5_WIDTH 1
#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
#define DMA_INT_INT6_MASK 0x40u
#define DMA_INT_INT6_SHIFT 6
#define DMA_INT_INT6_WIDTH 1
#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
#define DMA_INT_INT7_MASK 0x80u
#define DMA_INT_INT7_SHIFT 7
#define DMA_INT_INT7_WIDTH 1
#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
#define DMA_INT_INT8_MASK 0x100u
#define DMA_INT_INT8_SHIFT 8
#define DMA_INT_INT8_WIDTH 1
#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
#define DMA_INT_INT9_MASK 0x200u
#define DMA_INT_INT9_SHIFT 9
#define DMA_INT_INT9_WIDTH 1
#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
#define DMA_INT_INT10_MASK 0x400u
#define DMA_INT_INT10_SHIFT 10
#define DMA_INT_INT10_WIDTH 1
#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
#define DMA_INT_INT11_MASK 0x800u
#define DMA_INT_INT11_SHIFT 11
#define DMA_INT_INT11_WIDTH 1
#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
#define DMA_INT_INT12_MASK 0x1000u
#define DMA_INT_INT12_SHIFT 12
#define DMA_INT_INT12_WIDTH 1
#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
#define DMA_INT_INT13_MASK 0x2000u
#define DMA_INT_INT13_SHIFT 13
#define DMA_INT_INT13_WIDTH 1
#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
#define DMA_INT_INT14_MASK 0x4000u
#define DMA_INT_INT14_SHIFT 14
#define DMA_INT_INT14_WIDTH 1
#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
#define DMA_INT_INT15_MASK 0x8000u
#define DMA_INT_INT15_SHIFT 15
#define DMA_INT_INT15_WIDTH 1
#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
/* ERR Bit Fields */
#define DMA_ERR_ERR0_MASK 0x1u
#define DMA_ERR_ERR0_SHIFT 0
#define DMA_ERR_ERR0_WIDTH 1
#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
#define DMA_ERR_ERR1_MASK 0x2u
#define DMA_ERR_ERR1_SHIFT 1
#define DMA_ERR_ERR1_WIDTH 1
#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
#define DMA_ERR_ERR2_MASK 0x4u
#define DMA_ERR_ERR2_SHIFT 2
#define DMA_ERR_ERR2_WIDTH 1
#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
#define DMA_ERR_ERR3_MASK 0x8u
#define DMA_ERR_ERR3_SHIFT 3
#define DMA_ERR_ERR3_WIDTH 1
#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
#define DMA_ERR_ERR4_MASK 0x10u
#define DMA_ERR_ERR4_SHIFT 4
#define DMA_ERR_ERR4_WIDTH 1
#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
#define DMA_ERR_ERR5_MASK 0x20u
#define DMA_ERR_ERR5_SHIFT 5
#define DMA_ERR_ERR5_WIDTH 1
#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
#define DMA_ERR_ERR6_MASK 0x40u
#define DMA_ERR_ERR6_SHIFT 6
#define DMA_ERR_ERR6_WIDTH 1
#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
#define DMA_ERR_ERR7_MASK 0x80u
#define DMA_ERR_ERR7_SHIFT 7
#define DMA_ERR_ERR7_WIDTH 1
#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
#define DMA_ERR_ERR8_MASK 0x100u
#define DMA_ERR_ERR8_SHIFT 8
#define DMA_ERR_ERR8_WIDTH 1
#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
#define DMA_ERR_ERR9_MASK 0x200u
#define DMA_ERR_ERR9_SHIFT 9
#define DMA_ERR_ERR9_WIDTH 1
#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
#define DMA_ERR_ERR10_MASK 0x400u
#define DMA_ERR_ERR10_SHIFT 10
#define DMA_ERR_ERR10_WIDTH 1
#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
#define DMA_ERR_ERR11_MASK 0x800u
#define DMA_ERR_ERR11_SHIFT 11
#define DMA_ERR_ERR11_WIDTH 1
#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
#define DMA_ERR_ERR12_MASK 0x1000u
#define DMA_ERR_ERR12_SHIFT 12
#define DMA_ERR_ERR12_WIDTH 1
#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
#define DMA_ERR_ERR13_MASK 0x2000u
#define DMA_ERR_ERR13_SHIFT 13
#define DMA_ERR_ERR13_WIDTH 1
#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
#define DMA_ERR_ERR14_MASK 0x4000u
#define DMA_ERR_ERR14_SHIFT 14
#define DMA_ERR_ERR14_WIDTH 1
#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
#define DMA_ERR_ERR15_MASK 0x8000u
#define DMA_ERR_ERR15_SHIFT 15
#define DMA_ERR_ERR15_WIDTH 1
#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
/* HRS Bit Fields */
#define DMA_HRS_HRS0_MASK 0x1u
#define DMA_HRS_HRS0_SHIFT 0
#define DMA_HRS_HRS0_WIDTH 1
#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
#define DMA_HRS_HRS1_MASK 0x2u
#define DMA_HRS_HRS1_SHIFT 1
#define DMA_HRS_HRS1_WIDTH 1
#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
#define DMA_HRS_HRS2_MASK 0x4u
#define DMA_HRS_HRS2_SHIFT 2
#define DMA_HRS_HRS2_WIDTH 1
#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
#define DMA_HRS_HRS3_MASK 0x8u
#define DMA_HRS_HRS3_SHIFT 3
#define DMA_HRS_HRS3_WIDTH 1
#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
#define DMA_HRS_HRS4_MASK 0x10u
#define DMA_HRS_HRS4_SHIFT 4
#define DMA_HRS_HRS4_WIDTH 1
#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
#define DMA_HRS_HRS5_MASK 0x20u
#define DMA_HRS_HRS5_SHIFT 5
#define DMA_HRS_HRS5_WIDTH 1
#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
#define DMA_HRS_HRS6_MASK 0x40u
#define DMA_HRS_HRS6_SHIFT 6
#define DMA_HRS_HRS6_WIDTH 1
#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
#define DMA_HRS_HRS7_MASK 0x80u
#define DMA_HRS_HRS7_SHIFT 7
#define DMA_HRS_HRS7_WIDTH 1
#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
#define DMA_HRS_HRS8_MASK 0x100u
#define DMA_HRS_HRS8_SHIFT 8
#define DMA_HRS_HRS8_WIDTH 1
#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
#define DMA_HRS_HRS9_MASK 0x200u
#define DMA_HRS_HRS9_SHIFT 9
#define DMA_HRS_HRS9_WIDTH 1
#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
#define DMA_HRS_HRS10_MASK 0x400u
#define DMA_HRS_HRS10_SHIFT 10
#define DMA_HRS_HRS10_WIDTH 1
#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
#define DMA_HRS_HRS11_MASK 0x800u
#define DMA_HRS_HRS11_SHIFT 11
#define DMA_HRS_HRS11_WIDTH 1
#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
#define DMA_HRS_HRS12_MASK 0x1000u
#define DMA_HRS_HRS12_SHIFT 12
#define DMA_HRS_HRS12_WIDTH 1
#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
#define DMA_HRS_HRS13_MASK 0x2000u
#define DMA_HRS_HRS13_SHIFT 13
#define DMA_HRS_HRS13_WIDTH 1
#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
#define DMA_HRS_HRS14_MASK 0x4000u
#define DMA_HRS_HRS14_SHIFT 14
#define DMA_HRS_HRS14_WIDTH 1
#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
#define DMA_HRS_HRS15_MASK 0x8000u
#define DMA_HRS_HRS15_SHIFT 15
#define DMA_HRS_HRS15_WIDTH 1
#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
/* EARS Bit Fields */
#define DMA_EARS_EDREQ_0_MASK 0x1u
#define DMA_EARS_EDREQ_0_SHIFT 0
#define DMA_EARS_EDREQ_0_WIDTH 1
#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
#define DMA_EARS_EDREQ_1_MASK 0x2u
#define DMA_EARS_EDREQ_1_SHIFT 1
#define DMA_EARS_EDREQ_1_WIDTH 1
#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
#define DMA_EARS_EDREQ_2_MASK 0x4u
#define DMA_EARS_EDREQ_2_SHIFT 2
#define DMA_EARS_EDREQ_2_WIDTH 1
#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
#define DMA_EARS_EDREQ_3_MASK 0x8u
#define DMA_EARS_EDREQ_3_SHIFT 3
#define DMA_EARS_EDREQ_3_WIDTH 1
#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
#define DMA_EARS_EDREQ_4_MASK 0x10u
#define DMA_EARS_EDREQ_4_SHIFT 4
#define DMA_EARS_EDREQ_4_WIDTH 1
#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
#define DMA_EARS_EDREQ_5_MASK 0x20u
#define DMA_EARS_EDREQ_5_SHIFT 5
#define DMA_EARS_EDREQ_5_WIDTH 1
#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
#define DMA_EARS_EDREQ_6_MASK 0x40u
#define DMA_EARS_EDREQ_6_SHIFT 6
#define DMA_EARS_EDREQ_6_WIDTH 1
#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
#define DMA_EARS_EDREQ_7_MASK 0x80u
#define DMA_EARS_EDREQ_7_SHIFT 7
#define DMA_EARS_EDREQ_7_WIDTH 1
#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
#define DMA_EARS_EDREQ_8_MASK 0x100u
#define DMA_EARS_EDREQ_8_SHIFT 8
#define DMA_EARS_EDREQ_8_WIDTH 1
#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_8_SHIFT))&DMA_EARS_EDREQ_8_MASK)
#define DMA_EARS_EDREQ_9_MASK 0x200u
#define DMA_EARS_EDREQ_9_SHIFT 9
#define DMA_EARS_EDREQ_9_WIDTH 1
#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_9_SHIFT))&DMA_EARS_EDREQ_9_MASK)
#define DMA_EARS_EDREQ_10_MASK 0x400u
#define DMA_EARS_EDREQ_10_SHIFT 10
#define DMA_EARS_EDREQ_10_WIDTH 1
#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_10_SHIFT))&DMA_EARS_EDREQ_10_MASK)
#define DMA_EARS_EDREQ_11_MASK 0x800u
#define DMA_EARS_EDREQ_11_SHIFT 11
#define DMA_EARS_EDREQ_11_WIDTH 1
#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_11_SHIFT))&DMA_EARS_EDREQ_11_MASK)
#define DMA_EARS_EDREQ_12_MASK 0x1000u
#define DMA_EARS_EDREQ_12_SHIFT 12
#define DMA_EARS_EDREQ_12_WIDTH 1
#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_12_SHIFT))&DMA_EARS_EDREQ_12_MASK)
#define DMA_EARS_EDREQ_13_MASK 0x2000u
#define DMA_EARS_EDREQ_13_SHIFT 13
#define DMA_EARS_EDREQ_13_WIDTH 1
#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_13_SHIFT))&DMA_EARS_EDREQ_13_MASK)
#define DMA_EARS_EDREQ_14_MASK 0x4000u
#define DMA_EARS_EDREQ_14_SHIFT 14
#define DMA_EARS_EDREQ_14_WIDTH 1
#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_14_SHIFT))&DMA_EARS_EDREQ_14_MASK)
#define DMA_EARS_EDREQ_15_MASK 0x8000u
#define DMA_EARS_EDREQ_15_SHIFT 15
#define DMA_EARS_EDREQ_15_WIDTH 1
#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_15_SHIFT))&DMA_EARS_EDREQ_15_MASK)
/* DCHPRI3 Bit Fields */
#define DMA_DCHPRI3_CHPRI_MASK 0xFu
#define DMA_DCHPRI3_CHPRI_SHIFT 0
#define DMA_DCHPRI3_CHPRI_WIDTH 4
#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
#define DMA_DCHPRI3_DPA_MASK 0x40u
#define DMA_DCHPRI3_DPA_SHIFT 6
#define DMA_DCHPRI3_DPA_WIDTH 1
#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
#define DMA_DCHPRI3_ECP_MASK 0x80u
#define DMA_DCHPRI3_ECP_SHIFT 7
#define DMA_DCHPRI3_ECP_WIDTH 1
#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
/* DCHPRI2 Bit Fields */
#define DMA_DCHPRI2_CHPRI_MASK 0xFu
#define DMA_DCHPRI2_CHPRI_SHIFT 0
#define DMA_DCHPRI2_CHPRI_WIDTH 4
#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
#define DMA_DCHPRI2_DPA_MASK 0x40u
#define DMA_DCHPRI2_DPA_SHIFT 6
#define DMA_DCHPRI2_DPA_WIDTH 1
#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
#define DMA_DCHPRI2_ECP_MASK 0x80u
#define DMA_DCHPRI2_ECP_SHIFT 7
#define DMA_DCHPRI2_ECP_WIDTH 1
#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
/* DCHPRI1 Bit Fields */
#define DMA_DCHPRI1_CHPRI_MASK 0xFu
#define DMA_DCHPRI1_CHPRI_SHIFT 0
#define DMA_DCHPRI1_CHPRI_WIDTH 4
#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
#define DMA_DCHPRI1_DPA_MASK 0x40u
#define DMA_DCHPRI1_DPA_SHIFT 6
#define DMA_DCHPRI1_DPA_WIDTH 1
#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
#define DMA_DCHPRI1_ECP_MASK 0x80u
#define DMA_DCHPRI1_ECP_SHIFT 7
#define DMA_DCHPRI1_ECP_WIDTH 1
#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
/* DCHPRI0 Bit Fields */
#define DMA_DCHPRI0_CHPRI_MASK 0xFu
#define DMA_DCHPRI0_CHPRI_SHIFT 0
#define DMA_DCHPRI0_CHPRI_WIDTH 4
#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
#define DMA_DCHPRI0_DPA_MASK 0x40u
#define DMA_DCHPRI0_DPA_SHIFT 6
#define DMA_DCHPRI0_DPA_WIDTH 1
#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
#define DMA_DCHPRI0_ECP_MASK 0x80u
#define DMA_DCHPRI0_ECP_SHIFT 7
#define DMA_DCHPRI0_ECP_WIDTH 1
#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
/* DCHPRI7 Bit Fields */
#define DMA_DCHPRI7_CHPRI_MASK 0xFu
#define DMA_DCHPRI7_CHPRI_SHIFT 0
#define DMA_DCHPRI7_CHPRI_WIDTH 4
#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
#define DMA_DCHPRI7_DPA_MASK 0x40u
#define DMA_DCHPRI7_DPA_SHIFT 6
#define DMA_DCHPRI7_DPA_WIDTH 1
#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
#define DMA_DCHPRI7_ECP_MASK 0x80u
#define DMA_DCHPRI7_ECP_SHIFT 7
#define DMA_DCHPRI7_ECP_WIDTH 1
#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
/* DCHPRI6 Bit Fields */
#define DMA_DCHPRI6_CHPRI_MASK 0xFu
#define DMA_DCHPRI6_CHPRI_SHIFT 0
#define DMA_DCHPRI6_CHPRI_WIDTH 4
#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
#define DMA_DCHPRI6_DPA_MASK 0x40u
#define DMA_DCHPRI6_DPA_SHIFT 6
#define DMA_DCHPRI6_DPA_WIDTH 1
#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
#define DMA_DCHPRI6_ECP_MASK 0x80u
#define DMA_DCHPRI6_ECP_SHIFT 7
#define DMA_DCHPRI6_ECP_WIDTH 1
#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
/* DCHPRI5 Bit Fields */
#define DMA_DCHPRI5_CHPRI_MASK 0xFu
#define DMA_DCHPRI5_CHPRI_SHIFT 0
#define DMA_DCHPRI5_CHPRI_WIDTH 4
#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
#define DMA_DCHPRI5_DPA_MASK 0x40u
#define DMA_DCHPRI5_DPA_SHIFT 6
#define DMA_DCHPRI5_DPA_WIDTH 1
#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
#define DMA_DCHPRI5_ECP_MASK 0x80u
#define DMA_DCHPRI5_ECP_SHIFT 7
#define DMA_DCHPRI5_ECP_WIDTH 1
#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
/* DCHPRI4 Bit Fields */
#define DMA_DCHPRI4_CHPRI_MASK 0xFu
#define DMA_DCHPRI4_CHPRI_SHIFT 0
#define DMA_DCHPRI4_CHPRI_WIDTH 4
#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
#define DMA_DCHPRI4_DPA_MASK 0x40u
#define DMA_DCHPRI4_DPA_SHIFT 6
#define DMA_DCHPRI4_DPA_WIDTH 1
#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
#define DMA_DCHPRI4_ECP_MASK 0x80u
#define DMA_DCHPRI4_ECP_SHIFT 7
#define DMA_DCHPRI4_ECP_WIDTH 1
#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
/* DCHPRI11 Bit Fields */
#define DMA_DCHPRI11_CHPRI_MASK 0xFu
#define DMA_DCHPRI11_CHPRI_SHIFT 0
#define DMA_DCHPRI11_CHPRI_WIDTH 4
#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
#define DMA_DCHPRI11_DPA_MASK 0x40u
#define DMA_DCHPRI11_DPA_SHIFT 6
#define DMA_DCHPRI11_DPA_WIDTH 1
#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
#define DMA_DCHPRI11_ECP_MASK 0x80u
#define DMA_DCHPRI11_ECP_SHIFT 7
#define DMA_DCHPRI11_ECP_WIDTH 1
#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
/* DCHPRI10 Bit Fields */
#define DMA_DCHPRI10_CHPRI_MASK 0xFu
#define DMA_DCHPRI10_CHPRI_SHIFT 0
#define DMA_DCHPRI10_CHPRI_WIDTH 4
#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
#define DMA_DCHPRI10_DPA_MASK 0x40u
#define DMA_DCHPRI10_DPA_SHIFT 6
#define DMA_DCHPRI10_DPA_WIDTH 1
#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
#define DMA_DCHPRI10_ECP_MASK 0x80u
#define DMA_DCHPRI10_ECP_SHIFT 7
#define DMA_DCHPRI10_ECP_WIDTH 1
#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
/* DCHPRI9 Bit Fields */
#define DMA_DCHPRI9_CHPRI_MASK 0xFu
#define DMA_DCHPRI9_CHPRI_SHIFT 0
#define DMA_DCHPRI9_CHPRI_WIDTH 4
#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
#define DMA_DCHPRI9_DPA_MASK 0x40u
#define DMA_DCHPRI9_DPA_SHIFT 6
#define DMA_DCHPRI9_DPA_WIDTH 1
#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
#define DMA_DCHPRI9_ECP_MASK 0x80u
#define DMA_DCHPRI9_ECP_SHIFT 7
#define DMA_DCHPRI9_ECP_WIDTH 1
#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
/* DCHPRI8 Bit Fields */
#define DMA_DCHPRI8_CHPRI_MASK 0xFu
#define DMA_DCHPRI8_CHPRI_SHIFT 0
#define DMA_DCHPRI8_CHPRI_WIDTH 4
#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
#define DMA_DCHPRI8_DPA_MASK 0x40u
#define DMA_DCHPRI8_DPA_SHIFT 6
#define DMA_DCHPRI8_DPA_WIDTH 1
#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
#define DMA_DCHPRI8_ECP_MASK 0x80u
#define DMA_DCHPRI8_ECP_SHIFT 7
#define DMA_DCHPRI8_ECP_WIDTH 1
#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
/* DCHPRI15 Bit Fields */
#define DMA_DCHPRI15_CHPRI_MASK 0xFu
#define DMA_DCHPRI15_CHPRI_SHIFT 0
#define DMA_DCHPRI15_CHPRI_WIDTH 4
#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
#define DMA_DCHPRI15_DPA_MASK 0x40u
#define DMA_DCHPRI15_DPA_SHIFT 6
#define DMA_DCHPRI15_DPA_WIDTH 1
#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
#define DMA_DCHPRI15_ECP_MASK 0x80u
#define DMA_DCHPRI15_ECP_SHIFT 7
#define DMA_DCHPRI15_ECP_WIDTH 1
#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
/* DCHPRI14 Bit Fields */
#define DMA_DCHPRI14_CHPRI_MASK 0xFu
#define DMA_DCHPRI14_CHPRI_SHIFT 0
#define DMA_DCHPRI14_CHPRI_WIDTH 4
#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
#define DMA_DCHPRI14_DPA_MASK 0x40u
#define DMA_DCHPRI14_DPA_SHIFT 6
#define DMA_DCHPRI14_DPA_WIDTH 1
#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
#define DMA_DCHPRI14_ECP_MASK 0x80u
#define DMA_DCHPRI14_ECP_SHIFT 7
#define DMA_DCHPRI14_ECP_WIDTH 1
#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
/* DCHPRI13 Bit Fields */
#define DMA_DCHPRI13_CHPRI_MASK 0xFu
#define DMA_DCHPRI13_CHPRI_SHIFT 0
#define DMA_DCHPRI13_CHPRI_WIDTH 4
#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
#define DMA_DCHPRI13_DPA_MASK 0x40u
#define DMA_DCHPRI13_DPA_SHIFT 6
#define DMA_DCHPRI13_DPA_WIDTH 1
#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
#define DMA_DCHPRI13_ECP_MASK 0x80u
#define DMA_DCHPRI13_ECP_SHIFT 7
#define DMA_DCHPRI13_ECP_WIDTH 1
#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
/* DCHPRI12 Bit Fields */
#define DMA_DCHPRI12_CHPRI_MASK 0xFu
#define DMA_DCHPRI12_CHPRI_SHIFT 0
#define DMA_DCHPRI12_CHPRI_WIDTH 4
#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
#define DMA_DCHPRI12_DPA_MASK 0x40u
#define DMA_DCHPRI12_DPA_SHIFT 6
#define DMA_DCHPRI12_DPA_WIDTH 1
#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
#define DMA_DCHPRI12_ECP_MASK 0x80u
#define DMA_DCHPRI12_ECP_SHIFT 7
#define DMA_DCHPRI12_ECP_WIDTH 1
#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
/* SADDR Bit Fields */
#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
#define DMA_SADDR_SADDR_SHIFT 0
#define DMA_SADDR_SADDR_WIDTH 32
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
/* SOFF Bit Fields */
#define DMA_SOFF_SOFF_MASK 0xFFFFu
#define DMA_SOFF_SOFF_SHIFT 0
#define DMA_SOFF_SOFF_WIDTH 16
#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
/* ATTR Bit Fields */
#define DMA_ATTR_DSIZE_MASK 0x7u
#define DMA_ATTR_DSIZE_SHIFT 0
#define DMA_ATTR_DSIZE_WIDTH 3
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
#define DMA_ATTR_DMOD_MASK 0xF8u
#define DMA_ATTR_DMOD_SHIFT 3
#define DMA_ATTR_DMOD_WIDTH 5
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
#define DMA_ATTR_SSIZE_MASK 0x700u
#define DMA_ATTR_SSIZE_SHIFT 8
#define DMA_ATTR_SSIZE_WIDTH 3
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
#define DMA_ATTR_SMOD_MASK 0xF800u
#define DMA_ATTR_SMOD_SHIFT 11
#define DMA_ATTR_SMOD_WIDTH 5
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
/* NBYTES_MLNO Bit Fields */
#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
#define DMA_NBYTES_MLNO_NBYTES_WIDTH 32
#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
/* NBYTES_MLOFFNO Bit Fields */
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH 30
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH 1
#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH 1
#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
/* NBYTES_MLOFFYES Bit Fields */
#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH 10
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH 20
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH 1
#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH 1
#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
/* SLAST Bit Fields */
#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
#define DMA_SLAST_SLAST_SHIFT 0
#define DMA_SLAST_SLAST_WIDTH 32
#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
/* DADDR Bit Fields */
#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
#define DMA_DADDR_DADDR_SHIFT 0
#define DMA_DADDR_DADDR_WIDTH 32
#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
/* DOFF Bit Fields */
#define DMA_DOFF_DOFF_MASK 0xFFFFu
#define DMA_DOFF_DOFF_SHIFT 0
#define DMA_DOFF_DOFF_WIDTH 16
#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
/* CITER_ELINKNO Bit Fields */
#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
#define DMA_CITER_ELINKNO_CITER_SHIFT 0
#define DMA_CITER_ELINKNO_CITER_WIDTH 15
#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
#define DMA_CITER_ELINKNO_ELINK_WIDTH 1
#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
/* CITER_ELINKYES Bit Fields */
#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
#define DMA_CITER_ELINKYES_CITER_SHIFT 0
#define DMA_CITER_ELINKYES_CITER_WIDTH 9
#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
#define DMA_CITER_ELINKYES_LINKCH_WIDTH 4
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
#define DMA_CITER_ELINKYES_ELINK_WIDTH 1
#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
/* DLAST_SGA Bit Fields */
#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
#define DMA_DLAST_SGA_DLASTSGA_WIDTH 32
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
/* CSR Bit Fields */
#define DMA_CSR_START_MASK 0x1u
#define DMA_CSR_START_SHIFT 0
#define DMA_CSR_START_WIDTH 1
#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
#define DMA_CSR_INTMAJOR_MASK 0x2u
#define DMA_CSR_INTMAJOR_SHIFT 1
#define DMA_CSR_INTMAJOR_WIDTH 1
#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
#define DMA_CSR_INTHALF_MASK 0x4u
#define DMA_CSR_INTHALF_SHIFT 2
#define DMA_CSR_INTHALF_WIDTH 1
#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
#define DMA_CSR_DREQ_MASK 0x8u
#define DMA_CSR_DREQ_SHIFT 3
#define DMA_CSR_DREQ_WIDTH 1
#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
#define DMA_CSR_ESG_MASK 0x10u
#define DMA_CSR_ESG_SHIFT 4
#define DMA_CSR_ESG_WIDTH 1
#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
#define DMA_CSR_MAJORELINK_MASK 0x20u
#define DMA_CSR_MAJORELINK_SHIFT 5
#define DMA_CSR_MAJORELINK_WIDTH 1
#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
#define DMA_CSR_ACTIVE_MASK 0x40u
#define DMA_CSR_ACTIVE_SHIFT 6
#define DMA_CSR_ACTIVE_WIDTH 1
#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
#define DMA_CSR_DONE_MASK 0x80u
#define DMA_CSR_DONE_SHIFT 7
#define DMA_CSR_DONE_WIDTH 1
#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
#define DMA_CSR_MAJORLINKCH_SHIFT 8
#define DMA_CSR_MAJORLINKCH_WIDTH 4
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
#define DMA_CSR_BWC_MASK 0xC000u
#define DMA_CSR_BWC_SHIFT 14
#define DMA_CSR_BWC_WIDTH 2
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
/* BITER_ELINKNO Bit Fields */
#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
#define DMA_BITER_ELINKNO_BITER_SHIFT 0
#define DMA_BITER_ELINKNO_BITER_WIDTH 15
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
#define DMA_BITER_ELINKNO_ELINK_WIDTH 1
#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
/* BITER_ELINKYES Bit Fields */
#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
#define DMA_BITER_ELINKYES_BITER_SHIFT 0
#define DMA_BITER_ELINKYES_BITER_WIDTH 9
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
#define DMA_BITER_ELINKYES_LINKCH_WIDTH 4
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
#define DMA_BITER_ELINKYES_ELINK_WIDTH 1
#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
/*!
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral DMA base address */
#define DMA_BASE (0x40008000u)
/** Peripheral DMA base pointer */
#define DMA0 ((DMA_Type *)DMA_BASE)
#define DMA_BASE_PTR (DMA0)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { DMA_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { DMA0 }
/* ----------------------------------------------------------------------------
-- DMA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
* @{
*/
/* DMA - Register instance definitions */
/* DMA */
#define DMA_CR DMA_CR_REG(DMA0)
#define DMA_ES DMA_ES_REG(DMA0)
#define DMA_ERQ DMA_ERQ_REG(DMA0)
#define DMA_EEI DMA_EEI_REG(DMA0)
#define DMA_CEEI DMA_CEEI_REG(DMA0)
#define DMA_SEEI DMA_SEEI_REG(DMA0)
#define DMA_CERQ DMA_CERQ_REG(DMA0)
#define DMA_SERQ DMA_SERQ_REG(DMA0)
#define DMA_CDNE DMA_CDNE_REG(DMA0)
#define DMA_SSRT DMA_SSRT_REG(DMA0)
#define DMA_CERR DMA_CERR_REG(DMA0)
#define DMA_CINT DMA_CINT_REG(DMA0)
#define DMA_INT DMA_INT_REG(DMA0)
#define DMA_ERR DMA_ERR_REG(DMA0)
#define DMA_HRS DMA_HRS_REG(DMA0)
#define DMA_EARS DMA_EARS_REG(DMA0)
#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
/* DMA - Register array accessors */
#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
/*!
* @}
*/ /* end of group DMA_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMAMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
* @{
*/
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
} DMAMUX_Type, *DMAMUX_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DMAMUX - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
* @{
*/
/* DMAMUX - Register accessors */
#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
#define DMAMUX_CHCFG_COUNT 16
/*!
* @}
*/ /* end of group DMAMUX_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
/* CHCFG Bit Fields */
#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
#define DMAMUX_CHCFG_SOURCE_SHIFT 0
#define DMAMUX_CHCFG_SOURCE_WIDTH 6
#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
#define DMAMUX_CHCFG_TRIG_MASK 0x40u
#define DMAMUX_CHCFG_TRIG_SHIFT 6
#define DMAMUX_CHCFG_TRIG_WIDTH 1
#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
#define DMAMUX_CHCFG_ENBL_MASK 0x80u
#define DMAMUX_CHCFG_ENBL_SHIFT 7
#define DMAMUX_CHCFG_ENBL_WIDTH 1
#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
/*!
* @}
*/ /* end of group DMAMUX_Register_Masks */
/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX base address */
#define DMAMUX_BASE (0x40021000u)
/** Peripheral DMAMUX base pointer */
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
#define DMAMUX_BASE_PTR (DMAMUX)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS { DMAMUX }
/* ----------------------------------------------------------------------------
-- DMAMUX - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
* @{
*/
/* DMAMUX - Register instance definitions */
/* DMAMUX */
#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
/* DMAMUX - Register array accessors */
#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
/*!
* @}
*/ /* end of group DMAMUX_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EWM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
* @{
*/
/** EWM - Register Layout Typedef */
typedef struct {
__IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
__O uint8_t SERV; /**< Service Register, offset: 0x1 */
__IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
__IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
uint8_t RESERVED_0[1];
__IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
} EWM_Type, *EWM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- EWM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
* @{
*/
/* EWM - Register accessors */
#define EWM_CTRL_REG(base) ((base)->CTRL)
#define EWM_SERV_REG(base) ((base)->SERV)
#define EWM_CMPL_REG(base) ((base)->CMPL)
#define EWM_CMPH_REG(base) ((base)->CMPH)
#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER)
/*!
* @}
*/ /* end of group EWM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- EWM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Register_Masks EWM Register Masks
* @{
*/
/* CTRL Bit Fields */
#define EWM_CTRL_EWMEN_MASK 0x1u
#define EWM_CTRL_EWMEN_SHIFT 0
#define EWM_CTRL_EWMEN_WIDTH 1
#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
#define EWM_CTRL_ASSIN_MASK 0x2u
#define EWM_CTRL_ASSIN_SHIFT 1
#define EWM_CTRL_ASSIN_WIDTH 1
#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
#define EWM_CTRL_INEN_MASK 0x4u
#define EWM_CTRL_INEN_SHIFT 2
#define EWM_CTRL_INEN_WIDTH 1
#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
#define EWM_CTRL_INTEN_MASK 0x8u
#define EWM_CTRL_INTEN_SHIFT 3
#define EWM_CTRL_INTEN_WIDTH 1
#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
/* SERV Bit Fields */
#define EWM_SERV_SERVICE_MASK 0xFFu
#define EWM_SERV_SERVICE_SHIFT 0
#define EWM_SERV_SERVICE_WIDTH 8
#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
/* CMPL Bit Fields */
#define EWM_CMPL_COMPAREL_MASK 0xFFu
#define EWM_CMPL_COMPAREL_SHIFT 0
#define EWM_CMPL_COMPAREL_WIDTH 8
#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
/* CMPH Bit Fields */
#define EWM_CMPH_COMPAREH_MASK 0xFFu
#define EWM_CMPH_COMPAREH_SHIFT 0
#define EWM_CMPH_COMPAREH_WIDTH 8
#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
/* CLKPRESCALER Bit Fields */
#define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
#define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
#define EWM_CLKPRESCALER_CLK_DIV_WIDTH 8
#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
/*!
* @}
*/ /* end of group EWM_Register_Masks */
/* EWM - Peripheral instance base addresses */
/** Peripheral EWM base address */
#define EWM_BASE (0x40061000u)
/** Peripheral EWM base pointer */
#define EWM ((EWM_Type *)EWM_BASE)
#define EWM_BASE_PTR (EWM)
/** Array initializer of EWM peripheral base addresses */
#define EWM_BASE_ADDRS { EWM_BASE }
/** Array initializer of EWM peripheral base pointers */
#define EWM_BASE_PTRS { EWM }
/* ----------------------------------------------------------------------------
-- EWM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
* @{
*/
/* EWM - Register instance definitions */
/* EWM */
#define EWM_CTRL EWM_CTRL_REG(EWM)
#define EWM_SERV EWM_SERV_REG(EWM)
#define EWM_CMPL EWM_CMPL_REG(EWM)
#define EWM_CMPH EWM_CMPH_REG(EWM)
#define EWM_CLKPRESCALER EWM_CLKPRESCALER_REG(EWM)
/*!
* @}
*/ /* end of group EWM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group EWM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
* @{
*/
/** FLEXIO - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
__I uint32_t PIN; /**< Pin State Register, offset: 0xC */
__IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
__IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
__IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
uint8_t RESERVED_0[4];
__IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
__IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
__IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
uint8_t RESERVED_1[4];
__IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
uint8_t RESERVED_2[76];
__IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_3[112];
__IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_4[240];
__IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_5[112];
__IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
uint8_t RESERVED_6[112];
__IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
uint8_t RESERVED_7[112];
__IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
uint8_t RESERVED_8[112];
__IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
uint8_t RESERVED_9[112];
__IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
uint8_t RESERVED_10[112];
__IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
} FLEXIO_Type, *FLEXIO_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FLEXIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
* @{
*/
/* FLEXIO - Register accessors */
#define FLEXIO_VERID_REG(base) ((base)->VERID)
#define FLEXIO_PARAM_REG(base) ((base)->PARAM)
#define FLEXIO_CTRL_REG(base) ((base)->CTRL)
#define FLEXIO_PIN_REG(base) ((base)->PIN)
#define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT)
#define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR)
#define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT)
#define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN)
#define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN)
#define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN)
#define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN)
#define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index])
#define FLEXIO_SHIFTCTL_COUNT 4
#define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index])
#define FLEXIO_SHIFTCFG_COUNT 4
#define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index])
#define FLEXIO_SHIFTBUF_COUNT 4
#define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index])
#define FLEXIO_SHIFTBUFBIS_COUNT 4
#define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index])
#define FLEXIO_SHIFTBUFBYS_COUNT 4
#define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index])
#define FLEXIO_SHIFTBUFBBS_COUNT 4
#define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index])
#define FLEXIO_TIMCTL_COUNT 4
#define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index])
#define FLEXIO_TIMCFG_COUNT 4
#define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index])
#define FLEXIO_TIMCMP_COUNT 4
/*!
* @}
*/ /* end of group FLEXIO_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FLEXIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
* @{
*/
/* VERID Bit Fields */
#define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
#define FLEXIO_VERID_FEATURE_SHIFT 0
#define FLEXIO_VERID_FEATURE_WIDTH 16
#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
#define FLEXIO_VERID_MINOR_MASK 0xFF0000u
#define FLEXIO_VERID_MINOR_SHIFT 16
#define FLEXIO_VERID_MINOR_WIDTH 8
#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
#define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
#define FLEXIO_VERID_MAJOR_SHIFT 24
#define FLEXIO_VERID_MAJOR_WIDTH 8
#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
#define FLEXIO_PARAM_SHIFTER_SHIFT 0
#define FLEXIO_PARAM_SHIFTER_WIDTH 8
#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
#define FLEXIO_PARAM_TIMER_MASK 0xFF00u
#define FLEXIO_PARAM_TIMER_SHIFT 8
#define FLEXIO_PARAM_TIMER_WIDTH 8
#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
#define FLEXIO_PARAM_PIN_MASK 0xFF0000u
#define FLEXIO_PARAM_PIN_SHIFT 16
#define FLEXIO_PARAM_PIN_WIDTH 8
#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
#define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
#define FLEXIO_PARAM_TRIGGER_SHIFT 24
#define FLEXIO_PARAM_TRIGGER_WIDTH 8
#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
/* CTRL Bit Fields */
#define FLEXIO_CTRL_FLEXEN_MASK 0x1u
#define FLEXIO_CTRL_FLEXEN_SHIFT 0
#define FLEXIO_CTRL_FLEXEN_WIDTH 1
#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
#define FLEXIO_CTRL_SWRST_MASK 0x2u
#define FLEXIO_CTRL_SWRST_SHIFT 1
#define FLEXIO_CTRL_SWRST_WIDTH 1
#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
#define FLEXIO_CTRL_FASTACC_MASK 0x4u
#define FLEXIO_CTRL_FASTACC_SHIFT 2
#define FLEXIO_CTRL_FASTACC_WIDTH 1
#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
#define FLEXIO_CTRL_DBGE_MASK 0x40000000u
#define FLEXIO_CTRL_DBGE_SHIFT 30
#define FLEXIO_CTRL_DBGE_WIDTH 1
#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
#define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
#define FLEXIO_CTRL_DOZEN_SHIFT 31
#define FLEXIO_CTRL_DOZEN_WIDTH 1
#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
/* PIN Bit Fields */
#define FLEXIO_PIN_PDI_MASK 0xFFu
#define FLEXIO_PIN_PDI_SHIFT 0
#define FLEXIO_PIN_PDI_WIDTH 8
#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PIN_PDI_SHIFT))&FLEXIO_PIN_PDI_MASK)
/* SHIFTSTAT Bit Fields */
#define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
#define FLEXIO_SHIFTSTAT_SSF_SHIFT 0
#define FLEXIO_SHIFTSTAT_SSF_WIDTH 4
#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
/* SHIFTERR Bit Fields */
#define FLEXIO_SHIFTERR_SEF_MASK 0xFu
#define FLEXIO_SHIFTERR_SEF_SHIFT 0
#define FLEXIO_SHIFTERR_SEF_WIDTH 4
#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
/* TIMSTAT Bit Fields */
#define FLEXIO_TIMSTAT_TSF_MASK 0xFu
#define FLEXIO_TIMSTAT_TSF_SHIFT 0
#define FLEXIO_TIMSTAT_TSF_WIDTH 4
#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
/* SHIFTSIEN Bit Fields */
#define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0
#define FLEXIO_SHIFTSIEN_SSIE_WIDTH 4
#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
/* SHIFTEIEN Bit Fields */
#define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0
#define FLEXIO_SHIFTEIEN_SEIE_WIDTH 4
#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
/* TIMIEN Bit Fields */
#define FLEXIO_TIMIEN_TEIE_MASK 0xFu
#define FLEXIO_TIMIEN_TEIE_SHIFT 0
#define FLEXIO_TIMIEN_TEIE_WIDTH 4
#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
/* SHIFTSDEN Bit Fields */
#define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0
#define FLEXIO_SHIFTSDEN_SSDE_WIDTH 4
#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
/* SHIFTCTL Bit Fields */
#define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
#define FLEXIO_SHIFTCTL_SMOD_SHIFT 0
#define FLEXIO_SHIFTCTL_SMOD_WIDTH 3
#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
#define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7
#define FLEXIO_SHIFTCTL_PINPOL_WIDTH 1
#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
#define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8
#define FLEXIO_SHIFTCTL_PINSEL_WIDTH 3
#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
#define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16
#define FLEXIO_SHIFTCTL_PINCFG_WIDTH 2
#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
#define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23
#define FLEXIO_SHIFTCTL_TIMPOL_WIDTH 1
#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24
#define FLEXIO_SHIFTCTL_TIMSEL_WIDTH 2
#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
/* SHIFTCFG Bit Fields */
#define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
#define FLEXIO_SHIFTCFG_SSTART_SHIFT 0
#define FLEXIO_SHIFTCFG_SSTART_WIDTH 2
#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
#define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4
#define FLEXIO_SHIFTCFG_SSTOP_WIDTH 2
#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
#define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
#define FLEXIO_SHIFTCFG_INSRC_SHIFT 8
#define FLEXIO_SHIFTCFG_INSRC_WIDTH 1
#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
/* SHIFTBUF Bit Fields */
#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0
#define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH 32
#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/* SHIFTBUFBIS Bit Fields */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH 32
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/* SHIFTBUFBYS Bit Fields */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH 32
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/* SHIFTBUFBBS Bit Fields */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH 32
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/* TIMCTL Bit Fields */
#define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
#define FLEXIO_TIMCTL_TIMOD_SHIFT 0
#define FLEXIO_TIMCTL_TIMOD_WIDTH 2
#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
#define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
#define FLEXIO_TIMCTL_PINPOL_SHIFT 7
#define FLEXIO_TIMCTL_PINPOL_WIDTH 1
#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
#define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
#define FLEXIO_TIMCTL_PINSEL_SHIFT 8
#define FLEXIO_TIMCTL_PINSEL_WIDTH 3
#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
#define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
#define FLEXIO_TIMCTL_PINCFG_SHIFT 16
#define FLEXIO_TIMCTL_PINCFG_WIDTH 2
#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
#define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
#define FLEXIO_TIMCTL_TRGSRC_SHIFT 22
#define FLEXIO_TIMCTL_TRGSRC_WIDTH 1
#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
#define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
#define FLEXIO_TIMCTL_TRGPOL_SHIFT 23
#define FLEXIO_TIMCTL_TRGPOL_WIDTH 1
#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
#define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
#define FLEXIO_TIMCTL_TRGSEL_SHIFT 24
#define FLEXIO_TIMCTL_TRGSEL_WIDTH 4
#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
/* TIMCFG Bit Fields */
#define FLEXIO_TIMCFG_TSTART_MASK 0x2u
#define FLEXIO_TIMCFG_TSTART_SHIFT 1
#define FLEXIO_TIMCFG_TSTART_WIDTH 1
#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
#define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
#define FLEXIO_TIMCFG_TSTOP_SHIFT 4
#define FLEXIO_TIMCFG_TSTOP_WIDTH 2
#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
#define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
#define FLEXIO_TIMCFG_TIMENA_SHIFT 8
#define FLEXIO_TIMCFG_TIMENA_WIDTH 3
#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
#define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
#define FLEXIO_TIMCFG_TIMDIS_SHIFT 12
#define FLEXIO_TIMCFG_TIMDIS_WIDTH 3
#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
#define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
#define FLEXIO_TIMCFG_TIMRST_SHIFT 16
#define FLEXIO_TIMCFG_TIMRST_WIDTH 3
#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
#define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
#define FLEXIO_TIMCFG_TIMDEC_SHIFT 20
#define FLEXIO_TIMCFG_TIMDEC_WIDTH 2
#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
#define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
#define FLEXIO_TIMCFG_TIMOUT_SHIFT 24
#define FLEXIO_TIMCFG_TIMOUT_WIDTH 2
#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
/* TIMCMP Bit Fields */
#define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
#define FLEXIO_TIMCMP_CMP_SHIFT 0
#define FLEXIO_TIMCMP_CMP_WIDTH 16
#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
/*!
* @}
*/ /* end of group FLEXIO_Register_Masks */
/* FLEXIO - Peripheral instance base addresses */
/** Peripheral FLEXIO base address */
#define FLEXIO_BASE (0x4005F000u)
/** Peripheral FLEXIO base pointer */
#define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
#define FLEXIO_BASE_PTR (FLEXIO)
/** Array initializer of FLEXIO peripheral base addresses */
#define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
/** Array initializer of FLEXIO peripheral base pointers */
#define FLEXIO_BASE_PTRS { FLEXIO }
/* ----------------------------------------------------------------------------
-- FLEXIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
* @{
*/
/* FLEXIO - Register instance definitions */
/* FLEXIO */
#define FLEXIO_VERID FLEXIO_VERID_REG(FLEXIO)
#define FLEXIO_PARAM FLEXIO_PARAM_REG(FLEXIO)
#define FLEXIO_CTRL FLEXIO_CTRL_REG(FLEXIO)
#define FLEXIO_PIN FLEXIO_PIN_REG(FLEXIO)
#define FLEXIO_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO)
#define FLEXIO_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO)
#define FLEXIO_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO)
#define FLEXIO_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO)
#define FLEXIO_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO)
#define FLEXIO_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO)
#define FLEXIO_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO)
#define FLEXIO_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO,0)
#define FLEXIO_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO,1)
#define FLEXIO_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO,2)
#define FLEXIO_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO,3)
#define FLEXIO_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO,0)
#define FLEXIO_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO,1)
#define FLEXIO_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO,2)
#define FLEXIO_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO,3)
#define FLEXIO_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO,0)
#define FLEXIO_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO,1)
#define FLEXIO_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO,2)
#define FLEXIO_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO,3)
#define FLEXIO_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
#define FLEXIO_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
#define FLEXIO_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
#define FLEXIO_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
#define FLEXIO_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
#define FLEXIO_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
#define FLEXIO_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
#define FLEXIO_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
#define FLEXIO_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
#define FLEXIO_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
#define FLEXIO_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
#define FLEXIO_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
#define FLEXIO_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO,0)
#define FLEXIO_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO,1)
#define FLEXIO_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO,2)
#define FLEXIO_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO,3)
#define FLEXIO_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO,0)
#define FLEXIO_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO,1)
#define FLEXIO_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO,2)
#define FLEXIO_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO,3)
#define FLEXIO_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO,0)
#define FLEXIO_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO,1)
#define FLEXIO_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO,2)
#define FLEXIO_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO,3)
/* FLEXIO - Register array accessors */
#define FLEXIO_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO,index)
#define FLEXIO_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO,index)
#define FLEXIO_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO,index)
#define FLEXIO_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
#define FLEXIO_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
#define FLEXIO_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
#define FLEXIO_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO,index)
#define FLEXIO_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO,index)
#define FLEXIO_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO,index)
/*!
* @}
*/ /* end of group FLEXIO_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group FLEXIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
* @{
*/
/** FMC - Register Layout Typedef */
typedef struct {
__IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
__IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
__IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
uint8_t RESERVED_0[244];
__IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
__IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
__IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
__IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
uint8_t RESERVED_1[128];
struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
__IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
__IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
} SET[4][8];
} FMC_Type, *FMC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
* @{
*/
/* FMC - Register accessors */
#define FMC_PFAPR_REG(base) ((base)->PFAPR)
#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
#define FMC_TAGVDW0S_COUNT 8
#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
#define FMC_TAGVDW1S_COUNT 8
#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
#define FMC_TAGVDW2S_COUNT 8
#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
#define FMC_TAGVDW3S_COUNT 8
#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
#define FMC_DATA_U_COUNT 4
#define FMC_DATA_U_COUNT2 8
#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
#define FMC_DATA_L_COUNT 4
#define FMC_DATA_L_COUNT2 8
/*!
* @}
*/ /* end of group FMC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FMC_Register_Masks FMC Register Masks
* @{
*/
/* PFAPR Bit Fields */
#define FMC_PFAPR_M0AP_MASK 0x3u
#define FMC_PFAPR_M0AP_SHIFT 0
#define FMC_PFAPR_M0AP_WIDTH 2
#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
#define FMC_PFAPR_M1AP_MASK 0xCu
#define FMC_PFAPR_M1AP_SHIFT 2
#define FMC_PFAPR_M1AP_WIDTH 2
#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
#define FMC_PFAPR_M2AP_MASK 0x30u
#define FMC_PFAPR_M2AP_SHIFT 4
#define FMC_PFAPR_M2AP_WIDTH 2
#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
#define FMC_PFAPR_M3AP_MASK 0xC0u
#define FMC_PFAPR_M3AP_SHIFT 6
#define FMC_PFAPR_M3AP_WIDTH 2
#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
#define FMC_PFAPR_M4AP_MASK 0x300u
#define FMC_PFAPR_M4AP_SHIFT 8
#define FMC_PFAPR_M4AP_WIDTH 2
#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
#define FMC_PFAPR_M5AP_MASK 0xC00u
#define FMC_PFAPR_M5AP_SHIFT 10
#define FMC_PFAPR_M5AP_WIDTH 2
#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
#define FMC_PFAPR_M6AP_MASK 0x3000u
#define FMC_PFAPR_M6AP_SHIFT 12
#define FMC_PFAPR_M6AP_WIDTH 2
#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
#define FMC_PFAPR_M7AP_MASK 0xC000u
#define FMC_PFAPR_M7AP_SHIFT 14
#define FMC_PFAPR_M7AP_WIDTH 2
#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
#define FMC_PFAPR_M0PFD_MASK 0x10000u
#define FMC_PFAPR_M0PFD_SHIFT 16
#define FMC_PFAPR_M0PFD_WIDTH 1
#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
#define FMC_PFAPR_M1PFD_MASK 0x20000u
#define FMC_PFAPR_M1PFD_SHIFT 17
#define FMC_PFAPR_M1PFD_WIDTH 1
#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
#define FMC_PFAPR_M2PFD_MASK 0x40000u
#define FMC_PFAPR_M2PFD_SHIFT 18
#define FMC_PFAPR_M2PFD_WIDTH 1
#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
#define FMC_PFAPR_M3PFD_MASK 0x80000u
#define FMC_PFAPR_M3PFD_SHIFT 19
#define FMC_PFAPR_M3PFD_WIDTH 1
#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
#define FMC_PFAPR_M4PFD_MASK 0x100000u
#define FMC_PFAPR_M4PFD_SHIFT 20
#define FMC_PFAPR_M4PFD_WIDTH 1
#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
#define FMC_PFAPR_M5PFD_MASK 0x200000u
#define FMC_PFAPR_M5PFD_SHIFT 21
#define FMC_PFAPR_M5PFD_WIDTH 1
#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
#define FMC_PFAPR_M6PFD_MASK 0x400000u
#define FMC_PFAPR_M6PFD_SHIFT 22
#define FMC_PFAPR_M6PFD_WIDTH 1
#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
#define FMC_PFAPR_M7PFD_MASK 0x800000u
#define FMC_PFAPR_M7PFD_SHIFT 23
#define FMC_PFAPR_M7PFD_WIDTH 1
#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
/* PFB0CR Bit Fields */
#define FMC_PFB0CR_B0SEBE_MASK 0x1u
#define FMC_PFB0CR_B0SEBE_SHIFT 0
#define FMC_PFB0CR_B0SEBE_WIDTH 1
#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
#define FMC_PFB0CR_B0IPE_MASK 0x2u
#define FMC_PFB0CR_B0IPE_SHIFT 1
#define FMC_PFB0CR_B0IPE_WIDTH 1
#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
#define FMC_PFB0CR_B0DPE_MASK 0x4u
#define FMC_PFB0CR_B0DPE_SHIFT 2
#define FMC_PFB0CR_B0DPE_WIDTH 1
#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
#define FMC_PFB0CR_B0ICE_MASK 0x8u
#define FMC_PFB0CR_B0ICE_SHIFT 3
#define FMC_PFB0CR_B0ICE_WIDTH 1
#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
#define FMC_PFB0CR_B0DCE_MASK 0x10u
#define FMC_PFB0CR_B0DCE_SHIFT 4
#define FMC_PFB0CR_B0DCE_WIDTH 1
#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
#define FMC_PFB0CR_CRC_MASK 0xE0u
#define FMC_PFB0CR_CRC_SHIFT 5
#define FMC_PFB0CR_CRC_WIDTH 3
#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
#define FMC_PFB0CR_B0MW_MASK 0x60000u
#define FMC_PFB0CR_B0MW_SHIFT 17
#define FMC_PFB0CR_B0MW_WIDTH 2
#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
#define FMC_PFB0CR_S_B_INV_SHIFT 19
#define FMC_PFB0CR_S_B_INV_WIDTH 1
#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
#define FMC_PFB0CR_CINV_WAY_SHIFT 20
#define FMC_PFB0CR_CINV_WAY_WIDTH 4
#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
#define FMC_PFB0CR_CLCK_WAY_WIDTH 4
#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
#define FMC_PFB0CR_B0RWSC_SHIFT 28
#define FMC_PFB0CR_B0RWSC_WIDTH 4
#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
/* PFB1CR Bit Fields */
#define FMC_PFB1CR_B1SEBE_MASK 0x1u
#define FMC_PFB1CR_B1SEBE_SHIFT 0
#define FMC_PFB1CR_B1SEBE_WIDTH 1
#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
#define FMC_PFB1CR_B1IPE_MASK 0x2u
#define FMC_PFB1CR_B1IPE_SHIFT 1
#define FMC_PFB1CR_B1IPE_WIDTH 1
#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
#define FMC_PFB1CR_B1DPE_MASK 0x4u
#define FMC_PFB1CR_B1DPE_SHIFT 2
#define FMC_PFB1CR_B1DPE_WIDTH 1
#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
#define FMC_PFB1CR_B1ICE_MASK 0x8u
#define FMC_PFB1CR_B1ICE_SHIFT 3
#define FMC_PFB1CR_B1ICE_WIDTH 1
#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
#define FMC_PFB1CR_B1DCE_MASK 0x10u
#define FMC_PFB1CR_B1DCE_SHIFT 4
#define FMC_PFB1CR_B1DCE_WIDTH 1
#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
#define FMC_PFB1CR_B1MW_MASK 0x60000u
#define FMC_PFB1CR_B1MW_SHIFT 17
#define FMC_PFB1CR_B1MW_WIDTH 2
#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
#define FMC_PFB1CR_B1RWSC_SHIFT 28
#define FMC_PFB1CR_B1RWSC_WIDTH 4
#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
/* TAGVDW0S Bit Fields */
#define FMC_TAGVDW0S_valid_MASK 0x1u
#define FMC_TAGVDW0S_valid_SHIFT 0
#define FMC_TAGVDW0S_valid_WIDTH 1
#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
#define FMC_TAGVDW0S_tag_SHIFT 5
#define FMC_TAGVDW0S_tag_WIDTH 14
#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
/* TAGVDW1S Bit Fields */
#define FMC_TAGVDW1S_valid_MASK 0x1u
#define FMC_TAGVDW1S_valid_SHIFT 0
#define FMC_TAGVDW1S_valid_WIDTH 1
#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
#define FMC_TAGVDW1S_tag_SHIFT 5
#define FMC_TAGVDW1S_tag_WIDTH 14
#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
/* TAGVDW2S Bit Fields */
#define FMC_TAGVDW2S_valid_MASK 0x1u
#define FMC_TAGVDW2S_valid_SHIFT 0
#define FMC_TAGVDW2S_valid_WIDTH 1
#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
#define FMC_TAGVDW2S_tag_SHIFT 5
#define FMC_TAGVDW2S_tag_WIDTH 14
#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
/* TAGVDW3S Bit Fields */
#define FMC_TAGVDW3S_valid_MASK 0x1u
#define FMC_TAGVDW3S_valid_SHIFT 0
#define FMC_TAGVDW3S_valid_WIDTH 1
#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
#define FMC_TAGVDW3S_tag_SHIFT 5
#define FMC_TAGVDW3S_tag_WIDTH 14
#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
/* DATA_U Bit Fields */
#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
#define FMC_DATA_U_data_SHIFT 0
#define FMC_DATA_U_data_WIDTH 32
#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
/* DATA_L Bit Fields */
#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
#define FMC_DATA_L_data_SHIFT 0
#define FMC_DATA_L_data_WIDTH 32
#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
/*!
* @}
*/ /* end of group FMC_Register_Masks */
/* FMC - Peripheral instance base addresses */
/** Peripheral FMC base address */
#define FMC_BASE (0x4001F000u)
/** Peripheral FMC base pointer */
#define FMC ((FMC_Type *)FMC_BASE)
#define FMC_BASE_PTR (FMC)
/** Array initializer of FMC peripheral base addresses */
#define FMC_BASE_ADDRS { FMC_BASE }
/** Array initializer of FMC peripheral base pointers */
#define FMC_BASE_PTRS { FMC }
/* ----------------------------------------------------------------------------
-- FMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
* @{
*/
/* FMC - Register instance definitions */
/* FMC */
#define FMC_PFAPR FMC_PFAPR_REG(FMC)
#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
#define FMC_TAGVDW0S4 FMC_TAGVDW0S_REG(FMC,4)
#define FMC_TAGVDW0S5 FMC_TAGVDW0S_REG(FMC,5)
#define FMC_TAGVDW0S6 FMC_TAGVDW0S_REG(FMC,6)
#define FMC_TAGVDW0S7 FMC_TAGVDW0S_REG(FMC,7)
#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
#define FMC_TAGVDW1S4 FMC_TAGVDW1S_REG(FMC,4)
#define FMC_TAGVDW1S5 FMC_TAGVDW1S_REG(FMC,5)
#define FMC_TAGVDW1S6 FMC_TAGVDW1S_REG(FMC,6)
#define FMC_TAGVDW1S7 FMC_TAGVDW1S_REG(FMC,7)
#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
#define FMC_TAGVDW2S4 FMC_TAGVDW2S_REG(FMC,4)
#define FMC_TAGVDW2S5 FMC_TAGVDW2S_REG(FMC,5)
#define FMC_TAGVDW2S6 FMC_TAGVDW2S_REG(FMC,6)
#define FMC_TAGVDW2S7 FMC_TAGVDW2S_REG(FMC,7)
#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
#define FMC_TAGVDW3S4 FMC_TAGVDW3S_REG(FMC,4)
#define FMC_TAGVDW3S5 FMC_TAGVDW3S_REG(FMC,5)
#define FMC_TAGVDW3S6 FMC_TAGVDW3S_REG(FMC,6)
#define FMC_TAGVDW3S7 FMC_TAGVDW3S_REG(FMC,7)
#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
#define FMC_DATAW0S4U FMC_DATA_U_REG(FMC,0,4)
#define FMC_DATAW0S4L FMC_DATA_L_REG(FMC,0,4)
#define FMC_DATAW0S5U FMC_DATA_U_REG(FMC,0,5)
#define FMC_DATAW0S5L FMC_DATA_L_REG(FMC,0,5)
#define FMC_DATAW0S6U FMC_DATA_U_REG(FMC,0,6)
#define FMC_DATAW0S6L FMC_DATA_L_REG(FMC,0,6)
#define FMC_DATAW0S7U FMC_DATA_U_REG(FMC,0,7)
#define FMC_DATAW0S7L FMC_DATA_L_REG(FMC,0,7)
#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
#define FMC_DATAW1S4U FMC_DATA_U_REG(FMC,1,4)
#define FMC_DATAW1S4L FMC_DATA_L_REG(FMC,1,4)
#define FMC_DATAW1S5U FMC_DATA_U_REG(FMC,1,5)
#define FMC_DATAW1S5L FMC_DATA_L_REG(FMC,1,5)
#define FMC_DATAW1S6U FMC_DATA_U_REG(FMC,1,6)
#define FMC_DATAW1S6L FMC_DATA_L_REG(FMC,1,6)
#define FMC_DATAW1S7U FMC_DATA_U_REG(FMC,1,7)
#define FMC_DATAW1S7L FMC_DATA_L_REG(FMC,1,7)
#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
#define FMC_DATAW2S4U FMC_DATA_U_REG(FMC,2,4)
#define FMC_DATAW2S4L FMC_DATA_L_REG(FMC,2,4)
#define FMC_DATAW2S5U FMC_DATA_U_REG(FMC,2,5)
#define FMC_DATAW2S5L FMC_DATA_L_REG(FMC,2,5)
#define FMC_DATAW2S6U FMC_DATA_U_REG(FMC,2,6)
#define FMC_DATAW2S6L FMC_DATA_L_REG(FMC,2,6)
#define FMC_DATAW2S7U FMC_DATA_U_REG(FMC,2,7)
#define FMC_DATAW2S7L FMC_DATA_L_REG(FMC,2,7)
#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
#define FMC_DATAW3S4U FMC_DATA_U_REG(FMC,3,4)
#define FMC_DATAW3S4L FMC_DATA_L_REG(FMC,3,4)
#define FMC_DATAW3S5U FMC_DATA_U_REG(FMC,3,5)
#define FMC_DATAW3S5L FMC_DATA_L_REG(FMC,3,5)
#define FMC_DATAW3S6U FMC_DATA_U_REG(FMC,3,6)
#define FMC_DATAW3S6L FMC_DATA_L_REG(FMC,3,6)
#define FMC_DATAW3S7U FMC_DATA_U_REG(FMC,3,7)
#define FMC_DATAW3S7L FMC_DATA_L_REG(FMC,3,7)
/* FMC - Register array accessors */
#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
/*!
* @}
*/ /* end of group FMC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group FMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FTFA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
* @{
*/
/** FTFA - Register Layout Typedef */
typedef struct {
__IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
__IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
__I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
__I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
__IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
__IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
__IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
__IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
__IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
__IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
__IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
__IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
__IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
__IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
__IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
__IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
__IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
__IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
__IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
__IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
uint8_t RESERVED_0[4];
__I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
__I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
__I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
__I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
__I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
__I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
__I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
__I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
__I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
__I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
__I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
__I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
__I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
__I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
__I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
__I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
__I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
uint8_t RESERVED_1[2];
__I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
} FTFA_Type, *FTFA_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FTFA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
* @{
*/
/* FTFA - Register accessors */
#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
#define FTFA_FSEC_REG(base) ((base)->FSEC)
#define FTFA_FOPT_REG(base) ((base)->FOPT)
#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
#define FTFA_XACCH3_REG(base) ((base)->XACCH3)
#define FTFA_XACCH2_REG(base) ((base)->XACCH2)
#define FTFA_XACCH1_REG(base) ((base)->XACCH1)
#define FTFA_XACCH0_REG(base) ((base)->XACCH0)
#define FTFA_XACCL3_REG(base) ((base)->XACCL3)
#define FTFA_XACCL2_REG(base) ((base)->XACCL2)
#define FTFA_XACCL1_REG(base) ((base)->XACCL1)
#define FTFA_XACCL0_REG(base) ((base)->XACCL0)
#define FTFA_SACCH3_REG(base) ((base)->SACCH3)
#define FTFA_SACCH2_REG(base) ((base)->SACCH2)
#define FTFA_SACCH1_REG(base) ((base)->SACCH1)
#define FTFA_SACCH0_REG(base) ((base)->SACCH0)
#define FTFA_SACCL3_REG(base) ((base)->SACCL3)
#define FTFA_SACCL2_REG(base) ((base)->SACCL2)
#define FTFA_SACCL1_REG(base) ((base)->SACCL1)
#define FTFA_SACCL0_REG(base) ((base)->SACCL0)
#define FTFA_FACSS_REG(base) ((base)->FACSS)
#define FTFA_FACSN_REG(base) ((base)->FACSN)
/*!
* @}
*/ /* end of group FTFA_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FTFA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Masks FTFA Register Masks
* @{
*/
/* FSTAT Bit Fields */
#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
#define FTFA_FSTAT_MGSTAT0_SHIFT 0
#define FTFA_FSTAT_MGSTAT0_WIDTH 1
#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_MGSTAT0_SHIFT))&FTFA_FSTAT_MGSTAT0_MASK)
#define FTFA_FSTAT_FPVIOL_MASK 0x10u
#define FTFA_FSTAT_FPVIOL_SHIFT 4
#define FTFA_FSTAT_FPVIOL_WIDTH 1
#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_FPVIOL_SHIFT))&FTFA_FSTAT_FPVIOL_MASK)
#define FTFA_FSTAT_ACCERR_MASK 0x20u
#define FTFA_FSTAT_ACCERR_SHIFT 5
#define FTFA_FSTAT_ACCERR_WIDTH 1
#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_ACCERR_SHIFT))&FTFA_FSTAT_ACCERR_MASK)
#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
#define FTFA_FSTAT_RDCOLERR_SHIFT 6
#define FTFA_FSTAT_RDCOLERR_WIDTH 1
#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_RDCOLERR_SHIFT))&FTFA_FSTAT_RDCOLERR_MASK)
#define FTFA_FSTAT_CCIF_MASK 0x80u
#define FTFA_FSTAT_CCIF_SHIFT 7
#define FTFA_FSTAT_CCIF_WIDTH 1
#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_CCIF_SHIFT))&FTFA_FSTAT_CCIF_MASK)
/* FCNFG Bit Fields */
#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
#define FTFA_FCNFG_ERSSUSP_SHIFT 4
#define FTFA_FCNFG_ERSSUSP_WIDTH 1
#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSSUSP_SHIFT))&FTFA_FCNFG_ERSSUSP_MASK)
#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
#define FTFA_FCNFG_ERSAREQ_SHIFT 5
#define FTFA_FCNFG_ERSAREQ_WIDTH 1
#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSAREQ_SHIFT))&FTFA_FCNFG_ERSAREQ_MASK)
#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
#define FTFA_FCNFG_RDCOLLIE_WIDTH 1
#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_RDCOLLIE_SHIFT))&FTFA_FCNFG_RDCOLLIE_MASK)
#define FTFA_FCNFG_CCIE_MASK 0x80u
#define FTFA_FCNFG_CCIE_SHIFT 7
#define FTFA_FCNFG_CCIE_WIDTH 1
#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_CCIE_SHIFT))&FTFA_FCNFG_CCIE_MASK)
/* FSEC Bit Fields */
#define FTFA_FSEC_SEC_MASK 0x3u
#define FTFA_FSEC_SEC_SHIFT 0
#define FTFA_FSEC_SEC_WIDTH 2
#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
#define FTFA_FSEC_FSLACC_MASK 0xCu
#define FTFA_FSEC_FSLACC_SHIFT 2
#define FTFA_FSEC_FSLACC_WIDTH 2
#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
#define FTFA_FSEC_MEEN_MASK 0x30u
#define FTFA_FSEC_MEEN_SHIFT 4
#define FTFA_FSEC_MEEN_WIDTH 2
#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
#define FTFA_FSEC_KEYEN_MASK 0xC0u
#define FTFA_FSEC_KEYEN_SHIFT 6
#define FTFA_FSEC_KEYEN_WIDTH 2
#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
/* FOPT Bit Fields */
#define FTFA_FOPT_OPT_MASK 0xFFu
#define FTFA_FOPT_OPT_SHIFT 0
#define FTFA_FOPT_OPT_WIDTH 8
#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
/* FCCOB3 Bit Fields */
#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
#define FTFA_FCCOB3_CCOBn_SHIFT 0
#define FTFA_FCCOB3_CCOBn_WIDTH 8
#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
/* FCCOB2 Bit Fields */
#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
#define FTFA_FCCOB2_CCOBn_SHIFT 0
#define FTFA_FCCOB2_CCOBn_WIDTH 8
#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
/* FCCOB1 Bit Fields */
#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
#define FTFA_FCCOB1_CCOBn_SHIFT 0
#define FTFA_FCCOB1_CCOBn_WIDTH 8
#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
/* FCCOB0 Bit Fields */
#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
#define FTFA_FCCOB0_CCOBn_SHIFT 0
#define FTFA_FCCOB0_CCOBn_WIDTH 8
#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
/* FCCOB7 Bit Fields */
#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
#define FTFA_FCCOB7_CCOBn_SHIFT 0
#define FTFA_FCCOB7_CCOBn_WIDTH 8
#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
/* FCCOB6 Bit Fields */
#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
#define FTFA_FCCOB6_CCOBn_SHIFT 0
#define FTFA_FCCOB6_CCOBn_WIDTH 8
#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
/* FCCOB5 Bit Fields */
#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
#define FTFA_FCCOB5_CCOBn_SHIFT 0
#define FTFA_FCCOB5_CCOBn_WIDTH 8
#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
/* FCCOB4 Bit Fields */
#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
#define FTFA_FCCOB4_CCOBn_SHIFT 0
#define FTFA_FCCOB4_CCOBn_WIDTH 8
#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
/* FCCOBB Bit Fields */
#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
#define FTFA_FCCOBB_CCOBn_SHIFT 0
#define FTFA_FCCOBB_CCOBn_WIDTH 8
#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
/* FCCOBA Bit Fields */
#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
#define FTFA_FCCOBA_CCOBn_SHIFT 0
#define FTFA_FCCOBA_CCOBn_WIDTH 8
#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
/* FCCOB9 Bit Fields */
#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
#define FTFA_FCCOB9_CCOBn_SHIFT 0
#define FTFA_FCCOB9_CCOBn_WIDTH 8
#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
/* FCCOB8 Bit Fields */
#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
#define FTFA_FCCOB8_CCOBn_SHIFT 0
#define FTFA_FCCOB8_CCOBn_WIDTH 8
#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
/* FPROT3 Bit Fields */
#define FTFA_FPROT3_PROT_MASK 0xFFu
#define FTFA_FPROT3_PROT_SHIFT 0
#define FTFA_FPROT3_PROT_WIDTH 8
#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
/* FPROT2 Bit Fields */
#define FTFA_FPROT2_PROT_MASK 0xFFu
#define FTFA_FPROT2_PROT_SHIFT 0
#define FTFA_FPROT2_PROT_WIDTH 8
#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
/* FPROT1 Bit Fields */
#define FTFA_FPROT1_PROT_MASK 0xFFu
#define FTFA_FPROT1_PROT_SHIFT 0
#define FTFA_FPROT1_PROT_WIDTH 8
#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
/* FPROT0 Bit Fields */
#define FTFA_FPROT0_PROT_MASK 0xFFu
#define FTFA_FPROT0_PROT_SHIFT 0
#define FTFA_FPROT0_PROT_WIDTH 8
#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
/* XACCH3 Bit Fields */
#define FTFA_XACCH3_XA_MASK 0xFFu
#define FTFA_XACCH3_XA_SHIFT 0
#define FTFA_XACCH3_XA_WIDTH 8
#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
/* XACCH2 Bit Fields */
#define FTFA_XACCH2_XA_MASK 0xFFu
#define FTFA_XACCH2_XA_SHIFT 0
#define FTFA_XACCH2_XA_WIDTH 8
#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
/* XACCH1 Bit Fields */
#define FTFA_XACCH1_XA_MASK 0xFFu
#define FTFA_XACCH1_XA_SHIFT 0
#define FTFA_XACCH1_XA_WIDTH 8
#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
/* XACCH0 Bit Fields */
#define FTFA_XACCH0_XA_MASK 0xFFu
#define FTFA_XACCH0_XA_SHIFT 0
#define FTFA_XACCH0_XA_WIDTH 8
#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
/* XACCL3 Bit Fields */
#define FTFA_XACCL3_XA_MASK 0xFFu
#define FTFA_XACCL3_XA_SHIFT 0
#define FTFA_XACCL3_XA_WIDTH 8
#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
/* XACCL2 Bit Fields */
#define FTFA_XACCL2_XA_MASK 0xFFu
#define FTFA_XACCL2_XA_SHIFT 0
#define FTFA_XACCL2_XA_WIDTH 8
#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
/* XACCL1 Bit Fields */
#define FTFA_XACCL1_XA_MASK 0xFFu
#define FTFA_XACCL1_XA_SHIFT 0
#define FTFA_XACCL1_XA_WIDTH 8
#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
/* XACCL0 Bit Fields */
#define FTFA_XACCL0_XA_MASK 0xFFu
#define FTFA_XACCL0_XA_SHIFT 0
#define FTFA_XACCL0_XA_WIDTH 8
#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
/* SACCH3 Bit Fields */
#define FTFA_SACCH3_SA_MASK 0xFFu
#define FTFA_SACCH3_SA_SHIFT 0
#define FTFA_SACCH3_SA_WIDTH 8
#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
/* SACCH2 Bit Fields */
#define FTFA_SACCH2_SA_MASK 0xFFu
#define FTFA_SACCH2_SA_SHIFT 0
#define FTFA_SACCH2_SA_WIDTH 8
#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
/* SACCH1 Bit Fields */
#define FTFA_SACCH1_SA_MASK 0xFFu
#define FTFA_SACCH1_SA_SHIFT 0
#define FTFA_SACCH1_SA_WIDTH 8
#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
/* SACCH0 Bit Fields */
#define FTFA_SACCH0_SA_MASK 0xFFu
#define FTFA_SACCH0_SA_SHIFT 0
#define FTFA_SACCH0_SA_WIDTH 8
#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
/* SACCL3 Bit Fields */
#define FTFA_SACCL3_SA_MASK 0xFFu
#define FTFA_SACCL3_SA_SHIFT 0
#define FTFA_SACCL3_SA_WIDTH 8
#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
/* SACCL2 Bit Fields */
#define FTFA_SACCL2_SA_MASK 0xFFu
#define FTFA_SACCL2_SA_SHIFT 0
#define FTFA_SACCL2_SA_WIDTH 8
#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
/* SACCL1 Bit Fields */
#define FTFA_SACCL1_SA_MASK 0xFFu
#define FTFA_SACCL1_SA_SHIFT 0
#define FTFA_SACCL1_SA_WIDTH 8
#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
/* SACCL0 Bit Fields */
#define FTFA_SACCL0_SA_MASK 0xFFu
#define FTFA_SACCL0_SA_SHIFT 0
#define FTFA_SACCL0_SA_WIDTH 8
#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
/* FACSS Bit Fields */
#define FTFA_FACSS_SGSIZE_MASK 0xFFu
#define FTFA_FACSS_SGSIZE_SHIFT 0
#define FTFA_FACSS_SGSIZE_WIDTH 8
#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
/* FACSN Bit Fields */
#define FTFA_FACSN_NUMSG_MASK 0xFFu
#define FTFA_FACSN_NUMSG_SHIFT 0
#define FTFA_FACSN_NUMSG_WIDTH 8
#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
/*!
* @}
*/ /* end of group FTFA_Register_Masks */
/* FTFA - Peripheral instance base addresses */
/** Peripheral FTFA base address */
#define FTFA_BASE (0x40020000u)
/** Peripheral FTFA base pointer */
#define FTFA ((FTFA_Type *)FTFA_BASE)
#define FTFA_BASE_PTR (FTFA)
/** Array initializer of FTFA peripheral base addresses */
#define FTFA_BASE_ADDRS { FTFA_BASE }
/** Array initializer of FTFA peripheral base pointers */
#define FTFA_BASE_PTRS { FTFA }
/* ----------------------------------------------------------------------------
-- FTFA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
* @{
*/
/* FTFA - Register instance definitions */
/* FTFA */
#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
#define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
#define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
#define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
#define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
#define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
#define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
#define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
#define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
#define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
#define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
#define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
#define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
#define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
#define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
#define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
#define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
#define FTFA_FACSS FTFA_FACSS_REG(FTFA)
#define FTFA_FACSN FTFA_FACSN_REG(FTFA)
/*!
* @}
*/ /* end of group FTFA_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group FTFA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} GPIO_Type, *GPIO_MemMapPtr;
/* ----------------------------------------------------------------------------
-- GPIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
* @{
*/
/* GPIO - Register accessors */
#define GPIO_PDOR_REG(base) ((base)->PDOR)
#define GPIO_PSOR_REG(base) ((base)->PSOR)
#define GPIO_PCOR_REG(base) ((base)->PCOR)
#define GPIO_PTOR_REG(base) ((base)->PTOR)
#define GPIO_PDIR_REG(base) ((base)->PDIR)
#define GPIO_PDDR_REG(base) ((base)->PDDR)
/*!
* @}
*/ /* end of group GPIO_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/* PDOR Bit Fields */
#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
#define GPIO_PDOR_PDO_SHIFT 0
#define GPIO_PDOR_PDO_WIDTH 32
#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
/* PSOR Bit Fields */
#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
#define GPIO_PSOR_PTSO_SHIFT 0
#define GPIO_PSOR_PTSO_WIDTH 32
#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
/* PCOR Bit Fields */
#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
#define GPIO_PCOR_PTCO_SHIFT 0
#define GPIO_PCOR_PTCO_WIDTH 32
#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
/* PTOR Bit Fields */
#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
#define GPIO_PTOR_PTTO_SHIFT 0
#define GPIO_PTOR_PTTO_WIDTH 32
#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
/* PDIR Bit Fields */
#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
#define GPIO_PDIR_PDI_SHIFT 0
#define GPIO_PDIR_PDI_WIDTH 32
#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
/* PDDR Bit Fields */
#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
#define GPIO_PDDR_PDD_SHIFT 0
#define GPIO_PDDR_PDD_WIDTH 32
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral PTA base address */
#define PTA_BASE (0x400FF000u)
/** Peripheral PTA base pointer */
#define PTA ((GPIO_Type *)PTA_BASE)
#define PTA_BASE_PTR (PTA)
/** Peripheral PTB base address */
#define PTB_BASE (0x400FF040u)
/** Peripheral PTB base pointer */
#define PTB ((GPIO_Type *)PTB_BASE)
#define PTB_BASE_PTR (PTB)
/** Peripheral PTC base address */
#define PTC_BASE (0x400FF080u)
/** Peripheral PTC base pointer */
#define PTC ((GPIO_Type *)PTC_BASE)
#define PTC_BASE_PTR (PTC)
/** Peripheral PTD base address */
#define PTD_BASE (0x400FF0C0u)
/** Peripheral PTD base pointer */
#define PTD ((GPIO_Type *)PTD_BASE)
#define PTD_BASE_PTR (PTD)
/** Peripheral PTE base address */
#define PTE_BASE (0x400FF100u)
/** Peripheral PTE base pointer */
#define PTE ((GPIO_Type *)PTE_BASE)
#define PTE_BASE_PTR (PTE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
/* ----------------------------------------------------------------------------
-- GPIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
* @{
*/
/* GPIO - Register instance definitions */
/* PTA */
#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
/* PTB */
#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
/* PTC */
#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
/* PTD */
#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
/* PTE */
#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
/*!
* @}
*/ /* end of group GPIO_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2S Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
* @{
*/
/** I2S - Register Layout Typedef */
typedef struct {
__IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
__IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
__IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
__IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
__IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
__IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
uint8_t RESERVED_0[8];
__O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_1[28];
__I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
uint8_t RESERVED_2[28];
__IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
uint8_t RESERVED_3[28];
__IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
__IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
__IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
__IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
__IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
__IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
uint8_t RESERVED_4[8];
__I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
uint8_t RESERVED_5[28];
__I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_6[28];
__IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
uint8_t RESERVED_7[28];
__IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
__IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
} I2S_Type, *I2S_MemMapPtr;
/* ----------------------------------------------------------------------------
-- I2S - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
* @{
*/
/* I2S - Register accessors */
#define I2S_TCSR_REG(base) ((base)->TCSR)
#define I2S_TCR1_REG(base) ((base)->TCR1)
#define I2S_TCR2_REG(base) ((base)->TCR2)
#define I2S_TCR3_REG(base) ((base)->TCR3)
#define I2S_TCR4_REG(base) ((base)->TCR4)
#define I2S_TCR5_REG(base) ((base)->TCR5)
#define I2S_TDR_REG(base,index) ((base)->TDR[index])
#define I2S_TDR_COUNT 1
#define I2S_TFR_REG(base,index) ((base)->TFR[index])
#define I2S_TFR_COUNT 1
#define I2S_TMR_REG(base) ((base)->TMR)
#define I2S_RCSR_REG(base) ((base)->RCSR)
#define I2S_RCR1_REG(base) ((base)->RCR1)
#define I2S_RCR2_REG(base) ((base)->RCR2)
#define I2S_RCR3_REG(base) ((base)->RCR3)
#define I2S_RCR4_REG(base) ((base)->RCR4)
#define I2S_RCR5_REG(base) ((base)->RCR5)
#define I2S_RDR_REG(base,index) ((base)->RDR[index])
#define I2S_RDR_COUNT 1
#define I2S_RFR_REG(base,index) ((base)->RFR[index])
#define I2S_RFR_COUNT 1
#define I2S_RMR_REG(base) ((base)->RMR)
#define I2S_MCR_REG(base) ((base)->MCR)
#define I2S_MDR_REG(base) ((base)->MDR)
/*!
* @}
*/ /* end of group I2S_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- I2S Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Masks I2S Register Masks
* @{
*/
/* TCSR Bit Fields */
#define I2S_TCSR_FRDE_MASK 0x1u
#define I2S_TCSR_FRDE_SHIFT 0
#define I2S_TCSR_FRDE_WIDTH 1
#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
#define I2S_TCSR_FWDE_MASK 0x2u
#define I2S_TCSR_FWDE_SHIFT 1
#define I2S_TCSR_FWDE_WIDTH 1
#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
#define I2S_TCSR_FRIE_MASK 0x100u
#define I2S_TCSR_FRIE_SHIFT 8
#define I2S_TCSR_FRIE_WIDTH 1
#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
#define I2S_TCSR_FWIE_MASK 0x200u
#define I2S_TCSR_FWIE_SHIFT 9
#define I2S_TCSR_FWIE_WIDTH 1
#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
#define I2S_TCSR_FEIE_MASK 0x400u
#define I2S_TCSR_FEIE_SHIFT 10
#define I2S_TCSR_FEIE_WIDTH 1
#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
#define I2S_TCSR_SEIE_MASK 0x800u
#define I2S_TCSR_SEIE_SHIFT 11
#define I2S_TCSR_SEIE_WIDTH 1
#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
#define I2S_TCSR_WSIE_MASK 0x1000u
#define I2S_TCSR_WSIE_SHIFT 12
#define I2S_TCSR_WSIE_WIDTH 1
#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
#define I2S_TCSR_FRF_MASK 0x10000u
#define I2S_TCSR_FRF_SHIFT 16
#define I2S_TCSR_FRF_WIDTH 1
#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
#define I2S_TCSR_FWF_MASK 0x20000u
#define I2S_TCSR_FWF_SHIFT 17
#define I2S_TCSR_FWF_WIDTH 1
#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
#define I2S_TCSR_FEF_MASK 0x40000u
#define I2S_TCSR_FEF_SHIFT 18
#define I2S_TCSR_FEF_WIDTH 1
#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
#define I2S_TCSR_SEF_MASK 0x80000u
#define I2S_TCSR_SEF_SHIFT 19
#define I2S_TCSR_SEF_WIDTH 1
#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
#define I2S_TCSR_WSF_MASK 0x100000u
#define I2S_TCSR_WSF_SHIFT 20
#define I2S_TCSR_WSF_WIDTH 1
#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
#define I2S_TCSR_SR_MASK 0x1000000u
#define I2S_TCSR_SR_SHIFT 24
#define I2S_TCSR_SR_WIDTH 1
#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
#define I2S_TCSR_FR_MASK 0x2000000u
#define I2S_TCSR_FR_SHIFT 25
#define I2S_TCSR_FR_WIDTH 1
#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
#define I2S_TCSR_BCE_MASK 0x10000000u
#define I2S_TCSR_BCE_SHIFT 28
#define I2S_TCSR_BCE_WIDTH 1
#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
#define I2S_TCSR_DBGE_MASK 0x20000000u
#define I2S_TCSR_DBGE_SHIFT 29
#define I2S_TCSR_DBGE_WIDTH 1
#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
#define I2S_TCSR_STOPE_MASK 0x40000000u
#define I2S_TCSR_STOPE_SHIFT 30
#define I2S_TCSR_STOPE_WIDTH 1
#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
#define I2S_TCSR_TE_MASK 0x80000000u
#define I2S_TCSR_TE_SHIFT 31
#define I2S_TCSR_TE_WIDTH 1
#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
/* TCR1 Bit Fields */
#define I2S_TCR1_TFW_MASK 0x7u
#define I2S_TCR1_TFW_SHIFT 0
#define I2S_TCR1_TFW_WIDTH 3
#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
/* TCR2 Bit Fields */
#define I2S_TCR2_DIV_MASK 0xFFu
#define I2S_TCR2_DIV_SHIFT 0
#define I2S_TCR2_DIV_WIDTH 8
#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
#define I2S_TCR2_BCD_MASK 0x1000000u
#define I2S_TCR2_BCD_SHIFT 24
#define I2S_TCR2_BCD_WIDTH 1
#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
#define I2S_TCR2_BCP_MASK 0x2000000u
#define I2S_TCR2_BCP_SHIFT 25
#define I2S_TCR2_BCP_WIDTH 1
#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
#define I2S_TCR2_MSEL_MASK 0xC000000u
#define I2S_TCR2_MSEL_SHIFT 26
#define I2S_TCR2_MSEL_WIDTH 2
#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
#define I2S_TCR2_BCI_MASK 0x10000000u
#define I2S_TCR2_BCI_SHIFT 28
#define I2S_TCR2_BCI_WIDTH 1
#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
#define I2S_TCR2_BCS_MASK 0x20000000u
#define I2S_TCR2_BCS_SHIFT 29
#define I2S_TCR2_BCS_WIDTH 1
#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
#define I2S_TCR2_SYNC_MASK 0xC0000000u
#define I2S_TCR2_SYNC_SHIFT 30
#define I2S_TCR2_SYNC_WIDTH 2
#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
/* TCR3 Bit Fields */
#define I2S_TCR3_WDFL_MASK 0xFu
#define I2S_TCR3_WDFL_SHIFT 0
#define I2S_TCR3_WDFL_WIDTH 4
#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
#define I2S_TCR3_TCE_MASK 0x10000u
#define I2S_TCR3_TCE_SHIFT 16
#define I2S_TCR3_TCE_WIDTH 1
#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
/* TCR4 Bit Fields */
#define I2S_TCR4_FSD_MASK 0x1u
#define I2S_TCR4_FSD_SHIFT 0
#define I2S_TCR4_FSD_WIDTH 1
#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
#define I2S_TCR4_FSP_MASK 0x2u
#define I2S_TCR4_FSP_SHIFT 1
#define I2S_TCR4_FSP_WIDTH 1
#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
#define I2S_TCR4_ONDEM_MASK 0x4u
#define I2S_TCR4_ONDEM_SHIFT 2
#define I2S_TCR4_ONDEM_WIDTH 1
#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_ONDEM_SHIFT))&I2S_TCR4_ONDEM_MASK)
#define I2S_TCR4_FSE_MASK 0x8u
#define I2S_TCR4_FSE_SHIFT 3
#define I2S_TCR4_FSE_WIDTH 1
#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
#define I2S_TCR4_MF_MASK 0x10u
#define I2S_TCR4_MF_SHIFT 4
#define I2S_TCR4_MF_WIDTH 1
#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
#define I2S_TCR4_SYWD_MASK 0x1F00u
#define I2S_TCR4_SYWD_SHIFT 8
#define I2S_TCR4_SYWD_WIDTH 5
#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
#define I2S_TCR4_FRSZ_MASK 0xF0000u
#define I2S_TCR4_FRSZ_SHIFT 16
#define I2S_TCR4_FRSZ_WIDTH 4
#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
#define I2S_TCR4_FPACK_MASK 0x3000000u
#define I2S_TCR4_FPACK_SHIFT 24
#define I2S_TCR4_FPACK_WIDTH 2
#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
#define I2S_TCR4_FCONT_MASK 0x10000000u
#define I2S_TCR4_FCONT_SHIFT 28
#define I2S_TCR4_FCONT_WIDTH 1
#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FCONT_SHIFT))&I2S_TCR4_FCONT_MASK)
/* TCR5 Bit Fields */
#define I2S_TCR5_FBT_MASK 0x1F00u
#define I2S_TCR5_FBT_SHIFT 8
#define I2S_TCR5_FBT_WIDTH 5
#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
#define I2S_TCR5_W0W_MASK 0x1F0000u
#define I2S_TCR5_W0W_SHIFT 16
#define I2S_TCR5_W0W_WIDTH 5
#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
#define I2S_TCR5_WNW_MASK 0x1F000000u
#define I2S_TCR5_WNW_SHIFT 24
#define I2S_TCR5_WNW_WIDTH 5
#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
/* TDR Bit Fields */
#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
#define I2S_TDR_TDR_SHIFT 0
#define I2S_TDR_TDR_WIDTH 32
#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
/* TFR Bit Fields */
#define I2S_TFR_RFP_MASK 0xFu
#define I2S_TFR_RFP_SHIFT 0
#define I2S_TFR_RFP_WIDTH 4
#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
#define I2S_TFR_WFP_MASK 0xF0000u
#define I2S_TFR_WFP_SHIFT 16
#define I2S_TFR_WFP_WIDTH 4
#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
/* TMR Bit Fields */
#define I2S_TMR_TWM_MASK 0xFFFFu
#define I2S_TMR_TWM_SHIFT 0
#define I2S_TMR_TWM_WIDTH 16
#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
/* RCSR Bit Fields */
#define I2S_RCSR_FRDE_MASK 0x1u
#define I2S_RCSR_FRDE_SHIFT 0
#define I2S_RCSR_FRDE_WIDTH 1
#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
#define I2S_RCSR_FWDE_MASK 0x2u
#define I2S_RCSR_FWDE_SHIFT 1
#define I2S_RCSR_FWDE_WIDTH 1
#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
#define I2S_RCSR_FRIE_MASK 0x100u
#define I2S_RCSR_FRIE_SHIFT 8
#define I2S_RCSR_FRIE_WIDTH 1
#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
#define I2S_RCSR_FWIE_MASK 0x200u
#define I2S_RCSR_FWIE_SHIFT 9
#define I2S_RCSR_FWIE_WIDTH 1
#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
#define I2S_RCSR_FEIE_MASK 0x400u
#define I2S_RCSR_FEIE_SHIFT 10
#define I2S_RCSR_FEIE_WIDTH 1
#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
#define I2S_RCSR_SEIE_MASK 0x800u
#define I2S_RCSR_SEIE_SHIFT 11
#define I2S_RCSR_SEIE_WIDTH 1
#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
#define I2S_RCSR_WSIE_MASK 0x1000u
#define I2S_RCSR_WSIE_SHIFT 12
#define I2S_RCSR_WSIE_WIDTH 1
#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
#define I2S_RCSR_FRF_MASK 0x10000u
#define I2S_RCSR_FRF_SHIFT 16
#define I2S_RCSR_FRF_WIDTH 1
#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
#define I2S_RCSR_FWF_MASK 0x20000u
#define I2S_RCSR_FWF_SHIFT 17
#define I2S_RCSR_FWF_WIDTH 1
#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
#define I2S_RCSR_FEF_MASK 0x40000u
#define I2S_RCSR_FEF_SHIFT 18
#define I2S_RCSR_FEF_WIDTH 1
#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
#define I2S_RCSR_SEF_MASK 0x80000u
#define I2S_RCSR_SEF_SHIFT 19
#define I2S_RCSR_SEF_WIDTH 1
#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
#define I2S_RCSR_WSF_MASK 0x100000u
#define I2S_RCSR_WSF_SHIFT 20
#define I2S_RCSR_WSF_WIDTH 1
#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
#define I2S_RCSR_SR_MASK 0x1000000u
#define I2S_RCSR_SR_SHIFT 24
#define I2S_RCSR_SR_WIDTH 1
#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
#define I2S_RCSR_FR_MASK 0x2000000u
#define I2S_RCSR_FR_SHIFT 25
#define I2S_RCSR_FR_WIDTH 1
#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
#define I2S_RCSR_BCE_MASK 0x10000000u
#define I2S_RCSR_BCE_SHIFT 28
#define I2S_RCSR_BCE_WIDTH 1
#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
#define I2S_RCSR_DBGE_MASK 0x20000000u
#define I2S_RCSR_DBGE_SHIFT 29
#define I2S_RCSR_DBGE_WIDTH 1
#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
#define I2S_RCSR_STOPE_MASK 0x40000000u
#define I2S_RCSR_STOPE_SHIFT 30
#define I2S_RCSR_STOPE_WIDTH 1
#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
#define I2S_RCSR_RE_MASK 0x80000000u
#define I2S_RCSR_RE_SHIFT 31
#define I2S_RCSR_RE_WIDTH 1
#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
/* RCR1 Bit Fields */
#define I2S_RCR1_RFW_MASK 0x7u
#define I2S_RCR1_RFW_SHIFT 0
#define I2S_RCR1_RFW_WIDTH 3
#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
/* RCR2 Bit Fields */
#define I2S_RCR2_DIV_MASK 0xFFu
#define I2S_RCR2_DIV_SHIFT 0
#define I2S_RCR2_DIV_WIDTH 8
#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
#define I2S_RCR2_BCD_MASK 0x1000000u
#define I2S_RCR2_BCD_SHIFT 24
#define I2S_RCR2_BCD_WIDTH 1
#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
#define I2S_RCR2_BCP_MASK 0x2000000u
#define I2S_RCR2_BCP_SHIFT 25
#define I2S_RCR2_BCP_WIDTH 1
#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
#define I2S_RCR2_MSEL_MASK 0xC000000u
#define I2S_RCR2_MSEL_SHIFT 26
#define I2S_RCR2_MSEL_WIDTH 2
#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
#define I2S_RCR2_BCI_MASK 0x10000000u
#define I2S_RCR2_BCI_SHIFT 28
#define I2S_RCR2_BCI_WIDTH 1
#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
#define I2S_RCR2_BCS_MASK 0x20000000u
#define I2S_RCR2_BCS_SHIFT 29
#define I2S_RCR2_BCS_WIDTH 1
#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
#define I2S_RCR2_SYNC_MASK 0xC0000000u
#define I2S_RCR2_SYNC_SHIFT 30
#define I2S_RCR2_SYNC_WIDTH 2
#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
/* RCR3 Bit Fields */
#define I2S_RCR3_WDFL_MASK 0xFu
#define I2S_RCR3_WDFL_SHIFT 0
#define I2S_RCR3_WDFL_WIDTH 4
#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
#define I2S_RCR3_RCE_MASK 0x10000u
#define I2S_RCR3_RCE_SHIFT 16
#define I2S_RCR3_RCE_WIDTH 1
#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
/* RCR4 Bit Fields */
#define I2S_RCR4_FSD_MASK 0x1u
#define I2S_RCR4_FSD_SHIFT 0
#define I2S_RCR4_FSD_WIDTH 1
#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
#define I2S_RCR4_FSP_MASK 0x2u
#define I2S_RCR4_FSP_SHIFT 1
#define I2S_RCR4_FSP_WIDTH 1
#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
#define I2S_RCR4_ONDEM_MASK 0x4u
#define I2S_RCR4_ONDEM_SHIFT 2
#define I2S_RCR4_ONDEM_WIDTH 1
#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_ONDEM_SHIFT))&I2S_RCR4_ONDEM_MASK)
#define I2S_RCR4_FSE_MASK 0x8u
#define I2S_RCR4_FSE_SHIFT 3
#define I2S_RCR4_FSE_WIDTH 1
#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
#define I2S_RCR4_MF_MASK 0x10u
#define I2S_RCR4_MF_SHIFT 4
#define I2S_RCR4_MF_WIDTH 1
#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
#define I2S_RCR4_SYWD_MASK 0x1F00u
#define I2S_RCR4_SYWD_SHIFT 8
#define I2S_RCR4_SYWD_WIDTH 5
#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
#define I2S_RCR4_FRSZ_MASK 0xF0000u
#define I2S_RCR4_FRSZ_SHIFT 16
#define I2S_RCR4_FRSZ_WIDTH 4
#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
#define I2S_RCR4_FPACK_MASK 0x3000000u
#define I2S_RCR4_FPACK_SHIFT 24
#define I2S_RCR4_FPACK_WIDTH 2
#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
#define I2S_RCR4_FCONT_MASK 0x10000000u
#define I2S_RCR4_FCONT_SHIFT 28
#define I2S_RCR4_FCONT_WIDTH 1
#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FCONT_SHIFT))&I2S_RCR4_FCONT_MASK)
/* RCR5 Bit Fields */
#define I2S_RCR5_FBT_MASK 0x1F00u
#define I2S_RCR5_FBT_SHIFT 8
#define I2S_RCR5_FBT_WIDTH 5
#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
#define I2S_RCR5_W0W_MASK 0x1F0000u
#define I2S_RCR5_W0W_SHIFT 16
#define I2S_RCR5_W0W_WIDTH 5
#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
#define I2S_RCR5_WNW_MASK 0x1F000000u
#define I2S_RCR5_WNW_SHIFT 24
#define I2S_RCR5_WNW_WIDTH 5
#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
/* RDR Bit Fields */
#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
#define I2S_RDR_RDR_SHIFT 0
#define I2S_RDR_RDR_WIDTH 32
#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
/* RFR Bit Fields */
#define I2S_RFR_RFP_MASK 0xFu
#define I2S_RFR_RFP_SHIFT 0
#define I2S_RFR_RFP_WIDTH 4
#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
#define I2S_RFR_WFP_MASK 0xF0000u
#define I2S_RFR_WFP_SHIFT 16
#define I2S_RFR_WFP_WIDTH 4
#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
/* RMR Bit Fields */
#define I2S_RMR_RWM_MASK 0xFFFFu
#define I2S_RMR_RWM_SHIFT 0
#define I2S_RMR_RWM_WIDTH 16
#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
/* MCR Bit Fields */
#define I2S_MCR_MICS_MASK 0x3000000u
#define I2S_MCR_MICS_SHIFT 24
#define I2S_MCR_MICS_WIDTH 2
#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
#define I2S_MCR_MOE_MASK 0x40000000u
#define I2S_MCR_MOE_SHIFT 30
#define I2S_MCR_MOE_WIDTH 1
#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
#define I2S_MCR_DUF_MASK 0x80000000u
#define I2S_MCR_DUF_SHIFT 31
#define I2S_MCR_DUF_WIDTH 1
#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
/* MDR Bit Fields */
#define I2S_MDR_DIVIDE_MASK 0xFFFu
#define I2S_MDR_DIVIDE_SHIFT 0
#define I2S_MDR_DIVIDE_WIDTH 12
#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
#define I2S_MDR_FRACT_MASK 0xFF000u
#define I2S_MDR_FRACT_SHIFT 12
#define I2S_MDR_FRACT_WIDTH 8
#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
/*!
* @}
*/ /* end of group I2S_Register_Masks */
/* I2S - Peripheral instance base addresses */
/** Peripheral I2S0 base address */
#define I2S0_BASE (0x4002F000u)
/** Peripheral I2S0 base pointer */
#define I2S0 ((I2S_Type *)I2S0_BASE)
#define I2S0_BASE_PTR (I2S0)
/** Peripheral I2S1 base address */
#define I2S1_BASE (0x40030000u)
/** Peripheral I2S1 base pointer */
#define I2S1 ((I2S_Type *)I2S1_BASE)
#define I2S1_BASE_PTR (I2S1)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS { I2S0, I2S1 }
/* ----------------------------------------------------------------------------
-- I2S - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
* @{
*/
/* I2S - Register instance definitions */
/* I2S0 */
#define I2S0_TCSR I2S_TCSR_REG(I2S0)
#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
#define I2S0_TMR I2S_TMR_REG(I2S0)
#define I2S0_RCSR I2S_RCSR_REG(I2S0)
#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
#define I2S0_RMR I2S_RMR_REG(I2S0)
#define I2S0_MCR I2S_MCR_REG(I2S0)
#define I2S0_MDR I2S_MDR_REG(I2S0)
/* I2S1 */
#define I2S1_TCSR I2S_TCSR_REG(I2S1)
#define I2S1_TCR1 I2S_TCR1_REG(I2S1)
#define I2S1_TCR2 I2S_TCR2_REG(I2S1)
#define I2S1_TCR3 I2S_TCR3_REG(I2S1)
#define I2S1_TCR4 I2S_TCR4_REG(I2S1)
#define I2S1_TCR5 I2S_TCR5_REG(I2S1)
#define I2S1_TDR0 I2S_TDR_REG(I2S1,0)
#define I2S1_TFR0 I2S_TFR_REG(I2S1,0)
#define I2S1_TMR I2S_TMR_REG(I2S1)
#define I2S1_RCSR I2S_RCSR_REG(I2S1)
#define I2S1_RCR1 I2S_RCR1_REG(I2S1)
#define I2S1_RCR2 I2S_RCR2_REG(I2S1)
#define I2S1_RCR3 I2S_RCR3_REG(I2S1)
#define I2S1_RCR4 I2S_RCR4_REG(I2S1)
#define I2S1_RCR5 I2S_RCR5_REG(I2S1)
#define I2S1_RDR0 I2S_RDR_REG(I2S1,0)
#define I2S1_RFR0 I2S_RFR_REG(I2S1,0)
#define I2S1_RMR I2S_RMR_REG(I2S1)
#define I2S1_MCR I2S_MCR_REG(I2S1)
#define I2S1_MDR I2S_MDR_REG(I2S1)
/* I2S - Register array accessors */
#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
#define I2S1_TDR(index) I2S_TDR_REG(I2S1,index)
#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
#define I2S1_TFR(index) I2S_TFR_REG(I2S1,index)
#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
#define I2S1_RDR(index) I2S_RDR_REG(I2S1,index)
#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
#define I2S1_RFR(index) I2S_RFR_REG(I2S1,index)
/*!
* @}
*/ /* end of group I2S_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LLWU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
* @{
*/
/** LLWU - Register Layout Typedef */
typedef struct {
__IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
__IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
__IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
__IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
__IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */
__IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */
__IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */
__IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */
__IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */
__IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */
__IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */
__IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */
__IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */
__I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */
__IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */
__IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */
} LLWU_Type, *LLWU_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LLWU - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
* @{
*/
/* LLWU - Register accessors */
#define LLWU_PE1_REG(base) ((base)->PE1)
#define LLWU_PE2_REG(base) ((base)->PE2)
#define LLWU_PE3_REG(base) ((base)->PE3)
#define LLWU_PE4_REG(base) ((base)->PE4)
#define LLWU_PE5_REG(base) ((base)->PE5)
#define LLWU_PE6_REG(base) ((base)->PE6)
#define LLWU_PE7_REG(base) ((base)->PE7)
#define LLWU_PE8_REG(base) ((base)->PE8)
#define LLWU_ME_REG(base) ((base)->ME)
#define LLWU_PF1_REG(base) ((base)->PF1)
#define LLWU_PF2_REG(base) ((base)->PF2)
#define LLWU_PF3_REG(base) ((base)->PF3)
#define LLWU_PF4_REG(base) ((base)->PF4)
#define LLWU_MF5_REG(base) ((base)->MF5)
#define LLWU_FILT1_REG(base) ((base)->FILT1)
#define LLWU_FILT2_REG(base) ((base)->FILT2)
/*!
* @}
*/ /* end of group LLWU_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Masks LLWU Register Masks
* @{
*/
/* PE1 Bit Fields */
#define LLWU_PE1_WUPE0_MASK 0x3u
#define LLWU_PE1_WUPE0_SHIFT 0
#define LLWU_PE1_WUPE0_WIDTH 2
#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
#define LLWU_PE1_WUPE1_MASK 0xCu
#define LLWU_PE1_WUPE1_SHIFT 2
#define LLWU_PE1_WUPE1_WIDTH 2
#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
#define LLWU_PE1_WUPE2_MASK 0x30u
#define LLWU_PE1_WUPE2_SHIFT 4
#define LLWU_PE1_WUPE2_WIDTH 2
#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
#define LLWU_PE1_WUPE3_MASK 0xC0u
#define LLWU_PE1_WUPE3_SHIFT 6
#define LLWU_PE1_WUPE3_WIDTH 2
#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
/* PE2 Bit Fields */
#define LLWU_PE2_WUPE4_MASK 0x3u
#define LLWU_PE2_WUPE4_SHIFT 0
#define LLWU_PE2_WUPE4_WIDTH 2
#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
#define LLWU_PE2_WUPE5_MASK 0xCu
#define LLWU_PE2_WUPE5_SHIFT 2
#define LLWU_PE2_WUPE5_WIDTH 2
#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
#define LLWU_PE2_WUPE6_MASK 0x30u
#define LLWU_PE2_WUPE6_SHIFT 4
#define LLWU_PE2_WUPE6_WIDTH 2
#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
#define LLWU_PE2_WUPE7_MASK 0xC0u
#define LLWU_PE2_WUPE7_SHIFT 6
#define LLWU_PE2_WUPE7_WIDTH 2
#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
/* PE3 Bit Fields */
#define LLWU_PE3_WUPE8_MASK 0x3u
#define LLWU_PE3_WUPE8_SHIFT 0
#define LLWU_PE3_WUPE8_WIDTH 2
#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
#define LLWU_PE3_WUPE9_MASK 0xCu
#define LLWU_PE3_WUPE9_SHIFT 2
#define LLWU_PE3_WUPE9_WIDTH 2
#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
#define LLWU_PE3_WUPE10_MASK 0x30u
#define LLWU_PE3_WUPE10_SHIFT 4
#define LLWU_PE3_WUPE10_WIDTH 2
#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
#define LLWU_PE3_WUPE11_MASK 0xC0u
#define LLWU_PE3_WUPE11_SHIFT 6
#define LLWU_PE3_WUPE11_WIDTH 2
#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
/* PE4 Bit Fields */
#define LLWU_PE4_WUPE12_MASK 0x3u
#define LLWU_PE4_WUPE12_SHIFT 0
#define LLWU_PE4_WUPE12_WIDTH 2
#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
#define LLWU_PE4_WUPE13_MASK 0xCu
#define LLWU_PE4_WUPE13_SHIFT 2
#define LLWU_PE4_WUPE13_WIDTH 2
#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
#define LLWU_PE4_WUPE14_MASK 0x30u
#define LLWU_PE4_WUPE14_SHIFT 4
#define LLWU_PE4_WUPE14_WIDTH 2
#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
#define LLWU_PE4_WUPE15_MASK 0xC0u
#define LLWU_PE4_WUPE15_SHIFT 6
#define LLWU_PE4_WUPE15_WIDTH 2
#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
/* PE5 Bit Fields */
#define LLWU_PE5_WUPE16_MASK 0x3u
#define LLWU_PE5_WUPE16_SHIFT 0
#define LLWU_PE5_WUPE16_WIDTH 2
#define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE5_WUPE16_SHIFT))&LLWU_PE5_WUPE16_MASK)
#define LLWU_PE5_WUPE17_MASK 0xCu
#define LLWU_PE5_WUPE17_SHIFT 2
#define LLWU_PE5_WUPE17_WIDTH 2
#define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE5_WUPE17_SHIFT))&LLWU_PE5_WUPE17_MASK)
#define LLWU_PE5_WUPE18_MASK 0x30u
#define LLWU_PE5_WUPE18_SHIFT 4
#define LLWU_PE5_WUPE18_WIDTH 2
#define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE5_WUPE18_SHIFT))&LLWU_PE5_WUPE18_MASK)
#define LLWU_PE5_WUPE19_MASK 0xC0u
#define LLWU_PE5_WUPE19_SHIFT 6
#define LLWU_PE5_WUPE19_WIDTH 2
#define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE5_WUPE19_SHIFT))&LLWU_PE5_WUPE19_MASK)
/* PE6 Bit Fields */
#define LLWU_PE6_WUPE20_MASK 0x3u
#define LLWU_PE6_WUPE20_SHIFT 0
#define LLWU_PE6_WUPE20_WIDTH 2
#define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE6_WUPE20_SHIFT))&LLWU_PE6_WUPE20_MASK)
#define LLWU_PE6_WUPE21_MASK 0xCu
#define LLWU_PE6_WUPE21_SHIFT 2
#define LLWU_PE6_WUPE21_WIDTH 2
#define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE6_WUPE21_SHIFT))&LLWU_PE6_WUPE21_MASK)
#define LLWU_PE6_WUPE22_MASK 0x30u
#define LLWU_PE6_WUPE22_SHIFT 4
#define LLWU_PE6_WUPE22_WIDTH 2
#define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE6_WUPE22_SHIFT))&LLWU_PE6_WUPE22_MASK)
#define LLWU_PE6_WUPE23_MASK 0xC0u
#define LLWU_PE6_WUPE23_SHIFT 6
#define LLWU_PE6_WUPE23_WIDTH 2
#define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE6_WUPE23_SHIFT))&LLWU_PE6_WUPE23_MASK)
/* PE7 Bit Fields */
#define LLWU_PE7_WUPE24_MASK 0x3u
#define LLWU_PE7_WUPE24_SHIFT 0
#define LLWU_PE7_WUPE24_WIDTH 2
#define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE7_WUPE24_SHIFT))&LLWU_PE7_WUPE24_MASK)
#define LLWU_PE7_WUPE25_MASK 0xCu
#define LLWU_PE7_WUPE25_SHIFT 2
#define LLWU_PE7_WUPE25_WIDTH 2
#define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE7_WUPE25_SHIFT))&LLWU_PE7_WUPE25_MASK)
#define LLWU_PE7_WUPE26_MASK 0x30u
#define LLWU_PE7_WUPE26_SHIFT 4
#define LLWU_PE7_WUPE26_WIDTH 2
#define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE7_WUPE26_SHIFT))&LLWU_PE7_WUPE26_MASK)
#define LLWU_PE7_WUPE27_MASK 0xC0u
#define LLWU_PE7_WUPE27_SHIFT 6
#define LLWU_PE7_WUPE27_WIDTH 2
#define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE7_WUPE27_SHIFT))&LLWU_PE7_WUPE27_MASK)
/* PE8 Bit Fields */
#define LLWU_PE8_WUPE28_MASK 0x3u
#define LLWU_PE8_WUPE28_SHIFT 0
#define LLWU_PE8_WUPE28_WIDTH 2
#define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE8_WUPE28_SHIFT))&LLWU_PE8_WUPE28_MASK)
#define LLWU_PE8_WUPE29_MASK 0xCu
#define LLWU_PE8_WUPE29_SHIFT 2
#define LLWU_PE8_WUPE29_WIDTH 2
#define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE8_WUPE29_SHIFT))&LLWU_PE8_WUPE29_MASK)
#define LLWU_PE8_WUPE30_MASK 0x30u
#define LLWU_PE8_WUPE30_SHIFT 4
#define LLWU_PE8_WUPE30_WIDTH 2
#define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE8_WUPE30_SHIFT))&LLWU_PE8_WUPE30_MASK)
#define LLWU_PE8_WUPE31_MASK 0xC0u
#define LLWU_PE8_WUPE31_SHIFT 6
#define LLWU_PE8_WUPE31_WIDTH 2
#define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE8_WUPE31_SHIFT))&LLWU_PE8_WUPE31_MASK)
/* ME Bit Fields */
#define LLWU_ME_WUME0_MASK 0x1u
#define LLWU_ME_WUME0_SHIFT 0
#define LLWU_ME_WUME0_WIDTH 1
#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
#define LLWU_ME_WUME1_MASK 0x2u
#define LLWU_ME_WUME1_SHIFT 1
#define LLWU_ME_WUME1_WIDTH 1
#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
#define LLWU_ME_WUME2_MASK 0x4u
#define LLWU_ME_WUME2_SHIFT 2
#define LLWU_ME_WUME2_WIDTH 1
#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
#define LLWU_ME_WUME3_MASK 0x8u
#define LLWU_ME_WUME3_SHIFT 3
#define LLWU_ME_WUME3_WIDTH 1
#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
#define LLWU_ME_WUME4_MASK 0x10u
#define LLWU_ME_WUME4_SHIFT 4
#define LLWU_ME_WUME4_WIDTH 1
#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
#define LLWU_ME_WUME5_MASK 0x20u
#define LLWU_ME_WUME5_SHIFT 5
#define LLWU_ME_WUME5_WIDTH 1
#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
#define LLWU_ME_WUME6_MASK 0x40u
#define LLWU_ME_WUME6_SHIFT 6
#define LLWU_ME_WUME6_WIDTH 1
#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
#define LLWU_ME_WUME7_MASK 0x80u
#define LLWU_ME_WUME7_SHIFT 7
#define LLWU_ME_WUME7_WIDTH 1
#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
/* PF1 Bit Fields */
#define LLWU_PF1_WUF0_MASK 0x1u
#define LLWU_PF1_WUF0_SHIFT 0
#define LLWU_PF1_WUF0_WIDTH 1
#define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF0_SHIFT))&LLWU_PF1_WUF0_MASK)
#define LLWU_PF1_WUF1_MASK 0x2u
#define LLWU_PF1_WUF1_SHIFT 1
#define LLWU_PF1_WUF1_WIDTH 1
#define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF1_SHIFT))&LLWU_PF1_WUF1_MASK)
#define LLWU_PF1_WUF2_MASK 0x4u
#define LLWU_PF1_WUF2_SHIFT 2
#define LLWU_PF1_WUF2_WIDTH 1
#define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF2_SHIFT))&LLWU_PF1_WUF2_MASK)
#define LLWU_PF1_WUF3_MASK 0x8u
#define LLWU_PF1_WUF3_SHIFT 3
#define LLWU_PF1_WUF3_WIDTH 1
#define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF3_SHIFT))&LLWU_PF1_WUF3_MASK)
#define LLWU_PF1_WUF4_MASK 0x10u
#define LLWU_PF1_WUF4_SHIFT 4
#define LLWU_PF1_WUF4_WIDTH 1
#define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF4_SHIFT))&LLWU_PF1_WUF4_MASK)
#define LLWU_PF1_WUF5_MASK 0x20u
#define LLWU_PF1_WUF5_SHIFT 5
#define LLWU_PF1_WUF5_WIDTH 1
#define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF5_SHIFT))&LLWU_PF1_WUF5_MASK)
#define LLWU_PF1_WUF6_MASK 0x40u
#define LLWU_PF1_WUF6_SHIFT 6
#define LLWU_PF1_WUF6_WIDTH 1
#define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF6_SHIFT))&LLWU_PF1_WUF6_MASK)
#define LLWU_PF1_WUF7_MASK 0x80u
#define LLWU_PF1_WUF7_SHIFT 7
#define LLWU_PF1_WUF7_WIDTH 1
#define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF7_SHIFT))&LLWU_PF1_WUF7_MASK)
/* PF2 Bit Fields */
#define LLWU_PF2_WUF8_MASK 0x1u
#define LLWU_PF2_WUF8_SHIFT 0
#define LLWU_PF2_WUF8_WIDTH 1
#define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF8_SHIFT))&LLWU_PF2_WUF8_MASK)
#define LLWU_PF2_WUF9_MASK 0x2u
#define LLWU_PF2_WUF9_SHIFT 1
#define LLWU_PF2_WUF9_WIDTH 1
#define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF9_SHIFT))&LLWU_PF2_WUF9_MASK)
#define LLWU_PF2_WUF10_MASK 0x4u
#define LLWU_PF2_WUF10_SHIFT 2
#define LLWU_PF2_WUF10_WIDTH 1
#define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF10_SHIFT))&LLWU_PF2_WUF10_MASK)
#define LLWU_PF2_WUF11_MASK 0x8u
#define LLWU_PF2_WUF11_SHIFT 3
#define LLWU_PF2_WUF11_WIDTH 1
#define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF11_SHIFT))&LLWU_PF2_WUF11_MASK)
#define LLWU_PF2_WUF12_MASK 0x10u
#define LLWU_PF2_WUF12_SHIFT 4
#define LLWU_PF2_WUF12_WIDTH 1
#define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF12_SHIFT))&LLWU_PF2_WUF12_MASK)
#define LLWU_PF2_WUF13_MASK 0x20u
#define LLWU_PF2_WUF13_SHIFT 5
#define LLWU_PF2_WUF13_WIDTH 1
#define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF13_SHIFT))&LLWU_PF2_WUF13_MASK)
#define LLWU_PF2_WUF14_MASK 0x40u
#define LLWU_PF2_WUF14_SHIFT 6
#define LLWU_PF2_WUF14_WIDTH 1
#define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF14_SHIFT))&LLWU_PF2_WUF14_MASK)
#define LLWU_PF2_WUF15_MASK 0x80u
#define LLWU_PF2_WUF15_SHIFT 7
#define LLWU_PF2_WUF15_WIDTH 1
#define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF15_SHIFT))&LLWU_PF2_WUF15_MASK)
/* PF3 Bit Fields */
#define LLWU_PF3_WUF16_MASK 0x1u
#define LLWU_PF3_WUF16_SHIFT 0
#define LLWU_PF3_WUF16_WIDTH 1
#define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF16_SHIFT))&LLWU_PF3_WUF16_MASK)
#define LLWU_PF3_WUF17_MASK 0x2u
#define LLWU_PF3_WUF17_SHIFT 1
#define LLWU_PF3_WUF17_WIDTH 1
#define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF17_SHIFT))&LLWU_PF3_WUF17_MASK)
#define LLWU_PF3_WUF18_MASK 0x4u
#define LLWU_PF3_WUF18_SHIFT 2
#define LLWU_PF3_WUF18_WIDTH 1
#define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF18_SHIFT))&LLWU_PF3_WUF18_MASK)
#define LLWU_PF3_WUF19_MASK 0x8u
#define LLWU_PF3_WUF19_SHIFT 3
#define LLWU_PF3_WUF19_WIDTH 1
#define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF19_SHIFT))&LLWU_PF3_WUF19_MASK)
#define LLWU_PF3_WUF20_MASK 0x10u
#define LLWU_PF3_WUF20_SHIFT 4
#define LLWU_PF3_WUF20_WIDTH 1
#define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF20_SHIFT))&LLWU_PF3_WUF20_MASK)
#define LLWU_PF3_WUF21_MASK 0x20u
#define LLWU_PF3_WUF21_SHIFT 5
#define LLWU_PF3_WUF21_WIDTH 1
#define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF21_SHIFT))&LLWU_PF3_WUF21_MASK)
#define LLWU_PF3_WUF22_MASK 0x40u
#define LLWU_PF3_WUF22_SHIFT 6
#define LLWU_PF3_WUF22_WIDTH 1
#define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF22_SHIFT))&LLWU_PF3_WUF22_MASK)
#define LLWU_PF3_WUF23_MASK 0x80u
#define LLWU_PF3_WUF23_SHIFT 7
#define LLWU_PF3_WUF23_WIDTH 1
#define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF23_SHIFT))&LLWU_PF3_WUF23_MASK)
/* PF4 Bit Fields */
#define LLWU_PF4_WUF24_MASK 0x1u
#define LLWU_PF4_WUF24_SHIFT 0
#define LLWU_PF4_WUF24_WIDTH 1
#define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF24_SHIFT))&LLWU_PF4_WUF24_MASK)
#define LLWU_PF4_WUF25_MASK 0x2u
#define LLWU_PF4_WUF25_SHIFT 1
#define LLWU_PF4_WUF25_WIDTH 1
#define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF25_SHIFT))&LLWU_PF4_WUF25_MASK)
#define LLWU_PF4_WUF26_MASK 0x4u
#define LLWU_PF4_WUF26_SHIFT 2
#define LLWU_PF4_WUF26_WIDTH 1
#define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF26_SHIFT))&LLWU_PF4_WUF26_MASK)
#define LLWU_PF4_WUF27_MASK 0x8u
#define LLWU_PF4_WUF27_SHIFT 3
#define LLWU_PF4_WUF27_WIDTH 1
#define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF27_SHIFT))&LLWU_PF4_WUF27_MASK)
#define LLWU_PF4_WUF28_MASK 0x10u
#define LLWU_PF4_WUF28_SHIFT 4
#define LLWU_PF4_WUF28_WIDTH 1
#define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF28_SHIFT))&LLWU_PF4_WUF28_MASK)
#define LLWU_PF4_WUF29_MASK 0x20u
#define LLWU_PF4_WUF29_SHIFT 5
#define LLWU_PF4_WUF29_WIDTH 1
#define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF29_SHIFT))&LLWU_PF4_WUF29_MASK)
#define LLWU_PF4_WUF30_MASK 0x40u
#define LLWU_PF4_WUF30_SHIFT 6
#define LLWU_PF4_WUF30_WIDTH 1
#define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF30_SHIFT))&LLWU_PF4_WUF30_MASK)
#define LLWU_PF4_WUF31_MASK 0x80u
#define LLWU_PF4_WUF31_SHIFT 7
#define LLWU_PF4_WUF31_WIDTH 1
#define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF31_SHIFT))&LLWU_PF4_WUF31_MASK)
/* MF5 Bit Fields */
#define LLWU_MF5_MWUF0_MASK 0x1u
#define LLWU_MF5_MWUF0_SHIFT 0
#define LLWU_MF5_MWUF0_WIDTH 1
#define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF0_SHIFT))&LLWU_MF5_MWUF0_MASK)
#define LLWU_MF5_MWUF1_MASK 0x2u
#define LLWU_MF5_MWUF1_SHIFT 1
#define LLWU_MF5_MWUF1_WIDTH 1
#define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF1_SHIFT))&LLWU_MF5_MWUF1_MASK)
#define LLWU_MF5_MWUF2_MASK 0x4u
#define LLWU_MF5_MWUF2_SHIFT 2
#define LLWU_MF5_MWUF2_WIDTH 1
#define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF2_SHIFT))&LLWU_MF5_MWUF2_MASK)
#define LLWU_MF5_MWUF3_MASK 0x8u
#define LLWU_MF5_MWUF3_SHIFT 3
#define LLWU_MF5_MWUF3_WIDTH 1
#define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF3_SHIFT))&LLWU_MF5_MWUF3_MASK)
#define LLWU_MF5_MWUF4_MASK 0x10u
#define LLWU_MF5_MWUF4_SHIFT 4
#define LLWU_MF5_MWUF4_WIDTH 1
#define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF4_SHIFT))&LLWU_MF5_MWUF4_MASK)
#define LLWU_MF5_MWUF5_MASK 0x20u
#define LLWU_MF5_MWUF5_SHIFT 5
#define LLWU_MF5_MWUF5_WIDTH 1
#define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF5_SHIFT))&LLWU_MF5_MWUF5_MASK)
#define LLWU_MF5_MWUF6_MASK 0x40u
#define LLWU_MF5_MWUF6_SHIFT 6
#define LLWU_MF5_MWUF6_WIDTH 1
#define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF6_SHIFT))&LLWU_MF5_MWUF6_MASK)
#define LLWU_MF5_MWUF7_MASK 0x80u
#define LLWU_MF5_MWUF7_SHIFT 7
#define LLWU_MF5_MWUF7_WIDTH 1
#define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF7_SHIFT))&LLWU_MF5_MWUF7_MASK)
/* FILT1 Bit Fields */
#define LLWU_FILT1_FILTSEL_MASK 0x1Fu
#define LLWU_FILT1_FILTSEL_SHIFT 0
#define LLWU_FILT1_FILTSEL_WIDTH 5
#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
#define LLWU_FILT1_FILTE_MASK 0x60u
#define LLWU_FILT1_FILTE_SHIFT 5
#define LLWU_FILT1_FILTE_WIDTH 2
#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
#define LLWU_FILT1_FILTF_MASK 0x80u
#define LLWU_FILT1_FILTF_SHIFT 7
#define LLWU_FILT1_FILTF_WIDTH 1
#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
/* FILT2 Bit Fields */
#define LLWU_FILT2_FILTSEL_MASK 0x1Fu
#define LLWU_FILT2_FILTSEL_SHIFT 0
#define LLWU_FILT2_FILTSEL_WIDTH 5
#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
#define LLWU_FILT2_FILTE_MASK 0x60u
#define LLWU_FILT2_FILTE_SHIFT 5
#define LLWU_FILT2_FILTE_WIDTH 2
#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
#define LLWU_FILT2_FILTF_MASK 0x80u
#define LLWU_FILT2_FILTF_SHIFT 7
#define LLWU_FILT2_FILTF_WIDTH 1
#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
/*!
* @}
*/ /* end of group LLWU_Register_Masks */
/* LLWU - Peripheral instance base addresses */
/** Peripheral LLWU base address */
#define LLWU_BASE (0x4007C000u)
/** Peripheral LLWU base pointer */
#define LLWU ((LLWU_Type *)LLWU_BASE)
#define LLWU_BASE_PTR (LLWU)
/** Array initializer of LLWU peripheral base addresses */
#define LLWU_BASE_ADDRS { LLWU_BASE }
/** Array initializer of LLWU peripheral base pointers */
#define LLWU_BASE_PTRS { LLWU }
/* ----------------------------------------------------------------------------
-- LLWU - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
* @{
*/
/* LLWU - Register instance definitions */
/* LLWU */
#define LLWU_PE1 LLWU_PE1_REG(LLWU)
#define LLWU_PE2 LLWU_PE2_REG(LLWU)
#define LLWU_PE3 LLWU_PE3_REG(LLWU)
#define LLWU_PE4 LLWU_PE4_REG(LLWU)
#define LLWU_PE5 LLWU_PE5_REG(LLWU)
#define LLWU_PE6 LLWU_PE6_REG(LLWU)
#define LLWU_PE7 LLWU_PE7_REG(LLWU)
#define LLWU_PE8 LLWU_PE8_REG(LLWU)
#define LLWU_ME LLWU_ME_REG(LLWU)
#define LLWU_PF1 LLWU_PF1_REG(LLWU)
#define LLWU_PF2 LLWU_PF2_REG(LLWU)
#define LLWU_PF3 LLWU_PF3_REG(LLWU)
#define LLWU_PF4 LLWU_PF4_REG(LLWU)
#define LLWU_MF5 LLWU_MF5_REG(LLWU)
#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
/*!
* @}
*/ /* end of group LLWU_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPI2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
* @{
*/
/** LPI2C - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */
__IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */
__IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */
__IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */
__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */
__IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */
__IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */
__IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */
uint8_t RESERVED_1[16];
__IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */
uint8_t RESERVED_2[4];
__IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */
uint8_t RESERVED_3[4];
__IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */
uint8_t RESERVED_4[4];
__IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */
__I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */
__O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */
uint8_t RESERVED_5[12];
__I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */
uint8_t RESERVED_6[156];
__IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */
__IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */
__IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */
__IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */
uint8_t RESERVED_7[4];
__IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */
__IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */
uint8_t RESERVED_8[20];
__IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */
uint8_t RESERVED_9[12];
__I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */
__IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */
uint8_t RESERVED_10[8];
__O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */
uint8_t RESERVED_11[12];
__I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */
} LPI2C_Type, *LPI2C_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPI2C - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Accessor_Macros LPI2C - Register accessor macros
* @{
*/
/* LPI2C - Register accessors */
#define LPI2C_VERID_REG(base) ((base)->VERID)
#define LPI2C_PARAM_REG(base) ((base)->PARAM)
#define LPI2C_MCR_REG(base) ((base)->MCR)
#define LPI2C_MSR_REG(base) ((base)->MSR)
#define LPI2C_MIER_REG(base) ((base)->MIER)
#define LPI2C_MDER_REG(base) ((base)->MDER)
#define LPI2C_MCFGR0_REG(base) ((base)->MCFGR0)
#define LPI2C_MCFGR1_REG(base) ((base)->MCFGR1)
#define LPI2C_MCFGR2_REG(base) ((base)->MCFGR2)
#define LPI2C_MCFGR3_REG(base) ((base)->MCFGR3)
#define LPI2C_MDMR_REG(base) ((base)->MDMR)
#define LPI2C_MCCR0_REG(base) ((base)->MCCR0)
#define LPI2C_MCCR1_REG(base) ((base)->MCCR1)
#define LPI2C_MFCR_REG(base) ((base)->MFCR)
#define LPI2C_MFSR_REG(base) ((base)->MFSR)
#define LPI2C_MTDR_REG(base) ((base)->MTDR)
#define LPI2C_MRDR_REG(base) ((base)->MRDR)
#define LPI2C_SCR_REG(base) ((base)->SCR)
#define LPI2C_SSR_REG(base) ((base)->SSR)
#define LPI2C_SIER_REG(base) ((base)->SIER)
#define LPI2C_SDER_REG(base) ((base)->SDER)
#define LPI2C_SCFGR1_REG(base) ((base)->SCFGR1)
#define LPI2C_SCFGR2_REG(base) ((base)->SCFGR2)
#define LPI2C_SAMR_REG(base) ((base)->SAMR)
#define LPI2C_SASR_REG(base) ((base)->SASR)
#define LPI2C_STAR_REG(base) ((base)->STAR)
#define LPI2C_STDR_REG(base) ((base)->STDR)
#define LPI2C_SRDR_REG(base) ((base)->SRDR)
/*!
* @}
*/ /* end of group LPI2C_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPI2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Masks LPI2C Register Masks
* @{
*/
/* VERID Bit Fields */
#define LPI2C_VERID_FEATURE_MASK 0xFFFFu
#define LPI2C_VERID_FEATURE_SHIFT 0
#define LPI2C_VERID_FEATURE_WIDTH 16
#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_FEATURE_SHIFT))&LPI2C_VERID_FEATURE_MASK)
#define LPI2C_VERID_MINOR_MASK 0xFF0000u
#define LPI2C_VERID_MINOR_SHIFT 16
#define LPI2C_VERID_MINOR_WIDTH 8
#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MINOR_SHIFT))&LPI2C_VERID_MINOR_MASK)
#define LPI2C_VERID_MAJOR_MASK 0xFF000000u
#define LPI2C_VERID_MAJOR_SHIFT 24
#define LPI2C_VERID_MAJOR_WIDTH 8
#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MAJOR_SHIFT))&LPI2C_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define LPI2C_PARAM_MTXFIFO_MASK 0xFu
#define LPI2C_PARAM_MTXFIFO_SHIFT 0
#define LPI2C_PARAM_MTXFIFO_WIDTH 4
#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MTXFIFO_SHIFT))&LPI2C_PARAM_MTXFIFO_MASK)
#define LPI2C_PARAM_MRXFIFO_MASK 0xF00u
#define LPI2C_PARAM_MRXFIFO_SHIFT 8
#define LPI2C_PARAM_MRXFIFO_WIDTH 4
#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MRXFIFO_SHIFT))&LPI2C_PARAM_MRXFIFO_MASK)
/* MCR Bit Fields */
#define LPI2C_MCR_MEN_MASK 0x1u
#define LPI2C_MCR_MEN_SHIFT 0
#define LPI2C_MCR_MEN_WIDTH 1
#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_MEN_SHIFT))&LPI2C_MCR_MEN_MASK)
#define LPI2C_MCR_RST_MASK 0x2u
#define LPI2C_MCR_RST_SHIFT 1
#define LPI2C_MCR_RST_WIDTH 1
#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RST_SHIFT))&LPI2C_MCR_RST_MASK)
#define LPI2C_MCR_DOZEN_MASK 0x4u
#define LPI2C_MCR_DOZEN_SHIFT 2
#define LPI2C_MCR_DOZEN_WIDTH 1
#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DOZEN_SHIFT))&LPI2C_MCR_DOZEN_MASK)
#define LPI2C_MCR_DBGEN_MASK 0x8u
#define LPI2C_MCR_DBGEN_SHIFT 3
#define LPI2C_MCR_DBGEN_WIDTH 1
#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DBGEN_SHIFT))&LPI2C_MCR_DBGEN_MASK)
#define LPI2C_MCR_RTF_MASK 0x100u
#define LPI2C_MCR_RTF_SHIFT 8
#define LPI2C_MCR_RTF_WIDTH 1
#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RTF_SHIFT))&LPI2C_MCR_RTF_MASK)
#define LPI2C_MCR_RRF_MASK 0x200u
#define LPI2C_MCR_RRF_SHIFT 9
#define LPI2C_MCR_RRF_WIDTH 1
#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RRF_SHIFT))&LPI2C_MCR_RRF_MASK)
/* MSR Bit Fields */
#define LPI2C_MSR_TDF_MASK 0x1u
#define LPI2C_MSR_TDF_SHIFT 0
#define LPI2C_MSR_TDF_WIDTH 1
#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_TDF_SHIFT))&LPI2C_MSR_TDF_MASK)
#define LPI2C_MSR_RDF_MASK 0x2u
#define LPI2C_MSR_RDF_SHIFT 1
#define LPI2C_MSR_RDF_WIDTH 1
#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_RDF_SHIFT))&LPI2C_MSR_RDF_MASK)
#define LPI2C_MSR_EPF_MASK 0x100u
#define LPI2C_MSR_EPF_SHIFT 8
#define LPI2C_MSR_EPF_WIDTH 1
#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_EPF_SHIFT))&LPI2C_MSR_EPF_MASK)
#define LPI2C_MSR_SDF_MASK 0x200u
#define LPI2C_MSR_SDF_SHIFT 9
#define LPI2C_MSR_SDF_WIDTH 1
#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_SDF_SHIFT))&LPI2C_MSR_SDF_MASK)
#define LPI2C_MSR_NDF_MASK 0x400u
#define LPI2C_MSR_NDF_SHIFT 10
#define LPI2C_MSR_NDF_WIDTH 1
#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_NDF_SHIFT))&LPI2C_MSR_NDF_MASK)
#define LPI2C_MSR_ALF_MASK 0x800u
#define LPI2C_MSR_ALF_SHIFT 11
#define LPI2C_MSR_ALF_WIDTH 1
#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_ALF_SHIFT))&LPI2C_MSR_ALF_MASK)
#define LPI2C_MSR_FEF_MASK 0x1000u
#define LPI2C_MSR_FEF_SHIFT 12
#define LPI2C_MSR_FEF_WIDTH 1
#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_FEF_SHIFT))&LPI2C_MSR_FEF_MASK)
#define LPI2C_MSR_PLTF_MASK 0x2000u
#define LPI2C_MSR_PLTF_SHIFT 13
#define LPI2C_MSR_PLTF_WIDTH 1
#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_PLTF_SHIFT))&LPI2C_MSR_PLTF_MASK)
#define LPI2C_MSR_DMF_MASK 0x4000u
#define LPI2C_MSR_DMF_SHIFT 14
#define LPI2C_MSR_DMF_WIDTH 1
#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_DMF_SHIFT))&LPI2C_MSR_DMF_MASK)
#define LPI2C_MSR_MBF_MASK 0x1000000u
#define LPI2C_MSR_MBF_SHIFT 24
#define LPI2C_MSR_MBF_WIDTH 1
#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_MBF_SHIFT))&LPI2C_MSR_MBF_MASK)
#define LPI2C_MSR_BBF_MASK 0x2000000u
#define LPI2C_MSR_BBF_SHIFT 25
#define LPI2C_MSR_BBF_WIDTH 1
#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_BBF_SHIFT))&LPI2C_MSR_BBF_MASK)
/* MIER Bit Fields */
#define LPI2C_MIER_TDIE_MASK 0x1u
#define LPI2C_MIER_TDIE_SHIFT 0
#define LPI2C_MIER_TDIE_WIDTH 1
#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_TDIE_SHIFT))&LPI2C_MIER_TDIE_MASK)
#define LPI2C_MIER_RDIE_MASK 0x2u
#define LPI2C_MIER_RDIE_SHIFT 1
#define LPI2C_MIER_RDIE_WIDTH 1
#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_RDIE_SHIFT))&LPI2C_MIER_RDIE_MASK)
#define LPI2C_MIER_EPIE_MASK 0x100u
#define LPI2C_MIER_EPIE_SHIFT 8
#define LPI2C_MIER_EPIE_WIDTH 1
#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_EPIE_SHIFT))&LPI2C_MIER_EPIE_MASK)
#define LPI2C_MIER_SDIE_MASK 0x200u
#define LPI2C_MIER_SDIE_SHIFT 9
#define LPI2C_MIER_SDIE_WIDTH 1
#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_SDIE_SHIFT))&LPI2C_MIER_SDIE_MASK)
#define LPI2C_MIER_NDIE_MASK 0x400u
#define LPI2C_MIER_NDIE_SHIFT 10
#define LPI2C_MIER_NDIE_WIDTH 1
#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_NDIE_SHIFT))&LPI2C_MIER_NDIE_MASK)
#define LPI2C_MIER_ALIE_MASK 0x800u
#define LPI2C_MIER_ALIE_SHIFT 11
#define LPI2C_MIER_ALIE_WIDTH 1
#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_ALIE_SHIFT))&LPI2C_MIER_ALIE_MASK)
#define LPI2C_MIER_FEIE_MASK 0x1000u
#define LPI2C_MIER_FEIE_SHIFT 12
#define LPI2C_MIER_FEIE_WIDTH 1
#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_FEIE_SHIFT))&LPI2C_MIER_FEIE_MASK)
#define LPI2C_MIER_PLTIE_MASK 0x2000u
#define LPI2C_MIER_PLTIE_SHIFT 13
#define LPI2C_MIER_PLTIE_WIDTH 1
#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_PLTIE_SHIFT))&LPI2C_MIER_PLTIE_MASK)
#define LPI2C_MIER_DMIE_MASK 0x4000u
#define LPI2C_MIER_DMIE_SHIFT 14
#define LPI2C_MIER_DMIE_WIDTH 1
#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_DMIE_SHIFT))&LPI2C_MIER_DMIE_MASK)
/* MDER Bit Fields */
#define LPI2C_MDER_TDDE_MASK 0x1u
#define LPI2C_MDER_TDDE_SHIFT 0
#define LPI2C_MDER_TDDE_WIDTH 1
#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_TDDE_SHIFT))&LPI2C_MDER_TDDE_MASK)
#define LPI2C_MDER_RDDE_MASK 0x2u
#define LPI2C_MDER_RDDE_SHIFT 1
#define LPI2C_MDER_RDDE_WIDTH 1
#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_RDDE_SHIFT))&LPI2C_MDER_RDDE_MASK)
/* MCFGR0 Bit Fields */
#define LPI2C_MCFGR0_HREN_MASK 0x1u
#define LPI2C_MCFGR0_HREN_SHIFT 0
#define LPI2C_MCFGR0_HREN_WIDTH 1
#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HREN_SHIFT))&LPI2C_MCFGR0_HREN_MASK)
#define LPI2C_MCFGR0_HRPOL_MASK 0x2u
#define LPI2C_MCFGR0_HRPOL_SHIFT 1
#define LPI2C_MCFGR0_HRPOL_WIDTH 1
#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRPOL_SHIFT))&LPI2C_MCFGR0_HRPOL_MASK)
#define LPI2C_MCFGR0_HRSEL_MASK 0x4u
#define LPI2C_MCFGR0_HRSEL_SHIFT 2
#define LPI2C_MCFGR0_HRSEL_WIDTH 1
#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRSEL_SHIFT))&LPI2C_MCFGR0_HRSEL_MASK)
#define LPI2C_MCFGR0_CIRFIFO_MASK 0x100u
#define LPI2C_MCFGR0_CIRFIFO_SHIFT 8
#define LPI2C_MCFGR0_CIRFIFO_WIDTH 1
#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_CIRFIFO_SHIFT))&LPI2C_MCFGR0_CIRFIFO_MASK)
#define LPI2C_MCFGR0_RDMO_MASK 0x200u
#define LPI2C_MCFGR0_RDMO_SHIFT 9
#define LPI2C_MCFGR0_RDMO_WIDTH 1
#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_RDMO_SHIFT))&LPI2C_MCFGR0_RDMO_MASK)
/* MCFGR1 Bit Fields */
#define LPI2C_MCFGR1_PRESCALE_MASK 0x7u
#define LPI2C_MCFGR1_PRESCALE_SHIFT 0
#define LPI2C_MCFGR1_PRESCALE_WIDTH 3
#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PRESCALE_SHIFT))&LPI2C_MCFGR1_PRESCALE_MASK)
#define LPI2C_MCFGR1_AUTOSTOP_MASK 0x100u
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT 8
#define LPI2C_MCFGR1_AUTOSTOP_WIDTH 1
#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_AUTOSTOP_SHIFT))&LPI2C_MCFGR1_AUTOSTOP_MASK)
#define LPI2C_MCFGR1_IGNACK_MASK 0x200u
#define LPI2C_MCFGR1_IGNACK_SHIFT 9
#define LPI2C_MCFGR1_IGNACK_WIDTH 1
#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_IGNACK_SHIFT))&LPI2C_MCFGR1_IGNACK_MASK)
#define LPI2C_MCFGR1_TIMECFG_MASK 0x400u
#define LPI2C_MCFGR1_TIMECFG_SHIFT 10
#define LPI2C_MCFGR1_TIMECFG_WIDTH 1
#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_TIMECFG_SHIFT))&LPI2C_MCFGR1_TIMECFG_MASK)
#define LPI2C_MCFGR1_MATCFG_MASK 0x70000u
#define LPI2C_MCFGR1_MATCFG_SHIFT 16
#define LPI2C_MCFGR1_MATCFG_WIDTH 3
#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_MATCFG_SHIFT))&LPI2C_MCFGR1_MATCFG_MASK)
#define LPI2C_MCFGR1_PINCFG_MASK 0x7000000u
#define LPI2C_MCFGR1_PINCFG_SHIFT 24
#define LPI2C_MCFGR1_PINCFG_WIDTH 3
#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PINCFG_SHIFT))&LPI2C_MCFGR1_PINCFG_MASK)
/* MCFGR2 Bit Fields */
#define LPI2C_MCFGR2_BUSIDLE_MASK 0xFFFu
#define LPI2C_MCFGR2_BUSIDLE_SHIFT 0
#define LPI2C_MCFGR2_BUSIDLE_WIDTH 12
#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_BUSIDLE_SHIFT))&LPI2C_MCFGR2_BUSIDLE_MASK)
#define LPI2C_MCFGR2_FILTSCL_MASK 0xF0000u
#define LPI2C_MCFGR2_FILTSCL_SHIFT 16
#define LPI2C_MCFGR2_FILTSCL_WIDTH 4
#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSCL_SHIFT))&LPI2C_MCFGR2_FILTSCL_MASK)
#define LPI2C_MCFGR2_FILTSDA_MASK 0xF000000u
#define LPI2C_MCFGR2_FILTSDA_SHIFT 24
#define LPI2C_MCFGR2_FILTSDA_WIDTH 4
#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSDA_SHIFT))&LPI2C_MCFGR2_FILTSDA_MASK)
/* MCFGR3 Bit Fields */
#define LPI2C_MCFGR3_PINLOW_MASK 0xFFF00u
#define LPI2C_MCFGR3_PINLOW_SHIFT 8
#define LPI2C_MCFGR3_PINLOW_WIDTH 12
#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR3_PINLOW_SHIFT))&LPI2C_MCFGR3_PINLOW_MASK)
/* MDMR Bit Fields */
#define LPI2C_MDMR_MATCH0_MASK 0xFFu
#define LPI2C_MDMR_MATCH0_SHIFT 0
#define LPI2C_MDMR_MATCH0_WIDTH 8
#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH0_SHIFT))&LPI2C_MDMR_MATCH0_MASK)
#define LPI2C_MDMR_MATCH1_MASK 0xFF0000u
#define LPI2C_MDMR_MATCH1_SHIFT 16
#define LPI2C_MDMR_MATCH1_WIDTH 8
#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH1_SHIFT))&LPI2C_MDMR_MATCH1_MASK)
/* MCCR0 Bit Fields */
#define LPI2C_MCCR0_CLKLO_MASK 0x3Fu
#define LPI2C_MCCR0_CLKLO_SHIFT 0
#define LPI2C_MCCR0_CLKLO_WIDTH 6
#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKLO_SHIFT))&LPI2C_MCCR0_CLKLO_MASK)
#define LPI2C_MCCR0_CLKHI_MASK 0x3F00u
#define LPI2C_MCCR0_CLKHI_SHIFT 8
#define LPI2C_MCCR0_CLKHI_WIDTH 6
#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKHI_SHIFT))&LPI2C_MCCR0_CLKHI_MASK)
#define LPI2C_MCCR0_SETHOLD_MASK 0x3F0000u
#define LPI2C_MCCR0_SETHOLD_SHIFT 16
#define LPI2C_MCCR0_SETHOLD_WIDTH 6
#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_SETHOLD_SHIFT))&LPI2C_MCCR0_SETHOLD_MASK)
#define LPI2C_MCCR0_DATAVD_MASK 0x3F000000u
#define LPI2C_MCCR0_DATAVD_SHIFT 24
#define LPI2C_MCCR0_DATAVD_WIDTH 6
#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_DATAVD_SHIFT))&LPI2C_MCCR0_DATAVD_MASK)
/* MCCR1 Bit Fields */
#define LPI2C_MCCR1_CLKLO_MASK 0x3Fu
#define LPI2C_MCCR1_CLKLO_SHIFT 0
#define LPI2C_MCCR1_CLKLO_WIDTH 6
#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKLO_SHIFT))&LPI2C_MCCR1_CLKLO_MASK)
#define LPI2C_MCCR1_CLKHI_MASK 0x3F00u
#define LPI2C_MCCR1_CLKHI_SHIFT 8
#define LPI2C_MCCR1_CLKHI_WIDTH 6
#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKHI_SHIFT))&LPI2C_MCCR1_CLKHI_MASK)
#define LPI2C_MCCR1_SETHOLD_MASK 0x3F0000u
#define LPI2C_MCCR1_SETHOLD_SHIFT 16
#define LPI2C_MCCR1_SETHOLD_WIDTH 6
#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_SETHOLD_SHIFT))&LPI2C_MCCR1_SETHOLD_MASK)
#define LPI2C_MCCR1_DATAVD_MASK 0x3F000000u
#define LPI2C_MCCR1_DATAVD_SHIFT 24
#define LPI2C_MCCR1_DATAVD_WIDTH 6
#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_DATAVD_SHIFT))&LPI2C_MCCR1_DATAVD_MASK)
/* MFCR Bit Fields */
#define LPI2C_MFCR_TXWATER_MASK 0xFFu
#define LPI2C_MFCR_TXWATER_SHIFT 0
#define LPI2C_MFCR_TXWATER_WIDTH 8
#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_TXWATER_SHIFT))&LPI2C_MFCR_TXWATER_MASK)
#define LPI2C_MFCR_RXWATER_MASK 0xFF0000u
#define LPI2C_MFCR_RXWATER_SHIFT 16
#define LPI2C_MFCR_RXWATER_WIDTH 8
#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_RXWATER_SHIFT))&LPI2C_MFCR_RXWATER_MASK)
/* MFSR Bit Fields */
#define LPI2C_MFSR_TXCOUNT_MASK 0xFFu
#define LPI2C_MFSR_TXCOUNT_SHIFT 0
#define LPI2C_MFSR_TXCOUNT_WIDTH 8
#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_TXCOUNT_SHIFT))&LPI2C_MFSR_TXCOUNT_MASK)
#define LPI2C_MFSR_RXCOUNT_MASK 0xFF0000u
#define LPI2C_MFSR_RXCOUNT_SHIFT 16
#define LPI2C_MFSR_RXCOUNT_WIDTH 8
#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_RXCOUNT_SHIFT))&LPI2C_MFSR_RXCOUNT_MASK)
/* MTDR Bit Fields */
#define LPI2C_MTDR_DATA_MASK 0xFFu
#define LPI2C_MTDR_DATA_SHIFT 0
#define LPI2C_MTDR_DATA_WIDTH 8
#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_DATA_SHIFT))&LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_MASK 0x700u
#define LPI2C_MTDR_CMD_SHIFT 8
#define LPI2C_MTDR_CMD_WIDTH 3
#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_CMD_SHIFT))&LPI2C_MTDR_CMD_MASK)
/* MRDR Bit Fields */
#define LPI2C_MRDR_DATA_MASK 0xFFu
#define LPI2C_MRDR_DATA_SHIFT 0
#define LPI2C_MRDR_DATA_WIDTH 8
#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_DATA_SHIFT))&LPI2C_MRDR_DATA_MASK)
#define LPI2C_MRDR_RXEMPTY_MASK 0x4000u
#define LPI2C_MRDR_RXEMPTY_SHIFT 14
#define LPI2C_MRDR_RXEMPTY_WIDTH 1
#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_RXEMPTY_SHIFT))&LPI2C_MRDR_RXEMPTY_MASK)
/* SCR Bit Fields */
#define LPI2C_SCR_SEN_MASK 0x1u
#define LPI2C_SCR_SEN_SHIFT 0
#define LPI2C_SCR_SEN_WIDTH 1
#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_SEN_SHIFT))&LPI2C_SCR_SEN_MASK)
#define LPI2C_SCR_RST_MASK 0x2u
#define LPI2C_SCR_RST_SHIFT 1
#define LPI2C_SCR_RST_WIDTH 1
#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RST_SHIFT))&LPI2C_SCR_RST_MASK)
#define LPI2C_SCR_FILTEN_MASK 0x10u
#define LPI2C_SCR_FILTEN_SHIFT 4
#define LPI2C_SCR_FILTEN_WIDTH 1
#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTEN_SHIFT))&LPI2C_SCR_FILTEN_MASK)
#define LPI2C_SCR_FILTDZ_MASK 0x20u
#define LPI2C_SCR_FILTDZ_SHIFT 5
#define LPI2C_SCR_FILTDZ_WIDTH 1
#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTDZ_SHIFT))&LPI2C_SCR_FILTDZ_MASK)
#define LPI2C_SCR_RTF_MASK 0x100u
#define LPI2C_SCR_RTF_SHIFT 8
#define LPI2C_SCR_RTF_WIDTH 1
#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RTF_SHIFT))&LPI2C_SCR_RTF_MASK)
#define LPI2C_SCR_RRF_MASK 0x200u
#define LPI2C_SCR_RRF_SHIFT 9
#define LPI2C_SCR_RRF_WIDTH 1
#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RRF_SHIFT))&LPI2C_SCR_RRF_MASK)
/* SSR Bit Fields */
#define LPI2C_SSR_TDF_MASK 0x1u
#define LPI2C_SSR_TDF_SHIFT 0
#define LPI2C_SSR_TDF_WIDTH 1
#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TDF_SHIFT))&LPI2C_SSR_TDF_MASK)
#define LPI2C_SSR_RDF_MASK 0x2u
#define LPI2C_SSR_RDF_SHIFT 1
#define LPI2C_SSR_RDF_WIDTH 1
#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RDF_SHIFT))&LPI2C_SSR_RDF_MASK)
#define LPI2C_SSR_AVF_MASK 0x4u
#define LPI2C_SSR_AVF_SHIFT 2
#define LPI2C_SSR_AVF_WIDTH 1
#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AVF_SHIFT))&LPI2C_SSR_AVF_MASK)
#define LPI2C_SSR_TAF_MASK 0x8u
#define LPI2C_SSR_TAF_SHIFT 3
#define LPI2C_SSR_TAF_WIDTH 1
#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TAF_SHIFT))&LPI2C_SSR_TAF_MASK)
#define LPI2C_SSR_RSF_MASK 0x100u
#define LPI2C_SSR_RSF_SHIFT 8
#define LPI2C_SSR_RSF_WIDTH 1
#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RSF_SHIFT))&LPI2C_SSR_RSF_MASK)
#define LPI2C_SSR_SDF_MASK 0x200u
#define LPI2C_SSR_SDF_SHIFT 9
#define LPI2C_SSR_SDF_WIDTH 1
#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SDF_SHIFT))&LPI2C_SSR_SDF_MASK)
#define LPI2C_SSR_BEF_MASK 0x400u
#define LPI2C_SSR_BEF_SHIFT 10
#define LPI2C_SSR_BEF_WIDTH 1
#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BEF_SHIFT))&LPI2C_SSR_BEF_MASK)
#define LPI2C_SSR_FEF_MASK 0x800u
#define LPI2C_SSR_FEF_SHIFT 11
#define LPI2C_SSR_FEF_WIDTH 1
#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_FEF_SHIFT))&LPI2C_SSR_FEF_MASK)
#define LPI2C_SSR_AM0F_MASK 0x1000u
#define LPI2C_SSR_AM0F_SHIFT 12
#define LPI2C_SSR_AM0F_WIDTH 1
#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM0F_SHIFT))&LPI2C_SSR_AM0F_MASK)
#define LPI2C_SSR_AM1F_MASK 0x2000u
#define LPI2C_SSR_AM1F_SHIFT 13
#define LPI2C_SSR_AM1F_WIDTH 1
#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM1F_SHIFT))&LPI2C_SSR_AM1F_MASK)
#define LPI2C_SSR_GCF_MASK 0x4000u
#define LPI2C_SSR_GCF_SHIFT 14
#define LPI2C_SSR_GCF_WIDTH 1
#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_GCF_SHIFT))&LPI2C_SSR_GCF_MASK)
#define LPI2C_SSR_SARF_MASK 0x8000u
#define LPI2C_SSR_SARF_SHIFT 15
#define LPI2C_SSR_SARF_WIDTH 1
#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SARF_SHIFT))&LPI2C_SSR_SARF_MASK)
#define LPI2C_SSR_SBF_MASK 0x1000000u
#define LPI2C_SSR_SBF_SHIFT 24
#define LPI2C_SSR_SBF_WIDTH 1
#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SBF_SHIFT))&LPI2C_SSR_SBF_MASK)
#define LPI2C_SSR_BBF_MASK 0x2000000u
#define LPI2C_SSR_BBF_SHIFT 25
#define LPI2C_SSR_BBF_WIDTH 1
#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BBF_SHIFT))&LPI2C_SSR_BBF_MASK)
/* SIER Bit Fields */
#define LPI2C_SIER_TDIE_MASK 0x1u
#define LPI2C_SIER_TDIE_SHIFT 0
#define LPI2C_SIER_TDIE_WIDTH 1
#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TDIE_SHIFT))&LPI2C_SIER_TDIE_MASK)
#define LPI2C_SIER_RDIE_MASK 0x2u
#define LPI2C_SIER_RDIE_SHIFT 1
#define LPI2C_SIER_RDIE_WIDTH 1
#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RDIE_SHIFT))&LPI2C_SIER_RDIE_MASK)
#define LPI2C_SIER_AVIE_MASK 0x4u
#define LPI2C_SIER_AVIE_SHIFT 2
#define LPI2C_SIER_AVIE_WIDTH 1
#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AVIE_SHIFT))&LPI2C_SIER_AVIE_MASK)
#define LPI2C_SIER_TAIE_MASK 0x8u
#define LPI2C_SIER_TAIE_SHIFT 3
#define LPI2C_SIER_TAIE_WIDTH 1
#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TAIE_SHIFT))&LPI2C_SIER_TAIE_MASK)
#define LPI2C_SIER_RSIE_MASK 0x100u
#define LPI2C_SIER_RSIE_SHIFT 8
#define LPI2C_SIER_RSIE_WIDTH 1
#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RSIE_SHIFT))&LPI2C_SIER_RSIE_MASK)
#define LPI2C_SIER_SDIE_MASK 0x200u
#define LPI2C_SIER_SDIE_SHIFT 9
#define LPI2C_SIER_SDIE_WIDTH 1
#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SDIE_SHIFT))&LPI2C_SIER_SDIE_MASK)
#define LPI2C_SIER_BEIE_MASK 0x400u
#define LPI2C_SIER_BEIE_SHIFT 10
#define LPI2C_SIER_BEIE_WIDTH 1
#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_BEIE_SHIFT))&LPI2C_SIER_BEIE_MASK)
#define LPI2C_SIER_FEIE_MASK 0x800u
#define LPI2C_SIER_FEIE_SHIFT 11
#define LPI2C_SIER_FEIE_WIDTH 1
#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_FEIE_SHIFT))&LPI2C_SIER_FEIE_MASK)
#define LPI2C_SIER_AM0IE_MASK 0x1000u
#define LPI2C_SIER_AM0IE_SHIFT 12
#define LPI2C_SIER_AM0IE_WIDTH 1
#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM0IE_SHIFT))&LPI2C_SIER_AM0IE_MASK)
#define LPI2C_SIER_AM1F_MASK 0x2000u
#define LPI2C_SIER_AM1F_SHIFT 13
#define LPI2C_SIER_AM1F_WIDTH 1
#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM1F_SHIFT))&LPI2C_SIER_AM1F_MASK)
#define LPI2C_SIER_GCIE_MASK 0x4000u
#define LPI2C_SIER_GCIE_SHIFT 14
#define LPI2C_SIER_GCIE_WIDTH 1
#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_GCIE_SHIFT))&LPI2C_SIER_GCIE_MASK)
#define LPI2C_SIER_SARIE_MASK 0x8000u
#define LPI2C_SIER_SARIE_SHIFT 15
#define LPI2C_SIER_SARIE_WIDTH 1
#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SARIE_SHIFT))&LPI2C_SIER_SARIE_MASK)
/* SDER Bit Fields */
#define LPI2C_SDER_TDDE_MASK 0x1u
#define LPI2C_SDER_TDDE_SHIFT 0
#define LPI2C_SDER_TDDE_WIDTH 1
#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_TDDE_SHIFT))&LPI2C_SDER_TDDE_MASK)
#define LPI2C_SDER_RDDE_MASK 0x2u
#define LPI2C_SDER_RDDE_SHIFT 1
#define LPI2C_SDER_RDDE_WIDTH 1
#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_RDDE_SHIFT))&LPI2C_SDER_RDDE_MASK)
#define LPI2C_SDER_AVDE_MASK 0x4u
#define LPI2C_SDER_AVDE_SHIFT 2
#define LPI2C_SDER_AVDE_WIDTH 1
#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_AVDE_SHIFT))&LPI2C_SDER_AVDE_MASK)
/* SCFGR1 Bit Fields */
#define LPI2C_SCFGR1_ADRSTALL_MASK 0x1u
#define LPI2C_SCFGR1_ADRSTALL_SHIFT 0
#define LPI2C_SCFGR1_ADRSTALL_WIDTH 1
#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADRSTALL_SHIFT))&LPI2C_SCFGR1_ADRSTALL_MASK)
#define LPI2C_SCFGR1_RXSTALL_MASK 0x2u
#define LPI2C_SCFGR1_RXSTALL_SHIFT 1
#define LPI2C_SCFGR1_RXSTALL_WIDTH 1
#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXSTALL_SHIFT))&LPI2C_SCFGR1_RXSTALL_MASK)
#define LPI2C_SCFGR1_TXDSTALL_MASK 0x4u
#define LPI2C_SCFGR1_TXDSTALL_SHIFT 2
#define LPI2C_SCFGR1_TXDSTALL_WIDTH 1
#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXDSTALL_SHIFT))&LPI2C_SCFGR1_TXDSTALL_MASK)
#define LPI2C_SCFGR1_ACKSTALL_MASK 0x8u
#define LPI2C_SCFGR1_ACKSTALL_SHIFT 3
#define LPI2C_SCFGR1_ACKSTALL_WIDTH 1
#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ACKSTALL_SHIFT))&LPI2C_SCFGR1_ACKSTALL_MASK)
#define LPI2C_SCFGR1_GCEN_MASK 0x100u
#define LPI2C_SCFGR1_GCEN_SHIFT 8
#define LPI2C_SCFGR1_GCEN_WIDTH 1
#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_GCEN_SHIFT))&LPI2C_SCFGR1_GCEN_MASK)
#define LPI2C_SCFGR1_SAEN_MASK 0x200u
#define LPI2C_SCFGR1_SAEN_SHIFT 9
#define LPI2C_SCFGR1_SAEN_WIDTH 1
#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_SAEN_SHIFT))&LPI2C_SCFGR1_SAEN_MASK)
#define LPI2C_SCFGR1_TXCFG_MASK 0x400u
#define LPI2C_SCFGR1_TXCFG_SHIFT 10
#define LPI2C_SCFGR1_TXCFG_WIDTH 1
#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXCFG_SHIFT))&LPI2C_SCFGR1_TXCFG_MASK)
#define LPI2C_SCFGR1_RXCFG_MASK 0x800u
#define LPI2C_SCFGR1_RXCFG_SHIFT 11
#define LPI2C_SCFGR1_RXCFG_WIDTH 1
#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXCFG_SHIFT))&LPI2C_SCFGR1_RXCFG_MASK)
#define LPI2C_SCFGR1_IGNACK_MASK 0x1000u
#define LPI2C_SCFGR1_IGNACK_SHIFT 12
#define LPI2C_SCFGR1_IGNACK_WIDTH 1
#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_IGNACK_SHIFT))&LPI2C_SCFGR1_IGNACK_MASK)
#define LPI2C_SCFGR1_HSMEN_MASK 0x2000u
#define LPI2C_SCFGR1_HSMEN_SHIFT 13
#define LPI2C_SCFGR1_HSMEN_WIDTH 1
#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_HSMEN_SHIFT))&LPI2C_SCFGR1_HSMEN_MASK)
#define LPI2C_SCFGR1_ADDRCFG_MASK 0x70000u
#define LPI2C_SCFGR1_ADDRCFG_SHIFT 16
#define LPI2C_SCFGR1_ADDRCFG_WIDTH 3
#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADDRCFG_SHIFT))&LPI2C_SCFGR1_ADDRCFG_MASK)
/* SCFGR2 Bit Fields */
#define LPI2C_SCFGR2_CLKHOLD_MASK 0xFu
#define LPI2C_SCFGR2_CLKHOLD_SHIFT 0
#define LPI2C_SCFGR2_CLKHOLD_WIDTH 4
#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_CLKHOLD_SHIFT))&LPI2C_SCFGR2_CLKHOLD_MASK)
#define LPI2C_SCFGR2_DATAVD_MASK 0x3F00u
#define LPI2C_SCFGR2_DATAVD_SHIFT 8
#define LPI2C_SCFGR2_DATAVD_WIDTH 6
#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_DATAVD_SHIFT))&LPI2C_SCFGR2_DATAVD_MASK)
#define LPI2C_SCFGR2_FILTSCL_MASK 0xF0000u
#define LPI2C_SCFGR2_FILTSCL_SHIFT 16
#define LPI2C_SCFGR2_FILTSCL_WIDTH 4
#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSCL_SHIFT))&LPI2C_SCFGR2_FILTSCL_MASK)
#define LPI2C_SCFGR2_FILTSDA_MASK 0xF000000u
#define LPI2C_SCFGR2_FILTSDA_SHIFT 24
#define LPI2C_SCFGR2_FILTSDA_WIDTH 4
#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSDA_SHIFT))&LPI2C_SCFGR2_FILTSDA_MASK)
/* SAMR Bit Fields */
#define LPI2C_SAMR_ADDR0_MASK 0x7FEu
#define LPI2C_SAMR_ADDR0_SHIFT 1
#define LPI2C_SAMR_ADDR0_WIDTH 10
#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR0_SHIFT))&LPI2C_SAMR_ADDR0_MASK)
#define LPI2C_SAMR_ADDR1_MASK 0x7FE0000u
#define LPI2C_SAMR_ADDR1_SHIFT 17
#define LPI2C_SAMR_ADDR1_WIDTH 10
#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR1_SHIFT))&LPI2C_SAMR_ADDR1_MASK)
/* SASR Bit Fields */
#define LPI2C_SASR_RADDR_MASK 0x7FFu
#define LPI2C_SASR_RADDR_SHIFT 0
#define LPI2C_SASR_RADDR_WIDTH 11
#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_RADDR_SHIFT))&LPI2C_SASR_RADDR_MASK)
#define LPI2C_SASR_ANV_MASK 0x4000u
#define LPI2C_SASR_ANV_SHIFT 14
#define LPI2C_SASR_ANV_WIDTH 1
#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_ANV_SHIFT))&LPI2C_SASR_ANV_MASK)
/* STAR Bit Fields */
#define LPI2C_STAR_TXNACK_MASK 0x1u
#define LPI2C_STAR_TXNACK_SHIFT 0
#define LPI2C_STAR_TXNACK_WIDTH 1
#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STAR_TXNACK_SHIFT))&LPI2C_STAR_TXNACK_MASK)
/* STDR Bit Fields */
#define LPI2C_STDR_DATA_MASK 0xFFu
#define LPI2C_STDR_DATA_SHIFT 0
#define LPI2C_STDR_DATA_WIDTH 8
#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STDR_DATA_SHIFT))&LPI2C_STDR_DATA_MASK)
/* SRDR Bit Fields */
#define LPI2C_SRDR_DATA_MASK 0xFFu
#define LPI2C_SRDR_DATA_SHIFT 0
#define LPI2C_SRDR_DATA_WIDTH 8
#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_DATA_SHIFT))&LPI2C_SRDR_DATA_MASK)
#define LPI2C_SRDR_RXEMPTY_MASK 0x4000u
#define LPI2C_SRDR_RXEMPTY_SHIFT 14
#define LPI2C_SRDR_RXEMPTY_WIDTH 1
#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_RXEMPTY_SHIFT))&LPI2C_SRDR_RXEMPTY_MASK)
#define LPI2C_SRDR_SOF_MASK 0x8000u
#define LPI2C_SRDR_SOF_SHIFT 15
#define LPI2C_SRDR_SOF_WIDTH 1
#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_SOF_SHIFT))&LPI2C_SRDR_SOF_MASK)
/*!
* @}
*/ /* end of group LPI2C_Register_Masks */
/* LPI2C - Peripheral instance base addresses */
/** Peripheral LPI2C0 base address */
#define LPI2C0_BASE (0x40066000u)
/** Peripheral LPI2C0 base pointer */
#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
#define LPI2C0_BASE_PTR (LPI2C0)
/** Peripheral LPI2C1 base address */
#define LPI2C1_BASE (0x40067000u)
/** Peripheral LPI2C1 base pointer */
#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
#define LPI2C1_BASE_PTR (LPI2C1)
/** Array initializer of LPI2C peripheral base addresses */
#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE }
/** Array initializer of LPI2C peripheral base pointers */
#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1 }
/* ----------------------------------------------------------------------------
-- LPI2C - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Accessor_Macros LPI2C - Register accessor macros
* @{
*/
/* LPI2C - Register instance definitions */
/* LPI2C0 */
#define LPI2C0_VERID LPI2C_VERID_REG(LPI2C0)
#define LPI2C0_PARAM LPI2C_PARAM_REG(LPI2C0)
#define LPI2C0_MCR LPI2C_MCR_REG(LPI2C0)
#define LPI2C0_MSR LPI2C_MSR_REG(LPI2C0)
#define LPI2C0_MIER LPI2C_MIER_REG(LPI2C0)
#define LPI2C0_MDER LPI2C_MDER_REG(LPI2C0)
#define LPI2C0_MCFGR0 LPI2C_MCFGR0_REG(LPI2C0)
#define LPI2C0_MCFGR1 LPI2C_MCFGR1_REG(LPI2C0)
#define LPI2C0_MCFGR2 LPI2C_MCFGR2_REG(LPI2C0)
#define LPI2C0_MCFGR3 LPI2C_MCFGR3_REG(LPI2C0)
#define LPI2C0_MDMR LPI2C_MDMR_REG(LPI2C0)
#define LPI2C0_MCCR0 LPI2C_MCCR0_REG(LPI2C0)
#define LPI2C0_MCCR1 LPI2C_MCCR1_REG(LPI2C0)
#define LPI2C0_MFCR LPI2C_MFCR_REG(LPI2C0)
#define LPI2C0_MFSR LPI2C_MFSR_REG(LPI2C0)
#define LPI2C0_MTDR LPI2C_MTDR_REG(LPI2C0)
#define LPI2C0_MRDR LPI2C_MRDR_REG(LPI2C0)
#define LPI2C0_SCR LPI2C_SCR_REG(LPI2C0)
#define LPI2C0_SSR LPI2C_SSR_REG(LPI2C0)
#define LPI2C0_SIER LPI2C_SIER_REG(LPI2C0)
#define LPI2C0_SDER LPI2C_SDER_REG(LPI2C0)
#define LPI2C0_SCFGR1 LPI2C_SCFGR1_REG(LPI2C0)
#define LPI2C0_SCFGR2 LPI2C_SCFGR2_REG(LPI2C0)
#define LPI2C0_SAMR LPI2C_SAMR_REG(LPI2C0)
#define LPI2C0_SASR LPI2C_SASR_REG(LPI2C0)
#define LPI2C0_STAR LPI2C_STAR_REG(LPI2C0)
#define LPI2C0_STDR LPI2C_STDR_REG(LPI2C0)
#define LPI2C0_SRDR LPI2C_SRDR_REG(LPI2C0)
/* LPI2C1 */
#define LPI2C1_VERID LPI2C_VERID_REG(LPI2C1)
#define LPI2C1_PARAM LPI2C_PARAM_REG(LPI2C1)
#define LPI2C1_MCR LPI2C_MCR_REG(LPI2C1)
#define LPI2C1_MSR LPI2C_MSR_REG(LPI2C1)
#define LPI2C1_MIER LPI2C_MIER_REG(LPI2C1)
#define LPI2C1_MDER LPI2C_MDER_REG(LPI2C1)
#define LPI2C1_MCFGR0 LPI2C_MCFGR0_REG(LPI2C1)
#define LPI2C1_MCFGR1 LPI2C_MCFGR1_REG(LPI2C1)
#define LPI2C1_MCFGR2 LPI2C_MCFGR2_REG(LPI2C1)
#define LPI2C1_MCFGR3 LPI2C_MCFGR3_REG(LPI2C1)
#define LPI2C1_MDMR LPI2C_MDMR_REG(LPI2C1)
#define LPI2C1_MCCR0 LPI2C_MCCR0_REG(LPI2C1)
#define LPI2C1_MCCR1 LPI2C_MCCR1_REG(LPI2C1)
#define LPI2C1_MFCR LPI2C_MFCR_REG(LPI2C1)
#define LPI2C1_MFSR LPI2C_MFSR_REG(LPI2C1)
#define LPI2C1_MTDR LPI2C_MTDR_REG(LPI2C1)
#define LPI2C1_MRDR LPI2C_MRDR_REG(LPI2C1)
#define LPI2C1_SCR LPI2C_SCR_REG(LPI2C1)
#define LPI2C1_SSR LPI2C_SSR_REG(LPI2C1)
#define LPI2C1_SIER LPI2C_SIER_REG(LPI2C1)
#define LPI2C1_SDER LPI2C_SDER_REG(LPI2C1)
#define LPI2C1_SCFGR1 LPI2C_SCFGR1_REG(LPI2C1)
#define LPI2C1_SCFGR2 LPI2C_SCFGR2_REG(LPI2C1)
#define LPI2C1_SAMR LPI2C_SAMR_REG(LPI2C1)
#define LPI2C1_SASR LPI2C_SASR_REG(LPI2C1)
#define LPI2C1_STAR LPI2C_STAR_REG(LPI2C1)
#define LPI2C1_STDR LPI2C_STDR_REG(LPI2C1)
#define LPI2C1_SRDR LPI2C_SRDR_REG(LPI2C1)
/*!
* @}
*/ /* end of group LPI2C_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LPI2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPTMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
* @{
*/
/** LPTMR - Register Layout Typedef */
typedef struct {
__IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
__IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
} LPTMR_Type, *LPTMR_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPTMR - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
* @{
*/
/* LPTMR - Register accessors */
#define LPTMR_CSR_REG(base) ((base)->CSR)
#define LPTMR_PSR_REG(base) ((base)->PSR)
#define LPTMR_CMR_REG(base) ((base)->CMR)
#define LPTMR_CNR_REG(base) ((base)->CNR)
/*!
* @}
*/ /* end of group LPTMR_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
* @{
*/
/* CSR Bit Fields */
#define LPTMR_CSR_TEN_MASK 0x1u
#define LPTMR_CSR_TEN_SHIFT 0
#define LPTMR_CSR_TEN_WIDTH 1
#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
#define LPTMR_CSR_TMS_MASK 0x2u
#define LPTMR_CSR_TMS_SHIFT 1
#define LPTMR_CSR_TMS_WIDTH 1
#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
#define LPTMR_CSR_TFC_MASK 0x4u
#define LPTMR_CSR_TFC_SHIFT 2
#define LPTMR_CSR_TFC_WIDTH 1
#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
#define LPTMR_CSR_TPP_MASK 0x8u
#define LPTMR_CSR_TPP_SHIFT 3
#define LPTMR_CSR_TPP_WIDTH 1
#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
#define LPTMR_CSR_TPS_MASK 0x30u
#define LPTMR_CSR_TPS_SHIFT 4
#define LPTMR_CSR_TPS_WIDTH 2
#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
#define LPTMR_CSR_TIE_MASK 0x40u
#define LPTMR_CSR_TIE_SHIFT 6
#define LPTMR_CSR_TIE_WIDTH 1
#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
#define LPTMR_CSR_TCF_MASK 0x80u
#define LPTMR_CSR_TCF_SHIFT 7
#define LPTMR_CSR_TCF_WIDTH 1
#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
/* PSR Bit Fields */
#define LPTMR_PSR_PCS_MASK 0x3u
#define LPTMR_PSR_PCS_SHIFT 0
#define LPTMR_PSR_PCS_WIDTH 2
#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
#define LPTMR_PSR_PBYP_MASK 0x4u
#define LPTMR_PSR_PBYP_SHIFT 2
#define LPTMR_PSR_PBYP_WIDTH 1
#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
#define LPTMR_PSR_PRESCALE_MASK 0x78u
#define LPTMR_PSR_PRESCALE_SHIFT 3
#define LPTMR_PSR_PRESCALE_WIDTH 4
#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
/* CMR Bit Fields */
#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
#define LPTMR_CMR_COMPARE_SHIFT 0
#define LPTMR_CMR_COMPARE_WIDTH 16
#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
/* CNR Bit Fields */
#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
#define LPTMR_CNR_COUNTER_SHIFT 0
#define LPTMR_CNR_COUNTER_WIDTH 16
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
/*!
* @}
*/ /* end of group LPTMR_Register_Masks */
/* LPTMR - Peripheral instance base addresses */
/** Peripheral LPTMR0 base address */
#define LPTMR0_BASE (0x40040000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
#define LPTMR0_BASE_PTR (LPTMR0)
/** Array initializer of LPTMR peripheral base addresses */
#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
/** Array initializer of LPTMR peripheral base pointers */
#define LPTMR_BASE_PTRS { LPTMR0 }
/* ----------------------------------------------------------------------------
-- LPTMR - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
* @{
*/
/* LPTMR - Register instance definitions */
/* LPTMR0 */
#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
/*!
* @}
*/ /* end of group LPTMR_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPUART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
* @{
*/
/** LPUART - Register Layout Typedef */
typedef struct {
__IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
__IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
__IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
__IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
} LPUART_Type, *LPUART_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPUART - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
* @{
*/
/* LPUART - Register accessors */
#define LPUART_BAUD_REG(base) ((base)->BAUD)
#define LPUART_STAT_REG(base) ((base)->STAT)
#define LPUART_CTRL_REG(base) ((base)->CTRL)
#define LPUART_DATA_REG(base) ((base)->DATA)
#define LPUART_MATCH_REG(base) ((base)->MATCH)
#define LPUART_MODIR_REG(base) ((base)->MODIR)
/*!
* @}
*/ /* end of group LPUART_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPUART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Masks LPUART Register Masks
* @{
*/
/* BAUD Bit Fields */
#define LPUART_BAUD_SBR_MASK 0x1FFFu
#define LPUART_BAUD_SBR_SHIFT 0
#define LPUART_BAUD_SBR_WIDTH 13
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
#define LPUART_BAUD_SBNS_MASK 0x2000u
#define LPUART_BAUD_SBNS_SHIFT 13
#define LPUART_BAUD_SBNS_WIDTH 1
#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
#define LPUART_BAUD_RXEDGIE_SHIFT 14
#define LPUART_BAUD_RXEDGIE_WIDTH 1
#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
#define LPUART_BAUD_LBKDIE_MASK 0x8000u
#define LPUART_BAUD_LBKDIE_SHIFT 15
#define LPUART_BAUD_LBKDIE_WIDTH 1
#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
#define LPUART_BAUD_RESYNCDIS_SHIFT 16
#define LPUART_BAUD_RESYNCDIS_WIDTH 1
#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
#define LPUART_BAUD_BOTHEDGE_SHIFT 17
#define LPUART_BAUD_BOTHEDGE_WIDTH 1
#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
#define LPUART_BAUD_MATCFG_MASK 0xC0000u
#define LPUART_BAUD_MATCFG_SHIFT 18
#define LPUART_BAUD_MATCFG_WIDTH 2
#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
#define LPUART_BAUD_RDMAE_MASK 0x200000u
#define LPUART_BAUD_RDMAE_SHIFT 21
#define LPUART_BAUD_RDMAE_WIDTH 1
#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
#define LPUART_BAUD_TDMAE_MASK 0x800000u
#define LPUART_BAUD_TDMAE_SHIFT 23
#define LPUART_BAUD_TDMAE_WIDTH 1
#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
#define LPUART_BAUD_OSR_MASK 0x1F000000u
#define LPUART_BAUD_OSR_SHIFT 24
#define LPUART_BAUD_OSR_WIDTH 5
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
#define LPUART_BAUD_M10_MASK 0x20000000u
#define LPUART_BAUD_M10_SHIFT 29
#define LPUART_BAUD_M10_WIDTH 1
#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
#define LPUART_BAUD_MAEN2_MASK 0x40000000u
#define LPUART_BAUD_MAEN2_SHIFT 30
#define LPUART_BAUD_MAEN2_WIDTH 1
#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
#define LPUART_BAUD_MAEN1_MASK 0x80000000u
#define LPUART_BAUD_MAEN1_SHIFT 31
#define LPUART_BAUD_MAEN1_WIDTH 1
#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
/* STAT Bit Fields */
#define LPUART_STAT_MA2F_MASK 0x4000u
#define LPUART_STAT_MA2F_SHIFT 14
#define LPUART_STAT_MA2F_WIDTH 1
#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
#define LPUART_STAT_MA1F_MASK 0x8000u
#define LPUART_STAT_MA1F_SHIFT 15
#define LPUART_STAT_MA1F_WIDTH 1
#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
#define LPUART_STAT_PF_MASK 0x10000u
#define LPUART_STAT_PF_SHIFT 16
#define LPUART_STAT_PF_WIDTH 1
#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
#define LPUART_STAT_FE_MASK 0x20000u
#define LPUART_STAT_FE_SHIFT 17
#define LPUART_STAT_FE_WIDTH 1
#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
#define LPUART_STAT_NF_MASK 0x40000u
#define LPUART_STAT_NF_SHIFT 18
#define LPUART_STAT_NF_WIDTH 1
#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
#define LPUART_STAT_OR_MASK 0x80000u
#define LPUART_STAT_OR_SHIFT 19
#define LPUART_STAT_OR_WIDTH 1
#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
#define LPUART_STAT_IDLE_MASK 0x100000u
#define LPUART_STAT_IDLE_SHIFT 20
#define LPUART_STAT_IDLE_WIDTH 1
#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
#define LPUART_STAT_RDRF_MASK 0x200000u
#define LPUART_STAT_RDRF_SHIFT 21
#define LPUART_STAT_RDRF_WIDTH 1
#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
#define LPUART_STAT_TC_MASK 0x400000u
#define LPUART_STAT_TC_SHIFT 22
#define LPUART_STAT_TC_WIDTH 1
#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
#define LPUART_STAT_TDRE_MASK 0x800000u
#define LPUART_STAT_TDRE_SHIFT 23
#define LPUART_STAT_TDRE_WIDTH 1
#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
#define LPUART_STAT_RAF_MASK 0x1000000u
#define LPUART_STAT_RAF_SHIFT 24
#define LPUART_STAT_RAF_WIDTH 1
#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
#define LPUART_STAT_LBKDE_MASK 0x2000000u
#define LPUART_STAT_LBKDE_SHIFT 25
#define LPUART_STAT_LBKDE_WIDTH 1
#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
#define LPUART_STAT_BRK13_MASK 0x4000000u
#define LPUART_STAT_BRK13_SHIFT 26
#define LPUART_STAT_BRK13_WIDTH 1
#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
#define LPUART_STAT_RWUID_MASK 0x8000000u
#define LPUART_STAT_RWUID_SHIFT 27
#define LPUART_STAT_RWUID_WIDTH 1
#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
#define LPUART_STAT_RXINV_MASK 0x10000000u
#define LPUART_STAT_RXINV_SHIFT 28
#define LPUART_STAT_RXINV_WIDTH 1
#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
#define LPUART_STAT_MSBF_MASK 0x20000000u
#define LPUART_STAT_MSBF_SHIFT 29
#define LPUART_STAT_MSBF_WIDTH 1
#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
#define LPUART_STAT_RXEDGIF_SHIFT 30
#define LPUART_STAT_RXEDGIF_WIDTH 1
#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
#define LPUART_STAT_LBKDIF_MASK 0x80000000u
#define LPUART_STAT_LBKDIF_SHIFT 31
#define LPUART_STAT_LBKDIF_WIDTH 1
#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
/* CTRL Bit Fields */
#define LPUART_CTRL_PT_MASK 0x1u
#define LPUART_CTRL_PT_SHIFT 0
#define LPUART_CTRL_PT_WIDTH 1
#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
#define LPUART_CTRL_PE_MASK 0x2u
#define LPUART_CTRL_PE_SHIFT 1
#define LPUART_CTRL_PE_WIDTH 1
#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
#define LPUART_CTRL_ILT_MASK 0x4u
#define LPUART_CTRL_ILT_SHIFT 2
#define LPUART_CTRL_ILT_WIDTH 1
#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
#define LPUART_CTRL_WAKE_MASK 0x8u
#define LPUART_CTRL_WAKE_SHIFT 3
#define LPUART_CTRL_WAKE_WIDTH 1
#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
#define LPUART_CTRL_M_MASK 0x10u
#define LPUART_CTRL_M_SHIFT 4
#define LPUART_CTRL_M_WIDTH 1
#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
#define LPUART_CTRL_RSRC_MASK 0x20u
#define LPUART_CTRL_RSRC_SHIFT 5
#define LPUART_CTRL_RSRC_WIDTH 1
#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
#define LPUART_CTRL_DOZEEN_MASK 0x40u
#define LPUART_CTRL_DOZEEN_SHIFT 6
#define LPUART_CTRL_DOZEEN_WIDTH 1
#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
#define LPUART_CTRL_LOOPS_MASK 0x80u
#define LPUART_CTRL_LOOPS_SHIFT 7
#define LPUART_CTRL_LOOPS_WIDTH 1
#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
#define LPUART_CTRL_IDLECFG_MASK 0x700u
#define LPUART_CTRL_IDLECFG_SHIFT 8
#define LPUART_CTRL_IDLECFG_WIDTH 3
#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
#define LPUART_CTRL_MA2IE_MASK 0x4000u
#define LPUART_CTRL_MA2IE_SHIFT 14
#define LPUART_CTRL_MA2IE_WIDTH 1
#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
#define LPUART_CTRL_MA1IE_MASK 0x8000u
#define LPUART_CTRL_MA1IE_SHIFT 15
#define LPUART_CTRL_MA1IE_WIDTH 1
#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
#define LPUART_CTRL_SBK_MASK 0x10000u
#define LPUART_CTRL_SBK_SHIFT 16
#define LPUART_CTRL_SBK_WIDTH 1
#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
#define LPUART_CTRL_RWU_MASK 0x20000u
#define LPUART_CTRL_RWU_SHIFT 17
#define LPUART_CTRL_RWU_WIDTH 1
#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
#define LPUART_CTRL_RE_MASK 0x40000u
#define LPUART_CTRL_RE_SHIFT 18
#define LPUART_CTRL_RE_WIDTH 1
#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
#define LPUART_CTRL_TE_MASK 0x80000u
#define LPUART_CTRL_TE_SHIFT 19
#define LPUART_CTRL_TE_WIDTH 1
#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
#define LPUART_CTRL_ILIE_MASK 0x100000u
#define LPUART_CTRL_ILIE_SHIFT 20
#define LPUART_CTRL_ILIE_WIDTH 1
#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
#define LPUART_CTRL_RIE_MASK 0x200000u
#define LPUART_CTRL_RIE_SHIFT 21
#define LPUART_CTRL_RIE_WIDTH 1
#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
#define LPUART_CTRL_TCIE_MASK 0x400000u
#define LPUART_CTRL_TCIE_SHIFT 22
#define LPUART_CTRL_TCIE_WIDTH 1
#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
#define LPUART_CTRL_TIE_MASK 0x800000u
#define LPUART_CTRL_TIE_SHIFT 23
#define LPUART_CTRL_TIE_WIDTH 1
#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
#define LPUART_CTRL_PEIE_MASK 0x1000000u
#define LPUART_CTRL_PEIE_SHIFT 24
#define LPUART_CTRL_PEIE_WIDTH 1
#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
#define LPUART_CTRL_FEIE_MASK 0x2000000u
#define LPUART_CTRL_FEIE_SHIFT 25
#define LPUART_CTRL_FEIE_WIDTH 1
#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
#define LPUART_CTRL_NEIE_MASK 0x4000000u
#define LPUART_CTRL_NEIE_SHIFT 26
#define LPUART_CTRL_NEIE_WIDTH 1
#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
#define LPUART_CTRL_ORIE_MASK 0x8000000u
#define LPUART_CTRL_ORIE_SHIFT 27
#define LPUART_CTRL_ORIE_WIDTH 1
#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
#define LPUART_CTRL_TXINV_MASK 0x10000000u
#define LPUART_CTRL_TXINV_SHIFT 28
#define LPUART_CTRL_TXINV_WIDTH 1
#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
#define LPUART_CTRL_TXDIR_MASK 0x20000000u
#define LPUART_CTRL_TXDIR_SHIFT 29
#define LPUART_CTRL_TXDIR_WIDTH 1
#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
#define LPUART_CTRL_R9T8_MASK 0x40000000u
#define LPUART_CTRL_R9T8_SHIFT 30
#define LPUART_CTRL_R9T8_WIDTH 1
#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
#define LPUART_CTRL_R8T9_MASK 0x80000000u
#define LPUART_CTRL_R8T9_SHIFT 31
#define LPUART_CTRL_R8T9_WIDTH 1
#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
/* DATA Bit Fields */
#define LPUART_DATA_R0T0_MASK 0x1u
#define LPUART_DATA_R0T0_SHIFT 0
#define LPUART_DATA_R0T0_WIDTH 1
#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
#define LPUART_DATA_R1T1_MASK 0x2u
#define LPUART_DATA_R1T1_SHIFT 1
#define LPUART_DATA_R1T1_WIDTH 1
#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
#define LPUART_DATA_R2T2_MASK 0x4u
#define LPUART_DATA_R2T2_SHIFT 2
#define LPUART_DATA_R2T2_WIDTH 1
#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
#define LPUART_DATA_R3T3_MASK 0x8u
#define LPUART_DATA_R3T3_SHIFT 3
#define LPUART_DATA_R3T3_WIDTH 1
#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
#define LPUART_DATA_R4T4_MASK 0x10u
#define LPUART_DATA_R4T4_SHIFT 4
#define LPUART_DATA_R4T4_WIDTH 1
#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
#define LPUART_DATA_R5T5_MASK 0x20u
#define LPUART_DATA_R5T5_SHIFT 5
#define LPUART_DATA_R5T5_WIDTH 1
#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
#define LPUART_DATA_R6T6_MASK 0x40u
#define LPUART_DATA_R6T6_SHIFT 6
#define LPUART_DATA_R6T6_WIDTH 1
#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
#define LPUART_DATA_R7T7_MASK 0x80u
#define LPUART_DATA_R7T7_SHIFT 7
#define LPUART_DATA_R7T7_WIDTH 1
#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
#define LPUART_DATA_R8T8_MASK 0x100u
#define LPUART_DATA_R8T8_SHIFT 8
#define LPUART_DATA_R8T8_WIDTH 1
#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
#define LPUART_DATA_R9T9_MASK 0x200u
#define LPUART_DATA_R9T9_SHIFT 9
#define LPUART_DATA_R9T9_WIDTH 1
#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
#define LPUART_DATA_IDLINE_MASK 0x800u
#define LPUART_DATA_IDLINE_SHIFT 11
#define LPUART_DATA_IDLINE_WIDTH 1
#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
#define LPUART_DATA_RXEMPT_MASK 0x1000u
#define LPUART_DATA_RXEMPT_SHIFT 12
#define LPUART_DATA_RXEMPT_WIDTH 1
#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
#define LPUART_DATA_FRETSC_MASK 0x2000u
#define LPUART_DATA_FRETSC_SHIFT 13
#define LPUART_DATA_FRETSC_WIDTH 1
#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
#define LPUART_DATA_PARITYE_MASK 0x4000u
#define LPUART_DATA_PARITYE_SHIFT 14
#define LPUART_DATA_PARITYE_WIDTH 1
#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
#define LPUART_DATA_NOISY_MASK 0x8000u
#define LPUART_DATA_NOISY_SHIFT 15
#define LPUART_DATA_NOISY_WIDTH 1
#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
/* MATCH Bit Fields */
#define LPUART_MATCH_MA1_MASK 0x3FFu
#define LPUART_MATCH_MA1_SHIFT 0
#define LPUART_MATCH_MA1_WIDTH 10
#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
#define LPUART_MATCH_MA2_MASK 0x3FF0000u
#define LPUART_MATCH_MA2_SHIFT 16
#define LPUART_MATCH_MA2_WIDTH 10
#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
/* MODIR Bit Fields */
#define LPUART_MODIR_TXCTSE_MASK 0x1u
#define LPUART_MODIR_TXCTSE_SHIFT 0
#define LPUART_MODIR_TXCTSE_WIDTH 1
#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
#define LPUART_MODIR_TXRTSE_MASK 0x2u
#define LPUART_MODIR_TXRTSE_SHIFT 1
#define LPUART_MODIR_TXRTSE_WIDTH 1
#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
#define LPUART_MODIR_TXRTSPOL_MASK 0x4u
#define LPUART_MODIR_TXRTSPOL_SHIFT 2
#define LPUART_MODIR_TXRTSPOL_WIDTH 1
#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
#define LPUART_MODIR_RXRTSE_MASK 0x8u
#define LPUART_MODIR_RXRTSE_SHIFT 3
#define LPUART_MODIR_RXRTSE_WIDTH 1
#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
#define LPUART_MODIR_TXCTSC_MASK 0x10u
#define LPUART_MODIR_TXCTSC_SHIFT 4
#define LPUART_MODIR_TXCTSC_WIDTH 1
#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
#define LPUART_MODIR_TXCTSSRC_MASK 0x20u
#define LPUART_MODIR_TXCTSSRC_SHIFT 5
#define LPUART_MODIR_TXCTSSRC_WIDTH 1
#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
#define LPUART_MODIR_TNP_MASK 0x30000u
#define LPUART_MODIR_TNP_SHIFT 16
#define LPUART_MODIR_TNP_WIDTH 2
#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
#define LPUART_MODIR_IREN_MASK 0x40000u
#define LPUART_MODIR_IREN_SHIFT 18
#define LPUART_MODIR_IREN_WIDTH 1
#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
/*!
* @}
*/ /* end of group LPUART_Register_Masks */
/* LPUART - Peripheral instance base addresses */
/** Peripheral LPUART0 base address */
#define LPUART0_BASE (0x4002A000u)
/** Peripheral LPUART0 base pointer */
#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
#define LPUART0_BASE_PTR (LPUART0)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { LPUART0_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS { LPUART0 }
/* ----------------------------------------------------------------------------
-- LPUART - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
* @{
*/
/* LPUART - Register instance definitions */
/* LPUART0 */
#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
#define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
/*!
* @}
*/ /* end of group LPUART_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group LPUART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
* @{
*/
/** MCG - Register Layout Typedef */
typedef struct {
__IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
__IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
__IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
__IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
__IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
__IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
__IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
uint8_t RESERVED_0[1];
__IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
uint8_t RESERVED_1[1];
__IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
__IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
__IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
__IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
uint8_t RESERVED_2[3];
__I uint8_t C12; /**< MCG Control 12 Register, offset: 0x11 */
__I uint8_t S2; /**< MCG Status 2 Register, offset: 0x12 */
__I uint8_t T3; /**< MCG Test 3 Register, offset: 0x13 */
} MCG_Type, *MCG_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MCG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
* @{
*/
/* MCG - Register accessors */
#define MCG_C1_REG(base) ((base)->C1)
#define MCG_C2_REG(base) ((base)->C2)
#define MCG_C3_REG(base) ((base)->C3)
#define MCG_C4_REG(base) ((base)->C4)
#define MCG_C5_REG(base) ((base)->C5)
#define MCG_C6_REG(base) ((base)->C6)
#define MCG_S_REG(base) ((base)->S)
#define MCG_SC_REG(base) ((base)->SC)
#define MCG_ATCVH_REG(base) ((base)->ATCVH)
#define MCG_ATCVL_REG(base) ((base)->ATCVL)
#define MCG_C7_REG(base) ((base)->C7)
#define MCG_C8_REG(base) ((base)->C8)
#define MCG_C12_REG(base) ((base)->C12)
#define MCG_S2_REG(base) ((base)->S2)
#define MCG_T3_REG(base) ((base)->T3)
/*!
* @}
*/ /* end of group MCG_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MCG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCG_Register_Masks MCG Register Masks
* @{
*/
/* C1 Bit Fields */
#define MCG_C1_IREFSTEN_MASK 0x1u
#define MCG_C1_IREFSTEN_SHIFT 0
#define MCG_C1_IREFSTEN_WIDTH 1
#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
#define MCG_C1_IRCLKEN_MASK 0x2u
#define MCG_C1_IRCLKEN_SHIFT 1
#define MCG_C1_IRCLKEN_WIDTH 1
#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
#define MCG_C1_IREFS_MASK 0x4u
#define MCG_C1_IREFS_SHIFT 2
#define MCG_C1_IREFS_WIDTH 1
#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
#define MCG_C1_FRDIV_MASK 0x38u
#define MCG_C1_FRDIV_SHIFT 3
#define MCG_C1_FRDIV_WIDTH 3
#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
#define MCG_C1_CLKS_MASK 0xC0u
#define MCG_C1_CLKS_SHIFT 6
#define MCG_C1_CLKS_WIDTH 2
#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
/* C2 Bit Fields */
#define MCG_C2_IRCS_MASK 0x1u
#define MCG_C2_IRCS_SHIFT 0
#define MCG_C2_IRCS_WIDTH 1
#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
#define MCG_C2_LP_MASK 0x2u
#define MCG_C2_LP_SHIFT 1
#define MCG_C2_LP_WIDTH 1
#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
#define MCG_C2_EREFS_MASK 0x4u
#define MCG_C2_EREFS_SHIFT 2
#define MCG_C2_EREFS_WIDTH 1
#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
#define MCG_C2_HGO_MASK 0x8u
#define MCG_C2_HGO_SHIFT 3
#define MCG_C2_HGO_WIDTH 1
#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
#define MCG_C2_RANGE_MASK 0x30u
#define MCG_C2_RANGE_SHIFT 4
#define MCG_C2_RANGE_WIDTH 2
#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
#define MCG_C2_FCFTRIM_MASK 0x40u
#define MCG_C2_FCFTRIM_SHIFT 6
#define MCG_C2_FCFTRIM_WIDTH 1
#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
#define MCG_C2_LOCRE0_MASK 0x80u
#define MCG_C2_LOCRE0_SHIFT 7
#define MCG_C2_LOCRE0_WIDTH 1
#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
/* C3 Bit Fields */
#define MCG_C3_SCTRIM_MASK 0xFFu
#define MCG_C3_SCTRIM_SHIFT 0
#define MCG_C3_SCTRIM_WIDTH 8
#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
/* C4 Bit Fields */
#define MCG_C4_SCFTRIM_MASK 0x1u
#define MCG_C4_SCFTRIM_SHIFT 0
#define MCG_C4_SCFTRIM_WIDTH 1
#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
#define MCG_C4_FCTRIM_MASK 0x1Eu
#define MCG_C4_FCTRIM_SHIFT 1
#define MCG_C4_FCTRIM_WIDTH 4
#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
#define MCG_C4_DRST_DRS_MASK 0x60u
#define MCG_C4_DRST_DRS_SHIFT 5
#define MCG_C4_DRST_DRS_WIDTH 2
#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
#define MCG_C4_DMX32_MASK 0x80u
#define MCG_C4_DMX32_SHIFT 7
#define MCG_C4_DMX32_WIDTH 1
#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
/* C5 Bit Fields */
#define MCG_C5_PRDIV0_MASK 0x1Fu
#define MCG_C5_PRDIV0_SHIFT 0
#define MCG_C5_PRDIV0_WIDTH 5
#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
#define MCG_C5_PLLSTEN0_MASK 0x20u
#define MCG_C5_PLLSTEN0_SHIFT 5
#define MCG_C5_PLLSTEN0_WIDTH 1
#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
#define MCG_C5_PLLCLKEN0_MASK 0x40u
#define MCG_C5_PLLCLKEN0_SHIFT 6
#define MCG_C5_PLLCLKEN0_WIDTH 1
#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
/* C6 Bit Fields */
#define MCG_C6_VDIV0_MASK 0x1Fu
#define MCG_C6_VDIV0_SHIFT 0
#define MCG_C6_VDIV0_WIDTH 5
#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
#define MCG_C6_CME0_MASK 0x20u
#define MCG_C6_CME0_SHIFT 5
#define MCG_C6_CME0_WIDTH 1
#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
#define MCG_C6_PLLS_MASK 0x40u
#define MCG_C6_PLLS_SHIFT 6
#define MCG_C6_PLLS_WIDTH 1
#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
#define MCG_C6_LOLIE0_MASK 0x80u
#define MCG_C6_LOLIE0_SHIFT 7
#define MCG_C6_LOLIE0_WIDTH 1
#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
/* S Bit Fields */
#define MCG_S_IRCST_MASK 0x1u
#define MCG_S_IRCST_SHIFT 0
#define MCG_S_IRCST_WIDTH 1
#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
#define MCG_S_OSCINIT0_MASK 0x2u
#define MCG_S_OSCINIT0_SHIFT 1
#define MCG_S_OSCINIT0_WIDTH 1
#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
#define MCG_S_CLKST_MASK 0xCu
#define MCG_S_CLKST_SHIFT 2
#define MCG_S_CLKST_WIDTH 2
#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
#define MCG_S_IREFST_MASK 0x10u
#define MCG_S_IREFST_SHIFT 4
#define MCG_S_IREFST_WIDTH 1
#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
#define MCG_S_PLLST_MASK 0x20u
#define MCG_S_PLLST_SHIFT 5
#define MCG_S_PLLST_WIDTH 1
#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
#define MCG_S_LOCK0_MASK 0x40u
#define MCG_S_LOCK0_SHIFT 6
#define MCG_S_LOCK0_WIDTH 1
#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
#define MCG_S_LOLS0_MASK 0x80u
#define MCG_S_LOLS0_SHIFT 7
#define MCG_S_LOLS0_WIDTH 1
#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
/* SC Bit Fields */
#define MCG_SC_LOCS0_MASK 0x1u
#define MCG_SC_LOCS0_SHIFT 0
#define MCG_SC_LOCS0_WIDTH 1
#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
#define MCG_SC_FCRDIV_MASK 0xEu
#define MCG_SC_FCRDIV_SHIFT 1
#define MCG_SC_FCRDIV_WIDTH 3
#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
#define MCG_SC_FLTPRSRV_MASK 0x10u
#define MCG_SC_FLTPRSRV_SHIFT 4
#define MCG_SC_FLTPRSRV_WIDTH 1
#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
#define MCG_SC_ATMF_MASK 0x20u
#define MCG_SC_ATMF_SHIFT 5
#define MCG_SC_ATMF_WIDTH 1
#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
#define MCG_SC_ATMS_MASK 0x40u
#define MCG_SC_ATMS_SHIFT 6
#define MCG_SC_ATMS_WIDTH 1
#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
#define MCG_SC_ATME_MASK 0x80u
#define MCG_SC_ATME_SHIFT 7
#define MCG_SC_ATME_WIDTH 1
#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
/* ATCVH Bit Fields */
#define MCG_ATCVH_ATCVH_MASK 0xFFu
#define MCG_ATCVH_ATCVH_SHIFT 0
#define MCG_ATCVH_ATCVH_WIDTH 8
#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
/* ATCVL Bit Fields */
#define MCG_ATCVL_ATCVL_MASK 0xFFu
#define MCG_ATCVL_ATCVL_SHIFT 0
#define MCG_ATCVL_ATCVL_WIDTH 8
#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
/* C7 Bit Fields */
#define MCG_C7_OSCSEL_MASK 0x3u
#define MCG_C7_OSCSEL_SHIFT 0
#define MCG_C7_OSCSEL_WIDTH 2
#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
/* C8 Bit Fields */
#define MCG_C8_LOCS1_MASK 0x1u
#define MCG_C8_LOCS1_SHIFT 0
#define MCG_C8_LOCS1_WIDTH 1
#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
#define MCG_C8_CME1_MASK 0x20u
#define MCG_C8_CME1_SHIFT 5
#define MCG_C8_CME1_WIDTH 1
#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
#define MCG_C8_LOLRE_MASK 0x40u
#define MCG_C8_LOLRE_SHIFT 6
#define MCG_C8_LOLRE_WIDTH 1
#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
#define MCG_C8_LOCRE1_MASK 0x80u
#define MCG_C8_LOCRE1_SHIFT 7
#define MCG_C8_LOCRE1_WIDTH 1
#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
/*!
* @}
*/ /* end of group MCG_Register_Masks */
/* MCG - Peripheral instance base addresses */
/** Peripheral MCG base address */
#define MCG_BASE (0x40064000u)
/** Peripheral MCG base pointer */
#define MCG ((MCG_Type *)MCG_BASE)
#define MCG_BASE_PTR (MCG)
/** Array initializer of MCG peripheral base addresses */
#define MCG_BASE_ADDRS { MCG_BASE }
/** Array initializer of MCG peripheral base pointers */
#define MCG_BASE_PTRS { MCG }
/* ----------------------------------------------------------------------------
-- MCG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
* @{
*/
/* MCG - Register instance definitions */
/* MCG */
#define MCG_C1 MCG_C1_REG(MCG)
#define MCG_C2 MCG_C2_REG(MCG)
#define MCG_C3 MCG_C3_REG(MCG)
#define MCG_C4 MCG_C4_REG(MCG)
#define MCG_C5 MCG_C5_REG(MCG)
#define MCG_C6 MCG_C6_REG(MCG)
#define MCG_S MCG_S_REG(MCG)
#define MCG_SC MCG_SC_REG(MCG)
#define MCG_ATCVH MCG_ATCVH_REG(MCG)
#define MCG_ATCVL MCG_ATCVL_REG(MCG)
#define MCG_C7 MCG_C7_REG(MCG)
#define MCG_C8 MCG_C8_REG(MCG)
#define MCG_C12 MCG_C12_REG(MCG)
#define MCG_S2 MCG_S2_REG(MCG)
#define MCG_T3 MCG_T3_REG(MCG)
/*!
* @}
*/ /* end of group MCG_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group MCG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
* @{
*/
/** MCM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
__I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
__IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
__IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
uint8_t RESERVED_1[44];
__IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
} MCM_Type, *MCM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
* @{
*/
/* MCM - Register accessors */
#define MCM_PLASC_REG(base) ((base)->PLASC)
#define MCM_PLAMC_REG(base) ((base)->PLAMC)
#define MCM_PLACR_REG(base) ((base)->PLACR)
#define MCM_ISCR_REG(base) ((base)->ISCR)
#define MCM_CPO_REG(base) ((base)->CPO)
/*!
* @}
*/ /* end of group MCM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Masks MCM Register Masks
* @{
*/
/* PLASC Bit Fields */
#define MCM_PLASC_ASC_MASK 0xFFu
#define MCM_PLASC_ASC_SHIFT 0
#define MCM_PLASC_ASC_WIDTH 8
#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
/* PLAMC Bit Fields */
#define MCM_PLAMC_AMC_MASK 0xFFu
#define MCM_PLAMC_AMC_SHIFT 0
#define MCM_PLAMC_AMC_WIDTH 8
#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
/* PLACR Bit Fields */
#define MCM_PLACR_ARB_MASK 0x200u
#define MCM_PLACR_ARB_SHIFT 9
#define MCM_PLACR_ARB_WIDTH 1
#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ARB_SHIFT))&MCM_PLACR_ARB_MASK)
/* ISCR Bit Fields */
#define MCM_ISCR_FIOC_MASK 0x100u
#define MCM_ISCR_FIOC_SHIFT 8
#define MCM_ISCR_FIOC_WIDTH 1
#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
#define MCM_ISCR_FDZC_MASK 0x200u
#define MCM_ISCR_FDZC_SHIFT 9
#define MCM_ISCR_FDZC_WIDTH 1
#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
#define MCM_ISCR_FOFC_MASK 0x400u
#define MCM_ISCR_FOFC_SHIFT 10
#define MCM_ISCR_FOFC_WIDTH 1
#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
#define MCM_ISCR_FUFC_MASK 0x800u
#define MCM_ISCR_FUFC_SHIFT 11
#define MCM_ISCR_FUFC_WIDTH 1
#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
#define MCM_ISCR_FIXC_MASK 0x1000u
#define MCM_ISCR_FIXC_SHIFT 12
#define MCM_ISCR_FIXC_WIDTH 1
#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
#define MCM_ISCR_FIDC_MASK 0x8000u
#define MCM_ISCR_FIDC_SHIFT 15
#define MCM_ISCR_FIDC_WIDTH 1
#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
#define MCM_ISCR_FIOCE_MASK 0x1000000u
#define MCM_ISCR_FIOCE_SHIFT 24
#define MCM_ISCR_FIOCE_WIDTH 1
#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
#define MCM_ISCR_FDZCE_MASK 0x2000000u
#define MCM_ISCR_FDZCE_SHIFT 25
#define MCM_ISCR_FDZCE_WIDTH 1
#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
#define MCM_ISCR_FOFCE_MASK 0x4000000u
#define MCM_ISCR_FOFCE_SHIFT 26
#define MCM_ISCR_FOFCE_WIDTH 1
#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
#define MCM_ISCR_FUFCE_MASK 0x8000000u
#define MCM_ISCR_FUFCE_SHIFT 27
#define MCM_ISCR_FUFCE_WIDTH 1
#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
#define MCM_ISCR_FIXCE_MASK 0x10000000u
#define MCM_ISCR_FIXCE_SHIFT 28
#define MCM_ISCR_FIXCE_WIDTH 1
#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
#define MCM_ISCR_FIDCE_MASK 0x80000000u
#define MCM_ISCR_FIDCE_SHIFT 31
#define MCM_ISCR_FIDCE_WIDTH 1
#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
/* CPO Bit Fields */
#define MCM_CPO_CPOREQ_MASK 0x1u
#define MCM_CPO_CPOREQ_SHIFT 0
#define MCM_CPO_CPOREQ_WIDTH 1
#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
#define MCM_CPO_CPOACK_MASK 0x2u
#define MCM_CPO_CPOACK_SHIFT 1
#define MCM_CPO_CPOACK_WIDTH 1
#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
#define MCM_CPO_CPOWOI_MASK 0x4u
#define MCM_CPO_CPOWOI_SHIFT 2
#define MCM_CPO_CPOWOI_WIDTH 1
#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
/*!
* @}
*/ /* end of group MCM_Register_Masks */
/* MCM - Peripheral instance base addresses */
/** Peripheral MCM base address */
#define MCM_BASE (0xE0080000u)
/** Peripheral MCM base pointer */
#define MCM ((MCM_Type *)MCM_BASE)
#define MCM_BASE_PTR (MCM)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS { MCM_BASE }
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASE_PTRS { MCM }
/* ----------------------------------------------------------------------------
-- MCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
* @{
*/
/* MCM - Register instance definitions */
/* MCM */
#define MCM_PLASC MCM_PLASC_REG(MCM)
#define MCM_PLAMC MCM_PLAMC_REG(MCM)
#define MCM_PLACR MCM_PLACR_REG(MCM)
#define MCM_ISCR MCM_ISCR_REG(MCM)
#define MCM_CPO MCM_CPO_REG(MCM)
/*!
* @}
*/ /* end of group MCM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- NV Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
* @{
*/
/** NV - Register Layout Typedef */
typedef struct {
__I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
__I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
__I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
__I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
__I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
__I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
__I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
__I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
__I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
__I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
__I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
__I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
__I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
} NV_Type, *NV_MemMapPtr;
/* ----------------------------------------------------------------------------
-- NV - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
* @{
*/
/* NV - Register accessors */
#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
#define NV_FPROT3_REG(base) ((base)->FPROT3)
#define NV_FPROT2_REG(base) ((base)->FPROT2)
#define NV_FPROT1_REG(base) ((base)->FPROT1)
#define NV_FPROT0_REG(base) ((base)->FPROT0)
#define NV_FSEC_REG(base) ((base)->FSEC)
#define NV_FOPT_REG(base) ((base)->FOPT)
/*!
* @}
*/ /* end of group NV_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- NV Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Masks NV Register Masks
* @{
*/
/* BACKKEY3 Bit Fields */
#define NV_BACKKEY3_KEY_MASK 0xFFu
#define NV_BACKKEY3_KEY_SHIFT 0
#define NV_BACKKEY3_KEY_WIDTH 8
#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
/* BACKKEY2 Bit Fields */
#define NV_BACKKEY2_KEY_MASK 0xFFu
#define NV_BACKKEY2_KEY_SHIFT 0
#define NV_BACKKEY2_KEY_WIDTH 8
#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
/* BACKKEY1 Bit Fields */
#define NV_BACKKEY1_KEY_MASK 0xFFu
#define NV_BACKKEY1_KEY_SHIFT 0
#define NV_BACKKEY1_KEY_WIDTH 8
#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
/* BACKKEY0 Bit Fields */
#define NV_BACKKEY0_KEY_MASK 0xFFu
#define NV_BACKKEY0_KEY_SHIFT 0
#define NV_BACKKEY0_KEY_WIDTH 8
#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
/* BACKKEY7 Bit Fields */
#define NV_BACKKEY7_KEY_MASK 0xFFu
#define NV_BACKKEY7_KEY_SHIFT 0
#define NV_BACKKEY7_KEY_WIDTH 8
#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
/* BACKKEY6 Bit Fields */
#define NV_BACKKEY6_KEY_MASK 0xFFu
#define NV_BACKKEY6_KEY_SHIFT 0
#define NV_BACKKEY6_KEY_WIDTH 8
#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
/* BACKKEY5 Bit Fields */
#define NV_BACKKEY5_KEY_MASK 0xFFu
#define NV_BACKKEY5_KEY_SHIFT 0
#define NV_BACKKEY5_KEY_WIDTH 8
#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
/* BACKKEY4 Bit Fields */
#define NV_BACKKEY4_KEY_MASK 0xFFu
#define NV_BACKKEY4_KEY_SHIFT 0
#define NV_BACKKEY4_KEY_WIDTH 8
#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
/* FPROT3 Bit Fields */
#define NV_FPROT3_PROT_MASK 0xFFu
#define NV_FPROT3_PROT_SHIFT 0
#define NV_FPROT3_PROT_WIDTH 8
#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
/* FPROT2 Bit Fields */
#define NV_FPROT2_PROT_MASK 0xFFu
#define NV_FPROT2_PROT_SHIFT 0
#define NV_FPROT2_PROT_WIDTH 8
#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
/* FPROT1 Bit Fields */
#define NV_FPROT1_PROT_MASK 0xFFu
#define NV_FPROT1_PROT_SHIFT 0
#define NV_FPROT1_PROT_WIDTH 8
#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
/* FPROT0 Bit Fields */
#define NV_FPROT0_PROT_MASK 0xFFu
#define NV_FPROT0_PROT_SHIFT 0
#define NV_FPROT0_PROT_WIDTH 8
#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
/* FSEC Bit Fields */
#define NV_FSEC_SEC_MASK 0x3u
#define NV_FSEC_SEC_SHIFT 0
#define NV_FSEC_SEC_WIDTH 2
#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
#define NV_FSEC_FSLACC_MASK 0xCu
#define NV_FSEC_FSLACC_SHIFT 2
#define NV_FSEC_FSLACC_WIDTH 2
#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
#define NV_FSEC_MEEN_MASK 0x30u
#define NV_FSEC_MEEN_SHIFT 4
#define NV_FSEC_MEEN_WIDTH 2
#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
#define NV_FSEC_KEYEN_MASK 0xC0u
#define NV_FSEC_KEYEN_SHIFT 6
#define NV_FSEC_KEYEN_WIDTH 2
#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
/* FOPT Bit Fields */
#define NV_FOPT_LPBOOT_MASK 0x1u
#define NV_FOPT_LPBOOT_SHIFT 0
#define NV_FOPT_LPBOOT_WIDTH 1
#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
#define NV_FOPT_EZPORT_DIS_MASK 0x2u
#define NV_FOPT_EZPORT_DIS_SHIFT 1
#define NV_FOPT_EZPORT_DIS_WIDTH 1
#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
#define NV_FOPT_NMI_DIS_MASK 0x4u
#define NV_FOPT_NMI_DIS_SHIFT 2
#define NV_FOPT_NMI_DIS_WIDTH 1
#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_NMI_DIS_SHIFT))&NV_FOPT_NMI_DIS_MASK)
#define NV_FOPT_FAST_INIT_MASK 0x20u
#define NV_FOPT_FAST_INIT_SHIFT 5
#define NV_FOPT_FAST_INIT_WIDTH 1
#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_FAST_INIT_SHIFT))&NV_FOPT_FAST_INIT_MASK)
/*!
* @}
*/ /* end of group NV_Register_Masks */
/* NV - Peripheral instance base addresses */
/** Peripheral FTFA_FlashConfig base address */
#define FTFA_FlashConfig_BASE (0x400u)
/** Peripheral FTFA_FlashConfig base pointer */
#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
/** Array initializer of NV peripheral base addresses */
#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
/** Array initializer of NV peripheral base pointers */
#define NV_BASE_PTRS { FTFA_FlashConfig }
/* ----------------------------------------------------------------------------
-- NV - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
* @{
*/
/* NV - Register instance definitions */
/* FTFA_FlashConfig */
#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
/*!
* @}
*/ /* end of group NV_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- OSC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
* @{
*/
/** OSC - Register Layout Typedef */
typedef struct {
__IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
uint8_t RESERVED_0[1];
__IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
} OSC_Type, *OSC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- OSC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
* @{
*/
/* OSC - Register accessors */
#define OSC_CR_REG(base) ((base)->CR)
#define OSC_DIV_REG(base) ((base)->DIV)
/*!
* @}
*/ /* end of group OSC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- OSC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_Register_Masks OSC Register Masks
* @{
*/
/* CR Bit Fields */
#define OSC_CR_SC16P_MASK 0x1u
#define OSC_CR_SC16P_SHIFT 0
#define OSC_CR_SC16P_WIDTH 1
#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
#define OSC_CR_SC8P_MASK 0x2u
#define OSC_CR_SC8P_SHIFT 1
#define OSC_CR_SC8P_WIDTH 1
#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
#define OSC_CR_SC4P_MASK 0x4u
#define OSC_CR_SC4P_SHIFT 2
#define OSC_CR_SC4P_WIDTH 1
#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
#define OSC_CR_SC2P_MASK 0x8u
#define OSC_CR_SC2P_SHIFT 3
#define OSC_CR_SC2P_WIDTH 1
#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
#define OSC_CR_EREFSTEN_MASK 0x20u
#define OSC_CR_EREFSTEN_SHIFT 5
#define OSC_CR_EREFSTEN_WIDTH 1
#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
#define OSC_CR_ERCLKEN_MASK 0x80u
#define OSC_CR_ERCLKEN_SHIFT 7
#define OSC_CR_ERCLKEN_WIDTH 1
#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
/* DIV Bit Fields */
#define OSC_DIV_ERPS_MASK 0xC0u
#define OSC_DIV_ERPS_SHIFT 6
#define OSC_DIV_ERPS_WIDTH 2
#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
/*!
* @}
*/ /* end of group OSC_Register_Masks */
/* OSC - Peripheral instance base addresses */
/** Peripheral OSC base address */
#define OSC_BASE (0x40065000u)
/** Peripheral OSC base pointer */
#define OSC ((OSC_Type *)OSC_BASE)
#define OSC_BASE_PTR (OSC)
/** Array initializer of OSC peripheral base addresses */
#define OSC_BASE_ADDRS { OSC_BASE }
/** Array initializer of OSC peripheral base pointers */
#define OSC_BASE_PTRS { OSC }
/* ----------------------------------------------------------------------------
-- OSC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
* @{
*/
/* OSC - Register instance definitions */
/* OSC */
#define OSC_CR OSC_CR_REG(OSC)
#define OSC_DIV OSC_DIV_REG(OSC)
/*!
* @}
*/ /* end of group OSC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group OSC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PDB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
* @{
*/
/** PDB - Register Layout Typedef */
typedef struct {
__IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
__IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
__I uint32_t CNT; /**< Counter register, offset: 0x8 */
__IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
struct { /* offset: 0x10, array step: 0x10 */
__IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x10 */
__IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x10 */
__IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x10, index2*0x4 */
} CH[1];
uint8_t RESERVED_0[304];
struct { /* offset: 0x150, array step: 0x8 */
__IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
__IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
} DAC[1];
uint8_t RESERVED_1[56];
__IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
__IO uint32_t PODLY[1]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
} PDB_Type, *PDB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PDB - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
* @{
*/
/* PDB - Register accessors */
#define PDB_SC_REG(base) ((base)->SC)
#define PDB_MOD_REG(base) ((base)->MOD)
#define PDB_CNT_REG(base) ((base)->CNT)
#define PDB_IDLY_REG(base) ((base)->IDLY)
#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
#define PDB_C1_COUNT 1
#define PDB_S_REG(base,index) ((base)->CH[index].S)
#define PDB_S_COUNT 1
#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
#define PDB_DLY_COUNT 1
#define PDB_DLY_COUNT2 2
#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
#define PDB_INTC_COUNT 1
#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
#define PDB_INT_COUNT 1
#define PDB_POEN_REG(base) ((base)->POEN)
#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
#define PDB_PODLY_COUNT 1
/*!
* @}
*/ /* end of group PDB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PDB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDB_Register_Masks PDB Register Masks
* @{
*/
/* SC Bit Fields */
#define PDB_SC_LDOK_MASK 0x1u
#define PDB_SC_LDOK_SHIFT 0
#define PDB_SC_LDOK_WIDTH 1
#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
#define PDB_SC_CONT_MASK 0x2u
#define PDB_SC_CONT_SHIFT 1
#define PDB_SC_CONT_WIDTH 1
#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
#define PDB_SC_MULT_MASK 0xCu
#define PDB_SC_MULT_SHIFT 2
#define PDB_SC_MULT_WIDTH 2
#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
#define PDB_SC_PDBIE_MASK 0x20u
#define PDB_SC_PDBIE_SHIFT 5
#define PDB_SC_PDBIE_WIDTH 1
#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
#define PDB_SC_PDBIF_MASK 0x40u
#define PDB_SC_PDBIF_SHIFT 6
#define PDB_SC_PDBIF_WIDTH 1
#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
#define PDB_SC_PDBEN_MASK 0x80u
#define PDB_SC_PDBEN_SHIFT 7
#define PDB_SC_PDBEN_WIDTH 1
#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
#define PDB_SC_TRGSEL_MASK 0xF00u
#define PDB_SC_TRGSEL_SHIFT 8
#define PDB_SC_TRGSEL_WIDTH 4
#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
#define PDB_SC_PRESCALER_MASK 0x7000u
#define PDB_SC_PRESCALER_SHIFT 12
#define PDB_SC_PRESCALER_WIDTH 3
#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
#define PDB_SC_DMAEN_MASK 0x8000u
#define PDB_SC_DMAEN_SHIFT 15
#define PDB_SC_DMAEN_WIDTH 1
#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
#define PDB_SC_SWTRIG_MASK 0x10000u
#define PDB_SC_SWTRIG_SHIFT 16
#define PDB_SC_SWTRIG_WIDTH 1
#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
#define PDB_SC_PDBEIE_MASK 0x20000u
#define PDB_SC_PDBEIE_SHIFT 17
#define PDB_SC_PDBEIE_WIDTH 1
#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
#define PDB_SC_LDMOD_MASK 0xC0000u
#define PDB_SC_LDMOD_SHIFT 18
#define PDB_SC_LDMOD_WIDTH 2
#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
/* MOD Bit Fields */
#define PDB_MOD_MOD_MASK 0xFFFFu
#define PDB_MOD_MOD_SHIFT 0
#define PDB_MOD_MOD_WIDTH 16
#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
/* CNT Bit Fields */
#define PDB_CNT_CNT_MASK 0xFFFFu
#define PDB_CNT_CNT_SHIFT 0
#define PDB_CNT_CNT_WIDTH 16
#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
/* IDLY Bit Fields */
#define PDB_IDLY_IDLY_MASK 0xFFFFu
#define PDB_IDLY_IDLY_SHIFT 0
#define PDB_IDLY_IDLY_WIDTH 16
#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
/* C1 Bit Fields */
#define PDB_C1_EN_MASK 0xFFu
#define PDB_C1_EN_SHIFT 0
#define PDB_C1_EN_WIDTH 8
#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
#define PDB_C1_TOS_MASK 0xFF00u
#define PDB_C1_TOS_SHIFT 8
#define PDB_C1_TOS_WIDTH 8
#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
#define PDB_C1_BB_MASK 0xFF0000u
#define PDB_C1_BB_SHIFT 16
#define PDB_C1_BB_WIDTH 8
#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
/* S Bit Fields */
#define PDB_S_ERR_MASK 0xFFu
#define PDB_S_ERR_SHIFT 0
#define PDB_S_ERR_WIDTH 8
#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
#define PDB_S_CF_MASK 0xFF0000u
#define PDB_S_CF_SHIFT 16
#define PDB_S_CF_WIDTH 8
#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
/* DLY Bit Fields */
#define PDB_DLY_DLY_MASK 0xFFFFu
#define PDB_DLY_DLY_SHIFT 0
#define PDB_DLY_DLY_WIDTH 16
#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
/* INTC Bit Fields */
#define PDB_INTC_TOE_MASK 0x1u
#define PDB_INTC_TOE_SHIFT 0
#define PDB_INTC_TOE_WIDTH 1
#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
#define PDB_INTC_EXT_MASK 0x2u
#define PDB_INTC_EXT_SHIFT 1
#define PDB_INTC_EXT_WIDTH 1
#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
/* INT Bit Fields */
#define PDB_INT_INT_MASK 0xFFFFu
#define PDB_INT_INT_SHIFT 0
#define PDB_INT_INT_WIDTH 16
#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
/* POEN Bit Fields */
#define PDB_POEN_POEN_MASK 0xFFu
#define PDB_POEN_POEN_SHIFT 0
#define PDB_POEN_POEN_WIDTH 8
#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
/* PODLY Bit Fields */
#define PDB_PODLY_DLY2_MASK 0xFFFFu
#define PDB_PODLY_DLY2_SHIFT 0
#define PDB_PODLY_DLY2_WIDTH 16
#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
#define PDB_PODLY_DLY1_SHIFT 16
#define PDB_PODLY_DLY1_WIDTH 16
#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
/*!
* @}
*/ /* end of group PDB_Register_Masks */
/* PDB - Peripheral instance base addresses */
/** Peripheral PDB0 base address */
#define PDB0_BASE (0x40036000u)
/** Peripheral PDB0 base pointer */
#define PDB0 ((PDB_Type *)PDB0_BASE)
#define PDB0_BASE_PTR (PDB0)
/** Array initializer of PDB peripheral base addresses */
#define PDB_BASE_ADDRS { PDB0_BASE }
/** Array initializer of PDB peripheral base pointers */
#define PDB_BASE_PTRS { PDB0 }
/* ----------------------------------------------------------------------------
-- PDB - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
* @{
*/
/* PDB - Register instance definitions */
/* PDB0 */
#define PDB0_SC PDB_SC_REG(PDB0)
#define PDB0_MOD PDB_MOD_REG(PDB0)
#define PDB0_CNT PDB_CNT_REG(PDB0)
#define PDB0_IDLY PDB_IDLY_REG(PDB0)
#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
#define PDB0_CH0S PDB_S_REG(PDB0,0)
#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
#define PDB0_POEN PDB_POEN_REG(PDB0)
#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
/* PDB - Register array accessors */
#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
#define PDB0_S(index) PDB_S_REG(PDB0,index)
#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
/*!
* @}
*/ /* end of group PDB_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group PDB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PIT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
* @{
*/
/** PIT - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
uint8_t RESERVED_0[220];
__I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
__I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
uint8_t RESERVED_1[24];
struct { /* offset: 0x100, array step: 0x10 */
__IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
__I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
} CHANNEL[4];
} PIT_Type, *PIT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PIT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
* @{
*/
/* PIT - Register accessors */
#define PIT_MCR_REG(base) ((base)->MCR)
#define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
#define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
#define PIT_LDVAL_COUNT 4
#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
#define PIT_CVAL_COUNT 4
#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
#define PIT_TCTRL_COUNT 4
#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
#define PIT_TFLG_COUNT 4
/*!
* @}
*/ /* end of group PIT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PIT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PIT_Register_Masks PIT Register Masks
* @{
*/
/* MCR Bit Fields */
#define PIT_MCR_FRZ_MASK 0x1u
#define PIT_MCR_FRZ_SHIFT 0
#define PIT_MCR_FRZ_WIDTH 1
#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
#define PIT_MCR_MDIS_MASK 0x2u
#define PIT_MCR_MDIS_SHIFT 1
#define PIT_MCR_MDIS_WIDTH 1
#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
/* LTMR64H Bit Fields */
#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
#define PIT_LTMR64H_LTH_SHIFT 0
#define PIT_LTMR64H_LTH_WIDTH 32
#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
/* LTMR64L Bit Fields */
#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
#define PIT_LTMR64L_LTL_SHIFT 0
#define PIT_LTMR64L_LTL_WIDTH 32
#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
/* LDVAL Bit Fields */
#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
#define PIT_LDVAL_TSV_SHIFT 0
#define PIT_LDVAL_TSV_WIDTH 32
#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
/* CVAL Bit Fields */
#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
#define PIT_CVAL_TVL_SHIFT 0
#define PIT_CVAL_TVL_WIDTH 32
#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
/* TCTRL Bit Fields */
#define PIT_TCTRL_TEN_MASK 0x1u
#define PIT_TCTRL_TEN_SHIFT 0
#define PIT_TCTRL_TEN_WIDTH 1
#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
#define PIT_TCTRL_TIE_MASK 0x2u
#define PIT_TCTRL_TIE_SHIFT 1
#define PIT_TCTRL_TIE_WIDTH 1
#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
#define PIT_TCTRL_CHN_MASK 0x4u
#define PIT_TCTRL_CHN_SHIFT 2
#define PIT_TCTRL_CHN_WIDTH 1
#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
/* TFLG Bit Fields */
#define PIT_TFLG_TIF_MASK 0x1u
#define PIT_TFLG_TIF_SHIFT 0
#define PIT_TFLG_TIF_WIDTH 1
#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
/*!
* @}
*/ /* end of group PIT_Register_Masks */
/* PIT - Peripheral instance base addresses */
/** Peripheral PIT base address */
#define PIT_BASE (0x40037000u)
/** Peripheral PIT base pointer */
#define PIT ((PIT_Type *)PIT_BASE)
#define PIT_BASE_PTR (PIT)
/** Array initializer of PIT peripheral base addresses */
#define PIT_BASE_ADDRS { PIT_BASE }
/** Array initializer of PIT peripheral base pointers */
#define PIT_BASE_PTRS { PIT }
/* ----------------------------------------------------------------------------
-- PIT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
* @{
*/
/* PIT - Register instance definitions */
/* PIT */
#define PIT_MCR PIT_MCR_REG(PIT)
#define PIT_LTMR64H PIT_LTMR64H_REG(PIT)
#define PIT_LTMR64L PIT_LTMR64L_REG(PIT)
#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
/* PIT - Register array accessors */
#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
/*!
* @}
*/ /* end of group PIT_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group PIT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
* @{
*/
/** PMC - Register Layout Typedef */
typedef struct {
__IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
__IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
__IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
uint8_t RESERVED_0[8];
__IO uint8_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0xB */
} PMC_Type, *PMC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
* @{
*/
/* PMC - Register accessors */
#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
#define PMC_REGSC_REG(base) ((base)->REGSC)
#define PMC_HVDSC1_REG(base) ((base)->HVDSC1)
/*!
* @}
*/ /* end of group PMC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Masks PMC Register Masks
* @{
*/
/* LVDSC1 Bit Fields */
#define PMC_LVDSC1_LVDV_MASK 0x3u
#define PMC_LVDSC1_LVDV_SHIFT 0
#define PMC_LVDSC1_LVDV_WIDTH 2
#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
#define PMC_LVDSC1_LVDRE_MASK 0x10u
#define PMC_LVDSC1_LVDRE_SHIFT 4
#define PMC_LVDSC1_LVDRE_WIDTH 1
#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
#define PMC_LVDSC1_LVDIE_MASK 0x20u
#define PMC_LVDSC1_LVDIE_SHIFT 5
#define PMC_LVDSC1_LVDIE_WIDTH 1
#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
#define PMC_LVDSC1_LVDACK_MASK 0x40u
#define PMC_LVDSC1_LVDACK_SHIFT 6
#define PMC_LVDSC1_LVDACK_WIDTH 1
#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
#define PMC_LVDSC1_LVDF_MASK 0x80u
#define PMC_LVDSC1_LVDF_SHIFT 7
#define PMC_LVDSC1_LVDF_WIDTH 1
#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
/* LVDSC2 Bit Fields */
#define PMC_LVDSC2_LVWV_MASK 0x3u
#define PMC_LVDSC2_LVWV_SHIFT 0
#define PMC_LVDSC2_LVWV_WIDTH 2
#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
#define PMC_LVDSC2_LVWIE_MASK 0x20u
#define PMC_LVDSC2_LVWIE_SHIFT 5
#define PMC_LVDSC2_LVWIE_WIDTH 1
#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
#define PMC_LVDSC2_LVWACK_MASK 0x40u
#define PMC_LVDSC2_LVWACK_SHIFT 6
#define PMC_LVDSC2_LVWACK_WIDTH 1
#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
#define PMC_LVDSC2_LVWF_MASK 0x80u
#define PMC_LVDSC2_LVWF_SHIFT 7
#define PMC_LVDSC2_LVWF_WIDTH 1
#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
/* REGSC Bit Fields */
#define PMC_REGSC_BGBE_MASK 0x1u
#define PMC_REGSC_BGBE_SHIFT 0
#define PMC_REGSC_BGBE_WIDTH 1
#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
#define PMC_REGSC_REGONS_MASK 0x4u
#define PMC_REGSC_REGONS_SHIFT 2
#define PMC_REGSC_REGONS_WIDTH 1
#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
#define PMC_REGSC_ACKISO_MASK 0x8u
#define PMC_REGSC_ACKISO_SHIFT 3
#define PMC_REGSC_ACKISO_WIDTH 1
#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
#define PMC_REGSC_BGEN_MASK 0x10u
#define PMC_REGSC_BGEN_SHIFT 4
#define PMC_REGSC_BGEN_WIDTH 1
#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
/* HVDSC1 Bit Fields */
#define PMC_HVDSC1_HVDV_MASK 0x1u
#define PMC_HVDSC1_HVDV_SHIFT 0
#define PMC_HVDSC1_HVDV_WIDTH 1
#define PMC_HVDSC1_HVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDV_SHIFT))&PMC_HVDSC1_HVDV_MASK)
#define PMC_HVDSC1_HVDRE_MASK 0x10u
#define PMC_HVDSC1_HVDRE_SHIFT 4
#define PMC_HVDSC1_HVDRE_WIDTH 1
#define PMC_HVDSC1_HVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDRE_SHIFT))&PMC_HVDSC1_HVDRE_MASK)
#define PMC_HVDSC1_HVDIE_MASK 0x20u
#define PMC_HVDSC1_HVDIE_SHIFT 5
#define PMC_HVDSC1_HVDIE_WIDTH 1
#define PMC_HVDSC1_HVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDIE_SHIFT))&PMC_HVDSC1_HVDIE_MASK)
#define PMC_HVDSC1_HVDACK_MASK 0x40u
#define PMC_HVDSC1_HVDACK_SHIFT 6
#define PMC_HVDSC1_HVDACK_WIDTH 1
#define PMC_HVDSC1_HVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDACK_SHIFT))&PMC_HVDSC1_HVDACK_MASK)
#define PMC_HVDSC1_HVDF_MASK 0x80u
#define PMC_HVDSC1_HVDF_SHIFT 7
#define PMC_HVDSC1_HVDF_WIDTH 1
#define PMC_HVDSC1_HVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDF_SHIFT))&PMC_HVDSC1_HVDF_MASK)
/*!
* @}
*/ /* end of group PMC_Register_Masks */
/* PMC - Peripheral instance base addresses */
/** Peripheral PMC base address */
#define PMC_BASE (0x4007D000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
#define PMC_BASE_PTR (PMC)
/** Array initializer of PMC peripheral base addresses */
#define PMC_BASE_ADDRS { PMC_BASE }
/** Array initializer of PMC peripheral base pointers */
#define PMC_BASE_PTRS { PMC }
/* ----------------------------------------------------------------------------
-- PMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
* @{
*/
/* PMC - Register instance definitions */
/* PMC */
#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
#define PMC_REGSC PMC_REGSC_REG(PMC)
#define PMC_HVDSC1 PMC_HVDSC1_REG(PMC)
/*!
* @}
*/ /* end of group PMC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PORT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
* @{
*/
/** PORT - Register Layout Typedef */
typedef struct {
__IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */
__O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */
uint8_t RESERVED_0[16];
__IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
__IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
__IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
__IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} PORT_Type, *PORT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PORT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
* @{
*/
/* PORT - Register accessors */
#define PORT_PCR_REG(base,index) ((base)->PCR[index])
#define PORT_PCR_COUNT 32
#define PORT_GPCLR_REG(base) ((base)->GPCLR)
#define PORT_GPCHR_REG(base) ((base)->GPCHR)
#define PORT_GICLR_REG(base) ((base)->GICLR)
#define PORT_GICHR_REG(base) ((base)->GICHR)
#define PORT_ISFR_REG(base) ((base)->ISFR)
#define PORT_DFER_REG(base) ((base)->DFER)
#define PORT_DFCR_REG(base) ((base)->DFCR)
#define PORT_DFWR_REG(base) ((base)->DFWR)
/*!
* @}
*/ /* end of group PORT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PORT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Masks PORT Register Masks
* @{
*/
/* PCR Bit Fields */
#define PORT_PCR_PS_MASK 0x1u
#define PORT_PCR_PS_SHIFT 0
#define PORT_PCR_PS_WIDTH 1
#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
#define PORT_PCR_PE_MASK 0x2u
#define PORT_PCR_PE_SHIFT 1
#define PORT_PCR_PE_WIDTH 1
#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
#define PORT_PCR_SRE_MASK 0x4u
#define PORT_PCR_SRE_SHIFT 2
#define PORT_PCR_SRE_WIDTH 1
#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
#define PORT_PCR_PFE_MASK 0x10u
#define PORT_PCR_PFE_SHIFT 4
#define PORT_PCR_PFE_WIDTH 1
#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
#define PORT_PCR_ODE_MASK 0x20u
#define PORT_PCR_ODE_SHIFT 5
#define PORT_PCR_ODE_WIDTH 1
#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
#define PORT_PCR_DSE_MASK 0x40u
#define PORT_PCR_DSE_SHIFT 6
#define PORT_PCR_DSE_WIDTH 1
#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
#define PORT_PCR_MUX_MASK 0xF00u
#define PORT_PCR_MUX_SHIFT 8
#define PORT_PCR_MUX_WIDTH 4
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
#define PORT_PCR_LK_MASK 0x8000u
#define PORT_PCR_LK_SHIFT 15
#define PORT_PCR_LK_WIDTH 1
#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
#define PORT_PCR_IRQC_MASK 0xF0000u
#define PORT_PCR_IRQC_SHIFT 16
#define PORT_PCR_IRQC_WIDTH 4
#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
#define PORT_PCR_ISF_MASK 0x1000000u
#define PORT_PCR_ISF_SHIFT 24
#define PORT_PCR_ISF_WIDTH 1
#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
/* GPCLR Bit Fields */
#define PORT_GPCLR_GPWD_MASK 0xFFFFu
#define PORT_GPCLR_GPWD_SHIFT 0
#define PORT_GPCLR_GPWD_WIDTH 16
#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCLR_GPWE_SHIFT 16
#define PORT_GPCLR_GPWE_WIDTH 16
#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
/* GPCHR Bit Fields */
#define PORT_GPCHR_GPWD_MASK 0xFFFFu
#define PORT_GPCHR_GPWD_SHIFT 0
#define PORT_GPCHR_GPWD_WIDTH 16
#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCHR_GPWE_SHIFT 16
#define PORT_GPCHR_GPWE_WIDTH 16
#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
/* GICLR Bit Fields */
#define PORT_GICLR_GIWE_MASK 0xFFFFu
#define PORT_GICLR_GIWE_SHIFT 0
#define PORT_GICLR_GIWE_WIDTH 16
#define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWE_SHIFT))&PORT_GICLR_GIWE_MASK)
#define PORT_GICLR_GIWD_MASK 0xFFFF0000u
#define PORT_GICLR_GIWD_SHIFT 16
#define PORT_GICLR_GIWD_WIDTH 16
#define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWD_SHIFT))&PORT_GICLR_GIWD_MASK)
/* GICHR Bit Fields */
#define PORT_GICHR_GIWE_MASK 0xFFFFu
#define PORT_GICHR_GIWE_SHIFT 0
#define PORT_GICHR_GIWE_WIDTH 16
#define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWE_SHIFT))&PORT_GICHR_GIWE_MASK)
#define PORT_GICHR_GIWD_MASK 0xFFFF0000u
#define PORT_GICHR_GIWD_SHIFT 16
#define PORT_GICHR_GIWD_WIDTH 16
#define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWD_SHIFT))&PORT_GICHR_GIWD_MASK)
/* ISFR Bit Fields */
#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
#define PORT_ISFR_ISF_SHIFT 0
#define PORT_ISFR_ISF_WIDTH 32
#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
/* DFER Bit Fields */
#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
#define PORT_DFER_DFE_SHIFT 0
#define PORT_DFER_DFE_WIDTH 32
#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
/* DFCR Bit Fields */
#define PORT_DFCR_CS_MASK 0x1u
#define PORT_DFCR_CS_SHIFT 0
#define PORT_DFCR_CS_WIDTH 1
#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
/* DFWR Bit Fields */
#define PORT_DFWR_FILT_MASK 0x1Fu
#define PORT_DFWR_FILT_SHIFT 0
#define PORT_DFWR_FILT_WIDTH 5
#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
/*!
* @}
*/ /* end of group PORT_Register_Masks */
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base address */
#define PORTA_BASE (0x40049000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
#define PORTA_BASE_PTR (PORTA)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4004A000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
#define PORTB_BASE_PTR (PORTB)
/** Peripheral PORTC base address */
#define PORTC_BASE (0x4004B000u)
/** Peripheral PORTC base pointer */
#define PORTC ((PORT_Type *)PORTC_BASE)
#define PORTC_BASE_PTR (PORTC)
/** Peripheral PORTD base address */
#define PORTD_BASE (0x4004C000u)
/** Peripheral PORTD base pointer */
#define PORTD ((PORT_Type *)PORTD_BASE)
#define PORTD_BASE_PTR (PORTD)
/** Peripheral PORTE base address */
#define PORTE_BASE (0x4004D000u)
/** Peripheral PORTE base pointer */
#define PORTE ((PORT_Type *)PORTE_BASE)
#define PORTE_BASE_PTR (PORTE)
/** Array initializer of PORT peripheral base addresses */
#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
/** Array initializer of PORT peripheral base pointers */
#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
/* ----------------------------------------------------------------------------
-- PORT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
* @{
*/
/* PORT - Register instance definitions */
/* PORTA */
#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
#define PORTA_GICLR PORT_GICLR_REG(PORTA)
#define PORTA_GICHR PORT_GICHR_REG(PORTA)
#define PORTA_ISFR PORT_ISFR_REG(PORTA)
/* PORTB */
#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
#define PORTB_GICLR PORT_GICLR_REG(PORTB)
#define PORTB_GICHR PORT_GICHR_REG(PORTB)
#define PORTB_ISFR PORT_ISFR_REG(PORTB)
/* PORTC */
#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
#define PORTC_GICLR PORT_GICLR_REG(PORTC)
#define PORTC_GICHR PORT_GICHR_REG(PORTC)
#define PORTC_ISFR PORT_ISFR_REG(PORTC)
/* PORTD */
#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
#define PORTD_GICLR PORT_GICLR_REG(PORTD)
#define PORTD_GICHR PORT_GICHR_REG(PORTD)
#define PORTD_ISFR PORT_ISFR_REG(PORTD)
#define PORTD_DFER PORT_DFER_REG(PORTD)
#define PORTD_DFCR PORT_DFCR_REG(PORTD)
#define PORTD_DFWR PORT_DFWR_REG(PORTD)
/* PORTE */
#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
#define PORTE_GICLR PORT_GICLR_REG(PORTE)
#define PORTE_GICHR PORT_GICHR_REG(PORTE)
#define PORTE_ISFR PORT_ISFR_REG(PORTE)
/* PORT - Register array accessors */
#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
/*!
* @}
*/ /* end of group PORT_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
* @{
*/
/** RCM - Register Layout Typedef */
typedef struct {
__I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
__I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
uint8_t RESERVED_0[2];
__IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
__IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
uint8_t RESERVED_1[2];
__IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
__IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
} RCM_Type, *RCM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
* @{
*/
/* RCM - Register accessors */
#define RCM_SRS0_REG(base) ((base)->SRS0)
#define RCM_SRS1_REG(base) ((base)->SRS1)
#define RCM_RPFC_REG(base) ((base)->RPFC)
#define RCM_RPFW_REG(base) ((base)->RPFW)
#define RCM_SSRS0_REG(base) ((base)->SSRS0)
#define RCM_SSRS1_REG(base) ((base)->SSRS1)
/*!
* @}
*/ /* end of group RCM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Masks RCM Register Masks
* @{
*/
/* SRS0 Bit Fields */
#define RCM_SRS0_WAKEUP_MASK 0x1u
#define RCM_SRS0_WAKEUP_SHIFT 0
#define RCM_SRS0_WAKEUP_WIDTH 1
#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
#define RCM_SRS0_LVD_MASK 0x2u
#define RCM_SRS0_LVD_SHIFT 1
#define RCM_SRS0_LVD_WIDTH 1
#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
#define RCM_SRS0_LOC_MASK 0x4u
#define RCM_SRS0_LOC_SHIFT 2
#define RCM_SRS0_LOC_WIDTH 1
#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
#define RCM_SRS0_LOL_MASK 0x8u
#define RCM_SRS0_LOL_SHIFT 3
#define RCM_SRS0_LOL_WIDTH 1
#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
#define RCM_SRS0_WDOG_MASK 0x20u
#define RCM_SRS0_WDOG_SHIFT 5
#define RCM_SRS0_WDOG_WIDTH 1
#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
#define RCM_SRS0_PIN_MASK 0x40u
#define RCM_SRS0_PIN_SHIFT 6
#define RCM_SRS0_PIN_WIDTH 1
#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
#define RCM_SRS0_POR_MASK 0x80u
#define RCM_SRS0_POR_SHIFT 7
#define RCM_SRS0_POR_WIDTH 1
#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
/* SRS1 Bit Fields */
#define RCM_SRS1_JTAG_MASK 0x1u
#define RCM_SRS1_JTAG_SHIFT 0
#define RCM_SRS1_JTAG_WIDTH 1
#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
#define RCM_SRS1_LOCKUP_MASK 0x2u
#define RCM_SRS1_LOCKUP_SHIFT 1
#define RCM_SRS1_LOCKUP_WIDTH 1
#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
#define RCM_SRS1_SW_MASK 0x4u
#define RCM_SRS1_SW_SHIFT 2
#define RCM_SRS1_SW_WIDTH 1
#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
#define RCM_SRS1_MDM_AP_MASK 0x8u
#define RCM_SRS1_MDM_AP_SHIFT 3
#define RCM_SRS1_MDM_AP_WIDTH 1
#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
#define RCM_SRS1_SACKERR_MASK 0x20u
#define RCM_SRS1_SACKERR_SHIFT 5
#define RCM_SRS1_SACKERR_WIDTH 1
#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
/* RPFC Bit Fields */
#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
#define RCM_RPFC_RSTFLTSRW_SHIFT 0
#define RCM_RPFC_RSTFLTSRW_WIDTH 2
#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
#define RCM_RPFC_RSTFLTSS_MASK 0x4u
#define RCM_RPFC_RSTFLTSS_SHIFT 2
#define RCM_RPFC_RSTFLTSS_WIDTH 1
#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
/* RPFW Bit Fields */
#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
#define RCM_RPFW_RSTFLTSEL_SHIFT 0
#define RCM_RPFW_RSTFLTSEL_WIDTH 5
#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
/* SSRS0 Bit Fields */
#define RCM_SSRS0_SWAKEUP_MASK 0x1u
#define RCM_SSRS0_SWAKEUP_SHIFT 0
#define RCM_SSRS0_SWAKEUP_WIDTH 1
#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWAKEUP_SHIFT))&RCM_SSRS0_SWAKEUP_MASK)
#define RCM_SSRS0_SLVD_MASK 0x2u
#define RCM_SSRS0_SLVD_SHIFT 1
#define RCM_SSRS0_SLVD_WIDTH 1
#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLVD_SHIFT))&RCM_SSRS0_SLVD_MASK)
#define RCM_SSRS0_SLOC_MASK 0x4u
#define RCM_SSRS0_SLOC_SHIFT 2
#define RCM_SSRS0_SLOC_WIDTH 1
#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLOC_SHIFT))&RCM_SSRS0_SLOC_MASK)
#define RCM_SSRS0_SLOL_MASK 0x8u
#define RCM_SSRS0_SLOL_SHIFT 3
#define RCM_SSRS0_SLOL_WIDTH 1
#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLOL_SHIFT))&RCM_SSRS0_SLOL_MASK)
#define RCM_SSRS0_SWDOG_MASK 0x20u
#define RCM_SSRS0_SWDOG_SHIFT 5
#define RCM_SSRS0_SWDOG_WIDTH 1
#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWDOG_SHIFT))&RCM_SSRS0_SWDOG_MASK)
#define RCM_SSRS0_SPIN_MASK 0x40u
#define RCM_SSRS0_SPIN_SHIFT 6
#define RCM_SSRS0_SPIN_WIDTH 1
#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPIN_SHIFT))&RCM_SSRS0_SPIN_MASK)
#define RCM_SSRS0_SPOR_MASK 0x80u
#define RCM_SSRS0_SPOR_SHIFT 7
#define RCM_SSRS0_SPOR_WIDTH 1
#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPOR_SHIFT))&RCM_SSRS0_SPOR_MASK)
/* SSRS1 Bit Fields */
#define RCM_SSRS1_SJTAG_MASK 0x1u
#define RCM_SSRS1_SJTAG_SHIFT 0
#define RCM_SSRS1_SJTAG_WIDTH 1
#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SJTAG_SHIFT))&RCM_SSRS1_SJTAG_MASK)
#define RCM_SSRS1_SLOCKUP_MASK 0x2u
#define RCM_SSRS1_SLOCKUP_SHIFT 1
#define RCM_SSRS1_SLOCKUP_WIDTH 1
#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SLOCKUP_SHIFT))&RCM_SSRS1_SLOCKUP_MASK)
#define RCM_SSRS1_SSW_MASK 0x4u
#define RCM_SSRS1_SSW_SHIFT 2
#define RCM_SSRS1_SSW_WIDTH 1
#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSW_SHIFT))&RCM_SSRS1_SSW_MASK)
#define RCM_SSRS1_SMDM_AP_MASK 0x8u
#define RCM_SSRS1_SMDM_AP_SHIFT 3
#define RCM_SSRS1_SMDM_AP_WIDTH 1
#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SMDM_AP_SHIFT))&RCM_SSRS1_SMDM_AP_MASK)
#define RCM_SSRS1_SSACKERR_MASK 0x20u
#define RCM_SSRS1_SSACKERR_SHIFT 5
#define RCM_SSRS1_SSACKERR_WIDTH 1
#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSACKERR_SHIFT))&RCM_SSRS1_SSACKERR_MASK)
/*!
* @}
*/ /* end of group RCM_Register_Masks */
/* RCM - Peripheral instance base addresses */
/** Peripheral RCM base address */
#define RCM_BASE (0x4007F000u)
/** Peripheral RCM base pointer */
#define RCM ((RCM_Type *)RCM_BASE)
#define RCM_BASE_PTR (RCM)
/** Array initializer of RCM peripheral base addresses */
#define RCM_BASE_ADDRS { RCM_BASE }
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASE_PTRS { RCM }
/* ----------------------------------------------------------------------------
-- RCM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
* @{
*/
/* RCM - Register instance definitions */
/* RCM */
#define RCM_SRS0 RCM_SRS0_REG(RCM)
#define RCM_SRS1 RCM_SRS1_REG(RCM)
#define RCM_RPFC RCM_RPFC_REG(RCM)
#define RCM_RPFW RCM_RPFW_REG(RCM)
#define RCM_SSRS0 RCM_SSRS0_REG(RCM)
#define RCM_SSRS1 RCM_SSRS1_REG(RCM)
/*!
* @}
*/ /* end of group RCM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RFSYS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
* @{
*/
/** RFSYS - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
} RFSYS_Type, *RFSYS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RFSYS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
* @{
*/
/* RFSYS - Register accessors */
#define RFSYS_REG_REG(base,index) ((base)->REG[index])
#define RFSYS_REG_COUNT 8
/*!
* @}
*/ /* end of group RFSYS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RFSYS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFSYS_Register_Masks RFSYS Register Masks
* @{
*/
/* REG Bit Fields */
#define RFSYS_REG_LL_MASK 0xFFu
#define RFSYS_REG_LL_SHIFT 0
#define RFSYS_REG_LL_WIDTH 8
#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
#define RFSYS_REG_LH_MASK 0xFF00u
#define RFSYS_REG_LH_SHIFT 8
#define RFSYS_REG_LH_WIDTH 8
#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
#define RFSYS_REG_HL_MASK 0xFF0000u
#define RFSYS_REG_HL_SHIFT 16
#define RFSYS_REG_HL_WIDTH 8
#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
#define RFSYS_REG_HH_MASK 0xFF000000u
#define RFSYS_REG_HH_SHIFT 24
#define RFSYS_REG_HH_WIDTH 8
#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
/*!
* @}
*/ /* end of group RFSYS_Register_Masks */
/* RFSYS - Peripheral instance base addresses */
/** Peripheral RFSYS base address */
#define RFSYS_BASE (0x40041000u)
/** Peripheral RFSYS base pointer */
#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
#define RFSYS_BASE_PTR (RFSYS)
/** Array initializer of RFSYS peripheral base addresses */
#define RFSYS_BASE_ADDRS { RFSYS_BASE }
/** Array initializer of RFSYS peripheral base pointers */
#define RFSYS_BASE_PTRS { RFSYS }
/* ----------------------------------------------------------------------------
-- RFSYS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
* @{
*/
/* RFSYS - Register instance definitions */
/* RFSYS */
#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
/* RFSYS - Register array accessors */
#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
/*!
* @}
*/ /* end of group RFSYS_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group RFSYS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RFVBAT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
* @{
*/
/** RFVBAT - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
} RFVBAT_Type, *RFVBAT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RFVBAT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
* @{
*/
/* RFVBAT - Register accessors */
#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
#define RFVBAT_REG_COUNT 8
/*!
* @}
*/ /* end of group RFVBAT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RFVBAT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
* @{
*/
/* REG Bit Fields */
#define RFVBAT_REG_LL_MASK 0xFFu
#define RFVBAT_REG_LL_SHIFT 0
#define RFVBAT_REG_LL_WIDTH 8
#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
#define RFVBAT_REG_LH_MASK 0xFF00u
#define RFVBAT_REG_LH_SHIFT 8
#define RFVBAT_REG_LH_WIDTH 8
#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
#define RFVBAT_REG_HL_MASK 0xFF0000u
#define RFVBAT_REG_HL_SHIFT 16
#define RFVBAT_REG_HL_WIDTH 8
#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
#define RFVBAT_REG_HH_MASK 0xFF000000u
#define RFVBAT_REG_HH_SHIFT 24
#define RFVBAT_REG_HH_WIDTH 8
#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
/*!
* @}
*/ /* end of group RFVBAT_Register_Masks */
/* RFVBAT - Peripheral instance base addresses */
/** Peripheral RFVBAT base address */
#define RFVBAT_BASE (0x4003E000u)
/** Peripheral RFVBAT base pointer */
#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
#define RFVBAT_BASE_PTR (RFVBAT)
/** Array initializer of RFVBAT peripheral base addresses */
#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
/** Array initializer of RFVBAT peripheral base pointers */
#define RFVBAT_BASE_PTRS { RFVBAT }
/* ----------------------------------------------------------------------------
-- RFVBAT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
* @{
*/
/* RFVBAT - Register instance definitions */
/* RFVBAT */
#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
/* RFVBAT - Register array accessors */
#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
/*!
* @}
*/ /* end of group RFVBAT_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group RFVBAT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RNG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
* @{
*/
/** RNG - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
__I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
__O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
__I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
} RNG_Type, *RNG_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RNG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
* @{
*/
/* RNG - Register accessors */
#define RNG_CR_REG(base) ((base)->CR)
#define RNG_SR_REG(base) ((base)->SR)
#define RNG_ER_REG(base) ((base)->ER)
#define RNG_OR_REG(base) ((base)->OR)
/*!
* @}
*/ /* end of group RNG_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RNG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RNG_Register_Masks RNG Register Masks
* @{
*/
/* CR Bit Fields */
#define RNG_CR_GO_MASK 0x1u
#define RNG_CR_GO_SHIFT 0
#define RNG_CR_GO_WIDTH 1
#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
#define RNG_CR_HA_MASK 0x2u
#define RNG_CR_HA_SHIFT 1
#define RNG_CR_HA_WIDTH 1
#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
#define RNG_CR_INTM_MASK 0x4u
#define RNG_CR_INTM_SHIFT 2
#define RNG_CR_INTM_WIDTH 1
#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
#define RNG_CR_CLRI_MASK 0x8u
#define RNG_CR_CLRI_SHIFT 3
#define RNG_CR_CLRI_WIDTH 1
#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
#define RNG_CR_SLP_MASK 0x10u
#define RNG_CR_SLP_SHIFT 4
#define RNG_CR_SLP_WIDTH 1
#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
/* SR Bit Fields */
#define RNG_SR_SECV_MASK 0x1u
#define RNG_SR_SECV_SHIFT 0
#define RNG_SR_SECV_WIDTH 1
#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
#define RNG_SR_LRS_MASK 0x2u
#define RNG_SR_LRS_SHIFT 1
#define RNG_SR_LRS_WIDTH 1
#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
#define RNG_SR_ORU_MASK 0x4u
#define RNG_SR_ORU_SHIFT 2
#define RNG_SR_ORU_WIDTH 1
#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
#define RNG_SR_ERRI_MASK 0x8u
#define RNG_SR_ERRI_SHIFT 3
#define RNG_SR_ERRI_WIDTH 1
#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
#define RNG_SR_SLP_MASK 0x10u
#define RNG_SR_SLP_SHIFT 4
#define RNG_SR_SLP_WIDTH 1
#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
#define RNG_SR_OREG_LVL_MASK 0xFF00u
#define RNG_SR_OREG_LVL_SHIFT 8
#define RNG_SR_OREG_LVL_WIDTH 8
#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
#define RNG_SR_OREG_SIZE_MASK 0xFF0000u
#define RNG_SR_OREG_SIZE_SHIFT 16
#define RNG_SR_OREG_SIZE_WIDTH 8
#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
/* ER Bit Fields */
#define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
#define RNG_ER_EXT_ENT_SHIFT 0
#define RNG_ER_EXT_ENT_WIDTH 32
#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
/* OR Bit Fields */
#define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
#define RNG_OR_RANDOUT_SHIFT 0
#define RNG_OR_RANDOUT_WIDTH 32
#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
/*!
* @}
*/ /* end of group RNG_Register_Masks */
/* RNG - Peripheral instance base addresses */
/** Peripheral RNG base address */
#define RNG_BASE (0x40029000u)
/** Peripheral RNG base pointer */
#define RNG ((RNG_Type *)RNG_BASE)
#define RNG_BASE_PTR (RNG)
/** Array initializer of RNG peripheral base addresses */
#define RNG_BASE_ADDRS { RNG_BASE }
/** Array initializer of RNG peripheral base pointers */
#define RNG_BASE_PTRS { RNG }
/* ----------------------------------------------------------------------------
-- RNG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
* @{
*/
/* RNG - Register instance definitions */
/* RNG */
#define RNG_CR RNG_CR_REG(RNG)
#define RNG_SR RNG_SR_REG(RNG)
#define RNG_ER RNG_ER_REG(RNG)
#define RNG_OR RNG_OR_REG(RNG)
/*!
* @}
*/ /* end of group RNG_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group RNG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RTC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
* @{
*/
/** RTC - Register Layout Typedef */
typedef struct {
__IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
__IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
__IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
__IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
__IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
__IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
__IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
uint8_t RESERVED_0[2016];
__IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
__IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
} RTC_Type, *RTC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RTC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
* @{
*/
/* RTC - Register accessors */
#define RTC_TSR_REG(base) ((base)->TSR)
#define RTC_TPR_REG(base) ((base)->TPR)
#define RTC_TAR_REG(base) ((base)->TAR)
#define RTC_TCR_REG(base) ((base)->TCR)
#define RTC_CR_REG(base) ((base)->CR)
#define RTC_SR_REG(base) ((base)->SR)
#define RTC_LR_REG(base) ((base)->LR)
#define RTC_IER_REG(base) ((base)->IER)
#define RTC_WAR_REG(base) ((base)->WAR)
#define RTC_RAR_REG(base) ((base)->RAR)
/*!
* @}
*/ /* end of group RTC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RTC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Masks RTC Register Masks
* @{
*/
/* TSR Bit Fields */
#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
#define RTC_TSR_TSR_SHIFT 0
#define RTC_TSR_TSR_WIDTH 32
#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
/* TPR Bit Fields */
#define RTC_TPR_TPR_MASK 0xFFFFu
#define RTC_TPR_TPR_SHIFT 0
#define RTC_TPR_TPR_WIDTH 16
#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
/* TAR Bit Fields */
#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
#define RTC_TAR_TAR_SHIFT 0
#define RTC_TAR_TAR_WIDTH 32
#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
/* TCR Bit Fields */
#define RTC_TCR_TCR_MASK 0xFFu
#define RTC_TCR_TCR_SHIFT 0
#define RTC_TCR_TCR_WIDTH 8
#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
#define RTC_TCR_CIR_MASK 0xFF00u
#define RTC_TCR_CIR_SHIFT 8
#define RTC_TCR_CIR_WIDTH 8
#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
#define RTC_TCR_TCV_MASK 0xFF0000u
#define RTC_TCR_TCV_SHIFT 16
#define RTC_TCR_TCV_WIDTH 8
#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
#define RTC_TCR_CIC_MASK 0xFF000000u
#define RTC_TCR_CIC_SHIFT 24
#define RTC_TCR_CIC_WIDTH 8
#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
/* CR Bit Fields */
#define RTC_CR_SWR_MASK 0x1u
#define RTC_CR_SWR_SHIFT 0
#define RTC_CR_SWR_WIDTH 1
#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
#define RTC_CR_WPE_MASK 0x2u
#define RTC_CR_WPE_SHIFT 1
#define RTC_CR_WPE_WIDTH 1
#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
#define RTC_CR_SUP_MASK 0x4u
#define RTC_CR_SUP_SHIFT 2
#define RTC_CR_SUP_WIDTH 1
#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
#define RTC_CR_UM_MASK 0x8u
#define RTC_CR_UM_SHIFT 3
#define RTC_CR_UM_WIDTH 1
#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
#define RTC_CR_WPS_MASK 0x10u
#define RTC_CR_WPS_SHIFT 4
#define RTC_CR_WPS_WIDTH 1
#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
#define RTC_CR_OSCE_MASK 0x100u
#define RTC_CR_OSCE_SHIFT 8
#define RTC_CR_OSCE_WIDTH 1
#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
#define RTC_CR_CLKO_MASK 0x200u
#define RTC_CR_CLKO_SHIFT 9
#define RTC_CR_CLKO_WIDTH 1
#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
#define RTC_CR_SC16P_MASK 0x400u
#define RTC_CR_SC16P_SHIFT 10
#define RTC_CR_SC16P_WIDTH 1
#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
#define RTC_CR_SC8P_MASK 0x800u
#define RTC_CR_SC8P_SHIFT 11
#define RTC_CR_SC8P_WIDTH 1
#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
#define RTC_CR_SC4P_MASK 0x1000u
#define RTC_CR_SC4P_SHIFT 12
#define RTC_CR_SC4P_WIDTH 1
#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
#define RTC_CR_SC2P_MASK 0x2000u
#define RTC_CR_SC2P_SHIFT 13
#define RTC_CR_SC2P_WIDTH 1
#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
/* SR Bit Fields */
#define RTC_SR_TIF_MASK 0x1u
#define RTC_SR_TIF_SHIFT 0
#define RTC_SR_TIF_WIDTH 1
#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
#define RTC_SR_TOF_MASK 0x2u
#define RTC_SR_TOF_SHIFT 1
#define RTC_SR_TOF_WIDTH 1
#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
#define RTC_SR_TAF_MASK 0x4u
#define RTC_SR_TAF_SHIFT 2
#define RTC_SR_TAF_WIDTH 1
#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
#define RTC_SR_TCE_MASK 0x10u
#define RTC_SR_TCE_SHIFT 4
#define RTC_SR_TCE_WIDTH 1
#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
/* LR Bit Fields */
#define RTC_LR_TCL_MASK 0x8u
#define RTC_LR_TCL_SHIFT 3
#define RTC_LR_TCL_WIDTH 1
#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
#define RTC_LR_CRL_MASK 0x10u
#define RTC_LR_CRL_SHIFT 4
#define RTC_LR_CRL_WIDTH 1
#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
#define RTC_LR_SRL_MASK 0x20u
#define RTC_LR_SRL_SHIFT 5
#define RTC_LR_SRL_WIDTH 1
#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
#define RTC_LR_LRL_MASK 0x40u
#define RTC_LR_LRL_SHIFT 6
#define RTC_LR_LRL_WIDTH 1
#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
/* IER Bit Fields */
#define RTC_IER_TIIE_MASK 0x1u
#define RTC_IER_TIIE_SHIFT 0
#define RTC_IER_TIIE_WIDTH 1
#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
#define RTC_IER_TOIE_MASK 0x2u
#define RTC_IER_TOIE_SHIFT 1
#define RTC_IER_TOIE_WIDTH 1
#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
#define RTC_IER_TAIE_MASK 0x4u
#define RTC_IER_TAIE_SHIFT 2
#define RTC_IER_TAIE_WIDTH 1
#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
#define RTC_IER_TSIE_MASK 0x10u
#define RTC_IER_TSIE_SHIFT 4
#define RTC_IER_TSIE_WIDTH 1
#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
#define RTC_IER_WPON_MASK 0x80u
#define RTC_IER_WPON_SHIFT 7
#define RTC_IER_WPON_WIDTH 1
#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
/* WAR Bit Fields */
#define RTC_WAR_TSRW_MASK 0x1u
#define RTC_WAR_TSRW_SHIFT 0
#define RTC_WAR_TSRW_WIDTH 1
#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
#define RTC_WAR_TPRW_MASK 0x2u
#define RTC_WAR_TPRW_SHIFT 1
#define RTC_WAR_TPRW_WIDTH 1
#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
#define RTC_WAR_TARW_MASK 0x4u
#define RTC_WAR_TARW_SHIFT 2
#define RTC_WAR_TARW_WIDTH 1
#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
#define RTC_WAR_TCRW_MASK 0x8u
#define RTC_WAR_TCRW_SHIFT 3
#define RTC_WAR_TCRW_WIDTH 1
#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
#define RTC_WAR_CRW_MASK 0x10u
#define RTC_WAR_CRW_SHIFT 4
#define RTC_WAR_CRW_WIDTH 1
#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
#define RTC_WAR_SRW_MASK 0x20u
#define RTC_WAR_SRW_SHIFT 5
#define RTC_WAR_SRW_WIDTH 1
#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
#define RTC_WAR_LRW_MASK 0x40u
#define RTC_WAR_LRW_SHIFT 6
#define RTC_WAR_LRW_WIDTH 1
#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
#define RTC_WAR_IERW_MASK 0x80u
#define RTC_WAR_IERW_SHIFT 7
#define RTC_WAR_IERW_WIDTH 1
#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
/* RAR Bit Fields */
#define RTC_RAR_TSRR_MASK 0x1u
#define RTC_RAR_TSRR_SHIFT 0
#define RTC_RAR_TSRR_WIDTH 1
#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
#define RTC_RAR_TPRR_MASK 0x2u
#define RTC_RAR_TPRR_SHIFT 1
#define RTC_RAR_TPRR_WIDTH 1
#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
#define RTC_RAR_TARR_MASK 0x4u
#define RTC_RAR_TARR_SHIFT 2
#define RTC_RAR_TARR_WIDTH 1
#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
#define RTC_RAR_TCRR_MASK 0x8u
#define RTC_RAR_TCRR_SHIFT 3
#define RTC_RAR_TCRR_WIDTH 1
#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
#define RTC_RAR_CRR_MASK 0x10u
#define RTC_RAR_CRR_SHIFT 4
#define RTC_RAR_CRR_WIDTH 1
#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
#define RTC_RAR_SRR_MASK 0x20u
#define RTC_RAR_SRR_SHIFT 5
#define RTC_RAR_SRR_WIDTH 1
#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
#define RTC_RAR_LRR_MASK 0x40u
#define RTC_RAR_LRR_SHIFT 6
#define RTC_RAR_LRR_WIDTH 1
#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
#define RTC_RAR_IERR_MASK 0x80u
#define RTC_RAR_IERR_SHIFT 7
#define RTC_RAR_IERR_WIDTH 1
#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
/*!
* @}
*/ /* end of group RTC_Register_Masks */
/* RTC - Peripheral instance base addresses */
/** Peripheral RTC base address */
#define RTC_BASE (0x4003D000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
#define RTC_BASE_PTR (RTC)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS { RTC_BASE }
/** Array initializer of RTC peripheral base pointers */
#define RTC_BASE_PTRS { RTC }
/* ----------------------------------------------------------------------------
-- RTC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
* @{
*/
/* RTC - Register instance definitions */
/* RTC */
#define RTC_TSR RTC_TSR_REG(RTC)
#define RTC_TPR RTC_TPR_REG(RTC)
#define RTC_TAR RTC_TAR_REG(RTC)
#define RTC_TCR RTC_TCR_REG(RTC)
#define RTC_CR RTC_CR_REG(RTC)
#define RTC_SR RTC_SR_REG(RTC)
#define RTC_LR RTC_LR_REG(RTC)
#define RTC_IER RTC_IER_REG(RTC)
#define RTC_WAR RTC_WAR_REG(RTC)
#define RTC_RAR RTC_RAR_REG(RTC)
/*!
* @}
*/ /* end of group RTC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
* @{
*/
/** SIM - Register Layout Typedef */
typedef struct {
__IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
uint8_t RESERVED_0[4096];
__IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
uint8_t RESERVED_1[8];
__IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
uint8_t RESERVED_2[4];
__IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
uint8_t RESERVED_3[4];
__IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */
__I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint8_t RESERVED_4[12];
__IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
__IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
__IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
__IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
__IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
__IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
__IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
__I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
__I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
__IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */
uint8_t RESERVED_5[4];
__IO uint32_t MISCCTL; /**< Miscellaneous Control Register, offset: 0x106C */
} SIM_Type, *SIM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SIM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
* @{
*/
/* SIM - Register accessors */
#define SIM_SOPT1_REG(base) ((base)->SOPT1)
#define SIM_SOPT2_REG(base) ((base)->SOPT2)
#define SIM_SOPT5_REG(base) ((base)->SOPT5)
#define SIM_SOPT7_REG(base) ((base)->SOPT7)
#define SIM_SOPT9_REG(base) ((base)->SOPT9)
#define SIM_SDID_REG(base) ((base)->SDID)
#define SIM_SCGC4_REG(base) ((base)->SCGC4)
#define SIM_SCGC5_REG(base) ((base)->SCGC5)
#define SIM_SCGC6_REG(base) ((base)->SCGC6)
#define SIM_SCGC7_REG(base) ((base)->SCGC7)
#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
#define SIM_FCFG1_REG(base) ((base)->FCFG1)
#define SIM_FCFG2_REG(base) ((base)->FCFG2)
#define SIM_UIDH_REG(base) ((base)->UIDH)
#define SIM_UIDMH_REG(base) ((base)->UIDMH)
#define SIM_UIDML_REG(base) ((base)->UIDML)
#define SIM_UIDL_REG(base) ((base)->UIDL)
#define SIM_CLKDIV3_REG(base) ((base)->CLKDIV3)
#define SIM_MISCCTL_REG(base) ((base)->MISCCTL)
/*!
* @}
*/ /* end of group SIM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Masks SIM Register Masks
* @{
*/
/* SOPT1 Bit Fields */
#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
#define SIM_SOPT1_RAMSIZE_SHIFT 12
#define SIM_SOPT1_RAMSIZE_WIDTH 4
#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
#define SIM_SOPT1_OSC32KOUT_SHIFT 16
#define SIM_SOPT1_OSC32KOUT_WIDTH 2
#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
#define SIM_SOPT1_OSC32KSEL_SHIFT 18
#define SIM_SOPT1_OSC32KSEL_WIDTH 2
#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
/* SOPT2 Bit Fields */
#define SIM_SOPT2_LPI2C1SRC_MASK 0xCu
#define SIM_SOPT2_LPI2C1SRC_SHIFT 2
#define SIM_SOPT2_LPI2C1SRC_WIDTH 2
#define SIM_SOPT2_LPI2C1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPI2C1SRC_SHIFT))&SIM_SOPT2_LPI2C1SRC_MASK)
#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH 1
#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
#define SIM_SOPT2_CLKOUTSEL_WIDTH 3
#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
#define SIM_SOPT2_LPI2C0SRC_MASK 0xC00u
#define SIM_SOPT2_LPI2C0SRC_SHIFT 10
#define SIM_SOPT2_LPI2C0SRC_WIDTH 2
#define SIM_SOPT2_LPI2C0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPI2C0SRC_SHIFT))&SIM_SOPT2_LPI2C0SRC_MASK)
#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
#define SIM_SOPT2_TRACECLKSEL_WIDTH 1
#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
#define SIM_SOPT2_PLLFLLSEL_WIDTH 2
#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
#define SIM_SOPT2_USBSRC_MASK 0x40000u
#define SIM_SOPT2_USBSRC_SHIFT 18
#define SIM_SOPT2_USBSRC_WIDTH 1
#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
#define SIM_SOPT2_FLEXIOSRC_MASK 0xC00000u
#define SIM_SOPT2_FLEXIOSRC_SHIFT 22
#define SIM_SOPT2_FLEXIOSRC_WIDTH 2
#define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
#define SIM_SOPT2_TPMSRC_SHIFT 24
#define SIM_SOPT2_TPMSRC_WIDTH 2
#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
#define SIM_SOPT2_LPUARTSRC_MASK 0xC000000u
#define SIM_SOPT2_LPUARTSRC_SHIFT 26
#define SIM_SOPT2_LPUARTSRC_WIDTH 2
#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
/* SOPT5 Bit Fields */
#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
#define SIM_SOPT5_UART0TXSRC_SHIFT 0
#define SIM_SOPT5_UART0TXSRC_WIDTH 2
#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
#define SIM_SOPT5_UART0RXSRC_SHIFT 2
#define SIM_SOPT5_UART0RXSRC_WIDTH 2
#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
#define SIM_SOPT5_UART1TXSRC_SHIFT 4
#define SIM_SOPT5_UART1TXSRC_WIDTH 2
#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
#define SIM_SOPT5_UART1RXSRC_SHIFT 6
#define SIM_SOPT5_UART1RXSRC_WIDTH 2
#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
#define SIM_SOPT5_LPUART0TXSRC_MASK 0x30000u
#define SIM_SOPT5_LPUART0TXSRC_SHIFT 16
#define SIM_SOPT5_LPUART0TXSRC_WIDTH 2
#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
#define SIM_SOPT5_LPUART0RXSRC_MASK 0xC0000u
#define SIM_SOPT5_LPUART0RXSRC_SHIFT 18
#define SIM_SOPT5_LPUART0RXSRC_WIDTH 2
#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
/* SOPT7 Bit Fields */
#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
#define SIM_SOPT7_ADC0TRGSEL_WIDTH 4
#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH 1
#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH 1
#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
/* SOPT9 Bit Fields */
#define SIM_SOPT9_TPM1CH0SRC_MASK 0xC0000u
#define SIM_SOPT9_TPM1CH0SRC_SHIFT 18
#define SIM_SOPT9_TPM1CH0SRC_WIDTH 2
#define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM1CH0SRC_SHIFT))&SIM_SOPT9_TPM1CH0SRC_MASK)
#define SIM_SOPT9_TPM2CH0SRC_MASK 0x300000u
#define SIM_SOPT9_TPM2CH0SRC_SHIFT 20
#define SIM_SOPT9_TPM2CH0SRC_WIDTH 2
#define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM2CH0SRC_SHIFT))&SIM_SOPT9_TPM2CH0SRC_MASK)
#define SIM_SOPT9_TPM0CLKSEL_MASK 0x1000000u
#define SIM_SOPT9_TPM0CLKSEL_SHIFT 24
#define SIM_SOPT9_TPM0CLKSEL_WIDTH 1
#define SIM_SOPT9_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM0CLKSEL_SHIFT))&SIM_SOPT9_TPM0CLKSEL_MASK)
#define SIM_SOPT9_TPM1CLKSEL_MASK 0x2000000u
#define SIM_SOPT9_TPM1CLKSEL_SHIFT 25
#define SIM_SOPT9_TPM1CLKSEL_WIDTH 1
#define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM1CLKSEL_SHIFT))&SIM_SOPT9_TPM1CLKSEL_MASK)
#define SIM_SOPT9_TPM2CLKSEL_MASK 0x4000000u
#define SIM_SOPT9_TPM2CLKSEL_SHIFT 26
#define SIM_SOPT9_TPM2CLKSEL_WIDTH 1
#define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM2CLKSEL_SHIFT))&SIM_SOPT9_TPM2CLKSEL_MASK)
/* SDID Bit Fields */
#define SIM_SDID_PINID_MASK 0xFu
#define SIM_SDID_PINID_SHIFT 0
#define SIM_SDID_PINID_WIDTH 4
#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
#define SIM_SDID_FAMID_MASK 0x70u
#define SIM_SDID_FAMID_SHIFT 4
#define SIM_SDID_FAMID_WIDTH 3
#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
#define SIM_SDID_DIEID_MASK 0xF80u
#define SIM_SDID_DIEID_SHIFT 7
#define SIM_SDID_DIEID_WIDTH 5
#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
#define SIM_SDID_REVID_MASK 0xF000u
#define SIM_SDID_REVID_SHIFT 12
#define SIM_SDID_REVID_WIDTH 4
#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
#define SIM_SDID_SERIESID_MASK 0xF00000u
#define SIM_SDID_SERIESID_SHIFT 20
#define SIM_SDID_SERIESID_WIDTH 4
#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
#define SIM_SDID_SUBFAMID_MASK 0xF000000u
#define SIM_SDID_SUBFAMID_SHIFT 24
#define SIM_SDID_SUBFAMID_WIDTH 4
#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
#define SIM_SDID_FAMILYID_MASK 0xF0000000u
#define SIM_SDID_FAMILYID_SHIFT 28
#define SIM_SDID_FAMILYID_WIDTH 4
#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
/* SCGC4 Bit Fields */
#define SIM_SCGC4_EWM_MASK 0x2u
#define SIM_SCGC4_EWM_SHIFT 1
#define SIM_SCGC4_EWM_WIDTH 1
#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
#define SIM_SCGC4_LPI2C0_MASK 0x40u
#define SIM_SCGC4_LPI2C0_SHIFT 6
#define SIM_SCGC4_LPI2C0_WIDTH 1
#define SIM_SCGC4_LPI2C0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_LPI2C0_SHIFT))&SIM_SCGC4_LPI2C0_MASK)
#define SIM_SCGC4_LPI2C1_MASK 0x80u
#define SIM_SCGC4_LPI2C1_SHIFT 7
#define SIM_SCGC4_LPI2C1_WIDTH 1
#define SIM_SCGC4_LPI2C1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_LPI2C1_SHIFT))&SIM_SCGC4_LPI2C1_MASK)
#define SIM_SCGC4_UART0_MASK 0x400u
#define SIM_SCGC4_UART0_SHIFT 10
#define SIM_SCGC4_UART0_WIDTH 1
#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
#define SIM_SCGC4_UART1_MASK 0x800u
#define SIM_SCGC4_UART1_SHIFT 11
#define SIM_SCGC4_UART1_WIDTH 1
#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
#define SIM_SCGC4_UART2_MASK 0x1000u
#define SIM_SCGC4_UART2_SHIFT 12
#define SIM_SCGC4_UART2_WIDTH 1
#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
#define SIM_SCGC4_USBOTG_MASK 0x40000u
#define SIM_SCGC4_USBOTG_SHIFT 18
#define SIM_SCGC4_USBOTG_WIDTH 1
#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
#define SIM_SCGC4_CMP_MASK 0x80000u
#define SIM_SCGC4_CMP_SHIFT 19
#define SIM_SCGC4_CMP_WIDTH 1
#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
/* SCGC5 Bit Fields */
#define SIM_SCGC5_LPTMR_MASK 0x1u
#define SIM_SCGC5_LPTMR_SHIFT 0
#define SIM_SCGC5_LPTMR_WIDTH 1
#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
#define SIM_SCGC5_PORTA_MASK 0x200u
#define SIM_SCGC5_PORTA_SHIFT 9
#define SIM_SCGC5_PORTA_WIDTH 1
#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
#define SIM_SCGC5_PORTB_MASK 0x400u
#define SIM_SCGC5_PORTB_SHIFT 10
#define SIM_SCGC5_PORTB_WIDTH 1
#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
#define SIM_SCGC5_PORTC_MASK 0x800u
#define SIM_SCGC5_PORTC_SHIFT 11
#define SIM_SCGC5_PORTC_WIDTH 1
#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
#define SIM_SCGC5_PORTD_MASK 0x1000u
#define SIM_SCGC5_PORTD_SHIFT 12
#define SIM_SCGC5_PORTD_WIDTH 1
#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
#define SIM_SCGC5_PORTE_MASK 0x2000u
#define SIM_SCGC5_PORTE_SHIFT 13
#define SIM_SCGC5_PORTE_WIDTH 1
#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
#define SIM_SCGC5_FLEXIO_MASK 0x80000000u
#define SIM_SCGC5_FLEXIO_SHIFT 31
#define SIM_SCGC5_FLEXIO_WIDTH 1
#define SIM_SCGC5_FLEXIO(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_FLEXIO_SHIFT))&SIM_SCGC5_FLEXIO_MASK)
/* SCGC6 Bit Fields */
#define SIM_SCGC6_FTF_MASK 0x1u
#define SIM_SCGC6_FTF_SHIFT 0
#define SIM_SCGC6_FTF_WIDTH 1
#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
#define SIM_SCGC6_DMAMUX_MASK 0x2u
#define SIM_SCGC6_DMAMUX_SHIFT 1
#define SIM_SCGC6_DMAMUX_WIDTH 1
#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
#define SIM_SCGC6_FLEXCAN0_SHIFT 4
#define SIM_SCGC6_FLEXCAN0_WIDTH 1
#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
#define SIM_SCGC6_FLEXCAN1_MASK 0x20u
#define SIM_SCGC6_FLEXCAN1_SHIFT 5
#define SIM_SCGC6_FLEXCAN1_WIDTH 1
#define SIM_SCGC6_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN1_SHIFT))&SIM_SCGC6_FLEXCAN1_MASK)
#define SIM_SCGC6_RNGA_MASK 0x200u
#define SIM_SCGC6_RNGA_SHIFT 9
#define SIM_SCGC6_RNGA_WIDTH 1
#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
#define SIM_SCGC6_LPUART0_MASK 0x400u
#define SIM_SCGC6_LPUART0_SHIFT 10
#define SIM_SCGC6_LPUART0_WIDTH 1
#define SIM_SCGC6_LPUART0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_LPUART0_SHIFT))&SIM_SCGC6_LPUART0_MASK)
#define SIM_SCGC6_SPI0_MASK 0x1000u
#define SIM_SCGC6_SPI0_SHIFT 12
#define SIM_SCGC6_SPI0_WIDTH 1
#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
#define SIM_SCGC6_SPI1_MASK 0x2000u
#define SIM_SCGC6_SPI1_SHIFT 13
#define SIM_SCGC6_SPI1_WIDTH 1
#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
#define SIM_SCGC6_I2S0_MASK 0x8000u
#define SIM_SCGC6_I2S0_SHIFT 15
#define SIM_SCGC6_I2S0_WIDTH 1
#define SIM_SCGC6_I2S0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S0_SHIFT))&SIM_SCGC6_I2S0_MASK)
#define SIM_SCGC6_I2S1_MASK 0x10000u
#define SIM_SCGC6_I2S1_SHIFT 16
#define SIM_SCGC6_I2S1_WIDTH 1
#define SIM_SCGC6_I2S1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S1_SHIFT))&SIM_SCGC6_I2S1_MASK)
#define SIM_SCGC6_CRC_MASK 0x40000u
#define SIM_SCGC6_CRC_SHIFT 18
#define SIM_SCGC6_CRC_WIDTH 1
#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
#define SIM_SCGC6_PDB_MASK 0x400000u
#define SIM_SCGC6_PDB_SHIFT 22
#define SIM_SCGC6_PDB_WIDTH 1
#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
#define SIM_SCGC6_PIT_MASK 0x800000u
#define SIM_SCGC6_PIT_SHIFT 23
#define SIM_SCGC6_PIT_WIDTH 1
#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
#define SIM_SCGC6_TPM0_MASK 0x1000000u
#define SIM_SCGC6_TPM0_SHIFT 24
#define SIM_SCGC6_TPM0_WIDTH 1
#define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM0_SHIFT))&SIM_SCGC6_TPM0_MASK)
#define SIM_SCGC6_TPM1_MASK 0x2000000u
#define SIM_SCGC6_TPM1_SHIFT 25
#define SIM_SCGC6_TPM1_WIDTH 1
#define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM1_SHIFT))&SIM_SCGC6_TPM1_MASK)
#define SIM_SCGC6_TPM2_MASK 0x4000000u
#define SIM_SCGC6_TPM2_SHIFT 26
#define SIM_SCGC6_TPM2_WIDTH 1
#define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM2_SHIFT))&SIM_SCGC6_TPM2_MASK)
#define SIM_SCGC6_ADC0_MASK 0x8000000u
#define SIM_SCGC6_ADC0_SHIFT 27
#define SIM_SCGC6_ADC0_WIDTH 1
#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
#define SIM_SCGC6_RTC_MASK 0x20000000u
#define SIM_SCGC6_RTC_SHIFT 29
#define SIM_SCGC6_RTC_WIDTH 1
#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
#define SIM_SCGC6_DAC0_MASK 0x80000000u
#define SIM_SCGC6_DAC0_SHIFT 31
#define SIM_SCGC6_DAC0_WIDTH 1
#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
/* SCGC7 Bit Fields */
#define SIM_SCGC7_DMA_MASK 0x2u
#define SIM_SCGC7_DMA_SHIFT 1
#define SIM_SCGC7_DMA_WIDTH 1
#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
/* CLKDIV1 Bit Fields */
#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
#define SIM_CLKDIV1_OUTDIV4_WIDTH 4
#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
#define SIM_CLKDIV1_OUTDIV2_WIDTH 4
#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
#define SIM_CLKDIV1_OUTDIV1_WIDTH 4
#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
/* CLKDIV2 Bit Fields */
#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
#define SIM_CLKDIV2_USBFRAC_SHIFT 0
#define SIM_CLKDIV2_USBFRAC_WIDTH 1
#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
#define SIM_CLKDIV2_USBDIV_MASK 0xEu
#define SIM_CLKDIV2_USBDIV_SHIFT 1
#define SIM_CLKDIV2_USBDIV_WIDTH 3
#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
/* FCFG1 Bit Fields */
#define SIM_FCFG1_FLASHDIS_MASK 0x1u
#define SIM_FCFG1_FLASHDIS_SHIFT 0
#define SIM_FCFG1_FLASHDIS_WIDTH 1
#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
#define SIM_FCFG1_FLASHDOZE_SHIFT 1
#define SIM_FCFG1_FLASHDOZE_WIDTH 1
#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
#define SIM_FCFG1_PFSIZE_SHIFT 24
#define SIM_FCFG1_PFSIZE_WIDTH 4
#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
/* FCFG2 Bit Fields */
#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
#define SIM_FCFG2_MAXADDR0_SHIFT 24
#define SIM_FCFG2_MAXADDR0_WIDTH 7
#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
/* UIDH Bit Fields */
#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
#define SIM_UIDH_UID_SHIFT 0
#define SIM_UIDH_UID_WIDTH 32
#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
/* UIDMH Bit Fields */
#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
#define SIM_UIDMH_UID_SHIFT 0
#define SIM_UIDMH_UID_WIDTH 32
#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
/* UIDML Bit Fields */
#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
#define SIM_UIDML_UID_SHIFT 0
#define SIM_UIDML_UID_WIDTH 32
#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
/* UIDL Bit Fields */
#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
#define SIM_UIDL_UID_SHIFT 0
#define SIM_UIDL_UID_WIDTH 32
#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
/* CLKDIV3 Bit Fields */
#define SIM_CLKDIV3_PLLFLLFRAC_MASK 0x1u
#define SIM_CLKDIV3_PLLFLLFRAC_SHIFT 0
#define SIM_CLKDIV3_PLLFLLFRAC_WIDTH 1
#define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV3_PLLFLLFRAC_SHIFT))&SIM_CLKDIV3_PLLFLLFRAC_MASK)
#define SIM_CLKDIV3_PLLFLLDIV_MASK 0xEu
#define SIM_CLKDIV3_PLLFLLDIV_SHIFT 1
#define SIM_CLKDIV3_PLLFLLDIV_WIDTH 3
#define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV3_PLLFLLDIV_SHIFT))&SIM_CLKDIV3_PLLFLLDIV_MASK)
/* MISCCTL Bit Fields */
#define SIM_MISCCTL_UARTSELONUSB_MASK 0x3u
#define SIM_MISCCTL_UARTSELONUSB_SHIFT 0
#define SIM_MISCCTL_UARTSELONUSB_WIDTH 2
#define SIM_MISCCTL_UARTSELONUSB(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCCTL_UARTSELONUSB_SHIFT))&SIM_MISCCTL_UARTSELONUSB_MASK)
#define SIM_MISCCTL_FlexIOS0_MASK 0x4u
#define SIM_MISCCTL_FlexIOS0_SHIFT 2
#define SIM_MISCCTL_FlexIOS0_WIDTH 1
#define SIM_MISCCTL_FlexIOS0(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCCTL_FlexIOS0_SHIFT))&SIM_MISCCTL_FlexIOS0_MASK)
/*!
* @}
*/ /* end of group SIM_Register_Masks */
/* SIM - Peripheral instance base addresses */
/** Peripheral SIM base address */
#define SIM_BASE (0x40047000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
#define SIM_BASE_PTR (SIM)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS { SIM_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS { SIM }
/* ----------------------------------------------------------------------------
-- SIM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
* @{
*/
/* SIM - Register instance definitions */
/* SIM */
#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
#define SIM_SOPT9 SIM_SOPT9_REG(SIM)
#define SIM_SDID SIM_SDID_REG(SIM)
#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
#define SIM_UIDH SIM_UIDH_REG(SIM)
#define SIM_UIDMH SIM_UIDMH_REG(SIM)
#define SIM_UIDML SIM_UIDML_REG(SIM)
#define SIM_UIDL SIM_UIDL_REG(SIM)
#define SIM_CLKDIV3 SIM_CLKDIV3_REG(SIM)
#define SIM_MISCCTL SIM_MISCCTL_REG(SIM)
/*!
* @}
*/ /* end of group SIM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
* @{
*/
/** SMC - Register Layout Typedef */
typedef struct {
__IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
__IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
__IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
__I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
} SMC_Type, *SMC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
* @{
*/
/* SMC - Register accessors */
#define SMC_PMPROT_REG(base) ((base)->PMPROT)
#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
/*!
* @}
*/ /* end of group SMC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Masks SMC Register Masks
* @{
*/
/* PMPROT Bit Fields */
#define SMC_PMPROT_AVLLS_MASK 0x2u
#define SMC_PMPROT_AVLLS_SHIFT 1
#define SMC_PMPROT_AVLLS_WIDTH 1
#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
#define SMC_PMPROT_ALLS_MASK 0x8u
#define SMC_PMPROT_ALLS_SHIFT 3
#define SMC_PMPROT_ALLS_WIDTH 1
#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
#define SMC_PMPROT_AVLP_MASK 0x20u
#define SMC_PMPROT_AVLP_SHIFT 5
#define SMC_PMPROT_AVLP_WIDTH 1
#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
#define SMC_PMPROT_AHSRUN_MASK 0x80u
#define SMC_PMPROT_AHSRUN_SHIFT 7
#define SMC_PMPROT_AHSRUN_WIDTH 1
#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AHSRUN_SHIFT))&SMC_PMPROT_AHSRUN_MASK)
/* PMCTRL Bit Fields */
#define SMC_PMCTRL_STOPM_MASK 0x7u
#define SMC_PMCTRL_STOPM_SHIFT 0
#define SMC_PMCTRL_STOPM_WIDTH 3
#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
#define SMC_PMCTRL_STOPA_MASK 0x8u
#define SMC_PMCTRL_STOPA_SHIFT 3
#define SMC_PMCTRL_STOPA_WIDTH 1
#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
#define SMC_PMCTRL_RUNM_MASK 0x60u
#define SMC_PMCTRL_RUNM_SHIFT 5
#define SMC_PMCTRL_RUNM_WIDTH 2
#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
/* STOPCTRL Bit Fields */
#define SMC_STOPCTRL_LLSM_MASK 0x7u
#define SMC_STOPCTRL_LLSM_SHIFT 0
#define SMC_STOPCTRL_LLSM_WIDTH 3
#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
#define SMC_STOPCTRL_LPOPO_MASK 0x8u
#define SMC_STOPCTRL_LPOPO_SHIFT 3
#define SMC_STOPCTRL_LPOPO_WIDTH 1
#define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LPOPO_SHIFT))&SMC_STOPCTRL_LPOPO_MASK)
#define SMC_STOPCTRL_PORPO_MASK 0x20u
#define SMC_STOPCTRL_PORPO_SHIFT 5
#define SMC_STOPCTRL_PORPO_WIDTH 1
#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PORPO_SHIFT))&SMC_STOPCTRL_PORPO_MASK)
#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
#define SMC_STOPCTRL_PSTOPO_SHIFT 6
#define SMC_STOPCTRL_PSTOPO_WIDTH 2
#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
/* PMSTAT Bit Fields */
#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
#define SMC_PMSTAT_PMSTAT_SHIFT 0
#define SMC_PMSTAT_PMSTAT_WIDTH 8
#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
/*!
* @}
*/ /* end of group SMC_Register_Masks */
/* SMC - Peripheral instance base addresses */
/** Peripheral SMC base address */
#define SMC_BASE (0x4007E000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
#define SMC_BASE_PTR (SMC)
/** Array initializer of SMC peripheral base addresses */
#define SMC_BASE_ADDRS { SMC_BASE }
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASE_PTRS { SMC }
/* ----------------------------------------------------------------------------
-- SMC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
* @{
*/
/* SMC - Register instance definitions */
/* SMC */
#define SMC_PMPROT SMC_PMPROT_REG(SMC)
#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
/*!
* @}
*/ /* end of group SMC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
* @{
*/
/** SPI - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
uint8_t RESERVED_0[4];
__IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
union { /* offset: 0xC */
__IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
__IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
};
uint8_t RESERVED_1[24];
__IO uint32_t SR; /**< Status Register, offset: 0x2C */
__IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
union { /* offset: 0x34 */
__IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
__IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
};
__I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
__I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
__I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
__I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
__I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
uint8_t RESERVED_2[48];
__I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
__I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
__I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
__I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
} SPI_Type, *SPI_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SPI - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
* @{
*/
/* SPI - Register accessors */
#define SPI_MCR_REG(base) ((base)->MCR)
#define SPI_TCR_REG(base) ((base)->TCR)
#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
#define SPI_CTAR_COUNT 2
#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
#define SPI_CTAR_SLAVE_COUNT 1
#define SPI_SR_REG(base) ((base)->SR)
#define SPI_RSER_REG(base) ((base)->RSER)
#define SPI_PUSHR_REG(base) ((base)->PUSHR)
#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
#define SPI_POPR_REG(base) ((base)->POPR)
#define SPI_TXFR0_REG(base) ((base)->TXFR0)
#define SPI_TXFR1_REG(base) ((base)->TXFR1)
#define SPI_TXFR2_REG(base) ((base)->TXFR2)
#define SPI_TXFR3_REG(base) ((base)->TXFR3)
#define SPI_RXFR0_REG(base) ((base)->RXFR0)
#define SPI_RXFR1_REG(base) ((base)->RXFR1)
#define SPI_RXFR2_REG(base) ((base)->RXFR2)
#define SPI_RXFR3_REG(base) ((base)->RXFR3)
/*!
* @}
*/ /* end of group SPI_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Register_Masks SPI Register Masks
* @{
*/
/* MCR Bit Fields */
#define SPI_MCR_HALT_MASK 0x1u
#define SPI_MCR_HALT_SHIFT 0
#define SPI_MCR_HALT_WIDTH 1
#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
#define SPI_MCR_SMPL_PT_MASK 0x300u
#define SPI_MCR_SMPL_PT_SHIFT 8
#define SPI_MCR_SMPL_PT_WIDTH 2
#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
#define SPI_MCR_CLR_RXF_MASK 0x400u
#define SPI_MCR_CLR_RXF_SHIFT 10
#define SPI_MCR_CLR_RXF_WIDTH 1
#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
#define SPI_MCR_CLR_TXF_MASK 0x800u
#define SPI_MCR_CLR_TXF_SHIFT 11
#define SPI_MCR_CLR_TXF_WIDTH 1
#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
#define SPI_MCR_DIS_RXF_MASK 0x1000u
#define SPI_MCR_DIS_RXF_SHIFT 12
#define SPI_MCR_DIS_RXF_WIDTH 1
#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
#define SPI_MCR_DIS_TXF_MASK 0x2000u
#define SPI_MCR_DIS_TXF_SHIFT 13
#define SPI_MCR_DIS_TXF_WIDTH 1
#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
#define SPI_MCR_MDIS_MASK 0x4000u
#define SPI_MCR_MDIS_SHIFT 14
#define SPI_MCR_MDIS_WIDTH 1
#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
#define SPI_MCR_DOZE_MASK 0x8000u
#define SPI_MCR_DOZE_SHIFT 15
#define SPI_MCR_DOZE_WIDTH 1
#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
#define SPI_MCR_PCSIS_MASK 0x3F0000u
#define SPI_MCR_PCSIS_SHIFT 16
#define SPI_MCR_PCSIS_WIDTH 6
#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
#define SPI_MCR_ROOE_MASK 0x1000000u
#define SPI_MCR_ROOE_SHIFT 24
#define SPI_MCR_ROOE_WIDTH 1
#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
#define SPI_MCR_PCSSE_MASK 0x2000000u
#define SPI_MCR_PCSSE_SHIFT 25
#define SPI_MCR_PCSSE_WIDTH 1
#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
#define SPI_MCR_MTFE_MASK 0x4000000u
#define SPI_MCR_MTFE_SHIFT 26
#define SPI_MCR_MTFE_WIDTH 1
#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
#define SPI_MCR_FRZ_MASK 0x8000000u
#define SPI_MCR_FRZ_SHIFT 27
#define SPI_MCR_FRZ_WIDTH 1
#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
#define SPI_MCR_DCONF_MASK 0x30000000u
#define SPI_MCR_DCONF_SHIFT 28
#define SPI_MCR_DCONF_WIDTH 2
#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
#define SPI_MCR_CONT_SCKE_SHIFT 30
#define SPI_MCR_CONT_SCKE_WIDTH 1
#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
#define SPI_MCR_MSTR_MASK 0x80000000u
#define SPI_MCR_MSTR_SHIFT 31
#define SPI_MCR_MSTR_WIDTH 1
#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
/* TCR Bit Fields */
#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
#define SPI_TCR_SPI_TCNT_SHIFT 16
#define SPI_TCR_SPI_TCNT_WIDTH 16
#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
/* CTAR Bit Fields */
#define SPI_CTAR_BR_MASK 0xFu
#define SPI_CTAR_BR_SHIFT 0
#define SPI_CTAR_BR_WIDTH 4
#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
#define SPI_CTAR_DT_MASK 0xF0u
#define SPI_CTAR_DT_SHIFT 4
#define SPI_CTAR_DT_WIDTH 4
#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
#define SPI_CTAR_ASC_MASK 0xF00u
#define SPI_CTAR_ASC_SHIFT 8
#define SPI_CTAR_ASC_WIDTH 4
#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
#define SPI_CTAR_CSSCK_MASK 0xF000u
#define SPI_CTAR_CSSCK_SHIFT 12
#define SPI_CTAR_CSSCK_WIDTH 4
#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
#define SPI_CTAR_PBR_MASK 0x30000u
#define SPI_CTAR_PBR_SHIFT 16
#define SPI_CTAR_PBR_WIDTH 2
#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
#define SPI_CTAR_PDT_MASK 0xC0000u
#define SPI_CTAR_PDT_SHIFT 18
#define SPI_CTAR_PDT_WIDTH 2
#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
#define SPI_CTAR_PASC_MASK 0x300000u
#define SPI_CTAR_PASC_SHIFT 20
#define SPI_CTAR_PASC_WIDTH 2
#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
#define SPI_CTAR_PCSSCK_MASK 0xC00000u
#define SPI_CTAR_PCSSCK_SHIFT 22
#define SPI_CTAR_PCSSCK_WIDTH 2
#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
#define SPI_CTAR_LSBFE_MASK 0x1000000u
#define SPI_CTAR_LSBFE_SHIFT 24
#define SPI_CTAR_LSBFE_WIDTH 1
#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
#define SPI_CTAR_CPHA_MASK 0x2000000u
#define SPI_CTAR_CPHA_SHIFT 25
#define SPI_CTAR_CPHA_WIDTH 1
#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
#define SPI_CTAR_CPOL_MASK 0x4000000u
#define SPI_CTAR_CPOL_SHIFT 26
#define SPI_CTAR_CPOL_WIDTH 1
#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
#define SPI_CTAR_FMSZ_MASK 0x78000000u
#define SPI_CTAR_FMSZ_SHIFT 27
#define SPI_CTAR_FMSZ_WIDTH 4
#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
#define SPI_CTAR_DBR_MASK 0x80000000u
#define SPI_CTAR_DBR_SHIFT 31
#define SPI_CTAR_DBR_WIDTH 1
#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
/* CTAR_SLAVE Bit Fields */
#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
#define SPI_CTAR_SLAVE_CPHA_WIDTH 1
#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
#define SPI_CTAR_SLAVE_CPOL_WIDTH 1
#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
#define SPI_CTAR_SLAVE_FMSZ_MASK 0x78000000u
#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
#define SPI_CTAR_SLAVE_FMSZ_WIDTH 4
#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
/* SR Bit Fields */
#define SPI_SR_POPNXTPTR_MASK 0xFu
#define SPI_SR_POPNXTPTR_SHIFT 0
#define SPI_SR_POPNXTPTR_WIDTH 4
#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
#define SPI_SR_RXCTR_MASK 0xF0u
#define SPI_SR_RXCTR_SHIFT 4
#define SPI_SR_RXCTR_WIDTH 4
#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
#define SPI_SR_TXNXTPTR_MASK 0xF00u
#define SPI_SR_TXNXTPTR_SHIFT 8
#define SPI_SR_TXNXTPTR_WIDTH 4
#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
#define SPI_SR_TXCTR_MASK 0xF000u
#define SPI_SR_TXCTR_SHIFT 12
#define SPI_SR_TXCTR_WIDTH 4
#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
#define SPI_SR_RFDF_MASK 0x20000u
#define SPI_SR_RFDF_SHIFT 17
#define SPI_SR_RFDF_WIDTH 1
#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
#define SPI_SR_RFOF_MASK 0x80000u
#define SPI_SR_RFOF_SHIFT 19
#define SPI_SR_RFOF_WIDTH 1
#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
#define SPI_SR_TFFF_MASK 0x2000000u
#define SPI_SR_TFFF_SHIFT 25
#define SPI_SR_TFFF_WIDTH 1
#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
#define SPI_SR_TFUF_MASK 0x8000000u
#define SPI_SR_TFUF_SHIFT 27
#define SPI_SR_TFUF_WIDTH 1
#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
#define SPI_SR_EOQF_MASK 0x10000000u
#define SPI_SR_EOQF_SHIFT 28
#define SPI_SR_EOQF_WIDTH 1
#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
#define SPI_SR_TXRXS_MASK 0x40000000u
#define SPI_SR_TXRXS_SHIFT 30
#define SPI_SR_TXRXS_WIDTH 1
#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
#define SPI_SR_TCF_MASK 0x80000000u
#define SPI_SR_TCF_SHIFT 31
#define SPI_SR_TCF_WIDTH 1
#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
/* RSER Bit Fields */
#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
#define SPI_RSER_RFDF_DIRS_SHIFT 16
#define SPI_RSER_RFDF_DIRS_WIDTH 1
#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
#define SPI_RSER_RFDF_RE_MASK 0x20000u
#define SPI_RSER_RFDF_RE_SHIFT 17
#define SPI_RSER_RFDF_RE_WIDTH 1
#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
#define SPI_RSER_RFOF_RE_MASK 0x80000u
#define SPI_RSER_RFOF_RE_SHIFT 19
#define SPI_RSER_RFOF_RE_WIDTH 1
#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
#define SPI_RSER_TFFF_DIRS_SHIFT 24
#define SPI_RSER_TFFF_DIRS_WIDTH 1
#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
#define SPI_RSER_TFFF_RE_MASK 0x2000000u
#define SPI_RSER_TFFF_RE_SHIFT 25
#define SPI_RSER_TFFF_RE_WIDTH 1
#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
#define SPI_RSER_TFUF_RE_MASK 0x8000000u
#define SPI_RSER_TFUF_RE_SHIFT 27
#define SPI_RSER_TFUF_RE_WIDTH 1
#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
#define SPI_RSER_EOQF_RE_MASK 0x10000000u
#define SPI_RSER_EOQF_RE_SHIFT 28
#define SPI_RSER_EOQF_RE_WIDTH 1
#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
#define SPI_RSER_TCF_RE_MASK 0x80000000u
#define SPI_RSER_TCF_RE_SHIFT 31
#define SPI_RSER_TCF_RE_WIDTH 1
#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
/* PUSHR Bit Fields */
#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
#define SPI_PUSHR_TXDATA_SHIFT 0
#define SPI_PUSHR_TXDATA_WIDTH 16
#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
#define SPI_PUSHR_PCS_MASK 0x3F0000u
#define SPI_PUSHR_PCS_SHIFT 16
#define SPI_PUSHR_PCS_WIDTH 6
#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
#define SPI_PUSHR_CTCNT_MASK 0x4000000u
#define SPI_PUSHR_CTCNT_SHIFT 26
#define SPI_PUSHR_CTCNT_WIDTH 1
#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
#define SPI_PUSHR_EOQ_MASK 0x8000000u
#define SPI_PUSHR_EOQ_SHIFT 27
#define SPI_PUSHR_EOQ_WIDTH 1
#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
#define SPI_PUSHR_CTAS_MASK 0x70000000u
#define SPI_PUSHR_CTAS_SHIFT 28
#define SPI_PUSHR_CTAS_WIDTH 3
#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
#define SPI_PUSHR_CONT_MASK 0x80000000u
#define SPI_PUSHR_CONT_SHIFT 31
#define SPI_PUSHR_CONT_WIDTH 1
#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
/* PUSHR_SLAVE Bit Fields */
#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFu
#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
#define SPI_PUSHR_SLAVE_TXDATA_WIDTH 16
#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
/* POPR Bit Fields */
#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
#define SPI_POPR_RXDATA_SHIFT 0
#define SPI_POPR_RXDATA_WIDTH 32
#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
/* TXFR0 Bit Fields */
#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
#define SPI_TXFR0_TXDATA_SHIFT 0
#define SPI_TXFR0_TXDATA_WIDTH 16
#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR0_TXCMD_TXDATA_WIDTH 16
#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
/* TXFR1 Bit Fields */
#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
#define SPI_TXFR1_TXDATA_SHIFT 0
#define SPI_TXFR1_TXDATA_WIDTH 16
#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR1_TXCMD_TXDATA_WIDTH 16
#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
/* TXFR2 Bit Fields */
#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
#define SPI_TXFR2_TXDATA_SHIFT 0
#define SPI_TXFR2_TXDATA_WIDTH 16
#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR2_TXCMD_TXDATA_WIDTH 16
#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
/* TXFR3 Bit Fields */
#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
#define SPI_TXFR3_TXDATA_SHIFT 0
#define SPI_TXFR3_TXDATA_WIDTH 16
#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR3_TXCMD_TXDATA_WIDTH 16
#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
/* RXFR0 Bit Fields */
#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR0_RXDATA_SHIFT 0
#define SPI_RXFR0_RXDATA_WIDTH 32
#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
/* RXFR1 Bit Fields */
#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR1_RXDATA_SHIFT 0
#define SPI_RXFR1_RXDATA_WIDTH 32
#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
/* RXFR2 Bit Fields */
#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR2_RXDATA_SHIFT 0
#define SPI_RXFR2_RXDATA_WIDTH 32
#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
/* RXFR3 Bit Fields */
#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR3_RXDATA_SHIFT 0
#define SPI_RXFR3_RXDATA_WIDTH 32
#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
/*!
* @}
*/ /* end of group SPI_Register_Masks */
/* SPI - Peripheral instance base addresses */
/** Peripheral SPI0 base address */
#define SPI0_BASE (0x4002C000u)
/** Peripheral SPI0 base pointer */
#define SPI0 ((SPI_Type *)SPI0_BASE)
#define SPI0_BASE_PTR (SPI0)
/** Peripheral SPI1 base address */
#define SPI1_BASE (0x4002D000u)
/** Peripheral SPI1 base pointer */
#define SPI1 ((SPI_Type *)SPI1_BASE)
#define SPI1_BASE_PTR (SPI1)
/** Array initializer of SPI peripheral base addresses */
#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
/** Array initializer of SPI peripheral base pointers */
#define SPI_BASE_PTRS { SPI0, SPI1 }
/* ----------------------------------------------------------------------------
-- SPI - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
* @{
*/
/* SPI - Register instance definitions */
/* SPI0 */
#define SPI0_MCR SPI_MCR_REG(SPI0)
#define SPI0_TCR SPI_TCR_REG(SPI0)
#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
#define SPI0_SR SPI_SR_REG(SPI0)
#define SPI0_RSER SPI_RSER_REG(SPI0)
#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
#define SPI0_POPR SPI_POPR_REG(SPI0)
#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
/* SPI1 */
#define SPI1_MCR SPI_MCR_REG(SPI1)
#define SPI1_TCR SPI_TCR_REG(SPI1)
#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
#define SPI1_SR SPI_SR_REG(SPI1)
#define SPI1_RSER SPI_RSER_REG(SPI1)
#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
#define SPI1_POPR SPI_POPR_REG(SPI1)
#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
/* SPI - Register array accessors */
#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
/*!
* @}
*/ /* end of group SPI_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group SPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TPM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
* @{
*/
/** TPM - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t GLOBAL; /**< TPM Global Register, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t SC; /**< Status and Control, offset: 0x10 */
__IO uint32_t CNT; /**< Counter, offset: 0x14 */
__IO uint32_t MOD; /**< Modulo, offset: 0x18 */
__IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */
struct { /* offset: 0x20, array step: 0x8 */
__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
} CONTROLS[6];
uint8_t RESERVED_1[20];
__IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
uint8_t RESERVED_2[4];
__IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */
__IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
uint8_t RESERVED_3[4];
__IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
uint8_t RESERVED_4[4];
__IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
__IO uint32_t CONF; /**< Configuration, offset: 0x84 */
} TPM_Type, *TPM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TPM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
* @{
*/
/* TPM - Register accessors */
#define TPM_VERID_REG(base) ((base)->VERID)
#define TPM_PARAM_REG(base) ((base)->PARAM)
#define TPM_GLOBAL_REG(base) ((base)->GLOBAL)
#define TPM_SC_REG(base) ((base)->SC)
#define TPM_CNT_REG(base) ((base)->CNT)
#define TPM_MOD_REG(base) ((base)->MOD)
#define TPM_STATUS_REG(base) ((base)->STATUS)
#define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
#define TPM_CnSC_COUNT 6
#define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
#define TPM_CnV_COUNT 6
#define TPM_COMBINE_REG(base) ((base)->COMBINE)
#define TPM_TRIG_REG(base) ((base)->TRIG)
#define TPM_POL_REG(base) ((base)->POL)
#define TPM_FILTER_REG(base) ((base)->FILTER)
#define TPM_QDCTRL_REG(base) ((base)->QDCTRL)
#define TPM_CONF_REG(base) ((base)->CONF)
/*!
* @}
*/ /* end of group TPM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TPM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Register_Masks TPM Register Masks
* @{
*/
/* VERID Bit Fields */
#define TPM_VERID_FEATURE_MASK 0xFFFFu
#define TPM_VERID_FEATURE_SHIFT 0
#define TPM_VERID_FEATURE_WIDTH 16
#define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<TPM_VERID_FEATURE_SHIFT))&TPM_VERID_FEATURE_MASK)
#define TPM_VERID_MINOR_MASK 0xFF0000u
#define TPM_VERID_MINOR_SHIFT 16
#define TPM_VERID_MINOR_WIDTH 8
#define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<TPM_VERID_MINOR_SHIFT))&TPM_VERID_MINOR_MASK)
#define TPM_VERID_MAJOR_MASK 0xFF000000u
#define TPM_VERID_MAJOR_SHIFT 24
#define TPM_VERID_MAJOR_WIDTH 8
#define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<TPM_VERID_MAJOR_SHIFT))&TPM_VERID_MAJOR_MASK)
/* PARAM Bit Fields */
#define TPM_PARAM_CHAN_MASK 0xFFu
#define TPM_PARAM_CHAN_SHIFT 0
#define TPM_PARAM_CHAN_WIDTH 8
#define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_CHAN_SHIFT))&TPM_PARAM_CHAN_MASK)
#define TPM_PARAM_TRIG_MASK 0xFF00u
#define TPM_PARAM_TRIG_SHIFT 8
#define TPM_PARAM_TRIG_WIDTH 8
#define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_TRIG_SHIFT))&TPM_PARAM_TRIG_MASK)
#define TPM_PARAM_WIDTH_MASK 0xFF0000u
#define TPM_PARAM_WIDTH_SHIFT 16
#define TPM_PARAM_WIDTH_WIDTH 8
#define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_WIDTH_SHIFT))&TPM_PARAM_WIDTH_MASK)
/* GLOBAL Bit Fields */
#define TPM_GLOBAL_RST_MASK 0x2u
#define TPM_GLOBAL_RST_SHIFT 1
#define TPM_GLOBAL_RST_WIDTH 1
#define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x))<<TPM_GLOBAL_RST_SHIFT))&TPM_GLOBAL_RST_MASK)
/* SC Bit Fields */
#define TPM_SC_PS_MASK 0x7u
#define TPM_SC_PS_SHIFT 0
#define TPM_SC_PS_WIDTH 3
#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
#define TPM_SC_CMOD_MASK 0x18u
#define TPM_SC_CMOD_SHIFT 3
#define TPM_SC_CMOD_WIDTH 2
#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
#define TPM_SC_CPWMS_MASK 0x20u
#define TPM_SC_CPWMS_SHIFT 5
#define TPM_SC_CPWMS_WIDTH 1
#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CPWMS_SHIFT))&TPM_SC_CPWMS_MASK)
#define TPM_SC_TOIE_MASK 0x40u
#define TPM_SC_TOIE_SHIFT 6
#define TPM_SC_TOIE_WIDTH 1
#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOIE_SHIFT))&TPM_SC_TOIE_MASK)
#define TPM_SC_TOF_MASK 0x80u
#define TPM_SC_TOF_SHIFT 7
#define TPM_SC_TOF_WIDTH 1
#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOF_SHIFT))&TPM_SC_TOF_MASK)
#define TPM_SC_DMA_MASK 0x100u
#define TPM_SC_DMA_SHIFT 8
#define TPM_SC_DMA_WIDTH 1
#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_DMA_SHIFT))&TPM_SC_DMA_MASK)
/* CNT Bit Fields */
#define TPM_CNT_COUNT_MASK 0xFFFFu
#define TPM_CNT_COUNT_SHIFT 0
#define TPM_CNT_COUNT_WIDTH 16
#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
/* MOD Bit Fields */
#define TPM_MOD_MOD_MASK 0xFFFFu
#define TPM_MOD_MOD_SHIFT 0
#define TPM_MOD_MOD_WIDTH 16
#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
/* STATUS Bit Fields */
#define TPM_STATUS_CH0F_MASK 0x1u
#define TPM_STATUS_CH0F_SHIFT 0
#define TPM_STATUS_CH0F_WIDTH 1
#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH0F_SHIFT))&TPM_STATUS_CH0F_MASK)
#define TPM_STATUS_CH1F_MASK 0x2u
#define TPM_STATUS_CH1F_SHIFT 1
#define TPM_STATUS_CH1F_WIDTH 1
#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH1F_SHIFT))&TPM_STATUS_CH1F_MASK)
#define TPM_STATUS_CH2F_MASK 0x4u
#define TPM_STATUS_CH2F_SHIFT 2
#define TPM_STATUS_CH2F_WIDTH 1
#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH2F_SHIFT))&TPM_STATUS_CH2F_MASK)
#define TPM_STATUS_CH3F_MASK 0x8u
#define TPM_STATUS_CH3F_SHIFT 3
#define TPM_STATUS_CH3F_WIDTH 1
#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH3F_SHIFT))&TPM_STATUS_CH3F_MASK)
#define TPM_STATUS_CH4F_MASK 0x10u
#define TPM_STATUS_CH4F_SHIFT 4
#define TPM_STATUS_CH4F_WIDTH 1
#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH4F_SHIFT))&TPM_STATUS_CH4F_MASK)
#define TPM_STATUS_CH5F_MASK 0x20u
#define TPM_STATUS_CH5F_SHIFT 5
#define TPM_STATUS_CH5F_WIDTH 1
#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH5F_SHIFT))&TPM_STATUS_CH5F_MASK)
#define TPM_STATUS_TOF_MASK 0x100u
#define TPM_STATUS_TOF_SHIFT 8
#define TPM_STATUS_TOF_WIDTH 1
#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_TOF_SHIFT))&TPM_STATUS_TOF_MASK)
/* CnSC Bit Fields */
#define TPM_CnSC_DMA_MASK 0x1u
#define TPM_CnSC_DMA_SHIFT 0
#define TPM_CnSC_DMA_WIDTH 1
#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_DMA_SHIFT))&TPM_CnSC_DMA_MASK)
#define TPM_CnSC_ELSA_MASK 0x4u
#define TPM_CnSC_ELSA_SHIFT 2
#define TPM_CnSC_ELSA_WIDTH 1
#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSA_SHIFT))&TPM_CnSC_ELSA_MASK)
#define TPM_CnSC_ELSB_MASK 0x8u
#define TPM_CnSC_ELSB_SHIFT 3
#define TPM_CnSC_ELSB_WIDTH 1
#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSB_SHIFT))&TPM_CnSC_ELSB_MASK)
#define TPM_CnSC_MSA_MASK 0x10u
#define TPM_CnSC_MSA_SHIFT 4
#define TPM_CnSC_MSA_WIDTH 1
#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSA_SHIFT))&TPM_CnSC_MSA_MASK)
#define TPM_CnSC_MSB_MASK 0x20u
#define TPM_CnSC_MSB_SHIFT 5
#define TPM_CnSC_MSB_WIDTH 1
#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSB_SHIFT))&TPM_CnSC_MSB_MASK)
#define TPM_CnSC_CHIE_MASK 0x40u
#define TPM_CnSC_CHIE_SHIFT 6
#define TPM_CnSC_CHIE_WIDTH 1
#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHIE_SHIFT))&TPM_CnSC_CHIE_MASK)
#define TPM_CnSC_CHF_MASK 0x80u
#define TPM_CnSC_CHF_SHIFT 7
#define TPM_CnSC_CHF_WIDTH 1
#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHF_SHIFT))&TPM_CnSC_CHF_MASK)
/* CnV Bit Fields */
#define TPM_CnV_VAL_MASK 0xFFFFu
#define TPM_CnV_VAL_SHIFT 0
#define TPM_CnV_VAL_WIDTH 16
#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
/* COMBINE Bit Fields */
#define TPM_COMBINE_COMBINE0_MASK 0x1u
#define TPM_COMBINE_COMBINE0_SHIFT 0
#define TPM_COMBINE_COMBINE0_WIDTH 1
#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE0_SHIFT))&TPM_COMBINE_COMBINE0_MASK)
#define TPM_COMBINE_COMSWAP0_MASK 0x2u
#define TPM_COMBINE_COMSWAP0_SHIFT 1
#define TPM_COMBINE_COMSWAP0_WIDTH 1
#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP0_SHIFT))&TPM_COMBINE_COMSWAP0_MASK)
#define TPM_COMBINE_COMBINE1_MASK 0x100u
#define TPM_COMBINE_COMBINE1_SHIFT 8
#define TPM_COMBINE_COMBINE1_WIDTH 1
#define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE1_SHIFT))&TPM_COMBINE_COMBINE1_MASK)
#define TPM_COMBINE_COMSWAP1_MASK 0x200u
#define TPM_COMBINE_COMSWAP1_SHIFT 9
#define TPM_COMBINE_COMSWAP1_WIDTH 1
#define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP1_SHIFT))&TPM_COMBINE_COMSWAP1_MASK)
#define TPM_COMBINE_COMBINE2_MASK 0x10000u
#define TPM_COMBINE_COMBINE2_SHIFT 16
#define TPM_COMBINE_COMBINE2_WIDTH 1
#define TPM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE2_SHIFT))&TPM_COMBINE_COMBINE2_MASK)
#define TPM_COMBINE_COMSWAP2_MASK 0x20000u
#define TPM_COMBINE_COMSWAP2_SHIFT 17
#define TPM_COMBINE_COMSWAP2_WIDTH 1
#define TPM_COMBINE_COMSWAP2(x) (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP2_SHIFT))&TPM_COMBINE_COMSWAP2_MASK)
/* TRIG Bit Fields */
#define TPM_TRIG_TRIG0_MASK 0x1u
#define TPM_TRIG_TRIG0_SHIFT 0
#define TPM_TRIG_TRIG0_WIDTH 1
#define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG0_SHIFT))&TPM_TRIG_TRIG0_MASK)
#define TPM_TRIG_TRIG1_MASK 0x2u
#define TPM_TRIG_TRIG1_SHIFT 1
#define TPM_TRIG_TRIG1_WIDTH 1
#define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG1_SHIFT))&TPM_TRIG_TRIG1_MASK)
#define TPM_TRIG_TRIG2_MASK 0x4u
#define TPM_TRIG_TRIG2_SHIFT 2
#define TPM_TRIG_TRIG2_WIDTH 1
#define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG2_SHIFT))&TPM_TRIG_TRIG2_MASK)
#define TPM_TRIG_TRIG3_MASK 0x8u
#define TPM_TRIG_TRIG3_SHIFT 3
#define TPM_TRIG_TRIG3_WIDTH 1
#define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG3_SHIFT))&TPM_TRIG_TRIG3_MASK)
#define TPM_TRIG_TRIG4_MASK 0x10u
#define TPM_TRIG_TRIG4_SHIFT 4
#define TPM_TRIG_TRIG4_WIDTH 1
#define TPM_TRIG_TRIG4(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG4_SHIFT))&TPM_TRIG_TRIG4_MASK)
#define TPM_TRIG_TRIG5_MASK 0x20u
#define TPM_TRIG_TRIG5_SHIFT 5
#define TPM_TRIG_TRIG5_WIDTH 1
#define TPM_TRIG_TRIG5(x) (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG5_SHIFT))&TPM_TRIG_TRIG5_MASK)
/* POL Bit Fields */
#define TPM_POL_POL0_MASK 0x1u
#define TPM_POL_POL0_SHIFT 0
#define TPM_POL_POL0_WIDTH 1
#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL0_SHIFT))&TPM_POL_POL0_MASK)
#define TPM_POL_POL1_MASK 0x2u
#define TPM_POL_POL1_SHIFT 1
#define TPM_POL_POL1_WIDTH 1
#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL1_SHIFT))&TPM_POL_POL1_MASK)
#define TPM_POL_POL2_MASK 0x4u
#define TPM_POL_POL2_SHIFT 2
#define TPM_POL_POL2_WIDTH 1
#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL2_SHIFT))&TPM_POL_POL2_MASK)
#define TPM_POL_POL3_MASK 0x8u
#define TPM_POL_POL3_SHIFT 3
#define TPM_POL_POL3_WIDTH 1
#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL3_SHIFT))&TPM_POL_POL3_MASK)
#define TPM_POL_POL4_MASK 0x10u
#define TPM_POL_POL4_SHIFT 4
#define TPM_POL_POL4_WIDTH 1
#define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL4_SHIFT))&TPM_POL_POL4_MASK)
#define TPM_POL_POL5_MASK 0x20u
#define TPM_POL_POL5_SHIFT 5
#define TPM_POL_POL5_WIDTH 1
#define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL5_SHIFT))&TPM_POL_POL5_MASK)
/* FILTER Bit Fields */
#define TPM_FILTER_CH0FVAL_MASK 0xFu
#define TPM_FILTER_CH0FVAL_SHIFT 0
#define TPM_FILTER_CH0FVAL_WIDTH 4
#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH0FVAL_SHIFT))&TPM_FILTER_CH0FVAL_MASK)
#define TPM_FILTER_CH1FVAL_MASK 0xF0u
#define TPM_FILTER_CH1FVAL_SHIFT 4
#define TPM_FILTER_CH1FVAL_WIDTH 4
#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH1FVAL_SHIFT))&TPM_FILTER_CH1FVAL_MASK)
#define TPM_FILTER_CH2FVAL_MASK 0xF00u
#define TPM_FILTER_CH2FVAL_SHIFT 8
#define TPM_FILTER_CH2FVAL_WIDTH 4
#define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH2FVAL_SHIFT))&TPM_FILTER_CH2FVAL_MASK)
#define TPM_FILTER_CH3FVAL_MASK 0xF000u
#define TPM_FILTER_CH3FVAL_SHIFT 12
#define TPM_FILTER_CH3FVAL_WIDTH 4
#define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH3FVAL_SHIFT))&TPM_FILTER_CH3FVAL_MASK)
#define TPM_FILTER_CH4FVAL_MASK 0xF0000u
#define TPM_FILTER_CH4FVAL_SHIFT 16
#define TPM_FILTER_CH4FVAL_WIDTH 4
#define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH4FVAL_SHIFT))&TPM_FILTER_CH4FVAL_MASK)
#define TPM_FILTER_CH5FVAL_MASK 0xF00000u
#define TPM_FILTER_CH5FVAL_SHIFT 20
#define TPM_FILTER_CH5FVAL_WIDTH 4
#define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH5FVAL_SHIFT))&TPM_FILTER_CH5FVAL_MASK)
/* QDCTRL Bit Fields */
#define TPM_QDCTRL_QUADEN_MASK 0x1u
#define TPM_QDCTRL_QUADEN_SHIFT 0
#define TPM_QDCTRL_QUADEN_WIDTH 1
#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADEN_SHIFT))&TPM_QDCTRL_QUADEN_MASK)
#define TPM_QDCTRL_TOFDIR_MASK 0x2u
#define TPM_QDCTRL_TOFDIR_SHIFT 1
#define TPM_QDCTRL_TOFDIR_WIDTH 1
#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_TOFDIR_SHIFT))&TPM_QDCTRL_TOFDIR_MASK)
#define TPM_QDCTRL_QUADIR_MASK 0x4u
#define TPM_QDCTRL_QUADIR_SHIFT 2
#define TPM_QDCTRL_QUADIR_WIDTH 1
#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADIR_SHIFT))&TPM_QDCTRL_QUADIR_MASK)
#define TPM_QDCTRL_QUADMODE_MASK 0x8u
#define TPM_QDCTRL_QUADMODE_SHIFT 3
#define TPM_QDCTRL_QUADMODE_WIDTH 1
#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADMODE_SHIFT))&TPM_QDCTRL_QUADMODE_MASK)
/* CONF Bit Fields */
#define TPM_CONF_DOZEEN_MASK 0x20u
#define TPM_CONF_DOZEEN_SHIFT 5
#define TPM_CONF_DOZEEN_WIDTH 1
#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DOZEEN_SHIFT))&TPM_CONF_DOZEEN_MASK)
#define TPM_CONF_DBGMODE_MASK 0xC0u
#define TPM_CONF_DBGMODE_SHIFT 6
#define TPM_CONF_DBGMODE_WIDTH 2
#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
#define TPM_CONF_GTBSYNC_MASK 0x100u
#define TPM_CONF_GTBSYNC_SHIFT 8
#define TPM_CONF_GTBSYNC_WIDTH 1
#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBSYNC_SHIFT))&TPM_CONF_GTBSYNC_MASK)
#define TPM_CONF_GTBEEN_MASK 0x200u
#define TPM_CONF_GTBEEN_SHIFT 9
#define TPM_CONF_GTBEEN_WIDTH 1
#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBEEN_SHIFT))&TPM_CONF_GTBEEN_MASK)
#define TPM_CONF_CSOT_MASK 0x10000u
#define TPM_CONF_CSOT_SHIFT 16
#define TPM_CONF_CSOT_WIDTH 1
#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOT_SHIFT))&TPM_CONF_CSOT_MASK)
#define TPM_CONF_CSOO_MASK 0x20000u
#define TPM_CONF_CSOO_SHIFT 17
#define TPM_CONF_CSOO_WIDTH 1
#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOO_SHIFT))&TPM_CONF_CSOO_MASK)
#define TPM_CONF_CROT_MASK 0x40000u
#define TPM_CONF_CROT_SHIFT 18
#define TPM_CONF_CROT_WIDTH 1
#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CROT_SHIFT))&TPM_CONF_CROT_MASK)
#define TPM_CONF_CPOT_MASK 0x80000u
#define TPM_CONF_CPOT_SHIFT 19
#define TPM_CONF_CPOT_WIDTH 1
#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CPOT_SHIFT))&TPM_CONF_CPOT_MASK)
#define TPM_CONF_TRGPOL_MASK 0x400000u
#define TPM_CONF_TRGPOL_SHIFT 22
#define TPM_CONF_TRGPOL_WIDTH 1
#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGPOL_SHIFT))&TPM_CONF_TRGPOL_MASK)
#define TPM_CONF_TRGSRC_MASK 0x800000u
#define TPM_CONF_TRGSRC_SHIFT 23
#define TPM_CONF_TRGSRC_WIDTH 1
#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSRC_SHIFT))&TPM_CONF_TRGSRC_MASK)
#define TPM_CONF_TRGSEL_MASK 0xF000000u
#define TPM_CONF_TRGSEL_SHIFT 24
#define TPM_CONF_TRGSEL_WIDTH 4
#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
/*!
* @}
*/ /* end of group TPM_Register_Masks */
/* TPM - Peripheral instance base addresses */
/** Peripheral TPM0 base address */
#define TPM0_BASE (0x40038000u)
/** Peripheral TPM0 base pointer */
#define TPM0 ((TPM_Type *)TPM0_BASE)
#define TPM0_BASE_PTR (TPM0)
/** Peripheral TPM1 base address */
#define TPM1_BASE (0x40039000u)
/** Peripheral TPM1 base pointer */
#define TPM1 ((TPM_Type *)TPM1_BASE)
#define TPM1_BASE_PTR (TPM1)
/** Peripheral TPM2 base address */
#define TPM2_BASE (0x4003A000u)
/** Peripheral TPM2 base pointer */
#define TPM2 ((TPM_Type *)TPM2_BASE)
#define TPM2_BASE_PTR (TPM2)
/** Array initializer of TPM peripheral base addresses */
#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
/** Array initializer of TPM peripheral base pointers */
#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
/* ----------------------------------------------------------------------------
-- TPM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
* @{
*/
/* TPM - Register instance definitions */
/* TPM0 */
#define TPM0_VERID TPM_VERID_REG(TPM0)
#define TPM0_PARAM TPM_PARAM_REG(TPM0)
#define TPM0_GLOBAL TPM_GLOBAL_REG(TPM0)
#define TPM0_SC TPM_SC_REG(TPM0)
#define TPM0_CNT TPM_CNT_REG(TPM0)
#define TPM0_MOD TPM_MOD_REG(TPM0)
#define TPM0_STATUS TPM_STATUS_REG(TPM0)
#define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
#define TPM0_C0V TPM_CnV_REG(TPM0,0)
#define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
#define TPM0_C1V TPM_CnV_REG(TPM0,1)
#define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
#define TPM0_C2V TPM_CnV_REG(TPM0,2)
#define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
#define TPM0_C3V TPM_CnV_REG(TPM0,3)
#define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
#define TPM0_C4V TPM_CnV_REG(TPM0,4)
#define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
#define TPM0_C5V TPM_CnV_REG(TPM0,5)
#define TPM0_COMBINE TPM_COMBINE_REG(TPM0)
#define TPM0_TRIG TPM_TRIG_REG(TPM0)
#define TPM0_POL TPM_POL_REG(TPM0)
#define TPM0_FILTER TPM_FILTER_REG(TPM0)
#define TPM0_QDCTRL TPM_QDCTRL_REG(TPM0)
#define TPM0_CONF TPM_CONF_REG(TPM0)
/* TPM1 */
#define TPM1_VERID TPM_VERID_REG(TPM1)
#define TPM1_PARAM TPM_PARAM_REG(TPM1)
#define TPM1_GLOBAL TPM_GLOBAL_REG(TPM1)
#define TPM1_SC TPM_SC_REG(TPM1)
#define TPM1_CNT TPM_CNT_REG(TPM1)
#define TPM1_MOD TPM_MOD_REG(TPM1)
#define TPM1_STATUS TPM_STATUS_REG(TPM1)
#define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
#define TPM1_C0V TPM_CnV_REG(TPM1,0)
#define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
#define TPM1_C1V TPM_CnV_REG(TPM1,1)
#define TPM1_C2SC TPM_CnSC_REG(TPM1,2)
#define TPM1_C2V TPM_CnV_REG(TPM1,2)
#define TPM1_C3SC TPM_CnSC_REG(TPM1,3)
#define TPM1_C3V TPM_CnV_REG(TPM1,3)
#define TPM1_C4SC TPM_CnSC_REG(TPM1,4)
#define TPM1_C4V TPM_CnV_REG(TPM1,4)
#define TPM1_C5SC TPM_CnSC_REG(TPM1,5)
#define TPM1_C5V TPM_CnV_REG(TPM1,5)
#define TPM1_COMBINE TPM_COMBINE_REG(TPM1)
#define TPM1_TRIG TPM_TRIG_REG(TPM1)
#define TPM1_POL TPM_POL_REG(TPM1)
#define TPM1_FILTER TPM_FILTER_REG(TPM1)
#define TPM1_QDCTRL TPM_QDCTRL_REG(TPM1)
#define TPM1_CONF TPM_CONF_REG(TPM1)
/* TPM2 */
#define TPM2_VERID TPM_VERID_REG(TPM2)
#define TPM2_PARAM TPM_PARAM_REG(TPM2)
#define TPM2_GLOBAL TPM_GLOBAL_REG(TPM2)
#define TPM2_SC TPM_SC_REG(TPM2)
#define TPM2_CNT TPM_CNT_REG(TPM2)
#define TPM2_MOD TPM_MOD_REG(TPM2)
#define TPM2_STATUS TPM_STATUS_REG(TPM2)
#define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
#define TPM2_C0V TPM_CnV_REG(TPM2,0)
#define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
#define TPM2_C1V TPM_CnV_REG(TPM2,1)
#define TPM2_C2SC TPM_CnSC_REG(TPM2,2)
#define TPM2_C2V TPM_CnV_REG(TPM2,2)
#define TPM2_C3SC TPM_CnSC_REG(TPM2,3)
#define TPM2_C3V TPM_CnV_REG(TPM2,3)
#define TPM2_C4SC TPM_CnSC_REG(TPM2,4)
#define TPM2_C4V TPM_CnV_REG(TPM2,4)
#define TPM2_C5SC TPM_CnSC_REG(TPM2,5)
#define TPM2_C5V TPM_CnV_REG(TPM2,5)
#define TPM2_COMBINE TPM_COMBINE_REG(TPM2)
#define TPM2_TRIG TPM_TRIG_REG(TPM2)
#define TPM2_POL TPM_POL_REG(TPM2)
#define TPM2_FILTER TPM_FILTER_REG(TPM2)
#define TPM2_QDCTRL TPM_QDCTRL_REG(TPM2)
#define TPM2_CONF TPM_CONF_REG(TPM2)
/* TPM - Register array accessors */
#define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
#define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
#define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
#define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
#define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
#define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
/*!
* @}
*/ /* end of group TPM_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group TPM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- UART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
* @{
*/
/** UART - Register Layout Typedef */
typedef struct {
__IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
__IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
__IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
__IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
__I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
__IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
__IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
__IO uint8_t D; /**< UART Data Register, offset: 0x7 */
__IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
__IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
__IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
__IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
__I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
__IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
__IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
uint8_t RESERVED_0[1];
__IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
__IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
__IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
__IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
__I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
__IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
__I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
uint8_t RESERVED_1[1];
__IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
__IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
__IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
__IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
__IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
__IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
__IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
__IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
uint8_t RESERVED_2[26];
__IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
__IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
union { /* offset: 0x3C */
struct { /* offset: 0x3C */
__IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
__IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
} TYPE0;
struct { /* offset: 0x3C */
__IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
__IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
} TYPE1;
};
__IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
__IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
} UART_Type, *UART_MemMapPtr;
/* ----------------------------------------------------------------------------
-- UART - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
* @{
*/
/* UART - Register accessors */
#define UART_BDH_REG(base) ((base)->BDH)
#define UART_BDL_REG(base) ((base)->BDL)
#define UART_C1_REG(base) ((base)->C1)
#define UART_C2_REG(base) ((base)->C2)
#define UART_S1_REG(base) ((base)->S1)
#define UART_S2_REG(base) ((base)->S2)
#define UART_C3_REG(base) ((base)->C3)
#define UART_D_REG(base) ((base)->D)
#define UART_MA1_REG(base) ((base)->MA1)
#define UART_MA2_REG(base) ((base)->MA2)
#define UART_C4_REG(base) ((base)->C4)
#define UART_C5_REG(base) ((base)->C5)
#define UART_ED_REG(base) ((base)->ED)
#define UART_MODEM_REG(base) ((base)->MODEM)
#define UART_IR_REG(base) ((base)->IR)
#define UART_PFIFO_REG(base) ((base)->PFIFO)
#define UART_CFIFO_REG(base) ((base)->CFIFO)
#define UART_SFIFO_REG(base) ((base)->SFIFO)
#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
#define UART_C7816_REG(base) ((base)->C7816)
#define UART_IE7816_REG(base) ((base)->IE7816)
#define UART_IS7816_REG(base) ((base)->IS7816)
#define UART_WP7816_REG(base) ((base)->WP7816)
#define UART_WN7816_REG(base) ((base)->WN7816)
#define UART_WF7816_REG(base) ((base)->WF7816)
#define UART_ET7816_REG(base) ((base)->ET7816)
#define UART_TL7816_REG(base) ((base)->TL7816)
#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
/*!
* @}
*/ /* end of group UART_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- UART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup UART_Register_Masks UART Register Masks
* @{
*/
/* BDH Bit Fields */
#define UART_BDH_SBR_MASK 0x1Fu
#define UART_BDH_SBR_SHIFT 0
#define UART_BDH_SBR_WIDTH 5
#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
#define UART_BDH_SBNS_MASK 0x20u
#define UART_BDH_SBNS_SHIFT 5
#define UART_BDH_SBNS_WIDTH 1
#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
#define UART_BDH_RXEDGIE_MASK 0x40u
#define UART_BDH_RXEDGIE_SHIFT 6
#define UART_BDH_RXEDGIE_WIDTH 1
#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
#define UART_BDH_LBKDIE_MASK 0x80u
#define UART_BDH_LBKDIE_SHIFT 7
#define UART_BDH_LBKDIE_WIDTH 1
#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
/* BDL Bit Fields */
#define UART_BDL_SBR_MASK 0xFFu
#define UART_BDL_SBR_SHIFT 0
#define UART_BDL_SBR_WIDTH 8
#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
/* C1 Bit Fields */
#define UART_C1_PT_MASK 0x1u
#define UART_C1_PT_SHIFT 0
#define UART_C1_PT_WIDTH 1
#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
#define UART_C1_PE_MASK 0x2u
#define UART_C1_PE_SHIFT 1
#define UART_C1_PE_WIDTH 1
#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
#define UART_C1_ILT_MASK 0x4u
#define UART_C1_ILT_SHIFT 2
#define UART_C1_ILT_WIDTH 1
#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
#define UART_C1_WAKE_MASK 0x8u
#define UART_C1_WAKE_SHIFT 3
#define UART_C1_WAKE_WIDTH 1
#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
#define UART_C1_M_MASK 0x10u
#define UART_C1_M_SHIFT 4
#define UART_C1_M_WIDTH 1
#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
#define UART_C1_RSRC_MASK 0x20u
#define UART_C1_RSRC_SHIFT 5
#define UART_C1_RSRC_WIDTH 1
#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
#define UART_C1_UARTSWAI_MASK 0x40u
#define UART_C1_UARTSWAI_SHIFT 6
#define UART_C1_UARTSWAI_WIDTH 1
#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
#define UART_C1_LOOPS_MASK 0x80u
#define UART_C1_LOOPS_SHIFT 7
#define UART_C1_LOOPS_WIDTH 1
#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
/* C2 Bit Fields */
#define UART_C2_SBK_MASK 0x1u
#define UART_C2_SBK_SHIFT 0
#define UART_C2_SBK_WIDTH 1
#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
#define UART_C2_RWU_MASK 0x2u
#define UART_C2_RWU_SHIFT 1
#define UART_C2_RWU_WIDTH 1
#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
#define UART_C2_RE_MASK 0x4u
#define UART_C2_RE_SHIFT 2
#define UART_C2_RE_WIDTH 1
#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
#define UART_C2_TE_MASK 0x8u
#define UART_C2_TE_SHIFT 3
#define UART_C2_TE_WIDTH 1
#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
#define UART_C2_ILIE_MASK 0x10u
#define UART_C2_ILIE_SHIFT 4
#define UART_C2_ILIE_WIDTH 1
#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
#define UART_C2_RIE_MASK 0x20u
#define UART_C2_RIE_SHIFT 5
#define UART_C2_RIE_WIDTH 1
#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
#define UART_C2_TCIE_MASK 0x40u
#define UART_C2_TCIE_SHIFT 6
#define UART_C2_TCIE_WIDTH 1
#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
#define UART_C2_TIE_MASK 0x80u
#define UART_C2_TIE_SHIFT 7
#define UART_C2_TIE_WIDTH 1
#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
/* S1 Bit Fields */
#define UART_S1_PF_MASK 0x1u
#define UART_S1_PF_SHIFT 0
#define UART_S1_PF_WIDTH 1
#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
#define UART_S1_FE_MASK 0x2u
#define UART_S1_FE_SHIFT 1
#define UART_S1_FE_WIDTH 1
#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
#define UART_S1_NF_MASK 0x4u
#define UART_S1_NF_SHIFT 2
#define UART_S1_NF_WIDTH 1
#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
#define UART_S1_OR_MASK 0x8u
#define UART_S1_OR_SHIFT 3
#define UART_S1_OR_WIDTH 1
#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
#define UART_S1_IDLE_MASK 0x10u
#define UART_S1_IDLE_SHIFT 4
#define UART_S1_IDLE_WIDTH 1
#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
#define UART_S1_RDRF_MASK 0x20u
#define UART_S1_RDRF_SHIFT 5
#define UART_S1_RDRF_WIDTH 1
#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
#define UART_S1_TC_MASK 0x40u
#define UART_S1_TC_SHIFT 6
#define UART_S1_TC_WIDTH 1
#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
#define UART_S1_TDRE_MASK 0x80u
#define UART_S1_TDRE_SHIFT 7
#define UART_S1_TDRE_WIDTH 1
#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
/* S2 Bit Fields */
#define UART_S2_RAF_MASK 0x1u
#define UART_S2_RAF_SHIFT 0
#define UART_S2_RAF_WIDTH 1
#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
#define UART_S2_LBKDE_MASK 0x2u
#define UART_S2_LBKDE_SHIFT 1
#define UART_S2_LBKDE_WIDTH 1
#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
#define UART_S2_BRK13_MASK 0x4u
#define UART_S2_BRK13_SHIFT 2
#define UART_S2_BRK13_WIDTH 1
#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
#define UART_S2_RWUID_MASK 0x8u
#define UART_S2_RWUID_SHIFT 3
#define UART_S2_RWUID_WIDTH 1
#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
#define UART_S2_RXINV_MASK 0x10u
#define UART_S2_RXINV_SHIFT 4
#define UART_S2_RXINV_WIDTH 1
#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
#define UART_S2_MSBF_MASK 0x20u
#define UART_S2_MSBF_SHIFT 5
#define UART_S2_MSBF_WIDTH 1
#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
#define UART_S2_RXEDGIF_MASK 0x40u
#define UART_S2_RXEDGIF_SHIFT 6
#define UART_S2_RXEDGIF_WIDTH 1
#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
#define UART_S2_LBKDIF_MASK 0x80u
#define UART_S2_LBKDIF_SHIFT 7
#define UART_S2_LBKDIF_WIDTH 1
#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
/* C3 Bit Fields */
#define UART_C3_PEIE_MASK 0x1u
#define UART_C3_PEIE_SHIFT 0
#define UART_C3_PEIE_WIDTH 1
#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
#define UART_C3_FEIE_MASK 0x2u
#define UART_C3_FEIE_SHIFT 1
#define UART_C3_FEIE_WIDTH 1
#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
#define UART_C3_NEIE_MASK 0x4u
#define UART_C3_NEIE_SHIFT 2
#define UART_C3_NEIE_WIDTH 1
#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
#define UART_C3_ORIE_MASK 0x8u
#define UART_C3_ORIE_SHIFT 3
#define UART_C3_ORIE_WIDTH 1
#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
#define UART_C3_TXINV_MASK 0x10u
#define UART_C3_TXINV_SHIFT 4
#define UART_C3_TXINV_WIDTH 1
#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
#define UART_C3_TXDIR_MASK 0x20u
#define UART_C3_TXDIR_SHIFT 5
#define UART_C3_TXDIR_WIDTH 1
#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
#define UART_C3_T8_MASK 0x40u
#define UART_C3_T8_SHIFT 6
#define UART_C3_T8_WIDTH 1
#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
#define UART_C3_R8_MASK 0x80u
#define UART_C3_R8_SHIFT 7
#define UART_C3_R8_WIDTH 1
#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
/* D Bit Fields */
#define UART_D_RT_MASK 0xFFu
#define UART_D_RT_SHIFT 0
#define UART_D_RT_WIDTH 8
#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
/* MA1 Bit Fields */
#define UART_MA1_MA_MASK 0xFFu
#define UART_MA1_MA_SHIFT 0
#define UART_MA1_MA_WIDTH 8
#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
/* MA2 Bit Fields */
#define UART_MA2_MA_MASK 0xFFu
#define UART_MA2_MA_SHIFT 0
#define UART_MA2_MA_WIDTH 8
#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
/* C4 Bit Fields */
#define UART_C4_BRFA_MASK 0x1Fu
#define UART_C4_BRFA_SHIFT 0
#define UART_C4_BRFA_WIDTH 5
#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
#define UART_C4_M10_MASK 0x20u
#define UART_C4_M10_SHIFT 5
#define UART_C4_M10_WIDTH 1
#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
#define UART_C4_MAEN2_MASK 0x40u
#define UART_C4_MAEN2_SHIFT 6
#define UART_C4_MAEN2_WIDTH 1
#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
#define UART_C4_MAEN1_MASK 0x80u
#define UART_C4_MAEN1_SHIFT 7
#define UART_C4_MAEN1_WIDTH 1
#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
/* C5 Bit Fields */
#define UART_C5_LBKDDMAS_MASK 0x8u
#define UART_C5_LBKDDMAS_SHIFT 3
#define UART_C5_LBKDDMAS_WIDTH 1
#define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_LBKDDMAS_SHIFT))&UART_C5_LBKDDMAS_MASK)
#define UART_C5_RDMAS_MASK 0x20u
#define UART_C5_RDMAS_SHIFT 5
#define UART_C5_RDMAS_WIDTH 1
#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
#define UART_C5_TDMAS_MASK 0x80u
#define UART_C5_TDMAS_SHIFT 7
#define UART_C5_TDMAS_WIDTH 1
#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
/* ED Bit Fields */
#define UART_ED_PARITYE_MASK 0x40u
#define UART_ED_PARITYE_SHIFT 6
#define UART_ED_PARITYE_WIDTH 1
#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
#define UART_ED_NOISY_MASK 0x80u
#define UART_ED_NOISY_SHIFT 7
#define UART_ED_NOISY_WIDTH 1
#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
/* MODEM Bit Fields */
#define UART_MODEM_TXCTSE_MASK 0x1u
#define UART_MODEM_TXCTSE_SHIFT 0
#define UART_MODEM_TXCTSE_WIDTH 1
#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
#define UART_MODEM_TXRTSE_MASK 0x2u
#define UART_MODEM_TXRTSE_SHIFT 1
#define UART_MODEM_TXRTSE_WIDTH 1
#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
#define UART_MODEM_TXRTSPOL_MASK 0x4u
#define UART_MODEM_TXRTSPOL_SHIFT 2
#define UART_MODEM_TXRTSPOL_WIDTH 1
#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
#define UART_MODEM_RXRTSE_MASK 0x8u
#define UART_MODEM_RXRTSE_SHIFT 3
#define UART_MODEM_RXRTSE_WIDTH 1
#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
/* IR Bit Fields */
#define UART_IR_TNP_MASK 0x3u
#define UART_IR_TNP_SHIFT 0
#define UART_IR_TNP_WIDTH 2
#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
#define UART_IR_IREN_MASK 0x4u
#define UART_IR_IREN_SHIFT 2
#define UART_IR_IREN_WIDTH 1
#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
/* PFIFO Bit Fields */
#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
#define UART_PFIFO_RXFIFOSIZE_WIDTH 3
#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
#define UART_PFIFO_RXFE_MASK 0x8u
#define UART_PFIFO_RXFE_SHIFT 3
#define UART_PFIFO_RXFE_WIDTH 1
#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
#define UART_PFIFO_TXFIFOSIZE_WIDTH 3
#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
#define UART_PFIFO_TXFE_MASK 0x80u
#define UART_PFIFO_TXFE_SHIFT 7
#define UART_PFIFO_TXFE_WIDTH 1
#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
/* CFIFO Bit Fields */
#define UART_CFIFO_RXUFE_MASK 0x1u
#define UART_CFIFO_RXUFE_SHIFT 0
#define UART_CFIFO_RXUFE_WIDTH 1
#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
#define UART_CFIFO_TXOFE_MASK 0x2u
#define UART_CFIFO_TXOFE_SHIFT 1
#define UART_CFIFO_TXOFE_WIDTH 1
#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
#define UART_CFIFO_RXOFE_MASK 0x4u
#define UART_CFIFO_RXOFE_SHIFT 2
#define UART_CFIFO_RXOFE_WIDTH 1
#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
#define UART_CFIFO_RXFLUSH_MASK 0x40u
#define UART_CFIFO_RXFLUSH_SHIFT 6
#define UART_CFIFO_RXFLUSH_WIDTH 1
#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
#define UART_CFIFO_TXFLUSH_MASK 0x80u
#define UART_CFIFO_TXFLUSH_SHIFT 7
#define UART_CFIFO_TXFLUSH_WIDTH 1
#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
/* SFIFO Bit Fields */
#define UART_SFIFO_RXUF_MASK 0x1u
#define UART_SFIFO_RXUF_SHIFT 0
#define UART_SFIFO_RXUF_WIDTH 1
#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
#define UART_SFIFO_TXOF_MASK 0x2u
#define UART_SFIFO_TXOF_SHIFT 1
#define UART_SFIFO_TXOF_WIDTH 1
#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
#define UART_SFIFO_RXOF_MASK 0x4u
#define UART_SFIFO_RXOF_SHIFT 2
#define UART_SFIFO_RXOF_WIDTH 1
#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
#define UART_SFIFO_RXEMPT_MASK 0x40u
#define UART_SFIFO_RXEMPT_SHIFT 6
#define UART_SFIFO_RXEMPT_WIDTH 1
#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
#define UART_SFIFO_TXEMPT_MASK 0x80u
#define UART_SFIFO_TXEMPT_SHIFT 7
#define UART_SFIFO_TXEMPT_WIDTH 1
#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
/* TWFIFO Bit Fields */
#define UART_TWFIFO_TXWATER_MASK 0xFFu
#define UART_TWFIFO_TXWATER_SHIFT 0
#define UART_TWFIFO_TXWATER_WIDTH 8
#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
/* TCFIFO Bit Fields */
#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
#define UART_TCFIFO_TXCOUNT_SHIFT 0
#define UART_TCFIFO_TXCOUNT_WIDTH 8
#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
/* RWFIFO Bit Fields */
#define UART_RWFIFO_RXWATER_MASK 0xFFu
#define UART_RWFIFO_RXWATER_SHIFT 0
#define UART_RWFIFO_RXWATER_WIDTH 8
#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
/* RCFIFO Bit Fields */
#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
#define UART_RCFIFO_RXCOUNT_SHIFT 0
#define UART_RCFIFO_RXCOUNT_WIDTH 8
#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
/* C7816 Bit Fields */
#define UART_C7816_ISO_7816E_MASK 0x1u
#define UART_C7816_ISO_7816E_SHIFT 0
#define UART_C7816_ISO_7816E_WIDTH 1
#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
#define UART_C7816_TTYPE_MASK 0x2u
#define UART_C7816_TTYPE_SHIFT 1
#define UART_C7816_TTYPE_WIDTH 1
#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
#define UART_C7816_INIT_MASK 0x4u
#define UART_C7816_INIT_SHIFT 2
#define UART_C7816_INIT_WIDTH 1
#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
#define UART_C7816_ANACK_MASK 0x8u
#define UART_C7816_ANACK_SHIFT 3
#define UART_C7816_ANACK_WIDTH 1
#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
#define UART_C7816_ONACK_MASK 0x10u
#define UART_C7816_ONACK_SHIFT 4
#define UART_C7816_ONACK_WIDTH 1
#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
/* IE7816 Bit Fields */
#define UART_IE7816_RXTE_MASK 0x1u
#define UART_IE7816_RXTE_SHIFT 0
#define UART_IE7816_RXTE_WIDTH 1
#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
#define UART_IE7816_TXTE_MASK 0x2u
#define UART_IE7816_TXTE_SHIFT 1
#define UART_IE7816_TXTE_WIDTH 1
#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
#define UART_IE7816_GTVE_MASK 0x4u
#define UART_IE7816_GTVE_SHIFT 2
#define UART_IE7816_GTVE_WIDTH 1
#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
#define UART_IE7816_ADTE_MASK 0x8u
#define UART_IE7816_ADTE_SHIFT 3
#define UART_IE7816_ADTE_WIDTH 1
#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_ADTE_SHIFT))&UART_IE7816_ADTE_MASK)
#define UART_IE7816_INITDE_MASK 0x10u
#define UART_IE7816_INITDE_SHIFT 4
#define UART_IE7816_INITDE_WIDTH 1
#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
#define UART_IE7816_BWTE_MASK 0x20u
#define UART_IE7816_BWTE_SHIFT 5
#define UART_IE7816_BWTE_WIDTH 1
#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
#define UART_IE7816_CWTE_MASK 0x40u
#define UART_IE7816_CWTE_SHIFT 6
#define UART_IE7816_CWTE_WIDTH 1
#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
#define UART_IE7816_WTE_MASK 0x80u
#define UART_IE7816_WTE_SHIFT 7
#define UART_IE7816_WTE_WIDTH 1
#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
/* IS7816 Bit Fields */
#define UART_IS7816_RXT_MASK 0x1u
#define UART_IS7816_RXT_SHIFT 0
#define UART_IS7816_RXT_WIDTH 1
#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
#define UART_IS7816_TXT_MASK 0x2u
#define UART_IS7816_TXT_SHIFT 1
#define UART_IS7816_TXT_WIDTH 1
#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
#define UART_IS7816_GTV_MASK 0x4u
#define UART_IS7816_GTV_SHIFT 2
#define UART_IS7816_GTV_WIDTH 1
#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
#define UART_IS7816_ADT_MASK 0x8u
#define UART_IS7816_ADT_SHIFT 3
#define UART_IS7816_ADT_WIDTH 1
#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_ADT_SHIFT))&UART_IS7816_ADT_MASK)
#define UART_IS7816_INITD_MASK 0x10u
#define UART_IS7816_INITD_SHIFT 4
#define UART_IS7816_INITD_WIDTH 1
#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
#define UART_IS7816_BWT_MASK 0x20u
#define UART_IS7816_BWT_SHIFT 5
#define UART_IS7816_BWT_WIDTH 1
#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
#define UART_IS7816_CWT_MASK 0x40u
#define UART_IS7816_CWT_SHIFT 6
#define UART_IS7816_CWT_WIDTH 1
#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
#define UART_IS7816_WT_MASK 0x80u
#define UART_IS7816_WT_SHIFT 7
#define UART_IS7816_WT_WIDTH 1
#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
/* WP7816 Bit Fields */
#define UART_WP7816_WTX_MASK 0xFFu
#define UART_WP7816_WTX_SHIFT 0
#define UART_WP7816_WTX_WIDTH 8
#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
/* WN7816 Bit Fields */
#define UART_WN7816_GTN_MASK 0xFFu
#define UART_WN7816_GTN_SHIFT 0
#define UART_WN7816_GTN_WIDTH 8
#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
/* WF7816 Bit Fields */
#define UART_WF7816_GTFD_MASK 0xFFu
#define UART_WF7816_GTFD_SHIFT 0
#define UART_WF7816_GTFD_WIDTH 8
#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
/* ET7816 Bit Fields */
#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
#define UART_ET7816_RXTHRESHOLD_SHIFT 0
#define UART_ET7816_RXTHRESHOLD_WIDTH 4
#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
#define UART_ET7816_TXTHRESHOLD_SHIFT 4
#define UART_ET7816_TXTHRESHOLD_WIDTH 4
#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
/* TL7816 Bit Fields */
#define UART_TL7816_TLEN_MASK 0xFFu
#define UART_TL7816_TLEN_SHIFT 0
#define UART_TL7816_TLEN_WIDTH 8
#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
/* AP7816A_T0 Bit Fields */
#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
#define UART_AP7816A_T0_ADTI_H_SHIFT 0
#define UART_AP7816A_T0_ADTI_H_WIDTH 8
#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
/* AP7816B_T0 Bit Fields */
#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
#define UART_AP7816B_T0_ADTI_L_SHIFT 0
#define UART_AP7816B_T0_ADTI_L_WIDTH 8
#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
/* WP7816A_T0 Bit Fields */
#define UART_WP7816A_T0_WI_H_MASK 0xFFu
#define UART_WP7816A_T0_WI_H_SHIFT 0
#define UART_WP7816A_T0_WI_H_WIDTH 8
#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
/* WP7816B_T0 Bit Fields */
#define UART_WP7816B_T0_WI_L_MASK 0xFFu
#define UART_WP7816B_T0_WI_L_SHIFT 0
#define UART_WP7816B_T0_WI_L_WIDTH 8
#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
/* WP7816A_T1 Bit Fields */
#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
#define UART_WP7816A_T1_BWI_H_SHIFT 0
#define UART_WP7816A_T1_BWI_H_WIDTH 8
#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
/* WP7816B_T1 Bit Fields */
#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
#define UART_WP7816B_T1_BWI_L_SHIFT 0
#define UART_WP7816B_T1_BWI_L_WIDTH 8
#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
/* WGP7816_T1 Bit Fields */
#define UART_WGP7816_T1_BGI_MASK 0xFu
#define UART_WGP7816_T1_BGI_SHIFT 0
#define UART_WGP7816_T1_BGI_WIDTH 4
#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
#define UART_WGP7816_T1_CWI1_MASK 0xF0u
#define UART_WGP7816_T1_CWI1_SHIFT 4
#define UART_WGP7816_T1_CWI1_WIDTH 4
#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
/* WP7816C_T1 Bit Fields */
#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
#define UART_WP7816C_T1_CWI2_SHIFT 0
#define UART_WP7816C_T1_CWI2_WIDTH 5
#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
/*!
* @}
*/ /* end of group UART_Register_Masks */
/* UART - Peripheral instance base addresses */
/** Peripheral UART0 base address */
#define UART0_BASE (0x4006A000u)
/** Peripheral UART0 base pointer */
#define UART0 ((UART_Type *)UART0_BASE)
#define UART0_BASE_PTR (UART0)
/** Peripheral UART1 base address */
#define UART1_BASE (0x4006B000u)
/** Peripheral UART1 base pointer */
#define UART1 ((UART_Type *)UART1_BASE)
#define UART1_BASE_PTR (UART1)
/** Peripheral UART2 base address */
#define UART2_BASE (0x4006C000u)
/** Peripheral UART2 base pointer */
#define UART2 ((UART_Type *)UART2_BASE)
#define UART2_BASE_PTR (UART2)
/** Array initializer of UART peripheral base addresses */
#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
/** Array initializer of UART peripheral base pointers */
#define UART_BASE_PTRS { UART0, UART1, UART2 }
/* ----------------------------------------------------------------------------
-- UART - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
* @{
*/
/* UART - Register instance definitions */
/* UART0 */
#define UART0_BDH UART_BDH_REG(UART0)
#define UART0_BDL UART_BDL_REG(UART0)
#define UART0_C1 UART_C1_REG(UART0)
#define UART0_C2 UART_C2_REG(UART0)
#define UART0_S1 UART_S1_REG(UART0)
#define UART0_S2 UART_S2_REG(UART0)
#define UART0_C3 UART_C3_REG(UART0)
#define UART0_D UART_D_REG(UART0)
#define UART0_MA1 UART_MA1_REG(UART0)
#define UART0_MA2 UART_MA2_REG(UART0)
#define UART0_C4 UART_C4_REG(UART0)
#define UART0_C5 UART_C5_REG(UART0)
#define UART0_ED UART_ED_REG(UART0)
#define UART0_MODEM UART_MODEM_REG(UART0)
#define UART0_IR UART_IR_REG(UART0)
#define UART0_PFIFO UART_PFIFO_REG(UART0)
#define UART0_CFIFO UART_CFIFO_REG(UART0)
#define UART0_SFIFO UART_SFIFO_REG(UART0)
#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
#define UART0_C7816 UART_C7816_REG(UART0)
#define UART0_IE7816 UART_IE7816_REG(UART0)
#define UART0_IS7816 UART_IS7816_REG(UART0)
#define UART0_WP7816 UART_WP7816_REG(UART0)
#define UART0_WN7816 UART_WN7816_REG(UART0)
#define UART0_WF7816 UART_WF7816_REG(UART0)
#define UART0_ET7816 UART_ET7816_REG(UART0)
#define UART0_TL7816 UART_TL7816_REG(UART0)
#define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
#define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
#define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
#define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
#define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
#define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
#define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
#define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
/* UART1 */
#define UART1_BDH UART_BDH_REG(UART1)
#define UART1_BDL UART_BDL_REG(UART1)
#define UART1_C1 UART_C1_REG(UART1)
#define UART1_C2 UART_C2_REG(UART1)
#define UART1_S1 UART_S1_REG(UART1)
#define UART1_S2 UART_S2_REG(UART1)
#define UART1_C3 UART_C3_REG(UART1)
#define UART1_D UART_D_REG(UART1)
#define UART1_MA1 UART_MA1_REG(UART1)
#define UART1_MA2 UART_MA2_REG(UART1)
#define UART1_C4 UART_C4_REG(UART1)
#define UART1_C5 UART_C5_REG(UART1)
#define UART1_ED UART_ED_REG(UART1)
#define UART1_MODEM UART_MODEM_REG(UART1)
#define UART1_IR UART_IR_REG(UART1)
#define UART1_PFIFO UART_PFIFO_REG(UART1)
#define UART1_CFIFO UART_CFIFO_REG(UART1)
#define UART1_SFIFO UART_SFIFO_REG(UART1)
#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
/* UART2 */
#define UART2_BDH UART_BDH_REG(UART2)
#define UART2_BDL UART_BDL_REG(UART2)
#define UART2_C1 UART_C1_REG(UART2)
#define UART2_C2 UART_C2_REG(UART2)
#define UART2_S1 UART_S1_REG(UART2)
#define UART2_S2 UART_S2_REG(UART2)
#define UART2_C3 UART_C3_REG(UART2)
#define UART2_D UART_D_REG(UART2)
#define UART2_MA1 UART_MA1_REG(UART2)
#define UART2_MA2 UART_MA2_REG(UART2)
#define UART2_C4 UART_C4_REG(UART2)
#define UART2_C5 UART_C5_REG(UART2)
#define UART2_ED UART_ED_REG(UART2)
#define UART2_MODEM UART_MODEM_REG(UART2)
#define UART2_IR UART_IR_REG(UART2)
#define UART2_PFIFO UART_PFIFO_REG(UART2)
#define UART2_CFIFO UART_CFIFO_REG(UART2)
#define UART2_SFIFO UART_SFIFO_REG(UART2)
#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
/*!
* @}
*/ /* end of group UART_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group UART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
* @{
*/
/** USB - Register Layout Typedef */
typedef struct {
__I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
uint8_t RESERVED_0[3];
__I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
uint8_t RESERVED_1[3];
__I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
uint8_t RESERVED_2[3];
__I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
uint8_t RESERVED_3[3];
__IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
uint8_t RESERVED_4[3];
__IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
uint8_t RESERVED_5[3];
__IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
uint8_t RESERVED_6[3];
__IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
uint8_t RESERVED_7[99];
__IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
uint8_t RESERVED_8[3];
__IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
uint8_t RESERVED_9[3];
__IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
uint8_t RESERVED_10[3];
__IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
uint8_t RESERVED_11[3];
__I uint8_t STAT; /**< Status register, offset: 0x90 */
uint8_t RESERVED_12[3];
__IO uint8_t CTL; /**< Control register, offset: 0x94 */
uint8_t RESERVED_13[3];
__IO uint8_t ADDR; /**< Address register, offset: 0x98 */
uint8_t RESERVED_14[3];
__IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
uint8_t RESERVED_15[3];
__IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
uint8_t RESERVED_16[3];
__IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
uint8_t RESERVED_17[3];
__IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
uint8_t RESERVED_18[3];
__IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
uint8_t RESERVED_19[3];
__IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
uint8_t RESERVED_20[3];
__IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
uint8_t RESERVED_21[11];
struct { /* offset: 0xC0, array step: 0x4 */
__IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_0[3];
} ENDPOINT[16];
__IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
uint8_t RESERVED_22[3];
__I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
uint8_t RESERVED_23[3];
__IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
uint8_t RESERVED_24[3];
__IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
uint8_t RESERVED_25[7];
__IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
uint8_t RESERVED_26[23];
__IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */
uint8_t RESERVED_27[3];
__IO uint8_t STALL_IL_DIS; /**< Peripheral mode stall disable for endpoints 7 to 0 in IN direction, offset: 0x130 */
uint8_t RESERVED_28[3];
__IO uint8_t STALL_IH_DIS; /**< Peripheral mode stall disable for endpoints 15 to 8 in IN direction, offset: 0x134 */
uint8_t RESERVED_29[3];
__IO uint8_t STALL_OL_DIS; /**< Peripheral mode stall disable for endpoints 7 to 0 in OUT direction, offset: 0x138 */
uint8_t RESERVED_30[3];
__IO uint8_t STALL_OH_DIS; /**< Peripheral mode stall disable for endpoints 15 to 8 in OUT direction, offset: 0x13C */
uint8_t RESERVED_31[3];
__IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
uint8_t RESERVED_32[3];
__IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
uint8_t RESERVED_33[15];
__IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
uint8_t RESERVED_34[7];
__IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
} USB_Type, *USB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- USB - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
* @{
*/
/* USB - Register accessors */
#define USB_PERID_REG(base) ((base)->PERID)
#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
#define USB_REV_REG(base) ((base)->REV)
#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
#define USB_OTGICR_REG(base) ((base)->OTGICR)
#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
#define USB_ISTAT_REG(base) ((base)->ISTAT)
#define USB_INTEN_REG(base) ((base)->INTEN)
#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
#define USB_ERREN_REG(base) ((base)->ERREN)
#define USB_STAT_REG(base) ((base)->STAT)
#define USB_CTL_REG(base) ((base)->CTL)
#define USB_ADDR_REG(base) ((base)->ADDR)
#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
#define USB_TOKEN_REG(base) ((base)->TOKEN)
#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
#define USB_ENDPT_COUNT 16
#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
#define USB_CONTROL_REG(base) ((base)->CONTROL)
#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
#define USB_MISCCTRL_REG(base) ((base)->MISCCTRL)
#define USB_STALL_IL_DIS_REG(base) ((base)->STALL_IL_DIS)
#define USB_STALL_IH_DIS_REG(base) ((base)->STALL_IH_DIS)
#define USB_STALL_OL_DIS_REG(base) ((base)->STALL_OL_DIS)
#define USB_STALL_OH_DIS_REG(base) ((base)->STALL_OH_DIS)
#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
/*!
* @}
*/ /* end of group USB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- USB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
/* PERID Bit Fields */
#define USB_PERID_ID_MASK 0x3Fu
#define USB_PERID_ID_SHIFT 0
#define USB_PERID_ID_WIDTH 6
#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
/* IDCOMP Bit Fields */
#define USB_IDCOMP_NID_MASK 0x3Fu
#define USB_IDCOMP_NID_SHIFT 0
#define USB_IDCOMP_NID_WIDTH 6
#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
/* REV Bit Fields */
#define USB_REV_REV_MASK 0xFFu
#define USB_REV_REV_SHIFT 0
#define USB_REV_REV_WIDTH 8
#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
/* ADDINFO Bit Fields */
#define USB_ADDINFO_IEHOST_MASK 0x1u
#define USB_ADDINFO_IEHOST_SHIFT 0
#define USB_ADDINFO_IEHOST_WIDTH 1
#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
/* OTGISTAT Bit Fields */
#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH 1
#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
#define USB_OTGISTAT_ONEMSEC_SHIFT 6
#define USB_OTGISTAT_ONEMSEC_WIDTH 1
#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
/* OTGICR Bit Fields */
#define USB_OTGICR_LINESTATEEN_MASK 0x20u
#define USB_OTGICR_LINESTATEEN_SHIFT 5
#define USB_OTGICR_LINESTATEEN_WIDTH 1
#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
#define USB_OTGICR_ONEMSECEN_MASK 0x40u
#define USB_OTGICR_ONEMSECEN_SHIFT 6
#define USB_OTGICR_ONEMSECEN_WIDTH 1
#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
/* OTGSTAT Bit Fields */
#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
#define USB_OTGSTAT_LINESTATESTABLE_WIDTH 1
#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
#define USB_OTGSTAT_ONEMSECEN_WIDTH 1
#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
/* OTGCTL Bit Fields */
#define USB_OTGCTL_OTGEN_MASK 0x4u
#define USB_OTGCTL_OTGEN_SHIFT 2
#define USB_OTGCTL_OTGEN_WIDTH 1
#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
#define USB_OTGCTL_DMLOW_MASK 0x10u
#define USB_OTGCTL_DMLOW_SHIFT 4
#define USB_OTGCTL_DMLOW_WIDTH 1
#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
#define USB_OTGCTL_DPLOW_MASK 0x20u
#define USB_OTGCTL_DPLOW_SHIFT 5
#define USB_OTGCTL_DPLOW_WIDTH 1
#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
#define USB_OTGCTL_DPHIGH_MASK 0x80u
#define USB_OTGCTL_DPHIGH_SHIFT 7
#define USB_OTGCTL_DPHIGH_WIDTH 1
#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
/* ISTAT Bit Fields */
#define USB_ISTAT_USBRST_MASK 0x1u
#define USB_ISTAT_USBRST_SHIFT 0
#define USB_ISTAT_USBRST_WIDTH 1
#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
#define USB_ISTAT_ERROR_MASK 0x2u
#define USB_ISTAT_ERROR_SHIFT 1
#define USB_ISTAT_ERROR_WIDTH 1
#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
#define USB_ISTAT_SOFTOK_MASK 0x4u
#define USB_ISTAT_SOFTOK_SHIFT 2
#define USB_ISTAT_SOFTOK_WIDTH 1
#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
#define USB_ISTAT_TOKDNE_MASK 0x8u
#define USB_ISTAT_TOKDNE_SHIFT 3
#define USB_ISTAT_TOKDNE_WIDTH 1
#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
#define USB_ISTAT_SLEEP_MASK 0x10u
#define USB_ISTAT_SLEEP_SHIFT 4
#define USB_ISTAT_SLEEP_WIDTH 1
#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
#define USB_ISTAT_RESUME_MASK 0x20u
#define USB_ISTAT_RESUME_SHIFT 5
#define USB_ISTAT_RESUME_WIDTH 1
#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
#define USB_ISTAT_ATTACH_MASK 0x40u
#define USB_ISTAT_ATTACH_SHIFT 6
#define USB_ISTAT_ATTACH_WIDTH 1
#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
#define USB_ISTAT_STALL_MASK 0x80u
#define USB_ISTAT_STALL_SHIFT 7
#define USB_ISTAT_STALL_WIDTH 1
#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
/* INTEN Bit Fields */
#define USB_INTEN_USBRSTEN_MASK 0x1u
#define USB_INTEN_USBRSTEN_SHIFT 0
#define USB_INTEN_USBRSTEN_WIDTH 1
#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
#define USB_INTEN_ERROREN_MASK 0x2u
#define USB_INTEN_ERROREN_SHIFT 1
#define USB_INTEN_ERROREN_WIDTH 1
#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
#define USB_INTEN_SOFTOKEN_MASK 0x4u
#define USB_INTEN_SOFTOKEN_SHIFT 2
#define USB_INTEN_SOFTOKEN_WIDTH 1
#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
#define USB_INTEN_TOKDNEEN_MASK 0x8u
#define USB_INTEN_TOKDNEEN_SHIFT 3
#define USB_INTEN_TOKDNEEN_WIDTH 1
#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
#define USB_INTEN_SLEEPEN_MASK 0x10u
#define USB_INTEN_SLEEPEN_SHIFT 4
#define USB_INTEN_SLEEPEN_WIDTH 1
#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
#define USB_INTEN_RESUMEEN_MASK 0x20u
#define USB_INTEN_RESUMEEN_SHIFT 5
#define USB_INTEN_RESUMEEN_WIDTH 1
#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
#define USB_INTEN_ATTACHEN_MASK 0x40u
#define USB_INTEN_ATTACHEN_SHIFT 6
#define USB_INTEN_ATTACHEN_WIDTH 1
#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
#define USB_INTEN_STALLEN_MASK 0x80u
#define USB_INTEN_STALLEN_SHIFT 7
#define USB_INTEN_STALLEN_WIDTH 1
#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
/* ERRSTAT Bit Fields */
#define USB_ERRSTAT_PIDERR_MASK 0x1u
#define USB_ERRSTAT_PIDERR_SHIFT 0
#define USB_ERRSTAT_PIDERR_WIDTH 1
#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
#define USB_ERRSTAT_CRC5EOF_SHIFT 1
#define USB_ERRSTAT_CRC5EOF_WIDTH 1
#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
#define USB_ERRSTAT_CRC16_MASK 0x4u
#define USB_ERRSTAT_CRC16_SHIFT 2
#define USB_ERRSTAT_CRC16_WIDTH 1
#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
#define USB_ERRSTAT_DFN8_MASK 0x8u
#define USB_ERRSTAT_DFN8_SHIFT 3
#define USB_ERRSTAT_DFN8_WIDTH 1
#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
#define USB_ERRSTAT_BTOERR_MASK 0x10u
#define USB_ERRSTAT_BTOERR_SHIFT 4
#define USB_ERRSTAT_BTOERR_WIDTH 1
#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
#define USB_ERRSTAT_DMAERR_MASK 0x20u
#define USB_ERRSTAT_DMAERR_SHIFT 5
#define USB_ERRSTAT_DMAERR_WIDTH 1
#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
#define USB_ERRSTAT_OWNERR_MASK 0x40u
#define USB_ERRSTAT_OWNERR_SHIFT 6
#define USB_ERRSTAT_OWNERR_WIDTH 1
#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_OWNERR_SHIFT))&USB_ERRSTAT_OWNERR_MASK)
#define USB_ERRSTAT_BTSERR_MASK 0x80u
#define USB_ERRSTAT_BTSERR_SHIFT 7
#define USB_ERRSTAT_BTSERR_WIDTH 1
#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
/* ERREN Bit Fields */
#define USB_ERREN_PIDERREN_MASK 0x1u
#define USB_ERREN_PIDERREN_SHIFT 0
#define USB_ERREN_PIDERREN_WIDTH 1
#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
#define USB_ERREN_CRC5EOFEN_MASK 0x2u
#define USB_ERREN_CRC5EOFEN_SHIFT 1
#define USB_ERREN_CRC5EOFEN_WIDTH 1
#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
#define USB_ERREN_CRC16EN_MASK 0x4u
#define USB_ERREN_CRC16EN_SHIFT 2
#define USB_ERREN_CRC16EN_WIDTH 1
#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
#define USB_ERREN_DFN8EN_MASK 0x8u
#define USB_ERREN_DFN8EN_SHIFT 3
#define USB_ERREN_DFN8EN_WIDTH 1
#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
#define USB_ERREN_BTOERREN_MASK 0x10u
#define USB_ERREN_BTOERREN_SHIFT 4
#define USB_ERREN_BTOERREN_WIDTH 1
#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
#define USB_ERREN_DMAERREN_MASK 0x20u
#define USB_ERREN_DMAERREN_SHIFT 5
#define USB_ERREN_DMAERREN_WIDTH 1
#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
#define USB_ERREN_OWNERREN_MASK 0x40u
#define USB_ERREN_OWNERREN_SHIFT 6
#define USB_ERREN_OWNERREN_WIDTH 1
#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_OWNERREN_SHIFT))&USB_ERREN_OWNERREN_MASK)
#define USB_ERREN_BTSERREN_MASK 0x80u
#define USB_ERREN_BTSERREN_SHIFT 7
#define USB_ERREN_BTSERREN_WIDTH 1
#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
/* STAT Bit Fields */
#define USB_STAT_ODD_MASK 0x4u
#define USB_STAT_ODD_SHIFT 2
#define USB_STAT_ODD_WIDTH 1
#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
#define USB_STAT_TX_MASK 0x8u
#define USB_STAT_TX_SHIFT 3
#define USB_STAT_TX_WIDTH 1
#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
#define USB_STAT_ENDP_MASK 0xF0u
#define USB_STAT_ENDP_SHIFT 4
#define USB_STAT_ENDP_WIDTH 4
#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
/* CTL Bit Fields */
#define USB_CTL_USBENSOFEN_MASK 0x1u
#define USB_CTL_USBENSOFEN_SHIFT 0
#define USB_CTL_USBENSOFEN_WIDTH 1
#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
#define USB_CTL_ODDRST_MASK 0x2u
#define USB_CTL_ODDRST_SHIFT 1
#define USB_CTL_ODDRST_WIDTH 1
#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
#define USB_CTL_RESUME_MASK 0x4u
#define USB_CTL_RESUME_SHIFT 2
#define USB_CTL_RESUME_WIDTH 1
#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
#define USB_CTL_HOSTMODEEN_MASK 0x8u
#define USB_CTL_HOSTMODEEN_SHIFT 3
#define USB_CTL_HOSTMODEEN_WIDTH 1
#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
#define USB_CTL_RESET_MASK 0x10u
#define USB_CTL_RESET_SHIFT 4
#define USB_CTL_RESET_WIDTH 1
#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH 1
#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
#define USB_CTL_SE0_MASK 0x40u
#define USB_CTL_SE0_SHIFT 6
#define USB_CTL_SE0_WIDTH 1
#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
#define USB_CTL_JSTATE_MASK 0x80u
#define USB_CTL_JSTATE_SHIFT 7
#define USB_CTL_JSTATE_WIDTH 1
#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
/* ADDR Bit Fields */
#define USB_ADDR_ADDR_MASK 0x7Fu
#define USB_ADDR_ADDR_SHIFT 0
#define USB_ADDR_ADDR_WIDTH 7
#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
#define USB_ADDR_LSEN_MASK 0x80u
#define USB_ADDR_LSEN_SHIFT 7
#define USB_ADDR_LSEN_WIDTH 1
#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
/* BDTPAGE1 Bit Fields */
#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
#define USB_BDTPAGE1_BDTBA_SHIFT 1
#define USB_BDTPAGE1_BDTBA_WIDTH 7
#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
/* FRMNUML Bit Fields */
#define USB_FRMNUML_FRM_MASK 0xFFu
#define USB_FRMNUML_FRM_SHIFT 0
#define USB_FRMNUML_FRM_WIDTH 8
#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
/* FRMNUMH Bit Fields */
#define USB_FRMNUMH_FRM_MASK 0x7u
#define USB_FRMNUMH_FRM_SHIFT 0
#define USB_FRMNUMH_FRM_WIDTH 3
#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
/* TOKEN Bit Fields */
#define USB_TOKEN_TOKENENDPT_MASK 0xFu
#define USB_TOKEN_TOKENENDPT_SHIFT 0
#define USB_TOKEN_TOKENENDPT_WIDTH 4
#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
#define USB_TOKEN_TOKENPID_MASK 0xF0u
#define USB_TOKEN_TOKENPID_SHIFT 4
#define USB_TOKEN_TOKENPID_WIDTH 4
#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
/* SOFTHLD Bit Fields */
#define USB_SOFTHLD_CNT_MASK 0xFFu
#define USB_SOFTHLD_CNT_SHIFT 0
#define USB_SOFTHLD_CNT_WIDTH 8
#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
/* BDTPAGE2 Bit Fields */
#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
#define USB_BDTPAGE2_BDTBA_SHIFT 0
#define USB_BDTPAGE2_BDTBA_WIDTH 8
#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
/* BDTPAGE3 Bit Fields */
#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
#define USB_BDTPAGE3_BDTBA_SHIFT 0
#define USB_BDTPAGE3_BDTBA_WIDTH 8
#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
/* ENDPT Bit Fields */
#define USB_ENDPT_EPHSHK_MASK 0x1u
#define USB_ENDPT_EPHSHK_SHIFT 0
#define USB_ENDPT_EPHSHK_WIDTH 1
#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
#define USB_ENDPT_EPSTALL_MASK 0x2u
#define USB_ENDPT_EPSTALL_SHIFT 1
#define USB_ENDPT_EPSTALL_WIDTH 1
#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
#define USB_ENDPT_EPTXEN_MASK 0x4u
#define USB_ENDPT_EPTXEN_SHIFT 2
#define USB_ENDPT_EPTXEN_WIDTH 1
#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
#define USB_ENDPT_EPRXEN_MASK 0x8u
#define USB_ENDPT_EPRXEN_SHIFT 3
#define USB_ENDPT_EPRXEN_WIDTH 1
#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
#define USB_ENDPT_EPCTLDIS_MASK 0x10u
#define USB_ENDPT_EPCTLDIS_SHIFT 4
#define USB_ENDPT_EPCTLDIS_WIDTH 1
#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
#define USB_ENDPT_RETRYDIS_MASK 0x40u
#define USB_ENDPT_RETRYDIS_SHIFT 6
#define USB_ENDPT_RETRYDIS_WIDTH 1
#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
#define USB_ENDPT_HOSTWOHUB_SHIFT 7
#define USB_ENDPT_HOSTWOHUB_WIDTH 1
#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
/* USBCTRL Bit Fields */
#define USB_USBCTRL_UARTSEL_MASK 0x10u
#define USB_USBCTRL_UARTSEL_SHIFT 4
#define USB_USBCTRL_UARTSEL_WIDTH 1
#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_UARTSEL_SHIFT))&USB_USBCTRL_UARTSEL_MASK)
#define USB_USBCTRL_UARTCHLS_MASK 0x20u
#define USB_USBCTRL_UARTCHLS_SHIFT 5
#define USB_USBCTRL_UARTCHLS_WIDTH 1
#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_UARTCHLS_SHIFT))&USB_USBCTRL_UARTCHLS_MASK)
#define USB_USBCTRL_PDE_MASK 0x40u
#define USB_USBCTRL_PDE_SHIFT 6
#define USB_USBCTRL_PDE_WIDTH 1
#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
#define USB_USBCTRL_SUSP_MASK 0x80u
#define USB_USBCTRL_SUSP_SHIFT 7
#define USB_USBCTRL_SUSP_WIDTH 1
#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
/* OBSERVE Bit Fields */
#define USB_OBSERVE_DMPD_MASK 0x10u
#define USB_OBSERVE_DMPD_SHIFT 4
#define USB_OBSERVE_DMPD_WIDTH 1
#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
#define USB_OBSERVE_DPPD_MASK 0x40u
#define USB_OBSERVE_DPPD_SHIFT 6
#define USB_OBSERVE_DPPD_WIDTH 1
#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
#define USB_OBSERVE_DPPU_MASK 0x80u
#define USB_OBSERVE_DPPU_SHIFT 7
#define USB_OBSERVE_DPPU_WIDTH 1
#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
/* CONTROL Bit Fields */
#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
#define USB_CONTROL_DPPULLUPNONOTG_WIDTH 1
#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
/* USBTRC0 Bit Fields */
#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
#define USB_USBTRC0_USB_RESUME_INT_WIDTH 1
#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
#define USB_USBTRC0_SYNC_DET_MASK 0x2u
#define USB_USBTRC0_SYNC_DET_SHIFT 1
#define USB_USBTRC0_SYNC_DET_WIDTH 1
#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH 1
#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
#define USB_USBTRC0_VREDG_DET_MASK 0x8u
#define USB_USBTRC0_VREDG_DET_SHIFT 3
#define USB_USBTRC0_VREDG_DET_WIDTH 1
#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_VREDG_DET_SHIFT))&USB_USBTRC0_VREDG_DET_MASK)
#define USB_USBTRC0_VFEDG_DET_MASK 0x10u
#define USB_USBTRC0_VFEDG_DET_SHIFT 4
#define USB_USBTRC0_VFEDG_DET_WIDTH 1
#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_VFEDG_DET_SHIFT))&USB_USBTRC0_VFEDG_DET_MASK)
#define USB_USBTRC0_USBRESMEN_MASK 0x20u
#define USB_USBTRC0_USBRESMEN_SHIFT 5
#define USB_USBTRC0_USBRESMEN_WIDTH 1
#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
#define USB_USBTRC0_USBRESET_MASK 0x80u
#define USB_USBTRC0_USBRESET_SHIFT 7
#define USB_USBTRC0_USBRESET_WIDTH 1
#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
/* USBFRMADJUST Bit Fields */
#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
#define USB_USBFRMADJUST_ADJ_SHIFT 0
#define USB_USBFRMADJUST_ADJ_WIDTH 8
#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
/* MISCCTRL Bit Fields */
#define USB_MISCCTRL_SOFDYNTHLD_MASK 0x1u
#define USB_MISCCTRL_SOFDYNTHLD_SHIFT 0
#define USB_MISCCTRL_SOFDYNTHLD_WIDTH 1
#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_SOFDYNTHLD_SHIFT))&USB_MISCCTRL_SOFDYNTHLD_MASK)
#define USB_MISCCTRL_SOFBUSSET_MASK 0x2u
#define USB_MISCCTRL_SOFBUSSET_SHIFT 1
#define USB_MISCCTRL_SOFBUSSET_WIDTH 1
#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_SOFBUSSET_SHIFT))&USB_MISCCTRL_SOFBUSSET_MASK)
#define USB_MISCCTRL_OWNERRISODIS_MASK 0x4u
#define USB_MISCCTRL_OWNERRISODIS_SHIFT 2
#define USB_MISCCTRL_OWNERRISODIS_WIDTH 1
#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_OWNERRISODIS_SHIFT))&USB_MISCCTRL_OWNERRISODIS_MASK)
#define USB_MISCCTRL_VREDG_EN_MASK 0x8u
#define USB_MISCCTRL_VREDG_EN_SHIFT 3
#define USB_MISCCTRL_VREDG_EN_WIDTH 1
#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_VREDG_EN_SHIFT))&USB_MISCCTRL_VREDG_EN_MASK)
#define USB_MISCCTRL_VFEDG_EN_MASK 0x10u
#define USB_MISCCTRL_VFEDG_EN_SHIFT 4
#define USB_MISCCTRL_VFEDG_EN_WIDTH 1
#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_VFEDG_EN_SHIFT))&USB_MISCCTRL_VFEDG_EN_MASK)
#define USB_MISCCTRL_STL_ADJ_EN_MASK 0x80u
#define USB_MISCCTRL_STL_ADJ_EN_SHIFT 7
#define USB_MISCCTRL_STL_ADJ_EN_WIDTH 1
#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_STL_ADJ_EN_SHIFT))&USB_MISCCTRL_STL_ADJ_EN_MASK)
/* STALL_IL_DIS Bit Fields */
#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK 0x1u
#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT 0
#define USB_STALL_IL_DIS_STALL_I_DIS0_WIDTH 1
#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK 0x2u
#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT 1
#define USB_STALL_IL_DIS_STALL_I_DIS1_WIDTH 1
#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK 0x4u
#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT 2
#define USB_STALL_IL_DIS_STALL_I_DIS2_WIDTH 1
#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK 0x8u
#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT 3
#define USB_STALL_IL_DIS_STALL_I_DIS3_WIDTH 1
#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK 0x10u
#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT 4
#define USB_STALL_IL_DIS_STALL_I_DIS4_WIDTH 1
#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK 0x20u
#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT 5
#define USB_STALL_IL_DIS_STALL_I_DIS5_WIDTH 1
#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK 0x40u
#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT 6
#define USB_STALL_IL_DIS_STALL_I_DIS6_WIDTH 1
#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK 0x80u
#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT 7
#define USB_STALL_IL_DIS_STALL_I_DIS7_WIDTH 1
#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
/* STALL_IH_DIS Bit Fields */
#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK 0x1u
#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT 0
#define USB_STALL_IH_DIS_STALL_I_DIS8_WIDTH 1
#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK 0x2u
#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT 1
#define USB_STALL_IH_DIS_STALL_I_DIS9_WIDTH 1
#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK 0x4u
#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT 2
#define USB_STALL_IH_DIS_STALL_I_DIS10_WIDTH 1
#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK 0x8u
#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT 3
#define USB_STALL_IH_DIS_STALL_I_DIS11_WIDTH 1
#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK 0x10u
#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT 4
#define USB_STALL_IH_DIS_STALL_I_DIS12_WIDTH 1
#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK 0x20u
#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT 5
#define USB_STALL_IH_DIS_STALL_I_DIS13_WIDTH 1
#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK 0x40u
#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT 6
#define USB_STALL_IH_DIS_STALL_I_DIS14_WIDTH 1
#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK 0x80u
#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT 7
#define USB_STALL_IH_DIS_STALL_I_DIS15_WIDTH 1
#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
/* STALL_OL_DIS Bit Fields */
#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK 0x1u
#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT 0
#define USB_STALL_OL_DIS_STALL_O_DIS0_WIDTH 1
#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK 0x2u
#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT 1
#define USB_STALL_OL_DIS_STALL_O_DIS1_WIDTH 1
#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK 0x4u
#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT 2
#define USB_STALL_OL_DIS_STALL_O_DIS2_WIDTH 1
#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK 0x8u
#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT 3
#define USB_STALL_OL_DIS_STALL_O_DIS3_WIDTH 1
#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK 0x10u
#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT 4
#define USB_STALL_OL_DIS_STALL_O_DIS4_WIDTH 1
#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK 0x20u
#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT 5
#define USB_STALL_OL_DIS_STALL_O_DIS5_WIDTH 1
#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK 0x40u
#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT 6
#define USB_STALL_OL_DIS_STALL_O_DIS6_WIDTH 1
#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK 0x80u
#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT 7
#define USB_STALL_OL_DIS_STALL_O_DIS7_WIDTH 1
#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
/* STALL_OH_DIS Bit Fields */
#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK 0x1u
#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT 0
#define USB_STALL_OH_DIS_STALL_O_DIS8_WIDTH 1
#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK 0x2u
#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT 1
#define USB_STALL_OH_DIS_STALL_O_DIS9_WIDTH 1
#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK 0x4u
#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT 2
#define USB_STALL_OH_DIS_STALL_O_DIS10_WIDTH 1
#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK 0x8u
#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT 3
#define USB_STALL_OH_DIS_STALL_O_DIS11_WIDTH 1
#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK 0x10u
#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT 4
#define USB_STALL_OH_DIS_STALL_O_DIS12_WIDTH 1
#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK 0x20u
#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT 5
#define USB_STALL_OH_DIS_STALL_O_DIS13_WIDTH 1
#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK 0x40u
#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT 6
#define USB_STALL_OH_DIS_STALL_O_DIS14_WIDTH 1
#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK 0x80u
#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT 7
#define USB_STALL_OH_DIS_STALL_O_DIS15_WIDTH 1
#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
/* CLK_RECOVER_CTRL Bit Fields */
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
/* CLK_RECOVER_IRC_EN Bit Fields */
#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH 1
#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH 1
#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
/* CLK_RECOVER_INT_EN Bit Fields */
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_WIDTH 1
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT))&USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
/* CLK_RECOVER_INT_STATUS Bit Fields */
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
/*!
* @}
*/ /* end of group USB_Register_Masks */
/* USB - Peripheral instance base addresses */
/** Peripheral USB0 base address */
#define USB0_BASE (0x40072000u)
/** Peripheral USB0 base pointer */
#define USB0 ((USB_Type *)USB0_BASE)
#define USB0_BASE_PTR (USB0)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { USB0_BASE }
/** Array initializer of USB peripheral base pointers */
#define USB_BASE_PTRS { USB0 }
/* ----------------------------------------------------------------------------
-- USB - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
* @{
*/
/* USB - Register instance definitions */
/* USB0 */
#define USB0_PERID USB_PERID_REG(USB0)
#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
#define USB0_REV USB_REV_REG(USB0)
#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
#define USB0_OTGICR USB_OTGICR_REG(USB0)
#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
#define USB0_ISTAT USB_ISTAT_REG(USB0)
#define USB0_INTEN USB_INTEN_REG(USB0)
#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
#define USB0_ERREN USB_ERREN_REG(USB0)
#define USB0_STAT USB_STAT_REG(USB0)
#define USB0_CTL USB_CTL_REG(USB0)
#define USB0_ADDR USB_ADDR_REG(USB0)
#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
#define USB0_TOKEN USB_TOKEN_REG(USB0)
#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
#define USB0_CONTROL USB_CONTROL_REG(USB0)
#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
#define USB0_MISCCTRL USB_MISCCTRL_REG(USB0)
#define USB0_STALL_IL_DIS USB_STALL_IL_DIS_REG(USB0)
#define USB0_STALL_IH_DIS USB_STALL_IH_DIS_REG(USB0)
#define USB0_STALL_OL_DIS USB_STALL_OL_DIS_REG(USB0)
#define USB0_STALL_OH_DIS USB_STALL_OH_DIS_REG(USB0)
#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
#define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
/* USB - Register array accessors */
#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
/*!
* @}
*/ /* end of group USB_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- WDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
* @{
*/
/** WDOG - Register Layout Typedef */
typedef struct {
__IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
__IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
__IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
__IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
__IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
__IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
__IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
__IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
__IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
__IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
__IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
__IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
} WDOG_Type, *WDOG_MemMapPtr;
/* ----------------------------------------------------------------------------
-- WDOG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
* @{
*/
/* WDOG - Register accessors */
#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
#define WDOG_WINH_REG(base) ((base)->WINH)
#define WDOG_WINL_REG(base) ((base)->WINL)
#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
#define WDOG_PRESC_REG(base) ((base)->PRESC)
/*!
* @}
*/ /* end of group WDOG_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/* STCTRLH Bit Fields */
#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
#define WDOG_STCTRLH_WDOGEN_SHIFT 0
#define WDOG_STCTRLH_WDOGEN_WIDTH 1
#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
#define WDOG_STCTRLH_CLKSRC_SHIFT 1
#define WDOG_STCTRLH_CLKSRC_WIDTH 1
#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
#define WDOG_STCTRLH_IRQRSTEN_WIDTH 1
#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
#define WDOG_STCTRLH_WINEN_MASK 0x8u
#define WDOG_STCTRLH_WINEN_SHIFT 3
#define WDOG_STCTRLH_WINEN_WIDTH 1
#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH 1
#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
#define WDOG_STCTRLH_DBGEN_MASK 0x20u
#define WDOG_STCTRLH_DBGEN_SHIFT 5
#define WDOG_STCTRLH_DBGEN_WIDTH 1
#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
#define WDOG_STCTRLH_STOPEN_MASK 0x40u
#define WDOG_STCTRLH_STOPEN_SHIFT 6
#define WDOG_STCTRLH_STOPEN_WIDTH 1
#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
#define WDOG_STCTRLH_WAITEN_MASK 0x80u
#define WDOG_STCTRLH_WAITEN_SHIFT 7
#define WDOG_STCTRLH_WAITEN_WIDTH 1
#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
#define WDOG_STCTRLH_TESTWDOG_WIDTH 1
#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
#define WDOG_STCTRLH_TESTSEL_SHIFT 11
#define WDOG_STCTRLH_TESTSEL_WIDTH 1
#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
#define WDOG_STCTRLH_BYTESEL_SHIFT 12
#define WDOG_STCTRLH_BYTESEL_WIDTH 2
#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
#define WDOG_STCTRLH_DISTESTWDOG_WIDTH 1
#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
/* STCTRLL Bit Fields */
#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
#define WDOG_STCTRLL_INTFLG_SHIFT 15
#define WDOG_STCTRLL_INTFLG_WIDTH 1
#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
/* TOVALH Bit Fields */
#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
#define WDOG_TOVALH_TOVALHIGH_WIDTH 16
#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
/* TOVALL Bit Fields */
#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
#define WDOG_TOVALL_TOVALLOW_SHIFT 0
#define WDOG_TOVALL_TOVALLOW_WIDTH 16
#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
/* WINH Bit Fields */
#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
#define WDOG_WINH_WINHIGH_SHIFT 0
#define WDOG_WINH_WINHIGH_WIDTH 16
#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
/* WINL Bit Fields */
#define WDOG_WINL_WINLOW_MASK 0xFFFFu
#define WDOG_WINL_WINLOW_SHIFT 0
#define WDOG_WINL_WINLOW_WIDTH 16
#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
/* REFRESH Bit Fields */
#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
#define WDOG_REFRESH_WDOGREFRESH_WIDTH 16
#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
/* UNLOCK Bit Fields */
#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH 16
#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
/* TMROUTH Bit Fields */
#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH 16
#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
/* TMROUTL Bit Fields */
#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH 16
#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
/* RSTCNT Bit Fields */
#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
#define WDOG_RSTCNT_RSTCNT_SHIFT 0
#define WDOG_RSTCNT_RSTCNT_WIDTH 16
#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
/* PRESC Bit Fields */
#define WDOG_PRESC_PRESCVAL_MASK 0x700u
#define WDOG_PRESC_PRESCVAL_SHIFT 8
#define WDOG_PRESC_PRESCVAL_WIDTH 3
#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
/*!
* @}
*/ /* end of group WDOG_Register_Masks */
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG base address */
#define WDOG_BASE (0x40052000u)
/** Peripheral WDOG base pointer */
#define WDOG ((WDOG_Type *)WDOG_BASE)
#define WDOG_BASE_PTR (WDOG)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { WDOG_BASE }
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS { WDOG }
/* ----------------------------------------------------------------------------
-- WDOG - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
* @{
*/
/* WDOG - Register instance definitions */
/* WDOG */
#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
#define WDOG_WINH WDOG_WINH_REG(WDOG)
#define WDOG_WINL WDOG_WINL_REG(WDOG)
#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
/*!
* @}
*/ /* end of group WDOG_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma pop
#elif defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- Backward Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
* @{
*/
#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
#define ADC_BASES ADC_BASE_PTRS
#define CMP_BASES CMP_BASE_PTRS
#define CRC_BASES CRC_BASE_PTRS
#define DAC_BASES DAC_BASE_PTRS
#define DMA_BASES DMA_BASE_PTRS
#define DMAMUX_BASES DMAMUX_BASE_PTRS
#define EWM_BASES EWM_BASE_PTRS
#define FMC_BASES FMC_BASE_PTRS
#define FTFA_BASES FTFA_BASE_PTRS
#define FTM_BASES FTM_BASE_PTRS
#define GPIO_BASES GPIO_BASE_PTRS
#define I2C_BASES I2C_BASE_PTRS
#define I2S_BASES I2S_BASE_PTRS
#define LLWU_BASES LLWU_BASE_PTRS
#define LPTMR_BASES LPTMR_BASE_PTRS
#define LPUART_BASES LPUART_BASE_PTRS
#define MCG_BASES MCG_BASE_PTRS
#define MCM_BASES MCM_BASE_PTRS
#define NV_BASES NV_BASE_PTRS
#define OSC_BASES OSC_BASE_PTRS
#define PDB_BASES PDB_BASE_PTRS
#define PIT_BASES PIT_BASE_PTRS
#define PMC_BASES PMC_BASE_PTRS
#define PORT_BASES PORT_BASE_PTRS
#define RCM_BASES RCM_BASE_PTRS
#define RFSYS_BASES RFSYS_BASE_PTRS
#define RFVBAT_BASES RFVBAT_BASE_PTRS
#define RNG_BASES RNG_BASE_PTRS
#define RTC_BASES RTC_BASE_PTRS
#define SIM_BASES SIM_BASE_PTRS
#define SMC_BASES SMC_BASE_PTRS
#define SPI_BASES SPI_BASE_PTRS
#define UART_BASES UART_BASE_PTRS
#define USB_BASES USB_BASE_PTRS
#define VREF_BASES VREF_BASE_PTRS
#define WDOG_BASES WDOG_BASE_PTRS
#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
#define Watchdog_IRQn WDOG_EWM_IRQn
#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
#define LPTimer_IRQn LPTMR0_IRQn
#define LPTimer_IRQHandler LPTMR0_IRQHandler
#define LLW_IRQn LLWU_IRQn
#define LLW_IRQHandler LLWU_IRQHandler
/*!
* @}
*/ /* end of group Backward_Compatibility_Symbols */
#else /* #if !defined(MKS22F25612_H_) */
/* There is already included the same memory map. Check if it is compatible (has the same major version) */
#if (MCU_MEM_MAP_VERSION != 0x0200u)
#if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
#warning There are included two not compatible versions of memory maps. Please check possible differences.
#endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
#endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
#endif /* #if !defined(MKS22F25612_H_) */
/* MKS22F25612.h, eof. */
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/test/usbd_hid_test.c
|
#include "usbd_hid.h"
extern struct usbd_t usbd;
uint32_t data_send_notify(uint8_t ep)
{
printf("ep%d: data_send_notify\r\n", ep);
return CH_OK;
}
uint32_t hid_data_received(uint8_t ep, uint8_t *buf, uint32_t len)
{
int i;
printf("ep%d: received, size:%d\r\n", ep, len);
for(i=0; i<len; i++)
{
printf("%02X ", buf[i]);
}
printf("\r\n");
return CH_OK;
}
struct usbd_hid_callback_t hid_cb =
{
data_send_notify,
hid_data_received,
};
void usbd_hid_test(struct usbd_t *h)
{
usbd_hid_set_cb(&hid_cb);
usbd_hid_init(h, 2);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/src/system_MKL03Z4.c
|
<gh_stars>1-10
/*
** ###################################################################
** Processors: MKL03Z32CAF4
** MKL03Z32VFG4
** MKL03Z16VFG4
** MKL03Z8VFG4
** MKL03Z32VFK4
** MKL03Z16VFK4
** MKL03Z8VFK4
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL03P24M48SF0RM, Rev 2, Apr 2014
** Version: rev. 1.2, 2014-04-30
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2013-12-11)
** Initial version.
** - rev. 1.1 (2014-04-16)
** Update of the I2C module (SMBUS feature).
** Update of the MCG_Light module.
** Added register file system (RFSYS).
** - rev. 1.2 (2014-04-30)
** PEx compatibility macros has been added.
**
** ###################################################################
*/
/*!
* @file MKL03Z4
* @version 1.2
* @date 2014-04-30
* @brief Device specific configuration file for MKL03Z4 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MKL03Z4.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if (DISABLE_WDOG)
/* Disable the COP module */
/* SIM_COPC: COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
SIM->COPC = (uint32_t)0x00u;
#endif /* (DISABLE_WDOG) */
#if (CLOCK_SETUP == 0)
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
/* MCG->SC: FCRDIV=1 */
MCG->SC = MCG_SC_FCRDIV(0x01); /* Set the LIRC1 divider*/
/* MCG->MC: HIRC=0,LIRC_DIV2=0 */
MCG->MC = MCG_MC_LIRC_DIV2(0x00); /* Set the LIRC2 divider*/
/* OSC->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = (uint32_t)0x00u; /* Disable External reference */
/* MCG->C2: EREFS0=0,IRCS=1 */
MCG->C2 = MCG_C2_IRCS_MASK; /* Enable LIRC 8MHz */
/* Switch to LIRC 8MHz Mode */
/* MCG->C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x01) |
MCG_C1_IRCLKEN_MASK; /* Enable LIRC and select LIRC as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x04u) {} /* Check that the clock source is the LIRC clock. */
#elif (CLOCK_SETUP == 1)
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Set system prescalers */
/* MCG->SC: FCRDIV=1 */
MCG->SC = MCG_SC_FCRDIV(0x01); /* LIRC1 divider not used - leave the default value*/
/* MCG->MC: HIRC=1,LIRC_DIV2=0 */
MCG->MC = MCG_MC_HIRCEN_MASK; /* Enable HIRC clock source*/
/* OSC->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = (uint32_t)0x00u; /* Disable External reference */
/* MCG->C2: EREFS0=0,IRCS=1 */
MCG->C2 = MCG_C2_IRCS_MASK; /* Not used - leave default value */
/* Switch to HIRC Mode */
/* MCG->C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) |
MCG_C1_IRCLKEN_MASK; /* Leave LIRC enabled and select HIRC as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x00u) {} /* Check that the clock source is the HIRC clock. */
#elif (CLOCK_SETUP == 2)
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for port to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x00); /* Set system prescalers */
/* PORTA_PCR3: ISF=0,MUX=0 */
PORTA->PCR[3] &= (uint32_t)~(uint32_t)(PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07));
/* PORTA_PCR4: ISF=0,MUX=0 */
PORTA->PCR[4] &= (uint32_t)~(uint32_t)(PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07));
/* MCG->SC: FCRDIV=1 */
MCG->SC = MCG_SC_FCRDIV(0x01); /* LIRC1 divider not used - leave the default value*/
/* MCG->MC: HIRC=0,LIRC_DIV2=0 */
MCG->MC = MCG_MC_LIRC_DIV2(0x00); /* Not used - leave the default value */
/* MCG->C2: EREFS0=1,IRCS=1 */
MCG->C2 = MCG_C2_EREFS0_MASK | MCG_C2_IRCS_MASK; /* Select external crystal, for LIRC - leave default value */
/* OSC->CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK; /* Enable External reference */
/* Switch to EXT Mode */
/* MCG->C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x02); /* Disable LIRC and select EXT as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x08u) {} /* Check that the clock source is the EXT clock. */
#elif (CLOCK_SETUP == 3)
/* MCG->MC: HIRC=1 */
MCG->MC |= MCG_MC_HIRCEN_MASK; /* Enable HIRC clock source*/
/* MCG->C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) |
MCG_C1_IRCLKEN_MASK; /* Leave LIRC enabled and select HIRC as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x00u) {} /* Check that the clock source is the HIRC clock. */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Set system prescalers */
/* MCG->SC: FCRDIV=0 */
MCG->SC = MCG_SC_FCRDIV(0x00); /* Set the LIRC1 divider to 1*/
/* MCG->MC: HIRC=0,LIRC_DIV2=0 */
MCG->MC = MCG_MC_LIRC_DIV2(0x00); /* Set the LIRC2 divider to 1 */
/* OSC->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = (uint32_t)0x00u; /* Disable External reference */
/* MCG->C2: EREFS0=0,IRCS=0 */
MCG->C2 = (uint32_t)0x00u; /* Enable LIRC 2MHz */
/* Switch to LIRC 2MHz Mode */
/* MCG->C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x01) |
MCG_C1_IRCLKEN_MASK; /* Enable LIRC and select LIRC as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x04u) {} /* Check that the clock source is the LIRC clock. */
#endif
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t ICSOUTClock; /* Variable to store output clock frequency of the ICS module */
uint8_t Divider;
if ((MCG->S & MCG_S_CLKST_MASK) == 0x04u) {
/* LIRC reference clock is selected */
ICSOUTClock = CPU_INT_SLOW_CLK_HZ;
Divider = (uint8_t)(1u << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
ICSOUTClock = (ICSOUTClock / Divider); /* Calculate the divided LIRC clock */
} else if ((MCG->S & MCG_S_CLKST_MASK) == 0x0u) {
/* HIRC reference clock is selected */
ICSOUTClock = CPU_INT_FAST_CLK_HZ;
} else if ((MCG->S & MCG_S_CLKST_MASK) == 0x80u) {
/* External reference clock is selected */
ICSOUTClock = CPU_XTAL_CLK_HZ;
} else {
/* Reserved value */
return;
}
SystemCoreClock = (ICSOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/LPC82x.h
|
/****************************************************************************
* $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
* Project: NXP LPC8xx software example
*
* Description:
* CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
* NXP LPC800 Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*
* modified by ARM 02.09.2019
****************************************************************************/
#ifndef __LPC8xx_H__
#define __LPC8xx_H__
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
This file defines all structures and symbols for LPC8xx:
- Registers and bitfields
- peripheral base address
- PIO definitions
@{
*/
#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
Configuration of the Cortex-M0+ Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** LPC8xx Specific Interrupt Numbers ********************************************************/
SPI0_IRQn = 0, /*!< SPI0 */
SPI1_IRQn = 1, /*!< SPI1 */
Reserved0_IRQn = 2, /*!< Reserved Interrupt */
UART0_IRQn = 3, /*!< USART0 */
UART1_IRQn = 4, /*!< USART1 */
UART2_IRQn = 5, /*!< USART2 */
Reserved1_IRQn = 6, /*!< Reserved Interrupt */
I2C1_IRQn = 7, /*!< I2C1 */
I2C0_IRQn = 8, /*!< I2C0 */
SCT_IRQn = 9, /*!< SCT */
MRT_IRQn = 10, /*!< MRT */
CMP_IRQn = 11, /*!< CMP */
WDT_IRQn = 12, /*!< WDT */
BOD_IRQn = 13, /*!< BOD */
FLASH_IRQn = 14, /*!< FLASH */
WKT_IRQn = 15, /*!< WKT Interrupt */
ADC_SEQA_IRQn = 16, /*!< ADC Seq. A */
ADC_SEQB_IRQn = 17, /*!< ADC Seq. B */
ADC_THCMP_IRQn = 18, /*!< ADC Thresh Comp */
ADC_OVR_IRQn = 19, /*!< ADC overrun */
DMA_IRQn = 20, /*!< DMA */
I2C2_IRQn = 21, /*!< I2C2 */
I2C3_IRQn = 22, /*!< I2C3 */
Reserved11_IRQn = 23, /*!< Reserved Interrupt */
PININT0_IRQn = 24, /*!< External Interrupt 0 */
PININT1_IRQn = 25, /*!< External Interrupt 1 */
PININT2_IRQn = 26, /*!< External Interrupt 2 */
PININT3_IRQn = 27, /*!< External Interrupt 3 */
PININT4_IRQn = 28, /*!< External Interrupt 4 */
PININT5_IRQn = 29, /*!< External Interrupt 5 */
PININT6_IRQn = 30, /*!< External Interrupt 6 */
PININT7_IRQn = 31, /*!< External Interrupt 7 */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0PLUS_REV 0x0001
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/*@}*/ /* end of group LPC8xx_CMSIS */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
#include "system_LPC8xx.h" /* System Header */
/******************************************************************************/
/* Device Specific Peripheral Registers structures */
/******************************************************************************/
/* ARM 02.09.2019 */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
# warning Not supported compiler type
#endif
//------------- System Control (SYSCON) --------------------------------------
typedef struct
{
__IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
__IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
__IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
__IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
uint32_t RESERVED0[4];
__IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
__IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
__IO uint32_t IRCCTRL; // 0x28
uint32_t RESERVED1;
__IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
uint32_t RESERVED2[3];
__IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
__IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
uint32_t RESERVED3[10];
__IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
__IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
__IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
uint32_t RESERVED4[1];
__IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
uint32_t RESERVED5[4];
__IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
uint32_t RESERVED6[18];
__IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
__IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
__IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
uint32_t RESERVED7;
__IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
__IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
uint32_t RESERVED8[1];
__IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
__IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
uint32_t RESERVED9[12];
__IO uint32_t IOCONCLKDIV6; // 0x134
__IO uint32_t IOCONCLKDIV5; // 0x138
__IO uint32_t IOCONCLKDIV4; // 0x13c
__IO uint32_t IOCONCLKDIV3; // 0x140
__IO uint32_t IOCONCLKDIV2; // 0x144
__IO uint32_t IOCONCLKDIV1; // 0x148
__IO uint32_t IOCONCLKDIV0; // 0x14c
__IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
__IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
uint32_t RESERVED10[6];
__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
__IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
__IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
uint32_t RESERVED11[27];
__IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
uint32_t RESERVED12[3];
__IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
uint32_t RESERVED13[6];
__IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
__IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
__IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
uint32_t RESERVED14[111];
__I uint32_t DEVICE_ID; // 0x3f8
} LPC_SYSCON_TypeDef;
// ---------------- IOCON ----------------
typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
__IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
__IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
__IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
__IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
__IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
__IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
__IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
__IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
__IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
__IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
__IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
__IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
__IO uint32_t Reserved0; /*!< (@ 0x40044030) Reserved */
__IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
__IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
__IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
__IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
__IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
__IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
__IO uint32_t Reserved1; // 0x4c
__IO uint32_t PIO0_28; // 0x50
__IO uint32_t PIO0_27; // 0x54
__IO uint32_t PIO0_26; // 0x58
__IO uint32_t PIO0_25; // 0x5c
__IO uint32_t PIO0_24; // 0x60
__IO uint32_t PIO0_23; // 0x64
__IO uint32_t PIO0_22; // 0x68
__IO uint32_t PIO0_21; // 0x6c
__IO uint32_t PIO0_20; // 0x70
__IO uint32_t PIO0_19; // 0x74
__IO uint32_t PIO0_18; // 0x78
} LPC_IOCON_TypeDef;
// ================================================================================
// ================ FLASHCTRL ================
// ================================================================================
typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
__I uint32_t RESERVED0[4];
__IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
__I uint32_t RESERVED1[3];
__IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
__IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
__I uint32_t RESERVED2;
__I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */
} LPC_FLASHCTRL_TypeDef;
//------------- Power Management Unit (PMU) --------------------------
typedef struct
{
__IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
__IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
__IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
__IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
__IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
__IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
} LPC_PMU_TypeDef;
//------------- Switch Matrix (SWM) --------------------------
typedef struct
{
union {
__IO uint32_t PINASSIGN[12];
struct {
__IO uint32_t PINASSIGN0;
__IO uint32_t PINASSIGN1;
__IO uint32_t PINASSIGN2;
__IO uint32_t PINASSIGN3;
__IO uint32_t PINASSIGN4;
__IO uint32_t PINASSIGN5;
__IO uint32_t PINASSIGN6;
__IO uint32_t PINASSIGN7;
__IO uint32_t PINASSIGN8;
__IO uint32_t PINASSIGN9;
__IO uint32_t PINASSIGN10;
__IO uint32_t PINASSIGN11;
};
};
__I uint32_t RESERVED0[100];
__IO uint32_t PINENABLE0;
} LPC_SWM_TypeDef;
// ------------------------------------------------------------------------------------------------
// ----- General Purpose I/O (GPIO) -----
// ------------------------------------------------------------------------------------------------
typedef struct {
__IO uint8_t B0[29]; // 0x0 - 0x1c Byte pin registers P0.0 - P0.28
__I uint8_t RESERVED0[4067];
__IO uint32_t W0[29]; // 0x1000 - 0x1074 Word pin registers
uint32_t RESERVED1[995];
__IO uint32_t DIR0; // 0x2000
uint32_t RESERVED2[31];
__IO uint32_t MASK0; // 0x2080
uint32_t RESERVED3[31];
__IO uint32_t PIN0; // 0x2100
uint32_t RESERVED4[31];
__IO uint32_t MPIN0; // 0x2180
uint32_t RESERVED5[31];
__IO uint32_t SET0; // 0x2200
uint32_t RESERVED6[31];
__O uint32_t CLR0; // 0x2280
uint32_t RESERVED7[31];
__O uint32_t NOT0; // 0x2300
uint32_t RESERVED8[31];
__O uint32_t DIRSET0; // 0x2380
uint32_t RESERVED9[31];
__O uint32_t DIRCLR0; // 0x2400
uint32_t RESERVED10[31];
__O uint32_t DIRNOT0; // 0x2480
} LPC_GPIO_PORT_TypeDef;
// ------------------------------------------------------------------------------------------------
// ----- Pin Interrupts and Pattern Match (PIN_INT) -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
__IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
__IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
__IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
__IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
__IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
} LPC_PIN_INT_TypeDef;
//------------- CRC Engine (CRC) -----------------------------------------
typedef struct
{
__IO uint32_t MODE;
__IO uint32_t SEED;
union {
__I uint32_t SUM;
__O uint32_t WR_DATA;
};
} LPC_CRC_TypeDef;
//------------- Comparator (CMP) --------------------------------------------------
typedef struct { /*!< (@ 0x40024000) CMP Structure */
__IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
__IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
} LPC_CMP_TypeDef;
//------------- Self Wakeup Timer (WKT) --------------------------------------------------
typedef struct { /*!< (@ 0x40028000) WKT Structure */
__IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
uint32_t Reserved[2];
__IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
} LPC_WKT_TypeDef;
//------------- Multi-Rate Timer(MRT) --------------------------------------------------
typedef struct {
__IO uint32_t INTVAL;
__IO uint32_t TIMER;
__IO uint32_t CTRL;
__IO uint32_t STAT;
} MRT_Channel_cfg_Type;
typedef struct {
MRT_Channel_cfg_Type Channel[4];
uint32_t Reserved0[45]; // Address offsets = 0x40 - 0xF0
__IO uint32_t IDLE_CH;
__IO uint32_t IRQ_FLAG;
} LPC_MRT_TypeDef;
//------------- Universal Asynchronous Receiver Transmitter (USART) -----------
typedef struct
{
__IO uint32_t CFG;
__IO uint32_t CTL;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR;
__I uint32_t RXDAT;
__I uint32_t RXDATSTAT;
__IO uint32_t TXDAT;
__IO uint32_t BRG;
__I uint32_t INTSTAT;
__IO uint32_t OSR;
__IO uint32_t ADDR;
} LPC_USART_TypeDef;
//------------- SPI -----------------------
typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t DLY;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR; /* 0x10 */
__I uint32_t RXDAT;
__IO uint32_t TXDATCTL;
__IO uint32_t TXDAT;
__IO uint32_t TXCTL; /* 0x20 */
__IO uint32_t DIV;
__I uint32_t INTSTAT;
} LPC_SPI_TypeDef;
//------------- Inter-Integrated Circuit (I2C) -------------------------------
typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR;
__IO uint32_t TIMEOUT; /* 0x10 */
union {
__IO uint32_t CLKDIV;
__IO uint32_t DIV;
};
__IO uint32_t INTSTAT;
uint32_t Reserved0[1];
__IO uint32_t MSTCTL; /* 0x20 */
__IO uint32_t MSTTIME;
__IO uint32_t MSTDAT;
uint32_t Reserved1[5];
__IO uint32_t SLVCTL; /* 0x40 */
__IO uint32_t SLVDAT;
__IO uint32_t SLVADR0;
__IO uint32_t SLVADR1;
__IO uint32_t SLVADR2; /* 0x50 */
__IO uint32_t SLVADR3;
__IO uint32_t SLVQUAL0;
uint32_t Reserved2[9];
__I uint32_t MONRXDAT; /* 0x80 */
} LPC_I2C_TypeDef;
// ================================================================================
// == preferred SCT structure (fully populated with array access) =============
// ================================================================================
#define CONFIG_SCT_nEV (8) // Number of events
#define CONFIG_SCT_nRG (8) // Number of match/compare registers
#define CONFIG_SCT_nOU (6) // Number of outputs
typedef struct {
__IO uint32_t CONFIG; // 0x0
union {
__IO uint32_t CTRL; // 0x4
struct {
__IO uint16_t CTRL_L;
__IO uint16_t CTRL_H;
};
};
union {
__IO uint32_t LIMIT; // 0x8
struct {
__IO uint16_t LIMIT_L;
__IO uint16_t LIMIT_H;
};
};
union {
__IO uint32_t HALT; // 0xc
struct {
__IO uint16_t HALT_L;
__IO uint16_t HALT_H;
};
};
union {
__IO uint32_t STOP; // 0x10
struct {
__IO uint16_t STOP_L;
__IO uint16_t STOP_H;
};
};
union {
__IO uint32_t START; // 0x14
struct {
__IO uint16_t START_L;
__IO uint16_t START_H;
};
};
uint32_t RESERVED1[10];
union {
__IO uint32_t COUNT; // 0x40
struct {
__IO uint16_t COUNT_L;
__IO uint16_t COUNT_H;
};
};
union {
__IO uint32_t STATE; // 0x44
struct {
__IO uint16_t STATE_L;
__IO uint16_t STATE_H;
};
};
__I uint32_t INPUT; // 0x48
union {
__IO uint32_t REGMODE; // 0x4c
struct {
__IO uint16_t REGMODE_L;
__IO uint16_t REGMODE_H;
};
};
__IO uint32_t OUTPUT; // 0x50
__IO uint32_t OUTPUTDIRCTRL; // 0x54
__IO uint32_t RES; // 0x58
__IO uint32_t DMAREQ0; // 0x5c
__IO uint32_t DMAREQ1; // 0x60
uint32_t RESERVED2[35]; // 0x64 - 0xec
__IO uint32_t EVEN; // 0xf0
__IO uint32_t EVFLAG; // 0xf4
__IO uint32_t CONEN; // 0xf8
__IO uint32_t CONFLAG; // 0xfc
union { // Match / Capture 0x100 - 0x13c
__IO union {
uint32_t U; // MATCH[i].U Unified 32-bit register
struct {
uint16_t L; // MATCH[i].L Access to L value
uint16_t H; // MATCH[i].H Access to H value
};
} MATCH[CONFIG_SCT_nRG];
__I union {
uint32_t U; // CAP[i].U Unified 32-bit register
struct {
uint16_t L; // CAP[i].L Access to L value
uint16_t H; // CAP[i].H Access to H value
};
} CAP[CONFIG_SCT_nRG];
};
uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; // ...-0x17C reserved
union {
__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; // 0x180-... Match Value L counter
__I uint16_t CAP_L[CONFIG_SCT_nRG]; // 0x180-... Capture Value L counter
};
uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; // ...-0x1BE reserved
union {
__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; // 0x1C0-... Match Value H counter
__I uint16_t CAP_H[CONFIG_SCT_nRG]; // 0x1C0-... Capture Value H counter
};
uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; // ...-0x1FE reserved
union {
__IO union { // 0x200-... Match Reload / Capture Control value
uint32_t U; // MATCHREL[i].U Unified 32-bit register
struct {
uint16_t L; // MATCHREL[i].L Access to L value
uint16_t H; // MATCHREL[i].H Access to H value
};
} MATCHREL[CONFIG_SCT_nRG];
__IO union {
uint32_t U; // CAPCTRL[i].U Unified 32-bit register
struct {
uint16_t L; // CAPCTRL[i].L Access to L value
uint16_t H; // SCTCAPCTRL[i].H Access to H value
};
} CAPCTRL[CONFIG_SCT_nRG];
};
uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; // ...-0x27C reserved
union {
__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; // 0x280-... Match Reload value L counter
__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; // 0x280-... Capture Control value L counter
};
uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; // ...-0x2BE reserved
union {
__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; // 0x2C0-... Match Reload value H counter
__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; // 0x2C0-... Capture Control value H counter
};
uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; // ...-0x2FE reserved
__IO struct { // 0x300-0x3FC EVENT[i].STATE / EVENT[i].CTRL
uint32_t STATE;
uint32_t CTRL;
} EVENT[CONFIG_SCT_nEV];
uint32_t RESERVED9[128 - (2 * CONFIG_SCT_nEV)]; // ...-0x4FC reserved
__IO struct { // 0x500-0x57C OUT[n].SET / OUT[n].CLR
uint32_t SET; // Output n Set Register
uint32_t CLR; // Output n Clear Register
} OUT[CONFIG_SCT_nOU];
uint32_t RESERVED10[((0x300 / 4) - 1) - (2 * CONFIG_SCT_nOU)]; // ...-0x7F8 reserved
__I uint32_t MODULECONTENT; // 0x7FC Module Content
} LPC_SCT_TypeDef;
// ================================================================================
// == optional SCT structure (user manual verbatim, no array access) =============
// ================================================================================
/*
typedef struct { //!< (@ 0x50004000) SCT Structure
__IO uint32_t CONFIG; //!< (@ 0x50004000) SCT configuration register
__IO uint32_t CTRL; //!< (@ 0x50004004) SCT control register
__IO uint32_t LIMIT; //!< (@ 0x50004008) SCT limit register
__IO uint32_t HALT; //!< (@ 0x5000400C) SCT halt condition register
__IO uint32_t STOP; //!< (@ 0x50004010) SCT stop condition register
__IO uint32_t START; //!< (@ 0x50004014) SCT start condition register
__I uint32_t RESERVED0[10];
__IO uint32_t COUNT; //!< (@ 0x50004040) SCT counter register
__IO uint32_t STATE; //!< (@ 0x50004044) SCT state register
__I uint32_t INPUT; //!< (@ 0x50004048) SCT input register
__IO uint32_t REGMODE; //!< (@ 0x5000404C) SCT match/capture registers mode register
__IO uint32_t OUTPUT; //!< (@ 0x50004050) SCT output register
__IO uint32_t OUTPUTDIRCTRL; //!< (@ 0x50004054) SCT output counter direction control register
__IO uint32_t RES; //!< (@ 0x50004058) SCT conflict resolution register
__IO uint32_t DMAREQ0; //!< (@ 0x5000405C) SCT DMA request 0 register
__IO uint32_t DMAREQ1; //!< (@ 0x50004060) SCT DMA request 1 register
__I uint32_t RESERVED1[35];
__IO uint32_t EVEN; //!< (@ 0x500040F0) SCT event enable register
__IO uint32_t EVFLAG; //!< (@ 0x500040F4) SCT event flag register
__IO uint32_t CONEN; //!< (@ 0x500040F8) SCT conflict enable register
__IO uint32_t CONFLAG; //!< (@ 0x500040FC) SCT conflict flag register
union {
__IO uint32_t CAP0; //!< (@ 0x50004100) SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1
__IO uint32_t MATCH0; //!< (@ 0x50004100) SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0
};
union {
__IO uint32_t CAP1; //!< (@ 0x50004104) SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1
__IO uint32_t MATCH1; //!< (@ 0x50004104) SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0
};
union {
__IO uint32_t CAP2; //!< (@ 0x50004108) SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1
__IO uint32_t MATCH2; //!< (@ 0x50004108) SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0
};
union {
__IO uint32_t MATCH3; //!< (@ 0x5000410C) SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0
__IO uint32_t CAP3; //!< (@ 0x5000410C) SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1
};
union {
__IO uint32_t CAP4; //!< (@ 0x50004110) SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1
__IO uint32_t MATCH4; //!< (@ 0x50004110) SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0
};
union {
__IO uint32_t MATCH5; //!< (@ 0x50004114) SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0
__IO uint32_t CAP5; //!< (@ 0x50004114) SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1
};
union {
__IO uint32_t CAP6; //!< (@ 0x50004118) SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1
__IO uint32_t MATCH6; //!< (@ 0x50004118) SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0
};
union {
__IO uint32_t CAP7; //!< (@ 0x5000411C) SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1
__IO uint32_t MATCH7; //!< (@ 0x5000411C) SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0
};
__I uint32_t RESERVED2[56];
union {
__IO uint32_t CAPCTRL0; //!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1
__IO uint32_t MATCHREL0; //!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0
};
union {
__IO uint32_t CAPCTRL1; //!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1
__IO uint32_t MATCHREL1; //!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0
};
union {
__IO uint32_t CAPCTRL2; //!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1
__IO uint32_t MATCHREL2; //!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0
};
union {
__IO uint32_t MATCHREL3; //!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0
__IO uint32_t CAPCTRL3; //!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1
};
union {
__IO uint32_t CAPCTRL4; //!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1
__IO uint32_t MATCHREL4; //!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0
};
union {
__IO uint32_t CAPCTRL5; //!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1
__IO uint32_t MATCHREL5; //!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0
};
union {
__IO uint32_t CAPCTRL6; //!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1
__IO uint32_t MATCHREL6; //!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0
};
union {
__IO uint32_t CAPCTRL7; //!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1
__IO uint32_t MATCHREL7; //!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0
};
__I uint32_t RESERVED3[56];
__IO uint32_t EV0_STATE; //!< (@ 0x50004300) SCT event state register 0
__IO uint32_t EV0_CTRL; //!< (@ 0x50004304) SCT event control register 0
__IO uint32_t EV1_STATE; //!< (@ 0x50004308) SCT event state register 0
__IO uint32_t EV1_CTRL; //!< (@ 0x5000430C) SCT event control register 0
__IO uint32_t EV2_STATE; //!< (@ 0x50004310) SCT event state register 0
__IO uint32_t EV2_CTRL; //!< (@ 0x50004314) SCT event control register 0
__IO uint32_t EV3_STATE; //!< (@ 0x50004318) SCT event state register 0
__IO uint32_t EV3_CTRL; //!< (@ 0x5000431C) SCT event control register 0
__IO uint32_t EV4_STATE; //!< (@ 0x50004320) SCT event state register 0
__IO uint32_t EV4_CTRL; //!< (@ 0x50004324) SCT event control register 0
__IO uint32_t EV5_STATE; //!< (@ 0x50004328) SCT event state register 0
__IO uint32_t EV5_CTRL; //!< (@ 0x5000432C) SCT event control register 0
__IO uint32_t EV6_STATE; //!< (@ 0x50004330) SCT event state register 0
__IO uint32_t EV6_CTRL; //!< (@ 0x50004334) SCT event control register 0
__IO uint32_t EV7_STATE; //!< (@ 0x50004338) SCT event state register 0
__IO uint32_t EV7_CTRL; //!< (@ 0x5000433C) SCT event control register 0
__I uint32_t RESERVED4[112];
__IO uint32_t OUT0_SET; //!< (@ 0x50004500) SCT output 0 set register
__IO uint32_t OUT0_CLR; //!< (@ 0x50004504) SCT output 0 clear register
__IO uint32_t OUT1_SET; //!< (@ 0x50004508) SCT output 0 set register
__IO uint32_t OUT1_CLR; //!< (@ 0x5000450C) SCT output 0 clear register
__IO uint32_t OUT2_SET; //!< (@ 0x50004510) SCT output 0 set register
__IO uint32_t OUT2_CLR; //!< (@ 0x50004514) SCT output 0 clear register
__IO uint32_t OUT3_SET; //!< (@ 0x50004518) SCT output 0 set register
__IO uint32_t OUT3_CLR; //!< (@ 0x5000451C) SCT output 0 clear register
__IO uint32_t OUT4_SET; //!< (@ 0x50004520) SCT output 0 set register
__IO uint32_t OUT4_CLR; //!< (@ 0x50004524) SCT output 0 clear register
__IO uint32_t OUT5_SET; //!< (@ 0x50004528) SCT output 0 set register
__IO uint32_t OUT5_CLR; //!< (@ 0x5000452C) SCT output 0 clear register
} LPC_SCT_TypeDef;
*/
//------------- Windowed Watchdog Timer (WWDT) -----------------------------------------
typedef struct
{
__IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
__IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
__O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
__I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
__IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
__IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
} LPC_WWDT_TypeDef;
//------------- DMA Trigger Mux -----------------------------------------
typedef struct {
__IO uint32_t DMA_ITRIG_INMUX0; // 0x0
__IO uint32_t DMA_ITRIG_INMUX1; // 0x4
__IO uint32_t DMA_ITRIG_INMUX2; // 0x8
__IO uint32_t DMA_ITRIG_INMUX3; // 0xC
__IO uint32_t DMA_ITRIG_INMUX4; // 0x10
__IO uint32_t DMA_ITRIG_INMUX5; // 0x14
__IO uint32_t DMA_ITRIG_INMUX6; // 0x18
__IO uint32_t DMA_ITRIG_INMUX7; // 0x1C
__IO uint32_t DMA_ITRIG_INMUX8; // 0x20
__IO uint32_t DMA_ITRIG_INMUX9; // 0x24
__IO uint32_t DMA_ITRIG_INMUX10; // 0x28
__IO uint32_t DMA_ITRIG_INMUX11; // 0x2C
__IO uint32_t DMA_ITRIG_INMUX12; // 0x30
__IO uint32_t DMA_ITRIG_INMUX13; // 0x34
__IO uint32_t DMA_ITRIG_INMUX14; // 0x38
__IO uint32_t DMA_ITRIG_INMUX15; // 0x3C
__IO uint32_t DMA_ITRIG_INMUX16; // 0x40
__IO uint32_t DMA_ITRIG_INMUX17; // 0x44
} LPC_DMATRIGMUX_TypeDef;
//------------- Input Mux -----------------------------------------
typedef struct {
__IO uint32_t DMA_INMUX_INMUX0; // 0x0
__IO uint32_t DMA_INMUX_INMUX1; // 0x4
uint32_t Preserved[6]; // 0x8 - 0x1C
__IO uint32_t SCT0_INMUX0; // 0x20
__IO uint32_t SCT0_INMUX1; // 0x24
__IO uint32_t SCT0_INMUX2; // 0x28
__IO uint32_t SCT0_INMUX3; // 0x2C
} LPC_INPUTMUX_TypeDef;
/*------------- ADC -----------------------------------------*/
typedef struct {
__IO uint32_t CTRL; // 0x0
uint32_t RESERVED0; // 0x4
__IO uint32_t SEQA_CTRL; // 0x8
__IO uint32_t SEQB_CTRL; // 0xC
__IO uint32_t SEQA_GDAT; // 0x10
__IO uint32_t SEQB_GDAT; // 0x14
uint32_t RESERVED1[2]; // 0x18 - 0x1C
__IO uint32_t DAT[12]; // 0x20 - 0x4C
__IO uint32_t THR0_LOW; // 0x50
__IO uint32_t THR1_LOW; // 0x54
__IO uint32_t THR0_HIGH; // 0x58
__IO uint32_t THR1_HIGH; // 0x5C
__IO uint32_t CHAN_THRSEL; // 0x60
__IO uint32_t INTEN; // 0x64
__IO uint32_t FLAGS; // 0x68
__IO uint32_t TRM; // 0x6C
} LPC_ADC_TypeDef;
/*------------- DMA -----------------------------------------*/
#define NUM_DMA_CHANNELS 18
typedef struct {
__IO uint32_t CFG;
__I uint32_t CTLSTAT;
__IO uint32_t XFERCFG;
__I uint32_t RESERVED;
} LPC_DMA_CHANNEL_T;
typedef struct {
__IO uint32_t CTRL; // 0x0
__I uint32_t INTSTAT; // 0x4
__IO uint32_t SRAMBASE; // 0x8
__I uint32_t RESERVED0[5]; // 0x10 - 0x1C
__IO uint32_t ENABLESET0; // 0x20
__I uint32_t RESERVED1; // 0x24
__O uint32_t ENABLECLR0; // 0x28
__I uint32_t RESERVED2; // 0x2C
__I uint32_t ACTIVE0; // 0x30
__I uint32_t RESERVED3; // 0x34
__I uint32_t BUSY0; // 0x38
__I uint32_t RESERVED4; // 0x3C
__IO uint32_t ERRINT0; // 0x40
__I uint32_t RESERVED5; // 0x44
__IO uint32_t INTENSET0; // 0x48
__I uint32_t RESERVED6; // 0x4C
__O uint32_t INTENCLR0; // 0x50
__I uint32_t RESERVED7; // 0x54
__IO uint32_t INTA0; // 0x58
__I uint32_t RESERVED8; // 0x5C
__IO uint32_t INTB0; // 0x60
__I uint32_t RESERVED9; // 0x64
__O uint32_t SETVALID0; // 0x68
__I uint32_t RESERVED10; // 0x6C
__O uint32_t SETTRIG0; // 0x70
__I uint32_t RESERVED11; // 0x74
__O uint32_t ABORT0; // 0x78
__I uint32_t Absolutely_Nothing[225]; // 0x7C - 0x3FC
LPC_DMA_CHANNEL_T CHANNEL[NUM_DMA_CHANNELS]; // 0x400 - 0x51C
} LPC_DMA_TypeDef;
/* ARM 02.09.2019 */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Base addresses */
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_ROM_BASE (0x1FFF0000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_AHB_BASE (0x50000000UL)
/* APB0 peripherals */
#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
#define LPC_DMATRIGMUX_BASE (LPC_APB0_BASE + 0x28000)
#define LPC_INPUTMUX_BASE (LPC_APB0_BASE + 0x2C000)
#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x50000)
#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x54000)
#define LPC_I2C2_BASE (LPC_APB0_BASE + 0x70000)
#define LPC_I2C3_BASE (LPC_APB0_BASE + 0x74000)
#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
/* AHB peripherals */
#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
#define LPC_DMA_BASE (LPC_AHB_BASE + 0x08000)
#define LPC_GPIO_PORT_BASE (0xA0000000)
#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
/******************************************************************************/
/* Peripheral declarations */
/******************************************************************************/
#define LPC_DMA ((LPC_DMA_TypeDef *) LPC_DMA_BASE )
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_TypeDef *) LPC_DMATRIGMUX_BASE)
#define LPC_INPUTMUX ((LPC_INPUTMUX_TypeDef *) LPC_INPUTMUX_BASE )
#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
#define LPC_I2C3 ((LPC_I2C_TypeDef *) LPC_I2C3_BASE )
#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
#define LPC_SCT0 ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
#ifdef __cplusplus
}
#endif
#endif /* __LPC8xx_H__ */
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/sdif.h
|
<reponame>yandld/lpc_uart_server<filename>mcu_source/Libraries/drivers_lpc/inc/sdif.h<gh_stars>1-10
/**
******************************************************************************
* @file sdif.h
* @author YANDLD
* @version V3.0.0
* @date 2016.5.29
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_SDIF_H__
#define __CH_LIB_SDIF_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
typedef struct
{
uint32_t index; /*!< Command index */
uint32_t argument; /*!< Command argument */
uint32_t response[4U]; /*!< Response for this command */
uint32_t responseType; /*!< Command response type */
uint32_t flags; /*!< Cmd flags */
uint32_t block_size;
uint32_t block_cnt;
uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when recieve the cmd response */
}sdif_cmd_t;
#define MMC_PRODUCT_NAME_BYTES (6U)
typedef struct
{
uint8_t manufacturerID; /*!< Manufacturer ID */
uint16_t applicationID; /*!< OEM/Application ID */
uint8_t productName[MMC_PRODUCT_NAME_BYTES]; /*!< Product name */
uint8_t productVersion; /*!< Product revision */
uint32_t productSerialNumber; /*!< Product serial number */
uint8_t manufacturerData; /*!< Manufacturing date */
} mmc_cid_t;
typedef struct
{
uint8_t csdStructure; /*!< CSD structure [127:126] */
uint8_t dataReadAccessTime1; /*!< Data read access-time-1 [119:112] */
uint8_t dataReadAccessTime2; /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */
uint8_t transferSpeed; /*!< Maximum data transfer rate [103:96] */
uint16_t cardCommandClass; /*!< Card command classes [95:84] */
uint8_t readBlockLength; /*!< Maximum read data block length [83:80] */
uint16_t flags; /*!< Flags in _sd_csd_flag */
uint32_t deviceSize; /*!< Device size [73:62] */
/* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */
uint8_t readCurrentVddMin; /*!< Maximum read current at VDD min [61:59] */
uint8_t readCurrentVddMax; /*!< Maximum read current at VDD max [58:56] */
uint8_t writeCurrentVddMin; /*!< Maximum write current at VDD min [55:53] */
uint8_t writeCurrentVddMax; /*!< Maximum write current at VDD max [52:50] */
uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */
uint8_t eraseSectorSize; /*!< Erase sector size [45:39] */
uint8_t writeProtectGroupSize; /*!< Write protect group size [38:32] */
uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */
uint8_t writeBlockLength; /*!< Maximum write data block length [25:22] */
uint8_t fileFormat; /*!< File format [11:10] */
} sd_csd_t;
typedef struct
{
mmc_cid_t cid;
sd_csd_t csd;
uint32_t rel_addr;
uint32_t block_cnt;
uint32_t block_size;
}sd_card_t;
uint32_t SDIF_SendCmd(sdif_cmd_t *cmd, uint32_t timeout);
void SDIF_Init(void);
void SDIF_SetClock(uint32_t src_clk, uint32_t hz);
void SDIF_SetBusWidth(uint8_t width_bit);
uint32_t SDCardInit(sd_card_t *card, uint32_t hz);
bool SD_IsCardInsert(void);
uint32_t SD_ReadBlock(sd_card_t *card, uint32_t block_addr, uint32_t block_cnt, uint8_t *buf);
uint32_t SD_WriteBlock(sd_card_t *card, uint32_t block_addr, uint32_t block_cnt, uint8_t *buf);
uint32_t SD_SetCardDataBusWidth(sd_card_t *card, uint8_t width_in_bit);
bool SD_IsCardIdle(sd_card_t *card);
uint32_t SD_BlockTest(sd_card_t *card, uint8_t *buf, uint32_t block_addr, uint32_t block_cnt);
#ifdef __cplusplus
}
#endif
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/usbd_lpc_driver.c
|
#include "common.h"
#include "usbd.h"
#include "usbd_config.h"
void USBD_Reset (void);
void USBD_EnableEP (uint32_t EPNum);
void USBD_ResetEP (uint32_t EPNum);
#if defined(RTT)
#include <rtthread.h>
extern rt_mq_t msd_mq;
typedef struct
{
uint8_t param;
void (*exec)(uint32_t param);
}msd_msg_t;
#endif
#define BUF_ACTIVE (1UL << 31)
#define EP_DISABLED (1UL << 30)
#define EP_STALL (1UL << 29)
#define TOOGLE_RESET (1UL << 28)
#define EP_TYPE (1UL << 26)
#define N_BYTES(n) ((n & 0x3FF) << 16)
#define BUF_ADDR(addr) (((addr) >> 6) & 0xFFFF)
#define EP_OUT_IDX(EPNum) (EPNum * 2)
#define EP_IN_IDX(EPNum) (EPNum * 2 + 1)
#define MAX_EP_COUNT (5)
/* EP list must be 256 aligned */
ALIGN(256) volatile uint32_t EPList[(MAX_EP_COUNT) * 4];
/* buffer must be 64 byte aliged */
ALIGN(64) uint8_t EP_BUF_BASE[64*(MAX_EP_COUNT*2)*2]; /* 10 physical EP, each EP has 2 buffer */
typedef struct BUF_INFO
{
uint32_t buf_len;
uint32_t buf_ptr;
}EP_BUF_INFO;
EP_BUF_INFO EPBufInfo[(MAX_EP_COUNT) * 2];
static uint32_t addr;
void USBD_ConfigEP (uint8_t ep);
/*get EP Command/Status register */
uint32_t * GetEpCmdStatPtr (uint32_t EPNum)
{
uint32_t ptr = 0;
if (EPNum & 0x80)
{
EPNum &= ~0x80;
ptr = 8;
}
ptr += (uint32_t)EPList + EPNum * sizeof(uint32_t)*4;
return ((uint32_t *)ptr);
}
/*
* USB Device Initialize Function
* Called by the User to initialize USB Device
* Return Value: None
*/
void USBD_Init (void)
{
/* select USB clock to be 48M FRO */
#if defined(SYSCON_USB0CLKSEL_SEL_MASK)
SYSCON->USB0CLKSEL = SYSCON_USB0CLKSEL_SEL(0);
SYSCON->USB0CLKDIV = SYSCON_USB0CLKDIV_DIV((GetClock(kFROHfClock) == 48*1000*1000)?(0):(1));
#else
SYSCON->USBCLKSEL = SYSCON_USBCLKSEL_SEL(0);
SYSCON->USBCLKDIV = SYSCON_USBCLKDIV_DIV((GetClock(kFROHfClock) == 48*1000*1000)?(0):(1));
#endif
/* enable USB clock */
#if defined(SYSCON_AHBCLKCTRL_USB0D_MASK)
SYSCON->AHBCLKCTRL[1] |= SYSCON_AHBCLKCTRL_USB0D_MASK;
SYSCON->AHBCLKCTRL[2] |= SYSCON_AHBCLKCTRL_USB0HSL_MASK;
SYSCON->PDRUNCFG[0] &= ~SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK;
*((uint32_t *)(USBFSH_BASE + 0x5C)) |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
#else
SYSCON->AHBCLKCTRL[1] |= SYSCON_AHBCLKCTRL_USB0_MASK;
SYSCON->PDRUNCFG[0] &= ~SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK;
#endif
USBD_TRACE("EPNUm:%d\r\n", MAX_EP_COUNT);
USBD_TRACE("EP_BUF_BASE: 0x%08X\r\n", (uint32_t)EP_BUF_BASE);
USBD_TRACE("EPList: 0x%08X\r\n", (uint32_t)EPList);
USB0->DEVCMDSTAT |= (1UL << 9); /* PLL ON */
USB0->DATABUFSTART = (uint32_t)EP_BUF_BASE & 0xFFC00000;
USB0->EPLISTSTART = (uint32_t)EPList;
NVIC_EnableIRQ(USB0_IRQn);
USBD_Reset();
}
/*
* USB Device Connect Function
* Called by the User to Connect/Disconnect USB Device
* Parameters: con: Connect/Disconnect
* Return Value: None
*/
void USBD_Connect (bool con)
{
if ( con )
USB0->DEVCMDSTAT |= (1UL << 16);/* Set device connect status */
else
USB0->DEVCMDSTAT &= ~(1UL << 16);/* Clear device connect status */
return;
}
/*
* USB Device Reset Function
* Called automatically on USB Device Reset
* Return Value: None
*/
void USBD_Reset (void) {
uint32_t i;
uint32_t * ptr;
addr = 3 * 64 + (uint32_t)EP_BUF_BASE;
for (i = 2; i < (5 * 4); i++) {
EPList[i] = (1UL << 30); /* EPs disabled */
}
EPBufInfo[0].buf_len = EP0_MAX_SIZE;
EPBufInfo[0].buf_ptr = (uint32_t)EP_BUF_BASE;
EPBufInfo[1].buf_len = EP0_MAX_SIZE;
EPBufInfo[1].buf_ptr = (uint32_t)EP_BUF_BASE + 2 * 64;
ptr = GetEpCmdStatPtr(0);
*ptr = N_BYTES(EPBufInfo[0].buf_len) | /*EP0 OUT */
BUF_ADDR(EPBufInfo[0].buf_ptr)|
BUF_ACTIVE;
ptr++;
*ptr = BUF_ADDR(EPBufInfo[0].buf_ptr + 64);/* SETUP */
USB0->DEVCMDSTAT |= (1UL << 7); /* USB device enable */
USB0->INTSTAT = 0x2FC; /* clear EP interrupt flags */
USB0->INTEN = ( (1UL << 31)|/* SOF intr enable */
(1UL << 0 ) |/* EP0 OUT intr enable*/
(1UL << 1 ) |/* EP0 IN intr enable */
(1UL << 31)); /* stat change int en */
USBD_ConfigEP(0x01);
USBD_EnableEP(0x01);
USBD_ResetEP(0x01);
USBD_ConfigEP(0x81);
USBD_EnableEP(0x81);
USBD_ResetEP(0x81);
USBD_ConfigEP(0x02);
USBD_EnableEP(0x02);
USBD_ResetEP(0x02);
USBD_ConfigEP(0x82);
USBD_EnableEP(0x82);
USBD_ResetEP(0x82);
USBD_ConfigEP(0x03);
USBD_EnableEP(0x03);
USBD_ResetEP(0x03);
USBD_ConfigEP(0x83);
USBD_EnableEP(0x83);
USBD_ResetEP(0x83);
USBD_ConfigEP(0x04);
USBD_EnableEP(0x04);
USBD_ResetEP(0x04);
USBD_ConfigEP(0x84);
USBD_EnableEP(0x84);
USBD_ResetEP(0x84);
}
void USBD_SetAddress (uint32_t adr, uint32_t setup) {
if (!setup) {
USB0->DEVCMDSTAT &= ~0x7F;
USB0->DEVCMDSTAT |= adr | (1UL<<7);
}
}
/*
* Configure USB Device Endpoint according to Descriptor
* Parameters: pEPD: Pointer to Device Endpoint Descriptor
* Return Value: None
*/
void USBD_ConfigEP (uint8_t ep)
{
uint32_t num, val;
uint32_t * ptr;
num = ep;
val = 64;
/* IN EPs */
if (num & 0x80)
{
num &= ~0x80;
EPBufInfo[EP_IN_IDX(num)].buf_len = val;
EPBufInfo[EP_IN_IDX(num)].buf_ptr = addr;
addr += ((val + 63) >> 6) * 64; /* calc new free buffer address */
ptr = GetEpCmdStatPtr(num | 0x80);
*ptr = EP_DISABLED;
}
else /* OUT EPs */
{
EPBufInfo[EP_OUT_IDX(num)].buf_len = val;
EPBufInfo[EP_OUT_IDX(num)].buf_ptr = addr;
ptr = GetEpCmdStatPtr(num);
*ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(num)].buf_len) | BUF_ADDR(EPBufInfo[EP_OUT_IDX(num)].buf_ptr) | EP_DISABLED;
addr += ((val + 63) >> 6) * 64; /* calc new free buffer address */
}
}
/*
* Enable USB Device Endpoint
* Parameters: EPNum: Device Endpoint Number
* EPNum.0..3: Address
* EPNum.7: Dir
* Return Value: None
*/
void USBD_EnableEP (uint32_t EPNum)
{
uint32_t * ptr;;
ptr = GetEpCmdStatPtr(EPNum);
if (EPNum & 0x80) /* IN EP */
{
EPNum &= ~0x80;
*ptr &= ~EP_DISABLED;
USB0->INTSTAT = (1 << EP_IN_IDX(EPNum));
USB0->INTEN |= (1 << EP_IN_IDX(EPNum));
}
else /* OUT EP */
{
*ptr &= ~EP_DISABLED;
*ptr |= BUF_ACTIVE;
USB0->INTSTAT = (1 << EP_OUT_IDX(EPNum));
USB0->INTEN |= (1 << EP_OUT_IDX(EPNum));
}
}
void USBD_ResetEP (uint32_t EPNum)
{
uint32_t *ptr;
ptr = GetEpCmdStatPtr(EPNum);
*ptr |= TOOGLE_RESET;
}
uint32_t USBD_ReadEP (uint32_t EPNum, uint8_t *pData)
{
uint32_t cnt, i;
uint32_t *dataptr, *ptr;
ptr = GetEpCmdStatPtr(EPNum);
/* SETUP packet */
if ((EPNum == 0) && (USB0->DEVCMDSTAT & (1UL << 8)))
{
cnt = 8; /* LPC hardware cannot tell you how much byte setup packet has been received. standard request len = 8 */
dataptr = (uint32_t *)(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr + 64);
for (i = 0; i < (cnt + 3) / 4; i++)
{
*((__packed uint32_t *)pData) = dataptr[i];
pData += 4;
}
USB0->EPSKIP |= (1 << EP_IN_IDX(EPNum));
while (USB0->EPSKIP & (1 << EP_IN_IDX(EPNum)));
if (*(ptr + 2) & EP_STALL)
{
*(ptr + 2) &= ~(EP_STALL);
}
if (*ptr & EP_STALL)
{
*ptr &= ~(EP_STALL);
}
USB0->DEVCMDSTAT |= (1UL << 8);
}
else /*OUT packet */
{
ptr = GetEpCmdStatPtr(EPNum);
cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len - ((*ptr >> 16) & 0x3FF);
dataptr = (uint32_t *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr;
for (i = 0; i < (cnt + 3) / 4; i++)
{
*((__packed uint32_t *)pData) = dataptr[i];
pData += 4;
}
*ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(EPNum)].buf_len) | BUF_ADDR(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr) | BUF_ACTIVE;
}
return (cnt);
}
uint32_t USBD_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt)
{
uint32_t i;
uint32_t * dataptr, *ptr;
ptr = GetEpCmdStatPtr(EPNum);
EPNum &= ~0x80;
while (*ptr & BUF_ACTIVE);
*ptr &= ~(0x3FFFFFF);
*ptr |= BUF_ADDR(EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr) | N_BYTES(cnt);
dataptr = (uint32_t *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr;
for (i = 0; i < (cnt + 3) / 4; i++)
{
dataptr[i] = * ((__packed uint32_t *)pData);
pData += 4;
}
if (EPNum && (*ptr & EP_STALL))
{
return (0);
}
*ptr |= BUF_ACTIVE;
return (cnt);
}
/*
* USB Device Interrupt Service Routine
*/
void USBD_IRQHandler(void)
{
uint32_t sts, val, num;
sts = USB0->INTSTAT & USB0->INTEN;
USB0->INTSTAT = sts;
/* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */
if (sts & USB_INTSTAT_DEV_INT_MASK)
{
val = USB0->DEVCMDSTAT;
/* reset interrupt */
if (val & USB_DEVCMDSTAT_DRES_C_MASK)
{
USBD_TRACE("usbd reset\r\n");
USBD_Reset();
usbd_stack_reset();
USB0->DEVCMDSTAT |= USB_DEVCMDSTAT_DRES_C_MASK;
}
/* suspend/resume interrupt */
if (val & (1UL << 25))
{
USBD_TRACE("suspend/resume\r\n");
/* suspend interrupt */
if (val & (1UL << 17))
{
// USBD_Suspend();
}
/* resume interrupt */
else
{
}
USB0->DEVCMDSTAT |= (1UL << 25);
}
/* connect interrupt */
if (val & (1UL << 24))
{
USB0->DEVCMDSTAT |= (1UL << 24);
}
USB0->INTSTAT = USB_INTSTAT_DEV_INT_MASK;
}
/* Start of Frame */
if (sts & USB_INTSTAT_FRAME_INT_MASK)
{
USB0->INTSTAT = USB_INTSTAT_FRAME_INT_MASK;
}
/* EndPoint Interrupt */
if (sts & 0x3FF)
{
val = USB0->DEVCMDSTAT;
if (sts & USB_INTSTAT_EP0OUT_MASK)
{
if(val & USB_DEVCMDSTAT_SETUP_MASK) /* SETUP */
{
usbd_ep0_setup_handler();
}
else
{
usbd_ep0_out_handler();
}
}
else if (sts & USB_INTSTAT_EP0IN_MASK) /* EP0 in token */
{
usbd_ep0_in_handler();
}
else /* other ep */
{
for(num = 2; num < (MAX_EP_COUNT*2); num++)
{
if (sts & (1UL << num))
{
//printf("EP%d %s\r\n", num / 2, (num % 2)?("IN"):("OUT"));
#if defined(RTT)
msd_msg_t msg;
msg.param = num;
msg.exec = NULL;
rt_mq_send(msd_mq, &msg, sizeof(msg));
#else
usbd_data_ep_handler(num / 2, num % 2);
#endif
}
}
}
}
}
uint32_t ep_read(uint8_t ep, uint8_t *buf, uint8_t data01)
{
return USBD_ReadEP(ep, buf);
}
uint32_t ep_write(uint8_t ep, uint8_t *buf, uint32_t len, uint8_t data01)
{
ep |= 0x80; /* write ep must use IN EP */
return USBD_WriteEP (ep, buf, len);
}
uint32_t set_addr(uint8_t addr)
{
USBD_SetAddress(addr, 0);
return 0;
}
uint32_t usbd_config_ep(struct uendpoint_descriptor* d)
{
uint8_t num = d->bEndpointAddress;
uint32_t size = d->wMaxPacketSize;
uint8_t type = d->bmAttributes;
USBD_TRACE("ConfigEP:0x%X %d %d\r\n", num, size, type);
USBD_ConfigEP(num);
USBD_EnableEP(num);
USBD_ResetEP(num);
return 0;
}
uint32_t ep_clear_feature(uint8_t ep)
{
uint32_t *ptr;
ptr = GetEpCmdStatPtr(ep);
printf("ep_clear_feature:0x%X 0x%08X 0x%08X\r\n", ep, USB0->INFO >> 11, *ptr);
if (ep & 0x80)
{
*ptr &= ~EP_STALL;
}
else
{
*ptr &= ~EP_STALL;
*ptr |= BUF_ACTIVE;
}
USBD_ResetEP(ep);
return CH_OK;
}
const struct usbd_ops_t ops;
void ch_usb_init(struct usbd_t *h)
{
static struct usbd_ops_t ops;
ops.ep_read = ep_read;
ops.ep_write = ep_write;
ops.set_addr = set_addr;
ops.ep_config = usbd_config_ep;
ops.ep_clear_feature = ep_clear_feature;
usbd_init(h, &ops);
}
void USB_IRQHandler (void)
{
USBD_IRQHandler();
}
void USB0_IRQHandler (void)
{
USBD_IRQHandler();
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/spi.c
|
<gh_stars>1-10
/**
******************************************************************************
* @file spi.c
* @author YANDLD
* @version V3.0.0
* @date 2015.6.21
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "common.h"
#include "spi.h"
static FLEXCOMM_Type* const FLEXCOMMBases[] = FLEXCOMM_BASE_PTRS;
SPI_Type* const SPIBases[] = SPI_BASE_PTRS;
#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000)
#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16))
#define SPI_DEASSERT_ALL (0xF0000)
uint32_t SPI_SetClock(uint32_t instance)
{
SetFlexCommClk(instance, 1);
return GetClock(kFROHfClock);
}
void SPI_SetBaudRate(uint32_t instance, uint32_t baud)
{
uint32_t tmp, clk;
clk = SPI_SetClock(instance);
/* calculate baudrate */
tmp = (clk / baud);
LIB_TRACE("SPI input clock:%dHz div:%d\r\n", clk, tmp);
SPIBases[instance]->DIV &= ~SPI_DIV_DIVVAL_MASK;
SPIBases[instance]->DIV |= SPI_DIV_DIVVAL(tmp - 1);
}
uint32_t SPI_Init(uint32_t MAP, uint32_t baudrate)
{
map_t * pq = (map_t*)&(MAP);
uint32_t instance = pq->ip;
SYSCON->AHBCLKCTRL[1] |= SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK
| SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK
| SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK
| SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK
| SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK
| SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK
| SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK
| SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK;
/* select flexcomm to SPI */
FLEXCOMMBases[instance]->PSELID &= ~FLEXCOMM_PSELID_PERSEL_MASK;
FLEXCOMMBases[instance]->PSELID |= FLEXCOMM_PSELID_PERSEL(2);
SPIBases[instance]->CFG &= ~SPI_CFG_ENABLE_MASK;
SPI_SetBaudRate(instance, baudrate);
/* add some delay */
SPIBases[instance]->DLY = SPI_DLY_PRE_DELAY(0) | SPI_DLY_POST_DELAY(0) | SPI_DLY_TRANSFER_DELAY(0) | SPI_DLY_FRAME_DELAY(0);
/* enable and clear FIFO */
SPIBases[instance]->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK | SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
/* clear FIFO error */
SPIBases[instance]->FIFOSTAT = SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
SPIBases[instance]->CFG = SPI_CFG_ENABLE_MASK | SPI_CFG_MASTER_MASK;
return 0;
}
uint32_t SPI_ReadWriteEx(uint32_t instance, uint32_t data, uint16_t cs, uint32_t cs_states)
{
SPIBases[instance]->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
while((SPIBases[instance]->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) == 0);
SPIBases[instance]->FIFOWR = (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(cs)) | SPI_FIFOWR_TXDATA(data) | SPI_FIFOWR_LEN(7) | SPI_FIFOWR_EOT(cs_states);
while((SPIBases[instance]->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) == 0);
return (SPIBases[instance]->FIFORD & SPI_FIFORD_RXDATA_MASK);
}
uint32_t SPI_ReadFIFO(uint32_t instance, uint8_t *buf, uint32_t len)
{
uint32_t rd_count = 0;
uint32_t wr_count = len;
//uint32_t dummy;
//SPIBases[instance]->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
//SPIBases[instance]->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
while(1)
{
if(rd_count == len)
{
break;
}
if(wr_count)
{
if(SPIBases[instance]->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK)
{
SPIBases[instance]->FIFOWR = (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(0)) | SPI_FIFOWR_TXDATA(0xFF) | SPI_FIFOWR_LEN(7) | SPI_FIFOWR_EOT(0);
wr_count--;
}
}
if(SPIBases[instance]->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
{
*buf++ = SPIBases[instance]->FIFORD;
rd_count++;
}
}
return CH_OK;
}
uint32_t SPI_WriteFIFO(uint32_t instance, uint8_t *buf, uint32_t len)
{
volatile uint32_t dummy;
uint32_t rd_count = 0;
uint32_t wr_count = len;
while(1)
{
if(rd_count == len)
{
break;
}
if(wr_count)
{
if(SPIBases[instance]->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK)
{
SPIBases[instance]->FIFOWR = (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(0)) | SPI_FIFOWR_TXDATA(*buf++) | SPI_FIFOWR_LEN(7) | SPI_FIFOWR_EOT(0);
wr_count--;
}
}
if(SPIBases[instance]->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
{
dummy = SPIBases[instance]->FIFORD;
rd_count++;
}
}
return CH_OK;
}
uint32_t SPI_ReadWriteFIFO(uint32_t instance, uint8_t *in_buf, uint8_t *out_buf, uint32_t len)
{
volatile uint32_t dummy;
volatile uint32_t rd_count = 0;
volatile uint32_t wr_count = len;
while(1)
{
if(rd_count == len)
{
break;
}
if(wr_count)
{
if(SPIBases[instance]->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK)
{
SPIBases[instance]->FIFOWR = (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(0)) | SPI_FIFOWR_TXDATA(*out_buf++) | SPI_FIFOWR_LEN(7) | SPI_FIFOWR_EOT(0);
wr_count--;
}
}
if(SPIBases[instance]->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
{
if(in_buf != NULL)
{
*in_buf++ = SPIBases[instance]->FIFORD;
}
else
{
dummy = SPIBases[instance]->FIFORD;
}
rd_count++;
}
}
return CH_OK;
}
uint32_t SPI_ReadWrite(uint32_t instance, uint32_t data)
{
return SPI_ReadWriteEx(instance, data, 0, 1);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/examples/master402/master402_canopen.c
|
#include <stdint.h>
#include <rtthread.h>
#include <finsh.h>
#include "canfestival.h"
#include "canopen_callback.h"
#include "timers_driver.h"
#include "master402_canopen.h"
#include "master402_od.h"
#define PRODUCER_HEARTBEAT_TIME 500
#define CONSUMER_HEARTBEAT_TIME 1000
struct servo_config_state
{
uint8_t state;
uint8_t try_cnt;
struct rt_semaphore finish_sem;
};
void InitNodes(CO_Data* d, UNS32 id);
static void config_servo_param(uint8_t nodeId, struct servo_config_state *conf);
static struct servo_config_state servo_conf[4];
static void config_servo(uint8_t nodeId);
static void config_single_servo(void *parameter);
CO_Data *OD_Data = &master402_Data;
s_BOARD agv_board = {"0", "1M"};
int canopen_init(void)
{
OD_Data->heartbeatError = master402_heartbeatError;
OD_Data->initialisation = master402_initialisation;
OD_Data->preOperational = master402_preOperational;
OD_Data->operational = master402_operational;
OD_Data->stopped = master402_stopped;
OD_Data->post_sync = master402_post_sync;
OD_Data->post_TPDO = master402_post_TPDO;
OD_Data->storeODSubIndex = (storeODSubIndex_t)master402_storeODSubIndex;
OD_Data->post_emcy = (post_emcy_t)master402_post_emcy;
canOpen(&agv_board, OD_Data);
initTimer();
// Start timer thread
StartTimerLoop(&InitNodes);
return 0;
}
INIT_APP_EXPORT(canopen_init);
void InitNodes(CO_Data* d, UNS32 id)
{
setNodeId(OD_Data, 0x01);
setState(OD_Data, Initialisation);
}
void Exit(CO_Data* d, UNS32 id)
{
}
static void slaveBootupHdl(CO_Data* d, UNS8 nodeId)
{
rt_thread_t tid;
tid = rt_thread_create("co_cfg", config_single_servo, (void *)nodeId, 1024, 12 + nodeId, 2);
if(tid == RT_NULL)
{
rt_kprintf("canopen config thread start failed!\n");
}
else
{
rt_thread_startup(tid);
}
}
void canopen_start_thread_entry(void *parameter)
{
UNS32 sync_id, size;
UNS8 data_type, sub_cnt;
UNS32 consumer_heartbeat_time;
rt_thread_delay(200);
config_servo(SERVO_NODEID);
OD_Data->post_SlaveBootup = slaveBootupHdl;
consumer_heartbeat_time = (2 << 16) | CONSUMER_HEARTBEAT_TIME;
size = 4;
writeLocalDict(OD_Data, 0x1016, 1, &consumer_heartbeat_time, &size, 0);
consumer_heartbeat_time = (3 << 16) | CONSUMER_HEARTBEAT_TIME;
writeLocalDict(OD_Data, 0x1016, 2, &consumer_heartbeat_time, &size, 0);
sub_cnt = 2;
size = 1;
writeLocalDict(OD_Data, 0x1016, 0, &sub_cnt, &size, 0);
data_type = uint32;
setState(OD_Data, Operational);
masterSendNMTstateChange(OD_Data, SERVO_NODEID, NMT_Start_Node);
size = 4;
readLocalDict(OD_Data, 0x1005, 0, &sync_id, &size, &data_type, 0);
sync_id |= (1 << 30);
writeLocalDict(OD_Data, 0x1005, 0, &sync_id, &size, 0);
}
static void config_servo(uint8_t nodeId)
{
servo_conf[nodeId - 2].state = 0;
servo_conf[nodeId - 2].try_cnt = 0;
rt_sem_init(&(servo_conf[nodeId - 2].finish_sem), "servocnf", 0, RT_IPC_FLAG_FIFO);
EnterMutex();
config_servo_param(nodeId, &servo_conf[nodeId - 2]);
LeaveMutex();
rt_sem_take(&(servo_conf[nodeId - 2].finish_sem), RT_WAITING_FOREVER);
}
static void config_single_servo(void *parameter)
{
uint32_t nodeId;
nodeId = (uint32_t)parameter;
config_servo(nodeId);
masterSendNMTstateChange(OD_Data, nodeId, NMT_Start_Node);
}
static void config_servo_param_cb(CO_Data* d, UNS8 nodeId)
{
UNS32 abortCode;
UNS8 res;
struct servo_config_state *conf;
conf = &servo_conf[nodeId - 2];
res = getWriteResultNetworkDict(OD_Data, nodeId, &abortCode);
closeSDOtransfer(OD_Data, nodeId, SDO_CLIENT);
if(res != SDO_FINISHED)
{
conf->try_cnt++;
rt_kprintf("write SDO failed! nodeId = %d, abortCode = 0x%08X\n", nodeId, abortCode);
if(conf->try_cnt < 3)
{
config_servo_param(nodeId, conf);
}
else
{
rt_sem_release(&(conf->finish_sem));
conf->state = 0;
conf->try_cnt = 0;
rt_kprintf("SDO config try count > 3, config failed!\n");
}
}
else
{
conf->state++;
conf->try_cnt = 0;
config_servo_param(nodeId, conf);
}
}
static void config_servo_param(uint8_t nodeId, struct servo_config_state *conf)
{
switch(conf->state)
{
case 0:
{ // disable Slave's TPDO
UNS32 TPDO_COBId = 0x80000180 + nodeId;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1800, 1,
4, uint32, &TPDO_COBId, config_servo_param_cb, 0);
}
break;
case 1:
{
UNS8 trans_type = PDO_TRANSMISSION_TYPE;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1800, 2,
1, uint8, &trans_type, config_servo_param_cb, 0);
}
break;
case 2:
{
UNS8 pdo_map_cnt = 0;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1A00, 0,
1, uint8, &pdo_map_cnt, config_servo_param_cb, 0);
}
break;
case 3:
{
UNS32 pdo_map_val = 0x60410010;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1A00, 1,
4, uint32, &pdo_map_val, config_servo_param_cb, 0);
}
break;
case 4:
{
UNS32 pdo_map_val = 0x60630020;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1A00, 2,
4, uint32, &pdo_map_val, config_servo_param_cb, 0);
}
break;
case 5:
{
UNS8 pdo_map_cnt = 2;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1A00, 0,
1, uint8, &pdo_map_cnt, config_servo_param_cb, 0);
}
break;
case 6:
{ // enable Slave's TPDO
UNS32 TPDO_COBId = 0x00000180 + nodeId;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1800, 1,
4, uint32, &TPDO_COBId, config_servo_param_cb, 0);
}
break;
case 7:
{ // disable Slave's TPDO
UNS32 TPDO_COBId = 0x80000280 + nodeId;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1801, 1,
4, uint32, &TPDO_COBId, config_servo_param_cb, 0);
}
break;
case 8:
{
UNS8 trans_type = PDO_TRANSMISSION_TYPE;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1801, 2,
1, uint8, &trans_type, config_servo_param_cb, 0);
}
break;
case 9:
{
UNS8 pdo_map_cnt = 0;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1A01, 0,
1, uint8, &pdo_map_cnt, config_servo_param_cb, 0);
}
break;
case 10:
{
UNS32 pdo_map_val = 0x606c0020;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1A01, 1,
4, uint32, &pdo_map_val, config_servo_param_cb, 0);
}
break;
case 11:
{
UNS8 pdo_map_cnt = 1;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1A01, 0,
1, uint8, &pdo_map_cnt, config_servo_param_cb, 0);
}
break;
case 12:
{ // enable Slave's TPDO
UNS32 TPDO_COBId = 0x00000280 + nodeId;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1801, 1,
4, uint32, &TPDO_COBId, config_servo_param_cb, 0);
}
break;
case 13:
{ // disable Slave's RPDO
UNS32 RPDO_COBId = 0x80000200 + nodeId;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1400, 1,
4, uint32, &RPDO_COBId, config_servo_param_cb, 0);
}
break;
case 14:
{
UNS8 trans_type = PDO_TRANSMISSION_TYPE;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1400, 2,
1, uint8, &trans_type, config_servo_param_cb, 0);
}
break;
case 15:
{
UNS8 pdo_map_cnt = 0;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1600, 0,
1, uint8, &pdo_map_cnt, config_servo_param_cb, 0);
}
break;
case 16:
{
UNS32 pdo_map_val = 0x60400010;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1600, 1,
4, uint32, &pdo_map_val, config_servo_param_cb, 0);
}
break;
case 17:
{
UNS32 pdo_map_val = 0x60600008;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1600, 2,
4, uint32, &pdo_map_val, config_servo_param_cb, 0);
}
break;
case 18:
{
UNS8 pdo_map_cnt = 2;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1600, 0,
1, uint8, &pdo_map_cnt, config_servo_param_cb, 0);
}
break;
case 19:
{ // enable Slave's RPDO
UNS32 RPDO_COBId = 0x00000200 + nodeId;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1400, 1,
4, uint32, &RPDO_COBId, config_servo_param_cb, 0);
}
break;
case 20:
{ // disable Slave's RPDO
UNS32 RPDO_COBId = 0x80000300 + nodeId;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1401, 1,
4, uint32, &RPDO_COBId, config_servo_param_cb, 0);
}
break;
case 21:
{
UNS8 trans_type = PDO_TRANSMISSION_TYPE;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1401, 2,
1, uint8, &trans_type, config_servo_param_cb, 0);
}
break;
case 22:
{
UNS8 pdo_map_cnt = 0;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1601, 0,
1, uint8, &pdo_map_cnt, config_servo_param_cb, 0);
}
break;
case 23:
{
UNS32 pdo_map_val = 0x607a0020;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1601, 1,
4, uint32, &pdo_map_val, config_servo_param_cb, 0);
}
break;
case 24:
{
UNS32 pdo_map_val = 0x60810020;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1601, 2,
4, uint32, &pdo_map_val, config_servo_param_cb, 0);
}
break;
case 25:
{
UNS8 pdo_map_cnt = 2;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1601, 0,
1, uint8, &pdo_map_cnt, config_servo_param_cb, 0);
}
break;
case 26:
{ // enable Slave's RPDO
UNS32 TPDO_COBId = 0x00000300 + nodeId;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1401, 1,
4, uint32, &TPDO_COBId, config_servo_param_cb, 0);
}
break;
case 27:
{
UNS16 producer_heartbeat_time = PRODUCER_HEARTBEAT_TIME;
writeNetworkDictCallBack(OD_Data, nodeId, 0x1017, 0,
2, uint16, &producer_heartbeat_time, config_servo_param_cb, 0);
}
break;
case 28:
rt_sem_release(&(conf->finish_sem));
break;
default:
break;
}
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/QN908XB.h
|
<gh_stars>1-10
/*
** ###################################################################
** Processor: QN908X
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: User manual Rev. 1.0 25 May 2016
** Build: b170203
**
** Abstract:
** CMSIS Peripheral Access Layer for QN908X
**
** Copyright (c) 1997 - 2017 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
**
** ###################################################################
*/
/*!
* @file QN908X.h
* @version 0.0
* @date 0-00-00
* @brief CMSIS Peripheral Access Layer for QN908X
*
* CMSIS Peripheral Access Layer for QN908X
*/
#ifndef _QN908X_H_
#define _QN908X_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0000U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 68 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Auxiliary constants */
NotAvail_IRQn = -128, /**< Not available device specific interrupt */
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
/* Device specific interrupts */
EXT_GPIO_WAKEUP_IRQn = 0, /**< Ext GPIO wakeup */
OSC_IRQn = 1, /**< BLE wakeup */
ACMP0_IRQn = 2, /**< Analog comparator0 */
ACMP1_IRQn = 3, /**< Analog comparator1 */
RTC_SEC_IRQn = 5, /**< RTC second */
RTC_FR_IRQn = 6, /**< RTC free running */
CS_WAKEUP_IRQn = 7, /**< Capacitive sense wakeup */
CS_IRQn = 8, /**< Capacitive sense */
GPIOA_IRQn = 9, /**< GPIO group A */
GPIOB_IRQn = 10, /**< GPIO group B */
DMA0_IRQn = 11, /**< DMA controller */
PIN_INT0_IRQn = 12, /**< pin or pattern match engine slice 0 */
PIN_INT1_IRQn = 13, /**< pin or pattern match engine slice 1 */
PIN_INT2_IRQn = 14, /**< pin or pattern match engine slice 2 */
PIN_INT3_IRQn = 15, /**< pin or pattern match engine slice 3 */
OSC_INT_LOW_IRQn = 16, /**< Inverse of OSC */
USB0_IRQn = 17, /**< USB device */
FLEXCOMM0_IRQn = 18, /**< Flexcomm Interface 0 (USART) */
FLEXCOMM1_IRQn = 19, /**< Flexcomm Interface 1 (USART, I2C) */
FLEXCOMM2_IRQn = 20, /**< Flexcomm Interface 2 (SPI, I2C) */
FLEXCOMM3_IRQn = 21, /**< Flexcomm Interface 3 (SPI) */
BLE_IRQn = 22, /**< BLE interrupts */
FSP_IRQn = 23, /**< FSP */
QDEC0_IRQn = 24, /**< QDEC0 */
QDEC1_IRQn = 25, /**< QDEC1 */
CTIMER0_IRQn = 26, /**< Standard counter/timer CTIMER0 */
CTIMER1_IRQn = 27, /**< Standard counter/timer CTIMER1 */
CTIMER2_IRQn = 28, /**< Standard counter/timer CTIMER2 */
CTIMER3_IRQn = 29, /**< Standard counter/timer CTIMER3 */
WDT_IRQn = 30, /**< Watch dog timer */
ADC_IRQn = 31, /**< ADC */
DAC_IRQn = 32, /**< DAC */
XTAL_READY_IRQn = 33, /**< High frequency crystal ready */
FLASH_IRQn = 34, /**< Flash */
SPIFI0_IRQn = 35, /**< SPI flash interface */
SCT0_IRQn = 36, /**< SCTimer/PWM */
RNG_IRQn = 38, /**< Random number generator */
CALIB_IRQn = 40, /**< Calibration */
BLE_TX_IRQn = 42,
BLE_RX_IRQn = 43,
BLE_FREQ_HOP_IRQn = 44,
BOD_IRQn = 51 /**< Brown out dectect */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M4 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
* @{
*/
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
#include "core_cm4.h" /* Core Peripheral Access Layer */
#include "system_QN908XB.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Mapping Information
---------------------------------------------------------------------------- */
/*!
* @addtogroup Mapping_Information Mapping Information
* @{
*/
/** Mapping Information */
/*!
* @}
*/ /* end of group Mapping_Information */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language = extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct
{
__IO uint32_t CTRL; /**< ADC control register, offset: 0x0 */
__IO uint32_t CH_SEL; /**< ADC channel selection register, offset: 0x4 */
__IO uint32_t CH_CFG; /**< ADC channel configuration register, offset: 0x8 */
__IO uint32_t WCMP_THR; /**< Window compare threshold register, offset: 0xC */
__IO uint32_t INTEN; /**< ADC interrupt enable register, offset: 0x10 */
__IO uint32_t INT; /**< ADC interrupt status register, offset: 0x14 */
__I uint32_t DATA; /**< ADC converted data output, offset: 0x18 */
uint8_t RESERVED_0[4];
__IO uint32_t CFG[2]; /**< ADC configuration register, array offset: 0x20, array step: 0x4 */
__IO uint32_t BG_BF; /**< ADC bandcap and buffer setting register, offset: 0x28 */
__IO uint32_t ANA_CTRL; /**< ADC core and reference setting regsiter, offset: 0x2C */
} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/*! @name CTRL - ADC control register */
#define ADC_CTRL_ENABLE_MASK (0x1U)
#define ADC_CTRL_ENABLE_SHIFT (0U)
#define ADC_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ENABLE_SHIFT)) & ADC_CTRL_ENABLE_MASK)
#define ADC_CTRL_CONV_MODE_MASK (0x2U)
#define ADC_CTRL_CONV_MODE_SHIFT (1U)
#define ADC_CTRL_CONV_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CONV_MODE_SHIFT)) & ADC_CTRL_CONV_MODE_MASK)
#define ADC_CTRL_SCAN_EN_MASK (0x4U)
#define ADC_CTRL_SCAN_EN_SHIFT (2U)
#define ADC_CTRL_SCAN_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_SCAN_EN_SHIFT)) & ADC_CTRL_SCAN_EN_MASK)
#define ADC_CTRL_WCMP_EN_MASK (0x8U)
#define ADC_CTRL_WCMP_EN_SHIFT (3U)
#define ADC_CTRL_WCMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_WCMP_EN_SHIFT)) & ADC_CTRL_WCMP_EN_MASK)
#define ADC_CTRL_SW_START_MASK (0x80U)
#define ADC_CTRL_SW_START_SHIFT (7U)
#define ADC_CTRL_SW_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_SW_START_SHIFT)) & ADC_CTRL_SW_START_MASK)
#define ADC_CTRL_CLKSEL_MASK (0x1F00U)
#define ADC_CTRL_CLKSEL_SHIFT (8U)
#define ADC_CTRL_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKSEL_SHIFT)) & ADC_CTRL_CLKSEL_MASK)
#define ADC_CTRL_SIG_INV_EN_MASK (0x2000U)
#define ADC_CTRL_SIG_INV_EN_SHIFT (13U)
#define ADC_CTRL_SIG_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_SIG_INV_EN_SHIFT)) & ADC_CTRL_SIG_INV_EN_MASK)
#define ADC_CTRL_VREF_SEL_MASK (0xC000U)
#define ADC_CTRL_VREF_SEL_SHIFT (14U)
#define ADC_CTRL_VREF_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_VREF_SEL_SHIFT)) & ADC_CTRL_VREF_SEL_MASK)
#define ADC_CTRL_CH_IDX_EN_MASK (0x40000U)
#define ADC_CTRL_CH_IDX_EN_SHIFT (18U)
#define ADC_CTRL_CH_IDX_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CH_IDX_EN_SHIFT)) & ADC_CTRL_CH_IDX_EN_MASK)
#define ADC_CTRL_DATA_FORMAT_MASK (0x80000U)
#define ADC_CTRL_DATA_FORMAT_SHIFT (19U)
#define ADC_CTRL_DATA_FORMAT(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DATA_FORMAT_SHIFT)) & ADC_CTRL_DATA_FORMAT_MASK)
#define ADC_CTRL_VREFO_EN_MASK (0x100000U)
#define ADC_CTRL_VREFO_EN_SHIFT (20U)
#define ADC_CTRL_VREFO_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_VREFO_EN_SHIFT)) & ADC_CTRL_VREFO_EN_MASK)
#define ADC_CTRL_SRST_DIS_MASK (0x200000U)
#define ADC_CTRL_SRST_DIS_SHIFT (21U)
#define ADC_CTRL_SRST_DIS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_SRST_DIS_SHIFT)) & ADC_CTRL_SRST_DIS_MASK)
#define ADC_CTRL_TRIGGER_MASK (0x1F800000U)
#define ADC_CTRL_TRIGGER_SHIFT (23U)
#define ADC_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIGGER_SHIFT)) & ADC_CTRL_TRIGGER_MASK)
/*! @name CH_SEL - ADC channel selection register */
#define ADC_CH_SEL_CH_SEL_MASK (0xFFFFFFFFU)
#define ADC_CH_SEL_CH_SEL_SHIFT (0U)
#define ADC_CH_SEL_CH_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CH_SEL_CH_SEL_SHIFT)) & ADC_CH_SEL_CH_SEL_MASK)
/*! @name CH_CFG - ADC channel configuration register */
#define ADC_CH_CFG_CH_CFG_MASK (0xFFFFFFFFU)
#define ADC_CH_CFG_CH_CFG_SHIFT (0U)
#define ADC_CH_CFG_CH_CFG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CH_CFG_CH_CFG_SHIFT)) & ADC_CH_CFG_CH_CFG_MASK)
/*! @name WCMP_THR - Window compare threshold register */
#define ADC_WCMP_THR_WCMP_THR_LOW_MASK (0xFFFFU)
#define ADC_WCMP_THR_WCMP_THR_LOW_SHIFT (0U)
#define ADC_WCMP_THR_WCMP_THR_LOW(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_WCMP_THR_WCMP_THR_LOW_SHIFT)) & ADC_WCMP_THR_WCMP_THR_LOW_MASK)
#define ADC_WCMP_THR_WCMP_THR_HIGH_MASK (0xFFFF0000U)
#define ADC_WCMP_THR_WCMP_THR_HIGH_SHIFT (16U)
#define ADC_WCMP_THR_WCMP_THR_HIGH(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_WCMP_THR_WCMP_THR_HIGH_SHIFT)) & ADC_WCMP_THR_WCMP_THR_HIGH_MASK)
/*! @name INTEN - ADC interrupt enable register */
#define ADC_INTEN_DAT_RDY_INTEN_MASK (0x1U)
#define ADC_INTEN_DAT_RDY_INTEN_SHIFT (0U)
#define ADC_INTEN_DAT_RDY_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_INTEN_DAT_RDY_INTEN_SHIFT)) & ADC_INTEN_DAT_RDY_INTEN_MASK)
#define ADC_INTEN_WCMP_INTEN_MASK (0x2U)
#define ADC_INTEN_WCMP_INTEN_SHIFT (1U)
#define ADC_INTEN_WCMP_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_INTEN_WCMP_INTEN_SHIFT)) & ADC_INTEN_WCMP_INTEN_MASK)
#define ADC_INTEN_FIFO_OF_INTEN_MASK (0x4U)
#define ADC_INTEN_FIFO_OF_INTEN_SHIFT (2U)
#define ADC_INTEN_FIFO_OF_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_INTEN_FIFO_OF_INTEN_SHIFT)) & ADC_INTEN_FIFO_OF_INTEN_MASK)
#define ADC_INTEN_ADC_INTEN_MASK (0x80000000U)
#define ADC_INTEN_ADC_INTEN_SHIFT (31U)
#define ADC_INTEN_ADC_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADC_INTEN_SHIFT)) & ADC_INTEN_ADC_INTEN_MASK)
/*! @name INT - ADC interrupt status register */
#define ADC_INT_DAT_RDY_INT_MASK (0x1U)
#define ADC_INT_DAT_RDY_INT_SHIFT (0U)
#define ADC_INT_DAT_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_INT_DAT_RDY_INT_SHIFT)) & ADC_INT_DAT_RDY_INT_MASK)
#define ADC_INT_WCMP_INT_MASK (0x2U)
#define ADC_INT_WCMP_INT_SHIFT (1U)
#define ADC_INT_WCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_INT_WCMP_INT_SHIFT)) & ADC_INT_WCMP_INT_MASK)
#define ADC_INT_FIFO_OF_INT_MASK (0x4U)
#define ADC_INT_FIFO_OF_INT_SHIFT (2U)
#define ADC_INT_FIFO_OF_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_INT_FIFO_OF_INT_SHIFT)) & ADC_INT_FIFO_OF_INT_MASK)
#define ADC_INT_ADC_INT_MASK (0x80000000U)
#define ADC_INT_ADC_INT_SHIFT (31U)
#define ADC_INT_ADC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_INT_ADC_INT_SHIFT)) & ADC_INT_ADC_INT_MASK)
/*! @name DATA - ADC converted data output */
#define ADC_DATA_DATA_MASK (0xFFFFFFFFU)
#define ADC_DATA_DATA_SHIFT (0U)
#define ADC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_DATA_DATA_SHIFT)) & ADC_DATA_DATA_MASK)
/*! @name CFG - ADC configuration register */
#define ADC_CFG_PGA_GAIN_MASK (0x7U)
#define ADC_CFG_PGA_GAIN_SHIFT (0U)
#define ADC_CFG_PGA_GAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PGA_GAIN_SHIFT)) & ADC_CFG_PGA_GAIN_MASK)
#define ADC_CFG_PGA_BP_MASK (0x8U)
#define ADC_CFG_PGA_BP_SHIFT (3U)
#define ADC_CFG_PGA_BP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PGA_BP_SHIFT)) & ADC_CFG_PGA_BP_MASK)
#define ADC_CFG_PGA_VINN_MASK (0x30U)
#define ADC_CFG_PGA_VINN_SHIFT (4U)
#define ADC_CFG_PGA_VINN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PGA_VINN_SHIFT)) & ADC_CFG_PGA_VINN_MASK)
#define ADC_CFG_ADC_GAIN_MASK (0xC0U)
#define ADC_CFG_ADC_GAIN_SHIFT (6U)
#define ADC_CFG_ADC_GAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADC_GAIN_SHIFT)) & ADC_CFG_ADC_GAIN_MASK)
#define ADC_CFG_VREF_GAIN_MASK (0x100U)
#define ADC_CFG_VREF_GAIN_SHIFT (8U)
#define ADC_CFG_VREF_GAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_VREF_GAIN_SHIFT)) & ADC_CFG_VREF_GAIN_MASK)
#define ADC_CFG_ADC_VCM_MASK (0xE00U)
#define ADC_CFG_ADC_VCM_SHIFT (9U)
#define ADC_CFG_ADC_VCM(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADC_VCM_SHIFT)) & ADC_CFG_ADC_VCM_MASK)
#define ADC_CFG_PGA_VCM_EN_MASK (0x1000U)
#define ADC_CFG_PGA_VCM_EN_SHIFT (12U)
#define ADC_CFG_PGA_VCM_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PGA_VCM_EN_SHIFT)) & ADC_CFG_PGA_VCM_EN_MASK)
#define ADC_CFG_PGA_VCM_DIR_MASK (0x2000U)
#define ADC_CFG_PGA_VCM_DIR_SHIFT (13U)
#define ADC_CFG_PGA_VCM_DIR(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PGA_VCM_DIR_SHIFT)) & ADC_CFG_PGA_VCM_DIR_MASK)
#define ADC_CFG_PGA_VCM_MASK (0xFC000U)
#define ADC_CFG_PGA_VCM_SHIFT (14U)
#define ADC_CFG_PGA_VCM(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PGA_VCM_SHIFT)) & ADC_CFG_PGA_VCM_MASK)
#define ADC_CFG_DOWN_SAMPLE_RATE_MASK (0x700000U)
#define ADC_CFG_DOWN_SAMPLE_RATE_SHIFT (20U)
#define ADC_CFG_DOWN_SAMPLE_RATE(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_CFG_DOWN_SAMPLE_RATE_SHIFT)) & ADC_CFG_DOWN_SAMPLE_RATE_MASK)
#define ADC_CFG_DS_DATA_STABLE_MASK (0x1F800000U)
#define ADC_CFG_DS_DATA_STABLE_SHIFT (23U)
#define ADC_CFG_DS_DATA_STABLE(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_CFG_DS_DATA_STABLE_SHIFT)) & ADC_CFG_DS_DATA_STABLE_MASK)
#define ADC_CFG_SCAN_INTV_MASK (0xE0000000U)
#define ADC_CFG_SCAN_INTV_SHIFT (29U)
#define ADC_CFG_SCAN_INTV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_SCAN_INTV_SHIFT)) & ADC_CFG_SCAN_INTV_MASK)
/* The count of ADC_CFG */
#define ADC_CFG_COUNT (2U)
/*! @name BG_BF - ADC bandcap and buffer setting register */
#define ADC_BG_BF_PGA_BM_MASK (0x7U)
#define ADC_BG_BF_PGA_BM_SHIFT (0U)
#define ADC_BG_BF_PGA_BM(x) (((uint32_t)(((uint32_t)(x)) << ADC_BG_BF_PGA_BM_SHIFT)) & ADC_BG_BF_PGA_BM_MASK)
#define ADC_BG_BF_BG_SEL_MASK (0xF0U)
#define ADC_BG_BF_BG_SEL_SHIFT (4U)
#define ADC_BG_BF_BG_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_BG_BF_BG_SEL_SHIFT)) & ADC_BG_BF_BG_SEL_MASK)
#define ADC_BG_BF_TEMP_EN_MASK (0x1000U)
#define ADC_BG_BF_TEMP_EN_SHIFT (12U)
#define ADC_BG_BF_TEMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_BG_BF_TEMP_EN_SHIFT)) & ADC_BG_BF_TEMP_EN_MASK)
#define ADC_BG_BF_PGA_CHOP_EN_MASK (0x2000U)
#define ADC_BG_BF_PGA_CHOP_EN_SHIFT (13U)
#define ADC_BG_BF_PGA_CHOP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_BG_BF_PGA_CHOP_EN_SHIFT)) & ADC_BG_BF_PGA_CHOP_EN_MASK)
#define ADC_BG_BF_PGA_BM_DIV2_MASK (0x4000U)
#define ADC_BG_BF_PGA_BM_DIV2_SHIFT (14U)
#define ADC_BG_BF_PGA_BM_DIV2(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_BG_BF_PGA_BM_DIV2_SHIFT)) & ADC_BG_BF_PGA_BM_DIV2_MASK)
/*! @name ANA_CTRL - ADC core and reference setting regsiter */
#define ADC_ANA_CTRL_ADC_BM_MASK (0x7U)
#define ADC_ANA_CTRL_ADC_BM_SHIFT (0U)
#define ADC_ANA_CTRL_ADC_BM(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_ADC_BM_SHIFT)) & ADC_ANA_CTRL_ADC_BM_MASK)
#define ADC_ANA_CTRL_ADC_ORDER_MASK (0x10U)
#define ADC_ANA_CTRL_ADC_ORDER_SHIFT (4U)
#define ADC_ANA_CTRL_ADC_ORDER(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_ADC_ORDER_SHIFT)) & ADC_ANA_CTRL_ADC_ORDER_MASK)
#define ADC_ANA_CTRL_DITHER_EN_MASK (0x20U)
#define ADC_ANA_CTRL_DITHER_EN_SHIFT (5U)
#define ADC_ANA_CTRL_DITHER_EN(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_DITHER_EN_SHIFT)) & ADC_ANA_CTRL_DITHER_EN_MASK)
#define ADC_ANA_CTRL_CHOP_EN_MASK (0x40U)
#define ADC_ANA_CTRL_CHOP_EN_SHIFT (6U)
#define ADC_ANA_CTRL_CHOP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_CHOP_EN_SHIFT)) & ADC_ANA_CTRL_CHOP_EN_MASK)
#define ADC_ANA_CTRL_INV_CLK_MASK (0x80U)
#define ADC_ANA_CTRL_INV_CLK_SHIFT (7U)
#define ADC_ANA_CTRL_INV_CLK(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_INV_CLK_SHIFT)) & ADC_ANA_CTRL_INV_CLK_MASK)
#define ADC_ANA_CTRL_VREF_BM_MASK (0x700U)
#define ADC_ANA_CTRL_VREF_BM_SHIFT (8U)
#define ADC_ANA_CTRL_VREF_BM(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_VREF_BM_SHIFT)) & ADC_ANA_CTRL_VREF_BM_MASK)
#define ADC_ANA_CTRL_VREF_BM_X3_MASK (0x800U)
#define ADC_ANA_CTRL_VREF_BM_X3_SHIFT (11U)
#define ADC_ANA_CTRL_VREF_BM_X3(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_VREF_BM_X3_SHIFT)) & ADC_ANA_CTRL_VREF_BM_X3_MASK)
#define ADC_ANA_CTRL_VINN_IN_BM_MASK (0x7000U)
#define ADC_ANA_CTRL_VINN_IN_BM_SHIFT (12U)
#define ADC_ANA_CTRL_VINN_IN_BM(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_VINN_IN_BM_SHIFT)) & ADC_ANA_CTRL_VINN_IN_BM_MASK)
#define ADC_ANA_CTRL_VINN_OUT_BM_MASK (0x70000U)
#define ADC_ANA_CTRL_VINN_OUT_BM_SHIFT (16U)
#define ADC_ANA_CTRL_VINN_OUT_BM(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_VINN_OUT_BM_SHIFT)) & ADC_ANA_CTRL_VINN_OUT_BM_MASK)
#define ADC_ANA_CTRL_VINN_OUT_BM_X3_MASK (0x80000U)
#define ADC_ANA_CTRL_VINN_OUT_BM_X3_SHIFT (19U)
#define ADC_ANA_CTRL_VINN_OUT_BM_X3(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_VINN_OUT_BM_X3_SHIFT)) & ADC_ANA_CTRL_VINN_OUT_BM_X3_MASK)
#define ADC_ANA_CTRL_ADC_BM_DIV2_MASK (0x100000U)
#define ADC_ANA_CTRL_ADC_BM_DIV2_SHIFT (20U)
#define ADC_ANA_CTRL_ADC_BM_DIV2(x) \
(((uint32_t)(((uint32_t)(x)) << ADC_ANA_CTRL_ADC_BM_DIV2_SHIFT)) & ADC_ANA_CTRL_ADC_BM_DIV2_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC base address */
#define ADC_BASE (0x40007000u)
/** Peripheral ADC base pointer */
#define ADC ((ADC_Type *)ADC_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS \
{ \
ADC_BASE \
}
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS \
{ \
ADC \
}
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS \
{ \
ADC_IRQn \
}
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AGC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AGC_Peripheral_Access_Layer AGC Peripheral Access Layer
* @{
*/
/** AGC - Register Layout Typedef */
typedef struct
{
__IO uint32_t CTRL0; /**< AGC control register 0, offset: 0x0 */
__IO uint32_t CTRL1; /**< AGC control register 1, offset: 0x4 */
__IO uint32_t CTRL2; /**< AGC control register 2, offset: 0x8 */
__IO uint32_t CTRL3; /**< AGC control register 3, offset: 0xC */
__IO uint32_t CTRL4; /**< AGC control register 4, offset: 0x10 */
__IO uint32_t CTRL5; /**< AGC control register 5, offset: 0x14 */
__I uint32_t STAT; /**< AGC status register, offset: 0x18 */
} AGC_Type;
/* ----------------------------------------------------------------------------
-- AGC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AGC_Register_Masks AGC Register Masks
* @{
*/
/*! @name CTRL0 - AGC control register 0 */
#define AGC_CTRL0_PPF_INTRPT_MOD_MASK (0x3U)
#define AGC_CTRL0_PPF_INTRPT_MOD_SHIFT (0U)
#define AGC_CTRL0_PPF_INTRPT_MOD(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_PPF_INTRPT_MOD_SHIFT)) & AGC_CTRL0_PPF_INTRPT_MOD_MASK)
#define AGC_CTRL0_FREZ_MOD_MASK (0xCU)
#define AGC_CTRL0_FREZ_MOD_SHIFT (2U)
#define AGC_CTRL0_FREZ_MOD(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_FREZ_MOD_SHIFT)) & AGC_CTRL0_FREZ_MOD_MASK)
#define AGC_CTRL0_RRF_GAIN_SEL_MASK (0x70U)
#define AGC_CTRL0_RRF_GAIN_SEL_SHIFT (4U)
#define AGC_CTRL0_RRF_GAIN_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_RRF_GAIN_SEL_SHIFT)) & AGC_CTRL0_RRF_GAIN_SEL_MASK)
#define AGC_CTRL0_RRF_WEN_MASK (0x80U)
#define AGC_CTRL0_RRF_WEN_SHIFT (7U)
#define AGC_CTRL0_RRF_WEN(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_RRF_WEN_SHIFT)) & AGC_CTRL0_RRF_WEN_MASK)
#define AGC_CTRL0_PPF_GAIN_MASK (0xF00U)
#define AGC_CTRL0_PPF_GAIN_SHIFT (8U)
#define AGC_CTRL0_PPF_GAIN(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_PPF_GAIN_SHIFT)) & AGC_CTRL0_PPF_GAIN_MASK)
#define AGC_CTRL0_PPF_WEN_MASK (0x1000U)
#define AGC_CTRL0_PPF_WEN_SHIFT (12U)
#define AGC_CTRL0_PPF_WEN(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_PPF_WEN_SHIFT)) & AGC_CTRL0_PPF_WEN_MASK)
#define AGC_CTRL0_PKWT_TH_DIG_1_MASK (0x3E000U)
#define AGC_CTRL0_PKWT_TH_DIG_1_SHIFT (13U)
#define AGC_CTRL0_PKWT_TH_DIG_1(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_PKWT_TH_DIG_1_SHIFT)) & AGC_CTRL0_PKWT_TH_DIG_1_MASK)
#define AGC_CTRL0_PD_CLR_EN_MASK (0x40000U)
#define AGC_CTRL0_PD_CLR_EN_SHIFT (18U)
#define AGC_CTRL0_PD_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_PD_CLR_EN_SHIFT)) & AGC_CTRL0_PD_CLR_EN_MASK)
#define AGC_CTRL0_PD_RST_LEN_MASK (0x380000U)
#define AGC_CTRL0_PD_RST_LEN_SHIFT (19U)
#define AGC_CTRL0_PD_RST_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_PD_RST_LEN_SHIFT)) & AGC_CTRL0_PD_RST_LEN_MASK)
#define AGC_CTRL0_RFAGC_FSYNC_DET_DIS_MASK (0x400000U)
#define AGC_CTRL0_RFAGC_FSYNC_DET_DIS_SHIFT (22U)
#define AGC_CTRL0_RFAGC_FSYNC_DET_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_RFAGC_FSYNC_DET_DIS_SHIFT)) & AGC_CTRL0_RFAGC_FSYNC_DET_DIS_MASK)
#define AGC_CTRL0_RFAGC_DIRECTION_FREEZE_MASK (0x800000U)
#define AGC_CTRL0_RFAGC_DIRECTION_FREEZE_SHIFT (23U)
#define AGC_CTRL0_RFAGC_DIRECTION_FREEZE(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_RFAGC_DIRECTION_FREEZE_SHIFT)) & AGC_CTRL0_RFAGC_DIRECTION_FREEZE_MASK)
#define AGC_CTRL0_DOWN_24_EN_MASK (0x1000000U)
#define AGC_CTRL0_DOWN_24_EN_SHIFT (24U)
#define AGC_CTRL0_DOWN_24_EN(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_DOWN_24_EN_SHIFT)) & AGC_CTRL0_DOWN_24_EN_MASK)
#define AGC_CTRL0_SWITCH_PD_RST_LEN_MASK (0x6000000U)
#define AGC_CTRL0_SWITCH_PD_RST_LEN_SHIFT (25U)
#define AGC_CTRL0_SWITCH_PD_RST_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_SWITCH_PD_RST_LEN_SHIFT)) & AGC_CTRL0_SWITCH_PD_RST_LEN_MASK)
#define AGC_CTRL0_GLNA_MAX_REDU_MASK (0x8000000U)
#define AGC_CTRL0_GLNA_MAX_REDU_SHIFT (27U)
#define AGC_CTRL0_GLNA_MAX_REDU(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL0_GLNA_MAX_REDU_SHIFT)) & AGC_CTRL0_GLNA_MAX_REDU_MASK)
/*! @name CTRL1 - AGC control register 1 */
#define AGC_CTRL1_PD3_TH_REG_MASK (0x7U)
#define AGC_CTRL1_PD3_TH_REG_SHIFT (0U)
#define AGC_CTRL1_PD3_TH_REG(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL1_PD3_TH_REG_SHIFT)) & AGC_CTRL1_PD3_TH_REG_MASK)
#define AGC_CTRL1_PD3_TH_HYST_REG_MASK (0x78U)
#define AGC_CTRL1_PD3_TH_HYST_REG_SHIFT (3U)
#define AGC_CTRL1_PD3_TH_HYST_REG(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL1_PD3_TH_HYST_REG_SHIFT)) & AGC_CTRL1_PD3_TH_HYST_REG_MASK)
#define AGC_CTRL1_PKWT_TH_ANA_1_MASK (0x1F80U)
#define AGC_CTRL1_PKWT_TH_ANA_1_SHIFT (7U)
#define AGC_CTRL1_PKWT_TH_ANA_1(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL1_PKWT_TH_ANA_1_SHIFT)) & AGC_CTRL1_PKWT_TH_ANA_1_MASK)
#define AGC_CTRL1_PKWT_TH_ANA_0_MASK (0x3E000U)
#define AGC_CTRL1_PKWT_TH_ANA_0_SHIFT (13U)
#define AGC_CTRL1_PKWT_TH_ANA_0(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL1_PKWT_TH_ANA_0_SHIFT)) & AGC_CTRL1_PKWT_TH_ANA_0_MASK)
#define AGC_CTRL1_PKWT_TH_DIG_0_MASK (0x7C0000U)
#define AGC_CTRL1_PKWT_TH_DIG_0_SHIFT (18U)
#define AGC_CTRL1_PKWT_TH_DIG_0(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL1_PKWT_TH_DIG_0_SHIFT)) & AGC_CTRL1_PKWT_TH_DIG_0_MASK)
#define AGC_CTRL1_SETL_TH_PPF_2_MASK (0xF800000U)
#define AGC_CTRL1_SETL_TH_PPF_2_SHIFT (23U)
#define AGC_CTRL1_SETL_TH_PPF_2(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL1_SETL_TH_PPF_2_SHIFT)) & AGC_CTRL1_SETL_TH_PPF_2_MASK)
/*! @name CTRL2 - AGC control register 2 */
#define AGC_CTRL2_PPF_PDVTH_LOW_MASK (0x100U)
#define AGC_CTRL2_PPF_PDVTH_LOW_SHIFT (8U)
#define AGC_CTRL2_PPF_PDVTH_LOW(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL2_PPF_PDVTH_LOW_SHIFT)) & AGC_CTRL2_PPF_PDVTH_LOW_MASK)
#define AGC_CTRL2_RRF_MG_PK_MASK (0xE00U)
#define AGC_CTRL2_RRF_MG_PK_SHIFT (9U)
#define AGC_CTRL2_RRF_MG_PK(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL2_RRF_MG_PK_SHIFT)) & AGC_CTRL2_RRF_MG_PK_MASK)
#define AGC_CTRL2_RRF_HG_PK_MASK (0x7000U)
#define AGC_CTRL2_RRF_HG_PK_SHIFT (12U)
#define AGC_CTRL2_RRF_HG_PK(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL2_RRF_HG_PK_SHIFT)) & AGC_CTRL2_RRF_HG_PK_MASK)
/*! @name CTRL3 - AGC control register 3 */
#define AGC_CTRL3_GF2_PAR00_MASK (0xFU)
#define AGC_CTRL3_GF2_PAR00_SHIFT (0U)
#define AGC_CTRL3_GF2_PAR00(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL3_GF2_PAR00_SHIFT)) & AGC_CTRL3_GF2_PAR00_MASK)
#define AGC_CTRL3_GF2_PAR01_MASK (0xF0U)
#define AGC_CTRL3_GF2_PAR01_SHIFT (4U)
#define AGC_CTRL3_GF2_PAR01(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL3_GF2_PAR01_SHIFT)) & AGC_CTRL3_GF2_PAR01_MASK)
#define AGC_CTRL3_GF2_PAR10_MASK (0xF00U)
#define AGC_CTRL3_GF2_PAR10_SHIFT (8U)
#define AGC_CTRL3_GF2_PAR10(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL3_GF2_PAR10_SHIFT)) & AGC_CTRL3_GF2_PAR10_MASK)
#define AGC_CTRL3_SETL_TH_OVSHT_DIG_MASK (0x7000U)
#define AGC_CTRL3_SETL_TH_OVSHT_DIG_SHIFT (12U)
#define AGC_CTRL3_SETL_TH_OVSHT_DIG(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL3_SETL_TH_OVSHT_DIG_SHIFT)) & AGC_CTRL3_SETL_TH_OVSHT_DIG_MASK)
#define AGC_CTRL3_SETL_TH_OVSHT_INTRPT_MASK (0x38000U)
#define AGC_CTRL3_SETL_TH_OVSHT_INTRPT_SHIFT (15U)
#define AGC_CTRL3_SETL_TH_OVSHT_INTRPT(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL3_SETL_TH_OVSHT_INTRPT_SHIFT)) & AGC_CTRL3_SETL_TH_OVSHT_INTRPT_MASK)
#define AGC_CTRL3_SETL_TH_OVSHT_MASK (0x1C0000U)
#define AGC_CTRL3_SETL_TH_OVSHT_SHIFT (18U)
#define AGC_CTRL3_SETL_TH_OVSHT(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL3_SETL_TH_OVSHT_SHIFT)) & AGC_CTRL3_SETL_TH_OVSHT_MASK)
/*! @name CTRL4 - AGC control register 4 */
#define AGC_CTRL4_SETL_TH_PD1_MASK (0xFU)
#define AGC_CTRL4_SETL_TH_PD1_SHIFT (0U)
#define AGC_CTRL4_SETL_TH_PD1(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL4_SETL_TH_PD1_SHIFT)) & AGC_CTRL4_SETL_TH_PD1_MASK)
#define AGC_CTRL4_SETL_TH_PD2_MASK (0xF0U)
#define AGC_CTRL4_SETL_TH_PD2_SHIFT (4U)
#define AGC_CTRL4_SETL_TH_PD2(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL4_SETL_TH_PD2_SHIFT)) & AGC_CTRL4_SETL_TH_PD2_MASK)
#define AGC_CTRL4_SETL_TH_PD3_1_MASK (0x3F00U)
#define AGC_CTRL4_SETL_TH_PD3_1_SHIFT (8U)
#define AGC_CTRL4_SETL_TH_PD3_1(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL4_SETL_TH_PD3_1_SHIFT)) & AGC_CTRL4_SETL_TH_PD3_1_MASK)
#define AGC_CTRL4_SETL_TH_PD3_2_MASK (0xFC000U)
#define AGC_CTRL4_SETL_TH_PD3_2_SHIFT (14U)
#define AGC_CTRL4_SETL_TH_PD3_2(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL4_SETL_TH_PD3_2_SHIFT)) & AGC_CTRL4_SETL_TH_PD3_2_MASK)
#define AGC_CTRL4_GF2_STAT24_TH_MASK (0xF00000U)
#define AGC_CTRL4_GF2_STAT24_TH_SHIFT (20U)
#define AGC_CTRL4_GF2_STAT24_TH(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_CTRL4_GF2_STAT24_TH_SHIFT)) & AGC_CTRL4_GF2_STAT24_TH_MASK)
/*! @name CTRL5 - AGC control register 5 */
#define AGC_CTRL5_TEST_CTRL_MASK (0xFU)
#define AGC_CTRL5_TEST_CTRL_SHIFT (0U)
#define AGC_CTRL5_TEST_CTRL(x) (((uint32_t)(((uint32_t)(x)) << AGC_CTRL5_TEST_CTRL_SHIFT)) & AGC_CTRL5_TEST_CTRL_MASK)
/*! @name STAT - AGC status register */
#define AGC_STAT_GLNA_CODE_OUT_MASK (0x7U)
#define AGC_STAT_GLNA_CODE_OUT_SHIFT (0U)
#define AGC_STAT_GLNA_CODE_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_STAT_GLNA_CODE_OUT_SHIFT)) & AGC_STAT_GLNA_CODE_OUT_MASK)
#define AGC_STAT_GF2_CODE_OUT_MASK (0x78U)
#define AGC_STAT_GF2_CODE_OUT_SHIFT (3U)
#define AGC_STAT_GF2_CODE_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_STAT_GF2_CODE_OUT_SHIFT)) & AGC_STAT_GF2_CODE_OUT_MASK)
#define AGC_STAT_RFAGC_TRIGGER_O_MASK (0x80U)
#define AGC_STAT_RFAGC_TRIGGER_O_SHIFT (7U)
#define AGC_STAT_RFAGC_TRIGGER_O(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_STAT_RFAGC_TRIGGER_O_SHIFT)) & AGC_STAT_RFAGC_TRIGGER_O_MASK)
#define AGC_STAT_RF_GAIN_MASK (0x7F00U)
#define AGC_STAT_RF_GAIN_SHIFT (8U)
#define AGC_STAT_RF_GAIN(x) (((uint32_t)(((uint32_t)(x)) << AGC_STAT_RF_GAIN_SHIFT)) & AGC_STAT_RF_GAIN_MASK)
#define AGC_STAT_NUM_GAIN_ADJ_MASK (0xF8000U)
#define AGC_STAT_NUM_GAIN_ADJ_SHIFT (15U)
#define AGC_STAT_NUM_GAIN_ADJ(x) \
(((uint32_t)(((uint32_t)(x)) << AGC_STAT_NUM_GAIN_ADJ_SHIFT)) & AGC_STAT_NUM_GAIN_ADJ_MASK)
#define AGC_STAT_CUR_STAT_MASK (0x700000U)
#define AGC_STAT_CUR_STAT_SHIFT (20U)
#define AGC_STAT_CUR_STAT(x) (((uint32_t)(((uint32_t)(x)) << AGC_STAT_CUR_STAT_SHIFT)) & AGC_STAT_CUR_STAT_MASK)
/*!
* @}
*/ /* end of group AGC_Register_Masks */
/* AGC - Peripheral instance base addresses */
/** Peripheral AGC base address */
#define AGC_BASE (0x4000C000u)
/** Peripheral AGC base pointer */
#define AGC ((AGC_Type *)AGC_BASE)
/** Array initializer of AGC peripheral base addresses */
#define AGC_BASE_ADDRS \
{ \
AGC_BASE \
}
/** Array initializer of AGC peripheral base pointers */
#define AGC_BASE_PTRS \
{ \
AGC \
}
/*!
* @}
*/ /* end of group AGC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- BLEDP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup BLEDP_Peripheral_Access_Layer BLEDP Peripheral Access Layer
* @{
*/
/** BLEDP - Register Layout Typedef */
typedef struct
{
__IO uint32_t DP_TOP_SYSTEM_CTRL; /**< datapath system control register, offset: 0x0 */
__IO uint32_t PROP_MODE_CTRL; /**< properity mode control register, offset: 0x4 */
__IO uint32_t ACCESS_ADDRESS; /**< access address register, offset: 0x8 */
__IO uint32_t ANT_PDU_DATA0; /**< pdu data 0 to 1 byte, and preamble register, offset: 0xC */
__IO uint32_t ANT_PDU_DATA1; /**< pdu data 2 to 5 byte, offset: 0x10 */
__IO uint32_t ANT_PDU_DATA2; /**< pdu data 6 to 9 byte, offset: 0x14 */
__IO uint32_t ANT_PDU_DATA3; /**< pdu data 10 to 13 byte, offset: 0x18 */
__IO uint32_t ANT_PDU_DATA4; /**< pdu data 14 to 17 byte, offset: 0x1C */
__IO uint32_t ANT_PDU_DATA5; /**< pdu data 18 to 21 byte, offset: 0x20 */
__IO uint32_t ANT_PDU_DATA6; /**< pdu data 22 to 25 byte, offset: 0x24 */
__IO uint32_t ANT_PDU_DATA7; /**< pdu data 26 to 29 byte, offset: 0x28 */
__IO uint32_t CRCSEED; /**< crc seed, offset: 0x2C */
__IO uint32_t DP_FUNCTION_CTRL; /**< datapath function control register, offset: 0x30 */
__IO uint32_t DP_TEST_CTRL; /**< datapath test iinterface register, offset: 0x34 */
__I uint32_t BLE_DP_STATUS1; /**< datapath status register 1, offset: 0x38 */
__I uint32_t BLE_DP_STATUS2; /**< datapath status register 2, offset: 0x3C */
__I uint32_t BLE_DP_STATUS3; /**< datapath status register 3, offset: 0x40 */
__I uint32_t BLE_DP_STATUS4; /**< datapath status register 4, offset: 0x44 */
__IO uint32_t RX_FRONT_END_CTRL1; /**< rx front end control register 1, offset: 0x48 */
__IO uint32_t RX_FRONT_END_CTRL2; /**< rx front end control register 2, offset: 0x4C */
__IO uint32_t FREQ_DOMAIN_CTRL1; /**< frequency domain control register 1, offset: 0x50 */
__IO uint32_t FREQ_DOMAIN_CTRL2; /**< frequency domain control register 2, offset: 0x54 */
__IO uint32_t FREQ_DOMAIN_CTRL3; /**< frequency domain control register 3, offset: 0x58 */
__IO uint32_t FREQ_DOMAIN_CTRL4; /**< frequency domain control register 4, offset: 0x5C */
__IO uint32_t FREQ_DOMAIN_CTRL5; /**< frequency domain control register 5, offset: 0x60 */
__IO uint32_t FREQ_DOMAIN_CTRL6; /**< frequency domain control register 5, offset: 0x64 */
__IO uint32_t HP_MODE_CTRL1; /**< when high hp mode training size same as cfo tracking., offset: 0x68 */
__IO uint32_t HP_MODE_CTRL2; /**< q paramter in training period of phase offset iir of bmc, offset: 0x6C */
__I uint32_t FREQ_DOMAIN_STATUS1; /**< frequency domain status register 1, offset: 0x70 */
__I uint32_t FREQ_DOMAIN_STATUS2; /**< frequency domain status register 2, offset: 0x74 */
uint8_t RESERVED_0[12];
__IO uint32_t DP_AA_ERROR_CTRL; /**< AA error control register, offset: 0x84 */
__IO uint32_t DP_INT; /**< data path interrupt register, offset: 0x88 */
__IO uint32_t DP_AA_ERROR_TH; /**< AA error threshold register, offset: 0x8C */
__IO uint32_t DF_ANTENNA_CTRL; /**< antenna register, offset: 0x90 */
__IO uint32_t ANTENNA_MAP01; /**< antenna switch map register 0, offset: 0x94 */
__IO uint32_t ANTENNA_MAP23; /**< antenna switch map register 1, offset: 0x98 */
__IO uint32_t ANTENNA_MAP45; /**< antenna switch map register 2, offset: 0x9C */
__IO uint32_t ANTENNA_MAP67; /**< antenna switch map register 3, offset: 0xA0 */
} BLEDP_Type;
/* ----------------------------------------------------------------------------
-- BLEDP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup BLEDP_Register_Masks BLEDP Register Masks
* @{
*/
/*! @name DP_TOP_SYSTEM_CTRL - datapath system control register */
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_PDU_LEN_IN_MASK (0x3FFFU)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_PDU_LEN_IN_SHIFT (0U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_PDU_LEN_IN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_RX_PDU_LEN_IN_SHIFT)) & \
BLEDP_DP_TOP_SYSTEM_CTRL_RX_PDU_LEN_IN_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_AA_SEL_MASK (0x4000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_AA_SEL_SHIFT (14U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_AA_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_AA_SEL_SHIFT)) & BLEDP_DP_TOP_SYSTEM_CTRL_AA_SEL_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_PDU_LEN_SEL_MASK (0x8000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_PDU_LEN_SEL_SHIFT (15U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_PDU_LEN_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_PDU_LEN_SEL_SHIFT)) & \
BLEDP_DP_TOP_SYSTEM_CTRL_PDU_LEN_SEL_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_H_IDX_MASK (0xFF0000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_H_IDX_SHIFT (16U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_H_IDX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_H_IDX_SHIFT)) & BLEDP_DP_TOP_SYSTEM_CTRL_H_IDX_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_EN_SEL_MASK (0x1000000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_EN_SEL_SHIFT (24U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_EN_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_RX_EN_SEL_SHIFT)) & \
BLEDP_DP_TOP_SYSTEM_CTRL_RX_EN_SEL_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_TX_EN_SEL_MASK (0x2000000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_TX_EN_SEL_SHIFT (25U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_TX_EN_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_TX_EN_SEL_SHIFT)) & \
BLEDP_DP_TOP_SYSTEM_CTRL_TX_EN_SEL_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_REQ_MASK (0x4000000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_REQ_SHIFT (26U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_RX_REQ_SHIFT)) & BLEDP_DP_TOP_SYSTEM_CTRL_RX_REQ_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_TX_REQ_MASK (0x8000000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_TX_REQ_SHIFT (27U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_TX_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_TX_REQ_SHIFT)) & BLEDP_DP_TOP_SYSTEM_CTRL_TX_REQ_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_MODE_MASK (0x30000000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_MODE_SHIFT (28U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_RX_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_RX_MODE_SHIFT)) & BLEDP_DP_TOP_SYSTEM_CTRL_RX_MODE_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_ANT_DATA_START_MASK (0x40000000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_ANT_DATA_START_SHIFT (30U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_ANT_DATA_START(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_ANT_DATA_START_SHIFT)) & \
BLEDP_DP_TOP_SYSTEM_CTRL_ANT_DATA_START_MASK)
#define BLEDP_DP_TOP_SYSTEM_CTRL_DET_MODE_MASK (0x80000000U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_DET_MODE_SHIFT (31U)
#define BLEDP_DP_TOP_SYSTEM_CTRL_DET_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TOP_SYSTEM_CTRL_DET_MODE_SHIFT)) & BLEDP_DP_TOP_SYSTEM_CTRL_DET_MODE_MASK)
/*! @name PROP_MODE_CTRL - properity mode control register */
#define BLEDP_PROP_MODE_CTRL_PROP_AA_ADDR_IN_MASK (0xFFU)
#define BLEDP_PROP_MODE_CTRL_PROP_AA_ADDR_IN_SHIFT (0U)
#define BLEDP_PROP_MODE_CTRL_PROP_AA_ADDR_IN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_PROP_AA_ADDR_IN_SHIFT)) & \
BLEDP_PROP_MODE_CTRL_PROP_AA_ADDR_IN_MASK)
#define BLEDP_PROP_MODE_CTRL_PROP_CRC_NUM_MASK (0x300U)
#define BLEDP_PROP_MODE_CTRL_PROP_CRC_NUM_SHIFT (8U)
#define BLEDP_PROP_MODE_CTRL_PROP_CRC_NUM(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_PROP_CRC_NUM_SHIFT)) & BLEDP_PROP_MODE_CTRL_PROP_CRC_NUM_MASK)
#define BLEDP_PROP_MODE_CTRL_PROP_AA_NUM_MASK (0x3000U)
#define BLEDP_PROP_MODE_CTRL_PROP_AA_NUM_SHIFT (12U)
#define BLEDP_PROP_MODE_CTRL_PROP_AA_NUM(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_PROP_AA_NUM_SHIFT)) & BLEDP_PROP_MODE_CTRL_PROP_AA_NUM_MASK)
#define BLEDP_PROP_MODE_CTRL_PROP_PRE_NUM_MASK (0x70000U)
#define BLEDP_PROP_MODE_CTRL_PROP_PRE_NUM_SHIFT (16U)
#define BLEDP_PROP_MODE_CTRL_PROP_PRE_NUM(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_PROP_PRE_NUM_SHIFT)) & BLEDP_PROP_MODE_CTRL_PROP_PRE_NUM_MASK)
#define BLEDP_PROP_MODE_CTRL_PROP_DATA_RATE_MASK (0x300000U)
#define BLEDP_PROP_MODE_CTRL_PROP_DATA_RATE_SHIFT (20U)
#define BLEDP_PROP_MODE_CTRL_PROP_DATA_RATE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_PROP_DATA_RATE_SHIFT)) & \
BLEDP_PROP_MODE_CTRL_PROP_DATA_RATE_MASK)
#define BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_RATE_MASK (0xC00000U)
#define BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_RATE_SHIFT (22U)
#define BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_RATE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_RATE_SHIFT)) & \
BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_RATE_MASK)
#define BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_MODE_MASK (0x1000000U)
#define BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_MODE_SHIFT (24U)
#define BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_MODE_SHIFT)) & \
BLEDP_PROP_MODE_CTRL_PROP_DIRECTION_MODE_MASK)
#define BLEDP_PROP_MODE_CTRL_RX_ALWAYS_ON_MASK (0x2000000U)
#define BLEDP_PROP_MODE_CTRL_RX_ALWAYS_ON_SHIFT (25U)
#define BLEDP_PROP_MODE_CTRL_RX_ALWAYS_ON(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_RX_ALWAYS_ON_SHIFT)) & BLEDP_PROP_MODE_CTRL_RX_ALWAYS_ON_MASK)
#define BLEDP_PROP_MODE_CTRL_TX_ALWAYS_ON_MASK (0x4000000U)
#define BLEDP_PROP_MODE_CTRL_TX_ALWAYS_ON_SHIFT (26U)
#define BLEDP_PROP_MODE_CTRL_TX_ALWAYS_ON(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_TX_ALWAYS_ON_SHIFT)) & BLEDP_PROP_MODE_CTRL_TX_ALWAYS_ON_MASK)
#define BLEDP_PROP_MODE_CTRL_TX_POWER_DONE_TIME_MASK (0xF8000000U)
#define BLEDP_PROP_MODE_CTRL_TX_POWER_DONE_TIME_SHIFT (27U)
#define BLEDP_PROP_MODE_CTRL_TX_POWER_DONE_TIME(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_PROP_MODE_CTRL_TX_POWER_DONE_TIME_SHIFT)) & \
BLEDP_PROP_MODE_CTRL_TX_POWER_DONE_TIME_MASK)
/*! @name ACCESS_ADDRESS - access address register */
#define BLEDP_ACCESS_ADDRESS_AA_ADDR_IN_MASK (0xFFFFFFFFU)
#define BLEDP_ACCESS_ADDRESS_AA_ADDR_IN_SHIFT (0U)
#define BLEDP_ACCESS_ADDRESS_AA_ADDR_IN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ACCESS_ADDRESS_AA_ADDR_IN_SHIFT)) & BLEDP_ACCESS_ADDRESS_AA_ADDR_IN_MASK)
/*! @name ANT_PDU_DATA0 - pdu data 0 to 1 byte, and preamble register */
#define BLEDP_ANT_PDU_DATA0_PDU_DATA0_MASK (0xFFFFU)
#define BLEDP_ANT_PDU_DATA0_PDU_DATA0_SHIFT (0U)
#define BLEDP_ANT_PDU_DATA0_PDU_DATA0(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA0_PDU_DATA0_SHIFT)) & BLEDP_ANT_PDU_DATA0_PDU_DATA0_MASK)
#define BLEDP_ANT_PDU_DATA0_PATTERN_SEL_MASK (0xF0000U)
#define BLEDP_ANT_PDU_DATA0_PATTERN_SEL_SHIFT (16U)
#define BLEDP_ANT_PDU_DATA0_PATTERN_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA0_PATTERN_SEL_SHIFT)) & BLEDP_ANT_PDU_DATA0_PATTERN_SEL_MASK)
#define BLEDP_ANT_PDU_DATA0_TEST_PATTERN_EN_MASK (0x100000U)
#define BLEDP_ANT_PDU_DATA0_TEST_PATTERN_EN_SHIFT (20U)
#define BLEDP_ANT_PDU_DATA0_TEST_PATTERN_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA0_TEST_PATTERN_EN_SHIFT)) & \
BLEDP_ANT_PDU_DATA0_TEST_PATTERN_EN_MASK)
#define BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_WEN_MASK (0x800000U)
#define BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_WEN_SHIFT (23U)
#define BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_WEN_SHIFT)) & \
BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_WEN_MASK)
#define BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_MASK (0xFF000000U)
#define BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_SHIFT (24U)
#define BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_SHIFT)) & BLEDP_ANT_PDU_DATA0_PROP_PREAMBLE_MASK)
/*! @name ANT_PDU_DATA1 - pdu data 2 to 5 byte */
#define BLEDP_ANT_PDU_DATA1_PDU_DATA1_MASK (0xFFFFFFFFU)
#define BLEDP_ANT_PDU_DATA1_PDU_DATA1_SHIFT (0U)
#define BLEDP_ANT_PDU_DATA1_PDU_DATA1(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA1_PDU_DATA1_SHIFT)) & BLEDP_ANT_PDU_DATA1_PDU_DATA1_MASK)
/*! @name ANT_PDU_DATA2 - pdu data 6 to 9 byte */
#define BLEDP_ANT_PDU_DATA2_PDU_DATA2_MASK (0xFFFFFFFFU)
#define BLEDP_ANT_PDU_DATA2_PDU_DATA2_SHIFT (0U)
#define BLEDP_ANT_PDU_DATA2_PDU_DATA2(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA2_PDU_DATA2_SHIFT)) & BLEDP_ANT_PDU_DATA2_PDU_DATA2_MASK)
/*! @name ANT_PDU_DATA3 - pdu data 10 to 13 byte */
#define BLEDP_ANT_PDU_DATA3_PDU_DATA3_MASK (0xFFFFFFFFU)
#define BLEDP_ANT_PDU_DATA3_PDU_DATA3_SHIFT (0U)
#define BLEDP_ANT_PDU_DATA3_PDU_DATA3(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA3_PDU_DATA3_SHIFT)) & BLEDP_ANT_PDU_DATA3_PDU_DATA3_MASK)
/*! @name ANT_PDU_DATA4 - pdu data 14 to 17 byte */
#define BLEDP_ANT_PDU_DATA4_PDU_DATA4_MASK (0xFFFFFFFFU)
#define BLEDP_ANT_PDU_DATA4_PDU_DATA4_SHIFT (0U)
#define BLEDP_ANT_PDU_DATA4_PDU_DATA4(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA4_PDU_DATA4_SHIFT)) & BLEDP_ANT_PDU_DATA4_PDU_DATA4_MASK)
/*! @name ANT_PDU_DATA5 - pdu data 18 to 21 byte */
#define BLEDP_ANT_PDU_DATA5_PDU_DATA5_MASK (0xFFFFFFFFU)
#define BLEDP_ANT_PDU_DATA5_PDU_DATA5_SHIFT (0U)
#define BLEDP_ANT_PDU_DATA5_PDU_DATA5(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA5_PDU_DATA5_SHIFT)) & BLEDP_ANT_PDU_DATA5_PDU_DATA5_MASK)
/*! @name ANT_PDU_DATA6 - pdu data 22 to 25 byte */
#define BLEDP_ANT_PDU_DATA6_PDU_DATA6_MASK (0xFFFFFFFFU)
#define BLEDP_ANT_PDU_DATA6_PDU_DATA6_SHIFT (0U)
#define BLEDP_ANT_PDU_DATA6_PDU_DATA6(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA6_PDU_DATA6_SHIFT)) & BLEDP_ANT_PDU_DATA6_PDU_DATA6_MASK)
/*! @name ANT_PDU_DATA7 - pdu data 26 to 29 byte */
#define BLEDP_ANT_PDU_DATA7_PDU_DATA7_MASK (0xFFFFFFFFU)
#define BLEDP_ANT_PDU_DATA7_PDU_DATA7_SHIFT (0U)
#define BLEDP_ANT_PDU_DATA7_PDU_DATA7(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANT_PDU_DATA7_PDU_DATA7_SHIFT)) & BLEDP_ANT_PDU_DATA7_PDU_DATA7_MASK)
/*! @name CRCSEED - crc seed */
#define BLEDP_CRCSEED_CRC_SEED_IN_MASK (0xFFFFFFU)
#define BLEDP_CRCSEED_CRC_SEED_IN_SHIFT (0U)
#define BLEDP_CRCSEED_CRC_SEED_IN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_CRCSEED_CRC_SEED_IN_SHIFT)) & BLEDP_CRCSEED_CRC_SEED_IN_MASK)
#define BLEDP_CRCSEED_CRC_SEED_WEN_MASK (0x1000000U)
#define BLEDP_CRCSEED_CRC_SEED_WEN_SHIFT (24U)
#define BLEDP_CRCSEED_CRC_SEED_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_CRCSEED_CRC_SEED_WEN_SHIFT)) & BLEDP_CRCSEED_CRC_SEED_WEN_MASK)
/*! @name DP_FUNCTION_CTRL - datapath function control register */
#define BLEDP_DP_FUNCTION_CTRL_DP_STATISTICS_SEL_MASK (0x7U)
#define BLEDP_DP_FUNCTION_CTRL_DP_STATISTICS_SEL_SHIFT (0U)
#define BLEDP_DP_FUNCTION_CTRL_DP_STATISTICS_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_DP_STATISTICS_SEL_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_DP_STATISTICS_SEL_MASK)
#define BLEDP_DP_FUNCTION_CTRL_CHF_COEF_WEN_MASK (0x8U)
#define BLEDP_DP_FUNCTION_CTRL_CHF_COEF_WEN_SHIFT (3U)
#define BLEDP_DP_FUNCTION_CTRL_CHF_COEF_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_CHF_COEF_WEN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_CHF_COEF_WEN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_CHF_COEF_IDX_MASK (0x30U)
#define BLEDP_DP_FUNCTION_CTRL_CHF_COEF_IDX_SHIFT (4U)
#define BLEDP_DP_FUNCTION_CTRL_CHF_COEF_IDX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_CHF_COEF_IDX_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_CHF_COEF_IDX_MASK)
#define BLEDP_DP_FUNCTION_CTRL_LP_SNR_LEN_AUTO_MASK (0x40U)
#define BLEDP_DP_FUNCTION_CTRL_LP_SNR_LEN_AUTO_SHIFT (6U)
#define BLEDP_DP_FUNCTION_CTRL_LP_SNR_LEN_AUTO(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_LP_SNR_LEN_AUTO_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_LP_SNR_LEN_AUTO_MASK)
#define BLEDP_DP_FUNCTION_CTRL_DOUT_ADJ_DIS_MASK (0x80U)
#define BLEDP_DP_FUNCTION_CTRL_DOUT_ADJ_DIS_SHIFT (7U)
#define BLEDP_DP_FUNCTION_CTRL_DOUT_ADJ_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_DOUT_ADJ_DIS_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_DOUT_ADJ_DIS_MASK)
#define BLEDP_DP_FUNCTION_CTRL_LP_ADJ_MODE_MASK (0x100U)
#define BLEDP_DP_FUNCTION_CTRL_LP_ADJ_MODE_SHIFT (8U)
#define BLEDP_DP_FUNCTION_CTRL_LP_ADJ_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_LP_ADJ_MODE_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_LP_ADJ_MODE_MASK)
#define BLEDP_DP_FUNCTION_CTRL_FR_OFFSET_EN_MASK (0x200U)
#define BLEDP_DP_FUNCTION_CTRL_FR_OFFSET_EN_SHIFT (9U)
#define BLEDP_DP_FUNCTION_CTRL_FR_OFFSET_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_FR_OFFSET_EN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_FR_OFFSET_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_DC_AVE_EN_MASK (0x400U)
#define BLEDP_DP_FUNCTION_CTRL_DC_AVE_EN_SHIFT (10U)
#define BLEDP_DP_FUNCTION_CTRL_DC_AVE_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_DC_AVE_EN_SHIFT)) & BLEDP_DP_FUNCTION_CTRL_DC_AVE_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_FIX_DELAY_EN_MASK (0x800U)
#define BLEDP_DP_FUNCTION_CTRL_FIX_DELAY_EN_SHIFT (11U)
#define BLEDP_DP_FUNCTION_CTRL_FIX_DELAY_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_FIX_DELAY_EN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_FIX_DELAY_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_MASK (0x3000U)
#define BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_SHIFT (12U)
#define BLEDP_DP_FUNCTION_CTRL_TRACK_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_SHIFT)) & BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_WEN_MASK (0x4000U)
#define BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_WEN_SHIFT (14U)
#define BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_WEN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_TRACK_LEN_WEN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_FILT_EN_MASK (0x10000U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_FILT_EN_SHIFT (16U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_FILT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_XCORR_FILT_EN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_XCORR_FILT_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_FULLWIN_EN_MASK (0x20000U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_FULLWIN_EN_SHIFT (17U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_FULLWIN_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_XCORR_FULLWIN_EN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_XCORR_FULLWIN_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_MASK (0x40000U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_SHIFT (18U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_WEN_MASK (0x80000U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_WEN_SHIFT (19U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_WEN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_XCORR_AA_LEN_WEN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_WIN_AUTO_EN_MASK (0x100000U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_WIN_AUTO_EN_SHIFT (20U)
#define BLEDP_DP_FUNCTION_CTRL_XCORR_WIN_AUTO_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_XCORR_WIN_AUTO_EN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_XCORR_WIN_AUTO_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_MASK (0x200000U)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_SHIFT (21U)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_MASK)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_WEN_MASK (0x400000U)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_WEN_SHIFT (22U)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_WEN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_RESAMPLER_TAP_WEN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_BP_MASK (0x800000U)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_BP_SHIFT (23U)
#define BLEDP_DP_FUNCTION_CTRL_RESAMPLER_BP(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_RESAMPLER_BP_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_RESAMPLER_BP_MASK)
#define BLEDP_DP_FUNCTION_CTRL_FAGC_WIN_LEN_MASK (0x1000000U)
#define BLEDP_DP_FUNCTION_CTRL_FAGC_WIN_LEN_SHIFT (24U)
#define BLEDP_DP_FUNCTION_CTRL_FAGC_WIN_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_FAGC_WIN_LEN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_FAGC_WIN_LEN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_FAGC_WEN_MASK (0x2000000U)
#define BLEDP_DP_FUNCTION_CTRL_FAGC_WEN_SHIFT (25U)
#define BLEDP_DP_FUNCTION_CTRL_FAGC_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_FAGC_WEN_SHIFT)) & BLEDP_DP_FUNCTION_CTRL_FAGC_WEN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_HP_CFO_EN_MASK (0x4000000U)
#define BLEDP_DP_FUNCTION_CTRL_HP_CFO_EN_SHIFT (26U)
#define BLEDP_DP_FUNCTION_CTRL_HP_CFO_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_HP_CFO_EN_SHIFT)) & BLEDP_DP_FUNCTION_CTRL_HP_CFO_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_CFO_TRACK_EN_MASK (0x8000000U)
#define BLEDP_DP_FUNCTION_CTRL_CFO_TRACK_EN_SHIFT (27U)
#define BLEDP_DP_FUNCTION_CTRL_CFO_TRACK_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_CFO_TRACK_EN_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_CFO_TRACK_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_CFO_INI_EN_MASK (0x10000000U)
#define BLEDP_DP_FUNCTION_CTRL_CFO_INI_EN_SHIFT (28U)
#define BLEDP_DP_FUNCTION_CTRL_CFO_INI_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_CFO_INI_EN_SHIFT)) & BLEDP_DP_FUNCTION_CTRL_CFO_INI_EN_MASK)
#define BLEDP_DP_FUNCTION_CTRL_ADC_IN_FLIP_MASK (0x20000000U)
#define BLEDP_DP_FUNCTION_CTRL_ADC_IN_FLIP_SHIFT (29U)
#define BLEDP_DP_FUNCTION_CTRL_ADC_IN_FLIP(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_ADC_IN_FLIP_SHIFT)) & \
BLEDP_DP_FUNCTION_CTRL_ADC_IN_FLIP_MASK)
#define BLEDP_DP_FUNCTION_CTRL_TX_EN_MODE_MASK (0x40000000U)
#define BLEDP_DP_FUNCTION_CTRL_TX_EN_MODE_SHIFT (30U)
#define BLEDP_DP_FUNCTION_CTRL_TX_EN_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_TX_EN_MODE_SHIFT)) & BLEDP_DP_FUNCTION_CTRL_TX_EN_MODE_MASK)
#define BLEDP_DP_FUNCTION_CTRL_RX_EN_MODE_MASK (0x80000000U)
#define BLEDP_DP_FUNCTION_CTRL_RX_EN_MODE_SHIFT (31U)
#define BLEDP_DP_FUNCTION_CTRL_RX_EN_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_FUNCTION_CTRL_RX_EN_MODE_SHIFT)) & BLEDP_DP_FUNCTION_CTRL_RX_EN_MODE_MASK)
/*! @name DP_TEST_CTRL - datapath test iinterface register */
#define BLEDP_DP_TEST_CTRL_TIF_SEL_MASK (0xFFU)
#define BLEDP_DP_TEST_CTRL_TIF_SEL_SHIFT (0U)
#define BLEDP_DP_TEST_CTRL_TIF_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_TIF_SEL_SHIFT)) & BLEDP_DP_TEST_CTRL_TIF_SEL_MASK)
#define BLEDP_DP_TEST_CTRL_TIF_CLK_SEL_MASK (0x300U)
#define BLEDP_DP_TEST_CTRL_TIF_CLK_SEL_SHIFT (8U)
#define BLEDP_DP_TEST_CTRL_TIF_CLK_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_TIF_CLK_SEL_SHIFT)) & BLEDP_DP_TEST_CTRL_TIF_CLK_SEL_MASK)
#define BLEDP_DP_TEST_CTRL_CORDIC_DAC_OUT_MASK (0x800U)
#define BLEDP_DP_TEST_CTRL_CORDIC_DAC_OUT_SHIFT (11U)
#define BLEDP_DP_TEST_CTRL_CORDIC_DAC_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_CORDIC_DAC_OUT_SHIFT)) & BLEDP_DP_TEST_CTRL_CORDIC_DAC_OUT_MASK)
#define BLEDP_DP_TEST_CTRL_TIF_EN_MASK (0x1000U)
#define BLEDP_DP_TEST_CTRL_TIF_EN_SHIFT (12U)
#define BLEDP_DP_TEST_CTRL_TIF_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_TIF_EN_SHIFT)) & BLEDP_DP_TEST_CTRL_TIF_EN_MASK)
#define BLEDP_DP_TEST_CTRL_IMR_INV_MASK (0x2000U)
#define BLEDP_DP_TEST_CTRL_IMR_INV_SHIFT (13U)
#define BLEDP_DP_TEST_CTRL_IMR_INV(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_IMR_INV_SHIFT)) & BLEDP_DP_TEST_CTRL_IMR_INV_MASK)
#define BLEDP_DP_TEST_CTRL_CLK_TX_GATE_DIS_MASK (0x4000U)
#define BLEDP_DP_TEST_CTRL_CLK_TX_GATE_DIS_SHIFT (14U)
#define BLEDP_DP_TEST_CTRL_CLK_TX_GATE_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_CLK_TX_GATE_DIS_SHIFT)) & \
BLEDP_DP_TEST_CTRL_CLK_TX_GATE_DIS_MASK)
#define BLEDP_DP_TEST_CTRL_BUF_FULL_OFFRF_DIS_MASK (0x8000U)
#define BLEDP_DP_TEST_CTRL_BUF_FULL_OFFRF_DIS_SHIFT (15U)
#define BLEDP_DP_TEST_CTRL_BUF_FULL_OFFRF_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_BUF_FULL_OFFRF_DIS_SHIFT)) & \
BLEDP_DP_TEST_CTRL_BUF_FULL_OFFRF_DIS_MASK)
#define BLEDP_DP_TEST_CTRL_CLK_BUST_GATE_DIS_MASK (0x10000U)
#define BLEDP_DP_TEST_CTRL_CLK_BUST_GATE_DIS_SHIFT (16U)
#define BLEDP_DP_TEST_CTRL_CLK_BUST_GATE_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_CLK_BUST_GATE_DIS_SHIFT)) & \
BLEDP_DP_TEST_CTRL_CLK_BUST_GATE_DIS_MASK)
#define BLEDP_DP_TEST_CTRL_CLK_RX_GATE_DIS_MASK (0x20000U)
#define BLEDP_DP_TEST_CTRL_CLK_RX_GATE_DIS_SHIFT (17U)
#define BLEDP_DP_TEST_CTRL_CLK_RX_GATE_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_CLK_RX_GATE_DIS_SHIFT)) & \
BLEDP_DP_TEST_CTRL_CLK_RX_GATE_DIS_MASK)
#define BLEDP_DP_TEST_CTRL_CLK_LPDET_GATE_DIS_MASK (0x40000U)
#define BLEDP_DP_TEST_CTRL_CLK_LPDET_GATE_DIS_SHIFT (18U)
#define BLEDP_DP_TEST_CTRL_CLK_LPDET_GATE_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_CLK_LPDET_GATE_DIS_SHIFT)) & \
BLEDP_DP_TEST_CTRL_CLK_LPDET_GATE_DIS_MASK)
#define BLEDP_DP_TEST_CTRL_CLK_HPDET_GATE_DIS_MASK (0x80000U)
#define BLEDP_DP_TEST_CTRL_CLK_HPDET_GATE_DIS_SHIFT (19U)
#define BLEDP_DP_TEST_CTRL_CLK_HPDET_GATE_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_CLK_HPDET_GATE_DIS_SHIFT)) & \
BLEDP_DP_TEST_CTRL_CLK_HPDET_GATE_DIS_MASK)
#define BLEDP_DP_TEST_CTRL_CLK_RFE_GATE_DIS_MASK (0x100000U)
#define BLEDP_DP_TEST_CTRL_CLK_RFE_GATE_DIS_SHIFT (20U)
#define BLEDP_DP_TEST_CTRL_CLK_RFE_GATE_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_CLK_RFE_GATE_DIS_SHIFT)) & \
BLEDP_DP_TEST_CTRL_CLK_RFE_GATE_DIS_MASK)
#define BLEDP_DP_TEST_CTRL_IQSWAP_XOR_MASK (0x200000U)
#define BLEDP_DP_TEST_CTRL_IQSWAP_XOR_SHIFT (21U)
#define BLEDP_DP_TEST_CTRL_IQSWAP_XOR(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_IQSWAP_XOR_SHIFT)) & BLEDP_DP_TEST_CTRL_IQSWAP_XOR_MASK)
#define BLEDP_DP_TEST_CTRL_DAC_TEST_EN_MASK (0x800000U)
#define BLEDP_DP_TEST_CTRL_DAC_TEST_EN_SHIFT (23U)
#define BLEDP_DP_TEST_CTRL_DAC_TEST_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_DAC_TEST_EN_SHIFT)) & BLEDP_DP_TEST_CTRL_DAC_TEST_EN_MASK)
#define BLEDP_DP_TEST_CTRL_DAC_TEST_MASK (0xFF000000U)
#define BLEDP_DP_TEST_CTRL_DAC_TEST_SHIFT (24U)
#define BLEDP_DP_TEST_CTRL_DAC_TEST(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_TEST_CTRL_DAC_TEST_SHIFT)) & BLEDP_DP_TEST_CTRL_DAC_TEST_MASK)
/*! @name BLE_DP_STATUS1 - datapath status register 1 */
#define BLEDP_BLE_DP_STATUS1_SNR_EST_MASK (0xFFU)
#define BLEDP_BLE_DP_STATUS1_SNR_EST_SHIFT (0U)
#define BLEDP_BLE_DP_STATUS1_SNR_EST(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS1_SNR_EST_SHIFT)) & BLEDP_BLE_DP_STATUS1_SNR_EST_MASK)
#define BLEDP_BLE_DP_STATUS1_CNR_EST_MASK (0x3F00U)
#define BLEDP_BLE_DP_STATUS1_CNR_EST_SHIFT (8U)
#define BLEDP_BLE_DP_STATUS1_CNR_EST(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS1_CNR_EST_SHIFT)) & BLEDP_BLE_DP_STATUS1_CNR_EST_MASK)
#define BLEDP_BLE_DP_STATUS1_AGC_RSSI_MASK (0xFF0000U)
#define BLEDP_BLE_DP_STATUS1_AGC_RSSI_SHIFT (16U)
#define BLEDP_BLE_DP_STATUS1_AGC_RSSI(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS1_AGC_RSSI_SHIFT)) & BLEDP_BLE_DP_STATUS1_AGC_RSSI_MASK)
#define BLEDP_BLE_DP_STATUS1_AGC_RSSI_READY_MASK (0x1000000U)
#define BLEDP_BLE_DP_STATUS1_AGC_RSSI_READY_SHIFT (24U)
#define BLEDP_BLE_DP_STATUS1_AGC_RSSI_READY(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS1_AGC_RSSI_READY_SHIFT)) & \
BLEDP_BLE_DP_STATUS1_AGC_RSSI_READY_MASK)
#define BLEDP_BLE_DP_STATUS1_SNR_VLD_MASK (0x2000000U)
#define BLEDP_BLE_DP_STATUS1_SNR_VLD_SHIFT (25U)
#define BLEDP_BLE_DP_STATUS1_SNR_VLD(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS1_SNR_VLD_SHIFT)) & BLEDP_BLE_DP_STATUS1_SNR_VLD_MASK)
#define BLEDP_BLE_DP_STATUS1_CNR_VLD_MASK (0x4000000U)
#define BLEDP_BLE_DP_STATUS1_CNR_VLD_SHIFT (26U)
#define BLEDP_BLE_DP_STATUS1_CNR_VLD(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS1_CNR_VLD_SHIFT)) & BLEDP_BLE_DP_STATUS1_CNR_VLD_MASK)
#define BLEDP_BLE_DP_STATUS1_TX_BUSY_MASK (0x8000000U)
#define BLEDP_BLE_DP_STATUS1_TX_BUSY_SHIFT (27U)
#define BLEDP_BLE_DP_STATUS1_TX_BUSY(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS1_TX_BUSY_SHIFT)) & BLEDP_BLE_DP_STATUS1_TX_BUSY_MASK)
/*! @name BLE_DP_STATUS2 - datapath status register 2 */
#define BLEDP_BLE_DP_STATUS2_VALID_PCK_NUM_MASK (0xFFFFU)
#define BLEDP_BLE_DP_STATUS2_VALID_PCK_NUM_SHIFT (0U)
#define BLEDP_BLE_DP_STATUS2_VALID_PCK_NUM(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS2_VALID_PCK_NUM_SHIFT)) & \
BLEDP_BLE_DP_STATUS2_VALID_PCK_NUM_MASK)
#define BLEDP_BLE_DP_STATUS2_AA_ERR_NUM_MASK (0x3F0000U)
#define BLEDP_BLE_DP_STATUS2_AA_ERR_NUM_SHIFT (16U)
#define BLEDP_BLE_DP_STATUS2_AA_ERR_NUM(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS2_AA_ERR_NUM_SHIFT)) & BLEDP_BLE_DP_STATUS2_AA_ERR_NUM_MASK)
#define BLEDP_BLE_DP_STATUS2_CRC_ERROR_MASK (0x20000000U)
#define BLEDP_BLE_DP_STATUS2_CRC_ERROR_SHIFT (29U)
#define BLEDP_BLE_DP_STATUS2_CRC_ERROR(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS2_CRC_ERROR_SHIFT)) & BLEDP_BLE_DP_STATUS2_CRC_ERROR_MASK)
#define BLEDP_BLE_DP_STATUS2_BURST_DET_MASK (0x40000000U)
#define BLEDP_BLE_DP_STATUS2_BURST_DET_SHIFT (30U)
#define BLEDP_BLE_DP_STATUS2_BURST_DET(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS2_BURST_DET_SHIFT)) & BLEDP_BLE_DP_STATUS2_BURST_DET_MASK)
#define BLEDP_BLE_DP_STATUS2_DP_STATUS_VLD_0_MASK (0x80000000U)
#define BLEDP_BLE_DP_STATUS2_DP_STATUS_VLD_0_SHIFT (31U)
#define BLEDP_BLE_DP_STATUS2_DP_STATUS_VLD_0(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS2_DP_STATUS_VLD_0_SHIFT)) & \
BLEDP_BLE_DP_STATUS2_DP_STATUS_VLD_0_MASK)
/*! @name BLE_DP_STATUS3 - datapath status register 3 */
#define BLEDP_BLE_DP_STATUS3_FD_CFO_TRACK_MASK (0x7FFU)
#define BLEDP_BLE_DP_STATUS3_FD_CFO_TRACK_SHIFT (0U)
#define BLEDP_BLE_DP_STATUS3_FD_CFO_TRACK(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS3_FD_CFO_TRACK_SHIFT)) & BLEDP_BLE_DP_STATUS3_FD_CFO_TRACK_MASK)
#define BLEDP_BLE_DP_STATUS3_CFO_EST_FD_MASK (0x7FF0000U)
#define BLEDP_BLE_DP_STATUS3_CFO_EST_FD_SHIFT (16U)
#define BLEDP_BLE_DP_STATUS3_CFO_EST_FD(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS3_CFO_EST_FD_SHIFT)) & BLEDP_BLE_DP_STATUS3_CFO_EST_FD_MASK)
/*! @name BLE_DP_STATUS4 - datapath status register 4 */
#define BLEDP_BLE_DP_STATUS4_RESAMPLER_PH_MASK (0x3FFU)
#define BLEDP_BLE_DP_STATUS4_RESAMPLER_PH_SHIFT (0U)
#define BLEDP_BLE_DP_STATUS4_RESAMPLER_PH(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS4_RESAMPLER_PH_SHIFT)) & BLEDP_BLE_DP_STATUS4_RESAMPLER_PH_MASK)
#define BLEDP_BLE_DP_STATUS4_HP_CFO_MASK (0xFFF0000U)
#define BLEDP_BLE_DP_STATUS4_HP_CFO_SHIFT (16U)
#define BLEDP_BLE_DP_STATUS4_HP_CFO(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS4_HP_CFO_SHIFT)) & BLEDP_BLE_DP_STATUS4_HP_CFO_MASK)
#define BLEDP_BLE_DP_STATUS4_HP_CFO_VLD_MASK (0x80000000U)
#define BLEDP_BLE_DP_STATUS4_HP_CFO_VLD_SHIFT (31U)
#define BLEDP_BLE_DP_STATUS4_HP_CFO_VLD(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_BLE_DP_STATUS4_HP_CFO_VLD_SHIFT)) & BLEDP_BLE_DP_STATUS4_HP_CFO_VLD_MASK)
/*! @name RX_FRONT_END_CTRL1 - rx front end control register 1 */
#define BLEDP_RX_FRONT_END_CTRL1_CFO_COMP_MASK (0x7FFFU)
#define BLEDP_RX_FRONT_END_CTRL1_CFO_COMP_SHIFT (0U)
#define BLEDP_RX_FRONT_END_CTRL1_CFO_COMP(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL1_CFO_COMP_SHIFT)) & BLEDP_RX_FRONT_END_CTRL1_CFO_COMP_MASK)
#define BLEDP_RX_FRONT_END_CTRL1_DCNOTCH_GIN_MASK (0x30000U)
#define BLEDP_RX_FRONT_END_CTRL1_DCNOTCH_GIN_SHIFT (16U)
#define BLEDP_RX_FRONT_END_CTRL1_DCNOTCH_GIN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL1_DCNOTCH_GIN_SHIFT)) & \
BLEDP_RX_FRONT_END_CTRL1_DCNOTCH_GIN_MASK)
/*! @name RX_FRONT_END_CTRL2 - rx front end control register 2 */
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_GAIN_MASK (0x7FFU)
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_GAIN_SHIFT (0U)
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_GAIN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL2_FAGC_GAIN_SHIFT)) & \
BLEDP_RX_FRONT_END_CTRL2_FAGC_GAIN_MASK)
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_INI_VAL_MASK (0x800U)
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_INI_VAL_SHIFT (11U)
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_INI_VAL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL2_FAGC_INI_VAL_SHIFT)) & \
BLEDP_RX_FRONT_END_CTRL2_FAGC_INI_VAL_MASK)
#define BLEDP_RX_FRONT_END_CTRL2_CNR_IDX_DELTA_MASK (0xF000U)
#define BLEDP_RX_FRONT_END_CTRL2_CNR_IDX_DELTA_SHIFT (12U)
#define BLEDP_RX_FRONT_END_CTRL2_CNR_IDX_DELTA(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL2_CNR_IDX_DELTA_SHIFT)) & \
BLEDP_RX_FRONT_END_CTRL2_CNR_IDX_DELTA_MASK)
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_REF_MASK (0xFF0000U)
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_REF_SHIFT (16U)
#define BLEDP_RX_FRONT_END_CTRL2_FAGC_REF(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL2_FAGC_REF_SHIFT)) & BLEDP_RX_FRONT_END_CTRL2_FAGC_REF_MASK)
#define BLEDP_RX_FRONT_END_CTRL2_CORDIC_MIN_VIN_TH_MASK (0xF000000U)
#define BLEDP_RX_FRONT_END_CTRL2_CORDIC_MIN_VIN_TH_SHIFT (24U)
#define BLEDP_RX_FRONT_END_CTRL2_CORDIC_MIN_VIN_TH(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL2_CORDIC_MIN_VIN_TH_SHIFT)) & \
BLEDP_RX_FRONT_END_CTRL2_CORDIC_MIN_VIN_TH_MASK)
#define BLEDP_RX_FRONT_END_CTRL2_FREQ_TRADE_EN_MASK (0x10000000U)
#define BLEDP_RX_FRONT_END_CTRL2_FREQ_TRADE_EN_SHIFT (28U)
#define BLEDP_RX_FRONT_END_CTRL2_FREQ_TRADE_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL2_FREQ_TRADE_EN_SHIFT)) & \
BLEDP_RX_FRONT_END_CTRL2_FREQ_TRADE_EN_MASK)
#define BLEDP_RX_FRONT_END_CTRL2_CHN_SHIFT_MASK (0xE0000000U)
#define BLEDP_RX_FRONT_END_CTRL2_CHN_SHIFT_SHIFT (29U)
#define BLEDP_RX_FRONT_END_CTRL2_CHN_SHIFT(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_RX_FRONT_END_CTRL2_CHN_SHIFT_SHIFT)) & \
BLEDP_RX_FRONT_END_CTRL2_CHN_SHIFT_MASK)
/*! @name FREQ_DOMAIN_CTRL1 - frequency domain control register 1 */
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_IN0_MASK (0xFFU)
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_IN0_SHIFT (0U)
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_IN0(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_IN0_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_IN0_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_WEN_MASK (0x100U)
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_WEN_SHIFT (8U)
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_WEN_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL1_SYNC_WORD_WEN_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_P_SEL_MASK (0x8000U)
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_P_SEL_SHIFT (15U)
#define BLEDP_FREQ_DOMAIN_CTRL1_SYNC_P_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL1_SYNC_P_SEL_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL1_SYNC_P_SEL_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL1_RD_EXBIT_EN_MASK (0x10000U)
#define BLEDP_FREQ_DOMAIN_CTRL1_RD_EXBIT_EN_SHIFT (16U)
#define BLEDP_FREQ_DOMAIN_CTRL1_RD_EXBIT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL1_RD_EXBIT_EN_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL1_RD_EXBIT_EN_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL1_RFAGC_TRACK_DLY_MASK (0xE0000U)
#define BLEDP_FREQ_DOMAIN_CTRL1_RFAGC_TRACK_DLY_SHIFT (17U)
#define BLEDP_FREQ_DOMAIN_CTRL1_RFAGC_TRACK_DLY(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL1_RFAGC_TRACK_DLY_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL1_RFAGC_TRACK_DLY_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL1_PROP_DF_16US_MASK (0xFF000000U)
#define BLEDP_FREQ_DOMAIN_CTRL1_PROP_DF_16US_SHIFT (24U)
#define BLEDP_FREQ_DOMAIN_CTRL1_PROP_DF_16US(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL1_PROP_DF_16US_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL1_PROP_DF_16US_MASK)
/*! @name FREQ_DOMAIN_CTRL2 - frequency domain control register 2 */
#define BLEDP_FREQ_DOMAIN_CTRL2_SYNC_WORD_IN1_MASK (0xFFFFFFFFU)
#define BLEDP_FREQ_DOMAIN_CTRL2_SYNC_WORD_IN1_SHIFT (0U)
#define BLEDP_FREQ_DOMAIN_CTRL2_SYNC_WORD_IN1(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL2_SYNC_WORD_IN1_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL2_SYNC_WORD_IN1_MASK)
/*! @name FREQ_DOMAIN_CTRL3 - frequency domain control register 3 */
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH3_MASK (0x3FU)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH3_SHIFT (0U)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH3(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH3_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH3_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH2_MASK (0x3F00U)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH2_SHIFT (8U)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH2(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH2_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH2_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH1_MASK (0x3F0000U)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH1_SHIFT (16U)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH1(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH1_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH1_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH0_MASK (0x3F000000U)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH0_SHIFT (24U)
#define BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH0(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH0_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH0_MASK)
/*! @name FREQ_DOMAIN_CTRL4 - frequency domain control register 4 */
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH3_MASK (0x3FU)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH3_SHIFT (0U)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH3(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH3_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH3_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH2_MASK (0x3F00U)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH2_SHIFT (8U)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH2(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH2_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH2_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH1_MASK (0x3F0000U)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH1_SHIFT (16U)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH1(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH1_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH1_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH0_MASK (0x3F000000U)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH0_SHIFT (24U)
#define BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH0(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH0_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL4_XCORR_POW_TH0_MASK)
/*! @name FREQ_DOMAIN_CTRL5 - frequency domain control register 5 */
#define BLEDP_FREQ_DOMAIN_CTRL5_GAIN_TED_MASK (0x3U)
#define BLEDP_FREQ_DOMAIN_CTRL5_GAIN_TED_SHIFT (0U)
#define BLEDP_FREQ_DOMAIN_CTRL5_GAIN_TED(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_GAIN_TED_SHIFT)) & BLEDP_FREQ_DOMAIN_CTRL5_GAIN_TED_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_VALUE_MASK (0x70U)
#define BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_VALUE_SHIFT (4U)
#define BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_VALUE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_VALUE_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_VALUE_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_EN_MASK (0x80U)
#define BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_EN_SHIFT (7U)
#define BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_EN_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_EN_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL5_CNT_SETTLE_IDX_MASK (0x700U)
#define BLEDP_FREQ_DOMAIN_CTRL5_CNT_SETTLE_IDX_SHIFT (8U)
#define BLEDP_FREQ_DOMAIN_CTRL5_CNT_SETTLE_IDX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_CNT_SETTLE_IDX_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL5_CNT_SETTLE_IDX_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL5_TRIG_XCORR_CNT_MASK (0xF000U)
#define BLEDP_FREQ_DOMAIN_CTRL5_TRIG_XCORR_CNT_SHIFT (12U)
#define BLEDP_FREQ_DOMAIN_CTRL5_TRIG_XCORR_CNT(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_TRIG_XCORR_CNT_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL5_TRIG_XCORR_CNT_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH3_MASK (0xF0000U)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH3_SHIFT (16U)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH3(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH3_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH3_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH2_MASK (0xF00000U)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH2_SHIFT (20U)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH2(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH2_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH2_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH1_MASK (0xF000000U)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH1_SHIFT (24U)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH1(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH1_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH1_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH0_MASK (0xF0000000U)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH0_SHIFT (28U)
#define BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH0(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH0_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH0_MASK)
/*! @name FREQ_DOMAIN_CTRL6 - frequency domain control register 5 */
#define BLEDP_FREQ_DOMAIN_CTRL6_HP_TRAIN_SIZ_MASK (0x1FU)
#define BLEDP_FREQ_DOMAIN_CTRL6_HP_TRAIN_SIZ_SHIFT (0U)
#define BLEDP_FREQ_DOMAIN_CTRL6_HP_TRAIN_SIZ(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL6_HP_TRAIN_SIZ_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL6_HP_TRAIN_SIZ_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL6_HP_HIDX_GAIN_MASK (0xFF00U)
#define BLEDP_FREQ_DOMAIN_CTRL6_HP_HIDX_GAIN_SHIFT (8U)
#define BLEDP_FREQ_DOMAIN_CTRL6_HP_HIDX_GAIN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL6_HP_HIDX_GAIN_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL6_HP_HIDX_GAIN_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL6_H_REF_GAIN_MASK (0x3F0000U)
#define BLEDP_FREQ_DOMAIN_CTRL6_H_REF_GAIN_SHIFT (16U)
#define BLEDP_FREQ_DOMAIN_CTRL6_H_REF_GAIN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL6_H_REF_GAIN_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL6_H_REF_GAIN_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL6_DET_FR_IDX_MASK (0x3000000U)
#define BLEDP_FREQ_DOMAIN_CTRL6_DET_FR_IDX_SHIFT (24U)
#define BLEDP_FREQ_DOMAIN_CTRL6_DET_FR_IDX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL6_DET_FR_IDX_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL6_DET_FR_IDX_MASK)
#define BLEDP_FREQ_DOMAIN_CTRL6_CFO_FR_IDX_MASK (0x30000000U)
#define BLEDP_FREQ_DOMAIN_CTRL6_CFO_FR_IDX_SHIFT (28U)
#define BLEDP_FREQ_DOMAIN_CTRL6_CFO_FR_IDX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_CTRL6_CFO_FR_IDX_SHIFT)) & \
BLEDP_FREQ_DOMAIN_CTRL6_CFO_FR_IDX_MASK)
/*! @name HP_MODE_CTRL1 - when high hp mode training size same as cfo tracking. */
#define BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRACK_MASK (0x3FU)
#define BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRACK_SHIFT (0U)
#define BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRACK(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRACK_SHIFT)) & \
BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRACK_MASK)
#define BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRAIN_MASK (0x3F00U)
#define BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRAIN_SHIFT (8U)
#define BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRAIN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRAIN_SHIFT)) & \
BLEDP_HP_MODE_CTRL1_HP_BMC_P_TRAIN_MASK)
#define BLEDP_HP_MODE_CTRL1_HP_BMC_CZ1_MASK (0x3F0000U)
#define BLEDP_HP_MODE_CTRL1_HP_BMC_CZ1_SHIFT (16U)
#define BLEDP_HP_MODE_CTRL1_HP_BMC_CZ1(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL1_HP_BMC_CZ1_SHIFT)) & BLEDP_HP_MODE_CTRL1_HP_BMC_CZ1_MASK)
#define BLEDP_HP_MODE_CTRL1_BUF_IDX_DELTA_MASK (0xF000000U)
#define BLEDP_HP_MODE_CTRL1_BUF_IDX_DELTA_SHIFT (24U)
#define BLEDP_HP_MODE_CTRL1_BUF_IDX_DELTA(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL1_BUF_IDX_DELTA_SHIFT)) & BLEDP_HP_MODE_CTRL1_BUF_IDX_DELTA_MASK)
#define BLEDP_HP_MODE_CTRL1_WMF2_DSAMP_IDX_MASK (0x70000000U)
#define BLEDP_HP_MODE_CTRL1_WMF2_DSAMP_IDX_SHIFT (28U)
#define BLEDP_HP_MODE_CTRL1_WMF2_DSAMP_IDX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL1_WMF2_DSAMP_IDX_SHIFT)) & \
BLEDP_HP_MODE_CTRL1_WMF2_DSAMP_IDX_MASK)
#define BLEDP_HP_MODE_CTRL1_HP_TRAIN_SIZ_FIX_MASK (0x80000000U)
#define BLEDP_HP_MODE_CTRL1_HP_TRAIN_SIZ_FIX_SHIFT (31U)
#define BLEDP_HP_MODE_CTRL1_HP_TRAIN_SIZ_FIX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL1_HP_TRAIN_SIZ_FIX_SHIFT)) & \
BLEDP_HP_MODE_CTRL1_HP_TRAIN_SIZ_FIX_MASK)
/*! @name HP_MODE_CTRL2 - q paramter in training period of phase offset iir of bmc */
#define BLEDP_HP_MODE_CTRL2_SNR_EST_REF_MASK (0xFFU)
#define BLEDP_HP_MODE_CTRL2_SNR_EST_REF_SHIFT (0U)
#define BLEDP_HP_MODE_CTRL2_SNR_EST_REF(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL2_SNR_EST_REF_SHIFT)) & BLEDP_HP_MODE_CTRL2_SNR_EST_REF_MASK)
#define BLEDP_HP_MODE_CTRL2_SNR_EST_LEN_MASK (0x300U)
#define BLEDP_HP_MODE_CTRL2_SNR_EST_LEN_SHIFT (8U)
#define BLEDP_HP_MODE_CTRL2_SNR_EST_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL2_SNR_EST_LEN_SHIFT)) & BLEDP_HP_MODE_CTRL2_SNR_EST_LEN_MASK)
#define BLEDP_HP_MODE_CTRL2_SNR_EST_EN_MASK (0x1000U)
#define BLEDP_HP_MODE_CTRL2_SNR_EST_EN_SHIFT (12U)
#define BLEDP_HP_MODE_CTRL2_SNR_EST_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL2_SNR_EST_EN_SHIFT)) & BLEDP_HP_MODE_CTRL2_SNR_EST_EN_MASK)
#define BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRACK_MASK (0xFF0000U)
#define BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRACK_SHIFT (16U)
#define BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRACK(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRACK_SHIFT)) & \
BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRACK_MASK)
#define BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRAIN_MASK (0xFF000000U)
#define BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRAIN_SHIFT (24U)
#define BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRAIN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRAIN_SHIFT)) & \
BLEDP_HP_MODE_CTRL2_HP_BMC_Q_TRAIN_MASK)
/*! @name FREQ_DOMAIN_STATUS1 - frequency domain status register 1 */
#define BLEDP_FREQ_DOMAIN_STATUS1_MAX_XCORR_MASK (0x3FFU)
#define BLEDP_FREQ_DOMAIN_STATUS1_MAX_XCORR_SHIFT (0U)
#define BLEDP_FREQ_DOMAIN_STATUS1_MAX_XCORR(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_STATUS1_MAX_XCORR_SHIFT)) & \
BLEDP_FREQ_DOMAIN_STATUS1_MAX_XCORR_MASK)
#define BLEDP_FREQ_DOMAIN_STATUS1_PKT_OFFSET_COM_MASK (0x1FF0000U)
#define BLEDP_FREQ_DOMAIN_STATUS1_PKT_OFFSET_COM_SHIFT (16U)
#define BLEDP_FREQ_DOMAIN_STATUS1_PKT_OFFSET_COM(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_STATUS1_PKT_OFFSET_COM_SHIFT)) & \
BLEDP_FREQ_DOMAIN_STATUS1_PKT_OFFSET_COM_MASK)
#define BLEDP_FREQ_DOMAIN_STATUS1_NIDX_MASK (0xF0000000U)
#define BLEDP_FREQ_DOMAIN_STATUS1_NIDX_SHIFT (28U)
#define BLEDP_FREQ_DOMAIN_STATUS1_NIDX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_STATUS1_NIDX_SHIFT)) & BLEDP_FREQ_DOMAIN_STATUS1_NIDX_MASK)
/*! @name FREQ_DOMAIN_STATUS2 - frequency domain status register 2 */
#define BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_SPWR_MASK (0x3FFU)
#define BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_SPWR_SHIFT (0U)
#define BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_SPWR(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_SPWR_SHIFT)) & \
BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_SPWR_MASK)
#define BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_XCORR_MASK (0x3FF0000U)
#define BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_XCORR_SHIFT (16U)
#define BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_XCORR(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_XCORR_SHIFT)) & \
BLEDP_FREQ_DOMAIN_STATUS2_MAX_PAR_XCORR_MASK)
/*! @name DP_AA_ERROR_CTRL - AA error control register */
#define BLEDP_DP_AA_ERROR_CTRL_IQSWAP_SEL_MASK (0x1U)
#define BLEDP_DP_AA_ERROR_CTRL_IQSWAP_SEL_SHIFT (0U)
#define BLEDP_DP_AA_ERROR_CTRL_IQSWAP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_CTRL_IQSWAP_SEL_SHIFT)) & BLEDP_DP_AA_ERROR_CTRL_IQSWAP_SEL_MASK)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_EN_MASK (0x2U)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_EN_SHIFT (1U)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_EN_SHIFT)) & \
BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_EN_MASK)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_EN_MASK (0x4U)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_EN_SHIFT (2U)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_EN_SHIFT)) & \
BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_EN_MASK)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_SEL_MASK (0x8U)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_SEL_SHIFT (3U)
#define BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_SEL_SHIFT)) & \
BLEDP_DP_AA_ERROR_CTRL_AA_ERROR_CNR_SEL_MASK)
/*! @name DP_INT - data path interrupt register */
#define BLEDP_DP_INT_DP_INTERRUPT0_MASK (0x1U)
#define BLEDP_DP_INT_DP_INTERRUPT0_SHIFT (0U)
#define BLEDP_DP_INT_DP_INTERRUPT0(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT0_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT0_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT1_MASK (0x2U)
#define BLEDP_DP_INT_DP_INTERRUPT1_SHIFT (1U)
#define BLEDP_DP_INT_DP_INTERRUPT1(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT1_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT1_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT2_MASK (0x4U)
#define BLEDP_DP_INT_DP_INTERRUPT2_SHIFT (2U)
#define BLEDP_DP_INT_DP_INTERRUPT2(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT2_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT2_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT_MASK (0x8U)
#define BLEDP_DP_INT_DP_INTERRUPT_SHIFT (3U)
#define BLEDP_DP_INT_DP_INTERRUPT(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT0_SEL_MASK (0xF0000U)
#define BLEDP_DP_INT_DP_INTERRUPT0_SEL_SHIFT (16U)
#define BLEDP_DP_INT_DP_INTERRUPT0_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT0_SEL_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT0_SEL_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT1_SEL_MASK (0xF00000U)
#define BLEDP_DP_INT_DP_INTERRUPT1_SEL_SHIFT (20U)
#define BLEDP_DP_INT_DP_INTERRUPT1_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT1_SEL_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT1_SEL_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT2_SEL_MASK (0xF000000U)
#define BLEDP_DP_INT_DP_INTERRUPT2_SEL_SHIFT (24U)
#define BLEDP_DP_INT_DP_INTERRUPT2_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT2_SEL_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT2_SEL_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT0_MSK_MASK (0x10000000U)
#define BLEDP_DP_INT_DP_INTERRUPT0_MSK_SHIFT (28U)
#define BLEDP_DP_INT_DP_INTERRUPT0_MSK(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT0_MSK_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT0_MSK_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT1_MSK_MASK (0x20000000U)
#define BLEDP_DP_INT_DP_INTERRUPT1_MSK_SHIFT (29U)
#define BLEDP_DP_INT_DP_INTERRUPT1_MSK(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT1_MSK_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT1_MSK_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT2_MSK_MASK (0x40000000U)
#define BLEDP_DP_INT_DP_INTERRUPT2_MSK_SHIFT (30U)
#define BLEDP_DP_INT_DP_INTERRUPT2_MSK(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT2_MSK_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT2_MSK_MASK)
#define BLEDP_DP_INT_DP_INTERRUPT_MSK_MASK (0x80000000U)
#define BLEDP_DP_INT_DP_INTERRUPT_MSK_SHIFT (31U)
#define BLEDP_DP_INT_DP_INTERRUPT_MSK(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_INT_DP_INTERRUPT_MSK_SHIFT)) & BLEDP_DP_INT_DP_INTERRUPT_MSK_MASK)
/*! @name DP_AA_ERROR_TH - AA error threshold register */
#define BLEDP_DP_AA_ERROR_TH_HP_TRAIN_POSITION_MASK (0x1U)
#define BLEDP_DP_AA_ERROR_TH_HP_TRAIN_POSITION_SHIFT (0U)
#define BLEDP_DP_AA_ERROR_TH_HP_TRAIN_POSITION(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_TH_HP_TRAIN_POSITION_SHIFT)) & \
BLEDP_DP_AA_ERROR_TH_HP_TRAIN_POSITION_MASK)
#define BLEDP_DP_AA_ERROR_TH_CORDIC_IN_SCALE_MASK (0x2U)
#define BLEDP_DP_AA_ERROR_TH_CORDIC_IN_SCALE_SHIFT (1U)
#define BLEDP_DP_AA_ERROR_TH_CORDIC_IN_SCALE(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_TH_CORDIC_IN_SCALE_SHIFT)) & \
BLEDP_DP_AA_ERROR_TH_CORDIC_IN_SCALE_MASK)
#define BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_SEL_MASK (0x4U)
#define BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_SEL_SHIFT (2U)
#define BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_SEL_SHIFT)) & \
BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_SEL_MASK)
#define BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_EN_MASK (0x8U)
#define BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_EN_SHIFT (3U)
#define BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_EN_SHIFT)) & \
BLEDP_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_EN_MASK)
#define BLEDP_DP_AA_ERROR_TH_SNR_GOOD_TH_MASK (0x70U)
#define BLEDP_DP_AA_ERROR_TH_SNR_GOOD_TH_SHIFT (4U)
#define BLEDP_DP_AA_ERROR_TH_SNR_GOOD_TH(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_TH_SNR_GOOD_TH_SHIFT)) & BLEDP_DP_AA_ERROR_TH_SNR_GOOD_TH_MASK)
#define BLEDP_DP_AA_ERROR_TH_CNR_GOOD_TH_MASK (0x3F00U)
#define BLEDP_DP_AA_ERROR_TH_CNR_GOOD_TH_SHIFT (8U)
#define BLEDP_DP_AA_ERROR_TH_CNR_GOOD_TH(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_TH_CNR_GOOD_TH_SHIFT)) & BLEDP_DP_AA_ERROR_TH_CNR_GOOD_TH_MASK)
#define BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_TH_MASK (0xFF0000U)
#define BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_TH_SHIFT (16U)
#define BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_TH(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_TH_SHIFT)) & BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_TH_MASK)
#define BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_DBM_MASK (0xFF000000U)
#define BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_DBM_SHIFT (24U)
#define BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_DBM(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_DBM_SHIFT)) & \
BLEDP_DP_AA_ERROR_TH_RSSI_GOOD_DBM_MASK)
/*! @name DF_ANTENNA_CTRL - antenna register */
#define BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_8F_MASK (0x3U)
#define BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_8F_SHIFT (0U)
#define BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_8F(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_8F_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_8F_MASK)
#define BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_07_MASK (0xCU)
#define BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_07_SHIFT (2U)
#define BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_07(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_07_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_SWITCH_MAP_SEL_07_MASK)
#define BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_MASK (0xF0U)
#define BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_SHIFT (4U)
#define BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_MASK)
#define BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_WEN_MASK (0x100U)
#define BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_WEN_SHIFT (8U)
#define BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_WEN_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_EXT_ANTENNA_NUM_WEN_MASK)
#define BLEDP_DF_ANTENNA_CTRL_BUFFER_BP_MASK (0x10000U)
#define BLEDP_DF_ANTENNA_CTRL_BUFFER_BP_SHIFT (16U)
#define BLEDP_DF_ANTENNA_CTRL_BUFFER_BP(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_BUFFER_BP_SHIFT)) & BLEDP_DF_ANTENNA_CTRL_BUFFER_BP_MASK)
#define BLEDP_DF_ANTENNA_CTRL_TEST_TD_POWER_MASK (0x20000U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_TD_POWER_SHIFT (17U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_TD_POWER(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_TEST_TD_POWER_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_TEST_TD_POWER_MASK)
#define BLEDP_DF_ANTENNA_CTRL_TEST_FD_POWER_MASK (0x40000U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_FD_POWER_SHIFT (18U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_FD_POWER(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_TEST_FD_POWER_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_TEST_FD_POWER_MASK)
#define BLEDP_DF_ANTENNA_CTRL_TEST_SYNC_POWER_MASK (0x80000U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_SYNC_POWER_SHIFT (19U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_SYNC_POWER(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_TEST_SYNC_POWER_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_TEST_SYNC_POWER_MASK)
#define BLEDP_DF_ANTENNA_CTRL_TEST_RFE_CORDIC_POWER_MASK (0x100000U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_RFE_CORDIC_POWER_SHIFT (20U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_RFE_CORDIC_POWER(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_TEST_RFE_CORDIC_POWER_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_TEST_RFE_CORDIC_POWER_MASK)
#define BLEDP_DF_ANTENNA_CTRL_TEST_RFE_POWER_MASK (0x200000U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_RFE_POWER_SHIFT (21U)
#define BLEDP_DF_ANTENNA_CTRL_TEST_RFE_POWER(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_TEST_RFE_POWER_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_TEST_RFE_POWER_MASK)
#define BLEDP_DF_ANTENNA_CTRL_ADC01_SAMPLE_TIME_MASK (0x400000U)
#define BLEDP_DF_ANTENNA_CTRL_ADC01_SAMPLE_TIME_SHIFT (22U)
#define BLEDP_DF_ANTENNA_CTRL_ADC01_SAMPLE_TIME(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_ADC01_SAMPLE_TIME_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_ADC01_SAMPLE_TIME_MASK)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_MUX_MASK (0x800000U)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_MUX_SHIFT (23U)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_MUX(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_PHY_RATE_MUX_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_PHY_RATE_MUX_MASK)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_REG_MASK (0x1000000U)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_REG_SHIFT (24U)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_REG(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_PHY_RATE_REG_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_PHY_RATE_REG_MASK)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_WEN_MASK (0x2000000U)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_WEN_SHIFT (25U)
#define BLEDP_DF_ANTENNA_CTRL_PHY_RATE_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_PHY_RATE_WEN_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_PHY_RATE_WEN_MASK)
#define BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WAIT_TIME_MASK (0x4000000U)
#define BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WAIT_TIME_SHIFT (26U)
#define BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WAIT_TIME(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WAIT_TIME_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WAIT_TIME_MASK)
#define BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WIN_LEN_MASK (0x8000000U)
#define BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WIN_LEN_SHIFT (27U)
#define BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WIN_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WIN_LEN_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_PDU_RSSI_WIN_LEN_MASK)
#define BLEDP_DF_ANTENNA_CTRL_CAL_PDU_RSSI_EN_MASK (0x10000000U)
#define BLEDP_DF_ANTENNA_CTRL_CAL_PDU_RSSI_EN_SHIFT (28U)
#define BLEDP_DF_ANTENNA_CTRL_CAL_PDU_RSSI_EN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_CAL_PDU_RSSI_EN_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_CAL_PDU_RSSI_EN_MASK)
#define BLEDP_DF_ANTENNA_CTRL_PROP_CRC_AA_DIS_MASK (0x20000000U)
#define BLEDP_DF_ANTENNA_CTRL_PROP_CRC_AA_DIS_SHIFT (29U)
#define BLEDP_DF_ANTENNA_CTRL_PROP_CRC_AA_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_PROP_CRC_AA_DIS_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_PROP_CRC_AA_DIS_MASK)
#define BLEDP_DF_ANTENNA_CTRL_PROP_AA_LSB_FIRST_MASK (0x40000000U)
#define BLEDP_DF_ANTENNA_CTRL_PROP_AA_LSB_FIRST_SHIFT (30U)
#define BLEDP_DF_ANTENNA_CTRL_PROP_AA_LSB_FIRST(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_PROP_AA_LSB_FIRST_SHIFT)) & \
BLEDP_DF_ANTENNA_CTRL_PROP_AA_LSB_FIRST_MASK)
#define BLEDP_DF_ANTENNA_CTRL_PRE_NUM_WEN_MASK (0x80000000U)
#define BLEDP_DF_ANTENNA_CTRL_PRE_NUM_WEN_SHIFT (31U)
#define BLEDP_DF_ANTENNA_CTRL_PRE_NUM_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_DF_ANTENNA_CTRL_PRE_NUM_WEN_SHIFT)) & BLEDP_DF_ANTENNA_CTRL_PRE_NUM_WEN_MASK)
/*! @name ANTENNA_MAP01 - antenna switch map register 0 */
#define BLEDP_ANTENNA_MAP01_SWITCH_MAP_1_MASK (0x3FFFU)
#define BLEDP_ANTENNA_MAP01_SWITCH_MAP_1_SHIFT (0U)
#define BLEDP_ANTENNA_MAP01_SWITCH_MAP_1(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANTENNA_MAP01_SWITCH_MAP_1_SHIFT)) & BLEDP_ANTENNA_MAP01_SWITCH_MAP_1_MASK)
#define BLEDP_ANTENNA_MAP01_SWITCH_MAP_0_MASK (0x3FFF0000U)
#define BLEDP_ANTENNA_MAP01_SWITCH_MAP_0_SHIFT (16U)
#define BLEDP_ANTENNA_MAP01_SWITCH_MAP_0(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANTENNA_MAP01_SWITCH_MAP_0_SHIFT)) & BLEDP_ANTENNA_MAP01_SWITCH_MAP_0_MASK)
/*! @name ANTENNA_MAP23 - antenna switch map register 1 */
#define BLEDP_ANTENNA_MAP23_SWITCH_MAP_3_MASK (0x3FFFU)
#define BLEDP_ANTENNA_MAP23_SWITCH_MAP_3_SHIFT (0U)
#define BLEDP_ANTENNA_MAP23_SWITCH_MAP_3(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANTENNA_MAP23_SWITCH_MAP_3_SHIFT)) & BLEDP_ANTENNA_MAP23_SWITCH_MAP_3_MASK)
#define BLEDP_ANTENNA_MAP23_SWITCH_MAP_2_MASK (0x3FFF0000U)
#define BLEDP_ANTENNA_MAP23_SWITCH_MAP_2_SHIFT (16U)
#define BLEDP_ANTENNA_MAP23_SWITCH_MAP_2(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANTENNA_MAP23_SWITCH_MAP_2_SHIFT)) & BLEDP_ANTENNA_MAP23_SWITCH_MAP_2_MASK)
/*! @name ANTENNA_MAP45 - antenna switch map register 2 */
#define BLEDP_ANTENNA_MAP45_SWITCH_MAP_5_MASK (0x3FFFU)
#define BLEDP_ANTENNA_MAP45_SWITCH_MAP_5_SHIFT (0U)
#define BLEDP_ANTENNA_MAP45_SWITCH_MAP_5(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANTENNA_MAP45_SWITCH_MAP_5_SHIFT)) & BLEDP_ANTENNA_MAP45_SWITCH_MAP_5_MASK)
#define BLEDP_ANTENNA_MAP45_SWITCH_MAP_4_MASK (0x3FFF0000U)
#define BLEDP_ANTENNA_MAP45_SWITCH_MAP_4_SHIFT (16U)
#define BLEDP_ANTENNA_MAP45_SWITCH_MAP_4(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANTENNA_MAP45_SWITCH_MAP_4_SHIFT)) & BLEDP_ANTENNA_MAP45_SWITCH_MAP_4_MASK)
/*! @name ANTENNA_MAP67 - antenna switch map register 3 */
#define BLEDP_ANTENNA_MAP67_SWITCH_MAP_7_MASK (0x3FFFU)
#define BLEDP_ANTENNA_MAP67_SWITCH_MAP_7_SHIFT (0U)
#define BLEDP_ANTENNA_MAP67_SWITCH_MAP_7(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANTENNA_MAP67_SWITCH_MAP_7_SHIFT)) & BLEDP_ANTENNA_MAP67_SWITCH_MAP_7_MASK)
#define BLEDP_ANTENNA_MAP67_SWITCH_MAP_6_MASK (0x3FFF0000U)
#define BLEDP_ANTENNA_MAP67_SWITCH_MAP_6_SHIFT (16U)
#define BLEDP_ANTENNA_MAP67_SWITCH_MAP_6(x) \
(((uint32_t)(((uint32_t)(x)) << BLEDP_ANTENNA_MAP67_SWITCH_MAP_6_SHIFT)) & BLEDP_ANTENNA_MAP67_SWITCH_MAP_6_MASK)
/*!
* @}
*/ /* end of group BLEDP_Register_Masks */
/* BLEDP - Peripheral instance base addresses */
/** Peripheral BLEDP base address */
#define BLEDP_BASE (0x4000E000u)
/** Peripheral BLEDP base pointer */
#define BLEDP ((BLEDP_Type *)BLEDP_BASE)
/** Array initializer of BLEDP peripheral base addresses */
#define BLEDP_BASE_ADDRS \
{ \
BLEDP_BASE \
}
/** Array initializer of BLEDP peripheral base pointers */
#define BLEDP_BASE_PTRS \
{ \
BLEDP \
}
/** Interrupt vectors for the BLEDP peripheral type */
#define BLEDP_IRQS \
{ \
BLE_IRQn \
}
/*!
* @}
*/ /* end of group BLEDP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CALIB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CALIB_Peripheral_Access_Layer CALIB Peripheral Access Layer
* @{
*/
/** CALIB - Register Layout Typedef */
typedef struct
{
__IO uint32_t START; /**< calibration start register, offset: 0x0 */
__I uint32_t STATUS; /**< calibration FSM status register, offset: 0x4 */
__I uint32_t DC_CODE; /**< DC code status register, offset: 0x8 */
__IO uint32_t DC_CFG; /**< DC code configured code register, offset: 0xC */
__I uint32_t RCO_RC_REF_OSC_CODE; /**< RCO RC PLL48M OSC code status register, offset: 0x10 */
__IO uint32_t RCO_RC_REF_OSC_CFG; /**< RCO RC PLL48M OSC configured code register, offset: 0x14 */
__I uint32_t VCOA_KVCO2M_CODE; /**< reserved, offset: 0x18 */
__IO uint32_t VCOA_KVCO2M_CFG; /**< reserved, offset: 0x1C */
__I uint32_t VCOF_KVCO_PO_CODE; /**< reserved, offset: 0x20 */
__IO uint32_t VCOF_KVCO_CFG; /**< VCOF hop calibration bypass, offset: 0x24 */
__I uint32_t VCOF_KVCO_CODE; /**< reserved, offset: 0x28 */
__I uint32_t KVCO_HOP_CODE; /**< reserved, offset: 0x2C */
__IO uint32_t VCOF_CNT_SLOPE; /**< reserved, offset: 0x30 */
__I uint32_t XTL_CODE; /**< Reserved, offset: 0x34 */
__IO uint32_t XTL_CFG; /**< Reserved, offset: 0x38 */
__IO uint32_t CAL_DLY; /**< hop calibration delay bypass, offset: 0x3C */
__I uint32_t DONE; /**< Reserved, offset: 0x40 */
uint8_t RESERVED_0[956];
__IO uint32_t RRF1; /**< Amplitude of LO buffer for active mixer, offset: 0x400 */
__IO uint32_t PLL48_PPF; /**< reserved, offset: 0x404 */
__IO uint32_t LO0; /**< reserved, offset: 0x408 */
__IO uint32_t LO1; /**< Reserved, offset: 0x40C */
__IO uint32_t PA_CTRL; /**< Reserved, offset: 0x410 */
uint8_t RESERVED_1[1004];
__IO uint32_t CTRL; /**< Reserved, offset: 0x800 */
__IO uint32_t INT_RAW; /**< Reserved, offset: 0x804 */
__IO uint32_t INTEN; /**< Reserved, offset: 0x808 */
__I uint32_t INT_STAT; /**< Reserved, offset: 0x80C */
__IO uint32_t TIF; /**< reserved, offset: 0x810 */
__I uint32_t KVCO_MEAN; /**< reserved, offset: 0x814 */
__I uint32_t KVCO_DLT; /**< reserved, offset: 0x818 */
__IO uint32_t LO_CFG; /**< , offset: 0x81C */
__I uint32_t LO_TABLE; /**< , offset: 0x820 */
__I uint32_t LO_RATIO; /**< , offset: 0x824 */
__IO uint32_t VCO_MOD_CFG; /**< TRX 2M mode selection signal, offset: 0x828 */
__I uint32_t VCO_MOD_STAT; /**< , offset: 0x82C */
__I uint32_t CH_IDX; /**< , offset: 0x830 */
__I uint32_t VCOF_CNT_UP; /**< reserved, offset: 0x834 */
__I uint32_t VCOF_CNT_DN; /**< reserved, offset: 0x838 */
} CALIB_Type;
/* ----------------------------------------------------------------------------
-- CALIB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CALIB_Register_Masks CALIB Register Masks
* @{
*/
/*! @name START - calibration start register */
#define CALIB_START_PO_CLB_START_MASK (0x1U)
#define CALIB_START_PO_CLB_START_SHIFT (0U)
#define CALIB_START_PO_CLB_START(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_START_PO_CLB_START_SHIFT)) & CALIB_START_PO_CLB_START_MASK)
#define CALIB_START_HOP_CLB_START_MASK (0x2U)
#define CALIB_START_HOP_CLB_START_SHIFT (1U)
#define CALIB_START_HOP_CLB_START(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_START_HOP_CLB_START_SHIFT)) & CALIB_START_HOP_CLB_START_MASK)
#define CALIB_START_OSC_CLB_START_MASK (0x4U)
#define CALIB_START_OSC_CLB_START_SHIFT (2U)
#define CALIB_START_OSC_CLB_START(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_START_OSC_CLB_START_SHIFT)) & CALIB_START_OSC_CLB_START_MASK)
#define CALIB_START_REF_CLB_START_MASK (0x8U)
#define CALIB_START_REF_CLB_START_SHIFT (3U)
#define CALIB_START_REF_CLB_START(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_START_REF_CLB_START_SHIFT)) & CALIB_START_REF_CLB_START_MASK)
#define CALIB_START_RCO_CLB_START_MASK (0x10U)
#define CALIB_START_RCO_CLB_START_SHIFT (4U)
#define CALIB_START_RCO_CLB_START(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_START_RCO_CLB_START_SHIFT)) & CALIB_START_RCO_CLB_START_MASK)
#define CALIB_START_XTL_CLB_START_MASK (0x20U)
#define CALIB_START_XTL_CLB_START_SHIFT (5U)
#define CALIB_START_XTL_CLB_START(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_START_XTL_CLB_START_SHIFT)) & CALIB_START_XTL_CLB_START_MASK)
/*! @name STATUS - calibration FSM status register */
#define CALIB_STATUS_TOP_FSM_MASK (0x1FU)
#define CALIB_STATUS_TOP_FSM_SHIFT (0U)
#define CALIB_STATUS_TOP_FSM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_STATUS_TOP_FSM_SHIFT)) & CALIB_STATUS_TOP_FSM_MASK)
#define CALIB_STATUS_DC_FSM_MASK (0x1E0U)
#define CALIB_STATUS_DC_FSM_SHIFT (5U)
#define CALIB_STATUS_DC_FSM(x) (((uint32_t)(((uint32_t)(x)) << CALIB_STATUS_DC_FSM_SHIFT)) & CALIB_STATUS_DC_FSM_MASK)
#define CALIB_STATUS_VCOA_FSM_MASK (0xE00U)
#define CALIB_STATUS_VCOA_FSM_SHIFT (9U)
#define CALIB_STATUS_VCOA_FSM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_STATUS_VCOA_FSM_SHIFT)) & CALIB_STATUS_VCOA_FSM_MASK)
#define CALIB_STATUS_VCOF_FSM_MASK (0x1F000U)
#define CALIB_STATUS_VCOF_FSM_SHIFT (12U)
#define CALIB_STATUS_VCOF_FSM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_STATUS_VCOF_FSM_SHIFT)) & CALIB_STATUS_VCOF_FSM_MASK)
#define CALIB_STATUS_KVCO_FSM_MASK (0x1E0000U)
#define CALIB_STATUS_KVCO_FSM_SHIFT (17U)
#define CALIB_STATUS_KVCO_FSM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_STATUS_KVCO_FSM_SHIFT)) & CALIB_STATUS_KVCO_FSM_MASK)
#define CALIB_STATUS_RCO_FSM_MASK (0xE00000U)
#define CALIB_STATUS_RCO_FSM_SHIFT (21U)
#define CALIB_STATUS_RCO_FSM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_STATUS_RCO_FSM_SHIFT)) & CALIB_STATUS_RCO_FSM_MASK)
#define CALIB_STATUS_OSC_FSM_MASK (0x7000000U)
#define CALIB_STATUS_OSC_FSM_SHIFT (24U)
#define CALIB_STATUS_OSC_FSM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_STATUS_OSC_FSM_SHIFT)) & CALIB_STATUS_OSC_FSM_MASK)
#define CALIB_STATUS_REF_FSM_MASK (0x38000000U)
#define CALIB_STATUS_REF_FSM_SHIFT (27U)
#define CALIB_STATUS_REF_FSM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_STATUS_REF_FSM_SHIFT)) & CALIB_STATUS_REF_FSM_MASK)
/*! @name DC_CODE - DC code status register */
#define CALIB_DC_CODE_PPF_DCCAL2_I_MASK (0xFU)
#define CALIB_DC_CODE_PPF_DCCAL2_I_SHIFT (0U)
#define CALIB_DC_CODE_PPF_DCCAL2_I(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CODE_PPF_DCCAL2_I_SHIFT)) & CALIB_DC_CODE_PPF_DCCAL2_I_MASK)
#define CALIB_DC_CODE_PPF_DCCAL2_Q_MASK (0xF0U)
#define CALIB_DC_CODE_PPF_DCCAL2_Q_SHIFT (4U)
#define CALIB_DC_CODE_PPF_DCCAL2_Q(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CODE_PPF_DCCAL2_Q_SHIFT)) & CALIB_DC_CODE_PPF_DCCAL2_Q_MASK)
#define CALIB_DC_CODE_PPF_DCCAL_I_MASK (0x3F0000U)
#define CALIB_DC_CODE_PPF_DCCAL_I_SHIFT (16U)
#define CALIB_DC_CODE_PPF_DCCAL_I(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CODE_PPF_DCCAL_I_SHIFT)) & CALIB_DC_CODE_PPF_DCCAL_I_MASK)
#define CALIB_DC_CODE_PPF_DCCAL_Q_MASK (0x3F000000U)
#define CALIB_DC_CODE_PPF_DCCAL_Q_SHIFT (24U)
#define CALIB_DC_CODE_PPF_DCCAL_Q(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CODE_PPF_DCCAL_Q_SHIFT)) & CALIB_DC_CODE_PPF_DCCAL_Q_MASK)
/*! @name DC_CFG - DC code configured code register */
#define CALIB_DC_CFG_PPF_DCCAL2_CFG_I_MASK (0xFU)
#define CALIB_DC_CFG_PPF_DCCAL2_CFG_I_SHIFT (0U)
#define CALIB_DC_CFG_PPF_DCCAL2_CFG_I(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_PPF_DCCAL2_CFG_I_SHIFT)) & CALIB_DC_CFG_PPF_DCCAL2_CFG_I_MASK)
#define CALIB_DC_CFG_PPF_DCCAL2_CFG_Q_MASK (0xF0U)
#define CALIB_DC_CFG_PPF_DCCAL2_CFG_Q_SHIFT (4U)
#define CALIB_DC_CFG_PPF_DCCAL2_CFG_Q(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_PPF_DCCAL2_CFG_Q_SHIFT)) & CALIB_DC_CFG_PPF_DCCAL2_CFG_Q_MASK)
#define CALIB_DC_CFG_DC_2NDCAL_DIS_MASK (0x100U)
#define CALIB_DC_CFG_DC_2NDCAL_DIS_SHIFT (8U)
#define CALIB_DC_CFG_DC_2NDCAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_DC_2NDCAL_DIS_SHIFT)) & CALIB_DC_CFG_DC_2NDCAL_DIS_MASK)
#define CALIB_DC_CFG_DC_2NDCAL_REQ_MASK (0x200U)
#define CALIB_DC_CFG_DC_2NDCAL_REQ_SHIFT (9U)
#define CALIB_DC_CFG_DC_2NDCAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_DC_2NDCAL_REQ_SHIFT)) & CALIB_DC_CFG_DC_2NDCAL_REQ_MASK)
#define CALIB_DC_CFG_PPF_DCCAL_CFG_I_MASK (0x3F0000U)
#define CALIB_DC_CFG_PPF_DCCAL_CFG_I_SHIFT (16U)
#define CALIB_DC_CFG_PPF_DCCAL_CFG_I(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_PPF_DCCAL_CFG_I_SHIFT)) & CALIB_DC_CFG_PPF_DCCAL_CFG_I_MASK)
#define CALIB_DC_CFG_DC_HOP_CAL_BP_MASK (0x400000U)
#define CALIB_DC_CFG_DC_HOP_CAL_BP_SHIFT (22U)
#define CALIB_DC_CFG_DC_HOP_CAL_BP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_DC_HOP_CAL_BP_SHIFT)) & CALIB_DC_CFG_DC_HOP_CAL_BP_MASK)
#define CALIB_DC_CFG_PPF_DCCAL_CFG_Q_MASK (0x3F000000U)
#define CALIB_DC_CFG_PPF_DCCAL_CFG_Q_SHIFT (24U)
#define CALIB_DC_CFG_PPF_DCCAL_CFG_Q(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_PPF_DCCAL_CFG_Q_SHIFT)) & CALIB_DC_CFG_PPF_DCCAL_CFG_Q_MASK)
#define CALIB_DC_CFG_DC_1STCAL_DIS_MASK (0x40000000U)
#define CALIB_DC_CFG_DC_1STCAL_DIS_SHIFT (30U)
#define CALIB_DC_CFG_DC_1STCAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_DC_1STCAL_DIS_SHIFT)) & CALIB_DC_CFG_DC_1STCAL_DIS_MASK)
#define CALIB_DC_CFG_DC_1STCAL_REQ_MASK (0x80000000U)
#define CALIB_DC_CFG_DC_1STCAL_REQ_SHIFT (31U)
#define CALIB_DC_CFG_DC_1STCAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DC_CFG_DC_1STCAL_REQ_SHIFT)) & CALIB_DC_CFG_DC_1STCAL_REQ_MASK)
/*! @name RCO_RC_REF_OSC_CODE - RCO RC PLL48M OSC code status register */
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_RCO_CAP_MASK (0xFU)
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_RCO_CAP_SHIFT (0U)
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_RCO_CAP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CODE_CAU_RCO_CAP_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CODE_CAU_RCO_CAP_MASK)
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_OSC_CUR_MASK (0x1F00U)
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_OSC_CUR_SHIFT (8U)
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_OSC_CUR(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CODE_CAU_OSC_CUR_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CODE_CAU_OSC_CUR_MASK)
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_RC_CAL_OUT2REG_MASK (0xF0000U)
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_RC_CAL_OUT2REG_SHIFT (16U)
#define CALIB_RCO_RC_REF_OSC_CODE_CAU_RC_CAL_OUT2REG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CODE_CAU_RC_CAL_OUT2REG_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CODE_CAU_RC_CAL_OUT2REG_MASK)
#define CALIB_RCO_RC_REF_OSC_CODE_PLL48_ENREF_MASK (0xF000000U)
#define CALIB_RCO_RC_REF_OSC_CODE_PLL48_ENREF_SHIFT (24U)
#define CALIB_RCO_RC_REF_OSC_CODE_PLL48_ENREF(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CODE_PLL48_ENREF_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CODE_PLL48_ENREF_MASK)
/*! @name RCO_RC_REF_OSC_CFG - RCO RC PLL48M OSC configured code register */
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RCO_CAP_CFG_MASK (0xFU)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RCO_CAP_CFG_SHIFT (0U)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RCO_CAP_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_CAU_RCO_CAP_CFG_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_CAU_RCO_CAP_CFG_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_DIS_MASK (0x10U)
#define CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_DIS_SHIFT (4U)
#define CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_DIS_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_DIS_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_REQ_MASK (0x20U)
#define CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_REQ_SHIFT (5U)
#define CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_REQ_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_RCO_CAL_REQ_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_OSC_CUR_CFG_MASK (0x1F00U)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_OSC_CUR_CFG_SHIFT (8U)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_OSC_CUR_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_CAU_OSC_CUR_CFG_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_CAU_OSC_CUR_CFG_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_DIS_MASK (0x2000U)
#define CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_DIS_SHIFT (13U)
#define CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_DIS_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_DIS_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_REQ_MASK (0x4000U)
#define CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_REQ_SHIFT (14U)
#define CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_REQ_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_OSC_CAL_REQ_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_REG_IN_MASK (0xF0000U)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_REG_IN_SHIFT (16U)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_REG_IN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_REG_IN_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_REG_IN_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_DIS_MASK (0x100000U)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_DIS_SHIFT (20U)
#define CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_DIS_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_CAU_RC_CAL_DIS_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_RC_CAL_REQ_MASK (0x200000U)
#define CALIB_RCO_RC_REF_OSC_CFG_RC_CAL_REQ_SHIFT (21U)
#define CALIB_RCO_RC_REF_OSC_CFG_RC_CAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_RC_CAL_REQ_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_RC_CAL_REQ_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_PLL48_ENREF_CFG_MASK (0xF000000U)
#define CALIB_RCO_RC_REF_OSC_CFG_PLL48_ENREF_CFG_SHIFT (24U)
#define CALIB_RCO_RC_REF_OSC_CFG_PLL48_ENREF_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_PLL48_ENREF_CFG_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_PLL48_ENREF_CFG_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_DIS_MASK (0x10000000U)
#define CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_DIS_SHIFT (28U)
#define CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_DIS_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_DIS_MASK)
#define CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_REQ_MASK (0x20000000U)
#define CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_REQ_SHIFT (29U)
#define CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_REQ_SHIFT)) & \
CALIB_RCO_RC_REF_OSC_CFG_REF_CAL_REQ_MASK)
/*! @name VCOA_KVCO2M_CODE - reserved */
#define CALIB_VCOA_KVCO2M_CODE_KCALF2M_PO_MASK (0x7FFU)
#define CALIB_VCOA_KVCO2M_CODE_KCALF2M_PO_SHIFT (0U)
#define CALIB_VCOA_KVCO2M_CODE_KCALF2M_PO(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CODE_KCALF2M_PO_SHIFT)) & CALIB_VCOA_KVCO2M_CODE_KCALF2M_PO_MASK)
#define CALIB_VCOA_KVCO2M_CODE_TX_VCO_AMP_MASK (0x1F0000U)
#define CALIB_VCOA_KVCO2M_CODE_TX_VCO_AMP_SHIFT (16U)
#define CALIB_VCOA_KVCO2M_CODE_TX_VCO_AMP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CODE_TX_VCO_AMP_SHIFT)) & CALIB_VCOA_KVCO2M_CODE_TX_VCO_AMP_MASK)
#define CALIB_VCOA_KVCO2M_CODE_RX_VCO_AMP_MASK (0x1F000000U)
#define CALIB_VCOA_KVCO2M_CODE_RX_VCO_AMP_SHIFT (24U)
#define CALIB_VCOA_KVCO2M_CODE_RX_VCO_AMP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CODE_RX_VCO_AMP_SHIFT)) & CALIB_VCOA_KVCO2M_CODE_RX_VCO_AMP_MASK)
/*! @name VCOA_KVCO2M_CFG - reserved */
#define CALIB_VCOA_KVCO2M_CFG_KCALF2M_CFG_MASK (0x7FFU)
#define CALIB_VCOA_KVCO2M_CFG_KCALF2M_CFG_SHIFT (0U)
#define CALIB_VCOA_KVCO2M_CFG_KCALF2M_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CFG_KCALF2M_CFG_SHIFT)) & CALIB_VCOA_KVCO2M_CFG_KCALF2M_CFG_MASK)
#define CALIB_VCOA_KVCO2M_CFG_KCALF2M_BP_MASK (0x800U)
#define CALIB_VCOA_KVCO2M_CFG_KCALF2M_BP_SHIFT (11U)
#define CALIB_VCOA_KVCO2M_CFG_KCALF2M_BP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CFG_KCALF2M_BP_SHIFT)) & CALIB_VCOA_KVCO2M_CFG_KCALF2M_BP_MASK)
#define CALIB_VCOA_KVCO2M_CFG_KVCO_CAL_E_MASK (0x7000U)
#define CALIB_VCOA_KVCO2M_CFG_KVCO_CAL_E_SHIFT (12U)
#define CALIB_VCOA_KVCO2M_CFG_KVCO_CAL_E(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CFG_KVCO_CAL_E_SHIFT)) & CALIB_VCOA_KVCO2M_CFG_KVCO_CAL_E_MASK)
#define CALIB_VCOA_KVCO2M_CFG_TX_VCO_AMP_CFG_MASK (0x1F0000U)
#define CALIB_VCOA_KVCO2M_CFG_TX_VCO_AMP_CFG_SHIFT (16U)
#define CALIB_VCOA_KVCO2M_CFG_TX_VCO_AMP_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CFG_TX_VCO_AMP_CFG_SHIFT)) & \
CALIB_VCOA_KVCO2M_CFG_TX_VCO_AMP_CFG_MASK)
#define CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_DIS_MASK (0x200000U)
#define CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_DIS_SHIFT (21U)
#define CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_DIS_SHIFT)) & \
CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_DIS_MASK)
#define CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_REQ_MASK (0x400000U)
#define CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_REQ_SHIFT (22U)
#define CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_REQ_SHIFT)) & \
CALIB_VCOA_KVCO2M_CFG_VCOA_CAL_REQ_MASK)
#define CALIB_VCOA_KVCO2M_CFG_RX_VCO_AMP_CFG_MASK (0x1F000000U)
#define CALIB_VCOA_KVCO2M_CFG_RX_VCO_AMP_CFG_SHIFT (24U)
#define CALIB_VCOA_KVCO2M_CFG_RX_VCO_AMP_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOA_KVCO2M_CFG_RX_VCO_AMP_CFG_SHIFT)) & \
CALIB_VCOA_KVCO2M_CFG_RX_VCO_AMP_CFG_MASK)
/*! @name VCOF_KVCO_PO_CODE - reserved */
#define CALIB_VCOF_KVCO_PO_CODE_KCALF_PO_MASK (0x7FFU)
#define CALIB_VCOF_KVCO_PO_CODE_KCALF_PO_SHIFT (0U)
#define CALIB_VCOF_KVCO_PO_CODE_KCALF_PO(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_PO_CODE_KCALF_PO_SHIFT)) & CALIB_VCOF_KVCO_PO_CODE_KCALF_PO_MASK)
#define CALIB_VCOF_KVCO_PO_CODE_TX_VCO_CBANK_PO_MASK (0x3F0000U)
#define CALIB_VCOF_KVCO_PO_CODE_TX_VCO_CBANK_PO_SHIFT (16U)
#define CALIB_VCOF_KVCO_PO_CODE_TX_VCO_CBANK_PO(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_PO_CODE_TX_VCO_CBANK_PO_SHIFT)) & \
CALIB_VCOF_KVCO_PO_CODE_TX_VCO_CBANK_PO_MASK)
#define CALIB_VCOF_KVCO_PO_CODE_RX_VCO_CBANK_PO_MASK (0x3F000000U)
#define CALIB_VCOF_KVCO_PO_CODE_RX_VCO_CBANK_PO_SHIFT (24U)
#define CALIB_VCOF_KVCO_PO_CODE_RX_VCO_CBANK_PO(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_PO_CODE_RX_VCO_CBANK_PO_SHIFT)) & \
CALIB_VCOF_KVCO_PO_CODE_RX_VCO_CBANK_PO_MASK)
/*! @name VCOF_KVCO_CFG - VCOF hop calibration bypass */
#define CALIB_VCOF_KVCO_CFG_KCALF_CFG_MASK (0x7FFU)
#define CALIB_VCOF_KVCO_CFG_KCALF_CFG_SHIFT (0U)
#define CALIB_VCOF_KVCO_CFG_KCALF_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_KCALF_CFG_SHIFT)) & CALIB_VCOF_KVCO_CFG_KCALF_CFG_MASK)
#define CALIB_VCOF_KVCO_CFG_KVCO_REQ_MASK (0x800U)
#define CALIB_VCOF_KVCO_CFG_KVCO_REQ_SHIFT (11U)
#define CALIB_VCOF_KVCO_CFG_KVCO_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_KVCO_REQ_SHIFT)) & CALIB_VCOF_KVCO_CFG_KVCO_REQ_MASK)
#define CALIB_VCOF_KVCO_CFG_KVCO_DIS_MASK (0x1000U)
#define CALIB_VCOF_KVCO_CFG_KVCO_DIS_SHIFT (12U)
#define CALIB_VCOF_KVCO_CFG_KVCO_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_KVCO_DIS_SHIFT)) & CALIB_VCOF_KVCO_CFG_KVCO_DIS_MASK)
#define CALIB_VCOF_KVCO_CFG_KVCO_SKIP_MASK (0x2000U)
#define CALIB_VCOF_KVCO_CFG_KVCO_SKIP_SHIFT (13U)
#define CALIB_VCOF_KVCO_CFG_KVCO_SKIP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_KVCO_SKIP_SHIFT)) & CALIB_VCOF_KVCO_CFG_KVCO_SKIP_MASK)
#define CALIB_VCOF_KVCO_CFG_TX_VCO_CBANK_CFG_MASK (0x3F0000U)
#define CALIB_VCOF_KVCO_CFG_TX_VCO_CBANK_CFG_SHIFT (16U)
#define CALIB_VCOF_KVCO_CFG_TX_VCO_CBANK_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_TX_VCO_CBANK_CFG_SHIFT)) & \
CALIB_VCOF_KVCO_CFG_TX_VCO_CBANK_CFG_MASK)
#define CALIB_VCOF_KVCO_CFG_VCOF_CAL_DIS_MASK (0x400000U)
#define CALIB_VCOF_KVCO_CFG_VCOF_CAL_DIS_SHIFT (22U)
#define CALIB_VCOF_KVCO_CFG_VCOF_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_VCOF_CAL_DIS_SHIFT)) & CALIB_VCOF_KVCO_CFG_VCOF_CAL_DIS_MASK)
#define CALIB_VCOF_KVCO_CFG_VCOF_CAL_REQ_MASK (0x800000U)
#define CALIB_VCOF_KVCO_CFG_VCOF_CAL_REQ_SHIFT (23U)
#define CALIB_VCOF_KVCO_CFG_VCOF_CAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_VCOF_CAL_REQ_SHIFT)) & CALIB_VCOF_KVCO_CFG_VCOF_CAL_REQ_MASK)
#define CALIB_VCOF_KVCO_CFG_RX_VCO_CBANK_CFG_MASK (0x3F000000U)
#define CALIB_VCOF_KVCO_CFG_RX_VCO_CBANK_CFG_SHIFT (24U)
#define CALIB_VCOF_KVCO_CFG_RX_VCO_CBANK_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_RX_VCO_CBANK_CFG_SHIFT)) & \
CALIB_VCOF_KVCO_CFG_RX_VCO_CBANK_CFG_MASK)
#define CALIB_VCOF_KVCO_CFG_VCOF_SKIP_MASK (0x40000000U)
#define CALIB_VCOF_KVCO_CFG_VCOF_SKIP_SHIFT (30U)
#define CALIB_VCOF_KVCO_CFG_VCOF_SKIP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_VCOF_SKIP_SHIFT)) & CALIB_VCOF_KVCO_CFG_VCOF_SKIP_MASK)
#define CALIB_VCOF_KVCO_CFG_VCOF_HOP_BP_MASK (0x80000000U)
#define CALIB_VCOF_KVCO_CFG_VCOF_HOP_BP_SHIFT (31U)
#define CALIB_VCOF_KVCO_CFG_VCOF_HOP_BP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CFG_VCOF_HOP_BP_SHIFT)) & CALIB_VCOF_KVCO_CFG_VCOF_HOP_BP_MASK)
/*! @name VCOF_KVCO_CODE - reserved */
#define CALIB_VCOF_KVCO_CODE_KCALF_MASK (0x7FFU)
#define CALIB_VCOF_KVCO_CODE_KCALF_SHIFT (0U)
#define CALIB_VCOF_KVCO_CODE_KCALF(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CODE_KCALF_SHIFT)) & CALIB_VCOF_KVCO_CODE_KCALF_MASK)
#define CALIB_VCOF_KVCO_CODE_TX_VCO_CBANK_MASK (0x3F0000U)
#define CALIB_VCOF_KVCO_CODE_TX_VCO_CBANK_SHIFT (16U)
#define CALIB_VCOF_KVCO_CODE_TX_VCO_CBANK(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CODE_TX_VCO_CBANK_SHIFT)) & CALIB_VCOF_KVCO_CODE_TX_VCO_CBANK_MASK)
#define CALIB_VCOF_KVCO_CODE_RX_VCO_CBANK_MASK (0x3F000000U)
#define CALIB_VCOF_KVCO_CODE_RX_VCO_CBANK_SHIFT (24U)
#define CALIB_VCOF_KVCO_CODE_RX_VCO_CBANK(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_KVCO_CODE_RX_VCO_CBANK_SHIFT)) & CALIB_VCOF_KVCO_CODE_RX_VCO_CBANK_MASK)
/*! @name KVCO_HOP_CODE - reserved */
#define CALIB_KVCO_HOP_CODE_KCALF1M_MASK (0x7FFU)
#define CALIB_KVCO_HOP_CODE_KCALF1M_SHIFT (0U)
#define CALIB_KVCO_HOP_CODE_KCALF1M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_KVCO_HOP_CODE_KCALF1M_SHIFT)) & CALIB_KVCO_HOP_CODE_KCALF1M_MASK)
#define CALIB_KVCO_HOP_CODE_KCALF2M_MASK (0x7FF0000U)
#define CALIB_KVCO_HOP_CODE_KCALF2M_SHIFT (16U)
#define CALIB_KVCO_HOP_CODE_KCALF2M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_KVCO_HOP_CODE_KCALF2M_SHIFT)) & CALIB_KVCO_HOP_CODE_KCALF2M_MASK)
/*! @name VCOF_CNT_SLOPE - reserved */
#define CALIB_VCOF_CNT_SLOPE_TX_VCOF_CNT_MASK (0xFFU)
#define CALIB_VCOF_CNT_SLOPE_TX_VCOF_CNT_SHIFT (0U)
#define CALIB_VCOF_CNT_SLOPE_TX_VCOF_CNT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_CNT_SLOPE_TX_VCOF_CNT_SHIFT)) & CALIB_VCOF_CNT_SLOPE_TX_VCOF_CNT_MASK)
#define CALIB_VCOF_CNT_SLOPE_TX_SLOPE_MASK (0x3F00U)
#define CALIB_VCOF_CNT_SLOPE_TX_SLOPE_SHIFT (8U)
#define CALIB_VCOF_CNT_SLOPE_TX_SLOPE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_CNT_SLOPE_TX_SLOPE_SHIFT)) & CALIB_VCOF_CNT_SLOPE_TX_SLOPE_MASK)
#define CALIB_VCOF_CNT_SLOPE_RX_VCOF_CNT_MASK (0xFF0000U)
#define CALIB_VCOF_CNT_SLOPE_RX_VCOF_CNT_SHIFT (16U)
#define CALIB_VCOF_CNT_SLOPE_RX_VCOF_CNT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_CNT_SLOPE_RX_VCOF_CNT_SHIFT)) & CALIB_VCOF_CNT_SLOPE_RX_VCOF_CNT_MASK)
#define CALIB_VCOF_CNT_SLOPE_RX_SLOPE_MASK (0x3F000000U)
#define CALIB_VCOF_CNT_SLOPE_RX_SLOPE_SHIFT (24U)
#define CALIB_VCOF_CNT_SLOPE_RX_SLOPE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_CNT_SLOPE_RX_SLOPE_SHIFT)) & CALIB_VCOF_CNT_SLOPE_RX_SLOPE_MASK)
/*! @name XTL_CODE - Reserved */
#define CALIB_XTL_CODE_XTL_XICTRL_CODE_MASK (0x3FU)
#define CALIB_XTL_CODE_XTL_XICTRL_CODE_SHIFT (0U)
#define CALIB_XTL_CODE_XTL_XICTRL_CODE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_XTL_CODE_XTL_XICTRL_CODE_SHIFT)) & CALIB_XTL_CODE_XTL_XICTRL_CODE_MASK)
#define CALIB_XTL_CODE_XTL_AMP_DET_OUT_MASK (0x100U)
#define CALIB_XTL_CODE_XTL_AMP_DET_OUT_SHIFT (8U)
#define CALIB_XTL_CODE_XTL_AMP_DET_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_XTL_CODE_XTL_AMP_DET_OUT_SHIFT)) & CALIB_XTL_CODE_XTL_AMP_DET_OUT_MASK)
/*! @name XTL_CFG - Reserved */
#define CALIB_XTL_CFG_XTL_XICTRL_CFG_MASK (0x3FU)
#define CALIB_XTL_CFG_XTL_XICTRL_CFG_SHIFT (0U)
#define CALIB_XTL_CFG_XTL_XICTRL_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_XTL_CFG_XTL_XICTRL_CFG_SHIFT)) & CALIB_XTL_CFG_XTL_XICTRL_CFG_MASK)
#define CALIB_XTL_CFG_XTL_CAL_DIS_MASK (0x40U)
#define CALIB_XTL_CFG_XTL_CAL_DIS_SHIFT (6U)
#define CALIB_XTL_CFG_XTL_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_XTL_CFG_XTL_CAL_DIS_SHIFT)) & CALIB_XTL_CFG_XTL_CAL_DIS_MASK)
#define CALIB_XTL_CFG_XTL_CAL_REQ_MASK (0x80U)
#define CALIB_XTL_CFG_XTL_CAL_REQ_SHIFT (7U)
#define CALIB_XTL_CFG_XTL_CAL_REQ(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_XTL_CFG_XTL_CAL_REQ_SHIFT)) & CALIB_XTL_CFG_XTL_CAL_REQ_MASK)
/*! @name CAL_DLY - hop calibration delay bypass */
#define CALIB_CAL_DLY_HOP_DLY_MASK (0x3FU)
#define CALIB_CAL_DLY_HOP_DLY_SHIFT (0U)
#define CALIB_CAL_DLY_HOP_DLY(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CAL_DLY_HOP_DLY_SHIFT)) & CALIB_CAL_DLY_HOP_DLY_MASK)
#define CALIB_CAL_DLY_HOP_DLY_BP_MASK (0x80U)
#define CALIB_CAL_DLY_HOP_DLY_BP_SHIFT (7U)
#define CALIB_CAL_DLY_HOP_DLY_BP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CAL_DLY_HOP_DLY_BP_SHIFT)) & CALIB_CAL_DLY_HOP_DLY_BP_MASK)
#define CALIB_CAL_DLY_TX_DLY_DIG1M_MASK (0x300U)
#define CALIB_CAL_DLY_TX_DLY_DIG1M_SHIFT (8U)
#define CALIB_CAL_DLY_TX_DLY_DIG1M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CAL_DLY_TX_DLY_DIG1M_SHIFT)) & CALIB_CAL_DLY_TX_DLY_DIG1M_MASK)
#define CALIB_CAL_DLY_TX_DLY_DIG2M_MASK (0xC00U)
#define CALIB_CAL_DLY_TX_DLY_DIG2M_SHIFT (10U)
#define CALIB_CAL_DLY_TX_DLY_DIG2M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CAL_DLY_TX_DLY_DIG2M_SHIFT)) & CALIB_CAL_DLY_TX_DLY_DIG2M_MASK)
#define CALIB_CAL_DLY_TX_DLY_DAC_1M_MASK (0x3000U)
#define CALIB_CAL_DLY_TX_DLY_DAC_1M_SHIFT (12U)
#define CALIB_CAL_DLY_TX_DLY_DAC_1M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CAL_DLY_TX_DLY_DAC_1M_SHIFT)) & CALIB_CAL_DLY_TX_DLY_DAC_1M_MASK)
#define CALIB_CAL_DLY_TX_DLY_DAC_2M_MASK (0xC000U)
#define CALIB_CAL_DLY_TX_DLY_DAC_2M_SHIFT (14U)
#define CALIB_CAL_DLY_TX_DLY_DAC_2M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CAL_DLY_TX_DLY_DAC_2M_SHIFT)) & CALIB_CAL_DLY_TX_DLY_DAC_2M_MASK)
#define CALIB_CAL_DLY_RX_PWRUP_CNT_TH1M_MASK (0xFF0000U)
#define CALIB_CAL_DLY_RX_PWRUP_CNT_TH1M_SHIFT (16U)
#define CALIB_CAL_DLY_RX_PWRUP_CNT_TH1M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CAL_DLY_RX_PWRUP_CNT_TH1M_SHIFT)) & CALIB_CAL_DLY_RX_PWRUP_CNT_TH1M_MASK)
#define CALIB_CAL_DLY_RX_PWRUP_CNT_TH2M_MASK (0xFF000000U)
#define CALIB_CAL_DLY_RX_PWRUP_CNT_TH2M_SHIFT (24U)
#define CALIB_CAL_DLY_RX_PWRUP_CNT_TH2M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CAL_DLY_RX_PWRUP_CNT_TH2M_SHIFT)) & CALIB_CAL_DLY_RX_PWRUP_CNT_TH2M_MASK)
/*! @name DONE - Reserved */
#define CALIB_DONE_OSC_CAL_DONE_MASK (0x4U)
#define CALIB_DONE_OSC_CAL_DONE_SHIFT (2U)
#define CALIB_DONE_OSC_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_OSC_CAL_DONE_SHIFT)) & CALIB_DONE_OSC_CAL_DONE_MASK)
#define CALIB_DONE_REF_CAL_DONE_MASK (0x8U)
#define CALIB_DONE_REF_CAL_DONE_SHIFT (3U)
#define CALIB_DONE_REF_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_REF_CAL_DONE_SHIFT)) & CALIB_DONE_REF_CAL_DONE_MASK)
#define CALIB_DONE_RCO_CAL_DONE_MASK (0x10U)
#define CALIB_DONE_RCO_CAL_DONE_SHIFT (4U)
#define CALIB_DONE_RCO_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_RCO_CAL_DONE_SHIFT)) & CALIB_DONE_RCO_CAL_DONE_MASK)
#define CALIB_DONE_RC_CAL_DONE_MASK (0x20U)
#define CALIB_DONE_RC_CAL_DONE_SHIFT (5U)
#define CALIB_DONE_RC_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_RC_CAL_DONE_SHIFT)) & CALIB_DONE_RC_CAL_DONE_MASK)
#define CALIB_DONE_VCOF_CAL_DONE_MASK (0x40U)
#define CALIB_DONE_VCOF_CAL_DONE_SHIFT (6U)
#define CALIB_DONE_VCOF_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_VCOF_CAL_DONE_SHIFT)) & CALIB_DONE_VCOF_CAL_DONE_MASK)
#define CALIB_DONE_VCOA_CAL_DONE_MASK (0x80U)
#define CALIB_DONE_VCOA_CAL_DONE_SHIFT (7U)
#define CALIB_DONE_VCOA_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_VCOA_CAL_DONE_SHIFT)) & CALIB_DONE_VCOA_CAL_DONE_MASK)
#define CALIB_DONE_DC2ND_CAL_DONE_MASK (0x100U)
#define CALIB_DONE_DC2ND_CAL_DONE_SHIFT (8U)
#define CALIB_DONE_DC2ND_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_DC2ND_CAL_DONE_SHIFT)) & CALIB_DONE_DC2ND_CAL_DONE_MASK)
#define CALIB_DONE_DC1ST_CAL_DONE_MASK (0x200U)
#define CALIB_DONE_DC1ST_CAL_DONE_SHIFT (9U)
#define CALIB_DONE_DC1ST_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_DC1ST_CAL_DONE_SHIFT)) & CALIB_DONE_DC1ST_CAL_DONE_MASK)
#define CALIB_DONE_XTL_CAL_DONE_MASK (0x400U)
#define CALIB_DONE_XTL_CAL_DONE_SHIFT (10U)
#define CALIB_DONE_XTL_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_XTL_CAL_DONE_SHIFT)) & CALIB_DONE_XTL_CAL_DONE_MASK)
#define CALIB_DONE_KVCO_CAL_DONE_MASK (0x800U)
#define CALIB_DONE_KVCO_CAL_DONE_SHIFT (11U)
#define CALIB_DONE_KVCO_CAL_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_KVCO_CAL_DONE_SHIFT)) & CALIB_DONE_KVCO_CAL_DONE_MASK)
#define CALIB_DONE_KVCO_HOP_DONE_MASK (0x1000U)
#define CALIB_DONE_KVCO_HOP_DONE_SHIFT (12U)
#define CALIB_DONE_KVCO_HOP_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_DONE_KVCO_HOP_DONE_SHIFT)) & CALIB_DONE_KVCO_HOP_DONE_MASK)
/*! @name RRF1 - Amplitude of LO buffer for active mixer */
#define CALIB_RRF1_RRF_INCAP2_MASK (0x7U)
#define CALIB_RRF1_RRF_INCAP2_SHIFT (0U)
#define CALIB_RRF1_RRF_INCAP2(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_INCAP2_SHIFT)) & CALIB_RRF1_RRF_INCAP2_MASK)
#define CALIB_RRF1_RRF_LOAD_CAP_MASK (0x78U)
#define CALIB_RRF1_RRF_LOAD_CAP_SHIFT (3U)
#define CALIB_RRF1_RRF_LOAD_CAP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_LOAD_CAP_SHIFT)) & CALIB_RRF1_RRF_LOAD_CAP_MASK)
#define CALIB_RRF1_RRF_TX_INCAP1_MASK (0x380U)
#define CALIB_RRF1_RRF_TX_INCAP1_SHIFT (7U)
#define CALIB_RRF1_RRF_TX_INCAP1(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_TX_INCAP1_SHIFT)) & CALIB_RRF1_RRF_TX_INCAP1_MASK)
#define CALIB_RRF1_RRF_RX_INCAP1_MASK (0x1C00U)
#define CALIB_RRF1_RRF_RX_INCAP1_SHIFT (10U)
#define CALIB_RRF1_RRF_RX_INCAP1(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_RX_INCAP1_SHIFT)) & CALIB_RRF1_RRF_RX_INCAP1_MASK)
#define CALIB_RRF1_RRF_VGATE11_LNA_MASK (0xE000U)
#define CALIB_RRF1_RRF_VGATE11_LNA_SHIFT (13U)
#define CALIB_RRF1_RRF_VGATE11_LNA(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_VGATE11_LNA_SHIFT)) & CALIB_RRF1_RRF_VGATE11_LNA_MASK)
#define CALIB_RRF1_RRF_BM_GM_MASK (0x30000U)
#define CALIB_RRF1_RRF_BM_GM_SHIFT (16U)
#define CALIB_RRF1_RRF_BM_GM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_BM_GM_SHIFT)) & CALIB_RRF1_RRF_BM_GM_MASK)
#define CALIB_RRF1_RRF_BM_LNA_MASK (0xC0000U)
#define CALIB_RRF1_RRF_BM_LNA_SHIFT (18U)
#define CALIB_RRF1_RRF_BM_LNA(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_BM_LNA_SHIFT)) & CALIB_RRF1_RRF_BM_LNA_MASK)
#define CALIB_RRF1_RRF_BM_MIXER_MASK (0x300000U)
#define CALIB_RRF1_RRF_BM_MIXER_SHIFT (20U)
#define CALIB_RRF1_RRF_BM_MIXER(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_BM_MIXER_SHIFT)) & CALIB_RRF1_RRF_BM_MIXER_MASK)
#define CALIB_RRF1_PPF_DCCAL_RES_MASK (0xC00000U)
#define CALIB_RRF1_PPF_DCCAL_RES_SHIFT (22U)
#define CALIB_RRF1_PPF_DCCAL_RES(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_PPF_DCCAL_RES_SHIFT)) & CALIB_RRF1_PPF_DCCAL_RES_MASK)
#define CALIB_RRF1_RRF_CAL_MIX_EN_MASK (0x1000000U)
#define CALIB_RRF1_RRF_CAL_MIX_EN_SHIFT (24U)
#define CALIB_RRF1_RRF_CAL_MIX_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_CAL_MIX_EN_SHIFT)) & CALIB_RRF1_RRF_CAL_MIX_EN_MASK)
#define CALIB_RRF1_RRF_CAL_MIX1_EN_MASK (0x2000000U)
#define CALIB_RRF1_RRF_CAL_MIX1_EN_SHIFT (25U)
#define CALIB_RRF1_RRF_CAL_MIX1_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_CAL_MIX1_EN_SHIFT)) & CALIB_RRF1_RRF_CAL_MIX1_EN_MASK)
#define CALIB_RRF1_RRF_LO_SEL_P_MASK (0xC000000U)
#define CALIB_RRF1_RRF_LO_SEL_P_SHIFT (26U)
#define CALIB_RRF1_RRF_LO_SEL_P(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_LO_SEL_P_SHIFT)) & CALIB_RRF1_RRF_LO_SEL_P_MASK)
#define CALIB_RRF1_RRF_LO_SEL_N_MASK (0x30000000U)
#define CALIB_RRF1_RRF_LO_SEL_N_SHIFT (28U)
#define CALIB_RRF1_RRF_LO_SEL_N(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_LO_SEL_N_SHIFT)) & CALIB_RRF1_RRF_LO_SEL_N_MASK)
#define CALIB_RRF1_RRF_LO_AMP_MASK (0xC0000000U)
#define CALIB_RRF1_RRF_LO_AMP_SHIFT (30U)
#define CALIB_RRF1_RRF_LO_AMP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_RRF1_RRF_LO_AMP_SHIFT)) & CALIB_RRF1_RRF_LO_AMP_MASK)
/*! @name PLL48_PPF - reserved */
#define CALIB_PLL48_PPF_PPF_BM_MASK (0x3U)
#define CALIB_PLL48_PPF_PPF_BM_SHIFT (0U)
#define CALIB_PLL48_PPF_PPF_BM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PLL48_PPF_PPF_BM_SHIFT)) & CALIB_PLL48_PPF_PPF_BM_MASK)
#define CALIB_PLL48_PPF_PPF_IQSW_MASK (0x4U)
#define CALIB_PLL48_PPF_PPF_IQSW_SHIFT (2U)
#define CALIB_PLL48_PPF_PPF_IQSW(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PLL48_PPF_PPF_IQSW_SHIFT)) & CALIB_PLL48_PPF_PPF_IQSW_MASK)
#define CALIB_PLL48_PPF_PLL48_DIFF_CLK_48M_DIS_MASK (0x8U)
#define CALIB_PLL48_PPF_PLL48_DIFF_CLK_48M_DIS_SHIFT (3U)
#define CALIB_PLL48_PPF_PLL48_DIFF_CLK_48M_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PLL48_PPF_PLL48_DIFF_CLK_48M_DIS_SHIFT)) & \
CALIB_PLL48_PPF_PLL48_DIFF_CLK_48M_DIS_MASK)
#define CALIB_PLL48_PPF_PLL48_TST_CPREF_MASK (0xF0U)
#define CALIB_PLL48_PPF_PLL48_TST_CPREF_SHIFT (4U)
#define CALIB_PLL48_PPF_PLL48_TST_CPREF(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PLL48_PPF_PLL48_TST_CPREF_SHIFT)) & CALIB_PLL48_PPF_PLL48_TST_CPREF_MASK)
/*! @name LO0 - reserved */
#define CALIB_LO0_VCO_DAC_IPTAT_MASK (0xFU)
#define CALIB_LO0_VCO_DAC_IPTAT_SHIFT (0U)
#define CALIB_LO0_VCO_DAC_IPTAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_DAC_IPTAT_SHIFT)) & CALIB_LO0_VCO_DAC_IPTAT_MASK)
#define CALIB_LO0_VCO_TST_CP_MASK (0xF0U)
#define CALIB_LO0_VCO_TST_CP_SHIFT (4U)
#define CALIB_LO0_VCO_TST_CP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_TST_CP_SHIFT)) & CALIB_LO0_VCO_TST_CP_MASK)
#define CALIB_LO0_VCO_VTUN_SET_MASK (0x1F00U)
#define CALIB_LO0_VCO_VTUN_SET_SHIFT (8U)
#define CALIB_LO0_VCO_VTUN_SET(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_VTUN_SET_SHIFT)) & CALIB_LO0_VCO_VTUN_SET_MASK)
#define CALIB_LO0_VCO_ACAL_SET_MASK (0xE000U)
#define CALIB_LO0_VCO_ACAL_SET_SHIFT (13U)
#define CALIB_LO0_VCO_ACAL_SET(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_ACAL_SET_SHIFT)) & CALIB_LO0_VCO_ACAL_SET_MASK)
#define CALIB_LO0_VCO_BM_TXFIL_MASK (0x30000U)
#define CALIB_LO0_VCO_BM_TXFIL_SHIFT (16U)
#define CALIB_LO0_VCO_BM_TXFIL(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_BM_TXFIL_SHIFT)) & CALIB_LO0_VCO_BM_TXFIL_MASK)
#define CALIB_LO0_VCO_BM_TXDAC_MASK (0xC0000U)
#define CALIB_LO0_VCO_BM_TXDAC_SHIFT (18U)
#define CALIB_LO0_VCO_BM_TXDAC(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_BM_TXDAC_SHIFT)) & CALIB_LO0_VCO_BM_TXDAC_MASK)
#define CALIB_LO0_VCO_SAMP_EN_MASK (0x800000U)
#define CALIB_LO0_VCO_SAMP_EN_SHIFT (23U)
#define CALIB_LO0_VCO_SAMP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_SAMP_EN_SHIFT)) & CALIB_LO0_VCO_SAMP_EN_MASK)
#define CALIB_LO0_VCO_CAP_HALF_EN_MASK (0x1000000U)
#define CALIB_LO0_VCO_CAP_HALF_EN_SHIFT (24U)
#define CALIB_LO0_VCO_CAP_HALF_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_CAP_HALF_EN_SHIFT)) & CALIB_LO0_VCO_CAP_HALF_EN_MASK)
#define CALIB_LO0_VCO_SET_VCO_VDD_LOW_MASK (0x2000000U)
#define CALIB_LO0_VCO_SET_VCO_VDD_LOW_SHIFT (25U)
#define CALIB_LO0_VCO_SET_VCO_VDD_LOW(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_SET_VCO_VDD_LOW_SHIFT)) & CALIB_LO0_VCO_SET_VCO_VDD_LOW_MASK)
#define CALIB_LO0_VCO_8OR16M_INV_EN_MASK (0x4000000U)
#define CALIB_LO0_VCO_8OR16M_INV_EN_SHIFT (26U)
#define CALIB_LO0_VCO_8OR16M_INV_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_8OR16M_INV_EN_SHIFT)) & CALIB_LO0_VCO_8OR16M_INV_EN_MASK)
#define CALIB_LO0_VCO_DIV_PD_EN_MASK (0x8000000U)
#define CALIB_LO0_VCO_DIV_PD_EN_SHIFT (27U)
#define CALIB_LO0_VCO_DIV_PD_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_DIV_PD_EN_SHIFT)) & CALIB_LO0_VCO_DIV_PD_EN_MASK)
#define CALIB_LO0_VCO_TXDLY1M_MASK (0x10000000U)
#define CALIB_LO0_VCO_TXDLY1M_SHIFT (28U)
#define CALIB_LO0_VCO_TXDLY1M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_TXDLY1M_SHIFT)) & CALIB_LO0_VCO_TXDLY1M_MASK)
#define CALIB_LO0_VCO_TXDLY2M_MASK (0x20000000U)
#define CALIB_LO0_VCO_TXDLY2M_SHIFT (29U)
#define CALIB_LO0_VCO_TXDLY2M(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_TXDLY2M_SHIFT)) & CALIB_LO0_VCO_TXDLY2M_MASK)
#define CALIB_LO0_VCO_RX_CK_TST_MASK (0x40000000U)
#define CALIB_LO0_VCO_RX_CK_TST_SHIFT (30U)
#define CALIB_LO0_VCO_RX_CK_TST(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_RX_CK_TST_SHIFT)) & CALIB_LO0_VCO_RX_CK_TST_MASK)
#define CALIB_LO0_VCO_DSM_INT_EN_MASK (0x80000000U)
#define CALIB_LO0_VCO_DSM_INT_EN_SHIFT (31U)
#define CALIB_LO0_VCO_DSM_INT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO0_VCO_DSM_INT_EN_SHIFT)) & CALIB_LO0_VCO_DSM_INT_EN_MASK)
/*! @name LO1 - Reserved */
#define CALIB_LO1_SPEED_UP_TIME_MASK (0x1FU)
#define CALIB_LO1_SPEED_UP_TIME_SHIFT (0U)
#define CALIB_LO1_SPEED_UP_TIME(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO1_SPEED_UP_TIME_SHIFT)) & CALIB_LO1_SPEED_UP_TIME_MASK)
#define CALIB_LO1_SW_LO_SPEED_UP_MASK (0x20U)
#define CALIB_LO1_SW_LO_SPEED_UP_SHIFT (5U)
#define CALIB_LO1_SW_LO_SPEED_UP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO1_SW_LO_SPEED_UP_SHIFT)) & CALIB_LO1_SW_LO_SPEED_UP_MASK)
#define CALIB_LO1_RX_PLLPFD_EN_MASK (0x40U)
#define CALIB_LO1_RX_PLLPFD_EN_SHIFT (6U)
#define CALIB_LO1_RX_PLLPFD_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO1_RX_PLLPFD_EN_SHIFT)) & CALIB_LO1_RX_PLLPFD_EN_MASK)
#define CALIB_LO1_TX_PLLPFD_EN_MASK (0x80U)
#define CALIB_LO1_TX_PLLPFD_EN_SHIFT (7U)
#define CALIB_LO1_TX_PLLPFD_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO1_TX_PLLPFD_EN_SHIFT)) & CALIB_LO1_TX_PLLPFD_EN_MASK)
#define CALIB_LO1_LO_SET_TIME_MASK (0x3F00U)
#define CALIB_LO1_LO_SET_TIME_SHIFT (8U)
#define CALIB_LO1_LO_SET_TIME(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO1_LO_SET_TIME_SHIFT)) & CALIB_LO1_LO_SET_TIME_MASK)
#define CALIB_LO1_MOD_TEST_MASK (0x4000U)
#define CALIB_LO1_MOD_TEST_SHIFT (14U)
#define CALIB_LO1_MOD_TEST(x) (((uint32_t)(((uint32_t)(x)) << CALIB_LO1_MOD_TEST_SHIFT)) & CALIB_LO1_MOD_TEST_MASK)
#define CALIB_LO1_DIV_DIFF_CLK_LO_DIS_MASK (0x8000U)
#define CALIB_LO1_DIV_DIFF_CLK_LO_DIS_SHIFT (15U)
#define CALIB_LO1_DIV_DIFF_CLK_LO_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO1_DIV_DIFF_CLK_LO_DIS_SHIFT)) & CALIB_LO1_DIV_DIFF_CLK_LO_DIS_MASK)
#define CALIB_LO1_TX_VCO_FTC_SET_MASK (0x30000U)
#define CALIB_LO1_TX_VCO_FTC_SET_SHIFT (16U)
#define CALIB_LO1_TX_VCO_FTC_SET(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO1_TX_VCO_FTC_SET_SHIFT)) & CALIB_LO1_TX_VCO_FTC_SET_MASK)
#define CALIB_LO1_RX_VCO_FTC_SET_MASK (0xC0000U)
#define CALIB_LO1_RX_VCO_FTC_SET_SHIFT (18U)
#define CALIB_LO1_RX_VCO_FTC_SET(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO1_RX_VCO_FTC_SET_SHIFT)) & CALIB_LO1_RX_VCO_FTC_SET_MASK)
/*! @name PA_CTRL - Reserved */
#define CALIB_PA_CTRL_PA_ON_DLY_MASK (0x3FU)
#define CALIB_PA_CTRL_PA_ON_DLY_SHIFT (0U)
#define CALIB_PA_CTRL_PA_ON_DLY(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PA_CTRL_PA_ON_DLY_SHIFT)) & CALIB_PA_CTRL_PA_ON_DLY_MASK)
#define CALIB_PA_CTRL_PA_OFF_DLY_MASK (0xF00U)
#define CALIB_PA_CTRL_PA_OFF_DLY_SHIFT (8U)
#define CALIB_PA_CTRL_PA_OFF_DLY(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PA_CTRL_PA_OFF_DLY_SHIFT)) & CALIB_PA_CTRL_PA_OFF_DLY_MASK)
#define CALIB_PA_CTRL_PA_INCREASE_SEL_MASK (0x70000U)
#define CALIB_PA_CTRL_PA_INCREASE_SEL_SHIFT (16U)
#define CALIB_PA_CTRL_PA_INCREASE_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PA_CTRL_PA_INCREASE_SEL_SHIFT)) & CALIB_PA_CTRL_PA_INCREASE_SEL_MASK)
#define CALIB_PA_CTRL_PA_SEL_BIAS_MASK (0x80000U)
#define CALIB_PA_CTRL_PA_SEL_BIAS_SHIFT (19U)
#define CALIB_PA_CTRL_PA_SEL_BIAS(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PA_CTRL_PA_SEL_BIAS_SHIFT)) & CALIB_PA_CTRL_PA_SEL_BIAS_MASK)
#define CALIB_PA_CTRL_PA_BM_CUR_MASK (0x300000U)
#define CALIB_PA_CTRL_PA_BM_CUR_SHIFT (20U)
#define CALIB_PA_CTRL_PA_BM_CUR(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PA_CTRL_PA_BM_CUR_SHIFT)) & CALIB_PA_CTRL_PA_BM_CUR_MASK)
#define CALIB_PA_CTRL_PA_VDUTY_CYCLE_SEL_MASK (0xC00000U)
#define CALIB_PA_CTRL_PA_VDUTY_CYCLE_SEL_SHIFT (22U)
#define CALIB_PA_CTRL_PA_VDUTY_CYCLE_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PA_CTRL_PA_VDUTY_CYCLE_SEL_SHIFT)) & CALIB_PA_CTRL_PA_VDUTY_CYCLE_SEL_MASK)
#define CALIB_PA_CTRL_PA_VCDCG_MASK (0x1000000U)
#define CALIB_PA_CTRL_PA_VCDCG_SHIFT (24U)
#define CALIB_PA_CTRL_PA_VCDCG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_PA_CTRL_PA_VCDCG_SHIFT)) & CALIB_PA_CTRL_PA_VCDCG_MASK)
/*! @name CTRL - Reserved */
#define CALIB_CTRL_RC_TIM_MASK (0x3U)
#define CALIB_CTRL_RC_TIM_SHIFT (0U)
#define CALIB_CTRL_RC_TIM(x) (((uint32_t)(((uint32_t)(x)) << CALIB_CTRL_RC_TIM_SHIFT)) & CALIB_CTRL_RC_TIM_MASK)
#define CALIB_CTRL_VCO_TEST_INT_MASK (0x10U)
#define CALIB_CTRL_VCO_TEST_INT_SHIFT (4U)
#define CALIB_CTRL_VCO_TEST_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CTRL_VCO_TEST_INT_SHIFT)) & CALIB_CTRL_VCO_TEST_INT_MASK)
#define CALIB_CTRL_HOP_CLB_SEL_MASK (0x100U)
#define CALIB_CTRL_HOP_CLB_SEL_SHIFT (8U)
#define CALIB_CTRL_HOP_CLB_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CTRL_HOP_CLB_SEL_SHIFT)) & CALIB_CTRL_HOP_CLB_SEL_MASK)
#define CALIB_CTRL_XTL_PO_TIM_MASK (0x30000U)
#define CALIB_CTRL_XTL_PO_TIM_SHIFT (16U)
#define CALIB_CTRL_XTL_PO_TIM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CTRL_XTL_PO_TIM_SHIFT)) & CALIB_CTRL_XTL_PO_TIM_MASK)
#define CALIB_CTRL_XTL_CAL_TIM_MASK (0xC0000U)
#define CALIB_CTRL_XTL_CAL_TIM_SHIFT (18U)
#define CALIB_CTRL_XTL_CAL_TIM(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CTRL_XTL_CAL_TIM_SHIFT)) & CALIB_CTRL_XTL_CAL_TIM_MASK)
#define CALIB_CTRL_XTL_AMP_DET_PWR_SEL_MASK (0x300000U)
#define CALIB_CTRL_XTL_AMP_DET_PWR_SEL_SHIFT (20U)
#define CALIB_CTRL_XTL_AMP_DET_PWR_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CTRL_XTL_AMP_DET_PWR_SEL_SHIFT)) & CALIB_CTRL_XTL_AMP_DET_PWR_SEL_MASK)
#define CALIB_CTRL_XTL_SWCAL_EN_MASK (0x400000U)
#define CALIB_CTRL_XTL_SWCAL_EN_SHIFT (22U)
#define CALIB_CTRL_XTL_SWCAL_EN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_CTRL_XTL_SWCAL_EN_SHIFT)) & CALIB_CTRL_XTL_SWCAL_EN_MASK)
/*! @name INT_RAW - Reserved */
#define CALIB_INT_RAW_PO_CAL_DONE_INT_MASK (0x1U)
#define CALIB_INT_RAW_PO_CAL_DONE_INT_SHIFT (0U)
#define CALIB_INT_RAW_PO_CAL_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_RAW_PO_CAL_DONE_INT_SHIFT)) & CALIB_INT_RAW_PO_CAL_DONE_INT_MASK)
#define CALIB_INT_RAW_HOP_CAL_DONE_INT_MASK (0x2U)
#define CALIB_INT_RAW_HOP_CAL_DONE_INT_SHIFT (1U)
#define CALIB_INT_RAW_HOP_CAL_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_RAW_HOP_CAL_DONE_INT_SHIFT)) & CALIB_INT_RAW_HOP_CAL_DONE_INT_MASK)
#define CALIB_INT_RAW_OSC_CAL_DONE_INT_MASK (0x4U)
#define CALIB_INT_RAW_OSC_CAL_DONE_INT_SHIFT (2U)
#define CALIB_INT_RAW_OSC_CAL_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_RAW_OSC_CAL_DONE_INT_SHIFT)) & CALIB_INT_RAW_OSC_CAL_DONE_INT_MASK)
#define CALIB_INT_RAW_REF_CAL_DONE_INT_MASK (0x8U)
#define CALIB_INT_RAW_REF_CAL_DONE_INT_SHIFT (3U)
#define CALIB_INT_RAW_REF_CAL_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_RAW_REF_CAL_DONE_INT_SHIFT)) & CALIB_INT_RAW_REF_CAL_DONE_INT_MASK)
#define CALIB_INT_RAW_RCO_CAL_DONE_INT_MASK (0x10U)
#define CALIB_INT_RAW_RCO_CAL_DONE_INT_SHIFT (4U)
#define CALIB_INT_RAW_RCO_CAL_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_RAW_RCO_CAL_DONE_INT_SHIFT)) & CALIB_INT_RAW_RCO_CAL_DONE_INT_MASK)
#define CALIB_INT_RAW_XTL_CAL_DONE_INT_MASK (0x20U)
#define CALIB_INT_RAW_XTL_CAL_DONE_INT_SHIFT (5U)
#define CALIB_INT_RAW_XTL_CAL_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_RAW_XTL_CAL_DONE_INT_SHIFT)) & CALIB_INT_RAW_XTL_CAL_DONE_INT_MASK)
#define CALIB_INT_RAW_PO_ALL_DONE_INT_MASK (0x100U)
#define CALIB_INT_RAW_PO_ALL_DONE_INT_SHIFT (8U)
#define CALIB_INT_RAW_PO_ALL_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_RAW_PO_ALL_DONE_INT_SHIFT)) & CALIB_INT_RAW_PO_ALL_DONE_INT_MASK)
#define CALIB_INT_RAW_CAL_INT_MASK (0x10000U)
#define CALIB_INT_RAW_CAL_INT_SHIFT (16U)
#define CALIB_INT_RAW_CAL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_RAW_CAL_INT_SHIFT)) & CALIB_INT_RAW_CAL_INT_MASK)
/*! @name INTEN - Reserved */
#define CALIB_INTEN_PO_CAL_DONE_INTEN_MASK (0x1U)
#define CALIB_INTEN_PO_CAL_DONE_INTEN_SHIFT (0U)
#define CALIB_INTEN_PO_CAL_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INTEN_PO_CAL_DONE_INTEN_SHIFT)) & CALIB_INTEN_PO_CAL_DONE_INTEN_MASK)
#define CALIB_INTEN_HOP_CAL_DONE_INTEN_MASK (0x2U)
#define CALIB_INTEN_HOP_CAL_DONE_INTEN_SHIFT (1U)
#define CALIB_INTEN_HOP_CAL_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INTEN_HOP_CAL_DONE_INTEN_SHIFT)) & CALIB_INTEN_HOP_CAL_DONE_INTEN_MASK)
#define CALIB_INTEN_OSC_CAL_DONE_INTEN_MASK (0x4U)
#define CALIB_INTEN_OSC_CAL_DONE_INTEN_SHIFT (2U)
#define CALIB_INTEN_OSC_CAL_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INTEN_OSC_CAL_DONE_INTEN_SHIFT)) & CALIB_INTEN_OSC_CAL_DONE_INTEN_MASK)
#define CALIB_INTEN_REF_CAL_DONE_INTEN_MASK (0x8U)
#define CALIB_INTEN_REF_CAL_DONE_INTEN_SHIFT (3U)
#define CALIB_INTEN_REF_CAL_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INTEN_REF_CAL_DONE_INTEN_SHIFT)) & CALIB_INTEN_REF_CAL_DONE_INTEN_MASK)
#define CALIB_INTEN_RCO_CAL_DONE_INTEN_MASK (0x10U)
#define CALIB_INTEN_RCO_CAL_DONE_INTEN_SHIFT (4U)
#define CALIB_INTEN_RCO_CAL_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INTEN_RCO_CAL_DONE_INTEN_SHIFT)) & CALIB_INTEN_RCO_CAL_DONE_INTEN_MASK)
#define CALIB_INTEN_XTL_CAL_DONE_INTEN_MASK (0x20U)
#define CALIB_INTEN_XTL_CAL_DONE_INTEN_SHIFT (5U)
#define CALIB_INTEN_XTL_CAL_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INTEN_XTL_CAL_DONE_INTEN_SHIFT)) & CALIB_INTEN_XTL_CAL_DONE_INTEN_MASK)
#define CALIB_INTEN_PO_ALL_DONE_INTEN_MASK (0x100U)
#define CALIB_INTEN_PO_ALL_DONE_INTEN_SHIFT (8U)
#define CALIB_INTEN_PO_ALL_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INTEN_PO_ALL_DONE_INTEN_SHIFT)) & CALIB_INTEN_PO_ALL_DONE_INTEN_MASK)
/*! @name INT_STAT - Reserved */
#define CALIB_INT_STAT_PO_CAL_DONE_INT_STAT_MASK (0x1U)
#define CALIB_INT_STAT_PO_CAL_DONE_INT_STAT_SHIFT (0U)
#define CALIB_INT_STAT_PO_CAL_DONE_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_STAT_PO_CAL_DONE_INT_STAT_SHIFT)) & \
CALIB_INT_STAT_PO_CAL_DONE_INT_STAT_MASK)
#define CALIB_INT_STAT_HOP_CAL_DONE_INT_STAT_MASK (0x2U)
#define CALIB_INT_STAT_HOP_CAL_DONE_INT_STAT_SHIFT (1U)
#define CALIB_INT_STAT_HOP_CAL_DONE_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_STAT_HOP_CAL_DONE_INT_STAT_SHIFT)) & \
CALIB_INT_STAT_HOP_CAL_DONE_INT_STAT_MASK)
#define CALIB_INT_STAT_OSC_CAL_DONE_INT_STAT_MASK (0x4U)
#define CALIB_INT_STAT_OSC_CAL_DONE_INT_STAT_SHIFT (2U)
#define CALIB_INT_STAT_OSC_CAL_DONE_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_STAT_OSC_CAL_DONE_INT_STAT_SHIFT)) & \
CALIB_INT_STAT_OSC_CAL_DONE_INT_STAT_MASK)
#define CALIB_INT_STAT_REF_CAL_DONE_INT_STAT_MASK (0x8U)
#define CALIB_INT_STAT_REF_CAL_DONE_INT_STAT_SHIFT (3U)
#define CALIB_INT_STAT_REF_CAL_DONE_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_STAT_REF_CAL_DONE_INT_STAT_SHIFT)) & \
CALIB_INT_STAT_REF_CAL_DONE_INT_STAT_MASK)
#define CALIB_INT_STAT_RCO_CAL_DONE_INT_STAT_MASK (0x10U)
#define CALIB_INT_STAT_RCO_CAL_DONE_INT_STAT_SHIFT (4U)
#define CALIB_INT_STAT_RCO_CAL_DONE_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_STAT_RCO_CAL_DONE_INT_STAT_SHIFT)) & \
CALIB_INT_STAT_RCO_CAL_DONE_INT_STAT_MASK)
#define CALIB_INT_STAT_XTL_CAL_DONE_INT_STAT_MASK (0x20U)
#define CALIB_INT_STAT_XTL_CAL_DONE_INT_STAT_SHIFT (5U)
#define CALIB_INT_STAT_XTL_CAL_DONE_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_STAT_XTL_CAL_DONE_INT_STAT_SHIFT)) & \
CALIB_INT_STAT_XTL_CAL_DONE_INT_STAT_MASK)
#define CALIB_INT_STAT_PO_ALL_DONE_INT_STAT_MASK (0x100U)
#define CALIB_INT_STAT_PO_ALL_DONE_INT_STAT_SHIFT (8U)
#define CALIB_INT_STAT_PO_ALL_DONE_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_STAT_PO_ALL_DONE_INT_STAT_SHIFT)) & \
CALIB_INT_STAT_PO_ALL_DONE_INT_STAT_MASK)
#define CALIB_INT_STAT_CAL_INT_STAT_MASK (0x10000U)
#define CALIB_INT_STAT_CAL_INT_STAT_SHIFT (16U)
#define CALIB_INT_STAT_CAL_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_INT_STAT_CAL_INT_STAT_SHIFT)) & CALIB_INT_STAT_CAL_INT_STAT_MASK)
/*! @name TIF - reserved */
#define CALIB_TIF_TEST_CTRL_MASK (0xFU)
#define CALIB_TIF_TEST_CTRL_SHIFT (0U)
#define CALIB_TIF_TEST_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CALIB_TIF_TEST_CTRL_SHIFT)) & CALIB_TIF_TEST_CTRL_MASK)
/*! @name KVCO_MEAN - reserved */
#define CALIB_KVCO_MEAN_KVCO_CNT_MEAN_MASK (0x1FFFFFU)
#define CALIB_KVCO_MEAN_KVCO_CNT_MEAN_SHIFT (0U)
#define CALIB_KVCO_MEAN_KVCO_CNT_MEAN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_KVCO_MEAN_KVCO_CNT_MEAN_SHIFT)) & CALIB_KVCO_MEAN_KVCO_CNT_MEAN_MASK)
/*! @name KVCO_DLT - reserved */
#define CALIB_KVCO_DLT_KVCO_CNT_DLT_MASK (0x1FFU)
#define CALIB_KVCO_DLT_KVCO_CNT_DLT_SHIFT (0U)
#define CALIB_KVCO_DLT_KVCO_CNT_DLT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_KVCO_DLT_KVCO_CNT_DLT_SHIFT)) & CALIB_KVCO_DLT_KVCO_CNT_DLT_MASK)
/*! @name LO_CFG - */
#define CALIB_LO_CFG_LO_INT_CFG_MASK (0x3FU)
#define CALIB_LO_CFG_LO_INT_CFG_SHIFT (0U)
#define CALIB_LO_CFG_LO_INT_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO_CFG_LO_INT_CFG_SHIFT)) & CALIB_LO_CFG_LO_INT_CFG_MASK)
#define CALIB_LO_CFG_LO_FRAC_CFG_MASK (0xFFFFFC0U)
#define CALIB_LO_CFG_LO_FRAC_CFG_SHIFT (6U)
#define CALIB_LO_CFG_LO_FRAC_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO_CFG_LO_FRAC_CFG_SHIFT)) & CALIB_LO_CFG_LO_FRAC_CFG_MASK)
#define CALIB_LO_CFG_LO_SEL_MASK (0x40000000U)
#define CALIB_LO_CFG_LO_SEL_SHIFT (30U)
#define CALIB_LO_CFG_LO_SEL(x) (((uint32_t)(((uint32_t)(x)) << CALIB_LO_CFG_LO_SEL_SHIFT)) & CALIB_LO_CFG_LO_SEL_MASK)
#define CALIB_LO_CFG_LO_CHANGE_MASK (0x80000000U)
#define CALIB_LO_CFG_LO_CHANGE_SHIFT (31U)
#define CALIB_LO_CFG_LO_CHANGE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO_CFG_LO_CHANGE_SHIFT)) & CALIB_LO_CFG_LO_CHANGE_MASK)
/*! @name LO_TABLE - */
#define CALIB_LO_TABLE_LO_INT_TABLE_MASK (0x3FU)
#define CALIB_LO_TABLE_LO_INT_TABLE_SHIFT (0U)
#define CALIB_LO_TABLE_LO_INT_TABLE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO_TABLE_LO_INT_TABLE_SHIFT)) & CALIB_LO_TABLE_LO_INT_TABLE_MASK)
#define CALIB_LO_TABLE_LO_FRAC_TABLE_MASK (0x3FFFFC0U)
#define CALIB_LO_TABLE_LO_FRAC_TABLE_SHIFT (6U)
#define CALIB_LO_TABLE_LO_FRAC_TABLE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO_TABLE_LO_FRAC_TABLE_SHIFT)) & CALIB_LO_TABLE_LO_FRAC_TABLE_MASK)
/*! @name LO_RATIO - */
#define CALIB_LO_RATIO_LO_INT_MASK (0x3FU)
#define CALIB_LO_RATIO_LO_INT_SHIFT (0U)
#define CALIB_LO_RATIO_LO_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO_RATIO_LO_INT_SHIFT)) & CALIB_LO_RATIO_LO_INT_MASK)
#define CALIB_LO_RATIO_LO_FRAC_MASK (0xFFFFFC0U)
#define CALIB_LO_RATIO_LO_FRAC_SHIFT (6U)
#define CALIB_LO_RATIO_LO_FRAC(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_LO_RATIO_LO_FRAC_SHIFT)) & CALIB_LO_RATIO_LO_FRAC_MASK)
/*! @name VCO_MOD_CFG - TRX 2M mode selection signal */
#define CALIB_VCO_MOD_CFG_VCO_MOD_TX_CFG_MASK (0x1U)
#define CALIB_VCO_MOD_CFG_VCO_MOD_TX_CFG_SHIFT (0U)
#define CALIB_VCO_MOD_CFG_VCO_MOD_TX_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCO_MOD_CFG_VCO_MOD_TX_CFG_SHIFT)) & CALIB_VCO_MOD_CFG_VCO_MOD_TX_CFG_MASK)
#define CALIB_VCO_MOD_CFG_VCO_MOD_TX_SEL_MASK (0x2U)
#define CALIB_VCO_MOD_CFG_VCO_MOD_TX_SEL_SHIFT (1U)
#define CALIB_VCO_MOD_CFG_VCO_MOD_TX_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCO_MOD_CFG_VCO_MOD_TX_SEL_SHIFT)) & CALIB_VCO_MOD_CFG_VCO_MOD_TX_SEL_MASK)
#define CALIB_VCO_MOD_CFG_TRX2M_MODE_CFG_MASK (0x4U)
#define CALIB_VCO_MOD_CFG_TRX2M_MODE_CFG_SHIFT (2U)
#define CALIB_VCO_MOD_CFG_TRX2M_MODE_CFG(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCO_MOD_CFG_TRX2M_MODE_CFG_SHIFT)) & CALIB_VCO_MOD_CFG_TRX2M_MODE_CFG_MASK)
#define CALIB_VCO_MOD_CFG_TRX2M_MODE_SEL_MASK (0x8U)
#define CALIB_VCO_MOD_CFG_TRX2M_MODE_SEL_SHIFT (3U)
#define CALIB_VCO_MOD_CFG_TRX2M_MODE_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCO_MOD_CFG_TRX2M_MODE_SEL_SHIFT)) & CALIB_VCO_MOD_CFG_TRX2M_MODE_SEL_MASK)
#define CALIB_VCO_MOD_CFG_IMR_MASK (0x10U)
#define CALIB_VCO_MOD_CFG_IMR_SHIFT (4U)
#define CALIB_VCO_MOD_CFG_IMR(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCO_MOD_CFG_IMR_SHIFT)) & CALIB_VCO_MOD_CFG_IMR_MASK)
/*! @name VCO_MOD_STAT - */
#define CALIB_VCO_MOD_STAT_VCO_MOD_TX_MASK (0x1U)
#define CALIB_VCO_MOD_STAT_VCO_MOD_TX_SHIFT (0U)
#define CALIB_VCO_MOD_STAT_VCO_MOD_TX(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCO_MOD_STAT_VCO_MOD_TX_SHIFT)) & CALIB_VCO_MOD_STAT_VCO_MOD_TX_MASK)
#define CALIB_VCO_MOD_STAT_TRX2M_MODE_MASK (0x4U)
#define CALIB_VCO_MOD_STAT_TRX2M_MODE_SHIFT (2U)
#define CALIB_VCO_MOD_STAT_TRX2M_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCO_MOD_STAT_TRX2M_MODE_SHIFT)) & CALIB_VCO_MOD_STAT_TRX2M_MODE_MASK)
/*! @name CH_IDX - */
#define CALIB_CH_IDX_CH_IDX_MASK (0xFFU)
#define CALIB_CH_IDX_CH_IDX_SHIFT (0U)
#define CALIB_CH_IDX_CH_IDX(x) (((uint32_t)(((uint32_t)(x)) << CALIB_CH_IDX_CH_IDX_SHIFT)) & CALIB_CH_IDX_CH_IDX_MASK)
/*! @name VCOF_CNT_UP - reserved */
#define CALIB_VCOF_CNT_UP_TX_VCOF_CNT_UP_MASK (0xFFU)
#define CALIB_VCOF_CNT_UP_TX_VCOF_CNT_UP_SHIFT (0U)
#define CALIB_VCOF_CNT_UP_TX_VCOF_CNT_UP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_CNT_UP_TX_VCOF_CNT_UP_SHIFT)) & CALIB_VCOF_CNT_UP_TX_VCOF_CNT_UP_MASK)
#define CALIB_VCOF_CNT_UP_RX_VCOF_CNT_UP_MASK (0xFF0000U)
#define CALIB_VCOF_CNT_UP_RX_VCOF_CNT_UP_SHIFT (16U)
#define CALIB_VCOF_CNT_UP_RX_VCOF_CNT_UP(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_CNT_UP_RX_VCOF_CNT_UP_SHIFT)) & CALIB_VCOF_CNT_UP_RX_VCOF_CNT_UP_MASK)
/*! @name VCOF_CNT_DN - reserved */
#define CALIB_VCOF_CNT_DN_TX_VCOF_CNT_DN_MASK (0xFFU)
#define CALIB_VCOF_CNT_DN_TX_VCOF_CNT_DN_SHIFT (0U)
#define CALIB_VCOF_CNT_DN_TX_VCOF_CNT_DN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_CNT_DN_TX_VCOF_CNT_DN_SHIFT)) & CALIB_VCOF_CNT_DN_TX_VCOF_CNT_DN_MASK)
#define CALIB_VCOF_CNT_DN_RX_VCOF_CNT_DN_MASK (0xFF0000U)
#define CALIB_VCOF_CNT_DN_RX_VCOF_CNT_DN_SHIFT (16U)
#define CALIB_VCOF_CNT_DN_RX_VCOF_CNT_DN(x) \
(((uint32_t)(((uint32_t)(x)) << CALIB_VCOF_CNT_DN_RX_VCOF_CNT_DN_SHIFT)) & CALIB_VCOF_CNT_DN_RX_VCOF_CNT_DN_MASK)
/*!
* @}
*/ /* end of group CALIB_Register_Masks */
/* CALIB - Peripheral instance base addresses */
/** Peripheral CALIB base address */
#define CALIB_BASE (0x4000F000u)
/** Peripheral CALIB base pointer */
#define CALIB ((CALIB_Type *)CALIB_BASE)
/** Array initializer of CALIB peripheral base addresses */
#define CALIB_BASE_ADDRS \
{ \
CALIB_BASE \
}
/** Array initializer of CALIB peripheral base pointers */
#define CALIB_BASE_PTRS \
{ \
CALIB \
}
/** Interrupt vectors for the CALIB peripheral type */
#define CALIB_IRQS \
{ \
CALIB_IRQn \
}
/*!
* @}
*/ /* end of group CALIB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
* @{
*/
/** CRC - Register Layout Typedef */
typedef struct
{
__IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
__IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
union { /* offset: 0x8 */
__I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
__O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
};
} CRC_Type;
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/*! @name MODE - CRC mode register */
#define CRC_MODE_CRC_POLY_MASK (0x3U)
#define CRC_MODE_CRC_POLY_SHIFT (0U)
#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
#define CRC_MODE_CMPL_WR_MASK (0x8U)
#define CRC_MODE_CMPL_WR_SHIFT (3U)
#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
#define CRC_MODE_BIT_RVS_SUM(x) \
(((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
#define CRC_MODE_CMPL_SUM_MASK (0x20U)
#define CRC_MODE_CMPL_SUM_SHIFT (5U)
#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
/*! @name SEED - CRC seed register */
#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
#define CRC_SEED_CRC_SEED_SHIFT (0U)
#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
/*! @name SUM - CRC checksum register */
#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
#define CRC_SUM_CRC_SUM_SHIFT (0U)
#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
/*! @name WR_DATA - CRC data register */
#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
#define CRC_WR_DATA_CRC_WR_DATA(x) \
(((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
/*!
* @}
*/ /* end of group CRC_Register_Masks */
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC_ENGINE base address */
#define CRC_ENGINE_BASE (0x4008E000u)
/** Peripheral CRC_ENGINE base pointer */
#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS \
{ \
CRC_ENGINE_BASE \
}
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS \
{ \
CRC_ENGINE \
}
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CS_Peripheral_Access_Layer CS Peripheral Access Layer
* @{
*/
/** CS - Register Layout Typedef */
typedef struct
{
__IO uint32_t CTRL0; /**< CapSense control register 0, offset: 0x0 */
__IO uint32_t CTRL1; /**< CapSense control register 1, offset: 0x4 */
__IO uint32_t INT; /**< Interrupt status register, offset: 0x8 */
__IO uint32_t INTEN; /**< Interrupt mask register, offset: 0xC */
__I uint32_t DATA; /**< Output data register, offset: 0x10 */
__IO uint32_t LP_CTRL; /**< Control register for low power mode, offset: 0x14 */
__I uint32_t LP_INT; /**< Low power interrupt register, offset: 0x18 */
__IO uint32_t LP_INTEN; /**< low power interrupt enable register, offset: 0x1C */
__IO uint32_t IDLE_PERIOD; /**< Idle preiod number register, offset: 0x20 */
} CS_Type;
/* ----------------------------------------------------------------------------
-- CS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CS_Register_Masks CS Register Masks
* @{
*/
/*! @name CTRL0 - CapSense control register 0 */
#define CS_CTRL0_ENABLE_MASK (0x1U)
#define CS_CTRL0_ENABLE_SHIFT (0U)
#define CS_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CS_CTRL0_ENABLE_SHIFT)) & CS_CTRL0_ENABLE_MASK)
#define CS_CTRL0_SRST_MASK (0x2U)
#define CS_CTRL0_SRST_SHIFT (1U)
#define CS_CTRL0_SRST(x) (((uint32_t)(((uint32_t)(x)) << CS_CTRL0_SRST_SHIFT)) & CS_CTRL0_SRST_MASK)
#define CS_CTRL0_OSC_FREQ_MASK (0xFCU)
#define CS_CTRL0_OSC_FREQ_SHIFT (2U)
#define CS_CTRL0_OSC_FREQ(x) (((uint32_t)(((uint32_t)(x)) << CS_CTRL0_OSC_FREQ_SHIFT)) & CS_CTRL0_OSC_FREQ_MASK)
#define CS_CTRL0_CLK_DIV_MASK (0x1FF0000U)
#define CS_CTRL0_CLK_DIV_SHIFT (16U)
#define CS_CTRL0_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << CS_CTRL0_CLK_DIV_SHIFT)) & CS_CTRL0_CLK_DIV_MASK)
/*! @name CTRL1 - CapSense control register 1 */
#define CS_CTRL1_PERIOD_MASK (0xFFFFU)
#define CS_CTRL1_PERIOD_SHIFT (0U)
#define CS_CTRL1_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << CS_CTRL1_PERIOD_SHIFT)) & CS_CTRL1_PERIOD_MASK)
#define CS_CTRL1_CH_MASK (0xFF0000U)
#define CS_CTRL1_CH_SHIFT (16U)
#define CS_CTRL1_CH(x) (((uint32_t)(((uint32_t)(x)) << CS_CTRL1_CH_SHIFT)) & CS_CTRL1_CH_MASK)
/*! @name INT - Interrupt status register */
#define CS_INT_FIFO_NOTEMPTY_INT_MASK (0x1U)
#define CS_INT_FIFO_NOTEMPTY_INT_SHIFT (0U)
#define CS_INT_FIFO_NOTEMPTY_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CS_INT_FIFO_NOTEMPTY_INT_SHIFT)) & CS_INT_FIFO_NOTEMPTY_INT_MASK)
#define CS_INT_FIFO_HFULL_INT_MASK (0x2U)
#define CS_INT_FIFO_HFULL_INT_SHIFT (1U)
#define CS_INT_FIFO_HFULL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CS_INT_FIFO_HFULL_INT_SHIFT)) & CS_INT_FIFO_HFULL_INT_MASK)
#define CS_INT_FIFO_FULL_INT_MASK (0x4U)
#define CS_INT_FIFO_FULL_INT_SHIFT (2U)
#define CS_INT_FIFO_FULL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << CS_INT_FIFO_FULL_INT_SHIFT)) & CS_INT_FIFO_FULL_INT_MASK)
#define CS_INT_SCAN_INT_MASK (0x8U)
#define CS_INT_SCAN_INT_SHIFT (3U)
#define CS_INT_SCAN_INT(x) (((uint32_t)(((uint32_t)(x)) << CS_INT_SCAN_INT_SHIFT)) & CS_INT_SCAN_INT_MASK)
/*! @name INTEN - Interrupt mask register */
#define CS_INTEN_FIFO_NOTEMPTY_INTEN_MASK (0x1U)
#define CS_INTEN_FIFO_NOTEMPTY_INTEN_SHIFT (0U)
#define CS_INTEN_FIFO_NOTEMPTY_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CS_INTEN_FIFO_NOTEMPTY_INTEN_SHIFT)) & CS_INTEN_FIFO_NOTEMPTY_INTEN_MASK)
#define CS_INTEN_FIFO_HFULL_INTEN_MASK (0x2U)
#define CS_INTEN_FIFO_HFULL_INTEN_SHIFT (1U)
#define CS_INTEN_FIFO_HFULL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CS_INTEN_FIFO_HFULL_INTEN_SHIFT)) & CS_INTEN_FIFO_HFULL_INTEN_MASK)
#define CS_INTEN_FIFO_FULL_INTEN_MASK (0x4U)
#define CS_INTEN_FIFO_FULL_INTEN_SHIFT (2U)
#define CS_INTEN_FIFO_FULL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CS_INTEN_FIFO_FULL_INTEN_SHIFT)) & CS_INTEN_FIFO_FULL_INTEN_MASK)
#define CS_INTEN_SCAN_INTEN_MASK (0x8U)
#define CS_INTEN_SCAN_INTEN_SHIFT (3U)
#define CS_INTEN_SCAN_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CS_INTEN_SCAN_INTEN_SHIFT)) & CS_INTEN_SCAN_INTEN_MASK)
/*! @name DATA - Output data register */
#define CS_DATA_DATA_MASK (0x7FFFFU)
#define CS_DATA_DATA_SHIFT (0U)
#define CS_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << CS_DATA_DATA_SHIFT)) & CS_DATA_DATA_MASK)
/*! @name LP_CTRL - Control register for low power mode */
#define CS_LP_CTRL_DEBONCE_NUM_MASK (0xFU)
#define CS_LP_CTRL_DEBONCE_NUM_SHIFT (0U)
#define CS_LP_CTRL_DEBONCE_NUM(x) \
(((uint32_t)(((uint32_t)(x)) << CS_LP_CTRL_DEBONCE_NUM_SHIFT)) & CS_LP_CTRL_DEBONCE_NUM_MASK)
#define CS_LP_CTRL_LP_EN_MASK (0x10U)
#define CS_LP_CTRL_LP_EN_SHIFT (4U)
#define CS_LP_CTRL_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << CS_LP_CTRL_LP_EN_SHIFT)) & CS_LP_CTRL_LP_EN_MASK)
#define CS_LP_CTRL_LP_CH_MASK (0xE0U)
#define CS_LP_CTRL_LP_CH_SHIFT (5U)
#define CS_LP_CTRL_LP_CH(x) (((uint32_t)(((uint32_t)(x)) << CS_LP_CTRL_LP_CH_SHIFT)) & CS_LP_CTRL_LP_CH_MASK)
#define CS_LP_CTRL_THR_MASK (0xFFFF0000U)
#define CS_LP_CTRL_THR_SHIFT (16U)
#define CS_LP_CTRL_THR(x) (((uint32_t)(((uint32_t)(x)) << CS_LP_CTRL_THR_SHIFT)) & CS_LP_CTRL_THR_MASK)
/*! @name LP_INT - Low power interrupt register */
#define CS_LP_INT_LP_INT_MASK (0x1U)
#define CS_LP_INT_LP_INT_SHIFT (0U)
#define CS_LP_INT_LP_INT(x) (((uint32_t)(((uint32_t)(x)) << CS_LP_INT_LP_INT_SHIFT)) & CS_LP_INT_LP_INT_MASK)
/*! @name LP_INTEN - low power interrupt enable register */
#define CS_LP_INTEN_LP_INTEN_MASK (0x1U)
#define CS_LP_INTEN_LP_INTEN_SHIFT (0U)
#define CS_LP_INTEN_LP_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << CS_LP_INTEN_LP_INTEN_SHIFT)) & CS_LP_INTEN_LP_INTEN_MASK)
/*! @name IDLE_PERIOD - Idle preiod number register */
#define CS_IDLE_PERIOD_IDLE_PERIOD_MASK (0xFFFFU)
#define CS_IDLE_PERIOD_IDLE_PERIOD_SHIFT (0U)
#define CS_IDLE_PERIOD_IDLE_PERIOD(x) \
(((uint32_t)(((uint32_t)(x)) << CS_IDLE_PERIOD_IDLE_PERIOD_SHIFT)) & CS_IDLE_PERIOD_IDLE_PERIOD_MASK)
/*!
* @}
*/ /* end of group CS_Register_Masks */
/* CS - Peripheral instance base addresses */
/** Peripheral CS base address */
#define CS_BASE (0x40007800u)
/** Peripheral CS base pointer */
#define CS ((CS_Type *)CS_BASE)
/** Array initializer of CS peripheral base addresses */
#define CS_BASE_ADDRS \
{ \
CS_BASE \
}
/** Array initializer of CS peripheral base pointers */
#define CS_BASE_PTRS \
{ \
CS \
}
/** Interrupt vectors for the CS peripheral type */
#define CS_IRQS \
{ \
CS_IRQn, CS_WAKEUP_IRQn \
}
/*!
* @}
*/ /* end of group CS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CTIMER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
* @{
*/
/** CTIMER - Register Layout Typedef */
typedef struct
{
__IO uint32_t
IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of
eight possible interrupt sources are pending., offset: 0x0 */
__IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer
Counter can be disabled or reset through the TCR., offset: 0x4 */
__IO uint32_t
TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is
controlled through the TCR., offset: 0x8 */
__IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock
increments the TC and clears the PC., offset: 0xC */
__IO uint32_t
PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the
value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and
controllable through the bus interface., offset: 0x10 */
__IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the
TC is reset when a Match occurs., offset: 0x14 */
__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and
PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array
step: 0x4 */
__IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to
load the Capture Registers and whether or not an interrupt is generated when a capture takes
place., offset: 0x28 */
__I uint32_t CR[3]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn.
input., array offset: 0x2C, array step: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins.,
offset: 0x3C */
uint8_t RESERVED_1[48];
__IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter
mode selects the signal and edge(s) for counting., offset: 0x70 */
__IO uint32_t
PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
} CTIMER_Type;
/* ----------------------------------------------------------------------------
-- CTIMER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CTIMER_Register_Masks CTIMER Register Masks
* @{
*/
/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of
* eight possible interrupt sources are pending. */
#define CTIMER_IR_MR0INT_MASK (0x1U)
#define CTIMER_IR_MR0INT_SHIFT (0U)
#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
#define CTIMER_IR_MR1INT_MASK (0x2U)
#define CTIMER_IR_MR1INT_SHIFT (1U)
#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
#define CTIMER_IR_MR2INT_MASK (0x4U)
#define CTIMER_IR_MR2INT_SHIFT (2U)
#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
#define CTIMER_IR_MR3INT_MASK (0x8U)
#define CTIMER_IR_MR3INT_SHIFT (3U)
#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
#define CTIMER_IR_CR0INT_MASK (0x10U)
#define CTIMER_IR_CR0INT_SHIFT (4U)
#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
#define CTIMER_IR_CR1INT_MASK (0x20U)
#define CTIMER_IR_CR1INT_SHIFT (5U)
#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
#define CTIMER_IR_CR2INT_MASK (0x40U)
#define CTIMER_IR_CR2INT_SHIFT (6U)
#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
#define CTIMER_IR_CR3INT_MASK (0x80U)
#define CTIMER_IR_CR3INT_SHIFT (7U)
#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be
* disabled or reset through the TCR. */
#define CTIMER_TCR_CEN_MASK (0x1U)
#define CTIMER_TCR_CEN_SHIFT (0U)
#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
#define CTIMER_TCR_CRST_MASK (0x2U)
#define CTIMER_TCR_CRST_SHIFT (1U)
#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled
* through the TCR. */
#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
#define CTIMER_TC_TCVAL_SHIFT (0U)
#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the
* TC and clears the PC. */
#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
#define CTIMER_PR_PRVAL_SHIFT (0U)
#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the
* value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through
* the bus interface. */
#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
#define CTIMER_PC_PCVAL_SHIFT (0U)
#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset
* when a Match occurs. */
#define CTIMER_MCR_MR0I_MASK (0x1U)
#define CTIMER_MCR_MR0I_SHIFT (0U)
#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
#define CTIMER_MCR_MR0R_MASK (0x2U)
#define CTIMER_MCR_MR0R_SHIFT (1U)
#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
#define CTIMER_MCR_MR0S_MASK (0x4U)
#define CTIMER_MCR_MR0S_SHIFT (2U)
#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
#define CTIMER_MCR_MR1I_MASK (0x8U)
#define CTIMER_MCR_MR1I_SHIFT (3U)
#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
#define CTIMER_MCR_MR1R_MASK (0x10U)
#define CTIMER_MCR_MR1R_SHIFT (4U)
#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
#define CTIMER_MCR_MR1S_MASK (0x20U)
#define CTIMER_MCR_MR1S_SHIFT (5U)
#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
#define CTIMER_MCR_MR2I_MASK (0x40U)
#define CTIMER_MCR_MR2I_SHIFT (6U)
#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
#define CTIMER_MCR_MR2R_MASK (0x80U)
#define CTIMER_MCR_MR2R_SHIFT (7U)
#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
#define CTIMER_MCR_MR2S_MASK (0x100U)
#define CTIMER_MCR_MR2S_SHIFT (8U)
#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
#define CTIMER_MCR_MR3I_MASK (0x200U)
#define CTIMER_MCR_MR3I_SHIFT (9U)
#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
#define CTIMER_MCR_MR3R_MASK (0x400U)
#define CTIMER_MCR_MR3R_SHIFT (10U)
#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
#define CTIMER_MCR_MR3S_MASK (0x800U)
#define CTIMER_MCR_MR3S_SHIFT (11U)
#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or
* generate an interrupt every time MR matches the TC. */
#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
#define CTIMER_MR_MATCH_SHIFT (0U)
#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
/* The count of CTIMER_MR */
#define CTIMER_MR_COUNT (4U)
/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the
* Capture Registers and whether or not an interrupt is generated when a capture takes place. */
#define CTIMER_CCR_CAP0RE_MASK (0x1U)
#define CTIMER_CCR_CAP0RE_SHIFT (0U)
#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
#define CTIMER_CCR_CAP0FE_MASK (0x2U)
#define CTIMER_CCR_CAP0FE_SHIFT (1U)
#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
#define CTIMER_CCR_CAP0I_MASK (0x4U)
#define CTIMER_CCR_CAP0I_SHIFT (2U)
#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
#define CTIMER_CCR_CAP1RE_MASK (0x8U)
#define CTIMER_CCR_CAP1RE_SHIFT (3U)
#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
#define CTIMER_CCR_CAP1FE_MASK (0x10U)
#define CTIMER_CCR_CAP1FE_SHIFT (4U)
#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
#define CTIMER_CCR_CAP1I_MASK (0x20U)
#define CTIMER_CCR_CAP1I_SHIFT (5U)
#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
#define CTIMER_CCR_CAP2RE_MASK (0x40U)
#define CTIMER_CCR_CAP2RE_SHIFT (6U)
#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
#define CTIMER_CCR_CAP2FE_MASK (0x80U)
#define CTIMER_CCR_CAP2FE_SHIFT (7U)
#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
#define CTIMER_CCR_CAP2I_MASK (0x100U)
#define CTIMER_CCR_CAP2I_SHIFT (8U)
#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
#define CTIMER_CCR_CAP3RE_MASK (0x200U)
#define CTIMER_CCR_CAP3RE_SHIFT (9U)
#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
#define CTIMER_CCR_CAP3FE_MASK (0x400U)
#define CTIMER_CCR_CAP3FE_SHIFT (10U)
#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
#define CTIMER_CCR_CAP3I_MASK (0x800U)
#define CTIMER_CCR_CAP3I_SHIFT (11U)
#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
#define CTIMER_CR_CAP_SHIFT (0U)
#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
/* The count of CTIMER_CR */
#define CTIMER_CR_COUNT (3U)
/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
#define CTIMER_EMR_EM0_MASK (0x1U)
#define CTIMER_EMR_EM0_SHIFT (0U)
#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
#define CTIMER_EMR_EM1_MASK (0x2U)
#define CTIMER_EMR_EM1_SHIFT (1U)
#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
#define CTIMER_EMR_EM2_MASK (0x4U)
#define CTIMER_EMR_EM2_SHIFT (2U)
#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
#define CTIMER_EMR_EM3_MASK (0x8U)
#define CTIMER_EMR_EM3_SHIFT (3U)
#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
#define CTIMER_EMR_EMC0_MASK (0x30U)
#define CTIMER_EMR_EMC0_SHIFT (4U)
#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
#define CTIMER_EMR_EMC1_MASK (0xC0U)
#define CTIMER_EMR_EMC1_SHIFT (6U)
#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
#define CTIMER_EMR_EMC2_MASK (0x300U)
#define CTIMER_EMR_EMC2_SHIFT (8U)
#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
#define CTIMER_EMR_EMC3_MASK (0xC00U)
#define CTIMER_EMR_EMC3_SHIFT (10U)
#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects
* the signal and edge(s) for counting. */
#define CTIMER_CTCR_CTMODE_MASK (0x3U)
#define CTIMER_CTCR_CTMODE_SHIFT (0U)
#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
#define CTIMER_CTCR_CINSEL_MASK (0xCU)
#define CTIMER_CTCR_CINSEL_SHIFT (2U)
#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
#define CTIMER_CTCR_ENCC_MASK (0x10U)
#define CTIMER_CTCR_ENCC_SHIFT (4U)
#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
#define CTIMER_CTCR_SELCC_MASK (0xE0U)
#define CTIMER_CTCR_SELCC_SHIFT (5U)
#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
/*!
* @}
*/ /* end of group CTIMER_Register_Masks */
/* CTIMER - Peripheral instance base addresses */
/** Peripheral CTIMER0 base address */
#define CTIMER0_BASE (0x40002000u)
/** Peripheral CTIMER0 base pointer */
#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
/** Peripheral CTIMER1 base address */
#define CTIMER1_BASE (0x40003000u)
/** Peripheral CTIMER1 base pointer */
#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
/** Peripheral CTIMER2 base address */
#define CTIMER2_BASE (0x40004000u)
/** Peripheral CTIMER2 base pointer */
#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
/** Peripheral CTIMER3 base address */
#define CTIMER3_BASE (0x40005000u)
/** Peripheral CTIMER3 base pointer */
#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
/** Array initializer of CTIMER peripheral base addresses */
#define CTIMER_BASE_ADDRS \
{ \
CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE \
}
/** Array initializer of CTIMER peripheral base pointers */
#define CTIMER_BASE_PTRS \
{ \
CTIMER0, CTIMER1, CTIMER2, CTIMER3 \
}
/** Interrupt vectors for the CTIMER peripheral type */
#define CTIMER_IRQS \
{ \
CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn \
}
/*!
* @}
*/ /* end of group CTIMER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DAC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
* @{
*/
/** DAC - Register Layout Typedef */
typedef struct
{
__IO uint32_t ANA_CFG; /**< reserved, offset: 0x0 */
__IO uint32_t CTRL; /**< DAC clock invert, offset: 0x4 */
__IO uint32_t SIN_CFG0; /**< sin amplitude, offset: 0x8 */
__IO uint32_t SIN_CFG1; /**< reserved, offset: 0xC */
__IO uint32_t GAIN_CTRL; /**< reserved, offset: 0x10 */
__IO uint32_t CLR_TRG; /**< Reserved, offset: 0x14 */
__O uint32_t DIN; /**< DAC data input, offset: 0x18 */
__IO uint32_t INT; /**< Reserved, offset: 0x1C */
__IO uint32_t INTEN; /**< Reserved, offset: 0x20 */
__I uint32_t INT_STAT; /**< Reserved, offset: 0x24 */
__I uint32_t STATUS; /**< Reserved, offset: 0x28 */
} DAC_Type;
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/*! @name ANA_CFG - reserved */
#define DAC_ANA_CFG_FILTER_BM_MASK (0x7U)
#define DAC_ANA_CFG_FILTER_BM_SHIFT (0U)
#define DAC_ANA_CFG_FILTER_BM(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_ANA_CFG_FILTER_BM_SHIFT)) & DAC_ANA_CFG_FILTER_BM_MASK)
#define DAC_ANA_CFG_DAC_AMP_MASK (0x70U)
#define DAC_ANA_CFG_DAC_AMP_SHIFT (4U)
#define DAC_ANA_CFG_DAC_AMP(x) (((uint32_t)(((uint32_t)(x)) << DAC_ANA_CFG_DAC_AMP_SHIFT)) & DAC_ANA_CFG_DAC_AMP_MASK)
#define DAC_ANA_CFG_FILTER_BW_MASK (0x300U)
#define DAC_ANA_CFG_FILTER_BW_SHIFT (8U)
#define DAC_ANA_CFG_FILTER_BW(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_ANA_CFG_FILTER_BW_SHIFT)) & DAC_ANA_CFG_FILTER_BW_MASK)
#define DAC_ANA_CFG_FILTER_150K_EN_MASK (0x1000U)
#define DAC_ANA_CFG_FILTER_150K_EN_SHIFT (12U)
#define DAC_ANA_CFG_FILTER_150K_EN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_ANA_CFG_FILTER_150K_EN_SHIFT)) & DAC_ANA_CFG_FILTER_150K_EN_MASK)
#define DAC_ANA_CFG_VCM_MASK (0xF0000U)
#define DAC_ANA_CFG_VCM_SHIFT (16U)
#define DAC_ANA_CFG_VCM(x) (((uint32_t)(((uint32_t)(x)) << DAC_ANA_CFG_VCM_SHIFT)) & DAC_ANA_CFG_VCM_MASK)
/*! @name CTRL - DAC clock invert */
#define DAC_CTRL_ENABLE_MASK (0x1U)
#define DAC_CTRL_ENABLE_SHIFT (0U)
#define DAC_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_ENABLE_SHIFT)) & DAC_CTRL_ENABLE_MASK)
#define DAC_CTRL_SIN_EN_MASK (0x2U)
#define DAC_CTRL_SIN_EN_SHIFT (1U)
#define DAC_CTRL_SIN_EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_SIN_EN_SHIFT)) & DAC_CTRL_SIN_EN_MASK)
#define DAC_CTRL_MOD_EN_MASK (0x4U)
#define DAC_CTRL_MOD_EN_SHIFT (2U)
#define DAC_CTRL_MOD_EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_MOD_EN_SHIFT)) & DAC_CTRL_MOD_EN_MASK)
#define DAC_CTRL_MOD_WD_MASK (0x8U)
#define DAC_CTRL_MOD_WD_SHIFT (3U)
#define DAC_CTRL_MOD_WD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_MOD_WD_SHIFT)) & DAC_CTRL_MOD_WD_MASK)
#define DAC_CTRL_SMPL_RATE_MASK (0x70U)
#define DAC_CTRL_SMPL_RATE_SHIFT (4U)
#define DAC_CTRL_SMPL_RATE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_SMPL_RATE_SHIFT)) & DAC_CTRL_SMPL_RATE_MASK)
#define DAC_CTRL_SGN_INV_MASK (0x80U)
#define DAC_CTRL_SGN_INV_SHIFT (7U)
#define DAC_CTRL_SGN_INV(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_SGN_INV_SHIFT)) & DAC_CTRL_SGN_INV_MASK)
#define DAC_CTRL_BUF_IN_ALGN_MASK (0x100U)
#define DAC_CTRL_BUF_IN_ALGN_SHIFT (8U)
#define DAC_CTRL_BUF_IN_ALGN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_CTRL_BUF_IN_ALGN_SHIFT)) & DAC_CTRL_BUF_IN_ALGN_MASK)
#define DAC_CTRL_BUF_OUT_ALGN_MASK (0x200U)
#define DAC_CTRL_BUF_OUT_ALGN_SHIFT (9U)
#define DAC_CTRL_BUF_OUT_ALGN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_CTRL_BUF_OUT_ALGN_SHIFT)) & DAC_CTRL_BUF_OUT_ALGN_MASK)
#define DAC_CTRL_TRG_MODE_MASK (0x400U)
#define DAC_CTRL_TRG_MODE_SHIFT (10U)
#define DAC_CTRL_TRG_MODE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_TRG_MODE_SHIFT)) & DAC_CTRL_TRG_MODE_MASK)
#define DAC_CTRL_TRG_EDGE_MASK (0x1800U)
#define DAC_CTRL_TRG_EDGE_SHIFT (11U)
#define DAC_CTRL_TRG_EDGE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_TRG_EDGE_SHIFT)) & DAC_CTRL_TRG_EDGE_MASK)
#define DAC_CTRL_TRG_SEL_MASK (0x3F0000U)
#define DAC_CTRL_TRG_SEL_SHIFT (16U)
#define DAC_CTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_TRG_SEL_SHIFT)) & DAC_CTRL_TRG_SEL_MASK)
#define DAC_CTRL_CLK_DIV_MASK (0x7F000000U)
#define DAC_CTRL_CLK_DIV_SHIFT (24U)
#define DAC_CTRL_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_CLK_DIV_SHIFT)) & DAC_CTRL_CLK_DIV_MASK)
#define DAC_CTRL_CLK_INV_MASK (0x80000000U)
#define DAC_CTRL_CLK_INV_SHIFT (31U)
#define DAC_CTRL_CLK_INV(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_CLK_INV_SHIFT)) & DAC_CTRL_CLK_INV_MASK)
/*! @name SIN_CFG0 - sin amplitude */
#define DAC_SIN_CFG0_SIN_FREQ_MASK (0xFFFFU)
#define DAC_SIN_CFG0_SIN_FREQ_SHIFT (0U)
#define DAC_SIN_CFG0_SIN_FREQ(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_SIN_CFG0_SIN_FREQ_SHIFT)) & DAC_SIN_CFG0_SIN_FREQ_MASK)
#define DAC_SIN_CFG0_SIN_AMP_MASK (0xFFFF0000U)
#define DAC_SIN_CFG0_SIN_AMP_SHIFT (16U)
#define DAC_SIN_CFG0_SIN_AMP(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_SIN_CFG0_SIN_AMP_SHIFT)) & DAC_SIN_CFG0_SIN_AMP_MASK)
/*! @name SIN_CFG1 - reserved */
#define DAC_SIN_CFG1_SIN_DC_MASK (0xFFFFFU)
#define DAC_SIN_CFG1_SIN_DC_SHIFT (0U)
#define DAC_SIN_CFG1_SIN_DC(x) (((uint32_t)(((uint32_t)(x)) << DAC_SIN_CFG1_SIN_DC_SHIFT)) & DAC_SIN_CFG1_SIN_DC_MASK)
/*! @name GAIN_CTRL - reserved */
#define DAC_GAIN_CTRL_GAIN_CTRL_MASK (0xFFU)
#define DAC_GAIN_CTRL_GAIN_CTRL_SHIFT (0U)
#define DAC_GAIN_CTRL_GAIN_CTRL(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_GAIN_CTRL_GAIN_CTRL_SHIFT)) & DAC_GAIN_CTRL_GAIN_CTRL_MASK)
/*! @name CLR_TRG - Reserved */
#define DAC_CLR_TRG_BUF_CLR_MASK (0x1U)
#define DAC_CLR_TRG_BUF_CLR_SHIFT (0U)
#define DAC_CLR_TRG_BUF_CLR(x) (((uint32_t)(((uint32_t)(x)) << DAC_CLR_TRG_BUF_CLR_SHIFT)) & DAC_CLR_TRG_BUF_CLR_MASK)
#define DAC_CLR_TRG_SW_TRG_MASK (0x2U)
#define DAC_CLR_TRG_SW_TRG_SHIFT (1U)
#define DAC_CLR_TRG_SW_TRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CLR_TRG_SW_TRG_SHIFT)) & DAC_CLR_TRG_SW_TRG_MASK)
/*! @name DIN - DAC data input */
#define DAC_DIN_DIN_MASK (0xFFFFFFFFU)
#define DAC_DIN_DIN_SHIFT (0U)
#define DAC_DIN_DIN(x) (((uint32_t)(((uint32_t)(x)) << DAC_DIN_DIN_SHIFT)) & DAC_DIN_DIN_MASK)
/*! @name INT - Reserved */
#define DAC_INT_BUF_NFUL_INT_MASK (0x1U)
#define DAC_INT_BUF_NFUL_INT_SHIFT (0U)
#define DAC_INT_BUF_NFUL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_BUF_NFUL_INT_SHIFT)) & DAC_INT_BUF_NFUL_INT_MASK)
#define DAC_INT_BUF_FUL_INT_MASK (0x2U)
#define DAC_INT_BUF_FUL_INT_SHIFT (1U)
#define DAC_INT_BUF_FUL_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_INT_BUF_FUL_INT_SHIFT)) & DAC_INT_BUF_FUL_INT_MASK)
#define DAC_INT_BUF_EMT_INT_MASK (0x4U)
#define DAC_INT_BUF_EMT_INT_SHIFT (2U)
#define DAC_INT_BUF_EMT_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_INT_BUF_EMT_INT_SHIFT)) & DAC_INT_BUF_EMT_INT_MASK)
#define DAC_INT_BUF_HEMT_INT_MASK (0x8U)
#define DAC_INT_BUF_HEMT_INT_SHIFT (3U)
#define DAC_INT_BUF_HEMT_INT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_BUF_HEMT_INT_SHIFT)) & DAC_INT_BUF_HEMT_INT_MASK)
#define DAC_INT_BUF_OV_INT_MASK (0x10U)
#define DAC_INT_BUF_OV_INT_SHIFT (4U)
#define DAC_INT_BUF_OV_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_INT_BUF_OV_INT_SHIFT)) & DAC_INT_BUF_OV_INT_MASK)
#define DAC_INT_BUF_UD_INT_MASK (0x20U)
#define DAC_INT_BUF_UD_INT_SHIFT (5U)
#define DAC_INT_BUF_UD_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_INT_BUF_UD_INT_SHIFT)) & DAC_INT_BUF_UD_INT_MASK)
#define DAC_INT_BUF_HFUL_INT_MASK (0x40U)
#define DAC_INT_BUF_HFUL_INT_SHIFT (6U)
#define DAC_INT_BUF_HFUL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_BUF_HFUL_INT_SHIFT)) & DAC_INT_BUF_HFUL_INT_MASK)
/*! @name INTEN - Reserved */
#define DAC_INTEN_BUF_NFUL_INTEN_MASK (0x1U)
#define DAC_INTEN_BUF_NFUL_INTEN_SHIFT (0U)
#define DAC_INTEN_BUF_NFUL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INTEN_BUF_NFUL_INTEN_SHIFT)) & DAC_INTEN_BUF_NFUL_INTEN_MASK)
#define DAC_INTEN_BUF_FUL_INTEN_MASK (0x2U)
#define DAC_INTEN_BUF_FUL_INTEN_SHIFT (1U)
#define DAC_INTEN_BUF_FUL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INTEN_BUF_FUL_INTEN_SHIFT)) & DAC_INTEN_BUF_FUL_INTEN_MASK)
#define DAC_INTEN_BUF_EMT_INTEN_MASK (0x4U)
#define DAC_INTEN_BUF_EMT_INTEN_SHIFT (2U)
#define DAC_INTEN_BUF_EMT_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INTEN_BUF_EMT_INTEN_SHIFT)) & DAC_INTEN_BUF_EMT_INTEN_MASK)
#define DAC_INTEN_BUF_HEMT_INTEN_MASK (0x8U)
#define DAC_INTEN_BUF_HEMT_INTEN_SHIFT (3U)
#define DAC_INTEN_BUF_HEMT_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INTEN_BUF_HEMT_INTEN_SHIFT)) & DAC_INTEN_BUF_HEMT_INTEN_MASK)
#define DAC_INTEN_BUF_OV_INTEN_MASK (0x10U)
#define DAC_INTEN_BUF_OV_INTEN_SHIFT (4U)
#define DAC_INTEN_BUF_OV_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INTEN_BUF_OV_INTEN_SHIFT)) & DAC_INTEN_BUF_OV_INTEN_MASK)
#define DAC_INTEN_BUF_UD_INTEN_MASK (0x20U)
#define DAC_INTEN_BUF_UD_INTEN_SHIFT (5U)
#define DAC_INTEN_BUF_UD_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INTEN_BUF_UD_INTEN_SHIFT)) & DAC_INTEN_BUF_UD_INTEN_MASK)
#define DAC_INTEN_BUF_HFUL_INTEN_MASK (0x40U)
#define DAC_INTEN_BUF_HFUL_INTEN_SHIFT (6U)
#define DAC_INTEN_BUF_HFUL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INTEN_BUF_HFUL_INTEN_SHIFT)) & DAC_INTEN_BUF_HFUL_INTEN_MASK)
/*! @name INT_STAT - Reserved */
#define DAC_INT_STAT_BUF_NFUL_INT_STAT_MASK (0x1U)
#define DAC_INT_STAT_BUF_NFUL_INT_STAT_SHIFT (0U)
#define DAC_INT_STAT_BUF_NFUL_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_STAT_BUF_NFUL_INT_STAT_SHIFT)) & DAC_INT_STAT_BUF_NFUL_INT_STAT_MASK)
#define DAC_INT_STAT_BUF_FUL_INT_STAT_MASK (0x2U)
#define DAC_INT_STAT_BUF_FUL_INT_STAT_SHIFT (1U)
#define DAC_INT_STAT_BUF_FUL_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_STAT_BUF_FUL_INT_STAT_SHIFT)) & DAC_INT_STAT_BUF_FUL_INT_STAT_MASK)
#define DAC_INT_STAT_BUF_EMT_INT_STAT_MASK (0x4U)
#define DAC_INT_STAT_BUF_EMT_INT_STAT_SHIFT (2U)
#define DAC_INT_STAT_BUF_EMT_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_STAT_BUF_EMT_INT_STAT_SHIFT)) & DAC_INT_STAT_BUF_EMT_INT_STAT_MASK)
#define DAC_INT_STAT_BUF_HEMT_INT_STAT_MASK (0x8U)
#define DAC_INT_STAT_BUF_HEMT_INT_STAT_SHIFT (3U)
#define DAC_INT_STAT_BUF_HEMT_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_STAT_BUF_HEMT_INT_STAT_SHIFT)) & DAC_INT_STAT_BUF_HEMT_INT_STAT_MASK)
#define DAC_INT_STAT_BUF_OV_INT_STAT_MASK (0x10U)
#define DAC_INT_STAT_BUF_OV_INT_STAT_SHIFT (4U)
#define DAC_INT_STAT_BUF_OV_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_STAT_BUF_OV_INT_STAT_SHIFT)) & DAC_INT_STAT_BUF_OV_INT_STAT_MASK)
#define DAC_INT_STAT_BUF_UD_INT_STAT_MASK (0x20U)
#define DAC_INT_STAT_BUF_UD_INT_STAT_SHIFT (5U)
#define DAC_INT_STAT_BUF_UD_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_STAT_BUF_UD_INT_STAT_SHIFT)) & DAC_INT_STAT_BUF_UD_INT_STAT_MASK)
#define DAC_INT_STAT_BUF_HFUL_INT_STAT_MASK (0x40U)
#define DAC_INT_STAT_BUF_HFUL_INT_STAT_SHIFT (6U)
#define DAC_INT_STAT_BUF_HFUL_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_STAT_BUF_HFUL_INT_STAT_SHIFT)) & DAC_INT_STAT_BUF_HFUL_INT_STAT_MASK)
#define DAC_INT_STAT_DAC_INT_STAT_MASK (0x10000U)
#define DAC_INT_STAT_DAC_INT_STAT_SHIFT (16U)
#define DAC_INT_STAT_DAC_INT_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_INT_STAT_DAC_INT_STAT_SHIFT)) & DAC_INT_STAT_DAC_INT_STAT_MASK)
/*! @name STATUS - Reserved */
#define DAC_STATUS_BUSY_MASK (0x1U)
#define DAC_STATUS_BUSY_SHIFT (0U)
#define DAC_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << DAC_STATUS_BUSY_SHIFT)) & DAC_STATUS_BUSY_MASK)
#define DAC_STATUS_BUF_WR_PTR_MASK (0x70000U)
#define DAC_STATUS_BUF_WR_PTR_SHIFT (16U)
#define DAC_STATUS_BUF_WR_PTR(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_STATUS_BUF_WR_PTR_SHIFT)) & DAC_STATUS_BUF_WR_PTR_MASK)
#define DAC_STATUS_BUF_RD_PTR_MASK (0x700000U)
#define DAC_STATUS_BUF_RD_PTR_SHIFT (20U)
#define DAC_STATUS_BUF_RD_PTR(x) \
(((uint32_t)(((uint32_t)(x)) << DAC_STATUS_BUF_RD_PTR_SHIFT)) & DAC_STATUS_BUF_RD_PTR_MASK)
/*!
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC base address */
#define DAC_BASE (0x40007400u)
/** Peripheral DAC base pointer */
#define DAC ((DAC_Type *)DAC_BASE)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS \
{ \
DAC_BASE \
}
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASE_PTRS \
{ \
DAC \
}
/** Interrupt vectors for the DAC peripheral type */
#define DAC_IRQS \
{ \
DAC_IRQn \
}
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct
{
__IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
__I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
__IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
uint8_t RESERVED_0[20];
struct
{ /* offset: 0x20, array step: 0x5C */
__IO uint32_t
ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
uint8_t RESERVED_0[4];
__O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
uint8_t RESERVED_1[4];
__I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
uint8_t RESERVED_2[4];
__I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
uint8_t RESERVED_3[4];
__IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
uint8_t RESERVED_4[4];
__IO uint32_t
INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
uint8_t RESERVED_5[4];
__O uint32_t
INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
uint8_t RESERVED_6[4];
__IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
uint8_t RESERVED_7[4];
__IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
uint8_t RESERVED_8[4];
__O uint32_t
SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
uint8_t RESERVED_9[4];
__O uint32_t
SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
uint8_t RESERVED_10[4];
__O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
} COMMON[1];
uint8_t RESERVED_1[900];
struct
{ /* offset: 0x400, array step: 0x10 */
__IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
__I uint32_t
CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
__IO uint32_t
XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
uint8_t RESERVED_0[4];
} CHANNEL[20];
} DMA_Type;
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/*! @name CTRL - DMA control. */
#define DMA_CTRL_ENABLE_MASK (0x1U)
#define DMA_CTRL_ENABLE_SHIFT (0U)
#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
/*! @name INTSTAT - Interrupt status. */
#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
#define DMA_INTSTAT_ACTIVEINT(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
#define DMA_INTSTAT_ACTIVEERRINT(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
/*! @name SRAMBASE - SRAM address of the channel configuration table. */
#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
#define DMA_COMMON_ENABLESET_ENA(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
/* The count of DMA_COMMON_ENABLESET */
#define DMA_COMMON_ENABLESET_COUNT (1U)
/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
#define DMA_COMMON_ENABLECLR_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
/* The count of DMA_COMMON_ENABLECLR */
#define DMA_COMMON_ENABLECLR_COUNT (1U)
/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
#define DMA_COMMON_ACTIVE_ACT(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
/* The count of DMA_COMMON_ACTIVE */
#define DMA_COMMON_ACTIVE_COUNT (1U)
/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
/* The count of DMA_COMMON_BUSY */
#define DMA_COMMON_BUSY_COUNT (1U)
/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
#define DMA_COMMON_ERRINT_ERR(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
/* The count of DMA_COMMON_ERRINT */
#define DMA_COMMON_ERRINT_COUNT (1U)
/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
#define DMA_COMMON_INTENSET_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
/* The count of DMA_COMMON_INTENSET */
#define DMA_COMMON_INTENSET_COUNT (1U)
/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
#define DMA_COMMON_INTENCLR_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
/* The count of DMA_COMMON_INTENCLR */
#define DMA_COMMON_INTENCLR_COUNT (1U)
/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
#define DMA_COMMON_INTA_IA_SHIFT (0U)
#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
/* The count of DMA_COMMON_INTA */
#define DMA_COMMON_INTA_COUNT (1U)
/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
#define DMA_COMMON_INTB_IB_SHIFT (0U)
#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
/* The count of DMA_COMMON_INTB */
#define DMA_COMMON_INTB_COUNT (1U)
/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
#define DMA_COMMON_SETVALID_SV(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
/* The count of DMA_COMMON_SETVALID */
#define DMA_COMMON_SETVALID_COUNT (1U)
/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
#define DMA_COMMON_SETTRIG_TRIG(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
/* The count of DMA_COMMON_SETTRIG */
#define DMA_COMMON_SETTRIG_COUNT (1U)
/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
#define DMA_COMMON_ABORT_ABORTCTRL(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
/* The count of DMA_COMMON_ABORT */
#define DMA_COMMON_ABORT_COUNT (1U)
/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
#define DMA_CHANNEL_CFG_PERIPHREQEN(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
#define DMA_CHANNEL_CFG_HWTRIGEN(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
#define DMA_CHANNEL_CFG_TRIGPOL(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
#define DMA_CHANNEL_CFG_TRIGTYPE(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
#define DMA_CHANNEL_CFG_TRIGBURST(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
#define DMA_CHANNEL_CFG_BURSTPOWER(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
#define DMA_CHANNEL_CFG_CHPRIORITY(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
/* The count of DMA_CHANNEL_CFG */
#define DMA_CHANNEL_CFG_COUNT (20U)
/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
#define DMA_CHANNEL_CTLSTAT_TRIG(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
/* The count of DMA_CHANNEL_CTLSTAT */
#define DMA_CHANNEL_CTLSTAT_COUNT (20U)
/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
#define DMA_CHANNEL_XFERCFG_CFGVALID(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
#define DMA_CHANNEL_XFERCFG_RELOAD(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
#define DMA_CHANNEL_XFERCFG_SWTRIG(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
#define DMA_CHANNEL_XFERCFG_SETINTA(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
#define DMA_CHANNEL_XFERCFG_SETINTB(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
#define DMA_CHANNEL_XFERCFG_WIDTH(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
#define DMA_CHANNEL_XFERCFG_SRCINC(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
#define DMA_CHANNEL_XFERCFG_DSTINC(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) \
(((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
/* The count of DMA_CHANNEL_XFERCFG */
#define DMA_CHANNEL_XFERCFG_COUNT (20U)
/*!
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral DMA0 base address */
#define DMA0_BASE (0x40082000u)
/** Peripheral DMA0 base pointer */
#define DMA0 ((DMA_Type *)DMA0_BASE)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS \
{ \
DMA0_BASE \
}
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS \
{ \
DMA0 \
}
/** Interrupt vectors for the DMA peripheral type */
#define DMA_IRQS \
{ \
DMA0_IRQn \
}
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLASH Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer
* @{
*/
/** FLASH - Register Layout Typedef */
typedef struct
{
__IO uint32_t INI_RD_EN; /**< flash initial read register, offset: 0x0 */
__IO uint32_t ERASE_CTRL; /**< flash erase control register, offset: 0x4 */
__IO uint32_t ERASE_TIME; /**< flash erase time setting register, offset: 0x8 */
__IO uint32_t TIME_CTRL; /**< flash operation time setting register, offset: 0xC */
__IO uint32_t SMART_CTRL; /**< smart erase control register, offset: 0x10 */
__IO uint32_t INTEN; /**< interrupt enable register, offset: 0x14 */
__IO uint32_t INT_STAT; /**< interrupt status register, offset: 0x18 */
__IO uint32_t INTCLR; /**< interrupt clear register, offset: 0x1C */
__I uint32_t LOCK_STAT0; /**< lock control register 0, offset: 0x20 */
__I uint32_t LOCK_STAT1; /**< , offset: 0x24 */
__I uint32_t LOCK_STAT2; /**< , offset: 0x28 */
__I uint32_t LOCK_STAT3; /**< , offset: 0x2C */
__I uint32_t LOCK_STAT4; /**< , offset: 0x30 */
__I uint32_t LOCK_STAT5; /**< , offset: 0x34 */
__I uint32_t LOCK_STAT6; /**< , offset: 0x38 */
__I uint32_t LOCK_STAT7; /**< , offset: 0x3C */
__IO uint32_t LOCK_STAT8; /**< , offset: 0x40 */
uint8_t RESERVED_0[4];
__I uint32_t STATUS1; /**< , offset: 0x48 */
uint8_t RESERVED_1[16];
__I uint32_t ERR_INFOL1; /**< , offset: 0x5C */
__I uint32_t ERR_INFOL2; /**< , offset: 0x60 */
__I uint32_t ERR_INFOL3; /**< , offset: 0x64 */
__I uint32_t ERR_INFOH1; /**< , offset: 0x68 */
__I uint32_t ERR_INFOH2; /**< , offset: 0x6C */
__I uint32_t ERR_INFOH3; /**< , offset: 0x70 */
uint8_t RESERVED_2[52];
__IO uint32_t DEBUG_PASSWORD; /**< , offset: 0xA8 */
__IO uint32_t ERASE_PASSWORD; /**< , offset: 0xAC */
} FLASH_Type;
/* ----------------------------------------------------------------------------
-- FLASH Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLASH_Register_Masks FLASH Register Masks
* @{
*/
/*! @name INI_RD_EN - flash initial read register */
#define FLASH_INI_RD_EN_INI_RD_EN_MASK (0x1U)
#define FLASH_INI_RD_EN_INI_RD_EN_SHIFT (0U)
#define FLASH_INI_RD_EN_INI_RD_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INI_RD_EN_INI_RD_EN_SHIFT)) & FLASH_INI_RD_EN_INI_RD_EN_MASK)
/*! @name ERASE_CTRL - flash erase control register */
#define FLASH_ERASE_CTRL_PAGE_IDXL_MASK (0x7FU)
#define FLASH_ERASE_CTRL_PAGE_IDXL_SHIFT (0U)
#define FLASH_ERASE_CTRL_PAGE_IDXL(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERASE_CTRL_PAGE_IDXL_SHIFT)) & FLASH_ERASE_CTRL_PAGE_IDXL_MASK)
#define FLASH_ERASE_CTRL_PAGE_IDXH_MASK (0x7F00U)
#define FLASH_ERASE_CTRL_PAGE_IDXH_SHIFT (8U)
#define FLASH_ERASE_CTRL_PAGE_IDXH(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERASE_CTRL_PAGE_IDXH_SHIFT)) & FLASH_ERASE_CTRL_PAGE_IDXH_MASK)
#define FLASH_ERASE_CTRL_HALF_ERASEL_EN_MASK (0x10000000U)
#define FLASH_ERASE_CTRL_HALF_ERASEL_EN_SHIFT (28U)
#define FLASH_ERASE_CTRL_HALF_ERASEL_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERASE_CTRL_HALF_ERASEL_EN_SHIFT)) & FLASH_ERASE_CTRL_HALF_ERASEL_EN_MASK)
#define FLASH_ERASE_CTRL_HALF_ERASEH_EN_MASK (0x20000000U)
#define FLASH_ERASE_CTRL_HALF_ERASEH_EN_SHIFT (29U)
#define FLASH_ERASE_CTRL_HALF_ERASEH_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERASE_CTRL_HALF_ERASEH_EN_SHIFT)) & FLASH_ERASE_CTRL_HALF_ERASEH_EN_MASK)
#define FLASH_ERASE_CTRL_PAGE_ERASEL_EN_MASK (0x40000000U)
#define FLASH_ERASE_CTRL_PAGE_ERASEL_EN_SHIFT (30U)
#define FLASH_ERASE_CTRL_PAGE_ERASEL_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERASE_CTRL_PAGE_ERASEL_EN_SHIFT)) & FLASH_ERASE_CTRL_PAGE_ERASEL_EN_MASK)
#define FLASH_ERASE_CTRL_PAGE_ERASEH_EN_MASK (0x80000000U)
#define FLASH_ERASE_CTRL_PAGE_ERASEH_EN_SHIFT (31U)
#define FLASH_ERASE_CTRL_PAGE_ERASEH_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERASE_CTRL_PAGE_ERASEH_EN_SHIFT)) & FLASH_ERASE_CTRL_PAGE_ERASEH_EN_MASK)
/*! @name ERASE_TIME - flash erase time setting register */
#define FLASH_ERASE_TIME_ERASE_TIME_BASE_MASK (0xFFFFFU)
#define FLASH_ERASE_TIME_ERASE_TIME_BASE_SHIFT (0U)
#define FLASH_ERASE_TIME_ERASE_TIME_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERASE_TIME_ERASE_TIME_BASE_SHIFT)) & FLASH_ERASE_TIME_ERASE_TIME_BASE_MASK)
/*! @name TIME_CTRL - flash operation time setting register */
#define FLASH_TIME_CTRL_PRGM_CYCLE_MASK (0xFFFU)
#define FLASH_TIME_CTRL_PRGM_CYCLE_SHIFT (0U)
#define FLASH_TIME_CTRL_PRGM_CYCLE(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_TIME_CTRL_PRGM_CYCLE_SHIFT)) & FLASH_TIME_CTRL_PRGM_CYCLE_MASK)
#define FLASH_TIME_CTRL_TIME_BASE_MASK (0xFF000U)
#define FLASH_TIME_CTRL_TIME_BASE_SHIFT (12U)
#define FLASH_TIME_CTRL_TIME_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_TIME_CTRL_TIME_BASE_SHIFT)) & FLASH_TIME_CTRL_TIME_BASE_MASK)
/*! @name SMART_CTRL - smart erase control register */
#define FLASH_SMART_CTRL_PRGML_EN_MASK (0x1U)
#define FLASH_SMART_CTRL_PRGML_EN_SHIFT (0U)
#define FLASH_SMART_CTRL_PRGML_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_SMART_CTRL_PRGML_EN_SHIFT)) & FLASH_SMART_CTRL_PRGML_EN_MASK)
#define FLASH_SMART_CTRL_PRGMH_EN_MASK (0x2U)
#define FLASH_SMART_CTRL_PRGMH_EN_SHIFT (1U)
#define FLASH_SMART_CTRL_PRGMH_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_SMART_CTRL_PRGMH_EN_SHIFT)) & FLASH_SMART_CTRL_PRGMH_EN_MASK)
#define FLASH_SMART_CTRL_SMART_WRITEL_EN_MASK (0x4U)
#define FLASH_SMART_CTRL_SMART_WRITEL_EN_SHIFT (2U)
#define FLASH_SMART_CTRL_SMART_WRITEL_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_SMART_CTRL_SMART_WRITEL_EN_SHIFT)) & FLASH_SMART_CTRL_SMART_WRITEL_EN_MASK)
#define FLASH_SMART_CTRL_SMART_WRITEH_EN_MASK (0x8U)
#define FLASH_SMART_CTRL_SMART_WRITEH_EN_SHIFT (3U)
#define FLASH_SMART_CTRL_SMART_WRITEH_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_SMART_CTRL_SMART_WRITEH_EN_SHIFT)) & FLASH_SMART_CTRL_SMART_WRITEH_EN_MASK)
#define FLASH_SMART_CTRL_SMART_ERASEL_EN_MASK (0x10U)
#define FLASH_SMART_CTRL_SMART_ERASEL_EN_SHIFT (4U)
#define FLASH_SMART_CTRL_SMART_ERASEL_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_SMART_CTRL_SMART_ERASEL_EN_SHIFT)) & FLASH_SMART_CTRL_SMART_ERASEL_EN_MASK)
#define FLASH_SMART_CTRL_SMART_ERASEH_EN_MASK (0x20U)
#define FLASH_SMART_CTRL_SMART_ERASEH_EN_SHIFT (5U)
#define FLASH_SMART_CTRL_SMART_ERASEH_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_SMART_CTRL_SMART_ERASEH_EN_SHIFT)) & FLASH_SMART_CTRL_SMART_ERASEH_EN_MASK)
#define FLASH_SMART_CTRL_MAX_WRITE_MASK (0xF00U)
#define FLASH_SMART_CTRL_MAX_WRITE_SHIFT (8U)
#define FLASH_SMART_CTRL_MAX_WRITE(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_SMART_CTRL_MAX_WRITE_SHIFT)) & FLASH_SMART_CTRL_MAX_WRITE_MASK)
#define FLASH_SMART_CTRL_MAX_ERASE_MASK (0x3F000U)
#define FLASH_SMART_CTRL_MAX_ERASE_SHIFT (12U)
#define FLASH_SMART_CTRL_MAX_ERASE(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_SMART_CTRL_MAX_ERASE_SHIFT)) & FLASH_SMART_CTRL_MAX_ERASE_MASK)
/*! @name INTEN - interrupt enable register */
#define FLASH_INTEN_AHBL_INTEN_MASK (0x1U)
#define FLASH_INTEN_AHBL_INTEN_SHIFT (0U)
#define FLASH_INTEN_AHBL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_AHBL_INTEN_SHIFT)) & FLASH_INTEN_AHBL_INTEN_MASK)
#define FLASH_INTEN_LOCKL_INTEN_MASK (0x2U)
#define FLASH_INTEN_LOCKL_INTEN_SHIFT (1U)
#define FLASH_INTEN_LOCKL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_LOCKL_INTEN_SHIFT)) & FLASH_INTEN_LOCKL_INTEN_MASK)
#define FLASH_INTEN_ERASEL_INTEN_MASK (0x4U)
#define FLASH_INTEN_ERASEL_INTEN_SHIFT (2U)
#define FLASH_INTEN_ERASEL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_ERASEL_INTEN_SHIFT)) & FLASH_INTEN_ERASEL_INTEN_MASK)
#define FLASH_INTEN_WRITEL_INTEN_MASK (0x8U)
#define FLASH_INTEN_WRITEL_INTEN_SHIFT (3U)
#define FLASH_INTEN_WRITEL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_WRITEL_INTEN_SHIFT)) & FLASH_INTEN_WRITEL_INTEN_MASK)
#define FLASH_INTEN_WRBUFL_INTEN_MASK (0x10U)
#define FLASH_INTEN_WRBUFL_INTEN_SHIFT (4U)
#define FLASH_INTEN_WRBUFL_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_WRBUFL_INTEN_SHIFT)) & FLASH_INTEN_WRBUFL_INTEN_MASK)
#define FLASH_INTEN_AHBH_INTEN_MASK (0x100U)
#define FLASH_INTEN_AHBH_INTEN_SHIFT (8U)
#define FLASH_INTEN_AHBH_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_AHBH_INTEN_SHIFT)) & FLASH_INTEN_AHBH_INTEN_MASK)
#define FLASH_INTEN_LOCKH_INTEN_MASK (0x200U)
#define FLASH_INTEN_LOCKH_INTEN_SHIFT (9U)
#define FLASH_INTEN_LOCKH_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_LOCKH_INTEN_SHIFT)) & FLASH_INTEN_LOCKH_INTEN_MASK)
#define FLASH_INTEN_ERASEH_INTEN_MASK (0x400U)
#define FLASH_INTEN_ERASEH_INTEN_SHIFT (10U)
#define FLASH_INTEN_ERASEH_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_ERASEH_INTEN_SHIFT)) & FLASH_INTEN_ERASEH_INTEN_MASK)
#define FLASH_INTEN_WRITEH_INTEN_MASK (0x800U)
#define FLASH_INTEN_WRITEH_INTEN_SHIFT (11U)
#define FLASH_INTEN_WRITEH_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_WRITEH_INTEN_SHIFT)) & FLASH_INTEN_WRITEH_INTEN_MASK)
#define FLASH_INTEN_WRBUFH_INTEN_MASK (0x1000U)
#define FLASH_INTEN_WRBUFH_INTEN_SHIFT (12U)
#define FLASH_INTEN_WRBUFH_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_WRBUFH_INTEN_SHIFT)) & FLASH_INTEN_WRBUFH_INTEN_MASK)
#define FLASH_INTEN_FLASH_INTEN_MASK (0x80000000U)
#define FLASH_INTEN_FLASH_INTEN_SHIFT (31U)
#define FLASH_INTEN_FLASH_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_FLASH_INTEN_SHIFT)) & FLASH_INTEN_FLASH_INTEN_MASK)
/*! @name INT_STAT - interrupt status register */
#define FLASH_INT_STAT_AHBL_INT_MASK (0x1U)
#define FLASH_INT_STAT_AHBL_INT_SHIFT (0U)
#define FLASH_INT_STAT_AHBL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_AHBL_INT_SHIFT)) & FLASH_INT_STAT_AHBL_INT_MASK)
#define FLASH_INT_STAT_LOCKL_INT_MASK (0x2U)
#define FLASH_INT_STAT_LOCKL_INT_SHIFT (1U)
#define FLASH_INT_STAT_LOCKL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_LOCKL_INT_SHIFT)) & FLASH_INT_STAT_LOCKL_INT_MASK)
#define FLASH_INT_STAT_ERASEL_INT_MASK (0x4U)
#define FLASH_INT_STAT_ERASEL_INT_SHIFT (2U)
#define FLASH_INT_STAT_ERASEL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_ERASEL_INT_SHIFT)) & FLASH_INT_STAT_ERASEL_INT_MASK)
#define FLASH_INT_STAT_WRITEL_INT_MASK (0x8U)
#define FLASH_INT_STAT_WRITEL_INT_SHIFT (3U)
#define FLASH_INT_STAT_WRITEL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_WRITEL_INT_SHIFT)) & FLASH_INT_STAT_WRITEL_INT_MASK)
#define FLASH_INT_STAT_WRBUFL_INT_MASK (0x10U)
#define FLASH_INT_STAT_WRBUFL_INT_SHIFT (4U)
#define FLASH_INT_STAT_WRBUFL_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_WRBUFL_INT_SHIFT)) & FLASH_INT_STAT_WRBUFL_INT_MASK)
#define FLASH_INT_STAT_WRITE_FAIL_L_INT_MASK (0x20U)
#define FLASH_INT_STAT_WRITE_FAIL_L_INT_SHIFT (5U)
#define FLASH_INT_STAT_WRITE_FAIL_L_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_WRITE_FAIL_L_INT_SHIFT)) & FLASH_INT_STAT_WRITE_FAIL_L_INT_MASK)
#define FLASH_INT_STAT_ERASE_FAIL_L_INT_MASK (0x40U)
#define FLASH_INT_STAT_ERASE_FAIL_L_INT_SHIFT (6U)
#define FLASH_INT_STAT_ERASE_FAIL_L_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_ERASE_FAIL_L_INT_SHIFT)) & FLASH_INT_STAT_ERASE_FAIL_L_INT_MASK)
#define FLASH_INT_STAT_AHBH_INT_MASK (0x100U)
#define FLASH_INT_STAT_AHBH_INT_SHIFT (8U)
#define FLASH_INT_STAT_AHBH_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_AHBH_INT_SHIFT)) & FLASH_INT_STAT_AHBH_INT_MASK)
#define FLASH_INT_STAT_LOCKH_INT_MASK (0x200U)
#define FLASH_INT_STAT_LOCKH_INT_SHIFT (9U)
#define FLASH_INT_STAT_LOCKH_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_LOCKH_INT_SHIFT)) & FLASH_INT_STAT_LOCKH_INT_MASK)
#define FLASH_INT_STAT_ERASEH_INT_MASK (0x400U)
#define FLASH_INT_STAT_ERASEH_INT_SHIFT (10U)
#define FLASH_INT_STAT_ERASEH_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_ERASEH_INT_SHIFT)) & FLASH_INT_STAT_ERASEH_INT_MASK)
#define FLASH_INT_STAT_WRITEH_INT_MASK (0x800U)
#define FLASH_INT_STAT_WRITEH_INT_SHIFT (11U)
#define FLASH_INT_STAT_WRITEH_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_WRITEH_INT_SHIFT)) & FLASH_INT_STAT_WRITEH_INT_MASK)
#define FLASH_INT_STAT_WRBUFH_INT_MASK (0x1000U)
#define FLASH_INT_STAT_WRBUFH_INT_SHIFT (12U)
#define FLASH_INT_STAT_WRBUFH_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_WRBUFH_INT_SHIFT)) & FLASH_INT_STAT_WRBUFH_INT_MASK)
#define FLASH_INT_STAT_WRITE_FAIL_H_INT_MASK (0x2000U)
#define FLASH_INT_STAT_WRITE_FAIL_H_INT_SHIFT (13U)
#define FLASH_INT_STAT_WRITE_FAIL_H_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_WRITE_FAIL_H_INT_SHIFT)) & FLASH_INT_STAT_WRITE_FAIL_H_INT_MASK)
#define FLASH_INT_STAT_ERASE_FAIL_H_INT_MASK (0x4000U)
#define FLASH_INT_STAT_ERASE_FAIL_H_INT_SHIFT (14U)
#define FLASH_INT_STAT_ERASE_FAIL_H_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INT_STAT_ERASE_FAIL_H_INT_SHIFT)) & FLASH_INT_STAT_ERASE_FAIL_H_INT_MASK)
/*! @name INTCLR - interrupt clear register */
#define FLASH_INTCLR_AHBL_INTCLR_MASK (0x1U)
#define FLASH_INTCLR_AHBL_INTCLR_SHIFT (0U)
#define FLASH_INTCLR_AHBL_INTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTCLR_AHBL_INTCLR_SHIFT)) & FLASH_INTCLR_AHBL_INTCLR_MASK)
#define FLASH_INTCLR_LOCKL_INTCLR_MASK (0x2U)
#define FLASH_INTCLR_LOCKL_INTCLR_SHIFT (1U)
#define FLASH_INTCLR_LOCKL_INTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTCLR_LOCKL_INTCLR_SHIFT)) & FLASH_INTCLR_LOCKL_INTCLR_MASK)
#define FLASH_INTCLR_ERASEL_INTCLR_MASK (0x4U)
#define FLASH_INTCLR_ERASEL_INTCLR_SHIFT (2U)
#define FLASH_INTCLR_ERASEL_INTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTCLR_ERASEL_INTCLR_SHIFT)) & FLASH_INTCLR_ERASEL_INTCLR_MASK)
#define FLASH_INTCLR_WRITEL_INTCLR_MASK (0x8U)
#define FLASH_INTCLR_WRITEL_INTCLR_SHIFT (3U)
#define FLASH_INTCLR_WRITEL_INTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTCLR_WRITEL_INTCLR_SHIFT)) & FLASH_INTCLR_WRITEL_INTCLR_MASK)
#define FLASH_INTCLR_AHBH_INTCLR_MASK (0x100U)
#define FLASH_INTCLR_AHBH_INTCLR_SHIFT (8U)
#define FLASH_INTCLR_AHBH_INTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTCLR_AHBH_INTCLR_SHIFT)) & FLASH_INTCLR_AHBH_INTCLR_MASK)
#define FLASH_INTCLR_LOCKH_INTCLR_MASK (0x200U)
#define FLASH_INTCLR_LOCKH_INTCLR_SHIFT (9U)
#define FLASH_INTCLR_LOCKH_INTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTCLR_LOCKH_INTCLR_SHIFT)) & FLASH_INTCLR_LOCKH_INTCLR_MASK)
#define FLASH_INTCLR_ERASEH_INTCLR_MASK (0x400U)
#define FLASH_INTCLR_ERASEH_INTCLR_SHIFT (10U)
#define FLASH_INTCLR_ERASEH_INTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTCLR_ERASEH_INTCLR_SHIFT)) & FLASH_INTCLR_ERASEH_INTCLR_MASK)
#define FLASH_INTCLR_WRITEH_INTCLR_MASK (0x800U)
#define FLASH_INTCLR_WRITEH_INTCLR_SHIFT (11U)
#define FLASH_INTCLR_WRITEH_INTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_INTCLR_WRITEH_INTCLR_SHIFT)) & FLASH_INTCLR_WRITEH_INTCLR_MASK)
/*! @name LOCK_STAT0 - lock control register 0 */
#define FLASH_LOCK_STAT0_PAGE_LOCK0_MASK (0xFFFFFFFFU)
#define FLASH_LOCK_STAT0_PAGE_LOCK0_SHIFT (0U)
#define FLASH_LOCK_STAT0_PAGE_LOCK0(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT0_PAGE_LOCK0_SHIFT)) & FLASH_LOCK_STAT0_PAGE_LOCK0_MASK)
/*! @name LOCK_STAT1 - */
#define FLASH_LOCK_STAT1_PAGE_LOCK1_MASK (0xFFFFFFFFU)
#define FLASH_LOCK_STAT1_PAGE_LOCK1_SHIFT (0U)
#define FLASH_LOCK_STAT1_PAGE_LOCK1(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT1_PAGE_LOCK1_SHIFT)) & FLASH_LOCK_STAT1_PAGE_LOCK1_MASK)
/*! @name LOCK_STAT2 - */
#define FLASH_LOCK_STAT2_PAGE_LOCK2_MASK (0xFFFFFFFFU)
#define FLASH_LOCK_STAT2_PAGE_LOCK2_SHIFT (0U)
#define FLASH_LOCK_STAT2_PAGE_LOCK2(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT2_PAGE_LOCK2_SHIFT)) & FLASH_LOCK_STAT2_PAGE_LOCK2_MASK)
/*! @name LOCK_STAT3 - */
#define FLASH_LOCK_STAT3_PAGE_LOCK3_MASK (0xFFFFFFFFU)
#define FLASH_LOCK_STAT3_PAGE_LOCK3_SHIFT (0U)
#define FLASH_LOCK_STAT3_PAGE_LOCK3(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT3_PAGE_LOCK3_SHIFT)) & FLASH_LOCK_STAT3_PAGE_LOCK3_MASK)
/*! @name LOCK_STAT4 - */
#define FLASH_LOCK_STAT4_PAGE_LOCK4_MASK (0xFFFFFFFFU)
#define FLASH_LOCK_STAT4_PAGE_LOCK4_SHIFT (0U)
#define FLASH_LOCK_STAT4_PAGE_LOCK4(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT4_PAGE_LOCK4_SHIFT)) & FLASH_LOCK_STAT4_PAGE_LOCK4_MASK)
/*! @name LOCK_STAT5 - */
#define FLASH_LOCK_STAT5_PAGE_LOCK5_MASK (0xFFFFFFFFU)
#define FLASH_LOCK_STAT5_PAGE_LOCK5_SHIFT (0U)
#define FLASH_LOCK_STAT5_PAGE_LOCK5(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT5_PAGE_LOCK5_SHIFT)) & FLASH_LOCK_STAT5_PAGE_LOCK5_MASK)
/*! @name LOCK_STAT6 - */
#define FLASH_LOCK_STAT6_PAGE_LOCK6_MASK (0xFFFFFFFFU)
#define FLASH_LOCK_STAT6_PAGE_LOCK6_SHIFT (0U)
#define FLASH_LOCK_STAT6_PAGE_LOCK6(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT6_PAGE_LOCK6_SHIFT)) & FLASH_LOCK_STAT6_PAGE_LOCK6_MASK)
/*! @name LOCK_STAT7 - */
#define FLASH_LOCK_STAT7_PAGE_LOCK7_MASK (0xFFFFFFFFU)
#define FLASH_LOCK_STAT7_PAGE_LOCK7_SHIFT (0U)
#define FLASH_LOCK_STAT7_PAGE_LOCK7(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT7_PAGE_LOCK7_SHIFT)) & FLASH_LOCK_STAT7_PAGE_LOCK7_MASK)
/*! @name LOCK_STAT8 - */
#define FLASH_LOCK_STAT8_MASS_ERASE_LOCK_MASK (0x1U)
#define FLASH_LOCK_STAT8_MASS_ERASE_LOCK_SHIFT (0U)
#define FLASH_LOCK_STAT8_MASS_ERASE_LOCK(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT8_MASS_ERASE_LOCK_SHIFT)) & FLASH_LOCK_STAT8_MASS_ERASE_LOCK_MASK)
#define FLASH_LOCK_STAT8_FSH_PROTECT_MASK (0x2U)
#define FLASH_LOCK_STAT8_FSH_PROTECT_SHIFT (1U)
#define FLASH_LOCK_STAT8_FSH_PROTECT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT8_FSH_PROTECT_SHIFT)) & FLASH_LOCK_STAT8_FSH_PROTECT_MASK)
#define FLASH_LOCK_STAT8_MEM_PROTECT_MASK (0x4U)
#define FLASH_LOCK_STAT8_MEM_PROTECT_SHIFT (2U)
#define FLASH_LOCK_STAT8_MEM_PROTECT(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_LOCK_STAT8_MEM_PROTECT_SHIFT)) & FLASH_LOCK_STAT8_MEM_PROTECT_MASK)
/*! @name STATUS1 - */
#define FLASH_STATUS1_FSH_ERA_BUSY_L_MASK (0x200U)
#define FLASH_STATUS1_FSH_ERA_BUSY_L_SHIFT (9U)
#define FLASH_STATUS1_FSH_ERA_BUSY_L(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_FSH_ERA_BUSY_L_SHIFT)) & FLASH_STATUS1_FSH_ERA_BUSY_L_MASK)
#define FLASH_STATUS1_FSH_WR_BUSY_L_MASK (0x400U)
#define FLASH_STATUS1_FSH_WR_BUSY_L_SHIFT (10U)
#define FLASH_STATUS1_FSH_WR_BUSY_L(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_FSH_WR_BUSY_L_SHIFT)) & FLASH_STATUS1_FSH_WR_BUSY_L_MASK)
#define FLASH_STATUS1_DBG_ERA_DONE_L_MASK (0x800U)
#define FLASH_STATUS1_DBG_ERA_DONE_L_SHIFT (11U)
#define FLASH_STATUS1_DBG_ERA_DONE_L(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_DBG_ERA_DONE_L_SHIFT)) & FLASH_STATUS1_DBG_ERA_DONE_L_MASK)
#define FLASH_STATUS1_FSH_ERA_BUSY_H_MASK (0x1000U)
#define FLASH_STATUS1_FSH_ERA_BUSY_H_SHIFT (12U)
#define FLASH_STATUS1_FSH_ERA_BUSY_H(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_FSH_ERA_BUSY_H_SHIFT)) & FLASH_STATUS1_FSH_ERA_BUSY_H_MASK)
#define FLASH_STATUS1_FSH_WR_BUSY_H_MASK (0x2000U)
#define FLASH_STATUS1_FSH_WR_BUSY_H_SHIFT (13U)
#define FLASH_STATUS1_FSH_WR_BUSY_H(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_FSH_WR_BUSY_H_SHIFT)) & FLASH_STATUS1_FSH_WR_BUSY_H_MASK)
#define FLASH_STATUS1_DBG_ERA_DONE_H_MASK (0x4000U)
#define FLASH_STATUS1_DBG_ERA_DONE_H_SHIFT (14U)
#define FLASH_STATUS1_DBG_ERA_DONE_H(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_DBG_ERA_DONE_H_SHIFT)) & FLASH_STATUS1_DBG_ERA_DONE_H_MASK)
#define FLASH_STATUS1_INI_RD_DONE_MASK (0x8000U)
#define FLASH_STATUS1_INI_RD_DONE_SHIFT (15U)
#define FLASH_STATUS1_INI_RD_DONE(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_INI_RD_DONE_SHIFT)) & FLASH_STATUS1_INI_RD_DONE_MASK)
#define FLASH_STATUS1_FSH_STA_MASK (0x4000000U)
#define FLASH_STATUS1_FSH_STA_SHIFT (26U)
#define FLASH_STATUS1_FSH_STA(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_FSH_STA_SHIFT)) & FLASH_STATUS1_FSH_STA_MASK)
#define FLASH_STATUS1_RESERVED_MASK (0xF8000000U)
#define FLASH_STATUS1_RESERVED_SHIFT (27U)
#define FLASH_STATUS1_RESERVED(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_STATUS1_RESERVED_SHIFT)) & FLASH_STATUS1_RESERVED_MASK)
/*! @name ERR_INFOL1 - */
#define FLASH_ERR_INFOL1_WR_FAILEDL_ADDR_MASK (0x3FFFFU)
#define FLASH_ERR_INFOL1_WR_FAILEDL_ADDR_SHIFT (0U)
#define FLASH_ERR_INFOL1_WR_FAILEDL_ADDR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERR_INFOL1_WR_FAILEDL_ADDR_SHIFT)) & FLASH_ERR_INFOL1_WR_FAILEDL_ADDR_MASK)
#define FLASH_ERR_INFOL1_SMART_FAILL_CTR_MASK (0xFC0000U)
#define FLASH_ERR_INFOL1_SMART_FAILL_CTR_SHIFT (18U)
#define FLASH_ERR_INFOL1_SMART_FAILL_CTR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERR_INFOL1_SMART_FAILL_CTR_SHIFT)) & FLASH_ERR_INFOL1_SMART_FAILL_CTR_MASK)
/*! @name ERR_INFOL2 - */
#define FLASH_ERR_INFOL2_WR_FAILEDL_DATA_MASK (0xFFFFFFFFU)
#define FLASH_ERR_INFOL2_WR_FAILEDL_DATA_SHIFT (0U)
#define FLASH_ERR_INFOL2_WR_FAILEDL_DATA(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERR_INFOL2_WR_FAILEDL_DATA_SHIFT)) & FLASH_ERR_INFOL2_WR_FAILEDL_DATA_MASK)
/*! @name ERR_INFOL3 - */
#define FLASH_ERR_INFOL3_ERA_FAILEDL_INFO_MASK (0x3FFFFU)
#define FLASH_ERR_INFOL3_ERA_FAILEDL_INFO_SHIFT (0U)
#define FLASH_ERR_INFOL3_ERA_FAILEDL_INFO(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERR_INFOL3_ERA_FAILEDL_INFO_SHIFT)) & FLASH_ERR_INFOL3_ERA_FAILEDL_INFO_MASK)
/*! @name ERR_INFOH1 - */
#define FLASH_ERR_INFOH1_WR_FAILEDH_ADDR_MASK (0x3FFFFU)
#define FLASH_ERR_INFOH1_WR_FAILEDH_ADDR_SHIFT (0U)
#define FLASH_ERR_INFOH1_WR_FAILEDH_ADDR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERR_INFOH1_WR_FAILEDH_ADDR_SHIFT)) & FLASH_ERR_INFOH1_WR_FAILEDH_ADDR_MASK)
#define FLASH_ERR_INFOH1_SMART_FAILH_CTR_MASK (0xFC0000U)
#define FLASH_ERR_INFOH1_SMART_FAILH_CTR_SHIFT (18U)
#define FLASH_ERR_INFOH1_SMART_FAILH_CTR(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERR_INFOH1_SMART_FAILH_CTR_SHIFT)) & FLASH_ERR_INFOH1_SMART_FAILH_CTR_MASK)
/*! @name ERR_INFOH2 - */
#define FLASH_ERR_INFOH2_WR_FAILEDH_DATA_MASK (0xFFFFFFFFU)
#define FLASH_ERR_INFOH2_WR_FAILEDH_DATA_SHIFT (0U)
#define FLASH_ERR_INFOH2_WR_FAILEDH_DATA(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERR_INFOH2_WR_FAILEDH_DATA_SHIFT)) & FLASH_ERR_INFOH2_WR_FAILEDH_DATA_MASK)
/*! @name ERR_INFOH3 - */
#define FLASH_ERR_INFOH3_ERA_FAILEDH_INFO_MASK (0x3FFFFU)
#define FLASH_ERR_INFOH3_ERA_FAILEDH_INFO_SHIFT (0U)
#define FLASH_ERR_INFOH3_ERA_FAILEDH_INFO(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERR_INFOH3_ERA_FAILEDH_INFO_SHIFT)) & FLASH_ERR_INFOH3_ERA_FAILEDH_INFO_MASK)
/*! @name DEBUG_PASSWORD - */
#define FLASH_DEBUG_PASSWORD_DEBUG_PASSWORD_MASK (0xFFFFFFFFU)
#define FLASH_DEBUG_PASSWORD_DEBUG_PASSWORD_SHIFT (0U)
#define FLASH_DEBUG_PASSWORD_DEBUG_PASSWORD(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_DEBUG_PASSWORD_DEBUG_PASSWORD_SHIFT)) & \
FLASH_DEBUG_PASSWORD_DEBUG_PASSWORD_MASK)
/*! @name ERASE_PASSWORD - */
#define FLASH_ERASE_PASSWORD_ERASE_PASSWORD_MASK (0xFFFFFFFFU)
#define FLASH_ERASE_PASSWORD_ERASE_PASSWORD_SHIFT (0U)
#define FLASH_ERASE_PASSWORD_ERASE_PASSWORD(x) \
(((uint32_t)(((uint32_t)(x)) << FLASH_ERASE_PASSWORD_ERASE_PASSWORD_SHIFT)) & \
FLASH_ERASE_PASSWORD_ERASE_PASSWORD_MASK)
/*!
* @}
*/ /* end of group FLASH_Register_Masks */
/* FLASH - Peripheral instance base addresses */
/** Peripheral FLASH base address */
#define FLASH_BASE (0x40081000u)
/** Peripheral FLASH base pointer */
#define FLASH ((FLASH_Type *)FLASH_BASE)
/** Array initializer of FLASH peripheral base addresses */
#define FLASH_BASE_ADDRS \
{ \
FLASH_BASE \
}
/** Array initializer of FLASH peripheral base pointers */
#define FLASH_BASE_PTRS \
{ \
FLASH \
}
/** Interrupt vectors for the FLASH peripheral type */
#define FLASH_IRQS \
{ \
FLASH_IRQn \
}
/*!
* @}
*/ /* end of group FLASH_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXCOMM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
* @{
*/
/** FLEXCOMM - Register Layout Typedef */
typedef struct
{
uint8_t RESERVED_0[3840];
__IO uint32_t IOMODE; /**< io mode register, offset: 0xF00 */
uint8_t RESERVED_1[244];
__IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
__I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
} FLEXCOMM_Type;
/* ----------------------------------------------------------------------------
-- FLEXCOMM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
* @{
*/
/*! @name IOMODE - io mode register */
#define FLEXCOMM_IOMODE_DIO_MODE_MASK (0x1U)
#define FLEXCOMM_IOMODE_DIO_MODE_SHIFT (0U)
#define FLEXCOMM_IOMODE_DIO_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_IOMODE_DIO_MODE_SHIFT)) & FLEXCOMM_IOMODE_DIO_MODE_MASK)
#define FLEXCOMM_IOMODE_DIO_OEN_MASK (0x2U)
#define FLEXCOMM_IOMODE_DIO_OEN_SHIFT (1U)
#define FLEXCOMM_IOMODE_DIO_OEN(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_IOMODE_DIO_OEN_SHIFT)) & FLEXCOMM_IOMODE_DIO_OEN_MASK)
/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
#define FLEXCOMM_PSELID_PERSEL(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
#define FLEXCOMM_PSELID_LOCK(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
#define FLEXCOMM_PSELID_USARTPRESENT(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
#define FLEXCOMM_PSELID_SPIPRESENT(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
#define FLEXCOMM_PSELID_I2CPRESENT(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
#define FLEXCOMM_PSELID_I2SPRESENT(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
#define FLEXCOMM_PSELID_SC3W_MASK (0x100U)
#define FLEXCOMM_PSELID_SC3W_SHIFT (8U)
#define FLEXCOMM_PSELID_SC3W(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SC3W_SHIFT)) & FLEXCOMM_PSELID_SC3W_MASK)
#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
#define FLEXCOMM_PSELID_ID_SHIFT (12U)
#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
/*! @name PID - Peripheral identification register. */
#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
#define FLEXCOMM_PID_Minor_Rev(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
#define FLEXCOMM_PID_Major_Rev(x) \
(((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
#define FLEXCOMM_PID_ID_SHIFT (16U)
#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
/*!
* @}
*/ /* end of group FLEXCOMM_Register_Masks */
/* FLEXCOMM - Peripheral instance base addresses */
/** Peripheral FLEXCOMM0 base address */
#define FLEXCOMM0_BASE (0x40083000u)
/** Peripheral FLEXCOMM0 base pointer */
#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
/** Peripheral FLEXCOMM1 base address */
#define FLEXCOMM1_BASE (0x40086000u)
/** Peripheral FLEXCOMM1 base pointer */
#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
/** Peripheral FLEXCOMM2 base address */
#define FLEXCOMM2_BASE (0x40087000u)
/** Peripheral FLEXCOMM2 base pointer */
#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
/** Peripheral FLEXCOMM3 base address */
#define FLEXCOMM3_BASE (0x4008F000u)
/** Peripheral FLEXCOMM3 base pointer */
#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
/** Array initializer of FLEXCOMM peripheral base addresses */
#define FLEXCOMM_BASE_ADDRS \
{ \
FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE \
}
/** Array initializer of FLEXCOMM peripheral base pointers */
#define FLEXCOMM_BASE_PTRS \
{ \
FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3 \
}
/** Interrupt vectors for the FLEXCOMM peripheral type */
#define FLEXCOMM_IRQS \
{ \
FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn \
}
/*!
* @}
*/ /* end of group FLEXCOMM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FSP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FSP_Peripheral_Access_Layer FSP Peripheral Access Layer
* @{
*/
/** FSP - Register Layout Typedef */
typedef struct
{
__IO uint32_t SYS_CTRL; /**< FSP system control register, offset: 0x0 */
__I uint32_t STATUS; /**< FSP status register, offset: 0x4 */
__IO uint32_t INT; /**< FSP interrupt register, offset: 0x8 */
__IO uint32_t INTEN; /**< FSP interrupt enable register, offset: 0xC */
uint8_t RESERVED_0[16];
__IO uint32_t TE_CTRL; /**< transmit engine control register, offset: 0x20 */
__IO uint32_t TE_SRC_BASE; /**< transfer engine source data memory base register, offset: 0x24 */
__IO uint32_t TE_DST_BASE; /**< transfer engine destination data memory base register, offset: 0x28 */
uint8_t RESERVED_1[20];
__IO uint32_t MOU_CTRL; /**< matrix operation unit control register, offset: 0x40 */
__IO uint32_t MA_SRC_BASE; /**< matrix A source data memory base register, offset: 0x44 */
__IO uint32_t MB_SRC_BASE; /**< matrix B source data memory base register, offset: 0x48 */
__IO uint32_t MO_DST_BASE; /**< matrix output data memory base register, offset: 0x4C */
__IO uint32_t MOU_SCALEA; /**< scale coefficient A register, offset: 0x50 */
__IO uint32_t MOU_SCALEB; /**< scale coefficient B register, offset: 0x54 */
uint8_t RESERVED_2[8];
__IO uint32_t SE_CTRL; /**< stastic engine control register, offset: 0x60 */
__IO uint32_t SE_SRC_BASE; /**< statistic engine source data base register, offset: 0x64 */
__I uint32_t SE_IDX; /**< max or min data index register, offset: 0x68 */
__I uint32_t SE_SUM; /**< array summary result register, offset: 0x6C */
__I uint32_t SE_PWR; /**< array power result register, offset: 0x70 */
uint8_t RESERVED_3[12];
__IO uint32_t COR_CTRL; /**< correlation control register, offset: 0x80 */
__IO uint32_t CX_SRC_BASE; /**< correlation x sequence base register, offset: 0x84 */
__IO uint32_t CY_SRC_BASE; /**< correlation y sequence base register, offset: 0x88 */
__IO uint32_t CO_DST_BASE; /**< correlation output sequence base register, offset: 0x8C */
__IO uint32_t COR_OFFSET; /**< correlation offset register, offset: 0x90 */
uint8_t RESERVED_4[12];
__IO uint32_t FIR_CFG_CH0; /**< FIR channel 0 configuration register, offset: 0xA0 */
__IO uint32_t FIR_CFG_CH1; /**< FIR channel 1 configuration register, offset: 0xA4 */
__IO uint32_t FIR_CFG_CH2; /**< FIR channel 2 configuration register, offset: 0xA8 */
__IO uint32_t FIR_CFG_CH3; /**< FIR channel 3 configuration register, offset: 0xAC */
__IO uint32_t FIR_CFG_CH4; /**< FIR channel 4 configuration register, offset: 0xB0 */
__IO uint32_t FIR_CFG_CH5; /**< FIR channel 5 configuration register, offset: 0xB4 */
__IO uint32_t FIR_CFG_CH6; /**< FIR channel 6 configuration register, offset: 0xB8 */
__IO uint32_t FIR_CFG_CH7; /**< FIR channel 7 configuration register, offset: 0xBC */
__IO uint32_t FIR_CFG_CH8; /**< FIR channel 8 configuration register, offset: 0xC0 */
uint8_t RESERVED_5[12];
__IO uint32_t FIR_DAT0_FX; /**< FIR channel 0 fix point data input & output register, offset: 0xD0 */
__IO uint32_t FIR_DAT1_FX; /**< FIR channel 1 fix point data input & output register, offset: 0xD4 */
__IO uint32_t FIR_DAT2_FX; /**< FIR channel 2 fix point data input & output register, offset: 0xD8 */
__IO uint32_t FIR_DAT3_FX; /**< FIR channel 3 fix point data input & output register, offset: 0xDC */
__IO uint32_t FIR_DAT4_FX; /**< FIR channel 4 fix point data input & output register, offset: 0xE0 */
__IO uint32_t FIR_DAT5_FX; /**< FIR channel 5 fix point data input & output register, offset: 0xE4 */
__IO uint32_t FIR_DAT6_FX; /**< FIR channel 6 fix point data input & output register, offset: 0xE8 */
__IO uint32_t FIR_DAT7_FX; /**< FIR channel 7 fix point data input & output register, offset: 0xEC */
__IO uint32_t FIR_DAT8_FX; /**< FIR channel 8 fix point data input & output register, offset: 0xF0 */
uint8_t RESERVED_6[12];
__IO uint32_t FIR_DAT0_FL; /**< FIR channel 0 float point data input & output register, offset: 0x100 */
__IO uint32_t FIR_DAT1_FL; /**< FIR channel 1 float point data input & output register, offset: 0x104 */
__IO uint32_t FIR_DAT2_FL; /**< FIR channel 2 float point data input & output register, offset: 0x108 */
__IO uint32_t FIR_DAT3_FL; /**< FIR channel 3 float point data input & output register, offset: 0x10C */
__IO uint32_t FIR_DAT4_FL; /**< FIR channel 4 float point data input & output register, offset: 0x110 */
__IO uint32_t FIR_DAT5_FL; /**< FIR channel 5 float point data input & output register, offset: 0x114 */
__IO uint32_t FIR_DAT6_FL; /**< FIR channel 6 float point data input & output register, offset: 0x118 */
__IO uint32_t FIR_DAT7_FL; /**< FIR channel 7 float point data input & output register, offset: 0x11C */
__IO uint32_t FIR_DAT8_FL; /**< FIR channel 8 float point data input & output register, offset: 0x120 */
uint8_t RESERVED_7[28];
__O uint32_t SIN_COS_IXOX; /**< sin & cos input fix output fix mode data address register, offset: 0x140 */
__O uint32_t SIN_COS_IXOL; /**< sin & cos input fix output float mode data address register, offset: 0x144 */
__O uint32_t SIN_COS_ILOX; /**< sin & cos input float output fix mode data address register, offset: 0x148 */
__O uint32_t SIN_COS_ILOL; /**< sin & cos input float output float mode data address register, offset: 0x14C */
__O uint32_t LN_SQRT_IXOX; /**< LN & sqrt input fix output fix mode data address register, offset: 0x150 */
__O uint32_t LN_SQRT_IXOL; /**< LN & sqrt input fix output float mode data address register, offset: 0x154 */
__O uint32_t LN_SQRT_ILOX; /**< LN & sqrt input float output fix mode data address register, offset: 0x158 */
__O uint32_t LN_SQRT_ILOL; /**< LN & sqrt input float output float mode data address register, offset: 0x15C */
__O uint32_t
CORDIC_T0UP_IXOX; /**< native cordic input fix output fix, t=0, u=1 mode data address register, offset: 0x160 */
__O uint32_t CORDIC_T0UP_IXOL; /**< native cordic input fix output float, t=0, u=1 mode data address register,
offset: 0x164 */
__O uint32_t CORDIC_T0UP_ILOX; /**< native cordic input float output fix, t=0, u=1 mode data address register,
offset: 0x168 */
__O uint32_t CORDIC_T0UP_ILOL; /**< native cordic input float output float, t=0, u=1 mode data address register,
offset: 0x16C */
__O uint32_t CORDIC_T0UN_IXOX; /**< native cordic input fix output fix, t=0, u=-1 mode data address register,
offset: 0x170 */
__O uint32_t CORDIC_T0UN_IXOL; /**< native cordic input fix output float, t=0, u=-1 mode data address register,
offset: 0x174 */
__O uint32_t CORDIC_T0UN_ILOX; /**< native cordic input float output fix, t=0, u=-1 mode data address register,
offset: 0x178 */
__O uint32_t CORDIC_T0UN_ILOL; /**< native cordic input float output float, t=0, u=-1 mode data address register,
offset: 0x17C */
__O uint32_t
CORDIC_T1UP_IXOX; /**< native cordic input fix output fix, t=1, u=1 mode data address register, offset: 0x180 */
__O uint32_t CORDIC_T1UP_IXOL; /**< native cordic input fix output float, t=1, u=1 mode data address register,
offset: 0x184 */
__O uint32_t CORDIC_T1UP_ILOX; /**< native cordic input float output fix, t=1, u=1 mode data address register,
offset: 0x188 */
__O uint32_t CORDIC_T1UP_ILOL; /**< native cordic input float output float, t=1, u=1 mode data address register,
offset: 0x18C */
__O uint32_t CORDIC_T1UN_IXOX; /**< native cordic input fix output fix, t=1, u=-1 mode data address register,
offset: 0x190 */
__O uint32_t CORDIC_T1UN_IXOL; /**< native cordic input fix output float, t=1, u=-1 mode data address register,
offset: 0x194 */
__O uint32_t CORDIC_T1UN_ILOX; /**< native cordic input float output fix, t=1, u=-1 mode data address register,
offset: 0x198 */
__O uint32_t CORDIC_T1UN_ILOL; /**< native cordic input float output float, t=1, u=-1 mode data address register,
offset: 0x19C */
} FSP_Type;
/* ----------------------------------------------------------------------------
-- FSP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FSP_Register_Masks FSP Register Masks
* @{
*/
/*! @name SYS_CTRL - FSP system control register */
#define FSP_SYS_CTRL_TE_ABORT_MASK (0x1U)
#define FSP_SYS_CTRL_TE_ABORT_SHIFT (0U)
#define FSP_SYS_CTRL_TE_ABORT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SYS_CTRL_TE_ABORT_SHIFT)) & FSP_SYS_CTRL_TE_ABORT_MASK)
#define FSP_SYS_CTRL_MOU_ABORT_MASK (0x2U)
#define FSP_SYS_CTRL_MOU_ABORT_SHIFT (1U)
#define FSP_SYS_CTRL_MOU_ABORT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SYS_CTRL_MOU_ABORT_SHIFT)) & FSP_SYS_CTRL_MOU_ABORT_MASK)
#define FSP_SYS_CTRL_SCF_ABORT_MASK (0x4U)
#define FSP_SYS_CTRL_SCF_ABORT_SHIFT (2U)
#define FSP_SYS_CTRL_SCF_ABORT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SYS_CTRL_SCF_ABORT_SHIFT)) & FSP_SYS_CTRL_SCF_ABORT_MASK)
/*! @name STATUS - FSP status register */
#define FSP_STATUS_FPU0_BUSY_MASK (0x1U)
#define FSP_STATUS_FPU0_BUSY_SHIFT (0U)
#define FSP_STATUS_FPU0_BUSY(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_STATUS_FPU0_BUSY_SHIFT)) & FSP_STATUS_FPU0_BUSY_MASK)
#define FSP_STATUS_FPU1_BUSY_MASK (0x2U)
#define FSP_STATUS_FPU1_BUSY_SHIFT (1U)
#define FSP_STATUS_FPU1_BUSY(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_STATUS_FPU1_BUSY_SHIFT)) & FSP_STATUS_FPU1_BUSY_MASK)
#define FSP_STATUS_FIR_READY_MASK (0x4U)
#define FSP_STATUS_FIR_READY_SHIFT (2U)
#define FSP_STATUS_FIR_READY(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_STATUS_FIR_READY_SHIFT)) & FSP_STATUS_FIR_READY_MASK)
/*! @name INT - FSP interrupt register */
#define FSP_INT_TE_DONE_INT_MASK (0x1U)
#define FSP_INT_TE_DONE_INT_SHIFT (0U)
#define FSP_INT_TE_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << FSP_INT_TE_DONE_INT_SHIFT)) & FSP_INT_TE_DONE_INT_MASK)
#define FSP_INT_MOU_DONE_INT_MASK (0x2U)
#define FSP_INT_MOU_DONE_INT_SHIFT (1U)
#define FSP_INT_MOU_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_MOU_DONE_INT_SHIFT)) & FSP_INT_MOU_DONE_INT_MASK)
#define FSP_INT_SE_DONE_INT_MASK (0x4U)
#define FSP_INT_SE_DONE_INT_SHIFT (2U)
#define FSP_INT_SE_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << FSP_INT_SE_DONE_INT_SHIFT)) & FSP_INT_SE_DONE_INT_MASK)
#define FSP_INT_COR_DONE_INT_MASK (0x8U)
#define FSP_INT_COR_DONE_INT_SHIFT (3U)
#define FSP_INT_COR_DONE_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_COR_DONE_INT_SHIFT)) & FSP_INT_COR_DONE_INT_MASK)
#define FSP_INT_FPU0_CALC_IN_ERR_INT_MASK (0x100U)
#define FSP_INT_FPU0_CALC_IN_ERR_INT_SHIFT (8U)
#define FSP_INT_FPU0_CALC_IN_ERR_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FPU0_CALC_IN_ERR_INT_SHIFT)) & FSP_INT_FPU0_CALC_IN_ERR_INT_MASK)
#define FSP_INT_FPU0_CALC_OUT_ERR_INT_MASK (0x200U)
#define FSP_INT_FPU0_CALC_OUT_ERR_INT_SHIFT (9U)
#define FSP_INT_FPU0_CALC_OUT_ERR_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FPU0_CALC_OUT_ERR_INT_SHIFT)) & FSP_INT_FPU0_CALC_OUT_ERR_INT_MASK)
#define FSP_INT_FPU0_DIN_OV_INT_MASK (0x400U)
#define FSP_INT_FPU0_DIN_OV_INT_SHIFT (10U)
#define FSP_INT_FPU0_DIN_OV_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FPU0_DIN_OV_INT_SHIFT)) & FSP_INT_FPU0_DIN_OV_INT_MASK)
#define FSP_INT_FPU0_DOUT_OV_INT_MASK (0x800U)
#define FSP_INT_FPU0_DOUT_OV_INT_SHIFT (11U)
#define FSP_INT_FPU0_DOUT_OV_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FPU0_DOUT_OV_INT_SHIFT)) & FSP_INT_FPU0_DOUT_OV_INT_MASK)
#define FSP_INT_SINGULAR_INT_MASK (0x1000U)
#define FSP_INT_SINGULAR_INT_SHIFT (12U)
#define FSP_INT_SINGULAR_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_SINGULAR_INT_SHIFT)) & FSP_INT_SINGULAR_INT_MASK)
#define FSP_INT_FPU1_CALC_IN_ERR_INT_MASK (0x10000U)
#define FSP_INT_FPU1_CALC_IN_ERR_INT_SHIFT (16U)
#define FSP_INT_FPU1_CALC_IN_ERR_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FPU1_CALC_IN_ERR_INT_SHIFT)) & FSP_INT_FPU1_CALC_IN_ERR_INT_MASK)
#define FSP_INT_FPU1_CALC_OUT_ERR_INT_MASK (0x20000U)
#define FSP_INT_FPU1_CALC_OUT_ERR_INT_SHIFT (17U)
#define FSP_INT_FPU1_CALC_OUT_ERR_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FPU1_CALC_OUT_ERR_INT_SHIFT)) & FSP_INT_FPU1_CALC_OUT_ERR_INT_MASK)
#define FSP_INT_FPU1_DIN_OV_INT_MASK (0x40000U)
#define FSP_INT_FPU1_DIN_OV_INT_SHIFT (18U)
#define FSP_INT_FPU1_DIN_OV_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FPU1_DIN_OV_INT_SHIFT)) & FSP_INT_FPU1_DIN_OV_INT_MASK)
#define FSP_INT_FPU1_DOUT_OV_INT_MASK (0x80000U)
#define FSP_INT_FPU1_DOUT_OV_INT_SHIFT (19U)
#define FSP_INT_FPU1_DOUT_OV_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FPU1_DOUT_OV_INT_SHIFT)) & FSP_INT_FPU1_DOUT_OV_INT_MASK)
#define FSP_INT_FINV_DIN_ERR_INT_MASK (0x100000U)
#define FSP_INT_FINV_DIN_ERR_INT_SHIFT (20U)
#define FSP_INT_FINV_DIN_ERR_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FINV_DIN_ERR_INT_SHIFT)) & FSP_INT_FINV_DIN_ERR_INT_MASK)
#define FSP_INT_FINV_DOUT_OV_INT_MASK (0x200000U)
#define FSP_INT_FINV_DOUT_OV_INT_SHIFT (21U)
#define FSP_INT_FINV_DOUT_OV_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FINV_DOUT_OV_INT_SHIFT)) & FSP_INT_FINV_DOUT_OV_INT_MASK)
#define FSP_INT_FINV_ZERO_INT_MASK (0x400000U)
#define FSP_INT_FINV_ZERO_INT_SHIFT (22U)
#define FSP_INT_FINV_ZERO_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_FINV_ZERO_INT_SHIFT)) & FSP_INT_FINV_ZERO_INT_MASK)
#define FSP_INT_CORDIC_DIN_ERR_MASK (0x1000000U)
#define FSP_INT_CORDIC_DIN_ERR_SHIFT (24U)
#define FSP_INT_CORDIC_DIN_ERR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_CORDIC_DIN_ERR_SHIFT)) & FSP_INT_CORDIC_DIN_ERR_MASK)
#define FSP_INT_CORDIC_DOUT_ERR_INT_MASK (0x2000000U)
#define FSP_INT_CORDIC_DOUT_ERR_INT_SHIFT (25U)
#define FSP_INT_CORDIC_DOUT_ERR_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_CORDIC_DOUT_ERR_INT_SHIFT)) & FSP_INT_CORDIC_DOUT_ERR_INT_MASK)
#define FSP_INT_CORDIC_CALC_ERR_INT_MASK (0x4000000U)
#define FSP_INT_CORDIC_CALC_ERR_INT_SHIFT (26U)
#define FSP_INT_CORDIC_CALC_ERR_INT(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INT_CORDIC_CALC_ERR_INT_SHIFT)) & FSP_INT_CORDIC_CALC_ERR_INT_MASK)
#define FSP_INT_FSP_INT_MASK (0x80000000U)
#define FSP_INT_FSP_INT_SHIFT (31U)
#define FSP_INT_FSP_INT(x) (((uint32_t)(((uint32_t)(x)) << FSP_INT_FSP_INT_SHIFT)) & FSP_INT_FSP_INT_MASK)
/*! @name INTEN - FSP interrupt enable register */
#define FSP_INTEN_TE_DONE_INTEN_MASK (0x1U)
#define FSP_INTEN_TE_DONE_INTEN_SHIFT (0U)
#define FSP_INTEN_TE_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_TE_DONE_INTEN_SHIFT)) & FSP_INTEN_TE_DONE_INTEN_MASK)
#define FSP_INTEN_MOU_DONE_INTEN_MASK (0x2U)
#define FSP_INTEN_MOU_DONE_INTEN_SHIFT (1U)
#define FSP_INTEN_MOU_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_MOU_DONE_INTEN_SHIFT)) & FSP_INTEN_MOU_DONE_INTEN_MASK)
#define FSP_INTEN_SE_DONE_INTEN_MASK (0x4U)
#define FSP_INTEN_SE_DONE_INTEN_SHIFT (2U)
#define FSP_INTEN_SE_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_SE_DONE_INTEN_SHIFT)) & FSP_INTEN_SE_DONE_INTEN_MASK)
#define FSP_INTEN_COR_DONE_INTEN_MASK (0x8U)
#define FSP_INTEN_COR_DONE_INTEN_SHIFT (3U)
#define FSP_INTEN_COR_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_COR_DONE_INTEN_SHIFT)) & FSP_INTEN_COR_DONE_INTEN_MASK)
#define FSP_INTEN_FPU0_CALC_IN_ERR_INTEN_MASK (0x100U)
#define FSP_INTEN_FPU0_CALC_IN_ERR_INTEN_SHIFT (8U)
#define FSP_INTEN_FPU0_CALC_IN_ERR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FPU0_CALC_IN_ERR_INTEN_SHIFT)) & FSP_INTEN_FPU0_CALC_IN_ERR_INTEN_MASK)
#define FSP_INTEN_FPU0_CALC_OUT_ERR_INTEN_MASK (0x200U)
#define FSP_INTEN_FPU0_CALC_OUT_ERR_INTEN_SHIFT (9U)
#define FSP_INTEN_FPU0_CALC_OUT_ERR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FPU0_CALC_OUT_ERR_INTEN_SHIFT)) & FSP_INTEN_FPU0_CALC_OUT_ERR_INTEN_MASK)
#define FSP_INTEN_FPU0_DIN_OV_INTEN_MASK (0x400U)
#define FSP_INTEN_FPU0_DIN_OV_INTEN_SHIFT (10U)
#define FSP_INTEN_FPU0_DIN_OV_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FPU0_DIN_OV_INTEN_SHIFT)) & FSP_INTEN_FPU0_DIN_OV_INTEN_MASK)
#define FSP_INTEN_FPU0_DOUT_OV_INTEN_MASK (0x800U)
#define FSP_INTEN_FPU0_DOUT_OV_INTEN_SHIFT (11U)
#define FSP_INTEN_FPU0_DOUT_OV_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FPU0_DOUT_OV_INTEN_SHIFT)) & FSP_INTEN_FPU0_DOUT_OV_INTEN_MASK)
#define FSP_INTEN_SINGULAR_INTEN_MASK (0x1000U)
#define FSP_INTEN_SINGULAR_INTEN_SHIFT (12U)
#define FSP_INTEN_SINGULAR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_SINGULAR_INTEN_SHIFT)) & FSP_INTEN_SINGULAR_INTEN_MASK)
#define FSP_INTEN_FPU1_CALC_IN_ERR_INTEN_MASK (0x10000U)
#define FSP_INTEN_FPU1_CALC_IN_ERR_INTEN_SHIFT (16U)
#define FSP_INTEN_FPU1_CALC_IN_ERR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FPU1_CALC_IN_ERR_INTEN_SHIFT)) & FSP_INTEN_FPU1_CALC_IN_ERR_INTEN_MASK)
#define FSP_INTEN_FPU1_CALC_OUT_ERR_INTEN_MASK (0x20000U)
#define FSP_INTEN_FPU1_CALC_OUT_ERR_INTEN_SHIFT (17U)
#define FSP_INTEN_FPU1_CALC_OUT_ERR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FPU1_CALC_OUT_ERR_INTEN_SHIFT)) & FSP_INTEN_FPU1_CALC_OUT_ERR_INTEN_MASK)
#define FSP_INTEN_FPU1_DIN_OV_INTEN_MASK (0x40000U)
#define FSP_INTEN_FPU1_DIN_OV_INTEN_SHIFT (18U)
#define FSP_INTEN_FPU1_DIN_OV_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FPU1_DIN_OV_INTEN_SHIFT)) & FSP_INTEN_FPU1_DIN_OV_INTEN_MASK)
#define FSP_INTEN_FPU1_DOUT_OV_INTEN_MASK (0x80000U)
#define FSP_INTEN_FPU1_DOUT_OV_INTEN_SHIFT (19U)
#define FSP_INTEN_FPU1_DOUT_OV_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FPU1_DOUT_OV_INTEN_SHIFT)) & FSP_INTEN_FPU1_DOUT_OV_INTEN_MASK)
#define FSP_INTEN_FINV_DIN_ERR_INTEN_MASK (0x100000U)
#define FSP_INTEN_FINV_DIN_ERR_INTEN_SHIFT (20U)
#define FSP_INTEN_FINV_DIN_ERR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FINV_DIN_ERR_INTEN_SHIFT)) & FSP_INTEN_FINV_DIN_ERR_INTEN_MASK)
#define FSP_INTEN_FINV_DOUT_OV_INTEN_MASK (0x200000U)
#define FSP_INTEN_FINV_DOUT_OV_INTEN_SHIFT (21U)
#define FSP_INTEN_FINV_DOUT_OV_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FINV_DOUT_OV_INTEN_SHIFT)) & FSP_INTEN_FINV_DOUT_OV_INTEN_MASK)
#define FSP_INTEN_FINV_ZERO_INTEN_MASK (0x400000U)
#define FSP_INTEN_FINV_ZERO_INTEN_SHIFT (22U)
#define FSP_INTEN_FINV_ZERO_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FINV_ZERO_INTEN_SHIFT)) & FSP_INTEN_FINV_ZERO_INTEN_MASK)
#define FSP_INTEN_CORDIC_DIN_ERR_INTEN_MASK (0x1000000U)
#define FSP_INTEN_CORDIC_DIN_ERR_INTEN_SHIFT (24U)
#define FSP_INTEN_CORDIC_DIN_ERR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_CORDIC_DIN_ERR_INTEN_SHIFT)) & FSP_INTEN_CORDIC_DIN_ERR_INTEN_MASK)
#define FSP_INTEN_CORDIC_DOUT_ERR_INTEN_MASK (0x2000000U)
#define FSP_INTEN_CORDIC_DOUT_ERR_INTEN_SHIFT (25U)
#define FSP_INTEN_CORDIC_DOUT_ERR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_CORDIC_DOUT_ERR_INTEN_SHIFT)) & FSP_INTEN_CORDIC_DOUT_ERR_INTEN_MASK)
#define FSP_INTEN_CORDIC_CALC_ERR_INTEN_MASK (0x4000000U)
#define FSP_INTEN_CORDIC_CALC_ERR_INTEN_SHIFT (26U)
#define FSP_INTEN_CORDIC_CALC_ERR_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_INTEN_CORDIC_CALC_ERR_INTEN_SHIFT)) & FSP_INTEN_CORDIC_CALC_ERR_INTEN_MASK)
#define FSP_INTEN_FSP_INTEN_MASK (0x80000000U)
#define FSP_INTEN_FSP_INTEN_SHIFT (31U)
#define FSP_INTEN_FSP_INTEN(x) (((uint32_t)(((uint32_t)(x)) << FSP_INTEN_FSP_INTEN_SHIFT)) & FSP_INTEN_FSP_INTEN_MASK)
/*! @name TE_CTRL - transmit engine control register */
#define FSP_TE_CTRL_TE_MODE_MASK (0x3U)
#define FSP_TE_CTRL_TE_MODE_SHIFT (0U)
#define FSP_TE_CTRL_TE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FSP_TE_CTRL_TE_MODE_SHIFT)) & FSP_TE_CTRL_TE_MODE_MASK)
#define FSP_TE_CTRL_TE_IO_MODE_MASK (0xCU)
#define FSP_TE_CTRL_TE_IO_MODE_SHIFT (2U)
#define FSP_TE_CTRL_TE_IO_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_TE_CTRL_TE_IO_MODE_SHIFT)) & FSP_TE_CTRL_TE_IO_MODE_MASK)
#define FSP_TE_CTRL_TE_PTS_MASK (0x30U)
#define FSP_TE_CTRL_TE_PTS_SHIFT (4U)
#define FSP_TE_CTRL_TE_PTS(x) (((uint32_t)(((uint32_t)(x)) << FSP_TE_CTRL_TE_PTS_SHIFT)) & FSP_TE_CTRL_TE_PTS_MASK)
#define FSP_TE_CTRL_TE_DIN_FP_SEL_MASK (0x40U)
#define FSP_TE_CTRL_TE_DIN_FP_SEL_SHIFT (6U)
#define FSP_TE_CTRL_TE_DIN_FP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_TE_CTRL_TE_DIN_FP_SEL_SHIFT)) & FSP_TE_CTRL_TE_DIN_FP_SEL_MASK)
#define FSP_TE_CTRL_TE_DOUT_FP_SEL_MASK (0x80U)
#define FSP_TE_CTRL_TE_DOUT_FP_SEL_SHIFT (7U)
#define FSP_TE_CTRL_TE_DOUT_FP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_TE_CTRL_TE_DOUT_FP_SEL_SHIFT)) & FSP_TE_CTRL_TE_DOUT_FP_SEL_MASK)
#define FSP_TE_CTRL_TE_SCALE_MASK (0xFF00U)
#define FSP_TE_CTRL_TE_SCALE_SHIFT (8U)
#define FSP_TE_CTRL_TE_SCALE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_TE_CTRL_TE_SCALE_SHIFT)) & FSP_TE_CTRL_TE_SCALE_MASK)
#define FSP_TE_CTRL_TE_PAUSE_LVL_MASK (0x7000000U)
#define FSP_TE_CTRL_TE_PAUSE_LVL_SHIFT (24U)
#define FSP_TE_CTRL_TE_PAUSE_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_TE_CTRL_TE_PAUSE_LVL_SHIFT)) & FSP_TE_CTRL_TE_PAUSE_LVL_MASK)
/*! @name TE_SRC_BASE - transfer engine source data memory base register */
#define FSP_TE_SRC_BASE_TE_SRC_BASE_MASK (0x1FFFFU)
#define FSP_TE_SRC_BASE_TE_SRC_BASE_SHIFT (0U)
#define FSP_TE_SRC_BASE_TE_SRC_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_TE_SRC_BASE_TE_SRC_BASE_SHIFT)) & FSP_TE_SRC_BASE_TE_SRC_BASE_MASK)
/*! @name TE_DST_BASE - transfer engine destination data memory base register */
#define FSP_TE_DST_BASE_TE_DST_BASE_MASK (0x1FFFFU)
#define FSP_TE_DST_BASE_TE_DST_BASE_SHIFT (0U)
#define FSP_TE_DST_BASE_TE_DST_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_TE_DST_BASE_TE_DST_BASE_SHIFT)) & FSP_TE_DST_BASE_TE_DST_BASE_MASK)
/*! @name MOU_CTRL - matrix operation unit control register */
#define FSP_MOU_CTRL_OP_MODE_MASK (0xFU)
#define FSP_MOU_CTRL_OP_MODE_SHIFT (0U)
#define FSP_MOU_CTRL_OP_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_OP_MODE_SHIFT)) & FSP_MOU_CTRL_OP_MODE_MASK)
#define FSP_MOU_CTRL_MOU_DIN_FP_SEL_MASK (0x100U)
#define FSP_MOU_CTRL_MOU_DIN_FP_SEL_SHIFT (8U)
#define FSP_MOU_CTRL_MOU_DIN_FP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_MOU_DIN_FP_SEL_SHIFT)) & FSP_MOU_CTRL_MOU_DIN_FP_SEL_MASK)
#define FSP_MOU_CTRL_MOU_DOUT_FP_SEL_MASK (0x200U)
#define FSP_MOU_CTRL_MOU_DOUT_FP_SEL_SHIFT (9U)
#define FSP_MOU_CTRL_MOU_DOUT_FP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_MOU_DOUT_FP_SEL_SHIFT)) & FSP_MOU_CTRL_MOU_DOUT_FP_SEL_MASK)
#define FSP_MOU_CTRL_MAT_M_MASK (0xF0000U)
#define FSP_MOU_CTRL_MAT_M_SHIFT (16U)
#define FSP_MOU_CTRL_MAT_M(x) (((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_MAT_M_SHIFT)) & FSP_MOU_CTRL_MAT_M_MASK)
#define FSP_MOU_CTRL_MAT_N_MASK (0xF00000U)
#define FSP_MOU_CTRL_MAT_N_SHIFT (20U)
#define FSP_MOU_CTRL_MAT_N(x) (((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_MAT_N_SHIFT)) & FSP_MOU_CTRL_MAT_N_MASK)
#define FSP_MOU_CTRL_MAT_K_MASK (0xF000000U)
#define FSP_MOU_CTRL_MAT_K_SHIFT (24U)
#define FSP_MOU_CTRL_MAT_K(x) (((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_MAT_K_SHIFT)) & FSP_MOU_CTRL_MAT_K_MASK)
#define FSP_MOU_CTRL_DIV_EPSILON_MASK (0x30000000U)
#define FSP_MOU_CTRL_DIV_EPSILON_SHIFT (28U)
#define FSP_MOU_CTRL_DIV_EPSILON(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_DIV_EPSILON_SHIFT)) & FSP_MOU_CTRL_DIV_EPSILON_MASK)
#define FSP_MOU_CTRL_LU_STOP_MASK (0x40000000U)
#define FSP_MOU_CTRL_LU_STOP_SHIFT (30U)
#define FSP_MOU_CTRL_LU_STOP(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_LU_STOP_SHIFT)) & FSP_MOU_CTRL_LU_STOP_MASK)
#define FSP_MOU_CTRL_UINV_STOP_MASK (0x80000000U)
#define FSP_MOU_CTRL_UINV_STOP_SHIFT (31U)
#define FSP_MOU_CTRL_UINV_STOP(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MOU_CTRL_UINV_STOP_SHIFT)) & FSP_MOU_CTRL_UINV_STOP_MASK)
/*! @name MA_SRC_BASE - matrix A source data memory base register */
#define FSP_MA_SRC_BASE_MA_SRC_BASE_MASK (0x1FFFFU)
#define FSP_MA_SRC_BASE_MA_SRC_BASE_SHIFT (0U)
#define FSP_MA_SRC_BASE_MA_SRC_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MA_SRC_BASE_MA_SRC_BASE_SHIFT)) & FSP_MA_SRC_BASE_MA_SRC_BASE_MASK)
/*! @name MB_SRC_BASE - matrix B source data memory base register */
#define FSP_MB_SRC_BASE_MB_SRC_BASE_MASK (0x1FFFFU)
#define FSP_MB_SRC_BASE_MB_SRC_BASE_SHIFT (0U)
#define FSP_MB_SRC_BASE_MB_SRC_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MB_SRC_BASE_MB_SRC_BASE_SHIFT)) & FSP_MB_SRC_BASE_MB_SRC_BASE_MASK)
/*! @name MO_DST_BASE - matrix output data memory base register */
#define FSP_MO_DST_BASE_MO_DST_BASE_MASK (0x1FFFFU)
#define FSP_MO_DST_BASE_MO_DST_BASE_SHIFT (0U)
#define FSP_MO_DST_BASE_MO_DST_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MO_DST_BASE_MO_DST_BASE_SHIFT)) & FSP_MO_DST_BASE_MO_DST_BASE_MASK)
/*! @name MOU_SCALEA - scale coefficient A register */
#define FSP_MOU_SCALEA_MOU_SCALEA_MASK (0xFFFFFFFFU)
#define FSP_MOU_SCALEA_MOU_SCALEA_SHIFT (0U)
#define FSP_MOU_SCALEA_MOU_SCALEA(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MOU_SCALEA_MOU_SCALEA_SHIFT)) & FSP_MOU_SCALEA_MOU_SCALEA_MASK)
/*! @name MOU_SCALEB - scale coefficient B register */
#define FSP_MOU_SCALEB_MOU_SCALEB_MASK (0xFFFFFFFFU)
#define FSP_MOU_SCALEB_MOU_SCALEB_SHIFT (0U)
#define FSP_MOU_SCALEB_MOU_SCALEB(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_MOU_SCALEB_MOU_SCALEB_SHIFT)) & FSP_MOU_SCALEB_MOU_SCALEB_MASK)
/*! @name SE_CTRL - stastic engine control register */
#define FSP_SE_CTRL_MIN_SEL_MASK (0x1U)
#define FSP_SE_CTRL_MIN_SEL_SHIFT (0U)
#define FSP_SE_CTRL_MIN_SEL(x) (((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_MIN_SEL_SHIFT)) & FSP_SE_CTRL_MIN_SEL_MASK)
#define FSP_SE_CTRL_MAX_SEL_MASK (0x2U)
#define FSP_SE_CTRL_MAX_SEL_SHIFT (1U)
#define FSP_SE_CTRL_MAX_SEL(x) (((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_MAX_SEL_SHIFT)) & FSP_SE_CTRL_MAX_SEL_MASK)
#define FSP_SE_CTRL_MIN_IDX_EN_MASK (0x4U)
#define FSP_SE_CTRL_MIN_IDX_EN_SHIFT (2U)
#define FSP_SE_CTRL_MIN_IDX_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_MIN_IDX_EN_SHIFT)) & FSP_SE_CTRL_MIN_IDX_EN_MASK)
#define FSP_SE_CTRL_MAX_IDX_EN_MASK (0x8U)
#define FSP_SE_CTRL_MAX_IDX_EN_SHIFT (3U)
#define FSP_SE_CTRL_MAX_IDX_EN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_MAX_IDX_EN_SHIFT)) & FSP_SE_CTRL_MAX_IDX_EN_MASK)
#define FSP_SE_CTRL_SUM_EN_MASK (0x10U)
#define FSP_SE_CTRL_SUM_EN_SHIFT (4U)
#define FSP_SE_CTRL_SUM_EN(x) (((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_SUM_EN_SHIFT)) & FSP_SE_CTRL_SUM_EN_MASK)
#define FSP_SE_CTRL_PWR_EN_MASK (0x20U)
#define FSP_SE_CTRL_PWR_EN_SHIFT (5U)
#define FSP_SE_CTRL_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_PWR_EN_SHIFT)) & FSP_SE_CTRL_PWR_EN_MASK)
#define FSP_SE_CTRL_SE_DIN_FP_SEL_MASK (0x40U)
#define FSP_SE_CTRL_SE_DIN_FP_SEL_SHIFT (6U)
#define FSP_SE_CTRL_SE_DIN_FP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_SE_DIN_FP_SEL_SHIFT)) & FSP_SE_CTRL_SE_DIN_FP_SEL_MASK)
#define FSP_SE_CTRL_SE_DOUT_FP_SEL_MASK (0x80U)
#define FSP_SE_CTRL_SE_DOUT_FP_SEL_SHIFT (7U)
#define FSP_SE_CTRL_SE_DOUT_FP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_SE_DOUT_FP_SEL_SHIFT)) & FSP_SE_CTRL_SE_DOUT_FP_SEL_MASK)
#define FSP_SE_CTRL_SE_LEN_MASK (0xFF0000U)
#define FSP_SE_CTRL_SE_LEN_SHIFT (16U)
#define FSP_SE_CTRL_SE_LEN(x) (((uint32_t)(((uint32_t)(x)) << FSP_SE_CTRL_SE_LEN_SHIFT)) & FSP_SE_CTRL_SE_LEN_MASK)
/*! @name SE_SRC_BASE - statistic engine source data base register */
#define FSP_SE_SRC_BASE_SE_SRC_BASE_MASK (0x1FFFFU)
#define FSP_SE_SRC_BASE_SE_SRC_BASE_SHIFT (0U)
#define FSP_SE_SRC_BASE_SE_SRC_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SE_SRC_BASE_SE_SRC_BASE_SHIFT)) & FSP_SE_SRC_BASE_SE_SRC_BASE_MASK)
/*! @name SE_IDX - max or min data index register */
#define FSP_SE_IDX_SE_MIN_IDX_MASK (0xFFU)
#define FSP_SE_IDX_SE_MIN_IDX_SHIFT (0U)
#define FSP_SE_IDX_SE_MIN_IDX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SE_IDX_SE_MIN_IDX_SHIFT)) & FSP_SE_IDX_SE_MIN_IDX_MASK)
#define FSP_SE_IDX_SE_MAX_IDX_MASK (0xFF0000U)
#define FSP_SE_IDX_SE_MAX_IDX_SHIFT (16U)
#define FSP_SE_IDX_SE_MAX_IDX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SE_IDX_SE_MAX_IDX_SHIFT)) & FSP_SE_IDX_SE_MAX_IDX_MASK)
/*! @name SE_SUM - array summary result register */
#define FSP_SE_SUM_SE_SUM_MASK (0xFFFFFFFFU)
#define FSP_SE_SUM_SE_SUM_SHIFT (0U)
#define FSP_SE_SUM_SE_SUM(x) (((uint32_t)(((uint32_t)(x)) << FSP_SE_SUM_SE_SUM_SHIFT)) & FSP_SE_SUM_SE_SUM_MASK)
/*! @name SE_PWR - array power result register */
#define FSP_SE_PWR_SE_PWR_MASK (0xFFFFFFFFU)
#define FSP_SE_PWR_SE_PWR_SHIFT (0U)
#define FSP_SE_PWR_SE_PWR(x) (((uint32_t)(((uint32_t)(x)) << FSP_SE_PWR_SE_PWR_SHIFT)) & FSP_SE_PWR_SE_PWR_MASK)
/*! @name COR_CTRL - correlation control register */
#define FSP_COR_CTRL_COR_DIN_FP_SEL_MASK (0x100U)
#define FSP_COR_CTRL_COR_DIN_FP_SEL_SHIFT (8U)
#define FSP_COR_CTRL_COR_DIN_FP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_COR_CTRL_COR_DIN_FP_SEL_SHIFT)) & FSP_COR_CTRL_COR_DIN_FP_SEL_MASK)
#define FSP_COR_CTRL_COR_DOUT_FP_SEL_MASK (0x200U)
#define FSP_COR_CTRL_COR_DOUT_FP_SEL_SHIFT (9U)
#define FSP_COR_CTRL_COR_DOUT_FP_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_COR_CTRL_COR_DOUT_FP_SEL_SHIFT)) & FSP_COR_CTRL_COR_DOUT_FP_SEL_MASK)
#define FSP_COR_CTRL_COR_X_LEN_MASK (0xFF0000U)
#define FSP_COR_CTRL_COR_X_LEN_SHIFT (16U)
#define FSP_COR_CTRL_COR_X_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_COR_CTRL_COR_X_LEN_SHIFT)) & FSP_COR_CTRL_COR_X_LEN_MASK)
#define FSP_COR_CTRL_COR_Y_LEN_MASK (0xFF000000U)
#define FSP_COR_CTRL_COR_Y_LEN_SHIFT (24U)
#define FSP_COR_CTRL_COR_Y_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_COR_CTRL_COR_Y_LEN_SHIFT)) & FSP_COR_CTRL_COR_Y_LEN_MASK)
/*! @name CX_SRC_BASE - correlation x sequence base register */
#define FSP_CX_SRC_BASE_COR_X_ADDR_MASK (0x1FFFFU)
#define FSP_CX_SRC_BASE_COR_X_ADDR_SHIFT (0U)
#define FSP_CX_SRC_BASE_COR_X_ADDR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CX_SRC_BASE_COR_X_ADDR_SHIFT)) & FSP_CX_SRC_BASE_COR_X_ADDR_MASK)
/*! @name CY_SRC_BASE - correlation y sequence base register */
#define FSP_CY_SRC_BASE_COR_Y_ADDR_MASK (0x1FFFFU)
#define FSP_CY_SRC_BASE_COR_Y_ADDR_SHIFT (0U)
#define FSP_CY_SRC_BASE_COR_Y_ADDR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CY_SRC_BASE_COR_Y_ADDR_SHIFT)) & FSP_CY_SRC_BASE_COR_Y_ADDR_MASK)
/*! @name CO_DST_BASE - correlation output sequence base register */
#define FSP_CO_DST_BASE_COR_DST_BASE_MASK (0x1FFFFU)
#define FSP_CO_DST_BASE_COR_DST_BASE_SHIFT (0U)
#define FSP_CO_DST_BASE_COR_DST_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CO_DST_BASE_COR_DST_BASE_SHIFT)) & FSP_CO_DST_BASE_COR_DST_BASE_MASK)
/*! @name COR_OFFSET - correlation offset register */
#define FSP_COR_OFFSET_COR_X_OFFSET_MASK (0xFFU)
#define FSP_COR_OFFSET_COR_X_OFFSET_SHIFT (0U)
#define FSP_COR_OFFSET_COR_X_OFFSET(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_COR_OFFSET_COR_X_OFFSET_SHIFT)) & FSP_COR_OFFSET_COR_X_OFFSET_MASK)
#define FSP_COR_OFFSET_COR_Y_OFFSET_MASK (0xFF00U)
#define FSP_COR_OFFSET_COR_Y_OFFSET_SHIFT (8U)
#define FSP_COR_OFFSET_COR_Y_OFFSET(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_COR_OFFSET_COR_Y_OFFSET_SHIFT)) & FSP_COR_OFFSET_COR_Y_OFFSET_MASK)
/*! @name FIR_CFG_CH0 - FIR channel 0 configuration register */
#define FSP_FIR_CFG_CH0_FIR_CH0_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH0_FIR_CH0_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH0_FIR_CH0_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH0_FIR_CH0_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH0_FIR_CH0_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH0_FIR_CH0_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH0_FIR_CH0_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH0_FIR_CH0_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH0_FIR_CH0_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH0_FIR_CH0_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH0_FIR_BUF_CLR_ALL_MASK (0x40000000U)
#define FSP_FIR_CFG_CH0_FIR_BUF_CLR_ALL_SHIFT (30U)
#define FSP_FIR_CFG_CH0_FIR_BUF_CLR_ALL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH0_FIR_BUF_CLR_ALL_SHIFT)) & FSP_FIR_CFG_CH0_FIR_BUF_CLR_ALL_MASK)
#define FSP_FIR_CFG_CH0_FIR_CH0_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH0_FIR_CH0_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH0_FIR_CH0_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH0_FIR_CH0_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH0_FIR_CH0_BUF_CLR_MASK)
/*! @name FIR_CFG_CH1 - FIR channel 1 configuration register */
#define FSP_FIR_CFG_CH1_FIR_CH1_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH1_FIR_CH1_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH1_FIR_CH1_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH1_FIR_CH1_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH1_FIR_CH1_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH1_FIR_CH1_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH1_FIR_CH1_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH1_FIR_CH1_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH1_FIR_CH1_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH1_FIR_CH1_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH1_FIR_CH1_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH1_FIR_CH1_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH1_FIR_CH1_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH1_FIR_CH1_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH1_FIR_CH1_BUF_CLR_MASK)
/*! @name FIR_CFG_CH2 - FIR channel 2 configuration register */
#define FSP_FIR_CFG_CH2_FIR_CH2_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH2_FIR_CH2_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH2_FIR_CH2_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH2_FIR_CH2_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH2_FIR_CH2_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH2_FIR_CH2_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH2_FIR_CH2_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH2_FIR_CH2_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH2_FIR_CH2_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH2_FIR_CH2_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH2_FIR_CH2_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH2_FIR_CH2_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH2_FIR_CH2_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH2_FIR_CH2_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH2_FIR_CH2_BUF_CLR_MASK)
/*! @name FIR_CFG_CH3 - FIR channel 3 configuration register */
#define FSP_FIR_CFG_CH3_FIR_CH3_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH3_FIR_CH3_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH3_FIR_CH3_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH3_FIR_CH3_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH3_FIR_CH3_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH3_FIR_CH3_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH3_FIR_CH3_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH3_FIR_CH3_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH3_FIR_CH3_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH3_FIR_CH3_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH3_FIR_CH3_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH3_FIR_CH3_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH3_FIR_CH3_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH3_FIR_CH3_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH3_FIR_CH3_BUF_CLR_MASK)
/*! @name FIR_CFG_CH4 - FIR channel 4 configuration register */
#define FSP_FIR_CFG_CH4_FIR_CH4_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH4_FIR_CH4_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH4_FIR_CH4_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH4_FIR_CH4_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH4_FIR_CH4_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH4_FIR_CH4_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH4_FIR_CH4_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH4_FIR_CH4_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH4_FIR_CH4_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH4_FIR_CH4_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH4_FIR_CH4_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH4_FIR_CH4_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH4_FIR_CH4_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH4_FIR_CH4_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH4_FIR_CH4_BUF_CLR_MASK)
/*! @name FIR_CFG_CH5 - FIR channel 5 configuration register */
#define FSP_FIR_CFG_CH5_FIR_CH5_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH5_FIR_CH5_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH5_FIR_CH5_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH5_FIR_CH5_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH5_FIR_CH5_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH5_FIR_CH5_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH5_FIR_CH5_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH5_FIR_CH5_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH5_FIR_CH5_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH5_FIR_CH5_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH5_FIR_CH5_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH5_FIR_CH5_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH5_FIR_CH5_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH5_FIR_CH5_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH5_FIR_CH5_BUF_CLR_MASK)
/*! @name FIR_CFG_CH6 - FIR channel 6 configuration register */
#define FSP_FIR_CFG_CH6_FIR_CH6_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH6_FIR_CH6_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH6_FIR_CH6_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH6_FIR_CH6_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH6_FIR_CH6_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH6_FIR_CH6_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH6_FIR_CH6_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH6_FIR_CH6_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH6_FIR_CH6_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH6_FIR_CH6_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH6_FIR_CH6_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH6_FIR_CH6_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH6_FIR_CH6_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH6_FIR_CH6_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH6_FIR_CH6_BUF_CLR_MASK)
/*! @name FIR_CFG_CH7 - FIR channel 7 configuration register */
#define FSP_FIR_CFG_CH7_FIR_CH7_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH7_FIR_CH7_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH7_FIR_CH7_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH7_FIR_CH7_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH7_FIR_CH7_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH7_FIR_CH7_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH7_FIR_CH7_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH7_FIR_CH7_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH7_FIR_CH7_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH7_FIR_CH7_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH7_FIR_CH7_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH7_FIR_CH7_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH7_FIR_CH7_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH7_FIR_CH7_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH7_FIR_CH7_BUF_CLR_MASK)
/*! @name FIR_CFG_CH8 - FIR channel 8 configuration register */
#define FSP_FIR_CFG_CH8_FIR_CH8_COEF_BASE_MASK (0xFFFFU)
#define FSP_FIR_CFG_CH8_FIR_CH8_COEF_BASE_SHIFT (0U)
#define FSP_FIR_CFG_CH8_FIR_CH8_COEF_BASE(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH8_FIR_CH8_COEF_BASE_SHIFT)) & FSP_FIR_CFG_CH8_FIR_CH8_COEF_BASE_MASK)
#define FSP_FIR_CFG_CH8_FIR_CH8_TAP_LEN_MASK (0xF0000U)
#define FSP_FIR_CFG_CH8_FIR_CH8_TAP_LEN_SHIFT (16U)
#define FSP_FIR_CFG_CH8_FIR_CH8_TAP_LEN(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH8_FIR_CH8_TAP_LEN_SHIFT)) & FSP_FIR_CFG_CH8_FIR_CH8_TAP_LEN_MASK)
#define FSP_FIR_CFG_CH8_FIR_CH8_BUF_CLR_MASK (0x80000000U)
#define FSP_FIR_CFG_CH8_FIR_CH8_BUF_CLR_SHIFT (31U)
#define FSP_FIR_CFG_CH8_FIR_CH8_BUF_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_CFG_CH8_FIR_CH8_BUF_CLR_SHIFT)) & FSP_FIR_CFG_CH8_FIR_CH8_BUF_CLR_MASK)
/*! @name FIR_DAT0_FX - FIR channel 0 fix point data input & output register */
#define FSP_FIR_DAT0_FX_FIR_DAT0_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT0_FX_FIR_DAT0_FX_SHIFT (0U)
#define FSP_FIR_DAT0_FX_FIR_DAT0_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT0_FX_FIR_DAT0_FX_SHIFT)) & FSP_FIR_DAT0_FX_FIR_DAT0_FX_MASK)
/*! @name FIR_DAT1_FX - FIR channel 1 fix point data input & output register */
#define FSP_FIR_DAT1_FX_FIR_DAT1_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT1_FX_FIR_DAT1_FX_SHIFT (0U)
#define FSP_FIR_DAT1_FX_FIR_DAT1_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT1_FX_FIR_DAT1_FX_SHIFT)) & FSP_FIR_DAT1_FX_FIR_DAT1_FX_MASK)
/*! @name FIR_DAT2_FX - FIR channel 2 fix point data input & output register */
#define FSP_FIR_DAT2_FX_FIR_DAT2_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT2_FX_FIR_DAT2_FX_SHIFT (0U)
#define FSP_FIR_DAT2_FX_FIR_DAT2_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT2_FX_FIR_DAT2_FX_SHIFT)) & FSP_FIR_DAT2_FX_FIR_DAT2_FX_MASK)
/*! @name FIR_DAT3_FX - FIR channel 3 fix point data input & output register */
#define FSP_FIR_DAT3_FX_FIR_DAT3_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT3_FX_FIR_DAT3_FX_SHIFT (0U)
#define FSP_FIR_DAT3_FX_FIR_DAT3_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT3_FX_FIR_DAT3_FX_SHIFT)) & FSP_FIR_DAT3_FX_FIR_DAT3_FX_MASK)
/*! @name FIR_DAT4_FX - FIR channel 4 fix point data input & output register */
#define FSP_FIR_DAT4_FX_FIR_DAT4_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT4_FX_FIR_DAT4_FX_SHIFT (0U)
#define FSP_FIR_DAT4_FX_FIR_DAT4_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT4_FX_FIR_DAT4_FX_SHIFT)) & FSP_FIR_DAT4_FX_FIR_DAT4_FX_MASK)
/*! @name FIR_DAT5_FX - FIR channel 5 fix point data input & output register */
#define FSP_FIR_DAT5_FX_FIR_DAT5_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT5_FX_FIR_DAT5_FX_SHIFT (0U)
#define FSP_FIR_DAT5_FX_FIR_DAT5_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT5_FX_FIR_DAT5_FX_SHIFT)) & FSP_FIR_DAT5_FX_FIR_DAT5_FX_MASK)
/*! @name FIR_DAT6_FX - FIR channel 6 fix point data input & output register */
#define FSP_FIR_DAT6_FX_FIR_DAT6_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT6_FX_FIR_DAT6_FX_SHIFT (0U)
#define FSP_FIR_DAT6_FX_FIR_DAT6_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT6_FX_FIR_DAT6_FX_SHIFT)) & FSP_FIR_DAT6_FX_FIR_DAT6_FX_MASK)
/*! @name FIR_DAT7_FX - FIR channel 7 fix point data input & output register */
#define FSP_FIR_DAT7_FX_FIR_DAT7_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT7_FX_FIR_DAT7_FX_SHIFT (0U)
#define FSP_FIR_DAT7_FX_FIR_DAT7_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT7_FX_FIR_DAT7_FX_SHIFT)) & FSP_FIR_DAT7_FX_FIR_DAT7_FX_MASK)
/*! @name FIR_DAT8_FX - FIR channel 8 fix point data input & output register */
#define FSP_FIR_DAT8_FX_FIR_DAT8_FX_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT8_FX_FIR_DAT8_FX_SHIFT (0U)
#define FSP_FIR_DAT8_FX_FIR_DAT8_FX(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT8_FX_FIR_DAT8_FX_SHIFT)) & FSP_FIR_DAT8_FX_FIR_DAT8_FX_MASK)
/*! @name FIR_DAT0_FL - FIR channel 0 float point data input & output register */
#define FSP_FIR_DAT0_FL_FIR_DAT0_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT0_FL_FIR_DAT0_FL_SHIFT (0U)
#define FSP_FIR_DAT0_FL_FIR_DAT0_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT0_FL_FIR_DAT0_FL_SHIFT)) & FSP_FIR_DAT0_FL_FIR_DAT0_FL_MASK)
/*! @name FIR_DAT1_FL - FIR channel 1 float point data input & output register */
#define FSP_FIR_DAT1_FL_FIR_DAT1_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT1_FL_FIR_DAT1_FL_SHIFT (0U)
#define FSP_FIR_DAT1_FL_FIR_DAT1_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT1_FL_FIR_DAT1_FL_SHIFT)) & FSP_FIR_DAT1_FL_FIR_DAT1_FL_MASK)
/*! @name FIR_DAT2_FL - FIR channel 2 float point data input & output register */
#define FSP_FIR_DAT2_FL_FIR_DAT2_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT2_FL_FIR_DAT2_FL_SHIFT (0U)
#define FSP_FIR_DAT2_FL_FIR_DAT2_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT2_FL_FIR_DAT2_FL_SHIFT)) & FSP_FIR_DAT2_FL_FIR_DAT2_FL_MASK)
/*! @name FIR_DAT3_FL - FIR channel 3 float point data input & output register */
#define FSP_FIR_DAT3_FL_FIR_DAT3_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT3_FL_FIR_DAT3_FL_SHIFT (0U)
#define FSP_FIR_DAT3_FL_FIR_DAT3_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT3_FL_FIR_DAT3_FL_SHIFT)) & FSP_FIR_DAT3_FL_FIR_DAT3_FL_MASK)
/*! @name FIR_DAT4_FL - FIR channel 4 float point data input & output register */
#define FSP_FIR_DAT4_FL_FIR_DAT4_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT4_FL_FIR_DAT4_FL_SHIFT (0U)
#define FSP_FIR_DAT4_FL_FIR_DAT4_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT4_FL_FIR_DAT4_FL_SHIFT)) & FSP_FIR_DAT4_FL_FIR_DAT4_FL_MASK)
/*! @name FIR_DAT5_FL - FIR channel 5 float point data input & output register */
#define FSP_FIR_DAT5_FL_FIR_DAT5_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT5_FL_FIR_DAT5_FL_SHIFT (0U)
#define FSP_FIR_DAT5_FL_FIR_DAT5_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT5_FL_FIR_DAT5_FL_SHIFT)) & FSP_FIR_DAT5_FL_FIR_DAT5_FL_MASK)
/*! @name FIR_DAT6_FL - FIR channel 6 float point data input & output register */
#define FSP_FIR_DAT6_FL_FIR_DAT6_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT6_FL_FIR_DAT6_FL_SHIFT (0U)
#define FSP_FIR_DAT6_FL_FIR_DAT6_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT6_FL_FIR_DAT6_FL_SHIFT)) & FSP_FIR_DAT6_FL_FIR_DAT6_FL_MASK)
/*! @name FIR_DAT7_FL - FIR channel 7 float point data input & output register */
#define FSP_FIR_DAT7_FL_FIR_DAT7_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT7_FL_FIR_DAT7_FL_SHIFT (0U)
#define FSP_FIR_DAT7_FL_FIR_DAT7_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT7_FL_FIR_DAT7_FL_SHIFT)) & FSP_FIR_DAT7_FL_FIR_DAT7_FL_MASK)
/*! @name FIR_DAT8_FL - FIR channel 8 float point data input & output register */
#define FSP_FIR_DAT8_FL_FIR_DAT8_FL_MASK (0xFFFFFFFFU)
#define FSP_FIR_DAT8_FL_FIR_DAT8_FL_SHIFT (0U)
#define FSP_FIR_DAT8_FL_FIR_DAT8_FL(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_FIR_DAT8_FL_FIR_DAT8_FL_SHIFT)) & FSP_FIR_DAT8_FL_FIR_DAT8_FL_MASK)
/*! @name SIN_COS_IXOX - sin & cos input fix output fix mode data address register */
#define FSP_SIN_COS_IXOX_SIN_COS_IXOX_SRC_MASK (0xFFFFU)
#define FSP_SIN_COS_IXOX_SIN_COS_IXOX_SRC_SHIFT (0U)
#define FSP_SIN_COS_IXOX_SIN_COS_IXOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SIN_COS_IXOX_SIN_COS_IXOX_SRC_SHIFT)) & FSP_SIN_COS_IXOX_SIN_COS_IXOX_SRC_MASK)
#define FSP_SIN_COS_IXOX_SIN_COS_IXOX_DST_MASK (0xFFFF0000U)
#define FSP_SIN_COS_IXOX_SIN_COS_IXOX_DST_SHIFT (16U)
#define FSP_SIN_COS_IXOX_SIN_COS_IXOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SIN_COS_IXOX_SIN_COS_IXOX_DST_SHIFT)) & FSP_SIN_COS_IXOX_SIN_COS_IXOX_DST_MASK)
/*! @name SIN_COS_IXOL - sin & cos input fix output float mode data address register */
#define FSP_SIN_COS_IXOL_SIN_COS_IXOL_SRC_MASK (0xFFFFU)
#define FSP_SIN_COS_IXOL_SIN_COS_IXOL_SRC_SHIFT (0U)
#define FSP_SIN_COS_IXOL_SIN_COS_IXOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SIN_COS_IXOL_SIN_COS_IXOL_SRC_SHIFT)) & FSP_SIN_COS_IXOL_SIN_COS_IXOL_SRC_MASK)
#define FSP_SIN_COS_IXOL_SIN_COS_IXOL_DST_MASK (0xFFFF0000U)
#define FSP_SIN_COS_IXOL_SIN_COS_IXOL_DST_SHIFT (16U)
#define FSP_SIN_COS_IXOL_SIN_COS_IXOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SIN_COS_IXOL_SIN_COS_IXOL_DST_SHIFT)) & FSP_SIN_COS_IXOL_SIN_COS_IXOL_DST_MASK)
/*! @name SIN_COS_ILOX - sin & cos input float output fix mode data address register */
#define FSP_SIN_COS_ILOX_SIN_COS_ILOX_SRC_MASK (0xFFFFU)
#define FSP_SIN_COS_ILOX_SIN_COS_ILOX_SRC_SHIFT (0U)
#define FSP_SIN_COS_ILOX_SIN_COS_ILOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SIN_COS_ILOX_SIN_COS_ILOX_SRC_SHIFT)) & FSP_SIN_COS_ILOX_SIN_COS_ILOX_SRC_MASK)
#define FSP_SIN_COS_ILOX_SIN_COS_ILOX_DST_MASK (0xFFFF0000U)
#define FSP_SIN_COS_ILOX_SIN_COS_ILOX_DST_SHIFT (16U)
#define FSP_SIN_COS_ILOX_SIN_COS_ILOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SIN_COS_ILOX_SIN_COS_ILOX_DST_SHIFT)) & FSP_SIN_COS_ILOX_SIN_COS_ILOX_DST_MASK)
/*! @name SIN_COS_ILOL - sin & cos input float output float mode data address register */
#define FSP_SIN_COS_ILOL_SIN_COS_ILOL_SRC_MASK (0xFFFFU)
#define FSP_SIN_COS_ILOL_SIN_COS_ILOL_SRC_SHIFT (0U)
#define FSP_SIN_COS_ILOL_SIN_COS_ILOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SIN_COS_ILOL_SIN_COS_ILOL_SRC_SHIFT)) & FSP_SIN_COS_ILOL_SIN_COS_ILOL_SRC_MASK)
#define FSP_SIN_COS_ILOL_SIN_COS_ILOL_DST_MASK (0xFFFF0000U)
#define FSP_SIN_COS_ILOL_SIN_COS_ILOL_DST_SHIFT (16U)
#define FSP_SIN_COS_ILOL_SIN_COS_ILOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_SIN_COS_ILOL_SIN_COS_ILOL_DST_SHIFT)) & FSP_SIN_COS_ILOL_SIN_COS_ILOL_DST_MASK)
/*! @name LN_SQRT_IXOX - LN & sqrt input fix output fix mode data address register */
#define FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_SRC_MASK (0xFFFFU)
#define FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_SRC_SHIFT (0U)
#define FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_SRC_SHIFT)) & FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_SRC_MASK)
#define FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_DST_MASK (0xFFFF0000U)
#define FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_DST_SHIFT (16U)
#define FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_DST_SHIFT)) & FSP_LN_SQRT_IXOX_LN_SQRT_IXOX_DST_MASK)
/*! @name LN_SQRT_IXOL - LN & sqrt input fix output float mode data address register */
#define FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_SRC_MASK (0xFFFFU)
#define FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_SRC_SHIFT (0U)
#define FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_SRC_SHIFT)) & FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_SRC_MASK)
#define FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_DST_MASK (0xFFFF0000U)
#define FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_DST_SHIFT (16U)
#define FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_DST_SHIFT)) & FSP_LN_SQRT_IXOL_LN_SQRT_IXOL_DST_MASK)
/*! @name LN_SQRT_ILOX - LN & sqrt input float output fix mode data address register */
#define FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_SRC_MASK (0xFFFFU)
#define FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_SRC_SHIFT (0U)
#define FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_SRC_SHIFT)) & FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_SRC_MASK)
#define FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_DST_MASK (0xFFFF0000U)
#define FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_DST_SHIFT (16U)
#define FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_DST_SHIFT)) & FSP_LN_SQRT_ILOX_LN_SQRT_ILOX_DST_MASK)
/*! @name LN_SQRT_ILOL - LN & sqrt input float output float mode data address register */
#define FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_SRC_MASK (0xFFFFU)
#define FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_SRC_SHIFT (0U)
#define FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_SRC_SHIFT)) & FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_SRC_MASK)
#define FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_DST_MASK (0xFFFF0000U)
#define FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_DST_SHIFT (16U)
#define FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_DST_SHIFT)) & FSP_LN_SQRT_ILOL_LN_SQRT_ILOL_DST_MASK)
/*! @name CORDIC_T0UP_IXOX - native cordic input fix output fix, t=0, u=1 mode data address register */
#define FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_SRC_SHIFT (0U)
#define FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_SRC_SHIFT)) & \
FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_SRC_MASK)
#define FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_DST_SHIFT (16U)
#define FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_DST_SHIFT)) & \
FSP_CORDIC_T0UP_IXOX_CORDIC_T0UP_IXOX_DST_MASK)
/*! @name CORDIC_T0UP_IXOL - native cordic input fix output float, t=0, u=1 mode data address register */
#define FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_SRC_SHIFT (0U)
#define FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_SRC_SHIFT)) & \
FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_SRC_MASK)
#define FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_DST_SHIFT (16U)
#define FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_DST_SHIFT)) & \
FSP_CORDIC_T0UP_IXOL_CORDIC_T0UP_IXOL_DST_MASK)
/*! @name CORDIC_T0UP_ILOX - native cordic input float output fix, t=0, u=1 mode data address register */
#define FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_SRC_SHIFT (0U)
#define FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_SRC_SHIFT)) & \
FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_SRC_MASK)
#define FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_DST_SHIFT (16U)
#define FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_DST_SHIFT)) & \
FSP_CORDIC_T0UP_ILOX_CORDIC_T0UP_ILOX_DST_MASK)
/*! @name CORDIC_T0UP_ILOL - native cordic input float output float, t=0, u=1 mode data address register */
#define FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_SRC_SHIFT (0U)
#define FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_SRC_SHIFT)) & \
FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_SRC_MASK)
#define FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_DST_SHIFT (16U)
#define FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_DST_SHIFT)) & \
FSP_CORDIC_T0UP_ILOL_CORDIC_T0UP_ILOL_DST_MASK)
/*! @name CORDIC_T0UN_IXOX - native cordic input fix output fix, t=0, u=-1 mode data address register */
#define FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_SRC_SHIFT (0U)
#define FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_SRC_SHIFT)) & \
FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_SRC_MASK)
#define FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_DST_SHIFT (16U)
#define FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_DST_SHIFT)) & \
FSP_CORDIC_T0UN_IXOX_CORDIC_T0UN_IXOX_DST_MASK)
/*! @name CORDIC_T0UN_IXOL - native cordic input fix output float, t=0, u=-1 mode data address register */
#define FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_SRC_SHIFT (0U)
#define FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_SRC_SHIFT)) & \
FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_SRC_MASK)
#define FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_DST_SHIFT (16U)
#define FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_DST_SHIFT)) & \
FSP_CORDIC_T0UN_IXOL_CORDIC_T0UN_IXOL_DST_MASK)
/*! @name CORDIC_T0UN_ILOX - native cordic input float output fix, t=0, u=-1 mode data address register */
#define FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_SRC_SHIFT (0U)
#define FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_SRC_SHIFT)) & \
FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_SRC_MASK)
#define FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_DST_SHIFT (16U)
#define FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_DST_SHIFT)) & \
FSP_CORDIC_T0UN_ILOX_CORDIC_T0UN_ILOX_DST_MASK)
/*! @name CORDIC_T0UN_ILOL - native cordic input float output float, t=0, u=-1 mode data address register */
#define FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_SRC_SHIFT (0U)
#define FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_SRC_SHIFT)) & \
FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_SRC_MASK)
#define FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_DST_SHIFT (16U)
#define FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_DST_SHIFT)) & \
FSP_CORDIC_T0UN_ILOL_CORDIC_T0UN_ILOL_DST_MASK)
/*! @name CORDIC_T1UP_IXOX - native cordic input fix output fix, t=1, u=1 mode data address register */
#define FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_SRC_SHIFT (0U)
#define FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_SRC_SHIFT)) & \
FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_SRC_MASK)
#define FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_DST_SHIFT (16U)
#define FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_DST_SHIFT)) & \
FSP_CORDIC_T1UP_IXOX_CORDIC_T1UP_IXOX_DST_MASK)
/*! @name CORDIC_T1UP_IXOL - native cordic input fix output float, t=1, u=1 mode data address register */
#define FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_SRC_SHIFT (0U)
#define FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_SRC_SHIFT)) & \
FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_SRC_MASK)
#define FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_DST_SHIFT (16U)
#define FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_DST_SHIFT)) & \
FSP_CORDIC_T1UP_IXOL_CORDIC_T1UP_IXOL_DST_MASK)
/*! @name CORDIC_T1UP_ILOX - native cordic input float output fix, t=1, u=1 mode data address register */
#define FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_SRC_SHIFT (0U)
#define FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_SRC_SHIFT)) & \
FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_SRC_MASK)
#define FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_DST_SHIFT (16U)
#define FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_DST_SHIFT)) & \
FSP_CORDIC_T1UP_ILOX_CORDIC_T1UP_ILOX_DST_MASK)
/*! @name CORDIC_T1UP_ILOL - native cordic input float output float, t=1, u=1 mode data address register */
#define FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_SRC_SHIFT (0U)
#define FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_SRC_SHIFT)) & \
FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_SRC_MASK)
#define FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_DST_SHIFT (16U)
#define FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_DST_SHIFT)) & \
FSP_CORDIC_T1UP_ILOL_CORDIC_T1UP_ILOL_DST_MASK)
/*! @name CORDIC_T1UN_IXOX - native cordic input fix output fix, t=1, u=-1 mode data address register */
#define FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_SRC_SHIFT (0U)
#define FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_SRC_SHIFT)) & \
FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_SRC_MASK)
#define FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_DST_SHIFT (16U)
#define FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_DST_SHIFT)) & \
FSP_CORDIC_T1UN_IXOX_CORDIC_T1UN_IXOX_DST_MASK)
/*! @name CORDIC_T1UN_IXOL - native cordic input fix output float, t=1, u=-1 mode data address register */
#define FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_SRC_SHIFT (0U)
#define FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_SRC_SHIFT)) & \
FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_SRC_MASK)
#define FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_DST_SHIFT (16U)
#define FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_DST_SHIFT)) & \
FSP_CORDIC_T1UN_IXOL_CORDIC_T1UN_IXOL_DST_MASK)
/*! @name CORDIC_T1UN_ILOX - native cordic input float output fix, t=1, u=-1 mode data address register */
#define FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_SRC_SHIFT (0U)
#define FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_SRC_SHIFT)) & \
FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_SRC_MASK)
#define FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_DST_SHIFT (16U)
#define FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_DST_SHIFT)) & \
FSP_CORDIC_T1UN_ILOX_CORDIC_T1UN_ILOX_DST_MASK)
/*! @name CORDIC_T1UN_ILOL - native cordic input float output float, t=1, u=-1 mode data address register */
#define FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_SRC_MASK (0xFFFFU)
#define FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_SRC_SHIFT (0U)
#define FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_SRC(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_SRC_SHIFT)) & \
FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_SRC_MASK)
#define FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_DST_MASK (0xFFFF0000U)
#define FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_DST_SHIFT (16U)
#define FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_DST(x) \
(((uint32_t)(((uint32_t)(x)) << FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_DST_SHIFT)) & \
FSP_CORDIC_T1UN_ILOL_CORDIC_T1UN_ILOL_DST_MASK)
/*!
* @}
*/ /* end of group FSP_Register_Masks */
/* FSP - Peripheral instance base addresses */
/** Peripheral FSP base address */
#define FSP_BASE (0x40088000u)
/** Peripheral FSP base pointer */
#define FSP ((FSP_Type *)FSP_BASE)
/** Array initializer of FSP peripheral base addresses */
#define FSP_BASE_ADDRS \
{ \
FSP_BASE \
}
/** Array initializer of FSP peripheral base pointers */
#define FSP_BASE_PTRS \
{ \
FSP \
}
/** Interrupt vectors for the FSP peripheral type */
#define FSP_IRQS \
{ \
FSP_IRQn \
}
/*!
* @}
*/ /* end of group FSP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct
{
__I uint32_t DATA; /**< GPIO value register, offset: 0x0 */
__IO uint32_t DATAOUT; /**< GPIO output status register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t OUTENSET; /**< GPIO output enable set register, offset: 0x10 */
__IO uint32_t OUTENCLR; /**< GPIO output clear register, offset: 0x14 */
uint8_t RESERVED_1[8];
__IO uint32_t INTENSET; /**< GPIO interrupt enable set register, offset: 0x20 */
__IO uint32_t INTENCLR; /**< GPIO interrupt enable clear register, offset: 0x24 */
__IO uint32_t INTTYPESET; /**< GPIO interrupt type set register, offset: 0x28 */
__IO uint32_t INTTYPECLR; /**< GPIO interrupt type set register, offset: 0x2C */
__IO uint32_t INTPOLSET; /**< GPIO interrupt polarity set register, offset: 0x30 */
__IO uint32_t INTPOLCLR; /**< GPIO interrupt polarity clear register, offset: 0x34 */
__IO uint32_t INTSTATUS; /**< GPIO interrupt status register, offset: 0x38 */
} GPIO_Type;
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/*! @name DATA - GPIO value register */
#define GPIO_DATA_DATA_MASK (0xFFFFFFFFU)
#define GPIO_DATA_DATA_SHIFT (0U)
#define GPIO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DATA_DATA_SHIFT)) & GPIO_DATA_DATA_MASK)
/*! @name DATAOUT - GPIO output status register */
#define GPIO_DATAOUT_DATAOUT_MASK (0xFFFFFFFFU)
#define GPIO_DATAOUT_DATAOUT_SHIFT (0U)
#define GPIO_DATAOUT_DATAOUT(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_DATAOUT_DATAOUT_SHIFT)) & GPIO_DATAOUT_DATAOUT_MASK)
/*! @name OUTENSET - GPIO output enable set register */
#define GPIO_OUTENSET_OUTENSET_MASK (0xFFFFFFFFU)
#define GPIO_OUTENSET_OUTENSET_SHIFT (0U)
#define GPIO_OUTENSET_OUTENSET(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_OUTENSET_OUTENSET_SHIFT)) & GPIO_OUTENSET_OUTENSET_MASK)
/*! @name OUTENCLR - GPIO output clear register */
#define GPIO_OUTENCLR_OUTENCLR_MASK (0xFFFFFFFFU)
#define GPIO_OUTENCLR_OUTENCLR_SHIFT (0U)
#define GPIO_OUTENCLR_OUTENCLR(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_OUTENCLR_OUTENCLR_SHIFT)) & GPIO_OUTENCLR_OUTENCLR_MASK)
/*! @name INTENSET - GPIO interrupt enable set register */
#define GPIO_INTENSET_INTENSET_MASK (0xFFFFFFFFU)
#define GPIO_INTENSET_INTENSET_SHIFT (0U)
#define GPIO_INTENSET_INTENSET(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_INTENSET_INTENSET_SHIFT)) & GPIO_INTENSET_INTENSET_MASK)
/*! @name INTENCLR - GPIO interrupt enable clear register */
#define GPIO_INTENCLR_INTENCLR_MASK (0xFFFFFFFFU)
#define GPIO_INTENCLR_INTENCLR_SHIFT (0U)
#define GPIO_INTENCLR_INTENCLR(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_INTENCLR_INTENCLR_SHIFT)) & GPIO_INTENCLR_INTENCLR_MASK)
/*! @name INTTYPESET - GPIO interrupt type set register */
#define GPIO_INTTYPESET_INTTYPESET_MASK (0xFFFFFFFFU)
#define GPIO_INTTYPESET_INTTYPESET_SHIFT (0U)
#define GPIO_INTTYPESET_INTTYPESET(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_INTTYPESET_INTTYPESET_SHIFT)) & GPIO_INTTYPESET_INTTYPESET_MASK)
/*! @name INTTYPECLR - GPIO interrupt type set register */
#define GPIO_INTTYPECLR_INTTYPECLR_MASK (0xFFFFFFFFU)
#define GPIO_INTTYPECLR_INTTYPECLR_SHIFT (0U)
#define GPIO_INTTYPECLR_INTTYPECLR(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_INTTYPECLR_INTTYPECLR_SHIFT)) & GPIO_INTTYPECLR_INTTYPECLR_MASK)
/*! @name INTPOLSET - GPIO interrupt polarity set register */
#define GPIO_INTPOLSET_INTPOLSET_MASK (0xFFFFFFFFU)
#define GPIO_INTPOLSET_INTPOLSET_SHIFT (0U)
#define GPIO_INTPOLSET_INTPOLSET(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_INTPOLSET_INTPOLSET_SHIFT)) & GPIO_INTPOLSET_INTPOLSET_MASK)
/*! @name INTPOLCLR - GPIO interrupt polarity clear register */
#define GPIO_INTPOLCLR_INTPOLCLR_MASK (0xFFFFFFFFU)
#define GPIO_INTPOLCLR_INTPOLCLR_SHIFT (0U)
#define GPIO_INTPOLCLR_INTPOLCLR(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_INTPOLCLR_INTPOLCLR_SHIFT)) & GPIO_INTPOLCLR_INTPOLCLR_MASK)
/*! @name INTSTATUS - GPIO interrupt status register */
#define GPIO_INTSTATUS_INTSTATUS_MASK (0xFFFFFFFFU)
#define GPIO_INTSTATUS_INTSTATUS_SHIFT (0U)
#define GPIO_INTSTATUS_INTSTATUS(x) \
(((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATUS_INTSTATUS_SHIFT)) & GPIO_INTSTATUS_INTSTATUS_MASK)
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIOA base address */
#define GPIOA_BASE (0x4008C000u)
/** Peripheral GPIOA base pointer */
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
/** Peripheral GPIOB base address */
#define GPIOB_BASE (0x4008D000u)
/** Peripheral GPIOB base pointer */
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS \
{ \
GPIOA_BASE, GPIOB_BASE \
}
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS \
{ \
GPIOA, GPIOB \
}
/** Interrupt vectors for the GPIO peripheral type */
#define GPIO_IRQS \
{ \
GPIOA_IRQn, GPIOB_IRQn \
}
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
* @{
*/
/** I2C - Register Layout Typedef */
typedef struct
{
uint8_t RESERVED_0[2048];
__IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
__IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
__IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
__O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
__IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
__IO uint32_t
CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for
the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
__I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
uint8_t RESERVED_1[4];
__IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
__IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
__IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
uint8_t RESERVED_2[20];
__IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
__IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
__IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
__IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
uint8_t RESERVED_3[36];
__I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
uint8_t RESERVED_4[1912];
__I uint32_t ID; /**< I2C module Identification. This value appears in the shared Flexcomm peripheral ID register
when I2C is selected., offset: 0xFFC */
} I2C_Type;
/* ----------------------------------------------------------------------------
-- I2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2C_Register_Masks I2C Register Masks
* @{
*/
/*! @name CFG - Configuration for shared functions. */
#define I2C_CFG_MSTEN_MASK (0x1U)
#define I2C_CFG_MSTEN_SHIFT (0U)
#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
#define I2C_CFG_SLVEN_MASK (0x2U)
#define I2C_CFG_SLVEN_SHIFT (1U)
#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
#define I2C_CFG_MONEN_MASK (0x4U)
#define I2C_CFG_MONEN_SHIFT (2U)
#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
#define I2C_CFG_MONCLKSTR_MASK (0x10U)
#define I2C_CFG_MONCLKSTR_SHIFT (4U)
#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
#define I2C_STAT_MSTPENDING_MASK (0x1U)
#define I2C_STAT_MSTPENDING_SHIFT (0U)
#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
#define I2C_STAT_MSTSTATE_MASK (0xEU)
#define I2C_STAT_MSTSTATE_SHIFT (1U)
#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
#define I2C_STAT_MSTSTSTPERR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
#define I2C_STAT_SLVPENDING_MASK (0x100U)
#define I2C_STAT_SLVPENDING_SHIFT (8U)
#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
#define I2C_STAT_SLVSTATE_MASK (0x600U)
#define I2C_STAT_SLVSTATE_SHIFT (9U)
#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
#define I2C_STAT_SLVIDX_MASK (0x3000U)
#define I2C_STAT_SLVIDX_SHIFT (12U)
#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
#define I2C_STAT_SLVSEL_MASK (0x4000U)
#define I2C_STAT_SLVSEL_SHIFT (14U)
#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
#define I2C_STAT_SLVDESEL_MASK (0x8000U)
#define I2C_STAT_SLVDESEL_SHIFT (15U)
#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
#define I2C_STAT_MONRDY_MASK (0x10000U)
#define I2C_STAT_MONRDY_SHIFT (16U)
#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
#define I2C_STAT_MONOV_MASK (0x20000U)
#define I2C_STAT_MONOV_SHIFT (17U)
#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
#define I2C_STAT_MONACTIVE_MASK (0x40000U)
#define I2C_STAT_MONACTIVE_SHIFT (18U)
#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
#define I2C_STAT_MONIDLE_MASK (0x80000U)
#define I2C_STAT_MONIDLE_SHIFT (19U)
#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
#define I2C_STAT_EVENTTIMEOUT(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
/*! @name INTENSET - Interrupt Enable Set and read register. */
#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
#define I2C_INTENSET_MSTPENDINGEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
#define I2C_INTENSET_MSTARBLOSSEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
#define I2C_INTENSET_MSTSTSTPERREN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
#define I2C_INTENSET_SLVPENDINGEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
#define I2C_INTENSET_SLVNOTSTREN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
#define I2C_INTENSET_SLVDESELEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
#define I2C_INTENSET_MONRDYEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
#define I2C_INTENSET_MONOVEN_SHIFT (17U)
#define I2C_INTENSET_MONOVEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
#define I2C_INTENSET_MONIDLEEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
#define I2C_INTENSET_EVENTTIMEOUTEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
#define I2C_INTENSET_SCLTIMEOUTEN(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
/*! @name INTENCLR - Interrupt Enable Clear register. */
#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
#define I2C_INTENCLR_MSTPENDINGCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
#define I2C_INTENCLR_MSTARBLOSSCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
#define I2C_INTENCLR_MSTSTSTPERRCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
#define I2C_INTENCLR_SLVPENDINGCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
#define I2C_INTENCLR_SLVNOTSTRCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
#define I2C_INTENCLR_SLVDESELCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
#define I2C_INTENCLR_MONRDYCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
#define I2C_INTENCLR_MONOVCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
#define I2C_INTENCLR_MONIDLECLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
#define I2C_INTENCLR_SCLTIMEOUTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
/*! @name TIMEOUT - Time-out value register. */
#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
#define I2C_TIMEOUT_TO_SHIFT (4U)
#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the
* MSTTIME register, and controls some timing of the Slave function. */
#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
#define I2C_INTSTAT_MSTPENDING(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
#define I2C_INTSTAT_MSTARBLOSS(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
#define I2C_INTSTAT_MSTSTSTPERR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
#define I2C_INTSTAT_SLVPENDING(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
#define I2C_INTSTAT_SLVNOTSTR(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
#define I2C_INTSTAT_SLVDESEL(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
#define I2C_INTSTAT_MONRDY_SHIFT (16U)
#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
#define I2C_INTSTAT_MONOV_MASK (0x20000U)
#define I2C_INTSTAT_MONOV_SHIFT (17U)
#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
#define I2C_INTSTAT_EVENTTIMEOUT(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
#define I2C_INTSTAT_SCLTIMEOUT(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
/*! @name MSTCTL - Master control register. */
#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
#define I2C_MSTCTL_MSTCONTINUE(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
/*! @name MSTTIME - Master timing configuration. */
#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
#define I2C_MSTTIME_MSTSCLLOW(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
#define I2C_MSTTIME_MSTSCLHIGH(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
#define I2C_MSTDAT_DATA_MASK (0xFFU)
#define I2C_MSTDAT_DATA_SHIFT (0U)
#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
/*! @name SLVCTL - Slave control register. */
#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
#define I2C_SLVCTL_SLVCONTINUE(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
#define I2C_SLVCTL_AUTOACK_MASK (0x100U)
#define I2C_SLVCTL_AUTOACK_SHIFT (8U)
#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
#define I2C_SLVCTL_AUTOMATCHREAD(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
#define I2C_SLVDAT_DATA_MASK (0xFFU)
#define I2C_SLVDAT_DATA_SHIFT (0U)
#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
/*! @name SLVADR - Slave address register. */
#define I2C_SLVADR_SADISABLE_MASK (0x1U)
#define I2C_SLVADR_SADISABLE_SHIFT (0U)
#define I2C_SLVADR_SADISABLE(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
#define I2C_SLVADR_SLVADR_MASK (0xFEU)
#define I2C_SLVADR_SLVADR_SHIFT (1U)
#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
#define I2C_SLVADR_AUTONACK_MASK (0x8000U)
#define I2C_SLVADR_AUTONACK_SHIFT (15U)
#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
/* The count of I2C_SLVADR */
#define I2C_SLVADR_COUNT (4U)
/*! @name SLVQUAL0 - Slave Qualification for address 0. */
#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
#define I2C_SLVQUAL0_QUALMODE0(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
#define I2C_SLVQUAL0_SLVQUAL0(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
/*! @name MONRXDAT - Monitor receiver data register. */
#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
#define I2C_MONRXDAT_MONRXDAT(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
#define I2C_MONRXDAT_MONSTART(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
#define I2C_MONRXDAT_MONRESTART(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
#define I2C_MONRXDAT_MONNACK(x) \
(((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
/*! @name ID - I2C module Identification. This value appears in the shared Flexcomm peripheral ID register when I2C is
* selected. */
#define I2C_ID_APERTURE_MASK (0xFFU)
#define I2C_ID_APERTURE_SHIFT (0U)
#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
#define I2C_ID_MINOR_REV_MASK (0xF00U)
#define I2C_ID_MINOR_REV_SHIFT (8U)
#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
#define I2C_ID_MAJOR_REV_MASK (0xF000U)
#define I2C_ID_MAJOR_REV_SHIFT (12U)
#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
#define I2C_ID_ID_MASK (0xFFFF0000U)
#define I2C_ID_ID_SHIFT (16U)
#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
/*!
* @}
*/ /* end of group I2C_Register_Masks */
/* I2C - Peripheral instance base addresses */
/** Peripheral I2C0 base address */
#define I2C0_BASE (0x40086000u)
/** Peripheral I2C0 base pointer */
#define I2C0 ((I2C_Type *)I2C0_BASE)
/** Peripheral I2C1 base address */
#define I2C1_BASE (0x40087000u)
/** Peripheral I2C1 base pointer */
#define I2C1 ((I2C_Type *)I2C1_BASE)
/** Array initializer of I2C peripheral base addresses */
#define I2C_BASE_ADDRS \
{ \
I2C0_BASE, I2C1_BASE \
}
/** Array initializer of I2C peripheral base pointers */
#define I2C_BASE_PTRS \
{ \
I2C0, I2C1 \
}
/** Interrupt vectors for the I2C peripheral type */
#define I2C_IRQS \
{ \
FLEXCOMM1_IRQn, FLEXCOMM2_IRQn \
}
/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- INPUTMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
* @{
*/
/** INPUTMUX - Register Layout Typedef */
typedef struct
{
__IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0x0, array step: 0x4 */
uint8_t RESERVED_0[480];
__IO uint32_t
DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_1[1448];
__IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x800,
array step: 0x4 */
} INPUTMUX_Type;
/* ----------------------------------------------------------------------------
-- INPUTMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
* @{
*/
/*! @name PINTSEL - Pin interrupt select register */
#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU)
#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)
#define INPUTMUX_PINTSEL_INTPIN(x) \
(((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
/* The count of INPUTMUX_PINTSEL */
#define INPUTMUX_PINTSEL_COUNT (8U)
/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)
#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) \
(((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
/* The count of INPUTMUX_DMA_ITRIG_INMUX */
#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U)
/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU)
#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U)
#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) \
(((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
/* The count of INPUTMUX_DMA_OTRIG_INMUX */
#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U)
/*!
* @}
*/ /* end of group INPUTMUX_Register_Masks */
/* INPUTMUX - Peripheral instance base addresses */
/** Peripheral INPUTMUX base address */
#define INPUTMUX_BASE (0x40006200u)
/** Peripheral INPUTMUX base pointer */
#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
/** Array initializer of INPUTMUX peripheral base addresses */
#define INPUTMUX_BASE_ADDRS \
{ \
INPUTMUX_BASE \
}
/** Array initializer of INPUTMUX peripheral base pointers */
#define INPUTMUX_BASE_PTRS \
{ \
INPUTMUX \
}
/*!
* @}
*/ /* end of group INPUTMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PINT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
* @{
*/
/** PINT - Register Layout Typedef */
typedef struct
{
__IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
__IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
__O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
__O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
__IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
__O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
__O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
__IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
__IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
__IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
__IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
__IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
__IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
} PINT_Type;
/* ----------------------------------------------------------------------------
-- PINT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PINT_Register_Masks PINT Register Masks
* @{
*/
/*! @name ISEL - Pin Interrupt Mode register */
#define PINT_ISEL_PMODE_MASK (0xFFU)
#define PINT_ISEL_PMODE_SHIFT (0U)
#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
#define PINT_IENR_ENRL_MASK (0xFFU)
#define PINT_IENR_ENRL_SHIFT (0U)
#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
#define PINT_SIENR_SETENRL_MASK (0xFFU)
#define PINT_SIENR_SETENRL_SHIFT (0U)
#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
#define PINT_CIENR_CENRL_MASK (0xFFU)
#define PINT_CIENR_CENRL_SHIFT (0U)
#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
#define PINT_IENF_ENAF_MASK (0xFFU)
#define PINT_IENF_ENAF_SHIFT (0U)
#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
#define PINT_SIENF_SETENAF_MASK (0xFFU)
#define PINT_SIENF_SETENAF_SHIFT (0U)
#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
#define PINT_CIENF_CENAF_MASK (0xFFU)
#define PINT_CIENF_CENAF_SHIFT (0U)
#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
/*! @name RISE - Pin interrupt rising edge register */
#define PINT_RISE_RDET_MASK (0xFFU)
#define PINT_RISE_RDET_SHIFT (0U)
#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
/*! @name FALL - Pin interrupt falling edge register */
#define PINT_FALL_FDET_MASK (0xFFU)
#define PINT_FALL_FDET_SHIFT (0U)
#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
/*! @name IST - Pin interrupt status register */
#define PINT_IST_PSTAT_MASK (0xFFU)
#define PINT_IST_PSTAT_SHIFT (0U)
#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
/*! @name PMCTRL - Pattern match interrupt control register */
#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
#define PINT_PMCTRL_SEL_PMATCH(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
#define PINT_PMCTRL_ENA_RXEV(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
#define PINT_PMCTRL_PMAT_SHIFT (24U)
#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
/*! @name PMSRC - Pattern match interrupt bit-slice source register */
#define PINT_PMSRC_SRC0_MASK (0x700U)
#define PINT_PMSRC_SRC0_SHIFT (8U)
#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
#define PINT_PMSRC_SRC1_MASK (0x3800U)
#define PINT_PMSRC_SRC1_SHIFT (11U)
#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
#define PINT_PMSRC_SRC2_MASK (0x1C000U)
#define PINT_PMSRC_SRC2_SHIFT (14U)
#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
#define PINT_PMSRC_SRC3_MASK (0xE0000U)
#define PINT_PMSRC_SRC3_SHIFT (17U)
#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
#define PINT_PMSRC_SRC4_MASK (0x700000U)
#define PINT_PMSRC_SRC4_SHIFT (20U)
#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
#define PINT_PMSRC_SRC5_MASK (0x3800000U)
#define PINT_PMSRC_SRC5_SHIFT (23U)
#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
#define PINT_PMSRC_SRC6_SHIFT (26U)
#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
#define PINT_PMSRC_SRC7_SHIFT (29U)
#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
#define PINT_PMCFG_PROD_ENDPTS0(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
#define PINT_PMCFG_PROD_ENDPTS1(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
#define PINT_PMCFG_PROD_ENDPTS2(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
#define PINT_PMCFG_PROD_ENDPTS3(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
#define PINT_PMCFG_PROD_ENDPTS4(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
#define PINT_PMCFG_PROD_ENDPTS5(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
#define PINT_PMCFG_PROD_ENDPTS6(x) \
(((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
#define PINT_PMCFG_CFG0_MASK (0x700U)
#define PINT_PMCFG_CFG0_SHIFT (8U)
#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
#define PINT_PMCFG_CFG1_MASK (0x3800U)
#define PINT_PMCFG_CFG1_SHIFT (11U)
#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
#define PINT_PMCFG_CFG2_MASK (0x1C000U)
#define PINT_PMCFG_CFG2_SHIFT (14U)
#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
#define PINT_PMCFG_CFG3_MASK (0xE0000U)
#define PINT_PMCFG_CFG3_SHIFT (17U)
#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
#define PINT_PMCFG_CFG4_MASK (0x700000U)
#define PINT_PMCFG_CFG4_SHIFT (20U)
#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
#define PINT_PMCFG_CFG5_MASK (0x3800000U)
#define PINT_PMCFG_CFG5_SHIFT (23U)
#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
#define PINT_PMCFG_CFG6_SHIFT (26U)
#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
#define PINT_PMCFG_CFG7_SHIFT (29U)
#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
/*!
* @}
*/ /* end of group PINT_Register_Masks */
/* PINT - Peripheral instance base addresses */
/** Peripheral PINT base address */
#define PINT_BASE (0x40006000u)
/** Peripheral PINT base pointer */
#define PINT ((PINT_Type *)PINT_BASE)
/** Array initializer of PINT peripheral base addresses */
#define PINT_BASE_ADDRS \
{ \
PINT_BASE \
}
/** Array initializer of PINT peripheral base pointers */
#define PINT_BASE_PTRS \
{ \
PINT \
}
/** Interrupt vectors for the PINT peripheral type */
#define PINT_IRQS \
{ \
PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn \
}
/*!
* @}
*/ /* end of group PINT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PROP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PROP_Peripheral_Access_Layer PROP Peripheral Access Layer
* @{
*/
/** PROP - Register Layout Typedef */
typedef struct
{
__IO uint32_t TX_BUF; /**< transmit data buffer input port register, offset: 0x0 */
__I uint32_t RX_BUF; /**< received data buffer output register, offset: 0x4 */
__IO uint32_t STAT; /**< status register, offset: 0x8 */
} PROP_Type;
/* ----------------------------------------------------------------------------
-- PROP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PROP_Register_Masks PROP Register Masks
* @{
*/
/*! @name TX_BUF - transmit data buffer input port register */
#define PROP_TX_BUF_TX_BUF_MASK (0xFFU)
#define PROP_TX_BUF_TX_BUF_SHIFT (0U)
#define PROP_TX_BUF_TX_BUF(x) (((uint32_t)(((uint32_t)(x)) << PROP_TX_BUF_TX_BUF_SHIFT)) & PROP_TX_BUF_TX_BUF_MASK)
/*! @name RX_BUF - received data buffer output register */
#define PROP_RX_BUF_RX_BUF_MASK (0xFFU)
#define PROP_RX_BUF_RX_BUF_SHIFT (0U)
#define PROP_RX_BUF_RX_BUF(x) (((uint32_t)(((uint32_t)(x)) << PROP_RX_BUF_RX_BUF_SHIFT)) & PROP_RX_BUF_RX_BUF_MASK)
/*! @name STAT - status register */
#define PROP_STAT_BIT_ORDER_MASK (0x1U)
#define PROP_STAT_BIT_ORDER_SHIFT (0U)
#define PROP_STAT_BIT_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PROP_STAT_BIT_ORDER_SHIFT)) & PROP_STAT_BIT_ORDER_MASK)
#define PROP_STAT_TX_INTEN_MASK (0x2U)
#define PROP_STAT_TX_INTEN_SHIFT (1U)
#define PROP_STAT_TX_INTEN(x) (((uint32_t)(((uint32_t)(x)) << PROP_STAT_TX_INTEN_SHIFT)) & PROP_STAT_TX_INTEN_MASK)
#define PROP_STAT_RX_INTEN_MASK (0x4U)
#define PROP_STAT_RX_INTEN_SHIFT (2U)
#define PROP_STAT_RX_INTEN(x) (((uint32_t)(((uint32_t)(x)) << PROP_STAT_RX_INTEN_SHIFT)) & PROP_STAT_RX_INTEN_MASK)
#define PROP_STAT_RX_INT_MASK (0x8U)
#define PROP_STAT_RX_INT_SHIFT (3U)
#define PROP_STAT_RX_INT(x) (((uint32_t)(((uint32_t)(x)) << PROP_STAT_RX_INT_SHIFT)) & PROP_STAT_RX_INT_MASK)
#define PROP_STAT_TX_INT_MASK (0x10U)
#define PROP_STAT_TX_INT_SHIFT (4U)
#define PROP_STAT_TX_INT(x) (((uint32_t)(((uint32_t)(x)) << PROP_STAT_TX_INT_SHIFT)) & PROP_STAT_TX_INT_MASK)
#define PROP_STAT_RX_BUSY_MASK (0x20U)
#define PROP_STAT_RX_BUSY_SHIFT (5U)
#define PROP_STAT_RX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PROP_STAT_RX_BUSY_SHIFT)) & PROP_STAT_RX_BUSY_MASK)
#define PROP_STAT_TX_BUSY_MASK (0x40U)
#define PROP_STAT_TX_BUSY_SHIFT (6U)
#define PROP_STAT_TX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PROP_STAT_TX_BUSY_SHIFT)) & PROP_STAT_TX_BUSY_MASK)
#define PROP_STAT_CLR_MASK (0x80U)
#define PROP_STAT_CLR_SHIFT (7U)
#define PROP_STAT_CLR(x) (((uint32_t)(((uint32_t)(x)) << PROP_STAT_CLR_SHIFT)) & PROP_STAT_CLR_MASK)
/*!
* @}
*/ /* end of group PROP_Register_Masks */
/* PROP - Peripheral instance base addresses */
/** Peripheral PROP base address */
#define PROP_BASE (0x4000D000u)
/** Peripheral PROP base pointer */
#define PROP ((PROP_Type *)PROP_BASE)
/** Array initializer of PROP peripheral base addresses */
#define PROP_BASE_ADDRS \
{ \
PROP_BASE \
}
/** Array initializer of PROP peripheral base pointers */
#define PROP_BASE_PTRS \
{ \
PROP \
}
/*!
* @}
*/ /* end of group PROP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- QDEC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup QDEC_Peripheral_Access_Layer QDEC Peripheral Access Layer
* @{
*/
/** QDEC - Register Layout Typedef */
typedef struct
{
__IO uint32_t CTRL; /**< control register, offset: 0x0 */
__IO uint32_t SAMP_CTRL; /**< QDEC sample settting register, offset: 0x4 */
__I uint32_t SAMPLE; /**< QDEC sample result register, offset: 0x8 */
__I uint32_t ACC; /**< QDEC accumulate register, offset: 0xC */
__I uint32_t ACC_R; /**< QDEC accumulate snapshot register, offset: 0x10 */
__I uint32_t DB; /**< double sample register, offset: 0x14 */
__I uint32_t DB_R; /**< DB snapshot register, offset: 0x18 */
__IO uint32_t INT; /**< interrupt register, offset: 0x1C */
__IO uint32_t INTEN; /**< interrupt mask register, offset: 0x20 */
__I uint32_t STAT; /**< QDEC is running, offset: 0x24 */
} QDEC_Type;
/* ----------------------------------------------------------------------------
-- QDEC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup QDEC_Register_Masks QDEC Register Masks
* @{
*/
/*! @name CTRL - control register */
#define QDEC_CTRL_QDEC_EN_MASK (0x1U)
#define QDEC_CTRL_QDEC_EN_SHIFT (0U)
#define QDEC_CTRL_QDEC_EN(x) (((uint32_t)(((uint32_t)(x)) << QDEC_CTRL_QDEC_EN_SHIFT)) & QDEC_CTRL_QDEC_EN_MASK)
#define QDEC_CTRL_START_MASK (0x2U)
#define QDEC_CTRL_START_SHIFT (1U)
#define QDEC_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << QDEC_CTRL_START_SHIFT)) & QDEC_CTRL_START_MASK)
#define QDEC_CTRL_STOP_MASK (0x4U)
#define QDEC_CTRL_STOP_SHIFT (2U)
#define QDEC_CTRL_STOP(x) (((uint32_t)(((uint32_t)(x)) << QDEC_CTRL_STOP_SHIFT)) & QDEC_CTRL_STOP_MASK)
#define QDEC_CTRL_SOFT_CLR_MASK (0x8U)
#define QDEC_CTRL_SOFT_CLR_SHIFT (3U)
#define QDEC_CTRL_SOFT_CLR(x) (((uint32_t)(((uint32_t)(x)) << QDEC_CTRL_SOFT_CLR_SHIFT)) & QDEC_CTRL_SOFT_CLR_MASK)
#define QDEC_CTRL_AUTO_CLR_EN_MASK (0x10U)
#define QDEC_CTRL_AUTO_CLR_EN_SHIFT (4U)
#define QDEC_CTRL_AUTO_CLR_EN(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_CTRL_AUTO_CLR_EN_SHIFT)) & QDEC_CTRL_AUTO_CLR_EN_MASK)
#define QDEC_CTRL_SINGLE_SAMPLE_SRST_EN_MASK (0x20U)
#define QDEC_CTRL_SINGLE_SAMPLE_SRST_EN_SHIFT (5U)
#define QDEC_CTRL_SINGLE_SAMPLE_SRST_EN(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_CTRL_SINGLE_SAMPLE_SRST_EN_SHIFT)) & QDEC_CTRL_SINGLE_SAMPLE_SRST_EN_MASK)
#define QDEC_CTRL_DB_FILTER_EN_MASK (0x40U)
#define QDEC_CTRL_DB_FILTER_EN_SHIFT (6U)
#define QDEC_CTRL_DB_FILTER_EN(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_CTRL_DB_FILTER_EN_SHIFT)) & QDEC_CTRL_DB_FILTER_EN_MASK)
/*! @name SAMP_CTRL - QDEC sample settting register */
#define QDEC_SAMP_CTRL_DIVIDE_MASK (0x1FU)
#define QDEC_SAMP_CTRL_DIVIDE_SHIFT (0U)
#define QDEC_SAMP_CTRL_DIVIDE(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_SAMP_CTRL_DIVIDE_SHIFT)) & QDEC_SAMP_CTRL_DIVIDE_MASK)
#define QDEC_SAMP_CTRL_PTS_MASK (0xF00U)
#define QDEC_SAMP_CTRL_PTS_SHIFT (8U)
#define QDEC_SAMP_CTRL_PTS(x) (((uint32_t)(((uint32_t)(x)) << QDEC_SAMP_CTRL_PTS_SHIFT)) & QDEC_SAMP_CTRL_PTS_MASK)
#define QDEC_SAMP_CTRL_DB_SAMP_DIV_MASK (0xF0000U)
#define QDEC_SAMP_CTRL_DB_SAMP_DIV_SHIFT (16U)
#define QDEC_SAMP_CTRL_DB_SAMP_DIV(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_SAMP_CTRL_DB_SAMP_DIV_SHIFT)) & QDEC_SAMP_CTRL_DB_SAMP_DIV_MASK)
/*! @name SAMPLE - QDEC sample result register */
#define QDEC_SAMPLE_SAMPLE_MASK (0x3U)
#define QDEC_SAMPLE_SAMPLE_SHIFT (0U)
#define QDEC_SAMPLE_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << QDEC_SAMPLE_SAMPLE_SHIFT)) & QDEC_SAMPLE_SAMPLE_MASK)
/*! @name ACC - QDEC accumulate register */
#define QDEC_ACC_ACC_MASK (0x7FFU)
#define QDEC_ACC_ACC_SHIFT (0U)
#define QDEC_ACC_ACC(x) (((uint32_t)(((uint32_t)(x)) << QDEC_ACC_ACC_SHIFT)) & QDEC_ACC_ACC_MASK)
/*! @name ACC_R - QDEC accumulate snapshot register */
#define QDEC_ACC_R_ACC_R_MASK (0x7FFU)
#define QDEC_ACC_R_ACC_R_SHIFT (0U)
#define QDEC_ACC_R_ACC_R(x) (((uint32_t)(((uint32_t)(x)) << QDEC_ACC_R_ACC_R_SHIFT)) & QDEC_ACC_R_ACC_R_MASK)
/*! @name DB - double sample register */
#define QDEC_DB_DB_MASK (0xFU)
#define QDEC_DB_DB_SHIFT (0U)
#define QDEC_DB_DB(x) (((uint32_t)(((uint32_t)(x)) << QDEC_DB_DB_SHIFT)) & QDEC_DB_DB_MASK)
/*! @name DB_R - DB snapshot register */
#define QDEC_DB_R_DB_R_MASK (0xFU)
#define QDEC_DB_R_DB_R_SHIFT (0U)
#define QDEC_DB_R_DB_R(x) (((uint32_t)(((uint32_t)(x)) << QDEC_DB_R_DB_R_SHIFT)) & QDEC_DB_R_DB_R_MASK)
/*! @name INT - interrupt register */
#define QDEC_INT_SINGLE_SAMPLE_MASK (0x1U)
#define QDEC_INT_SINGLE_SAMPLE_SHIFT (0U)
#define QDEC_INT_SINGLE_SAMPLE(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_INT_SINGLE_SAMPLE_SHIFT)) & QDEC_INT_SINGLE_SAMPLE_MASK)
#define QDEC_INT_SAMPLE_END_MASK (0x2U)
#define QDEC_INT_SAMPLE_END_SHIFT (1U)
#define QDEC_INT_SAMPLE_END(x) (((uint32_t)(((uint32_t)(x)) << QDEC_INT_SAMPLE_END_SHIFT)) & QDEC_INT_SAMPLE_END_MASK)
#define QDEC_INT_ACC_OF_MASK (0x4U)
#define QDEC_INT_ACC_OF_SHIFT (2U)
#define QDEC_INT_ACC_OF(x) (((uint32_t)(((uint32_t)(x)) << QDEC_INT_ACC_OF_SHIFT)) & QDEC_INT_ACC_OF_MASK)
#define QDEC_INT_DB_OF_MASK (0x8U)
#define QDEC_INT_DB_OF_SHIFT (3U)
#define QDEC_INT_DB_OF(x) (((uint32_t)(((uint32_t)(x)) << QDEC_INT_DB_OF_SHIFT)) & QDEC_INT_DB_OF_MASK)
/*! @name INTEN - interrupt mask register */
#define QDEC_INTEN_SINGLE_SAMPLE_INTEN_MASK (0x1U)
#define QDEC_INTEN_SINGLE_SAMPLE_INTEN_SHIFT (0U)
#define QDEC_INTEN_SINGLE_SAMPLE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_INTEN_SINGLE_SAMPLE_INTEN_SHIFT)) & QDEC_INTEN_SINGLE_SAMPLE_INTEN_MASK)
#define QDEC_INTEN_SAMPLE_END_INTEN_MASK (0x2U)
#define QDEC_INTEN_SAMPLE_END_INTEN_SHIFT (1U)
#define QDEC_INTEN_SAMPLE_END_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_INTEN_SAMPLE_END_INTEN_SHIFT)) & QDEC_INTEN_SAMPLE_END_INTEN_MASK)
#define QDEC_INTEN_ACC_OF_INTEN_MASK (0x4U)
#define QDEC_INTEN_ACC_OF_INTEN_SHIFT (2U)
#define QDEC_INTEN_ACC_OF_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_INTEN_ACC_OF_INTEN_SHIFT)) & QDEC_INTEN_ACC_OF_INTEN_MASK)
#define QDEC_INTEN_DB_OF_INTEN_MASK (0x8U)
#define QDEC_INTEN_DB_OF_INTEN_SHIFT (3U)
#define QDEC_INTEN_DB_OF_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << QDEC_INTEN_DB_OF_INTEN_SHIFT)) & QDEC_INTEN_DB_OF_INTEN_MASK)
/*! @name STAT - QDEC is running */
#define QDEC_STAT_BUSY_MASK (0x1U)
#define QDEC_STAT_BUSY_SHIFT (0U)
#define QDEC_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QDEC_STAT_BUSY_SHIFT)) & QDEC_STAT_BUSY_MASK)
/*!
* @}
*/ /* end of group QDEC_Register_Masks */
/* QDEC - Peripheral instance base addresses */
/** Peripheral QDEC0 base address */
#define QDEC0_BASE (0x40009000u)
/** Peripheral QDEC0 base pointer */
#define QDEC0 ((QDEC_Type *)QDEC0_BASE)
/** Peripheral QDEC1 base address */
#define QDEC1_BASE (0x40009800u)
/** Peripheral QDEC1 base pointer */
#define QDEC1 ((QDEC_Type *)QDEC1_BASE)
/** Array initializer of QDEC peripheral base addresses */
#define QDEC_BASE_ADDRS \
{ \
QDEC0_BASE, QDEC1_BASE \
}
/** Array initializer of QDEC peripheral base pointers */
#define QDEC_BASE_PTRS \
{ \
QDEC0, QDEC1 \
}
/** Interrupt vectors for the QDEC peripheral type */
#define QDEC_IRQS \
{ \
QDEC0_IRQn, QDEC1_IRQn \
}
/*!
* @}
*/ /* end of group QDEC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RNG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
* @{
*/
/** RNG - Register Layout Typedef */
typedef struct
{
__IO uint32_t CTRL; /**< control register, offset: 0x0 */
__I uint32_t STAT; /**< status register, offset: 0x4 */
__I uint32_t DATA; /**< random data output register, offset: 0x8 */
__IO uint32_t INT; /**< interrupt register, offset: 0xC */
__IO uint32_t INTEN; /**< interrupt mask register, offset: 0x10 */
} RNG_Type;
/* ----------------------------------------------------------------------------
-- RNG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RNG_Register_Masks RNG Register Masks
* @{
*/
/*! @name CTRL - control register */
#define RNG_CTRL_ENABLE_MASK (0x1U)
#define RNG_CTRL_ENABLE_SHIFT (0U)
#define RNG_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CTRL_ENABLE_SHIFT)) & RNG_CTRL_ENABLE_MASK)
#define RNG_CTRL_START_MASK (0x2U)
#define RNG_CTRL_START_SHIFT (1U)
#define RNG_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << RNG_CTRL_START_SHIFT)) & RNG_CTRL_START_MASK)
#define RNG_CTRL_NUM_MASK (0x30U)
#define RNG_CTRL_NUM_SHIFT (4U)
#define RNG_CTRL_NUM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CTRL_NUM_SHIFT)) & RNG_CTRL_NUM_MASK)
/*! @name STAT - status register */
#define RNG_STAT_BUSY_MASK (0x1U)
#define RNG_STAT_BUSY_SHIFT (0U)
#define RNG_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << RNG_STAT_BUSY_SHIFT)) & RNG_STAT_BUSY_MASK)
/*! @name DATA - random data output register */
#define RNG_DATA_DATA_MASK (0xFFFFFFFFU)
#define RNG_DATA_DATA_SHIFT (0U)
#define RNG_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << RNG_DATA_DATA_SHIFT)) & RNG_DATA_DATA_MASK)
/*! @name INT - interrupt register */
#define RNG_INT_DONE_MASK (0x1U)
#define RNG_INT_DONE_SHIFT (0U)
#define RNG_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << RNG_INT_DONE_SHIFT)) & RNG_INT_DONE_MASK)
/*! @name INTEN - interrupt mask register */
#define RNG_INTEN_DONE_INTEN_MASK (0x1U)
#define RNG_INTEN_DONE_INTEN_SHIFT (0U)
#define RNG_INTEN_DONE_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << RNG_INTEN_DONE_INTEN_SHIFT)) & RNG_INTEN_DONE_INTEN_MASK)
/*!
* @}
*/ /* end of group RNG_Register_Masks */
/* RNG - Peripheral instance base addresses */
/** Peripheral RNG base address */
#define RNG_BASE (0x40007C00u)
/** Peripheral RNG base pointer */
#define RNG ((RNG_Type *)RNG_BASE)
/** Array initializer of RNG peripheral base addresses */
#define RNG_BASE_ADDRS \
{ \
RNG_BASE \
}
/** Array initializer of RNG peripheral base pointers */
#define RNG_BASE_PTRS \
{ \
RNG \
}
/** Interrupt vectors for the RNG peripheral type */
#define RNG_IRQS \
{ \
RNG_IRQn \
}
/*!
* @}
*/ /* end of group RNG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RTC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
* @{
*/
/** RTC - Register Layout Typedef */
typedef struct
{
__IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */
__IO uint32_t STATUS; /**< RTC status register, offset: 0x4 */
__IO uint32_t SEC; /**< RTC second register, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t CAL; /**< RTC calibration register, offset: 0x10 */
__I uint32_t CNT_VAL; /**< RTC count value register, offset: 0x14 */
uint8_t RESERVED_1[8];
__IO uint32_t CNT2_CTRL; /**< Free running control register, offset: 0x20 */
__IO uint32_t THR_INT; /**< interrupt threshold of free running counter register, offset: 0x24 */
__IO uint32_t THR_RST; /**< reset threshold of free running counter register, offset: 0x28 */
__I uint32_t CNT2; /**< free running count value, offset: 0x2C */
} RTC_Type;
/* ----------------------------------------------------------------------------
-- RTC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Masks RTC Register Masks
* @{
*/
/*! @name CTRL - RTC control register */
#define RTC_CTRL_SEC_INT_EN_MASK (0x1U)
#define RTC_CTRL_SEC_INT_EN_SHIFT (0U)
#define RTC_CTRL_SEC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SEC_INT_EN_SHIFT)) & RTC_CTRL_SEC_INT_EN_MASK)
#define RTC_CTRL_CFG_MASK (0x4U)
#define RTC_CTRL_CFG_SHIFT (2U)
#define RTC_CTRL_CFG(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_CFG_SHIFT)) & RTC_CTRL_CFG_MASK)
#define RTC_CTRL_CAL_EN_MASK (0x100U)
#define RTC_CTRL_CAL_EN_SHIFT (8U)
#define RTC_CTRL_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_CAL_EN_SHIFT)) & RTC_CTRL_CAL_EN_MASK)
/*! @name STATUS - RTC status register */
#define RTC_STATUS_SEC_INT_MASK (0x1U)
#define RTC_STATUS_SEC_INT_SHIFT (0U)
#define RTC_STATUS_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << RTC_STATUS_SEC_INT_SHIFT)) & RTC_STATUS_SEC_INT_MASK)
#define RTC_STATUS_CTRL_SYNC_MASK (0x100U)
#define RTC_STATUS_CTRL_SYNC_SHIFT (8U)
#define RTC_STATUS_CTRL_SYNC(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_STATUS_CTRL_SYNC_SHIFT)) & RTC_STATUS_CTRL_SYNC_MASK)
#define RTC_STATUS_STATUS_SYNC_MASK (0x200U)
#define RTC_STATUS_STATUS_SYNC_SHIFT (9U)
#define RTC_STATUS_STATUS_SYNC(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_STATUS_STATUS_SYNC_SHIFT)) & RTC_STATUS_STATUS_SYNC_MASK)
#define RTC_STATUS_SEC_SYNC_MASK (0x400U)
#define RTC_STATUS_SEC_SYNC_SHIFT (10U)
#define RTC_STATUS_SEC_SYNC(x) (((uint32_t)(((uint32_t)(x)) << RTC_STATUS_SEC_SYNC_SHIFT)) & RTC_STATUS_SEC_SYNC_MASK)
#define RTC_STATUS_CALIB_SYNC_MASK (0x1000U)
#define RTC_STATUS_CALIB_SYNC_SHIFT (12U)
#define RTC_STATUS_CALIB_SYNC(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_STATUS_CALIB_SYNC_SHIFT)) & RTC_STATUS_CALIB_SYNC_MASK)
#define RTC_STATUS_FREE_SYNC_MASK (0x10000U)
#define RTC_STATUS_FREE_SYNC_SHIFT (16U)
#define RTC_STATUS_FREE_SYNC(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_STATUS_FREE_SYNC_SHIFT)) & RTC_STATUS_FREE_SYNC_MASK)
#define RTC_STATUS_THR_INT_SYNC_MASK (0x20000U)
#define RTC_STATUS_THR_INT_SYNC_SHIFT (17U)
#define RTC_STATUS_THR_INT_SYNC(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_STATUS_THR_INT_SYNC_SHIFT)) & RTC_STATUS_THR_INT_SYNC_MASK)
#define RTC_STATUS_THR_RST_SYNC_MASK (0x40000U)
#define RTC_STATUS_THR_RST_SYNC_SHIFT (18U)
#define RTC_STATUS_THR_RST_SYNC(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_STATUS_THR_RST_SYNC_SHIFT)) & RTC_STATUS_THR_RST_SYNC_MASK)
#define RTC_STATUS_FREE_RUNNING_INT_MASK (0x80000000U)
#define RTC_STATUS_FREE_RUNNING_INT_SHIFT (31U)
#define RTC_STATUS_FREE_RUNNING_INT(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_STATUS_FREE_RUNNING_INT_SHIFT)) & RTC_STATUS_FREE_RUNNING_INT_MASK)
/*! @name SEC - RTC second register */
#define RTC_SEC_SEC_MASK (0xFFFFFFFFU)
#define RTC_SEC_SEC_SHIFT (0U)
#define RTC_SEC_SEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SEC_SEC_SHIFT)) & RTC_SEC_SEC_MASK)
/*! @name CAL - RTC calibration register */
#define RTC_CAL_PPM_MASK (0xFFFFU)
#define RTC_CAL_PPM_SHIFT (0U)
#define RTC_CAL_PPM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CAL_PPM_SHIFT)) & RTC_CAL_PPM_MASK)
#define RTC_CAL_DIR_MASK (0x10000U)
#define RTC_CAL_DIR_SHIFT (16U)
#define RTC_CAL_DIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CAL_DIR_SHIFT)) & RTC_CAL_DIR_MASK)
/*! @name CNT_VAL - RTC count value register */
#define RTC_CNT_VAL_CNT_MASK (0x7FFFU)
#define RTC_CNT_VAL_CNT_SHIFT (0U)
#define RTC_CNT_VAL_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_VAL_CNT_SHIFT)) & RTC_CNT_VAL_CNT_MASK)
/*! @name CNT2_CTRL - Free running control register */
#define RTC_CNT2_CTRL_CNT2_EN_MASK (0x1U)
#define RTC_CNT2_CTRL_CNT2_EN_SHIFT (0U)
#define RTC_CNT2_CTRL_CNT2_EN(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_CNT2_CTRL_CNT2_EN_SHIFT)) & RTC_CNT2_CTRL_CNT2_EN_MASK)
#define RTC_CNT2_CTRL_CNT2_INT_EN_MASK (0x2U)
#define RTC_CNT2_CTRL_CNT2_INT_EN_SHIFT (1U)
#define RTC_CNT2_CTRL_CNT2_INT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_CNT2_CTRL_CNT2_INT_EN_SHIFT)) & RTC_CNT2_CTRL_CNT2_INT_EN_MASK)
#define RTC_CNT2_CTRL_CNT2_WAKEUP_MASK (0x4U)
#define RTC_CNT2_CTRL_CNT2_WAKEUP_SHIFT (2U)
#define RTC_CNT2_CTRL_CNT2_WAKEUP(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_CNT2_CTRL_CNT2_WAKEUP_SHIFT)) & RTC_CNT2_CTRL_CNT2_WAKEUP_MASK)
#define RTC_CNT2_CTRL_CNT2_RST_MASK (0x8U)
#define RTC_CNT2_CTRL_CNT2_RST_SHIFT (3U)
#define RTC_CNT2_CTRL_CNT2_RST(x) \
(((uint32_t)(((uint32_t)(x)) << RTC_CNT2_CTRL_CNT2_RST_SHIFT)) & RTC_CNT2_CTRL_CNT2_RST_MASK)
/*! @name THR_INT - interrupt threshold of free running counter register */
#define RTC_THR_INT_THR_INT_MASK (0xFFFFFFFFU)
#define RTC_THR_INT_THR_INT_SHIFT (0U)
#define RTC_THR_INT_THR_INT(x) (((uint32_t)(((uint32_t)(x)) << RTC_THR_INT_THR_INT_SHIFT)) & RTC_THR_INT_THR_INT_MASK)
/*! @name THR_RST - reset threshold of free running counter register */
#define RTC_THR_RST_THR_RST_MASK (0xFFFFFFFFU)
#define RTC_THR_RST_THR_RST_SHIFT (0U)
#define RTC_THR_RST_THR_RST(x) (((uint32_t)(((uint32_t)(x)) << RTC_THR_RST_THR_RST_SHIFT)) & RTC_THR_RST_THR_RST_MASK)
/*! @name CNT2 - free running count value */
#define RTC_CNT2_CNT2_MASK (0xFFFFFFFFU)
#define RTC_CNT2_CNT2_SHIFT (0U)
#define RTC_CNT2_CNT2(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT2_CNT2_SHIFT)) & RTC_CNT2_CNT2_MASK)
/*!
* @}
*/ /* end of group RTC_Register_Masks */
/* RTC - Peripheral instance base addresses */
/** Peripheral RTC base address */
#define RTC_BASE (0x4000B000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS \
{ \
RTC_BASE \
}
/** Array initializer of RTC peripheral base pointers */
#define RTC_BASE_PTRS \
{ \
RTC \
}
/** Interrupt vectors for the RTC peripheral type */
#define RTC_IRQS \
{ \
RTC_SEC_IRQn, RTC_FR_IRQn \
}
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SCT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
* @{
*/
/** SCT - Register Layout Typedef */
typedef struct
{
__IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
__IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
__IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
__IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
__IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
__IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
uint8_t RESERVED_0[40];
__IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
__IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
__I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
__IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
__IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
__IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
__IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
__IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */
__IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */
uint8_t RESERVED_1[140];
__IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
__IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
__IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
__IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
union { /* offset: 0x100 */
__IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
__IO uint32_t
SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
};
uint8_t RESERVED_2[216];
union { /* offset: 0x200 */
__IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
__IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
};
uint8_t RESERVED_3[216];
struct
{ /* offset: 0x300, array step: 0x8 */
__IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
__IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
} EVENT[10];
uint8_t RESERVED_4[432];
struct
{ /* offset: 0x500, array step: 0x8 */
__IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
__IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
} OUT[8];
uint8_t RESERVED_5[700];
__IO uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */
} SCT_Type;
/* ----------------------------------------------------------------------------
-- SCT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SCT_Register_Masks SCT Register Masks
* @{
*/
/*! @name CONFIG - SCT configuration register */
#define SCT_CONFIG_UNIFY_MASK (0x1U)
#define SCT_CONFIG_UNIFY_SHIFT (0U)
#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
#define SCT_CONFIG_CLKMODE_MASK (0x6U)
#define SCT_CONFIG_CLKMODE_SHIFT (1U)
#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
#define SCT_CONFIG_CKSEL_MASK (0x78U)
#define SCT_CONFIG_CKSEL_SHIFT (3U)
#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
#define SCT_CONFIG_NORELAOD_L_MASK (0x80U)
#define SCT_CONFIG_NORELAOD_L_SHIFT (7U)
#define SCT_CONFIG_NORELAOD_L(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)
#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
#define SCT_CONFIG_NORELOAD_H(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
#define SCT_CONFIG_INSYNC_MASK (0x1E00U)
#define SCT_CONFIG_INSYNC_SHIFT (9U)
#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
#define SCT_CONFIG_AUTOLIMIT_L(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
#define SCT_CONFIG_AUTOLIMIT_H(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
/*! @name CTRL - SCT control register */
#define SCT_CTRL_DOWN_L_MASK (0x1U)
#define SCT_CTRL_DOWN_L_SHIFT (0U)
#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
#define SCT_CTRL_STOP_L_MASK (0x2U)
#define SCT_CTRL_STOP_L_SHIFT (1U)
#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
#define SCT_CTRL_HALT_L_MASK (0x4U)
#define SCT_CTRL_HALT_L_SHIFT (2U)
#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
#define SCT_CTRL_BIDIR_L_MASK (0x10U)
#define SCT_CTRL_BIDIR_L_SHIFT (4U)
#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
#define SCT_CTRL_PRE_L_SHIFT (5U)
#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
#define SCT_CTRL_DOWN_H_MASK (0x10000U)
#define SCT_CTRL_DOWN_H_SHIFT (16U)
#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
#define SCT_CTRL_STOP_H_MASK (0x20000U)
#define SCT_CTRL_STOP_H_SHIFT (17U)
#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
#define SCT_CTRL_HALT_H_MASK (0x40000U)
#define SCT_CTRL_HALT_H_SHIFT (18U)
#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
#define SCT_CTRL_BIDIR_H_SHIFT (20U)
#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
#define SCT_CTRL_PRE_H_SHIFT (21U)
#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
/*! @name LIMIT - SCT limit event select register */
#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
/*! @name HALT - SCT halt event select register */
#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
#define SCT_HALT_HALTMSK_L_SHIFT (0U)
#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
#define SCT_HALT_HALTMSK_H_SHIFT (16U)
#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
/*! @name STOP - SCT stop event select register */
#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
#define SCT_STOP_STOPMSK_L_SHIFT (0U)
#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
#define SCT_STOP_STOPMSK_H_SHIFT (16U)
#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
/*! @name START - SCT start event select register */
#define SCT_START_STARTMSK_L_MASK (0xFFFFU)
#define SCT_START_STARTMSK_L_SHIFT (0U)
#define SCT_START_STARTMSK_L(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
#define SCT_START_STARTMSK_H_SHIFT (16U)
#define SCT_START_STARTMSK_H(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
/*! @name COUNT - SCT counter register */
#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
#define SCT_COUNT_CTR_L_SHIFT (0U)
#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
#define SCT_COUNT_CTR_H_SHIFT (16U)
#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
/*! @name STATE - SCT state register */
#define SCT_STATE_STATE_L_MASK (0x1FU)
#define SCT_STATE_STATE_L_SHIFT (0U)
#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
#define SCT_STATE_STATE_H_MASK (0x1F0000U)
#define SCT_STATE_STATE_H_SHIFT (16U)
#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
/*! @name INPUT - SCT input register */
#define SCT_INPUT_AIN0_MASK (0x1U)
#define SCT_INPUT_AIN0_SHIFT (0U)
#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
#define SCT_INPUT_AIN1_MASK (0x2U)
#define SCT_INPUT_AIN1_SHIFT (1U)
#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
#define SCT_INPUT_AIN2_MASK (0x4U)
#define SCT_INPUT_AIN2_SHIFT (2U)
#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
#define SCT_INPUT_AIN3_MASK (0x8U)
#define SCT_INPUT_AIN3_SHIFT (3U)
#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
#define SCT_INPUT_AIN4_MASK (0x10U)
#define SCT_INPUT_AIN4_SHIFT (4U)
#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
#define SCT_INPUT_AIN5_MASK (0x20U)
#define SCT_INPUT_AIN5_SHIFT (5U)
#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
#define SCT_INPUT_AIN6_MASK (0x40U)
#define SCT_INPUT_AIN6_SHIFT (6U)
#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
#define SCT_INPUT_AIN7_MASK (0x80U)
#define SCT_INPUT_AIN7_SHIFT (7U)
#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
#define SCT_INPUT_AIN8_MASK (0x100U)
#define SCT_INPUT_AIN8_SHIFT (8U)
#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
#define SCT_INPUT_AIN9_MASK (0x200U)
#define SCT_INPUT_AIN9_SHIFT (9U)
#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
#define SCT_INPUT_AIN10_MASK (0x400U)
#define SCT_INPUT_AIN10_SHIFT (10U)
#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
#define SCT_INPUT_AIN11_MASK (0x800U)
#define SCT_INPUT_AIN11_SHIFT (11U)
#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
#define SCT_INPUT_AIN12_MASK (0x1000U)
#define SCT_INPUT_AIN12_SHIFT (12U)
#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
#define SCT_INPUT_AIN13_MASK (0x2000U)
#define SCT_INPUT_AIN13_SHIFT (13U)
#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
#define SCT_INPUT_AIN14_MASK (0x4000U)
#define SCT_INPUT_AIN14_SHIFT (14U)
#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
#define SCT_INPUT_AIN15_MASK (0x8000U)
#define SCT_INPUT_AIN15_SHIFT (15U)
#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
#define SCT_INPUT_SIN0_MASK (0x10000U)
#define SCT_INPUT_SIN0_SHIFT (16U)
#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
#define SCT_INPUT_SIN1_MASK (0x20000U)
#define SCT_INPUT_SIN1_SHIFT (17U)
#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
#define SCT_INPUT_SIN2_MASK (0x40000U)
#define SCT_INPUT_SIN2_SHIFT (18U)
#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
#define SCT_INPUT_SIN3_MASK (0x80000U)
#define SCT_INPUT_SIN3_SHIFT (19U)
#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
#define SCT_INPUT_SIN4_MASK (0x100000U)
#define SCT_INPUT_SIN4_SHIFT (20U)
#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
#define SCT_INPUT_SIN5_MASK (0x200000U)
#define SCT_INPUT_SIN5_SHIFT (21U)
#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
#define SCT_INPUT_SIN6_MASK (0x400000U)
#define SCT_INPUT_SIN6_SHIFT (22U)
#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
#define SCT_INPUT_SIN7_MASK (0x800000U)
#define SCT_INPUT_SIN7_SHIFT (23U)
#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
#define SCT_INPUT_SIN8_MASK (0x1000000U)
#define SCT_INPUT_SIN8_SHIFT (24U)
#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
#define SCT_INPUT_SIN9_MASK (0x2000000U)
#define SCT_INPUT_SIN9_SHIFT (25U)
#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
#define SCT_INPUT_SIN10_MASK (0x4000000U)
#define SCT_INPUT_SIN10_SHIFT (26U)
#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
#define SCT_INPUT_SIN11_MASK (0x8000000U)
#define SCT_INPUT_SIN11_SHIFT (27U)
#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
#define SCT_INPUT_SIN12_MASK (0x10000000U)
#define SCT_INPUT_SIN12_SHIFT (28U)
#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
#define SCT_INPUT_SIN13_MASK (0x20000000U)
#define SCT_INPUT_SIN13_SHIFT (29U)
#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
#define SCT_INPUT_SIN14_MASK (0x40000000U)
#define SCT_INPUT_SIN14_SHIFT (30U)
#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
#define SCT_INPUT_SIN15_MASK (0x80000000U)
#define SCT_INPUT_SIN15_SHIFT (31U)
#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
/*! @name REGMODE - SCT match/capture mode register */
#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
#define SCT_REGMODE_REGMOD_L(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
#define SCT_REGMODE_REGMOD_H(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
/*! @name OUTPUT - SCT output register */
#define SCT_OUTPUT_OUT_MASK (0xFFFFU)
#define SCT_OUTPUT_OUT_SHIFT (0U)
#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
#define SCT_OUTPUTDIRCTRL_SETCLR0(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
#define SCT_OUTPUTDIRCTRL_SETCLR1(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
#define SCT_OUTPUTDIRCTRL_SETCLR2(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
#define SCT_OUTPUTDIRCTRL_SETCLR3(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
#define SCT_OUTPUTDIRCTRL_SETCLR4(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
#define SCT_OUTPUTDIRCTRL_SETCLR5(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
#define SCT_OUTPUTDIRCTRL_SETCLR6(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
#define SCT_OUTPUTDIRCTRL_SETCLR7(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
#define SCT_OUTPUTDIRCTRL_SETCLR8(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
#define SCT_OUTPUTDIRCTRL_SETCLR9(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)
#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)
#define SCT_OUTPUTDIRCTRL_SETCLR10(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)
#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)
#define SCT_OUTPUTDIRCTRL_SETCLR11(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)
#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)
#define SCT_OUTPUTDIRCTRL_SETCLR12(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)
#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)
#define SCT_OUTPUTDIRCTRL_SETCLR13(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)
#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)
#define SCT_OUTPUTDIRCTRL_SETCLR14(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)
#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)
#define SCT_OUTPUTDIRCTRL_SETCLR15(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
/*! @name RES - SCT conflict resolution register */
#define SCT_RES_O0RES_MASK (0x3U)
#define SCT_RES_O0RES_SHIFT (0U)
#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
#define SCT_RES_O1RES_MASK (0xCU)
#define SCT_RES_O1RES_SHIFT (2U)
#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
#define SCT_RES_O2RES_MASK (0x30U)
#define SCT_RES_O2RES_SHIFT (4U)
#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
#define SCT_RES_O3RES_MASK (0xC0U)
#define SCT_RES_O3RES_SHIFT (6U)
#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
#define SCT_RES_O4RES_MASK (0x300U)
#define SCT_RES_O4RES_SHIFT (8U)
#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
#define SCT_RES_O5RES_MASK (0xC00U)
#define SCT_RES_O5RES_SHIFT (10U)
#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
#define SCT_RES_O6RES_MASK (0x3000U)
#define SCT_RES_O6RES_SHIFT (12U)
#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
#define SCT_RES_O7RES_MASK (0xC000U)
#define SCT_RES_O7RES_SHIFT (14U)
#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
#define SCT_RES_O8RES_MASK (0x30000U)
#define SCT_RES_O8RES_SHIFT (16U)
#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
#define SCT_RES_O9RES_MASK (0xC0000U)
#define SCT_RES_O9RES_SHIFT (18U)
#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
#define SCT_RES_O10RES_MASK (0x300000U)
#define SCT_RES_O10RES_SHIFT (20U)
#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
#define SCT_RES_O11RES_MASK (0xC00000U)
#define SCT_RES_O11RES_SHIFT (22U)
#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
#define SCT_RES_O12RES_MASK (0x3000000U)
#define SCT_RES_O12RES_SHIFT (24U)
#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
#define SCT_RES_O13RES_MASK (0xC000000U)
#define SCT_RES_O13RES_SHIFT (26U)
#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
#define SCT_RES_O14RES_MASK (0x30000000U)
#define SCT_RES_O14RES_SHIFT (28U)
#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
#define SCT_RES_O15RES_MASK (0xC0000000U)
#define SCT_RES_O15RES_SHIFT (30U)
#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
/*! @name DMA0REQUEST - SCT DMA request 0 register */
#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU)
#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U)
#define SCT_DMA0REQUEST_DEV_0(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)
#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U)
#define SCT_DMA0REQUEST_DRL0_SHIFT (30U)
#define SCT_DMA0REQUEST_DRL0(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)
#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U)
#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U)
#define SCT_DMA0REQUEST_DRQ0(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)
/*! @name DMA1REQUEST - SCT DMA request 1 register */
#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU)
#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U)
#define SCT_DMA1REQUEST_DEV_1(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)
#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U)
#define SCT_DMA1REQUEST_DRL1_SHIFT (30U)
#define SCT_DMA1REQUEST_DRL1(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)
#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U)
#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U)
#define SCT_DMA1REQUEST_DRQ1(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)
/*! @name EVEN - SCT event interrupt enable register */
#define SCT_EVEN_IEN_MASK (0xFFFFU)
#define SCT_EVEN_IEN_SHIFT (0U)
#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
/*! @name EVFLAG - SCT event flag register */
#define SCT_EVFLAG_FLAG_MASK (0xFFFFU)
#define SCT_EVFLAG_FLAG_SHIFT (0U)
#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
/*! @name CONEN - SCT conflict interrupt enable register */
#define SCT_CONEN_NCEN_MASK (0xFFFFU)
#define SCT_CONEN_NCEN_SHIFT (0U)
#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
/*! @name CONFLAG - SCT conflict flag register */
#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)
#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
/*! @name SCTCAP - SCT capture register of capture channel */
#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU)
#define SCT_SCTCAP_CAPn_L_SHIFT (0U)
#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)
#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U)
#define SCT_SCTCAP_CAPn_H_SHIFT (16U)
#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)
/* The count of SCT_SCTCAP */
#define SCT_SCTCAP_COUNT (10U)
/*! @name SCTMATCH - SCT match value register of match channels */
#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU)
#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U)
#define SCT_SCTMATCH_MATCHn_L(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)
#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U)
#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U)
#define SCT_SCTMATCH_MATCHn_H(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)
/* The count of SCT_SCTMATCH */
#define SCT_SCTMATCH_COUNT (10U)
/*! @name SCTCAPCTRL - SCT capture control register */
#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU)
#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U)
#define SCT_SCTCAPCTRL_CAPCONn_L(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)
#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U)
#define SCT_SCTCAPCTRL_CAPCONn_H(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)
/* The count of SCT_SCTCAPCTRL */
#define SCT_SCTCAPCTRL_COUNT (10U)
/*! @name SCTMATCHREL - SCT match reload value register */
#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU)
#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U)
#define SCT_SCTMATCHREL_RELOADn_L(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)
#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U)
#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U)
#define SCT_SCTMATCHREL_RELOADn_H(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)
/* The count of SCT_SCTMATCHREL */
#define SCT_SCTMATCHREL_COUNT (10U)
/*! @name EVENT_STATE - SCT event state register 0 */
#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU)
#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U)
#define SCT_EVENT_STATE_STATEMSKn(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)
/* The count of SCT_EVENT_STATE */
#define SCT_EVENT_STATE_COUNT (10U)
/*! @name EVENT_CTRL - SCT event control register 0 */
#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU)
#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U)
#define SCT_EVENT_CTRL_MATCHSEL(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)
#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U)
#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U)
#define SCT_EVENT_CTRL_HEVENT(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)
#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U)
#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U)
#define SCT_EVENT_CTRL_OUTSEL(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)
#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U)
#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U)
#define SCT_EVENT_CTRL_IOSEL(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)
#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U)
#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U)
#define SCT_EVENT_CTRL_IOCOND(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)
#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U)
#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U)
#define SCT_EVENT_CTRL_COMBMODE(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)
#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U)
#define SCT_EVENT_CTRL_STATELD_SHIFT (14U)
#define SCT_EVENT_CTRL_STATELD(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)
#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U)
#define SCT_EVENT_CTRL_STATEV_SHIFT (15U)
#define SCT_EVENT_CTRL_STATEV(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)
#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U)
#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U)
#define SCT_EVENT_CTRL_MATCHMEM(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)
#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U)
#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U)
#define SCT_EVENT_CTRL_DIRECTION(x) \
(((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)
/* The count of SCT_EVENT_CTRL */
#define SCT_EVENT_CTRL_COUNT (10U)
/*! @name OUT_SET - SCT output 0 set register */
#define SCT_OUT_SET_SET_MASK (0xFFFFU)
#define SCT_OUT_SET_SET_SHIFT (0U)
#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
/* The count of SCT_OUT_SET */
#define SCT_OUT_SET_COUNT (8U)
/*! @name OUT_CLR - SCT output 0 clear register */
#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
#define SCT_OUT_CLR_CLR_SHIFT (0U)
#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
/* The count of SCT_OUT_CLR */
#define SCT_OUT_CLR_COUNT (8U)
/*!
* @}
*/ /* end of group SCT_Register_Masks */
/* SCT - Peripheral instance base addresses */
/** Peripheral SCT0 base address */
#define SCT0_BASE (0x40085000u)
/** Peripheral SCT0 base pointer */
#define SCT0 ((SCT_Type *)SCT0_BASE)
/** Array initializer of SCT peripheral base addresses */
#define SCT_BASE_ADDRS \
{ \
SCT0_BASE \
}
/** Array initializer of SCT peripheral base pointers */
#define SCT_BASE_PTRS \
{ \
SCT0 \
}
/** Interrupt vectors for the SCT peripheral type */
#define SCT_IRQS \
{ \
SCT0_IRQn \
}
/*!
* @}
*/ /* end of group SCT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
* @{
*/
/** SPI - Register Layout Typedef */
typedef struct
{
uint8_t RESERVED_0[1024];
__IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */
__IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */
__IO uint32_t
STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
__IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register.
Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
__O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the
corresponding bit in INTENSET to be cleared., offset: 0x410 */
uint8_t RESERVED_1[16];
__IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */
__I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */
uint8_t RESERVED_2[2516];
__IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
__IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
__IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
uint8_t RESERVED_3[4];
__IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
__IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
__I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
uint8_t RESERVED_4[4];
__IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
uint8_t RESERVED_5[12];
__I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
uint8_t RESERVED_6[12];
__I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
uint8_t RESERVED_7[440];
__I uint32_t ID; /**< SPI module Identification. This value appears in the shared Flexcomm peripheral ID register
when SPI is selected., offset: 0xFFC */
} SPI_Type;
/* ----------------------------------------------------------------------------
-- SPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Register_Masks SPI Register Masks
* @{
*/
/*! @name CFG - SPI Configuration register */
#define SPI_CFG_ENABLE_MASK (0x1U)
#define SPI_CFG_ENABLE_SHIFT (0U)
#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
#define SPI_CFG_MASTER_MASK (0x4U)
#define SPI_CFG_MASTER_SHIFT (2U)
#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
#define SPI_CFG_LSBF_MASK (0x8U)
#define SPI_CFG_LSBF_SHIFT (3U)
#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
#define SPI_CFG_CPHA_MASK (0x10U)
#define SPI_CFG_CPHA_SHIFT (4U)
#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
#define SPI_CFG_CPOL_MASK (0x20U)
#define SPI_CFG_CPOL_SHIFT (5U)
#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
#define SPI_CFG_LOOP_MASK (0x80U)
#define SPI_CFG_LOOP_SHIFT (7U)
#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
#define SPI_CFG_SPOL0_MASK (0x100U)
#define SPI_CFG_SPOL0_SHIFT (8U)
#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
#define SPI_CFG_SPOL1_MASK (0x200U)
#define SPI_CFG_SPOL1_SHIFT (9U)
#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
#define SPI_CFG_SPOL2_MASK (0x400U)
#define SPI_CFG_SPOL2_SHIFT (10U)
#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
#define SPI_CFG_SPOL3_MASK (0x800U)
#define SPI_CFG_SPOL3_SHIFT (11U)
#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
/*! @name DLY - SPI Delay register */
#define SPI_DLY_PRE_DELAY_MASK (0xFU)
#define SPI_DLY_PRE_DELAY_SHIFT (0U)
#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
#define SPI_DLY_POST_DELAY_MASK (0xF0U)
#define SPI_DLY_POST_DELAY_SHIFT (4U)
#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
#define SPI_DLY_TRANSFER_DELAY(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
#define SPI_STAT_SSA_MASK (0x10U)
#define SPI_STAT_SSA_SHIFT (4U)
#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
#define SPI_STAT_SSD_MASK (0x20U)
#define SPI_STAT_SSD_SHIFT (5U)
#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
#define SPI_STAT_STALLED_MASK (0x40U)
#define SPI_STAT_STALLED_SHIFT (6U)
#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
#define SPI_STAT_ENDTRANSFER(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
#define SPI_STAT_MSTIDLE_MASK (0x100U)
#define SPI_STAT_MSTIDLE_SHIFT (8U)
#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to
* any implemented bit position causes that bit to be set. */
#define SPI_INTENSET_SSAEN_MASK (0x10U)
#define SPI_INTENSET_SSAEN_SHIFT (4U)
#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
#define SPI_INTENSET_SSDEN_MASK (0x20U)
#define SPI_INTENSET_SSDEN_SHIFT (5U)
#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
#define SPI_INTENSET_MSTIDLEEN(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding
* bit in INTENSET to be cleared. */
#define SPI_INTENCLR_SSAEN_MASK (0x10U)
#define SPI_INTENCLR_SSAEN_SHIFT (4U)
#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
#define SPI_INTENCLR_SSDEN_MASK (0x20U)
#define SPI_INTENCLR_SSDEN_SHIFT (5U)
#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
#define SPI_INTENCLR_MSTIDLE(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
/*! @name DIV - SPI clock Divider */
#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
#define SPI_DIV_DIVVAL_SHIFT (0U)
#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
/*! @name INTSTAT - SPI Interrupt Status */
#define SPI_INTSTAT_SSA_MASK (0x10U)
#define SPI_INTSTAT_SSA_SHIFT (4U)
#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
#define SPI_INTSTAT_SSD_MASK (0x20U)
#define SPI_INTSTAT_SSD_SHIFT (5U)
#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
/*! @name FIFOCFG - FIFO configuration and enable register. */
#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
#define SPI_FIFOCFG_ENABLETX(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
#define SPI_FIFOCFG_ENABLERX(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
#define SPI_FIFOCFG_SIZE_MASK (0x30U)
#define SPI_FIFOCFG_SIZE_SHIFT (4U)
#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
#define SPI_FIFOCFG_DMATX_MASK (0x1000U)
#define SPI_FIFOCFG_DMATX_SHIFT (12U)
#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
#define SPI_FIFOCFG_DMARX_MASK (0x2000U)
#define SPI_FIFOCFG_DMARX_SHIFT (13U)
#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
/*! @name FIFOSTAT - FIFO status register. */
#define SPI_FIFOSTAT_TXERR_MASK (0x1U)
#define SPI_FIFOSTAT_TXERR_SHIFT (0U)
#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
#define SPI_FIFOSTAT_RXERR_MASK (0x2U)
#define SPI_FIFOSTAT_RXERR_SHIFT (1U)
#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
#define SPI_FIFOSTAT_PERINT_MASK (0x8U)
#define SPI_FIFOSTAT_PERINT_SHIFT (3U)
#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
#define SPI_FIFOSTAT_TXEMPTY(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
#define SPI_FIFOSTAT_TXNOTFULL(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
#define SPI_FIFOSTAT_RXNOTEMPTY(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
#define SPI_FIFOTRIG_TXLVLENA(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
#define SPI_FIFOTRIG_RXLVLENA(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
#define SPI_FIFOINTENSET_TXERR(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
#define SPI_FIFOINTENSET_RXERR(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
#define SPI_FIFOINTENSET_TXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
#define SPI_FIFOINTENSET_RXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
#define SPI_FIFOINTENCLR_TXERR(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
#define SPI_FIFOINTENCLR_RXERR(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
#define SPI_FIFOINTENCLR_TXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
#define SPI_FIFOINTENCLR_RXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
/*! @name FIFOINTSTAT - FIFO interrupt status register. */
#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
#define SPI_FIFOINTSTAT_TXERR(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
#define SPI_FIFOINTSTAT_RXERR(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
#define SPI_FIFOINTSTAT_TXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
#define SPI_FIFOINTSTAT_RXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
#define SPI_FIFOINTSTAT_PERINT(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
/*! @name FIFOWR - FIFO write data. */
#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
#define SPI_FIFOWR_TXDATA_SHIFT (0U)
#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
#define SPI_FIFOWR_TXSSEL0_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
#define SPI_FIFOWR_TXSSEL1_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
#define SPI_FIFOWR_TXSSEL2_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
#define SPI_FIFOWR_TXSSEL3_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
#define SPI_FIFOWR_EOT_MASK (0x100000U)
#define SPI_FIFOWR_EOT_SHIFT (20U)
#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
#define SPI_FIFOWR_EOF_MASK (0x200000U)
#define SPI_FIFOWR_EOF_SHIFT (21U)
#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
#define SPI_FIFOWR_LEN_MASK (0xF000000U)
#define SPI_FIFOWR_LEN_SHIFT (24U)
#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
/*! @name FIFORD - FIFO read data. */
#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
#define SPI_FIFORD_RXDATA_SHIFT (0U)
#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
#define SPI_FIFORD_RXSSEL0_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
#define SPI_FIFORD_RXSSEL1_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
#define SPI_FIFORD_RXSSEL2_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
#define SPI_FIFORD_RXSSEL3_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
#define SPI_FIFORD_SOT_MASK (0x100000U)
#define SPI_FIFORD_SOT_SHIFT (20U)
#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
#define SPI_FIFORDNOPOP_RXDATA(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
#define SPI_FIFORDNOPOP_RXSSEL0_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
#define SPI_FIFORDNOPOP_RXSSEL1_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
#define SPI_FIFORDNOPOP_RXSSEL2_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
#define SPI_FIFORDNOPOP_RXSSEL3_N(x) \
(((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
/*! @name ID - SPI module Identification. This value appears in the shared Flexcomm peripheral ID register when SPI is
* selected. */
#define SPI_ID_APERTURE_MASK (0xFFU)
#define SPI_ID_APERTURE_SHIFT (0U)
#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
#define SPI_ID_MINOR_REV_MASK (0xF00U)
#define SPI_ID_MINOR_REV_SHIFT (8U)
#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
#define SPI_ID_MAJOR_REV_MASK (0xF000U)
#define SPI_ID_MAJOR_REV_SHIFT (12U)
#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
#define SPI_ID_ID_MASK (0xFFFF0000U)
#define SPI_ID_ID_SHIFT (16U)
#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
/*!
* @}
*/ /* end of group SPI_Register_Masks */
/* SPI - Peripheral instance base addresses */
/** Peripheral SPI0 base address */
#define SPI0_BASE (0x40087000u)
/** Peripheral SPI0 base pointer */
#define SPI0 ((SPI_Type *)SPI0_BASE)
/** Peripheral SPI1 base address */
#define SPI1_BASE (0x4008F000u)
/** Peripheral SPI1 base pointer */
#define SPI1 ((SPI_Type *)SPI1_BASE)
/** Array initializer of SPI peripheral base addresses */
#define SPI_BASE_ADDRS \
{ \
SPI0_BASE, SPI1_BASE \
}
/** Array initializer of SPI peripheral base pointers */
#define SPI_BASE_PTRS \
{ \
SPI0, SPI1 \
}
/** Interrupt vectors for the SPI peripheral type */
#define SPI_IRQS \
{ \
FLEXCOMM2_IRQn, FLEXCOMM3_IRQn \
}
/*!
* @}
*/ /* end of group SPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SPIFI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
* @{
*/
/** SPIFI - Register Layout Typedef */
typedef struct
{
__IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */
__IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */
__IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */
__IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */
__IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */
__IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */
__IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */
__IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */
} SPIFI_Type;
/* ----------------------------------------------------------------------------
-- SPIFI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPIFI_Register_Masks SPIFI Register Masks
* @{
*/
/*! @name CTRL - SPIFI control register */
#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU)
#define SPIFI_CTRL_TIMEOUT_SHIFT (0U)
#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U)
#define SPIFI_CTRL_CSHIGH_SHIFT (16U)
#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U)
#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U)
#define SPIFI_CTRL_D_PRFTCH_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
#define SPIFI_CTRL_INTEN_MASK (0x400000U)
#define SPIFI_CTRL_INTEN_SHIFT (22U)
#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
#define SPIFI_CTRL_MODE3_MASK (0x800000U)
#define SPIFI_CTRL_MODE3_SHIFT (23U)
#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U)
#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U)
#define SPIFI_CTRL_PRFTCH_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
#define SPIFI_CTRL_DUAL_MASK (0x10000000U)
#define SPIFI_CTRL_DUAL_SHIFT (28U)
#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
#define SPIFI_CTRL_RFCLK_MASK (0x20000000U)
#define SPIFI_CTRL_RFCLK_SHIFT (29U)
#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
#define SPIFI_CTRL_FBCLK_MASK (0x40000000U)
#define SPIFI_CTRL_FBCLK_SHIFT (30U)
#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
#define SPIFI_CTRL_DMAEN_MASK (0x80000000U)
#define SPIFI_CTRL_DMAEN_SHIFT (31U)
#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
/*! @name CMD - SPIFI command register */
#define SPIFI_CMD_DATALEN_MASK (0x3FFFU)
#define SPIFI_CMD_DATALEN_SHIFT (0U)
#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
#define SPIFI_CMD_POLL_MASK (0x4000U)
#define SPIFI_CMD_POLL_SHIFT (14U)
#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
#define SPIFI_CMD_DOUT_MASK (0x8000U)
#define SPIFI_CMD_DOUT_SHIFT (15U)
#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
#define SPIFI_CMD_INTLEN_MASK (0x70000U)
#define SPIFI_CMD_INTLEN_SHIFT (16U)
#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
#define SPIFI_CMD_FIELDFORM_MASK (0x180000U)
#define SPIFI_CMD_FIELDFORM_SHIFT (19U)
#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U)
#define SPIFI_CMD_FRAMEFORM_SHIFT (21U)
#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
#define SPIFI_CMD_OPCODE_MASK (0xFF000000U)
#define SPIFI_CMD_OPCODE_SHIFT (24U)
#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
/*! @name ADDR - SPIFI address register */
#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU)
#define SPIFI_ADDR_ADDRESS_SHIFT (0U)
#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
/*! @name IDATA - SPIFI intermediate data register */
#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU)
#define SPIFI_IDATA_IDATA_SHIFT (0U)
#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
/*! @name CLIMIT - SPIFI limit register */
#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU)
#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U)
#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
/*! @name DATA - SPIFI data register */
#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU)
#define SPIFI_DATA_DATA_SHIFT (0U)
#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
/*! @name MCMD - SPIFI memory command register */
#define SPIFI_MCMD_POLL_MASK (0x4000U)
#define SPIFI_MCMD_POLL_SHIFT (14U)
#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
#define SPIFI_MCMD_DOUT_MASK (0x8000U)
#define SPIFI_MCMD_DOUT_SHIFT (15U)
#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
#define SPIFI_MCMD_INTLEN_MASK (0x70000U)
#define SPIFI_MCMD_INTLEN_SHIFT (16U)
#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U)
#define SPIFI_MCMD_FIELDFORM_SHIFT (19U)
#define SPIFI_MCMD_FIELDFORM(x) \
(((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U)
#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U)
#define SPIFI_MCMD_FRAMEFORM(x) \
(((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U)
#define SPIFI_MCMD_OPCODE_SHIFT (24U)
#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
/*! @name STAT - SPIFI status register */
#define SPIFI_STAT_MCINIT_MASK (0x1U)
#define SPIFI_STAT_MCINIT_SHIFT (0U)
#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
#define SPIFI_STAT_CMD_MASK (0x2U)
#define SPIFI_STAT_CMD_SHIFT (1U)
#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
#define SPIFI_STAT_RESET_MASK (0x10U)
#define SPIFI_STAT_RESET_SHIFT (4U)
#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
#define SPIFI_STAT_INTRQ_MASK (0x20U)
#define SPIFI_STAT_INTRQ_SHIFT (5U)
#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
#define SPIFI_STAT_VERSION_MASK (0xFF000000U)
#define SPIFI_STAT_VERSION_SHIFT (24U)
#define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK)
/*!
* @}
*/ /* end of group SPIFI_Register_Masks */
/* SPIFI - Peripheral instance base addresses */
/** Peripheral SPIFI0 base address */
#define SPIFI0_BASE (0x40080000u)
/** Peripheral SPIFI0 base pointer */
#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE)
/** Array initializer of SPIFI peripheral base addresses */
#define SPIFI_BASE_ADDRS \
{ \
SPIFI0_BASE \
}
/** Array initializer of SPIFI peripheral base pointers */
#define SPIFI_BASE_PTRS \
{ \
SPIFI0 \
}
/** Interrupt vectors for the SPIFI peripheral type */
#define SPIFI_IRQS \
{ \
SPIFI0_IRQn \
}
/*!
* @}
*/ /* end of group SPIFI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SYSCON Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
* @{
*/
/** SYSCON - Register Layout Typedef */
typedef struct
{
__IO uint32_t RST_SW_SET; /**< block software reset set register, offset: 0x0 */
__IO uint32_t RST_SW_CLR; /**< block software reset clear register, offset: 0x4 */
__IO uint32_t CLK_DIS; /**< clock disable register, offset: 0x8 */
__IO uint32_t CLK_EN; /**< clock enable register, offset: 0xC */
__IO uint32_t CLK_CTRL; /**< system clock source and divider register, offset: 0x10 */
__IO uint32_t SYS_MODE_CTRL; /**< system mode and address remap register, offset: 0x14 */
uint8_t RESERVED_0[104];
__I uint32_t SYS_STAT; /**< system status register, offset: 0x80 */
uint8_t RESERVED_1[124];
__IO uint32_t SYS_TICK; /**< systick timer control register, offset: 0x100 */
__IO uint32_t SRAM_CTRL; /**< Exchange memory base address register, offset: 0x104 */
__I uint32_t CHIP_ID; /**< chip id register, offset: 0x108 */
uint8_t RESERVED_2[4];
__IO uint32_t ANA_CTRL0; /**< crystal and PA register, offset: 0x110 */
uint8_t RESERVED_3[108];
__IO uint32_t XTAL_CTRL; /**< crystal control register, offset: 0x180 */
__IO uint32_t BUCK; /**< buck control register, offset: 0x184 */
uint8_t RESERVED_4[120];
__IO uint32_t FC_FRG; /**< flexcomm 0 and 1 clock divider register, offset: 0x200 */
uint8_t RESERVED_5[1532];
__IO uint32_t PIO_PULL_CFG[3]; /**< pad pull control register 0..pad pull control register 2, array offset: 0x800,
array step: 0x4 */
__IO uint32_t IO_CAP; /**< io status capture register, offset: 0x80C */
__IO uint32_t PIO_DRV_CFG[3]; /**< pad drive strength register 0..pad drive extra register, array offset: 0x810,
array step: 0x4 */
__IO uint32_t PIO_CFG_MISC; /**< pin misc control register, offset: 0x81C */
__IO uint32_t PIO_WAKEUP_LVL0; /**< pin wakeup polarity register 0, offset: 0x820 */
__IO uint32_t PIO_WAKEUP_LVL1; /**< pin wakeup polarity register 1, offset: 0x824 */
__IO uint32_t PIO_IE_CFG0; /**< pad input enable register 0, offset: 0x828 */
__IO uint32_t PIO_IE_CFG1; /**< pad input enable register 1, offset: 0x82C */
__IO uint32_t PIO_FUNC_CFG[4]; /**< pin mux control register 0..pin mux control register 3, array offset: 0x830,
array step: 0x4 */
__IO uint32_t PIO_WAKEUP_EN0; /**< pin function selection in power down mode register 0, offset: 0x840 */
__IO uint32_t PIO_WAKEUP_EN1; /**< pin function selection in power down mode register 1, offset: 0x844 */
__I uint32_t
PIO_CAP_OE0; /**< pin output enable status register 0 while captured by writing 1 to IO_CAP, offset: 0x848 */
__I uint32_t
PIO_CAP_OE1; /**< pin output enable status register 1 while captured by writing 1 to IO_CAP, offset: 0x84C */
__I uint32_t PIO_CAP_OUT0; /**< pin output status register 0 while captured by writing 1 to IO_CAP, offset: 0x850 */
__I uint32_t PIO_CAP_OUT1; /**< pin output status register 0 while captured by writing 1 to IO_CAP, offset: 0x854 */
__IO uint32_t RST_CAUSE_SRC; /**< reset source status register, offset: 0x858 */
__IO uint32_t PMU_CTRL0; /**< power management uinit control register 0, offset: 0x85C */
__IO uint32_t PMU_CTRL1; /**< power management uinit control register 1, offset: 0x860 */
__IO uint32_t ANA_EN; /**< analog setting register, offset: 0x864 */
__IO uint32_t XTAL32K_CTRL; /**< crystal 32K control register, offset: 0x868 */
__IO uint32_t USB_CFG; /**< USB configuration register, offset: 0x86C */
uint8_t RESERVED_6[16];
__IO uint32_t PMU_CTRL2; /**< power management uinit control register 2, offset: 0x880 */
__IO uint32_t ANA_CTRL1; /**< IVREF and DVREG setting register, offset: 0x884 */
uint8_t RESERVED_7[8];
__IO uint32_t MISC; /**< MISC register, offset: 0x890 */
} SYSCON_Type;
/* ----------------------------------------------------------------------------
-- SYSCON Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SYSCON_Register_Masks SYSCON Register Masks
* @{
*/
/*! @name RST_SW_SET - block software reset set register */
#define SYSCON_RST_SW_SET_SET_FC0_RST_MASK (0x1U)
#define SYSCON_RST_SW_SET_SET_FC0_RST_SHIFT (0U)
#define SYSCON_RST_SW_SET_SET_FC0_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_FC0_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_FC0_RST_MASK)
#define SYSCON_RST_SW_SET_SET_FC1_RST_MASK (0x2U)
#define SYSCON_RST_SW_SET_SET_FC1_RST_SHIFT (1U)
#define SYSCON_RST_SW_SET_SET_FC1_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_FC1_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_FC1_RST_MASK)
#define SYSCON_RST_SW_SET_SET_FC2_RST_MASK (0x4U)
#define SYSCON_RST_SW_SET_SET_FC2_RST_SHIFT (2U)
#define SYSCON_RST_SW_SET_SET_FC2_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_FC2_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_FC2_RST_MASK)
#define SYSCON_RST_SW_SET_SET_FC3_RST_MASK (0x8U)
#define SYSCON_RST_SW_SET_SET_FC3_RST_SHIFT (3U)
#define SYSCON_RST_SW_SET_SET_FC3_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_FC3_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_FC3_RST_MASK)
#define SYSCON_RST_SW_SET_SET_TIM0_RST_MASK (0x10U)
#define SYSCON_RST_SW_SET_SET_TIM0_RST_SHIFT (4U)
#define SYSCON_RST_SW_SET_SET_TIM0_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_TIM0_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_TIM0_RST_MASK)
#define SYSCON_RST_SW_SET_SET_TIM1_RST_MASK (0x20U)
#define SYSCON_RST_SW_SET_SET_TIM1_RST_SHIFT (5U)
#define SYSCON_RST_SW_SET_SET_TIM1_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_TIM1_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_TIM1_RST_MASK)
#define SYSCON_RST_SW_SET_SET_TIM2_RST_MASK (0x40U)
#define SYSCON_RST_SW_SET_SET_TIM2_RST_SHIFT (6U)
#define SYSCON_RST_SW_SET_SET_TIM2_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_TIM2_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_TIM2_RST_MASK)
#define SYSCON_RST_SW_SET_SET_TIM3_RST_MASK (0x80U)
#define SYSCON_RST_SW_SET_SET_TIM3_RST_SHIFT (7U)
#define SYSCON_RST_SW_SET_SET_TIM3_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_TIM3_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_TIM3_RST_MASK)
#define SYSCON_RST_SW_SET_SET_SCT_RST_MASK (0x100U)
#define SYSCON_RST_SW_SET_SET_SCT_RST_SHIFT (8U)
#define SYSCON_RST_SW_SET_SET_SCT_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_SCT_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_SCT_RST_MASK)
#define SYSCON_RST_SW_SET_SET_WDT_RST_MASK (0x200U)
#define SYSCON_RST_SW_SET_SET_WDT_RST_SHIFT (9U)
#define SYSCON_RST_SW_SET_SET_WDT_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_WDT_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_WDT_RST_MASK)
#define SYSCON_RST_SW_SET_SET_USB_RST_MASK (0x400U)
#define SYSCON_RST_SW_SET_SET_USB_RST_SHIFT (10U)
#define SYSCON_RST_SW_SET_SET_USB_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_USB_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_USB_RST_MASK)
#define SYSCON_RST_SW_SET_SET_GPIO_RST_MASK (0x800U)
#define SYSCON_RST_SW_SET_SET_GPIO_RST_SHIFT (11U)
#define SYSCON_RST_SW_SET_SET_GPIO_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_GPIO_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_GPIO_RST_MASK)
#define SYSCON_RST_SW_SET_SET_RTC_RST_MASK (0x1000U)
#define SYSCON_RST_SW_SET_SET_RTC_RST_SHIFT (12U)
#define SYSCON_RST_SW_SET_SET_RTC_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_RTC_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_RTC_RST_MASK)
#define SYSCON_RST_SW_SET_SET_ADC_RST_MASK (0x2000U)
#define SYSCON_RST_SW_SET_SET_ADC_RST_SHIFT (13U)
#define SYSCON_RST_SW_SET_SET_ADC_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_ADC_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_ADC_RST_MASK)
#define SYSCON_RST_SW_SET_SET_DAC_RST_MASK (0x4000U)
#define SYSCON_RST_SW_SET_SET_DAC_RST_SHIFT (14U)
#define SYSCON_RST_SW_SET_SET_DAC_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_DAC_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_DAC_RST_MASK)
#define SYSCON_RST_SW_SET_SET_CS_RST_MASK (0x8000U)
#define SYSCON_RST_SW_SET_SET_CS_RST_SHIFT (15U)
#define SYSCON_RST_SW_SET_SET_CS_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_CS_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_CS_RST_MASK)
#define SYSCON_RST_SW_SET_SET_FSP_RST_MASK (0x10000U)
#define SYSCON_RST_SW_SET_SET_FSP_RST_SHIFT (16U)
#define SYSCON_RST_SW_SET_SET_FSP_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_FSP_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_FSP_RST_MASK)
#define SYSCON_RST_SW_SET_SET_DMA_RST_MASK (0x20000U)
#define SYSCON_RST_SW_SET_SET_DMA_RST_SHIFT (17U)
#define SYSCON_RST_SW_SET_SET_DMA_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_DMA_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_DMA_RST_MASK)
#define SYSCON_RST_SW_SET_SET_QDEC0_RST_MASK (0x80000U)
#define SYSCON_RST_SW_SET_SET_QDEC0_RST_SHIFT (19U)
#define SYSCON_RST_SW_SET_SET_QDEC0_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_QDEC0_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_QDEC0_RST_MASK)
#define SYSCON_RST_SW_SET_SET_QDEC1_RST_MASK (0x100000U)
#define SYSCON_RST_SW_SET_SET_QDEC1_RST_SHIFT (20U)
#define SYSCON_RST_SW_SET_SET_QDEC1_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_QDEC1_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_QDEC1_RST_MASK)
#define SYSCON_RST_SW_SET_SET_SPIFI_RST_MASK (0x400000U)
#define SYSCON_RST_SW_SET_SET_SPIFI_RST_SHIFT (22U)
#define SYSCON_RST_SW_SET_SET_SPIFI_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_SPIFI_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_SPIFI_RST_MASK)
#define SYSCON_RST_SW_SET_SET_CPU_RST_MASK (0x4000000U)
#define SYSCON_RST_SW_SET_SET_CPU_RST_SHIFT (26U)
#define SYSCON_RST_SW_SET_SET_CPU_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_CPU_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_CPU_RST_MASK)
#define SYSCON_RST_SW_SET_SET_BLE_RST_MASK (0x8000000U)
#define SYSCON_RST_SW_SET_SET_BLE_RST_SHIFT (27U)
#define SYSCON_RST_SW_SET_SET_BLE_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_BLE_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_BLE_RST_MASK)
#define SYSCON_RST_SW_SET_SET_FLASH_RST_MASK (0x10000000U)
#define SYSCON_RST_SW_SET_SET_FLASH_RST_SHIFT (28U)
#define SYSCON_RST_SW_SET_SET_FLASH_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_FLASH_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_FLASH_RST_MASK)
#define SYSCON_RST_SW_SET_SET_DP_RST_MASK (0x20000000U)
#define SYSCON_RST_SW_SET_SET_DP_RST_SHIFT (29U)
#define SYSCON_RST_SW_SET_SET_DP_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_DP_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_DP_RST_MASK)
#define SYSCON_RST_SW_SET_SET_REG_RST_MASK (0x40000000U)
#define SYSCON_RST_SW_SET_SET_REG_RST_SHIFT (30U)
#define SYSCON_RST_SW_SET_SET_REG_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_REG_RST_SHIFT)) & SYSCON_RST_SW_SET_SET_REG_RST_MASK)
#define SYSCON_RST_SW_SET_SET_REBOOT_MASK (0x80000000U)
#define SYSCON_RST_SW_SET_SET_REBOOT_SHIFT (31U)
#define SYSCON_RST_SW_SET_SET_REBOOT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_SET_SET_REBOOT_SHIFT)) & SYSCON_RST_SW_SET_SET_REBOOT_MASK)
/*! @name RST_SW_CLR - block software reset clear register */
#define SYSCON_RST_SW_CLR_CLR_FC0_RST_MASK (0x1U)
#define SYSCON_RST_SW_CLR_CLR_FC0_RST_SHIFT (0U)
#define SYSCON_RST_SW_CLR_CLR_FC0_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_FC0_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_FC0_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_FC1_RST_MASK (0x2U)
#define SYSCON_RST_SW_CLR_CLR_FC1_RST_SHIFT (1U)
#define SYSCON_RST_SW_CLR_CLR_FC1_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_FC1_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_FC1_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_FC2_RST_MASK (0x4U)
#define SYSCON_RST_SW_CLR_CLR_FC2_RST_SHIFT (2U)
#define SYSCON_RST_SW_CLR_CLR_FC2_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_FC2_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_FC2_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_FC3_RST_MASK (0x8U)
#define SYSCON_RST_SW_CLR_CLR_FC3_RST_SHIFT (3U)
#define SYSCON_RST_SW_CLR_CLR_FC3_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_FC3_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_FC3_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_TIM0_RST_MASK (0x10U)
#define SYSCON_RST_SW_CLR_CLR_TIM0_RST_SHIFT (4U)
#define SYSCON_RST_SW_CLR_CLR_TIM0_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_TIM0_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_TIM0_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_TIM1_RST_MASK (0x20U)
#define SYSCON_RST_SW_CLR_CLR_TIM1_RST_SHIFT (5U)
#define SYSCON_RST_SW_CLR_CLR_TIM1_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_TIM1_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_TIM1_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_TIM2_RST_MASK (0x40U)
#define SYSCON_RST_SW_CLR_CLR_TIM2_RST_SHIFT (6U)
#define SYSCON_RST_SW_CLR_CLR_TIM2_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_TIM2_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_TIM2_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_TIM3_RST_MASK (0x80U)
#define SYSCON_RST_SW_CLR_CLR_TIM3_RST_SHIFT (7U)
#define SYSCON_RST_SW_CLR_CLR_TIM3_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_TIM3_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_TIM3_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_SCT_RST_MASK (0x100U)
#define SYSCON_RST_SW_CLR_CLR_SCT_RST_SHIFT (8U)
#define SYSCON_RST_SW_CLR_CLR_SCT_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_SCT_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_SCT_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_WDT_RST_MASK (0x200U)
#define SYSCON_RST_SW_CLR_CLR_WDT_RST_SHIFT (9U)
#define SYSCON_RST_SW_CLR_CLR_WDT_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_WDT_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_WDT_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_USB_RST_MASK (0x400U)
#define SYSCON_RST_SW_CLR_CLR_USB_RST_SHIFT (10U)
#define SYSCON_RST_SW_CLR_CLR_USB_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_USB_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_USB_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_GPIO_RST_MASK (0x800U)
#define SYSCON_RST_SW_CLR_CLR_GPIO_RST_SHIFT (11U)
#define SYSCON_RST_SW_CLR_CLR_GPIO_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_GPIO_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_GPIO_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_RTC_RST_MASK (0x1000U)
#define SYSCON_RST_SW_CLR_CLR_RTC_RST_SHIFT (12U)
#define SYSCON_RST_SW_CLR_CLR_RTC_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_RTC_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_RTC_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_ADC_RST_MASK (0x2000U)
#define SYSCON_RST_SW_CLR_CLR_ADC_RST_SHIFT (13U)
#define SYSCON_RST_SW_CLR_CLR_ADC_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_ADC_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_ADC_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_DAC_RST_MASK (0x4000U)
#define SYSCON_RST_SW_CLR_CLR_DAC_RST_SHIFT (14U)
#define SYSCON_RST_SW_CLR_CLR_DAC_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_DAC_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_DAC_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_CS_RST_MASK (0x8000U)
#define SYSCON_RST_SW_CLR_CLR_CS_RST_SHIFT (15U)
#define SYSCON_RST_SW_CLR_CLR_CS_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_CS_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_CS_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_FSP_RST_MASK (0x10000U)
#define SYSCON_RST_SW_CLR_CLR_FSP_RST_SHIFT (16U)
#define SYSCON_RST_SW_CLR_CLR_FSP_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_FSP_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_FSP_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_DMA_RST_MASK (0x20000U)
#define SYSCON_RST_SW_CLR_CLR_DMA_RST_SHIFT (17U)
#define SYSCON_RST_SW_CLR_CLR_DMA_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_DMA_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_DMA_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_QDEC0_RST_MASK (0x80000U)
#define SYSCON_RST_SW_CLR_CLR_QDEC0_RST_SHIFT (19U)
#define SYSCON_RST_SW_CLR_CLR_QDEC0_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_QDEC0_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_QDEC0_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_QDEC1_RST_MASK (0x100000U)
#define SYSCON_RST_SW_CLR_CLR_QDEC1_RST_SHIFT (20U)
#define SYSCON_RST_SW_CLR_CLR_QDEC1_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_QDEC1_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_QDEC1_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_SPIFI_RST_MASK (0x400000U)
#define SYSCON_RST_SW_CLR_CLR_SPIFI_RST_SHIFT (22U)
#define SYSCON_RST_SW_CLR_CLR_SPIFI_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_SPIFI_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_SPIFI_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_CPU_RST_MASK (0x4000000U)
#define SYSCON_RST_SW_CLR_CLR_CPU_RST_SHIFT (26U)
#define SYSCON_RST_SW_CLR_CLR_CPU_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_CPU_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_CPU_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_BLE_RST_MASK (0x8000000U)
#define SYSCON_RST_SW_CLR_CLR_BLE_RST_SHIFT (27U)
#define SYSCON_RST_SW_CLR_CLR_BLE_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_BLE_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_BLE_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_FLASH_RST_MASK (0x10000000U)
#define SYSCON_RST_SW_CLR_CLR_FLASH_RST_SHIFT (28U)
#define SYSCON_RST_SW_CLR_CLR_FLASH_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_FLASH_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_FLASH_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_DP_RST_MASK (0x20000000U)
#define SYSCON_RST_SW_CLR_CLR_DP_RST_SHIFT (29U)
#define SYSCON_RST_SW_CLR_CLR_DP_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_DP_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_DP_RST_MASK)
#define SYSCON_RST_SW_CLR_CLR_REG_RST_MASK (0x40000000U)
#define SYSCON_RST_SW_CLR_CLR_REG_RST_SHIFT (30U)
#define SYSCON_RST_SW_CLR_CLR_REG_RST(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_SW_CLR_CLR_REG_RST_SHIFT)) & SYSCON_RST_SW_CLR_CLR_REG_RST_MASK)
/*! @name CLK_DIS - clock disable register */
#define SYSCON_CLK_DIS_CLK_FC0_DIS_MASK (0x1U)
#define SYSCON_CLK_DIS_CLK_FC0_DIS_SHIFT (0U)
#define SYSCON_CLK_DIS_CLK_FC0_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_FC0_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_FC0_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_FC1_DIS_MASK (0x2U)
#define SYSCON_CLK_DIS_CLK_FC1_DIS_SHIFT (1U)
#define SYSCON_CLK_DIS_CLK_FC1_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_FC1_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_FC1_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_FC2_DIS_MASK (0x4U)
#define SYSCON_CLK_DIS_CLK_FC2_DIS_SHIFT (2U)
#define SYSCON_CLK_DIS_CLK_FC2_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_FC2_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_FC2_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_FC3_DIS_MASK (0x8U)
#define SYSCON_CLK_DIS_CLK_FC3_DIS_SHIFT (3U)
#define SYSCON_CLK_DIS_CLK_FC3_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_FC3_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_FC3_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_TIM0_DIS_MASK (0x10U)
#define SYSCON_CLK_DIS_CLK_TIM0_DIS_SHIFT (4U)
#define SYSCON_CLK_DIS_CLK_TIM0_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_TIM0_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_TIM0_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_TIM1_DIS_MASK (0x20U)
#define SYSCON_CLK_DIS_CLK_TIM1_DIS_SHIFT (5U)
#define SYSCON_CLK_DIS_CLK_TIM1_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_TIM1_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_TIM1_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_TIM2_DIS_MASK (0x40U)
#define SYSCON_CLK_DIS_CLK_TIM2_DIS_SHIFT (6U)
#define SYSCON_CLK_DIS_CLK_TIM2_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_TIM2_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_TIM2_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_TIM3_DIS_MASK (0x80U)
#define SYSCON_CLK_DIS_CLK_TIM3_DIS_SHIFT (7U)
#define SYSCON_CLK_DIS_CLK_TIM3_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_TIM3_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_TIM3_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_SCT_DIS_MASK (0x100U)
#define SYSCON_CLK_DIS_CLK_SCT_DIS_SHIFT (8U)
#define SYSCON_CLK_DIS_CLK_SCT_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_SCT_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_SCT_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_WDT_DIS_MASK (0x200U)
#define SYSCON_CLK_DIS_CLK_WDT_DIS_SHIFT (9U)
#define SYSCON_CLK_DIS_CLK_WDT_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_WDT_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_WDT_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_USB_DIS_MASK (0x400U)
#define SYSCON_CLK_DIS_CLK_USB_DIS_SHIFT (10U)
#define SYSCON_CLK_DIS_CLK_USB_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_USB_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_USB_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_GPIO_DIS_MASK (0x800U)
#define SYSCON_CLK_DIS_CLK_GPIO_DIS_SHIFT (11U)
#define SYSCON_CLK_DIS_CLK_GPIO_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_GPIO_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_GPIO_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_BIV_DIS_MASK (0x1000U)
#define SYSCON_CLK_DIS_CLK_BIV_DIS_SHIFT (12U)
#define SYSCON_CLK_DIS_CLK_BIV_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_BIV_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_BIV_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_ADC_DIS_MASK (0x2000U)
#define SYSCON_CLK_DIS_CLK_ADC_DIS_SHIFT (13U)
#define SYSCON_CLK_DIS_CLK_ADC_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_ADC_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_ADC_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_DAC_DIS_MASK (0x4000U)
#define SYSCON_CLK_DIS_CLK_DAC_DIS_SHIFT (14U)
#define SYSCON_CLK_DIS_CLK_DAC_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_DAC_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_DAC_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_CS_DIS_MASK (0x8000U)
#define SYSCON_CLK_DIS_CLK_CS_DIS_SHIFT (15U)
#define SYSCON_CLK_DIS_CLK_CS_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_CS_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_CS_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_FSP_DIS_MASK (0x10000U)
#define SYSCON_CLK_DIS_CLK_FSP_DIS_SHIFT (16U)
#define SYSCON_CLK_DIS_CLK_FSP_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_FSP_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_FSP_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_DMA_DIS_MASK (0x20000U)
#define SYSCON_CLK_DIS_CLK_DMA_DIS_SHIFT (17U)
#define SYSCON_CLK_DIS_CLK_DMA_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_DMA_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_DMA_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_QDEC0_DIS_MASK (0x80000U)
#define SYSCON_CLK_DIS_CLK_QDEC0_DIS_SHIFT (19U)
#define SYSCON_CLK_DIS_CLK_QDEC0_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_QDEC0_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_QDEC0_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_QDEC1_DIS_MASK (0x100000U)
#define SYSCON_CLK_DIS_CLK_QDEC1_DIS_SHIFT (20U)
#define SYSCON_CLK_DIS_CLK_QDEC1_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_QDEC1_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_QDEC1_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_DP_DIS_MASK (0x200000U)
#define SYSCON_CLK_DIS_CLK_DP_DIS_SHIFT (21U)
#define SYSCON_CLK_DIS_CLK_DP_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_DP_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_DP_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_SPIFI_DIS_MASK (0x400000U)
#define SYSCON_CLK_DIS_CLK_SPIFI_DIS_SHIFT (22U)
#define SYSCON_CLK_DIS_CLK_SPIFI_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_SPIFI_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_SPIFI_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_CAL_DIS_MASK (0x2000000U)
#define SYSCON_CLK_DIS_CLK_CAL_DIS_SHIFT (25U)
#define SYSCON_CLK_DIS_CLK_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_CAL_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_CAL_DIS_MASK)
#define SYSCON_CLK_DIS_CLK_BLE_DIS_MASK (0x8000000U)
#define SYSCON_CLK_DIS_CLK_BLE_DIS_SHIFT (27U)
#define SYSCON_CLK_DIS_CLK_BLE_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_CLK_BLE_DIS_SHIFT)) & SYSCON_CLK_DIS_CLK_BLE_DIS_MASK)
#define SYSCON_CLK_DIS_PCLK_DIS_MASK (0x40000000U)
#define SYSCON_CLK_DIS_PCLK_DIS_SHIFT (30U)
#define SYSCON_CLK_DIS_PCLK_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_PCLK_DIS_SHIFT)) & SYSCON_CLK_DIS_PCLK_DIS_MASK)
#define SYSCON_CLK_DIS_FCLK_DIS_MASK (0x80000000U)
#define SYSCON_CLK_DIS_FCLK_DIS_SHIFT (31U)
#define SYSCON_CLK_DIS_FCLK_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIS_FCLK_DIS_SHIFT)) & SYSCON_CLK_DIS_FCLK_DIS_MASK)
/*! @name CLK_EN - clock enable register */
#define SYSCON_CLK_EN_CLK_FC0_EN_MASK (0x1U)
#define SYSCON_CLK_EN_CLK_FC0_EN_SHIFT (0U)
#define SYSCON_CLK_EN_CLK_FC0_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_FC0_EN_SHIFT)) & SYSCON_CLK_EN_CLK_FC0_EN_MASK)
#define SYSCON_CLK_EN_CLK_FC1_EN_MASK (0x2U)
#define SYSCON_CLK_EN_CLK_FC1_EN_SHIFT (1U)
#define SYSCON_CLK_EN_CLK_FC1_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_FC1_EN_SHIFT)) & SYSCON_CLK_EN_CLK_FC1_EN_MASK)
#define SYSCON_CLK_EN_CLK_FC2_EN_MASK (0x4U)
#define SYSCON_CLK_EN_CLK_FC2_EN_SHIFT (2U)
#define SYSCON_CLK_EN_CLK_FC2_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_FC2_EN_SHIFT)) & SYSCON_CLK_EN_CLK_FC2_EN_MASK)
#define SYSCON_CLK_EN_CLK_FC3_EN_MASK (0x8U)
#define SYSCON_CLK_EN_CLK_FC3_EN_SHIFT (3U)
#define SYSCON_CLK_EN_CLK_FC3_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_FC3_EN_SHIFT)) & SYSCON_CLK_EN_CLK_FC3_EN_MASK)
#define SYSCON_CLK_EN_CLK_TIM0_EN_MASK (0x10U)
#define SYSCON_CLK_EN_CLK_TIM0_EN_SHIFT (4U)
#define SYSCON_CLK_EN_CLK_TIM0_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_TIM0_EN_SHIFT)) & SYSCON_CLK_EN_CLK_TIM0_EN_MASK)
#define SYSCON_CLK_EN_CLK_TIM1_EN_MASK (0x20U)
#define SYSCON_CLK_EN_CLK_TIM1_EN_SHIFT (5U)
#define SYSCON_CLK_EN_CLK_TIM1_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_TIM1_EN_SHIFT)) & SYSCON_CLK_EN_CLK_TIM1_EN_MASK)
#define SYSCON_CLK_EN_CLK_TIM2_EN_MASK (0x40U)
#define SYSCON_CLK_EN_CLK_TIM2_EN_SHIFT (6U)
#define SYSCON_CLK_EN_CLK_TIM2_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_TIM2_EN_SHIFT)) & SYSCON_CLK_EN_CLK_TIM2_EN_MASK)
#define SYSCON_CLK_EN_CLK_TIM3_EN_MASK (0x80U)
#define SYSCON_CLK_EN_CLK_TIM3_EN_SHIFT (7U)
#define SYSCON_CLK_EN_CLK_TIM3_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_TIM3_EN_SHIFT)) & SYSCON_CLK_EN_CLK_TIM3_EN_MASK)
#define SYSCON_CLK_EN_CLK_SCT_EN_MASK (0x100U)
#define SYSCON_CLK_EN_CLK_SCT_EN_SHIFT (8U)
#define SYSCON_CLK_EN_CLK_SCT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_SCT_EN_SHIFT)) & SYSCON_CLK_EN_CLK_SCT_EN_MASK)
#define SYSCON_CLK_EN_CLK_WDT_EN_MASK (0x200U)
#define SYSCON_CLK_EN_CLK_WDT_EN_SHIFT (9U)
#define SYSCON_CLK_EN_CLK_WDT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_WDT_EN_SHIFT)) & SYSCON_CLK_EN_CLK_WDT_EN_MASK)
#define SYSCON_CLK_EN_CLK_USB_EN_MASK (0x400U)
#define SYSCON_CLK_EN_CLK_USB_EN_SHIFT (10U)
#define SYSCON_CLK_EN_CLK_USB_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_USB_EN_SHIFT)) & SYSCON_CLK_EN_CLK_USB_EN_MASK)
#define SYSCON_CLK_EN_CLK_GPIO_EN_MASK (0x800U)
#define SYSCON_CLK_EN_CLK_GPIO_EN_SHIFT (11U)
#define SYSCON_CLK_EN_CLK_GPIO_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_GPIO_EN_SHIFT)) & SYSCON_CLK_EN_CLK_GPIO_EN_MASK)
#define SYSCON_CLK_EN_CLK_BIV_EN_MASK (0x1000U)
#define SYSCON_CLK_EN_CLK_BIV_EN_SHIFT (12U)
#define SYSCON_CLK_EN_CLK_BIV_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_BIV_EN_SHIFT)) & SYSCON_CLK_EN_CLK_BIV_EN_MASK)
#define SYSCON_CLK_EN_CLK_ADC_EN_MASK (0x2000U)
#define SYSCON_CLK_EN_CLK_ADC_EN_SHIFT (13U)
#define SYSCON_CLK_EN_CLK_ADC_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_ADC_EN_SHIFT)) & SYSCON_CLK_EN_CLK_ADC_EN_MASK)
#define SYSCON_CLK_EN_CLK_DAC_EN_MASK (0x4000U)
#define SYSCON_CLK_EN_CLK_DAC_EN_SHIFT (14U)
#define SYSCON_CLK_EN_CLK_DAC_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_DAC_EN_SHIFT)) & SYSCON_CLK_EN_CLK_DAC_EN_MASK)
#define SYSCON_CLK_EN_CLK_CS_EN_MASK (0x8000U)
#define SYSCON_CLK_EN_CLK_CS_EN_SHIFT (15U)
#define SYSCON_CLK_EN_CLK_CS_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_CS_EN_SHIFT)) & SYSCON_CLK_EN_CLK_CS_EN_MASK)
#define SYSCON_CLK_EN_CLK_FSP_EN_MASK (0x10000U)
#define SYSCON_CLK_EN_CLK_FSP_EN_SHIFT (16U)
#define SYSCON_CLK_EN_CLK_FSP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_FSP_EN_SHIFT)) & SYSCON_CLK_EN_CLK_FSP_EN_MASK)
#define SYSCON_CLK_EN_CLK_DMA_EN_MASK (0x20000U)
#define SYSCON_CLK_EN_CLK_DMA_EN_SHIFT (17U)
#define SYSCON_CLK_EN_CLK_DMA_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_DMA_EN_SHIFT)) & SYSCON_CLK_EN_CLK_DMA_EN_MASK)
#define SYSCON_CLK_EN_CLK_QDEC0_EN_MASK (0x80000U)
#define SYSCON_CLK_EN_CLK_QDEC0_EN_SHIFT (19U)
#define SYSCON_CLK_EN_CLK_QDEC0_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_QDEC0_EN_SHIFT)) & SYSCON_CLK_EN_CLK_QDEC0_EN_MASK)
#define SYSCON_CLK_EN_CLK_QDEC1_EN_MASK (0x100000U)
#define SYSCON_CLK_EN_CLK_QDEC1_EN_SHIFT (20U)
#define SYSCON_CLK_EN_CLK_QDEC1_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_QDEC1_EN_SHIFT)) & SYSCON_CLK_EN_CLK_QDEC1_EN_MASK)
#define SYSCON_CLK_EN_CLK_DP_EN_MASK (0x200000U)
#define SYSCON_CLK_EN_CLK_DP_EN_SHIFT (21U)
#define SYSCON_CLK_EN_CLK_DP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_DP_EN_SHIFT)) & SYSCON_CLK_EN_CLK_DP_EN_MASK)
#define SYSCON_CLK_EN_CLK_SPIFI_EN_MASK (0x400000U)
#define SYSCON_CLK_EN_CLK_SPIFI_EN_SHIFT (22U)
#define SYSCON_CLK_EN_CLK_SPIFI_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_SPIFI_EN_SHIFT)) & SYSCON_CLK_EN_CLK_SPIFI_EN_MASK)
#define SYSCON_CLK_EN_CLK_CAL_EN_MASK (0x2000000U)
#define SYSCON_CLK_EN_CLK_CAL_EN_SHIFT (25U)
#define SYSCON_CLK_EN_CLK_CAL_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_CAL_EN_SHIFT)) & SYSCON_CLK_EN_CLK_CAL_EN_MASK)
#define SYSCON_CLK_EN_CLK_BLE_EN_MASK (0x8000000U)
#define SYSCON_CLK_EN_CLK_BLE_EN_SHIFT (27U)
#define SYSCON_CLK_EN_CLK_BLE_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_EN_CLK_BLE_EN_SHIFT)) & SYSCON_CLK_EN_CLK_BLE_EN_MASK)
/*! @name CLK_CTRL - system clock source and divider register */
#define SYSCON_CLK_CTRL_APB_DIV_MASK (0xFU)
#define SYSCON_CLK_CTRL_APB_DIV_SHIFT (0U)
#define SYSCON_CLK_CTRL_APB_DIV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_APB_DIV_SHIFT)) & SYSCON_CLK_CTRL_APB_DIV_MASK)
#define SYSCON_CLK_CTRL_AHB_DIV_MASK (0x1FFF0U)
#define SYSCON_CLK_CTRL_AHB_DIV_SHIFT (4U)
#define SYSCON_CLK_CTRL_AHB_DIV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_AHB_DIV_SHIFT)) & SYSCON_CLK_CTRL_AHB_DIV_MASK)
#define SYSCON_CLK_CTRL_CLK_BLE_SEL_MASK (0x20000U)
#define SYSCON_CLK_CTRL_CLK_BLE_SEL_SHIFT (17U)
#define SYSCON_CLK_CTRL_CLK_BLE_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_CLK_BLE_SEL_SHIFT)) & SYSCON_CLK_CTRL_CLK_BLE_SEL_MASK)
#define SYSCON_CLK_CTRL_CLK_WDT_SEL_MASK (0x40000U)
#define SYSCON_CLK_CTRL_CLK_WDT_SEL_SHIFT (18U)
#define SYSCON_CLK_CTRL_CLK_WDT_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_CLK_WDT_SEL_SHIFT)) & SYSCON_CLK_CTRL_CLK_WDT_SEL_MASK)
#define SYSCON_CLK_CTRL_CLK_XTAL_SEL_MASK (0x80000U)
#define SYSCON_CLK_CTRL_CLK_XTAL_SEL_SHIFT (19U)
#define SYSCON_CLK_CTRL_CLK_XTAL_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_CLK_XTAL_SEL_SHIFT)) & SYSCON_CLK_CTRL_CLK_XTAL_SEL_MASK)
#define SYSCON_CLK_CTRL_CLK_OSC32M_DIV_MASK (0x100000U)
#define SYSCON_CLK_CTRL_CLK_OSC32M_DIV_SHIFT (20U)
#define SYSCON_CLK_CTRL_CLK_OSC32M_DIV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_CLK_OSC32M_DIV_SHIFT)) & SYSCON_CLK_CTRL_CLK_OSC32M_DIV_MASK)
#define SYSCON_CLK_CTRL_CLK_32K_SEL_MASK (0x200000U)
#define SYSCON_CLK_CTRL_CLK_32K_SEL_SHIFT (21U)
#define SYSCON_CLK_CTRL_CLK_32K_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_CLK_32K_SEL_SHIFT)) & SYSCON_CLK_CTRL_CLK_32K_SEL_MASK)
#define SYSCON_CLK_CTRL_CLK_XTAL_OE_MASK (0x400000U)
#define SYSCON_CLK_CTRL_CLK_XTAL_OE_SHIFT (22U)
#define SYSCON_CLK_CTRL_CLK_XTAL_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_CLK_XTAL_OE_SHIFT)) & SYSCON_CLK_CTRL_CLK_XTAL_OE_MASK)
#define SYSCON_CLK_CTRL_CLK_32K_OE_MASK (0x800000U)
#define SYSCON_CLK_CTRL_CLK_32K_OE_SHIFT (23U)
#define SYSCON_CLK_CTRL_CLK_32K_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_CLK_32K_OE_SHIFT)) & SYSCON_CLK_CTRL_CLK_32K_OE_MASK)
#define SYSCON_CLK_CTRL_XTAL_OUT_DIV_MASK (0xF000000U)
#define SYSCON_CLK_CTRL_XTAL_OUT_DIV_SHIFT (24U)
#define SYSCON_CLK_CTRL_XTAL_OUT_DIV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_XTAL_OUT_DIV_SHIFT)) & SYSCON_CLK_CTRL_XTAL_OUT_DIV_MASK)
#define SYSCON_CLK_CTRL_CGBYPASS_MASK (0x10000000U)
#define SYSCON_CLK_CTRL_CGBYPASS_SHIFT (28U)
#define SYSCON_CLK_CTRL_CGBYPASS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_CGBYPASS_SHIFT)) & SYSCON_CLK_CTRL_CGBYPASS_MASK)
#define SYSCON_CLK_CTRL_SYS_CLK_SEL_MASK (0xC0000000U)
#define SYSCON_CLK_CTRL_SYS_CLK_SEL_SHIFT (30U)
#define SYSCON_CLK_CTRL_SYS_CLK_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_CTRL_SYS_CLK_SEL_SHIFT)) & SYSCON_CLK_CTRL_SYS_CLK_SEL_MASK)
/*! @name SYS_MODE_CTRL - system mode and address remap register */
#define SYSCON_SYS_MODE_CTRL_REMAP_MASK (0x3U)
#define SYSCON_SYS_MODE_CTRL_REMAP_SHIFT (0U)
#define SYSCON_SYS_MODE_CTRL_REMAP(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_MODE_CTRL_REMAP_SHIFT)) & SYSCON_SYS_MODE_CTRL_REMAP_MASK)
#define SYSCON_SYS_MODE_CTRL_LOCKUP_EN_MASK (0x4U)
#define SYSCON_SYS_MODE_CTRL_LOCKUP_EN_SHIFT (2U)
#define SYSCON_SYS_MODE_CTRL_LOCKUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_MODE_CTRL_LOCKUP_EN_SHIFT)) & SYSCON_SYS_MODE_CTRL_LOCKUP_EN_MASK)
#define SYSCON_SYS_MODE_CTRL_XTAL_RDY_MASK (0x2000000U)
#define SYSCON_SYS_MODE_CTRL_XTAL_RDY_SHIFT (25U)
#define SYSCON_SYS_MODE_CTRL_XTAL_RDY(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_MODE_CTRL_XTAL_RDY_SHIFT)) & SYSCON_SYS_MODE_CTRL_XTAL_RDY_MASK)
#define SYSCON_SYS_MODE_CTRL_XTAL32K_RDY_MASK (0x4000000U)
#define SYSCON_SYS_MODE_CTRL_XTAL32K_RDY_SHIFT (26U)
#define SYSCON_SYS_MODE_CTRL_XTAL32K_RDY(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_MODE_CTRL_XTAL32K_RDY_SHIFT)) & SYSCON_SYS_MODE_CTRL_XTAL32K_RDY_MASK)
#define SYSCON_SYS_MODE_CTRL_PLL48M_RDY_MASK (0x8000000U)
#define SYSCON_SYS_MODE_CTRL_PLL48M_RDY_SHIFT (27U)
#define SYSCON_SYS_MODE_CTRL_PLL48M_RDY(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_MODE_CTRL_PLL48M_RDY_SHIFT)) & SYSCON_SYS_MODE_CTRL_PLL48M_RDY_MASK)
#define SYSCON_SYS_MODE_CTRL_OSC32M_RDY_MASK (0x10000000U)
#define SYSCON_SYS_MODE_CTRL_OSC32M_RDY_SHIFT (28U)
#define SYSCON_SYS_MODE_CTRL_OSC32M_RDY(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_MODE_CTRL_OSC32M_RDY_SHIFT)) & SYSCON_SYS_MODE_CTRL_OSC32M_RDY_MASK)
#define SYSCON_SYS_MODE_CTRL_BG_RDY_MASK (0x20000000U)
#define SYSCON_SYS_MODE_CTRL_BG_RDY_SHIFT (29U)
#define SYSCON_SYS_MODE_CTRL_BG_RDY(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_MODE_CTRL_BG_RDY_SHIFT)) & SYSCON_SYS_MODE_CTRL_BG_RDY_MASK)
#define SYSCON_SYS_MODE_CTRL_BOOT_MODE_MASK (0x80000000U)
#define SYSCON_SYS_MODE_CTRL_BOOT_MODE_SHIFT (31U)
#define SYSCON_SYS_MODE_CTRL_BOOT_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_MODE_CTRL_BOOT_MODE_SHIFT)) & SYSCON_SYS_MODE_CTRL_BOOT_MODE_MASK)
/*! @name SYS_STAT - system status register */
#define SYSCON_SYS_STAT_FREQ_WORD_MASK (0xFFU)
#define SYSCON_SYS_STAT_FREQ_WORD_SHIFT (0U)
#define SYSCON_SYS_STAT_FREQ_WORD(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_STAT_FREQ_WORD_SHIFT)) & SYSCON_SYS_STAT_FREQ_WORD_MASK)
#define SYSCON_SYS_STAT_BLE_FREQ_HOP_MASK (0x100U)
#define SYSCON_SYS_STAT_BLE_FREQ_HOP_SHIFT (8U)
#define SYSCON_SYS_STAT_BLE_FREQ_HOP(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_STAT_BLE_FREQ_HOP_SHIFT)) & SYSCON_SYS_STAT_BLE_FREQ_HOP_MASK)
#define SYSCON_SYS_STAT_EVENT_IN_PROCESS_MASK (0x200U)
#define SYSCON_SYS_STAT_EVENT_IN_PROCESS_SHIFT (9U)
#define SYSCON_SYS_STAT_EVENT_IN_PROCESS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_STAT_EVENT_IN_PROCESS_SHIFT)) & SYSCON_SYS_STAT_EVENT_IN_PROCESS_MASK)
#define SYSCON_SYS_STAT_RX_EN_MASK (0x400U)
#define SYSCON_SYS_STAT_RX_EN_SHIFT (10U)
#define SYSCON_SYS_STAT_RX_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_STAT_RX_EN_SHIFT)) & SYSCON_SYS_STAT_RX_EN_MASK)
#define SYSCON_SYS_STAT_TX_EN_MASK (0x800U)
#define SYSCON_SYS_STAT_TX_EN_SHIFT (11U)
#define SYSCON_SYS_STAT_TX_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_STAT_TX_EN_SHIFT)) & SYSCON_SYS_STAT_TX_EN_MASK)
#define SYSCON_SYS_STAT_OSC_EN_MASK (0x1000U)
#define SYSCON_SYS_STAT_OSC_EN_SHIFT (12U)
#define SYSCON_SYS_STAT_OSC_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_STAT_OSC_EN_SHIFT)) & SYSCON_SYS_STAT_OSC_EN_MASK)
#define SYSCON_SYS_STAT_RADIO_EN_MASK (0x2000U)
#define SYSCON_SYS_STAT_RADIO_EN_SHIFT (13U)
#define SYSCON_SYS_STAT_RADIO_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_STAT_RADIO_EN_SHIFT)) & SYSCON_SYS_STAT_RADIO_EN_MASK)
#define SYSCON_SYS_STAT_CLK_STATUS_MASK (0x4000U)
#define SYSCON_SYS_STAT_CLK_STATUS_SHIFT (14U)
#define SYSCON_SYS_STAT_CLK_STATUS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_STAT_CLK_STATUS_SHIFT)) & SYSCON_SYS_STAT_CLK_STATUS_MASK)
/*! @name SYS_TICK - systick timer control register */
#define SYSCON_SYS_TICK_TENMS_MASK (0xFFFFFFU)
#define SYSCON_SYS_TICK_TENMS_SHIFT (0U)
#define SYSCON_SYS_TICK_TENMS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_TICK_TENMS_SHIFT)) & SYSCON_SYS_TICK_TENMS_MASK)
#define SYSCON_SYS_TICK_SKEW_MASK (0x1000000U)
#define SYSCON_SYS_TICK_SKEW_SHIFT (24U)
#define SYSCON_SYS_TICK_SKEW(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_TICK_SKEW_SHIFT)) & SYSCON_SYS_TICK_SKEW_MASK)
#define SYSCON_SYS_TICK_NOREF_MASK (0x2000000U)
#define SYSCON_SYS_TICK_NOREF_SHIFT (25U)
#define SYSCON_SYS_TICK_NOREF(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_TICK_NOREF_SHIFT)) & SYSCON_SYS_TICK_NOREF_MASK)
#define SYSCON_SYS_TICK_EN_STCLKEN_MASK (0x80000000U)
#define SYSCON_SYS_TICK_EN_STCLKEN_SHIFT (31U)
#define SYSCON_SYS_TICK_EN_STCLKEN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_TICK_EN_STCLKEN_SHIFT)) & SYSCON_SYS_TICK_EN_STCLKEN_MASK)
/*! @name SRAM_CTRL - Exchange memory base address register */
#define SYSCON_SRAM_CTRL_EM_BASE_ADDR_MASK (0x7FFFU)
#define SYSCON_SRAM_CTRL_EM_BASE_ADDR_SHIFT (0U)
#define SYSCON_SRAM_CTRL_EM_BASE_ADDR(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_CTRL_EM_BASE_ADDR_SHIFT)) & SYSCON_SRAM_CTRL_EM_BASE_ADDR_MASK)
/*! @name CHIP_ID - chip id register */
#define SYSCON_CHIP_ID_CID0_MASK (0x7U)
#define SYSCON_CHIP_ID_CID0_SHIFT (0U)
#define SYSCON_CHIP_ID_CID0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_CID0_SHIFT)) & SYSCON_CHIP_ID_CID0_MASK)
#define SYSCON_CHIP_ID_CID1_MASK (0x38U)
#define SYSCON_CHIP_ID_CID1_SHIFT (3U)
#define SYSCON_CHIP_ID_CID1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_CID1_SHIFT)) & SYSCON_CHIP_ID_CID1_MASK)
#define SYSCON_CHIP_ID_CID2_MASK (0xC0U)
#define SYSCON_CHIP_ID_CID2_SHIFT (6U)
#define SYSCON_CHIP_ID_CID2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_CID2_SHIFT)) & SYSCON_CHIP_ID_CID2_MASK)
#define SYSCON_CHIP_ID_CID3_MASK (0x3F00U)
#define SYSCON_CHIP_ID_CID3_SHIFT (8U)
#define SYSCON_CHIP_ID_CID3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_CID3_SHIFT)) & SYSCON_CHIP_ID_CID3_MASK)
#define SYSCON_CHIP_ID_CID4_MASK (0xC000U)
#define SYSCON_CHIP_ID_CID4_SHIFT (14U)
#define SYSCON_CHIP_ID_CID4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_CID4_SHIFT)) & SYSCON_CHIP_ID_CID4_MASK)
#define SYSCON_CHIP_ID_MEM_OPTION_MASK (0x4000000U)
#define SYSCON_CHIP_ID_MEM_OPTION_SHIFT (26U)
#define SYSCON_CHIP_ID_MEM_OPTION(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_MEM_OPTION_SHIFT)) & SYSCON_CHIP_ID_MEM_OPTION_MASK)
#define SYSCON_CHIP_ID_ADC_OPTION_MASK (0x8000000U)
#define SYSCON_CHIP_ID_ADC_OPTION_SHIFT (27U)
#define SYSCON_CHIP_ID_ADC_OPTION(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_ADC_OPTION_SHIFT)) & SYSCON_CHIP_ID_ADC_OPTION_MASK)
#define SYSCON_CHIP_ID_FLASH_OPTION_MASK (0x10000000U)
#define SYSCON_CHIP_ID_FLASH_OPTION_SHIFT (28U)
#define SYSCON_CHIP_ID_FLASH_OPTION(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_FLASH_OPTION_SHIFT)) & SYSCON_CHIP_ID_FLASH_OPTION_MASK)
#define SYSCON_CHIP_ID_FPU_OPTION_MASK (0x20000000U)
#define SYSCON_CHIP_ID_FPU_OPTION_SHIFT (29U)
#define SYSCON_CHIP_ID_FPU_OPTION(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_FPU_OPTION_SHIFT)) & SYSCON_CHIP_ID_FPU_OPTION_MASK)
#define SYSCON_CHIP_ID_USB_OPTION_MASK (0x40000000U)
#define SYSCON_CHIP_ID_USB_OPTION_SHIFT (30U)
#define SYSCON_CHIP_ID_USB_OPTION(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_USB_OPTION_SHIFT)) & SYSCON_CHIP_ID_USB_OPTION_MASK)
#define SYSCON_CHIP_ID_FSP_OPTION_MASK (0x80000000U)
#define SYSCON_CHIP_ID_FSP_OPTION_SHIFT (31U)
#define SYSCON_CHIP_ID_FSP_OPTION(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_CHIP_ID_FSP_OPTION_SHIFT)) & SYSCON_CHIP_ID_FSP_OPTION_MASK)
/*! @name ANA_CTRL0 - crystal and PA register */
#define SYSCON_ANA_CTRL0_PA_POWER_MASK (0xFFU)
#define SYSCON_ANA_CTRL0_PA_POWER_SHIFT (0U)
#define SYSCON_ANA_CTRL0_PA_POWER(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL0_PA_POWER_SHIFT)) & SYSCON_ANA_CTRL0_PA_POWER_MASK)
#define SYSCON_ANA_CTRL0_XTAL_AMP_MASK (0x300000U)
#define SYSCON_ANA_CTRL0_XTAL_AMP_SHIFT (20U)
#define SYSCON_ANA_CTRL0_XTAL_AMP(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL0_XTAL_AMP_SHIFT)) & SYSCON_ANA_CTRL0_XTAL_AMP_MASK)
#define SYSCON_ANA_CTRL0_XTAL_LOAD_CAP_MASK (0xFC00000U)
#define SYSCON_ANA_CTRL0_XTAL_LOAD_CAP_SHIFT (22U)
#define SYSCON_ANA_CTRL0_XTAL_LOAD_CAP(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL0_XTAL_LOAD_CAP_SHIFT)) & SYSCON_ANA_CTRL0_XTAL_LOAD_CAP_MASK)
#define SYSCON_ANA_CTRL0_XTAL_EXTRA_CAP_MASK (0x10000000U)
#define SYSCON_ANA_CTRL0_XTAL_EXTRA_CAP_SHIFT (28U)
#define SYSCON_ANA_CTRL0_XTAL_EXTRA_CAP(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL0_XTAL_EXTRA_CAP_SHIFT)) & SYSCON_ANA_CTRL0_XTAL_EXTRA_CAP_MASK)
#define SYSCON_ANA_CTRL0_XTAL_MODE_MASK (0xC0000000U)
#define SYSCON_ANA_CTRL0_XTAL_MODE_SHIFT (30U)
#define SYSCON_ANA_CTRL0_XTAL_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL0_XTAL_MODE_SHIFT)) & SYSCON_ANA_CTRL0_XTAL_MODE_MASK)
/*! @name XTAL_CTRL - crystal control register */
#define SYSCON_XTAL_CTRL_XTAL_XCUR_BOOST_REG_MASK (0x20U)
#define SYSCON_XTAL_CTRL_XTAL_XCUR_BOOST_REG_SHIFT (5U)
#define SYSCON_XTAL_CTRL_XTAL_XCUR_BOOST_REG(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_XCUR_BOOST_REG_SHIFT)) & \
SYSCON_XTAL_CTRL_XTAL_XCUR_BOOST_REG_MASK)
#define SYSCON_XTAL_CTRL_XTAL_BPXDLY_MASK (0x40U)
#define SYSCON_XTAL_CTRL_XTAL_BPXDLY_SHIFT (6U)
#define SYSCON_XTAL_CTRL_XTAL_BPXDLY(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_BPXDLY_SHIFT)) & SYSCON_XTAL_CTRL_XTAL_BPXDLY_MASK)
#define SYSCON_XTAL_CTRL_XTAL_BP_HYSRES_REG_MASK (0x80U)
#define SYSCON_XTAL_CTRL_XTAL_BP_HYSRES_REG_SHIFT (7U)
#define SYSCON_XTAL_CTRL_XTAL_BP_HYSRES_REG(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_BP_HYSRES_REG_SHIFT)) & \
SYSCON_XTAL_CTRL_XTAL_BP_HYSRES_REG_MASK)
#define SYSCON_XTAL_CTRL_XTAL_XSMT_EN_REG_MASK (0x100U)
#define SYSCON_XTAL_CTRL_XTAL_XSMT_EN_REG_SHIFT (8U)
#define SYSCON_XTAL_CTRL_XTAL_XSMT_EN_REG(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_XSMT_EN_REG_SHIFT)) & SYSCON_XTAL_CTRL_XTAL_XSMT_EN_REG_MASK)
#define SYSCON_XTAL_CTRL_XTAL_XRDY_REG_MASK (0x200U)
#define SYSCON_XTAL_CTRL_XTAL_XRDY_REG_SHIFT (9U)
#define SYSCON_XTAL_CTRL_XTAL_XRDY_REG(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_XRDY_REG_SHIFT)) & SYSCON_XTAL_CTRL_XTAL_XRDY_REG_MASK)
#define SYSCON_XTAL_CTRL_XTAL_XOUT_DIS_REG_MASK (0x400U)
#define SYSCON_XTAL_CTRL_XTAL_XOUT_DIS_REG_SHIFT (10U)
#define SYSCON_XTAL_CTRL_XTAL_XOUT_DIS_REG(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_XOUT_DIS_REG_SHIFT)) & \
SYSCON_XTAL_CTRL_XTAL_XOUT_DIS_REG_MASK)
#define SYSCON_XTAL_CTRL_DIV_DIFF_CLK_DIG_DIS_MASK (0x800U)
#define SYSCON_XTAL_CTRL_DIV_DIFF_CLK_DIG_DIS_SHIFT (11U)
#define SYSCON_XTAL_CTRL_DIV_DIFF_CLK_DIG_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_DIV_DIFF_CLK_DIG_DIS_SHIFT)) & \
SYSCON_XTAL_CTRL_DIV_DIFF_CLK_DIG_DIS_MASK)
#define SYSCON_XTAL_CTRL_XTAL_SU_CB_REG_MASK (0x3F0000U)
#define SYSCON_XTAL_CTRL_XTAL_SU_CB_REG_SHIFT (16U)
#define SYSCON_XTAL_CTRL_XTAL_SU_CB_REG(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_SU_CB_REG_SHIFT)) & SYSCON_XTAL_CTRL_XTAL_SU_CB_REG_MASK)
#define SYSCON_XTAL_CTRL_XTAL_SU_CA_REG_MASK (0x3F000000U)
#define SYSCON_XTAL_CTRL_XTAL_SU_CA_REG_SHIFT (24U)
#define SYSCON_XTAL_CTRL_XTAL_SU_CA_REG(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_SU_CA_REG_SHIFT)) & SYSCON_XTAL_CTRL_XTAL_SU_CA_REG_MASK)
#define SYSCON_XTAL_CTRL_XTAL_INV_MASK (0x40000000U)
#define SYSCON_XTAL_CTRL_XTAL_INV_SHIFT (30U)
#define SYSCON_XTAL_CTRL_XTAL_INV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_INV_SHIFT)) & SYSCON_XTAL_CTRL_XTAL_INV_MASK)
#define SYSCON_XTAL_CTRL_XTAL_DIV_MASK (0x80000000U)
#define SYSCON_XTAL_CTRL_XTAL_DIV_SHIFT (31U)
#define SYSCON_XTAL_CTRL_XTAL_DIV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CTRL_XTAL_DIV_SHIFT)) & SYSCON_XTAL_CTRL_XTAL_DIV_MASK)
/*! @name BUCK - buck control register */
#define SYSCON_BUCK_BUCK_DRIVER_PART_EN_MASK (0x1U)
#define SYSCON_BUCK_BUCK_DRIVER_PART_EN_SHIFT (0U)
#define SYSCON_BUCK_BUCK_DRIVER_PART_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_BUCK_BUCK_DRIVER_PART_EN_SHIFT)) & SYSCON_BUCK_BUCK_DRIVER_PART_EN_MASK)
#define SYSCON_BUCK_BUCK_IND_USE_EN_MASK (0x2U)
#define SYSCON_BUCK_BUCK_IND_USE_EN_SHIFT (1U)
#define SYSCON_BUCK_BUCK_IND_USE_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_BUCK_BUCK_IND_USE_EN_SHIFT)) & SYSCON_BUCK_BUCK_IND_USE_EN_MASK)
#define SYSCON_BUCK_BUCK_ISEL_MASK (0x300U)
#define SYSCON_BUCK_BUCK_ISEL_SHIFT (8U)
#define SYSCON_BUCK_BUCK_ISEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_BUCK_BUCK_ISEL_SHIFT)) & SYSCON_BUCK_BUCK_ISEL_MASK)
#define SYSCON_BUCK_BUCK_VREF_SEL_MASK (0xC00U)
#define SYSCON_BUCK_BUCK_VREF_SEL_SHIFT (10U)
#define SYSCON_BUCK_BUCK_VREF_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_BUCK_BUCK_VREF_SEL_SHIFT)) & SYSCON_BUCK_BUCK_VREF_SEL_MASK)
#define SYSCON_BUCK_BUCK_VBG_SEL_MASK (0x3000U)
#define SYSCON_BUCK_BUCK_VBG_SEL_SHIFT (12U)
#define SYSCON_BUCK_BUCK_VBG_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_BUCK_BUCK_VBG_SEL_SHIFT)) & SYSCON_BUCK_BUCK_VBG_SEL_MASK)
#define SYSCON_BUCK_BUCK_TMOS_MASK (0x1F0000U)
#define SYSCON_BUCK_BUCK_TMOS_SHIFT (16U)
#define SYSCON_BUCK_BUCK_TMOS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_BUCK_BUCK_TMOS_SHIFT)) & SYSCON_BUCK_BUCK_TMOS_MASK)
#define SYSCON_BUCK_BUCK_IC_MASK (0x200000U)
#define SYSCON_BUCK_BUCK_IC_SHIFT (21U)
#define SYSCON_BUCK_BUCK_IC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUCK_BUCK_IC_SHIFT)) & SYSCON_BUCK_BUCK_IC_MASK)
/*! @name FC_FRG - flexcomm 0 and 1 clock divider register */
#define SYSCON_FC_FRG_FRG_DIV0_MASK (0xFFU)
#define SYSCON_FC_FRG_FRG_DIV0_SHIFT (0U)
#define SYSCON_FC_FRG_FRG_DIV0(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_FC_FRG_FRG_DIV0_SHIFT)) & SYSCON_FC_FRG_FRG_DIV0_MASK)
#define SYSCON_FC_FRG_FRG_MULT0_MASK (0xFF00U)
#define SYSCON_FC_FRG_FRG_MULT0_SHIFT (8U)
#define SYSCON_FC_FRG_FRG_MULT0(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_FC_FRG_FRG_MULT0_SHIFT)) & SYSCON_FC_FRG_FRG_MULT0_MASK)
#define SYSCON_FC_FRG_FRG_DIV1_MASK (0xFF0000U)
#define SYSCON_FC_FRG_FRG_DIV1_SHIFT (16U)
#define SYSCON_FC_FRG_FRG_DIV1(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_FC_FRG_FRG_DIV1_SHIFT)) & SYSCON_FC_FRG_FRG_DIV1_MASK)
#define SYSCON_FC_FRG_FRG_MULT1_MASK (0xFF000000U)
#define SYSCON_FC_FRG_FRG_MULT1_SHIFT (24U)
#define SYSCON_FC_FRG_FRG_MULT1(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_FC_FRG_FRG_MULT1_SHIFT)) & SYSCON_FC_FRG_FRG_MULT1_MASK)
/*! @name PIO_PULL_CFG - pad pull control register 0..pad pull control register 2 */
#define SYSCON_PIO_PULL_CFG_PA00_PULL_MASK (0x3U)
#define SYSCON_PIO_PULL_CFG_PA00_PULL_SHIFT (0U)
#define SYSCON_PIO_PULL_CFG_PA00_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA00_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA00_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA16_PULL_MASK (0x3U)
#define SYSCON_PIO_PULL_CFG_PA16_PULL_SHIFT (0U)
#define SYSCON_PIO_PULL_CFG_PA16_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA16_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA16_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PB00_PULL_MASK (0x3U)
#define SYSCON_PIO_PULL_CFG_PB00_PULL_SHIFT (0U)
#define SYSCON_PIO_PULL_CFG_PB00_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PB00_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PB00_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PB01_PULL_MASK (0xCU)
#define SYSCON_PIO_PULL_CFG_PB01_PULL_SHIFT (2U)
#define SYSCON_PIO_PULL_CFG_PB01_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PB01_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PB01_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA01_PULL_MASK (0xCU)
#define SYSCON_PIO_PULL_CFG_PA01_PULL_SHIFT (2U)
#define SYSCON_PIO_PULL_CFG_PA01_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA01_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA01_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA17_PULL_MASK (0xCU)
#define SYSCON_PIO_PULL_CFG_PA17_PULL_SHIFT (2U)
#define SYSCON_PIO_PULL_CFG_PA17_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA17_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA17_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PB02_PULL_MASK (0x30U)
#define SYSCON_PIO_PULL_CFG_PB02_PULL_SHIFT (4U)
#define SYSCON_PIO_PULL_CFG_PB02_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PB02_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PB02_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA18_PULL_MASK (0x30U)
#define SYSCON_PIO_PULL_CFG_PA18_PULL_SHIFT (4U)
#define SYSCON_PIO_PULL_CFG_PA18_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA18_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA18_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA02_PULL_MASK (0x30U)
#define SYSCON_PIO_PULL_CFG_PA02_PULL_SHIFT (4U)
#define SYSCON_PIO_PULL_CFG_PA02_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA02_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA02_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA19_PULL_MASK (0xC0U)
#define SYSCON_PIO_PULL_CFG_PA19_PULL_SHIFT (6U)
#define SYSCON_PIO_PULL_CFG_PA19_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA19_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA19_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA03_PULL_MASK (0xC0U)
#define SYSCON_PIO_PULL_CFG_PA03_PULL_SHIFT (6U)
#define SYSCON_PIO_PULL_CFG_PA03_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA03_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA03_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA04_PULL_MASK (0x300U)
#define SYSCON_PIO_PULL_CFG_PA04_PULL_SHIFT (8U)
#define SYSCON_PIO_PULL_CFG_PA04_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA04_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA04_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA20_PULL_MASK (0x300U)
#define SYSCON_PIO_PULL_CFG_PA20_PULL_SHIFT (8U)
#define SYSCON_PIO_PULL_CFG_PA20_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA20_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA20_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA21_PULL_MASK (0xC00U)
#define SYSCON_PIO_PULL_CFG_PA21_PULL_SHIFT (10U)
#define SYSCON_PIO_PULL_CFG_PA21_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA21_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA21_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA05_PULL_MASK (0xC00U)
#define SYSCON_PIO_PULL_CFG_PA05_PULL_SHIFT (10U)
#define SYSCON_PIO_PULL_CFG_PA05_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA05_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA05_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA22_PULL_MASK (0x3000U)
#define SYSCON_PIO_PULL_CFG_PA22_PULL_SHIFT (12U)
#define SYSCON_PIO_PULL_CFG_PA22_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA22_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA22_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA06_PULL_MASK (0x3000U)
#define SYSCON_PIO_PULL_CFG_PA06_PULL_SHIFT (12U)
#define SYSCON_PIO_PULL_CFG_PA06_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA06_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA06_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA23_PULL_MASK (0xC000U)
#define SYSCON_PIO_PULL_CFG_PA23_PULL_SHIFT (14U)
#define SYSCON_PIO_PULL_CFG_PA23_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA23_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA23_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA07_PULL_MASK (0xC000U)
#define SYSCON_PIO_PULL_CFG_PA07_PULL_SHIFT (14U)
#define SYSCON_PIO_PULL_CFG_PA07_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA07_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA07_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA08_PULL_MASK (0x30000U)
#define SYSCON_PIO_PULL_CFG_PA08_PULL_SHIFT (16U)
#define SYSCON_PIO_PULL_CFG_PA08_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA08_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA08_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA24_PULL_MASK (0x30000U)
#define SYSCON_PIO_PULL_CFG_PA24_PULL_SHIFT (16U)
#define SYSCON_PIO_PULL_CFG_PA24_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA24_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA24_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA09_PULL_MASK (0xC0000U)
#define SYSCON_PIO_PULL_CFG_PA09_PULL_SHIFT (18U)
#define SYSCON_PIO_PULL_CFG_PA09_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA09_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA09_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA25_PULL_MASK (0xC0000U)
#define SYSCON_PIO_PULL_CFG_PA25_PULL_SHIFT (18U)
#define SYSCON_PIO_PULL_CFG_PA25_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA25_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA25_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA26_PULL_MASK (0x300000U)
#define SYSCON_PIO_PULL_CFG_PA26_PULL_SHIFT (20U)
#define SYSCON_PIO_PULL_CFG_PA26_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA26_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA26_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA10_PULL_MASK (0x300000U)
#define SYSCON_PIO_PULL_CFG_PA10_PULL_SHIFT (20U)
#define SYSCON_PIO_PULL_CFG_PA10_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA10_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA10_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA11_PULL_MASK (0xC00000U)
#define SYSCON_PIO_PULL_CFG_PA11_PULL_SHIFT (22U)
#define SYSCON_PIO_PULL_CFG_PA11_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA11_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA11_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA27_PULL_MASK (0xC00000U)
#define SYSCON_PIO_PULL_CFG_PA27_PULL_SHIFT (22U)
#define SYSCON_PIO_PULL_CFG_PA27_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA27_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA27_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA12_PULL_MASK (0x3000000U)
#define SYSCON_PIO_PULL_CFG_PA12_PULL_SHIFT (24U)
#define SYSCON_PIO_PULL_CFG_PA12_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA12_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA12_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA28_PULL_MASK (0x3000000U)
#define SYSCON_PIO_PULL_CFG_PA28_PULL_SHIFT (24U)
#define SYSCON_PIO_PULL_CFG_PA28_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA28_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA28_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA29_PULL_MASK (0xC000000U)
#define SYSCON_PIO_PULL_CFG_PA29_PULL_SHIFT (26U)
#define SYSCON_PIO_PULL_CFG_PA29_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA29_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA29_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA13_PULL_MASK (0xC000000U)
#define SYSCON_PIO_PULL_CFG_PA13_PULL_SHIFT (26U)
#define SYSCON_PIO_PULL_CFG_PA13_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA13_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA13_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA30_PULL_MASK (0x30000000U)
#define SYSCON_PIO_PULL_CFG_PA30_PULL_SHIFT (28U)
#define SYSCON_PIO_PULL_CFG_PA30_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA30_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA30_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA14_PULL_MASK (0x30000000U)
#define SYSCON_PIO_PULL_CFG_PA14_PULL_SHIFT (28U)
#define SYSCON_PIO_PULL_CFG_PA14_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA14_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA14_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA15_PULL_MASK (0xC0000000U)
#define SYSCON_PIO_PULL_CFG_PA15_PULL_SHIFT (30U)
#define SYSCON_PIO_PULL_CFG_PA15_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA15_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA15_PULL_MASK)
#define SYSCON_PIO_PULL_CFG_PA31_PULL_MASK (0xC0000000U)
#define SYSCON_PIO_PULL_CFG_PA31_PULL_SHIFT (30U)
#define SYSCON_PIO_PULL_CFG_PA31_PULL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_PULL_CFG_PA31_PULL_SHIFT)) & SYSCON_PIO_PULL_CFG_PA31_PULL_MASK)
/* The count of SYSCON_PIO_PULL_CFG */
#define SYSCON_PIO_PULL_CFG_COUNT (3U)
/*! @name IO_CAP - io status capture register */
#define SYSCON_IO_CAP_PIN_RETENTION_MASK (0x1U)
#define SYSCON_IO_CAP_PIN_RETENTION_SHIFT (0U)
#define SYSCON_IO_CAP_PIN_RETENTION(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_IO_CAP_PIN_RETENTION_SHIFT)) & SYSCON_IO_CAP_PIN_RETENTION_MASK)
/*! @name PIO_DRV_CFG - pad drive strength register 0..pad drive extra register */
#define SYSCON_PIO_DRV_CFG_PB00_DRV_MASK (0x1U)
#define SYSCON_PIO_DRV_CFG_PB00_DRV_SHIFT (0U)
#define SYSCON_PIO_DRV_CFG_PB00_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PB00_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PB00_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA00_DRV_MASK (0x1U)
#define SYSCON_PIO_DRV_CFG_PA00_DRV_SHIFT (0U)
#define SYSCON_PIO_DRV_CFG_PA00_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA00_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA00_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA01_DRV_MASK (0x2U)
#define SYSCON_PIO_DRV_CFG_PA01_DRV_SHIFT (1U)
#define SYSCON_PIO_DRV_CFG_PA01_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA01_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA01_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PB01_DRV_MASK (0x2U)
#define SYSCON_PIO_DRV_CFG_PB01_DRV_SHIFT (1U)
#define SYSCON_PIO_DRV_CFG_PB01_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PB01_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PB01_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PB02_DRV_MASK (0x4U)
#define SYSCON_PIO_DRV_CFG_PB02_DRV_SHIFT (2U)
#define SYSCON_PIO_DRV_CFG_PB02_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PB02_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PB02_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA02_DRV_MASK (0x4U)
#define SYSCON_PIO_DRV_CFG_PA02_DRV_SHIFT (2U)
#define SYSCON_PIO_DRV_CFG_PA02_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA02_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA02_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA03_DRV_MASK (0x8U)
#define SYSCON_PIO_DRV_CFG_PA03_DRV_SHIFT (3U)
#define SYSCON_PIO_DRV_CFG_PA03_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA03_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA03_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA04_DRV_MASK (0x10U)
#define SYSCON_PIO_DRV_CFG_PA04_DRV_SHIFT (4U)
#define SYSCON_PIO_DRV_CFG_PA04_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA04_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA04_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA05_DRV_MASK (0x20U)
#define SYSCON_PIO_DRV_CFG_PA05_DRV_SHIFT (5U)
#define SYSCON_PIO_DRV_CFG_PA05_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA05_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA05_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA06_DRV_MASK (0x40U)
#define SYSCON_PIO_DRV_CFG_PA06_DRV_SHIFT (6U)
#define SYSCON_PIO_DRV_CFG_PA06_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA06_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA06_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA06_DRV_EXTRA_MASK (0x40U)
#define SYSCON_PIO_DRV_CFG_PA06_DRV_EXTRA_SHIFT (6U)
#define SYSCON_PIO_DRV_CFG_PA06_DRV_EXTRA(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA06_DRV_EXTRA_SHIFT)) & SYSCON_PIO_DRV_CFG_PA06_DRV_EXTRA_MASK)
#define SYSCON_PIO_DRV_CFG_PA07_DRV_MASK (0x80U)
#define SYSCON_PIO_DRV_CFG_PA07_DRV_SHIFT (7U)
#define SYSCON_PIO_DRV_CFG_PA07_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA07_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA07_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA08_DRV_MASK (0x100U)
#define SYSCON_PIO_DRV_CFG_PA08_DRV_SHIFT (8U)
#define SYSCON_PIO_DRV_CFG_PA08_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA08_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA08_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA09_DRV_MASK (0x200U)
#define SYSCON_PIO_DRV_CFG_PA09_DRV_SHIFT (9U)
#define SYSCON_PIO_DRV_CFG_PA09_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA09_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA09_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA10_DRV_MASK (0x400U)
#define SYSCON_PIO_DRV_CFG_PA10_DRV_SHIFT (10U)
#define SYSCON_PIO_DRV_CFG_PA10_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA10_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA10_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA11_DRV_EXTRA_MASK (0x800U)
#define SYSCON_PIO_DRV_CFG_PA11_DRV_EXTRA_SHIFT (11U)
#define SYSCON_PIO_DRV_CFG_PA11_DRV_EXTRA(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA11_DRV_EXTRA_SHIFT)) & SYSCON_PIO_DRV_CFG_PA11_DRV_EXTRA_MASK)
#define SYSCON_PIO_DRV_CFG_PA11_DRV_MASK (0x800U)
#define SYSCON_PIO_DRV_CFG_PA11_DRV_SHIFT (11U)
#define SYSCON_PIO_DRV_CFG_PA11_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA11_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA11_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA12_DRV_MASK (0x1000U)
#define SYSCON_PIO_DRV_CFG_PA12_DRV_SHIFT (12U)
#define SYSCON_PIO_DRV_CFG_PA12_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA12_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA12_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA13_DRV_MASK (0x2000U)
#define SYSCON_PIO_DRV_CFG_PA13_DRV_SHIFT (13U)
#define SYSCON_PIO_DRV_CFG_PA13_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA13_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA13_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA14_DRV_MASK (0x4000U)
#define SYSCON_PIO_DRV_CFG_PA14_DRV_SHIFT (14U)
#define SYSCON_PIO_DRV_CFG_PA14_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA14_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA14_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA15_DRV_MASK (0x8000U)
#define SYSCON_PIO_DRV_CFG_PA15_DRV_SHIFT (15U)
#define SYSCON_PIO_DRV_CFG_PA15_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA15_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA15_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA16_DRV_MASK (0x10000U)
#define SYSCON_PIO_DRV_CFG_PA16_DRV_SHIFT (16U)
#define SYSCON_PIO_DRV_CFG_PA16_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA16_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA16_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA17_DRV_MASK (0x20000U)
#define SYSCON_PIO_DRV_CFG_PA17_DRV_SHIFT (17U)
#define SYSCON_PIO_DRV_CFG_PA17_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA17_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA17_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA18_DRV_MASK (0x40000U)
#define SYSCON_PIO_DRV_CFG_PA18_DRV_SHIFT (18U)
#define SYSCON_PIO_DRV_CFG_PA18_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA18_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA18_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA19_DRV_EXTRA_MASK (0x80000U)
#define SYSCON_PIO_DRV_CFG_PA19_DRV_EXTRA_SHIFT (19U)
#define SYSCON_PIO_DRV_CFG_PA19_DRV_EXTRA(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA19_DRV_EXTRA_SHIFT)) & SYSCON_PIO_DRV_CFG_PA19_DRV_EXTRA_MASK)
#define SYSCON_PIO_DRV_CFG_PA19_DRV_MASK (0x80000U)
#define SYSCON_PIO_DRV_CFG_PA19_DRV_SHIFT (19U)
#define SYSCON_PIO_DRV_CFG_PA19_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA19_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA19_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA20_DRV_MASK (0x100000U)
#define SYSCON_PIO_DRV_CFG_PA20_DRV_SHIFT (20U)
#define SYSCON_PIO_DRV_CFG_PA20_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA20_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA20_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA21_DRV_MASK (0x200000U)
#define SYSCON_PIO_DRV_CFG_PA21_DRV_SHIFT (21U)
#define SYSCON_PIO_DRV_CFG_PA21_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA21_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA21_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA22_DRV_MASK (0x400000U)
#define SYSCON_PIO_DRV_CFG_PA22_DRV_SHIFT (22U)
#define SYSCON_PIO_DRV_CFG_PA22_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA22_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA22_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA23_DRV_MASK (0x800000U)
#define SYSCON_PIO_DRV_CFG_PA23_DRV_SHIFT (23U)
#define SYSCON_PIO_DRV_CFG_PA23_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA23_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA23_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA24_DRV_MASK (0x1000000U)
#define SYSCON_PIO_DRV_CFG_PA24_DRV_SHIFT (24U)
#define SYSCON_PIO_DRV_CFG_PA24_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA24_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA24_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA25_DRV_MASK (0x2000000U)
#define SYSCON_PIO_DRV_CFG_PA25_DRV_SHIFT (25U)
#define SYSCON_PIO_DRV_CFG_PA25_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA25_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA25_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA26_DRV_MASK (0x4000000U)
#define SYSCON_PIO_DRV_CFG_PA26_DRV_SHIFT (26U)
#define SYSCON_PIO_DRV_CFG_PA26_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA26_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA26_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA26_DRV_EXTRA_MASK (0x4000000U)
#define SYSCON_PIO_DRV_CFG_PA26_DRV_EXTRA_SHIFT (26U)
#define SYSCON_PIO_DRV_CFG_PA26_DRV_EXTRA(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA26_DRV_EXTRA_SHIFT)) & SYSCON_PIO_DRV_CFG_PA26_DRV_EXTRA_MASK)
#define SYSCON_PIO_DRV_CFG_PA27_DRV_EXTRA_MASK (0x8000000U)
#define SYSCON_PIO_DRV_CFG_PA27_DRV_EXTRA_SHIFT (27U)
#define SYSCON_PIO_DRV_CFG_PA27_DRV_EXTRA(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA27_DRV_EXTRA_SHIFT)) & SYSCON_PIO_DRV_CFG_PA27_DRV_EXTRA_MASK)
#define SYSCON_PIO_DRV_CFG_PA27_DRV_MASK (0x8000000U)
#define SYSCON_PIO_DRV_CFG_PA27_DRV_SHIFT (27U)
#define SYSCON_PIO_DRV_CFG_PA27_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA27_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA27_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA28_DRV_MASK (0x10000000U)
#define SYSCON_PIO_DRV_CFG_PA28_DRV_SHIFT (28U)
#define SYSCON_PIO_DRV_CFG_PA28_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA28_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA28_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA29_DRV_MASK (0x20000000U)
#define SYSCON_PIO_DRV_CFG_PA29_DRV_SHIFT (29U)
#define SYSCON_PIO_DRV_CFG_PA29_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA29_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA29_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA30_DRV_MASK (0x40000000U)
#define SYSCON_PIO_DRV_CFG_PA30_DRV_SHIFT (30U)
#define SYSCON_PIO_DRV_CFG_PA30_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA30_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA30_DRV_MASK)
#define SYSCON_PIO_DRV_CFG_PA31_DRV_MASK (0x80000000U)
#define SYSCON_PIO_DRV_CFG_PA31_DRV_SHIFT (31U)
#define SYSCON_PIO_DRV_CFG_PA31_DRV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_DRV_CFG_PA31_DRV_SHIFT)) & SYSCON_PIO_DRV_CFG_PA31_DRV_MASK)
/* The count of SYSCON_PIO_DRV_CFG */
#define SYSCON_PIO_DRV_CFG_COUNT (3U)
/*! @name PIO_CFG_MISC - pin misc control register */
#define SYSCON_PIO_CFG_MISC_PB00_AE_MASK (0x1U)
#define SYSCON_PIO_CFG_MISC_PB00_AE_SHIFT (0U)
#define SYSCON_PIO_CFG_MISC_PB00_AE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CFG_MISC_PB00_AE_SHIFT)) & SYSCON_PIO_CFG_MISC_PB00_AE_MASK)
#define SYSCON_PIO_CFG_MISC_PB01_AE_MASK (0x2U)
#define SYSCON_PIO_CFG_MISC_PB01_AE_SHIFT (1U)
#define SYSCON_PIO_CFG_MISC_PB01_AE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CFG_MISC_PB01_AE_SHIFT)) & SYSCON_PIO_CFG_MISC_PB01_AE_MASK)
#define SYSCON_PIO_CFG_MISC_PSYNC_MASK (0x8000U)
#define SYSCON_PIO_CFG_MISC_PSYNC_SHIFT (15U)
#define SYSCON_PIO_CFG_MISC_PSYNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CFG_MISC_PSYNC_SHIFT)) & SYSCON_PIO_CFG_MISC_PSYNC_MASK)
#define SYSCON_PIO_CFG_MISC_PB02_MODE_MASK (0x10000U)
#define SYSCON_PIO_CFG_MISC_PB02_MODE_SHIFT (16U)
#define SYSCON_PIO_CFG_MISC_PB02_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CFG_MISC_PB02_MODE_SHIFT)) & SYSCON_PIO_CFG_MISC_PB02_MODE_MASK)
#define SYSCON_PIO_CFG_MISC_TRX_EN_INV_MASK (0x40000U)
#define SYSCON_PIO_CFG_MISC_TRX_EN_INV_SHIFT (18U)
#define SYSCON_PIO_CFG_MISC_TRX_EN_INV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CFG_MISC_TRX_EN_INV_SHIFT)) & SYSCON_PIO_CFG_MISC_TRX_EN_INV_MASK)
#define SYSCON_PIO_CFG_MISC_RFE_INV_MASK (0x80000U)
#define SYSCON_PIO_CFG_MISC_RFE_INV_SHIFT (19U)
#define SYSCON_PIO_CFG_MISC_RFE_INV(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CFG_MISC_RFE_INV_SHIFT)) & SYSCON_PIO_CFG_MISC_RFE_INV_MASK)
/*! @name PIO_WAKEUP_LVL0 - pin wakeup polarity register 0 */
#define SYSCON_PIO_WAKEUP_LVL0_PA00_WAKEUP_LVL_MASK (0x1U)
#define SYSCON_PIO_WAKEUP_LVL0_PA00_WAKEUP_LVL_SHIFT (0U)
#define SYSCON_PIO_WAKEUP_LVL0_PA00_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA00_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA00_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA01_WAKEUP_LVL_MASK (0x2U)
#define SYSCON_PIO_WAKEUP_LVL0_PA01_WAKEUP_LVL_SHIFT (1U)
#define SYSCON_PIO_WAKEUP_LVL0_PA01_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA01_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA01_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA02_WAKEUP_LVL_MASK (0x4U)
#define SYSCON_PIO_WAKEUP_LVL0_PA02_WAKEUP_LVL_SHIFT (2U)
#define SYSCON_PIO_WAKEUP_LVL0_PA02_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA02_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA02_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA03_WAKEUP_LVL_MASK (0x8U)
#define SYSCON_PIO_WAKEUP_LVL0_PA03_WAKEUP_LVL_SHIFT (3U)
#define SYSCON_PIO_WAKEUP_LVL0_PA03_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA03_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA03_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA04_WAKEUP_LVL_MASK (0x10U)
#define SYSCON_PIO_WAKEUP_LVL0_PA04_WAKEUP_LVL_SHIFT (4U)
#define SYSCON_PIO_WAKEUP_LVL0_PA04_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA04_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA04_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA05_WAKEUP_LVL_MASK (0x20U)
#define SYSCON_PIO_WAKEUP_LVL0_PA05_WAKEUP_LVL_SHIFT (5U)
#define SYSCON_PIO_WAKEUP_LVL0_PA05_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA05_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA05_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA06_WAKEUP_LVL_MASK (0x40U)
#define SYSCON_PIO_WAKEUP_LVL0_PA06_WAKEUP_LVL_SHIFT (6U)
#define SYSCON_PIO_WAKEUP_LVL0_PA06_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA06_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA06_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA07_WAKEUP_LVL_MASK (0x80U)
#define SYSCON_PIO_WAKEUP_LVL0_PA07_WAKEUP_LVL_SHIFT (7U)
#define SYSCON_PIO_WAKEUP_LVL0_PA07_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA07_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA07_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA08_WAKEUP_LVL_MASK (0x100U)
#define SYSCON_PIO_WAKEUP_LVL0_PA08_WAKEUP_LVL_SHIFT (8U)
#define SYSCON_PIO_WAKEUP_LVL0_PA08_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA08_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA08_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA09_WAKEUP_LVL_MASK (0x200U)
#define SYSCON_PIO_WAKEUP_LVL0_PA09_WAKEUP_LVL_SHIFT (9U)
#define SYSCON_PIO_WAKEUP_LVL0_PA09_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA09_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA09_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA10_WAKEUP_LVL_MASK (0x400U)
#define SYSCON_PIO_WAKEUP_LVL0_PA10_WAKEUP_LVL_SHIFT (10U)
#define SYSCON_PIO_WAKEUP_LVL0_PA10_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA10_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA10_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA11_WAKEUP_LVL_MASK (0x800U)
#define SYSCON_PIO_WAKEUP_LVL0_PA11_WAKEUP_LVL_SHIFT (11U)
#define SYSCON_PIO_WAKEUP_LVL0_PA11_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA11_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA11_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA12_WAKEUP_LVL_MASK (0x1000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA12_WAKEUP_LVL_SHIFT (12U)
#define SYSCON_PIO_WAKEUP_LVL0_PA12_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA12_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA12_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA13_WAKEUP_LVL_MASK (0x2000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA13_WAKEUP_LVL_SHIFT (13U)
#define SYSCON_PIO_WAKEUP_LVL0_PA13_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA13_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA13_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA14_WAKEUP_LVL_MASK (0x4000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA14_WAKEUP_LVL_SHIFT (14U)
#define SYSCON_PIO_WAKEUP_LVL0_PA14_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA14_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA14_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA15_WAKEUP_LVL_MASK (0x8000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA15_WAKEUP_LVL_SHIFT (15U)
#define SYSCON_PIO_WAKEUP_LVL0_PA15_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA15_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA15_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA16_WAKEUP_LVL_MASK (0x10000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA16_WAKEUP_LVL_SHIFT (16U)
#define SYSCON_PIO_WAKEUP_LVL0_PA16_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA16_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA16_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA17_WAKEUP_LVL_MASK (0x20000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA17_WAKEUP_LVL_SHIFT (17U)
#define SYSCON_PIO_WAKEUP_LVL0_PA17_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA17_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA17_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA18_WAKEUP_LVL_MASK (0x40000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA18_WAKEUP_LVL_SHIFT (18U)
#define SYSCON_PIO_WAKEUP_LVL0_PA18_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA18_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA18_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA19_WAKEUP_LVL_MASK (0x80000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA19_WAKEUP_LVL_SHIFT (19U)
#define SYSCON_PIO_WAKEUP_LVL0_PA19_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA19_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA19_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA20_WAKEUP_LVL_MASK (0x100000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA20_WAKEUP_LVL_SHIFT (20U)
#define SYSCON_PIO_WAKEUP_LVL0_PA20_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA20_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA20_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA21_WAKEUP_LVL_MASK (0x200000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA21_WAKEUP_LVL_SHIFT (21U)
#define SYSCON_PIO_WAKEUP_LVL0_PA21_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA21_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA21_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA22_WAKEUP_LVL_MASK (0x400000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA22_WAKEUP_LVL_SHIFT (22U)
#define SYSCON_PIO_WAKEUP_LVL0_PA22_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA22_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA22_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA23_WAKEUP_LVL_MASK (0x800000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA23_WAKEUP_LVL_SHIFT (23U)
#define SYSCON_PIO_WAKEUP_LVL0_PA23_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA23_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA23_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA24_WAKEUP_LVL_MASK (0x1000000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA24_WAKEUP_LVL_SHIFT (24U)
#define SYSCON_PIO_WAKEUP_LVL0_PA24_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA24_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA24_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA25_WAKEUP_LVL_MASK (0x2000000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA25_WAKEUP_LVL_SHIFT (25U)
#define SYSCON_PIO_WAKEUP_LVL0_PA25_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA25_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA25_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA26_WAKEUP_LVL_MASK (0x4000000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA26_WAKEUP_LVL_SHIFT (26U)
#define SYSCON_PIO_WAKEUP_LVL0_PA26_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA26_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA26_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA27_WAKEUP_LVL_MASK (0x8000000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA27_WAKEUP_LVL_SHIFT (27U)
#define SYSCON_PIO_WAKEUP_LVL0_PA27_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA27_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA27_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA28_WAKEUP_LVL_MASK (0x10000000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA28_WAKEUP_LVL_SHIFT (28U)
#define SYSCON_PIO_WAKEUP_LVL0_PA28_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA28_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA28_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA29_WAKEUP_LVL_MASK (0x20000000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA29_WAKEUP_LVL_SHIFT (29U)
#define SYSCON_PIO_WAKEUP_LVL0_PA29_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA29_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA29_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA30_WAKEUP_LVL_MASK (0x40000000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA30_WAKEUP_LVL_SHIFT (30U)
#define SYSCON_PIO_WAKEUP_LVL0_PA30_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA30_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA30_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL0_PA31_WAKEUP_LVL_MASK (0x80000000U)
#define SYSCON_PIO_WAKEUP_LVL0_PA31_WAKEUP_LVL_SHIFT (31U)
#define SYSCON_PIO_WAKEUP_LVL0_PA31_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL0_PA31_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL0_PA31_WAKEUP_LVL_MASK)
/*! @name PIO_WAKEUP_LVL1 - pin wakeup polarity register 1 */
#define SYSCON_PIO_WAKEUP_LVL1_PB00_WAKEUP_LVL_MASK (0x1U)
#define SYSCON_PIO_WAKEUP_LVL1_PB00_WAKEUP_LVL_SHIFT (0U)
#define SYSCON_PIO_WAKEUP_LVL1_PB00_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL1_PB00_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL1_PB00_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL1_PB01_WAKEUP_LVL_MASK (0x2U)
#define SYSCON_PIO_WAKEUP_LVL1_PB01_WAKEUP_LVL_SHIFT (1U)
#define SYSCON_PIO_WAKEUP_LVL1_PB01_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL1_PB01_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL1_PB01_WAKEUP_LVL_MASK)
#define SYSCON_PIO_WAKEUP_LVL1_PB02_WAKEUP_LVL_MASK (0x4U)
#define SYSCON_PIO_WAKEUP_LVL1_PB02_WAKEUP_LVL_SHIFT (2U)
#define SYSCON_PIO_WAKEUP_LVL1_PB02_WAKEUP_LVL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_LVL1_PB02_WAKEUP_LVL_SHIFT)) & \
SYSCON_PIO_WAKEUP_LVL1_PB02_WAKEUP_LVL_MASK)
/*! @name PIO_IE_CFG0 - pad input enable register 0 */
#define SYSCON_PIO_IE_CFG0_PA00_IE_MASK (0x1U)
#define SYSCON_PIO_IE_CFG0_PA00_IE_SHIFT (0U)
#define SYSCON_PIO_IE_CFG0_PA00_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA00_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA00_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA01_IE_MASK (0x2U)
#define SYSCON_PIO_IE_CFG0_PA01_IE_SHIFT (1U)
#define SYSCON_PIO_IE_CFG0_PA01_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA01_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA01_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA02_IE_MASK (0x4U)
#define SYSCON_PIO_IE_CFG0_PA02_IE_SHIFT (2U)
#define SYSCON_PIO_IE_CFG0_PA02_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA02_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA02_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA03_IE_MASK (0x8U)
#define SYSCON_PIO_IE_CFG0_PA03_IE_SHIFT (3U)
#define SYSCON_PIO_IE_CFG0_PA03_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA03_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA03_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA04_IE_MASK (0x10U)
#define SYSCON_PIO_IE_CFG0_PA04_IE_SHIFT (4U)
#define SYSCON_PIO_IE_CFG0_PA04_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA04_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA04_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA05_IE_MASK (0x20U)
#define SYSCON_PIO_IE_CFG0_PA05_IE_SHIFT (5U)
#define SYSCON_PIO_IE_CFG0_PA05_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA05_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA05_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA06_IE_MASK (0x40U)
#define SYSCON_PIO_IE_CFG0_PA06_IE_SHIFT (6U)
#define SYSCON_PIO_IE_CFG0_PA06_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA06_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA06_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA07_IE_MASK (0x80U)
#define SYSCON_PIO_IE_CFG0_PA07_IE_SHIFT (7U)
#define SYSCON_PIO_IE_CFG0_PA07_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA07_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA07_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA08_IE_MASK (0x100U)
#define SYSCON_PIO_IE_CFG0_PA08_IE_SHIFT (8U)
#define SYSCON_PIO_IE_CFG0_PA08_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA08_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA08_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA09_IE_MASK (0x200U)
#define SYSCON_PIO_IE_CFG0_PA09_IE_SHIFT (9U)
#define SYSCON_PIO_IE_CFG0_PA09_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA09_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA09_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA10_IE_MASK (0x400U)
#define SYSCON_PIO_IE_CFG0_PA10_IE_SHIFT (10U)
#define SYSCON_PIO_IE_CFG0_PA10_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA10_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA10_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA11_IE_MASK (0x800U)
#define SYSCON_PIO_IE_CFG0_PA11_IE_SHIFT (11U)
#define SYSCON_PIO_IE_CFG0_PA11_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA11_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA11_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA12_IE_MASK (0x1000U)
#define SYSCON_PIO_IE_CFG0_PA12_IE_SHIFT (12U)
#define SYSCON_PIO_IE_CFG0_PA12_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA12_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA12_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA13_IE_MASK (0x2000U)
#define SYSCON_PIO_IE_CFG0_PA13_IE_SHIFT (13U)
#define SYSCON_PIO_IE_CFG0_PA13_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA13_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA13_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA14_IE_MASK (0x4000U)
#define SYSCON_PIO_IE_CFG0_PA14_IE_SHIFT (14U)
#define SYSCON_PIO_IE_CFG0_PA14_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA14_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA14_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA15_IE_MASK (0x8000U)
#define SYSCON_PIO_IE_CFG0_PA15_IE_SHIFT (15U)
#define SYSCON_PIO_IE_CFG0_PA15_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA15_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA15_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA16_IE_MASK (0x10000U)
#define SYSCON_PIO_IE_CFG0_PA16_IE_SHIFT (16U)
#define SYSCON_PIO_IE_CFG0_PA16_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA16_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA16_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA17_IE_MASK (0x20000U)
#define SYSCON_PIO_IE_CFG0_PA17_IE_SHIFT (17U)
#define SYSCON_PIO_IE_CFG0_PA17_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA17_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA17_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA18_IE_MASK (0x40000U)
#define SYSCON_PIO_IE_CFG0_PA18_IE_SHIFT (18U)
#define SYSCON_PIO_IE_CFG0_PA18_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA18_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA18_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA19_IE_MASK (0x80000U)
#define SYSCON_PIO_IE_CFG0_PA19_IE_SHIFT (19U)
#define SYSCON_PIO_IE_CFG0_PA19_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA19_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA19_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA20_IE_MASK (0x100000U)
#define SYSCON_PIO_IE_CFG0_PA20_IE_SHIFT (20U)
#define SYSCON_PIO_IE_CFG0_PA20_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA20_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA20_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA21_IE_MASK (0x200000U)
#define SYSCON_PIO_IE_CFG0_PA21_IE_SHIFT (21U)
#define SYSCON_PIO_IE_CFG0_PA21_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA21_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA21_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA22_IE_MASK (0x400000U)
#define SYSCON_PIO_IE_CFG0_PA22_IE_SHIFT (22U)
#define SYSCON_PIO_IE_CFG0_PA22_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA22_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA22_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA23_IE_MASK (0x800000U)
#define SYSCON_PIO_IE_CFG0_PA23_IE_SHIFT (23U)
#define SYSCON_PIO_IE_CFG0_PA23_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA23_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA23_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA24_IE_MASK (0x1000000U)
#define SYSCON_PIO_IE_CFG0_PA24_IE_SHIFT (24U)
#define SYSCON_PIO_IE_CFG0_PA24_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA24_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA24_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA25_IE_MASK (0x2000000U)
#define SYSCON_PIO_IE_CFG0_PA25_IE_SHIFT (25U)
#define SYSCON_PIO_IE_CFG0_PA25_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA25_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA25_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA26_IE_MASK (0x4000000U)
#define SYSCON_PIO_IE_CFG0_PA26_IE_SHIFT (26U)
#define SYSCON_PIO_IE_CFG0_PA26_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA26_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA26_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA27_IE_MASK (0x8000000U)
#define SYSCON_PIO_IE_CFG0_PA27_IE_SHIFT (27U)
#define SYSCON_PIO_IE_CFG0_PA27_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA27_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA27_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA28_IE_MASK (0x10000000U)
#define SYSCON_PIO_IE_CFG0_PA28_IE_SHIFT (28U)
#define SYSCON_PIO_IE_CFG0_PA28_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA28_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA28_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA29_IE_MASK (0x20000000U)
#define SYSCON_PIO_IE_CFG0_PA29_IE_SHIFT (29U)
#define SYSCON_PIO_IE_CFG0_PA29_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA29_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA29_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA30_IE_MASK (0x40000000U)
#define SYSCON_PIO_IE_CFG0_PA30_IE_SHIFT (30U)
#define SYSCON_PIO_IE_CFG0_PA30_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA30_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA30_IE_MASK)
#define SYSCON_PIO_IE_CFG0_PA31_IE_MASK (0x80000000U)
#define SYSCON_PIO_IE_CFG0_PA31_IE_SHIFT (31U)
#define SYSCON_PIO_IE_CFG0_PA31_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG0_PA31_IE_SHIFT)) & SYSCON_PIO_IE_CFG0_PA31_IE_MASK)
/*! @name PIO_IE_CFG1 - pad input enable register 1 */
#define SYSCON_PIO_IE_CFG1_PB00_IE_MASK (0x1U)
#define SYSCON_PIO_IE_CFG1_PB00_IE_SHIFT (0U)
#define SYSCON_PIO_IE_CFG1_PB00_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG1_PB00_IE_SHIFT)) & SYSCON_PIO_IE_CFG1_PB00_IE_MASK)
#define SYSCON_PIO_IE_CFG1_PB01_IE_MASK (0x2U)
#define SYSCON_PIO_IE_CFG1_PB01_IE_SHIFT (1U)
#define SYSCON_PIO_IE_CFG1_PB01_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG1_PB01_IE_SHIFT)) & SYSCON_PIO_IE_CFG1_PB01_IE_MASK)
#define SYSCON_PIO_IE_CFG1_BOOT_MODE_IE_MASK (0x4U)
#define SYSCON_PIO_IE_CFG1_BOOT_MODE_IE_SHIFT (2U)
#define SYSCON_PIO_IE_CFG1_BOOT_MODE_IE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_IE_CFG1_BOOT_MODE_IE_SHIFT)) & SYSCON_PIO_IE_CFG1_BOOT_MODE_IE_MASK)
/*! @name PIO_FUNC_CFG - pin mux control register 0..pin mux control register 3 */
#define SYSCON_PIO_FUNC_CFG_PA00_FUNC_MASK (0x7U)
#define SYSCON_PIO_FUNC_CFG_PA00_FUNC_SHIFT (0U)
#define SYSCON_PIO_FUNC_CFG_PA00_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA00_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA00_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA24_FUNC_MASK (0x7U)
#define SYSCON_PIO_FUNC_CFG_PA24_FUNC_SHIFT (0U)
#define SYSCON_PIO_FUNC_CFG_PA24_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA24_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA24_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA16_FUNC_MASK (0x7U)
#define SYSCON_PIO_FUNC_CFG_PA16_FUNC_SHIFT (0U)
#define SYSCON_PIO_FUNC_CFG_PA16_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA16_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA16_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA08_FUNC_MASK (0x7U)
#define SYSCON_PIO_FUNC_CFG_PA08_FUNC_SHIFT (0U)
#define SYSCON_PIO_FUNC_CFG_PA08_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA08_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA08_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA25_FUNC_MASK (0x70U)
#define SYSCON_PIO_FUNC_CFG_PA25_FUNC_SHIFT (4U)
#define SYSCON_PIO_FUNC_CFG_PA25_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA25_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA25_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA17_FUNC_MASK (0x70U)
#define SYSCON_PIO_FUNC_CFG_PA17_FUNC_SHIFT (4U)
#define SYSCON_PIO_FUNC_CFG_PA17_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA17_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA17_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA09_FUNC_MASK (0x70U)
#define SYSCON_PIO_FUNC_CFG_PA09_FUNC_SHIFT (4U)
#define SYSCON_PIO_FUNC_CFG_PA09_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA09_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA09_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA01_FUNC_MASK (0x70U)
#define SYSCON_PIO_FUNC_CFG_PA01_FUNC_SHIFT (4U)
#define SYSCON_PIO_FUNC_CFG_PA01_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA01_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA01_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA10_FUNC_MASK (0x700U)
#define SYSCON_PIO_FUNC_CFG_PA10_FUNC_SHIFT (8U)
#define SYSCON_PIO_FUNC_CFG_PA10_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA10_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA10_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA02_FUNC_MASK (0x700U)
#define SYSCON_PIO_FUNC_CFG_PA02_FUNC_SHIFT (8U)
#define SYSCON_PIO_FUNC_CFG_PA02_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA02_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA02_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA18_FUNC_MASK (0x700U)
#define SYSCON_PIO_FUNC_CFG_PA18_FUNC_SHIFT (8U)
#define SYSCON_PIO_FUNC_CFG_PA18_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA18_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA18_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA26_FUNC_MASK (0x700U)
#define SYSCON_PIO_FUNC_CFG_PA26_FUNC_SHIFT (8U)
#define SYSCON_PIO_FUNC_CFG_PA26_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA26_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA26_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA27_FUNC_MASK (0x7000U)
#define SYSCON_PIO_FUNC_CFG_PA27_FUNC_SHIFT (12U)
#define SYSCON_PIO_FUNC_CFG_PA27_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA27_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA27_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA11_FUNC_MASK (0x7000U)
#define SYSCON_PIO_FUNC_CFG_PA11_FUNC_SHIFT (12U)
#define SYSCON_PIO_FUNC_CFG_PA11_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA11_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA11_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA03_FUNC_MASK (0x7000U)
#define SYSCON_PIO_FUNC_CFG_PA03_FUNC_SHIFT (12U)
#define SYSCON_PIO_FUNC_CFG_PA03_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA03_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA03_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA19_FUNC_MASK (0x7000U)
#define SYSCON_PIO_FUNC_CFG_PA19_FUNC_SHIFT (12U)
#define SYSCON_PIO_FUNC_CFG_PA19_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA19_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA19_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA20_FUNC_MASK (0x70000U)
#define SYSCON_PIO_FUNC_CFG_PA20_FUNC_SHIFT (16U)
#define SYSCON_PIO_FUNC_CFG_PA20_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA20_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA20_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA12_FUNC_MASK (0x70000U)
#define SYSCON_PIO_FUNC_CFG_PA12_FUNC_SHIFT (16U)
#define SYSCON_PIO_FUNC_CFG_PA12_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA12_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA12_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA28_FUNC_MASK (0x70000U)
#define SYSCON_PIO_FUNC_CFG_PA28_FUNC_SHIFT (16U)
#define SYSCON_PIO_FUNC_CFG_PA28_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA28_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA28_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA04_FUNC_MASK (0x70000U)
#define SYSCON_PIO_FUNC_CFG_PA04_FUNC_SHIFT (16U)
#define SYSCON_PIO_FUNC_CFG_PA04_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA04_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA04_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA05_FUNC_MASK (0x700000U)
#define SYSCON_PIO_FUNC_CFG_PA05_FUNC_SHIFT (20U)
#define SYSCON_PIO_FUNC_CFG_PA05_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA05_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA05_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA29_FUNC_MASK (0x700000U)
#define SYSCON_PIO_FUNC_CFG_PA29_FUNC_SHIFT (20U)
#define SYSCON_PIO_FUNC_CFG_PA29_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA29_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA29_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA13_FUNC_MASK (0x700000U)
#define SYSCON_PIO_FUNC_CFG_PA13_FUNC_SHIFT (20U)
#define SYSCON_PIO_FUNC_CFG_PA13_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA13_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA13_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA21_FUNC_MASK (0x700000U)
#define SYSCON_PIO_FUNC_CFG_PA21_FUNC_SHIFT (20U)
#define SYSCON_PIO_FUNC_CFG_PA21_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA21_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA21_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA06_FUNC_MASK (0x7000000U)
#define SYSCON_PIO_FUNC_CFG_PA06_FUNC_SHIFT (24U)
#define SYSCON_PIO_FUNC_CFG_PA06_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA06_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA06_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA22_FUNC_MASK (0x7000000U)
#define SYSCON_PIO_FUNC_CFG_PA22_FUNC_SHIFT (24U)
#define SYSCON_PIO_FUNC_CFG_PA22_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA22_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA22_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA30_FUNC_MASK (0x7000000U)
#define SYSCON_PIO_FUNC_CFG_PA30_FUNC_SHIFT (24U)
#define SYSCON_PIO_FUNC_CFG_PA30_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA30_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA30_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA14_FUNC_MASK (0x7000000U)
#define SYSCON_PIO_FUNC_CFG_PA14_FUNC_SHIFT (24U)
#define SYSCON_PIO_FUNC_CFG_PA14_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA14_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA14_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA31_FUNC_MASK (0x70000000U)
#define SYSCON_PIO_FUNC_CFG_PA31_FUNC_SHIFT (28U)
#define SYSCON_PIO_FUNC_CFG_PA31_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA31_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA31_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA07_FUNC_MASK (0x70000000U)
#define SYSCON_PIO_FUNC_CFG_PA07_FUNC_SHIFT (28U)
#define SYSCON_PIO_FUNC_CFG_PA07_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA07_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA07_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA23_FUNC_MASK (0x70000000U)
#define SYSCON_PIO_FUNC_CFG_PA23_FUNC_SHIFT (28U)
#define SYSCON_PIO_FUNC_CFG_PA23_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA23_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA23_FUNC_MASK)
#define SYSCON_PIO_FUNC_CFG_PA15_FUNC_MASK (0x70000000U)
#define SYSCON_PIO_FUNC_CFG_PA15_FUNC_SHIFT (28U)
#define SYSCON_PIO_FUNC_CFG_PA15_FUNC(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_FUNC_CFG_PA15_FUNC_SHIFT)) & SYSCON_PIO_FUNC_CFG_PA15_FUNC_MASK)
/* The count of SYSCON_PIO_FUNC_CFG */
#define SYSCON_PIO_FUNC_CFG_COUNT (4U)
/*! @name PIO_WAKEUP_EN0 - pin function selection in power down mode register 0 */
#define SYSCON_PIO_WAKEUP_EN0_PA00_WAKEUP_EN_MASK (0x1U)
#define SYSCON_PIO_WAKEUP_EN0_PA00_WAKEUP_EN_SHIFT (0U)
#define SYSCON_PIO_WAKEUP_EN0_PA00_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA00_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA00_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA01_WAKEUP_EN_MASK (0x2U)
#define SYSCON_PIO_WAKEUP_EN0_PA01_WAKEUP_EN_SHIFT (1U)
#define SYSCON_PIO_WAKEUP_EN0_PA01_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA01_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA01_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA02_WAKEUP_EN_MASK (0x4U)
#define SYSCON_PIO_WAKEUP_EN0_PA02_WAKEUP_EN_SHIFT (2U)
#define SYSCON_PIO_WAKEUP_EN0_PA02_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA02_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA02_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA03_WAKEUP_EN_MASK (0x8U)
#define SYSCON_PIO_WAKEUP_EN0_PA03_WAKEUP_EN_SHIFT (3U)
#define SYSCON_PIO_WAKEUP_EN0_PA03_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA03_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA03_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA04_WAKEUP_EN_MASK (0x10U)
#define SYSCON_PIO_WAKEUP_EN0_PA04_WAKEUP_EN_SHIFT (4U)
#define SYSCON_PIO_WAKEUP_EN0_PA04_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA04_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA04_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA05_WAKEUP_EN_MASK (0x20U)
#define SYSCON_PIO_WAKEUP_EN0_PA05_WAKEUP_EN_SHIFT (5U)
#define SYSCON_PIO_WAKEUP_EN0_PA05_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA05_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA05_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA06_WAKEUP_EN_MASK (0x40U)
#define SYSCON_PIO_WAKEUP_EN0_PA06_WAKEUP_EN_SHIFT (6U)
#define SYSCON_PIO_WAKEUP_EN0_PA06_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA06_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA06_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA07_WAKEUP_EN_MASK (0x80U)
#define SYSCON_PIO_WAKEUP_EN0_PA07_WAKEUP_EN_SHIFT (7U)
#define SYSCON_PIO_WAKEUP_EN0_PA07_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA07_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA07_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA08_WAKEUP_EN_MASK (0x100U)
#define SYSCON_PIO_WAKEUP_EN0_PA08_WAKEUP_EN_SHIFT (8U)
#define SYSCON_PIO_WAKEUP_EN0_PA08_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA08_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA08_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA09_WAKEUP_EN_MASK (0x200U)
#define SYSCON_PIO_WAKEUP_EN0_PA09_WAKEUP_EN_SHIFT (9U)
#define SYSCON_PIO_WAKEUP_EN0_PA09_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA09_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA09_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA10_WAKEUP_EN_MASK (0x400U)
#define SYSCON_PIO_WAKEUP_EN0_PA10_WAKEUP_EN_SHIFT (10U)
#define SYSCON_PIO_WAKEUP_EN0_PA10_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA10_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA10_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA11_WAKEUP_EN_MASK (0x800U)
#define SYSCON_PIO_WAKEUP_EN0_PA11_WAKEUP_EN_SHIFT (11U)
#define SYSCON_PIO_WAKEUP_EN0_PA11_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA11_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA11_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA12_WAKEUP_EN_MASK (0x1000U)
#define SYSCON_PIO_WAKEUP_EN0_PA12_WAKEUP_EN_SHIFT (12U)
#define SYSCON_PIO_WAKEUP_EN0_PA12_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA12_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA12_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA13_WAKEUP_EN_MASK (0x2000U)
#define SYSCON_PIO_WAKEUP_EN0_PA13_WAKEUP_EN_SHIFT (13U)
#define SYSCON_PIO_WAKEUP_EN0_PA13_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA13_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA13_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA14_WAKEUP_EN_MASK (0x4000U)
#define SYSCON_PIO_WAKEUP_EN0_PA14_WAKEUP_EN_SHIFT (14U)
#define SYSCON_PIO_WAKEUP_EN0_PA14_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA14_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA14_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA15_WAKEUP_EN_MASK (0x8000U)
#define SYSCON_PIO_WAKEUP_EN0_PA15_WAKEUP_EN_SHIFT (15U)
#define SYSCON_PIO_WAKEUP_EN0_PA15_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA15_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA15_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA16_WAKEUP_EN_MASK (0x10000U)
#define SYSCON_PIO_WAKEUP_EN0_PA16_WAKEUP_EN_SHIFT (16U)
#define SYSCON_PIO_WAKEUP_EN0_PA16_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA16_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA16_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA17_WAKEUP_EN_MASK (0x20000U)
#define SYSCON_PIO_WAKEUP_EN0_PA17_WAKEUP_EN_SHIFT (17U)
#define SYSCON_PIO_WAKEUP_EN0_PA17_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA17_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA17_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA18_WAKEUP_EN_MASK (0x40000U)
#define SYSCON_PIO_WAKEUP_EN0_PA18_WAKEUP_EN_SHIFT (18U)
#define SYSCON_PIO_WAKEUP_EN0_PA18_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA18_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA18_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA19_WAKEUP_EN_MASK (0x80000U)
#define SYSCON_PIO_WAKEUP_EN0_PA19_WAKEUP_EN_SHIFT (19U)
#define SYSCON_PIO_WAKEUP_EN0_PA19_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA19_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA19_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA20_WAKEUP_EN_MASK (0x100000U)
#define SYSCON_PIO_WAKEUP_EN0_PA20_WAKEUP_EN_SHIFT (20U)
#define SYSCON_PIO_WAKEUP_EN0_PA20_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA20_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA20_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA21_WAKEUP_EN_MASK (0x200000U)
#define SYSCON_PIO_WAKEUP_EN0_PA21_WAKEUP_EN_SHIFT (21U)
#define SYSCON_PIO_WAKEUP_EN0_PA21_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA21_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA21_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA22_WAKEUP_EN_MASK (0x400000U)
#define SYSCON_PIO_WAKEUP_EN0_PA22_WAKEUP_EN_SHIFT (22U)
#define SYSCON_PIO_WAKEUP_EN0_PA22_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA22_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA22_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA23_WAKEUP_EN_MASK (0x800000U)
#define SYSCON_PIO_WAKEUP_EN0_PA23_WAKEUP_EN_SHIFT (23U)
#define SYSCON_PIO_WAKEUP_EN0_PA23_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA23_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA23_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA24_WAKEUP_EN_MASK (0x1000000U)
#define SYSCON_PIO_WAKEUP_EN0_PA24_WAKEUP_EN_SHIFT (24U)
#define SYSCON_PIO_WAKEUP_EN0_PA24_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA24_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA24_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA25_WAKEUP_EN_MASK (0x2000000U)
#define SYSCON_PIO_WAKEUP_EN0_PA25_WAKEUP_EN_SHIFT (25U)
#define SYSCON_PIO_WAKEUP_EN0_PA25_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA25_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA25_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA26_WAKEUP_EN_MASK (0x4000000U)
#define SYSCON_PIO_WAKEUP_EN0_PA26_WAKEUP_EN_SHIFT (26U)
#define SYSCON_PIO_WAKEUP_EN0_PA26_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA26_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA26_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA27_WAKEUP_EN_MASK (0x8000000U)
#define SYSCON_PIO_WAKEUP_EN0_PA27_WAKEUP_EN_SHIFT (27U)
#define SYSCON_PIO_WAKEUP_EN0_PA27_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA27_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA27_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA28_WAKEUP_EN_MASK (0x10000000U)
#define SYSCON_PIO_WAKEUP_EN0_PA28_WAKEUP_EN_SHIFT (28U)
#define SYSCON_PIO_WAKEUP_EN0_PA28_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA28_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA28_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA29_WAKEUP_EN_MASK (0x20000000U)
#define SYSCON_PIO_WAKEUP_EN0_PA29_WAKEUP_EN_SHIFT (29U)
#define SYSCON_PIO_WAKEUP_EN0_PA29_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA29_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA29_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA30_WAKEUP_EN_MASK (0x40000000U)
#define SYSCON_PIO_WAKEUP_EN0_PA30_WAKEUP_EN_SHIFT (30U)
#define SYSCON_PIO_WAKEUP_EN0_PA30_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA30_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA30_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN0_PA31_WAKEUP_EN_MASK (0x80000000U)
#define SYSCON_PIO_WAKEUP_EN0_PA31_WAKEUP_EN_SHIFT (31U)
#define SYSCON_PIO_WAKEUP_EN0_PA31_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN0_PA31_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN0_PA31_WAKEUP_EN_MASK)
/*! @name PIO_WAKEUP_EN1 - pin function selection in power down mode register 1 */
#define SYSCON_PIO_WAKEUP_EN1_PB00_WAKEUP_EN_MASK (0x1U)
#define SYSCON_PIO_WAKEUP_EN1_PB00_WAKEUP_EN_SHIFT (0U)
#define SYSCON_PIO_WAKEUP_EN1_PB00_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PB00_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN1_PB00_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PB01_WAKEUP_EN_MASK (0x2U)
#define SYSCON_PIO_WAKEUP_EN1_PB01_WAKEUP_EN_SHIFT (1U)
#define SYSCON_PIO_WAKEUP_EN1_PB01_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PB01_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN1_PB01_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PB02_WAKEUP_EN_MASK (0x4U)
#define SYSCON_PIO_WAKEUP_EN1_PB02_WAKEUP_EN_SHIFT (2U)
#define SYSCON_PIO_WAKEUP_EN1_PB02_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PB02_WAKEUP_EN_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN1_PB02_WAKEUP_EN_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PA04_32K_OE_MASK (0x10U)
#define SYSCON_PIO_WAKEUP_EN1_PA04_32K_OE_SHIFT (4U)
#define SYSCON_PIO_WAKEUP_EN1_PA04_32K_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PA04_32K_OE_SHIFT)) & SYSCON_PIO_WAKEUP_EN1_PA04_32K_OE_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PA05_XTAL_OE_MASK (0x20U)
#define SYSCON_PIO_WAKEUP_EN1_PA05_XTAL_OE_SHIFT (5U)
#define SYSCON_PIO_WAKEUP_EN1_PA05_XTAL_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PA05_XTAL_OE_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN1_PA05_XTAL_OE_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PA10_32K_OE_MASK (0x400U)
#define SYSCON_PIO_WAKEUP_EN1_PA10_32K_OE_SHIFT (10U)
#define SYSCON_PIO_WAKEUP_EN1_PA10_32K_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PA10_32K_OE_SHIFT)) & SYSCON_PIO_WAKEUP_EN1_PA10_32K_OE_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PA11_XTAL_OE_MASK (0x800U)
#define SYSCON_PIO_WAKEUP_EN1_PA11_XTAL_OE_SHIFT (11U)
#define SYSCON_PIO_WAKEUP_EN1_PA11_XTAL_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PA11_XTAL_OE_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN1_PA11_XTAL_OE_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PA18_32K_OE_MASK (0x40000U)
#define SYSCON_PIO_WAKEUP_EN1_PA18_32K_OE_SHIFT (18U)
#define SYSCON_PIO_WAKEUP_EN1_PA18_32K_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PA18_32K_OE_SHIFT)) & SYSCON_PIO_WAKEUP_EN1_PA18_32K_OE_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PA19_XTAL_OE_MASK (0x80000U)
#define SYSCON_PIO_WAKEUP_EN1_PA19_XTAL_OE_SHIFT (19U)
#define SYSCON_PIO_WAKEUP_EN1_PA19_XTAL_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PA19_XTAL_OE_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN1_PA19_XTAL_OE_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PA24_32K_OE_MASK (0x1000000U)
#define SYSCON_PIO_WAKEUP_EN1_PA24_32K_OE_SHIFT (24U)
#define SYSCON_PIO_WAKEUP_EN1_PA24_32K_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PA24_32K_OE_SHIFT)) & SYSCON_PIO_WAKEUP_EN1_PA24_32K_OE_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PA25_XTAL_OE_MASK (0x2000000U)
#define SYSCON_PIO_WAKEUP_EN1_PA25_XTAL_OE_SHIFT (25U)
#define SYSCON_PIO_WAKEUP_EN1_PA25_XTAL_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PA25_XTAL_OE_SHIFT)) & \
SYSCON_PIO_WAKEUP_EN1_PA25_XTAL_OE_MASK)
#define SYSCON_PIO_WAKEUP_EN1_PDM_IO_SEL_MASK (0x80000000U)
#define SYSCON_PIO_WAKEUP_EN1_PDM_IO_SEL_SHIFT (31U)
#define SYSCON_PIO_WAKEUP_EN1_PDM_IO_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_WAKEUP_EN1_PDM_IO_SEL_SHIFT)) & SYSCON_PIO_WAKEUP_EN1_PDM_IO_SEL_MASK)
/*! @name PIO_CAP_OE0 - pin output enable status register 0 while captured by writing 1 to IO_CAP */
#define SYSCON_PIO_CAP_OE0_PA00_CAP_OE_MASK (0x1U)
#define SYSCON_PIO_CAP_OE0_PA00_CAP_OE_SHIFT (0U)
#define SYSCON_PIO_CAP_OE0_PA00_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA00_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA00_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA01_CAP_OE_MASK (0x2U)
#define SYSCON_PIO_CAP_OE0_PA01_CAP_OE_SHIFT (1U)
#define SYSCON_PIO_CAP_OE0_PA01_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA01_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA01_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA02_CAP_OE_MASK (0x4U)
#define SYSCON_PIO_CAP_OE0_PA02_CAP_OE_SHIFT (2U)
#define SYSCON_PIO_CAP_OE0_PA02_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA02_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA02_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA03_CAP_OE_MASK (0x8U)
#define SYSCON_PIO_CAP_OE0_PA03_CAP_OE_SHIFT (3U)
#define SYSCON_PIO_CAP_OE0_PA03_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA03_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA03_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA04_CAP_OE_MASK (0x10U)
#define SYSCON_PIO_CAP_OE0_PA04_CAP_OE_SHIFT (4U)
#define SYSCON_PIO_CAP_OE0_PA04_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA04_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA04_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA05_CAP_OE_MASK (0x20U)
#define SYSCON_PIO_CAP_OE0_PA05_CAP_OE_SHIFT (5U)
#define SYSCON_PIO_CAP_OE0_PA05_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA05_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA05_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA06_CAP_OE_MASK (0x40U)
#define SYSCON_PIO_CAP_OE0_PA06_CAP_OE_SHIFT (6U)
#define SYSCON_PIO_CAP_OE0_PA06_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA06_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA06_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA07_CAP_OE_MASK (0x80U)
#define SYSCON_PIO_CAP_OE0_PA07_CAP_OE_SHIFT (7U)
#define SYSCON_PIO_CAP_OE0_PA07_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA07_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA07_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA08_CAP_OE_MASK (0x100U)
#define SYSCON_PIO_CAP_OE0_PA08_CAP_OE_SHIFT (8U)
#define SYSCON_PIO_CAP_OE0_PA08_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA08_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA08_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA09_CAP_OE_MASK (0x200U)
#define SYSCON_PIO_CAP_OE0_PA09_CAP_OE_SHIFT (9U)
#define SYSCON_PIO_CAP_OE0_PA09_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA09_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA09_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA10_CAP_OE_MASK (0x400U)
#define SYSCON_PIO_CAP_OE0_PA10_CAP_OE_SHIFT (10U)
#define SYSCON_PIO_CAP_OE0_PA10_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA10_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA10_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA11_CAP_OE_MASK (0x800U)
#define SYSCON_PIO_CAP_OE0_PA11_CAP_OE_SHIFT (11U)
#define SYSCON_PIO_CAP_OE0_PA11_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA11_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA11_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA12_CAP_OE_MASK (0x1000U)
#define SYSCON_PIO_CAP_OE0_PA12_CAP_OE_SHIFT (12U)
#define SYSCON_PIO_CAP_OE0_PA12_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA12_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA12_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA13_CAP_OE_MASK (0x2000U)
#define SYSCON_PIO_CAP_OE0_PA13_CAP_OE_SHIFT (13U)
#define SYSCON_PIO_CAP_OE0_PA13_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA13_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA13_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA14_CAP_OE_MASK (0x4000U)
#define SYSCON_PIO_CAP_OE0_PA14_CAP_OE_SHIFT (14U)
#define SYSCON_PIO_CAP_OE0_PA14_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA14_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA14_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA15_CAP_OE_MASK (0x8000U)
#define SYSCON_PIO_CAP_OE0_PA15_CAP_OE_SHIFT (15U)
#define SYSCON_PIO_CAP_OE0_PA15_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA15_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA15_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA16_CAP_OE_MASK (0x10000U)
#define SYSCON_PIO_CAP_OE0_PA16_CAP_OE_SHIFT (16U)
#define SYSCON_PIO_CAP_OE0_PA16_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA16_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA16_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA17_CAP_OE_MASK (0x20000U)
#define SYSCON_PIO_CAP_OE0_PA17_CAP_OE_SHIFT (17U)
#define SYSCON_PIO_CAP_OE0_PA17_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA17_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA17_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA18_CAP_OE_MASK (0x40000U)
#define SYSCON_PIO_CAP_OE0_PA18_CAP_OE_SHIFT (18U)
#define SYSCON_PIO_CAP_OE0_PA18_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA18_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA18_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA19_CAP_OE_MASK (0x80000U)
#define SYSCON_PIO_CAP_OE0_PA19_CAP_OE_SHIFT (19U)
#define SYSCON_PIO_CAP_OE0_PA19_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA19_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA19_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA20_CAP_OE_MASK (0x100000U)
#define SYSCON_PIO_CAP_OE0_PA20_CAP_OE_SHIFT (20U)
#define SYSCON_PIO_CAP_OE0_PA20_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA20_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA20_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA21_CAP_OE_MASK (0x200000U)
#define SYSCON_PIO_CAP_OE0_PA21_CAP_OE_SHIFT (21U)
#define SYSCON_PIO_CAP_OE0_PA21_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA21_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA21_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA22_CAP_OE_MASK (0x400000U)
#define SYSCON_PIO_CAP_OE0_PA22_CAP_OE_SHIFT (22U)
#define SYSCON_PIO_CAP_OE0_PA22_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA22_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA22_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA23_CAP_OE_MASK (0x800000U)
#define SYSCON_PIO_CAP_OE0_PA23_CAP_OE_SHIFT (23U)
#define SYSCON_PIO_CAP_OE0_PA23_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA23_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA23_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA24_CAP_OE_MASK (0x1000000U)
#define SYSCON_PIO_CAP_OE0_PA24_CAP_OE_SHIFT (24U)
#define SYSCON_PIO_CAP_OE0_PA24_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA24_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA24_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA25_CAP_OE_MASK (0x2000000U)
#define SYSCON_PIO_CAP_OE0_PA25_CAP_OE_SHIFT (25U)
#define SYSCON_PIO_CAP_OE0_PA25_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA25_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA25_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA26_CAP_OE_MASK (0x4000000U)
#define SYSCON_PIO_CAP_OE0_PA26_CAP_OE_SHIFT (26U)
#define SYSCON_PIO_CAP_OE0_PA26_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA26_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA26_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA27_CAP_OE_MASK (0x8000000U)
#define SYSCON_PIO_CAP_OE0_PA27_CAP_OE_SHIFT (27U)
#define SYSCON_PIO_CAP_OE0_PA27_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA27_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA27_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA28_CAP_OE_MASK (0x10000000U)
#define SYSCON_PIO_CAP_OE0_PA28_CAP_OE_SHIFT (28U)
#define SYSCON_PIO_CAP_OE0_PA28_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA28_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA28_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA29_CAP_OE_MASK (0x20000000U)
#define SYSCON_PIO_CAP_OE0_PA29_CAP_OE_SHIFT (29U)
#define SYSCON_PIO_CAP_OE0_PA29_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA29_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA29_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA30_CAP_OE_MASK (0x40000000U)
#define SYSCON_PIO_CAP_OE0_PA30_CAP_OE_SHIFT (30U)
#define SYSCON_PIO_CAP_OE0_PA30_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA30_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA30_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE0_PA31_CAP_OE_MASK (0x80000000U)
#define SYSCON_PIO_CAP_OE0_PA31_CAP_OE_SHIFT (31U)
#define SYSCON_PIO_CAP_OE0_PA31_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE0_PA31_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE0_PA31_CAP_OE_MASK)
/*! @name PIO_CAP_OE1 - pin output enable status register 1 while captured by writing 1 to IO_CAP */
#define SYSCON_PIO_CAP_OE1_PB00_CAP_OE_MASK (0x1U)
#define SYSCON_PIO_CAP_OE1_PB00_CAP_OE_SHIFT (0U)
#define SYSCON_PIO_CAP_OE1_PB00_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE1_PB00_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE1_PB00_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE1_PB01_CAP_OE_MASK (0x2U)
#define SYSCON_PIO_CAP_OE1_PB01_CAP_OE_SHIFT (1U)
#define SYSCON_PIO_CAP_OE1_PB01_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE1_PB01_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE1_PB01_CAP_OE_MASK)
#define SYSCON_PIO_CAP_OE1_PB02_CAP_OE_MASK (0x4U)
#define SYSCON_PIO_CAP_OE1_PB02_CAP_OE_SHIFT (2U)
#define SYSCON_PIO_CAP_OE1_PB02_CAP_OE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OE1_PB02_CAP_OE_SHIFT)) & SYSCON_PIO_CAP_OE1_PB02_CAP_OE_MASK)
/*! @name PIO_CAP_OUT0 - pin output status register 0 while captured by writing 1 to IO_CAP */
#define SYSCON_PIO_CAP_OUT0_PA00_CAP_OUT_MASK (0x1U)
#define SYSCON_PIO_CAP_OUT0_PA00_CAP_OUT_SHIFT (0U)
#define SYSCON_PIO_CAP_OUT0_PA00_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA00_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA00_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA01_CAP_OUT_MASK (0x2U)
#define SYSCON_PIO_CAP_OUT0_PA01_CAP_OUT_SHIFT (1U)
#define SYSCON_PIO_CAP_OUT0_PA01_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA01_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA01_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA02_CAP_OUT_MASK (0x4U)
#define SYSCON_PIO_CAP_OUT0_PA02_CAP_OUT_SHIFT (2U)
#define SYSCON_PIO_CAP_OUT0_PA02_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA02_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA02_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA03_CAP_OUT_MASK (0x8U)
#define SYSCON_PIO_CAP_OUT0_PA03_CAP_OUT_SHIFT (3U)
#define SYSCON_PIO_CAP_OUT0_PA03_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA03_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA03_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA04_CAP_OUT_MASK (0x10U)
#define SYSCON_PIO_CAP_OUT0_PA04_CAP_OUT_SHIFT (4U)
#define SYSCON_PIO_CAP_OUT0_PA04_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA04_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA04_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA05_CAP_OUT_MASK (0x20U)
#define SYSCON_PIO_CAP_OUT0_PA05_CAP_OUT_SHIFT (5U)
#define SYSCON_PIO_CAP_OUT0_PA05_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA05_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA05_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA06_CAP_OUT_MASK (0x40U)
#define SYSCON_PIO_CAP_OUT0_PA06_CAP_OUT_SHIFT (6U)
#define SYSCON_PIO_CAP_OUT0_PA06_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA06_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA06_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA07_CAP_OUT_MASK (0x80U)
#define SYSCON_PIO_CAP_OUT0_PA07_CAP_OUT_SHIFT (7U)
#define SYSCON_PIO_CAP_OUT0_PA07_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA07_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA07_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA08_CAP_OUT_MASK (0x100U)
#define SYSCON_PIO_CAP_OUT0_PA08_CAP_OUT_SHIFT (8U)
#define SYSCON_PIO_CAP_OUT0_PA08_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA08_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA08_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA09_CAP_OUT_MASK (0x200U)
#define SYSCON_PIO_CAP_OUT0_PA09_CAP_OUT_SHIFT (9U)
#define SYSCON_PIO_CAP_OUT0_PA09_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA09_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA09_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA10_CAP_OUT_MASK (0x400U)
#define SYSCON_PIO_CAP_OUT0_PA10_CAP_OUT_SHIFT (10U)
#define SYSCON_PIO_CAP_OUT0_PA10_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA10_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA10_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA11_CAP_OUT_MASK (0x800U)
#define SYSCON_PIO_CAP_OUT0_PA11_CAP_OUT_SHIFT (11U)
#define SYSCON_PIO_CAP_OUT0_PA11_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA11_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA11_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA12_CAP_OUT_MASK (0x1000U)
#define SYSCON_PIO_CAP_OUT0_PA12_CAP_OUT_SHIFT (12U)
#define SYSCON_PIO_CAP_OUT0_PA12_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA12_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA12_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA13_CAP_OUT_MASK (0x2000U)
#define SYSCON_PIO_CAP_OUT0_PA13_CAP_OUT_SHIFT (13U)
#define SYSCON_PIO_CAP_OUT0_PA13_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA13_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA13_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA14_CAP_OUT_MASK (0x4000U)
#define SYSCON_PIO_CAP_OUT0_PA14_CAP_OUT_SHIFT (14U)
#define SYSCON_PIO_CAP_OUT0_PA14_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA14_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA14_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA15_CAP_OUT_MASK (0x8000U)
#define SYSCON_PIO_CAP_OUT0_PA15_CAP_OUT_SHIFT (15U)
#define SYSCON_PIO_CAP_OUT0_PA15_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA15_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA15_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA16_CAP_OUT_MASK (0x10000U)
#define SYSCON_PIO_CAP_OUT0_PA16_CAP_OUT_SHIFT (16U)
#define SYSCON_PIO_CAP_OUT0_PA16_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA16_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA16_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA17_CAP_OUT_MASK (0x20000U)
#define SYSCON_PIO_CAP_OUT0_PA17_CAP_OUT_SHIFT (17U)
#define SYSCON_PIO_CAP_OUT0_PA17_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA17_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA17_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA18_CAP_OUT_MASK (0x40000U)
#define SYSCON_PIO_CAP_OUT0_PA18_CAP_OUT_SHIFT (18U)
#define SYSCON_PIO_CAP_OUT0_PA18_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA18_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA18_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA19_CAP_OUT_MASK (0x80000U)
#define SYSCON_PIO_CAP_OUT0_PA19_CAP_OUT_SHIFT (19U)
#define SYSCON_PIO_CAP_OUT0_PA19_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA19_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA19_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA20_CAP_OUT_MASK (0x100000U)
#define SYSCON_PIO_CAP_OUT0_PA20_CAP_OUT_SHIFT (20U)
#define SYSCON_PIO_CAP_OUT0_PA20_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA20_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA20_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA21_CAP_OUT_MASK (0x200000U)
#define SYSCON_PIO_CAP_OUT0_PA21_CAP_OUT_SHIFT (21U)
#define SYSCON_PIO_CAP_OUT0_PA21_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA21_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA21_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA22_CAP_OUT_MASK (0x400000U)
#define SYSCON_PIO_CAP_OUT0_PA22_CAP_OUT_SHIFT (22U)
#define SYSCON_PIO_CAP_OUT0_PA22_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA22_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA22_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA23_CAP_OUT_MASK (0x800000U)
#define SYSCON_PIO_CAP_OUT0_PA23_CAP_OUT_SHIFT (23U)
#define SYSCON_PIO_CAP_OUT0_PA23_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA23_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA23_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA24_CAP_OUT_MASK (0x1000000U)
#define SYSCON_PIO_CAP_OUT0_PA24_CAP_OUT_SHIFT (24U)
#define SYSCON_PIO_CAP_OUT0_PA24_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA24_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA24_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA25_CAP_OUT_MASK (0x2000000U)
#define SYSCON_PIO_CAP_OUT0_PA25_CAP_OUT_SHIFT (25U)
#define SYSCON_PIO_CAP_OUT0_PA25_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA25_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA25_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA26_CAP_OUT_MASK (0x4000000U)
#define SYSCON_PIO_CAP_OUT0_PA26_CAP_OUT_SHIFT (26U)
#define SYSCON_PIO_CAP_OUT0_PA26_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA26_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA26_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA27_CAP_OUT_MASK (0x8000000U)
#define SYSCON_PIO_CAP_OUT0_PA27_CAP_OUT_SHIFT (27U)
#define SYSCON_PIO_CAP_OUT0_PA27_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA27_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA27_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA28_CAP_OUT_MASK (0x10000000U)
#define SYSCON_PIO_CAP_OUT0_PA28_CAP_OUT_SHIFT (28U)
#define SYSCON_PIO_CAP_OUT0_PA28_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA28_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA28_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA29_CAP_OUT_MASK (0x20000000U)
#define SYSCON_PIO_CAP_OUT0_PA29_CAP_OUT_SHIFT (29U)
#define SYSCON_PIO_CAP_OUT0_PA29_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA29_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA29_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA30_CAP_OUT_MASK (0x40000000U)
#define SYSCON_PIO_CAP_OUT0_PA30_CAP_OUT_SHIFT (30U)
#define SYSCON_PIO_CAP_OUT0_PA30_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA30_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA30_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT0_PA31_CAP_OUT_MASK (0x80000000U)
#define SYSCON_PIO_CAP_OUT0_PA31_CAP_OUT_SHIFT (31U)
#define SYSCON_PIO_CAP_OUT0_PA31_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT0_PA31_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT0_PA31_CAP_OUT_MASK)
/*! @name PIO_CAP_OUT1 - pin output status register 0 while captured by writing 1 to IO_CAP */
#define SYSCON_PIO_CAP_OUT1_PB00_CAP_OUT_MASK (0x1U)
#define SYSCON_PIO_CAP_OUT1_PB00_CAP_OUT_SHIFT (0U)
#define SYSCON_PIO_CAP_OUT1_PB00_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT1_PB00_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT1_PB00_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT1_PB01_CAP_OUT_MASK (0x2U)
#define SYSCON_PIO_CAP_OUT1_PB01_CAP_OUT_SHIFT (1U)
#define SYSCON_PIO_CAP_OUT1_PB01_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT1_PB01_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT1_PB01_CAP_OUT_MASK)
#define SYSCON_PIO_CAP_OUT1_PB02_CAP_OUT_MASK (0x4U)
#define SYSCON_PIO_CAP_OUT1_PB02_CAP_OUT_SHIFT (2U)
#define SYSCON_PIO_CAP_OUT1_PB02_CAP_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PIO_CAP_OUT1_PB02_CAP_OUT_SHIFT)) & SYSCON_PIO_CAP_OUT1_PB02_CAP_OUT_MASK)
/*! @name RST_CAUSE_SRC - reset source status register */
#define SYSCON_RST_CAUSE_SRC_RESET_CAUSE_MASK (0x1FFU)
#define SYSCON_RST_CAUSE_SRC_RESET_CAUSE_SHIFT (0U)
#define SYSCON_RST_CAUSE_SRC_RESET_CAUSE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_CAUSE_SRC_RESET_CAUSE_SHIFT)) & SYSCON_RST_CAUSE_SRC_RESET_CAUSE_MASK)
#define SYSCON_RST_CAUSE_SRC_RST_CAUSE_CLR_MASK (0x80000000U)
#define SYSCON_RST_CAUSE_SRC_RST_CAUSE_CLR_SHIFT (31U)
#define SYSCON_RST_CAUSE_SRC_RST_CAUSE_CLR(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_RST_CAUSE_SRC_RST_CAUSE_CLR_SHIFT)) & \
SYSCON_RST_CAUSE_SRC_RST_CAUSE_CLR_MASK)
/*! @name PMU_CTRL0 - power management uinit control register 0 */
#define SYSCON_PMU_CTRL0_MEM0_DIS_MASK (0x1U)
#define SYSCON_PMU_CTRL0_MEM0_DIS_SHIFT (0U)
#define SYSCON_PMU_CTRL0_MEM0_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM0_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM0_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM1_DIS_MASK (0x2U)
#define SYSCON_PMU_CTRL0_MEM1_DIS_SHIFT (1U)
#define SYSCON_PMU_CTRL0_MEM1_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM1_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM1_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM2_DIS_MASK (0x4U)
#define SYSCON_PMU_CTRL0_MEM2_DIS_SHIFT (2U)
#define SYSCON_PMU_CTRL0_MEM2_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM2_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM2_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM3_DIS_MASK (0x8U)
#define SYSCON_PMU_CTRL0_MEM3_DIS_SHIFT (3U)
#define SYSCON_PMU_CTRL0_MEM3_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM3_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM3_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM4_DIS_MASK (0x10U)
#define SYSCON_PMU_CTRL0_MEM4_DIS_SHIFT (4U)
#define SYSCON_PMU_CTRL0_MEM4_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM4_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM4_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM5_DIS_MASK (0x20U)
#define SYSCON_PMU_CTRL0_MEM5_DIS_SHIFT (5U)
#define SYSCON_PMU_CTRL0_MEM5_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM5_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM5_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM6_DIS_MASK (0x40U)
#define SYSCON_PMU_CTRL0_MEM6_DIS_SHIFT (6U)
#define SYSCON_PMU_CTRL0_MEM6_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM6_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM6_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM7_DIS_MASK (0x80U)
#define SYSCON_PMU_CTRL0_MEM7_DIS_SHIFT (7U)
#define SYSCON_PMU_CTRL0_MEM7_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM7_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM7_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM8_DIS_MASK (0x100U)
#define SYSCON_PMU_CTRL0_MEM8_DIS_SHIFT (8U)
#define SYSCON_PMU_CTRL0_MEM8_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM8_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM8_DIS_MASK)
#define SYSCON_PMU_CTRL0_MEM9_DIS_MASK (0x200U)
#define SYSCON_PMU_CTRL0_MEM9_DIS_SHIFT (9U)
#define SYSCON_PMU_CTRL0_MEM9_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MEM9_DIS_SHIFT)) & SYSCON_PMU_CTRL0_MEM9_DIS_MASK)
#define SYSCON_PMU_CTRL0_BLE_DIS_MASK (0x10000U)
#define SYSCON_PMU_CTRL0_BLE_DIS_SHIFT (16U)
#define SYSCON_PMU_CTRL0_BLE_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_BLE_DIS_SHIFT)) & SYSCON_PMU_CTRL0_BLE_DIS_MASK)
#define SYSCON_PMU_CTRL0_FIR_DIS_MASK (0x20000U)
#define SYSCON_PMU_CTRL0_FIR_DIS_SHIFT (17U)
#define SYSCON_PMU_CTRL0_FIR_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_FIR_DIS_SHIFT)) & SYSCON_PMU_CTRL0_FIR_DIS_MASK)
#define SYSCON_PMU_CTRL0_FSP_DIS_MASK (0x40000U)
#define SYSCON_PMU_CTRL0_FSP_DIS_SHIFT (18U)
#define SYSCON_PMU_CTRL0_FSP_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_FSP_DIS_SHIFT)) & SYSCON_PMU_CTRL0_FSP_DIS_MASK)
#define SYSCON_PMU_CTRL0_MCU_MODE_MASK (0x100000U)
#define SYSCON_PMU_CTRL0_MCU_MODE_SHIFT (20U)
#define SYSCON_PMU_CTRL0_MCU_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_MCU_MODE_SHIFT)) & SYSCON_PMU_CTRL0_MCU_MODE_MASK)
#define SYSCON_PMU_CTRL0_OSC_INT_EN_MASK (0x4000000U)
#define SYSCON_PMU_CTRL0_OSC_INT_EN_SHIFT (26U)
#define SYSCON_PMU_CTRL0_OSC_INT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_OSC_INT_EN_SHIFT)) & SYSCON_PMU_CTRL0_OSC_INT_EN_MASK)
#define SYSCON_PMU_CTRL0_RTC_SEC_WAKEUP_EN_MASK (0x8000000U)
#define SYSCON_PMU_CTRL0_RTC_SEC_WAKEUP_EN_SHIFT (27U)
#define SYSCON_PMU_CTRL0_RTC_SEC_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_RTC_SEC_WAKEUP_EN_SHIFT)) & \
SYSCON_PMU_CTRL0_RTC_SEC_WAKEUP_EN_MASK)
#define SYSCON_PMU_CTRL0_WAKEUP_EN_MASK (0x10000000U)
#define SYSCON_PMU_CTRL0_WAKEUP_EN_SHIFT (28U)
#define SYSCON_PMU_CTRL0_WAKEUP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_WAKEUP_EN_SHIFT)) & SYSCON_PMU_CTRL0_WAKEUP_EN_MASK)
#define SYSCON_PMU_CTRL0_PMU_EN_MASK (0x20000000U)
#define SYSCON_PMU_CTRL0_PMU_EN_SHIFT (29U)
#define SYSCON_PMU_CTRL0_PMU_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_PMU_EN_SHIFT)) & SYSCON_PMU_CTRL0_PMU_EN_MASK)
#define SYSCON_PMU_CTRL0_RETENTION_EN_MASK (0x40000000U)
#define SYSCON_PMU_CTRL0_RETENTION_EN_SHIFT (30U)
#define SYSCON_PMU_CTRL0_RETENTION_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_RETENTION_EN_SHIFT)) & SYSCON_PMU_CTRL0_RETENTION_EN_MASK)
#define SYSCON_PMU_CTRL0_BOND_EN_MASK (0x80000000U)
#define SYSCON_PMU_CTRL0_BOND_EN_SHIFT (31U)
#define SYSCON_PMU_CTRL0_BOND_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL0_BOND_EN_SHIFT)) & SYSCON_PMU_CTRL0_BOND_EN_MASK)
/*! @name PMU_CTRL1 - power management uinit control register 1 */
#define SYSCON_PMU_CTRL1_RCO32K_DIS_MASK (0x1U)
#define SYSCON_PMU_CTRL1_RCO32K_DIS_SHIFT (0U)
#define SYSCON_PMU_CTRL1_RCO32K_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_RCO32K_DIS_SHIFT)) & SYSCON_PMU_CTRL1_RCO32K_DIS_MASK)
#define SYSCON_PMU_CTRL1_XTAL32K_DIS_MASK (0x2U)
#define SYSCON_PMU_CTRL1_XTAL32K_DIS_SHIFT (1U)
#define SYSCON_PMU_CTRL1_XTAL32K_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_XTAL32K_DIS_SHIFT)) & SYSCON_PMU_CTRL1_XTAL32K_DIS_MASK)
#define SYSCON_PMU_CTRL1_XTAL_DIS_MASK (0x4U)
#define SYSCON_PMU_CTRL1_XTAL_DIS_SHIFT (2U)
#define SYSCON_PMU_CTRL1_XTAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_XTAL_DIS_SHIFT)) & SYSCON_PMU_CTRL1_XTAL_DIS_MASK)
#define SYSCON_PMU_CTRL1_OSC32M_DIS_MASK (0x8U)
#define SYSCON_PMU_CTRL1_OSC32M_DIS_SHIFT (3U)
#define SYSCON_PMU_CTRL1_OSC32M_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_OSC32M_DIS_SHIFT)) & SYSCON_PMU_CTRL1_OSC32M_DIS_MASK)
#define SYSCON_PMU_CTRL1_USBPLL_DIS_MASK (0x10U)
#define SYSCON_PMU_CTRL1_USBPLL_DIS_SHIFT (4U)
#define SYSCON_PMU_CTRL1_USBPLL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_USBPLL_DIS_SHIFT)) & SYSCON_PMU_CTRL1_USBPLL_DIS_MASK)
#define SYSCON_PMU_CTRL1_ADC_BUF_DIS_MASK (0x20U)
#define SYSCON_PMU_CTRL1_ADC_BUF_DIS_SHIFT (5U)
#define SYSCON_PMU_CTRL1_ADC_BUF_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_ADC_BUF_DIS_SHIFT)) & SYSCON_PMU_CTRL1_ADC_BUF_DIS_MASK)
#define SYSCON_PMU_CTRL1_ADC_BG_DIS_MASK (0x40U)
#define SYSCON_PMU_CTRL1_ADC_BG_DIS_SHIFT (6U)
#define SYSCON_PMU_CTRL1_ADC_BG_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_ADC_BG_DIS_SHIFT)) & SYSCON_PMU_CTRL1_ADC_BG_DIS_MASK)
#define SYSCON_PMU_CTRL1_ADC_DIS_MASK (0x80U)
#define SYSCON_PMU_CTRL1_ADC_DIS_SHIFT (7U)
#define SYSCON_PMU_CTRL1_ADC_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_ADC_DIS_SHIFT)) & SYSCON_PMU_CTRL1_ADC_DIS_MASK)
#define SYSCON_PMU_CTRL1_ADC_VCM_DIS_MASK (0x100U)
#define SYSCON_PMU_CTRL1_ADC_VCM_DIS_SHIFT (8U)
#define SYSCON_PMU_CTRL1_ADC_VCM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_ADC_VCM_DIS_SHIFT)) & SYSCON_PMU_CTRL1_ADC_VCM_DIS_MASK)
#define SYSCON_PMU_CTRL1_ADC_VREF_DIS_MASK (0x200U)
#define SYSCON_PMU_CTRL1_ADC_VREF_DIS_SHIFT (9U)
#define SYSCON_PMU_CTRL1_ADC_VREF_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_ADC_VREF_DIS_SHIFT)) & SYSCON_PMU_CTRL1_ADC_VREF_DIS_MASK)
#define SYSCON_PMU_CTRL1_DAC_DIS_MASK (0x400U)
#define SYSCON_PMU_CTRL1_DAC_DIS_SHIFT (10U)
#define SYSCON_PMU_CTRL1_DAC_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_DAC_DIS_SHIFT)) & SYSCON_PMU_CTRL1_DAC_DIS_MASK)
#define SYSCON_PMU_CTRL1_CAP_SEN_DIS_MASK (0x800U)
#define SYSCON_PMU_CTRL1_CAP_SEN_DIS_SHIFT (11U)
#define SYSCON_PMU_CTRL1_CAP_SEN_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_CAP_SEN_DIS_SHIFT)) & SYSCON_PMU_CTRL1_CAP_SEN_DIS_MASK)
#define SYSCON_PMU_CTRL1_BUCK_CTRL_MASK (0xF0000U)
#define SYSCON_PMU_CTRL1_BUCK_CTRL_SHIFT (16U)
#define SYSCON_PMU_CTRL1_BUCK_CTRL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_BUCK_CTRL_SHIFT)) & SYSCON_PMU_CTRL1_BUCK_CTRL_MASK)
#define SYSCON_PMU_CTRL1_RCO32K_PDM_DIS_MASK (0x40000000U)
#define SYSCON_PMU_CTRL1_RCO32K_PDM_DIS_SHIFT (30U)
#define SYSCON_PMU_CTRL1_RCO32K_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_RCO32K_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL1_RCO32K_PDM_DIS_MASK)
#define SYSCON_PMU_CTRL1_XTAL32K_PDM_DIS_MASK (0x80000000U)
#define SYSCON_PMU_CTRL1_XTAL32K_PDM_DIS_SHIFT (31U)
#define SYSCON_PMU_CTRL1_XTAL32K_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL1_XTAL32K_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL1_XTAL32K_PDM_DIS_MASK)
/*! @name ANA_EN - analog setting register */
#define SYSCON_ANA_EN_BOD_AMP_EN_MASK (0x1U)
#define SYSCON_ANA_EN_BOD_AMP_EN_SHIFT (0U)
#define SYSCON_ANA_EN_BOD_AMP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_BOD_AMP_EN_SHIFT)) & SYSCON_ANA_EN_BOD_AMP_EN_MASK)
#define SYSCON_ANA_EN_BOD_EN_MASK (0x2U)
#define SYSCON_ANA_EN_BOD_EN_SHIFT (1U)
#define SYSCON_ANA_EN_BOD_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_BOD_EN_SHIFT)) & SYSCON_ANA_EN_BOD_EN_MASK)
#define SYSCON_ANA_EN_BAT_MON_EN_MASK (0x4U)
#define SYSCON_ANA_EN_BAT_MON_EN_SHIFT (2U)
#define SYSCON_ANA_EN_BAT_MON_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_BAT_MON_EN_SHIFT)) & SYSCON_ANA_EN_BAT_MON_EN_MASK)
#define SYSCON_ANA_EN_ACMP0_EN_MASK (0x8U)
#define SYSCON_ANA_EN_ACMP0_EN_SHIFT (3U)
#define SYSCON_ANA_EN_ACMP0_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP0_EN_SHIFT)) & SYSCON_ANA_EN_ACMP0_EN_MASK)
#define SYSCON_ANA_EN_ACMP1_EN_MASK (0x10U)
#define SYSCON_ANA_EN_ACMP1_EN_SHIFT (4U)
#define SYSCON_ANA_EN_ACMP1_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP1_EN_SHIFT)) & SYSCON_ANA_EN_ACMP1_EN_MASK)
#define SYSCON_ANA_EN_BOR_AMP_EN_MASK (0x20U)
#define SYSCON_ANA_EN_BOR_AMP_EN_SHIFT (5U)
#define SYSCON_ANA_EN_BOR_AMP_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_BOR_AMP_EN_SHIFT)) & SYSCON_ANA_EN_BOR_AMP_EN_MASK)
#define SYSCON_ANA_EN_BOR_EN_MASK (0x40U)
#define SYSCON_ANA_EN_BOR_EN_SHIFT (6U)
#define SYSCON_ANA_EN_BOR_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_BOR_EN_SHIFT)) & SYSCON_ANA_EN_BOR_EN_MASK)
#define SYSCON_ANA_EN_ACMP0_REF_MASK (0xF00U)
#define SYSCON_ANA_EN_ACMP0_REF_SHIFT (8U)
#define SYSCON_ANA_EN_ACMP0_REF(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP0_REF_SHIFT)) & SYSCON_ANA_EN_ACMP0_REF_MASK)
#define SYSCON_ANA_EN_ACMP1_REF_MASK (0xF000U)
#define SYSCON_ANA_EN_ACMP1_REF_SHIFT (12U)
#define SYSCON_ANA_EN_ACMP1_REF(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP1_REF_SHIFT)) & SYSCON_ANA_EN_ACMP1_REF_MASK)
#define SYSCON_ANA_EN_ACMP0_HYST_EN_MASK (0x10000U)
#define SYSCON_ANA_EN_ACMP0_HYST_EN_SHIFT (16U)
#define SYSCON_ANA_EN_ACMP0_HYST_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP0_HYST_EN_SHIFT)) & SYSCON_ANA_EN_ACMP0_HYST_EN_MASK)
#define SYSCON_ANA_EN_ACMP1_HYST_EN_MASK (0x20000U)
#define SYSCON_ANA_EN_ACMP1_HYST_EN_SHIFT (17U)
#define SYSCON_ANA_EN_ACMP1_HYST_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP1_HYST_EN_SHIFT)) & SYSCON_ANA_EN_ACMP1_HYST_EN_MASK)
#define SYSCON_ANA_EN_ACMP_VREF_SEL_MASK (0x40000U)
#define SYSCON_ANA_EN_ACMP_VREF_SEL_SHIFT (18U)
#define SYSCON_ANA_EN_ACMP_VREF_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP_VREF_SEL_SHIFT)) & SYSCON_ANA_EN_ACMP_VREF_SEL_MASK)
#define SYSCON_ANA_EN_BOD_THR_MASK (0x180000U)
#define SYSCON_ANA_EN_BOD_THR_SHIFT (19U)
#define SYSCON_ANA_EN_BOD_THR(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_BOD_THR_SHIFT)) & SYSCON_ANA_EN_BOD_THR_MASK)
#define SYSCON_ANA_EN_BOR_THR_MASK (0x600000U)
#define SYSCON_ANA_EN_BOR_THR_SHIFT (21U)
#define SYSCON_ANA_EN_BOR_THR(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_BOR_THR_SHIFT)) & SYSCON_ANA_EN_BOR_THR_MASK)
#define SYSCON_ANA_EN_ACMP0_OUT_MASK (0x1000000U)
#define SYSCON_ANA_EN_ACMP0_OUT_SHIFT (24U)
#define SYSCON_ANA_EN_ACMP0_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP0_OUT_SHIFT)) & SYSCON_ANA_EN_ACMP0_OUT_MASK)
#define SYSCON_ANA_EN_ACMP1_OUT_MASK (0x2000000U)
#define SYSCON_ANA_EN_ACMP1_OUT_SHIFT (25U)
#define SYSCON_ANA_EN_ACMP1_OUT(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP1_OUT_SHIFT)) & SYSCON_ANA_EN_ACMP1_OUT_MASK)
#define SYSCON_ANA_EN_ACMP0_EDGE_SEL_MASK (0xC000000U)
#define SYSCON_ANA_EN_ACMP0_EDGE_SEL_SHIFT (26U)
#define SYSCON_ANA_EN_ACMP0_EDGE_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP0_EDGE_SEL_SHIFT)) & SYSCON_ANA_EN_ACMP0_EDGE_SEL_MASK)
#define SYSCON_ANA_EN_ACMP1_EDGE_SEL_MASK (0x30000000U)
#define SYSCON_ANA_EN_ACMP1_EDGE_SEL_SHIFT (28U)
#define SYSCON_ANA_EN_ACMP1_EDGE_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP1_EDGE_SEL_SHIFT)) & SYSCON_ANA_EN_ACMP1_EDGE_SEL_MASK)
#define SYSCON_ANA_EN_ACMP0_INTEN_MASK (0x40000000U)
#define SYSCON_ANA_EN_ACMP0_INTEN_SHIFT (30U)
#define SYSCON_ANA_EN_ACMP0_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP0_INTEN_SHIFT)) & SYSCON_ANA_EN_ACMP0_INTEN_MASK)
#define SYSCON_ANA_EN_ACMP1_INTEN_MASK (0x80000000U)
#define SYSCON_ANA_EN_ACMP1_INTEN_SHIFT (31U)
#define SYSCON_ANA_EN_ACMP1_INTEN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_EN_ACMP1_INTEN_SHIFT)) & SYSCON_ANA_EN_ACMP1_INTEN_MASK)
/*! @name XTAL32K_CTRL - crystal 32K control register */
#define SYSCON_XTAL32K_CTRL_XTAL32K_ICTRL_MASK (0x3FU)
#define SYSCON_XTAL32K_CTRL_XTAL32K_ICTRL_SHIFT (0U)
#define SYSCON_XTAL32K_CTRL_XTAL32K_ICTRL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32K_CTRL_XTAL32K_ICTRL_SHIFT)) & SYSCON_XTAL32K_CTRL_XTAL32K_ICTRL_MASK)
#define SYSCON_XTAL32K_CTRL_XTAL32K_INJ_MASK (0xC0U)
#define SYSCON_XTAL32K_CTRL_XTAL32K_INJ_SHIFT (6U)
#define SYSCON_XTAL32K_CTRL_XTAL32K_INJ(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32K_CTRL_XTAL32K_INJ_SHIFT)) & SYSCON_XTAL32K_CTRL_XTAL32K_INJ_MASK)
#define SYSCON_XTAL32K_CTRL_XTAL32K_LOAD_CAP_MASK (0x3F00U)
#define SYSCON_XTAL32K_CTRL_XTAL32K_LOAD_CAP_SHIFT (8U)
#define SYSCON_XTAL32K_CTRL_XTAL32K_LOAD_CAP(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32K_CTRL_XTAL32K_LOAD_CAP_SHIFT)) & \
SYSCON_XTAL32K_CTRL_XTAL32K_LOAD_CAP_MASK)
#define SYSCON_XTAL32K_CTRL_XTAL32K_EXTRA_CAP_MASK (0x4000U)
#define SYSCON_XTAL32K_CTRL_XTAL32K_EXTRA_CAP_SHIFT (14U)
#define SYSCON_XTAL32K_CTRL_XTAL32K_EXTRA_CAP(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32K_CTRL_XTAL32K_EXTRA_CAP_SHIFT)) & \
SYSCON_XTAL32K_CTRL_XTAL32K_EXTRA_CAP_MASK)
/*! @name USB_CFG - USB configuration register */
#define SYSCON_USB_CFG_DPPUEN_B_PHY_POL_MASK (0x1U)
#define SYSCON_USB_CFG_DPPUEN_B_PHY_POL_SHIFT (0U)
#define SYSCON_USB_CFG_DPPUEN_B_PHY_POL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_USB_CFG_DPPUEN_B_PHY_POL_SHIFT)) & SYSCON_USB_CFG_DPPUEN_B_PHY_POL_MASK)
#define SYSCON_USB_CFG_DPPUEN_B_PHY_SEL_MASK (0x2U)
#define SYSCON_USB_CFG_DPPUEN_B_PHY_SEL_SHIFT (1U)
#define SYSCON_USB_CFG_DPPUEN_B_PHY_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_USB_CFG_DPPUEN_B_PHY_SEL_SHIFT)) & SYSCON_USB_CFG_DPPUEN_B_PHY_SEL_MASK)
#define SYSCON_USB_CFG_USB_VBUS_MASK (0x8U)
#define SYSCON_USB_CFG_USB_VBUS_SHIFT (3U)
#define SYSCON_USB_CFG_USB_VBUS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_USB_CFG_USB_VBUS_SHIFT)) & SYSCON_USB_CFG_USB_VBUS_MASK)
#define SYSCON_USB_CFG_USB_PHYSTDBY_MASK (0x10U)
#define SYSCON_USB_CFG_USB_PHYSTDBY_SHIFT (4U)
#define SYSCON_USB_CFG_USB_PHYSTDBY(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_USB_CFG_USB_PHYSTDBY_SHIFT)) & SYSCON_USB_CFG_USB_PHYSTDBY_MASK)
#define SYSCON_USB_CFG_USB_PHYSTDBY_WEN_MASK (0x20U)
#define SYSCON_USB_CFG_USB_PHYSTDBY_WEN_SHIFT (5U)
#define SYSCON_USB_CFG_USB_PHYSTDBY_WEN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_USB_CFG_USB_PHYSTDBY_WEN_SHIFT)) & SYSCON_USB_CFG_USB_PHYSTDBY_WEN_MASK)
/*! @name PMU_CTRL2 - power management uinit control register 2 */
#define SYSCON_PMU_CTRL2_BG_PDM_DIS_MASK (0x1U)
#define SYSCON_PMU_CTRL2_BG_PDM_DIS_SHIFT (0U)
#define SYSCON_PMU_CTRL2_BG_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_BG_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL2_BG_PDM_DIS_MASK)
#define SYSCON_PMU_CTRL2_V2I_PDM_DIS_MASK (0x2U)
#define SYSCON_PMU_CTRL2_V2I_PDM_DIS_SHIFT (1U)
#define SYSCON_PMU_CTRL2_V2I_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_V2I_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL2_V2I_PDM_DIS_MASK)
#define SYSCON_PMU_CTRL2_VREG_A_PDM_DIS_MASK (0x4U)
#define SYSCON_PMU_CTRL2_VREG_A_PDM_DIS_SHIFT (2U)
#define SYSCON_PMU_CTRL2_VREG_A_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_VREG_A_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL2_VREG_A_PDM_DIS_MASK)
#define SYSCON_PMU_CTRL2_VREG_D_PDM_DIS_MASK (0x8U)
#define SYSCON_PMU_CTRL2_VREG_D_PDM_DIS_SHIFT (3U)
#define SYSCON_PMU_CTRL2_VREG_D_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_VREG_D_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL2_VREG_D_PDM_DIS_MASK)
#define SYSCON_PMU_CTRL2_XTAL_PDM_DIS_MASK (0x10U)
#define SYSCON_PMU_CTRL2_XTAL_PDM_DIS_SHIFT (4U)
#define SYSCON_PMU_CTRL2_XTAL_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_XTAL_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL2_XTAL_PDM_DIS_MASK)
#define SYSCON_PMU_CTRL2_OSC32M_PDM_DIS_MASK (0x20U)
#define SYSCON_PMU_CTRL2_OSC32M_PDM_DIS_SHIFT (5U)
#define SYSCON_PMU_CTRL2_OSC32M_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_OSC32M_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL2_OSC32M_PDM_DIS_MASK)
#define SYSCON_PMU_CTRL2_RFAGC_ON_MASK (0x40U)
#define SYSCON_PMU_CTRL2_RFAGC_ON_SHIFT (6U)
#define SYSCON_PMU_CTRL2_RFAGC_ON(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_RFAGC_ON_SHIFT)) & SYSCON_PMU_CTRL2_RFAGC_ON_MASK)
#define SYSCON_PMU_CTRL2_RX_EN_SEL_MASK (0x80U)
#define SYSCON_PMU_CTRL2_RX_EN_SEL_SHIFT (7U)
#define SYSCON_PMU_CTRL2_RX_EN_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_RX_EN_SEL_SHIFT)) & SYSCON_PMU_CTRL2_RX_EN_SEL_MASK)
#define SYSCON_PMU_CTRL2_BG_DIS_MASK (0x100U)
#define SYSCON_PMU_CTRL2_BG_DIS_SHIFT (8U)
#define SYSCON_PMU_CTRL2_BG_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_BG_DIS_SHIFT)) & SYSCON_PMU_CTRL2_BG_DIS_MASK)
#define SYSCON_PMU_CTRL2_V2I_DIS_MASK (0x200U)
#define SYSCON_PMU_CTRL2_V2I_DIS_SHIFT (9U)
#define SYSCON_PMU_CTRL2_V2I_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_V2I_DIS_SHIFT)) & SYSCON_PMU_CTRL2_V2I_DIS_MASK)
#define SYSCON_PMU_CTRL2_VREG_A_DIS_MASK (0x400U)
#define SYSCON_PMU_CTRL2_VREG_A_DIS_SHIFT (10U)
#define SYSCON_PMU_CTRL2_VREG_A_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_VREG_A_DIS_SHIFT)) & SYSCON_PMU_CTRL2_VREG_A_DIS_MASK)
#define SYSCON_PMU_CTRL2_VREG_D_DIS_MASK (0x800U)
#define SYSCON_PMU_CTRL2_VREG_D_DIS_SHIFT (11U)
#define SYSCON_PMU_CTRL2_VREG_D_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_VREG_D_DIS_SHIFT)) & SYSCON_PMU_CTRL2_VREG_D_DIS_MASK)
#define SYSCON_PMU_CTRL2_LO_DIS_MASK (0x1000U)
#define SYSCON_PMU_CTRL2_LO_DIS_SHIFT (12U)
#define SYSCON_PMU_CTRL2_LO_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_LO_DIS_SHIFT)) & SYSCON_PMU_CTRL2_LO_DIS_MASK)
#define SYSCON_PMU_CTRL2_VCO_DIS_MASK (0x2000U)
#define SYSCON_PMU_CTRL2_VCO_DIS_SHIFT (13U)
#define SYSCON_PMU_CTRL2_VCO_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_VCO_DIS_SHIFT)) & SYSCON_PMU_CTRL2_VCO_DIS_MASK)
#define SYSCON_PMU_CTRL2_PA_PK_DIS_MASK (0x4000U)
#define SYSCON_PMU_CTRL2_PA_PK_DIS_SHIFT (14U)
#define SYSCON_PMU_CTRL2_PA_PK_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_PA_PK_DIS_SHIFT)) & SYSCON_PMU_CTRL2_PA_PK_DIS_MASK)
#define SYSCON_PMU_CTRL2_PA_DIS_MASK (0x8000U)
#define SYSCON_PMU_CTRL2_PA_DIS_SHIFT (15U)
#define SYSCON_PMU_CTRL2_PA_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_PA_DIS_SHIFT)) & SYSCON_PMU_CTRL2_PA_DIS_MASK)
#define SYSCON_PMU_CTRL2_LNA_DIS_MASK (0x10000U)
#define SYSCON_PMU_CTRL2_LNA_DIS_SHIFT (16U)
#define SYSCON_PMU_CTRL2_LNA_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_LNA_DIS_SHIFT)) & SYSCON_PMU_CTRL2_LNA_DIS_MASK)
#define SYSCON_PMU_CTRL2_MIXER_DIS_MASK (0x20000U)
#define SYSCON_PMU_CTRL2_MIXER_DIS_SHIFT (17U)
#define SYSCON_PMU_CTRL2_MIXER_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_MIXER_DIS_SHIFT)) & SYSCON_PMU_CTRL2_MIXER_DIS_MASK)
#define SYSCON_PMU_CTRL2_PKDET_DIS_MASK (0x40000U)
#define SYSCON_PMU_CTRL2_PKDET_DIS_SHIFT (18U)
#define SYSCON_PMU_CTRL2_PKDET_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_PKDET_DIS_SHIFT)) & SYSCON_PMU_CTRL2_PKDET_DIS_MASK)
#define SYSCON_PMU_CTRL2_PPF_DIS_MASK (0x80000U)
#define SYSCON_PMU_CTRL2_PPF_DIS_SHIFT (19U)
#define SYSCON_PMU_CTRL2_PPF_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_PPF_DIS_SHIFT)) & SYSCON_PMU_CTRL2_PPF_DIS_MASK)
#define SYSCON_PMU_CTRL2_SAR_DIS_MASK (0x100000U)
#define SYSCON_PMU_CTRL2_SAR_DIS_SHIFT (20U)
#define SYSCON_PMU_CTRL2_SAR_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_SAR_DIS_SHIFT)) & SYSCON_PMU_CTRL2_SAR_DIS_MASK)
#define SYSCON_PMU_CTRL2_RC_CAL_DIS_MASK (0x200000U)
#define SYSCON_PMU_CTRL2_RC_CAL_DIS_SHIFT (21U)
#define SYSCON_PMU_CTRL2_RC_CAL_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_RC_CAL_DIS_SHIFT)) & SYSCON_PMU_CTRL2_RC_CAL_DIS_MASK)
#define SYSCON_PMU_CTRL2_FLSH_DIS_MASK (0x20000000U)
#define SYSCON_PMU_CTRL2_FLSH_DIS_SHIFT (29U)
#define SYSCON_PMU_CTRL2_FLSH_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_FLSH_DIS_SHIFT)) & SYSCON_PMU_CTRL2_FLSH_DIS_MASK)
#define SYSCON_PMU_CTRL2_FLSH_PDM_DIS_MASK (0x40000000U)
#define SYSCON_PMU_CTRL2_FLSH_PDM_DIS_SHIFT (30U)
#define SYSCON_PMU_CTRL2_FLSH_PDM_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_FLSH_PDM_DIS_SHIFT)) & SYSCON_PMU_CTRL2_FLSH_PDM_DIS_MASK)
#define SYSCON_PMU_CTRL2_SEL_PD_MASK (0x80000000U)
#define SYSCON_PMU_CTRL2_SEL_PD_SHIFT (31U)
#define SYSCON_PMU_CTRL2_SEL_PD(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_PMU_CTRL2_SEL_PD_SHIFT)) & SYSCON_PMU_CTRL2_SEL_PD_MASK)
/*! @name ANA_CTRL1 - IVREF and DVREG setting register */
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_PDM_MASK (0x3U)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_PDM_SHIFT (0U)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_PDM(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_VDD_PMU_SET_PDM_SHIFT)) & SYSCON_ANA_CTRL1_VDD_PMU_SET_PDM_MASK)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_MASK (0xCU)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_SHIFT (2U)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_VDD_PMU_SET_SHIFT)) & SYSCON_ANA_CTRL1_VDD_PMU_SET_MASK)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET_PDM_MASK (0x30U)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET_PDM_SHIFT (4U)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET_PDM(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_VDD_MEM_SET_PDM_SHIFT)) & SYSCON_ANA_CTRL1_VDD_MEM_SET_PDM_MASK)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET_MASK (0xC0U)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET_SHIFT (6U)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_VDD_MEM_SET_SHIFT)) & SYSCON_ANA_CTRL1_VDD_MEM_SET_MASK)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_EXTRA_MASK (0x100U)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_EXTRA_SHIFT (8U)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_EXTRA(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_VDD_PMU_SET_EXTRA_SHIFT)) & \
SYSCON_ANA_CTRL1_VDD_PMU_SET_EXTRA_MASK)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET_EXTRA_MASK (0x200U)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET_EXTRA_SHIFT (9U)
#define SYSCON_ANA_CTRL1_VDD_MEM_SET_EXTRA(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_VDD_MEM_SET_EXTRA_SHIFT)) & \
SYSCON_ANA_CTRL1_VDD_MEM_SET_EXTRA_MASK)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_ULTRA_LOW_MASK (0x400U)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_ULTRA_LOW_SHIFT (10U)
#define SYSCON_ANA_CTRL1_VDD_PMU_SET_ULTRA_LOW(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_VDD_PMU_SET_ULTRA_LOW_SHIFT)) & \
SYSCON_ANA_CTRL1_VDD_PMU_SET_ULTRA_LOW_MASK)
#define SYSCON_ANA_CTRL1_VDD_PMU_MEM_SW_MASK (0x800U)
#define SYSCON_ANA_CTRL1_VDD_PMU_MEM_SW_SHIFT (11U)
#define SYSCON_ANA_CTRL1_VDD_PMU_MEM_SW(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_VDD_PMU_MEM_SW_SHIFT)) & SYSCON_ANA_CTRL1_VDD_PMU_MEM_SW_MASK)
#define SYSCON_ANA_CTRL1_IV_BG_SEL_MASK (0xF000U)
#define SYSCON_ANA_CTRL1_IV_BG_SEL_SHIFT (12U)
#define SYSCON_ANA_CTRL1_IV_BG_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_IV_BG_SEL_SHIFT)) & SYSCON_ANA_CTRL1_IV_BG_SEL_MASK)
#define SYSCON_ANA_CTRL1_PDM_DIS_BUCK_MASK (0x10000U)
#define SYSCON_ANA_CTRL1_PDM_DIS_BUCK_SHIFT (16U)
#define SYSCON_ANA_CTRL1_PDM_DIS_BUCK(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_PDM_DIS_BUCK_SHIFT)) & SYSCON_ANA_CTRL1_PDM_DIS_BUCK_MASK)
#define SYSCON_ANA_CTRL1_BUCK_PD_CCM_MASK (0x20000U)
#define SYSCON_ANA_CTRL1_BUCK_PD_CCM_SHIFT (17U)
#define SYSCON_ANA_CTRL1_BUCK_PD_CCM(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_BUCK_PD_CCM_SHIFT)) & SYSCON_ANA_CTRL1_BUCK_PD_CCM_MASK)
#define SYSCON_ANA_CTRL1_BUCK_PD_DCM_MASK (0x40000U)
#define SYSCON_ANA_CTRL1_BUCK_PD_DCM_SHIFT (18U)
#define SYSCON_ANA_CTRL1_BUCK_PD_DCM(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_BUCK_PD_DCM_SHIFT)) & SYSCON_ANA_CTRL1_BUCK_PD_DCM_MASK)
#define SYSCON_ANA_CTRL1_IV_IREF_SEL_MASK (0x180000U)
#define SYSCON_ANA_CTRL1_IV_IREF_SEL_SHIFT (19U)
#define SYSCON_ANA_CTRL1_IV_IREF_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_IV_IREF_SEL_SHIFT)) & SYSCON_ANA_CTRL1_IV_IREF_SEL_MASK)
#define SYSCON_ANA_CTRL1_IV_VREG11_SET_MASK (0xE00000U)
#define SYSCON_ANA_CTRL1_IV_VREG11_SET_SHIFT (21U)
#define SYSCON_ANA_CTRL1_IV_VREG11_SET(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_IV_VREG11_SET_SHIFT)) & SYSCON_ANA_CTRL1_IV_VREG11_SET_MASK)
#define SYSCON_ANA_CTRL1_XTAL32K_FORCE_RDY_MASK (0x1000000U)
#define SYSCON_ANA_CTRL1_XTAL32K_FORCE_RDY_SHIFT (24U)
#define SYSCON_ANA_CTRL1_XTAL32K_FORCE_RDY(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_XTAL32K_FORCE_RDY_SHIFT)) & \
SYSCON_ANA_CTRL1_XTAL32K_FORCE_RDY_MASK)
#define SYSCON_ANA_CTRL1_X32_SMT_EN_MASK (0x2000000U)
#define SYSCON_ANA_CTRL1_X32_SMT_EN_SHIFT (25U)
#define SYSCON_ANA_CTRL1_X32_SMT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_X32_SMT_EN_SHIFT)) & SYSCON_ANA_CTRL1_X32_SMT_EN_MASK)
#define SYSCON_ANA_CTRL1_BM_X32BUF_MASK (0xC000000U)
#define SYSCON_ANA_CTRL1_BM_X32BUF_SHIFT (26U)
#define SYSCON_ANA_CTRL1_BM_X32BUF(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_BM_X32BUF_SHIFT)) & SYSCON_ANA_CTRL1_BM_X32BUF_MASK)
#define SYSCON_ANA_CTRL1_DVREG11_SET_DIG_MASK (0x70000000U)
#define SYSCON_ANA_CTRL1_DVREG11_SET_DIG_SHIFT (28U)
#define SYSCON_ANA_CTRL1_DVREG11_SET_DIG(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_DVREG11_SET_DIG_SHIFT)) & SYSCON_ANA_CTRL1_DVREG11_SET_DIG_MASK)
#define SYSCON_ANA_CTRL1_BUCK_DPD_MASK (0x80000000U)
#define SYSCON_ANA_CTRL1_BUCK_DPD_SHIFT (31U)
#define SYSCON_ANA_CTRL1_BUCK_DPD(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_ANA_CTRL1_BUCK_DPD_SHIFT)) & SYSCON_ANA_CTRL1_BUCK_DPD_MASK)
/*! @name MISC - MISC register */
#define SYSCON_MISC_RCO_PWR_MODE_MASK (0x3U)
#define SYSCON_MISC_RCO_PWR_MODE_SHIFT (0U)
#define SYSCON_MISC_RCO_PWR_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_MISC_RCO_PWR_MODE_SHIFT)) & SYSCON_MISC_RCO_PWR_MODE_MASK)
#define SYSCON_MISC_EN_SWD_MASK (0x10000U)
#define SYSCON_MISC_EN_SWD_SHIFT (16U)
#define SYSCON_MISC_EN_SWD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MISC_EN_SWD_SHIFT)) & SYSCON_MISC_EN_SWD_MASK)
#define SYSCON_MISC_DIS_FLSH_POWER_MASK (0x20000U)
#define SYSCON_MISC_DIS_FLSH_POWER_SHIFT (17U)
#define SYSCON_MISC_DIS_FLSH_POWER(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_MISC_DIS_FLSH_POWER_SHIFT)) & SYSCON_MISC_DIS_FLSH_POWER_MASK)
#define SYSCON_MISC_DIS_USB_PULLUP_MASK (0x40000U)
#define SYSCON_MISC_DIS_USB_PULLUP_SHIFT (18U)
#define SYSCON_MISC_DIS_USB_PULLUP(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_MISC_DIS_USB_PULLUP_SHIFT)) & SYSCON_MISC_DIS_USB_PULLUP_MASK)
#define SYSCON_MISC_DPPU_OPT_SEL_MASK (0x1000000U)
#define SYSCON_MISC_DPPU_OPT_SEL_SHIFT (24U)
#define SYSCON_MISC_DPPU_OPT_SEL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_MISC_DPPU_OPT_SEL_SHIFT)) & SYSCON_MISC_DPPU_OPT_SEL_MASK)
#define SYSCON_MISC_DPPU_OPT_POL_MASK (0x2000000U)
#define SYSCON_MISC_DPPU_OPT_POL_SHIFT (25U)
#define SYSCON_MISC_DPPU_OPT_POL(x) \
(((uint32_t)(((uint32_t)(x)) << SYSCON_MISC_DPPU_OPT_POL_SHIFT)) & SYSCON_MISC_DPPU_OPT_POL_MASK)
/*!
* @}
*/ /* end of group SYSCON_Register_Masks */
/* SYSCON - Peripheral instance base addresses */
/** Peripheral SYSCON base address */
#define SYSCON_BASE (0x40000000u)
/** Peripheral SYSCON base pointer */
#define SYSCON ((SYSCON_Type *)SYSCON_BASE)
/** Array initializer of SYSCON peripheral base addresses */
#define SYSCON_BASE_ADDRS \
{ \
SYSCON_BASE \
}
/** Array initializer of SYSCON peripheral base pointers */
#define SYSCON_BASE_PTRS \
{ \
SYSCON \
}
/** Interrupt vectors for the SYSCON peripheral type */
#define SYSCON_IRQS \
{ \
EXT_GPIO_WAKEUP_IRQn, ACMP0_IRQn, ACMP1_IRQn, XTAL_READY_IRQn, OSC_IRQn, OSC_INT_LOW_IRQn, BOD_IRQn \
}
/*!
* @}
*/ /* end of group SYSCON_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
* @{
*/
/** USART - Register Layout Typedef */
typedef struct
{
__IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not
changed during operation., offset: 0x0 */
__IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during
operation., offset: 0x4 */
__IO uint32_t
STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in
the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
__IO
uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual
interrupt enable bits for each potential USART interrupt. A complete value may be read
from this register. Writing a 1 to any implemented bit position causes that bit to be
set., offset: 0xC */
__O
uint32_t
INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET
register. Writing a 1 to any implemented bit position causes the corresponding bit to be
cleared., offset: 0x10 */
uint8_t RESERVED_0[12];
__IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
__I uint32_t
INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
__IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */
__IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */
uint8_t RESERVED_1[3536];
__IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
__IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
__IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
uint8_t RESERVED_2[4];
__IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
__IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
__I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
uint8_t RESERVED_3[4];
__IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
uint8_t RESERVED_4[12];
__I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
uint8_t RESERVED_5[12];
__I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
uint8_t RESERVED_6[440];
__I uint32_t
ID; /**< USART module Identification. This value appears in the shared Flexcomm peripheral ID register when
USART is selected., offset: 0xFFC */
} USART_Type;
/* ----------------------------------------------------------------------------
-- USART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USART_Register_Masks USART Register Masks
* @{
*/
/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during
* operation. */
#define USART_CFG_ENABLE_MASK (0x1U)
#define USART_CFG_ENABLE_SHIFT (0U)
#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
#define USART_CFG_DATALEN_MASK (0xCU)
#define USART_CFG_DATALEN_SHIFT (2U)
#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
#define USART_CFG_PARITYSEL_MASK (0x30U)
#define USART_CFG_PARITYSEL_SHIFT (4U)
#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
#define USART_CFG_STOPLEN_MASK (0x40U)
#define USART_CFG_STOPLEN_SHIFT (6U)
#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
#define USART_CFG_MODE32K_MASK (0x80U)
#define USART_CFG_MODE32K_SHIFT (7U)
#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
#define USART_CFG_LINMODE_MASK (0x100U)
#define USART_CFG_LINMODE_SHIFT (8U)
#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
#define USART_CFG_CTSEN_MASK (0x200U)
#define USART_CFG_CTSEN_SHIFT (9U)
#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
#define USART_CFG_SYNCEN_MASK (0x800U)
#define USART_CFG_SYNCEN_SHIFT (11U)
#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
#define USART_CFG_CLKPOL_MASK (0x1000U)
#define USART_CFG_CLKPOL_SHIFT (12U)
#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
#define USART_CFG_SYNCMST_MASK (0x4000U)
#define USART_CFG_SYNCMST_SHIFT (14U)
#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
#define USART_CFG_LOOP_MASK (0x8000U)
#define USART_CFG_LOOP_SHIFT (15U)
#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
#define USART_CFG_OETA_MASK (0x40000U)
#define USART_CFG_OETA_SHIFT (18U)
#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
#define USART_CFG_AUTOADDR_MASK (0x80000U)
#define USART_CFG_AUTOADDR_SHIFT (19U)
#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
#define USART_CFG_OESEL_MASK (0x100000U)
#define USART_CFG_OESEL_SHIFT (20U)
#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
#define USART_CFG_OEPOL_MASK (0x200000U)
#define USART_CFG_OEPOL_SHIFT (21U)
#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
#define USART_CFG_RXPOL_MASK (0x400000U)
#define USART_CFG_RXPOL_SHIFT (22U)
#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
#define USART_CFG_TXPOL_MASK (0x800000U)
#define USART_CFG_TXPOL_SHIFT (23U)
#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
#define USART_CTL_TXBRKEN_MASK (0x2U)
#define USART_CTL_TXBRKEN_SHIFT (1U)
#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
#define USART_CTL_ADDRDET_MASK (0x4U)
#define USART_CTL_ADDRDET_SHIFT (2U)
#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
#define USART_CTL_TXDIS_MASK (0x40U)
#define USART_CTL_TXDIS_SHIFT (6U)
#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
#define USART_CTL_CC_MASK (0x100U)
#define USART_CTL_CC_SHIFT (8U)
#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
#define USART_CTL_CLRCCONRX_MASK (0x200U)
#define USART_CTL_CLRCCONRX_SHIFT (9U)
#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
#define USART_CTL_AUTOBAUD_MASK (0x10000U)
#define USART_CTL_AUTOBAUD_SHIFT (16U)
#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the
* register. Some bits can be cleared by writing a 1 to them. */
#define USART_STAT_RXIDLE_MASK (0x2U)
#define USART_STAT_RXIDLE_SHIFT (1U)
#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
#define USART_STAT_TXIDLE_MASK (0x8U)
#define USART_STAT_TXIDLE_SHIFT (3U)
#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
#define USART_STAT_CTS_MASK (0x10U)
#define USART_STAT_CTS_SHIFT (4U)
#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
#define USART_STAT_DELTACTS_MASK (0x20U)
#define USART_STAT_DELTACTS_SHIFT (5U)
#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
#define USART_STAT_TXDISSTAT_MASK (0x40U)
#define USART_STAT_TXDISSTAT_SHIFT (6U)
#define USART_STAT_TXDISSTAT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
#define USART_STAT_RXBRK_MASK (0x400U)
#define USART_STAT_RXBRK_SHIFT (10U)
#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
#define USART_STAT_DELTARXBRK_MASK (0x800U)
#define USART_STAT_DELTARXBRK_SHIFT (11U)
#define USART_STAT_DELTARXBRK(x) \
(((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
#define USART_STAT_START_MASK (0x1000U)
#define USART_STAT_START_SHIFT (12U)
#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
#define USART_STAT_FRAMERRINT_MASK (0x2000U)
#define USART_STAT_FRAMERRINT_SHIFT (13U)
#define USART_STAT_FRAMERRINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
#define USART_STAT_PARITYERRINT_MASK (0x4000U)
#define USART_STAT_PARITYERRINT_SHIFT (14U)
#define USART_STAT_PARITYERRINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
#define USART_STAT_RXNOISEINT_MASK (0x8000U)
#define USART_STAT_RXNOISEINT_SHIFT (15U)
#define USART_STAT_RXNOISEINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
#define USART_STAT_ABERR_MASK (0x10000U)
#define USART_STAT_ABERR_SHIFT (16U)
#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt
* enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any
* implemented bit position causes that bit to be set. */
#define USART_INTENSET_TXIDLEEN_MASK (0x8U)
#define USART_INTENSET_TXIDLEEN_SHIFT (3U)
#define USART_INTENSET_TXIDLEEN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
#define USART_INTENSET_DELTACTSEN_MASK (0x20U)
#define USART_INTENSET_DELTACTSEN_SHIFT (5U)
#define USART_INTENSET_DELTACTSEN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
#define USART_INTENSET_TXDISEN_MASK (0x40U)
#define USART_INTENSET_TXDISEN_SHIFT (6U)
#define USART_INTENSET_TXDISEN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
#define USART_INTENSET_DELTARXBRKEN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
#define USART_INTENSET_STARTEN_MASK (0x1000U)
#define USART_INTENSET_STARTEN_SHIFT (12U)
#define USART_INTENSET_STARTEN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
#define USART_INTENSET_FRAMERREN_MASK (0x2000U)
#define USART_INTENSET_FRAMERREN_SHIFT (13U)
#define USART_INTENSET_FRAMERREN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
#define USART_INTENSET_PARITYERREN_MASK (0x4000U)
#define USART_INTENSET_PARITYERREN_SHIFT (14U)
#define USART_INTENSET_PARITYERREN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
#define USART_INTENSET_RXNOISEEN_SHIFT (15U)
#define USART_INTENSET_RXNOISEEN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
#define USART_INTENSET_ABERREN_MASK (0x10000U)
#define USART_INTENSET_ABERREN_SHIFT (16U)
#define USART_INTENSET_ABERREN(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register.
* Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
#define USART_INTENCLR_TXIDLECLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
#define USART_INTENCLR_DELTACTSCLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
#define USART_INTENCLR_TXDISCLR_MASK (0x40U)
#define USART_INTENCLR_TXDISCLR_SHIFT (6U)
#define USART_INTENCLR_TXDISCLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
#define USART_INTENCLR_DELTARXBRKCLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
#define USART_INTENCLR_STARTCLR_MASK (0x1000U)
#define USART_INTENCLR_STARTCLR_SHIFT (12U)
#define USART_INTENCLR_STARTCLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
#define USART_INTENCLR_FRAMERRCLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
#define USART_INTENCLR_PARITYERRCLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
#define USART_INTENCLR_RXNOISECLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
#define USART_INTENCLR_ABERRCLR_SHIFT (16U)
#define USART_INTENCLR_ABERRCLR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
#define USART_BRG_BRGVAL_MASK (0xFFFFU)
#define USART_BRG_BRGVAL_SHIFT (0U)
#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
#define USART_INTSTAT_TXIDLE_MASK (0x8U)
#define USART_INTSTAT_TXIDLE_SHIFT (3U)
#define USART_INTSTAT_TXIDLE(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
#define USART_INTSTAT_DELTACTS_MASK (0x20U)
#define USART_INTSTAT_DELTACTS_SHIFT (5U)
#define USART_INTSTAT_DELTACTS(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
#define USART_INTSTAT_TXDISINT_MASK (0x40U)
#define USART_INTSTAT_TXDISINT_SHIFT (6U)
#define USART_INTSTAT_TXDISINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
#define USART_INTSTAT_DELTARXBRK(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
#define USART_INTSTAT_START_MASK (0x1000U)
#define USART_INTSTAT_START_SHIFT (12U)
#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
#define USART_INTSTAT_FRAMERRINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
#define USART_INTSTAT_PARITYERRINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
#define USART_INTSTAT_RXNOISEINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
#define USART_INTSTAT_ABERRINT_MASK (0x10000U)
#define USART_INTSTAT_ABERRINT_SHIFT (16U)
#define USART_INTSTAT_ABERRINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
/*! @name OSR - Oversample selection register for asynchronous communication. */
#define USART_OSR_OSRVAL_MASK (0xFU)
#define USART_OSR_OSRVAL_SHIFT (0U)
#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
/*! @name ADDR - Address register for automatic address matching. */
#define USART_ADDR_ADDRESS_MASK (0xFFU)
#define USART_ADDR_ADDRESS_SHIFT (0U)
#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
/*! @name FIFOCFG - FIFO configuration and enable register. */
#define USART_FIFOCFG_ENABLETX_MASK (0x1U)
#define USART_FIFOCFG_ENABLETX_SHIFT (0U)
#define USART_FIFOCFG_ENABLETX(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
#define USART_FIFOCFG_ENABLERX_MASK (0x2U)
#define USART_FIFOCFG_ENABLERX_SHIFT (1U)
#define USART_FIFOCFG_ENABLERX(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
#define USART_FIFOCFG_SIZE_MASK (0x30U)
#define USART_FIFOCFG_SIZE_SHIFT (4U)
#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
#define USART_FIFOCFG_DMATX_MASK (0x1000U)
#define USART_FIFOCFG_DMATX_SHIFT (12U)
#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
#define USART_FIFOCFG_DMARX_MASK (0x2000U)
#define USART_FIFOCFG_DMARX_SHIFT (13U)
#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
#define USART_FIFOCFG_EMPTYTX(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
#define USART_FIFOCFG_EMPTYRX(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
/*! @name FIFOSTAT - FIFO status register. */
#define USART_FIFOSTAT_TXERR_MASK (0x1U)
#define USART_FIFOSTAT_TXERR_SHIFT (0U)
#define USART_FIFOSTAT_TXERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
#define USART_FIFOSTAT_RXERR_MASK (0x2U)
#define USART_FIFOSTAT_RXERR_SHIFT (1U)
#define USART_FIFOSTAT_RXERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
#define USART_FIFOSTAT_PERINT_MASK (0x8U)
#define USART_FIFOSTAT_PERINT_SHIFT (3U)
#define USART_FIFOSTAT_PERINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
#define USART_FIFOSTAT_TXEMPTY(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
#define USART_FIFOSTAT_TXNOTFULL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
#define USART_FIFOSTAT_RXNOTEMPTY(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
#define USART_FIFOSTAT_RXFULL_MASK (0x80U)
#define USART_FIFOSTAT_RXFULL_SHIFT (7U)
#define USART_FIFOSTAT_RXFULL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
#define USART_FIFOSTAT_TXLVL_SHIFT (8U)
#define USART_FIFOSTAT_TXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
#define USART_FIFOSTAT_RXLVL_SHIFT (16U)
#define USART_FIFOSTAT_RXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
#define USART_FIFOTRIG_TXLVLENA(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
#define USART_FIFOTRIG_RXLVLENA(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
#define USART_FIFOTRIG_TXLVL_SHIFT (8U)
#define USART_FIFOTRIG_TXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
#define USART_FIFOTRIG_RXLVL_SHIFT (16U)
#define USART_FIFOTRIG_RXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
#define USART_FIFOINTENSET_TXERR_MASK (0x1U)
#define USART_FIFOINTENSET_TXERR_SHIFT (0U)
#define USART_FIFOINTENSET_TXERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
#define USART_FIFOINTENSET_RXERR_MASK (0x2U)
#define USART_FIFOINTENSET_RXERR_SHIFT (1U)
#define USART_FIFOINTENSET_RXERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
#define USART_FIFOINTENSET_TXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
#define USART_FIFOINTENSET_RXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
#define USART_FIFOINTENCLR_TXERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
#define USART_FIFOINTENCLR_RXERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
#define USART_FIFOINTENCLR_TXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
#define USART_FIFOINTENCLR_RXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
/*! @name FIFOINTSTAT - FIFO interrupt status register. */
#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
#define USART_FIFOINTSTAT_TXERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
#define USART_FIFOINTSTAT_RXERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
#define USART_FIFOINTSTAT_TXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
#define USART_FIFOINTSTAT_RXLVL(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
#define USART_FIFOINTSTAT_PERINT(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
/*! @name FIFOWR - FIFO write data. */
#define USART_FIFOWR_TXDATA_MASK (0x1FFU)
#define USART_FIFOWR_TXDATA_SHIFT (0U)
#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
/*! @name FIFORD - FIFO read data. */
#define USART_FIFORD_RXDATA_MASK (0x1FFU)
#define USART_FIFORD_RXDATA_SHIFT (0U)
#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
#define USART_FIFORD_FRAMERR_MASK (0x2000U)
#define USART_FIFORD_FRAMERR_SHIFT (13U)
#define USART_FIFORD_FRAMERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
#define USART_FIFORD_PARITYERR_MASK (0x4000U)
#define USART_FIFORD_PARITYERR_SHIFT (14U)
#define USART_FIFORD_PARITYERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
#define USART_FIFORD_RXNOISE_MASK (0x8000U)
#define USART_FIFORD_RXNOISE_SHIFT (15U)
#define USART_FIFORD_RXNOISE(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
#define USART_FIFORDNOPOP_RXDATA(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
#define USART_FIFORDNOPOP_FRAMERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
#define USART_FIFORDNOPOP_PARITYERR(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
#define USART_FIFORDNOPOP_RXNOISE(x) \
(((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
/*! @name ID - USART module Identification. This value appears in the shared Flexcomm peripheral ID register when USART
* is selected. */
#define USART_ID_APERTURE_MASK (0xFFU)
#define USART_ID_APERTURE_SHIFT (0U)
#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
#define USART_ID_MINOR_REV_MASK (0xF00U)
#define USART_ID_MINOR_REV_SHIFT (8U)
#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
#define USART_ID_MAJOR_REV_MASK (0xF000U)
#define USART_ID_MAJOR_REV_SHIFT (12U)
#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
#define USART_ID_ID_MASK (0xFFFF0000U)
#define USART_ID_ID_SHIFT (16U)
#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
/*!
* @}
*/ /* end of group USART_Register_Masks */
/* USART - Peripheral instance base addresses */
/** Peripheral USART0 base address */
#define USART0_BASE (0x40083000u)
/** Peripheral USART0 base pointer */
#define USART0 ((USART_Type *)USART0_BASE)
/** Peripheral USART1 base address */
#define USART1_BASE (0x40086000u)
/** Peripheral USART1 base pointer */
#define USART1 ((USART_Type *)USART1_BASE)
/** Array initializer of USART peripheral base addresses */
#define USART_BASE_ADDRS \
{ \
USART0_BASE, USART1_BASE \
}
/** Array initializer of USART peripheral base pointers */
#define USART_BASE_PTRS \
{ \
USART0, USART1 \
}
/** Interrupt vectors for the USART peripheral type */
#define USART_IRQS \
{ \
FLEXCOMM0_IRQn, FLEXCOMM1_IRQn \
}
/*!
* @}
*/ /* end of group USART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
* @{
*/
/** USB - Register Layout Typedef */
typedef struct
{
__IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
__IO uint32_t INFO; /**< USB Info register, offset: 0x4 */
__IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
__IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
__IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
__IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
__IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
__IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
__IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
__IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
__IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
uint8_t RESERVED_0[8];
__I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
} USB_Type;
/* ----------------------------------------------------------------------------
-- USB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
/*! @name DEVCMDSTAT - USB Device Command/Status register */
#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
#define USB_DEVCMDSTAT_DEV_ADDR(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)
#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)
#define USB_DEVCMDSTAT_DEV_EN(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
#define USB_DEVCMDSTAT_SETUP_MASK (0x100U)
#define USB_DEVCMDSTAT_SETUP_SHIFT (8U)
#define USB_DEVCMDSTAT_SETUP(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
#define USB_DEVCMDSTAT_LPM_SUP(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
#define USB_DEVCMDSTAT_INTONNAK_AO(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
#define USB_DEVCMDSTAT_INTONNAK_AI(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
#define USB_DEVCMDSTAT_INTONNAK_CO(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
#define USB_DEVCMDSTAT_INTONNAK_CI(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
#define USB_DEVCMDSTAT_DCON_MASK (0x10000U)
#define USB_DEVCMDSTAT_DCON_SHIFT (16U)
#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)
#define USB_DEVCMDSTAT_DSUS_SHIFT (17U)
#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
#define USB_DEVCMDSTAT_LPM_SUS(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
#define USB_DEVCMDSTAT_LPM_REWP(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)
#define USB_DEVCMDSTAT_DCON_C(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)
#define USB_DEVCMDSTAT_DSUS_C(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)
#define USB_DEVCMDSTAT_DRES_C(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)
#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)
#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
/*! @name INFO - USB Info register */
#define USB_INFO_FRAME_NR_MASK (0x7FFU)
#define USB_INFO_FRAME_NR_SHIFT (0U)
#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
#define USB_INFO_ERR_CODE_MASK (0x7800U)
#define USB_INFO_ERR_CODE_SHIFT (11U)
#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
/*! @name EPLISTSTART - USB EP Command/Status List start address */
#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)
#define USB_EPLISTSTART_EP_LIST_SHIFT (8U)
#define USB_EPLISTSTART_EP_LIST(x) \
(((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
/*! @name DATABUFSTART - USB Data buffer start address */
#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)
#define USB_DATABUFSTART_DA_BUF_SHIFT (22U)
#define USB_DATABUFSTART_DA_BUF(x) \
(((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
/*! @name LPM - USB Link Power Management register */
#define USB_LPM_HIRD_HW_MASK (0xFU)
#define USB_LPM_HIRD_HW_SHIFT (0U)
#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
#define USB_LPM_HIRD_SW_MASK (0xF0U)
#define USB_LPM_HIRD_SW_SHIFT (4U)
#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
#define USB_LPM_DATA_PENDING_MASK (0x100U)
#define USB_LPM_DATA_PENDING_SHIFT (8U)
#define USB_LPM_DATA_PENDING(x) \
(((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
/*! @name EPSKIP - USB Endpoint skip */
#define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU)
#define USB_EPSKIP_SKIP_SHIFT (0U)
#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
/*! @name EPINUSE - USB Endpoint Buffer in use */
#define USB_EPINUSE_BUF_MASK (0x3FCU)
#define USB_EPINUSE_BUF_SHIFT (2U)
#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)
#define USB_EPBUFCFG_BUF_SB_SHIFT (2U)
#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
/*! @name INTSTAT - USB interrupt status register */
#define USB_INTSTAT_EP0OUT_MASK (0x1U)
#define USB_INTSTAT_EP0OUT_SHIFT (0U)
#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
#define USB_INTSTAT_EP0IN_MASK (0x2U)
#define USB_INTSTAT_EP0IN_SHIFT (1U)
#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
#define USB_INTSTAT_EP1OUT_MASK (0x4U)
#define USB_INTSTAT_EP1OUT_SHIFT (2U)
#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
#define USB_INTSTAT_EP1IN_MASK (0x8U)
#define USB_INTSTAT_EP1IN_SHIFT (3U)
#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
#define USB_INTSTAT_EP2OUT_MASK (0x10U)
#define USB_INTSTAT_EP2OUT_SHIFT (4U)
#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
#define USB_INTSTAT_EP2IN_MASK (0x20U)
#define USB_INTSTAT_EP2IN_SHIFT (5U)
#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
#define USB_INTSTAT_EP3OUT_MASK (0x40U)
#define USB_INTSTAT_EP3OUT_SHIFT (6U)
#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
#define USB_INTSTAT_EP3IN_MASK (0x80U)
#define USB_INTSTAT_EP3IN_SHIFT (7U)
#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
#define USB_INTSTAT_EP4OUT_MASK (0x100U)
#define USB_INTSTAT_EP4OUT_SHIFT (8U)
#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
#define USB_INTSTAT_EP4IN_MASK (0x200U)
#define USB_INTSTAT_EP4IN_SHIFT (9U)
#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
#define USB_INTSTAT_EP5OUT_MASK (0x400U)
#define USB_INTSTAT_EP5OUT_SHIFT (10U)
#define USB_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP5OUT_SHIFT)) & USB_INTSTAT_EP5OUT_MASK)
#define USB_INTSTAT_EP5IN_MASK (0x800U)
#define USB_INTSTAT_EP5IN_SHIFT (11U)
#define USB_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP5IN_SHIFT)) & USB_INTSTAT_EP5IN_MASK)
#define USB_INTSTAT_EP6OUT_MASK (0x1000U)
#define USB_INTSTAT_EP6OUT_SHIFT (12U)
#define USB_INTSTAT_EP6OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP6OUT_SHIFT)) & USB_INTSTAT_EP6OUT_MASK)
#define USB_INTSTAT_EP6IN_MASK (0x2000U)
#define USB_INTSTAT_EP6IN_SHIFT (13U)
#define USB_INTSTAT_EP6IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP6IN_SHIFT)) & USB_INTSTAT_EP6IN_MASK)
#define USB_INTSTAT_EP7OUT_MASK (0x4000U)
#define USB_INTSTAT_EP7OUT_SHIFT (14U)
#define USB_INTSTAT_EP7OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP7OUT_SHIFT)) & USB_INTSTAT_EP7OUT_MASK)
#define USB_INTSTAT_EP7IN_MASK (0x8000U)
#define USB_INTSTAT_EP7IN_SHIFT (15U)
#define USB_INTSTAT_EP7IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP7IN_SHIFT)) & USB_INTSTAT_EP7IN_MASK)
#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)
#define USB_INTSTAT_FRAME_INT_SHIFT (30U)
#define USB_INTSTAT_FRAME_INT(x) \
(((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
#define USB_INTSTAT_DEV_INT_MASK (0x80000000U)
#define USB_INTSTAT_DEV_INT_SHIFT (31U)
#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
/*! @name INTEN - USB interrupt enable register */
#define USB_INTEN_EP_INT_EN_MASK (0xFFFFU)
#define USB_INTEN_EP_INT_EN_SHIFT (0U)
#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)
#define USB_INTEN_FRAME_INT_EN_SHIFT (30U)
#define USB_INTEN_FRAME_INT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)
#define USB_INTEN_DEV_INT_EN_SHIFT (31U)
#define USB_INTEN_DEV_INT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
/*! @name INTSETSTAT - USB set interrupt status register */
#define USB_INTSETSTAT_EP_SET_INT_MASK (0xFFFFU)
#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)
#define USB_INTSETSTAT_EP_SET_INT(x) \
(((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
#define USB_INTSETSTAT_FRAME_SET_INT(x) \
(((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
#define USB_INTSETSTAT_DEV_SET_INT(x) \
(((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
/*! @name EPTOGGLE - USB Endpoint toggle register */
#define USB_EPTOGGLE_TOGGLE_MASK (0xFFFFU)
#define USB_EPTOGGLE_TOGGLE_SHIFT (0U)
#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
/*!
* @}
*/ /* end of group USB_Register_Masks */
/* USB - Peripheral instance base addresses */
/** Peripheral USB0 base address */
#define USB0_BASE (0x40084000u)
/** Peripheral USB0 base pointer */
#define USB0 ((USB_Type *)USB0_BASE)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS \
{ \
USB0_BASE \
}
/** Array initializer of USB peripheral base pointers */
#define USB_BASE_PTRS \
{ \
USB0 \
}
/** Interrupt vectors for the USB peripheral type */
#define USB_IRQS \
{ \
USB0_IRQn \
}
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- WDT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDT_Peripheral_Access_Layer WDT Peripheral Access Layer
* @{
*/
/** WDT - Register Layout Typedef */
typedef struct
{
__IO uint32_t LOAD; /**< watch dog counter start value register, offset: 0x0 */
__IO uint32_t VALUE; /**< watch dog counter value register, offset: 0x4 */
__IO uint32_t CTRL; /**< watch dog control register, offset: 0x8 */
__IO uint32_t INT_CLR; /**< interrupt clear register, offset: 0xC */
__I uint32_t INT_RAW; /**< raw interrupt status register, offset: 0x10 */
__IO uint32_t MIS; /**< interrupt mask register, offset: 0x14 */
uint8_t RESERVED_0[8];
__IO uint32_t LOCK; /**< watch dog lock register, offset: 0x20 */
uint8_t RESERVED_1[28];
__IO uint32_t ITCR; /**< integrated test control register, offset: 0x40 */
__IO uint32_t ITOP; /**< integrated test output set register, offset: 0x44 */
} WDT_Type;
/* ----------------------------------------------------------------------------
-- WDT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDT_Register_Masks WDT Register Masks
* @{
*/
/*! @name LOAD - watch dog counter start value register */
#define WDT_LOAD_LOAD_MASK (0xFFFFFFFFU)
#define WDT_LOAD_LOAD_SHIFT (0U)
#define WDT_LOAD_LOAD(x) (((uint32_t)(((uint32_t)(x)) << WDT_LOAD_LOAD_SHIFT)) & WDT_LOAD_LOAD_MASK)
/*! @name VALUE - watch dog counter value register */
#define WDT_VALUE_VALUE_MASK (0xFFFFFFFFU)
#define WDT_VALUE_VALUE_SHIFT (0U)
#define WDT_VALUE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << WDT_VALUE_VALUE_SHIFT)) & WDT_VALUE_VALUE_MASK)
/*! @name CTRL - watch dog control register */
#define WDT_CTRL_INTEN_MASK (0x1U)
#define WDT_CTRL_INTEN_SHIFT (0U)
#define WDT_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << WDT_CTRL_INTEN_SHIFT)) & WDT_CTRL_INTEN_MASK)
#define WDT_CTRL_RESEN_MASK (0x2U)
#define WDT_CTRL_RESEN_SHIFT (1U)
#define WDT_CTRL_RESEN(x) (((uint32_t)(((uint32_t)(x)) << WDT_CTRL_RESEN_SHIFT)) & WDT_CTRL_RESEN_MASK)
/*! @name INT_CLR - interrupt clear register */
#define WDT_INT_CLR_INTCLR_MASK (0x1U)
#define WDT_INT_CLR_INTCLR_SHIFT (0U)
#define WDT_INT_CLR_INTCLR(x) (((uint32_t)(((uint32_t)(x)) << WDT_INT_CLR_INTCLR_SHIFT)) & WDT_INT_CLR_INTCLR_MASK)
/*! @name INT_RAW - raw interrupt status register */
#define WDT_INT_RAW_RAWINTSTAT_MASK (0x1U)
#define WDT_INT_RAW_RAWINTSTAT_SHIFT (0U)
#define WDT_INT_RAW_RAWINTSTAT(x) \
(((uint32_t)(((uint32_t)(x)) << WDT_INT_RAW_RAWINTSTAT_SHIFT)) & WDT_INT_RAW_RAWINTSTAT_MASK)
/*! @name MIS - interrupt mask register */
#define WDT_MIS_MASKINTSTAT_MASK (0x1U)
#define WDT_MIS_MASKINTSTAT_SHIFT (0U)
#define WDT_MIS_MASKINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << WDT_MIS_MASKINTSTAT_SHIFT)) & WDT_MIS_MASKINTSTAT_MASK)
/*! @name LOCK - watch dog lock register */
#define WDT_LOCK_LOCK_31_0_MASK (0xFFFFFFFFU)
#define WDT_LOCK_LOCK_31_0_SHIFT (0U)
#define WDT_LOCK_LOCK_31_0(x) (((uint32_t)(((uint32_t)(x)) << WDT_LOCK_LOCK_31_0_SHIFT)) & WDT_LOCK_LOCK_31_0_MASK)
/*! @name ITCR - integrated test control register */
#define WDT_ITCR_INTEGTESTEN_MASK (0x1U)
#define WDT_ITCR_INTEGTESTEN_SHIFT (0U)
#define WDT_ITCR_INTEGTESTEN(x) \
(((uint32_t)(((uint32_t)(x)) << WDT_ITCR_INTEGTESTEN_SHIFT)) & WDT_ITCR_INTEGTESTEN_MASK)
/*! @name ITOP - integrated test output set register */
#define WDT_ITOP_INTEGTESTOUTSET_MASK (0x3U)
#define WDT_ITOP_INTEGTESTOUTSET_SHIFT (0U)
#define WDT_ITOP_INTEGTESTOUTSET(x) \
(((uint32_t)(((uint32_t)(x)) << WDT_ITOP_INTEGTESTOUTSET_SHIFT)) & WDT_ITOP_INTEGTESTOUTSET_MASK)
/*!
* @}
*/ /* end of group WDT_Register_Masks */
/* WDT - Peripheral instance base addresses */
/** Peripheral WDT base address */
#define WDT_BASE (0x40001000u)
/** Peripheral WDT base pointer */
#define WDT ((WDT_Type *)WDT_BASE)
/** Array initializer of WDT peripheral base addresses */
#define WDT_BASE_ADDRS \
{ \
WDT_BASE \
}
/** Array initializer of WDT peripheral base pointers */
#define WDT_BASE_PTRS \
{ \
WDT \
}
/** Interrupt vectors for the WDT peripheral type */
#define WDT_IRQS \
{ \
WDT_IRQn \
}
/*!
* @}
*/ /* end of group WDT_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language = default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
---------------------------------------------------------------------------- */
/*!
* @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
* @{
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang system_header
#endif
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma system_include
#endif
/**
* @brief Mask and left-shift a bit field value for use in a register bit range.
* @param field Name of the register bit field.
* @param value Value of the bit field.
* @return Masked and shifted value.
*/
#define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK))
/**
* @brief Mask and right-shift a register value to extract a bit field value.
* @param field Name of the register bit field.
* @param value Value of the register.
* @return Masked and shifted bit field value.
*/
#define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT))
/*!
* @}
*/ /* end of group Bit_Field_Generic_Macros */
/* ----------------------------------------------------------------------------
-- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
/* No SDK compatibility issues. */
/*!
* @}
*/ /* end of group SDK_Compatibility_Symbols */
#endif /* _QN908X_H_ */
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/inc/usbd.h
|
#ifndef __CHLIB_USBD_H_
#define __CHLIB_USBD_H_
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include "usb_common.h"
#include "usbd_config.h"
#if ( USBD_DEBUG == 1 )
#include <stdio.h>
#endif
#if ( USBD_DEBUG == 1 )
#define USBD_TRACE printf
#else
#define USBD_TRACE(...)
#endif
#define USBD_USE_HID0 (1 << USBD_HID0_IF_IDX)
#define USBD_USE_HID1 (1 << USBD_HID1_IF_IDX)
#define USBD_USE_HID2 (1 << USBD_HID2_IF_IDX)
#define USBD_USE_CDC (1 << USBD_CDC_CIF_IDX)
#define USBD_USE_MSC (1 << USBD_MSC_IF_IDX)
struct usbd_ops_t
{
uint32_t (*ep_read)(uint8_t ep, uint8_t *buf, uint8_t data01);
uint32_t (*ep_write)(uint8_t ep, uint8_t *buf, uint32_t len, uint8_t data01);
uint32_t (*ep_config)(struct uendpoint_descriptor* d);
uint32_t (*ep_clear_feature)(uint8_t ep);
uint32_t (*set_addr)(uint8_t addr);
};
struct usbd_t
{
uint8_t* ep0_in_buf;
uint32_t ep0_in_remain_size;
uint8_t ep0_out_buf[64];
uint32_t ep0_out_remain_size;
uint8_t *ep0_out_ptr;
struct usbd_ops_t *ops;
struct urequest setup;
uint8_t addr;
uint32_t data01_in; /* data toggle status for ep_write */
uint32_t data01_out; /* data toggle status for ep_read */
bool need_zlp; /* need to send zero lengh IN packet */
bool is_configured;
uint32_t (*class_request_handler)(struct usbd_t *h);
uint32_t (*standard_request_to_intf_handler)(struct usbd_t *h);
uint32_t (*setup_out_data_received_handler)(uint8_t *buf, uint32_t len);
uint32_t (*data_ep_handler)(uint8_t ep, uint8_t dir);
uint32_t (*vender_request_handler)(struct usbd_t *h);
};
/* API */
void usbd_init(struct usbd_t *dev, struct usbd_ops_t *ops);
uint32_t usbd_ep_read(uint8_t ep, uint8_t *buf);
uint32_t usbd_ep_write(uint8_t ep, uint8_t *buf, uint32_t len);
uint32_t usbd_ep0_setup_handler(void);
uint32_t usbd_ep0_in_handler(void);
uint32_t usbd_ep0_out_handler(void);
void begin_data_in_stage(uint8_t *buf, uint32_t len);
void usbd_data_ep_handler(uint8_t ep, uint8_t dir);
void usbd_status_in_stage(void);
void usbd_status_out_stage(void);
void usbd_stack_reset(void);
bool usbd_is_configured(void);
uint32_t get_descriptor_data(const char *name, desc_t *d);
void create_string_descriptor(struct ustring_descriptor *d, uint8_t *buf, uint32_t len);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/syscon.c
|
/**
******************************************************************************
* @file syscon.c
* @author YANDLD
* @version V3.0.0
* @date 2016.5.28
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "syscon.h"
#include "common.h"
#include "fsl_power.h"
#define PLL_SSCG0_MDEC_VAL_P (0U) /* MDEC is in bits 16 downto 0 */
#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */
#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
#define NVALMAX (0x100U)
#define PVALMAX (0x20U)
#define MVALMAX (0x8000U)
/* Find encoded NDEC value for raw N value, max N = NVALMAX */
static uint32_t pllEncodeN(uint32_t N)
{
uint32_t x, i;
/* Find NDec */
switch (N)
{
case 0U:
x = 0xFFFU;
break;
case 1U:
x = 0x302U;
break;
case 2U:
x = 0x202U;
break;
default:
x = 0x080U;
for (i = N; i <= NVALMAX; i++)
{
x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
}
break;
}
return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
}
static uint32_t pllEncodeM(uint32_t M)
{
uint32_t i, x;
/* Find MDec */
switch (M)
{
case 0U:
x = 0xFFFFFU;
break;
case 1U:
x = 0x18003U;
break;
case 2U:
x = 0x10003U;
break;
default:
x = 0x04000U;
for (i = M; i <= MVALMAX; i++)
{
x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
}
break;
}
return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P);
}
/* Find encoded PDEC value for raw P value, max P = PVALMAX */
//static uint32_t pllEncodeP(uint32_t P)
//{
// uint32_t x, i;
// /* Find PDec */
// switch (P)
// {
// case 0U:
// x = 0xFFU;
// break;
// case 1U:
// x = 0x62U;
// break;
// case 2U:
// x = 0x42U;
// break;
// default:
// x = 0x10U;
// for (i = P; i <= PVALMAX; i++)
// {
// x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
// }
// break;
// }
// return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
//}
void SetFlashClock(uint32_t clk)
{
#if defined(SYSCON_FLASHCFG_FLASHTIM_MASK)
if (clk <= 12000000U)
{
SYSCON->FLASHCFG |= SYSCON_FLASHCFG_FLASHTIM(0);
}
else if (clk <= 30000000U)
{
SYSCON->FLASHCFG |= SYSCON_FLASHCFG_FLASHTIM(1);
}
else if (clk <= 60000000U)
{
SYSCON->FLASHCFG |= SYSCON_FLASHCFG_FLASHTIM(2);
}
else if (clk <= 85000000U)
{
SYSCON->FLASHCFG |= SYSCON_FLASHCFG_FLASHTIM(3);
}
else
{
SYSCON->FLASHCFG |= SYSCON_FLASHCFG_FLASHTIM(8);
}
#endif
}
void SetFROClock(uint32_t freq, bool val)
{
uint32_t reg;
if(val)
{
reg = SYSCON->FROCTRL;
SYSCON->PDRUNCFG[0] &= ~SYSCON_PDRUNCFG_PDEN_FRO_MASK;
reg |= SYSCON_FROCTRL_HSPDCLK_MASK | SYSCON_FROCTRL_USBCLKADJ_MASK;
(freq == 48*1000*1000)?(reg &= ~SYSCON_FROCTRL_SEL_MASK):(reg |= SYSCON_FROCTRL_SEL_MASK);
SYSCON->FROCTRL = reg;
}
else
{
SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK_MASK;
}
}
void SetClockOut(uint32_t opt)
{
/*
0x0 Main clock (main_clk)
0x1 CLKIN (clk_in)
0x2 Watchdog oscillator (wdt_clk)
0x3 FRO 96 or 48 MHz (fro_hf)
0x4 PLL output (pll_clk)
0x5 FRO 12 MHz (fro_12m)
0x6 RTC oscillator 32 kHz output (32k_clk)
*/
SYSCON->CLKOUTSELA = SYSCON_CLKOUTSELA_SEL(opt);
SYSCON->CLKOUTDIV &= ~SYSCON_CLKOUTDIV_HALT_MASK;
}
void SetExtOSC(uint32_t freq, bool val)
{
#if defined(SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
if(val)
{
(freq <= 20*1000*1000)?(SYSCON->SYSOSCCTRL &= ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK):(SYSCON->SYSOSCCTRL |= SYSCON_SYSOSCCTRL_FREQRANGE_MASK);
SYSCON->PDRUNCFG[0] &= ~SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
SYSCON->PDRUNCFG[1] &= ~SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
}
#endif
}
/* Find encoded PDEC value for raw P value, max P = PVALMAX */
static uint32_t pllEncodeP(uint32_t P)
{
uint32_t x, i;
/* Find PDec */
switch (P)
{
case 0U:
x = 0xFFU;
break;
case 1U:
x = 0x62U;
break;
case 2U:
x = 0x42U;
break;
default:
x = 0x10U;
for (i = P; i <= PVALMAX; i++)
{
x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
}
break;
}
return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
}
/* select
0x0 FRO 12 MHz (fro_12m)
0x1 CLKIN (clk_in)
*/
uint32_t SetupSystemPLL(uint32_t opt, uint32_t out_clk)
{
uint32_t SELR, SELI, SELP, in_clk;
bool isFind = false;
uint32_t M, m, N, n, P, Fcco, Fout;
SYSCON->SYSPLLCLKSEL = SYSCON_SYSPLLCLKSEL_SEL(opt);
if(opt == 0)
{
in_clk = GetClock(kFROLfClock);
}
if(opt == 1)
{
in_clk = GetClock(kExtOSCClock);
SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_IOCON_MASK;
IOCON->PIO[0][22] = IOCON_PIO_FUNC(1) | IOCON_PIO_DIGIMODE_MASK;
SetExtOSC(in_clk, true);
}
/* power off PLL */
#if defined(SYSCON_PDRUNCFG_PDEN_VD3_MASK)
SYSCON->PDRUNCFG[0] |= (SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK | SYSCON_PDRUNCFG_PDEN_VD3_MASK);
#else
SYSCON->PDRUNCFG[0] |= SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK;
#endif
#if defined(SYSCON_SYSPLLSSCTRL1_PD_MASK)
SYSCON->SYSPLLSSCTRL1 |= SYSCON_SYSPLLSSCTRL1_PD_MASK;
#endif
/* n: pre divider, p: post div, m feedback */
/* n:1-256, m:1-32768, p:1-32 */
/* Fout = Fcco = 2 x M x Fin / N */
for(m=1; m<=60; m++)
{
for(n=1; n<256; n++)
{
Fcco = 2 * m * in_clk/n;
Fout = Fcco/2; /* P = 1 */
if(Fout == out_clk && Fcco >= 60*1000*1000 && Fcco <= 500*1000*1000)
{
M = m;
N = n;
LIB_TRACE("m:%d, n:%d Fcco:%dHz\r\n", M, N, Fcco);
isFind = true;
goto FIND_SYS_PLL_PARAM;
}
}
}
if(isFind == false)
{
return CH_ERR;
}
FIND_SYS_PLL_PARAM:
SELR = 0U;
SELI = (M & 0x3cU) + 4U;
SELP = (M >> 1U) + 1U;
#if defined(SYSCON_SYSPLLCTRL_BANDSEL_MASK)
SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_BANDSEL_MASK | SYSCON_SYSPLLCTRL_SELR(SELR) | SYSCON_SYSPLLCTRL_SELP(SELP) | SYSCON_SYSPLLCTRL_SELI(SELI);
#else
SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_SELR(SELR) | SYSCON_SYSPLLCTRL_SELP(SELP) | SYSCON_SYSPLLCTRL_SELI(SELI);
#endif
#if defined(SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK)
SYSCON->SYSPLLSSCTRL0 = SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK | pllEncodeM(M) | SYSCON_SYSPLLSSCTRL0_MREQ_MASK; /* M */
#else
SYSCON->SYSPLLMDEC = pllEncodeM(M) | SYSCON_SYSPLLMDEC_MREQ_MASK;
#endif
/* post div, div by 2 */
P = 1;
SYSCON->SYSPLLNDEC = SYSCON_SYSPLLNDEC_NREQ_MASK | pllEncodeN(N); /* N */
SYSCON->SYSPLLPDEC = SYSCON_SYSPLLPDEC_PREQ_MASK | pllEncodeP(P); /* P */
/* power up PLL */
#if defined(SYSCON_PDRUNCFG_PDEN_VD3_MASK)
SYSCON->PDRUNCFG[0] &= ~(SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK | SYSCON_PDRUNCFG_PDEN_VD3_MASK);
#else
SYSCON->PDRUNCFG[0] &= ~SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK;
#endif
/* wait lock */
while((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) == 0);
POWER_SetVoltageForFreq(Fout);
SetFlashClock(Fout);
/* select main clock to be PLL */
SYSCON->MAINCLKSELB = SYSCON_MAINCLKSELB_SEL(2);
SystemCoreClockUpdate();
SystemCoreClock = out_clk;
return CH_OK;
}
/* USB PLL in clock fixed to exteral clk, USB PLL output clock is fixed to 48Mhz */
uint32_t SetupUSBPLL(void)
{
#if defined(SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
uint32_t M, m, N, n, p, P, Fcco, Fout, in_clk;
Fout = 48*1000*1000;
in_clk = GetClock(kExtOSCClock);
SYSCON->PDRUNCFG[1] |= SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK;
for(m=1; m<=256; m++)
{
for(n=1; n<4; n++)
{
for(p=1; p<8; p++)
{
Fcco = Fout*(2*p);
if((in_clk / n) * m == Fcco)
{
M = m;
N = n;
P = p;
LIB_TRACE("m:%d, n:%d p:%d Fcco:%dHz\r\n", M, N, P, Fcco);
goto FIND_USB_PLL_PARAM;
}
}
}
}
FIND_USB_PLL_PARAM:
SYSCON->USBPLLCTRL = SYSCON_USBPLLCTRL_MSEL(M-1) | SYSCON_USBPLLCTRL_PSEL(P-1) | SYSCON_USBPLLCTRL_NSEL(N-1);
SYSCON->PDRUNCFG[1] &= ~SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK;
/* wait lock */
while((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) == 0);
#endif
return 0;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/vsc/usbd_cp210x.c
|
<reponame>yandld/lpc_uart_server<filename>mcu_source/Libraries/utilities/chusb/src/vsc/usbd_cp210x.c
#include <string.h>
#include "usb_common.h"
#include "usbd.h"
#include "usbd_cp210x.h"
#include "uart_bridge.h"
#include "uart.h"
/* https://www.silabs.com/documents/public/application-notes/AN571.pdf */
typedef struct
{
uint16_t vid;
uint16_t pid;
const char* name;
}cp210x_id_t;
cp210x_id_t cp210x_id_table[] =
{
{0x10C4, 0xEA60, "CP2102"}, /* USB-1UART */
{0x10C4, 0xEA70, "CP2105"}, /* USB-2UART */
{0x10C4, 0xEA71, "CP2108"}, /* USB-4UART */
};
typedef struct
{
struct usbd_t *h;
cp210x_id_t id;
struct usbd_cp210x_callback_t *cb;
}cp210x_t;
static cp210x_t cp210x;
#define USBD_CP210X_CH0_BULKIN (1)
#define USBD_CP210X_CH0_BULKOUT (2)
#define USBD_CP210X_BUCK_SIZE (512)
static cp210x_cpr_t cpr;
static cp210x_ssr_t ssr;
static uint8_t cdc_out_buf[USBD_CP210X_BUCK_SIZE];
static rt_sem_t cp_out_sem;
extern rt_mutex_t usb_lock;
const uint8_t cp210x_descriptor[] =
{
/* CH0 */
USB_DESC_LENGTH_INTERFACE,
USB_DESC_TYPE_INTERFACE,
0, /* interfac index */
0x00,
0x02, /* 2 eps */
USB_CLASS_VEND_SPECIFIC,
0x00,
0x00,
USBD_IF_STR_IDX(USBD_MSC_IF_IDX),
/* eps descriptor */
0x07,
USB_DESC_TYPE_ENDPOINT,
(0x00 | USBD_CP210X_CH0_BULKOUT),
0x02,
WBVAL(USBD_CP210X_BUCK_SIZE),
0,
0x07,
USB_DESC_TYPE_ENDPOINT,
(0x80 | USBD_CP210X_CH0_BULKIN),
0x02, /* buck endpoint */
WBVAL(USBD_CP210X_BUCK_SIZE), /* size */
0, /* internal, 0 in buck */
};
/* data handler */
static uint32_t cp210x_data_ep_handler(uint8_t ep, uint8_t dir)
{
if(dir == 1) /* in */
{
if(ep == USBD_CP210X_CH0_BULKIN)
{
bridge_uart_usb_data_in_ready();
}
}
else /* out */
{
if(ep == USBD_CP210X_CH0_BULKOUT)
{
rt_sem_release(cp_out_sem);
}
}
return 0;
}
/* handle vender specfic class request */
static uint32_t cp210x_vender_request_handler(struct usbd_t *h)
{
uint8_t in_resp[8];
switch(h->setup.request)
{
case CP210X_VENDOR_SPECIFIC:
USBD_TRACE("CP210X_VENDOR_SPECIFIC\r\n");
switch(h->setup.value)
{
case 0x370B:
in_resp[0] = 0;
begin_data_in_stage(in_resp, 1);
break;
default:
USBD_TRACE("unknown vender specific request value:%X\r\n", h->setup.value);
break;
}
break;
case CP210X_SET_LINE_CTL:
USBD_TRACE("CP210X_SET_LINE_CTL\r\n");
break;
case CP210X_SET_CHAR:
USBD_TRACE("CP210X_SET_CHAR\r\n");
break;
case CP210X_IFC_ENABLE:
USBD_TRACE("CP210X_IFC_ENABLE\r\n");
break;
case CP210X_SET_BAUDDIV:
USBD_TRACE("CP210X_SET_BAUDDIV\r\n");
break;
case CP210X_GET_MDMSTS:
USBD_TRACE("CP210X_GET_MDMSTS\r\n");
in_resp[0] = 0;
begin_data_in_stage(in_resp, 1);
break;
case CP210X_SET_FLOW:
USBD_TRACE("CP210X_SET_FLOW\r\n");
break;
case CP210X_SET_CHARS:
USBD_TRACE("CP210X_SET_CHARS\r\n");
break;
case CP210X_SET_BAUDRATE:
USBD_TRACE("CP210X_SET_BAUDRATE\r\n");
break;
case CP210X_GET_COMM_STATUS:
USBD_TRACE("CP210X_GET_COMM_STATUS\r\n");
ssr.ulAmountInOutQueue = 0;
begin_data_in_stage((uint8_t*)&ssr, sizeof(ssr));
break;
case CP210X_GET_PROPS:
USBD_TRACE("CP210X_GET_PROPS\r\n");
cpr.wLength = sizeof(cp210x_cpr_t);
cpr.bcdVersion = 0x0100;
cpr.ulServiceMask = 0x00000001;
cpr.ulMaxTxQueue = USBD_CP210X_BUCK_SIZE;
cpr.ulCurrentRxQueue = USBD_CP210X_BUCK_SIZE;
cpr.ulMaxBaud = 1*1000*1000;
cpr.ulProvSubType = 0;
cpr.ulProvCapabilities = 0x00;
cpr.ulSettableParams = 0x3F;
cpr.ulSettableBaud = 0xFFFFFFFF;
cpr.wSettableData = 0xFF;
cpr.ulCurrentTxQueue = USBD_CP210X_BUCK_SIZE;
cpr.ulCurrentRxQueue = USBD_CP210X_BUCK_SIZE;
memcpy(cpr.uniProvName, L"SILABS USB V1.0", sizeof(cpr.uniProvName));
begin_data_in_stage((uint8_t*)&cpr, cpr.wLength);
break;
default:
USBD_TRACE("Unknown cp210x vender specfic reqeust\r\n");
break;
}
if(h->setup.length == 0 && (h->setup.request_type & 0x80) == 0x00)
{
usbd_status_in_stage();
}
return 0;
}
void cp_out_thread_entry(void* parameter)
{
int i, free, size;
while(1)
{
rt_sem_take(cp_out_sem, RT_WAITING_FOREVER);
/* read data from USB */
rt_mutex_take(usb_lock, RT_WAITING_FOREVER);
size = usbd_ep_read(USBD_CP210X_CH0_BULKOUT, cdc_out_buf);
rt_mutex_release(usb_lock);
for(i=4; i<5; i++)
{
/* get free buffer */
free = bridge_uart_tx_get_free(i);
while(free < size)
{
free = bridge_uart_tx_get_free(i);
rt_thread_delay(1);
}
bridge_uart_send(i, cdc_out_buf, size);
}
}
}
void usbd_vsc_cp210x_init(struct usbd_t *h)
{
cp210x.id = cp210x_id_table[0];
uint8_t *p;
struct uconfig_descriptor *uconfiguration_descriptor;
desc_t d;
/* make descriptor */
get_descriptor_data("device_descriptor", &d);
struct udevice_descriptor* device_desc = (struct udevice_descriptor*)d.buf;
device_desc->bDeviceClass = 0x00;
device_desc->bDeviceSubClass = 0x00;
device_desc->bDeviceProtocol = 0x00;
device_desc->idVendor = cp210x.id.vid;
device_desc->idProduct = cp210x.id.pid;
/* make configuration descriptor */
get_descriptor_data("configuration_descriptor", &d);
uconfiguration_descriptor = (struct uconfig_descriptor *)d.buf;
uconfiguration_descriptor->bLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->type = USB_DESC_TYPE_CONFIGURATION;
uconfiguration_descriptor->wTotalLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->bNumInterfaces = 1; /* interfae count */
uconfiguration_descriptor->bConfigurationValue = 1;
uconfiguration_descriptor->iConfiguration = 0;
uconfiguration_descriptor->bmAttributes = 0x80;
uconfiguration_descriptor->MaxPower = 0x32;
/* make intf and add to configuation data */
p = uconfiguration_descriptor->data;
d.buf = cp210x_descriptor;
d.len = sizeof(cp210x_descriptor);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
h->vender_request_handler = cp210x_vender_request_handler;
h->data_ep_handler = cp210x_data_ep_handler;
rt_thread_t tid;
cp_out_sem = rt_sem_create("cpout", 0, RT_IPC_FLAG_FIFO);
tid = rt_thread_create("cpout", cp_out_thread_entry, RT_NULL, 512, 19, 20);
rt_thread_startup(tid);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/usbd_msc.c
|
#include <string.h>
#include "usb_common.h"
#include "usbd.h"
#include "usbd_msc.h"
/* MSC state machine */
enum STAT
{
STAT_CBW, /* receive CBW block */
STAT_CMD, /* process cmd */
STAT_CSW, /* send CSW */
STAT_RECEIVE, /* receive data */
STAT_SEND, /* send data */
};
struct ustorage
{
struct usbd_t *h; /* usbd handle */
uint32_t total_block_cnt; /* total block count */
uint32_t block_size; /* how many bytes in one block */
uint32_t t_start_addr;
uint32_t t_total_cnt;
uint32_t t_current_offset;
uint32_t t_current_cnt;
struct ustorage_cbw cbw; /* cbw struct */
struct ustorage_csw csw; /* csw struct */
uint8_t buf[MSD_BUF_SIZE]; /* data buffer */
int status; /* state machine */
struct usbd_msc_callback_t *cb; /* callback */
};
struct ustorage msc;
void usbd_msc_set_cb(struct usbd_msc_callback_t *cb)
{
msc.cb = cb;
}
uint32_t msc_class_request_handler(struct usbd_t *h)
{
uint8_t lun[1];
if(h->setup.index == USBD_MSC_IF_IDX)
{
USBD_TRACE("class request send to msc interface:%d\r\n", USBD_MSC_IF_IDX);
switch(h->setup.request)
{
case USBREQ_GET_MAX_LUN:
/* get disk info */
msc.cb->msc_get_disk_info(&msc.total_block_cnt, &msc.block_size);
/* disk cnt = 1 */
USBD_TRACE("USBREQ_GET_MAX_LUN\r\n");
lun[0] = 0;
begin_data_in_stage(lun, 1);
msc.status = STAT_CBW;
break;
case USBREQ_MASS_STORAGE_RESET: /* set control line state */
usbd_status_in_stage();
USBD_TRACE("USBREQ_MASS_STORAGE_RESET\r\n");
break;
default:
USBD_TRACE("MSC UNKOWN REQUEST\r\n");
break;
}
}
return CH_OK;
}
uint32_t msc_standard_request_to_intf_handler(struct usbd_t *h)
{
USBD_TRACE("msc_standard_request_to_intf_handler\r\n");
return CH_OK;
}
static void _send_status(void)
{
msc.csw.tag = msc.cbw.tag;
msc.csw.signature = CSW_SIGNATURE;
msc.csw.data_reside = 0x00;
msc.csw.status = 0x00;
usbd_ep_write(USBD_MSC_EP_BULKIN, (uint8_t*)&msc.csw, SIZEOF_CSW);
}
static void cbw_dump(struct ustorage_cbw* cbw)
{
USBD_TRACE("signature 0x%x\r\n", cbw->signature);
USBD_TRACE("tag 0x%x\r\n", cbw->tag);
USBD_TRACE("xfer_len %d\r\n", cbw->xfer_len);
USBD_TRACE("dflags 0x%x\r\n", cbw->dflags);
USBD_TRACE("lun 0x%x\r\n", cbw->lun);
USBD_TRACE("cb_len %d\r\n", cbw->cb_len);
USBD_TRACE("cb[0] 0x%x\r\n", cbw->cb[0]);
}
static void _inquiry_cmd (void)
{
USBD_TRACE("inquiry\r\n");
msc.buf[0] = 0x00; /* Direct Access Device */
msc.buf[1] = 0x80; /* RMB = 1: Removable Medium */
msc.buf[2] = 0x02; /* Version: ANSI X3.131: 1994 */
msc.buf[3] = 0x02;
msc.buf[4] = 32; /* Additional Length */
msc.buf[5] = 0x00; /* SCCS = 0: No Storage Controller Component */
msc.buf[6] = 0x00;
msc.buf[7] = 0x00;
memset(&msc.buf[8], ' ', 28);
memcpy(&msc.buf[8], "CHUSB", 5);
memcpy(&msc.buf[16], "DISK", 4);
usbd_ep_write(USBD_MSC_EP_BULKIN, msc.buf, 36);
}
static void _read_capacities(void)
{
USBD_TRACE("read capacities\r\n");
msc.buf[0] = 0x00;
msc.buf[1] = 0x00;
msc.buf[2] = 0x00;
msc.buf[3] = 0x08; /* list length */
/* block count */
msc.buf[4] = (msc.total_block_cnt >> 24) & 0xFF;
msc.buf[5] = (msc.total_block_cnt >> 16) & 0xFF;
msc.buf[6] = (msc.total_block_cnt >> 8) & 0xFF;
msc.buf[7] = (msc.total_block_cnt >> 0) & 0xFF;
/* block size */
msc.buf[8] = 0x02; /* Descriptor Code: Formatted Media */
msc.buf[9] = (msc.block_size >> 16) & 0xFF;
msc.buf[10] = (msc.block_size >> 8) & 0xFF;
msc.buf[11] = (msc.block_size >> 0) & 0xFF;
usbd_ep_write(USBD_MSC_EP_BULKIN, msc.buf, 12);
}
static void _read_capacity(void)
{
/* Last Logical Block */
msc.buf[0] = ((msc.total_block_cnt - 1) >> 24) & 0xFF;
msc.buf[1] = ((msc.total_block_cnt - 1) >> 16) & 0xFF;
msc.buf[2] = ((msc.total_block_cnt - 1) >> 8) & 0xFF;
msc.buf[3] = ((msc.total_block_cnt - 1) >> 0) & 0xFF;
/* Block Length */
msc.buf[4] = (msc.block_size >> 24) & 0xFF;
msc.buf[5] = (msc.block_size >> 16) & 0xFF;
msc.buf[6] = (msc.block_size >> 8) & 0xFF;
msc.buf[7] = (msc.block_size >> 0) & 0xFF;
usbd_ep_write(USBD_MSC_EP_BULKIN, msc.buf, 8);
}
static void _read_10(void)
{
msc.t_start_addr = msc.cbw.cb[2]<<24 | msc.cbw.cb[3]<<16 | msc.cbw.cb[4]<<8 | msc.cbw.cb[5]<<0;
msc.t_total_cnt = msc.cbw.cb[7]<<8 | msc.cbw.cb[8]<<0;
msc.t_current_offset = 0;
msc.t_current_cnt = 0;
//USBD_TRACE("_read10 block:%d count:%d\r\n", msc.t_start_addr, msc.t_total_cnt);
}
static void _write_10(void)
{
msc.t_start_addr = msc.cbw.cb[2]<<24 | msc.cbw.cb[3]<<16 | msc.cbw.cb[4]<<8 | msc.cbw.cb[5]<<0;
msc.t_total_cnt = msc.cbw.cb[7]<<8 | msc.cbw.cb[8]<<0;
msc.t_current_offset = 0;
msc.t_current_cnt = 0;
USBD_TRACE("WRITE10 addr:%d cnt:%d\r\n", msc.t_start_addr, msc.t_total_cnt);
}
static void _memory_read(void)
{
uint32_t buck_len;
uint32_t block_cnt; /* how many block r/w in callback function, msc_read_sector */
if((msc.t_total_cnt - msc.t_current_cnt) > (sizeof(msc.buf)/msc.block_size))
{
block_cnt = (sizeof(msc.buf)/msc.block_size);
}
else
{
block_cnt = msc.t_total_cnt - msc.t_current_cnt;
}
if(msc.t_current_offset == 0 || msc.t_current_offset == (block_cnt*msc.block_size))
{
msc.cb->msc_read_sector(msc.t_start_addr + msc.t_current_cnt, msc.buf, block_cnt);
msc.t_current_cnt += block_cnt;
msc.t_current_offset = 0;
}
(msc.csw.data_reside > MSD_EP_SIZE)?(buck_len = MSD_EP_SIZE):(buck_len = msc.csw.data_reside);
//USBD_TRACE("read meory: current_ofs:%d buck_len:%d %d data_reside: %d\r\n", msc.t_current_offset, buck_len, msc.t_current_cnt, msc.csw.data_reside);
usbd_ep_write(USBD_MSC_EP_BULKIN, msc.buf + msc.t_current_offset, buck_len);
msc.t_current_offset += buck_len;
msc.csw.data_reside -= buck_len;
}
static void _memory_write(void)
{
uint32_t buck_len;
uint32_t write_cnt;
uint32_t buf_block_cnt = sizeof(msc.buf)/msc.block_size;
if((msc.t_total_cnt - msc.t_current_cnt) > buf_block_cnt)
{
write_cnt = buf_block_cnt;
}
else
{
write_cnt = msc.t_total_cnt - msc.t_current_cnt;
}
buck_len = usbd_ep_read(USBD_MSC_EP_BULKOUT, msc.buf + msc.t_current_offset);
//USBD_TRACE("we len:%d write_cnt:%d ofs:%d\r\n", buck_len, write_cnt, msc.t_current_offset);
msc.csw.data_reside -= buck_len;
msc.t_current_offset += buck_len;
if(msc.t_current_offset == write_cnt*msc.block_size)
{
msc.cb->msc_write_sector(msc.t_start_addr + msc.t_current_cnt, msc.buf, write_cnt);
msc.t_current_cnt += write_cnt;
msc.t_current_offset = 0;
}
}
static void _mode_sense_6(void)
{
//USBD_TRACE("_mode_sense_6\r\n");
msc.buf[0] = 3;
msc.buf[1] = 0;
msc.buf[2] = 0;
msc.buf[3] = 0;
usbd_ep_write(USBD_MSC_EP_BULKIN, msc.buf, SIZEOF_MODE_SENSE_6);
}
static void _log_sense(void)
{
USBD_TRACE("_log_sense\r\n");
msc.buf[0] = 0;
msc.buf[1] = 0;
msc.buf[2] = 0;
msc.buf[3] = 0;
usbd_ep_write(USBD_MSC_EP_BULKIN, msc.buf, 4);
}
uint32_t msc_data_ep_handler(uint8_t ep, uint8_t dir)
{
uint32_t size;
if(ep == USBD_MSC_EP_BULKOUT && dir == 0) /* OUT TOKEN */
{
switch(msc.status)
{
case STAT_CBW:
size = usbd_ep_read(ep, (uint8_t*)&msc.cbw);
if(size != SIZEOF_CBW)
{
USBD_TRACE("size of CBW error! %d != %d \r\n", size, SIZEOF_CBW);
while(1);
}
//cbw_dump(&msc.cbw);
if(msc.cbw.signature == CBW_SIGNATURE)
{
msc.csw.data_reside = msc.cbw.xfer_len;
msc.csw.tag = msc.cbw.tag;
switch (msc.cbw.cb[0])
{
case SCSI_INQUIRY_CMD:
_inquiry_cmd();
msc.status = STAT_CSW;
break;
case SCSI_READ_CAPACITIES:
_read_capacities();
msc.status = STAT_CSW;
break;
case SCSI_MODE_SENSE_6:
_mode_sense_6();
msc.status = STAT_CSW;
break;
case SCSI_READ_CAPACITY:
case 0x9E:
_read_capacity();
msc.status = STAT_CSW;
break;
case SCSI_READ_10: /* PC read data, IN transfer */
_read_10();
_memory_read();
if(msc.csw.data_reside == 0)
{
msc.status = STAT_CSW;
}
else
{
msc.status = STAT_SEND;
}
break;
case SCSI_WRITE_10: /* PC send data, out transfer */
_write_10();
msc.status = STAT_RECEIVE;
break;
case SCSI_TEST_UNIT_READY:
_send_status();
msc.status = STAT_CBW;
break;
case SCSI_ALLOW_REMOVAL:
_send_status();
msc.status = STAT_CBW;
break;
case 0x4D:
_log_sense();
msc.status = STAT_CSW;
break;
default:
USBD_TRACE("Unknown CBW command 0x%X\r\n", msc.cbw.cb[0]);
cbw_dump(&msc.cbw);
_send_status();
msc.status = STAT_CBW;
//while(1);
break;
}
}
break;
case STAT_RECEIVE:
_memory_write();
if(msc.csw.data_reside == 0)
{
_send_status();
msc.status = STAT_CBW;
}
break;
}
}
if(ep == USBD_MSC_EP_BULKIN && dir == 1) /* IN TOKEN */
{
switch(msc.status)
{
case STAT_CMD:
USBD_TRACE("STAT_CMD\r\n");
break;
case STAT_SEND:
_memory_read();
if(msc.csw.data_reside == 0)
{
msc.status = STAT_CSW;
}
break;
case STAT_CSW:
_send_status();
msc.status = STAT_CBW;
break;
default:
//USBD_TRACE("Unknwon In BuckIn event %d\r\n", msc.status);
break;
}
}
return CH_OK;
}
void usbd_msc_init(struct usbd_t *h)
{
msc.h = h;
uint8_t *p;
struct uconfig_descriptor *uconfiguration_descriptor;
desc_t d;
if(msc.block_size > MSD_BUF_SIZE)
{
USBD_TRACE("MSD_BUF_SIZE must greater then msc.block_size");
return;
}
get_descriptor_data("configuration_descriptor", &d);
uconfiguration_descriptor = (struct uconfig_descriptor *)d.buf;
uconfiguration_descriptor->bLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->type = USB_DESC_TYPE_CONFIGURATION;
uconfiguration_descriptor->wTotalLength = USB_DESC_LENGTH_CONFIG;
uconfiguration_descriptor->bNumInterfaces = 1;
uconfiguration_descriptor->bConfigurationValue = 1;
uconfiguration_descriptor->iConfiguration = 0;
uconfiguration_descriptor->bmAttributes = 0x80;
uconfiguration_descriptor->MaxPower = 0x32;
/* add configuation data */
p = uconfiguration_descriptor->data;
get_descriptor_data("msc_descriptor", &d);
memcpy(p, d.buf, d.len);
p += d.len;
uconfiguration_descriptor->wTotalLength += d.len;
/* install class callback */
msc.h->class_request_handler = msc_class_request_handler;
msc.h->standard_request_to_intf_handler = msc_standard_request_to_intf_handler;
msc.h->data_ep_handler = msc_data_ep_handler;
msc.h->vender_request_handler = NULL;
msc.status = STAT_CBW;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/spi.h
|
<gh_stars>1-10
/**
******************************************************************************
* @file spi.h
* @author YANDLD
* @version V3.0.0
* @date 2016.6.2
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_LPC_SPI_H__
#define __CH_LIB_LPC_SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#define HW_SPI0 (0)
#define HW_SPI1 (1)
#define HW_SPI2 (2)
#define HW_SPI3 (3)
#define HW_SPI4 (4)
#define HW_SPI5 (5)
#define HW_SPI6 (6)
#include <stdint.h>
#include <stdbool.h>
uint32_t SPI_Init(uint32_t MAP, uint32_t baudrate);
uint32_t SPI_ReadWriteEx(uint32_t instance, uint32_t data, uint16_t cs, uint32_t cs_state);
uint32_t SPI_ReadWrite(uint32_t instance, uint32_t data);
uint32_t SPI_WriteFIFO(uint32_t instance, uint8_t *buf, uint32_t len);
uint32_t SPI_ReadFIFO(uint32_t instance, uint8_t *buf, uint32_t len);
uint32_t SPI_ReadWriteFIFO(uint32_t instance, uint8_t *in_buf, uint8_t *out_buf, uint32_t len);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/syscon.h
|
/**
******************************************************************************
* @file syscon.h
* @author YANDLD
* @version V3.0.0
* @date 2016.05.31
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_SYSCON_H__
#define __CH_LIB_SYSCON_H__
#include <stdint.h>
#include <stdbool.h>
enum
{
kPLLSrcFRO12M = 0,
kPLLSrcCLKIN = 1,
};
uint32_t SetupSystemPLL(uint32_t in_clk, uint32_t out_clk);
uint32_t SetupUSBPLL(void);
void SetFlashClock(uint32_t clk);
void SetFROClock(uint32_t freq, bool val);
void SetClockOut(uint32_t opt);
void SetExtOSC(uint32_t freq, bool val);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/usbd.c
|
#include "usbd.h"
#include "usb_common.h"
/* usbd device handle */
static struct usbd_t *handle;
/* read data from PC */
uint32_t usbd_ep_read(uint8_t ep, uint8_t *buf)
{
uint32_t size;
size = handle->ops->ep_read(ep, buf, (handle->data01_out >> ep) & 0x01);
handle->data01_out ^= (1 << ep);
return size;
}
/* write data to EP to prepare PC to read EP */
uint32_t usbd_ep_write(uint8_t ep, uint8_t *buf, uint32_t len)
{
uint32_t size;
size = handle->ops->ep_write(ep, buf, len, (handle->data01_in >> ep) & 0x01);
handle->data01_in ^= (1 << ep);
return size;
}
void usbd_status_in_stage(void)
{
/* status in stage, use DATA 1 */
handle->data01_in |= (1 << 0);
usbd_ep_write(0, NULL, 0);
}
void usbd_status_out_stage(void)
{
handle->data01_out |= (1 << 0);
usbd_ep_read(0, handle->ep0_out_buf);
}
void usbd_data_in_stage(void)
{
uint32_t len;
if(handle->ep0_in_remain_size > EP0_MAX_SIZE)
{
len = EP0_MAX_SIZE;
}
else
{
len = handle->ep0_in_remain_size;
}
if(len || handle->need_zlp)
usbd_ep_write(0, handle->ep0_in_buf, len);
handle->ep0_in_buf += len;
handle->ep0_in_remain_size -= len;
}
/*
request_type:
D7: dir
0, host to device
1, device to host
D6~5: request type:
0: standard
1: class
2: vender
D4~0: receiver of request
0: device
1: interface
2: endpoint
*/
void _dump_setup_packet(struct urequest *setup)
{
USBD_TRACE("\r\n[setup: ");
USBD_TRACE("request_type:0x%X ", setup->request_type);
USBD_TRACE("request:0x%X ", setup->request);
USBD_TRACE("value:0x%X ", setup->value);
USBD_TRACE("index:0x%X ", setup->index);
USBD_TRACE("length:%d ", setup->length);
USBD_TRACE("]\r\n");
}
void usbd_stack_reset(void)
{
handle->data01_in = 0x00000000; /* ep_write function, all begin with DATA0 */
handle->data01_out = 0xFFFFFFFF; /* ep_read function, means begin with second read, so, must be DATA1 */
handle->ep0_out_ptr = handle->ep0_out_buf;
handle->ep0_out_remain_size = 0;
handle->need_zlp = false;
handle->is_configured = false;
}
void usbd_init(struct usbd_t *dev, struct usbd_ops_t *ops)
{
handle = dev;
handle->ops = ops;
usbd_stack_reset();
}
bool usbd_is_configured(void)
{
return handle->is_configured;
}
void begin_data_in_stage(uint8_t *buf, uint32_t len)
{
handle->ep0_in_buf = buf;
handle->ep0_in_remain_size = len;
/* data in stage begin with DATA1 */
handle->data01_in |= (1 << 0);
if((len % EP0_MAX_SIZE) == 0 && (len >= EP0_MAX_SIZE))
{
handle->need_zlp = true;
}
else
{
handle->need_zlp = false;
}
usbd_data_in_stage();
}
void begin_data_out_stage(void)
{
handle->ep0_out_remain_size = handle->setup.length;
handle->ep0_out_ptr = handle->ep0_out_buf;
}
void data_out_stage(void)
{
uint32_t size;
size = usbd_ep_read(0, handle->ep0_out_ptr);
handle->ep0_out_ptr += size;
handle->ep0_out_remain_size -= size;
if(handle->ep0_out_remain_size == 0)
{
if(handle->setup_out_data_received_handler)
{
handle->setup_out_data_received_handler(handle->ep0_out_buf, handle->setup.length);
}
/* status in stage */
usbd_status_in_stage();
}
}
static uint32_t _get_descriptor(struct urequest* setup)
{
struct ustring_descriptor ustr;
uint8_t string_index;
uint8_t language_str_buf[] = {0x04, 0x03, 0x09, 0x04};
desc_t d;
if(setup->request_type == USB_REQ_TYPE_DIR_IN)
{
switch(setup->value >> 8)
{
case USB_DESC_TYPE_DEVICE:
USBD_TRACE("device_descriptor\r\n");
get_descriptor_data("device_descriptor", &d);
break;
case USB_DESC_TYPE_CONFIGURATION:
USBD_TRACE("configuration_descriptor\r\n");
get_descriptor_data("configuration_descriptor", &d);
struct uconfig_descriptor *p = (struct uconfig_descriptor*)d.buf;
d.len = p->wTotalLength;
break;
case USB_DESC_TYPE_DEVICEQUALIFIER:
USBD_TRACE("usb_qualifier_descriptor\r\n");
get_descriptor_data("qualifier_descriptor", &d);
break;
case USB_DESC_TYPE_STRING:
string_index = (setup->value & 0xFF);
USBD_TRACE("string_descriptor:%d\r\n", string_index);
switch(string_index)
{
case 0:
create_string_descriptor(&ustr, (uint8_t*)language_str_buf, sizeof(language_str_buf));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case 1:
create_string_descriptor(&ustr, (uint8_t*)MANUFACTURE_STR, sizeof(MANUFACTURE_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case 2:
create_string_descriptor(&ustr, (uint8_t*)PRODUCT_STR, sizeof(PRODUCT_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case 3:
create_string_descriptor(&ustr, (uint8_t*)SERIAL_STR, sizeof(SERIAL_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case USBD_IF_STR_IDX(USBD_MSC_IF_IDX):
create_string_descriptor(&ustr, (uint8_t*)USBD_MSC_IF_STR, sizeof(USBD_MSC_IF_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case USBD_IF_STR_IDX(USBD_CDC_CIF_IDX):
create_string_descriptor(&ustr, (uint8_t*)USBD_CDC_CIF_STR, sizeof(USBD_CDC_CIF_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case USBD_IF_STR_IDX(USBD_CDC_DIF_IDX):
create_string_descriptor(&ustr, (uint8_t*)USBD_CDC_DIF_STR, sizeof(USBD_CDC_CIF_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case USBD_IF_STR_IDX(USBD_HID0_IF_IDX):
create_string_descriptor(&ustr, (uint8_t*)USBD_HID0_IF_STR, sizeof(USBD_HID0_IF_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case USBD_IF_STR_IDX(USBD_HID1_IF_IDX):
create_string_descriptor(&ustr, (uint8_t*)USBD_HID1_IF_STR, sizeof(USBD_HID1_IF_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
case USBD_IF_STR_IDX(USBD_HID2_IF_IDX):
create_string_descriptor(&ustr, (uint8_t*)USBD_HID2_IF_STR, sizeof(USBD_HID2_IF_STR));
d.buf = (uint8_t*)&ustr;
d.len = ustr.bLength;
break;
default:
USBD_TRACE("unknown string index:%d, use default\r\n", string_index);
break;
}
break;
default:
USBD_TRACE("unsupported descriptor request:%d\n", setup->value >> 8);
d.buf = NULL;
d.len = 0;
break;
}
if(setup->length < d.len)
{
begin_data_in_stage((uint8_t*)d.buf, setup->length);
}
else
{
begin_data_in_stage((uint8_t*)d.buf, d.len);
}
}
else
{
USBD_TRACE("request direction error\n");
}
return CH_OK;
}
static uint32_t _standard_request(struct urequest* setup)
{
desc_t d;
uint8_t *p;
uint8_t ofs, len;
struct uconfig_descriptor *uconfiguration_descriptor;
switch(setup->request_type & USB_REQ_TYPE_RECIPIENT_MASK)
{
case USB_REQ_TYPE_DEVICE:
switch(setup->request)
{
case USB_REQ_GET_DESCRIPTOR:
_get_descriptor(setup);
break;
case USB_REQ_SET_ADDRESS:
USBD_TRACE("standard request: set addr:%d\r\n", setup->value);
handle->addr = (setup->value & 0x7F);
usbd_status_in_stage();
break;
case USB_REQ_SET_CONFIGURATION:
USBD_TRACE("standard request: set configuration\r\n");
/* find endpoint descriptor and call ep_config */
get_descriptor_data("configuration_descriptor", &d);
uconfiguration_descriptor = (struct uconfig_descriptor *)d.buf;
p = (uint8_t*)d.buf;
ofs = 0;
len = 0;
while((ofs < uconfiguration_descriptor->wTotalLength) && (*p) != 0)
{
len = (*p);
switch(*(p+1))
{
case USB_DESC_TYPE_ENDPOINT:
if(handle->ops->ep_config)
{
handle->ops->ep_config((struct uendpoint_descriptor*)(p));
}
break;
}
p += len;
ofs += len;
}
usbd_status_in_stage();
handle->is_configured = true;
break;
case USB_REQ_GET_STATUS:
USBD_TRACE("standard request, get status\r\n");
static uint8_t get_status_responds[2] = {0x00, 0x00};
begin_data_in_stage(get_status_responds, 2);
break;
default:
USBD_TRACE("unkown request %d to device \r\n", setup->request);
break;
}
break;
case USB_REQ_TYPE_INTERFACE:
USBD_TRACE("request to interface\r\n");
handle->standard_request_to_intf_handler(handle);
break;
case USB_REQ_TYPE_ENDPOINT:
if(setup->request == USB_REQ_CLEAR_FEATURE)
{
handle->ops->ep_clear_feature(handle->setup.index);
}
else
{
USBD_TRACE("other request to endpoint\r\n");
}
usbd_status_in_stage();
break;
case USB_REQ_TYPE_OTHER:
USBD_TRACE("unknown other type request\n");
break;
default:
USBD_TRACE("unknown device request\n");
break;
}
return CH_OK;
}
uint32_t usbd_ep0_setup_handler(void)
{
int size;
size = usbd_ep_read(0, (uint8_t*)&handle->setup);
if(size != sizeof(struct urequest))
{
USBD_TRACE("read setup packet error size:%d\r\n", size);
return CH_ERR;
}
_dump_setup_packet(&handle->setup);
/* if has data stage && dir = OUT. means there is data out stage */
if(handle->setup.length && ((handle->setup.request_type & 0x80) == 0x00))
{
handle->data01_out |= (1 << 0); /* force set to DATA1 */
begin_data_out_stage();
}
else /* next is a setup package */
{
handle->data01_out &= ~(1 << 0); /* force set to DATA0 */
}
switch(handle->setup.request_type & USB_REQ_TYPE_MASK)
{
case USB_REQ_TYPE_STANDARD:
_standard_request(&handle->setup);
break;
case USB_REQ_TYPE_CLASS:
handle->class_request_handler(handle);
break;
case USB_REQ_TYPE_VENDOR:
USBD_TRACE("vendor type request\n");
if(handle->vender_request_handler != NULL)
{
handle->vender_request_handler(handle);
}
break;
default:
USBD_TRACE("unknown setup request type\n");
//rt_usbd_ep0_set_stall(device);
return CH_ERR;
}
return CH_OK;
}
uint32_t usbd_ep0_out_handler(void)
{
if(((handle->setup.request_type & 0x80) == 0x00) && handle->setup.length) /* data out stage */
{
USBD_TRACE("Data out stage\r\n");
data_out_stage();
}
else
{
usbd_status_out_stage();
}
return CH_OK;
}
/* 0:OUT packet 1:IN packet */
void usbd_data_ep_handler(uint8_t ep, uint8_t dir)
{
handle->data_ep_handler(ep, dir);
}
uint32_t usbd_ep0_in_handler(void)
{
/* host to device direction means it's a set address request */
if((handle->setup.request_type & 0x80) == USB_REQ_TYPE_DIR_OUT)
{
handle->ops->set_addr(handle->addr);
}
else
{
usbd_data_in_stage();
}
return CH_OK;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/inc/usbd_cdc.h
|
#ifndef __USBD_cdc_H_
#define __USBD_cdc_H_
#include <stdint.h>
#include <usbd.h>
#include <usb_common.h>
struct usbd_cdc_callback_t
{
uint32_t (*get_line_coding)(struct ucdc_line_coding *line_coding);
uint32_t (*set_line_coding)(struct ucdc_line_coding *line_coding);
uint32_t (*set_control_line_serial_state)(uint8_t val);
uint32_t (*recv_handler)(uint8_t *buf, uint32_t len);
uint32_t (*send_notify)(void);
};
void usbd_cdc_init(struct usbd_t *h);
uint32_t usbd_cdc_send(uint8_t *buf, uint32_t len);
void usbd_cdc_set_cb(struct usbd_cdc_callback_t *cb);
uint32_t cdc_class_request_handler(struct usbd_t *h);
uint32_t cdc_standard_request_to_intf_handler(struct usbd_t *h);
uint32_t cdc_data_ep_handler(uint8_t ep, uint8_t dir);
uint32_t cdc_setup_out_data_received(uint8_t *buf, uint32_t len);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/wdog.h
|
/**
******************************************************************************
* @file wdog.h
* @author YANDLD
* @version V3.0.0
* @date 2016.2.16
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_WDOG_H__
#define __CH_LIB_WDOG_H__
#include <stdint.h>
#include <stdbool.h>
/* API */
void WDOG_Init(uint32_t ms);
void WDOG_Refresh(void);
uint32_t WDOG_GetValue(void);
uint32_t WDOG_GetResetCnt(void);
void WDOG_Disable(void);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/src/usbd_lpc_driver_hs.c
|
<gh_stars>1-10
#include "common.h"
#include "syscon.h"
#include "usbd.h"
#include "usbd_config.h"
void USBD_Reset (void);
void USBD_EnableEP (uint32_t EPNum);
void USBD_ResetEP (uint32_t EPNum);
#if defined(RTT)
#include <rtthread.h>
extern rt_mq_t msd_mq;
typedef struct
{
uint8_t param;
void (*exec)(uint32_t param);
}msd_msg_t;
#endif
#define BUF_ACTIVE (1UL << 31)
#define EP_DISABLED (1UL << 30)
#define EP_STALL (1UL << 29)
#define TOOGLE_RESET (1UL << 28)
#define EP_TYPE (1UL << 26)
#define EP_RF_TV (1UL << 27)
#define N_BYTES(n) ((n & 0x7FFF) << 11)
#define BUF_ADDR(addr) (((addr) >> 6) & 0x7FF)
#define EP_OUT_IDX(EPNum) (EPNum * 2)
#define EP_IN_IDX(EPNum) (EPNum * 2 + 1)
#define MAX_EP_COUNT (6)
#define EP_BUFFER_SIZE (MSD_EP_SIZE)
/* EP list must be 256 aligned */
uint32_t *EPList = (uint32_t*)0x40101F00;
/* buffer must be 64 byte aliged */
uint8_t *EP_BUF_BASE = (uint8_t*)0x40100000;
typedef struct BUF_INFO
{
uint32_t buf_len;
uint32_t buf_ptr;
}EP_BUF_INFO;
EP_BUF_INFO EPBufInfo[(MAX_EP_COUNT) * 2];
static uint32_t addr;
void USBD_ConfigEP (uint8_t ep);
/*get EP Command/Status register */
uint32_t * GetEpCmdStatPtr (uint32_t EPNum)
{
uint32_t ptr = 0;
if (EPNum & 0x80)
{
EPNum &= ~0x80;
ptr = 8;
}
ptr += (uint32_t)EPList + EPNum * sizeof(uint32_t)*4;
return ((uint32_t *)ptr);
}
/*
// Enable source power for USB PHYs
void POWER_SetUsbPhy(void)
{
SYSCON->PDRUNCFGCLR[0] = PDRUNCFG_PD_VD5;
// wait until VD5 fully power
while((POWER->MREG_VDOK & POWER_VD5_OK_LOAD) != POWER_VD5_OK_LOAD );
}
*/
void USBD_Init (void)
{
int i;
SetupUSBPLL();
/* select USB clock to be usb pll */
SYSCON->USB1CLKSEL = SYSCON_USB1CLKSEL_SEL(2);
for(i=1; i<0xFF; i++)
{
if((GetClock(kUSBPLLClock) / i) == 48*1000*1000)
{
USBD_TRACE("USB1D divider found:%d\r\n", i);
SYSCON->USB1CLKDIV = SYSCON_USB1CLKDIV_DIV(i-1);
break;
}
}
if(i == 0xFF)
{
USBD_TRACE("cannot found divider\r\n");
}
SYSCON->PDRUNCFG[0] &= ~SYSCON_PDRUNCFG_PDEN_VD5_MASK;
/* wait until VD5 fully power */
DelayMs(2);
/* Enable USB1D and USB1RAM */
SYSCON->AHBCLKCTRL[2] |= SYSCON_AHBCLKCTRL_USB1H_MASK | SYSCON_AHBCLKCTRL_USB1D_MASK | SYSCON_AHBCLKCTRL_USB1RAM_MASK;
SYSCON->PDRUNCFG[0] &= ~(SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK | SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK | SYSCON_PDRUNCFG_PDEN_VD3_MASK | SYSCON_PDRUNCFG_PDEN_VD5_MASK);
SYSCON->PDRUNCFG[1] &= ~(SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK);
*((uint32_t *)(USBHSH_BASE + 0x50)) |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
USBD_TRACE("EPNUm:%d\r\n", MAX_EP_COUNT);
USBD_TRACE("EP_BUF_BASE: 0x%08X\r\n", (uint32_t)EP_BUF_BASE);
USBD_TRACE("EPList: 0x%08X\r\n", (uint32_t)EPList);
USBHSD->DEVCMDSTAT &= ~USBHSD_DEVCMDSTAT_DCON_MASK;
USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK;
USBHSD->EPLISTSTART = (uint32_t)EPList;
USBD_TRACE("EPLISTSTART:0x%08X\r\n", USBHSD->EPLISTSTART);
USBD_TRACE("DATABUFSTART:0x%08X\r\n", USBHSD->DATABUFSTART);
USBD_Reset();
NVIC_EnableIRQ(USB1_IRQn);
}
void USBD_Connect (bool con)
{
if(con)
{
USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DCON_MASK;
}
else
{
USBHSD->DEVCMDSTAT &= ~USBHSD_DEVCMDSTAT_DCON_MASK;
}
}
void USBD_Reset (void)
{
uint32_t * ptr;
addr = 3 * EP_BUFFER_SIZE + (uint32_t)EP_BUF_BASE;
EPBufInfo[0].buf_len = EP0_MAX_SIZE;
EPBufInfo[0].buf_ptr = (uint32_t)EP_BUF_BASE;
EPBufInfo[1].buf_len = EP0_MAX_SIZE;
EPBufInfo[1].buf_ptr = (uint32_t)EP_BUF_BASE + 2 * EP_BUFFER_SIZE;
ptr = GetEpCmdStatPtr(0);
/* EP0 OUT */
*ptr = N_BYTES(EPBufInfo[0].buf_len) | BUF_ADDR(EPBufInfo[0].buf_ptr) | BUF_ACTIVE;
ptr++;
*ptr = BUF_ADDR(EPBufInfo[0].buf_ptr + EP_BUFFER_SIZE); /* SETUP */
USBHSD->DEVCMDSTAT &= ~USBHSD_DEVCMDSTAT_DEV_ADDR_MASK;
USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DEV_EN_MASK; /* USB device enable */
USBHSD->INTSTAT = 0xFFFFFFFF;
USBHSD->INTEN = USBHSD_INTEN_EP_INT_EN_MASK | USBHSD_INTEN_FRAME_INT_EN_MASK | USBHSD_INTEN_DEV_INT_EN_MASK;
}
uint32_t usbd_config_ep(struct uendpoint_descriptor* d)
{
uint32_t * ptr;
uint8_t num = d->bEndpointAddress;
uint32_t size = d->wMaxPacketSize;
volatile uint8_t type = d->bmAttributes;
USBD_TRACE("ConfigEP:0x%X %d %d\r\n", num, size, type);
if (num & 0x80) /* IN EPs */
{
num &= ~0x80;
EPBufInfo[EP_IN_IDX(num)].buf_len = size;
EPBufInfo[EP_IN_IDX(num)].buf_ptr = addr;
addr += (((size + (EP_BUFFER_SIZE-1)) >> 6) * EP_BUFFER_SIZE); /* calc new free buffer address */
ptr = GetEpCmdStatPtr(num | 0x80);
*ptr = EP_DISABLED;
*ptr &= ~EP_DISABLED;
*ptr |= TOOGLE_RESET;
}
else /* OUT */
{
EPBufInfo[EP_OUT_IDX(num)].buf_len = size;
EPBufInfo[EP_OUT_IDX(num)].buf_ptr = addr;
ptr = GetEpCmdStatPtr(num);
*ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(num)].buf_len) | BUF_ADDR(EPBufInfo[EP_OUT_IDX(num)].buf_ptr);
*ptr |= BUF_ACTIVE;
*ptr |= TOOGLE_RESET;
addr += ((size + (EP_BUFFER_SIZE-1)) >> 6) * EP_BUFFER_SIZE; /* calc new free buffer address */
}
return 0;
}
uint32_t USBD_ReadEP (uint32_t EPNum, uint8_t *pData)
{
uint32_t cnt, i;
uint32_t *dataptr, *ptr;
ptr = GetEpCmdStatPtr(EPNum);
/* SETUP packet */
if ((EPNum == 0) && (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK))
{
cnt = 8; /* LPC hardware cannot tell you how much byte setup packet has been received. standard request len = 8 */
dataptr = (uint32_t *)(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr + EP_BUFFER_SIZE);
for (i = 0; i < (cnt + 3) / 4; i++)
{
*((__packed uint32_t *)pData) = dataptr[i];
pData += 4;
}
USBHSD->EPSKIP |= (1 << EP_IN_IDX(EPNum));
while (USBHSD->EPSKIP & (1 << EP_IN_IDX(EPNum)));
if (*(ptr + 2) & EP_STALL)
{
*(ptr + 2) &= ~(EP_STALL);
}
if (*ptr & EP_STALL)
{
*ptr &= ~(EP_STALL);
}
USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_SETUP_MASK;
}
else /*OUT packet */
{
ptr = GetEpCmdStatPtr(EPNum);
cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len - ((*ptr >> 11) & 0x7FFF);
dataptr = (uint32_t *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr;
for (i = 0; i < (cnt + 3) / 4; i++)
{
*((__packed uint32_t *)pData) = dataptr[i];
pData += 4;
}
*ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(EPNum)].buf_len) | BUF_ADDR(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr) | BUF_ACTIVE | EP_TYPE | EP_RF_TV;;
}
return (cnt);
}
uint32_t USBD_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt)
{
uint32_t i;
uint32_t * dataptr, *ptr;
ptr = GetEpCmdStatPtr(EPNum);
EPNum &= ~0x80;
if(*ptr & BUF_ACTIVE)
{
//USBD_TRACE("USBD_WriteEP error\r\n");
return 0;
}
*ptr &= ~(0x03FFFFFF);
*ptr |= BUF_ADDR(EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr) | N_BYTES(cnt);
//USBD_TRACE("WriteEP%d len:%d 0x%08X\r\n", EPNum, cnt, EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr);
dataptr = (uint32_t *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr;
for (i = 0; i < (cnt + 3) / 4; i++)
{
dataptr[i] = * ((__packed uint32_t *)pData);
pData += 4;
}
if (EPNum && (*ptr & EP_STALL))
{
return (0);
}
if((EPNum & 0x0F) == 0)
{
/* When EP0 IN is received, set ACTIVE bit on both EP0 IN and OUT. */
*(ptr - 2) |= BUF_ACTIVE; /* Set ACTIVE bit on EP0 OUT */
}
*ptr |= BUF_ACTIVE;
return (cnt);
}
/*
* USB Device Interrupt Service Routine
*/
void USBD_IRQHandler(void)
{
uint32_t sts, val, num;
sts = USBHSD->INTSTAT;
USBHSD->INTSTAT = sts;
sts &= USBHSD->INTEN;
/* Save USB info register. Used later for NAK and Error handling */
uint32_t err = (USBHSD->INFO >> 11) & 0x0F;
/* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */
if (sts & USBHSD_INTSTAT_DEV_INT_MASK)
{
val = USBHSD->DEVCMDSTAT;
if(val & USBHSD_DEVCMDSTAT_DCON_C_MASK)
{
val |= USBHSD_DEVCMDSTAT_DCON_C_MASK;
USBD_TRACE("detach\r\n");
}
/* reset interrupt */
if (val & USBHSD_DEVCMDSTAT_DRES_C_MASK)
{
USBD_TRACE("usbd reset %d\r\n", ((val & USBHSD_DEVCMDSTAT_Speed_MASK) >> USBHSD_DEVCMDSTAT_Speed_SHIFT));
USBD_Reset();
usbd_stack_reset();
USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DRES_C_MASK;
}
/* suspend/resume interrupt */
if (val & (1UL << 25))
{
//USBD_TRACE("suspend/resume\r\n");
/* suspend interrupt */
if (val & (1UL << 17))
{
// USBD_Suspend();
}
/* resume interrupt */
else
{
}
USBHSD->DEVCMDSTAT |= (1UL << 25);
}
/* connect interrupt */
if (val & (1UL << 24))
{
USBHSD->DEVCMDSTAT |= (1UL << 24);
}
USBHSD->INTSTAT = USBHSD_INTSTAT_DEV_INT_MASK;
}
/* Start of Frame */
if (sts & USBHSD_INTSTAT_FRAME_INT_MASK)
{
USBHSD->INTSTAT = USBHSD_INTSTAT_FRAME_INT_MASK;
}
/* EndPoint Interrupt */
if (sts & 0x3FF)
{
val = USBHSD->DEVCMDSTAT;
if (sts & USBHSD_INTSTAT_EP0OUT_MASK)
{
if(val & USBHSD_DEVCMDSTAT_SETUP_MASK) /* SETUP */
{
usbd_ep0_setup_handler();
}
else
{
usbd_ep0_out_handler();
}
}
if (sts & USBHSD_INTSTAT_EP0IN_MASK) /* EP0 in token */
{
usbd_ep0_in_handler();
}
else /* other ep */
{
for(num = 2; num < (MAX_EP_COUNT*2); num++)
{
if (sts & (1UL << num))
{
#if defined(RTT)
msd_msg_t msg;
msg.param = num;
msg.exec = NULL;
rt_mq_send(msd_mq, &msg, sizeof(msg));
#else
usbd_data_ep_handler(num/2, num % 2);
#endif
}
}
}
}
}
uint32_t ep_read(uint8_t ep, uint8_t *buf, uint8_t data01)
{
return USBD_ReadEP(ep, buf);
}
uint32_t ep_write(uint8_t ep, uint8_t *buf, uint32_t len, uint8_t data01)
{
ep |= 0x80; /* write ep must use IN EP */
return USBD_WriteEP (ep, buf, len);
}
uint32_t set_addr(uint8_t addr)
{
USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DEV_ADDR(addr);
return 0;
}
uint32_t ep_clear_feature(uint8_t ep)
{
USBD_TRACE("ep clear features\r\n");
return 0;
}
uint32_t detach(void)
{
USBD_TRACE("detach\r\n");
return 0;
}
const struct usbd_ops_t ops;
void ch_usb_init(struct usbd_t *h)
{
static struct usbd_ops_t ops;
ops.ep_read = ep_read;
ops.ep_write = ep_write;
ops.set_addr = set_addr;
ops.ep_config = usbd_config_ep;
ops.ep_clear_feature = ep_clear_feature;
usbd_init(h, &ops);
}
void USB1_IRQHandler (void)
{
USBD_IRQHandler();
}
|
yandld/lpc_uart_server
|
user_space_test_program/usbttytest_multiply.c
|
<reponame>yandld/lpc_uart_server<gh_stars>1-10
#include <pthread.h>
#include <stdio.h>
#include <sys/time.h>
#include <string.h>
#include <unistd.h>
#include <termios.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/select.h>
#include <errno.h>
#include <signal.h>
#define PORT_NUMBERS 10
#define BULK_IN_SIZE 253
#define BULK_OUT_SIZE 253
#define EVERY_PRINT 64
typedef struct
{
int index;
int baud;
int loopback;
const char* readFileName;
const char* writeFileName;
const char* devName;
const char* loopbackAttrName;
}ReadWriteThreadArgument;
typedef struct
{
int fd;
int index;
const char* sendFileName;
}WriteThreadArgument;
void startThread(void* p,int isWrite);
void serial_init(int fd,int baud)
{
struct termios options;
int realbaud = 0;
tcgetattr(fd,&options);
options.c_cflag |= ( CLOCAL | CREAD);
options.c_cflag &= ~CSIZE;
options.c_cflag &= ~CRTSCTS;
options.c_cflag |= CS8;
options.c_cflag &= ~CSTOPB;
options.c_cflag |= IGNPAR;
options.c_iflag &= ~(BRKINT | ICRNL | INPCK| ISTRIP | IXON);
options.c_oflag = 0;
options.c_lflag = 0;
switch (baud) {
case 4800:
realbaud = B4800;
break;
case 9600:
realbaud = B9600;
break;
case 38400:
realbaud = B38400;
break;
case 115200:
realbaud = B115200;
break;
default:
realbaud = B115200;
}
cfsetispeed(&options,realbaud);
cfsetospeed(&options,realbaud);
tcsetattr(fd,TCSANOW,&options);
}
void * writePort(void* data)
{
WriteThreadArgument* p = (WriteThreadArgument*) data;
int readfd = 0;
int everyinfo = EVERY_PRINT * 1024;
int everysum = 0;
int writefd = p->fd;
int index = p->index;
const char* sendfile = p->sendFileName;
unsigned char buffer[BULK_OUT_SIZE];
unsigned char tmpbuf[1024];
int length = 0;
int writelength = 0;
int readsum = 0;
int writesum = 0;
int filesize = 0;
fd_set rset,wset;
FD_ZERO(&rset);
FD_ZERO(&wset);
FD_SET(writefd,&wset);
FD_SET(readfd,&rset);
readfd = open(sendfile,O_RDWR);
if(-1 == readfd)
{
printf("can't open the %s file\n",sendfile);
pthread_exit(NULL);
}
filesize = lseek(readfd,0,SEEK_END);
lseek(readfd,0,SEEK_SET);
while((length = read(readfd,buffer,sizeof(buffer))) != 0)
{
readsum += length;
everysum += length;
while(length)
{
select(writefd + 1,NULL,&wset,NULL,NULL);
if(FD_ISSET(writefd,&wset))
{
writelength= write(writefd,buffer,length);
if(writelength == -1 && errno == EAGAIN)
{
continue;
}
length -= writelength;
writesum += writelength;
}
}
/* if(4 == index )
{
memmove(tmpbuf,buffer,writelength);
tmpbuf[writelength] = '\0';
printf("%s\n",tmpbuf);
}*/
fflush(stdout);
printf("have send data percent %d%%\r",(int)((readsum*100.0)/filesize));
}
printf("--%d--port read sum is %d -- send sum is %d\n",index,readsum,writesum);
pthread_exit(NULL);
}
void * readWritePort(void* data)
{
ReadWriteThreadArgument* p = (ReadWriteThreadArgument*) data;
WriteThreadArgument writeThreadArguments;
const char* devname = p->devName;
const char* sendfile = p->readFileName;
const char* recvfile = p->writeFileName;
const char* loopattrname = p->loopbackAttrName;
int index = p->index;
int loopback = p->loopback;
int devfd = 0;
int loopfd = 0;
int sendfd = 0;
int recvfd = 0;
int readsum = 0;
int recvsum = 0;
int writelength = 0;
int length = 0;
fd_set rset, wset;
char loopbool[2] = {'0','1'};
unsigned char buffer[BULK_IN_SIZE] = {0};
devfd = open(devname,O_RDWR | O_NOCTTY | O_NDELAY);
if(-1 == devfd)
{
printf("can't open the %s port\n",devname);
pthread_exit(NULL);
}
serial_init(devfd,p->baud);
//setup the loopback
loopfd = open(loopattrname,O_RDWR);
if(-1 == loopfd)
{
printf("can't open the loopback attribute %s\n",loopattrname);
pthread_exit(NULL);
}
if(loopback)
{
length = write(loopfd,&loopbool[1],1);
}
else
{
length = write(loopfd,&loopbool[0],1);
}
if(-1 == length)
{
printf("write the loopback attribute failed\n");
pthread_exit(NULL);
}
recvfd = open(recvfile, O_RDWR | O_CREAT | O_TRUNC,0666);
if(-1 == recvfd)
{
printf("can't open the %s file\n",recvfile);
pthread_exit(NULL);
}
/*send the data to index port*/
writeThreadArguments.fd = devfd;
writeThreadArguments.index = index;
writeThreadArguments.sendFileName = sendfile;
startThread(&writeThreadArguments,1);
FD_ZERO(&rset);
FD_ZERO(&wset);
FD_SET(devfd,&rset);
FD_SET(recvfd,&wset);
while(1)
{
if(select(devfd+1,&rset,NULL,NULL,NULL) < 0)
{
printf("--%d-- port select error\n",index);
pthread_exit(NULL);
}
if(FD_ISSET(devfd,&rset))
{
length = read(devfd,buffer,sizeof(buffer));
if(length == 0)
{
break;
}
readsum += length;
while(length)
{
select(recvfd + 1,NULL,&wset,NULL,NULL);
if(FD_ISSET(recvfd,&wset))
{
writelength= write(recvfd,buffer,length);
length -= writelength;
recvsum += writelength;
}
}
}
}
printf("--%d--port read sum is %d -- recv sum is %d\n",index,readsum,recvsum);
pthread_exit(NULL);
}
void startThread(void* p,int isWrite)
{
pthread_t tid;
int index = 0;
int ret = 0;
if(!isWrite)
{
index = ((ReadWriteThreadArgument*)p)->index;
ret = pthread_create(&tid, NULL, readWritePort, p);
}
else
{
index = ((WriteThreadArgument*)p)->index;
ret = pthread_create(&tid, NULL, writePort, p);
}
if(ret)
{
printf("create the %d thread failed\n",index);
pthread_exit(&ret);
}
}
int main(int argc, const char* argv[])
{
/**
*
* some variables
*
*/
int i = 0;
int loopback = 0;
int base = 0;
int numbers = 0;
int baud = 0;
int fds[PORT_NUMBERS] = {0};
char devnames[PORT_NUMBERS][13] = {0};
char recvfiles[PORT_NUMBERS][20] = {0};
char loopbackattr[PORT_NUMBERS][64] = {0};
unsigned char mainloop[5];
ReadWriteThreadArgument arguments[PORT_NUMBERS] = {0};
/**
* some arguments basic deal
*/
if(argc < 7)
{
printf("format is %s <base> <numbers> <sendfilename> <recvfilename> <baud0|1> <loopback>\n",argv[0]);
exit(-1);
}
base = atoi(argv[1]);
numbers = atoi(argv[2]);
baud = atoi(argv[5]);
loopback = atoi(argv[6]);
if(numbers > 10 || numbers < 1)
{
printf("please input the reasonable digital from 1 to 10\n");
exit(-1);
}
for(i = base; i < numbers ; i++)
{
snprintf(devnames[i],13,"/dev/ttyUSB%d",i);
sprintf(recvfiles[i],"%s%d",argv[4],i);
snprintf(loopbackattr[i],39,"/sys/class/tty/ttyUSB%d/device/loopback",i);
// printf("devname is %s\n",devnames[i]);
// printf("recvfile is %s\n",recvfiles[i]);
arguments[i].index = i;
arguments[i].baud = baud;
arguments[i].loopback = loopback;
arguments[i].devName = devnames[i];
arguments[i].readFileName = argv[3];
arguments[i].writeFileName = recvfiles[i];
arguments[i].loopbackAttrName = loopbackattr[i];
startThread(&arguments[i],0);
}
/**
* exit from main thread
*/
for(;;)
{
scanf("%s",mainloop);
if(strncmp(mainloop,"exit",4) == 0)
{
kill(getpid(),SIGINT);
}
}
return 0;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/inc/usbd_msc.h
|
<filename>mcu_source/Libraries/utilities/chusb/inc/usbd_msc.h
#ifndef __USBD_MSC_H_
#define __USBD_MSC_H_
#include <stdint.h>
#include <usbd.h>
#include <usb_common.h>
struct usbd_msc_callback_t
{
uint32_t (*msc_read_sector) (uint32_t block, uint8_t *buf, uint32_t block_cnt);
uint32_t (*msc_write_sector)(uint32_t block, uint8_t *buf, uint32_t block_cnt);
uint32_t (*msc_get_disk_info)(uint32_t *total_block_cnt, uint32_t *block_size);
};
void usbd_msc_set_cb(struct usbd_msc_callback_t *cb);
void usbd_msc_init(struct usbd_t *h);
uint32_t msc_standard_request_to_intf_handler(struct usbd_t *h);
uint32_t msc_class_request_handler(struct usbd_t *h);
uint32_t msc_data_ep_handler(uint8_t ep, uint8_t dir);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/LPC8xx.h
|
<reponame>yandld/lpc_uart_server
// Attention please!
// This is the header file for the LPC80x product family only.
/****************************************************************************
* $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
* Project: NXP LPC8xx software example
*
* Description:
* CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
* NXP LPC800 Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#ifndef __LPC8xx_H__
#define __LPC8xx_H__
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
This file defines all structures and symbols for LPC8xx:
- Registers and bitfields
- peripheral base address
- PIO definitions
@{
*/
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
Configuration of the Cortex-M0+ Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** LPC80x Specific Interrupt Numbers ********************************************************/
SPI0_IRQn = 0, /*!< SPI0 */
DAC0_IRQn = 2, /*!< DAC0 Interrupt */
UART0_IRQn = 3, /*!< USART0 */
UART1_IRQn = 4, /*!< USART1 */
I2C1_IRQn = 7, /*!< I2C1 */
I2C0_IRQn = 8, /*!< I2C0 */
MRT_IRQn = 10, /*!< MRT */
CMP_IRQn = 11, /*!< Analog Comparator */
WDT_IRQn = 12, /*!< WDT */
BOD_IRQn = 13, /*!< BOD */
FLASH_IRQn = 14, /*!< FLASH */
WKT_IRQn = 15, /*!< WKT Interrupt */
ADC_SEQA_IRQn = 16, /*!< ADC Seq. A */
ADC_SEQB_IRQn = 17, /*!< ADC Seq. B */
ADC_THCMP_IRQn = 18, /*!< ADC Thresh Comp */
ADC_OVR_IRQn = 19, /*!< ADC overrun */
CTIMER0_IRQn = 23, /*!< Timer 0 Interrupt */
PININT0_IRQn = 24, /*!< External Interrupt 0 */
PININT1_IRQn = 25, /*!< External Interrupt 1 */
PININT2_IRQn = 26, /*!< External Interrupt 2 */
PININT3_IRQn = 27, /*!< External Interrupt 3 */
PININT4_IRQn = 28, /*!< External Interrupt 4 */
PININT5_IRQn = 29, /*!< External Interrupt 5 */
PININT6_IRQn = 30, /*!< External Interrupt 6 */
PININT7_IRQn = 31, /*!< External Interrupt 7 */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0PLUS_REV 0x0001
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/*@}*/ /* end of group LPC8xx_CMSIS */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
#include "system_LPC8xx.h" /* System Header */
#if defined ( __CC_ARM )
#pragma anon_unions // This is needed by the Keil compiler
#endif
/******************************************************************************/
/* Device Specific Peripheral Registers structures */
/******************************************************************************/
//------------- System Control (SYSCON) --------------------------------------
typedef struct
{
__IO uint32_t SYSMEMREMAP ; ///< (0x000) System memory remap
__IO uint32_t RESERVED0[8] ; ///< (0x004 - 0x020)
__IO uint32_t LPOSCCTRL ; ///< (0x024) Low power oscillator control
__IO uint32_t FROOSCCTRL ; ///< (0x028) FRO oscillator control
__IO uint32_t RESERVED2[3] ; ///< (0x02C - 0x034)
__IO uint32_t SYSRSTSTAT ; ///< (0x038) System reset status 0
__IO uint32_t RESERVED3[5] ; ///< (0x03C - 0x04C)
__IO uint32_t MAINCLKSEL ; ///< (0x050) Main clock source select
__IO uint32_t MAINCLKUEN ; ///< (0x054) Main clock source update enable
__IO uint32_t SYSAHBCLKDIV ; ///< (0x058) System clock divider
__IO uint32_t RESERVED4[2] ; ///< (0x05C - 0x060)
__IO uint32_t ADCCLKSEL ; ///< (0x064) ADC clock source select
__IO uint32_t ADCCLKDIV ; ///< (0x068) ADC clock divider
__IO uint32_t RESERVED5[4] ; ///< (0x06C - 0x078)
__IO uint32_t LPOSCCLKEN ; ///< (0x07C)
union {
__IO uint32_t SYSAHBCLKCTRL[2] ;
struct {
__IO uint32_t SYSAHBCLKCTRL0 ; ///< (0x080) System clock group 0 control
__IO uint32_t SYSAHBCLKCTRL1 ; ///< (0x084) System clock group 1 control
};
};
union {
__IO uint32_t PRESETCTRL[2] ;
struct {
__IO uint32_t PRESETCTRL0 ; ///< (0x088) Peripheral reset group 0 control
__IO uint32_t PRESETCTRL1 ; ///< (0x08C) Peripheral reset group 1 control
};
};
union {
__IO uint32_t FCLKSEL[11] ;
struct {
__IO uint32_t UART0CLKSEL ; ///< (0x090) FCLK0 clock source select
__IO uint32_t UART1CLKSEL ; ///< (0x094) FCLK1 clock source select
__IO uint32_t unimp2CLKSEL ; ///< (0x098) FCLK2 clock source select
__IO uint32_t unimp3CLKSEL ; ///< (0x09C) FCLK3 clock source select
__IO uint32_t unimp4CLKSEL ; ///< (0x0A0) FCLK4 clock source select
__IO uint32_t I2C0CLKSEL ; ///< (0x0A4) FCLK5 clock source select
__IO uint32_t I2C1CLKSEL ; ///< (0x0A8) FCLK6 clock source select
__IO uint32_t unimp7CLKSEL ; ///< (0x0AC) FCLK7 clock source select
__IO uint32_t unimp8CLKSEL ; ///< (0x0B0) FCLK8 clock source select
__IO uint32_t SPI0CLKSEL ; ///< (0x0B4) FCLK9 clock source select
__IO uint32_t unimp10CLKSEL ; ///< (0x0B8) FCLK10 clock source select
};
};
__IO uint32_t RESERVED6[5] ; ///< (0x0BC - 0x0CC)
__IO uint32_t FRG0DIV ; ///< (0x0D0) Fractional generator divider value
__IO uint32_t FRG0MULT ; ///< (0x0D4) Fractional generator multiplier value
__IO uint32_t FRG0CLKSEL ; ///< (0x0D8) FRG0 clock source select
__IO uint32_t RESERVED8[5] ; ///< (0x0DC - 0x0EC)
__IO uint32_t CLKOUTSEL ; ///< (0x0F0) CLKOUT clock source select
__IO uint32_t CLKOUTDIV ; ///< (0x0F4) CLKOUT clock divider
__IO uint32_t RESERVED10[2] ; ///< (0x0F8 - 0x0FC)
__I uint32_t PIOPORCAP0 ; ///< (0x100) POR captured PIO0 status 0
__I uint32_t RESERVED11[19] ; ///< (0x104 - 0x14C)
__IO uint32_t BODCTRL ; ///< (0x150) Brown-Out Detect
__IO uint32_t SYSTCKCAL ; ///< (0x154) System tick counter calibration
__IO uint32_t RESERVED12[6] ; ///< (0x158 - 0x16C)
__IO uint32_t IRQLATENCY ; ///< (0x170) IRQ delay. Allows trade-off between interrupt latency and determinism.
__IO uint32_t NMISRC ; ///< (0x174) NMI Source Control
union {
__IO uint32_t PINTSEL[8] ;
struct {
__IO uint32_t PINTSEL0 ; ///< (0x178) GPIO Pin Interrupt Select 0
__IO uint32_t PINTSEL1 ; ///< (0x17C) GPIO Pin Interrupt Select 1
__IO uint32_t PINTSEL2 ; ///< (0x180) GPIO Pin Interrupt Select 2
__IO uint32_t PINTSEL3 ; ///< (0x184) GPIO Pin Interrupt Select 3
__IO uint32_t PINTSEL4 ; ///< (0x188) GPIO Pin Interrupt Select 4
__IO uint32_t PINTSEL5 ; ///< (0x18C) GPIO Pin Interrupt Select 5
__IO uint32_t PINTSEL6 ; ///< (0x190) GPIO Pin Interrupt Select 6
__IO uint32_t PINTSEL7 ; ///< (0x194) GPIO Pin Interrupt Select 7
};
};
__IO uint32_t RESERVED13[27] ; ///< (0x198 - 0x200)
__IO uint32_t STARTERP0 ; ///< (0x204) Start logic 0 pin wake-up enable
__IO uint32_t RESERVED14[3] ; ///< (0x208 - 0x210)
__IO uint32_t STARTERP1 ; ///< (0x214) Start logic 1 interrupt wake-up enable
__IO uint32_t RESERVED15[6] ; ///< (0x218 - 0x22C)
__IO uint32_t PDSLEEPCFG ; ///< (0x230) Power-down states in deep-sleep mode
__IO uint32_t PDAWAKECFG ; ///< (0x234) Power-down states for wake-up from deep-sleep
__IO uint32_t PDRUNCFG ; ///< (0x238) Power configuration
__IO uint32_t RESERVED16[111] ; ///< (0x23C - 0x3F4)
__I uint32_t DEVICE_ID ; ///< (0x3F8) Device ID
} LPC_SYSCON_TypeDef;
// ---------------- IOCON ----------------
typedef struct {
__IO uint32_t PIO0_17; // 0x00
__IO uint32_t PIO0_13; // 0x04
__IO uint32_t PIO0_12; // 0x08
__IO uint32_t PIO0_5; // 0x0C
__IO uint32_t PIO0_4; // 0x10
__IO uint32_t PIO0_3; // 0x14
__IO uint32_t PIO0_2; // 0x18
__IO uint32_t PIO0_11; // 0x1C
__IO uint32_t PIO0_10; // 0x20
__IO uint32_t PIO0_16; // 0x24
__IO uint32_t PIO0_15; // 0x28
__IO uint32_t PIO0_1; // 0x2C
__IO uint32_t PIO0_21; // 0x30
__IO uint32_t PIO0_9; // 0x34
__IO uint32_t PIO0_8; // 0x38
__IO uint32_t PIO0_7; // 0x3C
__IO uint32_t PIO0_29; // 0x40
__IO uint32_t PIO0_0; // 0x44
__IO uint32_t PIO0_14; // 0x48
__IO uint32_t PIO0_28; // 0x4C
__IO uint32_t PIO0_27; // 0x50
__IO uint32_t PIO0_26; // 0x54
__IO uint32_t PIO0_20; // 0x58
__IO uint32_t PIO0_30; // 0x5C
__IO uint32_t PIO0_19; // 0x60
__IO uint32_t PIO0_25; // 0x64
__IO uint32_t PIO0_24; // 0x68
__IO uint32_t PIO0_23; // 0x6C
__IO uint32_t PIO0_22; // 0x70
__IO uint32_t PIO0_18; // 0x74
} LPC_IOCON_TypeDef;
//------------- Power Management Unit (PMU) --------------------------
typedef struct
{
__IO uint32_t PCON; //!< Offset: 0x000 Power control Register (R/W)
__IO uint32_t GPREG0; //!< Offset: 0x004 General purpose Register 0 (R/W)
__IO uint32_t GPREG1; //!< Offset: 0x008 General purpose Register 1 (R/W)
__IO uint32_t GPREG2; //!< Offset: 0x00C General purpose Register 2 (R/W)
__IO uint32_t GPREG3; //!< Offset: 0x010 General purpose Register 3 (R/W)
__IO uint32_t GPREG4; //!< Offset: 0x014 General purpose Register 4 (R/W)
__I uint32_t RESERVED[2]; // 0x18 - 0x1C
__IO uint32_t WUSRCREG; // 0x20
__IO uint32_t WUENAREG; // 0x24
} LPC_PMU_TypeDef;
//------------- Switch Matrix (SWM) --------------------------
typedef struct
{
union {
__IO uint32_t PINASSIGN[10];
struct {
__IO uint32_t PINASSIGN0; // 0x000
__IO uint32_t PINASSIGN1; // 0x004
__IO uint32_t PINASSIGN2; // 0x008
__IO uint32_t PINASSIGN3; // 0x00C
__IO uint32_t PINASSIGN4; // 0x010
__IO uint32_t PINASSIGN5; // 0x014
__IO uint32_t PINASSIGN6; // 0x018
__IO uint32_t PINASSIGN7; // 0x01C
__IO uint32_t PINASSIGN8; // 0x020
__IO uint32_t PINASSIGN9; // 0x024
};
};
__I uint32_t Reserved0[86]; // 0x028 - 0x17C
__IO uint32_t PINASSIGN_4PIN; // 0x180
__I uint32_t Reserved1[15]; // 0x184 - 0x1BC
__IO uint32_t PINENABLE0; // 0x1C0
__IO uint32_t PINENABLE1; // 0x1C4
} LPC_SWM_TypeDef;
// ------------------------------------------------------------------------------------------------
// ----- General Purpose I/O (GPIO) -----
// ------------------------------------------------------------------------------------------------
typedef struct {
__IO uint8_t B0[32]; // 0x00 - 0x1F Byte pin registers P0.0 - P0.31
__IO uint8_t B1[32]; // 0x20 - 0x3F Byte pin registers P1.0 - P1.31
__I uint8_t Reserved0[4032]; // 0x40 - 0xFFF
__IO uint32_t W0[32]; // 0x1000 - 0x107C Word pin registers P0.0 - P0.31
__IO uint32_t W1[32]; // 0x1080 - 0x10FC Word pin registers P1.0 - P1.31
__I uint32_t Reserved1[960]; // 0x1100 - 0x1FFC (960d = 0x3c0)
union {
__IO uint32_t DIR[2]; // 0x2000 - 0x2004
struct {
__IO uint32_t DIR0; // 0x2000
__IO uint32_t DIR1; // 0x2004
};
};
__I uint32_t Reserved2[30]; // 0x2008 - 0x207C
union {
__IO uint32_t MASK[2]; // 0x2080 - 0x2084
struct {
__IO uint32_t MASK0; // 0x2080
__IO uint32_t MASK1; // 0x2084
};
};
__I uint32_t Reserved3[30]; // 0x2088 - 0x20FC
union {
__IO uint32_t PIN[2]; // 0x2100 - 0x2104
struct {
__IO uint32_t PIN0; // 0x2100
__IO uint32_t PIN1; // 0x2104
};
};
__I uint32_t Reserved4[30]; // 0x2108 - 0x217C
union {
__IO uint32_t MPIN[2]; // 0x22180 - 0x2184
struct {
__IO uint32_t MPIN0; // 0x2180
__IO uint32_t MPIN1; // 0x2184
};
};
__I uint32_t Reserved5[30]; // 0x2188 - 0x21FC
union {
__IO uint32_t SET[2]; // 0x2200 -0x2204
struct {
__IO uint32_t SET0; // 0x2200
__IO uint32_t SET1; // 0x2204
};
};
__I uint32_t Reserved6[30]; // 0x2208 - 0x227C
union {
__O uint32_t CLR[2]; // 0x2280 - 0x2284
struct {
__O uint32_t CLR0; // 0x2280
__O uint32_t CLR1; // 0x2284
};
};
__I uint32_t Reserved7[30]; // 0x2288 - 0x22FC
union {
__O uint32_t NOT[2]; // 0x2300 - 0x2304
struct {
__O uint32_t NOT0; // 0x2300
__O uint32_t NOT1; // 0x2304
};
};
__I uint32_t Reserved8[30]; // 0x2308 - 0x237C
union {
__O uint32_t DIRSET[2]; // 0x2380 - 0x2384
struct {
__O uint32_t DIRSET0; // 0x2380
__O uint32_t DIRSET1; // 0x2384
};
};
__I uint32_t Reserved9[30]; // 0x2388 - 0x23FC
union {
__O uint32_t DIRCLR[2]; // 0x2400 - 0x2404
struct {
__O uint32_t DIRCLR0; // 0x2400
__O uint32_t DIRCLR1; // 0x2404
};
};
__I uint32_t Reserved10[30]; // 0x2408 - 0x247C
union {
__O uint32_t DIRNOT[2]; // 0x2480 - 0x2484
struct {
__O uint32_t DIRNOT0; // 0x2480
__O uint32_t DIRNOT1; // 0x2484
};
};
} LPC_GPIO_PORT_TypeDef;
// ------------------------------------------------------------------------------------------------
// ----- Pin Interrupts and Pattern Match (PIN_INT) -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
__IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
__IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
__IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
__IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
__IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
} LPC_PIN_INT_TypeDef;
//------------- CRC Engine (CRC) -----------------------------------------
typedef struct
{
__IO uint32_t MODE;
__IO uint32_t SEED;
union {
__I uint32_t SUM;
__O uint32_t WR_DATA;
};
} LPC_CRC_TypeDef;
//------------- Comparator (CMP) --------------------------------------------------
typedef struct { /*!< (@ 0x40024000) CMP Structure */
__IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
__IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
} LPC_CMP_TypeDef;
//------------- Self Wakeup Timer (WKT) --------------------------------------------------
typedef struct { /*!< (@ 0x40028000) WKT Structure */
__IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
uint32_t Reserved[2];
__IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
} LPC_WKT_TypeDef;
//------------- Multi-Rate Timer (MRT) --------------------------------------------------
typedef struct {
__IO uint32_t INTVAL;
__IO uint32_t TIMER;
__IO uint32_t CTRL;
__IO uint32_t STAT;
} MRT_Channel_cfg_Type;
typedef struct {
MRT_Channel_cfg_Type Channel[4];
uint32_t Reserved0[45]; // Address offsets = 0x40 - 0xF0
__IO uint32_t IDLE_CH;
__IO uint32_t IRQ_FLAG;
} LPC_MRT_TypeDef;
//------------- USART -----------
typedef struct
{
__IO uint32_t CFG;
__IO uint32_t CTL;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR;
__I uint32_t RXDAT;
__I uint32_t RXDATSTAT;
__IO uint32_t TXDAT;
__IO uint32_t BRG;
__I uint32_t INTSTAT;
__IO uint32_t OSR;
__IO uint32_t ADDR;
} LPC_USART_TypeDef;
//------------- SPI -----------------------
typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t DLY;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR; /* 0x10 */
__I uint32_t RXDAT;
__IO uint32_t TXDATCTL;
__IO uint32_t TXDAT;
__IO uint32_t TXCTL; /* 0x20 */
__IO uint32_t DIV;
__I uint32_t INTSTAT;
} LPC_SPI_TypeDef;
//------------- I2C -------------------------------
typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR;
__IO uint32_t TIMEOUT; /* 0x10 */
union {
__IO uint32_t CLKDIV;
__IO uint32_t DIV;
};
__IO uint32_t INTSTAT;
uint32_t Reserved0[1];
__IO uint32_t MSTCTL; /* 0x20 */
__IO uint32_t MSTTIME;
__IO uint32_t MSTDAT;
uint32_t Reserved1[5];
__IO uint32_t SLVCTL; /* 0x40 */
__IO uint32_t SLVDAT;
__IO uint32_t SLVADR0;
__IO uint32_t SLVADR1;
__IO uint32_t SLVADR2; /* 0x50 */
__IO uint32_t SLVADR3;
__IO uint32_t SLVQUAL0;
uint32_t Reserved2[9];
__I uint32_t MONRXDAT; /* 0x80 */
} LPC_I2C_TypeDef;
//------------------- Standard Counter/Timer (CTIMER) ---------------------
typedef struct {
__IO uint32_t IR; // 0x00
__IO uint32_t TCR; // 0x04
__IO uint32_t TC; // 0x08
__IO uint32_t PR; // 0x0C
__IO uint32_t PC; // 0x10
__IO uint32_t MCR; // 0x14
__IO uint32_t MR[4]; // 0x18 - 0x24
__IO uint32_t CCR; // 0x28
__IO uint32_t CR[4]; // 0x2C - 0x38
__IO uint32_t EMR; // 0x3C
__I uint32_t RESERVED0[12]; // 0x40 - 0x6C
__IO uint32_t CTCR; // 0x70
__IO uint32_t PWMC; // 0x74
} LPC_TIMER_TypeDef;
//------------- Widowed Watchdog Timer (WWDT) -----------------------------------------
typedef struct
{
__IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
__IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
__O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
__I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
__IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
__IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
} LPC_WWDT_TypeDef;
//------------- ADC -----------------------------------------
typedef struct {
__IO uint32_t CTRL; // 0x0
uint32_t RESERVED0; // 0x4
__IO uint32_t SEQA_CTRL; // 0x8
__IO uint32_t SEQB_CTRL; // 0xC
__IO uint32_t SEQA_GDAT; // 0x10
__IO uint32_t SEQB_GDAT; // 0x14
uint32_t RESERVED1[2]; // 0x18 - 0x1C
__IO uint32_t DAT[12]; // 0x20 - 0x4C
__IO uint32_t THR0_LOW; // 0x50
__IO uint32_t THR1_LOW; // 0x54
__IO uint32_t THR0_HIGH; // 0x58
__IO uint32_t THR1_HIGH; // 0x5C
__IO uint32_t CHAN_THRSEL; // 0x60
__IO uint32_t INTEN; // 0x64
__IO uint32_t FLAGS; // 0x68
__IO uint32_t TRM; // 0x6C
} LPC_ADC_TypeDef;
//------------- DAC ----------------
typedef struct {
__IO uint32_t CR; // 0x00
__IO uint32_t CTRL; // 0x04
__IO uint32_t CNTVAL; // 0x08
} LPC_DAC_TypeDef;
//------------- PLU ----------------
#define NUM_LUTS 26
#define GAP1 ((0x800 - 4*((8*NUM_LUTS)-1)) / 4) - 1
#define GAP2 ((0x900 - (0x800 + 4*(NUM_LUTS-1))) / 4) - 1
typedef struct {
__IO uint32_t INP0_MUX;
__IO uint32_t INP1_MUX;
__IO uint32_t INP2_MUX;
__IO uint32_t INP3_MUX;
__IO uint32_t INP4_MUX;
__I uint32_t reserved[3];
} LPC_PLU_INREG_T;
typedef struct {
LPC_PLU_INREG_T LUT[NUM_LUTS]; // 0x000 - 0x33C = 0x0 through (26x8 - 1)*4 = (0x1Ax8 - 1)*4 = 0x33C
__I uint32_t reserved1[GAP1]; // 0x340 - 0x7FC 304 = (0x800 - 0x340)/4
__IO uint32_t LUT_TRUTH[NUM_LUTS]; // 0x800 - 0x864
__I uint32_t reserved2[GAP2]; // 0x868 - 0x8FC 38
__O uint32_t OUTPUTS; // 0x900
__I uint32_t reserved3[191]; // 0x904 - 0xBFC
__IO uint32_t OUTPUT_MUX[8]; // 0xC00 - 0xC1C
} LPC_PLU_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
// Base addresses
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_ROM_BASE (0x1FFF0000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_AHB_BASE (0x50000000UL)
// APB0 peripherals
#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
// (LPC_APB0_BASE + 0x10000)
#define LPC_DAC0_BASE (LPC_APB0_BASE + 0x14000)
// (LPC_APB0_BASE + 0x18000)
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
// (LPC_APB0_BASE + 0x28000)
// (LPC_APB0_BASE + 0x2C000)
// (LPC_APB0_BASE + 0x30000)
// (LPC_APB0_BASE + 0x34000)
#define LPC_CTIMER0_BASE (LPC_APB0_BASE + 0x38000)
// (LPC_APB0_BASE + 0x38000)
#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x50000)
#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x54000)
#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
// (LPC_APB0_BASE + 0x5C000)
// (LPC_APB0_BASE + 0x60000)
#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
// (LPC_APB0_BASE + 0x6C000)
// (LPC_APB0_BASE + 0x70000)
// (LPC_APB0_BASE + 0x74000)
// AHB peripherals
#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
// (LPC_AHB_BASE + 0x04000)
// (LPC_AHB_BASE + 0x08000)
// (LPC_AHB_BASE + 0x0C000)
// (LPC_AHB_BASE + 0x10000)
#define LPC_GPIO_PORT_BASE (0xA0000000)
#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
/******************************************************************************/
/* Peripheral declarations */
/******************************************************************************/
#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
#define LPC_DAC0 ((LPC_DAC_TypeDef *) LPC_DAC0_BASE )
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
#define LPC_CTIMER0 ((LPC_TIMER_TypeDef *) LPC_CTIMER0_BASE )
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
///////////////////////////////////////////////////////////////////////////////
// Other chip-specific macro definitions (a.k.a. the chip.h section)
///////////////////////////////////////////////////////////////////////////////
// ACMP_I-to-IOCON mapping
#define ACMP_I1_PORT PIO0_0
#define ACMP_I2_PORT PIO0_1
#define ACMP_I3_PORT PIO0_14
#define ACMP_I4_PORT PIO0_16
#define ACMP_I5_PORT PIO0_21
// For looping through the pad controls
#define NUM_IOCON_SLOTS 30
#ifdef __cplusplus
}
#endif
#endif /* __LPC8xx_H__ */
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/examples/master402/master402_od.h
|
/* File generated by gen_cfile.py. Should not be modified. */
#ifndef MASTER402_H
#define MASTER402_H
#include "data.h"
/* Prototypes of function provided by object dictionnary */
UNS32 master402_valueRangeTest (UNS8 typeValue, void * value);
const indextable * master402_scanIndexOD (CO_Data *d, UNS16 wIndex, UNS32 * errorCode);
/* Master node data struct */
extern CO_Data master402_Data;
extern UNS16 control_word_6040; /* Mapped at index 0x2000, subindex 0x00*/
extern INTEGER8 modes_of_operation_6060; /* Mapped at index 0x2001, subindex 0x00*/
extern INTEGER32 target_position_607a; /* Mapped at index 0x2002, subindex 0x00*/
extern UNS32 profile_velocity_6081; /* Mapped at index 0x2003, subindex 0x00*/
extern UNS16 status_word_6041; /* Mapped at index 0x2004, subindex 0x00*/
extern INTEGER32 position_actual_value_6063; /* Mapped at index 0x2005, subindex 0x00*/
extern INTEGER32 velocity_actual_value_606c; /* Mapped at index 0x2006, subindex 0x00*/
#endif // MASTER402_H
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/system_MK02F12810.h
|
/*
** ###################################################################
** Processors: MK02FN128VFM10
** MK02FN64VFM10
** MK02FN128VLF10
** MK02FN64VLF10
** MK02FN128VLH10
** MK02FN64VLH10
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K02P64M100SFARM, Rev. 0, February 14, 2014
** Version: rev. 0.1, 2014-02-24
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2014 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 0.1 (2014-02-24)
** Initial version
**
** ###################################################################
*/
/*!
* @file MK02F12810
* @version 0.1
* @date 2014-02-24
* @brief Device specific configuration file for MK02F12810 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_MK02F12810_H_
#define SYSTEM_MK02F12810_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define DISABLE_WDOG 1
#ifndef CLOCK_SETUP
#define CLOCK_SETUP 0
#endif
/* Predefined clock setups
0 ... Default part configuration
Multipurpose Clock Generator (MCG) in FEI mode.
Reference clock source for MCG module: Slow internal reference clock
Core clock = 20.97152MHz
Bus clock = 20.97152MHz
1 ... Maximum achievable clock frequency configuration
Multipurpose Clock Generator (MCG) in FEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 80MHz
Bus clock = 40MHz
2 ... Internally clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPI mode.
Reference clock source for MCG module: Fast internal reference clock
Core clock = 4MHz
Bus clock = 4MHz
3 ... Externally clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 4MHz
Bus clock = 4MHz
*/
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#if (CLOCK_SETUP == 0)
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MK02F12810_H_) */
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/led_thread.c
|
#include "rtthread.h"
#include "rtdevice.h"
#include "gpio.h"
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
typedef struct
{
uint8_t port;
uint8_t pin;
} led_t;
led_t leds[] =
{
{HW_GPIO3, 6},
{HW_GPIO3, 7},
{HW_GPIO3, 8},
{HW_GPIO3, 9},
{HW_GPIO3, 10},
{HW_GPIO3, 11},
{HW_GPIO3, 12},
{HW_GPIO3, 13},
{HW_GPIO3, 14},
{HW_GPIO3, 15},
};
static uint32_t led_flag = 0;
static uint32_t led_idle_cnt[10];
void set_led(uint8_t idx, uint8_t val)
{
led_flag |= (1<<idx);
}
void thread_led_entry(void* parameter)
{
int i;
/* init led pins */
GPIO_Init(HW_GPIO1, 1, kGPIO_OPPH);
for(i=0; i<ARRAY_SIZE(leds); i++)
{
GPIO_Init(leds[i].port, leds[i].pin, kGPIO_OPPH);
}
while(1)
{
for(i=0; i<ARRAY_SIZE(leds); i++)
{
if(led_flag & (1<<i))
{
GPIO_PinWrite(leds[i].port, leds[i].pin, 0);
led_idle_cnt[i]++;
}
if(led_idle_cnt[i] > 2)
{
led_idle_cnt[i] = 0;
led_flag &= ~(1<<i);
GPIO_PinWrite(leds[i].port, leds[i].pin, 1);
}
}
GPIO_PinToggle(HW_GPIO1, 1);
rt_thread_delay(rt_tick_from_millisecond(10));
}
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/bsp/lpc546xx/drv_spi.c
|
<reponame>yandld/lpc_uart_server<filename>mcu_source/Libraries/utilities/rtthread/bsp/lpc546xx/drv_spi.c
#include <rthw.h>
#include <stdio.h>
#include <rtthread.h>
#include "common.h"
#include "spi.h"
#include "gpio.h"
#include <rtdevice.h>
#include <drivers/spi.h>
static struct rt_spi_bus bus;
#define SPI10_CS P1out(26)
#define SPI21_CS P1out(0)
struct lpc_spi_device
{
struct rt_spi_device rt_spi_dev;
uint8_t bus_instance;
uint8_t cs_port;
uint8_t cs_pin;
uint8_t cs;
};
static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
{
return RT_EOK;
}
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
{
rt_uint32_t size = message->length;
const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf;
struct lpc_spi_device* dev = (struct lpc_spi_device*)device->parent.user_data;
/* take cs */
switch(dev->cs)
{
case 0:
SPI10_CS = 0;
break;
case 1:
SPI21_CS = 0;
break;
}
SPI_ReadWriteFIFO(dev->bus_instance, recv_ptr, (uint8_t*)send_ptr, size);
if(message->cs_release)
{
switch(dev->cs)
{
case 0:
SPI10_CS = 1;
break;
case 1:
SPI21_CS = 1;
break;
}
}
return message->length;
}
static struct rt_spi_ops ops =
{
configure,
xfer
};
int rt_hw_spi_bus_init(const char *name)
{
uint32_t instance;
sscanf(name, "spi%d", &instance);
SPI_Init(instance, 1000*1000*48);
switch(instance)
{
case 1:
SetPinMux(HW_GPIO0, 29, 1);
SetPinMux(HW_GPIO0, 30, 1);
SetPinMux(HW_GPIO1, 10, 4); /* SCK */
break;
case 2:
// SetPinMux(HW_GPIO1, 23, 1);
// SetPinMux(HW_GPIO1, 24, 1);
// SetPinMux(HW_GPIO1, 25, 1);
// SetPinMux(HW_GPIO0, 8, 1);
// SetPinMux(HW_GPIO0, 9, 1);
// SetPinMux(HW_GPIO0, 10, 1);
break;
}
return rt_spi_bus_register(&bus, name, &ops);
}
void rt_hw_spi_init(const char *spi_bus_name, const char *spi_device_name, uint32_t cs)
{
struct lpc_spi_device* lpc_spi_dev = rt_malloc(sizeof(struct lpc_spi_device));
sscanf(spi_bus_name, "spi%d", (int*)&lpc_spi_dev->bus_instance);
lpc_spi_dev->cs = cs;
switch(lpc_spi_dev->cs)
{
case 0:
switch(lpc_spi_dev->bus_instance)
{
case 2:
GPIO_Init(HW_GPIO1, 26, kGPIO_OPPH);
lpc_spi_dev->cs_port = HW_GPIO1;
lpc_spi_dev->cs_pin = 26;
break;
}
break;
case 1:
GPIO_Init(HW_GPIO1, 0, kGPIO_OPPH);
lpc_spi_dev->cs_port = HW_GPIO1;
lpc_spi_dev->cs_pin = 0;
break;
}
rt_spi_bus_attach_device(&lpc_spi_dev->rt_spi_dev, spi_device_name, spi_bus_name, (void*)lpc_spi_dev);
}
INIT_BOARD_EXPORT(rt_hw_spi_init);
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/inc/usb_common.h
|
<filename>mcu_source/Libraries/utilities/chusb/inc/usb_common.h
#ifndef __CHLIB_USB_COMMON_H_
#define __CHLIB_USB_COMMON_H_
#include <stdint.h>
#include <stdbool.h>
#if !defined(CH_OK)
#define CH_OK (0)
#endif
#if !defined(CH_ERR)
#define CH_ERR (1)
#endif
#define USB_CLASS_DEVICE 0x00
#define USB_CLASS_AUDIO 0x01
#define USB_CLASS_CDC 0x02
#define USB_CLASS_HID 0x03
#define USB_CLASS_PHYSICAL 0x05
#define USB_CLASS_IMAGE 0x06
#define USB_CLASS_PRINTER 0x07
#define USB_CLASS_MASS_STORAGE 0x08
#define USB_CLASS_HUB 0x09
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_SMART_CARD 0x0b
#define USB_CLASS_SECURITY 0x0d
#define USB_CLASS_VIDEO 0x0e
#define USB_CLASS_HEALTHCARE 0x0f
#define USB_CLASS_DIAG_DEVICE 0xdc
#define USB_CLASS_WIRELESS 0xe0
#define USB_CLASS_MISC 0xef
#define USB_CLASS_APP_SPECIFIC 0xfe
#define USB_CLASS_VEND_SPECIFIC 0xff
#define USB_REQ_TYPE_STANDARD 0x00
#define USB_REQ_TYPE_CLASS 0x20
#define USB_REQ_TYPE_VENDOR 0x40
#define USB_REQ_TYPE_MASK 0x60
#define USB_REQ_TYPE_DIR_OUT 0x00
#define USB_REQ_TYPE_DIR_IN 0x80
#define USB_REQ_TYPE_DEVICE 0x00
#define USB_REQ_TYPE_INTERFACE 0x01
#define USB_REQ_TYPE_ENDPOINT 0x02
#define USB_REQ_TYPE_OTHER 0x03
#define USB_REQ_TYPE_RECIPIENT_MASK 0x1f
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
#define USB_REQ_SET_ENCRYPTION 0x0D
#define USB_REQ_GET_ENCRYPTION 0x0E
#define USB_REQ_RPIPE_ABORT 0x0E
#define USB_REQ_SET_HANDSHAKE 0x0F
#define USB_REQ_RPIPE_RESET 0x0F
#define USB_REQ_GET_HANDSHAKE 0x10
#define USB_REQ_SET_CONNECTION 0x11
#define USB_REQ_SET_SECURITY_DATA 0x12
#define USB_REQ_GET_SECURITY_DATA 0x13
#define USB_REQ_SET_WUSB_DATA 0x14
#define USB_REQ_LOOPBACK_DATA_WRITE 0x15
#define USB_REQ_LOOPBACK_DATA_READ 0x16
#define USB_REQ_SET_INTERFACE_DS 0x17
#define USB_DESC_LENGTH_DEVICE 0x12
#define USB_DESC_LENGTH_CONFIG 0x9
#define USB_DESC_LENGTH_IAD 0x8
#define USB_DESC_LENGTH_STRING 0x4
#define USB_DESC_LENGTH_INTERFACE 0x9
#define USB_DESC_LENGTH_ENDPOINT 0x7
#define USB_DESC_TYPE_DEVICE 0x01
#define USB_DESC_TYPE_CONFIGURATION 0x02
#define USB_DESC_TYPE_STRING 0x03
#define USB_DESC_TYPE_INTERFACE 0x04
#define USB_DESC_TYPE_ENDPOINT 0x05
#define USB_DESC_TYPE_DEVICEQUALIFIER 0x06
#define USB_DESC_TYPE_OTHERSPEED 0x07
#define USB_DESC_TYPE_IAD 0x0b
#define USB_DESC_TYPE_HID 0x21
#define USB_DESC_TYPE_REPORT 0x22
#define USB_DESC_TYPE_PHYSICAL 0x23
#define USB_DESC_TYPE_HUB 0x29
/* bRequest: USB Standard Request Codes */
#define USB_REQUEST_GET_STATUS (0)
#define USB_REQUEST_CLEAR_FEATURE (1)
#define USB_REQUEST_SET_FEATURE (3)
#define USB_REQUEST_SET_ADDRESS (5)
#define USB_REQUEST_GET_DESCRIPTOR (6)
#define USB_REQUEST_SET_DESCRIPTOR (7)
#define USB_REQUEST_GET_CONFIGURATION (8)
#define USB_REQUEST_SET_CONFIGURATION (9)
#define USB_REQUEST_GET_INTERFACE (10)
#define USB_REQUEST_SET_INTERFACE (11)
#define USB_REQUEST_SYNC_FRAME (12)
#define WBVAL(x) (x & 0xFF),((x >> 8) & 0xFF)
/* USB Specification Release Number */
#define USB_VERSION_2_0 (0x0200)
typedef struct
{
uint32_t tag;
const char* name;
const uint8_t *buf;
uint16_t len;
}desc_t;
struct udevice_descriptor
{
uint8_t bLength;
uint8_t type;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
};
struct uconfig_descriptor
{
uint8_t bLength;
uint8_t type;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t MaxPower;
uint8_t data[256];
};
typedef struct uconfig_descriptor* ucfg_desc_t;
struct usb_qualifier_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB; // TODO: big-endian.
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint8_t bNumConfigurations;
uint8_t bRESERVED;
} __attribute__ ((packed));
struct ustring_descriptor
{
uint8_t bLength;
uint8_t type;
uint8_t String[64];
};
typedef struct ustring_descriptor* ustr_desc_t;
struct uinterface_descriptor
{
uint8_t bLength;
uint8_t type;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
};
typedef struct uinterface_descriptor* uintf_desc_t;
/* Interface Association Descriptor (IAD) */
struct uiad_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bFirstInterface;
uint8_t bInterfaceCount;
uint8_t bFunctionClass;
uint8_t bFunctionSubClass;
uint8_t bFunctionProtocol;
uint8_t iFunction;
};
typedef struct uiad_descriptor* uiad_desc_t;
struct uendpoint_descriptor
{
uint8_t bLength;
uint8_t type;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint16_t wMaxPacketSize;
uint8_t bInterval;
};
typedef struct uendpoint_descriptor* uep_desc_t;
/* usb stanrd request */
struct urequest
{
uint8_t request_type;
uint8_t request;
uint16_t value;
uint16_t index;
uint16_t length;
};
struct ucdc_line_coding
{
uint32_t dwDTERate;
uint8_t bCharFormat;
uint8_t bParityType;
uint8_t bDataBits;
};
//! @brief Computes the number of elements in an array.
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
/*
* the define related to mass storage
*/
#define USBREQ_GET_MAX_LUN 0xfe
#define USBREQ_MASS_STORAGE_RESET 0xff
#define SIZEOF_CSW 0x0d
#define SIZEOF_CBW 0x1f
#define SIZEOF_INQUIRY_CMD 0x24
#define SIZEOF_MODE_SENSE_6 0x4
#define SIZEOF_READ_CAPACITIES 0xc
#define SIZEOF_READ_CAPACITY 0x8
#define SIZEOF_REQUEST_SENSE 0x12
#define CBWFLAGS_DIR_M 0x80
#define CBWFLAGS_DIR_IN 0x80
#define CBWFLAGS_DIR_OUT 0x00
#define SCSI_TEST_UNIT_READY 0x00
#define SCSI_REQUEST_SENSE 0x03
#define SCSI_INQUIRY_CMD 0x12
#define SCSI_ALLOW_REMOVAL 0x1e
#define SCSI_MODE_SENSE_6 0x1a
#define SCSI_START_STOP 0x1b
#define SCSI_READ_CAPACITIES 0x23
#define SCSI_READ_CAPACITY 0x25
#define SCSI_READ_10 0x28
#define SCSI_WRITE_10 0x2a
#define SCSI_VERIFY_10 0x2f
#define CBW_SIGNATURE 0x43425355
#define CSW_SIGNATURE 0x53425355
#define CBW_TAG_VALUE 0x12345678
struct ustorage_cbw
{
uint32_t signature;
uint32_t tag;
uint32_t xfer_len;
uint8_t dflags;
uint8_t lun;
uint8_t cb_len;
uint8_t cb[16];
};
typedef struct ustorage_cbw* ustorage_cbw_t;
struct ustorage_csw
{
uint32_t signature;
uint32_t tag;
int32_t data_reside;
uint8_t status;
};
typedef struct ustorage_csw* ustorage_csw_t;
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/examples/master402/master402_od.c
|
/* File generated by gen_cfile.py. Should not be modified. */
#include "master402_od.h"
/**************************************************************************/
/* Declaration of mapped variables */
/**************************************************************************/
UNS16 control_word_6040 = 0x0; /* Mapped at index 0x2000, subindex 0x00 */
INTEGER8 modes_of_operation_6060 = 0x0; /* Mapped at index 0x2001, subindex 0x00 */
INTEGER32 target_position_607a = 0x0; /* Mapped at index 0x2002, subindex 0x00 */
UNS32 profile_velocity_6081 = 0x0; /* Mapped at index 0x2003, subindex 0x00 */
UNS16 status_word_6041 = 0x0; /* Mapped at index 0x2004, subindex 0x00 */
INTEGER32 position_actual_value_6063 = 0x0; /* Mapped at index 0x2005, subindex 0x00 */
INTEGER32 velocity_actual_value_606c = 0x0; /* Mapped at index 0x2006, subindex 0x00 */
/**************************************************************************/
/* Declaration of value range types */
/**************************************************************************/
#define valueRange_EMC 0x9F /* Type for index 0x1003 subindex 0x00 (only set of value 0 is possible) */
UNS32 master402_valueRangeTest (UNS8 typeValue, void * value)
{
switch (typeValue) {
case valueRange_EMC:
if (*(UNS8*)value != (UNS8)0) return OD_VALUE_RANGE_EXCEEDED;
break;
}
return 0;
}
/**************************************************************************/
/* The node id */
/**************************************************************************/
/* node_id default value.*/
UNS8 master402_bDeviceNodeId = 0x00;
/**************************************************************************/
/* Array of message processing information */
const UNS8 master402_iam_a_slave = 0;
TIMER_HANDLE master402_heartBeatTimers[1] = {TIMER_NONE};
/*
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
OBJECT DICTIONARY
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
*/
/* index 0x1000 : Device Type. */
UNS32 master402_obj1000 = 0x0; /* 0 */
subindex master402_Index1000[] =
{
{ RO, uint32, sizeof (UNS32), (void*)&master402_obj1000, NULL }
};
/* index 0x1001 : Error Register. */
UNS8 master402_obj1001 = 0x0; /* 0 */
subindex master402_Index1001[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_obj1001, NULL }
};
/* index 0x1003 : Pre-defined Error Field */
UNS8 master402_highestSubIndex_obj1003 = 0; /* number of subindex - 1*/
UNS32 master402_obj1003[] =
{
0x0 /* 0 */
};
subindex master402_Index1003[] =
{
{ RW, valueRange_EMC, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1003, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&master402_obj1003[0], NULL }
};
/* index 0x1005 : SYNC COB ID. */
UNS32 master402_obj1005 = 0x80; /* 128 */
subindex master402_Index1005[] =
{
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1005, NULL }
};
/* index 0x1006 : Communication / Cycle Period. */
UNS32 master402_obj1006 = 0x2710; /* 10000 */
subindex master402_Index1006[] =
{
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1006, NULL }
};
/* index 0x100C : Guard Time */
UNS16 master402_obj100C = 0x0; /* 0 */
/* index 0x100D : Life Time Factor */
UNS8 master402_obj100D = 0x0; /* 0 */
/* index 0x1014 : Emergency COB ID. */
UNS32 master402_obj1014 = 0x80; /* 128 */
subindex master402_Index1014[] =
{
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1014, NULL }
};
/* index 0x1016 : Consumer Heartbeat Time. */
UNS8 master402_highestSubIndex_obj1016 = 1; /* number of subindex - 1*/
UNS32 master402_obj1016[] =
{
0x0 /* 0 */
};
subindex master402_Index1016[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1016, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1016[0], NULL }
};
/* index 0x1017 : Producer Heartbeat Time. */
UNS16 master402_obj1017 = 0x0; /* 0 */
subindex master402_Index1017[] =
{
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1017, NULL }
};
/* index 0x1018 : Identity. */
UNS8 master402_highestSubIndex_obj1018 = 4; /* number of subindex - 1*/
UNS32 master402_obj1018_Vendor_ID = 0x123456; /* 1193046 */
UNS32 master402_obj1018_Product_Code = 0x1; /* 1 */
UNS32 master402_obj1018_Revision_Number = 0x1; /* 1 */
UNS32 master402_obj1018_Serial_Number = 0x12345678; /* 305419896 */
subindex master402_Index1018[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1018, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&master402_obj1018_Vendor_ID, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&master402_obj1018_Product_Code, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&master402_obj1018_Revision_Number, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&master402_obj1018_Serial_Number, NULL }
};
/* index 0x1200 : Server SDO Parameter. */
UNS8 master402_highestSubIndex_obj1200 = 2; /* number of subindex - 1*/
UNS32 master402_obj1200_COB_ID_Client_to_Server_Receive_SDO = 0x600; /* 1536 */
UNS32 master402_obj1200_COB_ID_Server_to_Client_Transmit_SDO = 0x580; /* 1408 */
subindex master402_Index1200[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1200, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&master402_obj1200_COB_ID_Client_to_Server_Receive_SDO, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&master402_obj1200_COB_ID_Server_to_Client_Transmit_SDO, NULL }
};
/* index 0x1280 : Client SDO 1 Parameter. */
UNS8 master402_highestSubIndex_obj1280 = 3; /* number of subindex - 1*/
UNS32 master402_obj1280_COB_ID_Client_to_Server_Transmit_SDO = 0x602; /* 1538 */
UNS32 master402_obj1280_COB_ID_Server_to_Client_Receive_SDO = 0x582; /* 1410 */
UNS8 master402_obj1280_Node_ID_of_the_SDO_Server = 0x2; /* 2 */
subindex master402_Index1280[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1280, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1280_COB_ID_Client_to_Server_Transmit_SDO, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1280_COB_ID_Server_to_Client_Receive_SDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1280_Node_ID_of_the_SDO_Server, NULL }
};
/* index 0x1400 : Receive PDO 1 Parameter. */
UNS8 master402_highestSubIndex_obj1400 = 6; /* number of subindex - 1*/
UNS32 master402_obj1400_COB_ID_used_by_PDO = 0x182; /* 386 */
UNS8 master402_obj1400_Transmission_Type = 0x1; /* 1 */
UNS16 master402_obj1400_Inhibit_Time = 0x0; /* 0 */
UNS8 master402_obj1400_Compatibility_Entry = 0x0; /* 0 */
UNS16 master402_obj1400_Event_Timer = 0x0; /* 0 */
UNS8 master402_obj1400_SYNC_start_value = 0x0; /* 0 */
subindex master402_Index1400[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1400, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1400_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1400_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1400_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1400_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1400_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1400_SYNC_start_value, NULL }
};
/* index 0x1401 : Receive PDO 2 Parameter. */
UNS8 master402_highestSubIndex_obj1401 = 6; /* number of subindex - 1*/
UNS32 master402_obj1401_COB_ID_used_by_PDO = 0x282; /* 642 */
UNS8 master402_obj1401_Transmission_Type = 0x1; /* 1 */
UNS16 master402_obj1401_Inhibit_Time = 0x0; /* 0 */
UNS8 master402_obj1401_Compatibility_Entry = 0x0; /* 0 */
UNS16 master402_obj1401_Event_Timer = 0x0; /* 0 */
UNS8 master402_obj1401_SYNC_start_value = 0x0; /* 0 */
subindex master402_Index1401[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1401, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1401_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1401_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1401_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1401_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1401_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1401_SYNC_start_value, NULL }
};
/* index 0x1600 : Receive PDO 1 Mapping. */
UNS8 master402_highestSubIndex_obj1600 = 2; /* number of subindex - 1*/
UNS32 master402_obj1600[] =
{
0x20040010, /* 537133072 */
0x20050020 /* 537198624 */
};
subindex master402_Index1600[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1600, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1600[0], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1600[1], NULL }
};
/* index 0x1601 : Receive PDO 2 Mapping. */
UNS8 master402_highestSubIndex_obj1601 = 1; /* number of subindex - 1*/
UNS32 master402_obj1601[] =
{
0x20060020 /* 537264160 */
};
subindex master402_Index1601[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1601, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1601[0], NULL }
};
/* index 0x1800 : Transmit PDO 1 Parameter. */
UNS8 master402_highestSubIndex_obj1800 = 6; /* number of subindex - 1*/
UNS32 master402_obj1800_COB_ID_used_by_PDO = 0x202; /* 514 */
UNS8 master402_obj1800_Transmission_Type = 0x1; /* 1 */
UNS16 master402_obj1800_Inhibit_Time = 0x0; /* 0 */
UNS8 master402_obj1800_Compatibility_Entry = 0x0; /* 0 */
UNS16 master402_obj1800_Event_Timer = 0x0; /* 0 */
UNS8 master402_obj1800_SYNC_start_value = 0x0; /* 0 */
subindex master402_Index1800[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1800, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1800_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1800_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1800_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1800_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1800_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1800_SYNC_start_value, NULL }
};
/* index 0x1801 : Transmit PDO 2 Parameter. */
UNS8 master402_highestSubIndex_obj1801 = 6; /* number of subindex - 1*/
UNS32 master402_obj1801_COB_ID_used_by_PDO = 0x302; /* 770 */
UNS8 master402_obj1801_Transmission_Type = 0x1; /* 1 */
UNS16 master402_obj1801_Inhibit_Time = 0x0; /* 0 */
UNS8 master402_obj1801_Compatibility_Entry = 0x0; /* 0 */
UNS16 master402_obj1801_Event_Timer = 0x0; /* 0 */
UNS8 master402_obj1801_SYNC_start_value = 0x0; /* 0 */
subindex master402_Index1801[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1801, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1801_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1801_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1801_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1801_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&master402_obj1801_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&master402_obj1801_SYNC_start_value, NULL }
};
/* index 0x1A00 : Transmit PDO 1 Mapping. */
UNS8 master402_highestSubIndex_obj1A00 = 2; /* number of subindex - 1*/
UNS32 master402_obj1A00[] =
{
0x20000010, /* 536870928 */
0x20010008 /* 536936456 */
};
subindex master402_Index1A00[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1A00, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1A00[0], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1A00[1], NULL }
};
/* index 0x1A01 : Transmit PDO 2 Mapping. */
UNS8 master402_highestSubIndex_obj1A01 = 2; /* number of subindex - 1*/
UNS32 master402_obj1A01[] =
{
0x20020020, /* 537002016 */
0x20030020 /* 537067552 */
};
subindex master402_Index1A01[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&master402_highestSubIndex_obj1A01, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1A01[0], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&master402_obj1A01[1], NULL }
};
/* index 0x2000 : Mapped variable control_word_6040 */
subindex master402_Index2000[] =
{
{ RW, uint16, sizeof (UNS16), (void*)&control_word_6040, NULL }
};
/* index 0x2001 : Mapped variable modes_of_operation_6060 */
subindex master402_Index2001[] =
{
{ RW, int8, sizeof (INTEGER8), (void*)&modes_of_operation_6060, NULL }
};
/* index 0x2002 : Mapped variable target_position_607a */
subindex master402_Index2002[] =
{
{ RW, int32, sizeof (INTEGER32), (void*)&target_position_607a, NULL }
};
/* index 0x2003 : Mapped variable profile_velocity_6081 */
subindex master402_Index2003[] =
{
{ RW, uint32, sizeof (UNS32), (void*)&profile_velocity_6081, NULL }
};
/* index 0x2004 : Mapped variable status_word_6041 */
subindex master402_Index2004[] =
{
{ RW, uint16, sizeof (UNS16), (void*)&status_word_6041, NULL }
};
/* index 0x2005 : Mapped variable position_actual_value_6063 */
subindex master402_Index2005[] =
{
{ RW, int32, sizeof (INTEGER32), (void*)&position_actual_value_6063, NULL }
};
/* index 0x2006 : Mapped variable velocity_actual_value_606c */
subindex master402_Index2006[] =
{
{ RW, int32, sizeof (INTEGER32), (void*)&velocity_actual_value_606c, NULL }
};
/**************************************************************************/
/* Declaration of pointed variables */
/**************************************************************************/
const indextable master402_objdict[] =
{
{ (subindex*)master402_Index1000,sizeof(master402_Index1000)/sizeof(master402_Index1000[0]), 0x1000},
{ (subindex*)master402_Index1001,sizeof(master402_Index1001)/sizeof(master402_Index1001[0]), 0x1001},
{ (subindex*)master402_Index1005,sizeof(master402_Index1005)/sizeof(master402_Index1005[0]), 0x1005},
{ (subindex*)master402_Index1006,sizeof(master402_Index1006)/sizeof(master402_Index1006[0]), 0x1006},
{ (subindex*)master402_Index1014,sizeof(master402_Index1014)/sizeof(master402_Index1014[0]), 0x1014},
{ (subindex*)master402_Index1016,sizeof(master402_Index1016)/sizeof(master402_Index1016[0]), 0x1016},
{ (subindex*)master402_Index1017,sizeof(master402_Index1017)/sizeof(master402_Index1017[0]), 0x1017},
{ (subindex*)master402_Index1018,sizeof(master402_Index1018)/sizeof(master402_Index1018[0]), 0x1018},
{ (subindex*)master402_Index1200,sizeof(master402_Index1200)/sizeof(master402_Index1200[0]), 0x1200},
{ (subindex*)master402_Index1280,sizeof(master402_Index1280)/sizeof(master402_Index1280[0]), 0x1280},
{ (subindex*)master402_Index1400,sizeof(master402_Index1400)/sizeof(master402_Index1400[0]), 0x1400},
{ (subindex*)master402_Index1401,sizeof(master402_Index1401)/sizeof(master402_Index1401[0]), 0x1401},
{ (subindex*)master402_Index1600,sizeof(master402_Index1600)/sizeof(master402_Index1600[0]), 0x1600},
{ (subindex*)master402_Index1601,sizeof(master402_Index1601)/sizeof(master402_Index1601[0]), 0x1601},
{ (subindex*)master402_Index1800,sizeof(master402_Index1800)/sizeof(master402_Index1800[0]), 0x1800},
{ (subindex*)master402_Index1801,sizeof(master402_Index1801)/sizeof(master402_Index1801[0]), 0x1801},
{ (subindex*)master402_Index1A00,sizeof(master402_Index1A00)/sizeof(master402_Index1A00[0]), 0x1A00},
{ (subindex*)master402_Index1A01,sizeof(master402_Index1A01)/sizeof(master402_Index1A01[0]), 0x1A01},
{ (subindex*)master402_Index2000,sizeof(master402_Index2000)/sizeof(master402_Index2000[0]), 0x2000},
{ (subindex*)master402_Index2001,sizeof(master402_Index2001)/sizeof(master402_Index2001[0]), 0x2001},
{ (subindex*)master402_Index2002,sizeof(master402_Index2002)/sizeof(master402_Index2002[0]), 0x2002},
{ (subindex*)master402_Index2003,sizeof(master402_Index2003)/sizeof(master402_Index2003[0]), 0x2003},
{ (subindex*)master402_Index2004,sizeof(master402_Index2004)/sizeof(master402_Index2004[0]), 0x2004},
{ (subindex*)master402_Index2005,sizeof(master402_Index2005)/sizeof(master402_Index2005[0]), 0x2005},
{ (subindex*)master402_Index2006,sizeof(master402_Index2006)/sizeof(master402_Index2006[0]), 0x2006},
};
const indextable * master402_scanIndexOD (CO_Data *d, UNS16 wIndex, UNS32 * errorCode)
{
int i;
switch(wIndex){
case 0x1000: i = 0;break;
case 0x1001: i = 1;break;
case 0x1005: i = 2;break;
case 0x1006: i = 3;break;
case 0x1014: i = 4;break;
case 0x1016: i = 5;break;
case 0x1017: i = 6;break;
case 0x1018: i = 7;break;
case 0x1200: i = 8;break;
case 0x1280: i = 9;break;
case 0x1400: i = 10;break;
case 0x1401: i = 11;break;
case 0x1600: i = 12;break;
case 0x1601: i = 13;break;
case 0x1800: i = 14;break;
case 0x1801: i = 15;break;
case 0x1A00: i = 16;break;
case 0x1A01: i = 17;break;
case 0x2000: i = 18;break;
case 0x2001: i = 19;break;
case 0x2002: i = 20;break;
case 0x2003: i = 21;break;
case 0x2004: i = 22;break;
case 0x2005: i = 23;break;
case 0x2006: i = 24;break;
default:
*errorCode = OD_NO_SUCH_OBJECT;
return NULL;
}
*errorCode = OD_SUCCESSFUL;
return &master402_objdict[i];
}
/*
* To count at which received SYNC a PDO must be sent.
* Even if no pdoTransmit are defined, at least one entry is computed
* for compilations issues.
*/
s_PDO_status master402_PDO_status[2] = {s_PDO_status_Initializer,s_PDO_status_Initializer};
const quick_index master402_firstIndex = {
8, /* SDO_SVR */
9, /* SDO_CLT */
10, /* PDO_RCV */
12, /* PDO_RCV_MAP */
14, /* PDO_TRS */
16 /* PDO_TRS_MAP */
};
const quick_index master402_lastIndex = {
8, /* SDO_SVR */
9, /* SDO_CLT */
11, /* PDO_RCV */
13, /* PDO_RCV_MAP */
15, /* PDO_TRS */
17 /* PDO_TRS_MAP */
};
const UNS16 master402_ObjdictSize = sizeof(master402_objdict)/sizeof(master402_objdict[0]);
CO_Data master402_Data = CANOPEN_NODE_DATA_INITIALIZER(master402);
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/spifi.c
|
/**
******************************************************************************
* @file spifi.c
* @author YANDLD
* @version V3.0.0
* @date 2016.5.28
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "spifi.h"
#include <string.h>
#include "common.h"
#if defined(SPIFI0) && defined(LPC54608)
void SPIFI_Reset(void)
{
/* reset */
SPIFI0->STAT = SPIFI_STAT_RESET_MASK;
/* Wait for the RESET flag cleared by HW */
while (SPIFI0->STAT & SPIFI_STAT_RESET_MASK) {};
}
void SPIFI_Init(uint32_t baud)
{
SYSCON->SPIFICLKSEL = SYSCON_SPIFICLKSEL_SEL(3); /* select SPIFI clock to kFROHfClock */
(GetClock(kFROHfClock) == 96*1000*1000)?(SYSCON->SPIFICLKDIV = SYSCON_SPIFICLKDIV_DIV(1)):(SYSCON->SPIFICLKDIV = SYSCON_SPIFICLKDIV_DIV(0));
/* enable clock */
#if defined(SYSCON_AHBCLKCTRL_SPIFI_MASK)
SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_SPIFI_MASK;
#endif
SPIFI_Reset();
/* Set time delay parameter */
SPIFI0->CTRL = SPIFI_CTRL_TIMEOUT(0xFFFF) | SPIFI_CTRL_CSHIGH(0x0F) | SPIFI_CTRL_D_PRFTCH_DIS(0) | SPIFI_CTRL_MODE3(0) | SPIFI_CTRL_PRFTCH_DIS(0) | SPIFI_CTRL_DUAL(0) | SPIFI_CTRL_RFCLK(1) | SPIFI_CTRL_FBCLK(1);
}
void SPIFI_SetCmd(spifi_command_t *cmd)
{
/* If SPIFI in memory mode, call reset function to abort memory mode */
if (SPIFI0->STAT& SPIFI_STAT_MCINIT_MASK)
{
SPIFI_Reset();
}
/* Wait for other command finished */
while (SPIFI0->STAT & SPIFI_STAT_CMD_MASK)
{
}
SPIFI0->CMD = SPIFI_CMD_DATALEN(cmd->dataLen) | SPIFI_CMD_POLL(0) | SPIFI_CMD_DOUT(cmd->direction) |
SPIFI_CMD_INTLEN(cmd->intermediateBytes) | SPIFI_CMD_FIELDFORM(cmd->format) |
SPIFI_CMD_FRAMEFORM(cmd->type) | SPIFI_CMD_OPCODE(cmd->opcode);
}
void SPIFI_SetMemoryCmd(spifi_command_t *cmd)
{
/* Wait for the CMD and MCINT flag all be 0 */
while (SPIFI0->STAT & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK)) {};
SPIFI0->MCMD = SPIFI_MCMD_POLL(0U) | SPIFI_MCMD_DOUT(0U) | SPIFI_MCMD_INTLEN(cmd->intermediateBytes) | SPIFI_MCMD_FIELDFORM(cmd->format) | SPIFI_MCMD_FRAMEFORM(cmd->type) | SPIFI_MCMD_OPCODE(cmd->opcode);
}
void QSPI_Init(qspi_flash_t * ctx, uint32_t freq)
{
SPIFI_Init(freq);
SPIFI_Reset();
SPIFI_SetMemoryCmd(&ctx->cmd[QSPI_CMD_READ_IDX]);
}
uint32_t QSPI_GetDeviceID(qspi_flash_t *ctx)
{
SPIFI_Reset();
SPIFI_SetCmd(&ctx->cmd[QSPI_READ_ID_IDX]);
while ((SPIFI0->STAT & SPIFI_STAT_INTRQ_MASK) == 0U) {};
return SPIFI0->DAT32;
}
uint32_t QSPI_WaitComplete(qspi_flash_t *ctx)
{
uint8_t val = 0;
/* Check WIP bit */
do
{
SPIFI_SetCmd(&ctx->cmd[QSPI_GET_STATUS_IDX]);
while ((SPIFI0->STAT & SPIFI_STAT_INTRQ_MASK) == 0U) {};
val = *((volatile uint8_t *)(&(SPIFI0->DAT8)));
} while (val & 0x1);
return CH_OK;
}
uint32_t QSPI_WritePage(qspi_flash_t *ctx, uint32_t addr, uint8_t *buf)
{
int i;
uint32_t *p = (uint32_t*)buf;
SPIFI_SetCmd(&ctx->cmd[QSPI_WRITE_ENABLE_IDX]);
SPIFI0->ADDR = (addr & 0x0FFFFFFF);
SPIFI_SetCmd(&ctx->cmd[QSPI_PROGRAM_PAGE_IDX]);
for (i=0; i<ctx->page_size/sizeof(uint32_t); i++)
{
SPIFI0->DAT32 = p[i];
}
QSPI_WaitComplete(ctx);
return CH_OK;
}
uint32_t QSPI_WriteSector(qspi_flash_t *ctx, uint32_t addr, uint8_t *buf)
{
uint32_t i;
for(i=0; i< (ctx->sector_size / ctx->page_size); i++)
{
QSPI_WritePage(ctx, addr + i*ctx->page_size, buf + i*ctx->page_size);
}
return CH_OK;
}
uint32_t QSPI_EraseSector(qspi_flash_t *ctx, uint32_t addr)
{
SPIFI_SetCmd(&ctx->cmd[QSPI_WRITE_ENABLE_IDX]);
SPIFI0->ADDR = (addr & 0x0FFFFFFF);
SPIFI_SetCmd(&ctx->cmd[QSPI_ERASE_SECTOR_IDX]);
return QSPI_WaitComplete(ctx);
}
void QSPI_SetReadMode(qspi_flash_t *ctx)
{
SPIFI_Reset();
SPIFI_SetMemoryCmd(&ctx->cmd[QSPI_CMD_READ_IDX]);
}
void QSPI_Read(qspi_flash_t *ctx, uint32_t addr, uint8_t *buf, uint32_t len)
{
QSPI_SetReadMode(ctx);
memcpy(buf, (uint8_t*)addr, len);
}
uint32_t QSPI_SectorTest(qspi_flash_t *ctx, uint32_t addr, uint8_t *buf)
{
int i;
uint8_t *p;
p = (uint8_t *)(addr);
SPIFI_Reset();
QSPI_EraseSector(ctx, addr);
QSPI_SetReadMode(ctx);
for(i=0; i<ctx->sector_size; i++)
{
if(p[i] != 0xFF)
{
printf("erase err %d\r\n", i);
return CH_ERR;
}
}
for(i=0; i<ctx->sector_size; i++)
{
buf[i] = i & 0xFF;
}
SPIFI_Reset();
QSPI_WriteSector(ctx, addr, buf);
/* memory read */
QSPI_SetReadMode(ctx);
for(i=0; i<ctx->sector_size; i++)
{
if(p[i] != (i & 0xFF))
{
printf("err read:%X shoud:%X\r\n", p[i], (i % 0xFF));
return CH_ERR;
}
}
return CH_OK;
}
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/slave_od/TaskSlave.c
|
/* File generated by gen_cfile.py. Should not be modified. */
#include "TaskSlave.h"
/**************************************************************************/
/* Declaration of mapped variables */
/**************************************************************************/
INTEGER16 ACC[] = /* Mapped at index 0x2000, subindex 0x01 - 0x03 */
{
0x1, /* 1 */
0x2, /* 2 */
0x320 /* 800 */
};
INTEGER16 GYR[] = /* Mapped at index 0x2001, subindex 0x01 - 0x03 */
{
0x1, /* 1 */
0x2, /* 2 */
0x3 /* 3 */
};
INTEGER16 EUL[] = /* Mapped at index 0x2003, subindex 0x01 - 0x03 */
{
0x2, /* 2 */
0x3, /* 3 */
0x4 /* 4 */
};
INTEGER16 QUAT[] = /* Mapped at index 0x2004, subindex 0x01 - 0x04 */
{
0x3E8, /* 1000 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
INTEGER32 CAN_BAUD = 0x7A120; /* Mapped at index 0x2100, subindex 0x00 */
INTEGER32 NodeID = 0x8; /* Mapped at index 0x2101, subindex 0x00 */
/**************************************************************************/
/* Declaration of value range types */
/**************************************************************************/
#define valueRange_EMC 0x9F /* Type for index 0x1003 subindex 0x00 (only set of value 0 is possible) */
UNS32 TaskSlave_valueRangeTest (UNS8 typeValue, void * value)
{
switch (typeValue) {
case valueRange_EMC:
if (*(UNS8*)value != (UNS8)0) return OD_VALUE_RANGE_EXCEEDED;
break;
}
return 0;
}
/**************************************************************************/
/* The node id */
/**************************************************************************/
/* node_id default value.*/
UNS8 TaskSlave_bDeviceNodeId = 0x00;
/**************************************************************************/
/* Array of message processing information */
const UNS8 TaskSlave_iam_a_slave = 1;
TIMER_HANDLE TaskSlave_heartBeatTimers[1] = {TIMER_NONE};
/*
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
OBJECT DICTIONARY
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
*/
/* index 0x1000 : Device Type. */
UNS32 TaskSlave_obj1000 = 0x20192; /* 131474 */
subindex TaskSlave_Index1000[] =
{
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1000, NULL }
};
/* index 0x1001 : Error Register. */
UNS8 TaskSlave_obj1001 = 0x0; /* 0 */
subindex TaskSlave_Index1001[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1001, NULL }
};
/* index 0x1002 : Manufacturer Status Register. */
UNS32 TaskSlave_obj1002 = 0x0; /* 0 */
subindex TaskSlave_Index1002[] =
{
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1002, NULL }
};
/* index 0x1003 : Pre-defined Error Field */
UNS8 TaskSlave_highestSubIndex_obj1003 = 0; /* number of subindex - 1*/
UNS32 TaskSlave_obj1003[] =
{
0x0 /* 0 */
};
subindex TaskSlave_Index1003[] =
{
{ RW, valueRange_EMC, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1003, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1003[0], NULL }
};
/* index 0x1005 : SYNC COB ID. */
UNS32 TaskSlave_obj1005 = 0x0; /* 0 */
subindex TaskSlave_Index1005[] =
{
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1005, NULL }
};
/* index 0x1006 : Communication / Cycle Period */
UNS32 TaskSlave_obj1006 = 0x0; /* 0 */
/* index 0x100C : Guard Time */
UNS16 TaskSlave_obj100C = 0x0; /* 0 */
/* index 0x100D : Life Time Factor */
UNS8 TaskSlave_obj100D = 0x0; /* 0 */
/* index 0x1014 : Emergency COB ID */
UNS32 TaskSlave_obj1014 = 0x80 + 0x00; /* 128 + NodeID */
/* index 0x1016 : Consumer Heartbeat Time. */
UNS8 TaskSlave_highestSubIndex_obj1016 = 1; /* number of subindex - 1*/
UNS32 TaskSlave_obj1016[] =
{
0x0 /* 0 */
};
subindex TaskSlave_Index1016[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1016, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1016[0], NULL }
};
/* index 0x1017 : Producer Heartbeat Time. */
UNS16 TaskSlave_obj1017 = 0x0; /* 0 */
subindex TaskSlave_Index1017[] =
{
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1017, NULL }
};
/* index 0x1018 : Identity. */
UNS8 TaskSlave_highestSubIndex_obj1018 = 4; /* number of subindex - 1*/
UNS32 TaskSlave_obj1018_Vendor_ID = 0x700; /* 1792 */
UNS32 TaskSlave_obj1018_Product_Code = 0x700; /* 1792 */
UNS32 TaskSlave_obj1018_Revision_Number = 0x1; /* 1 */
UNS32 TaskSlave_obj1018_Serial_Number = 0x9B939E8F; /* 2610142863 */
subindex TaskSlave_Index1018[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1018, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1018_Vendor_ID, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1018_Product_Code, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1018_Revision_Number, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1018_Serial_Number, NULL }
};
/* index 0x1200 : Server SDO Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1200 = 2; /* number of subindex - 1*/
UNS32 TaskSlave_obj1200_COB_ID_Client_to_Server_Receive_SDO = 0x600; /* 1536 */
UNS32 TaskSlave_obj1200_COB_ID_Server_to_Client_Transmit_SDO = 0x580; /* 1408 */
subindex TaskSlave_Index1200[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1200, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1200_COB_ID_Client_to_Server_Receive_SDO, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1200_COB_ID_Server_to_Client_Transmit_SDO, NULL }
};
/* index 0x1400 : Receive PDO 1 Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1400 = 6; /* number of subindex - 1*/
UNS32 TaskSlave_obj1400_COB_ID_used_by_PDO = 0x200; /* 512 */
UNS8 TaskSlave_obj1400_Transmission_Type = 0x0; /* 0 */
UNS16 TaskSlave_obj1400_Inhibit_Time = 0x0; /* 0 */
UNS8 TaskSlave_obj1400_Compatibility_Entry = 0x0; /* 0 */
UNS16 TaskSlave_obj1400_Event_Timer = 0x0; /* 0 */
UNS8 TaskSlave_obj1400_SYNC_start_value = 0x0; /* 0 */
subindex TaskSlave_Index1400[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1400, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1400_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1400_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1400_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1400_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1400_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1400_SYNC_start_value, NULL }
};
/* index 0x1401 : Receive PDO 2 Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1401 = 6; /* number of subindex - 1*/
UNS32 TaskSlave_obj1401_COB_ID_used_by_PDO = 0x300; /* 768 */
UNS8 TaskSlave_obj1401_Transmission_Type = 0x0; /* 0 */
UNS16 TaskSlave_obj1401_Inhibit_Time = 0x0; /* 0 */
UNS8 TaskSlave_obj1401_Compatibility_Entry = 0x0; /* 0 */
UNS16 TaskSlave_obj1401_Event_Timer = 0x0; /* 0 */
UNS8 TaskSlave_obj1401_SYNC_start_value = 0x0; /* 0 */
subindex TaskSlave_Index1401[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1401, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1401_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1401_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1401_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1401_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1401_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1401_SYNC_start_value, NULL }
};
/* index 0x1402 : Receive PDO 3 Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1402 = 6; /* number of subindex - 1*/
UNS32 TaskSlave_obj1402_COB_ID_used_by_PDO = 0x400; /* 1024 */
UNS8 TaskSlave_obj1402_Transmission_Type = 0x0; /* 0 */
UNS16 TaskSlave_obj1402_Inhibit_Time = 0x0; /* 0 */
UNS8 TaskSlave_obj1402_Compatibility_Entry = 0x0; /* 0 */
UNS16 TaskSlave_obj1402_Event_Timer = 0x0; /* 0 */
UNS8 TaskSlave_obj1402_SYNC_start_value = 0x0; /* 0 */
subindex TaskSlave_Index1402[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1402, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1402_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1402_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1402_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1402_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1402_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1402_SYNC_start_value, NULL }
};
/* index 0x1403 : Receive PDO 4 Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1403 = 6; /* number of subindex - 1*/
UNS32 TaskSlave_obj1403_COB_ID_used_by_PDO = 0x500; /* 1280 */
UNS8 TaskSlave_obj1403_Transmission_Type = 0x0; /* 0 */
UNS16 TaskSlave_obj1403_Inhibit_Time = 0x0; /* 0 */
UNS8 TaskSlave_obj1403_Compatibility_Entry = 0x0; /* 0 */
UNS16 TaskSlave_obj1403_Event_Timer = 0x0; /* 0 */
UNS8 TaskSlave_obj1403_SYNC_start_value = 0x0; /* 0 */
subindex TaskSlave_Index1403[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1403, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1403_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1403_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1403_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1403_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1403_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1403_SYNC_start_value, NULL }
};
/* index 0x1600 : Receive PDO 1 Mapping. */
UNS8 TaskSlave_highestSubIndex_obj1600 = 8; /* number of subindex - 1*/
UNS32 TaskSlave_obj1600[] =
{
0x20000110, /* 536871184 */
0x20000210, /* 536871440 */
0x20000310, /* 536871696 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
subindex TaskSlave_Index1600[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1600, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1600[0], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1600[1], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1600[2], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1600[3], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1600[4], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1600[5], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1600[6], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1600[7], NULL }
};
/* index 0x1601 : Receive PDO 2 Mapping. */
UNS8 TaskSlave_highestSubIndex_obj1601 = 8; /* number of subindex - 1*/
UNS32 TaskSlave_obj1601[] =
{
0x20010110, /* 536936720 */
0x20010210, /* 536936976 */
0x20010310, /* 536937232 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
subindex TaskSlave_Index1601[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1601, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1601[0], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1601[1], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1601[2], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1601[3], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1601[4], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1601[5], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1601[6], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1601[7], NULL }
};
/* index 0x1602 : Receive PDO 3 Mapping. */
UNS8 TaskSlave_highestSubIndex_obj1602 = 8; /* number of subindex - 1*/
UNS32 TaskSlave_obj1602[] =
{
0x20030110, /* 537067792 */
0x20030210, /* 537068048 */
0x20030310, /* 537068304 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
subindex TaskSlave_Index1602[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1602, NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1602[0], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1602[1], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1602[2], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1602[3], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1602[4], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1602[5], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1602[6], NULL },
{ RO, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1602[7], NULL }
};
/* index 0x1603 : Receive PDO 4 Mapping. */
UNS8 TaskSlave_highestSubIndex_obj1603 = 8; /* number of subindex - 1*/
UNS32 TaskSlave_obj1603[] =
{
0x20040110, /* 537133328 */
0x20040210, /* 537133584 */
0x20040310, /* 537133840 */
0x20040410, /* 537134096 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
subindex TaskSlave_Index1603[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1603, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1603[0], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1603[1], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1603[2], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1603[3], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1603[4], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1603[5], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1603[6], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1603[7], NULL }
};
/* index 0x1800 : Transmit PDO 1 Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1800 = 6; /* number of subindex - 1*/
UNS32 TaskSlave_obj1800_COB_ID_used_by_PDO = 0x180; /* 384 */
UNS8 TaskSlave_obj1800_Transmission_Type = 0xFE; /* 254 */
UNS16 TaskSlave_obj1800_Inhibit_Time = 0x40; /* 64 */
UNS8 TaskSlave_obj1800_Compatibility_Entry = 0x0; /* 0 */
UNS16 TaskSlave_obj1800_Event_Timer = 0xA; /* 10 */
UNS8 TaskSlave_obj1800_SYNC_start_value = 0x0; /* 0 */
subindex TaskSlave_Index1800[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1800, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1800_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1800_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1800_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1800_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1800_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1800_SYNC_start_value, NULL }
};
/* index 0x1801 : Transmit PDO 2 Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1801 = 6; /* number of subindex - 1*/
UNS32 TaskSlave_obj1801_COB_ID_used_by_PDO = 0x280; /* 640 */
UNS8 TaskSlave_obj1801_Transmission_Type = 0xFE; /* 254 */
UNS16 TaskSlave_obj1801_Inhibit_Time = 0x40; /* 64 */
UNS8 TaskSlave_obj1801_Compatibility_Entry = 0x0; /* 0 */
UNS16 TaskSlave_obj1801_Event_Timer = 0xA; /* 10 */
UNS8 TaskSlave_obj1801_SYNC_start_value = 0x0; /* 0 */
subindex TaskSlave_Index1801[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1801, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1801_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1801_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1801_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1801_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1801_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1801_SYNC_start_value, NULL }
};
/* index 0x1802 : Transmit PDO 3 Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1802 = 6; /* number of subindex - 1*/
UNS32 TaskSlave_obj1802_COB_ID_used_by_PDO = 0x380; /* 896 */
UNS8 TaskSlave_obj1802_Transmission_Type = 0xFE; /* 254 */
UNS16 TaskSlave_obj1802_Inhibit_Time = 0x40; /* 64 */
UNS8 TaskSlave_obj1802_Compatibility_Entry = 0x0; /* 0 */
UNS16 TaskSlave_obj1802_Event_Timer = 0xA; /* 10 */
UNS8 TaskSlave_obj1802_SYNC_start_value = 0x0; /* 0 */
subindex TaskSlave_Index1802[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1802, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1802_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1802_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1802_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1802_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1802_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1802_SYNC_start_value, NULL }
};
/* index 0x1803 : Transmit PDO 4 Parameter. */
UNS8 TaskSlave_highestSubIndex_obj1803 = 6; /* number of subindex - 1*/
UNS32 TaskSlave_obj1803_COB_ID_used_by_PDO = 0x480; /* 1152 */
UNS8 TaskSlave_obj1803_Transmission_Type = 0x1; /* 1 */
UNS16 TaskSlave_obj1803_Inhibit_Time = 0x40; /* 64 */
UNS8 TaskSlave_obj1803_Compatibility_Entry = 0x0; /* 0 */
UNS16 TaskSlave_obj1803_Event_Timer = 0xA; /* 10 */
UNS8 TaskSlave_obj1803_SYNC_start_value = 0x0; /* 0 */
subindex TaskSlave_Index1803[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1803, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1803_COB_ID_used_by_PDO, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1803_Transmission_Type, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1803_Inhibit_Time, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1803_Compatibility_Entry, NULL },
{ RW, uint16, sizeof (UNS16), (void*)&TaskSlave_obj1803_Event_Timer, NULL },
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_obj1803_SYNC_start_value, NULL }
};
/* index 0x1A00 : Transmit PDO 1 Mapping. */
UNS8 TaskSlave_highestSubIndex_obj1A00 = 8; /* number of subindex - 1*/
UNS32 TaskSlave_obj1A00[] =
{
0x20000110, /* 536871184 */
0x20000210, /* 536871440 */
0x20000310, /* 536871696 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
subindex TaskSlave_Index1A00[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1A00, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A00[0], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A00[1], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A00[2], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A00[3], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A00[4], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A00[5], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A00[6], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A00[7], NULL }
};
/* index 0x1A01 : Transmit PDO 2 Mapping. */
UNS8 TaskSlave_highestSubIndex_obj1A01 = 8; /* number of subindex - 1*/
UNS32 TaskSlave_obj1A01[] =
{
0x20010110, /* 536936720 */
0x20010210, /* 536936976 */
0x20010310, /* 536937232 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
subindex TaskSlave_Index1A01[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1A01, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A01[0], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A01[1], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A01[2], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A01[3], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A01[4], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A01[5], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A01[6], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A01[7], NULL }
};
/* index 0x1A02 : Transmit PDO 3 Mapping. */
UNS8 TaskSlave_highestSubIndex_obj1A02 = 8; /* number of subindex - 1*/
UNS32 TaskSlave_obj1A02[] =
{
0x20030110, /* 537067792 */
0x20030210, /* 537068048 */
0x20030310, /* 537068304 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
subindex TaskSlave_Index1A02[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1A02, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A02[0], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A02[1], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A02[2], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A02[3], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A02[4], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A02[5], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A02[6], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A02[7], NULL }
};
/* index 0x1A03 : Transmit PDO 4 Mapping. */
UNS8 TaskSlave_highestSubIndex_obj1A03 = 8; /* number of subindex - 1*/
UNS32 TaskSlave_obj1A03[] =
{
0x20040110, /* 537133328 */
0x20040210, /* 537133584 */
0x20040310, /* 537133840 */
0x20040410, /* 537134096 */
0x0, /* 0 */
0x0, /* 0 */
0x0, /* 0 */
0x0 /* 0 */
};
subindex TaskSlave_Index1A03[] =
{
{ RW, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj1A03, NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A03[0], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A03[1], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A03[2], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A03[3], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A03[4], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A03[5], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A03[6], NULL },
{ RW, uint32, sizeof (UNS32), (void*)&TaskSlave_obj1A03[7], NULL }
};
/* index 0x2000 : Mapped variable ACC */
UNS8 TaskSlave_highestSubIndex_obj2000 = 3; /* number of subindex - 1*/
subindex TaskSlave_Index2000[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj2000, NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&ACC[0], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&ACC[1], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&ACC[2], NULL }
};
/* index 0x2001 : Mapped variable GYR */
UNS8 TaskSlave_highestSubIndex_obj2001 = 3; /* number of subindex - 1*/
subindex TaskSlave_Index2001[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj2001, NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&GYR[0], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&GYR[1], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&GYR[2], NULL }
};
/* index 0x2003 : Mapped variable EUL */
UNS8 TaskSlave_highestSubIndex_obj2003 = 3; /* number of subindex - 1*/
subindex TaskSlave_Index2003[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj2003, NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&EUL[0], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&EUL[1], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&EUL[2], NULL }
};
/* index 0x2004 : Mapped variable QUAT */
UNS8 TaskSlave_highestSubIndex_obj2004 = 4; /* number of subindex - 1*/
subindex TaskSlave_Index2004[] =
{
{ RO, uint8, sizeof (UNS8), (void*)&TaskSlave_highestSubIndex_obj2004, NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&QUAT[0], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&QUAT[1], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&QUAT[2], NULL },
{ RO, int16, sizeof (INTEGER16), (void*)&QUAT[3], NULL }
};
/* index 0x2100 : Mapped variable CAN_BAUD */
subindex TaskSlave_Index2100[] =
{
{ RW|TO_BE_SAVE, int32, sizeof (INTEGER32), (void*)&CAN_BAUD, NULL }
};
/* index 0x2101 : Mapped variable NodeID */
subindex TaskSlave_Index2101[] =
{
{ RW|TO_BE_SAVE, int32, sizeof (INTEGER32), (void*)&NodeID, NULL }
};
/**************************************************************************/
/* Declaration of pointed variables */
/**************************************************************************/
const indextable TaskSlave_objdict[] =
{
{ (subindex*)TaskSlave_Index1000,sizeof(TaskSlave_Index1000)/sizeof(TaskSlave_Index1000[0]), 0x1000},
{ (subindex*)TaskSlave_Index1001,sizeof(TaskSlave_Index1001)/sizeof(TaskSlave_Index1001[0]), 0x1001},
{ (subindex*)TaskSlave_Index1002,sizeof(TaskSlave_Index1002)/sizeof(TaskSlave_Index1002[0]), 0x1002},
{ (subindex*)TaskSlave_Index1005,sizeof(TaskSlave_Index1005)/sizeof(TaskSlave_Index1005[0]), 0x1005},
{ (subindex*)TaskSlave_Index1016,sizeof(TaskSlave_Index1016)/sizeof(TaskSlave_Index1016[0]), 0x1016},
{ (subindex*)TaskSlave_Index1017,sizeof(TaskSlave_Index1017)/sizeof(TaskSlave_Index1017[0]), 0x1017},
{ (subindex*)TaskSlave_Index1018,sizeof(TaskSlave_Index1018)/sizeof(TaskSlave_Index1018[0]), 0x1018},
{ (subindex*)TaskSlave_Index1200,sizeof(TaskSlave_Index1200)/sizeof(TaskSlave_Index1200[0]), 0x1200},
{ (subindex*)TaskSlave_Index1400,sizeof(TaskSlave_Index1400)/sizeof(TaskSlave_Index1400[0]), 0x1400},
{ (subindex*)TaskSlave_Index1401,sizeof(TaskSlave_Index1401)/sizeof(TaskSlave_Index1401[0]), 0x1401},
{ (subindex*)TaskSlave_Index1402,sizeof(TaskSlave_Index1402)/sizeof(TaskSlave_Index1402[0]), 0x1402},
{ (subindex*)TaskSlave_Index1403,sizeof(TaskSlave_Index1403)/sizeof(TaskSlave_Index1403[0]), 0x1403},
{ (subindex*)TaskSlave_Index1600,sizeof(TaskSlave_Index1600)/sizeof(TaskSlave_Index1600[0]), 0x1600},
{ (subindex*)TaskSlave_Index1601,sizeof(TaskSlave_Index1601)/sizeof(TaskSlave_Index1601[0]), 0x1601},
{ (subindex*)TaskSlave_Index1602,sizeof(TaskSlave_Index1602)/sizeof(TaskSlave_Index1602[0]), 0x1602},
{ (subindex*)TaskSlave_Index1603,sizeof(TaskSlave_Index1603)/sizeof(TaskSlave_Index1603[0]), 0x1603},
{ (subindex*)TaskSlave_Index1800,sizeof(TaskSlave_Index1800)/sizeof(TaskSlave_Index1800[0]), 0x1800},
{ (subindex*)TaskSlave_Index1801,sizeof(TaskSlave_Index1801)/sizeof(TaskSlave_Index1801[0]), 0x1801},
{ (subindex*)TaskSlave_Index1802,sizeof(TaskSlave_Index1802)/sizeof(TaskSlave_Index1802[0]), 0x1802},
{ (subindex*)TaskSlave_Index1803,sizeof(TaskSlave_Index1803)/sizeof(TaskSlave_Index1803[0]), 0x1803},
{ (subindex*)TaskSlave_Index1A00,sizeof(TaskSlave_Index1A00)/sizeof(TaskSlave_Index1A00[0]), 0x1A00},
{ (subindex*)TaskSlave_Index1A01,sizeof(TaskSlave_Index1A01)/sizeof(TaskSlave_Index1A01[0]), 0x1A01},
{ (subindex*)TaskSlave_Index1A02,sizeof(TaskSlave_Index1A02)/sizeof(TaskSlave_Index1A02[0]), 0x1A02},
{ (subindex*)TaskSlave_Index1A03,sizeof(TaskSlave_Index1A03)/sizeof(TaskSlave_Index1A03[0]), 0x1A03},
{ (subindex*)TaskSlave_Index2000,sizeof(TaskSlave_Index2000)/sizeof(TaskSlave_Index2000[0]), 0x2000},
{ (subindex*)TaskSlave_Index2001,sizeof(TaskSlave_Index2001)/sizeof(TaskSlave_Index2001[0]), 0x2001},
{ (subindex*)TaskSlave_Index2003,sizeof(TaskSlave_Index2003)/sizeof(TaskSlave_Index2003[0]), 0x2003},
{ (subindex*)TaskSlave_Index2004,sizeof(TaskSlave_Index2004)/sizeof(TaskSlave_Index2004[0]), 0x2004},
{ (subindex*)TaskSlave_Index2100,sizeof(TaskSlave_Index2100)/sizeof(TaskSlave_Index2100[0]), 0x2100},
{ (subindex*)TaskSlave_Index2101,sizeof(TaskSlave_Index2101)/sizeof(TaskSlave_Index2101[0]), 0x2101},
};
const indextable * TaskSlave_scanIndexOD (CO_Data *d, UNS16 wIndex, UNS32 * errorCode)
{
(void)d;
int i;
switch(wIndex){
case 0x1000: i = 0;break;
case 0x1001: i = 1;break;
case 0x1002: i = 2;break;
case 0x1005: i = 3;break;
case 0x1016: i = 4;break;
case 0x1017: i = 5;break;
case 0x1018: i = 6;break;
case 0x1200: i = 7;break;
case 0x1400: i = 8;break;
case 0x1401: i = 9;break;
case 0x1402: i = 10;break;
case 0x1403: i = 11;break;
case 0x1600: i = 12;break;
case 0x1601: i = 13;break;
case 0x1602: i = 14;break;
case 0x1603: i = 15;break;
case 0x1800: i = 16;break;
case 0x1801: i = 17;break;
case 0x1802: i = 18;break;
case 0x1803: i = 19;break;
case 0x1A00: i = 20;break;
case 0x1A01: i = 21;break;
case 0x1A02: i = 22;break;
case 0x1A03: i = 23;break;
case 0x2000: i = 24;break;
case 0x2001: i = 25;break;
case 0x2003: i = 26;break;
case 0x2004: i = 27;break;
case 0x2100: i = 28;break;
case 0x2101: i = 29;break;
default:
*errorCode = OD_NO_SUCH_OBJECT;
return NULL;
}
*errorCode = OD_SUCCESSFUL;
return &TaskSlave_objdict[i];
}
/*
* To count at which received SYNC a PDO must be sent.
* Even if no pdoTransmit are defined, at least one entry is computed
* for compilations issues.
*/
s_PDO_status TaskSlave_PDO_status[4] = {s_PDO_status_Initializer,s_PDO_status_Initializer,s_PDO_status_Initializer,s_PDO_status_Initializer};
const quick_index TaskSlave_firstIndex = {
7, /* SDO_SVR */
0, /* SDO_CLT */
8, /* PDO_RCV */
12, /* PDO_RCV_MAP */
16, /* PDO_TRS */
20 /* PDO_TRS_MAP */
};
const quick_index TaskSlave_lastIndex = {
7, /* SDO_SVR */
0, /* SDO_CLT */
11, /* PDO_RCV */
15, /* PDO_RCV_MAP */
19, /* PDO_TRS */
23 /* PDO_TRS_MAP */
};
const UNS16 TaskSlave_ObjdictSize = sizeof(TaskSlave_objdict)/sizeof(TaskSlave_objdict[0]);
CO_Data TaskSlave_Data = CANOPEN_NODE_DATA_INITIALIZER(TaskSlave);
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/src/system_MKE18F16.c
|
/*
** ###################################################################
** Processors: MKE18F256VLH16
** MKE18F256VLL16
** MKE18F512VLH16
** MKE18F512VLL16
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KE1xP100M150SF0RM, Rev. 0, Nov. 2015
** Version: rev. 2.0, 2015-12-03
** Build: b160125
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2015-11-18)
** Initial version.
** - rev. 2.0 (2015-12-03)
** Alpha version based on rev0 RDP.
**
** ###################################################################
*/
/*!
* @file MKE18F16
* @version 2.0
* @date 2015-12-03
* @brief Device specific configuration file for MKE18F16 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MKE18F16.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if (DISABLE_WDOG)
WDOG->CNT = WDOG_UPDATE_KEY;
WDOG->TOVAL = 0xFFFF;
WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
#endif /* (DISABLE_WDOG) */
/* Initialize Cache */
/* Enable Code Bus Cache */
/* set command to invalidate all ways, enable write buffer
and write GO bit to initiate command */
LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
/* Wait until the command completes */
while (LMEM->PCCCR & LMEM_PCCCR_GO_MASK) {
}
/* Enable cache, enable write buffer */
LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
__ISB();
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */
uint16_t Divider, prediv, multi, srcdiv;
Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
case 0x1:
/* System OSC */
SCGOUTClock = CPU_XTAL_CLK_HZ;
srcdiv = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV1_SHIFT;
break;
case 0x2:
/* Slow IRC */
SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
srcdiv = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV1_SHIFT;
break;
case 0x3:
/* Fast IRC */
SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
srcdiv = (SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV1_SHIFT;
break;
case 0x6:
/* System PLL */
if ((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) >> SCG_SPLLCFG_SOURCE_SHIFT) {
SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
}
else {
SCGOUTClock = CPU_XTAL_CLK_HZ;
}
srcdiv = (SCG->SPLLDIV & SCG_SPLLDIV_SPLLDIV1_MASK) >> SCG_SPLLDIV_SPLLDIV1_SHIFT;
prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1;
multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16;
SCGOUTClock = SCGOUTClock * multi / (prediv * 2);
break;
default:
return;
}
if (srcdiv)
{
SystemCoreClock = (SCGOUTClock / (Divider * (1 << (srcdiv - 1))));
}
else
{
SystemCoreClock = 0;
}
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/src/system_MKL33Z4.c
|
/*
** ###################################################################
** Processors: MKL33Z256VLH4
** MKL33Z128VLH4
** MKL33Z64VLH4
** MKL33Z256VMP4
** MKL33Z128VMP4
** MKL33Z64VMP4
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL33P64M48SF6RM, Rev.3, Aug 2014
** Version: rev. 1.3, 2014-08-21
** Build: b140821
**
** Abstract:
** CMSIS Peripheral Access Layer for MKL33Z4
**
** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2014-03-27)
** Initial version.
** - rev. 1.1 (2014-05-26)
** I2S registers TCR2/RCR2 and others were changed.
** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
** Clock configuration for high range external oscillator has been added.
** RFSYS module access has been added.
** - rev. 1.2 (2014-07-10)
** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
** UART0 - UART0 module renamed to UART2.
** I2S - removed MDR register.
** - rev. 1.3 (2014-08-21)
** UART2 - Removed ED register.
** UART2 - Removed MODEM register.
** UART2 - Removed IR register.
** UART2 - Removed PFIFO register.
** UART2 - Removed CFIFO register.
** UART2 - Removed SFIFO register.
** UART2 - Removed TWFIFO register.
** UART2 - Removed TCFIFO register.
** UART2 - Removed RWFIFO register.
** UART2 - Removed RCFIFO register.
** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
** SIM - Removed bitfield DIEID in SDID register.
**
** ###################################################################
*/
/*!
* @file MKL33Z4
* @version 1.3
* @date 2014-08-21
* @brief Device specific configuration file for MKL33Z4 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MKL33Z4.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if (DISABLE_WDOG)
/* Disable the COP module */
/* SIM_COPC: COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
SIM->COPC = (uint32_t)0x00u;
#endif /* (DISABLE_WDOG) */
#if (CLOCK_SETUP == 0)
/* SIM->SOPT2: USBSRC=0 */
SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; /* USB_CLKIN is clock source for USB FS (applicable only for derivatived with USB)*/
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
/* MCG->SC: FCRDIV=1 */
MCG->SC = MCG_SC_FCRDIV(0x01); /* Set the LIRC1 divider*/
/* MCG->MC: HIRC=0,LIRC_DIV2=0 */
MCG->MC = MCG_MC_LIRC_DIV2(0x00); /* Set the LIRC2 divider*/
/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint32_t)0x00u; /* Disable External reference */
/* MCG->C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
MCG->C2 = MCG_C2_IRCS_MASK; /* Enable LIRC 8MHz */
/* Switch to LIRC 8MHz Mode */
/* MCG->C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x01) |
MCG_C1_IRCLKEN_MASK; /* Enable LIRC and select LIRC as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x04u) {} /* Check that the clock source is the LIRC clock. */
#elif (CLOCK_SETUP == 1)
/* SIM->SOPT2: USBSRC=0 */
SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; /* USB_CLKIN is clock source for USB FS (applicable only for derivatived with USB)*/
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Set system prescalers */
/* MCG->SC: FCRDIV=1 */
MCG->SC = MCG_SC_FCRDIV(0x01); /* LIRC1 divider not used - leave the default value*/
/* MCG->MC: HIRC=1,LIRC_DIV2=0 */
MCG->MC = MCG_MC_HIRCEN_MASK; /* Enable HIRC clock source*/
/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint32_t)0x00u; /* Disable External reference */
/* MCG->C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
MCG->C2 = MCG_C2_IRCS_MASK; /* Not used - leave default value */
/* Switch to HIRC Mode */
/* MCG->C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) |
MCG_C1_IRCLKEN_MASK; /* Leave LIRC enabled and select HIRC as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x00u) {} /* Check that the clock source is the HIRC clock. */
#elif (CLOCK_SETUP == 2)
/* SIM->SOPT2: USBSRC=0 */
SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; /* USB_CLKIN is clock source for USB FS (applicable only for derivatived with USB)*/
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for port to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x00); /* Set system prescalers */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~(uint32_t)(PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07));
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA->PCR[19] &= (uint32_t)~(uint32_t)(PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07));
/* MCG->SC: FCRDIV=1 */
MCG->SC = MCG_SC_FCRDIV(0x01); /* LIRC1 divider not used - leave the default value*/
/* MCG->MC: HIRC=0,LIRC_DIV2=0 */
MCG->MC = MCG_MC_LIRC_DIV2(0x00); /* Not used - leave the default value */
/* MCG->C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
MCG->C2 = MCG_C2_EREFS0_MASK | MCG_C2_IRCS_MASK; /* Select external crystal, low range, low power, for LIRC - leave default value */
/* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK; /* Enable External reference */
/* Switch to EXT Mode */
/* MCG->C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x02); /* Disable LIRC and select EXT as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x08u) {} /* Check that the clock source is the EXT clock. */
#elif (CLOCK_SETUP == 3)
/* SIM->SOPT2: USBSRC=0 */
SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; /* USB_CLKIN is clock source for USB FS (applicable only for derivatived with USB)*/
/* MCG->MC: HIRC=1 */
MCG->MC |= MCG_MC_HIRCEN_MASK; /* Enable HIRC clock source*/
/* MCG->C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) |
MCG_C1_IRCLKEN_MASK; /* Leave LIRC enabled and select HIRC as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x00u) {} /* Check that the clock source is the HIRC clock. */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Set system prescalers */
/* MCG->SC: FCRDIV=0 */
MCG->SC = MCG_SC_FCRDIV(0x00); /* Set the LIRC1 divider to 1*/
/* MCG->MC: HIRC=0,LIRC_DIV2=0 */
MCG->MC = MCG_MC_LIRC_DIV2(0x00); /* Set the LIRC2 divider to 1 */
/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint32_t)0x00u; /* Disable External reference */
/* MCG->C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
MCG->C2 = (uint32_t)0x00u; /* Enable LIRC 2MHz */
/* Switch to LIRC 2MHz Mode */
/* MCG->C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x01) |
MCG_C1_IRCLKEN_MASK; /* Enable LIRC and select LIRC as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x04u) {} /* Check that the clock source is the LIRC clock. */
#elif (CLOCK_SETUP == 5)
/* SIM->SOPT2: USBSRC=0 */
SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; /* USB_CLKIN is clock source for USB FS (applicable only for derivatived with USB)*/
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for port to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Set system prescalers */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~(uint32_t)(PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07));
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA->PCR[19] &= (uint32_t)~(uint32_t)(PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07));
/* MCG->SC: FCRDIV=1 */
MCG->SC = MCG_SC_FCRDIV(0x01); /* LIRC1 divider not used - leave the default value*/
/* MCG->MC: HIRC=0,LIRC_DIV2=0 */
MCG->MC = MCG_MC_LIRC_DIV2(0x00); /* Not used - leave the default value */
/* MCG->C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
MCG->C2 = MCG_C2_EREFS0_MASK | MCG_C2_IRCS_MASK | MCG_C2_RANGE0(1); /* Select external crystal, high range, low power, for LIRC - leave default value */
/* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK; /* Enable External reference */
/* Switch to EXT Mode */
/* MCG->C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x02); /* Disable LIRC and select EXT as a clock source */
while((MCG->S & MCG_S_CLKST_MASK) != 0x08u) {} /* Check that the clock source is the EXT clock. */
#endif
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t ICSOUTClock; /* Variable to store output clock frequency of the ICS module */
uint8_t Divider;
if ((MCG->S & MCG_S_CLKST_MASK) == 0x04u) {
/* LIRC reference clock is selected */
ICSOUTClock = CPU_INT_SLOW_CLK_HZ;
Divider = (uint8_t)(1u << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
ICSOUTClock = (ICSOUTClock / Divider); /* Calculate the divided LIRC clock */
} else if ((MCG->S & MCG_S_CLKST_MASK) == 0x0u) {
/* HIRC reference clock is selected */
ICSOUTClock = CPU_INT_FAST_CLK_HZ;
} else if ((MCG->S & MCG_S_CLKST_MASK) == 0x80u) {
/* External reference clock is selected */
ICSOUTClock = CPU_XTAL_CLK_HZ;
} else {
/* Reserved value */
return;
}
SystemCoreClock = (ICSOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/sdif.c
|
<gh_stars>1-10
/**
******************************************************************************
* @file sdif.c
* @author YANDLD
* @version V3.0.0
* @date 2016.5.28
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "common.h"
#include "sdif.h"
#define kSDIF_DataTransferError (SDIF_RINTSTS_FRUN_MASK | SDIF_RINTSTS_SBE_MASK | SDIF_RINTSTS_HLE_MASK | SDIF_RINTSTS_DRTO_BDS_MASK)
void print_cmd(sdif_cmd_t *cmd)
{
LIB_TRACE("CMD:%d\r\n", cmd->index);
LIB_TRACE(" arg:0x%X\r\n", cmd->argument);
LIB_TRACE(" flag:0x%X\r\n", cmd->flags);
LIB_TRACE(" bsize:%d bcnt:%d\r\n", cmd->block_size, cmd->block_cnt);
LIB_TRACE(" resp:0x%X 0x%X 0x%X 0x%X\r\n", cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3]);
}
static uint32_t SDIF_WaitCmdDone(sdif_cmd_t *cmd)
{
uint32_t status = 0U;
do
{
status = SDIF->RINTSTS;
if(status & (SDIF_RINTSTS_RE_MASK | SDIF_RINTSTS_RCRC_MASK | SDIF_RINTSTS_RTO_BAR_MASK | SDIF_RINTSTS_HLE_MASK))
{
SDIF->RINTSTS &= SDIF_RINTSTS_RE_MASK | SDIF_RINTSTS_RCRC_MASK | SDIF_RINTSTS_RTO_BAR_MASK | SDIF_RINTSTS_HLE_MASK;
return CH_ERR;
}
} while ((status & SDIF_RINTSTS_CDONE_MASK) != SDIF_RINTSTS_CDONE_MASK);
/* clear the command done bit */
SDIF->RINTSTS &= SDIF_RINTSTS_CDONE_MASK;
cmd->response[0] = SDIF->RESP[0];
cmd->response[1] = SDIF->RESP[1];
cmd->response[2] = SDIF->RESP[2];
cmd->response[3] = SDIF->RESP[3];
return CH_OK;
}
uint32_t SDIF_SendCmd(sdif_cmd_t *cmd, uint32_t timeout)
{
//print_cmd(cmd);
SDIF->CMDARG = cmd->argument;
if(cmd->flags & SDIF_CMD_DATA_EXPECTED_MASK)
{
SDIF->BLKSIZ = cmd->block_size;
SDIF->BYTCNT = cmd->block_size*cmd->block_cnt;
}
SDIF->CMD = SDIF_CMD_CMD_INDEX(cmd->index) | SDIF_CMD_USE_HOLD_REG_MASK | SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK | SDIF_CMD_START_CMD_MASK | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK));
cmd->response[0] = 0;
cmd->response[1] = 0;
cmd->response[2] = 0;
cmd->response[3] = 0;
/* wait start_cmd bit auto clear within timeout */
while ((SDIF->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK)
{
if (!timeout)
{
break;
}
--timeout;
}
if(timeout)
{
return SDIF_WaitCmdDone(cmd);
}
LIB_TRACE("SDIO command send timeout\r\n");
return CH_ERR;
}
#define SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY (0X17U)
#define SDIF_INDENTIFICATION_MODE_DRV_DELAY (0X17U)
#define SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY (0x10U)
#define SDIF_HIGHSPEED_25MHZ_DRV_DELAY (0x10U)
void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider)
{
/*config the clock delay and pharse shift
*should config the clk_in_drv,
*clk_in_sample to meet the min hold and
*setup time
*/
if (target_HZ <= 400*1000)
{
/*min hold time:5ns
* min setup time: 5ns
* delay = (x+1)*250ps
*/
SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY) |
SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_INDENTIFICATION_MODE_DRV_DELAY);
}
else
{
/*
* user need to pay attention to this parameter
* can be change the setting for you card and board
* min hold time:5ns
* min setup time: 5ns
* delay = (x+1)*250ps
*/
SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY) |
SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_25MHZ_DRV_DELAY);
/* means the input clock = 2 * card clock,
* can use clock pharse shift tech
*/
if (divider == 1U)
{
SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(1) |
SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(1);
}
}
}
void SDIF_SetClock(uint32_t src_clk, uint32_t hz)
{
uint32_t div;
SDIF->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK;
SDIF->CMDARG = 0x00;
SDIF->CMD = SDIF_CMD_CMD_INDEX(0) | SDIF_CMD_START_CMD_MASK | SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK | SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK;
div = (src_clk / (SYSCON->SDIOCLKDIV + 1) / hz + 1U) / 2U;
LIB_TRACE("SDIF->CLKDIV:0x%X\r\n", div);
SDIF->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(div);
SDIF->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK;
SDIF->CMDARG = 0x00;
SDIF->CMD = SDIF_CMD_CMD_INDEX(0) | SDIF_CMD_START_CMD_MASK | SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK | SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK;
SDIF_ConfigClockDelay(hz, div);
}
void SDIF_SetBusWidth(uint8_t width_bit)
{
if(width_bit == 1)
{
SDIF->CTYPE = 0;
}
if(width_bit == 4)
{
SDIF->CTYPE = 1;
}
}
void SDIF_Init(void)
{
/* clock setup: SDIF clock = main_clock/(SYSCON->SDIOCLKDIV+1) */
SYSCON->AHBCLKCTRL[2] |= SYSCON_AHBCLKCTRL_SDIO_MASK;
SYSCON->SDIOCLKSEL = 0x00;
SYSCON->SDIOCLKDIV = 1;
/* reset & power */
SDIF->BMOD |= SDIF_BMOD_SWR_MASK;
SDIF->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK;
/* clear status */
SDIF->RINTSTS = 0xFFFFFFFF;
SDIF->IDSTS = 0xFFFFFFFF;
SDIF->INTMASK = 0x1FFFFU;
SDIF_SetClock(GetClock(kCoreClock), 400*1000);
}
/* SD card driver layer */
static void SD_DecodeCid(mmc_cid_t *cid, uint32_t *rawCid)
{
cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U);
cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U);
cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU));
cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U);
cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U);
cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U);
cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU));
cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U);
cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U);
cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U);
cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U);
}
static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd)
{
sd_csd_t *csd;
csd = &(card->csd);
csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U);
csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U);
csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U);
csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU);
csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U);
csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U);
// if (rawCsd[2U] & 0x8000U)
// {
// csd->flags |= kSD_CsdReadBlockPartialFlag;
// }
// if (rawCsd[2U] & 0x4000U)
// {
// csd->flags |= kSD_CsdReadBlockPartialFlag;
// }
// if (rawCsd[2U] & 0x2000U)
// {
// csd->flags |= kSD_CsdReadBlockMisalignFlag;
// }
// if (rawCsd[2U] & 0x1000U)
// {
// csd->flags |= kSD_CsdDsrImplementedFlag;
// }
switch (csd->csdStructure)
{
case 0:
csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FFU) << 2U);
csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xC0000000U) >> 30U);
csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U);
csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x7000000U) >> 24U);
csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0xE00000U) >> 20U);
csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x1C0000U) >> 18U);
csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x38000U) >> 15U);
/* Get card total block count and block size. */
card->block_cnt = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U));
card->block_size = (1U << (csd->readBlockLength));
if (card->block_size != 512)
{
card->block_cnt = (card->block_cnt * card->block_size);
card->block_size = 512;
card->block_cnt = (card->block_cnt / card->block_size);
}
break;
case 1:
card->block_size = 512;
csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FU) << 16U);
csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFFF0000U) >> 16U);
// if (csd->deviceSize >= 0xFFFFU)
// {
// card->flags |= kSD_SupportSdxcFlag;
// }
card->block_cnt = ((csd->deviceSize + 1U) * 1024U);
break;
default:
break;
}
// if ((uint8_t)((rawCsd[1U] & 0x4000U) >> 14U))
// {
// csd->flags |= kSD_CsdEraseBlockEnabledFlag;
// }
csd->eraseSectorSize = (uint8_t)((rawCsd[1U] & 0x3F80U) >> 7U);
csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x7FU);
// if ((uint8_t)(rawCsd[0U] & 0x80000000U))
// {
// csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag;
// }
csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U);
csd->writeBlockLength = (uint8_t)((rawCsd[0U] & 0x3C00000U) >> 22U);
// if ((uint8_t)((rawCsd[0U] & 0x200000U) >> 21U))
// {
// csd->flags |= kSD_CsdWriteBlockPartialFlag;
// }
// if ((uint8_t)((rawCsd[0U] & 0x8000U) >> 15U))
// {
// csd->flags |= kSD_CsdFileFormatGroupFlag;
// }
// if ((uint8_t)((rawCsd[0U] & 0x4000U) >> 14U))
// {
// csd->flags |= kSD_CsdCopyFlag;
// }
// if ((uint8_t)((rawCsd[0U] & 0x2000U) >> 13U))
// {
// csd->flags |= kSD_CsdPermanentWriteProtectFlag;
// }
// if ((uint8_t)((rawCsd[0U] & 0x1000U) >> 12U))
// {
// csd->flags |= kSD_CsdTemporaryWriteProtectFlag;
// }
csd->fileFormat = (uint8_t)((rawCsd[0U] & 0xC00U) >> 10U);
}
uint32_t SDCardInit(sd_card_t *card, uint32_t hz)
{
sdif_cmd_t cmd = {0};
int ret;
/* CMD0 -> CMD8 -> while(CMD55+ACMD41) ->CMD2 -> CMD3 ->CMD9 -> CMD7-> CMD16->(CMD55+ACMD6) */
cmd.index = 0; /* go idle */
cmd.flags = SDIF_CMD_USE_HOLD_REG_MASK;
cmd.argument = 0x00;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
LIB_TRACE("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
cmd.index = 8; /* Send Interface Condition Command */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK;
cmd.argument = 0x1AAU;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
LIB_TRACE("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
/* trap if not SDHC or demaged card */
if((cmd.response[0] & 0xAA) != 0xAA)
{
LIB_TRACE("bad or not SDHC card\r\n");
return CH_ERR;
}
while(1)
{
cmd.index = 55; /* enable Application-Specific Command APP_CMD (CMD55) */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK;
cmd.argument = 0;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
printf("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
/* trap if APP_CMD status is not enabled */
if((cmd.response[0] & (1<<5)) == 0)
{
LIB_TRACE("app cmd status still not enabled\r\n");
return CH_ERR;
}
cmd.index = 41; /* SD_APP_OP_COND ACMD41 */
cmd.flags = SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK | SDIF_CMD_RESPONSE_EXPECT_MASK;
cmd.argument = 0x40300000;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
LIB_TRACE("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
if(cmd.response[0] & 0x80000000)
{
break;
}
}
cmd.index = 2; /* ALL_SEND_CID */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK | SDIF_CMD_RESPONSE_LENGTH_MASK;
cmd.argument = 0;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
LIB_TRACE("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
if(ret)
{
while(1);
}
SD_DecodeCid(&card->cid, cmd.response);
LIB_TRACE("%s\r\n", card->cid.productName);
LIB_TRACE("%d\r\n", card->cid.manufacturerData);
cmd.index = 3; /* SEND_RELATIVE_ADDR */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK;
cmd.argument = 0;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
LIB_TRACE("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
card->rel_addr = cmd.response[0] >> 16;
LIB_TRACE("card rel addr:0x%X\r\n", card->rel_addr);
cmd.index = 9; /* SEND_CSD */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK | SDIF_CMD_RESPONSE_LENGTH_MASK;
cmd.argument = card->rel_addr << 16;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
LIB_TRACE("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
SD_DecodeCsd(card, cmd.response);
LIB_TRACE("block_cnt:%d\r\n", card->block_cnt);
LIB_TRACE("block_size:%d\r\n", card->block_size);
LIB_TRACE("total size:%dMB\r\n", (card->block_cnt / 1024 / 1024) * card->block_size);
cmd.index = 7; /* SELECT/DESELECT_CARD */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK;
cmd.argument = card->rel_addr << 16;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
LIB_TRACE("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
cmd.index = 16; /* SET_BLOCKLEN */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK;
cmd.argument = 512;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
LIB_TRACE("ret:%s\r\n", (ret == CH_OK)?("ok"):("err"));
SDIF_SetClock(GetClock(kCoreClock), hz);
return CH_OK;
}
uint32_t SD_SetCardDataBusWidth(sd_card_t *card, uint8_t width_in_bit)
{
int ret;
sdif_cmd_t cmd = {0};
cmd.index = 55; /* enable Application-Specific Command APP_CMD (CMD55) */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK;
cmd.argument = card->rel_addr << 16;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
/* trap if APP_CMD status is not enabled */
if((cmd.response[0] & (1<<5)) == 0)
{
LIB_TRACE("app cmd status still not enabled\r\n");
return CH_ERR;
}
cmd.index = 6; /* SET_BUS_WIDTH ACMD6 */
cmd.flags = SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK | SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK;
switch(width_in_bit)
{
case 1:
cmd.argument = 0;
break;
case 4:
cmd.argument = 2;
break;
default:
LIB_TRACE("wrong bus width\r\n");
break;
}
SDIF_SendCmd(&cmd, 0xFFFF);
return CH_OK;
}
bool SD_IsCardInsert(void)
{
if(SDIF->CDETECT)
{
return false;
}
return true;
}
bool SD_IsCardIdle(sd_card_t *card)
{
int ret;
sdif_cmd_t cmd = {0};
cmd.index = 13; /* SEND_STATUS */
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK;
cmd.argument = card->rel_addr << 16;
ret = SDIF_SendCmd(&cmd, 0xFFFF);
/* see SD Specifications Part 1 Physical Layer Simplified Specification Version 2.00 September 25, 2006 */
if(ret == CH_OK && cmd.response[0] & (1<<8) && ((cmd.response[0] & 0x00001E00U) >> 9) != 7)
{
return true;
}
return false;
}
uint32_t SD_ReadBlock(sd_card_t *card, uint32_t block_addr, uint32_t block_cnt, uint8_t *buf)
{
int i, status;
bool transferOver = false;
sdif_cmd_t cmd = {0};
while(SD_IsCardIdle(card) == false);
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK | SDIF_CMD_DATA_EXPECTED_MASK;
cmd.argument = block_addr;
cmd.block_cnt = block_cnt;
cmd.block_size = 512;
if(cmd.block_cnt > 1)
{
cmd.index = 18; /* READ_MULTIPLE_BLOCK */
cmd.flags |= SDIF_CMD_SEND_AUTO_STOP_MASK;
}
else
{
cmd.index = 17; /* READ_SINGLE_BLOCK */
}
SDIF_SendCmd(&cmd, 0xFFFF);
uint32_t *p = (uint32_t *)buf;
for(i=0; i<cmd.block_cnt*cmd.block_size/(sizeof(uint32_t)); i++)
{
do
{
status = SDIF->RINTSTS;
} while((status & (SDIF_RINTSTS_RXDR_MASK | SDIF_RINTSTS_DTO_MASK)) == 0 && !transferOver);
if(status & SDIF_RINTSTS_DTO_MASK)
{
transferOver = true;
}
*p++ = SDIF->FIFO[0];
SDIF->RINTSTS &= status;
}
return CH_OK;
}
uint32_t SD_WriteBlock(sd_card_t *card, uint32_t block_addr, uint32_t block_cnt, uint8_t *buf)
{
int i;
sdif_cmd_t cmd = {0};
while(SD_IsCardIdle(card) == false);
cmd.flags = SDIF_CMD_RESPONSE_EXPECT_MASK | SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK | SDIF_CMD_CHECK_RESPONSE_CRC_MASK | SDIF_CMD_DATA_EXPECTED_MASK | SDIF_CMD_READ_WRITE_MASK;
cmd.argument = block_addr;
cmd.block_cnt = block_cnt;
cmd.block_size = 512;
if(cmd.block_cnt > 1)
{
cmd.index = 25; /* WRITE_MULTIPLE_BLOCK */
cmd.flags |= SDIF_CMD_SEND_AUTO_STOP_MASK;
}
else
{
cmd.index = 24; /* WRITE_BLOCK */
}
SDIF_SendCmd(&cmd, 0xFFFF);
uint32_t *p = (uint32_t *)buf;
for(i=0; i<cmd.block_size*cmd.block_cnt/(sizeof(uint32_t)); i++)
{
/* waiting for Tx ready */
while((SDIF->RINTSTS & SDIF_RINTSTS_TXDR_MASK) == 0);
SDIF->RINTSTS &= SDIF_RINTSTS_TXDR_MASK;
if(SDIF->RINTSTS & kSDIF_DataTransferError)
{
return CH_ERR;
}
SDIF->FIFO[0] = *p++;
}
/* waitting for transfer complete */
while((SDIF->RINTSTS & SDIF_RINTSTS_DTO_MASK) == 0);
SDIF->RINTSTS &= SDIF_RINTSTS_DTO_MASK;
return CH_OK;
}
uint32_t SD_BlockTest(sd_card_t *card, uint8_t *buf, uint32_t block_addr, uint32_t block_cnt)
{
int i;
for(i=0; i<block_cnt*512; i++)
{
buf[i] = i & 0xFF;
}
SD_WriteBlock(card, block_addr, block_cnt, buf);
for(i=0; i<block_cnt*512; i++)
{
buf[i] = 0;
}
SD_ReadBlock(card, block_addr, block_cnt, buf);
for(i=0; i<block_cnt*512; i++)
{
if(buf[i] != (i & 0xFF))
{
LIB_TRACE("sector%d error buf[%X]:%X\r\n", block_addr, i, buf[i]);
return CH_ERR;
}
}
return CH_OK;
}
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/uart_bridge.c
|
#include <rtthread.h>
#include "uart_bridge.h"
#include "common.h"
#include "gpio.h"
#include "uart.h"
#include "dma.h"
#include "rtdevice.h"
#include "usbd.h"
#include "ulog.h"
void set_led(uint8_t idx, uint8_t val);
void _setup_dma_tx_desc(uint8_t ch, DMA_ChlSetup_t *setup);
void _setup_dma_rx_desc(uint8_t ch, DMA_ChlSetup_t *setup);
static rt_sem_t utx_dma_complete;
rt_mutex_t usb_lock;
static int usb_in_ready = 1;
int usb_ctl_need_report_stat = 0;
int usb_report_stat_chl = 1;
uart_bridge_t bridge[10];
stat_t stat;
static void stat_timer_cb(void* parameter)
{
/* caluate total OUT and IN speed */
stat.total_in_speed = stat.total_in;
stat.total_in = 0;
stat.total_out_speed = stat.total_out;
stat.total_out = 0;
}
void uart_bridge_init(uint8_t ch, uart_bridge_t *handle)
{
/* tx */
rt_ringbuffer_init(&handle->trb, handle->trb_buf, sizeof(handle->trb_buf));
_setup_dma_tx_desc(ch, &handle->tx_setup);
DMA_SetChlIntMode(handle->tx_setup.chl, true);
handle->tx_idle = 1;
handle->tx_sum = 0;
handle->tx_dma_complete_timeout = 0;
/* rx */
handle->rx_sum = 0;
handle->rx_dma_sum = 0;
rt_ringbuffer_init(&handle->rrb, handle->rrb_buf, sizeof(handle->rrb_buf));
handle->rx_setup.transferCnt = sizeof(handle->rdma_buf);
handle->rx_setup.dAddr = (uint32_t)handle->rdma_buf;
_setup_dma_rx_desc(ch, &handle->rx_setup);
DMA_SWTrigger(handle->rx_setup.chl);
}
uint32_t bridge_uart_send(uint8_t ch, uint8_t *buf, uint32_t size)
{
return rt_ringbuffer_put(&bridge[ch].trb, buf, size);
}
uint32_t bridge_uart_tx_get_free(uint8_t ch)
{
return rt_ringbuffer_space_len(&bridge[ch].trb);
}
uint32_t bridge_uart_rx_get_free(uint8_t ch)
{
return rt_ringbuffer_space_len(&bridge[ch].rrb);
}
void bridge_uart_usb_data_in_ready(void)
{
usb_in_ready = 1;
}
void serial_tx_thread_entey(void* parameter)
{
int i;
uint32_t len;
for(i=1; i<ARRAY_SIZE(bridge); i++)
{
uart_bridge_init(i, &bridge[i]);
}
rt_timer_start(rt_timer_create("stat", stat_timer_cb, RT_NULL, rt_tick_from_millisecond(1000), RT_TIMER_FLAG_PERIODIC));
utx_dma_complete = rt_sem_create("tx", 1, RT_IPC_FLAG_FIFO);
usb_lock = rt_mutex_create("ulock", RT_IPC_FLAG_FIFO);
while(1)
{
rt_sem_take(utx_dma_complete, 1);
for(i=1; i< ARRAY_SIZE(bridge); i++)
{
if(bridge[i].tx_idle)
{
bridge[i].tx_dma_complete_timeout = 0;
len = rt_ringbuffer_get(&bridge[i].trb, bridge[i].tbuf, sizeof(bridge[i].tbuf));
if(len)
{
bridge[i].tx_idle = 0;
bridge[i].tx_setup.sAddr = (uint32_t)bridge[i].tbuf;
bridge[i].tx_setup.transferCnt = len;
set_led(i, 0);
DMA_SetupChl(&bridge[i].tx_setup);
DMA_SWTrigger(bridge[i].tx_setup.chl);
bridge[i].tx_sum += len;
rt_thread_delay(1);
//printf("down[%d] len:%d sum:%d\r\n", i, len, bridge[i].tx_sum );
}
}
else
{
bridge[i].tx_dma_complete_timeout ++;
}
if(bridge[i].tx_dma_complete_timeout > 1000)
{
bridge[i].tx_idle = 1;
}
}
}
}
void serial_rx_thread_entry(void* parameter)
{
int i;
int rx_dma_cnt;
int timeout;
while(1)
{
for(i=1; i< ARRAY_SIZE(bridge); i++)
{
timeout = 0;
while(DMA0->COMMON[0].BUSY & (1 << bridge[i].rx_setup.chl))
{
timeout++;
if(timeout > 10000)
{
break;
}
}
DMA0->COMMON[0].ENABLECLR = (1 << bridge[i].rx_setup.chl);
rx_dma_cnt = sizeof(bridge[i].rdma_buf) - DMA_GetTransferCnt(bridge[i].rx_setup.chl);
if(rx_dma_cnt)
{
set_led(i, 0);
stat.total_in += rx_dma_cnt;
rt_ringbuffer_put(&bridge[i].rrb, bridge[i].rdma_buf, rx_dma_cnt);
bridge[i].rx_dma_sum += rx_dma_cnt;
}
DMA_SetupChl(&bridge[i].rx_setup);
DMA_SWTrigger(bridge[i].rx_setup.chl);
}
rt_thread_delay(1);
}
}
void usb_ctl_in_thread_entry(void* parameter)
{
int free;
/* waitting for usb readly */
while(usbd_is_configured() == false)
{
rt_thread_delay(rt_tick_from_millisecond(10));
}
while(1)
{
uint8_t buf[4];
buf[0] = 22;
buf[1] = usb_report_stat_chl;
buf[2] = 0;
buf[3] = 0;
free = bridge_uart_tx_get_free(usb_report_stat_chl);
if(free < 100)
{
buf[2] = 1; /* full */
}
else
{
buf[2] = 0; /* empty */
}
if(usb_ctl_need_report_stat)
{
usb_ctl_need_report_stat = 0;
// LOG_I("ctl in chl:%d %X\r\n", buf[1], buf[2]);
usbd_ep_write(2, buf, sizeof(buf));
}
rt_thread_delay(1);
}
}
void usb_data_in_thread_entry(void* parameter)
{
int len, i;
int usb_not_ready_cnt = 0;
int min_free, min_free_chl, free;
/* waitting for usb readly */
while(usbd_is_configured() == false)
{
rt_thread_delay(rt_tick_from_millisecond(10));
}
while(1)
{
min_free = 2048;
min_free_chl = 1;
/* find the buf is most likely full */
for(i=1; i< ARRAY_SIZE(bridge); i++)
{
free = bridge_uart_rx_get_free(i);
if(free < min_free)
{
min_free = free;
min_free_chl = i;
}
}
if(usb_in_ready)
{
usb_not_ready_cnt = 0;
//len = rt_ringbuffer_get(&bridge[min_free_chl].rrb, bridge[min_free_chl].rbuf, sizeof(bridge[min_free_chl].rbuf));
len = rt_ringbuffer_get(&bridge[min_free_chl].rrb, &bridge[min_free_chl].rbuf[3], sizeof(bridge[min_free_chl].rbuf)-3);
if(len)
{
usb_in_ready = 0;
bridge[min_free_chl].rx_sum += len;
//printf("up[%d] len:%d sum:%d\r\n", min_free_chl, len, bridge[min_free_chl].rx_sum);
bridge[min_free_chl].rbuf[0] = 19; /* DIGI_CMD_RECEIVE_DATA */
bridge[min_free_chl].rbuf[1] = min_free_chl;
bridge[min_free_chl].rbuf[2] = len;
usbd_ep_write(1, bridge[min_free_chl].rbuf, len+3);
//ulog_hexdump("TEST", 16, bridge[min_free_chl].rbuf, len);
//usbd_ep_write(1, bridge[min_free_chl].rbuf, len);
// rt_thread_delay(1);
}
else
{
rt_thread_delay(1);
}
// if(usb_in_ready)
// {
// rt_thread_delay(1);
// }
}
else
{
rt_thread_delay(1);
usb_not_ready_cnt++;
if(usb_not_ready_cnt > 1000)
{
usb_not_ready_cnt = 0;
usb_in_ready = 1;
}
}
}
}
void DMA0_IRQHandler(void)
{
int i;
static volatile uint32_t INTA;
INTA = DMA0->COMMON[0].INTA;
DMA0->COMMON[0].INTA = DMA0->COMMON[0].INTA;
if(INTA & (1 << DMAREQ_FLEXCOMM8_TX))
{
bridge[8].tx_idle = 1;
}
if(INTA & (1 << DMAREQ_FLEXCOMM9_TX))
{
bridge[9].tx_idle = 1;
}
for(i=1; i<ARRAY_SIZE(bridge); i++)
{
if(INTA & (1 << (i*2 + 1)))
{
bridge[i].tx_idle = 1;
}
}
rt_sem_release(utx_dma_complete);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/dma.c
|
/**
******************************************************************************
* @file dma.c
* @author YANDLD
* @version V3.0.0
* @date 2016.5.28
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "dma.h"
#include "common.h"
/* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase()
function if a DMA SRAM table is needed. */
ALIGN(512) DMA_Desc_t DMA_DescTbl[MAX_DMA_CHANNEL];
void DMA_Init(void)
{
/* enable dma clock gate */
#if defined(SYSCON_AHBCLKCTRL_DMA0_MASK)
SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_DMA0_MASK;
#else
SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_DMA_MASK;
#endif
/* set descriptor table */
DMA0->SRAMBASE = (uint32_t)DMA_DescTbl;
/* enable dma peripheral */
DMA0->CTRL |= DMA_CTRL_ENABLE_MASK;
}
void DMA_SetChlIntMode(uint32_t chl, bool val)
{
(val)?(DMA0->COMMON[0].INTENSET = (1 << chl)):(DMA0->COMMON[0].INTENCLR = (1 << chl));
NVIC_EnableIRQ(DMA0_IRQn);
}
void DMA_SWTrigger(uint32_t chl)
{
DMA0->CHANNEL[chl].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
}
void DMA_SetChlLink(uint8_t chl, DMA_Desc_t *list)
{
DMA_Desc_t *p = (DMA_Desc_t *) DMA0->SRAMBASE;
p[chl].next = (uint32_t)list;
DMA0->CHANNEL[chl].XFERCFG |= DMA_CHANNEL_XFERCFG_RELOAD_MASK;
}
uint32_t DMA_GetTransferCnt(uint8_t chl)
{
return ((DMA0->CHANNEL[chl].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1;
}
void DMA_CopyDesc(uint8_t ch, DMA_Desc_t *desc)
{
DMA_Desc_t *p = (DMA_Desc_t *) DMA0->SRAMBASE;
*desc = p[ch];
}
DMA_Desc_t *DMA_GetDesc(uint8_t ch)
{
DMA_Desc_t *p = (DMA_Desc_t *) DMA0->SRAMBASE;
return &p[ch];
}
void DMA_SetupChl(DMA_ChlSetup_t *setup)
{
uint8_t sInc, dInc;
DMA_Desc_t *p = (DMA_Desc_t *) DMA0->SRAMBASE;
DMA_Desc_t desc;
desc.next = NULL;
if(setup->transferCnt == 0)
{
return;
}
/* the actuall sAddr and dAddr is the end address */
desc.src = setup->sAddr + setup->dataWidth * setup->sAddrInc * (setup->transferCnt - 1);
desc.dest = setup->dAddr + setup->dataWidth * setup->dAddrInc * (setup->transferCnt - 1);
p[setup->chl] = desc;
sInc = setup->sAddrInc == 4 ? 3 : setup->sAddrInc;
dInc = setup->dAddrInc == 4 ? 3 : setup->dAddrInc;
/* DMA_CHANNEL_XFERCFG6_SRCINC : fixme when 4xwidth, it will be error */
DMA0->CHANNEL[setup->chl].XFERCFG = DMA_CHANNEL_XFERCFG_SETINTA_MASK |
DMA_CHANNEL_XFERCFG_XFERCOUNT(setup->transferCnt - 1) |
DMA_CHANNEL_XFERCFG_WIDTH(setup->dataWidth/2) |
DMA_CHANNEL_XFERCFG_SRCINC(sInc) |
DMA_CHANNEL_XFERCFG_DSTINC(dInc);
(setup->isPeriph)?(DMA0->CHANNEL[setup->chl].CFG = DMA_CHANNEL_CFG_PERIPHREQEN_MASK):(DMA0->CHANNEL[setup->chl].CFG = 0);
/* enable channel */
DMA0->COMMON[0].ENABLESET = (1 << setup->chl);
DMA0->COMMON[0].SETVALID = (1 << setup->chl);
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/rtthread/components/net/canfestival/slave_od/TaskSlave.h
|
/* File generated by gen_cfile.py. Should not be modified. */
#ifndef TASKSLAVE_H
#define TASKSLAVE_H
#include "data.h"
/* Prototypes of function provided by object dictionnary */
UNS32 TaskSlave_valueRangeTest (UNS8 typeValue, void * value);
const indextable * TaskSlave_scanIndexOD (CO_Data *d, UNS16 wIndex, UNS32 * errorCode);
/* Master node data struct */
extern CO_Data TaskSlave_Data;
extern INTEGER16 ACC[3]; /* Mapped at index 0x2000, subindex 0x01 - 0x03 */
extern INTEGER16 GYR[3]; /* Mapped at index 0x2001, subindex 0x01 - 0x03 */
extern INTEGER16 EUL[3]; /* Mapped at index 0x2003, subindex 0x01 - 0x03 */
extern INTEGER16 QUAT[4]; /* Mapped at index 0x2004, subindex 0x01 - 0x04 */
extern INTEGER32 CAN_BAUD; /* Mapped at index 0x2100, subindex 0x00*/
extern INTEGER32 NodeID; /* Mapped at index 0x2101, subindex 0x00*/
#endif // TASKSLAVE_H
|
yandld/lpc_uart_server
|
mcu_source/Libraries/startup/inc/MKV10Z7.h
|
<filename>mcu_source/Libraries/startup/inc/MKV10Z7.h
/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KV10P48M75RM Rev.2, July 2013
** Version: rev. 1.0, 2013-05-09
**
** Abstract:
** CMSIS Peripheral Access Layer for MKV10Z7
**
** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: <EMAIL>
**
** Revisions:
** - rev. 1.0 (2013-05-09)
** Initial version.
**
** ###################################################################
*/
/*!
* @file MKV10Z7.h
* @version 1.0
* @date 2013-05-09
* @brief CMSIS Peripheral Access Layer for MKV10Z7
*
* CMSIS Peripheral Access Layer for MKV10Z7
*/
#if !defined(MKV10Z7_H_)
#define MKV10Z7_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0100u
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
typedef enum IRQn {
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
/* Device specific interrupts */
DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
DMA_Error_IRQn = 4, /**< DMA channel 0 1 2 3 error */
FTFA_IRQn = 5, /**< Command complete and read collision */
PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
LLWU_IRQn = 7, /**< Low Leakage Wakeup */
I2C0_IRQn = 8, /**< I2C0 interrupt */
Reserved25_IRQn = 9, /**< Reserved interrupt */
SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
Reserved27_IRQn = 11, /**< Reserved interrupt */
UART0_IRQn = 12, /**< UART0 status and error */
UART1_IRQn = 13, /**< UART1 status and error */
Reserved30_IRQn = 14, /**< Reserved interrupt */
ADC0_IRQn = 15, /**< ADC0 interrupt */
ADC1_IRQn = 16, /**< ADC1 interrupt */
FTM0_IRQn = 17, /**< FTM0 single interrupt vector for all sources */
FTM1_IRQn = 18, /**< FTM1 single interrupt vector for all sources */
FTM2_IRQn = 19, /**< FTM2 single interrupt vector for all sources */
CMP0_IRQn = 20, /**< CMP0 interrupt */
CMP1_IRQn = 21, /**< CMP1 interrupt */
Reserved38_IRQn = 22, /**< Reserved interrupt */
WDOG_EWM_IRQn = 23, /**< Single interrupt vector for WDOG and EWM */
Reserved40_IRQn = 24, /**< Reserved interrupt */
DAC0_IRQn = 25, /**< DAC0 interrupt */
Reserved42_IRQn = 26, /**< Reserved interrupt */
MCG_IRQn = 27, /**< MCG interrupt */
LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
PDB0_IRQn = 29, /**< PDB0 interrupt */
PORTA_IRQn = 30, /**< GPIOA Pin detect */
PORTBCDE_IRQn = 31 /**< Single interrupt vector for GPIOB; GPIOC; GPIOD; GPIOE Pin detect */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M0 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm0plus.h" /* Core Peripheral Access Layer */
#include "system_MKV10Z7.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
__IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
__I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
__IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
__IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
__IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
__IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
__IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
__IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
__IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
__IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
__IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
__IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
__IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
__IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
__IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
__IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
__IO uint32_t PGA; /**< ADC PGA Register, offset: 0x50 */
__IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
__IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
__IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
__IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK 0x20u
#define ADC_SC1_DIFF_SHIFT 5
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK 0x4u
#define ADC_SC2_DMAEN_SHIFT 2
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
/* PG Bit Fields */
#define ADC_PG_PG_MASK 0xFFFFu
#define ADC_PG_PG_SHIFT 0
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
/* MG Bit Fields */
#define ADC_MG_MG_MASK 0xFFFFu
#define ADC_MG_MG_SHIFT 0
#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
/* CLPD Bit Fields */
#define ADC_CLPD_CLPD_MASK 0x3Fu
#define ADC_CLPD_CLPD_SHIFT 0
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
/* CLPS Bit Fields */
#define ADC_CLPS_CLPS_MASK 0x3Fu
#define ADC_CLPS_CLPS_SHIFT 0
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
/* CLP4 Bit Fields */
#define ADC_CLP4_CLP4_MASK 0x3FFu
#define ADC_CLP4_CLP4_SHIFT 0
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
/* CLP3 Bit Fields */
#define ADC_CLP3_CLP3_MASK 0x1FFu
#define ADC_CLP3_CLP3_SHIFT 0
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
/* CLP2 Bit Fields */
#define ADC_CLP2_CLP2_MASK 0xFFu
#define ADC_CLP2_CLP2_SHIFT 0
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
/* CLP1 Bit Fields */
#define ADC_CLP1_CLP1_MASK 0x7Fu
#define ADC_CLP1_CLP1_SHIFT 0
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
/* CLP0 Bit Fields */
#define ADC_CLP0_CLP0_MASK 0x3Fu
#define ADC_CLP0_CLP0_SHIFT 0
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
/* PGA Bit Fields */
#define ADC_PGA_PGAOFSM_MASK 0x4000u
#define ADC_PGA_PGAOFSM_SHIFT 14
#define ADC_PGA_PGAG_MASK 0xF0000u
#define ADC_PGA_PGAG_SHIFT 16
#define ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
#define ADC_PGA_PGALPb_MASK 0x100000u
#define ADC_PGA_PGALPb_SHIFT 20
#define ADC_PGA_PGACHPb_MASK 0x200000u
#define ADC_PGA_PGACHPb_SHIFT 21
#define ADC_PGA_PGAEN_MASK 0x800000u
#define ADC_PGA_PGAEN_SHIFT 23
/* CLMD Bit Fields */
#define ADC_CLMD_CLMD_MASK 0x3Fu
#define ADC_CLMD_CLMD_SHIFT 0
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
/* CLMS Bit Fields */
#define ADC_CLMS_CLMS_MASK 0x3Fu
#define ADC_CLMS_CLMS_SHIFT 0
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
/* CLM4 Bit Fields */
#define ADC_CLM4_CLM4_MASK 0x3FFu
#define ADC_CLM4_CLM4_SHIFT 0
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
/* CLM3 Bit Fields */
#define ADC_CLM3_CLM3_MASK 0x1FFu
#define ADC_CLM3_CLM3_SHIFT 0
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
/* CLM2 Bit Fields */
#define ADC_CLM2_CLM2_MASK 0xFFu
#define ADC_CLM2_CLM2_SHIFT 0
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
/* CLM1 Bit Fields */
#define ADC_CLM1_CLM1_MASK 0x7Fu
#define ADC_CLM1_CLM1_SHIFT 0
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
/* CLM0 Bit Fields */
#define ADC_CLM0_CLM0_MASK 0x3Fu
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
/** Peripheral ADC1 base address */
#define ADC1_BASE (0x4003C000u)
/** Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASES { ADC0, ADC1 }
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Register Layout Typedef */
typedef struct {
__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/* CR0 Bit Fields */
#define CMP_CR0_HYSTCTR_MASK 0x3u
#define CMP_CR0_HYSTCTR_SHIFT 0
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK 0x70u
#define CMP_CR0_FILTER_CNT_SHIFT 4
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
/* CR1 Bit Fields */
#define CMP_CR1_EN_MASK 0x1u
#define CMP_CR1_EN_SHIFT 0
#define CMP_CR1_OPE_MASK 0x2u
#define CMP_CR1_OPE_SHIFT 1
#define CMP_CR1_COS_MASK 0x4u
#define CMP_CR1_COS_SHIFT 2
#define CMP_CR1_INV_MASK 0x8u
#define CMP_CR1_INV_SHIFT 3
#define CMP_CR1_PMODE_MASK 0x10u
#define CMP_CR1_PMODE_SHIFT 4
#define CMP_CR1_TRIGM_MASK 0x20u
#define CMP_CR1_TRIGM_SHIFT 5
#define CMP_CR1_WE_MASK 0x40u
#define CMP_CR1_WE_SHIFT 6
#define CMP_CR1_SE_MASK 0x80u
#define CMP_CR1_SE_SHIFT 7
/* FPR Bit Fields */
#define CMP_FPR_FILT_PER_MASK 0xFFu
#define CMP_FPR_FILT_PER_SHIFT 0
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
/* SCR Bit Fields */
#define CMP_SCR_COUT_MASK 0x1u
#define CMP_SCR_COUT_SHIFT 0
#define CMP_SCR_CFF_MASK 0x2u
#define CMP_SCR_CFF_SHIFT 1
#define CMP_SCR_CFR_MASK 0x4u
#define CMP_SCR_CFR_SHIFT 2
#define CMP_SCR_IEF_MASK 0x8u
#define CMP_SCR_IEF_SHIFT 3
#define CMP_SCR_IER_MASK 0x10u
#define CMP_SCR_IER_SHIFT 4
#define CMP_SCR_DMAEN_MASK 0x40u
#define CMP_SCR_DMAEN_SHIFT 6
/* DACCR Bit Fields */
#define CMP_DACCR_VOSEL_MASK 0x3Fu
#define CMP_DACCR_VOSEL_SHIFT 0
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK 0x40u
#define CMP_DACCR_VRSEL_SHIFT 6
#define CMP_DACCR_DACEN_MASK 0x80u
#define CMP_DACCR_DACEN_SHIFT 7
/* MUXCR Bit Fields */
#define CMP_MUXCR_MSEL_MASK 0x7u
#define CMP_MUXCR_MSEL_SHIFT 0
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK 0x38u
#define CMP_MUXCR_PSEL_SHIFT 3
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base address */
#define CMP0_BASE (0x40073000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x40073008u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASES { CMP0, CMP1 }
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
* @{
*/
/** CRC - Register Layout Typedef */
typedef struct {
union { /* offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
__IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
} ACCESS16BIT;
__IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
__IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
__IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
__IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
} ACCESS8BIT;
};
union { /* offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
__IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
} GPOLY_ACCESS16BIT;
__IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
__IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
__IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
__IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
} GPOLY_ACCESS8BIT;
};
union { /* offset: 0x8 */
__IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
struct { /* offset: 0x8 */
uint8_t RESERVED_0[3];
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
} CRC_Type;
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/* DATAL Bit Fields */
#define CRC_DATAL_DATAL_MASK 0xFFFFu
#define CRC_DATAL_DATAL_SHIFT 0
#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
/* DATAH Bit Fields */
#define CRC_DATAH_DATAH_MASK 0xFFFFu
#define CRC_DATAH_DATAH_SHIFT 0
#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
/* DATA Bit Fields */
#define CRC_DATA_LL_MASK 0xFFu
#define CRC_DATA_LL_SHIFT 0
#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
#define CRC_DATA_LU_MASK 0xFF00u
#define CRC_DATA_LU_SHIFT 8
#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
#define CRC_DATA_HL_MASK 0xFF0000u
#define CRC_DATA_HL_SHIFT 16
#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
#define CRC_DATA_HU_MASK 0xFF000000u
#define CRC_DATA_HU_SHIFT 24
#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
/* DATALL Bit Fields */
#define CRC_DATALL_DATALL_MASK 0xFFu
#define CRC_DATALL_DATALL_SHIFT 0
#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
/* DATALU Bit Fields */
#define CRC_DATALU_DATALU_MASK 0xFFu
#define CRC_DATALU_DATALU_SHIFT 0
#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
/* DATAHL Bit Fields */
#define CRC_DATAHL_DATAHL_MASK 0xFFu
#define CRC_DATAHL_DATAHL_SHIFT 0
#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
/* DATAHU Bit Fields */
#define CRC_DATAHU_DATAHU_MASK 0xFFu
#define CRC_DATAHU_DATAHU_SHIFT 0
#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
/* GPOLYL Bit Fields */
#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
#define CRC_GPOLYL_GPOLYL_SHIFT 0
#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
/* GPOLYH Bit Fields */
#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
#define CRC_GPOLYH_GPOLYH_SHIFT 0
#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
/* GPOLY Bit Fields */
#define CRC_GPOLY_LOW_MASK 0xFFFFu
#define CRC_GPOLY_LOW_SHIFT 0
#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
#define CRC_GPOLY_HIGH_SHIFT 16
#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
/* GPOLYLL Bit Fields */
#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
/* GPOLYLU Bit Fields */
#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
/* GPOLYHL Bit Fields */
#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
/* GPOLYHU Bit Fields */
#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
/* CTRL Bit Fields */
#define CRC_CTRL_TCRC_MASK 0x1000000u
#define CRC_CTRL_TCRC_SHIFT 24
#define CRC_CTRL_WAS_MASK 0x2000000u
#define CRC_CTRL_WAS_SHIFT 25
#define CRC_CTRL_FXOR_MASK 0x4000000u
#define CRC_CTRL_FXOR_SHIFT 26
#define CRC_CTRL_TOTR_MASK 0x30000000u
#define CRC_CTRL_TOTR_SHIFT 28
#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
#define CRC_CTRL_TOT_MASK 0xC0000000u
#define CRC_CTRL_TOT_SHIFT 30
#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
/* CTRLHU Bit Fields */
#define CRC_CTRLHU_TCRC_MASK 0x1u
#define CRC_CTRLHU_TCRC_SHIFT 0
#define CRC_CTRLHU_WAS_MASK 0x2u
#define CRC_CTRLHU_WAS_SHIFT 1
#define CRC_CTRLHU_FXOR_MASK 0x4u
#define CRC_CTRLHU_FXOR_SHIFT 2
#define CRC_CTRLHU_TOTR_MASK 0x30u
#define CRC_CTRLHU_TOTR_SHIFT 4
#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
#define CRC_CTRLHU_TOT_MASK 0xC0u
#define CRC_CTRLHU_TOT_SHIFT 6
#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
/*!
* @}
*/ /* end of group CRC_Register_Masks */
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base address */
#define CRC_BASE (0x40032000u)
/** Peripheral CRC base pointer */
#define CRC0 ((CRC_Type *)CRC_BASE)
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASES { CRC0 }
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DAC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
* @{
*/
/** DAC - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x2 */
__IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
__IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
} DAT[2];
uint8_t RESERVED_0[28];
__IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
} DAC_Type;
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/* DATL Bit Fields */
#define DAC_DATL_DATA0_MASK 0xFFu
#define DAC_DATL_DATA0_SHIFT 0
#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
/* DATH Bit Fields */
#define DAC_DATH_DATA1_MASK 0xFu
#define DAC_DATH_DATA1_SHIFT 0
#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
/* SR Bit Fields */
#define DAC_SR_DACBFRPBF_MASK 0x1u
#define DAC_SR_DACBFRPBF_SHIFT 0
#define DAC_SR_DACBFRPTF_MASK 0x2u
#define DAC_SR_DACBFRPTF_SHIFT 1
#define DAC_SR_DACBFWMF_MASK 0x4u
#define DAC_SR_DACBFWMF_SHIFT 2
/* C0 Bit Fields */
#define DAC_C0_DACBBIEN_MASK 0x1u
#define DAC_C0_DACBBIEN_SHIFT 0
#define DAC_C0_DACBTIEN_MASK 0x2u
#define DAC_C0_DACBTIEN_SHIFT 1
#define DAC_C0_DACBWIEN_MASK 0x4u
#define DAC_C0_DACBWIEN_SHIFT 2
#define DAC_C0_LPEN_MASK 0x8u
#define DAC_C0_LPEN_SHIFT 3
#define DAC_C0_DACSWTRG_MASK 0x10u
#define DAC_C0_DACSWTRG_SHIFT 4
#define DAC_C0_DACTRGSEL_MASK 0x20u
#define DAC_C0_DACTRGSEL_SHIFT 5
#define DAC_C0_DACRFS_MASK 0x40u
#define DAC_C0_DACRFS_SHIFT 6
#define DAC_C0_DACEN_MASK 0x80u
#define DAC_C0_DACEN_SHIFT 7
/* C1 Bit Fields */
#define DAC_C1_DACBFEN_MASK 0x1u
#define DAC_C1_DACBFEN_SHIFT 0
#define DAC_C1_DACBFMD_MASK 0x6u
#define DAC_C1_DACBFMD_SHIFT 1
#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
#define DAC_C1_DACBFWM_MASK 0x18u
#define DAC_C1_DACBFWM_SHIFT 3
#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
#define DAC_C1_DMAEN_MASK 0x80u
#define DAC_C1_DMAEN_SHIFT 7
/* C2 Bit Fields */
#define DAC_C2_DACBFUP_MASK 0x1u
#define DAC_C2_DACBFUP_SHIFT 0
#define DAC_C2_DACBFRP_MASK 0x10u
#define DAC_C2_DACBFRP_SHIFT 4
/*!
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base address */
#define DAC0_BASE (0x4003F000u)
/** Peripheral DAC0 base pointer */
#define DAC0 ((DAC_Type *)DAC0_BASE)
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASES { DAC0 }
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< Control Register, offset: 0x0 */
__I uint32_t ES; /**< Error Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
uint8_t RESERVED_1[4];
__IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
__O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
__O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
__O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
__O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
uint8_t RESERVED_2[4];
__IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
uint8_t RESERVED_3[4];
__IO uint32_t ERR; /**< Error Register, offset: 0x2C */
uint8_t RESERVED_4[4];
__IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
uint8_t RESERVED_5[12];
__IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
uint8_t RESERVED_6[184];
__IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
__IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
__IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
__IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
uint8_t RESERVED_7[3836];
struct { /* offset: 0x1000, array step: 0x20 */
__IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
};
__IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
__IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
union { /* offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
};
__IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
union { /* offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[4];
} DMA_Type;
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/* CR Bit Fields */
#define DMA_CR_EDBG_MASK 0x2u
#define DMA_CR_EDBG_SHIFT 1
#define DMA_CR_ERCA_MASK 0x4u
#define DMA_CR_ERCA_SHIFT 2
#define DMA_CR_HOE_MASK 0x10u
#define DMA_CR_HOE_SHIFT 4
#define DMA_CR_HALT_MASK 0x20u
#define DMA_CR_HALT_SHIFT 5
#define DMA_CR_CLM_MASK 0x40u
#define DMA_CR_CLM_SHIFT 6
#define DMA_CR_EMLM_MASK 0x80u
#define DMA_CR_EMLM_SHIFT 7
#define DMA_CR_ECX_MASK 0x10000u
#define DMA_CR_ECX_SHIFT 16
#define DMA_CR_CX_MASK 0x20000u
#define DMA_CR_CX_SHIFT 17
/* ES Bit Fields */
#define DMA_ES_DBE_MASK 0x1u
#define DMA_ES_DBE_SHIFT 0
#define DMA_ES_SBE_MASK 0x2u
#define DMA_ES_SBE_SHIFT 1
#define DMA_ES_SGE_MASK 0x4u
#define DMA_ES_SGE_SHIFT 2
#define DMA_ES_NCE_MASK 0x8u
#define DMA_ES_NCE_SHIFT 3
#define DMA_ES_DOE_MASK 0x10u
#define DMA_ES_DOE_SHIFT 4
#define DMA_ES_DAE_MASK 0x20u
#define DMA_ES_DAE_SHIFT 5
#define DMA_ES_SOE_MASK 0x40u
#define DMA_ES_SOE_SHIFT 6
#define DMA_ES_SAE_MASK 0x80u
#define DMA_ES_SAE_SHIFT 7
#define DMA_ES_ERRCHN_MASK 0x300u
#define DMA_ES_ERRCHN_SHIFT 8
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK 0x4000u
#define DMA_ES_CPE_SHIFT 14
#define DMA_ES_ECX_MASK 0x10000u
#define DMA_ES_ECX_SHIFT 16
#define DMA_ES_VLD_MASK 0x80000000u
#define DMA_ES_VLD_SHIFT 31
/* ERQ Bit Fields */
#define DMA_ERQ_ERQ0_MASK 0x1u
#define DMA_ERQ_ERQ0_SHIFT 0
#define DMA_ERQ_ERQ1_MASK 0x2u
#define DMA_ERQ_ERQ1_SHIFT 1
#define DMA_ERQ_ERQ2_MASK 0x4u
#define DMA_ERQ_ERQ2_SHIFT 2
#define DMA_ERQ_ERQ3_MASK 0x8u
#define DMA_ERQ_ERQ3_SHIFT 3
/* EEI Bit Fields */
#define DMA_EEI_EEI0_MASK 0x1u
#define DMA_EEI_EEI0_SHIFT 0
#define DMA_EEI_EEI1_MASK 0x2u
#define DMA_EEI_EEI1_SHIFT 1
#define DMA_EEI_EEI2_MASK 0x4u
#define DMA_EEI_EEI2_SHIFT 2
#define DMA_EEI_EEI3_MASK 0x8u
#define DMA_EEI_EEI3_SHIFT 3
/* CEEI Bit Fields */
#define DMA_CEEI_CEEI_MASK 0x3u
#define DMA_CEEI_CEEI_SHIFT 0
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK 0x40u
#define DMA_CEEI_CAEE_SHIFT 6
#define DMA_CEEI_NOP_MASK 0x80u
#define DMA_CEEI_NOP_SHIFT 7
/* SEEI Bit Fields */
#define DMA_SEEI_SEEI_MASK 0x3u
#define DMA_SEEI_SEEI_SHIFT 0
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK 0x40u
#define DMA_SEEI_SAEE_SHIFT 6
#define DMA_SEEI_NOP_MASK 0x80u
#define DMA_SEEI_NOP_SHIFT 7
/* CERQ Bit Fields */
#define DMA_CERQ_CERQ_MASK 0x3u
#define DMA_CERQ_CERQ_SHIFT 0
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK 0x40u
#define DMA_CERQ_CAER_SHIFT 6
#define DMA_CERQ_NOP_MASK 0x80u
#define DMA_CERQ_NOP_SHIFT 7
/* SERQ Bit Fields */
#define DMA_SERQ_SERQ_MASK 0x3u
#define DMA_SERQ_SERQ_SHIFT 0
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK 0x40u
#define DMA_SERQ_SAER_SHIFT 6
#define DMA_SERQ_NOP_MASK 0x80u
#define DMA_SERQ_NOP_SHIFT 7
/* CDNE Bit Fields */
#define DMA_CDNE_CDNE_MASK 0x3u
#define DMA_CDNE_CDNE_SHIFT 0
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK 0x40u
#define DMA_CDNE_CADN_SHIFT 6
#define DMA_CDNE_NOP_MASK 0x80u
#define DMA_CDNE_NOP_SHIFT 7
/* SSRT Bit Fields */
#define DMA_SSRT_SSRT_MASK 0x3u
#define DMA_SSRT_SSRT_SHIFT 0
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK 0x40u
#define DMA_SSRT_SAST_SHIFT 6
#define DMA_SSRT_NOP_MASK 0x80u
#define DMA_SSRT_NOP_SHIFT 7
/* CERR Bit Fields */
#define DMA_CERR_CERR_MASK 0x3u
#define DMA_CERR_CERR_SHIFT 0
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK 0x40u
#define DMA_CERR_CAEI_SHIFT 6
#define DMA_CERR_NOP_MASK 0x80u
#define DMA_CERR_NOP_SHIFT 7
/* CINT Bit Fields */
#define DMA_CINT_CINT_MASK 0x3u
#define DMA_CINT_CINT_SHIFT 0
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK 0x40u
#define DMA_CINT_CAIR_SHIFT 6
#define DMA_CINT_NOP_MASK 0x80u
#define DMA_CINT_NOP_SHIFT 7
/* INT Bit Fields */
#define DMA_INT_INT0_MASK 0x1u
#define DMA_INT_INT0_SHIFT 0
#define DMA_INT_INT1_MASK 0x2u
#define DMA_INT_INT1_SHIFT 1
#define DMA_INT_INT2_MASK 0x4u
#define DMA_INT_INT2_SHIFT 2
#define DMA_INT_INT3_MASK 0x8u
#define DMA_INT_INT3_SHIFT 3
/* ERR Bit Fields */
#define DMA_ERR_ERR0_MASK 0x1u
#define DMA_ERR_ERR0_SHIFT 0
#define DMA_ERR_ERR1_MASK 0x2u
#define DMA_ERR_ERR1_SHIFT 1
#define DMA_ERR_ERR2_MASK 0x4u
#define DMA_ERR_ERR2_SHIFT 2
#define DMA_ERR_ERR3_MASK 0x8u
#define DMA_ERR_ERR3_SHIFT 3
/* HRS Bit Fields */
#define DMA_HRS_HRS0_MASK 0x1u
#define DMA_HRS_HRS0_SHIFT 0
#define DMA_HRS_HRS1_MASK 0x2u
#define DMA_HRS_HRS1_SHIFT 1
#define DMA_HRS_HRS2_MASK 0x4u
#define DMA_HRS_HRS2_SHIFT 2
#define DMA_HRS_HRS3_MASK 0x8u
#define DMA_HRS_HRS3_SHIFT 3
/* EARS Bit Fields */
#define DMA_EARS_EDREQ_0_MASK 0x1u
#define DMA_EARS_EDREQ_0_SHIFT 0
#define DMA_EARS_EDREQ_1_MASK 0x2u
#define DMA_EARS_EDREQ_1_SHIFT 1
#define DMA_EARS_EDREQ_2_MASK 0x4u
#define DMA_EARS_EDREQ_2_SHIFT 2
#define DMA_EARS_EDREQ_3_MASK 0x8u
#define DMA_EARS_EDREQ_3_SHIFT 3
/* DCHPRI3 Bit Fields */
#define DMA_DCHPRI3_CHPRI_MASK 0x3u
#define DMA_DCHPRI3_CHPRI_SHIFT 0
#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
#define DMA_DCHPRI3_DPA_MASK 0x40u
#define DMA_DCHPRI3_DPA_SHIFT 6
#define DMA_DCHPRI3_ECP_MASK 0x80u
#define DMA_DCHPRI3_ECP_SHIFT 7
/* DCHPRI2 Bit Fields */
#define DMA_DCHPRI2_CHPRI_MASK 0x3u
#define DMA_DCHPRI2_CHPRI_SHIFT 0
#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
#define DMA_DCHPRI2_DPA_MASK 0x40u
#define DMA_DCHPRI2_DPA_SHIFT 6
#define DMA_DCHPRI2_ECP_MASK 0x80u
#define DMA_DCHPRI2_ECP_SHIFT 7
/* DCHPRI1 Bit Fields */
#define DMA_DCHPRI1_CHPRI_MASK 0x3u
#define DMA_DCHPRI1_CHPRI_SHIFT 0
#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
#define DMA_DCHPRI1_DPA_MASK 0x40u
#define DMA_DCHPRI1_DPA_SHIFT 6
#define DMA_DCHPRI1_ECP_MASK 0x80u
#define DMA_DCHPRI1_ECP_SHIFT 7
/* DCHPRI0 Bit Fields */
#define DMA_DCHPRI0_CHPRI_MASK 0x3u
#define DMA_DCHPRI0_CHPRI_SHIFT 0
#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
#define DMA_DCHPRI0_DPA_MASK 0x40u
#define DMA_DCHPRI0_DPA_SHIFT 6
#define DMA_DCHPRI0_ECP_MASK 0x80u
#define DMA_DCHPRI0_ECP_SHIFT 7
/* SADDR Bit Fields */
#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
#define DMA_SADDR_SADDR_SHIFT 0
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
/* SOFF Bit Fields */
#define DMA_SOFF_SOFF_MASK 0xFFFFu
#define DMA_SOFF_SOFF_SHIFT 0
#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
/* ATTR Bit Fields */
#define DMA_ATTR_DSIZE_MASK 0x7u
#define DMA_ATTR_DSIZE_SHIFT 0
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
#define DMA_ATTR_DMOD_MASK 0xF8u
#define DMA_ATTR_DMOD_SHIFT 3
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
#define DMA_ATTR_SSIZE_MASK 0x700u
#define DMA_ATTR_SSIZE_SHIFT 8
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
#define DMA_ATTR_SMOD_MASK 0xF800u
#define DMA_ATTR_SMOD_SHIFT 11
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
/* NBYTES_MLNO Bit Fields */
#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
/* NBYTES_MLOFFNO Bit Fields */
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
/* NBYTES_MLOFFYES Bit Fields */
#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
/* SLAST Bit Fields */
#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
#define DMA_SLAST_SLAST_SHIFT 0
#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
/* DADDR Bit Fields */
#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
#define DMA_DADDR_DADDR_SHIFT 0
#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
/* DOFF Bit Fields */
#define DMA_DOFF_DOFF_MASK 0xFFFFu
#define DMA_DOFF_DOFF_SHIFT 0
#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
/* CITER_ELINKNO Bit Fields */
#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
#define DMA_CITER_ELINKNO_CITER_SHIFT 0
#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
/* CITER_ELINKYES Bit Fields */
#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
#define DMA_CITER_ELINKYES_CITER_SHIFT 0
#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
#define DMA_CITER_ELINKYES_LINKCH_MASK 0x600u
#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
/* DLAST_SGA Bit Fields */
#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
/* CSR Bit Fields */
#define DMA_CSR_START_MASK 0x1u
#define DMA_CSR_START_SHIFT 0
#define DMA_CSR_INTMAJOR_MASK 0x2u
#define DMA_CSR_INTMAJOR_SHIFT 1
#define DMA_CSR_INTHALF_MASK 0x4u
#define DMA_CSR_INTHALF_SHIFT 2
#define DMA_CSR_DREQ_MASK 0x8u
#define DMA_CSR_DREQ_SHIFT 3
#define DMA_CSR_ESG_MASK 0x10u
#define DMA_CSR_ESG_SHIFT 4
#define DMA_CSR_MAJORELINK_MASK 0x20u
#define DMA_CSR_MAJORELINK_SHIFT 5
#define DMA_CSR_ACTIVE_MASK 0x40u
#define DMA_CSR_ACTIVE_SHIFT 6
#define DMA_CSR_DONE_MASK 0x80u
#define DMA_CSR_DONE_SHIFT 7
#define DMA_CSR_MAJORLINKCH_MASK 0x300u
#define DMA_CSR_MAJORLINKCH_SHIFT 8
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
#define DMA_CSR_BWC_MASK 0xC000u
#define DMA_CSR_BWC_SHIFT 14
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
/* BITER_ELINKNO Bit Fields */
#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
#define DMA_BITER_ELINKNO_BITER_SHIFT 0
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
/* BITER_ELINKYES Bit Fields */
#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
#define DMA_BITER_ELINKYES_BITER_SHIFT 0
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
#define DMA_BITER_ELINKYES_LINKCH_MASK 0x600u
#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
/*!
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral DMA base address */
#define DMA_BASE (0x40008000u)
/** Peripheral DMA base pointer */
#define DMA0 ((DMA_Type *)DMA_BASE)
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASES { DMA0 }
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMAMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
* @{
*/
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
} DMAMUX_Type;
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
/* CHCFG Bit Fields */
#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
#define DMAMUX_CHCFG_SOURCE_SHIFT 0
#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
#define DMAMUX_CHCFG_TRIG_MASK 0x40u
#define DMAMUX_CHCFG_TRIG_SHIFT 6
#define DMAMUX_CHCFG_ENBL_MASK 0x80u
#define DMAMUX_CHCFG_ENBL_SHIFT 7
/*!
* @}
*/ /* end of group DMAMUX_Register_Masks */
/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX base address */
#define DMAMUX_BASE (0x40021000u)
/** Peripheral DMAMUX base pointer */
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASES { DMAMUX }
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EWM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
* @{
*/
/** EWM - Register Layout Typedef */
typedef struct {
__IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
__O uint8_t SERV; /**< Service Register, offset: 0x1 */
__IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
__IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
__IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */
__IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
} EWM_Type;
/* ----------------------------------------------------------------------------
-- EWM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Register_Masks EWM Register Masks
* @{
*/
/* CTRL Bit Fields */
#define EWM_CTRL_EWMEN_MASK 0x1u
#define EWM_CTRL_EWMEN_SHIFT 0
#define EWM_CTRL_ASSIN_MASK 0x2u
#define EWM_CTRL_ASSIN_SHIFT 1
#define EWM_CTRL_INEN_MASK 0x4u
#define EWM_CTRL_INEN_SHIFT 2
#define EWM_CTRL_INTEN_MASK 0x8u
#define EWM_CTRL_INTEN_SHIFT 3
/* SERV Bit Fields */
#define EWM_SERV_SERVICE_MASK 0xFFu
#define EWM_SERV_SERVICE_SHIFT 0
#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
/* CMPL Bit Fields */
#define EWM_CMPL_COMPAREL_MASK 0xFFu
#define EWM_CMPL_COMPAREL_SHIFT 0
#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
/* CMPH Bit Fields */
#define EWM_CMPH_COMPAREH_MASK 0xFFu
#define EWM_CMPH_COMPAREH_SHIFT 0
#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
/* CLKCTRL Bit Fields */
#define EWM_CLKCTRL_CLKSEL_MASK 0x3u
#define EWM_CLKCTRL_CLKSEL_SHIFT 0
#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKCTRL_CLKSEL_SHIFT))&EWM_CLKCTRL_CLKSEL_MASK)
/* CLKPRESCALER Bit Fields */
#define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
#define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
/*!
* @}
*/ /* end of group EWM_Register_Masks */
/* EWM - Peripheral instance base addresses */
/** Peripheral EWM base address */
#define EWM_BASE (0x40061000u)
/** Peripheral EWM base pointer */
#define EWM ((EWM_Type *)EWM_BASE)
/** Array initializer of EWM peripheral base pointers */
#define EWM_BASES { EWM }
/*!
* @}
*/ /* end of group EWM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FTFA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
* @{
*/
/** FTFA - Register Layout Typedef */
typedef struct {
__IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
__IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
__I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
__I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
__IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
__IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
__IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
__IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
__IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
__IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
__IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
__IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
__IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
__IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
__IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
__IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
__IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
__IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
__IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
__IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
} FTFA_Type;
/* ----------------------------------------------------------------------------
-- FTFA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Masks FTFA Register Masks
* @{
*/
/* FSTAT Bit Fields */
#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
#define FTFA_FSTAT_MGSTAT0_SHIFT 0
#define FTFA_FSTAT_FPVIOL_MASK 0x10u
#define FTFA_FSTAT_FPVIOL_SHIFT 4
#define FTFA_FSTAT_ACCERR_MASK 0x20u
#define FTFA_FSTAT_ACCERR_SHIFT 5
#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
#define FTFA_FSTAT_RDCOLERR_SHIFT 6
#define FTFA_FSTAT_CCIF_MASK 0x80u
#define FTFA_FSTAT_CCIF_SHIFT 7
/* FCNFG Bit Fields */
#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
#define FTFA_FCNFG_ERSSUSP_SHIFT 4
#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
#define FTFA_FCNFG_ERSAREQ_SHIFT 5
#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
#define FTFA_FCNFG_CCIE_MASK 0x80u
#define FTFA_FCNFG_CCIE_SHIFT 7
/* FSEC Bit Fields */
#define FTFA_FSEC_SEC_MASK 0x3u
#define FTFA_FSEC_SEC_SHIFT 0
#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
#define FTFA_FSEC_FSLACC_MASK 0xCu
#define FTFA_FSEC_FSLACC_SHIFT 2
#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
#define FTFA_FSEC_MEEN_MASK 0x30u
#define FTFA_FSEC_MEEN_SHIFT 4
#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
#define FTFA_FSEC_KEYEN_MASK 0xC0u
#define FTFA_FSEC_KEYEN_SHIFT 6
#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
/* FOPT Bit Fields */
#define FTFA_FOPT_OPT_MASK 0xFFu
#define FTFA_FOPT_OPT_SHIFT 0
#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
/* FCCOB3 Bit Fields */
#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
#define FTFA_FCCOB3_CCOBn_SHIFT 0
#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
/* FCCOB2 Bit Fields */
#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
#define FTFA_FCCOB2_CCOBn_SHIFT 0
#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
/* FCCOB1 Bit Fields */
#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
#define FTFA_FCCOB1_CCOBn_SHIFT 0
#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
/* FCCOB0 Bit Fields */
#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
#define FTFA_FCCOB0_CCOBn_SHIFT 0
#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
/* FCCOB7 Bit Fields */
#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
#define FTFA_FCCOB7_CCOBn_SHIFT 0
#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
/* FCCOB6 Bit Fields */
#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
#define FTFA_FCCOB6_CCOBn_SHIFT 0
#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
/* FCCOB5 Bit Fields */
#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
#define FTFA_FCCOB5_CCOBn_SHIFT 0
#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
/* FCCOB4 Bit Fields */
#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
#define FTFA_FCCOB4_CCOBn_SHIFT 0
#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
/* FCCOBB Bit Fields */
#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
#define FTFA_FCCOBB_CCOBn_SHIFT 0
#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
/* FCCOBA Bit Fields */
#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
#define FTFA_FCCOBA_CCOBn_SHIFT 0
#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
/* FCCOB9 Bit Fields */
#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
#define FTFA_FCCOB9_CCOBn_SHIFT 0
#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
/* FCCOB8 Bit Fields */
#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
#define FTFA_FCCOB8_CCOBn_SHIFT 0
#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
/* FPROT3 Bit Fields */
#define FTFA_FPROT3_PROT_MASK 0xFFu
#define FTFA_FPROT3_PROT_SHIFT 0
#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
/* FPROT2 Bit Fields */
#define FTFA_FPROT2_PROT_MASK 0xFFu
#define FTFA_FPROT2_PROT_SHIFT 0
#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
/* FPROT1 Bit Fields */
#define FTFA_FPROT1_PROT_MASK 0xFFu
#define FTFA_FPROT1_PROT_SHIFT 0
#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
/* FPROT0 Bit Fields */
#define FTFA_FPROT0_PROT_MASK 0xFFu
#define FTFA_FPROT0_PROT_SHIFT 0
#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
/*!
* @}
*/ /* end of group FTFA_Register_Masks */
/* FTFA - Peripheral instance base addresses */
/** Peripheral FTFA base address */
#define FTFA_BASE (0x40020000u)
/** Peripheral FTFA base pointer */
#define FTFA ((FTFA_Type *)FTFA_BASE)
/** Array initializer of FTFA peripheral base pointers */
#define FTFA_BASES { FTFA }
/*!
* @}
*/ /* end of group FTFA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FTM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
* @{
*/
/** FTM - Register Layout Typedef */
typedef struct {
__IO uint32_t SC; /**< Status And Control, offset: 0x0 */
__IO uint32_t CNT; /**< Counter, offset: 0x4 */
__IO uint32_t MOD; /**< Modulo, offset: 0x8 */
struct { /* offset: 0xC, array step: 0x8 */
__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
} CONTROLS[6];
uint8_t RESERVED_0[16];
__IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
__I uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
__IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
__IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
__IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
__IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
__IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
__IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
__IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
__IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
__IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
__IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
__IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
__IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
__IO uint32_t CONF; /**< Configuration, offset: 0x84 */
__IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
__IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
__IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
__IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
__IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
} FTM_Type;
/* ----------------------------------------------------------------------------
-- FTM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTM_Register_Masks FTM Register Masks
* @{
*/
/* SC Bit Fields */
#define FTM_SC_PS_MASK 0x7u
#define FTM_SC_PS_SHIFT 0
#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
#define FTM_SC_CLKS_MASK 0x18u
#define FTM_SC_CLKS_SHIFT 3
#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
#define FTM_SC_CPWMS_MASK 0x20u
#define FTM_SC_CPWMS_SHIFT 5
#define FTM_SC_TOIE_MASK 0x40u
#define FTM_SC_TOIE_SHIFT 6
#define FTM_SC_TOF_MASK 0x80u
#define FTM_SC_TOF_SHIFT 7
/* CNT Bit Fields */
#define FTM_CNT_COUNT_MASK 0xFFFFu
#define FTM_CNT_COUNT_SHIFT 0
#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
/* MOD Bit Fields */
#define FTM_MOD_MOD_MASK 0xFFFFu
#define FTM_MOD_MOD_SHIFT 0
#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
/* CnSC Bit Fields */
#define FTM_CnSC_DMA_MASK 0x1u
#define FTM_CnSC_DMA_SHIFT 0
#define FTM_CnSC_ICRST_MASK 0x2u
#define FTM_CnSC_ICRST_SHIFT 1
#define FTM_CnSC_ELSA_MASK 0x4u
#define FTM_CnSC_ELSA_SHIFT 2
#define FTM_CnSC_ELSB_MASK 0x8u
#define FTM_CnSC_ELSB_SHIFT 3
#define FTM_CnSC_MSA_MASK 0x10u
#define FTM_CnSC_MSA_SHIFT 4
#define FTM_CnSC_MSB_MASK 0x20u
#define FTM_CnSC_MSB_SHIFT 5
#define FTM_CnSC_CHIE_MASK 0x40u
#define FTM_CnSC_CHIE_SHIFT 6
#define FTM_CnSC_CHF_MASK 0x80u
#define FTM_CnSC_CHF_SHIFT 7
/* CnV Bit Fields */
#define FTM_CnV_VAL_MASK 0xFFFFu
#define FTM_CnV_VAL_SHIFT 0
#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
/* CNTIN Bit Fields */
#define FTM_CNTIN_INIT_MASK 0xFFFFu
#define FTM_CNTIN_INIT_SHIFT 0
#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
/* STATUS Bit Fields */
#define FTM_STATUS_CH0F_MASK 0x1u
#define FTM_STATUS_CH0F_SHIFT 0
#define FTM_STATUS_CH1F_MASK 0x2u
#define FTM_STATUS_CH1F_SHIFT 1
#define FTM_STATUS_CH2F_MASK 0x4u
#define FTM_STATUS_CH2F_SHIFT 2
#define FTM_STATUS_CH3F_MASK 0x8u
#define FTM_STATUS_CH3F_SHIFT 3
#define FTM_STATUS_CH4F_MASK 0x10u
#define FTM_STATUS_CH4F_SHIFT 4
#define FTM_STATUS_CH5F_MASK 0x20u
#define FTM_STATUS_CH5F_SHIFT 5
#define FTM_STATUS_CH6F_MASK 0x40u
#define FTM_STATUS_CH6F_SHIFT 6
#define FTM_STATUS_CH7F_MASK 0x80u
#define FTM_STATUS_CH7F_SHIFT 7
/* MODE Bit Fields */
#define FTM_MODE_FTMEN_MASK 0x1u
#define FTM_MODE_FTMEN_SHIFT 0
#define FTM_MODE_INIT_MASK 0x2u
#define FTM_MODE_INIT_SHIFT 1
#define FTM_MODE_WPDIS_MASK 0x4u
#define FTM_MODE_WPDIS_SHIFT 2
#define FTM_MODE_PWMSYNC_MASK 0x8u
#define FTM_MODE_PWMSYNC_SHIFT 3
#define FTM_MODE_CAPTEST_MASK 0x10u
#define FTM_MODE_CAPTEST_SHIFT 4
#define FTM_MODE_FAULTM_MASK 0x60u
#define FTM_MODE_FAULTM_SHIFT 5
#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
#define FTM_MODE_FAULTIE_MASK 0x80u
#define FTM_MODE_FAULTIE_SHIFT 7
/* SYNC Bit Fields */
#define FTM_SYNC_CNTMIN_MASK 0x1u
#define FTM_SYNC_CNTMIN_SHIFT 0
#define FTM_SYNC_CNTMAX_MASK 0x2u
#define FTM_SYNC_CNTMAX_SHIFT 1
#define FTM_SYNC_REINIT_MASK 0x4u
#define FTM_SYNC_REINIT_SHIFT 2
#define FTM_SYNC_SYNCHOM_MASK 0x8u
#define FTM_SYNC_SYNCHOM_SHIFT 3
#define FTM_SYNC_TRIG0_MASK 0x10u
#define FTM_SYNC_TRIG0_SHIFT 4
#define FTM_SYNC_TRIG1_MASK 0x20u
#define FTM_SYNC_TRIG1_SHIFT 5
#define FTM_SYNC_TRIG2_MASK 0x40u
#define FTM_SYNC_TRIG2_SHIFT 6
#define FTM_SYNC_SWSYNC_MASK 0x80u
#define FTM_SYNC_SWSYNC_SHIFT 7
/* OUTINIT Bit Fields */
#define FTM_OUTINIT_CH0OI_MASK 0x1u
#define FTM_OUTINIT_CH0OI_SHIFT 0
#define FTM_OUTINIT_CH1OI_MASK 0x2u
#define FTM_OUTINIT_CH1OI_SHIFT 1
#define FTM_OUTINIT_CH2OI_MASK 0x4u
#define FTM_OUTINIT_CH2OI_SHIFT 2
#define FTM_OUTINIT_CH3OI_MASK 0x8u
#define FTM_OUTINIT_CH3OI_SHIFT 3
#define FTM_OUTINIT_CH4OI_MASK 0x10u
#define FTM_OUTINIT_CH4OI_SHIFT 4
#define FTM_OUTINIT_CH5OI_MASK 0x20u
#define FTM_OUTINIT_CH5OI_SHIFT 5
#define FTM_OUTINIT_CH6OI_MASK 0x40u
#define FTM_OUTINIT_CH6OI_SHIFT 6
#define FTM_OUTINIT_CH7OI_MASK 0x80u
#define FTM_OUTINIT_CH7OI_SHIFT 7
/* OUTMASK Bit Fields */
#define FTM_OUTMASK_CH0OM_MASK 0x1u
#define FTM_OUTMASK_CH0OM_SHIFT 0
#define FTM_OUTMASK_CH1OM_MASK 0x2u
#define FTM_OUTMASK_CH1OM_SHIFT 1
#define FTM_OUTMASK_CH2OM_MASK 0x4u
#define FTM_OUTMASK_CH2OM_SHIFT 2
#define FTM_OUTMASK_CH3OM_MASK 0x8u
#define FTM_OUTMASK_CH3OM_SHIFT 3
#define FTM_OUTMASK_CH4OM_MASK 0x10u
#define FTM_OUTMASK_CH4OM_SHIFT 4
#define FTM_OUTMASK_CH5OM_MASK 0x20u
#define FTM_OUTMASK_CH5OM_SHIFT 5
#define FTM_OUTMASK_CH6OM_MASK 0x40u
#define FTM_OUTMASK_CH6OM_SHIFT 6
#define FTM_OUTMASK_CH7OM_MASK 0x80u
#define FTM_OUTMASK_CH7OM_SHIFT 7
/* COMBINE Bit Fields */
#define FTM_COMBINE_COMBINE0_MASK 0x1u
#define FTM_COMBINE_COMBINE0_SHIFT 0
#define FTM_COMBINE_COMP0_MASK 0x2u
#define FTM_COMBINE_COMP0_SHIFT 1
#define FTM_COMBINE_DECAPEN0_MASK 0x4u
#define FTM_COMBINE_DECAPEN0_SHIFT 2
#define FTM_COMBINE_DECAP0_MASK 0x8u
#define FTM_COMBINE_DECAP0_SHIFT 3
#define FTM_COMBINE_DTEN0_MASK 0x10u
#define FTM_COMBINE_DTEN0_SHIFT 4
#define FTM_COMBINE_SYNCEN0_MASK 0x20u
#define FTM_COMBINE_SYNCEN0_SHIFT 5
#define FTM_COMBINE_FAULTEN0_MASK 0x40u
#define FTM_COMBINE_FAULTEN0_SHIFT 6
#define FTM_COMBINE_COMBINE1_MASK 0x100u
#define FTM_COMBINE_COMBINE1_SHIFT 8
#define FTM_COMBINE_COMP1_MASK 0x200u
#define FTM_COMBINE_COMP1_SHIFT 9
#define FTM_COMBINE_DECAPEN1_MASK 0x400u
#define FTM_COMBINE_DECAPEN1_SHIFT 10
#define FTM_COMBINE_DECAP1_MASK 0x800u
#define FTM_COMBINE_DECAP1_SHIFT 11
#define FTM_COMBINE_DTEN1_MASK 0x1000u
#define FTM_COMBINE_DTEN1_SHIFT 12
#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
#define FTM_COMBINE_SYNCEN1_SHIFT 13
#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
#define FTM_COMBINE_FAULTEN1_SHIFT 14
#define FTM_COMBINE_COMBINE2_MASK 0x10000u
#define FTM_COMBINE_COMBINE2_SHIFT 16
#define FTM_COMBINE_COMP2_MASK 0x20000u
#define FTM_COMBINE_COMP2_SHIFT 17
#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
#define FTM_COMBINE_DECAPEN2_SHIFT 18
#define FTM_COMBINE_DECAP2_MASK 0x80000u
#define FTM_COMBINE_DECAP2_SHIFT 19
#define FTM_COMBINE_DTEN2_MASK 0x100000u
#define FTM_COMBINE_DTEN2_SHIFT 20
#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
#define FTM_COMBINE_SYNCEN2_SHIFT 21
#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
#define FTM_COMBINE_FAULTEN2_SHIFT 22
#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
#define FTM_COMBINE_COMBINE3_SHIFT 24
#define FTM_COMBINE_COMP3_MASK 0x2000000u
#define FTM_COMBINE_COMP3_SHIFT 25
#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
#define FTM_COMBINE_DECAPEN3_SHIFT 26
#define FTM_COMBINE_DECAP3_MASK 0x8000000u
#define FTM_COMBINE_DECAP3_SHIFT 27
#define FTM_COMBINE_DTEN3_MASK 0x10000000u
#define FTM_COMBINE_DTEN3_SHIFT 28
#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
#define FTM_COMBINE_SYNCEN3_SHIFT 29
#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
#define FTM_COMBINE_FAULTEN3_SHIFT 30
/* DEADTIME Bit Fields */
#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
#define FTM_DEADTIME_DTVAL_SHIFT 0
#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
#define FTM_DEADTIME_DTPS_MASK 0xC0u
#define FTM_DEADTIME_DTPS_SHIFT 6
#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
/* EXTTRIG Bit Fields */
#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
#define FTM_EXTTRIG_TRIGF_MASK 0x80u
#define FTM_EXTTRIG_TRIGF_SHIFT 7
/* POL Bit Fields */
#define FTM_POL_POL0_MASK 0x1u
#define FTM_POL_POL0_SHIFT 0
#define FTM_POL_POL1_MASK 0x2u
#define FTM_POL_POL1_SHIFT 1
#define FTM_POL_POL2_MASK 0x4u
#define FTM_POL_POL2_SHIFT 2
#define FTM_POL_POL3_MASK 0x8u
#define FTM_POL_POL3_SHIFT 3
#define FTM_POL_POL4_MASK 0x10u
#define FTM_POL_POL4_SHIFT 4
#define FTM_POL_POL5_MASK 0x20u
#define FTM_POL_POL5_SHIFT 5
#define FTM_POL_POL6_MASK 0x40u
#define FTM_POL_POL6_SHIFT 6
#define FTM_POL_POL7_MASK 0x80u
#define FTM_POL_POL7_SHIFT 7
/* FMS Bit Fields */
#define FTM_FMS_FAULTF0_MASK 0x1u
#define FTM_FMS_FAULTF0_SHIFT 0
#define FTM_FMS_FAULTF1_MASK 0x2u
#define FTM_FMS_FAULTF1_SHIFT 1
#define FTM_FMS_FAULTF2_MASK 0x4u
#define FTM_FMS_FAULTF2_SHIFT 2
#define FTM_FMS_FAULTF3_MASK 0x8u
#define FTM_FMS_FAULTF3_SHIFT 3
#define FTM_FMS_FAULTIN_MASK 0x20u
#define FTM_FMS_FAULTIN_SHIFT 5
#define FTM_FMS_WPEN_MASK 0x40u
#define FTM_FMS_WPEN_SHIFT 6
#define FTM_FMS_FAULTF_MASK 0x80u
#define FTM_FMS_FAULTF_SHIFT 7
/* FILTER Bit Fields */
#define FTM_FILTER_CH0FVAL_MASK 0xFu
#define FTM_FILTER_CH0FVAL_SHIFT 0
#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
#define FTM_FILTER_CH1FVAL_MASK 0xF0u
#define FTM_FILTER_CH1FVAL_SHIFT 4
#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
#define FTM_FILTER_CH2FVAL_MASK 0xF00u
#define FTM_FILTER_CH2FVAL_SHIFT 8
#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
#define FTM_FILTER_CH3FVAL_MASK 0xF000u
#define FTM_FILTER_CH3FVAL_SHIFT 12
#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
/* FLTCTRL Bit Fields */
#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
#define FTM_FLTCTRL_FFVAL_SHIFT 8
#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
/* QDCTRL Bit Fields */
#define FTM_QDCTRL_QUADEN_MASK 0x1u
#define FTM_QDCTRL_QUADEN_SHIFT 0
#define FTM_QDCTRL_TOFDIR_MASK 0x2u
#define FTM_QDCTRL_TOFDIR_SHIFT 1
#define FTM_QDCTRL_QUADIR_MASK 0x4u
#define FTM_QDCTRL_QUADIR_SHIFT 2
#define FTM_QDCTRL_QUADMODE_MASK 0x8u
#define FTM_QDCTRL_QUADMODE_SHIFT 3
#define FTM_QDCTRL_PHBPOL_MASK 0x10u
#define FTM_QDCTRL_PHBPOL_SHIFT 4
#define FTM_QDCTRL_PHAPOL_MASK 0x20u
#define FTM_QDCTRL_PHAPOL_SHIFT 5
#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
/* CONF Bit Fields */
#define FTM_CONF_NUMTOF_MASK 0x1Fu
#define FTM_CONF_NUMTOF_SHIFT 0
#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
#define FTM_CONF_BDMMODE_MASK 0xC0u
#define FTM_CONF_BDMMODE_SHIFT 6
#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
#define FTM_CONF_GTBEEN_MASK 0x200u
#define FTM_CONF_GTBEEN_SHIFT 9
#define FTM_CONF_GTBEOUT_MASK 0x400u
#define FTM_CONF_GTBEOUT_SHIFT 10
/* FLTPOL Bit Fields */
#define FTM_FLTPOL_FLT0POL_MASK 0x1u
#define FTM_FLTPOL_FLT0POL_SHIFT 0
#define FTM_FLTPOL_FLT1POL_MASK 0x2u
#define FTM_FLTPOL_FLT1POL_SHIFT 1
#define FTM_FLTPOL_FLT2POL_MASK 0x4u
#define FTM_FLTPOL_FLT2POL_SHIFT 2
#define FTM_FLTPOL_FLT3POL_MASK 0x8u
#define FTM_FLTPOL_FLT3POL_SHIFT 3
/* SYNCONF Bit Fields */
#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
#define FTM_SYNCONF_CNTINC_MASK 0x4u
#define FTM_SYNCONF_CNTINC_SHIFT 2
#define FTM_SYNCONF_INVC_MASK 0x10u
#define FTM_SYNCONF_INVC_SHIFT 4
#define FTM_SYNCONF_SWOC_MASK 0x20u
#define FTM_SYNCONF_SWOC_SHIFT 5
#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
#define FTM_SYNCONF_SYNCMODE_SHIFT 7
#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
#define FTM_SYNCONF_SWWRBUF_SHIFT 9
#define FTM_SYNCONF_SWOM_MASK 0x400u
#define FTM_SYNCONF_SWOM_SHIFT 10
#define FTM_SYNCONF_SWINVC_MASK 0x800u
#define FTM_SYNCONF_SWINVC_SHIFT 11
#define FTM_SYNCONF_SWSOC_MASK 0x1000u
#define FTM_SYNCONF_SWSOC_SHIFT 12
#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
#define FTM_SYNCONF_HWWRBUF_SHIFT 17
#define FTM_SYNCONF_HWOM_MASK 0x40000u
#define FTM_SYNCONF_HWOM_SHIFT 18
#define FTM_SYNCONF_HWINVC_MASK 0x80000u
#define FTM_SYNCONF_HWINVC_SHIFT 19
#define FTM_SYNCONF_HWSOC_MASK 0x100000u
#define FTM_SYNCONF_HWSOC_SHIFT 20
/* INVCTRL Bit Fields */
#define FTM_INVCTRL_INV0EN_MASK 0x1u
#define FTM_INVCTRL_INV0EN_SHIFT 0
#define FTM_INVCTRL_INV1EN_MASK 0x2u
#define FTM_INVCTRL_INV1EN_SHIFT 1
#define FTM_INVCTRL_INV2EN_MASK 0x4u
#define FTM_INVCTRL_INV2EN_SHIFT 2
#define FTM_INVCTRL_INV3EN_MASK 0x8u
#define FTM_INVCTRL_INV3EN_SHIFT 3
/* SWOCTRL Bit Fields */
#define FTM_SWOCTRL_CH0OC_MASK 0x1u
#define FTM_SWOCTRL_CH0OC_SHIFT 0
#define FTM_SWOCTRL_CH1OC_MASK 0x2u
#define FTM_SWOCTRL_CH1OC_SHIFT 1
#define FTM_SWOCTRL_CH2OC_MASK 0x4u
#define FTM_SWOCTRL_CH2OC_SHIFT 2
#define FTM_SWOCTRL_CH3OC_MASK 0x8u
#define FTM_SWOCTRL_CH3OC_SHIFT 3
#define FTM_SWOCTRL_CH4OC_MASK 0x10u
#define FTM_SWOCTRL_CH4OC_SHIFT 4
#define FTM_SWOCTRL_CH5OC_MASK 0x20u
#define FTM_SWOCTRL_CH5OC_SHIFT 5
#define FTM_SWOCTRL_CH6OC_MASK 0x40u
#define FTM_SWOCTRL_CH6OC_SHIFT 6
#define FTM_SWOCTRL_CH7OC_MASK 0x80u
#define FTM_SWOCTRL_CH7OC_SHIFT 7
#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
#define FTM_SWOCTRL_CH0OCV_SHIFT 8
#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
#define FTM_SWOCTRL_CH1OCV_SHIFT 9
#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
#define FTM_SWOCTRL_CH2OCV_SHIFT 10
#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
#define FTM_SWOCTRL_CH3OCV_SHIFT 11
#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
#define FTM_SWOCTRL_CH4OCV_SHIFT 12
#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
#define FTM_SWOCTRL_CH5OCV_SHIFT 13
#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
#define FTM_SWOCTRL_CH6OCV_SHIFT 14
#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
#define FTM_SWOCTRL_CH7OCV_SHIFT 15
/* PWMLOAD Bit Fields */
#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
#define FTM_PWMLOAD_CH0SEL_SHIFT 0
#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
#define FTM_PWMLOAD_CH1SEL_SHIFT 1
#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
#define FTM_PWMLOAD_CH2SEL_SHIFT 2
#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
#define FTM_PWMLOAD_CH3SEL_SHIFT 3
#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
#define FTM_PWMLOAD_CH4SEL_SHIFT 4
#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
#define FTM_PWMLOAD_CH5SEL_SHIFT 5
#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
#define FTM_PWMLOAD_CH6SEL_SHIFT 6
#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
#define FTM_PWMLOAD_CH7SEL_SHIFT 7
#define FTM_PWMLOAD_LDOK_MASK 0x200u
#define FTM_PWMLOAD_LDOK_SHIFT 9
/*!
* @}
*/ /* end of group FTM_Register_Masks */
/* FTM - Peripheral instance base addresses */
/** Peripheral FTM0 base address */
#define FTM0_BASE (0x40038000u)
/** Peripheral FTM0 base pointer */
#define FTM0 ((FTM_Type *)FTM0_BASE)
/** Peripheral FTM1 base address */
#define FTM1_BASE (0x40039000u)
/** Peripheral FTM1 base pointer */
#define FTM1 ((FTM_Type *)FTM1_BASE)
/** Peripheral FTM2 base address */
#define FTM2_BASE (0x4003A000u)
/** Peripheral FTM2 base pointer */
#define FTM2 ((FTM_Type *)FTM2_BASE)
/** Array initializer of FTM peripheral base pointers */
#define FTM_BASES { FTM0, FTM1, FTM2 }
/*!
* @}
*/ /* end of group FTM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} GPIO_Type;
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/* PDOR Bit Fields */
#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
#define GPIO_PDOR_PDO_SHIFT 0
#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
/* PSOR Bit Fields */
#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
#define GPIO_PSOR_PTSO_SHIFT 0
#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
/* PCOR Bit Fields */
#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
#define GPIO_PCOR_PTCO_SHIFT 0
#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
/* PTOR Bit Fields */
#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
#define GPIO_PTOR_PTTO_SHIFT 0
#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
/* PDIR Bit Fields */
#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
#define GPIO_PDIR_PDI_SHIFT 0
#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
/* PDDR Bit Fields */
#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
#define GPIO_PDDR_PDD_SHIFT 0
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIOA base address */
#define GPIOA_BASE (0x400FF000u)
/** Peripheral GPIOA base pointer */
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
/** Peripheral GPIOB base address */
#define GPIOB_BASE (0x400FF040u)
/** Peripheral GPIOB base pointer */
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
/** Peripheral GPIOC base address */
#define GPIOC_BASE (0x400FF080u)
/** Peripheral GPIOC base pointer */
#define GPIOC ((GPIO_Type *)GPIOC_BASE)
/** Peripheral GPIOD base address */
#define GPIOD_BASE (0x400FF0C0u)
/** Peripheral GPIOD base pointer */
#define GPIOD ((GPIO_Type *)GPIOD_BASE)
/** Peripheral GPIOE base address */
#define GPIOE_BASE (0x400FF100u)
/** Peripheral GPIOE base pointer */
#define GPIOE ((GPIO_Type *)GPIOE_BASE)
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASES { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
* @{
*/
/** I2C - Register Layout Typedef */
typedef struct {
__IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
__IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
__IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
__IO uint8_t S; /**< I2C Status register, offset: 0x3 */
__IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
__IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
__IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
__IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
__IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
__IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
__IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
__IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
} I2C_Type;
/* ----------------------------------------------------------------------------
-- I2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2C_Register_Masks I2C Register Masks
* @{
*/
/* A1 Bit Fields */
#define I2C_A1_AD_MASK 0xFEu
#define I2C_A1_AD_SHIFT 1
#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
/* F Bit Fields */
#define I2C_F_ICR_MASK 0x3Fu
#define I2C_F_ICR_SHIFT 0
#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
#define I2C_F_MULT_MASK 0xC0u
#define I2C_F_MULT_SHIFT 6
#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
/* C1 Bit Fields */
#define I2C_C1_DMAEN_MASK 0x1u
#define I2C_C1_DMAEN_SHIFT 0
#define I2C_C1_WUEN_MASK 0x2u
#define I2C_C1_WUEN_SHIFT 1
#define I2C_C1_RSTA_MASK 0x4u
#define I2C_C1_RSTA_SHIFT 2
#define I2C_C1_TXAK_MASK 0x8u
#define I2C_C1_TXAK_SHIFT 3
#define I2C_C1_TX_MASK 0x10u
#define I2C_C1_TX_SHIFT 4
#define I2C_C1_MST_MASK 0x20u
#define I2C_C1_MST_SHIFT 5
#define I2C_C1_IICIE_MASK 0x40u
#define I2C_C1_IICIE_SHIFT 6
#define I2C_C1_IICEN_MASK 0x80u
#define I2C_C1_IICEN_SHIFT 7
/* S Bit Fields */
#define I2C_S_RXAK_MASK 0x1u
#define I2C_S_RXAK_SHIFT 0
#define I2C_S_IICIF_MASK 0x2u
#define I2C_S_IICIF_SHIFT 1
#define I2C_S_SRW_MASK 0x4u
#define I2C_S_SRW_SHIFT 2
#define I2C_S_RAM_MASK 0x8u
#define I2C_S_RAM_SHIFT 3
#define I2C_S_ARBL_MASK 0x10u
#define I2C_S_ARBL_SHIFT 4
#define I2C_S_BUSY_MASK 0x20u
#define I2C_S_BUSY_SHIFT 5
#define I2C_S_IAAS_MASK 0x40u
#define I2C_S_IAAS_SHIFT 6
#define I2C_S_TCF_MASK 0x80u
#define I2C_S_TCF_SHIFT 7
/* D Bit Fields */
#define I2C_D_DATA_MASK 0xFFu
#define I2C_D_DATA_SHIFT 0
#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
/* C2 Bit Fields */
#define I2C_C2_AD_MASK 0x7u
#define I2C_C2_AD_SHIFT 0
#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
#define I2C_C2_RMEN_MASK 0x8u
#define I2C_C2_RMEN_SHIFT 3
#define I2C_C2_SBRC_MASK 0x10u
#define I2C_C2_SBRC_SHIFT 4
#define I2C_C2_HDRS_MASK 0x20u
#define I2C_C2_HDRS_SHIFT 5
#define I2C_C2_ADEXT_MASK 0x40u
#define I2C_C2_ADEXT_SHIFT 6
#define I2C_C2_GCAEN_MASK 0x80u
#define I2C_C2_GCAEN_SHIFT 7
/* FLT Bit Fields */
#define I2C_FLT_FLT_MASK 0x1Fu
#define I2C_FLT_FLT_SHIFT 0
#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
#define I2C_FLT_STOPIE_MASK 0x20u
#define I2C_FLT_STOPIE_SHIFT 5
#define I2C_FLT_STOPF_MASK 0x40u
#define I2C_FLT_STOPF_SHIFT 6
#define I2C_FLT_SHEN_MASK 0x80u
#define I2C_FLT_SHEN_SHIFT 7
/* RA Bit Fields */
#define I2C_RA_RAD_MASK 0xFEu
#define I2C_RA_RAD_SHIFT 1
#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
/* SMB Bit Fields */
#define I2C_SMB_SHTF2IE_MASK 0x1u
#define I2C_SMB_SHTF2IE_SHIFT 0
#define I2C_SMB_SHTF2_MASK 0x2u
#define I2C_SMB_SHTF2_SHIFT 1
#define I2C_SMB_SHTF1_MASK 0x4u
#define I2C_SMB_SHTF1_SHIFT 2
#define I2C_SMB_SLTF_MASK 0x8u
#define I2C_SMB_SLTF_SHIFT 3
#define I2C_SMB_TCKSEL_MASK 0x10u
#define I2C_SMB_TCKSEL_SHIFT 4
#define I2C_SMB_SIICAEN_MASK 0x20u
#define I2C_SMB_SIICAEN_SHIFT 5
#define I2C_SMB_ALERTEN_MASK 0x40u
#define I2C_SMB_ALERTEN_SHIFT 6
#define I2C_SMB_FACK_MASK 0x80u
#define I2C_SMB_FACK_SHIFT 7
/* A2 Bit Fields */
#define I2C_A2_SAD_MASK 0xFEu
#define I2C_A2_SAD_SHIFT 1
#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
/* SLTH Bit Fields */
#define I2C_SLTH_SSLT_MASK 0xFFu
#define I2C_SLTH_SSLT_SHIFT 0
#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
/* SLTL Bit Fields */
#define I2C_SLTL_SSLT_MASK 0xFFu
#define I2C_SLTL_SSLT_SHIFT 0
#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
/*!
* @}
*/ /* end of group I2C_Register_Masks */
/* I2C - Peripheral instance base addresses */
/** Peripheral I2C0 base address */
#define I2C0_BASE (0x40066000u)
/** Peripheral I2C0 base pointer */
#define I2C0 ((I2C_Type *)I2C0_BASE)
/** Array initializer of I2C peripheral base pointers */
#define I2C_BASES { I2C0 }
/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LLWU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
* @{
*/
/** LLWU - Register Layout Typedef */
typedef struct {
__IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
__IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
__IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
__IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
__IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
__IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
__IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
__I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
__IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
__IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
} LLWU_Type;
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Masks LLWU Register Masks
* @{
*/
/* PE1 Bit Fields */
#define LLWU_PE1_WUPE0_MASK 0x3u
#define LLWU_PE1_WUPE0_SHIFT 0
#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
#define LLWU_PE1_WUPE1_MASK 0xCu
#define LLWU_PE1_WUPE1_SHIFT 2
#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
#define LLWU_PE1_WUPE2_MASK 0x30u
#define LLWU_PE1_WUPE2_SHIFT 4
#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
#define LLWU_PE1_WUPE3_MASK 0xC0u
#define LLWU_PE1_WUPE3_SHIFT 6
#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
/* PE2 Bit Fields */
#define LLWU_PE2_WUPE4_MASK 0x3u
#define LLWU_PE2_WUPE4_SHIFT 0
#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
#define LLWU_PE2_WUPE5_MASK 0xCu
#define LLWU_PE2_WUPE5_SHIFT 2
#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
#define LLWU_PE2_WUPE6_MASK 0x30u
#define LLWU_PE2_WUPE6_SHIFT 4
#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
#define LLWU_PE2_WUPE7_MASK 0xC0u
#define LLWU_PE2_WUPE7_SHIFT 6
#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
/* PE3 Bit Fields */
#define LLWU_PE3_WUPE8_MASK 0x3u
#define LLWU_PE3_WUPE8_SHIFT 0
#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
#define LLWU_PE3_WUPE9_MASK 0xCu
#define LLWU_PE3_WUPE9_SHIFT 2
#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
#define LLWU_PE3_WUPE10_MASK 0x30u
#define LLWU_PE3_WUPE10_SHIFT 4
#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
#define LLWU_PE3_WUPE11_MASK 0xC0u
#define LLWU_PE3_WUPE11_SHIFT 6
#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
/* PE4 Bit Fields */
#define LLWU_PE4_WUPE12_MASK 0x3u
#define LLWU_PE4_WUPE12_SHIFT 0
#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
#define LLWU_PE4_WUPE13_MASK 0xCu
#define LLWU_PE4_WUPE13_SHIFT 2
#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
#define LLWU_PE4_WUPE14_MASK 0x30u
#define LLWU_PE4_WUPE14_SHIFT 4
#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
#define LLWU_PE4_WUPE15_MASK 0xC0u
#define LLWU_PE4_WUPE15_SHIFT 6
#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
/* ME Bit Fields */
#define LLWU_ME_WUME0_MASK 0x1u
#define LLWU_ME_WUME0_SHIFT 0
#define LLWU_ME_WUME1_MASK 0x2u
#define LLWU_ME_WUME1_SHIFT 1
#define LLWU_ME_WUME2_MASK 0x4u
#define LLWU_ME_WUME2_SHIFT 2
#define LLWU_ME_WUME3_MASK 0x8u
#define LLWU_ME_WUME3_SHIFT 3
#define LLWU_ME_WUME4_MASK 0x10u
#define LLWU_ME_WUME4_SHIFT 4
#define LLWU_ME_WUME5_MASK 0x20u
#define LLWU_ME_WUME5_SHIFT 5
#define LLWU_ME_WUME6_MASK 0x40u
#define LLWU_ME_WUME6_SHIFT 6
#define LLWU_ME_WUME7_MASK 0x80u
#define LLWU_ME_WUME7_SHIFT 7
/* F1 Bit Fields */
#define LLWU_F1_WUF0_MASK 0x1u
#define LLWU_F1_WUF0_SHIFT 0
#define LLWU_F1_WUF1_MASK 0x2u
#define LLWU_F1_WUF1_SHIFT 1
#define LLWU_F1_WUF2_MASK 0x4u
#define LLWU_F1_WUF2_SHIFT 2
#define LLWU_F1_WUF3_MASK 0x8u
#define LLWU_F1_WUF3_SHIFT 3
#define LLWU_F1_WUF4_MASK 0x10u
#define LLWU_F1_WUF4_SHIFT 4
#define LLWU_F1_WUF5_MASK 0x20u
#define LLWU_F1_WUF5_SHIFT 5
#define LLWU_F1_WUF6_MASK 0x40u
#define LLWU_F1_WUF6_SHIFT 6
#define LLWU_F1_WUF7_MASK 0x80u
#define LLWU_F1_WUF7_SHIFT 7
/* F2 Bit Fields */
#define LLWU_F2_WUF8_MASK 0x1u
#define LLWU_F2_WUF8_SHIFT 0
#define LLWU_F2_WUF9_MASK 0x2u
#define LLWU_F2_WUF9_SHIFT 1
#define LLWU_F2_WUF10_MASK 0x4u
#define LLWU_F2_WUF10_SHIFT 2
#define LLWU_F2_WUF11_MASK 0x8u
#define LLWU_F2_WUF11_SHIFT 3
#define LLWU_F2_WUF12_MASK 0x10u
#define LLWU_F2_WUF12_SHIFT 4
#define LLWU_F2_WUF13_MASK 0x20u
#define LLWU_F2_WUF13_SHIFT 5
#define LLWU_F2_WUF14_MASK 0x40u
#define LLWU_F2_WUF14_SHIFT 6
#define LLWU_F2_WUF15_MASK 0x80u
#define LLWU_F2_WUF15_SHIFT 7
/* F3 Bit Fields */
#define LLWU_F3_MWUF0_MASK 0x1u
#define LLWU_F3_MWUF0_SHIFT 0
#define LLWU_F3_MWUF1_MASK 0x2u
#define LLWU_F3_MWUF1_SHIFT 1
#define LLWU_F3_MWUF2_MASK 0x4u
#define LLWU_F3_MWUF2_SHIFT 2
#define LLWU_F3_MWUF3_MASK 0x8u
#define LLWU_F3_MWUF3_SHIFT 3
#define LLWU_F3_MWUF4_MASK 0x10u
#define LLWU_F3_MWUF4_SHIFT 4
#define LLWU_F3_MWUF5_MASK 0x20u
#define LLWU_F3_MWUF5_SHIFT 5
#define LLWU_F3_MWUF6_MASK 0x40u
#define LLWU_F3_MWUF6_SHIFT 6
#define LLWU_F3_MWUF7_MASK 0x80u
#define LLWU_F3_MWUF7_SHIFT 7
/* FILT1 Bit Fields */
#define LLWU_FILT1_FILTSEL_MASK 0xFu
#define LLWU_FILT1_FILTSEL_SHIFT 0
#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
#define LLWU_FILT1_FILTE_MASK 0x60u
#define LLWU_FILT1_FILTE_SHIFT 5
#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
#define LLWU_FILT1_FILTF_MASK 0x80u
#define LLWU_FILT1_FILTF_SHIFT 7
/* FILT2 Bit Fields */
#define LLWU_FILT2_FILTSEL_MASK 0xFu
#define LLWU_FILT2_FILTSEL_SHIFT 0
#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
#define LLWU_FILT2_FILTE_MASK 0x60u
#define LLWU_FILT2_FILTE_SHIFT 5
#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
#define LLWU_FILT2_FILTF_MASK 0x80u
#define LLWU_FILT2_FILTF_SHIFT 7
/*!
* @}
*/ /* end of group LLWU_Register_Masks */
/* LLWU - Peripheral instance base addresses */
/** Peripheral LLWU base address */
#define LLWU_BASE (0x4007C000u)
/** Peripheral LLWU base pointer */
#define LLWU ((LLWU_Type *)LLWU_BASE)
/** Array initializer of LLWU peripheral base pointers */
#define LLWU_BASES { LLWU }
/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPTMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
* @{
*/
/** LPTMR - Register Layout Typedef */
typedef struct {
__IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
__I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
} LPTMR_Type;
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
* @{
*/
/* CSR Bit Fields */
#define LPTMR_CSR_TEN_MASK 0x1u
#define LPTMR_CSR_TEN_SHIFT 0
#define LPTMR_CSR_TMS_MASK 0x2u
#define LPTMR_CSR_TMS_SHIFT 1
#define LPTMR_CSR_TFC_MASK 0x4u
#define LPTMR_CSR_TFC_SHIFT 2
#define LPTMR_CSR_TPP_MASK 0x8u
#define LPTMR_CSR_TPP_SHIFT 3
#define LPTMR_CSR_TPS_MASK 0x30u
#define LPTMR_CSR_TPS_SHIFT 4
#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
#define LPTMR_CSR_TIE_MASK 0x40u
#define LPTMR_CSR_TIE_SHIFT 6
#define LPTMR_CSR_TCF_MASK 0x80u
#define LPTMR_CSR_TCF_SHIFT 7
/* PSR Bit Fields */
#define LPTMR_PSR_PCS_MASK 0x3u
#define LPTMR_PSR_PCS_SHIFT 0
#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
#define LPTMR_PSR_PBYP_MASK 0x4u
#define LPTMR_PSR_PBYP_SHIFT 2
#define LPTMR_PSR_PRESCALE_MASK 0x78u
#define LPTMR_PSR_PRESCALE_SHIFT 3
#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
/* CMR Bit Fields */
#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
#define LPTMR_CMR_COMPARE_SHIFT 0
#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
/* CNR Bit Fields */
#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
#define LPTMR_CNR_COUNTER_SHIFT 0
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
/*!
* @}
*/ /* end of group LPTMR_Register_Masks */
/* LPTMR - Peripheral instance base addresses */
/** Peripheral LPTMR0 base address */
#define LPTMR0_BASE (0x40040000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
/** Array initializer of LPTMR peripheral base pointers */
#define LPTMR_BASES { LPTMR0 }
/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
* @{
*/
/** MCG - Register Layout Typedef */
typedef struct {
__IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
__IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
__IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
__IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
uint8_t RESERVED_0[1];
__IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
__I uint8_t S; /**< MCG Status Register, offset: 0x6 */
uint8_t RESERVED_1[1];
__IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
uint8_t RESERVED_2[1];
__IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
__IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
} MCG_Type;
/* ----------------------------------------------------------------------------
-- MCG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCG_Register_Masks MCG Register Masks
* @{
*/
/* C1 Bit Fields */
#define MCG_C1_IREFSTEN_MASK 0x1u
#define MCG_C1_IREFSTEN_SHIFT 0
#define MCG_C1_IRCLKEN_MASK 0x2u
#define MCG_C1_IRCLKEN_SHIFT 1
#define MCG_C1_IREFS_MASK 0x4u
#define MCG_C1_IREFS_SHIFT 2
#define MCG_C1_FRDIV_MASK 0x38u
#define MCG_C1_FRDIV_SHIFT 3
#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
#define MCG_C1_CLKS_MASK 0xC0u
#define MCG_C1_CLKS_SHIFT 6
#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
/* C2 Bit Fields */
#define MCG_C2_IRCS_MASK 0x1u
#define MCG_C2_IRCS_SHIFT 0
#define MCG_C2_LP_MASK 0x2u
#define MCG_C2_LP_SHIFT 1
#define MCG_C2_EREFS0_MASK 0x4u
#define MCG_C2_EREFS0_SHIFT 2
#define MCG_C2_HGO0_MASK 0x8u
#define MCG_C2_HGO0_SHIFT 3
#define MCG_C2_RANGE0_MASK 0x30u
#define MCG_C2_RANGE0_SHIFT 4
#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
#define MCG_C2_FCFTRIM_MASK 0x40u
#define MCG_C2_FCFTRIM_SHIFT 6
#define MCG_C2_LOCRE0_MASK 0x80u
#define MCG_C2_LOCRE0_SHIFT 7
/* C3 Bit Fields */
#define MCG_C3_SCTRIM_MASK 0xFFu
#define MCG_C3_SCTRIM_SHIFT 0
#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
/* C4 Bit Fields */
#define MCG_C4_SCFTRIM_MASK 0x1u
#define MCG_C4_SCFTRIM_SHIFT 0
#define MCG_C4_FCTRIM_MASK 0x1Eu
#define MCG_C4_FCTRIM_SHIFT 1
#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
#define MCG_C4_DRST_DRS_MASK 0x60u
#define MCG_C4_DRST_DRS_SHIFT 5
#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
#define MCG_C4_DMX32_MASK 0x80u
#define MCG_C4_DMX32_SHIFT 7
/* C6 Bit Fields */
#define MCG_C6_CME_MASK 0x20u
#define MCG_C6_CME_SHIFT 5
/* S Bit Fields */
#define MCG_S_IRCST_MASK 0x1u
#define MCG_S_IRCST_SHIFT 0
#define MCG_S_OSCINIT0_MASK 0x2u
#define MCG_S_OSCINIT0_SHIFT 1
#define MCG_S_CLKST_MASK 0xCu
#define MCG_S_CLKST_SHIFT 2
#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
#define MCG_S_IREFST_MASK 0x10u
#define MCG_S_IREFST_SHIFT 4
/* SC Bit Fields */
#define MCG_SC_LOCS0_MASK 0x1u
#define MCG_SC_LOCS0_SHIFT 0
#define MCG_SC_FCRDIV_MASK 0xEu
#define MCG_SC_FCRDIV_SHIFT 1
#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
#define MCG_SC_FLTPRSRV_MASK 0x10u
#define MCG_SC_FLTPRSRV_SHIFT 4
#define MCG_SC_ATMF_MASK 0x20u
#define MCG_SC_ATMF_SHIFT 5
#define MCG_SC_ATMS_MASK 0x40u
#define MCG_SC_ATMS_SHIFT 6
#define MCG_SC_ATME_MASK 0x80u
#define MCG_SC_ATME_SHIFT 7
/* ATCVH Bit Fields */
#define MCG_ATCVH_ATCVH_MASK 0xFFu
#define MCG_ATCVH_ATCVH_SHIFT 0
#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
/* ATCVL Bit Fields */
#define MCG_ATCVL_ATCVL_MASK 0xFFu
#define MCG_ATCVL_ATCVL_SHIFT 0
#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
/*!
* @}
*/ /* end of group MCG_Register_Masks */
/* MCG - Peripheral instance base addresses */
/** Peripheral MCG base address */
#define MCG_BASE (0x40064000u)
/** Peripheral MCG base pointer */
#define MCG ((MCG_Type *)MCG_BASE)
/** Array initializer of MCG peripheral base pointers */
#define MCG_BASES { MCG }
/*!
* @}
*/ /* end of group MCG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
* @{
*/
/** MCM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
__I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
__IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
uint8_t RESERVED_1[48];
__IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
} MCM_Type;
/* ----------------------------------------------------------------------------
-- MCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Masks MCM Register Masks
* @{
*/
/* PLASC Bit Fields */
#define MCM_PLASC_ASC_MASK 0xFFu
#define MCM_PLASC_ASC_SHIFT 0
#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
/* PLAMC Bit Fields */
#define MCM_PLAMC_AMC_MASK 0xFFu
#define MCM_PLAMC_AMC_SHIFT 0
#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
/* PLACR Bit Fields */
#define MCM_PLACR_ARB_MASK 0x200u
#define MCM_PLACR_ARB_SHIFT 9
#define MCM_PLACR_CFCC_MASK 0x400u
#define MCM_PLACR_CFCC_SHIFT 10
#define MCM_PLACR_DFCDA_MASK 0x800u
#define MCM_PLACR_DFCDA_SHIFT 11
#define MCM_PLACR_DFCIC_MASK 0x1000u
#define MCM_PLACR_DFCIC_SHIFT 12
#define MCM_PLACR_DFCC_MASK 0x2000u
#define MCM_PLACR_DFCC_SHIFT 13
#define MCM_PLACR_EFDS_MASK 0x4000u
#define MCM_PLACR_EFDS_SHIFT 14
#define MCM_PLACR_DFCS_MASK 0x8000u
#define MCM_PLACR_DFCS_SHIFT 15
#define MCM_PLACR_ESFC_MASK 0x10000u
#define MCM_PLACR_ESFC_SHIFT 16
/* CPO Bit Fields */
#define MCM_CPO_CPOREQ_MASK 0x1u
#define MCM_CPO_CPOREQ_SHIFT 0
#define MCM_CPO_CPOACK_MASK 0x2u
#define MCM_CPO_CPOACK_SHIFT 1
#define MCM_CPO_CPOWOI_MASK 0x4u
#define MCM_CPO_CPOWOI_SHIFT 2
/*!
* @}
*/ /* end of group MCM_Register_Masks */
/* MCM - Peripheral instance base addresses */
/** Peripheral MCM base address */
#define MCM_BASE (0xF0003000u)
/** Peripheral MCM base pointer */
#define MCM ((MCM_Type *)MCM_BASE)
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASES { MCM }
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MMDVSQ Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer
* @{
*/
/** MMDVSQ - Register Layout Typedef */
typedef struct {
__IO uint32_t DEND; /**< Dividend Register, offset: 0x0 */
__IO uint32_t DSOR; /**< Divisor Register, offset: 0x4 */
__IO uint32_t CSR; /**< Control/Status Register, offset: 0x8 */
__IO uint32_t RES; /**< Result Register, offset: 0xC */
__IO uint32_t RCND; /**< Radicand Register, offset: 0x10 */
} MMDVSQ_Type;
/* ----------------------------------------------------------------------------
-- MMDVSQ Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks
* @{
*/
/* DEND Bit Fields */
#define MMDVSQ_DEND_DIVIDEND_MASK 0xFFFFFFFFu
#define MMDVSQ_DEND_DIVIDEND_SHIFT 0
#define MMDVSQ_DEND_DIVIDEND(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_DEND_DIVIDEND_SHIFT))&MMDVSQ_DEND_DIVIDEND_MASK)
/* DSOR Bit Fields */
#define MMDVSQ_DSOR_DIVISOR_MASK 0xFFFFFFFFu
#define MMDVSQ_DSOR_DIVISOR_SHIFT 0
#define MMDVSQ_DSOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_DSOR_DIVISOR_SHIFT))&MMDVSQ_DSOR_DIVISOR_MASK)
/* CSR Bit Fields */
#define MMDVSQ_CSR_SRT_MASK 0x1u
#define MMDVSQ_CSR_SRT_SHIFT 0
#define MMDVSQ_CSR_USGN_MASK 0x2u
#define MMDVSQ_CSR_USGN_SHIFT 1
#define MMDVSQ_CSR_REM_MASK 0x4u
#define MMDVSQ_CSR_REM_SHIFT 2
#define MMDVSQ_CSR_DZE_MASK 0x8u
#define MMDVSQ_CSR_DZE_SHIFT 3
#define MMDVSQ_CSR_DZ_MASK 0x10u
#define MMDVSQ_CSR_DZ_SHIFT 4
#define MMDVSQ_CSR_DFS_MASK 0x20u
#define MMDVSQ_CSR_DFS_SHIFT 5
#define MMDVSQ_CSR_SQRT_MASK 0x20000000u
#define MMDVSQ_CSR_SQRT_SHIFT 29
#define MMDVSQ_CSR_DIV_MASK 0x40000000u
#define MMDVSQ_CSR_DIV_SHIFT 30
#define MMDVSQ_CSR_BUSY_MASK 0x80000000u
#define MMDVSQ_CSR_BUSY_SHIFT 31
/* RES Bit Fields */
#define MMDVSQ_RES_RESULT_MASK 0xFFFFFFFFu
#define MMDVSQ_RES_RESULT_SHIFT 0
#define MMDVSQ_RES_RESULT(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_RES_RESULT_SHIFT))&MMDVSQ_RES_RESULT_MASK)
/* RCND Bit Fields */
#define MMDVSQ_RCND_RADICAND_MASK 0xFFFFFFFFu
#define MMDVSQ_RCND_RADICAND_SHIFT 0
#define MMDVSQ_RCND_RADICAND(x) (((uint32_t)(((uint32_t)(x))<<MMDVSQ_RCND_RADICAND_SHIFT))&MMDVSQ_RCND_RADICAND_MASK)
/*!
* @}
*/ /* end of group MMDVSQ_Register_Masks */
/* MMDVSQ - Peripheral instance base addresses */
/** Peripheral MMDVSQ base address */
#define MMDVSQ_BASE (0xF0004000u)
/** Peripheral MMDVSQ base pointer */
#define MMDVSQ ((MMDVSQ_Type *)MMDVSQ_BASE)
/** Array initializer of MMDVSQ peripheral base pointers */
#define MMDVSQ_BASES { MMDVSQ }
/*!
* @}
*/ /* end of group MMDVSQ_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MTB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
* @{
*/
/** MTB - Register Layout Typedef */
typedef struct {
__IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
__IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
__IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
__I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
uint8_t RESERVED_0[3824];
__I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
uint8_t RESERVED_1[156];
__I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
__I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
uint8_t RESERVED_2[8];
__I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
__I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
__I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
__I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
uint8_t RESERVED_3[8];
__I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
__I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
__I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
} MTB_Type;
/* ----------------------------------------------------------------------------
-- MTB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Register_Masks MTB Register Masks
* @{
*/
/* POSITION Bit Fields */
#define MTB_POSITION_WRAP_MASK 0x4u
#define MTB_POSITION_WRAP_SHIFT 2
#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
#define MTB_POSITION_POINTER_SHIFT 3
#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
/* MASTER Bit Fields */
#define MTB_MASTER_MASK_MASK 0x1Fu
#define MTB_MASTER_MASK_SHIFT 0
#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
#define MTB_MASTER_TSTARTEN_MASK 0x20u
#define MTB_MASTER_TSTARTEN_SHIFT 5
#define MTB_MASTER_TSTOPEN_MASK 0x40u
#define MTB_MASTER_TSTOPEN_SHIFT 6
#define MTB_MASTER_SFRWPRIV_MASK 0x80u
#define MTB_MASTER_SFRWPRIV_SHIFT 7
#define MTB_MASTER_RAMPRIV_MASK 0x100u
#define MTB_MASTER_RAMPRIV_SHIFT 8
#define MTB_MASTER_HALTREQ_MASK 0x200u
#define MTB_MASTER_HALTREQ_SHIFT 9
#define MTB_MASTER_EN_MASK 0x80000000u
#define MTB_MASTER_EN_SHIFT 31
/* FLOW Bit Fields */
#define MTB_FLOW_AUTOSTOP_MASK 0x1u
#define MTB_FLOW_AUTOSTOP_SHIFT 0
#define MTB_FLOW_AUTOHALT_MASK 0x2u
#define MTB_FLOW_AUTOHALT_SHIFT 1
#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
#define MTB_FLOW_WATERMARK_SHIFT 3
#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
/* BASE Bit Fields */
#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
#define MTB_BASE_BASEADDR_SHIFT 0
#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
/* MODECTRL Bit Fields */
#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
#define MTB_MODECTRL_MODECTRL_SHIFT 0
#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
/* TAGSET Bit Fields */
#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
#define MTB_TAGSET_TAGSET_SHIFT 0
#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
/* TAGCLEAR Bit Fields */
#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
/* LOCKACCESS Bit Fields */
#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
/* LOCKSTAT Bit Fields */
#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
/* AUTHSTAT Bit Fields */
#define MTB_AUTHSTAT_BIT0_MASK 0x1u
#define MTB_AUTHSTAT_BIT0_SHIFT 0
#define MTB_AUTHSTAT_BIT2_MASK 0x4u
#define MTB_AUTHSTAT_BIT2_SHIFT 2
/* DEVICEARCH Bit Fields */
#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
/* DEVICECFG Bit Fields */
#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
/* DEVICETYPID Bit Fields */
#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
/* PERIPHID Bit Fields */
#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
#define MTB_PERIPHID_PERIPHID_SHIFT 0
#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
/* COMPID Bit Fields */
#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
#define MTB_COMPID_COMPID_SHIFT 0
#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
/*!
* @}
*/ /* end of group MTB_Register_Masks */
/* MTB - Peripheral instance base addresses */
/** Peripheral MTB base address */
#define MTB_BASE (0xF0000000u)
/** Peripheral MTB base pointer */
#define MTB ((MTB_Type *)MTB_BASE)
/** Array initializer of MTB peripheral base pointers */
#define MTB_BASES { MTB }
/*!
* @}
*/ /* end of group MTB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MTBDWT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
* @{
*/
/** MTBDWT - Register Layout Typedef */
typedef struct {
__I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
uint8_t RESERVED_0[28];
struct { /* offset: 0x20, array step: 0x10 */
__IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
__IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
__IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
uint8_t RESERVED_0[4];
} COMPARATOR[2];
uint8_t RESERVED_1[448];
__IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
uint8_t RESERVED_2[3524];
__I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
__I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
__I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
} MTBDWT_Type;
/* ----------------------------------------------------------------------------
-- MTBDWT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
* @{
*/
/* CTRL Bit Fields */
#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
#define MTBDWT_CTRL_NUMCMP_SHIFT 28
#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
/* COMP Bit Fields */
#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
#define MTBDWT_COMP_COMP_SHIFT 0
#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
/* MASK Bit Fields */
#define MTBDWT_MASK_MASK_MASK 0x1Fu
#define MTBDWT_MASK_MASK_SHIFT 0
#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
/* FCT Bit Fields */
#define MTBDWT_FCT_FUNCTION_MASK 0xFu
#define MTBDWT_FCT_FUNCTION_SHIFT 0
#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
#define MTBDWT_FCT_MATCHED_SHIFT 24
/* TBCTRL Bit Fields */
#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
/* DEVICECFG Bit Fields */
#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
/* DEVICETYPID Bit Fields */
#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
/* PERIPHID Bit Fields */
#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
/* COMPID Bit Fields */
#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
#define MTBDWT_COMPID_COMPID_SHIFT 0
#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
/*!
* @}
*/ /* end of group MTBDWT_Register_Masks */
/* MTBDWT - Peripheral instance base addresses */
/** Peripheral MTBDWT base address */
#define MTBDWT_BASE (0xF0001000u)
/** Peripheral MTBDWT base pointer */
#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
/** Array initializer of MTBDWT peripheral base pointers */
#define MTBDWT_BASES { MTBDWT }
/*!
* @}
*/ /* end of group MTBDWT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- NV Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
* @{
*/
/** NV - Register Layout Typedef */
typedef struct {
__I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
__I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
__I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
__I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
__I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
__I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
__I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
__I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
__I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
__I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
__I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
__I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
__I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
} NV_Type;
/* ----------------------------------------------------------------------------
-- NV Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Masks NV Register Masks
* @{
*/
/* BACKKEY3 Bit Fields */
#define NV_BACKKEY3_KEY_MASK 0xFFu
#define NV_BACKKEY3_KEY_SHIFT 0
#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
/* BACKKEY2 Bit Fields */
#define NV_BACKKEY2_KEY_MASK 0xFFu
#define NV_BACKKEY2_KEY_SHIFT 0
#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
/* BACKKEY1 Bit Fields */
#define NV_BACKKEY1_KEY_MASK 0xFFu
#define NV_BACKKEY1_KEY_SHIFT 0
#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
/* BACKKEY0 Bit Fields */
#define NV_BACKKEY0_KEY_MASK 0xFFu
#define NV_BACKKEY0_KEY_SHIFT 0
#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
/* BACKKEY7 Bit Fields */
#define NV_BACKKEY7_KEY_MASK 0xFFu
#define NV_BACKKEY7_KEY_SHIFT 0
#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
/* BACKKEY6 Bit Fields */
#define NV_BACKKEY6_KEY_MASK 0xFFu
#define NV_BACKKEY6_KEY_SHIFT 0
#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
/* BACKKEY5 Bit Fields */
#define NV_BACKKEY5_KEY_MASK 0xFFu
#define NV_BACKKEY5_KEY_SHIFT 0
#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
/* BACKKEY4 Bit Fields */
#define NV_BACKKEY4_KEY_MASK 0xFFu
#define NV_BACKKEY4_KEY_SHIFT 0
#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
/* FPROT3 Bit Fields */
#define NV_FPROT3_PROT_MASK 0xFFu
#define NV_FPROT3_PROT_SHIFT 0
#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
/* FPROT2 Bit Fields */
#define NV_FPROT2_PROT_MASK 0xFFu
#define NV_FPROT2_PROT_SHIFT 0
#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
/* FPROT1 Bit Fields */
#define NV_FPROT1_PROT_MASK 0xFFu
#define NV_FPROT1_PROT_SHIFT 0
#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
/* FPROT0 Bit Fields */
#define NV_FPROT0_PROT_MASK 0xFFu
#define NV_FPROT0_PROT_SHIFT 0
#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
/* FSEC Bit Fields */
#define NV_FSEC_SEC_MASK 0x3u
#define NV_FSEC_SEC_SHIFT 0
#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
#define NV_FSEC_FSLACC_MASK 0xCu
#define NV_FSEC_FSLACC_SHIFT 2
#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
#define NV_FSEC_MEEN_MASK 0x30u
#define NV_FSEC_MEEN_SHIFT 4
#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
#define NV_FSEC_KEYEN_MASK 0xC0u
#define NV_FSEC_KEYEN_SHIFT 6
#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
/* FOPT Bit Fields */
#define NV_FOPT_LPBOOT0_MASK 0x1u
#define NV_FOPT_LPBOOT0_SHIFT 0
#define NV_FOPT_NMI_DIS_MASK 0x4u
#define NV_FOPT_NMI_DIS_SHIFT 2
#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
#define NV_FOPT_LPBOOT1_MASK 0x10u
#define NV_FOPT_LPBOOT1_SHIFT 4
#define NV_FOPT_FAST_INIT_MASK 0x20u
#define NV_FOPT_FAST_INIT_SHIFT 5
/*!
* @}
*/ /* end of group NV_Register_Masks */
/* NV - Peripheral instance base addresses */
/** Peripheral FTFA_FlashConfig base address */
#define FTFA_FlashConfig_BASE (0x400u)
/** Peripheral FTFA_FlashConfig base pointer */
#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
/** Array initializer of NV peripheral base pointers */
#define NV_BASES { FTFA_FlashConfig }
/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- OSC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
* @{
*/
/** OSC - Register Layout Typedef */
typedef struct {
__IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
} OSC_Type;
/* ----------------------------------------------------------------------------
-- OSC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_Register_Masks OSC Register Masks
* @{
*/
/* CR Bit Fields */
#define OSC_CR_SC16P_MASK 0x1u
#define OSC_CR_SC16P_SHIFT 0
#define OSC_CR_SC8P_MASK 0x2u
#define OSC_CR_SC8P_SHIFT 1
#define OSC_CR_SC4P_MASK 0x4u
#define OSC_CR_SC4P_SHIFT 2
#define OSC_CR_SC2P_MASK 0x8u
#define OSC_CR_SC2P_SHIFT 3
#define OSC_CR_EREFSTEN_MASK 0x20u
#define OSC_CR_EREFSTEN_SHIFT 5
#define OSC_CR_ERCLKEN_MASK 0x80u
#define OSC_CR_ERCLKEN_SHIFT 7
/*!
* @}
*/ /* end of group OSC_Register_Masks */
/* OSC - Peripheral instance base addresses */
/** Peripheral OSC0 base address */
#define OSC0_BASE (0x40065000u)
/** Peripheral OSC0 base pointer */
#define OSC0 ((OSC_Type *)OSC0_BASE)
/** Array initializer of OSC peripheral base pointers */
#define OSC_BASES { OSC0 }
/*!
* @}
*/ /* end of group OSC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PDB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
* @{
*/
/** PDB - Register Layout Typedef */
typedef struct {
__IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
__IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
__I uint32_t CNT; /**< Counter register, offset: 0x8 */
__IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
struct { /* offset: 0x10, array step: 0x28 */
__IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
__IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
__IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
uint8_t RESERVED_0[24];
} CH[2];
uint8_t RESERVED_0[240];
struct { /* offset: 0x150, array step: 0x8 */
__IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
__IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
} DAC[1];
uint8_t RESERVED_1[56];
__IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
__IO uint32_t PODLY; /**< Pulse-Out n Delay register, offset: 0x194 */
} PDB_Type;
/* ----------------------------------------------------------------------------
-- PDB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDB_Register_Masks PDB Register Masks
* @{
*/
/* SC Bit Fields */
#define PDB_SC_LDOK_MASK 0x1u
#define PDB_SC_LDOK_SHIFT 0
#define PDB_SC_CONT_MASK 0x2u
#define PDB_SC_CONT_SHIFT 1
#define PDB_SC_MULT_MASK 0xCu
#define PDB_SC_MULT_SHIFT 2
#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
#define PDB_SC_PDBIE_MASK 0x20u
#define PDB_SC_PDBIE_SHIFT 5
#define PDB_SC_PDBIF_MASK 0x40u
#define PDB_SC_PDBIF_SHIFT 6
#define PDB_SC_PDBEN_MASK 0x80u
#define PDB_SC_PDBEN_SHIFT 7
#define PDB_SC_TRGSEL_MASK 0xF00u
#define PDB_SC_TRGSEL_SHIFT 8
#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
#define PDB_SC_PRESCALER_MASK 0x7000u
#define PDB_SC_PRESCALER_SHIFT 12
#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
#define PDB_SC_DMAEN_MASK 0x8000u
#define PDB_SC_DMAEN_SHIFT 15
#define PDB_SC_SWTRIG_MASK 0x10000u
#define PDB_SC_SWTRIG_SHIFT 16
#define PDB_SC_PDBEIE_MASK 0x20000u
#define PDB_SC_PDBEIE_SHIFT 17
#define PDB_SC_LDMOD_MASK 0xC0000u
#define PDB_SC_LDMOD_SHIFT 18
#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
/* MOD Bit Fields */
#define PDB_MOD_MOD_MASK 0xFFFFu
#define PDB_MOD_MOD_SHIFT 0
#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
/* CNT Bit Fields */
#define PDB_CNT_CNT_MASK 0xFFFFu
#define PDB_CNT_CNT_SHIFT 0
#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
/* IDLY Bit Fields */
#define PDB_IDLY_IDLY_MASK 0xFFFFu
#define PDB_IDLY_IDLY_SHIFT 0
#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
/* C1 Bit Fields */
#define PDB_C1_EN_MASK 0xFFu
#define PDB_C1_EN_SHIFT 0
#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
#define PDB_C1_TOS_MASK 0xFF00u
#define PDB_C1_TOS_SHIFT 8
#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
#define PDB_C1_BB_MASK 0xFF0000u
#define PDB_C1_BB_SHIFT 16
#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
/* S Bit Fields */
#define PDB_S_ERR_MASK 0xFFu
#define PDB_S_ERR_SHIFT 0
#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
#define PDB_S_CF_MASK 0xFF0000u
#define PDB_S_CF_SHIFT 16
#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
/* DLY Bit Fields */
#define PDB_DLY_DLY_MASK 0xFFFFu
#define PDB_DLY_DLY_SHIFT 0
#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
/* INTC Bit Fields */
#define PDB_INTC_TOE_MASK 0x1u
#define PDB_INTC_TOE_SHIFT 0
#define PDB_INTC_EXT_MASK 0x2u
#define PDB_INTC_EXT_SHIFT 1
/* INT Bit Fields */
#define PDB_INT_INT_MASK 0xFFFFu
#define PDB_INT_INT_SHIFT 0
#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
/* POEN Bit Fields */
#define PDB_POEN_POEN_MASK 0xFFu
#define PDB_POEN_POEN_SHIFT 0
#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
/* PODLY Bit Fields */
#define PDB_PODLY_DLY2_MASK 0xFFFFu
#define PDB_PODLY_DLY2_SHIFT 0
#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
#define PDB_PODLY_DLY1_SHIFT 16
#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
/*!
* @}
*/ /* end of group PDB_Register_Masks */
/* PDB - Peripheral instance base addresses */
/** Peripheral PDB0 base address */
#define PDB0_BASE (0x40036000u)
/** Peripheral PDB0 base pointer */
#define PDB0 ((PDB_Type *)PDB0_BASE)
/** Array initializer of PDB peripheral base pointers */
#define PDB_BASES { PDB0 }
/*!
* @}
*/ /* end of group PDB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
* @{
*/
/** PMC - Register Layout Typedef */
typedef struct {
__IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
__IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
__IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
} PMC_Type;
/* ----------------------------------------------------------------------------
-- PMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Masks PMC Register Masks
* @{
*/
/* LVDSC1 Bit Fields */
#define PMC_LVDSC1_LVDV_MASK 0x3u
#define PMC_LVDSC1_LVDV_SHIFT 0
#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
#define PMC_LVDSC1_LVDRE_MASK 0x10u
#define PMC_LVDSC1_LVDRE_SHIFT 4
#define PMC_LVDSC1_LVDIE_MASK 0x20u
#define PMC_LVDSC1_LVDIE_SHIFT 5
#define PMC_LVDSC1_LVDACK_MASK 0x40u
#define PMC_LVDSC1_LVDACK_SHIFT 6
#define PMC_LVDSC1_LVDF_MASK 0x80u
#define PMC_LVDSC1_LVDF_SHIFT 7
/* LVDSC2 Bit Fields */
#define PMC_LVDSC2_LVWV_MASK 0x3u
#define PMC_LVDSC2_LVWV_SHIFT 0
#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
#define PMC_LVDSC2_LVWIE_MASK 0x20u
#define PMC_LVDSC2_LVWIE_SHIFT 5
#define PMC_LVDSC2_LVWACK_MASK 0x40u
#define PMC_LVDSC2_LVWACK_SHIFT 6
#define PMC_LVDSC2_LVWF_MASK 0x80u
#define PMC_LVDSC2_LVWF_SHIFT 7
/* REGSC Bit Fields */
#define PMC_REGSC_BGBE_MASK 0x1u
#define PMC_REGSC_BGBE_SHIFT 0
#define PMC_REGSC_REGONS_MASK 0x4u
#define PMC_REGSC_REGONS_SHIFT 2
#define PMC_REGSC_ACKISO_MASK 0x8u
#define PMC_REGSC_ACKISO_SHIFT 3
#define PMC_REGSC_BGEN_MASK 0x10u
#define PMC_REGSC_BGEN_SHIFT 4
/*!
* @}
*/ /* end of group PMC_Register_Masks */
/* PMC - Peripheral instance base addresses */
/** Peripheral PMC base address */
#define PMC_BASE (0x4007D000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
/** Array initializer of PMC peripheral base pointers */
#define PMC_BASES { PMC }
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PORT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
* @{
*/
/** PORT - Register Layout Typedef */
typedef struct {
__IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
__IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
} PORT_Type;
/* ----------------------------------------------------------------------------
-- PORT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Masks PORT Register Masks
* @{
*/
/* PCR Bit Fields */
#define PORT_PCR_PS_MASK 0x1u
#define PORT_PCR_PS_SHIFT 0
#define PORT_PCR_PE_MASK 0x2u
#define PORT_PCR_PE_SHIFT 1
#define PORT_PCR_SRE_MASK 0x4u
#define PORT_PCR_SRE_SHIFT 2
#define PORT_PCR_PFE_MASK 0x10u
#define PORT_PCR_PFE_SHIFT 4
#define PORT_PCR_DSE_MASK 0x40u
#define PORT_PCR_DSE_SHIFT 6
#define PORT_PCR_MUX_MASK 0x700u
#define PORT_PCR_MUX_SHIFT 8
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
#define PORT_PCR_IRQC_MASK 0xF0000u
#define PORT_PCR_IRQC_SHIFT 16
#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
#define PORT_PCR_ISF_MASK 0x1000000u
#define PORT_PCR_ISF_SHIFT 24
/* GPCLR Bit Fields */
#define PORT_GPCLR_GPWD_MASK 0xFFFFu
#define PORT_GPCLR_GPWD_SHIFT 0
#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCLR_GPWE_SHIFT 16
#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
/* GPCHR Bit Fields */
#define PORT_GPCHR_GPWD_MASK 0xFFFFu
#define PORT_GPCHR_GPWD_SHIFT 0
#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCHR_GPWE_SHIFT 16
#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
/* ISFR Bit Fields */
#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
#define PORT_ISFR_ISF_SHIFT 0
#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
/*!
* @}
*/ /* end of group PORT_Register_Masks */
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base address */
#define PORTA_BASE (0x40049000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4004A000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
/** Peripheral PORTC base address */
#define PORTC_BASE (0x4004B000u)
/** Peripheral PORTC base pointer */
#define PORTC ((PORT_Type *)PORTC_BASE)
/** Peripheral PORTD base address */
#define PORTD_BASE (0x4004C000u)
/** Peripheral PORTD base pointer */
#define PORTD ((PORT_Type *)PORTD_BASE)
/** Peripheral PORTE base address */
#define PORTE_BASE (0x4004D000u)
/** Peripheral PORTE base pointer */
#define PORTE ((PORT_Type *)PORTE_BASE)
/** Array initializer of PORT peripheral base pointers */
#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
* @{
*/
/** RCM - Register Layout Typedef */
typedef struct {
__I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
__I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
uint8_t RESERVED_0[2];
__IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
__IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
} RCM_Type;
/* ----------------------------------------------------------------------------
-- RCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Masks RCM Register Masks
* @{
*/
/* SRS0 Bit Fields */
#define RCM_SRS0_WAKEUP_MASK 0x1u
#define RCM_SRS0_WAKEUP_SHIFT 0
#define RCM_SRS0_LVD_MASK 0x2u
#define RCM_SRS0_LVD_SHIFT 1
#define RCM_SRS0_LOC_MASK 0x4u
#define RCM_SRS0_LOC_SHIFT 2
#define RCM_SRS0_WDOG_MASK 0x20u
#define RCM_SRS0_WDOG_SHIFT 5
#define RCM_SRS0_PIN_MASK 0x40u
#define RCM_SRS0_PIN_SHIFT 6
#define RCM_SRS0_POR_MASK 0x80u
#define RCM_SRS0_POR_SHIFT 7
/* SRS1 Bit Fields */
#define RCM_SRS1_LOCKUP_MASK 0x2u
#define RCM_SRS1_LOCKUP_SHIFT 1
#define RCM_SRS1_SW_MASK 0x4u
#define RCM_SRS1_SW_SHIFT 2
#define RCM_SRS1_MDM_AP_MASK 0x8u
#define RCM_SRS1_MDM_AP_SHIFT 3
#define RCM_SRS1_SACKERR_MASK 0x20u
#define RCM_SRS1_SACKERR_SHIFT 5
/* RPFC Bit Fields */
#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
#define RCM_RPFC_RSTFLTSRW_SHIFT 0
#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
#define RCM_RPFC_RSTFLTSS_MASK 0x4u
#define RCM_RPFC_RSTFLTSS_SHIFT 2
/* RPFW Bit Fields */
#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
#define RCM_RPFW_RSTFLTSEL_SHIFT 0
#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
/*!
* @}
*/ /* end of group RCM_Register_Masks */
/* RCM - Peripheral instance base addresses */
/** Peripheral RCM base address */
#define RCM_BASE (0x4007F000u)
/** Peripheral RCM base pointer */
#define RCM ((RCM_Type *)RCM_BASE)
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASES { RCM }
/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ROM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
* @{
*/
/** ROM - Register Layout Typedef */
typedef struct {
__I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
__I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
uint8_t RESERVED_0[4028];
__I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
__I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
__I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
__I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
__I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
__I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
__I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
__I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
__I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
} ROM_Type;
/* ----------------------------------------------------------------------------
-- ROM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ROM_Register_Masks ROM Register Masks
* @{
*/
/* ENTRY Bit Fields */
#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
#define ROM_ENTRY_ENTRY_SHIFT 0
#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
/* TABLEMARK Bit Fields */
#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
#define ROM_TABLEMARK_MARK_SHIFT 0
#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
/* SYSACCESS Bit Fields */
#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
/* PERIPHID4 Bit Fields */
#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
#define ROM_PERIPHID4_PERIPHID_SHIFT 0
#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
/* PERIPHID5 Bit Fields */
#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
#define ROM_PERIPHID5_PERIPHID_SHIFT 0
#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
/* PERIPHID6 Bit Fields */
#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
#define ROM_PERIPHID6_PERIPHID_SHIFT 0
#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
/* PERIPHID7 Bit Fields */
#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
#define ROM_PERIPHID7_PERIPHID_SHIFT 0
#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
/* PERIPHID0 Bit Fields */
#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
#define ROM_PERIPHID0_PERIPHID_SHIFT 0
#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
/* PERIPHID1 Bit Fields */
#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
#define ROM_PERIPHID1_PERIPHID_SHIFT 0
#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
/* PERIPHID2 Bit Fields */
#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
#define ROM_PERIPHID2_PERIPHID_SHIFT 0
#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
/* PERIPHID3 Bit Fields */
#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
#define ROM_PERIPHID3_PERIPHID_SHIFT 0
#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
/* COMPID Bit Fields */
#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
#define ROM_COMPID_COMPID_SHIFT 0
#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
/*!
* @}
*/ /* end of group ROM_Register_Masks */
/* ROM - Peripheral instance base addresses */
/** Peripheral ROM base address */
#define ROM_BASE (0xF0002000u)
/** Peripheral ROM base pointer */
#define ROM ((ROM_Type *)ROM_BASE)
/** Array initializer of ROM peripheral base pointers */
#define ROM_BASES { ROM }
/*!
* @}
*/ /* end of group ROM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
* @{
*/
/** SIM - Register Layout Typedef */
typedef struct {
__IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
uint8_t RESERVED_0[4096];
__IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
uint8_t RESERVED_1[4];
__IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
__IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
uint8_t RESERVED_2[4];
__IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
__IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
uint8_t RESERVED_3[4];
__I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint8_t RESERVED_4[12];
__IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
__IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
__IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
__IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
__IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
uint8_t RESERVED_5[4];
__IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
__I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
uint8_t RESERVED_6[4];
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
uint8_t RESERVED_7[156];
__IO uint32_t WDOGCTRL; /**< WDOG Control Register, offset: 0x1100 */
} SIM_Type;
/* ----------------------------------------------------------------------------
-- SIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Masks SIM Register Masks
* @{
*/
/* SOPT1 Bit Fields */
#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
#define SIM_SOPT1_OSC32KSEL_SHIFT 18
#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
/* SOPT2 Bit Fields */
#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
#define SIM_SOPT2_FTMFFCLKSEL_MASK 0x3000000u
#define SIM_SOPT2_FTMFFCLKSEL_SHIFT 24
#define SIM_SOPT2_FTMFFCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FTMFFCLKSEL_SHIFT))&SIM_SOPT2_FTMFFCLKSEL_MASK)
/* SOPT4 Bit Fields */
#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
#define SIM_SOPT4_FTM0FLT0_SHIFT 0
#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
#define SIM_SOPT4_FTM0FLT1_SHIFT 1
#define SIM_SOPT4_FTM1FLT0_MASK 0x4u
#define SIM_SOPT4_FTM1FLT0_SHIFT 2
#define SIM_SOPT4_FTM2FLT0_MASK 0x8u
#define SIM_SOPT4_FTM2FLT0_SHIFT 3
#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x80u
#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 7
#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x100u
#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 8
#define SIM_SOPT4_FTM0TRG2SRC_MASK 0x200u
#define SIM_SOPT4_FTM0TRG2SRC_SHIFT 9
#define SIM_SOPT4_FTM1TRG0SRC_MASK 0x400u
#define SIM_SOPT4_FTM1TRG0SRC_SHIFT 10
#define SIM_SOPT4_FTM1TRG1SRC_MASK 0x800u
#define SIM_SOPT4_FTM1TRG1SRC_SHIFT 11
#define SIM_SOPT4_FTM1TRG2SRC_MASK 0x1000u
#define SIM_SOPT4_FTM1TRG2SRC_SHIFT 12
#define SIM_SOPT4_FTM2TRG0SRC_MASK 0x2000u
#define SIM_SOPT4_FTM2TRG0SRC_SHIFT 13
#define SIM_SOPT4_FTM2TRG1SRC_MASK 0x4000u
#define SIM_SOPT4_FTM2TRG1SRC_SHIFT 14
#define SIM_SOPT4_FTM2TRG2SRC_MASK 0x8000u
#define SIM_SOPT4_FTM2TRG2SRC_SHIFT 15
#define SIM_SOPT4_FTM1ICH0SRC_MASK 0xC0000u
#define SIM_SOPT4_FTM1ICH0SRC_SHIFT 18
#define SIM_SOPT4_FTM1ICH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1ICH0SRC_SHIFT))&SIM_SOPT4_FTM1ICH0SRC_MASK)
#define SIM_SOPT4_FTM2ICH0SRC_MASK 0x300000u
#define SIM_SOPT4_FTM2ICH0SRC_SHIFT 20
#define SIM_SOPT4_FTM2ICH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2ICH0SRC_SHIFT))&SIM_SOPT4_FTM2ICH0SRC_MASK)
#define SIM_SOPT4_FTM2ICH1SRC_MASK 0x400000u
#define SIM_SOPT4_FTM2ICH1SRC_SHIFT 22
#define SIM_SOPT4_FTM0CLKSEL_MASK 0x3000000u
#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
#define SIM_SOPT4_FTM1CLKSEL_MASK 0xC000000u
#define SIM_SOPT4_FTM1CLKSEL_SHIFT 26
#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
#define SIM_SOPT4_FTM2CLKSEL_MASK 0x30000000u
#define SIM_SOPT4_FTM2CLKSEL_SHIFT 28
#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
/* SOPT5 Bit Fields */
#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
#define SIM_SOPT5_UART0TXSRC_SHIFT 0
#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
#define SIM_SOPT5_UART0RXSRC_SHIFT 2
#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
#define SIM_SOPT5_UART1TXSRC_SHIFT 4
#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
#define SIM_SOPT5_UART1RXSRC_SHIFT 6
#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
#define SIM_SOPT5_UART0ODE_MASK 0x10000u
#define SIM_SOPT5_UART0ODE_SHIFT 16
#define SIM_SOPT5_UART1ODE_MASK 0x20000u
#define SIM_SOPT5_UART1ODE_SHIFT 17
/* SOPT7 Bit Fields */
#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
#define SIM_SOPT7_ADC0ALTCLKSRC_MASK 0x3000000u
#define SIM_SOPT7_ADC0ALTCLKSRC_SHIFT 24
#define SIM_SOPT7_ADC0ALTCLKSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTCLKSRC_SHIFT))&SIM_SOPT7_ADC0ALTCLKSRC_MASK)
#define SIM_SOPT7_ADC1ALTCLKSRC_MASK 0xC000000u
#define SIM_SOPT7_ADC1ALTCLKSRC_SHIFT 26
#define SIM_SOPT7_ADC1ALTCLKSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTCLKSRC_SHIFT))&SIM_SOPT7_ADC1ALTCLKSRC_MASK)
/* SOPT8 Bit Fields */
#define SIM_SOPT8_FTM0SYNCBIT_MASK 0x1u
#define SIM_SOPT8_FTM0SYNCBIT_SHIFT 0
#define SIM_SOPT8_FTM1SYNCBIT_MASK 0x2u
#define SIM_SOPT8_FTM1SYNCBIT_SHIFT 1
#define SIM_SOPT8_FTM2SYNCBIT_MASK 0x4u
#define SIM_SOPT8_FTM2SYNCBIT_SHIFT 2
#define SIM_SOPT8_CARRIER_SELECT_MASK 0x100u
#define SIM_SOPT8_CARRIER_SELECT_SHIFT 8
#define SIM_SOPT8_FTM0OCH0SRC_MASK 0x10000u
#define SIM_SOPT8_FTM0OCH0SRC_SHIFT 16
#define SIM_SOPT8_FTM0OCH1SRC_MASK 0x20000u
#define SIM_SOPT8_FTM0OCH1SRC_SHIFT 17
#define SIM_SOPT8_FTM0OCH2SRC_MASK 0x40000u
#define SIM_SOPT8_FTM0OCH2SRC_SHIFT 18
#define SIM_SOPT8_FTM0OCH3SRC_MASK 0x80000u
#define SIM_SOPT8_FTM0OCH3SRC_SHIFT 19
#define SIM_SOPT8_FTM0OCH4SRC_MASK 0x100000u
#define SIM_SOPT8_FTM0OCH4SRC_SHIFT 20
#define SIM_SOPT8_FTM0OCH5SRC_MASK 0x200000u
#define SIM_SOPT8_FTM0OCH5SRC_SHIFT 21
#define SIM_SOPT8_FTM2OCH0SRC_MASK 0x400000u
#define SIM_SOPT8_FTM2OCH0SRC_SHIFT 22
#define SIM_SOPT8_FTM2OCH1SRC_MASK 0x800000u
#define SIM_SOPT8_FTM2OCH1SRC_SHIFT 23
/* SDID Bit Fields */
#define SIM_SDID_PINID_MASK 0xFu
#define SIM_SDID_PINID_SHIFT 0
#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
#define SIM_SDID_DIEID_MASK 0xF80u
#define SIM_SDID_DIEID_SHIFT 7
#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
#define SIM_SDID_REVID_MASK 0xF000u
#define SIM_SDID_REVID_SHIFT 12
#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
#define SIM_SDID_SRAMSIZE_SHIFT 16
#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
#define SIM_SDID_SERIERID_MASK 0xF00000u
#define SIM_SDID_SERIERID_SHIFT 20
#define SIM_SDID_SERIERID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIERID_SHIFT))&SIM_SDID_SERIERID_MASK)
#define SIM_SDID_SUBFAMID_MASK 0xF000000u
#define SIM_SDID_SUBFAMID_SHIFT 24
#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
#define SIM_SDID_FAMID_MASK 0xF0000000u
#define SIM_SDID_FAMID_SHIFT 28
#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
/* SCGC4 Bit Fields */
#define SIM_SCGC4_EWM_MASK 0x2u
#define SIM_SCGC4_EWM_SHIFT 1
#define SIM_SCGC4_I2C0_MASK 0x40u
#define SIM_SCGC4_I2C0_SHIFT 6
#define SIM_SCGC4_UART0_MASK 0x400u
#define SIM_SCGC4_UART0_SHIFT 10
#define SIM_SCGC4_UART1_MASK 0x800u
#define SIM_SCGC4_UART1_SHIFT 11
#define SIM_SCGC4_CMP_MASK 0x80000u
#define SIM_SCGC4_CMP_SHIFT 19
/* SCGC5 Bit Fields */
#define SIM_SCGC5_LPTMR_MASK 0x1u
#define SIM_SCGC5_LPTMR_SHIFT 0
#define SIM_SCGC5_PORTA_MASK 0x200u
#define SIM_SCGC5_PORTA_SHIFT 9
#define SIM_SCGC5_PORTB_MASK 0x400u
#define SIM_SCGC5_PORTB_SHIFT 10
#define SIM_SCGC5_PORTC_MASK 0x800u
#define SIM_SCGC5_PORTC_SHIFT 11
#define SIM_SCGC5_PORTD_MASK 0x1000u
#define SIM_SCGC5_PORTD_SHIFT 12
#define SIM_SCGC5_PORTE_MASK 0x2000u
#define SIM_SCGC5_PORTE_SHIFT 13
/* SCGC6 Bit Fields */
#define SIM_SCGC6_FTF_MASK 0x1u
#define SIM_SCGC6_FTF_SHIFT 0
#define SIM_SCGC6_DMAMUX_MASK 0x2u
#define SIM_SCGC6_DMAMUX_SHIFT 1
#define SIM_SCGC6_SPI0_MASK 0x1000u
#define SIM_SCGC6_SPI0_SHIFT 12
#define SIM_SCGC6_CRC_MASK 0x40000u
#define SIM_SCGC6_CRC_SHIFT 18
#define SIM_SCGC6_PDB_MASK 0x400000u
#define SIM_SCGC6_PDB_SHIFT 22
#define SIM_SCGC6_FTM0_MASK 0x1000000u
#define SIM_SCGC6_FTM0_SHIFT 24
#define SIM_SCGC6_FTM1_MASK 0x2000000u
#define SIM_SCGC6_FTM1_SHIFT 25
#define SIM_SCGC6_FTM2_MASK 0x4000000u
#define SIM_SCGC6_FTM2_SHIFT 26
#define SIM_SCGC6_ADC0_MASK 0x8000000u
#define SIM_SCGC6_ADC0_SHIFT 27
#define SIM_SCGC6_ADC1_MASK 0x10000000u
#define SIM_SCGC6_ADC1_SHIFT 28
#define SIM_SCGC6_DAC0_MASK 0x80000000u
#define SIM_SCGC6_DAC0_SHIFT 31
/* SCGC7 Bit Fields */
#define SIM_SCGC7_DMA_MASK 0x100u
#define SIM_SCGC7_DMA_SHIFT 8
/* CLKDIV1 Bit Fields */
#define SIM_CLKDIV1_OUTDIV5_MASK 0x7000u
#define SIM_CLKDIV1_OUTDIV5_SHIFT 12
#define SIM_CLKDIV1_OUTDIV5(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV5_SHIFT))&SIM_CLKDIV1_OUTDIV5_MASK)
#define SIM_CLKDIV1_OUTDIV5EN_MASK 0x8000u
#define SIM_CLKDIV1_OUTDIV5EN_SHIFT 15
#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
/* FCFG1 Bit Fields */
#define SIM_FCFG1_FLASHDIS_MASK 0x1u
#define SIM_FCFG1_FLASHDIS_SHIFT 0
#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
#define SIM_FCFG1_FLASHDOZE_SHIFT 1
#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
#define SIM_FCFG1_PFSIZE_SHIFT 24
#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
/* FCFG2 Bit Fields */
#define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
#define SIM_FCFG2_MAXADDR_SHIFT 24
#define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
/* UIDMH Bit Fields */
#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
#define SIM_UIDMH_UID_SHIFT 0
#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
/* UIDML Bit Fields */
#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
#define SIM_UIDML_UID_SHIFT 0
#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
/* UIDL Bit Fields */
#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
#define SIM_UIDL_UID_SHIFT 0
#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
/* WDOGCTRL Bit Fields */
#define SIM_WDOGCTRL_WDOGCLKS_MASK 0x2u
#define SIM_WDOGCTRL_WDOGCLKS_SHIFT 1
/*!
* @}
*/ /* end of group SIM_Register_Masks */
/* SIM - Peripheral instance base addresses */
/** Peripheral SIM base address */
#define SIM_BASE (0x40047000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASES { SIM }
/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
* @{
*/
/** SMC - Register Layout Typedef */
typedef struct {
__IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
__IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
__IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
__I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
} SMC_Type;
/* ----------------------------------------------------------------------------
-- SMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Masks SMC Register Masks
* @{
*/
/* PMPROT Bit Fields */
#define SMC_PMPROT_AVLLS_MASK 0x2u
#define SMC_PMPROT_AVLLS_SHIFT 1
#define SMC_PMPROT_AVLP_MASK 0x20u
#define SMC_PMPROT_AVLP_SHIFT 5
/* PMCTRL Bit Fields */
#define SMC_PMCTRL_STOPM_MASK 0x7u
#define SMC_PMCTRL_STOPM_SHIFT 0
#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
#define SMC_PMCTRL_STOPA_MASK 0x8u
#define SMC_PMCTRL_STOPA_SHIFT 3
#define SMC_PMCTRL_RUNM_MASK 0x60u
#define SMC_PMCTRL_RUNM_SHIFT 5
#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
/* STOPCTRL Bit Fields */
#define SMC_STOPCTRL_VLLSM_MASK 0x7u
#define SMC_STOPCTRL_VLLSM_SHIFT 0
#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
#define SMC_STOPCTRL_LPOPO_MASK 0x8u
#define SMC_STOPCTRL_LPOPO_SHIFT 3
#define SMC_STOPCTRL_PORPO_MASK 0x20u
#define SMC_STOPCTRL_PORPO_SHIFT 5
#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
#define SMC_STOPCTRL_PSTOPO_SHIFT 6
#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
/* PMSTAT Bit Fields */
#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
#define SMC_PMSTAT_PMSTAT_SHIFT 0
#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
/*!
* @}
*/ /* end of group SMC_Register_Masks */
/* SMC - Peripheral instance base addresses */
/** Peripheral SMC base address */
#define SMC_BASE (0x4007E000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASES { SMC }
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
* @{
*/
/** SPI - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
uint8_t RESERVED_0[4];
__IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
union { /* offset: 0xC */
__IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
__IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
};
uint8_t RESERVED_1[24];
__IO uint32_t SR; /**< Status Register, offset: 0x2C */
__IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
union { /* offset: 0x34 */
__IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
__IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
};
__I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
__I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
__I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
__I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
__I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
uint8_t RESERVED_2[48];
__I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
__I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
__I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
__I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
uint8_t RESERVED_3[176];
__IO uint32_t SREX; /**< Status Register Extended, offset: 0x13C */
} SPI_Type;
/* ----------------------------------------------------------------------------
-- SPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Register_Masks SPI Register Masks
* @{
*/
/* MCR Bit Fields */
#define SPI_MCR_HALT_MASK 0x1u
#define SPI_MCR_HALT_SHIFT 0
#define SPI_MCR_SMPL_PT_MASK 0x300u
#define SPI_MCR_SMPL_PT_SHIFT 8
#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
#define SPI_MCR_CLR_RXF_MASK 0x400u
#define SPI_MCR_CLR_RXF_SHIFT 10
#define SPI_MCR_CLR_TXF_MASK 0x800u
#define SPI_MCR_CLR_TXF_SHIFT 11
#define SPI_MCR_DIS_RXF_MASK 0x1000u
#define SPI_MCR_DIS_RXF_SHIFT 12
#define SPI_MCR_DIS_TXF_MASK 0x2000u
#define SPI_MCR_DIS_TXF_SHIFT 13
#define SPI_MCR_MDIS_MASK 0x4000u
#define SPI_MCR_MDIS_SHIFT 14
#define SPI_MCR_DOZE_MASK 0x8000u
#define SPI_MCR_DOZE_SHIFT 15
#define SPI_MCR_PCSIS_MASK 0x1F0000u
#define SPI_MCR_PCSIS_SHIFT 16
#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
#define SPI_MCR_ROOE_MASK 0x1000000u
#define SPI_MCR_ROOE_SHIFT 24
#define SPI_MCR_MTFE_MASK 0x4000000u
#define SPI_MCR_MTFE_SHIFT 26
#define SPI_MCR_FRZ_MASK 0x8000000u
#define SPI_MCR_FRZ_SHIFT 27
#define SPI_MCR_DCONF_MASK 0x30000000u
#define SPI_MCR_DCONF_SHIFT 28
#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
#define SPI_MCR_CONT_SCKE_SHIFT 30
#define SPI_MCR_MSTR_MASK 0x80000000u
#define SPI_MCR_MSTR_SHIFT 31
/* TCR Bit Fields */
#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
#define SPI_TCR_SPI_TCNT_SHIFT 16
#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
/* CTAR Bit Fields */
#define SPI_CTAR_BR_MASK 0xFu
#define SPI_CTAR_BR_SHIFT 0
#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
#define SPI_CTAR_DT_MASK 0xF0u
#define SPI_CTAR_DT_SHIFT 4
#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
#define SPI_CTAR_ASC_MASK 0xF00u
#define SPI_CTAR_ASC_SHIFT 8
#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
#define SPI_CTAR_CSSCK_MASK 0xF000u
#define SPI_CTAR_CSSCK_SHIFT 12
#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
#define SPI_CTAR_PBR_MASK 0x30000u
#define SPI_CTAR_PBR_SHIFT 16
#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
#define SPI_CTAR_PDT_MASK 0xC0000u
#define SPI_CTAR_PDT_SHIFT 18
#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
#define SPI_CTAR_PASC_MASK 0x300000u
#define SPI_CTAR_PASC_SHIFT 20
#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
#define SPI_CTAR_PCSSCK_MASK 0xC00000u
#define SPI_CTAR_PCSSCK_SHIFT 22
#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
#define SPI_CTAR_LSBFE_MASK 0x1000000u
#define SPI_CTAR_LSBFE_SHIFT 24
#define SPI_CTAR_CPHA_MASK 0x2000000u
#define SPI_CTAR_CPHA_SHIFT 25
#define SPI_CTAR_CPOL_MASK 0x4000000u
#define SPI_CTAR_CPOL_SHIFT 26
#define SPI_CTAR_FMSZ_MASK 0x78000000u
#define SPI_CTAR_FMSZ_SHIFT 27
#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
#define SPI_CTAR_DBR_MASK 0x80000000u
#define SPI_CTAR_DBR_SHIFT 31
/* CTAR_SLAVE Bit Fields */
#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
/* SR Bit Fields */
#define SPI_SR_POPNXTPTR_MASK 0xFu
#define SPI_SR_POPNXTPTR_SHIFT 0
#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
#define SPI_SR_RXCTR_MASK 0xF0u
#define SPI_SR_RXCTR_SHIFT 4
#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
#define SPI_SR_TXNXTPTR_MASK 0xF00u
#define SPI_SR_TXNXTPTR_SHIFT 8
#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
#define SPI_SR_TXCTR_MASK 0xF000u
#define SPI_SR_TXCTR_SHIFT 12
#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
#define SPI_SR_RFDF_MASK 0x20000u
#define SPI_SR_RFDF_SHIFT 17
#define SPI_SR_RFOF_MASK 0x80000u
#define SPI_SR_RFOF_SHIFT 19
#define SPI_SR_TFFF_MASK 0x2000000u
#define SPI_SR_TFFF_SHIFT 25
#define SPI_SR_TFUF_MASK 0x8000000u
#define SPI_SR_TFUF_SHIFT 27
#define SPI_SR_EOQF_MASK 0x10000000u
#define SPI_SR_EOQF_SHIFT 28
#define SPI_SR_TXRXS_MASK 0x40000000u
#define SPI_SR_TXRXS_SHIFT 30
#define SPI_SR_TCF_MASK 0x80000000u
#define SPI_SR_TCF_SHIFT 31
/* RSER Bit Fields */
#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
#define SPI_RSER_RFDF_DIRS_SHIFT 16
#define SPI_RSER_RFDF_RE_MASK 0x20000u
#define SPI_RSER_RFDF_RE_SHIFT 17
#define SPI_RSER_RFOF_RE_MASK 0x80000u
#define SPI_RSER_RFOF_RE_SHIFT 19
#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
#define SPI_RSER_TFFF_DIRS_SHIFT 24
#define SPI_RSER_TFFF_RE_MASK 0x2000000u
#define SPI_RSER_TFFF_RE_SHIFT 25
#define SPI_RSER_TFUF_RE_MASK 0x8000000u
#define SPI_RSER_TFUF_RE_SHIFT 27
#define SPI_RSER_EOQF_RE_MASK 0x10000000u
#define SPI_RSER_EOQF_RE_SHIFT 28
#define SPI_RSER_TCF_RE_MASK 0x80000000u
#define SPI_RSER_TCF_RE_SHIFT 31
/* PUSHR Bit Fields */
#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
#define SPI_PUSHR_TXDATA_SHIFT 0
#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
#define SPI_PUSHR_PCS_MASK 0x1F0000u
#define SPI_PUSHR_PCS_SHIFT 16
#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
#define SPI_PUSHR_CTCNT_MASK 0x4000000u
#define SPI_PUSHR_CTCNT_SHIFT 26
#define SPI_PUSHR_EOQ_MASK 0x8000000u
#define SPI_PUSHR_EOQ_SHIFT 27
#define SPI_PUSHR_CTAS_MASK 0x70000000u
#define SPI_PUSHR_CTAS_SHIFT 28
#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
#define SPI_PUSHR_CONT_MASK 0x80000000u
#define SPI_PUSHR_CONT_SHIFT 31
/* PUSHR_SLAVE Bit Fields */
#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFu
#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
/* POPR Bit Fields */
#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
#define SPI_POPR_RXDATA_SHIFT 0
#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
/* TXFR0 Bit Fields */
#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
#define SPI_TXFR0_TXDATA_SHIFT 0
#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
/* TXFR1 Bit Fields */
#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
#define SPI_TXFR1_TXDATA_SHIFT 0
#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
/* TXFR2 Bit Fields */
#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
#define SPI_TXFR2_TXDATA_SHIFT 0
#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
/* TXFR3 Bit Fields */
#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
#define SPI_TXFR3_TXDATA_SHIFT 0
#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
/* RXFR0 Bit Fields */
#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR0_RXDATA_SHIFT 0
#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
/* RXFR1 Bit Fields */
#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR1_RXDATA_SHIFT 0
#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
/* RXFR2 Bit Fields */
#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR2_RXDATA_SHIFT 0
#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
/* RXFR3 Bit Fields */
#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR3_RXDATA_SHIFT 0
#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
/* SREX Bit Fields */
#define SPI_SREX_CMDNXTPTR_MASK 0xFu
#define SPI_SREX_CMDNXTPTR_SHIFT 0
#define SPI_SREX_CMDNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SREX_CMDNXTPTR_SHIFT))&SPI_SREX_CMDNXTPTR_MASK)
#define SPI_SREX_CMDCTR_MASK 0x1F0u
#define SPI_SREX_CMDCTR_SHIFT 4
#define SPI_SREX_CMDCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SREX_CMDCTR_SHIFT))&SPI_SREX_CMDCTR_MASK)
#define SPI_SREX_TXCTR4_MASK 0x800u
#define SPI_SREX_TXCTR4_SHIFT 11
#define SPI_SREX_RXCTR4_MASK 0x4000u
#define SPI_SREX_RXCTR4_SHIFT 14
/*!
* @}
*/ /* end of group SPI_Register_Masks */
/* SPI - Peripheral instance base addresses */
/** Peripheral SPI0 base address */
#define SPI0_BASE (0x4002C000u)
/** Peripheral SPI0 base pointer */
#define SPI0 ((SPI_Type *)SPI0_BASE)
/** Array initializer of SPI peripheral base pointers */
#define SPI_BASES { SPI0 }
/*!
* @}
*/ /* end of group SPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- UART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
* @{
*/
/** UART - Register Layout Typedef */
typedef struct {
__IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
__IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
__IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
__IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
__I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
__IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
__IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
__IO uint8_t D; /**< UART Data Register, offset: 0x7 */
__IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
__IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
__IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
__IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
__I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
__IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
uint8_t RESERVED_0[2];
__IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
__IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
__IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
__IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
__I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
__IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
__I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
uint8_t RESERVED_1[10];
__IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
__IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
__IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
__IO uint8_t IE0; /**< UART CEA709.1-B Interrupt Enable Register 0, offset: 0x24 */
__IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
__IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
__IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
__IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
__IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
__IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
__IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
__IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
__I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
__I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
__IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
__IO uint8_t RIDTH; /**< UART CEA709.1-B Receive Indeterminate Time High, offset: 0x30 */
__IO uint8_t RIDTL; /**< UART CEA709.1-B Receive Indeterminate Time Low, offset: 0x31 */
__IO uint8_t TIDTH; /**< UART CEA709.1-B Transmit Indeterminate Time High, offset: 0x32 */
__IO uint8_t TIDTL; /**< UART CEA709.1-B Transmit Indeterminate Time Low, offset: 0x33 */
__IO uint8_t RB1TH; /**< UART CEA709.1-B Receive Beta1 Timer High, offset: 0x34 */
__IO uint8_t RB1TL; /**< UART CEA709.1-B Receive Beta1 Timer Low, offset: 0x35 */
__IO uint8_t TB1TH; /**< UART CEA709.1-B Transmit Beta1 Timer High, offset: 0x36 */
__IO uint8_t TB1TL; /**< UART CEA709.1-B Transmit Beta1 Timer Low, offset: 0x37 */
__IO uint8_t PROG_REG; /**< UART CEA709.1-B Programmable register, offset: 0x38 */
__I uint8_t STATE_REG; /**< UART CEA709.1-B State register, offset: 0x39 */
} UART_Type;
/* ----------------------------------------------------------------------------
-- UART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup UART_Register_Masks UART Register Masks
* @{
*/
/* BDH Bit Fields */
#define UART_BDH_SBR_MASK 0x1Fu
#define UART_BDH_SBR_SHIFT 0
#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
#define UART_BDH_SBNS_MASK 0x20u
#define UART_BDH_SBNS_SHIFT 5
#define UART_BDH_RXEDGIE_MASK 0x40u
#define UART_BDH_RXEDGIE_SHIFT 6
#define UART_BDH_LBKDIE_MASK 0x80u
#define UART_BDH_LBKDIE_SHIFT 7
/* BDL Bit Fields */
#define UART_BDL_SBR_MASK 0xFFu
#define UART_BDL_SBR_SHIFT 0
#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
/* C1 Bit Fields */
#define UART_C1_PT_MASK 0x1u
#define UART_C1_PT_SHIFT 0
#define UART_C1_PE_MASK 0x2u
#define UART_C1_PE_SHIFT 1
#define UART_C1_ILT_MASK 0x4u
#define UART_C1_ILT_SHIFT 2
#define UART_C1_WAKE_MASK 0x8u
#define UART_C1_WAKE_SHIFT 3
#define UART_C1_M_MASK 0x10u
#define UART_C1_M_SHIFT 4
#define UART_C1_RSRC_MASK 0x20u
#define UART_C1_RSRC_SHIFT 5
#define UART_C1_UARTSWAI_MASK 0x40u
#define UART_C1_UARTSWAI_SHIFT 6
#define UART_C1_LOOPS_MASK 0x80u
#define UART_C1_LOOPS_SHIFT 7
/* C2 Bit Fields */
#define UART_C2_SBK_MASK 0x1u
#define UART_C2_SBK_SHIFT 0
#define UART_C2_RWU_MASK 0x2u
#define UART_C2_RWU_SHIFT 1
#define UART_C2_RE_MASK 0x4u
#define UART_C2_RE_SHIFT 2
#define UART_C2_TE_MASK 0x8u
#define UART_C2_TE_SHIFT 3
#define UART_C2_ILIE_MASK 0x10u
#define UART_C2_ILIE_SHIFT 4
#define UART_C2_RIE_MASK 0x20u
#define UART_C2_RIE_SHIFT 5
#define UART_C2_TCIE_MASK 0x40u
#define UART_C2_TCIE_SHIFT 6
#define UART_C2_TIE_MASK 0x80u
#define UART_C2_TIE_SHIFT 7
/* S1 Bit Fields */
#define UART_S1_PF_MASK 0x1u
#define UART_S1_PF_SHIFT 0
#define UART_S1_FE_MASK 0x2u
#define UART_S1_FE_SHIFT 1
#define UART_S1_NF_MASK 0x4u
#define UART_S1_NF_SHIFT 2
#define UART_S1_OR_MASK 0x8u
#define UART_S1_OR_SHIFT 3
#define UART_S1_IDLE_MASK 0x10u
#define UART_S1_IDLE_SHIFT 4
#define UART_S1_RDRF_MASK 0x20u
#define UART_S1_RDRF_SHIFT 5
#define UART_S1_TC_MASK 0x40u
#define UART_S1_TC_SHIFT 6
#define UART_S1_TDRE_MASK 0x80u
#define UART_S1_TDRE_SHIFT 7
/* S2 Bit Fields */
#define UART_S2_RAF_MASK 0x1u
#define UART_S2_RAF_SHIFT 0
#define UART_S2_LBKDE_MASK 0x2u
#define UART_S2_LBKDE_SHIFT 1
#define UART_S2_BRK13_MASK 0x4u
#define UART_S2_BRK13_SHIFT 2
#define UART_S2_RWUID_MASK 0x8u
#define UART_S2_RWUID_SHIFT 3
#define UART_S2_RXINV_MASK 0x10u
#define UART_S2_RXINV_SHIFT 4
#define UART_S2_MSBF_MASK 0x20u
#define UART_S2_MSBF_SHIFT 5
#define UART_S2_RXEDGIF_MASK 0x40u
#define UART_S2_RXEDGIF_SHIFT 6
#define UART_S2_LBKDIF_MASK 0x80u
#define UART_S2_LBKDIF_SHIFT 7
/* C3 Bit Fields */
#define UART_C3_PEIE_MASK 0x1u
#define UART_C3_PEIE_SHIFT 0
#define UART_C3_FEIE_MASK 0x2u
#define UART_C3_FEIE_SHIFT 1
#define UART_C3_NEIE_MASK 0x4u
#define UART_C3_NEIE_SHIFT 2
#define UART_C3_ORIE_MASK 0x8u
#define UART_C3_ORIE_SHIFT 3
#define UART_C3_TXINV_MASK 0x10u
#define UART_C3_TXINV_SHIFT 4
#define UART_C3_TXDIR_MASK 0x20u
#define UART_C3_TXDIR_SHIFT 5
#define UART_C3_T8_MASK 0x40u
#define UART_C3_T8_SHIFT 6
#define UART_C3_R8_MASK 0x80u
#define UART_C3_R8_SHIFT 7
/* D Bit Fields */
#define UART_D_RT_MASK 0xFFu
#define UART_D_RT_SHIFT 0
#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
/* MA1 Bit Fields */
#define UART_MA1_MA_MASK 0xFFu
#define UART_MA1_MA_SHIFT 0
#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
/* MA2 Bit Fields */
#define UART_MA2_MA_MASK 0xFFu
#define UART_MA2_MA_SHIFT 0
#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
/* C4 Bit Fields */
#define UART_C4_BRFA_MASK 0x1Fu
#define UART_C4_BRFA_SHIFT 0
#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
#define UART_C4_M10_MASK 0x20u
#define UART_C4_M10_SHIFT 5
#define UART_C4_MAEN2_MASK 0x40u
#define UART_C4_MAEN2_SHIFT 6
#define UART_C4_MAEN1_MASK 0x80u
#define UART_C4_MAEN1_SHIFT 7
/* C5 Bit Fields */
#define UART_C5_LBKDDMAS_MASK 0x8u
#define UART_C5_LBKDDMAS_SHIFT 3
#define UART_C5_RDMAS_MASK 0x20u
#define UART_C5_RDMAS_SHIFT 5
#define UART_C5_TDMAS_MASK 0x80u
#define UART_C5_TDMAS_SHIFT 7
/* ED Bit Fields */
#define UART_ED_PARITYE_MASK 0x40u
#define UART_ED_PARITYE_SHIFT 6
#define UART_ED_NOISY_MASK 0x80u
#define UART_ED_NOISY_SHIFT 7
/* MODEM Bit Fields */
#define UART_MODEM_TXCTSE_MASK 0x1u
#define UART_MODEM_TXCTSE_SHIFT 0
#define UART_MODEM_TXRTSE_MASK 0x2u
#define UART_MODEM_TXRTSE_SHIFT 1
#define UART_MODEM_TXRTSPOL_MASK 0x4u
#define UART_MODEM_TXRTSPOL_SHIFT 2
#define UART_MODEM_RXRTSE_MASK 0x8u
#define UART_MODEM_RXRTSE_SHIFT 3
/* PFIFO Bit Fields */
#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
#define UART_PFIFO_RXFE_MASK 0x8u
#define UART_PFIFO_RXFE_SHIFT 3
#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
#define UART_PFIFO_TXFE_MASK 0x80u
#define UART_PFIFO_TXFE_SHIFT 7
/* CFIFO Bit Fields */
#define UART_CFIFO_RXUFE_MASK 0x1u
#define UART_CFIFO_RXUFE_SHIFT 0
#define UART_CFIFO_TXOFE_MASK 0x2u
#define UART_CFIFO_TXOFE_SHIFT 1
#define UART_CFIFO_RXOFE_MASK 0x4u
#define UART_CFIFO_RXOFE_SHIFT 2
#define UART_CFIFO_RXFLUSH_MASK 0x40u
#define UART_CFIFO_RXFLUSH_SHIFT 6
#define UART_CFIFO_TXFLUSH_MASK 0x80u
#define UART_CFIFO_TXFLUSH_SHIFT 7
/* SFIFO Bit Fields */
#define UART_SFIFO_RXUF_MASK 0x1u
#define UART_SFIFO_RXUF_SHIFT 0
#define UART_SFIFO_TXOF_MASK 0x2u
#define UART_SFIFO_TXOF_SHIFT 1
#define UART_SFIFO_RXOF_MASK 0x4u
#define UART_SFIFO_RXOF_SHIFT 2
#define UART_SFIFO_RXEMPT_MASK 0x40u
#define UART_SFIFO_RXEMPT_SHIFT 6
#define UART_SFIFO_TXEMPT_MASK 0x80u
#define UART_SFIFO_TXEMPT_SHIFT 7
/* TWFIFO Bit Fields */
#define UART_TWFIFO_TXWATER_MASK 0xFFu
#define UART_TWFIFO_TXWATER_SHIFT 0
#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
/* TCFIFO Bit Fields */
#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
#define UART_TCFIFO_TXCOUNT_SHIFT 0
#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
/* RWFIFO Bit Fields */
#define UART_RWFIFO_RXWATER_MASK 0xFFu
#define UART_RWFIFO_RXWATER_SHIFT 0
#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
/* RCFIFO Bit Fields */
#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
#define UART_RCFIFO_RXCOUNT_SHIFT 0
#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
/* C6 Bit Fields */
#define UART_C6_CP_MASK 0x10u
#define UART_C6_CP_SHIFT 4
#define UART_C6_CE_MASK 0x20u
#define UART_C6_CE_SHIFT 5
#define UART_C6_TX709_MASK 0x40u
#define UART_C6_TX709_SHIFT 6
#define UART_C6_EN709_MASK 0x80u
#define UART_C6_EN709_SHIFT 7
/* PCTH Bit Fields */
#define UART_PCTH_PCTH_MASK 0xFFu
#define UART_PCTH_PCTH_SHIFT 0
#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
/* PCTL Bit Fields */
#define UART_PCTL_PCTL_MASK 0xFFu
#define UART_PCTL_PCTL_SHIFT 0
#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
/* IE0 Bit Fields */
#define UART_IE0_CPTXIE_MASK 0x1u
#define UART_IE0_CPTXIE_SHIFT 0
#define UART_IE0_CTXDIE_MASK 0x2u
#define UART_IE0_CTXDIE_SHIFT 1
#define UART_IE0_RPLOFIE_MASK 0x4u
#define UART_IE0_RPLOFIE_SHIFT 2
/* SDTH Bit Fields */
#define UART_SDTH_SDTH_MASK 0xFFu
#define UART_SDTH_SDTH_SHIFT 0
#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
/* SDTL Bit Fields */
#define UART_SDTL_SDTL_MASK 0xFFu
#define UART_SDTL_SDTL_SHIFT 0
#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
/* PRE Bit Fields */
#define UART_PRE_PREAMBLE_MASK 0xFFu
#define UART_PRE_PREAMBLE_SHIFT 0
#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
/* TPL Bit Fields */
#define UART_TPL_TPL_MASK 0xFFu
#define UART_TPL_TPL_SHIFT 0
#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
/* IE Bit Fields */
#define UART_IE_TXDIE_MASK 0x1u
#define UART_IE_TXDIE_SHIFT 0
#define UART_IE_PSIE_MASK 0x2u
#define UART_IE_PSIE_SHIFT 1
#define UART_IE_PCTEIE_MASK 0x4u
#define UART_IE_PCTEIE_SHIFT 2
#define UART_IE_PTXIE_MASK 0x8u
#define UART_IE_PTXIE_SHIFT 3
#define UART_IE_PRXIE_MASK 0x10u
#define UART_IE_PRXIE_SHIFT 4
#define UART_IE_ISDIE_MASK 0x20u
#define UART_IE_ISDIE_SHIFT 5
#define UART_IE_WBEIE_MASK 0x40u
#define UART_IE_WBEIE_SHIFT 6
#define UART_IE_PEIE_MASK 0x80u
#define UART_IE_PEIE_SHIFT 7
/* WB Bit Fields */
#define UART_WB_WBASE_MASK 0xFFu
#define UART_WB_WBASE_SHIFT 0
#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
/* S3 Bit Fields */
#define UART_S3_TXFF_MASK 0x1u
#define UART_S3_TXFF_SHIFT 0
#define UART_S3_PSF_MASK 0x2u
#define UART_S3_PSF_SHIFT 1
#define UART_S3_PCTEF_MASK 0x4u
#define UART_S3_PCTEF_SHIFT 2
#define UART_S3_PTXF_MASK 0x8u
#define UART_S3_PTXF_SHIFT 3
#define UART_S3_PRXF_MASK 0x10u
#define UART_S3_PRXF_SHIFT 4
#define UART_S3_ISD_MASK 0x20u
#define UART_S3_ISD_SHIFT 5
#define UART_S3_WBEF_MASK 0x40u
#define UART_S3_WBEF_SHIFT 6
#define UART_S3_PEF_MASK 0x80u
#define UART_S3_PEF_SHIFT 7
/* S4 Bit Fields */
#define UART_S4_FE_MASK 0x1u
#define UART_S4_FE_SHIFT 0
#define UART_S4_TXDF_MASK 0x2u
#define UART_S4_TXDF_SHIFT 1
#define UART_S4_CDET_MASK 0xCu
#define UART_S4_CDET_SHIFT 2
#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
#define UART_S4_RPLOF_MASK 0x10u
#define UART_S4_RPLOF_SHIFT 4
#define UART_S4_LNF_MASK 0x20u
#define UART_S4_LNF_SHIFT 5
/* RPL Bit Fields */
#define UART_RPL_RPL_MASK 0xFFu
#define UART_RPL_RPL_SHIFT 0
#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
/* RPREL Bit Fields */
#define UART_RPREL_RPREL_MASK 0xFFu
#define UART_RPREL_RPREL_SHIFT 0
#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
/* CPW Bit Fields */
#define UART_CPW_CPW_MASK 0xFFu
#define UART_CPW_CPW_SHIFT 0
#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
/* RIDTH Bit Fields */
#define UART_RIDTH_RIDTH_MASK 0xFFu
#define UART_RIDTH_RIDTH_SHIFT 0
#define UART_RIDTH_RIDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDTH_RIDTH_SHIFT))&UART_RIDTH_RIDTH_MASK)
/* RIDTL Bit Fields */
#define UART_RIDTL_RIDTL_MASK 0xFFu
#define UART_RIDTL_RIDTL_SHIFT 0
#define UART_RIDTL_RIDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDTL_RIDTL_SHIFT))&UART_RIDTL_RIDTL_MASK)
/* TIDTH Bit Fields */
#define UART_TIDTH_TIDTH_MASK 0xFFu
#define UART_TIDTH_TIDTH_SHIFT 0
#define UART_TIDTH_TIDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDTH_TIDTH_SHIFT))&UART_TIDTH_TIDTH_MASK)
/* TIDTL Bit Fields */
#define UART_TIDTL_TIDTL_MASK 0xFFu
#define UART_TIDTL_TIDTL_SHIFT 0
#define UART_TIDTL_TIDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDTL_TIDTL_SHIFT))&UART_TIDTL_TIDTL_MASK)
/* RB1TH Bit Fields */
#define UART_RB1TH_RB1TH_MASK 0xFFu
#define UART_RB1TH_RB1TH_SHIFT 0
#define UART_RB1TH_RB1TH(x) (((uint8_t)(((uint8_t)(x))<<UART_RB1TH_RB1TH_SHIFT))&UART_RB1TH_RB1TH_MASK)
/* RB1TL Bit Fields */
#define UART_RB1TL_RB1TL_MASK 0xFFu
#define UART_RB1TL_RB1TL_SHIFT 0
#define UART_RB1TL_RB1TL(x) (((uint8_t)(((uint8_t)(x))<<UART_RB1TL_RB1TL_SHIFT))&UART_RB1TL_RB1TL_MASK)
/* TB1TH Bit Fields */
#define UART_TB1TH_TB1TH_MASK 0xFFu
#define UART_TB1TH_TB1TH_SHIFT 0
#define UART_TB1TH_TB1TH(x) (((uint8_t)(((uint8_t)(x))<<UART_TB1TH_TB1TH_SHIFT))&UART_TB1TH_TB1TH_MASK)
/* TB1TL Bit Fields */
#define UART_TB1TL_TB1TL_MASK 0xFFu
#define UART_TB1TL_TB1TL_SHIFT 0
#define UART_TB1TL_TB1TL(x) (((uint8_t)(((uint8_t)(x))<<UART_TB1TL_TB1TL_SHIFT))&UART_TB1TL_TB1TL_MASK)
/* PROG_REG Bit Fields */
#define UART_PROG_REG_MIN_DMC1_MASK 0xFu
#define UART_PROG_REG_MIN_DMC1_SHIFT 0
#define UART_PROG_REG_MIN_DMC1(x) (((uint8_t)(((uint8_t)(x))<<UART_PROG_REG_MIN_DMC1_SHIFT))&UART_PROG_REG_MIN_DMC1_MASK)
#define UART_PROG_REG_LCV_LEN_MASK 0xF0u
#define UART_PROG_REG_LCV_LEN_SHIFT 4
#define UART_PROG_REG_LCV_LEN(x) (((uint8_t)(((uint8_t)(x))<<UART_PROG_REG_LCV_LEN_SHIFT))&UART_PROG_REG_LCV_LEN_MASK)
/* STATE_REG Bit Fields */
#define UART_STATE_REG_SM_STATE_MASK 0x7u
#define UART_STATE_REG_SM_STATE_SHIFT 0
#define UART_STATE_REG_SM_STATE(x) (((uint8_t)(((uint8_t)(x))<<UART_STATE_REG_SM_STATE_SHIFT))&UART_STATE_REG_SM_STATE_MASK)
#define UART_STATE_REG_TX_STATE_MASK 0x38u
#define UART_STATE_REG_TX_STATE_SHIFT 3
#define UART_STATE_REG_TX_STATE(x) (((uint8_t)(((uint8_t)(x))<<UART_STATE_REG_TX_STATE_SHIFT))&UART_STATE_REG_TX_STATE_MASK)
/*!
* @}
*/ /* end of group UART_Register_Masks */
/* UART - Peripheral instance base addresses */
/** Peripheral UART0 base address */
#define UART0_BASE (0x4006A000u)
/** Peripheral UART0 base pointer */
#define UART0 ((UART_Type *)UART0_BASE)
/** Peripheral UART1 base address */
#define UART1_BASE (0x4006B000u)
/** Peripheral UART1 base pointer */
#define UART1 ((UART_Type *)UART1_BASE)
/** Array initializer of UART peripheral base pointers */
#define UART_BASES { UART0, UART1 }
/*!
* @}
*/ /* end of group UART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- WDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
* @{
*/
/** WDOG - Register Layout Typedef */
typedef struct {
__IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
__IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
__IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
__IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
__IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
__IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
__IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
__IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
__IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
__IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
__IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
__IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
} WDOG_Type;
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/* STCTRLH Bit Fields */
#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
#define WDOG_STCTRLH_WDOGEN_SHIFT 0
#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
#define WDOG_STCTRLH_CLKSRC_SHIFT 1
#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
#define WDOG_STCTRLH_WINEN_MASK 0x8u
#define WDOG_STCTRLH_WINEN_SHIFT 3
#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
#define WDOG_STCTRLH_DBGEN_MASK 0x20u
#define WDOG_STCTRLH_DBGEN_SHIFT 5
#define WDOG_STCTRLH_STOPEN_MASK 0x40u
#define WDOG_STCTRLH_STOPEN_SHIFT 6
#define WDOG_STCTRLH_WAITEN_MASK 0x80u
#define WDOG_STCTRLH_WAITEN_SHIFT 7
#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
#define WDOG_STCTRLH_TESTSEL_SHIFT 11
#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
#define WDOG_STCTRLH_BYTESEL_SHIFT 12
#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
/* STCTRLL Bit Fields */
#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
#define WDOG_STCTRLL_INTFLG_SHIFT 15
/* TOVALH Bit Fields */
#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
/* TOVALL Bit Fields */
#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
#define WDOG_TOVALL_TOVALLOW_SHIFT 0
#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
/* WINH Bit Fields */
#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
#define WDOG_WINH_WINHIGH_SHIFT 0
#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
/* WINL Bit Fields */
#define WDOG_WINL_WINLOW_MASK 0xFFFFu
#define WDOG_WINL_WINLOW_SHIFT 0
#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
/* REFRESH Bit Fields */
#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
/* UNLOCK Bit Fields */
#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
/* TMROUTH Bit Fields */
#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
/* TMROUTL Bit Fields */
#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
/* RSTCNT Bit Fields */
#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
#define WDOG_RSTCNT_RSTCNT_SHIFT 0
#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
/* PRESC Bit Fields */
#define WDOG_PRESC_PRESCVAL_MASK 0x700u
#define WDOG_PRESC_PRESCVAL_SHIFT 8
#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
/*!
* @}
*/ /* end of group WDOG_Register_Masks */
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG base address */
#define WDOG_BASE (0x40052000u)
/** Peripheral WDOG base pointer */
#define WDOG ((WDOG_Type *)WDOG_BASE)
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASES { WDOG }
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma pop
#elif defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- Backward Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
* @{
*/
/* No backward compatibility issues. */
/*!
* @}
*/ /* end of group Backward_Compatibility_Symbols */
#endif /* #if !defined(MKV10Z7_H_) */
/* MKV10Z7.h, eof. */
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/src/emc.c
|
<gh_stars>1-10
/**
******************************************************************************
* @file emc.c
* @author YANDLD
* @version V3.0.0
* @date 2016.5.28
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#include "common.h"
#include "emc.h"
/*! @brief Define the chip numbers for dynamic and static memory devices. */
#define EMC_STATIC_MEMDEV_NUM (4U)
#define EMC_DYNAMIC_MEMDEV_NUM (4U)
#define EMC_ADDRMAP_SHIFT EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT
#define EMC_ADDRMAP_MASK (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK | EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
#define EMC_ADDRMAP(x) (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK)
#define EMC_HZ_ONEMHZ (1000000U)
#define EMC_MILLISECS_ONESEC (1000U)
#define EMC_SDRAM_MODE_CL_SHIFT (4U)
#define EMC_SDRAM_MODE_CL_MASK (0x70U)
#define EMC_HZ_ONEMHZ (1000000U)
#define EMC_REFRESH_CLOCK_PARAM (16U)
#define EMC_SDRAM_WAIT_CYCLES (2000U)
#define EMC_DYNCTL_COLUMNBASE_OFFSET (0U)
#define EMC_DYNCTL_COLUMNBASE_MASK (0x3U)
#define EMC_DYNCTL_COLUMNPLUS_OFFSET (3U)
#define EMC_DYNCTL_COLUMNPLUS_MASK (0x18U)
#define EMC_DYNCTL_BUSWIDTH_MASK (0x80U)
#define EMC_DYNCTL_BUSADDRMAP_MASK (0x20U)
#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU)
#define EMC_SDRAM_BANKCS_BA0_MASK (uint32_t)(0x2000)
#define EMC_SDRAM_BANKCS_BA1_MASK (uint32_t)(0x4000)
#define EMC_SDRAM_BANKCS_BA_MASK (EMC_SDRAM_BANKCS_BA0_MASK | EMC_SDRAM_BANKCS_BA1_MASK)
#define EMC_DIV_ROUND_UP(n, m) (((n) + (m)-1) / (m))
void EMC_Init(void)
{
SYSCON->AHBCLKCTRL[2] |= SYSCON_AHBCLKCTRL_EMC_MASK;
/* Reset the EMC. */
SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK;
SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_EMC_RESET_MASK;
/* EMC clock = core clock / 2. */
SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(1);
SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(0);
/* Set the endian mode to little endian */
EMC->CONFIG = 0;
/* Enable the EMC module with normal memory map mode and normal work mode. */
EMC->CONTROL = EMC_CONTROL_E_MASK;
}
static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus)
{
uint32_t cycles;
cycles = GetClock(kEMCClock) / EMC_HZ_ONEMHZ * timer_Ns;
cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */
/* Decrese according to the plus. */
if (cycles >= plus)
{
cycles = cycles - plus;
}
else
{
cycles = 0;
}
return cycles;
}
static uint32_t EMC_ModeOffset(uint32_t addrMap)
{
uint8_t offset = 0;
uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK;
/* First calculate the column length. */
if (columbase == 0x10)
{
offset = 8;
}
else
{
if (!columbase)
{
offset = 9;
}
else
{
offset = 8;
}
/* Add column length increase check. */
if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 1)
{
offset += 1;
}
else if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 2)
{
offset += 2;
}
else
{
/* To avoid MISRA rule 14.10 error. */
}
}
/* Add Buswidth/16. */
if (addrMap & EMC_DYNCTL_BUSWIDTH_MASK)
{
offset += 2;
}
else
{
offset += 1;
}
/* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */
if (!(addrMap & EMC_DYNCTL_BUSADDRMAP_MASK))
{
if (!(addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK))
{
offset += 1;
}
else
{
offset += 2;
}
}
return offset;
}
void SDRAM_Init(emc_dynamic_timing_config_t *timing, emc_dynamic_chip_config_t *config)
{
uint32_t count;
uint8_t casLatency;
uint32_t addr;
uint32_t offset;
uint32_t data;
/* Setting for dynamic memory controller chip independent configuration. */
EMC->DYNAMIC[0].DYNAMICCONFIG = EMC_DYNAMIC_DYNAMICCONFIG_MD(config->dynamicDevice) | EMC_ADDRMAP(config->devAddrMap);
/* Abstract CAS latency from the sdram mode reigster setting values. */
casLatency = (config->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT;
EMC->DYNAMIC[0].DYNAMICRASCAS = EMC_DYNAMIC_DYNAMICRASCAS_RAS(config->rAS_Nclk) | EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency);
/* Configure the Dynamic Memory controller timing/latency for all chips. */
EMC->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig);
EMC->DYNAMICRP = EMC_CalculateTimerCycles(EMC, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK;
EMC->DYNAMICRAS = EMC_CalculateTimerCycles(EMC, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK;
EMC->DYNAMICSREX = EMC_CalculateTimerCycles(EMC, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK;
EMC->DYNAMICAPR = EMC_CalculateTimerCycles(EMC, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK;
EMC->DYNAMICDAL = EMC_CalculateTimerCycles(EMC, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK;
EMC->DYNAMICWR = EMC_CalculateTimerCycles(EMC, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK;
EMC->DYNAMICRC = EMC_CalculateTimerCycles(EMC, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK;
EMC->DYNAMICRFC = EMC_CalculateTimerCycles(EMC, timing->tRfc_Ns, 1) & EMC_DYNAMICRFC_TRFC_MASK;
EMC->DYNAMICXSR = EMC_CalculateTimerCycles(EMC, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK;
EMC->DYNAMICRRD = EMC_CalculateTimerCycles(EMC, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK;
EMC->DYNAMICMRD = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0) ? timing->tMrd_Nclk - 1 : 0);
/* Initialize the SDRAM.*/
for (count = 0; count < EMC_SDRAM_WAIT_CYCLES; count++)
{
}
/* Step 2. issue nop command. */
EMC->DYNAMICCONTROL = 0x00000183;
for (count = 0; count < EMC_SDRAM_WAIT_CYCLES; count++)
{
}
/* Step 3. issue precharge all command. */
EMC->DYNAMICCONTROL = 0x00000103;
/* Step 4. issue two auto-refresh command. */
EMC->DYNAMICREFRESH = 2;
for (count = 0; count < EMC_SDRAM_WAIT_CYCLES / 2; count++)
{
}
EMC->DYNAMICREFRESH = EMC_CalculateTimerCycles(EMC, timing->refreshPeriod_Nanosec, 0) / EMC_REFRESH_CLOCK_PARAM;
/* Step 5. issue a mode command and set the mode value. */
EMC->DYNAMICCONTROL = 0x00000083;
/* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */
/* Get the shift value first. */
offset = EMC_ModeOffset(config->devAddrMap);
addr = (EMC_DYCS0_BASE | ((uint32_t)(config->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) << offset));
/* Set the right mode setting value. */
data = *(volatile uint32_t *)addr;
data = data;
/* Step 6. issue normal operation command. */
EMC->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */
/* The buffer shall be disabled when do the sdram initialization and enabled after the initialization during normal opeation. */
EMC->DYNAMIC[0].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK;
}
|
yandld/lpc_uart_server
|
mcu_source/Libraries/utilities/chusb/test/usbd_config.h
|
<filename>mcu_source/Libraries/utilities/chusb/test/usbd_config.h
#ifndef __CHLIB_USBD_CONFIG_H_
#define __CHLIB_USBD_CONFIG_H_
/* general USBD configration */
#define EP0_MAX_SIZE (64)
#define USBD_VID (0x0465)
#define USBD_PID (0x622F)
#define MANUFACTURE_STR L"HIPNUC"
#define PRODUCT_STR L"USBTEST"
#define SERIAL_STR L"0123"
#define USBD_DEBUG (0)
/* intf defination */
#define USBD_MSC_IF_IDX (0)
#define USBD_MSC_IF_STR L"MSC"
#define MSD_BUF_SIZE (1024*4)
#define MSD_EP_SIZE (64)
#define USBD_CDC_CIF_IDX (1)
#define USBD_CDC_CIF_STR L"CDC CIF"
#define USBD_CDC_DIF_IDX (2)
#define USBD_CDC_DIF_STR L"CDC_DIF"
#define CDC_EP_SIZE (64)
#define USBD_HID0_IF_IDX (3)
#define USBD_HID0_IF_STR L"HID0"
#define USBD_HID1_IF_IDX (4)
#define USBD_HID1_IF_STR L"HID1"
#define USBD_HID2_IF_IDX (5)
#define USBD_HID2_IF_STR L"CMSIS-DAP"
#define USBD_HID_CUSTOM_REPORT_SIZE (64)
#define USBD_HID_EP_INTERVAL (1)
#define USBD_IF_STR_IDX(IF_NUM) (4 + IF_NUM)
/* ep defination */
#define USBD_HID0_EP_INTIN (3)
#define USBD_HID0_EP_INTOUT (3)
#define USBD_HID1_EP_INTIN (8)
#define USBD_HID1_EP_INTOUT (8)
#define USBD_HID2_EP_INTIN (1)
#define USBD_HID2_EP_INTOUT (1)
#define USBD_CDC_ACM_EP_INTIN (3)
#define USBD_CDC_ACM_EP_BULKIN (4)
#define USBD_CDC_ACM_EP_BULKOUT (4)
#define USBD_MSC_EP_BULKIN (2)
#define USBD_MSC_EP_BULKOUT (2)
#endif
|
yandld/lpc_uart_server
|
mcu_source/Libraries/drivers_lpc/inc/i2c.h
|
<reponame>yandld/lpc_uart_server
/**
******************************************************************************
* @file i2c.h
* @author YANDLD
* @version V3.0.0
* @date 2016.6.2
* @brief www.beyondcore.net http://upcmcu.taobao.com
******************************************************************************
*/
#ifndef __CH_LIB_LPC_I2C_H__
#define __CH_LIB_LPC_I2C_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#define HW_I2C0 (0)
#define HW_I2C1 (1)
#define HW_I2C2 (2)
#define HW_I2C3 (3)
#define HW_I2C4 (4)
#define HW_I2C5 (5)
#define HW_I2C6 (6)
#define HW_I2C7 (7)
#define HW_I2C8 (8)
typedef enum
{
kI2C_SlavePending,
kI2C_SlaveDeselect,
}I2C_Int_t;
void I2C_SetBaudRate(uint32_t instance, uint32_t baud);
uint32_t I2C_Init(uint32_t MAP, uint32_t baudrate);
uint32_t I2C_BurstRead(uint32_t instance, uint8_t addr, uint32_t regAddr, uint32_t regLen, uint8_t* buf, uint32_t len);
uint32_t I2C_BurstWrite(uint32_t instance ,uint8_t addr, uint32_t regAddr, uint32_t regLen, uint8_t *buf, uint32_t len);
uint32_t I2C_ReadReg(uint32_t instance, uint8_t addr, uint8_t regAddr, uint8_t* buf);
uint32_t I2C_WriteReg(uint32_t instance, uint8_t addr, uint8_t regAddr, uint8_t buf);
uint32_t SCCB_ReadReg(uint32_t instance, uint8_t addr, uint8_t regAddr, uint8_t* buf);
uint32_t SCCB_WriteReg(uint32_t instance, uint8_t addr, uint8_t regAddr, uint8_t buf);
void I2C_Scan(uint32_t instance);
uint32_t I2C_SetSalveAddr(uint32_t instance, uint8_t slot, uint8_t addr);
uint32_t I2C_Write(uint32_t instance, uint8_t addr, uint8_t *buf, uint32_t len);
uint32_t I2C_Read(uint32_t instance, uint8_t addr, uint8_t* buf, uint32_t len);
uint32_t I2C_SetIntMode(uint32_t instance, I2C_Int_t val);
#endif
|
yandld/lpc_uart_server
|
mcu_source/Project/Internal/lpc54018_uart_server/src/uart_bridge.h
|
#ifndef __UART_BRIDGE_H_
#define __UART_BRIDGE_H_
#include <rtthread.h>
#include "rtdevice.h"
#include <dma.h>
typedef struct
{
uint32_t total_out;
uint32_t total_out_speed;
uint32_t total_in;
uint32_t total_in_speed;
}stat_t;
typedef struct
{
struct rt_ringbuffer trb; /* tx ring buffer instance */
uint8_t trb_buf[512]; /* tx ring buffer */
uint8_t tx_idle; /* if uart tx is idle */
int tx_dma_complete_timeout;
struct rt_ringbuffer rrb; /* rx ring buffer instance */
uint8_t rrb_buf[253*8]; /* rx ring buffer */
DMA_ChlSetup_t tx_setup;
DMA_ChlSetup_t rx_setup;
uint8_t tbuf[512]; /* tmp buffer for serial tx to send */
uint8_t rbuf[256]; /* tmp buffer for tx to send */
uint8_t rdma_buf[1024]; /* tmp buffer for rx to received */
uint32_t tx_sum;
uint32_t rx_sum;
uint32_t rx_dma_sum;
}uart_bridge_t;
uint32_t bridge_uart_send(uint8_t chl, uint8_t *buf, uint32_t size);
uint32_t bridge_uart_tx_get_free(uint8_t ch);
uint32_t bridge_uart_rx_get_free(uint8_t ch);
void bridge_uart_usb_data_in_ready(void);
void bridge_uart_usb_ctl_in_ready(void);
#endif
|
TozyZuo/DingTalkPlugin
|
Pods/DingDingPod/Headers/DDSettingHeader.h
|
<gh_stars>1-10
//
// DDSettingHeader.h
// DingTalk
//
// Created by TozyZuo on 2018/3/9.
// Copyright © 2018年 TozyZuo. All rights reserved.
//
#ifndef DDSettingHeader_h
#define DDSettingHeader_h
@interface DTCellItem : NSObject
@property(retain, nonatomic) UIFont *titleFont;
@property(retain, nonatomic) UIColor *titleColor;
@property( copy , nonatomic) NSString *title;
@property(nonatomic) _Bool showIndicator;
@property(copy, nonatomic) void(^selectedBlock)(DTCellItem *item, UIView *cell);
@end
@interface DTSectionItem : NSObject
@property(copy, nonatomic) NSArray<DTCellItem *> *dataSource;
+ (id)itemWithSectionHeader:(id)arg1 sectionFooter:(id)arg2;
@end
@interface DTTableViewDataSource : NSObject
@property(copy, nonatomic) NSArray<DTSectionItem *> *tableViewDataSource;
@end
@interface DTTableViewHandler : NSObject
@property(retain, nonatomic) DTTableViewDataSource *dataSource;
@end
@interface DTSettingListViewController : UITableViewController
@property(retain, nonatomic) DTTableViewHandler *tableViewHandler;
- (void)tableViewReloadData;
@end
#endif /* DDSettingHeader_h */
|
TozyZuo/DingTalkPlugin
|
DingTalkDylib/DingTalkDylib.h
|
<filename>DingTalkDylib/DingTalkDylib.h
// weibo: http://weibo.com/xiaoqing28
// blog: http://www.alonemonkey.com
//
// DingTalkDylib.h
// DingTalkDylib
//
// Created by TozyZuo on 2018/3/1.
// Copyright (c) 2018年 TozyZuo. All rights reserved.
//
#import <Foundation/Foundation.h>
|
coleworld87/grpc
|
src/core/ext/upb-generated/envoy/api/v2/scoped_route.upb.c
|
<filename>src/core/ext/upb-generated/envoy/api/v2/scoped_route.upb.c
/* This file was generated by upbc (the upb compiler) from the input
* file:
*
* envoy/api/v2/scoped_route.proto
*
* Do not edit -- your changes will be discarded when the file is
* regenerated. */
#include <stddef.h>
#include "upb/msg.h"
#include "envoy/api/v2/scoped_route.upb.h"
#include "udpa/annotations/migrate.upb.h"
#include "validate/validate.upb.h"
#include "upb/port_def.inc"
static const upb_msglayout *const envoy_api_v2_ScopedRouteConfiguration_submsgs[1] = {
&envoy_api_v2_ScopedRouteConfiguration_Key_msginit,
};
static const upb_msglayout_field envoy_api_v2_ScopedRouteConfiguration__fields[3] = {
{1, UPB_SIZE(0, 0), 0, 0, 9, 1},
{2, UPB_SIZE(8, 16), 0, 0, 9, 1},
{3, UPB_SIZE(16, 32), 0, 0, 11, 1},
};
const upb_msglayout envoy_api_v2_ScopedRouteConfiguration_msginit = {
&envoy_api_v2_ScopedRouteConfiguration_submsgs[0],
&envoy_api_v2_ScopedRouteConfiguration__fields[0],
UPB_SIZE(24, 48), 3, false,
};
static const upb_msglayout *const envoy_api_v2_ScopedRouteConfiguration_Key_submsgs[1] = {
&envoy_api_v2_ScopedRouteConfiguration_Key_Fragment_msginit,
};
static const upb_msglayout_field envoy_api_v2_ScopedRouteConfiguration_Key__fields[1] = {
{1, UPB_SIZE(0, 0), 0, 0, 11, 3},
};
const upb_msglayout envoy_api_v2_ScopedRouteConfiguration_Key_msginit = {
&envoy_api_v2_ScopedRouteConfiguration_Key_submsgs[0],
&envoy_api_v2_ScopedRouteConfiguration_Key__fields[0],
UPB_SIZE(4, 8), 1, false,
};
static const upb_msglayout_field envoy_api_v2_ScopedRouteConfiguration_Key_Fragment__fields[1] = {
{1, UPB_SIZE(0, 0), UPB_SIZE(-9, -17), 0, 9, 1},
};
const upb_msglayout envoy_api_v2_ScopedRouteConfiguration_Key_Fragment_msginit = {
NULL,
&envoy_api_v2_ScopedRouteConfiguration_Key_Fragment__fields[0],
UPB_SIZE(16, 32), 1, false,
};
#include "upb/port_undef.inc"
|
coleworld87/grpc
|
src/core/ext/upb-generated/envoy/api/v2/srds.upb.h
|
<filename>src/core/ext/upb-generated/envoy/api/v2/srds.upb.h
/* This file was generated by upbc (the upb compiler) from the input
* file:
*
* envoy/api/v2/srds.proto
*
* Do not edit -- your changes will be discarded when the file is
* regenerated. */
#ifndef ENVOY_API_V2_SRDS_PROTO_UPB_H_
#define ENVOY_API_V2_SRDS_PROTO_UPB_H_
#include "upb/generated_util.h"
#include "upb/msg.h"
#include "upb/decode.h"
#include "upb/encode.h"
/* Public Imports. */
#include "envoy/api/v2/scoped_route.upb.h"
#include "upb/port_def.inc"
#ifdef __cplusplus
extern "C" {
#endif
struct envoy_api_v2_SrdsDummy;
typedef struct envoy_api_v2_SrdsDummy envoy_api_v2_SrdsDummy;
extern const upb_msglayout envoy_api_v2_SrdsDummy_msginit;
/* envoy.api.v2.SrdsDummy */
UPB_INLINE envoy_api_v2_SrdsDummy *envoy_api_v2_SrdsDummy_new(upb_arena *arena) {
return (envoy_api_v2_SrdsDummy *)upb_msg_new(&envoy_api_v2_SrdsDummy_msginit, arena);
}
UPB_INLINE envoy_api_v2_SrdsDummy *envoy_api_v2_SrdsDummy_parse(const char *buf, size_t size,
upb_arena *arena) {
envoy_api_v2_SrdsDummy *ret = envoy_api_v2_SrdsDummy_new(arena);
return (ret && upb_decode(buf, size, ret, &envoy_api_v2_SrdsDummy_msginit, arena)) ? ret : NULL;
}
UPB_INLINE char *envoy_api_v2_SrdsDummy_serialize(const envoy_api_v2_SrdsDummy *msg, upb_arena *arena, size_t *len) {
return upb_encode(msg, &envoy_api_v2_SrdsDummy_msginit, arena, len);
}
#ifdef __cplusplus
} /* extern "C" */
#endif
#include "upb/port_undef.inc"
#endif /* ENVOY_API_V2_SRDS_PROTO_UPB_H_ */
|
coleworld87/grpc
|
src/core/ext/filters/client_channel/server_address.h
|
<filename>src/core/ext/filters/client_channel/server_address.h
/*
*
* Copyright 2018 gRPC authors.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef GRPC_CORE_EXT_FILTERS_CLIENT_CHANNEL_SERVER_ADDRESS_H
#define GRPC_CORE_EXT_FILTERS_CLIENT_CHANNEL_SERVER_ADDRESS_H
#include <grpc/support/port_platform.h>
#include "src/core/lib/channel/channel_args.h"
#include "src/core/lib/gprpp/inlined_vector.h"
#include "src/core/lib/iomgr/resolve_address.h"
namespace grpc_core {
//
// ServerAddress
//
// A server address is a grpc_resolved_address with an associated set of
// channel args. Any args present here will be merged into the channel
// args when a subchannel is created for this address.
class ServerAddress {
public:
// Takes ownership of args.
ServerAddress(const grpc_resolved_address& address, grpc_channel_args* args);
ServerAddress(const void* address, size_t address_len,
grpc_channel_args* args);
~ServerAddress() { grpc_channel_args_destroy(args_); }
// Copyable.
ServerAddress(const ServerAddress& other)
: address_(other.address_), args_(grpc_channel_args_copy(other.args_)) {}
ServerAddress& operator=(const ServerAddress& other) {
address_ = other.address_;
grpc_channel_args_destroy(args_);
args_ = grpc_channel_args_copy(other.args_);
return *this;
}
// Movable.
ServerAddress(ServerAddress&& other)
: address_(other.address_), args_(other.args_) {
other.args_ = nullptr;
}
ServerAddress& operator=(ServerAddress&& other) {
address_ = other.address_;
grpc_channel_args_destroy(args_);
args_ = other.args_;
other.args_ = nullptr;
return *this;
}
bool operator==(const ServerAddress& other) const { return Cmp(other) == 0; }
int Cmp(const ServerAddress& other) const;
const grpc_resolved_address& address() const { return address_; }
const grpc_channel_args* args() const { return args_; }
private:
grpc_resolved_address address_;
grpc_channel_args* args_;
};
//
// ServerAddressList
//
typedef InlinedVector<ServerAddress, 1> ServerAddressList;
} // namespace grpc_core
#endif /* GRPC_CORE_EXT_FILTERS_CLIENT_CHANNEL_SERVER_ADDRESS_H */
|
coleworld87/grpc
|
src/core/ext/upb-generated/envoy/type/semantic_version.upb.h
|
/* This file was generated by upbc (the upb compiler) from the input
* file:
*
* envoy/type/semantic_version.proto
*
* Do not edit -- your changes will be discarded when the file is
* regenerated. */
#ifndef ENVOY_TYPE_SEMANTIC_VERSION_PROTO_UPB_H_
#define ENVOY_TYPE_SEMANTIC_VERSION_PROTO_UPB_H_
#include "upb/generated_util.h"
#include "upb/msg.h"
#include "upb/decode.h"
#include "upb/encode.h"
#include "upb/port_def.inc"
#ifdef __cplusplus
extern "C" {
#endif
struct envoy_type_SemanticVersion;
typedef struct envoy_type_SemanticVersion envoy_type_SemanticVersion;
extern const upb_msglayout envoy_type_SemanticVersion_msginit;
/* envoy.type.SemanticVersion */
UPB_INLINE envoy_type_SemanticVersion *envoy_type_SemanticVersion_new(upb_arena *arena) {
return (envoy_type_SemanticVersion *)upb_msg_new(&envoy_type_SemanticVersion_msginit, arena);
}
UPB_INLINE envoy_type_SemanticVersion *envoy_type_SemanticVersion_parse(const char *buf, size_t size,
upb_arena *arena) {
envoy_type_SemanticVersion *ret = envoy_type_SemanticVersion_new(arena);
return (ret && upb_decode(buf, size, ret, &envoy_type_SemanticVersion_msginit, arena)) ? ret : NULL;
}
UPB_INLINE char *envoy_type_SemanticVersion_serialize(const envoy_type_SemanticVersion *msg, upb_arena *arena, size_t *len) {
return upb_encode(msg, &envoy_type_SemanticVersion_msginit, arena, len);
}
UPB_INLINE uint32_t envoy_type_SemanticVersion_major_number(const envoy_type_SemanticVersion *msg) { return UPB_FIELD_AT(msg, uint32_t, UPB_SIZE(0, 0)); }
UPB_INLINE uint32_t envoy_type_SemanticVersion_minor_number(const envoy_type_SemanticVersion *msg) { return UPB_FIELD_AT(msg, uint32_t, UPB_SIZE(4, 4)); }
UPB_INLINE uint32_t envoy_type_SemanticVersion_patch(const envoy_type_SemanticVersion *msg) { return UPB_FIELD_AT(msg, uint32_t, UPB_SIZE(8, 8)); }
UPB_INLINE void envoy_type_SemanticVersion_set_major_number(envoy_type_SemanticVersion *msg, uint32_t value) {
UPB_FIELD_AT(msg, uint32_t, UPB_SIZE(0, 0)) = value;
}
UPB_INLINE void envoy_type_SemanticVersion_set_minor_number(envoy_type_SemanticVersion *msg, uint32_t value) {
UPB_FIELD_AT(msg, uint32_t, UPB_SIZE(4, 4)) = value;
}
UPB_INLINE void envoy_type_SemanticVersion_set_patch(envoy_type_SemanticVersion *msg, uint32_t value) {
UPB_FIELD_AT(msg, uint32_t, UPB_SIZE(8, 8)) = value;
}
#ifdef __cplusplus
} /* extern "C" */
#endif
#include "upb/port_undef.inc"
#endif /* ENVOY_TYPE_SEMANTIC_VERSION_PROTO_UPB_H_ */
|
coleworld87/grpc
|
src/core/ext/upb-generated/envoy/api/v2/lds.upb.h
|
/* This file was generated by upbc (the upb compiler) from the input
* file:
*
* envoy/api/v2/lds.proto
*
* Do not edit -- your changes will be discarded when the file is
* regenerated. */
#ifndef ENVOY_API_V2_LDS_PROTO_UPB_H_
#define ENVOY_API_V2_LDS_PROTO_UPB_H_
#include "upb/generated_util.h"
#include "upb/msg.h"
#include "upb/decode.h"
#include "upb/encode.h"
/* Public Imports. */
#include "envoy/api/v2/listener.upb.h"
#include "upb/port_def.inc"
#ifdef __cplusplus
extern "C" {
#endif
struct envoy_api_v2_LdsDummy;
typedef struct envoy_api_v2_LdsDummy envoy_api_v2_LdsDummy;
extern const upb_msglayout envoy_api_v2_LdsDummy_msginit;
/* envoy.api.v2.LdsDummy */
UPB_INLINE envoy_api_v2_LdsDummy *envoy_api_v2_LdsDummy_new(upb_arena *arena) {
return (envoy_api_v2_LdsDummy *)upb_msg_new(&envoy_api_v2_LdsDummy_msginit, arena);
}
UPB_INLINE envoy_api_v2_LdsDummy *envoy_api_v2_LdsDummy_parse(const char *buf, size_t size,
upb_arena *arena) {
envoy_api_v2_LdsDummy *ret = envoy_api_v2_LdsDummy_new(arena);
return (ret && upb_decode(buf, size, ret, &envoy_api_v2_LdsDummy_msginit, arena)) ? ret : NULL;
}
UPB_INLINE char *envoy_api_v2_LdsDummy_serialize(const envoy_api_v2_LdsDummy *msg, upb_arena *arena, size_t *len) {
return upb_encode(msg, &envoy_api_v2_LdsDummy_msginit, arena, len);
}
#ifdef __cplusplus
} /* extern "C" */
#endif
#include "upb/port_undef.inc"
#endif /* ENVOY_API_V2_LDS_PROTO_UPB_H_ */
|
coleworld87/grpc
|
src/core/ext/upb-generated/envoy/api/v2/endpoint.upb.c
|
<gh_stars>1-10
/* This file was generated by upbc (the upb compiler) from the input
* file:
*
* envoy/api/v2/endpoint.proto
*
* Do not edit -- your changes will be discarded when the file is
* regenerated. */
#include <stddef.h>
#include "upb/msg.h"
#include "envoy/api/v2/endpoint.upb.h"
#include "envoy/api/v2/endpoint/endpoint_components.upb.h"
#include "envoy/type/percent.upb.h"
#include "google/api/annotations.upb.h"
#include "google/protobuf/duration.upb.h"
#include "google/protobuf/wrappers.upb.h"
#include "udpa/annotations/migrate.upb.h"
#include "validate/validate.upb.h"
#include "upb/port_def.inc"
static const upb_msglayout *const envoy_api_v2_ClusterLoadAssignment_submsgs[3] = {
&envoy_api_v2_ClusterLoadAssignment_NamedEndpointsEntry_msginit,
&envoy_api_v2_ClusterLoadAssignment_Policy_msginit,
&envoy_api_v2_endpoint_LocalityLbEndpoints_msginit,
};
static const upb_msglayout_field envoy_api_v2_ClusterLoadAssignment__fields[4] = {
{1, UPB_SIZE(0, 0), 0, 0, 9, 1},
{2, UPB_SIZE(12, 24), 0, 2, 11, 3},
{4, UPB_SIZE(8, 16), 0, 1, 11, 1},
{5, UPB_SIZE(16, 32), 0, 0, 11, 3},
};
const upb_msglayout envoy_api_v2_ClusterLoadAssignment_msginit = {
&envoy_api_v2_ClusterLoadAssignment_submsgs[0],
&envoy_api_v2_ClusterLoadAssignment__fields[0],
UPB_SIZE(24, 48), 4, false,
};
static const upb_msglayout *const envoy_api_v2_ClusterLoadAssignment_Policy_submsgs[3] = {
&envoy_api_v2_ClusterLoadAssignment_Policy_DropOverload_msginit,
&google_protobuf_Duration_msginit,
&google_protobuf_UInt32Value_msginit,
};
static const upb_msglayout_field envoy_api_v2_ClusterLoadAssignment_Policy__fields[4] = {
{2, UPB_SIZE(12, 24), 0, 0, 11, 3},
{3, UPB_SIZE(4, 8), 0, 2, 11, 1},
{4, UPB_SIZE(8, 16), 0, 1, 11, 1},
{5, UPB_SIZE(0, 0), 0, 0, 8, 1},
};
const upb_msglayout envoy_api_v2_ClusterLoadAssignment_Policy_msginit = {
&envoy_api_v2_ClusterLoadAssignment_Policy_submsgs[0],
&envoy_api_v2_ClusterLoadAssignment_Policy__fields[0],
UPB_SIZE(16, 32), 4, false,
};
static const upb_msglayout *const envoy_api_v2_ClusterLoadAssignment_Policy_DropOverload_submsgs[1] = {
&envoy_type_FractionalPercent_msginit,
};
static const upb_msglayout_field envoy_api_v2_ClusterLoadAssignment_Policy_DropOverload__fields[2] = {
{1, UPB_SIZE(0, 0), 0, 0, 9, 1},
{2, UPB_SIZE(8, 16), 0, 0, 11, 1},
};
const upb_msglayout envoy_api_v2_ClusterLoadAssignment_Policy_DropOverload_msginit = {
&envoy_api_v2_ClusterLoadAssignment_Policy_DropOverload_submsgs[0],
&envoy_api_v2_ClusterLoadAssignment_Policy_DropOverload__fields[0],
UPB_SIZE(16, 32), 2, false,
};
static const upb_msglayout *const envoy_api_v2_ClusterLoadAssignment_NamedEndpointsEntry_submsgs[1] = {
&envoy_api_v2_endpoint_Endpoint_msginit,
};
static const upb_msglayout_field envoy_api_v2_ClusterLoadAssignment_NamedEndpointsEntry__fields[2] = {
{1, UPB_SIZE(0, 0), 0, 0, 9, 1},
{2, UPB_SIZE(8, 16), 0, 0, 11, 1},
};
const upb_msglayout envoy_api_v2_ClusterLoadAssignment_NamedEndpointsEntry_msginit = {
&envoy_api_v2_ClusterLoadAssignment_NamedEndpointsEntry_submsgs[0],
&envoy_api_v2_ClusterLoadAssignment_NamedEndpointsEntry__fields[0],
UPB_SIZE(16, 32), 2, false,
};
#include "upb/port_undef.inc"
|
coleworld87/grpc
|
src/core/ext/upb-generated/envoy/api/v2/listener.upb.h
|
<reponame>coleworld87/grpc
/* This file was generated by upbc (the upb compiler) from the input
* file:
*
* envoy/api/v2/listener.proto
*
* Do not edit -- your changes will be discarded when the file is
* regenerated. */
#ifndef ENVOY_API_V2_LISTENER_PROTO_UPB_H_
#define ENVOY_API_V2_LISTENER_PROTO_UPB_H_
#include "upb/generated_util.h"
#include "upb/msg.h"
#include "upb/decode.h"
#include "upb/encode.h"
#include "upb/port_def.inc"
#ifdef __cplusplus
extern "C" {
#endif
struct envoy_api_v2_Listener;
struct envoy_api_v2_Listener_DeprecatedV1;
struct envoy_api_v2_Listener_ConnectionBalanceConfig;
struct envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance;
typedef struct envoy_api_v2_Listener envoy_api_v2_Listener;
typedef struct envoy_api_v2_Listener_DeprecatedV1 envoy_api_v2_Listener_DeprecatedV1;
typedef struct envoy_api_v2_Listener_ConnectionBalanceConfig envoy_api_v2_Listener_ConnectionBalanceConfig;
typedef struct envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance;
extern const upb_msglayout envoy_api_v2_Listener_msginit;
extern const upb_msglayout envoy_api_v2_Listener_DeprecatedV1_msginit;
extern const upb_msglayout envoy_api_v2_Listener_ConnectionBalanceConfig_msginit;
extern const upb_msglayout envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_msginit;
struct envoy_api_v2_core_Address;
struct envoy_api_v2_core_Metadata;
struct envoy_api_v2_core_SocketOption;
struct envoy_api_v2_listener_FilterChain;
struct envoy_api_v2_listener_ListenerFilter;
struct envoy_api_v2_listener_UdpListenerConfig;
struct envoy_config_listener_v2_ApiListener;
struct google_protobuf_BoolValue;
struct google_protobuf_Duration;
struct google_protobuf_UInt32Value;
extern const upb_msglayout envoy_api_v2_core_Address_msginit;
extern const upb_msglayout envoy_api_v2_core_Metadata_msginit;
extern const upb_msglayout envoy_api_v2_core_SocketOption_msginit;
extern const upb_msglayout envoy_api_v2_listener_FilterChain_msginit;
extern const upb_msglayout envoy_api_v2_listener_ListenerFilter_msginit;
extern const upb_msglayout envoy_api_v2_listener_UdpListenerConfig_msginit;
extern const upb_msglayout envoy_config_listener_v2_ApiListener_msginit;
extern const upb_msglayout google_protobuf_BoolValue_msginit;
extern const upb_msglayout google_protobuf_Duration_msginit;
extern const upb_msglayout google_protobuf_UInt32Value_msginit;
typedef enum {
envoy_api_v2_Listener_DEFAULT = 0,
envoy_api_v2_Listener_MODIFY_ONLY = 1
} envoy_api_v2_Listener_DrainType;
/* envoy.api.v2.Listener */
UPB_INLINE envoy_api_v2_Listener *envoy_api_v2_Listener_new(upb_arena *arena) {
return (envoy_api_v2_Listener *)upb_msg_new(&envoy_api_v2_Listener_msginit, arena);
}
UPB_INLINE envoy_api_v2_Listener *envoy_api_v2_Listener_parse(const char *buf, size_t size,
upb_arena *arena) {
envoy_api_v2_Listener *ret = envoy_api_v2_Listener_new(arena);
return (ret && upb_decode(buf, size, ret, &envoy_api_v2_Listener_msginit, arena)) ? ret : NULL;
}
UPB_INLINE char *envoy_api_v2_Listener_serialize(const envoy_api_v2_Listener *msg, upb_arena *arena, size_t *len) {
return upb_encode(msg, &envoy_api_v2_Listener_msginit, arena, len);
}
UPB_INLINE upb_strview envoy_api_v2_Listener_name(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, upb_strview, UPB_SIZE(20, 24)); }
UPB_INLINE const struct envoy_api_v2_core_Address* envoy_api_v2_Listener_address(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct envoy_api_v2_core_Address*, UPB_SIZE(28, 40)); }
UPB_INLINE const struct envoy_api_v2_listener_FilterChain* const* envoy_api_v2_Listener_filter_chains(const envoy_api_v2_Listener *msg, size_t *len) { return (const struct envoy_api_v2_listener_FilterChain* const*)_upb_array_accessor(msg, UPB_SIZE(76, 136), len); }
UPB_INLINE const struct google_protobuf_BoolValue* envoy_api_v2_Listener_use_original_dst(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct google_protobuf_BoolValue*, UPB_SIZE(32, 48)); }
UPB_INLINE const struct google_protobuf_UInt32Value* envoy_api_v2_Listener_per_connection_buffer_limit_bytes(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct google_protobuf_UInt32Value*, UPB_SIZE(36, 56)); }
UPB_INLINE const struct envoy_api_v2_core_Metadata* envoy_api_v2_Listener_metadata(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct envoy_api_v2_core_Metadata*, UPB_SIZE(40, 64)); }
UPB_INLINE const envoy_api_v2_Listener_DeprecatedV1* envoy_api_v2_Listener_deprecated_v1(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const envoy_api_v2_Listener_DeprecatedV1*, UPB_SIZE(44, 72)); }
UPB_INLINE int32_t envoy_api_v2_Listener_drain_type(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, int32_t, UPB_SIZE(0, 0)); }
UPB_INLINE const struct envoy_api_v2_listener_ListenerFilter* const* envoy_api_v2_Listener_listener_filters(const envoy_api_v2_Listener *msg, size_t *len) { return (const struct envoy_api_v2_listener_ListenerFilter* const*)_upb_array_accessor(msg, UPB_SIZE(80, 144), len); }
UPB_INLINE const struct google_protobuf_BoolValue* envoy_api_v2_Listener_transparent(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct google_protobuf_BoolValue*, UPB_SIZE(48, 80)); }
UPB_INLINE const struct google_protobuf_BoolValue* envoy_api_v2_Listener_freebind(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct google_protobuf_BoolValue*, UPB_SIZE(52, 88)); }
UPB_INLINE const struct google_protobuf_UInt32Value* envoy_api_v2_Listener_tcp_fast_open_queue_length(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct google_protobuf_UInt32Value*, UPB_SIZE(56, 96)); }
UPB_INLINE const struct envoy_api_v2_core_SocketOption* const* envoy_api_v2_Listener_socket_options(const envoy_api_v2_Listener *msg, size_t *len) { return (const struct envoy_api_v2_core_SocketOption* const*)_upb_array_accessor(msg, UPB_SIZE(84, 152), len); }
UPB_INLINE const struct google_protobuf_Duration* envoy_api_v2_Listener_listener_filters_timeout(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct google_protobuf_Duration*, UPB_SIZE(60, 104)); }
UPB_INLINE int32_t envoy_api_v2_Listener_traffic_direction(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, int32_t, UPB_SIZE(8, 8)); }
UPB_INLINE bool envoy_api_v2_Listener_continue_on_listener_filters_timeout(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, bool, UPB_SIZE(16, 16)); }
UPB_INLINE const struct envoy_api_v2_listener_UdpListenerConfig* envoy_api_v2_Listener_udp_listener_config(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct envoy_api_v2_listener_UdpListenerConfig*, UPB_SIZE(64, 112)); }
UPB_INLINE const struct envoy_config_listener_v2_ApiListener* envoy_api_v2_Listener_api_listener(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const struct envoy_config_listener_v2_ApiListener*, UPB_SIZE(68, 120)); }
UPB_INLINE const envoy_api_v2_Listener_ConnectionBalanceConfig* envoy_api_v2_Listener_connection_balance_config(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, const envoy_api_v2_Listener_ConnectionBalanceConfig*, UPB_SIZE(72, 128)); }
UPB_INLINE bool envoy_api_v2_Listener_reuse_port(const envoy_api_v2_Listener *msg) { return UPB_FIELD_AT(msg, bool, UPB_SIZE(17, 17)); }
UPB_INLINE void envoy_api_v2_Listener_set_name(envoy_api_v2_Listener *msg, upb_strview value) {
UPB_FIELD_AT(msg, upb_strview, UPB_SIZE(20, 24)) = value;
}
UPB_INLINE void envoy_api_v2_Listener_set_address(envoy_api_v2_Listener *msg, struct envoy_api_v2_core_Address* value) {
UPB_FIELD_AT(msg, struct envoy_api_v2_core_Address*, UPB_SIZE(28, 40)) = value;
}
UPB_INLINE struct envoy_api_v2_core_Address* envoy_api_v2_Listener_mutable_address(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_api_v2_core_Address* sub = (struct envoy_api_v2_core_Address*)envoy_api_v2_Listener_address(msg);
if (sub == NULL) {
sub = (struct envoy_api_v2_core_Address*)upb_msg_new(&envoy_api_v2_core_Address_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_address(msg, sub);
}
return sub;
}
UPB_INLINE struct envoy_api_v2_listener_FilterChain** envoy_api_v2_Listener_mutable_filter_chains(envoy_api_v2_Listener *msg, size_t *len) {
return (struct envoy_api_v2_listener_FilterChain**)_upb_array_mutable_accessor(msg, UPB_SIZE(76, 136), len);
}
UPB_INLINE struct envoy_api_v2_listener_FilterChain** envoy_api_v2_Listener_resize_filter_chains(envoy_api_v2_Listener *msg, size_t len, upb_arena *arena) {
return (struct envoy_api_v2_listener_FilterChain**)_upb_array_resize_accessor(msg, UPB_SIZE(76, 136), len, UPB_SIZE(4, 8), UPB_TYPE_MESSAGE, arena);
}
UPB_INLINE struct envoy_api_v2_listener_FilterChain* envoy_api_v2_Listener_add_filter_chains(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_api_v2_listener_FilterChain* sub = (struct envoy_api_v2_listener_FilterChain*)upb_msg_new(&envoy_api_v2_listener_FilterChain_msginit, arena);
bool ok = _upb_array_append_accessor(
msg, UPB_SIZE(76, 136), UPB_SIZE(4, 8), UPB_TYPE_MESSAGE, &sub, arena);
if (!ok) return NULL;
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_use_original_dst(envoy_api_v2_Listener *msg, struct google_protobuf_BoolValue* value) {
UPB_FIELD_AT(msg, struct google_protobuf_BoolValue*, UPB_SIZE(32, 48)) = value;
}
UPB_INLINE struct google_protobuf_BoolValue* envoy_api_v2_Listener_mutable_use_original_dst(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct google_protobuf_BoolValue* sub = (struct google_protobuf_BoolValue*)envoy_api_v2_Listener_use_original_dst(msg);
if (sub == NULL) {
sub = (struct google_protobuf_BoolValue*)upb_msg_new(&google_protobuf_BoolValue_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_use_original_dst(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_per_connection_buffer_limit_bytes(envoy_api_v2_Listener *msg, struct google_protobuf_UInt32Value* value) {
UPB_FIELD_AT(msg, struct google_protobuf_UInt32Value*, UPB_SIZE(36, 56)) = value;
}
UPB_INLINE struct google_protobuf_UInt32Value* envoy_api_v2_Listener_mutable_per_connection_buffer_limit_bytes(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct google_protobuf_UInt32Value* sub = (struct google_protobuf_UInt32Value*)envoy_api_v2_Listener_per_connection_buffer_limit_bytes(msg);
if (sub == NULL) {
sub = (struct google_protobuf_UInt32Value*)upb_msg_new(&google_protobuf_UInt32Value_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_per_connection_buffer_limit_bytes(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_metadata(envoy_api_v2_Listener *msg, struct envoy_api_v2_core_Metadata* value) {
UPB_FIELD_AT(msg, struct envoy_api_v2_core_Metadata*, UPB_SIZE(40, 64)) = value;
}
UPB_INLINE struct envoy_api_v2_core_Metadata* envoy_api_v2_Listener_mutable_metadata(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_api_v2_core_Metadata* sub = (struct envoy_api_v2_core_Metadata*)envoy_api_v2_Listener_metadata(msg);
if (sub == NULL) {
sub = (struct envoy_api_v2_core_Metadata*)upb_msg_new(&envoy_api_v2_core_Metadata_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_metadata(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_deprecated_v1(envoy_api_v2_Listener *msg, envoy_api_v2_Listener_DeprecatedV1* value) {
UPB_FIELD_AT(msg, envoy_api_v2_Listener_DeprecatedV1*, UPB_SIZE(44, 72)) = value;
}
UPB_INLINE struct envoy_api_v2_Listener_DeprecatedV1* envoy_api_v2_Listener_mutable_deprecated_v1(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_api_v2_Listener_DeprecatedV1* sub = (struct envoy_api_v2_Listener_DeprecatedV1*)envoy_api_v2_Listener_deprecated_v1(msg);
if (sub == NULL) {
sub = (struct envoy_api_v2_Listener_DeprecatedV1*)upb_msg_new(&envoy_api_v2_Listener_DeprecatedV1_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_deprecated_v1(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_drain_type(envoy_api_v2_Listener *msg, int32_t value) {
UPB_FIELD_AT(msg, int32_t, UPB_SIZE(0, 0)) = value;
}
UPB_INLINE struct envoy_api_v2_listener_ListenerFilter** envoy_api_v2_Listener_mutable_listener_filters(envoy_api_v2_Listener *msg, size_t *len) {
return (struct envoy_api_v2_listener_ListenerFilter**)_upb_array_mutable_accessor(msg, UPB_SIZE(80, 144), len);
}
UPB_INLINE struct envoy_api_v2_listener_ListenerFilter** envoy_api_v2_Listener_resize_listener_filters(envoy_api_v2_Listener *msg, size_t len, upb_arena *arena) {
return (struct envoy_api_v2_listener_ListenerFilter**)_upb_array_resize_accessor(msg, UPB_SIZE(80, 144), len, UPB_SIZE(4, 8), UPB_TYPE_MESSAGE, arena);
}
UPB_INLINE struct envoy_api_v2_listener_ListenerFilter* envoy_api_v2_Listener_add_listener_filters(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_api_v2_listener_ListenerFilter* sub = (struct envoy_api_v2_listener_ListenerFilter*)upb_msg_new(&envoy_api_v2_listener_ListenerFilter_msginit, arena);
bool ok = _upb_array_append_accessor(
msg, UPB_SIZE(80, 144), UPB_SIZE(4, 8), UPB_TYPE_MESSAGE, &sub, arena);
if (!ok) return NULL;
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_transparent(envoy_api_v2_Listener *msg, struct google_protobuf_BoolValue* value) {
UPB_FIELD_AT(msg, struct google_protobuf_BoolValue*, UPB_SIZE(48, 80)) = value;
}
UPB_INLINE struct google_protobuf_BoolValue* envoy_api_v2_Listener_mutable_transparent(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct google_protobuf_BoolValue* sub = (struct google_protobuf_BoolValue*)envoy_api_v2_Listener_transparent(msg);
if (sub == NULL) {
sub = (struct google_protobuf_BoolValue*)upb_msg_new(&google_protobuf_BoolValue_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_transparent(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_freebind(envoy_api_v2_Listener *msg, struct google_protobuf_BoolValue* value) {
UPB_FIELD_AT(msg, struct google_protobuf_BoolValue*, UPB_SIZE(52, 88)) = value;
}
UPB_INLINE struct google_protobuf_BoolValue* envoy_api_v2_Listener_mutable_freebind(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct google_protobuf_BoolValue* sub = (struct google_protobuf_BoolValue*)envoy_api_v2_Listener_freebind(msg);
if (sub == NULL) {
sub = (struct google_protobuf_BoolValue*)upb_msg_new(&google_protobuf_BoolValue_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_freebind(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_tcp_fast_open_queue_length(envoy_api_v2_Listener *msg, struct google_protobuf_UInt32Value* value) {
UPB_FIELD_AT(msg, struct google_protobuf_UInt32Value*, UPB_SIZE(56, 96)) = value;
}
UPB_INLINE struct google_protobuf_UInt32Value* envoy_api_v2_Listener_mutable_tcp_fast_open_queue_length(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct google_protobuf_UInt32Value* sub = (struct google_protobuf_UInt32Value*)envoy_api_v2_Listener_tcp_fast_open_queue_length(msg);
if (sub == NULL) {
sub = (struct google_protobuf_UInt32Value*)upb_msg_new(&google_protobuf_UInt32Value_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_tcp_fast_open_queue_length(msg, sub);
}
return sub;
}
UPB_INLINE struct envoy_api_v2_core_SocketOption** envoy_api_v2_Listener_mutable_socket_options(envoy_api_v2_Listener *msg, size_t *len) {
return (struct envoy_api_v2_core_SocketOption**)_upb_array_mutable_accessor(msg, UPB_SIZE(84, 152), len);
}
UPB_INLINE struct envoy_api_v2_core_SocketOption** envoy_api_v2_Listener_resize_socket_options(envoy_api_v2_Listener *msg, size_t len, upb_arena *arena) {
return (struct envoy_api_v2_core_SocketOption**)_upb_array_resize_accessor(msg, UPB_SIZE(84, 152), len, UPB_SIZE(4, 8), UPB_TYPE_MESSAGE, arena);
}
UPB_INLINE struct envoy_api_v2_core_SocketOption* envoy_api_v2_Listener_add_socket_options(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_api_v2_core_SocketOption* sub = (struct envoy_api_v2_core_SocketOption*)upb_msg_new(&envoy_api_v2_core_SocketOption_msginit, arena);
bool ok = _upb_array_append_accessor(
msg, UPB_SIZE(84, 152), UPB_SIZE(4, 8), UPB_TYPE_MESSAGE, &sub, arena);
if (!ok) return NULL;
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_listener_filters_timeout(envoy_api_v2_Listener *msg, struct google_protobuf_Duration* value) {
UPB_FIELD_AT(msg, struct google_protobuf_Duration*, UPB_SIZE(60, 104)) = value;
}
UPB_INLINE struct google_protobuf_Duration* envoy_api_v2_Listener_mutable_listener_filters_timeout(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct google_protobuf_Duration* sub = (struct google_protobuf_Duration*)envoy_api_v2_Listener_listener_filters_timeout(msg);
if (sub == NULL) {
sub = (struct google_protobuf_Duration*)upb_msg_new(&google_protobuf_Duration_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_listener_filters_timeout(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_traffic_direction(envoy_api_v2_Listener *msg, int32_t value) {
UPB_FIELD_AT(msg, int32_t, UPB_SIZE(8, 8)) = value;
}
UPB_INLINE void envoy_api_v2_Listener_set_continue_on_listener_filters_timeout(envoy_api_v2_Listener *msg, bool value) {
UPB_FIELD_AT(msg, bool, UPB_SIZE(16, 16)) = value;
}
UPB_INLINE void envoy_api_v2_Listener_set_udp_listener_config(envoy_api_v2_Listener *msg, struct envoy_api_v2_listener_UdpListenerConfig* value) {
UPB_FIELD_AT(msg, struct envoy_api_v2_listener_UdpListenerConfig*, UPB_SIZE(64, 112)) = value;
}
UPB_INLINE struct envoy_api_v2_listener_UdpListenerConfig* envoy_api_v2_Listener_mutable_udp_listener_config(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_api_v2_listener_UdpListenerConfig* sub = (struct envoy_api_v2_listener_UdpListenerConfig*)envoy_api_v2_Listener_udp_listener_config(msg);
if (sub == NULL) {
sub = (struct envoy_api_v2_listener_UdpListenerConfig*)upb_msg_new(&envoy_api_v2_listener_UdpListenerConfig_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_udp_listener_config(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_api_listener(envoy_api_v2_Listener *msg, struct envoy_config_listener_v2_ApiListener* value) {
UPB_FIELD_AT(msg, struct envoy_config_listener_v2_ApiListener*, UPB_SIZE(68, 120)) = value;
}
UPB_INLINE struct envoy_config_listener_v2_ApiListener* envoy_api_v2_Listener_mutable_api_listener(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_config_listener_v2_ApiListener* sub = (struct envoy_config_listener_v2_ApiListener*)envoy_api_v2_Listener_api_listener(msg);
if (sub == NULL) {
sub = (struct envoy_config_listener_v2_ApiListener*)upb_msg_new(&envoy_config_listener_v2_ApiListener_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_api_listener(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_connection_balance_config(envoy_api_v2_Listener *msg, envoy_api_v2_Listener_ConnectionBalanceConfig* value) {
UPB_FIELD_AT(msg, envoy_api_v2_Listener_ConnectionBalanceConfig*, UPB_SIZE(72, 128)) = value;
}
UPB_INLINE struct envoy_api_v2_Listener_ConnectionBalanceConfig* envoy_api_v2_Listener_mutable_connection_balance_config(envoy_api_v2_Listener *msg, upb_arena *arena) {
struct envoy_api_v2_Listener_ConnectionBalanceConfig* sub = (struct envoy_api_v2_Listener_ConnectionBalanceConfig*)envoy_api_v2_Listener_connection_balance_config(msg);
if (sub == NULL) {
sub = (struct envoy_api_v2_Listener_ConnectionBalanceConfig*)upb_msg_new(&envoy_api_v2_Listener_ConnectionBalanceConfig_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_set_connection_balance_config(msg, sub);
}
return sub;
}
UPB_INLINE void envoy_api_v2_Listener_set_reuse_port(envoy_api_v2_Listener *msg, bool value) {
UPB_FIELD_AT(msg, bool, UPB_SIZE(17, 17)) = value;
}
/* envoy.api.v2.Listener.DeprecatedV1 */
UPB_INLINE envoy_api_v2_Listener_DeprecatedV1 *envoy_api_v2_Listener_DeprecatedV1_new(upb_arena *arena) {
return (envoy_api_v2_Listener_DeprecatedV1 *)upb_msg_new(&envoy_api_v2_Listener_DeprecatedV1_msginit, arena);
}
UPB_INLINE envoy_api_v2_Listener_DeprecatedV1 *envoy_api_v2_Listener_DeprecatedV1_parse(const char *buf, size_t size,
upb_arena *arena) {
envoy_api_v2_Listener_DeprecatedV1 *ret = envoy_api_v2_Listener_DeprecatedV1_new(arena);
return (ret && upb_decode(buf, size, ret, &envoy_api_v2_Listener_DeprecatedV1_msginit, arena)) ? ret : NULL;
}
UPB_INLINE char *envoy_api_v2_Listener_DeprecatedV1_serialize(const envoy_api_v2_Listener_DeprecatedV1 *msg, upb_arena *arena, size_t *len) {
return upb_encode(msg, &envoy_api_v2_Listener_DeprecatedV1_msginit, arena, len);
}
UPB_INLINE const struct google_protobuf_BoolValue* envoy_api_v2_Listener_DeprecatedV1_bind_to_port(const envoy_api_v2_Listener_DeprecatedV1 *msg) { return UPB_FIELD_AT(msg, const struct google_protobuf_BoolValue*, UPB_SIZE(0, 0)); }
UPB_INLINE void envoy_api_v2_Listener_DeprecatedV1_set_bind_to_port(envoy_api_v2_Listener_DeprecatedV1 *msg, struct google_protobuf_BoolValue* value) {
UPB_FIELD_AT(msg, struct google_protobuf_BoolValue*, UPB_SIZE(0, 0)) = value;
}
UPB_INLINE struct google_protobuf_BoolValue* envoy_api_v2_Listener_DeprecatedV1_mutable_bind_to_port(envoy_api_v2_Listener_DeprecatedV1 *msg, upb_arena *arena) {
struct google_protobuf_BoolValue* sub = (struct google_protobuf_BoolValue*)envoy_api_v2_Listener_DeprecatedV1_bind_to_port(msg);
if (sub == NULL) {
sub = (struct google_protobuf_BoolValue*)upb_msg_new(&google_protobuf_BoolValue_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_DeprecatedV1_set_bind_to_port(msg, sub);
}
return sub;
}
/* envoy.api.v2.Listener.ConnectionBalanceConfig */
UPB_INLINE envoy_api_v2_Listener_ConnectionBalanceConfig *envoy_api_v2_Listener_ConnectionBalanceConfig_new(upb_arena *arena) {
return (envoy_api_v2_Listener_ConnectionBalanceConfig *)upb_msg_new(&envoy_api_v2_Listener_ConnectionBalanceConfig_msginit, arena);
}
UPB_INLINE envoy_api_v2_Listener_ConnectionBalanceConfig *envoy_api_v2_Listener_ConnectionBalanceConfig_parse(const char *buf, size_t size,
upb_arena *arena) {
envoy_api_v2_Listener_ConnectionBalanceConfig *ret = envoy_api_v2_Listener_ConnectionBalanceConfig_new(arena);
return (ret && upb_decode(buf, size, ret, &envoy_api_v2_Listener_ConnectionBalanceConfig_msginit, arena)) ? ret : NULL;
}
UPB_INLINE char *envoy_api_v2_Listener_ConnectionBalanceConfig_serialize(const envoy_api_v2_Listener_ConnectionBalanceConfig *msg, upb_arena *arena, size_t *len) {
return upb_encode(msg, &envoy_api_v2_Listener_ConnectionBalanceConfig_msginit, arena, len);
}
typedef enum {
envoy_api_v2_Listener_ConnectionBalanceConfig_balance_type_exact_balance = 1,
envoy_api_v2_Listener_ConnectionBalanceConfig_balance_type_NOT_SET = 0
} envoy_api_v2_Listener_ConnectionBalanceConfig_balance_type_oneofcases;
UPB_INLINE envoy_api_v2_Listener_ConnectionBalanceConfig_balance_type_oneofcases envoy_api_v2_Listener_ConnectionBalanceConfig_balance_type_case(const envoy_api_v2_Listener_ConnectionBalanceConfig* msg) { return (envoy_api_v2_Listener_ConnectionBalanceConfig_balance_type_oneofcases)UPB_FIELD_AT(msg, int32_t, UPB_SIZE(4, 8)); }
UPB_INLINE bool envoy_api_v2_Listener_ConnectionBalanceConfig_has_exact_balance(const envoy_api_v2_Listener_ConnectionBalanceConfig *msg) { return _upb_has_oneof_field(msg, UPB_SIZE(4, 8), 1); }
UPB_INLINE const envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance* envoy_api_v2_Listener_ConnectionBalanceConfig_exact_balance(const envoy_api_v2_Listener_ConnectionBalanceConfig *msg) { return UPB_READ_ONEOF(msg, const envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance*, UPB_SIZE(0, 0), UPB_SIZE(4, 8), 1, NULL); }
UPB_INLINE void envoy_api_v2_Listener_ConnectionBalanceConfig_set_exact_balance(envoy_api_v2_Listener_ConnectionBalanceConfig *msg, envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance* value) {
UPB_WRITE_ONEOF(msg, envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance*, UPB_SIZE(0, 0), value, UPB_SIZE(4, 8), 1);
}
UPB_INLINE struct envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance* envoy_api_v2_Listener_ConnectionBalanceConfig_mutable_exact_balance(envoy_api_v2_Listener_ConnectionBalanceConfig *msg, upb_arena *arena) {
struct envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance* sub = (struct envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance*)envoy_api_v2_Listener_ConnectionBalanceConfig_exact_balance(msg);
if (sub == NULL) {
sub = (struct envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance*)upb_msg_new(&envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_msginit, arena);
if (!sub) return NULL;
envoy_api_v2_Listener_ConnectionBalanceConfig_set_exact_balance(msg, sub);
}
return sub;
}
/* envoy.api.v2.Listener.ConnectionBalanceConfig.ExactBalance */
UPB_INLINE envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance *envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_new(upb_arena *arena) {
return (envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance *)upb_msg_new(&envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_msginit, arena);
}
UPB_INLINE envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance *envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_parse(const char *buf, size_t size,
upb_arena *arena) {
envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance *ret = envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_new(arena);
return (ret && upb_decode(buf, size, ret, &envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_msginit, arena)) ? ret : NULL;
}
UPB_INLINE char *envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_serialize(const envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance *msg, upb_arena *arena, size_t *len) {
return upb_encode(msg, &envoy_api_v2_Listener_ConnectionBalanceConfig_ExactBalance_msginit, arena, len);
}
#ifdef __cplusplus
} /* extern "C" */
#endif
#include "upb/port_undef.inc"
#endif /* ENVOY_API_V2_LISTENER_PROTO_UPB_H_ */
|
dad98253/razer_pad
|
pad.c
|
<filename>pad.c
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdarg.h>
#include <errno.h>
#include <dirent.h>
#include <string.h>
#define mydebug 0
#define FOUND 0
#define NOT_FOUND 1
#define READ_ERROR 2
#define OPEN_ERROR 3
int LoadDirectoryContents(const char* sDir,const char* name);
int breaknow = 0;
char OpenPath[2048];
int main() {
int bright,dim,mindim,val,iret,red,green;
unsigned long long int user,nice,system,idle,iowait,irq,softirq,steal,guest,guest_nice,tot,oldidle,oldtot;
unsigned char rgb[3];
float percent;
char strcpu[1000];
FILE *fptr;
FILE *fptr2;
FILE *fptr3;
oldidle = 0;
oldtot = 0;
bright = 255;
mindim = 32;
dim = 32;
// Note that the following open statement is based on the usb device address for the pad when installed on my machine
// You will likely need to modify this address to match the location on your machine.
// This approach works on ubuntu 18.04.
// fptr = fopen("/sys/devices/pci0000:00/0000:00:14.0/usb3/3-7/3-7:1.0/0003:1532:0C02.0006/matrix_brightness","r+");
// fptr = fopen("/sys/devices/pci0000:00/0000:00:14.0/usb3/3-7/3-7:1.0/0003:1532:0C02.000F/matrix_brightness","r+");
// fptr = fopen("/sys/devices/pci0000:00/0000:00:14.0/usb3/3-7/3-7:1.0/0003:1532:0C02.0005/matrix_brightness","r+");
#ifdef DEBUG
fprintf(stderr,"look for matix_brightness" ); // prints look for matix_brightness
#endif
iret = LoadDirectoryContents("/sys/devices","matrix_brightness");
fptr = fopen(OpenPath,"r+");
if(fptr == NULL) {
printf("Error 1!");
exit(1);
}
// On ubuntu 18.04, the cpu status is available here:
fptr2 = fopen("/proc/stat","r");
if(fptr2 == NULL) {
printf("Error 2!");
exit(2);
}
// 'matrix_effect_static', b'\xFF\x00\x00'
// (see note above regarding usb addresses)
//fptr3 = fopen("/sys/devices/pci0000:00/0000:00:14.0/usb3/3-7/3-7:1.0/0003:1532:0C02.0005/matrix_effect_static","wb");
breaknow = 0;
iret = LoadDirectoryContents("/sys/devices","matrix_effect_static");
fptr3 = fopen(OpenPath,"wb");
if(fptr3 == NULL) {
printf("Error 5!");
exit(5);
}
fscanf(fptr,"%i",&val);
if ( mydebug ) printf("initial val = %i\n",val);
rewind(fptr);
while(1) {
/*
sleep(1);
fscanf(fptr,"%i",&val);
if ( mydebug ) printf("initial val = %i\n",val);
rewind(fptr);
fprintf(fptr,"%i",bright);
rewind(fptr);
fscanf(fptr,"%i",&val);
if ( mydebug ) printf("set to bright val = %i\n",val);
*/
fclose(fptr2);
fptr2 = fopen("/proc/stat","r");
if(fptr2 == NULL) {
printf("Error 2!");
exit(2);
}
// rewind(fptr2);
// Note: The format of this line has evolved. Linux developers have added fields over time. This worked on ubuntu 18.04 on January 1, 2020. If you are running an older
// or newer linux, you may need to adjust it.
iret = fscanf(fptr2,"%s %llu %llu %llu %llu %llu %llu %llu %llu %llu %llu",strcpu,&user,&nice,&system,&idle,&iowait,&irq,&softirq,&steal,&guest,&guest_nice);
if ( iret == EOF ) {
printf("EOF on /proc/stat, errno = %i\n",errno);
clearerr(fptr2);
exit(3);
}
if ( iret != 11 ) {
printf("failed to read full line on /proc/stat, iret = %i\n",iret);
clearerr(fptr2);
exit(4);
}
// if ( mydebug ) printf("%s %llu %llu %llu %llu %llu %llu %llu %llu %llu %llu\n",strcpu,user,nice,system,idle,iowait,irq,softirq,steal,guest,guest_nice);
clearerr(fptr2);
tot = user+nice+system+idle+iowait+irq+softirq+steal+guest+guest_nice;
// if ( mydebug ) printf("tot = %llu, idel = %llu\n",tot,idle);
if ( oldtot ) {
percent = 1.0 - ((float)(idle-oldidle)/(float)(tot-oldtot));
dim = mindim + (unsigned int)((bright-mindim) * percent);
red = (unsigned int)(255 * percent);
green = (unsigned int)(255 * ( 1.0 - percent) );
rgb[0] = (unsigned char)red;
rgb[1] = (unsigned char)green;
rgb[2] = '\00';
rewind(fptr3);
fwrite(rgb,sizeof(rgb),1,fptr3);
rewind(fptr);
fprintf(fptr,"%i",dim);
rewind(fptr);
fscanf(fptr,"%i",&val);
if ( mydebug ) printf("set to dim val = %i\n",val);
}
sleep(1);
oldtot = tot;
oldidle = idle;
}
fclose(fptr);
return(0);
}
int LoadDirectoryContents(const char* sDir,const char* name){
struct dirent *dp;
struct dirent d;
DIR *dirp;
dp = &d;
// const char * typemsg;
char sPath[2048];
if (breaknow) return (0);
dirp = opendir(sDir);
while (dirp) {
errno = 0;
if ((dp = readdir(dirp)) != NULL) {
if (strcmp(dp->d_name, ".") != 0
&& strcmp(dp->d_name, "..") != 0)
{
#ifdef DEBUG
// fprintf(stderr, "in LoadDirectoryContents, found \"%s\"\n", dp->d_name);
#endif
//Build up our file path using the passed in
// [sDir] and the file/foldername we just found:
sprintf(sPath, "%s/%s", sDir, dp->d_name);
#ifdef DEBUG
/* if ( dp->d_type == DT_BLK ) typemsg = "This is a block device.";
if ( dp->d_type == DT_CHR ) typemsg = "This is a character device.";
if ( dp->d_type == DT_DIR ) typemsg = "This is a directory.";
if ( dp->d_type == DT_FIFO ) typemsg = "This is a named pipe (FIFO).";
if ( dp->d_type == DT_LNK ) typemsg = "This is a symbolic link.";
if ( dp->d_type == DT_REG ) typemsg = "This is a regular file.";
if ( dp->d_type == DT_SOCK ) typemsg = "This is a UNIX domain socket.";
if ( dp->d_type == DT_UNKNOWN ) typemsg = "The file type could not be determined.";
fprintf(stderr,"%s ... %s\n",sPath,typemsg); */
#endif
//Is the entity a File or Folder?
if ( dp->d_type == DT_DIR ) {
LoadDirectoryContents(sPath,name);
if(breaknow) {
closedir(dirp);
return FOUND;
}
} else {
#ifdef DEBUG
// printf("\"%s\" ... at %s\n",dp->d_name,sPath);
#endif
if (strcmp(dp->d_name, name) == 0) {
breaknow = 1;
#ifdef DEBUG
printf("%s found! ... at %s\n",name,sPath);
#endif
strcpy(OpenPath,sPath);
closedir(dirp);
return FOUND;
}
}
}
} else {
if (errno == 0) {
closedir(dirp);
return NOT_FOUND;
}
closedir(dirp);
return READ_ERROR;
}
}
return OPEN_ERROR;
}
|
Foran/civetweb
|
examples/websocket/WebSockCallbacks.h
|
#ifndef WEBSOCKCALLBACKS_H_INCLUDED
#define WEBSOCKCALLBACKS_H_INCLUDED
#include "civetweb.h"
#ifdef __cplusplus
extern "C" {
#endif
void websock_init_lib(void);
void websock_exit_lib(void);
void websock_send_broadcast(const char * data, int data_len);
void websocket_ready_handler(struct mg_connection *conn);
int websocket_data_handler(struct mg_connection *conn, int flags, char *data, size_t data_len);
void connection_close_handler(struct mg_connection *conn);
#ifdef __cplusplus
}
#endif
#endif
|
Foran/civetweb
|
examples/websocket/WebSockCallbacks.c
|
<reponame>Foran/civetweb<filename>examples/websocket/WebSockCallbacks.c
#include <assert.h>
#include <stdlib.h>
#include <time.h>
#include "WebSockCallbacks.h"
#ifdef __APPLE__
#include <string.h>
#endif
#ifdef _WIN32
#include <Windows.h>
typedef HANDLE pthread_mutex_t;
static int pthread_mutex_init(pthread_mutex_t *mutex, void *unused) {
unused = NULL;
*mutex = CreateMutex(NULL, FALSE, NULL);
return *mutex == NULL ? -1 : 0;
}
static int pthread_mutex_destroy(pthread_mutex_t *mutex) {
return CloseHandle(*mutex) == 0 ? -1 : 0;
}
static int pthread_mutex_lock(pthread_mutex_t *mutex) {
return WaitForSingleObject(*mutex, INFINITE) == WAIT_OBJECT_0? 0 : -1;
}
static int pthread_mutex_unlock(pthread_mutex_t *mutex) {
return ReleaseMutex(*mutex) == 0 ? -1 : 0;
}
#define mg_sleep(x) Sleep(x)
#else
#include <unistd.h>
#include <pthread.h>
#define mg_sleep(x) usleep((x) * 1000)
#endif
typedef struct tWebSockInfo {
int webSockState;
unsigned long initId;
struct mg_connection *conn;
} tWebSockInfo;
static pthread_mutex_t sMutex;
#define MAX_NUM_OF_WEBSOCKS (256)
static tWebSockInfo *socketList[MAX_NUM_OF_WEBSOCKS];
static void send_to_all_websockets(const char * data, int data_len) {
int i;
for (i=0;i<MAX_NUM_OF_WEBSOCKS;i++) {
if (socketList[i] && (socketList[i]->webSockState==2)) {
mg_websocket_write(socketList[i]->conn, WEBSOCKET_OPCODE_TEXT, data, data_len);
}
}
}
void websocket_ready_handler(struct mg_connection *conn) {
int i;
struct mg_request_info * rq = mg_get_request_info(conn);
tWebSockInfo * wsock = malloc(sizeof(tWebSockInfo));
assert(wsock);
wsock->webSockState = 0;
rq->conn_data = wsock;
pthread_mutex_lock(&sMutex);
for (i=0;i<MAX_NUM_OF_WEBSOCKS;i++) {
if (0==socketList[i]) {
socketList[i] = wsock;
wsock->conn = conn;
wsock->webSockState = 1;
break;
}
}
printf("\nNew websocket attached: %08lx:%u\n", rq->remote_ip, rq->remote_port);
pthread_mutex_unlock(&sMutex);
}
static void websocket_done(tWebSockInfo * wsock) {
int i;
if (wsock) {
wsock->webSockState = 99;
for (i=0;i<MAX_NUM_OF_WEBSOCKS;i++) {
if (wsock==socketList[i]) {
socketList[i] = 0;
break;
}
}
printf("\nClose websocket attached: %08lx:%u\n", mg_get_request_info(wsock->conn)->remote_ip, mg_get_request_info(wsock->conn)->remote_port);
free(wsock);
}
}
int websocket_data_handler(struct mg_connection *conn, int flags, char *data, size_t data_len) {
struct mg_request_info * rq = mg_get_request_info(conn);
tWebSockInfo * wsock = (tWebSockInfo*)rq->conn_data;
char msg[128];
pthread_mutex_lock(&sMutex);
if (flags==136) {
// close websock
websocket_done(wsock);
rq->conn_data = 0;
pthread_mutex_unlock(&sMutex);
return 1;
}
if (((data_len>=5) && (data_len<100) && (flags==129)) || (flags==130)) {
// init command
if ((wsock->webSockState==1) && (!memcmp(data,"init ",5))) {
char * chk;
unsigned long gid;
memcpy(msg,data+5,data_len-5);
msg[data_len-5]=0;
gid = strtoul(msg,&chk,10);
wsock->initId = gid;
if (gid>0 && chk!=NULL && *chk==0) {
wsock->webSockState = 2;
}
pthread_mutex_unlock(&sMutex);
return 1;
}
// chat message
if ((wsock->webSockState==2) && (!memcmp(data,"msg ",4))) {
send_to_all_websockets(data, data_len);
pthread_mutex_unlock(&sMutex);
return 1;
}
}
// keep alive
if ((data_len==4) && !memcmp(data,"ping",4)) {
pthread_mutex_unlock(&sMutex);
return 1;
}
pthread_mutex_unlock(&sMutex);
return 0;
}
void connection_close_handler(struct mg_connection *conn) {
struct mg_request_info * rq = mg_get_request_info(conn);
tWebSockInfo * wsock = (tWebSockInfo*)rq->conn_data;
pthread_mutex_lock(&sMutex);
websocket_done(wsock);
rq->conn_data = 0;
pthread_mutex_unlock(&sMutex);
}
static int runLoop = 0;
static void * eventMain(void * _ignored) {
int i;
char msg[256];
runLoop = 1;
while (runLoop) {
time_t t = time(0);
struct tm * timestr = localtime(&t);
sprintf(msg,"title %s",asctime(timestr));
pthread_mutex_lock(&sMutex);
for (i=0;i<MAX_NUM_OF_WEBSOCKS;i++) {
if (socketList[i] && (socketList[i]->webSockState==2)) {
mg_websocket_write(socketList[i]->conn, WEBSOCKET_OPCODE_TEXT, msg, strlen(msg));
}
}
pthread_mutex_unlock(&sMutex);
mg_sleep(1000);
}
return _ignored;
}
void websock_send_broadcast(const char * data, int data_len) {
char buffer[260];
if (data_len<=256) {
strcpy(buffer, "msg ");
memcpy(buffer+4, data, data_len);
pthread_mutex_lock(&sMutex);
send_to_all_websockets(buffer, data_len+4);
pthread_mutex_unlock(&sMutex);
}
}
void websock_init_lib(void) {
int ret;
ret = pthread_mutex_init(&sMutex, 0);
assert(ret==0);
memset(socketList,0,sizeof(socketList));
mg_start_thread(eventMain, 0);
}
void websock_exit_lib(void) {
runLoop = 0;
}
|
Eszrah/chrone-memory
|
chrone-memory/include/LinearMemoryMapper.h
|
#pragma once
#include <utility>
#include "NativeType.h"
#include "CoreAllocatorProxy.h"
namespace chrone::memory
{
struct LinearAllocatorProxy
{
void* (*Allocate)(void*, Uint32) { CoreAllocatorProxy::Allocate };
void (*Deallocate)(void*, void*) { CoreAllocatorProxy::Deallocate };
void* allocatorData{ nullptr };
};
struct StaticLinearMemoryMapper
{
StaticLinearMemoryMapper(Uint32 const size,
LinearAllocatorProxy allocatorProxy):
size{ size },
offset{ size },
memory{ nullptr },
allocatorProxy{ allocatorProxy }
{}
Uint32 size{ 0u };
Uint32 offset{ 0u };
Char* memory{ nullptr };
LinearAllocatorProxy allocatorProxy{};
};
struct DynamicLinearMemoryMapper
{
DynamicLinearMemoryMapper(Uint32 const size,
LinearAllocatorProxy allocatorProxy) :
blockSize{ size },
begin{ nullptr },
end{ nullptr },
current{ nullptr },
allocatorProxy{ allocatorProxy }
{}
struct BufferNode
{
Uint32 offset{ 0u };
Char* memory{ nullptr };
BufferNode* next{};
};
Uint32 blockSize{ 0u };
BufferNode* begin{ nullptr };
BufferNode* end{ nullptr };
BufferNode* current{ nullptr };
LinearAllocatorProxy allocatorProxy{};
};
}
|
Eszrah/chrone-memory
|
chrone-memory/include/NativeType.h
|
<reponame>Eszrah/chrone-memory<filename>chrone-memory/include/NativeType.h
#pragma once
#include <cstdint>
#include <cstddef>
using PtrSize = std::ptrdiff_t;
using UChar = std::uint8_t;
using Char = std::int8_t;
using Bool8 = std::uint8_t;
using Uint8 = std::uint8_t;
using Int8 = std::int8_t;
using Uint16 = std::uint16_t;
using Int16 = std::int16_t;
using Uint32 = std::uint32_t;
using Int32 = std::int32_t;
using Uint64 = std::uint64_t;
using Int64 = std::int64_t;
using Decimal32 = float;
using Decimal64 = double;
|
Eszrah/chrone-memory
|
chrone-memory/include/MemoryConstructor.h
|
#pragma once
namespace chrone::memory
{
struct MemoryConstructor
{
using InstanceCountType = size_t;
template<class T, class... Args>
inline static void Construct(T* instance, Args&&... args);
template<class T, class... Args>
inline static void ConstructRange(InstanceCountType count, T* instance, Args&&... args);
template<class T>
inline static void Destruct(T* instance);
template<class T>
inline static void DestructRange(InstanceCountType count, T* instance);
};
template<
class T,
class ...Args>
inline void
MemoryConstructor::Construct(
T * instance,
Args && ...args)
{
new(instance) T(std::forward<Args>(args)...);
}
template<
class T,
class ...Args>
inline void
MemoryConstructor::ConstructRange(
InstanceCountType count,
T* instance,
Args && ...args)
{
for (auto index{ 0u }; index < count; ++index)
{
Construct(instance + index, std::forward<Args>(args)...);
}
}
template<class T>
inline void
MemoryConstructor::Destruct(
T* instance)
{
(*instance).~T();
}
template<class T>
inline void MemoryConstructor::DestructRange(InstanceCountType count, T * instance)
{
for (auto index{ 0u }; index < count; ++index)
{
Destruct(instance + index);
}
}
}
|
Eszrah/chrone-memory
|
chrone-memory/include/CoreAllocatorProxy.h
|
<gh_stars>0
#pragma once
#include "NativeType.h"
namespace chrone::memory
{
struct CoreAllocatorProxy
{
inline static void*
Allocate(
void* /*allocatorData*/,
Uint32 byteCount)
{
return new Char[byteCount];
}
inline static void
Deallocate(
void* /*allocatorData*/,
void* memory)
{
delete[] memory;
}
};
}
|
Eszrah/chrone-memory
|
chrone-memory/include/LinearMemoryMapperFunc.h
|
<reponame>Eszrah/chrone-memory
#pragma once
#include "NativeType.h"
namespace chrone::memory
{
struct StaticLinearMemoryMapper;
struct DynamicLinearMemoryMapper;
struct LinearAllocatorProxy;
struct LinearMemoryMapperFunc
{
static void
Allocate(StaticLinearMemoryMapper& mapper);
static Char*
MapMemory(StaticLinearMemoryMapper& mapper,
Uint32 const byteCount);
static void
Clear(StaticLinearMemoryMapper& mapper);
static void
Reset(StaticLinearMemoryMapper& mapper);
static void
Allocate(DynamicLinearMemoryMapper& mapper);
static Char*
MapMemory(DynamicLinearMemoryMapper& mapper,
Uint32 const byteCount);
static void
Clear(DynamicLinearMemoryMapper& mapper);
static void
Reset(DynamicLinearMemoryMapper& mapper);
};
}
|
shvets/WebAPI
|
WebAPI_tvOS/WebAPI_tvOS.h
|
<filename>WebAPI_tvOS/WebAPI_tvOS.h
//
// WebAPI_tvOS.h
// WebAPI_tvOS
//
// Created by <NAME> on 10/27/17.
//
#import <UIKit/UIKit.h>
//! Project version number for WebAPI_tvOS.
FOUNDATION_EXPORT double WebAPI_tvOSVersionNumber;
//! Project version string for WebAPI_tvOS.
FOUNDATION_EXPORT const unsigned char WebAPI_tvOSVersionString[];
// In this header, you should import all the public headers of your framework using statements like #import <WebAPI_tvOS/PublicHeader.h>
|
shvets/WebAPI
|
WebAPI_macOS/WebAPI_macOS.h
|
<reponame>shvets/WebAPI<gh_stars>0
//
// WebAPI_macOS.h
// WebAPI_macOS
//
// Created by <NAME> on 10/27/17.
//
#import <Cocoa/Cocoa.h>
//! Project version number for WebAPI_macOS.
FOUNDATION_EXPORT double WebAPI_macOSVersionNumber;
//! Project version string for WebAPI_macOS.
FOUNDATION_EXPORT const unsigned char WebAPI_macOSVersionString[];
// In this header, you should import all the public headers of your framework using statements like #import <WebAPI_macOS/PublicHeader.h>
|
shvets/WebAPI
|
WebAPI_iOS/WebAPI_iOS.h
|
//
// WebAPI_iOS.h
// WebAPI_iOS
//
// Created by <NAME> on 10/27/17.
//
#import <UIKit/UIKit.h>
//! Project version number for WebAPI_iOS.
FOUNDATION_EXPORT double WebAPI_iOSVersionNumber;
//! Project version string for WebAPI_iOS.
FOUNDATION_EXPORT const unsigned char WebAPI_iOSVersionString[];
// In this header, you should import all the public headers of your framework using statements like #import <WebAPI_iOS/PublicHeader.h>
|
onodera-punpun/xdesktop
|
xdesktop.c
|
<reponame>onodera-punpun/xdesktop
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <stdbool.h>
#include <unistd.h>
#include <signal.h>
#include <sys/select.h>
#include <xcb/xcb.h>
#include <xcb/xcb_event.h>
#include <xcb/xcb_icccm.h>
#include <xcb/xcb_ewmh.h>
#include "xdesktop.h"
uint32_t cur_desktop;
uint32_t tot_desktops;
xcb_atom_t cur_desktop_atom;
int main(int argc, char *argv[])
{
dpy = NULL;
ewmh = NULL;
bool snoop = false;
bool total = false;
bool get = true;
bool nextprev = false;
char direction;
unsigned int query = 0;
int ret = EXIT_SUCCESS;
char opt;
signal(SIGINT, hold);
signal(SIGHUP, hold);
signal(SIGTERM, hold);
while ((opt = getopt(argc, argv, "hvstg:pn")) != -1) {
switch (opt) {
case 'h':
printf("xdesktop [-h|-v|-s|-t|-p|-n|-g DESKTOP]\n");
goto end;
break;
case 'v':
printf("%s\n", VERSION);
goto end;
break;
case 's':
snoop = true;
break;
case 't':
total = true;
break;
case 'p':
case 'n':
get = false;
nextprev = true;
direction = opt;
break;
case 'g':
get = false;
query = atoi(optarg);
break;
}
}
if (!setup()) {
ret = EXIT_FAILURE;
goto end;
}
if (get) {
if (total) {
output_total_desktops();
} else {
output_current_desktop();
if (snoop) {
const uint32_t values[] = {XCB_EVENT_MASK_PROPERTY_CHANGE};
xcb_change_window_attributes (dpy, root, XCB_CW_EVENT_MASK, values);
xcb_intern_atom_cookie_t ac = xcb_intern_atom(dpy, 0, strlen("_NET_CURRENT_DESKTOP"), "_NET_CURRENT_DESKTOP");
cur_desktop_atom = xcb_intern_atom_reply(dpy, ac, NULL)->atom;
fd_set descriptors;
int fd = xcb_get_file_descriptor(dpy);
running = true;
xcb_flush(dpy);
while (running) {
FD_ZERO(&descriptors);
FD_SET(fd, &descriptors);
if (select(fd + 1, &descriptors, NULL, NULL, NULL) > 0) {
xcb_generic_event_t *evt;
while ((evt = xcb_poll_for_event(dpy)) != NULL) {
if (desktop_changed(evt))
output_current_desktop();
free(evt);
}
}
if (xcb_connection_has_error(dpy)) {
warnx("The server closed the connection.\n");
running = false;
}
}
}
}
} else {
xcb_ewmh_get_number_of_desktops_reply(ewmh, xcb_ewmh_get_number_of_desktops(ewmh, default_screen), &tot_desktops, NULL);
tot_desktops = tot_desktops - 1;
if (nextprev) {
xcb_ewmh_get_current_desktop_reply(ewmh, xcb_ewmh_get_current_desktop(ewmh, default_screen), &cur_desktop, NULL);
switch (direction) {
case 'p':
if (cur_desktop == 0) {
query = tot_desktops;
} else {
query = cur_desktop - 1;
}
break;
case 'n':
if (cur_desktop == tot_desktops) {
query = 0;
} else {
query = cur_desktop + 1;
}
break;
}
} else {
query = query - 1;
if (query > tot_desktops)
err("You don't have a desktop %i.\n", query + 1);
}
xcb_ewmh_request_change_current_desktop(ewmh, default_screen, query, XCB_CURRENT_TIME);
xcb_flush(dpy);
}
end:
if (ewmh != NULL) {
xcb_ewmh_connection_wipe(ewmh);
}
if (dpy != NULL) {
xcb_disconnect(dpy);
}
free(ewmh);
return ret;
}
bool setup(void)
{
dpy = xcb_connect(NULL, &default_screen);
if (xcb_connection_has_error(dpy)) {
warnx("can't open display.");
return false;
}
xcb_screen_t *screen = xcb_setup_roots_iterator(xcb_get_setup(dpy)).data;
if (screen == NULL) {
warnx("can't acquire screen.");
return false;
}
root = screen->root;
ewmh = malloc(sizeof(xcb_ewmh_connection_t));
if (xcb_ewmh_init_atoms_replies(ewmh, xcb_ewmh_init_atoms(dpy, ewmh), NULL) == 0) {
warnx("can't initialize EWMH atoms.");
return false;
}
return true;
}
void output_current_desktop(void)
{
xcb_ewmh_get_current_desktop_reply(ewmh, xcb_ewmh_get_current_desktop(ewmh, default_screen), &cur_desktop, NULL);
cur_desktop = cur_desktop + 1;
printf("%i\n", cur_desktop);
fflush(stdout);
}
void output_total_desktops(void)
{
xcb_ewmh_get_number_of_desktops_reply(ewmh, xcb_ewmh_get_number_of_desktops(ewmh, default_screen), &tot_desktops, NULL);
printf("%i\n", tot_desktops);
fflush(stdout);
}
bool desktop_changed(xcb_generic_event_t *evt)
{
if (XCB_EVENT_RESPONSE_TYPE(evt) == XCB_PROPERTY_NOTIFY){
xcb_property_notify_event_t *pne = (xcb_property_notify_event_t*) evt;
if(pne->atom == cur_desktop_atom)
return true;
}
return false;
}
void hold(int sig)
{
if (sig == SIGHUP || sig == SIGINT || sig == SIGTERM)
running = false;
}
|
andywx/agensgraph
|
src/backend/parser/uname_const_decl.c
|
/*
* uname_const_decl.c
*
* $Id$
*
* Constant declarations of commonly used UNAMEs.
*
* This file is part of the OpenLink Software Virtuoso Open-Source (VOS)
* project.
*
* Copyright (C) 1998-2019 OpenLink Software
*
* This project is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; only version 2 of the License, dated June 1991.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#include "Dk.h"
#include "uname_const_decl.h"
#define RDF_NS_URI "http://www.w3.org/1999/02/22-rdf-syntax-ns#"
#define XML_NS_URI "http://www.w3.org/XML/1998/namespace"
#define XMLSCHEMA_NS_URI "http://www.w3.org/2001/XMLSchema"
caddr_t uname__bang_cdata_section_elements;
caddr_t uname__bang_exclude_result_prefixes;
caddr_t uname__bang_file;
caddr_t uname__bang_location;
caddr_t uname__bang_name;
caddr_t uname__bang_ns;
caddr_t uname__bang_uri;
caddr_t uname__bang_use_attribute_sets;
caddr_t uname__bang_xmlns;
caddr_t uname__attr;
caddr_t uname__comment;
caddr_t uname__disable_output_escaping;
caddr_t uname__root;
caddr_t uname__pi;
caddr_t uname__ref;
caddr_t uname__srcfile;
caddr_t uname__srcline;
caddr_t uname__txt;
caddr_t uname__xslt;
caddr_t uname_at_id;
caddr_t uname_at_num;
caddr_t uname_SPECIAL_cc_bif_c_AVG;
caddr_t uname_SPECIAL_cc_bif_c_COUNT;
caddr_t uname_SPECIAL_cc_bif_c_GROUPING;
caddr_t uname_SPECIAL_cc_bif_c_MAX;
caddr_t uname_SPECIAL_cc_bif_c_MIN;
caddr_t uname_SPECIAL_cc_bif_c_SUM;
caddr_t uname_bif_c_contains;
caddr_t uname_bif_c_spatial_contains;
caddr_t uname_bif_c_spatial_intersects;
caddr_t uname_bif_c_st_contains;
caddr_t uname_bif_c_st_intersects;
caddr_t uname_bif_c_st_may_intersect;
caddr_t uname_bif_c_st_within;
caddr_t uname_bif_c_xcontains;
caddr_t uname_bif_c_xpath_contains;
caddr_t uname_bif_c_xquery_contains;
caddr_t uname_bif_ns_uri;
caddr_t uname_opengis_def_function_gs_ns_uri;
caddr_t uname_opengis_def_function_gs_ns_uri_boundary;
caddr_t uname_opengis_def_function_gs_ns_uri_buffer;
caddr_t uname_opengis_def_function_gs_ns_uri_convexHull;
caddr_t uname_opengis_def_function_gs_ns_uri_difference;
caddr_t uname_opengis_def_function_gs_ns_uri_distance;
caddr_t uname_opengis_def_function_gs_ns_uri_ehContains;
caddr_t uname_opengis_def_function_gs_ns_uri_ehCoveredBy;
caddr_t uname_opengis_def_function_gs_ns_uri_ehCovers;
caddr_t uname_opengis_def_function_gs_ns_uri_ehDisjoint;
caddr_t uname_opengis_def_function_gs_ns_uri_ehEquals;
caddr_t uname_opengis_def_function_gs_ns_uri_ehInside;
caddr_t uname_opengis_def_function_gs_ns_uri_ehMeet;
caddr_t uname_opengis_def_function_gs_ns_uri_ehOverlap;
caddr_t uname_opengis_def_function_gs_ns_uri_envelope;
caddr_t uname_opengis_def_function_gs_ns_uri_getSRID;
caddr_t uname_opengis_def_function_gs_ns_uri_intersection;
caddr_t uname_opengis_def_function_gs_ns_uri_rcc8dc;
caddr_t uname_opengis_def_function_gs_ns_uri_rcc8ec;
caddr_t uname_opengis_def_function_gs_ns_uri_rcc8eq;
caddr_t uname_opengis_def_function_gs_ns_uri_rcc8ntpp;
caddr_t uname_opengis_def_function_gs_ns_uri_rcc8ntppi;
caddr_t uname_opengis_def_function_gs_ns_uri_rcc8po;
caddr_t uname_opengis_def_function_gs_ns_uri_rcc8tpp;
caddr_t uname_opengis_def_function_gs_ns_uri_rcc8tppi;
caddr_t uname_opengis_def_function_gs_ns_uri_relate;
caddr_t uname_opengis_def_function_gs_ns_uri_sfContains;
caddr_t uname_opengis_def_function_gs_ns_uri_sfCrosses;
caddr_t uname_opengis_def_function_gs_ns_uri_sfDisjoint;
caddr_t uname_opengis_def_function_gs_ns_uri_sfEquals;
caddr_t uname_opengis_def_function_gs_ns_uri_sfIntersects;
caddr_t uname_opengis_def_function_gs_ns_uri_sfOverlaps;
caddr_t uname_opengis_def_function_gs_ns_uri_sfTouches;
caddr_t uname_opengis_def_function_gs_ns_uri_sfWithin;
caddr_t uname_opengis_def_function_gs_ns_uri_symDifference;
caddr_t uname_opengis_def_function_gs_ns_uri_union;
caddr_t uname_opengis_def_rule_gs_ns_uri;
caddr_t uname_opengis_def_rule_gs_ns_uri_ehContains;
caddr_t uname_opengis_def_rule_gs_ns_uri_ehCoveredBy;
caddr_t uname_opengis_def_rule_gs_ns_uri_ehCovers;
caddr_t uname_opengis_def_rule_gs_ns_uri_ehDisjoint;
caddr_t uname_opengis_def_rule_gs_ns_uri_ehEquals;
caddr_t uname_opengis_def_rule_gs_ns_uri_ehInside;
caddr_t uname_opengis_def_rule_gs_ns_uri_ehMeet;
caddr_t uname_opengis_def_rule_gs_ns_uri_ehOverlap;
caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8dc;
caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8ec;
caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8eq;
caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8ntpp;
caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8ntppi;
caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8po;
caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8tpp;
caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8tppi;
caddr_t uname_opengis_ns_uri;
caddr_t uname_opengis_ont_gml_ns_uri;
caddr_t uname_opengis_ont_gs_ns_uri;
caddr_t uname_opengis_ont_gs_ns_uri_Feature;
caddr_t uname_opengis_ont_gs_ns_uri_SpatialObject;
caddr_t uname_opengis_ont_gs_ns_uri_asGML;
caddr_t uname_opengis_ont_gs_ns_uri_asWKT;
caddr_t uname_opengis_ont_gs_ns_uri_coordinateDimension;
caddr_t uname_opengis_ont_gs_ns_uri_dimension;
caddr_t uname_opengis_ont_gs_ns_uri_ehContains;
caddr_t uname_opengis_ont_gs_ns_uri_ehCoveredBy;
caddr_t uname_opengis_ont_gs_ns_uri_ehCovers;
caddr_t uname_opengis_ont_gs_ns_uri_ehDisjoint;
caddr_t uname_opengis_ont_gs_ns_uri_ehEquals;
caddr_t uname_opengis_ont_gs_ns_uri_ehInside;
caddr_t uname_opengis_ont_gs_ns_uri_ehMeet;
caddr_t uname_opengis_ont_gs_ns_uri_ehOverlap;
caddr_t uname_opengis_ont_gs_ns_uri_gmlLiteral;
caddr_t uname_opengis_ont_gs_ns_uri_hasDefaultGeometry;
caddr_t uname_opengis_ont_gs_ns_uri_hasGeometry;
caddr_t uname_opengis_ont_gs_ns_uri_hasSerialization;
caddr_t uname_opengis_ont_gs_ns_uri_isEmpty;
caddr_t uname_opengis_ont_gs_ns_uri_isSimple;
caddr_t uname_opengis_ont_gs_ns_uri_rcc8dc;
caddr_t uname_opengis_ont_gs_ns_uri_rcc8ec;
caddr_t uname_opengis_ont_gs_ns_uri_rcc8eq;
caddr_t uname_opengis_ont_gs_ns_uri_rcc8ntpp;
caddr_t uname_opengis_ont_gs_ns_uri_rcc8ntppi;
caddr_t uname_opengis_ont_gs_ns_uri_rcc8po;
caddr_t uname_opengis_ont_gs_ns_uri_rcc8tpp;
caddr_t uname_opengis_ont_gs_ns_uri_rcc8tppi;
caddr_t uname_opengis_ont_gs_ns_uri_sfContains;
caddr_t uname_opengis_ont_gs_ns_uri_sfCrosses;
caddr_t uname_opengis_ont_gs_ns_uri_sfDisjoint;
caddr_t uname_opengis_ont_gs_ns_uri_sfEquals;
caddr_t uname_opengis_ont_gs_ns_uri_sfIntersects;
caddr_t uname_opengis_ont_gs_ns_uri_sfOverlaps;
caddr_t uname_opengis_ont_gs_ns_uri_sfTouches;
caddr_t uname_opengis_ont_gs_ns_uri_sfWithin;
caddr_t uname_opengis_ont_gs_ns_uri_spatialDimension;
caddr_t uname_opengis_ont_gs_ns_uri_wktLiteral;
caddr_t uname_opengis_ont_sf_ns_uri;
caddr_t uname_false;
caddr_t uname_lang;
caddr_t uname_nil;
caddr_t uname_nodeID_ns;
caddr_t uname_nodeID_ns_0;
caddr_t uname_nodeID_ns_8192;
caddr_t uname_rdf_ns_uri;
caddr_t uname_rdf_ns_uri_Description;
caddr_t uname_rdf_ns_uri_ID;
caddr_t uname_rdf_ns_uri_RDF;
caddr_t uname_rdf_ns_uri_Seq;
caddr_t uname_rdf_ns_uri_Statement;
caddr_t uname_rdf_ns_uri_XMLLiteral;
caddr_t uname_rdf_ns_uri_about;
caddr_t uname_rdf_ns_uri_first;
caddr_t uname_rdf_ns_uri_li;
caddr_t uname_rdf_ns_uri_nil;
caddr_t uname_rdf_ns_uri_nodeID;
caddr_t uname_rdf_ns_uri_object;
caddr_t uname_rdf_ns_uri_predicate;
caddr_t uname_rdf_ns_uri_resource;
caddr_t uname_rdf_ns_uri_rest;
caddr_t uname_rdf_ns_uri_subject;
caddr_t uname_rdf_ns_uri_type;
caddr_t uname_rdf_ns_uri_datatype;
caddr_t uname_rdf_ns_uri_parseType;
caddr_t uname_rdf_ns_uri_value;
caddr_t uname_rdfdf_ns_uri;
caddr_t uname_rdfdf_ns_uri_default;
caddr_t uname_rdfdf_ns_uri_default_nullable;
caddr_t uname_rdfdf_ns_uri_default_iid;
caddr_t uname_rdfdf_ns_uri_default_iid_nullable;
caddr_t uname_space;
caddr_t uname_sql_ns_uri;
caddr_t uname_swap_reify_ns_uri;
caddr_t uname_swap_reify_ns_uri_statement;
caddr_t uname_true;
caddr_t uname_virtrdf_ns_uri;
caddr_t uname_virtrdf_ns_uri_DefaultQuadMap;
caddr_t uname_virtrdf_ns_uri_DefaultQuadStorage;
caddr_t uname_virtrdf_ns_uri_DefaultServiceMap;
caddr_t uname_virtrdf_ns_uri_DefaultServiceStorage;
caddr_t uname_virtrdf_ns_uri_DefaultSparul11Target;
caddr_t uname_virtrdf_ns_uri_Geometry;
caddr_t uname_virtrdf_ns_uri_PrivateGraphs;
caddr_t uname_virtrdf_ns_uri_QuadMap;
caddr_t uname_virtrdf_ns_uri_QuadMapFormat;
caddr_t uname_virtrdf_ns_uri_QuadStorage;
caddr_t uname_virtrdf_ns_uri_RdfDebuggerSingletone;
caddr_t uname_virtrdf_ns_uri_SparqlMacroLibrary;
caddr_t uname_virtrdf_ns_uri_SyncToQuads;
caddr_t uname_virtrdf_ns_uri_array_of_any;
caddr_t uname_virtrdf_ns_uri_array_of_string;
caddr_t uname_virtrdf_ns_uri_bitmask;
caddr_t uname_virtrdf_ns_uri_bnode_base;
caddr_t uname_virtrdf_ns_uri_bnode_label;
caddr_t uname_virtrdf_ns_uri_bnode_row;
caddr_t uname_virtrdf_ns_uri_dialect;
caddr_t uname_virtrdf_ns_uri_dialect_exceptions;
caddr_t uname_virtrdf_ns_uri_isSpecialPredicate;
caddr_t uname_virtrdf_ns_uri_isSubclassOf;
caddr_t uname_virtrdf_ns_uri_loadAs;
caddr_t uname_virtrdf_ns_uri_namespace_base;
caddr_t uname_virtrdf_ns_uri_namespace_iri;
caddr_t uname_virtrdf_ns_uri_namespace_prefix;
caddr_t uname_virtrdf_ns_uri_namespace_row;
caddr_t uname_virtrdf_ns_uri_rdf_repl_all;
caddr_t uname_virtrdf_ns_uri_rdf_repl_graph_group;
caddr_t uname_virtrdf_ns_uri_rdf_repl_world;
caddr_t uname_xhv_ns_uri;
caddr_t uname_xhv_ns_uri_alternate;
caddr_t uname_xhv_ns_uri_appendix;
caddr_t uname_xhv_ns_uri_bookmark;
caddr_t uname_xhv_ns_uri_chapter;
caddr_t uname_xhv_ns_uri_cite;
caddr_t uname_xhv_ns_uri_contents;
caddr_t uname_xhv_ns_uri_copyright;
caddr_t uname_xhv_ns_uri_first;
caddr_t uname_xhv_ns_uri_glossary;
caddr_t uname_xhv_ns_uri_help;
caddr_t uname_xhv_ns_uri_icon;
caddr_t uname_xhv_ns_uri_index;
caddr_t uname_xhv_ns_uri_last;
caddr_t uname_xhv_ns_uri_license;
caddr_t uname_xhv_ns_uri_meta;
caddr_t uname_xhv_ns_uri_next;
caddr_t uname_xhv_ns_uri_p3pv1;
caddr_t uname_xhv_ns_uri_prev;
caddr_t uname_xhv_ns_uri_role;
caddr_t uname_xhv_ns_uri_section;
caddr_t uname_xhv_ns_uri_start;
caddr_t uname_xhv_ns_uri_stylesheet;
caddr_t uname_xhv_ns_uri_subsection;
caddr_t uname_xhv_ns_uri_up;
caddr_t uname_xml;
caddr_t uname_xmlns;
caddr_t uname_xml_colon_base;
caddr_t uname_xml_colon_lang;
caddr_t uname_xml_colon_space;
caddr_t uname_xml_ns_uri;
caddr_t uname_xml_ns_uri_colon_base;
caddr_t uname_xml_ns_uri_colon_lang;
caddr_t uname_xml_ns_uri_colon_space;
caddr_t uname_xmlschema_ns_uri;
caddr_t uname_xmlschema_ns_uri_hash;
caddr_t uname_xmlschema_ns_uri_hash_ENTITY;
caddr_t uname_xmlschema_ns_uri_hash_ENTITIES;
caddr_t uname_xmlschema_ns_uri_hash_ID;
caddr_t uname_xmlschema_ns_uri_hash_IDREF;
caddr_t uname_xmlschema_ns_uri_hash_IDREFS;
caddr_t uname_xmlschema_ns_uri_hash_NCName;
caddr_t uname_xmlschema_ns_uri_hash_Name;
caddr_t uname_xmlschema_ns_uri_hash_NMTOKEN;
caddr_t uname_xmlschema_ns_uri_hash_NMTOKENS;
caddr_t uname_xmlschema_ns_uri_hash_NOTATION;
caddr_t uname_xmlschema_ns_uri_hash_QName;
caddr_t uname_xmlschema_ns_uri_hash_any;
caddr_t uname_xmlschema_ns_uri_hash_anyAtomicType;
caddr_t uname_xmlschema_ns_uri_hash_anySimpleType;
caddr_t uname_xmlschema_ns_uri_hash_anyType;
caddr_t uname_xmlschema_ns_uri_hash_anyURI;
caddr_t uname_xmlschema_ns_uri_hash_base64Binary;
caddr_t uname_xmlschema_ns_uri_hash_bitmask;
caddr_t uname_xmlschema_ns_uri_hash_boolean;
caddr_t uname_xmlschema_ns_uri_hash_byte;
caddr_t uname_xmlschema_ns_uri_hash_date;
caddr_t uname_xmlschema_ns_uri_hash_dateTime;
caddr_t uname_xmlschema_ns_uri_hash_dateTimeStamp;
caddr_t uname_xmlschema_ns_uri_hash_dayTimeDuration;
caddr_t uname_xmlschema_ns_uri_hash_decimal;
caddr_t uname_xmlschema_ns_uri_hash_double;
caddr_t uname_xmlschema_ns_uri_hash_duration;
caddr_t uname_xmlschema_ns_uri_hash_float;
caddr_t uname_xmlschema_ns_uri_hash_gDay;
caddr_t uname_xmlschema_ns_uri_hash_gMonth;
caddr_t uname_xmlschema_ns_uri_hash_gMonthDay;
caddr_t uname_xmlschema_ns_uri_hash_gYear;
caddr_t uname_xmlschema_ns_uri_hash_gYearMonth;
caddr_t uname_xmlschema_ns_uri_hash_hexBinary;
caddr_t uname_xmlschema_ns_uri_hash_int;
caddr_t uname_xmlschema_ns_uri_hash_integer;
caddr_t uname_xmlschema_ns_uri_hash_language;
caddr_t uname_xmlschema_ns_uri_hash_long;
caddr_t uname_xmlschema_ns_uri_hash_negativeInteger;
caddr_t uname_xmlschema_ns_uri_hash_nonNegativeInteger;
caddr_t uname_xmlschema_ns_uri_hash_nonPositiveInteger;
caddr_t uname_xmlschema_ns_uri_hash_normalizedString;
caddr_t uname_xmlschema_ns_uri_hash_positiveInteger;
caddr_t uname_xmlschema_ns_uri_hash_short;
caddr_t uname_xmlschema_ns_uri_hash_string;
caddr_t uname_xmlschema_ns_uri_hash_time;
caddr_t uname_xmlschema_ns_uri_hash_token;
caddr_t uname_xmlschema_ns_uri_hash_unsignedByte;
caddr_t uname_xmlschema_ns_uri_hash_unsignedInt;
caddr_t uname_xmlschema_ns_uri_hash_unsignedLong;
caddr_t uname_xmlschema_ns_uri_hash_unsignedShort;
caddr_t uname_xmlschema_ns_uri_hash_yearMonthDuration;
caddr_t unames_colon_number[20];
typedef struct uname_const_decl_s
{
caddr_t *var_ptr;
const char *text;
} uname_const_decl_t;
void
uname_const_decl_init (void)
{
int ctr;
static uname_const_decl_t uname_const_decls[] = {
{ &uname__bang_cdata_section_elements , " !cdata-section-elements" },
{ &uname__bang_exclude_result_prefixes , " !exclude_result_prefixes" },
{ &uname__bang_file , " !file" },
{ &uname__bang_location , " !location" },
{ &uname__bang_name , " !name" },
{ &uname__bang_ns , " !ns" },
{ &uname__bang_uri , " !uri" },
{ &uname__bang_use_attribute_sets , " !use-attribute-sets" },
{ &uname__bang_xmlns , " !xmlns" },
{ &uname__attr , " attr" },
{ &uname__comment , " comment" },
{ &uname__disable_output_escaping , " disable-output-escaping" },
{ &uname__root , " root" },
{ &uname__pi , " pi" },
{ &uname__ref , " ref" },
{ &uname__srcfile , " srcfile" },
{ &uname__srcline , " srcline" },
{ &uname__txt , " txt" },
{ &uname__xslt , " xslt" },
{ &uname_at_id , "@id" },
{ &uname_at_num , "@num" },
{ &uname_SPECIAL_cc_bif_c_AVG , "SPECIAL::bif:AVG" },
{ &uname_SPECIAL_cc_bif_c_COUNT , "SPECIAL::bif:COUNT" },
{ &uname_SPECIAL_cc_bif_c_GROUPING , "SPECIAL::bif:GROUPING" },
{ &uname_SPECIAL_cc_bif_c_MAX , "SPECIAL::bif:MAX" },
{ &uname_SPECIAL_cc_bif_c_MIN , "SPECIAL::bif:MIN" },
{ &uname_SPECIAL_cc_bif_c_SUM , "SPECIAL::bif:SUM" },
{ &uname_bif_c_contains , "bif:contains" },
{ &uname_bif_c_spatial_contains , "bif:spatial_contains" },
{ &uname_bif_c_spatial_intersects , "bif:spatial_intersects" },
{ &uname_bif_c_st_contains , "bif:st_contains" },
{ &uname_bif_c_st_intersects , "bif:st_intersects" },
{ &uname_bif_c_st_may_intersect , "bif:st_may_intersect" },
{ &uname_bif_c_st_within , "bif:st_within" },
{ &uname_bif_c_xcontains , "bif:xcontains" },
{ &uname_bif_c_xpath_contains , "bif:xpath_contains" },
{ &uname_bif_c_xquery_contains , "bif:xquery_contains" },
{ &uname_bif_ns_uri , OPENLINKSW_BIF_NS_URI },
{ &uname_opengis_def_function_gs_ns_uri , OPENGIS_DEF_FUNCTION_GS_NS_URI },
{ &uname_opengis_def_function_gs_ns_uri_boundary , OPENGIS_DEF_FUNCTION_GS_NS_URI "boundary" },
{ &uname_opengis_def_function_gs_ns_uri_buffer , OPENGIS_DEF_FUNCTION_GS_NS_URI "buffer" },
{ &uname_opengis_def_function_gs_ns_uri_convexHull , OPENGIS_DEF_FUNCTION_GS_NS_URI "convexHull" },
{ &uname_opengis_def_function_gs_ns_uri_difference , OPENGIS_DEF_FUNCTION_GS_NS_URI "difference" },
{ &uname_opengis_def_function_gs_ns_uri_distance , OPENGIS_DEF_FUNCTION_GS_NS_URI "distance" },
{ &uname_opengis_def_function_gs_ns_uri_ehContains , OPENGIS_DEF_FUNCTION_GS_NS_URI "ehContains" },
{ &uname_opengis_def_function_gs_ns_uri_ehCoveredBy , OPENGIS_DEF_FUNCTION_GS_NS_URI "ehCoveredBy" },
{ &uname_opengis_def_function_gs_ns_uri_ehCovers , OPENGIS_DEF_FUNCTION_GS_NS_URI "ehCovers" },
{ &uname_opengis_def_function_gs_ns_uri_ehDisjoint , OPENGIS_DEF_FUNCTION_GS_NS_URI "ehDisjoint" },
{ &uname_opengis_def_function_gs_ns_uri_ehEquals , OPENGIS_DEF_FUNCTION_GS_NS_URI "ehEquals" },
{ &uname_opengis_def_function_gs_ns_uri_ehInside , OPENGIS_DEF_FUNCTION_GS_NS_URI "ehInside" },
{ &uname_opengis_def_function_gs_ns_uri_ehMeet , OPENGIS_DEF_FUNCTION_GS_NS_URI "ehMeet" },
{ &uname_opengis_def_function_gs_ns_uri_ehOverlap , OPENGIS_DEF_FUNCTION_GS_NS_URI "ehOverlap" },
{ &uname_opengis_def_function_gs_ns_uri_envelope , OPENGIS_DEF_FUNCTION_GS_NS_URI "envelope" },
{ &uname_opengis_def_function_gs_ns_uri_getSRID , OPENGIS_DEF_FUNCTION_GS_NS_URI "getSRID" },
{ &uname_opengis_def_function_gs_ns_uri_intersection , OPENGIS_DEF_FUNCTION_GS_NS_URI "intersection" },
{ &uname_opengis_def_function_gs_ns_uri_rcc8dc , OPENGIS_DEF_FUNCTION_GS_NS_URI "rcc8dc" },
{ &uname_opengis_def_function_gs_ns_uri_rcc8ec , OPENGIS_DEF_FUNCTION_GS_NS_URI "rcc8ec" },
{ &uname_opengis_def_function_gs_ns_uri_rcc8eq , OPENGIS_DEF_FUNCTION_GS_NS_URI "rcc8eq" },
{ &uname_opengis_def_function_gs_ns_uri_rcc8ntpp , OPENGIS_DEF_FUNCTION_GS_NS_URI "rcc8ntpp" },
{ &uname_opengis_def_function_gs_ns_uri_rcc8ntppi , OPENGIS_DEF_FUNCTION_GS_NS_URI "rcc8ntppi" },
{ &uname_opengis_def_function_gs_ns_uri_rcc8po , OPENGIS_DEF_FUNCTION_GS_NS_URI "rcc8po" },
{ &uname_opengis_def_function_gs_ns_uri_rcc8tpp , OPENGIS_DEF_FUNCTION_GS_NS_URI "rcc8tpp" },
{ &uname_opengis_def_function_gs_ns_uri_rcc8tppi , OPENGIS_DEF_FUNCTION_GS_NS_URI "rcc8tppi" },
{ &uname_opengis_def_function_gs_ns_uri_relate , OPENGIS_DEF_FUNCTION_GS_NS_URI "relate" },
{ &uname_opengis_def_function_gs_ns_uri_sfContains , OPENGIS_DEF_FUNCTION_GS_NS_URI "sfContains" },
{ &uname_opengis_def_function_gs_ns_uri_sfCrosses , OPENGIS_DEF_FUNCTION_GS_NS_URI "sfCrosses" },
{ &uname_opengis_def_function_gs_ns_uri_sfDisjoint , OPENGIS_DEF_FUNCTION_GS_NS_URI "sfDisjoint" },
{ &uname_opengis_def_function_gs_ns_uri_sfEquals , OPENGIS_DEF_FUNCTION_GS_NS_URI "sfEquals" },
{ &uname_opengis_def_function_gs_ns_uri_sfIntersects , OPENGIS_DEF_FUNCTION_GS_NS_URI "sfIntersects" },
{ &uname_opengis_def_function_gs_ns_uri_sfOverlaps , OPENGIS_DEF_FUNCTION_GS_NS_URI "sfOverlaps" },
{ &uname_opengis_def_function_gs_ns_uri_sfTouches , OPENGIS_DEF_FUNCTION_GS_NS_URI "sfTouches" },
{ &uname_opengis_def_function_gs_ns_uri_sfWithin , OPENGIS_DEF_FUNCTION_GS_NS_URI "sfWithin" },
{ &uname_opengis_def_function_gs_ns_uri_symDifference , OPENGIS_DEF_FUNCTION_GS_NS_URI "symDifference"},
{ &uname_opengis_def_function_gs_ns_uri_union , OPENGIS_DEF_FUNCTION_GS_NS_URI "union" },
{ &uname_opengis_def_rule_gs_ns_uri , OPENGIS_DEF_RULE_GS_NS_URI },
{ &uname_opengis_def_rule_gs_ns_uri_ehContains , OPENGIS_DEF_RULE_GS_NS_URI "ehContains" },
{ &uname_opengis_def_rule_gs_ns_uri_ehCoveredBy , OPENGIS_DEF_RULE_GS_NS_URI "ehCoveredBy" },
{ &uname_opengis_def_rule_gs_ns_uri_ehCovers , OPENGIS_DEF_RULE_GS_NS_URI "ehCovers" },
{ &uname_opengis_def_rule_gs_ns_uri_ehDisjoint , OPENGIS_DEF_RULE_GS_NS_URI "ehDisjoint" },
{ &uname_opengis_def_rule_gs_ns_uri_ehEquals , OPENGIS_DEF_RULE_GS_NS_URI "ehEquals" },
{ &uname_opengis_def_rule_gs_ns_uri_ehInside , OPENGIS_DEF_RULE_GS_NS_URI "ehInside" },
{ &uname_opengis_def_rule_gs_ns_uri_ehMeet , OPENGIS_DEF_RULE_GS_NS_URI "ehMeet" },
{ &uname_opengis_def_rule_gs_ns_uri_ehOverlap , OPENGIS_DEF_RULE_GS_NS_URI "ehOverlap" },
{ &uname_opengis_def_rule_gs_ns_uri_rcc8dc , OPENGIS_DEF_RULE_GS_NS_URI "rcc8dc" },
{ &uname_opengis_def_rule_gs_ns_uri_rcc8ec , OPENGIS_DEF_RULE_GS_NS_URI "rcc8ec" },
{ &uname_opengis_def_rule_gs_ns_uri_rcc8eq , OPENGIS_DEF_RULE_GS_NS_URI "rcc8eq" },
{ &uname_opengis_def_rule_gs_ns_uri_rcc8ntpp , OPENGIS_DEF_RULE_GS_NS_URI "rcc8ntpp" },
{ &uname_opengis_def_rule_gs_ns_uri_rcc8ntppi , OPENGIS_DEF_RULE_GS_NS_URI "rcc8ntppi" },
{ &uname_opengis_def_rule_gs_ns_uri_rcc8po , OPENGIS_DEF_RULE_GS_NS_URI "rcc8po" },
{ &uname_opengis_def_rule_gs_ns_uri_rcc8tpp , OPENGIS_DEF_RULE_GS_NS_URI "rcc8tpp" },
{ &uname_opengis_def_rule_gs_ns_uri_rcc8tppi , OPENGIS_DEF_RULE_GS_NS_URI "rcc8tppi" },
{ &uname_opengis_ns_uri , OPENGIS_NS_URI },
{ &uname_opengis_ont_gml_ns_uri , OPENGIS_ONT_GML_NS_URI },
{ &uname_opengis_ont_gs_ns_uri , OPENGIS_ONT_GS_NS_URI },
{ &uname_opengis_ont_gs_ns_uri_Feature , OPENGIS_ONT_GS_NS_URI "Feature" },
{ &uname_opengis_ont_gs_ns_uri_SpatialObject , OPENGIS_ONT_GS_NS_URI "SpatialObject" },
{ &uname_opengis_ont_gs_ns_uri_asGML , OPENGIS_ONT_GS_NS_URI "asGML" },
{ &uname_opengis_ont_gs_ns_uri_asWKT , OPENGIS_ONT_GS_NS_URI "asWKT" },
{ &uname_opengis_ont_gs_ns_uri_coordinateDimension , OPENGIS_ONT_GS_NS_URI "coordinateDimension" },
{ &uname_opengis_ont_gs_ns_uri_dimension , OPENGIS_ONT_GS_NS_URI "dimension" },
{ &uname_opengis_ont_gs_ns_uri_ehContains , OPENGIS_ONT_GS_NS_URI "ehContains" },
{ &uname_opengis_ont_gs_ns_uri_ehCoveredBy , OPENGIS_ONT_GS_NS_URI "ehCoveredBy" },
{ &uname_opengis_ont_gs_ns_uri_ehCovers , OPENGIS_ONT_GS_NS_URI "ehCovers" },
{ &uname_opengis_ont_gs_ns_uri_ehDisjoint , OPENGIS_ONT_GS_NS_URI "ehDisjoint" },
{ &uname_opengis_ont_gs_ns_uri_ehEquals , OPENGIS_ONT_GS_NS_URI "ehEquals" },
{ &uname_opengis_ont_gs_ns_uri_ehInside , OPENGIS_ONT_GS_NS_URI "ehInside" },
{ &uname_opengis_ont_gs_ns_uri_ehMeet , OPENGIS_ONT_GS_NS_URI "ehMeet" },
{ &uname_opengis_ont_gs_ns_uri_ehOverlap , OPENGIS_ONT_GS_NS_URI "ehOverlap" },
{ &uname_opengis_ont_gs_ns_uri_gmlLiteral , OPENGIS_ONT_GS_NS_URI "gmlLiteral" },
{ &uname_opengis_ont_gs_ns_uri_hasDefaultGeometry , OPENGIS_ONT_GS_NS_URI "hasDefaultGeometry" },
{ &uname_opengis_ont_gs_ns_uri_hasGeometry , OPENGIS_ONT_GS_NS_URI "hasGeometry" },
{ &uname_opengis_ont_gs_ns_uri_hasSerialization , OPENGIS_ONT_GS_NS_URI "hasSerialization" },
{ &uname_opengis_ont_gs_ns_uri_isEmpty , OPENGIS_ONT_GS_NS_URI "isEmpty" },
{ &uname_opengis_ont_gs_ns_uri_isSimple , OPENGIS_ONT_GS_NS_URI "isSimple" },
{ &uname_opengis_ont_gs_ns_uri_rcc8dc , OPENGIS_ONT_GS_NS_URI "rcc8dc" },
{ &uname_opengis_ont_gs_ns_uri_rcc8ec , OPENGIS_ONT_GS_NS_URI "rcc8ec" },
{ &uname_opengis_ont_gs_ns_uri_rcc8eq , OPENGIS_ONT_GS_NS_URI "rcc8eq" },
{ &uname_opengis_ont_gs_ns_uri_rcc8ntpp , OPENGIS_ONT_GS_NS_URI "rcc8ntpp" },
{ &uname_opengis_ont_gs_ns_uri_rcc8ntppi , OPENGIS_ONT_GS_NS_URI "rcc8ntppi" },
{ &uname_opengis_ont_gs_ns_uri_rcc8po , OPENGIS_ONT_GS_NS_URI "rcc8po" },
{ &uname_opengis_ont_gs_ns_uri_rcc8tpp , OPENGIS_ONT_GS_NS_URI "rcc8tpp" },
{ &uname_opengis_ont_gs_ns_uri_rcc8tppi , OPENGIS_ONT_GS_NS_URI "rcc8tppi" },
{ &uname_opengis_ont_gs_ns_uri_sfContains , OPENGIS_ONT_GS_NS_URI "sfContains" },
{ &uname_opengis_ont_gs_ns_uri_sfCrosses , OPENGIS_ONT_GS_NS_URI "sfCrosses" },
{ &uname_opengis_ont_gs_ns_uri_sfDisjoint , OPENGIS_ONT_GS_NS_URI "sfDisjoint" },
{ &uname_opengis_ont_gs_ns_uri_sfEquals , OPENGIS_ONT_GS_NS_URI "sfEquals" },
{ &uname_opengis_ont_gs_ns_uri_sfIntersects , OPENGIS_ONT_GS_NS_URI "sfIntersects" },
{ &uname_opengis_ont_gs_ns_uri_sfOverlaps , OPENGIS_ONT_GS_NS_URI "sfOverlaps" },
{ &uname_opengis_ont_gs_ns_uri_sfTouches , OPENGIS_ONT_GS_NS_URI "sfTouches" },
{ &uname_opengis_ont_gs_ns_uri_sfWithin , OPENGIS_ONT_GS_NS_URI "sfWithin" },
{ &uname_opengis_ont_gs_ns_uri_spatialDimension , OPENGIS_ONT_GS_NS_URI "spatialDimension" },
{ &uname_opengis_ont_gs_ns_uri_wktLiteral , OPENGIS_ONT_GS_NS_URI "wktLiteral" },
{ &uname_opengis_ont_sf_ns_uri , OPENGIS_ONT_SF_NS_URI },
{ &uname_false , "false" },
{ &uname_lang , "lang" },
{ &uname_nil , "nil" },
{ &uname_nodeID_ns , "nodeID://" },
{ &uname_nodeID_ns_0 , "nodeID://0" },
{ &uname_nodeID_ns_8192 , "nodeID://8192" },
{ &uname_rdf_ns_uri , RDF_NS_URI },
{ &uname_rdf_ns_uri_Description , RDF_NS_URI "Description" },
{ &uname_rdf_ns_uri_ID , RDF_NS_URI "ID" },
{ &uname_rdf_ns_uri_RDF , RDF_NS_URI "RDF" },
{ &uname_rdf_ns_uri_Seq , RDF_NS_URI "Seq" },
{ &uname_rdf_ns_uri_Statement , RDF_NS_URI "Statement" },
{ &uname_rdf_ns_uri_XMLLiteral , RDF_NS_URI "XMLLiteral" },
{ &uname_rdf_ns_uri_about , RDF_NS_URI "about" },
{ &uname_rdf_ns_uri_first , RDF_NS_URI "first" },
{ &uname_rdf_ns_uri_li , RDF_NS_URI "li" },
{ &uname_rdf_ns_uri_nil , RDF_NS_URI "nil" },
{ &uname_rdf_ns_uri_nodeID , RDF_NS_URI "nodeID" },
{ &uname_rdf_ns_uri_object , RDF_NS_URI "object" },
{ &uname_rdf_ns_uri_predicate , RDF_NS_URI "predicate" },
{ &uname_rdf_ns_uri_resource , RDF_NS_URI "resource" },
{ &uname_rdf_ns_uri_subject , RDF_NS_URI "subject" },
{ &uname_rdf_ns_uri_rest , RDF_NS_URI "rest" },
{ &uname_rdf_ns_uri_type , RDF_NS_URI "type" },
{ &uname_rdf_ns_uri_datatype , RDF_NS_URI "datatype" },
{ &uname_rdf_ns_uri_parseType , RDF_NS_URI "parseType" },
{ &uname_rdf_ns_uri_value , RDF_NS_URI "value" },
{ &uname_rdfdf_ns_uri , RDFDF_NS_URI },
{ &uname_rdfdf_ns_uri_default , RDFDF_NS_URI "default" },
{ &uname_rdfdf_ns_uri_default_nullable , RDFDF_NS_URI "default-nullable" },
{ &uname_rdfdf_ns_uri_default_iid , RDFDF_NS_URI "default-iid" },
{ &uname_rdfdf_ns_uri_default_iid_nullable , RDFDF_NS_URI "default-iid-nullable" },
{ &uname_space , "space" },
{ &uname_sql_ns_uri , OPENLINKSW_SQL_NS_URI },
{ &uname_swap_reify_ns_uri , SWAP_REIFY_NS_URI },
{ &uname_swap_reify_ns_uri_statement , SWAP_REIFY_NS_URI "statement" },
{ &uname_true , "true" },
{ &uname_virtrdf_ns_uri , VIRTRDF_NS_URI },
{ &uname_virtrdf_ns_uri_DefaultQuadMap , VIRTRDF_NS_URI "DefaultQuadMap" },
{ &uname_virtrdf_ns_uri_DefaultQuadStorage , VIRTRDF_NS_URI "DefaultQuadStorage" },
{ &uname_virtrdf_ns_uri_DefaultServiceMap , VIRTRDF_NS_URI "DefaultServiceMap" },
{ &uname_virtrdf_ns_uri_DefaultServiceStorage , VIRTRDF_NS_URI "DefaultServiceStorage" },
{ &uname_virtrdf_ns_uri_DefaultSparul11Target , VIRTRDF_NS_URI "DefaultSparul11Target" },
{ &uname_virtrdf_ns_uri_Geometry , VIRTRDF_NS_URI "Geometry" },
{ &uname_virtrdf_ns_uri_PrivateGraphs , VIRTRDF_NS_URI "PrivateGraphs" },
{ &uname_virtrdf_ns_uri_QuadMap , VIRTRDF_NS_URI "QuadMap" },
{ &uname_virtrdf_ns_uri_QuadMapFormat , VIRTRDF_NS_URI "QuadMapFormat" },
{ &uname_virtrdf_ns_uri_QuadStorage , VIRTRDF_NS_URI "QuadStorage" },
{&uname_virtrdf_ns_uri_RdfDebuggerSingletone, VIRTRDF_NS_URI "RdfDebuggerSingletone"},
{ &uname_virtrdf_ns_uri_SparqlMacroLibrary , VIRTRDF_NS_URI "SparqlMacroLibrary" },
{ &uname_virtrdf_ns_uri_SyncToQuads , VIRTRDF_NS_URI "SyncToQuads" },
{ &uname_virtrdf_ns_uri_array_of_any , VIRTRDF_NS_URI "array-of-any" },
{ &uname_virtrdf_ns_uri_array_of_string , VIRTRDF_NS_URI "array-of-string" },
{ &uname_virtrdf_ns_uri_bitmask , VIRTRDF_NS_URI "bitmask" },
{ &uname_virtrdf_ns_uri_bnode_base , VIRTRDF_NS_URI "bnode-base" },
{ &uname_virtrdf_ns_uri_bnode_label , VIRTRDF_NS_URI "bnode-label" },
{ &uname_virtrdf_ns_uri_bnode_row , VIRTRDF_NS_URI "bnode-row" },
{ &uname_virtrdf_ns_uri_dialect , VIRTRDF_NS_URI "dialect" },
{ &uname_virtrdf_ns_uri_dialect_exceptions , VIRTRDF_NS_URI "dialect-exceptions" },
{ &uname_virtrdf_ns_uri_isSpecialPredicate , VIRTRDF_NS_URI "isSpecialPredicate" },
{ &uname_virtrdf_ns_uri_isSubclassOf , VIRTRDF_NS_URI "isSubclassOf" },
{ &uname_virtrdf_ns_uri_loadAs , VIRTRDF_NS_URI "loadAs" },
{ &uname_virtrdf_ns_uri_namespace_base , VIRTRDF_NS_URI "namespace-base" },
{ &uname_virtrdf_ns_uri_namespace_iri , VIRTRDF_NS_URI "namespace-iri" },
{ &uname_virtrdf_ns_uri_namespace_prefix , VIRTRDF_NS_URI "namespace-prefix" },
{ &uname_virtrdf_ns_uri_namespace_row , VIRTRDF_NS_URI "namespace-row" },
{ &uname_virtrdf_ns_uri_rdf_repl_all , VIRTRDF_NS_URI "rdf_repl_all" },
{ &uname_virtrdf_ns_uri_rdf_repl_graph_group , VIRTRDF_NS_URI "rdf_repl_graph_group" },
{ &uname_virtrdf_ns_uri_rdf_repl_world , VIRTRDF_NS_URI "rdf_repl_world" },
{ &uname_xhv_ns_uri , XHV_NS_URI },
{ &uname_xhv_ns_uri_alternate , XHV_NS_URI "alternate" },
{ &uname_xhv_ns_uri_appendix , XHV_NS_URI "appendix" },
{ &uname_xhv_ns_uri_bookmark , XHV_NS_URI "bookmark" },
{ &uname_xhv_ns_uri_chapter , XHV_NS_URI "chapter" },
{ &uname_xhv_ns_uri_cite , XHV_NS_URI "cite" },
{ &uname_xhv_ns_uri_contents , XHV_NS_URI "contents" },
{ &uname_xhv_ns_uri_copyright , XHV_NS_URI "copyright" },
{ &uname_xhv_ns_uri_first , XHV_NS_URI "first" },
{ &uname_xhv_ns_uri_glossary , XHV_NS_URI "glossary" },
{ &uname_xhv_ns_uri_help , XHV_NS_URI "help" },
{ &uname_xhv_ns_uri_icon , XHV_NS_URI "icon" },
{ &uname_xhv_ns_uri_index , XHV_NS_URI "index" },
{ &uname_xhv_ns_uri_last , XHV_NS_URI "last" },
{ &uname_xhv_ns_uri_license , XHV_NS_URI "license" },
{ &uname_xhv_ns_uri_meta , XHV_NS_URI "meta" },
{ &uname_xhv_ns_uri_next , XHV_NS_URI "next" },
{ &uname_xhv_ns_uri_p3pv1 , XHV_NS_URI "p3pv1" },
{ &uname_xhv_ns_uri_prev , XHV_NS_URI "prev" },
{ &uname_xhv_ns_uri_role , XHV_NS_URI "role" },
{ &uname_xhv_ns_uri_section , XHV_NS_URI "section" },
{ &uname_xhv_ns_uri_start , XHV_NS_URI "start" },
{ &uname_xhv_ns_uri_stylesheet , XHV_NS_URI "stylesheet" },
{ &uname_xhv_ns_uri_subsection , XHV_NS_URI "subsection" },
{ &uname_xhv_ns_uri_up , XHV_NS_URI "up" },
{ &uname_xml , "xml" },
{ &uname_xmlns , "xmlns" },
{ &uname_xml_colon_base , "xml:base" },
{ &uname_xml_colon_lang , "xml:lang" },
{ &uname_xml_colon_space , "xml:space" },
{ &uname_xml_ns_uri , XML_NS_URI },
{ &uname_xml_ns_uri_colon_base , XML_NS_URI ":base" },
{ &uname_xml_ns_uri_colon_lang , XML_NS_URI ":lang" },
{ &uname_xml_ns_uri_colon_space , XML_NS_URI ":space" },
{ &uname_xmlschema_ns_uri , XMLSCHEMA_NS_URI },
{ &uname_xmlschema_ns_uri_hash , XMLSCHEMA_NS_URI "#" },
{ &uname_xmlschema_ns_uri_hash_ENTITY , XMLSCHEMA_NS_URI "#ENTITY" },
{ &uname_xmlschema_ns_uri_hash_ENTITIES , XMLSCHEMA_NS_URI "#ENTITIES" },
{ &uname_xmlschema_ns_uri_hash_ID , XMLSCHEMA_NS_URI "#ID" },
{ &uname_xmlschema_ns_uri_hash_IDREF , XMLSCHEMA_NS_URI "#IDREF" },
{ &uname_xmlschema_ns_uri_hash_IDREFS , XMLSCHEMA_NS_URI "#IDREFS" },
{ &uname_xmlschema_ns_uri_hash_NCName , XMLSCHEMA_NS_URI "#NCName" },
{ &uname_xmlschema_ns_uri_hash_Name , XMLSCHEMA_NS_URI "#Name" },
{ &uname_xmlschema_ns_uri_hash_NMTOKEN , XMLSCHEMA_NS_URI "#NMTOKEN" },
{ &uname_xmlschema_ns_uri_hash_NMTOKENS , XMLSCHEMA_NS_URI "#NMTOKENS" },
{ &uname_xmlschema_ns_uri_hash_NOTATION , XMLSCHEMA_NS_URI "#NOTATION" },
{ &uname_xmlschema_ns_uri_hash_QName , XMLSCHEMA_NS_URI "#QName" },
{ &uname_xmlschema_ns_uri_hash_any , XMLSCHEMA_NS_URI "#any" },
{ &uname_xmlschema_ns_uri_hash_anyAtomicType , XMLSCHEMA_NS_URI "#anyAtomicType" },
{ &uname_xmlschema_ns_uri_hash_anySimpleType , XMLSCHEMA_NS_URI "#anySimpleType" },
{ &uname_xmlschema_ns_uri_hash_anyType , XMLSCHEMA_NS_URI "#anyType" },
{ &uname_xmlschema_ns_uri_hash_anyURI , XMLSCHEMA_NS_URI "#anyURI" },
{ &uname_xmlschema_ns_uri_hash_base64Binary , XMLSCHEMA_NS_URI "#base64Binary" },
{ &uname_xmlschema_ns_uri_hash_boolean , XMLSCHEMA_NS_URI "#boolean" },
{ &uname_xmlschema_ns_uri_hash_byte , XMLSCHEMA_NS_URI "#byte" },
{ &uname_xmlschema_ns_uri_hash_date , XMLSCHEMA_NS_URI "#date" },
{ &uname_xmlschema_ns_uri_hash_dateTime , XMLSCHEMA_NS_URI "#dateTime" },
{ &uname_xmlschema_ns_uri_hash_dateTimeStamp , XMLSCHEMA_NS_URI "#dateTimeStamp" },
{ &uname_xmlschema_ns_uri_hash_dayTimeDuration , XMLSCHEMA_NS_URI "#dayTimeDuration" },
{ &uname_xmlschema_ns_uri_hash_decimal , XMLSCHEMA_NS_URI "#decimal" },
{ &uname_xmlschema_ns_uri_hash_double , XMLSCHEMA_NS_URI "#double" },
{ &uname_xmlschema_ns_uri_hash_duration , XMLSCHEMA_NS_URI "#duration" },
{ &uname_xmlschema_ns_uri_hash_float , XMLSCHEMA_NS_URI "#float" },
{ &uname_xmlschema_ns_uri_hash_gDay , XMLSCHEMA_NS_URI "#gDay" },
{ &uname_xmlschema_ns_uri_hash_gMonth , XMLSCHEMA_NS_URI "#gMonth" },
{ &uname_xmlschema_ns_uri_hash_gMonthDay , XMLSCHEMA_NS_URI "#gMonthDay" },
{ &uname_xmlschema_ns_uri_hash_gYear , XMLSCHEMA_NS_URI "#gYear" },
{ &uname_xmlschema_ns_uri_hash_gYearMonth , XMLSCHEMA_NS_URI "#gYearMonth" },
{ &uname_xmlschema_ns_uri_hash_hexBinary , XMLSCHEMA_NS_URI "#hexBinary" },
{ &uname_xmlschema_ns_uri_hash_int , XMLSCHEMA_NS_URI "#int" },
{ &uname_xmlschema_ns_uri_hash_integer , XMLSCHEMA_NS_URI "#integer" },
{ &uname_xmlschema_ns_uri_hash_language , XMLSCHEMA_NS_URI "#language" },
{ &uname_xmlschema_ns_uri_hash_long , XMLSCHEMA_NS_URI "#long" },
{ &uname_xmlschema_ns_uri_hash_negativeInteger , XMLSCHEMA_NS_URI "#negativeInteger" },
{ &uname_xmlschema_ns_uri_hash_nonNegativeInteger , XMLSCHEMA_NS_URI "#nonNegativeInteger" },
{ &uname_xmlschema_ns_uri_hash_nonPositiveInteger , XMLSCHEMA_NS_URI "#nonPositiveInteger" },
{ &uname_xmlschema_ns_uri_hash_normalizedString , XMLSCHEMA_NS_URI "#normalizedString" },
{ &uname_xmlschema_ns_uri_hash_positiveInteger , XMLSCHEMA_NS_URI "#positiveInteger" },
{ &uname_xmlschema_ns_uri_hash_short , XMLSCHEMA_NS_URI "#short" },
{ &uname_xmlschema_ns_uri_hash_string , XMLSCHEMA_NS_URI "#string" },
{ &uname_xmlschema_ns_uri_hash_time , XMLSCHEMA_NS_URI "#time" },
{ &uname_xmlschema_ns_uri_hash_token , XMLSCHEMA_NS_URI "#token" },
{ &uname_xmlschema_ns_uri_hash_unsignedByte , XMLSCHEMA_NS_URI "#unsignedByte" },
{ &uname_xmlschema_ns_uri_hash_unsignedInt , XMLSCHEMA_NS_URI "#unsignedInt" },
{ &uname_xmlschema_ns_uri_hash_unsignedLong , XMLSCHEMA_NS_URI "#unsignedLong" },
{ &uname_xmlschema_ns_uri_hash_unsignedShort , XMLSCHEMA_NS_URI "#unsignedShort" },
{ &uname_xmlschema_ns_uri_hash_yearMonthDuration , XMLSCHEMA_NS_URI "#yearMonthDuration" },
{NULL, NULL}
};
uname_const_decl_t *tail = uname_const_decls;
while (NULL != tail->var_ptr)
{
//UNAME_IT (tail->var_ptr[0], tail->text);
tail++;
}
for (ctr = 0; ctr < (sizeof (unames_colon_number) / sizeof (caddr_t)); ctr++)
{
char tmp[15];
sprintf (tmp, ":%d", ctr);
// UNAME_IT((unames_colon_number[ctr]), tmp);
}
}
|
andywx/agensgraph
|
src/backend/parser/dkpool.h
|
/*
* dkpool.h
*
* Created on: 2019年11月21日
* Author: liu
*/
#ifndef SRC_BACKEND_PARSER_DKPOOL_H_
#define SRC_BACKEND_PARSER_DKPOOL_H_
/*
* Dkpool.h
*
* $Id$
*
* Temp memory pool for objects that should be allocated one by one but freed
* together.
*
* This file is part of the OpenLink Software Virtuoso Open-Source (VOS)
* project.
*
* Copyright (C) 1998-2019 OpenLink Software
*
* This project is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; only version 2 of the License, dated June 1991.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#include"sparql.h"
#include"sparql_l.h"
#include <stdio.h>
#include<memory.h>
typedef struct mem_pool_s mem_pool_t;
typedef void *box_t;
typedef long long int int64;
typedef int64 boxint;
void mp_free (mem_pool_t * mp);
void mp_free_large (mem_pool_t * mp, void * ptr);
void mp_cache_large (size_t sz, int n);
extern size_t mp_large_in_use;
extern size_t mp_max_large_in_use;
extern size_t mp_large_reserved;
extern size_t mp_max_large_reserved;
extern size_t mp_large_reserve_limit;
extern size_t mp_large_soft_cap;
extern size_t mp_large_hard_cap;
#define DV_NON_BOX 101
#define DV_REFERENCE 206
#define DV_SHORT_STRING_SERIAL 181
#define DV_LONG_STRING 182
#define DV_SHORT_STRING 182
#define DV_UNAME 217
#define DV_XPATH_QUERY 232
#define ENOMEM 12
#define INT32_MAX (2147483647)
typedef signed int int32; /* == 32 bits */
# define uptrlong unsigned long
typedef caddr_t (*box_copy_f) (caddr_t box);
typedef long long int64;
#define uint64 unsigned int64
#ifdef VALGRIND
#define LACERATED_POOL
#endif
#ifdef MALLOC_DEBUG
#define LACERATED_POOL
#endif
#define MP_LARGE_SOFT_CK (mp_large_soft_cap && mp_large_in_use > mp_large_soft_cap)
typedef struct mem_block_s mem_block_t;
typedef void mem_pool_size_cap_cbk_t (mem_pool_t *mp, void *cbk_env);
#ifdef LACERATED_POOL
struct mem_pool_s
{
int mp_fill;
int mp_size;
int mp_block_size;
caddr_t * mp_allocs;
size_t mp_bytes;
dk_hash_t mp_large;
resource_t ** mp_large_reuse;
dk_hash_t * mp_unames;
dk_set_t mp_trash; /* dk_alloc_box boxes that must be freed with the mp */
size_t mp_reserved;
size_t mp_max_bytes;
#if defined (DEBUG) || defined (MALLOC_DEBUG)
const char * mp_alloc_file;
int mp_alloc_line;
#endif
#if defined (MALLOC_DEBUG) | defined (VALGRIND)
dk_hash_t * mp_box_to_dc; /* debug to map a copied box to its owner dc in this mp */
const char * mp_list_alloc_file;
int mp_list_alloc_line;
#endif
mem_pool_size_cap_t mp_size_cap;
caddr_t mp_comment;
struct TLSF_struct * mp_tlsf;
};
#else
typedef void (*rc_destr_t) (void *item);
typedef void *(*rc_constr_t) (void *cdata);
typedef struct mutex_s dk_mutex_t;
#endif
#if defined (DEBUG) || defined (MALLOC_DEBUG)
extern mem_pool_t *dbg_mem_pool_alloc (const char *file, int line);
#define mem_pool_alloc() dbg_mem_pool_alloc (__FILE__, __LINE__)
#endif
void * mp_large_alloc (mem_pool_t * mp, size_t sz);
void mp_set_tlsf (mem_pool_t * mp, size_t sz);
#ifdef MALLOC_DEBUG
extern caddr_t dbg_mp_alloc_box (const char *file, int line, mem_pool_t * mp, size_t len, dtp_t dtp);
extern caddr_t dbg_mp_alloc_box_ni (const char *file, int line, mem_pool_t * mp, int len, dtp_t dtp);
extern caddr_t dbg_mp_box_string (const char *file, int line, mem_pool_t * mp, const char *str);
extern caddr_t dbg_mp_box_substr (const char *file, int line, mem_pool_t * mp, ccaddr_t str, int n1, int n2);
extern caddr_t dbg_mp_box_dv_short_nchars (const char *file, int line, mem_pool_t * mp, const char *str, size_t len);
extern caddr_t dbg_mp_box_dv_short_concat (const char *file, int line, mem_pool_t * mp, ccaddr_t str1, ccaddr_t str2);
extern caddr_t dbg_mp_box_dv_short_strconcat (const char *file, int line, mem_pool_t * mp, const char *str1, const char *str2);
extern caddr_t dbg_mp_box_dv_uname_string (const char *file, int line, mem_pool_t * mp, const char *str);
extern caddr_t dbg_mp_box_dv_uname_nchars (const char *file, int line, mem_pool_t * mp, const char *str, size_t len);
extern caddr_t dbg_mp_box_copy (const char *file, int line, mem_pool_t * mp, caddr_t box);
extern caddr_t dbg_mp_box_copy_tree (const char *file, int line, mem_pool_t * mp, caddr_t box);
extern caddr_t dbg_mp_full_box_copy_tree (const char *file, int line, mem_pool_t * mp, caddr_t box);
extern caddr_t dbg_mp_box_num (const char *file, int line, mem_pool_t * mp, boxint num);
extern caddr_t dbg_mp_box_iri_id (const char *file, int line, mem_pool_t * mp, iri_id_t num);
extern caddr_t dbg_mp_box_double (const char *file, int line, mem_pool_t * mp, double num);
extern caddr_t dbg_mp_box_float (const char *file, int line, mem_pool_t * mp, float num);
#ifndef _USRDLL
#ifndef EXPORT_GATE
#define mp_alloc_box(mp,len,dtp) dbg_mp_alloc_box (__FILE__, __LINE__, (mp), (len), (dtp))
#define mp_alloc_box_ni(mp,len,dtp) dbg_mp_alloc_box_ni (__FILE__, __LINE__, (mp), (len), (dtp))
#define mp_box_string(mp, str) dbg_mp_box_string (__FILE__, __LINE__, (mp), (str))
#define mp_box_substr(mp, str, n1, n2) dbg_mp_box_substr (__FILE__, __LINE__, (mp), (str), (n1), (n2))
#define mp_box_dv_short_nchars(mp, str, len) dbg_mp_box_dv_short_nchars (__FILE__, __LINE__, (mp), (str), (len))
#define mp_box_dv_short_concat(mp, str1, str2) dbg_mp_box_dv_short_concat (__FILE__, __LINE__, (mp), (str1), (str2))
#define mp_box_dv_short_strconcat(mp, str1, str2) dbg_mp_box_dv_short_strconcat (__FILE__, __LINE__, (mp), (str1), (str2))
#define mp_box_dv_uname_string(mp, str) dbg_mp_box_dv_uname_string (__FILE__, __LINE__, (mp), (str))
#define mp_box_dv_uname_nchars(mp, str, len) dbg_mp_box_dv_uname_nchars (__FILE__, __LINE__, (mp), (str), (len))
#define mp_box_copy(mp, box) dbg_mp_box_copy (__FILE__, __LINE__, (mp), (box))
#define mp_box_copy_tree(mp, box) dbg_mp_box_copy_tree (__FILE__, __LINE__, (mp), (box))
#define mp_full_box_copy_tree(mp, box) dbg_mp_full_box_copy_tree (__FILE__, __LINE__, (mp), (box))
#define mp_box_num(mp, num) dbg_mp_box_num (__FILE__, __LINE__, (mp), (num))
#define mp_box_iri_id(mp, num) dbg_mp_box_iri_id (__FILE__, __LINE__, (mp), (num))
#define mp_box_double(mp, num) dbg_mp_box_double (__FILE__, __LINE__, (mp), (num))
#define mp_box_float(mp, num) dbg_mp_box_float (__FILE__, __LINE__, (mp), (num))
#endif
#endif
#endif
#ifdef LACERATED_POOL
void mp_alloc_box_assert (mem_pool_t * mp, caddr_t box);
#else
#define mp_alloc_box_assert(mp,box) ;
#endif
caddr_t *mp_list (mem_pool_t * mp, long n, ...);
#define mp_alloc(mp, n) mp_alloc_box (mp, n, DV_CUSTOM)
#define THR_TMP_POOL ((mem_pool_t *) THREAD_CURRENT_THREAD->thr_tmp_pool)
#define SET_THR_TMP_POOL(v) (THREAD_CURRENT_THREAD->thr_tmp_pool = (void*) v)
#ifdef DEBUG /* Not MALLOC_DEBUG */
#define MP_START() \
do { \
mem_pool_t *thread_mem_pool = THR_TMP_POOL; \
if (thread_mem_pool != NULL) \
GPF_T1 ("MP reallocated"); \
SET_THR_TMP_POOL (dbg_mem_pool_alloc (__FILE__, __LINE__)); \
} while (0)
#else
#define MP_START() \
do { \
if (THR_TMP_POOL != NULL) \
GPF_T1 ("MP reallocated"); \
SET_THR_TMP_POOL (mem_pool_alloc ()); \
} while (0)
#endif
#define MP_DONE() \
do { \
mp_free (THR_TMP_POOL); \
SET_THR_TMP_POOL (NULL); \
} while (0)
#ifdef _DEBUG
#define mp_box_tag_modify_impl(box,new_tag) \
do { \
box_tag_aux((box)) = (new_tag); \
} while (0)
#else
#define mp_box_tag_modify_impl(box,new_tag) (box_tag_aux((box)) = (new_tag))
#endif
#ifdef MALLOC_DEBUG
#define mp_box_tag_modify(box,new_tag) \
do { \
if (DV_UNAME == new_tag) \
GPF_T1 ("Can't make UNAME by mp_box_tag_modify"); \
if (DV_UNAME == box_tag_aux(box)) \
GPF_T1 ("Can't alter UNAME by mp_box_tag_modify"); \
if (DV_REFERENCE == new_tag) \
GPF_T1 ("Can't make REFERENCE by mp_box_tag_modify"); \
if (DV_REFERENCE == box_tag_aux(box)) \
GPF_T1 ("Can't alter REFERENCE by mp_box_tag_modify"); \
if (TAG_FREE == new_tag) \
GPF_T1 ("Can't make TAG_FREE box by mp_box_tag_modify"); \
if (TAG_FREE == box_tag_aux(box)) \
GPF_T1 ("Can't alter TAG_FREE by mp_box_tag_modify"); \
if (TAG_BAD == new_tag) \
GPF_T1 ("Can't make TAG_BAD box by mp_box_tag_modify"); \
if (TAG_BAD == box_tag_aux(box)) \
GPF_T1 ("Can't alter TAG_BAD by mp_box_tag_modify"); \
mp_box_tag_modify_impl(box,new_tag); \
} while (0);
#else
#define mp_box_tag_modify(box,new_tag) mp_box_tag_modify_impl(box,new_tag)
#endif
#define dbg_t_alloc_box(len,dtp) dbg_mp_alloc_box (DBG_ARGS THR_TMP_POOL, (len), (dtp))
#define dbg_t_box_string(str) dbg_mp_box_string (DBG_ARGS THR_TMP_POOL, (str))
#define dbg_t_box_substr(str,n1,n2) dbg_mp_box_substr (DBG_ARGS THR_TMP_POOL, (str), (n1), (n2))
#define dbg_t_box_dv_short_nchars(str,len) dbg_mp_box_dv_short_nchars (DBG_ARGS THR_TMP_POOL, (str), (len))
#define dbg_t_box_dv_short_concat(str1,str2) dbg_mp_box_dv_short_concat (DBG_ARGS THR_TMP_POOL, (str1), (str2))
#define dbg_t_box_dv_short_strconcat(str1,str2) dbg_mp_box_dv_short_strconcat (DBG_ARGS THR_TMP_POOL, (str1), (str2))
#define dbg_t_box_dv_uname_string(str) dbg_mp_box_dv_uname_string (DBG_ARGS THR_TMP_POOL, (str))
#define dbg_t_box_dv_uname_nchars(str,len) dbg_mp_box_dv_uname_nchars (DBG_ARGS THR_TMP_POOL, (str), (len))
#define dbg_t_box_copy(box) dbg_mp_box_copy (DBG_ARGS THR_TMP_POOL, (box))
#define dbg_t_box_copy_tree(box) dbg_mp_box_copy_tree (DBG_ARGS THR_TMP_POOL, (box))
#define dbg_t_full_box_copy_tree(box) dbg_mp_full_box_copy_tree (DBG_ARGS THR_TMP_POOL, (box))
#define t_alloc_box(len,dtp) mp_alloc_box (THR_TMP_POOL, (len), (dtp))
#define t_box_string(str) mp_box_string (THR_TMP_POOL, (str))
#define t_box_substr(str,n1,n2) mp_box_substr (THR_TMP_POOL, (str), (n1), (n2))
#define t_box_dv_short_nchars(str,len) mp_box_dv_short_nchars (THR_TMP_POOL, (str), (len))
#define t_box_dv_short_concat(str1,str2) mp_box_dv_short_concat (THR_TMP_POOL, (str1), (str2))
#define t_box_dv_short_strconcat(str1,str2) mp_box_dv_short_strconcat (THR_TMP_POOL, (str1), (str2))
#define t_box_dv_uname_string(str) mp_box_dv_uname_string (THR_TMP_POOL, (str))
#define t_box_dv_uname_nchars(str,len) mp_box_dv_uname_nchars (THR_TMP_POOL, (str), (len))
#define t_box_copy(box) mp_box_copy (THR_TMP_POOL, (box))
#define t_box_copy_tree(box) mp_box_copy_tree (THR_TMP_POOL, (box))
#define t_full_box_copy_tree(box) mp_full_box_copy_tree (THR_TMP_POOL, (box))
#define t_alloc_list(n) ((caddr_t *)t_alloc_box ((n) * sizeof (caddr_t), DV_ARRAY_OF_POINTER))
extern caddr_t *t_list_memcpy (long n, ccaddr_t *src);
extern caddr_t *t_list_concat_tail (caddr_t list, long n, ...);
extern caddr_t *t_list_concat (caddr_t list1, caddr_t list2);
extern caddr_t *t_list_remove_nth (caddr_t list, int pos);
extern caddr_t *t_list_insert_before_nth (caddr_t list, caddr_t new_item, int pos);
extern caddr_t *t_list_insert_many_before_nth (caddr_t list, caddr_t * new_items, int ins_count, int pos);
caddr_t *t_sc_list (long n, ...);
#define t_NEW_DB_NULL t_alloc_box (0, DV_DB_NULL)
#ifdef MALLOC_DEBUG
caddr_t dbg_t_box_num (const char *file, int line, boxint box);
caddr_t dbg_t_box_num_and_zero (const char *file, int line, boxint box);
box_t dbg_t_box_double (const char *file, int line, double d);
box_t dbg_t_box_float (const char *file, int line, float d);
caddr_t dbg_t_box_iri_id (const char *file, int line, int64 n);
#define t_box_num(box) dbg_t_box_num (__FILE__, __LINE__, (box))
#define t_box_double(d) dbg_t_box_double (__FILE__, __LINE__, (d))
#define t_box_float(d) dbg_t_box_float (__FILE__, __LINE__, (d))
#define t_box_iri_id(d) dbg_t_box_iri_id (__FILE__, __LINE__, (d))
#define t_box_num_and_zero(box) dbg_t_box_num_and_zero (__FILE__, __LINE__, (box))
extern caddr_t *t_list_impl (long n, ...);
typedef caddr_t *(*t_list_impl_ptr_t) (long n, ...);
extern t_list_impl_ptr_t t_list_cock (const char *file, int line);
#define t_list (t_list_cock (__FILE__, __LINE__))
#else
caddr_t t_box_num (boxint box);
caddr_t t_box_num_and_zero (boxint box);
box_t t_box_double (double d);
box_t t_box_float (float d);
caddr_t t_box_iri_id (int64 n);
extern caddr_t *t_list (long n, ...);
#endif
#define DV_CUSTOM 203
#define t_alloc(sz) t_alloc_box ((sz), DV_CUSTOM)
#define t_box_num_nonull t_box_num_and_zero
#define t_box_dv_short_string t_box_string
#define TNEW(dt, v) \
dt * v = (dt *) t_alloc (sizeof (dt))
#define t_NEW_VARZ(dt, v) \
TNEW(dt, v); \
memset (v, 0, sizeof (dt))
#define t_NEW_VAR(dt, v) \
TNEW(dt, v)
#ifdef MALLOC_DEBUG
void dbg_mp_set_push (const char *file, int line, mem_pool_t * mp, dk_set_t * set, void *elt);
dk_set_t dbg_t_cons (const char *file, int line, void *car, dk_set_t cdr);
void dbg_t_set_push (const char *file, int line, dk_set_t * set, void *elt);
int dbg_t_set_pushnew (const char *file, int line, s_node_t ** set, void *item);
int dbg_t_set_push_new_string (const char *file, int line, s_node_t ** set, char *item);
void *dbg_t_set_pop (const char *file, int line, dk_set_t * set);
dk_set_t dbg_t_set_union (const char *file, int line, dk_set_t s1, dk_set_t s2);
dk_set_t dbg_t_set_intersect (const char *file, int line, dk_set_t s1, dk_set_t s2);
dk_set_t dbg_t_set_diff (const char *file, int line, dk_set_t s1, dk_set_t s2);
caddr_t *dbg_t_list_to_array (const char *file, int line, dk_set_t list);
caddr_t *dbg_t_revlist_to_array (const char *file, int line, dk_set_t list);
int dbg_t_set_delete (const char *file, int line, dk_set_t * set, void *item);
void * dbg_t_set_delete_nth (const char *file, int line, dk_set_t * set, int nth);
dk_set_t dbg_t_set_copy (const char *file, int line, dk_set_t s);
#define mp_set_push(mp,set,elt) dbg_mp_set_push (__FILE__, __LINE__, (mp), (set), (elt))
#define t_cons(car,cdr) dbg_t_cons (__FILE__, __LINE__, (car), (cdr))
#define t_set_push(set,elt) dbg_t_set_push (__FILE__, __LINE__, (set), (elt))
#define t_set_pushnew(set,item) dbg_t_set_pushnew (__FILE__, __LINE__, (set), (item))
#define t_set_push_new_string(set,item) dbg_t_set_push_new_string (__FILE__, __LINE__, (set), (item))
#define t_set_pop(set) dbg_t_set_pop (__FILE__, __LINE__, (set))
#define t_set_union(s1,s2) dbg_t_set_union (__FILE__, __LINE__, (s1), (s2))
#define t_set_intersect(s1,s2) dbg_t_set_intersect (__FILE__, __LINE__, (s1), (s2))
#define t_set_diff(s1,s2) dbg_t_set_diff (__FILE__, __LINE__, (s1), (s2))
#define t_list_to_array(list) dbg_t_list_to_array (__FILE__, __LINE__, (list))
#define t_revlist_to_array(list) dbg_t_revlist_to_array (__FILE__, __LINE__, (list))
#define t_set_delete(set,item) dbg_t_set_delete (__FILE__, __LINE__, (set), (item))
#define t_set_delete_nth(set,nth) dbg_t_set_delete_nth (__FILE__, __LINE__, (set), (nth))
#define t_set_copy(s) dbg_t_set_copy (__FILE__, __LINE__, (s))
#else
void mp_set_push (mem_pool_t * mp, dk_set_t * set, void *elt);
dk_set_t t_cons (void *car, dk_set_t cdr);
void t_set_push (dk_set_t * set, void *elt);
int t_set_pushnew (s_node_t ** set, void *item);
int t_set_push_new_string (s_node_t ** set, char *item);
void *t_set_pop (dk_set_t * set);
dk_set_t t_set_union (dk_set_t s1, dk_set_t s2);
dk_set_t t_set_intersect (dk_set_t s1, dk_set_t s2);
dk_set_t t_set_diff (dk_set_t s1, dk_set_t s2);
caddr_t *t_list_to_array (dk_set_t list);
caddr_t *t_revlist_to_array (dk_set_t list);
int t_set_delete (dk_set_t * set, void *item);
void * t_set_delete_nth (dk_set_t * set, int nth);
dk_set_t t_set_copy (dk_set_t s);
#endif
#define mp_set_nreverse(mp,s) dk_set_nreverse((s))
#define t_set_nreverse(s) dk_set_nreverse((s))
#define t_revlist_to_array_or_null(list) ((NULL != (list)) ? t_revlist_to_array ((list)) : NULL)
#ifdef MALLOC_DEBUG
void mp_check (mem_pool_t * mp);
void mp_check_tree (mem_pool_t * mp, box_t box);
#define t_check_tree(box) mp_check_tree (THR_TMP_POOL, (box))
#else
#define mp_check_tree(mp,box) ;
#define t_check_tree(box) ;
#endif
#ifdef _DKSYSTEM_H
caddr_t t_box_vsprintf (size_t buflen_eval, const char *format, va_list tail);
caddr_t t_box_vsprintf_uname (size_t buflen_eval, const char *format, va_list tail);
caddr_t t_box_sprintf (size_t buflen_eval, const char *format, ...)
#ifdef __GNUC__
__attribute__ ((format (printf, 2, 3)))
#endif
;
caddr_t t_box_sprintf_uname (size_t buflen_eval, const char *format, ...)
#ifdef __GNUC__
__attribute__ ((format (printf, 2, 3)))
#endif
;
#endif
void mp_trash (mem_pool_t * mp, caddr_t box);
#define mp_trash_push(mp,box) dk_set_push (&((mp)->mp_trash), (void *)(box))
#define t_trash_push(box) mp_trash_push(THR_TMP_POOL,box)
typedef caddr_t (*box_tmp_copy_f) (mem_pool_t * mp, caddr_t box);
extern box_tmp_copy_f box_tmp_copier[256];
#ifdef LACERATED_POOL
#define MP_BYTES(x, mp, len) { (x) = (void *)mp_alloc_box (mp, len, DV_NON_BOX); }
#else
#define MP_BYTES(x, mp, len2) \
{ \
int __len = ALIGN_8 (len2); \
mem_block_t * f = mp->mp_first; \
if (f && f->mb_fill + __len <= f->mb_size) \
{ \
*(void**)&(x) = (void *)(((char*)f) + f->mb_fill); \
f->mb_fill += __len; \
} \
else \
*(void**)&(x) = (void *)mp_alloc_box (mp, len2, DV_NON_BOX); \
}
#endif
#define MP_INT(x, mp, v, tag_word) \
{ \
MP_BYTES (x, mp, 16); \
x = ((char *)x) + 8; \
*(int64 *)x = v; \
((int64*)x)[-1] = tag_word; \
}
#define MP_DOUBLE(x, mp, v, tag_word) \
{ \
MP_BYTES (x, mp, 16); \
x = ((char *)x) + 8; \
*(double *)x = v; \
((int64*)x)[-1] = tag_word; \
}
#define MP_FLOAT(x, mp, v, tag_word) \
{ \
MP_BYTES (x, mp, 16); \
x = ((char *)x) + 8; \
*(float *)x = v; \
((int64*)x)[-1] = tag_word; \
}
typedef struct auto_pool_s
{
caddr_t ap_area;
int ap_size;
int ap_fill;
} auto_pool_t;
#define AUTO_POOL(n) \
int64 area[n]; \
auto_pool_t ap; \
ap.ap_area = (caddr_t) &area; \
ap.ap_fill = 0; \
ap.ap_size = sizeof (area); \
caddr_t ap_box_num (auto_pool_t * ap, int64 i);
caddr_t ap_alloc_box (auto_pool_t * ap, int n, dtp_t tag);
caddr_t *ap_list (auto_pool_t * apool, long n, ...);
caddr_t ap_box_iri_id (auto_pool_t * ap, int64 n);
extern caddr_t *t_list_nc (long n, ...);
#define WITHOUT_TMP_POOL \
{ \
mem_pool_t * __mp = THR_TMP_POOL; \
SET_THR_TMP_POOL (NULL);
#define END_WITHOUT_TMP_POOL \
SET_THR_TMP_POOL (__mp); \
}
#define NO_TMP_POOL \
if (THR_TMP_POOL) GPF_T1 ("not supposed to have a tmp pool in effect here");
#ifdef linux
#define HAVE_SYS_MMAN_H 1
#endif
void mm_cache_init (size_t sz, size_t min, size_t max, int steps, float step);
void* mm_large_alloc (size_t sz);
void mm_free_sized (void* ptr, size_t sz);
size_t mm_next_size (size_t n, int * nth);
size_t mm_cache_trim (size_t target_sz, int age_limit, int old_only);
extern size_t mp_block_size;
#if defined (DEBUG) || defined (MALLOC_DEBUG) || !defined(NDEBUG)
#define MP_MAP_CHECK
#endif
#ifdef MP_MAP_CHECK
extern dk_hash_t * mp_registered;
struct mutex_s
{
/* os specific handle */
#ifdef WITH_PTHREADS
#ifdef HAVE_SPINLOCK
#define mtx_mtx l.mtx
union {
pthread_mutex_t mtx;
pthread_spinlock_t spinl;
} l;
#else
pthread_mutex_t mtx_mtx;
#endif
#endif
void * mtx_handle;
#ifdef APP_SPIN
int mtx_spins;
#endif
#if defined (MTX_DEBUG) || defined (MTX_METER)
caddr_t mtx_name;
#endif
#ifdef MTX_DEBUG
thread_t * mtx_owner;
const char * mtx_entry_file;
int mtx_entry_line;
const char * mtx_leave_file;
int mtx_leave_line;
mtx_entry_check_t mtx_entry_check;
void * mtx_entry_check_cd;
#endif
#ifdef MTX_METER
long mtx_spin_waits;
long mtx_waits;
long mtx_enters;
long long mtx_wait_clocks;
#endif
int mtx_type;
};
typedef struct mutex_s dk_mutex_t;
extern dk_mutex_t mp_reg_mtx;
typedef struct dk_pool_4g {
unsigned char bits[128 * 1024];
} dk_pool_4g_t;
extern dk_pool_4g_t * dk_pool_map[256 * 256];
void mp_check_not_in_pool (int64 ptr);
#define ASSERT_NOT_IN_POOL(ptr) \
{ \
int64 __ptr = (int64)ptr; \
dk_pool_4g_t * map = dk_pool_map[__ptr >> 32]; \
if (map && map->bits[((uint32)__ptr) >> 15] & (1 << (((((uint32)__ptr) >> 12) & 0x7)))) \
mp_check_not_in_pool (__ptr); \
}
#else
#define ASSERT_NOT_IN_POOL(ptr)
#endif
int mp_reuse_large (mem_pool_t * mp, void * ptr);
int mp_reserve (mem_pool_t * mp, size_t inc);
void mp_comment (mem_pool_t * mp, const char * str1, const char * str2);
size_t mp_block_size_sc (size_t sz);
void * mp_mmap (size_t sz);
extern thread_t * thread_current (void);
extern numeric_t t_numeric_allocate (void); /* thread space dynamic allocation */
#endif /* SRC_BACKEND_PARSER_DKPOOL_H_ */
|
andywx/agensgraph
|
src/backend/parser/sparql_func.c
|
/*
* sparql_func.c
*
* Created on: 2019年11月14日
* Author: liu
*/
#include "sparql.h"
#include"sparql_l.h"
#include "sparql_p.h"
#include "sparql_func.h"
#include <ctype.h>
#include <stdio.h>
#include <stdarg.h>
uint32 dk_set_length(s_node_t *set) {
uint32 count;
for (count = 0; set; set = set->next)
count++;
return count;
}
void sparyyerror_impl (sparp_t *xpp, char *raw_text, const char *strg){
}
SPART **t_spartlist_concat (SPART **list1, SPART **list2){
}
void sparp_configure_storage_and_macro_libs (sparp_t *sparp){
}
SPART* spartlist (sparp_t *sparp, ptrlong length, ptrlong type, ...){
}
SPART *sparp_make_builtin_call (sparp_t *sparp, ptrlong bif_id, SPART **arguments){
}
void spar_error_if_unsupported_syntax_imp (sparp_t *sparp, int feature_in_use, const char *feature_name){
}
SPART *spar_gp_finalize (sparp_t *sparp, SPART **options){
}
SPART *spar_make_fake_action_solution (sparp_t *sparp){
}
SPART *spar_make_sparul_drop (sparp_t *sparp, SPART *graph_precode, int silent){
}
SPART *spar_make_sparul_create (sparp_t *sparp, SPART *graph_precode, int silent){
}
SPART *spar_make_sparul_load_service_data (sparp_t *sparp, SPART *proxy_iri_precode, SPART *service_iri_precode, int silent){
}
SPART *spar_make_sparul_load (sparp_t *sparp, SPART *graph_precode, SPART *src_precode, int silent){
}
SPART *spar_make_sparul_clear (sparp_t *sparp, SPART *graph_precode, int silent){
}
SPART *spar_make_top_or_special_case_from_wm (sparp_t *sparp, ptrlong subtype, SPART **retvals, SPART *wm ){
}
void spar_compose_retvals_of_modify (sparp_t *sparp, SPART *top, SPART *graph_to_patch, SPART *del_ctor_gp, SPART *ins_ctor_gp){
}
void spar_compose_retvals_of_insert_or_delete (sparp_t *sparp, SPART *top, SPART *graph_to_patch, SPART *ctor_gp){
}
SPART *spar_make_drop_macro_lib (sparp_t *sparp, SPART *sml_precode, int silent){
}
caddr_t spar_mkid (sparp_t * sparp, const char *prefix){
}
SPART *spar_make_blank_node (sparp_t *sparp, caddr_t name, int bracketed){
}
caddr_t sparp_expand_qname_prefix (sparp_t *sparp, caddr_t qname){
}
caddr_t sparp_expand_q_iri_ref (sparp_t *sparp, caddr_t ref){
}
SPART *spar_make_topmost_sparul_sql (sparp_t *sparp, SPART **actions){
}
void sparp_define (sparp_t *sparp, caddr_t param, ptrlong value_lexem_type, caddr_t value){
}
void spar_gp_init (sparp_t *sparp, ptrlong subtype){
}
SPART *spar_make_param_or_variable (sparp_t *sparp, caddr_t name){
}
void sparp_check_dm_arg_for_redecl (sparp_t *sparp, dk_set_t recent, caddr_t dm_arg_vname){
}
void sparp_make_defmacro_paramnames_from_template (sparp_t *sparp, SPART *defm){
}
void sparp_defmacro_finalize (sparp_t *sparp, SPART *body){
}
SPART *sparp_defmacro_init (sparp_t *sparp, caddr_t mname){
}
void sparp_defmacro_store (sparp_t *sparp, SPART *defm){
}
SPART *spar_make_qm_col_desc (sparp_t *sparp, SPART *col){
}
void spar_qm_add_aliased_table_or_sqlquery (sparp_t *sparp, caddr_t parent_qtable, caddr_t new_alias){
}
SPART *spar_make_qm_sql (sparp_t *sparp, const char *fname, SPART **fixed, SPART **named){
}
void sparp_jso_push_affected (sparp_t *sparp, ccaddr_t inst_iri){
}
void sparp_jso_push_deleted (sparp_t *sparp, ccaddr_t class_iri, ccaddr_t inst_iri){
}
void spar_qm_pop_bookmark (sparp_t *sparp){
}
void spar_qm_push_bookmark (sparp_t *sparp){
}
SPART *spar_make_vector_qm_sql (sparp_t *sparp, SPART **fixed){
}
SPART *spar_make_wm (sparp_t *sparp, SPART *pattern, SPART **groupings, SPART *having, SPART **order, SPART *limit, SPART *offset, SPART *binv){
}
void spar_gp_add_member (sparp_t *sparp, SPART *memb){
}
SPART *spar_default_sparul_target (sparp_t *sparp, const char *reason_to_use, int preliminary_call){
}
void spar_apply_fallback_default_graph (sparp_t *sparp, int target_fallback_first){
}
void spar_qm_add_text_literal (sparp_t *sparp, caddr_t ft_type, caddr_t ft_table_alias, SPART *ft_col, SPART **qmv_cols, SPART **options){
}
void spar_qm_add_table_filter (sparp_t *sparp, caddr_t tmpl){
}
void spar_qm_add_aliased_alias (sparp_t *sparp, caddr_t parent_alias, caddr_t new_alias){
}
SPART *spar_make_sparul_copymoveadd (sparp_t *sparp, ptrlong opcode, SPART *from_graph_precode, SPART *to_graph_precode, int silent){
}
int spar_ctor_uses_default_graph (SPART *ctor_gp){
}
void spar_compose_retvals_of_delete_from_wm (sparp_t *sparp, SPART *tree, SPART *graph_to_patch){
}
void sparp_make_and_push_new_graph_source (sparp_t *sparp, ptrlong subtype, SPART *iri_expn, SPART **options, int freeze_ignore_mask){
}
void spar_qm_push_local (sparp_t *sparp, int key, SPART *value, int can_overwrite){
}
void spar_qm_clean_locals (sparp_t *sparp){
}
SPART *spar_make_qm_value (sparp_t *sparp, caddr_t format_name, SPART **cols){
}
SPART *spar_qm_make_empty_mapping (sparp_t *sparp, caddr_t qm_id, SPART **options){
}
SPART *spar_qm_get_local (sparp_t *sparp, int key, int error_if_missing){
}
void spar_qm_pop_key (sparp_t *sparp, int key_to_pop){
}
SPART *spar_qm_make_real_mapping (sparp_t *sparp, caddr_t qm_id, SPART **options){
}
SPART *spar_make_variable (sparp_t *sparp, caddr_t name){
}
SPART *spar_add_propvariable (sparp_t *sparp, SPART *lvar, int opcode, SPART *verb_qname, int verb_lexem_type, caddr_t verb_lexem_text){
}
int sparp_namesake_macro_param (sparp_t *sparp, SPART *dm, caddr_t param_name){
}
SPART *spar_make_macropu (sparp_t *sparp, caddr_t name, ptrlong pos){
}
SPART *spar_make_funcall (sparp_t *sparp, int aggregate_mode, const char *funname, SPART **arguments){
}
SPART *spar_gp_add_triplelike (sparp_t *sparp, SPART *graph, SPART *subject, SPART *predicate, SPART *object, SPART **sinv_idx_and_qms, SPART **options, int banned_tricks){
}
SPART **spar_make_sources_like_top (sparp_t *sparp, ptrlong top_subtype){
}
SPART *spar_make_service_inv (sparp_t *sparp, SPART *endpoint, dk_set_t all_options, ptrlong permitted_syntax, ptrlong syntax_exceptions, SPART **sources, caddr_t sinv_storage_uri, int silent){
}
void spar_add_service_inv_to_sg (sparp_t *sparp, SPART *sinv){
}
SPART *spar_make_top (sparp_t *sparp, ptrlong subtype, SPART **retvals, SPART *pattern, SPART **groupings, SPART *having, SPART **order, SPART *limit, SPART *offset, SPART *binv){
}
void spar_env_pop (sparp_t *sparp){
}
SPART *spar_gp_finalize_with_subquery (sparp_t *sparp, SPART **options, SPART *subquery){
}
quad_storage_t *sparp_find_storage_by_name (sparp_t *sparp, ccaddr_t name){
}
SPART *spar_make_ppath (sparp_t *sparp, char subtype, SPART *part1, SPART *part2, ptrlong mincount, ptrlong maxcount){
}
void sparp_expand_top_retvals (sparp_t *sparp, SPART *query, int safely_copy_all_vars, dk_set_t binds_revlist){
}
void spar_verify_funcall_security (sparp_t *sparp, int *is_agg_ret, const char **fname_ptr, SPART **args){
}
SPART *spar_make_regex_or_like_or_eq (sparp_t *sparp, SPART *strg, SPART *regexpn){
}
void sparp_find_language_dialect_by_service (sparp_t *sparp, SPART *service_expn, int *dialect_ret, int *exceptions_ret){
}
caddr_t spar_unescape_strliteral (sparp_t *sparp, const char *sparyytext, int count_of_quotes, int mode){
}
void spar_error (sparp_t *sparp, const char *format, ...){
}
caddr_t spar_make_iri_from_template (sparp_t *sparp, caddr_t tmpl){
}
SPART *spar_compose_ctor_gp_from_where_gp (sparp_t *sparp, int subtype, SPART *where_gp, SPART *gtp){
}
void spar_compose_retvals_of_construct (sparp_t *sparp, SPART *top, SPART *ctor_gp, const char *formatter, const char *agg_formatter, const char *agg_mdata){
}
void spar_env_push (sparp_t *sparp){
}
void spar_gp_add_filter (sparp_t *sparp, SPART *filt, int filt_is_movable){
}
SPART *spar_gp_finalize_with_inline_data (sparp_t *sparp, SPART **vars, SPART ***rows){
}
void spar_gp_finalize_binds (sparp_t *sparp, dk_set_t bind_revlist){
}
SPART *spar_bind_prepare (sparp_t *sparp, SPART *expn, int bind_has_scalar_subqs){
}
SPART *spar_make_bindings_inv_with_fake_equivs (sparp_t *sparp, SPART **vars, SPART ***data_rows, SPART *wrapper_gp){
}
void sparp_validate_options_of_tree (sparp_t *sparp, SPART *tree, SPART **options){
}
SPART *sparp_make_qm_sqlcol (sparp_t *sparp, ptrlong type, caddr_t name){
}
void spar_change_sign (caddr_t *lit_ptr){
}
SPART *spar_make_typed_literal (sparp_t *sparp, caddr_t strg, caddr_t type, caddr_t lang){
}
void spar_gp_add_filters_for_named_graph (sparp_t *sparp){
}
SPART *sparp_make_macro_call (sparp_t *sparp, const char * funname, int call_is_explicit, SPART **arguments){
}
SPART *spar_find_defmacro_by_iri_or_fields (sparp_t *sparp, const char *mname, SPART **fields){
}
SPART *spar_make_topmost_qm_sql (sparp_t *sparp){
}
void ssg_find_formatter_by_name_and_subtype (ccaddr_t name, ptrlong subtype,
const char **ret_formatter, const char **ret_agg_formatter, const char **ret_agg_mdata ){
}
caddr_t dbg_mp_box_string (const char *file, int line, mem_pool_t * mp, const char *str){
}
/*
* Assign a string to a number
*/
int
stricmp (const char *s1, const char *s2)
{
int cmp;
while (*s1)
{
if ((cmp = toupper (*s1) - toupper (*s2)) != 0)
return cmp;
s1++;
s2++;
}
return (*s2) ? -1 : 0;
}
int
numeric_from_string (numeric_t n, const char *s)
{
}
dk_set_t
dk_set_nreverse (dk_set_t set)
{
dk_set_t next;
dk_set_t next2;
if (!set)
return NULL;
next = set->next;
set->next = NULL;
for (;;)
{
if (!next)
return set;
next2 = next->next;
next->next = set;
set = next;
next = next2;
}
}
void *
dk_set_get_keyword (dk_set_t set, const char *key_strg, void *dflt_val)
{
while (set)
{
if (!strcmp ((const char *) set->data, key_strg))
return set->next->data;
set = set->next->next;
}
return dflt_val;
}
dk_set_t
dk_set_conc (dk_set_t s1, dk_set_t s2)
{
}
int
dk_set_position (dk_set_t set, void *elt)
{
int nth = 0;
while (set)
{
if (set->data == elt)
return nth;
nth++;
set = set->next;
}
return -1;
}
box_t box_tag(ccaddr_t box)
{
return (*((const dtp_t *) &(((const unsigned char *)((box)))[-1])));
}
boxint
unbox (ccaddr_t box)
{
if (!IS_BOX_POINTER (box))
return (boxint) (ptrlong) box;
if (box_tag (box) == DV_LONG_INT)
return *(boxint *) box;
return (boxint) (ptrlong) box;
}
caddr_t
DBG_NAME(thr_get_error_code) (DBG_PARAMS thread_t *thr)
{
caddr_t ret = thr->thr_reset_code;
thr->thr_reset_code = NULL;
#ifdef ERR_DEBUG
fprintf (stderr, "thr_get_error_code (%p)=%p [%s]\n",
thr, ret, ret ? (ERROR_REPORT_P (ret) ? ((caddr_t *)ret)[2] : "<not found>") : "<none>");
#endif
#ifdef SIGNAL_DEBUG
if (ERROR_REPORT_P(ret))
log_error_report_event (ret, 0, "THR_GET at %s:%d", file, line);
#endif
return ret;
}
int BOX_ELEMENTS(caddr_t b){
return (box_length ((box_t) (b)) / sizeof (box_t));
}
int BOX_ELEMENTS_0(caddr_t b){
return ((NULL != (b)) ? BOX_ELEMENTS(b) : (size_t)0);
}
box_t
DBG_NAME (box_dv_uname_string) (DBG_PARAMS const char *string)
{
//return DBG_NAME (box_dv_uname_nchars) (DBG_ARGS string, strlen (string));
}
int
dk_free_tree (box_t box)
{
}
void
DBG_NAME(thr_set_error_code) (DBG_PARAMS thread_t *thr, caddr_t err)
{
#ifdef ERR_DEBUG
fprintf (stderr, "thr_set_error_code (%p, %p [%s]) -> free %p [%s]\n",
thr, err, err ? (ERROR_REPORT_P (err) ? ((caddr_t *)err)[2] : "<not found>") : "<none>",
thr->thr_reset_code, thr->thr_reset_code ? (ARRAYP (thr->thr_reset_code) ? ((caddr_t *)thr->thr_reset_code)[2] : "<not found>") : "<none>");
#endif
#ifdef SIGNAL_DEBUG
if (ERROR_REPORT_P(err))
log_error_report_event (err, 0, "THR_SET at %s:%d", file, line);
#endif
dk_free_tree (thr->thr_reset_code);
thr->thr_reset_code = err;
}
|
andywx/agensgraph
|
src/backend/parser/sparql_func.h
|
<reponame>andywx/agensgraph
/*
* sparql_func.h
*
* Created on: 2019年11月16日
* Author: liu
*/
#include"sparql.h"
#include"sparql_l.h"
#include <string.h>
#include <stdlib.h>
#include "Dk.h"
#include "dkpool.h"
#ifndef SRC_BACKEND_PARSER_SPARQL_FUNC_H_
#define SRC_BACKEND_PARSER_SPARQL_FUNC_H_
#define DBG_NAME(nm) nm
#define DBG_PARAMS
#define DBG_PARAMS_0 void
#define DBG_ARGS
#define DBG_ARGS_0
#define DK_ALLOC dk_alloc
#define DK_FREE dk_free
#define IS_BOX_POINTER(n) \
(((unsigned ptrlong) (n)) >= (unsigned ptrlong)SMALLEST_POSSIBLE_POINTER)
#define SMALLEST_POSSIBLE_POINTER ((ptrlong)(0x100000))
#ifdef MTX_DEBUG
# define ASSERT_IN_MTX(mtx) \
if (THREAD_CURRENT_THREAD != (mtx)->mtx_owner) GPF_T1 ("Not inside mutex.");
# define ASSERT_OUTSIDE_MTX(mtx) \
if (THREAD_CURRENT_THREAD == (mtx)->mtx_owner) GPF_T1 ("Not outside mutex.");
#else
# define ASSERT_IN_MTX(mtx)
# define ASSERT_OUTSIDE_MTX(mtx)
#endif
#define CLAQ_UNWIND_CK
#define ASSERT_OUTSIDE_TXN \
ASSERT_OUTSIDE_MTX (wi_inst.wi_txn_mtx)
void DBG_NAME(sqlr_new_error) (DBG_PARAMS const char *code, const char *virt_code, const char *string, ...);
void DBG_NAME(thr_set_error_code) (DBG_PARAMS thread_t *thr, caddr_t err);
extern void spar_error (sparp_t *sparp, const char *format, ...)
#ifdef __GNUC__
__attribute__ ((format (printf, 2, 3)))
#endif
;
extern uint32 dk_set_length (s_node_t * set);
extern void sparyyerror_impl (sparp_t *xpp, char *raw_text, const char *strg);
extern SPART **t_spartlist_concat (SPART **list1, SPART **list2);
extern void sparp_configure_storage_and_macro_libs (sparp_t *sparp);
extern SPART* spartlist (sparp_t *sparp, ptrlong length, ptrlong type, ...);
extern SPART *sparp_make_builtin_call (sparp_t *sparp, ptrlong bif_id, SPART **arguments);
extern void spar_error_if_unsupported_syntax_imp (sparp_t *sparp, int feature_in_use, const char *feature_name);
extern SPART *spar_gp_finalize (sparp_t *sparp, SPART **options);
extern SPART *spar_make_fake_action_solution (sparp_t *sparp);
extern SPART *spar_make_sparul_drop (sparp_t *sparp, SPART *graph_precode, int silent);
extern SPART *spar_make_sparul_create (sparp_t *sparp, SPART *graph_precode, int silent);
extern SPART *spar_make_sparul_load_service_data (sparp_t *sparp, SPART *proxy_iri_precode, SPART *service_iri_precode, int silent);
extern SPART *spar_make_sparul_load (sparp_t *sparp, SPART *graph_precode, SPART *src_precode, int silent);
extern SPART *spar_make_sparul_clear (sparp_t *sparp, SPART *graph_precode, int silent);
extern SPART *spar_make_top_or_special_case_from_wm (sparp_t *sparp, ptrlong subtype, SPART **retvals, SPART *wm );
extern void spar_compose_retvals_of_modify (sparp_t *sparp, SPART *top, SPART *graph_to_patch, SPART *del_ctor_gp, SPART *ins_ctor_gp);
extern void spar_compose_retvals_of_insert_or_delete (sparp_t *sparp, SPART *top, SPART *graph_to_patch, SPART *ctor_gp);
extern SPART *spar_make_drop_macro_lib (sparp_t *sparp, SPART *sml_precode, int silent);
#define SPAR_ERROR_IF_UNSUPPORTED_SYNTAX(feat,name) do { \
if (!((feat) & sparp_arg->sparp_permitted_syntax)) \
spar_error_if_unsupported_syntax_imp (sparp_arg, (feat), (name)); \
} while (0)
extern SPART *sparp_make_builtin_call (sparp_t *sparp, ptrlong bif_id, SPART **arguments);
extern caddr_t spar_mkid (sparp_t * sparp, const char *prefix);
extern SPART *spar_make_blank_node (sparp_t *sparp, caddr_t name, int bracketed);
extern caddr_t sparp_expand_qname_prefix (sparp_t *sparp, caddr_t qname);
extern caddr_t sparp_expand_q_iri_ref (sparp_t *sparp, caddr_t ref);
extern void sparyyerror_impl (sparp_t *xpp, char *raw_text, const char *strg);
extern SPART *spar_make_topmost_sparul_sql (sparp_t *sparp, SPART **actions);
extern void sparp_define (sparp_t *sparp, caddr_t param, ptrlong value_lexem_type, caddr_t value);
extern SPART *spar_gp_finalize (sparp_t *sparp, SPART **options);
extern void spar_gp_init (sparp_t *sparp, ptrlong subtype);
extern SPART *spar_make_param_or_variable (sparp_t *sparp, caddr_t name);
extern void sparp_check_dm_arg_for_redecl (sparp_t *sparp, dk_set_t recent, caddr_t dm_arg_vname);
extern void sparp_make_defmacro_paramnames_from_template (sparp_t *sparp, SPART *defm);
extern void sparp_defmacro_finalize (sparp_t *sparp, SPART *body);
extern SPART *sparp_defmacro_init (sparp_t *sparp, caddr_t mname);
extern void sparp_defmacro_store (sparp_t *sparp, SPART *defm);
extern SPART *spar_make_qm_col_desc (sparp_t *sparp, SPART *col);
extern void spar_qm_add_aliased_table_or_sqlquery (sparp_t *sparp, caddr_t parent_qtable, caddr_t new_alias);
extern SPART *spar_make_qm_sql (sparp_t *sparp, const char *fname, SPART **fixed, SPART **named);
extern void sparp_jso_push_affected (sparp_t *sparp, ccaddr_t inst_iri);
extern void sparp_jso_push_deleted (sparp_t *sparp, ccaddr_t class_iri, ccaddr_t inst_iri);
extern void spar_qm_pop_bookmark (sparp_t *sparp);
extern void spar_qm_push_bookmark (sparp_t *sparp);
extern SPART *spar_make_vector_qm_sql (sparp_t *sparp, SPART **fixed);
extern SPART *spar_make_wm (sparp_t *sparp, SPART *pattern, SPART **groupings, SPART *having, SPART **order, SPART *limit, SPART *offset, SPART *binv);
extern void spar_gp_add_member (sparp_t *sparp, SPART *memb);
extern SPART *spar_default_sparul_target (sparp_t *sparp, const char *reason_to_use, int preliminary_call);
extern void spar_apply_fallback_default_graph (sparp_t *sparp, int target_fallback_first);
extern void spar_qm_add_text_literal (sparp_t *sparp, caddr_t ft_type, caddr_t ft_table_alias, SPART *ft_col, SPART **qmv_cols, SPART **options);
extern void spar_qm_add_table_filter (sparp_t *sparp, caddr_t tmpl);
extern void spar_qm_add_aliased_table_or_sqlquery (sparp_t *sparp, caddr_t parent_qtable, caddr_t new_alias);
extern void spar_qm_add_aliased_alias (sparp_t *sparp, caddr_t parent_alias, caddr_t new_alias);
extern SPART *spar_make_sparul_copymoveadd (sparp_t *sparp, ptrlong opcode, SPART *from_graph_precode, SPART *to_graph_precode, int silent);
extern SPART *spar_make_top_or_special_case_from_wm (sparp_t *sparp, ptrlong subtype, SPART **retvals, SPART *wm );
extern void spar_compose_retvals_of_insert_or_delete (sparp_t *sparp, SPART *top, SPART *graph_to_patch, SPART *ctor_gp);
extern int spar_ctor_uses_default_graph (SPART *ctor_gp);
extern SPART *spar_gp_finalize (sparp_t *sparp, SPART **options);
extern void spar_compose_retvals_of_delete_from_wm (sparp_t *sparp, SPART *tree, SPART *graph_to_patch);
extern void sparp_make_and_push_new_graph_source (sparp_t *sparp, ptrlong subtype, SPART *iri_expn, SPART **options, int freeze_ignore_mask);
extern void spar_qm_push_local (sparp_t *sparp, int key, SPART *value, int can_overwrite);
extern void spar_qm_clean_locals (sparp_t *sparp);
extern SPART *spar_make_qm_value (sparp_t *sparp, caddr_t format_name, SPART **cols);
extern SPART *spar_qm_make_empty_mapping (sparp_t *sparp, caddr_t qm_id, SPART **options);
extern SPART *spar_qm_get_local (sparp_t *sparp, int key, int error_if_missing);
extern void spar_qm_pop_key (sparp_t *sparp, int key_to_pop);
extern SPART *spar_qm_make_real_mapping (sparp_t *sparp, caddr_t qm_id, SPART **options);
extern SPART *spar_make_variable (sparp_t *sparp, caddr_t name);
extern SPART *spar_add_propvariable (sparp_t *sparp, SPART *lvar, int opcode, SPART *verb_qname, int verb_lexem_type, caddr_t verb_lexem_text);
extern int sparp_namesake_macro_param (sparp_t *sparp, SPART *dm, caddr_t param_name);
extern SPART *spar_make_macropu (sparp_t *sparp, caddr_t name, ptrlong pos);
extern SPART *spar_make_funcall (sparp_t *sparp, int aggregate_mode, const char *funname, SPART **arguments);
extern SPART *spar_gp_add_triplelike (sparp_t *sparp, SPART *graph, SPART *subject, SPART *predicate, SPART *object, SPART **sinv_idx_and_qms, SPART **options, int banned_tricks);
extern SPART **spar_make_sources_like_top (sparp_t *sparp, ptrlong top_subtype);
extern SPART *spar_make_service_inv (sparp_t *sparp, SPART *endpoint, dk_set_t all_options, ptrlong permitted_syntax, ptrlong syntax_exceptions, SPART **sources, caddr_t sinv_storage_uri, int silent);
extern void spar_add_service_inv_to_sg (sparp_t *sparp, SPART *sinv);
extern SPART *spar_make_top (sparp_t *sparp, ptrlong subtype, SPART **retvals,
SPART *pattern, SPART **groupings, SPART *having, SPART **order, SPART *limit, SPART *offset, SPART *binv);
extern void spar_env_pop (sparp_t *sparp);
extern SPART *spar_gp_finalize_with_subquery (sparp_t *sparp, SPART **options, SPART *subquery);
extern quad_storage_t *sparp_find_storage_by_name (sparp_t *sparp, ccaddr_t name);
extern SPART *spar_make_ppath (sparp_t *sparp, char subtype, SPART *part1, SPART *part2, ptrlong mincount, ptrlong maxcount);
#define SPARP_ENV_CONTEXT_GP_SUBTYPE(sparp) ((ptrlong)((sparp)->sparp_env->spare_context_gp_subtypes->data))
extern void sparp_expand_top_retvals (sparp_t *sparp, SPART *query, int safely_copy_all_vars, dk_set_t binds_revlist);
extern void spar_verify_funcall_security (sparp_t *sparp, int *is_agg_ret, const char **fname_ptr, SPART **args);
extern SPART *spar_make_regex_or_like_or_eq (sparp_t *sparp, SPART *strg, SPART *regexpn);
#define SPART_TYPE(st) ((DV_ARRAY_OF_POINTER == DV_TYPE_OF(st)) ? (st)->type : SPAR_LIT)
#define SPART_IS_DEFAULT_GRAPH_BLANK(g) ( \
(SPAR_BLANK_NODE_LABEL == SPART_TYPE (g)) && \
!strncmp (g->_.var.vname, "_::default", 10) )
extern void sparp_find_language_dialect_by_service (sparp_t *sparp, SPART *service_expn, int *dialect_ret, int *exceptions_ret);
caddr_t uname_xmlschema_ns_uri_hash_integer;
#define SPAR_MAKE_INT_LITERAL(sparp,v) (spartlist ((sparp), 5, SPAR_LIT, (SPART *)t_box_num_nonull(v), uname_xmlschema_ns_uri_hash_integer, NULL, NULL))
extern caddr_t spar_unescape_strliteral (sparp_t *sparp, const char *sparyytext, int count_of_quotes, int mode);
extern caddr_t spar_make_iri_from_template (sparp_t *sparp, caddr_t tmpl);
extern SPART *spar_compose_ctor_gp_from_where_gp (sparp_t *sparp, int subtype, SPART *where_gp, SPART *gtp);
extern void spar_compose_retvals_of_construct (sparp_t *sparp, SPART *top, SPART *ctor_gp, const char *formatter, const char *agg_formatter, const char *agg_mdata);
extern void spar_env_push (sparp_t *sparp);
extern void spar_gp_add_filter (sparp_t *sparp, SPART *filt, int filt_is_movable);
extern SPART *spar_gp_finalize_with_inline_data (sparp_t *sparp, SPART **vars, SPART ***rows);
extern void spar_gp_finalize_binds (sparp_t *sparp, dk_set_t bind_revlist);
extern SPART *spar_bind_prepare (sparp_t *sparp, SPART *expn, int bind_has_scalar_subqs);
extern SPART *spar_make_bindings_inv_with_fake_equivs (sparp_t *sparp, SPART **vars, SPART ***data_rows, SPART *wrapper_gp);
extern void sparp_validate_options_of_tree (sparp_t *sparp, SPART *tree, SPART **options);
caddr_t uname_xmlschema_ns_uri_hash_boolean;
#define SPAR_MAKE_EBV_LITERAL(sparp,v) (spartlist ((sparp), 5, SPAR_LIT, (SPART *)t_box_num_nonull((v)?1:0), uname_xmlschema_ns_uri_hash_boolean, NULL, t_box_string((v)?"true":"false")))
extern SPART *sparp_make_qm_sqlcol (sparp_t *sparp, ptrlong type, caddr_t name);
extern void spar_change_sign (caddr_t *lit_ptr);
extern SPART *spar_make_typed_literal (sparp_t *sparp, caddr_t strg, caddr_t type, caddr_t lang);
extern void spar_gp_add_filters_for_named_graph (sparp_t *sparp);
extern SPART *sparp_make_macro_call (sparp_t *sparp, const char * funname, int call_is_explicit, SPART **arguments);
extern SPART *spar_find_defmacro_by_iri_or_fields (sparp_t *sparp, const char *mname, SPART **fields);
extern SPART *spar_make_topmost_qm_sql (sparp_t *sparp);
extern void ssg_find_formatter_by_name_and_subtype (ccaddr_t name, ptrlong subtype,
const char **ret_formatter, const char **ret_agg_formatter, const char **ret_agg_mdata );
extern int stricmp (const char *s1, const char *s2);
extern int numeric_from_string (numeric_t n, const char *s);
extern dk_set_t dk_set_nreverse (dk_set_t set);
extern void * dk_set_get_keyword (dk_set_t set, const char *key_strg, void *dflt_val);
extern dk_set_t dk_set_conc (dk_set_t s1, dk_set_t s2);
extern int dk_set_position (dk_set_t set, void *elt);
extern box_t box_tag(ccaddr_t box) ;
typedef long long int64;
typedef int64 boxint;
extern boxint unbox (ccaddr_t box);
extern int BOX_ELEMENTS(caddr_t b);
extern int BOX_ELEMENTS_0(caddr_t b);
extern caddr_t DBG_NAME(thr_get_error_code) (DBG_PARAMS thread_t *thr);
extern box_t DBG_NAME (box_dv_uname_string) (DBG_PARAMS const char *string);
extern void DBG_NAME(thr_set_error_code) (DBG_PARAMS thread_t *thr, caddr_t err);
int dk_free_tree (box_t box);
caddr_t dbg_mp_box_string (const char *file, int line, mem_pool_t * mp, const char *str);
#endif /* SRC_BACKEND_PARSER_SPARQL_FUNC_H_ */
|
andywx/agensgraph
|
src/backend/parser/uname_const_decl.h
|
/*
* $Id$
*
* This file is part of the OpenLink Software Virtuoso Open-Source (VOS)
* project.
*
* Copyright (C) 1998-2019 OpenLink Software
*
* This project is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; only version 2 of the License, dated June 1991.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#ifndef UNAME_CONST_DECL_H
#define UNAME_CONST_DECL_H
#include "Dk.h"
/* 0 1 2 3 */
/* 012345678901234567890123456789012345678 */
#define OPENLINKSW_BIF_NS_URI "http://www.openlinksw.com/schemas/bif#"
#define OPENLINKSW_SQL_NS_URI "http://www.openlinksw.com/schemas/sql#"
#define OPENLINKSW_BIF_NS_URI_LEN 38
#define OPENLINKSW_SQL_NS_URI_LEN 38
/* 0 1 2 3 */
/* 012345678901234567890123456789012345678 */
#define OPENLINKSW_BIF_NS_URI "http://www.openlinksw.com/schemas/bif#"
#define OPENLINKSW_SQL_NS_URI "http://www.openlinksw.com/schemas/sql#"
#define OPENLINKSW_BIF_NS_URI_LEN 38
#define OPENLINKSW_SQL_NS_URI_LEN 38
/* 0 1 2 3 */
/* 01234567890123456789012345678901234567 */
#define SWAP_REIFY_NS_URI "http://www.w3.org/2000/10/swap/reify#"
#define SWAP_REIFY_NS_URI_LEN 37
/* 0 1 2 3 4 */
/* 0123456789012345678901234567890123456789012 */
#define VIRTRDF_NS_URI "http://www.openlinksw.com/schemas/virtrdf#"
#define VIRTRDF_NS_URI_LEN 42
/* 0 1 2 3 4 */
/* 012345678901234567890123456789012345678901234567 */
#define RDFDF_NS_URI "http://www.openlinksw.com/virtrdf-data-formats#"
#define RDFDF_NS_URI_LEN 47
/* 0 1 2 3 */
/* 012345678901234567890123456789012345 */
#define XHV_NS_URI "http://www.w3.org/1999/xhtml/vocab#"
#define XHV_NS_URI_LEN 35
/* 0 1 2 */
/* 012345678901234567890123 */
#define OPENGIS_NS_URI "http://www.opengis.net/"
#define OPENGIS_NS_URI_LEN 23
/* 0 1 2 3 4 */
/* 01234567890123456789012345678901234567890123456 */
#define OPENGIS_DEF_FUNCTION_GS_NS_URI "http://www.opengis.net/def/function/geosparql/"
#define OPENGIS_DEF_FUNCTION_GS_NS_URI_LEN 46
/* 0 1 2 3 4 */
/* 0123456789012345678901234567890123456789012 */
#define OPENGIS_DEF_RULE_GS_NS_URI "http://www.opengis.net/def/rule/geosparql/"
#define OPENGIS_DEF_RULE_GS_NS_URI_LEN 42
/* 0 1 2 3 */
/* 0123456789012345678901234567890123456789 */
#define OPENGIS_DEF_UOM_GS_NS_URI "http://www.opengis.net/def/uom/OGC/1.0/"
#define OPENGIS_DEF_UOM_GS_NS_URI_LEN 39
/* 0 1 2 3 */
/* 01234567890123456789012345678901234567 */
#define OPENGIS_ONT_GS_NS_URI "http://www.opengis.net/ont/geosparql#"
#define OPENGIS_ONT_GS_NS_URI_LEN 37
#define OPENGIS_ONT_GML_NS_URI "http://www.opengis.net/ont/gml#"
#define OPENGIS_ONT_SF_NS_URI "http://www.opengis.net/ont/sf#"
extern void uname_const_decl_init (void);
extern caddr_t uname___empty;
extern caddr_t uname__bang_cdata_section_elements;
extern caddr_t uname__bang_exclude_result_prefixes;
extern caddr_t uname__bang_file;
extern caddr_t uname__bang_location;
extern caddr_t uname__bang_name;
extern caddr_t uname__bang_ns;
extern caddr_t uname__bang_uri;
extern caddr_t uname__bang_use_attribute_sets;
extern caddr_t uname__bang_xmlns;
extern caddr_t uname__attr;
extern caddr_t uname__comment;
extern caddr_t uname__disable_output_escaping;
extern caddr_t uname__root;
extern caddr_t uname__pi;
extern caddr_t uname__ref;
extern caddr_t uname__srcfile;
extern caddr_t uname__srcline;
extern caddr_t uname__txt;
extern caddr_t uname__xslt;
extern caddr_t uname_at_id;
extern caddr_t uname_at_num;
extern caddr_t uname_SPECIAL_cc_bif_c_AVG;
extern caddr_t uname_SPECIAL_cc_bif_c_COUNT;
extern caddr_t uname_SPECIAL_cc_bif_c_GROUPING;
extern caddr_t uname_SPECIAL_cc_bif_c_MAX;
extern caddr_t uname_SPECIAL_cc_bif_c_MIN;
extern caddr_t uname_SPECIAL_cc_bif_c_SUM;
extern caddr_t uname_bif_c_contains;
extern caddr_t uname_bif_c_spatial_contains;
extern caddr_t uname_bif_c_spatial_intersects;
extern caddr_t uname_bif_c_st_contains;
extern caddr_t uname_bif_c_st_intersects;
extern caddr_t uname_bif_c_st_may_intersect;
extern caddr_t uname_bif_c_st_within;
extern caddr_t uname_bif_c_xcontains;
extern caddr_t uname_bif_c_xpath_contains;
extern caddr_t uname_bif_c_xquery_contains;
extern caddr_t uname_bif_ns_uri;
extern caddr_t uname_opengis_def_function_gs_ns_uri;
extern caddr_t uname_opengis_def_function_gs_ns_uri_boundary;
extern caddr_t uname_opengis_def_function_gs_ns_uri_buffer;
extern caddr_t uname_opengis_def_function_gs_ns_uri_convexHull;
extern caddr_t uname_opengis_def_function_gs_ns_uri_difference;
extern caddr_t uname_opengis_def_function_gs_ns_uri_distance;
extern caddr_t uname_opengis_def_function_gs_ns_uri_ehContains;
extern caddr_t uname_opengis_def_function_gs_ns_uri_ehCoveredBy;
extern caddr_t uname_opengis_def_function_gs_ns_uri_ehCovers;
extern caddr_t uname_opengis_def_function_gs_ns_uri_ehDisjoint;
extern caddr_t uname_opengis_def_function_gs_ns_uri_ehEquals;
extern caddr_t uname_opengis_def_function_gs_ns_uri_ehInside;
extern caddr_t uname_opengis_def_function_gs_ns_uri_ehMeet;
extern caddr_t uname_opengis_def_function_gs_ns_uri_ehOverlap;
extern caddr_t uname_opengis_def_function_gs_ns_uri_envelope;
extern caddr_t uname_opengis_def_function_gs_ns_uri_getSRID;
extern caddr_t uname_opengis_def_function_gs_ns_uri_intersection;
extern caddr_t uname_opengis_def_function_gs_ns_uri_rcc8dc;
extern caddr_t uname_opengis_def_function_gs_ns_uri_rcc8ec;
extern caddr_t uname_opengis_def_function_gs_ns_uri_rcc8eq;
extern caddr_t uname_opengis_def_function_gs_ns_uri_rcc8ntpp;
extern caddr_t uname_opengis_def_function_gs_ns_uri_rcc8ntppi;
extern caddr_t uname_opengis_def_function_gs_ns_uri_rcc8po;
extern caddr_t uname_opengis_def_function_gs_ns_uri_rcc8tpp;
extern caddr_t uname_opengis_def_function_gs_ns_uri_rcc8tppi;
extern caddr_t uname_opengis_def_function_gs_ns_uri_relate;
extern caddr_t uname_opengis_def_function_gs_ns_uri_sfContains;
extern caddr_t uname_opengis_def_function_gs_ns_uri_sfCrosses;
extern caddr_t uname_opengis_def_function_gs_ns_uri_sfDisjoint;
extern caddr_t uname_opengis_def_function_gs_ns_uri_sfEquals;
extern caddr_t uname_opengis_def_function_gs_ns_uri_sfIntersects;
extern caddr_t uname_opengis_def_function_gs_ns_uri_sfOverlaps;
extern caddr_t uname_opengis_def_function_gs_ns_uri_sfTouches;
extern caddr_t uname_opengis_def_function_gs_ns_uri_sfWithin;
extern caddr_t uname_opengis_def_function_gs_ns_uri_symDifference;
extern caddr_t uname_opengis_def_function_gs_ns_uri_union;
extern caddr_t uname_opengis_def_rule_gs_ns_uri;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_ehContains;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_ehCoveredBy;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_ehCovers;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_ehDisjoint;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_ehEquals;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_ehInside;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_ehMeet;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_ehOverlap;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8dc;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8ec;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8eq;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8ntpp;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8ntppi;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8po;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8tpp;
extern caddr_t uname_opengis_def_rule_gs_ns_uri_rcc8tppi;
extern caddr_t uname_opengis_ns_uri;
extern caddr_t uname_opengis_ont_gml_ns_uri;
extern caddr_t uname_opengis_ont_gs_ns_uri;
extern caddr_t uname_opengis_ont_gs_ns_uri_Feature;
extern caddr_t uname_opengis_ont_gs_ns_uri_SpatialObject;
extern caddr_t uname_opengis_ont_gs_ns_uri_asGML;
extern caddr_t uname_opengis_ont_gs_ns_uri_asWKT;
extern caddr_t uname_opengis_ont_gs_ns_uri_coordinateDimension;
extern caddr_t uname_opengis_ont_gs_ns_uri_dimension;
extern caddr_t uname_opengis_ont_gs_ns_uri_ehContains;
extern caddr_t uname_opengis_ont_gs_ns_uri_ehCoveredBy;
extern caddr_t uname_opengis_ont_gs_ns_uri_ehCovers;
extern caddr_t uname_opengis_ont_gs_ns_uri_ehDisjoint;
extern caddr_t uname_opengis_ont_gs_ns_uri_ehEquals;
extern caddr_t uname_opengis_ont_gs_ns_uri_ehInside;
extern caddr_t uname_opengis_ont_gs_ns_uri_ehMeet;
extern caddr_t uname_opengis_ont_gs_ns_uri_ehOverlap;
extern caddr_t uname_opengis_ont_gs_ns_uri_gmlLiteral;
extern caddr_t uname_opengis_ont_gs_ns_uri_hasDefaultGeometry;
extern caddr_t uname_opengis_ont_gs_ns_uri_hasGeometry;
extern caddr_t uname_opengis_ont_gs_ns_uri_hasSerialization;
extern caddr_t uname_opengis_ont_gs_ns_uri_isEmpty;
extern caddr_t uname_opengis_ont_gs_ns_uri_isSimple;
extern caddr_t uname_opengis_ont_gs_ns_uri_rcc8dc;
extern caddr_t uname_opengis_ont_gs_ns_uri_rcc8ec;
extern caddr_t uname_opengis_ont_gs_ns_uri_rcc8eq;
extern caddr_t uname_opengis_ont_gs_ns_uri_rcc8ntpp;
extern caddr_t uname_opengis_ont_gs_ns_uri_rcc8ntppi;
extern caddr_t uname_opengis_ont_gs_ns_uri_rcc8po;
extern caddr_t uname_opengis_ont_gs_ns_uri_rcc8tpp;
extern caddr_t uname_opengis_ont_gs_ns_uri_rcc8tppi;
extern caddr_t uname_opengis_ont_gs_ns_uri_sfContains;
extern caddr_t uname_opengis_ont_gs_ns_uri_sfCrosses;
extern caddr_t uname_opengis_ont_gs_ns_uri_sfDisjoint;
extern caddr_t uname_opengis_ont_gs_ns_uri_sfEquals;
extern caddr_t uname_opengis_ont_gs_ns_uri_sfIntersects;
extern caddr_t uname_opengis_ont_gs_ns_uri_sfOverlaps;
extern caddr_t uname_opengis_ont_gs_ns_uri_sfTouches;
extern caddr_t uname_opengis_ont_gs_ns_uri_sfWithin;
extern caddr_t uname_opengis_ont_gs_ns_uri_spatialDimension;
extern caddr_t uname_opengis_ont_gs_ns_uri_wktLiteral;
extern caddr_t uname_opengis_ont_sf_ns_uri;
extern caddr_t uname_false;
extern caddr_t uname_lang;
extern caddr_t uname_nil;
extern caddr_t uname_nodeID_ns;
extern caddr_t uname_nodeID_ns_0;
extern caddr_t uname_nodeID_ns_8192;
extern caddr_t uname_rdf_ns_uri;
extern caddr_t uname_rdf_ns_uri_Description;
extern caddr_t uname_rdf_ns_uri_ID;
extern caddr_t uname_rdf_ns_uri_RDF;
extern caddr_t uname_rdf_ns_uri_Seq;
extern caddr_t uname_rdf_ns_uri_Statement;
extern caddr_t uname_rdf_ns_uri_XMLLiteral;
extern caddr_t uname_rdf_ns_uri_about;
extern caddr_t uname_rdf_ns_uri_first;
extern caddr_t uname_rdf_ns_uri_li;
extern caddr_t uname_rdf_ns_uri_nil;
extern caddr_t uname_rdf_ns_uri_nodeID;
extern caddr_t uname_rdf_ns_uri_object;
extern caddr_t uname_rdf_ns_uri_predicate;
extern caddr_t uname_rdf_ns_uri_resource;
extern caddr_t uname_rdf_ns_uri_rest;
extern caddr_t uname_rdf_ns_uri_subject;
extern caddr_t uname_rdf_ns_uri_type;
extern caddr_t uname_rdf_ns_uri_datatype;
extern caddr_t uname_rdf_ns_uri_parseType;
extern caddr_t uname_rdf_ns_uri_value;
extern caddr_t uname_rdfdf_ns_uri;
extern caddr_t uname_rdfdf_ns_uri_default;
extern caddr_t uname_rdfdf_ns_uri_default_nullable;
extern caddr_t uname_rdfdf_ns_uri_default_iid;
extern caddr_t uname_rdfdf_ns_uri_default_iid_nullable;
extern caddr_t uname_space;
extern caddr_t uname_sql_ns_uri;
extern caddr_t uname_swap_reify_ns_uri;
extern caddr_t uname_swap_reify_ns_uri_statement;
extern caddr_t uname_true;
extern caddr_t uname_virtrdf_ns_uri;
extern caddr_t uname_virtrdf_ns_uri_DefaultQuadMap;
extern caddr_t uname_virtrdf_ns_uri_DefaultQuadStorage;
extern caddr_t uname_virtrdf_ns_uri_DefaultServiceMap;
extern caddr_t uname_virtrdf_ns_uri_DefaultServiceStorage;
extern caddr_t uname_virtrdf_ns_uri_DefaultSparul11Target;
extern caddr_t uname_virtrdf_ns_uri_Geometry;
extern caddr_t uname_virtrdf_ns_uri_PrivateGraphs;
extern caddr_t uname_virtrdf_ns_uri_QuadMap;
extern caddr_t uname_virtrdf_ns_uri_QuadMapFormat;
extern caddr_t uname_virtrdf_ns_uri_QuadStorage;
extern caddr_t uname_virtrdf_ns_uri_RdfDebuggerSingletone;
extern caddr_t uname_virtrdf_ns_uri_SparqlMacroLibrary;
extern caddr_t uname_virtrdf_ns_uri_SyncToQuads;
extern caddr_t uname_virtrdf_ns_uri_array_of_any;
extern caddr_t uname_virtrdf_ns_uri_array_of_string;
extern caddr_t uname_virtrdf_ns_uri_bitmask;
extern caddr_t uname_virtrdf_ns_uri_bnode_base;
extern caddr_t uname_virtrdf_ns_uri_bnode_label;
extern caddr_t uname_virtrdf_ns_uri_bnode_row;
extern caddr_t uname_virtrdf_ns_uri_dialect;
extern caddr_t uname_virtrdf_ns_uri_dialect_exceptions;
extern caddr_t uname_virtrdf_ns_uri_isSpecialPredicate;
extern caddr_t uname_virtrdf_ns_uri_isSubclassOf;
extern caddr_t uname_virtrdf_ns_uri_loadAs;
extern caddr_t uname_virtrdf_ns_uri_namespace_base;
extern caddr_t uname_virtrdf_ns_uri_namespace_iri;
extern caddr_t uname_virtrdf_ns_uri_namespace_prefix;
extern caddr_t uname_virtrdf_ns_uri_namespace_row;
extern caddr_t uname_virtrdf_ns_uri_rdf_repl_all;
extern caddr_t uname_virtrdf_ns_uri_rdf_repl_graph_group;
extern caddr_t uname_virtrdf_ns_uri_rdf_repl_world;
extern caddr_t uname_xhv_ns_uri;
extern caddr_t uname_xhv_ns_uri_alternate;
extern caddr_t uname_xhv_ns_uri_appendix;
extern caddr_t uname_xhv_ns_uri_bookmark;
extern caddr_t uname_xhv_ns_uri_cite;
extern caddr_t uname_xhv_ns_uri_chapter;
extern caddr_t uname_xhv_ns_uri_contents;
extern caddr_t uname_xhv_ns_uri_copyright;
extern caddr_t uname_xhv_ns_uri_first;
extern caddr_t uname_xhv_ns_uri_glossary;
extern caddr_t uname_xhv_ns_uri_help;
extern caddr_t uname_xhv_ns_uri_icon;
extern caddr_t uname_xhv_ns_uri_index;
extern caddr_t uname_xhv_ns_uri_last;
extern caddr_t uname_xhv_ns_uri_license;
extern caddr_t uname_xhv_ns_uri_meta;
extern caddr_t uname_xhv_ns_uri_next;
extern caddr_t uname_xhv_ns_uri_p3pv1;
extern caddr_t uname_xhv_ns_uri_prev;
extern caddr_t uname_xhv_ns_uri_role;
extern caddr_t uname_xhv_ns_uri_section;
extern caddr_t uname_xhv_ns_uri_stylesheet;
extern caddr_t uname_xhv_ns_uri_subsection;
extern caddr_t uname_xhv_ns_uri_start;
extern caddr_t uname_xhv_ns_uri_up;
extern caddr_t uname_xml;
extern caddr_t uname_xmlns;
extern caddr_t uname_xml_colon_base;
extern caddr_t uname_xml_colon_lang;
extern caddr_t uname_xml_colon_space;
extern caddr_t uname_xml_ns_uri;
extern caddr_t uname_xml_ns_uri_colon_base;
extern caddr_t uname_xml_ns_uri_colon_lang;
extern caddr_t uname_xml_ns_uri_colon_space;
extern caddr_t uname_xmlschema_ns_uri;
extern caddr_t uname_xmlschema_ns_uri_hash;
extern caddr_t uname_xmlschema_ns_uri_hash_ENTITY;
extern caddr_t uname_xmlschema_ns_uri_hash_ENTITIES;
extern caddr_t uname_xmlschema_ns_uri_hash_ID;
extern caddr_t uname_xmlschema_ns_uri_hash_IDREF;
extern caddr_t uname_xmlschema_ns_uri_hash_IDREFS;
extern caddr_t uname_xmlschema_ns_uri_hash_NCName;
extern caddr_t uname_xmlschema_ns_uri_hash_Name;
extern caddr_t uname_xmlschema_ns_uri_hash_NMTOKEN;
extern caddr_t uname_xmlschema_ns_uri_hash_NMTOKENS;
extern caddr_t uname_xmlschema_ns_uri_hash_NOTATION;
extern caddr_t uname_xmlschema_ns_uri_hash_QName;
extern caddr_t uname_xmlschema_ns_uri_hash_any;
extern caddr_t uname_xmlschema_ns_uri_hash_anyAtomicType;
extern caddr_t uname_xmlschema_ns_uri_hash_anySimpleType;
extern caddr_t uname_xmlschema_ns_uri_hash_anyType;
extern caddr_t uname_xmlschema_ns_uri_hash_anyURI;
extern caddr_t uname_xmlschema_ns_uri_hash_base64Binary;
extern caddr_t uname_xmlschema_ns_uri_hash_boolean;
extern caddr_t uname_xmlschema_ns_uri_hash_byte;
extern caddr_t uname_xmlschema_ns_uri_hash_date;
extern caddr_t uname_xmlschema_ns_uri_hash_dateTime;
extern caddr_t uname_xmlschema_ns_uri_hash_dateTimeStamp;
extern caddr_t uname_xmlschema_ns_uri_hash_decimal;
extern caddr_t uname_xmlschema_ns_uri_hash_double;
extern caddr_t uname_xmlschema_ns_uri_hash_duration;
extern caddr_t uname_xmlschema_ns_uri_hash_dayTimeDuration;
extern caddr_t uname_xmlschema_ns_uri_hash_yearMonthDuration;
extern caddr_t uname_xmlschema_ns_uri_hash_float;
extern caddr_t uname_xmlschema_ns_uri_hash_gDay;
extern caddr_t uname_xmlschema_ns_uri_hash_gMonth;
extern caddr_t uname_xmlschema_ns_uri_hash_gMonthDay;
extern caddr_t uname_xmlschema_ns_uri_hash_gYear;
extern caddr_t uname_xmlschema_ns_uri_hash_gYearMonth;
extern caddr_t uname_xmlschema_ns_uri_hash_hexBinary;
extern caddr_t uname_xmlschema_ns_uri_hash_int;
extern caddr_t uname_xmlschema_ns_uri_hash_integer;
extern caddr_t uname_xmlschema_ns_uri_hash_language;
extern caddr_t uname_xmlschema_ns_uri_hash_long;
extern caddr_t uname_xmlschema_ns_uri_hash_negativeInteger;
extern caddr_t uname_xmlschema_ns_uri_hash_nonNegativeInteger;
extern caddr_t uname_xmlschema_ns_uri_hash_nonPositiveInteger;
extern caddr_t uname_xmlschema_ns_uri_hash_normalizedString;
extern caddr_t uname_xmlschema_ns_uri_hash_positiveInteger;
extern caddr_t uname_xmlschema_ns_uri_hash_short;
extern caddr_t uname_xmlschema_ns_uri_hash_string;
extern caddr_t uname_xmlschema_ns_uri_hash_time;
extern caddr_t uname_xmlschema_ns_uri_hash_token;
extern caddr_t uname_xmlschema_ns_uri_hash_unsignedByte;
extern caddr_t uname_xmlschema_ns_uri_hash_unsignedInt;
extern caddr_t uname_xmlschema_ns_uri_hash_unsignedLong;
extern caddr_t uname_xmlschema_ns_uri_hash_unsignedShort;
extern caddr_t unames_colon_number[20];
#endif
|
andywx/agensgraph
|
src/backend/parser/sparql_l.h
|
<filename>src/backend/parser/sparql_l.h<gh_stars>1-10
#pragma once
#define DV_STRING 182
#define MAX_XML_LNAME_LENGTH 500 /* for local names, namespace prefixes and namespace URIs */
#define MAX_XML_QNAME_LENGTH (2*MAX_XML_LNAME_LENGTH + 1) /* for qualified names (that have semicolons) */
#define NUMERIC_MAX_SCALE 15
#define NUMERIC_STS_INVALID_STR 4 /* Invalid string */
#define NUMERIC_MAX_PRECISION 40
#define NUMERIC_EXTRA_SCALE 5
#define NUMERIC_MAX_PRECISION_INT (NUMERIC_MAX_PRECISION + NUMERIC_EXTRA_SCALE)
#define NUMERIC_MAX_DATA_BYTES (2 * NUMERIC_MAX_PRECISION_INT + 4)
#define NUMERIC_MAX_SCALE_INT (NUMERIC_MAX_SCALE + NUMERIC_EXTRA_SCALE)
#include "sparql.h"
#ifdef OS2
#include <process.h>
#endif
#include <setjmp.h>
#include <sys/select.h>
#include <time.h>
#define box_length(box) ((uint32)(0x00ffffff & ((const uint32 *)(box))[-1]))
typedef struct jmp_buf_splice_s
{
jmp_buf buf;
#ifdef JMP_CKSUM
uint32 j_cksum;
#endif
#ifdef SIGNAL_DEBUG
const char *j_file;
int j_line;
struct jmp_buf_splice_s *j_parent;
#endif
} jmp_buf_splice;
#define current_thread thread_current()
#define THREAD_CURRENT_THREAD current_thread
#define du_thread_t thread_t
typedef struct thread_hdr_s thread_hdr_t;
typedef struct thread_queue_s thread_queue_t;
typedef int (*thread_init_func) (void *arg);
/*
* Thread queue
*/
typedef struct semaphore_s semaphore_t;
struct thread_hdr_s
{
thread_hdr_t * thr_next;
thread_hdr_t * thr_prev;
};
struct thread_queue_s
{
thread_hdr_t thq_head;
int thq_count;
};
struct thread_s
{
/* pointers for a thread queue */
thread_hdr_t thr_hdr;
/* running status, see below */
int thr_status;
/* current priority */
int thr_priority;
/* thread specific attributes (thread local storage) */
void * thr_attributes;
/* thread specific errno */
int thr_err;
/* if WAITING, thr_timer can interrupt */
void * thr_event;
timer_t * thr_timer;
/* used in thread_select */
int thr_retcode;
int thr_nfds;
fd_set thr_rfds;
fd_set thr_wfds;
/* restart context for a "dead" or new thread */
jmp_buf thr_init_context;
thread_init_func thr_initial_function;
void * thr_initial_argument;
/* stack size, if applicable */
unsigned long thr_stack_size;
void * thr_stack_base; /* address near bottom, use for overflow detection */
/* saved during a context switch */
jmp_buf thr_context; /* simulated threads */
/* stack protection */
unsigned int * thr_stack_marker; /* simulated threads */
void * thr_cv; /* condition variable */
void * thr_handle; /* os specific handle */
#ifdef WIN32
void * thr_sec_token; /* Win security token */
#endif
/* Compatibility dk_thread */
semaphore_t * thr_sem;
semaphore_t * thr_schedule_sem;
void * thr_client_data;
void * thr_alloc_cache;
struct TLSF_struct * thr_tlsf;
struct TLSF_struct * thr_own_tlsf;
/* preallocated thread attributes */
jmp_buf_splice * thr_reset_ctx;
caddr_t thr_reset_code;
caddr_t thr_func_value;
void * thr_tmp_pool;
void * thr_sql_scs;
int thr_attached;
caddr_t thr_dbg;
struct lock_trx_s * thr_lt; /* use to access lt during checkpoint wait */
#ifndef NDEBUG
void * thr_pg_dbg;
#endif
};
typedef struct thread_s thread_t;
typedef struct numeric_s *numeric_t;
thread_t * thread_current (void);
#define NUMERIC_STS_SUCCESS 0 /* OK */
#define SPAR_STRLITERAL_SPARQL_STRING 0
#define SPAR_STRLITERAL_JSON_STRING 1
#define SPAR_STRLITERAL_SPARQL_QNAME 2
#define SPARP_MAX_BRACE_DEPTH 80 /*!< Maximum allowed number of any opened parenthesis outside pair of curly braces in SQL text. SQL lexer has its own limit of the sort, \c SCN3_MAX_BRACE_DEPTH */
#define MAX_FLI (30)
#define FLI_OFFSET (6) /* tlsf structure just will manage blocks bigger */
#define REAL_FLI (MAX_FLI - FLI_OFFSET)
#define MAX_LOG2_SLI (5)
#define MAX_SLI (1 << MAX_LOG2_SLI) /* MAX_SLI = 2^MAX_LOG2_SLI */
typedef struct hash_elt_s hash_elt_t;
int numeric_from_string (numeric_t n, const char *s);
typedef unsigned int u32_t; /* NOTE: Make sure that this type is 4 bytes long on your computer */
typedef unsigned char u8_t; /* NOTE: Make sure that this type is 1 byte on your computer */
typedef unsigned int uint;
typedef uint uint32;
typedef struct free_ptr_struct {
struct bhdr_struct *prev;
struct bhdr_struct *next;
} free_ptr_t;
typedef struct bhdr_struct {
/* This pointer is just valid if the first bit of size is set */
struct bhdr_struct *prev_hdr;
/* The size is stored in bytes */
uint32 size; /* bit 0 indicates whether the block is used and */
/* bit 1 allows to know whether the previous block is free */
uint32 bhdr_info; /* source tlsf and optional code of alloc file/line */
union {
struct free_ptr_struct free_ptr;
u8_t buffer[1]; /*sizeof(struct free_ptr_struct)]; */
} ptr;
} bhdr_t;
typedef struct area_info_struct {
bhdr_t *end;
struct area_info_struct *next;
} area_info_t;
typedef struct
{
hash_elt_t * ht_elements;
uint32 ht_count;
uint32 ht_actual_size;
uint32 ht_rehash_threshold;
#ifdef MTX_DEBUG
dk_mutex_t * ht_required_mtx;
#endif
#ifdef HT_STATS
uint32 ht_max_colls;
uint32 ht_stats[30];
uint32 ht_ngets;
uint32 ht_nsets;
#endif
} dk_hash_t;
typedef struct TLSF_struct {
/* the TLSF's structure signature */
u32_t tlsf_signature;
#if TLSF_USE_LOCKS
dk_mutex_t tlsf_mtx;
#endif
#if TLSF_STATISTIC
/* These can not be calculated outside tlsf because we
* do not know the sizes when freeing/reallocing memory. */
size_t used_size;
size_t max_size;
#endif
size_t tlsf_total_mapped;
/* A linked list holding all the existing areas */
area_info_t *area_head;
char tlsf_on_thread;
short tlsf_id; /* index in table of all tlsfs */
/* the first-level bitmap */
/* This array should have a size of REAL_FLI bits */
u32_t fl_bitmap;
/* the second-level bitmap */
u32_t sl_bitmap[REAL_FLI];
bhdr_t *matrix[REAL_FLI][MAX_SLI];
size_t tlsf_grow_quantum;
dk_hash_t tlsf_large_alloc;
caddr_t tlsf_comment;
struct mem_pool_s * tlsf_mp;
#ifdef MALLOC_DEBUG
id_hash_t * tlsf_allocs;
#endif
} tlsf_t;
#ifdef JMP_CKSUM
#define longjmp_splice(b,f) longjmp_brk ((b), f)
uint32 j_cksum (jmp_buf j);
int j_set_cksum (jmp_buf_splice * j, int rc);
#define setjmp_splice(b) j_set_cksum (b, setjmp ((b)->buf))
void longjmp_brk (jmp_buf_splice * j, int rc);
#else
#define setjmp_splice(b) setjmp ((b)->buf)
#define longjmp_splice(b,f) longjmp ((b)->buf, f)
#endif
#ifdef SIGNAL_DEBUG
#define QR_RESET_CTX_T_CTX_IMPL(thr, __ctx, file, line) \
du_thread_t * __self = (thr); \
int reset_code; \
struct TLSF_struct * __tlsf = __self->thr_tlsf; \
jmp_buf_splice * __old_ctx = __self->thr_reset_ctx; \
(__ctx)->j_file = (file); \
(__ctx)->j_line = (line); \
(__ctx)->j_parent = (__old_ctx); \
__self->thr_reset_ctx = (__ctx); \
if (0 == (reset_code = setjmp_splice ((__ctx)))) \
{
#else
#define QR_RESET_CTX_T_CTX_IMPL(thr, __ctx, file, line) \
du_thread_t * __self = (thr); \
int reset_code; \
struct TLSF_struct * __tlsf = __self->thr_tlsf; \
jmp_buf_splice * __old_ctx = __self->thr_reset_ctx;\
__self->thr_reset_ctx = (__ctx); \
if (0 == (reset_code = setjmp_splice ((__ctx)))) \
{
#endif
#define QR_RESET_CTX_T_CTX(thr, __ctx) \
{ QR_RESET_CTX_T_CTX_IMPL(thr, __ctx, __FILE__, __LINE__)
#define QR_RESET_CTX_T(thr) \
{ jmp_buf_splice __ctx; QR_RESET_CTX_T_CTX_IMPL(thr, &__ctx, __FILE__, __LINE__)
#define QR_RESET_CTX QR_RESET_CTX_T (THREAD_CURRENT_THREAD)
#define QR_RESET_CODE \
} \
else \
{ __self->thr_tlsf = __tlsf;
#define END_QR_RESET \
} \
POP_QR_RESET; \
__self->thr_tlsf = __tlsf; \
}
#define POP_QR_RESET \
__self->thr_reset_ctx = __old_ctx
|
andywx/agensgraph
|
src/backend/parser/dkpool.c
|
<gh_stars>1-10
/*
* dkpool.c
*
* Created on: 2019年11月21日
* Author: liu
*/
/*
* Dkpool.c
*
* $Id$
*
* Temp memory pool for objects that should be allocated one by one but freed
* together.
*
* This file is part of the OpenLink Software Virtuoso Open-Source (VOS)
* project.
*
* Copyright (C) 1998-2019 OpenLink Software
*
* This project is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; only version 2 of the License, dated June 1991.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#include "Dk.h"
#ifdef HAVE_SYS_MMAN_H
#include <sys/mman.h>
#endif
#undef log
#include "math.h"
#include "dkpool.h"
#include"sparql.h"
#include"sparql_l.h"
#include"sparql_func.h"
void
mp_free_reuse (mem_pool_t * mp)
{
}
#ifdef MP_MAP_CHECK
dk_hash_t * mp_registered;
dk_mutex_t mp_reg_mtx;
void
mp_register (mem_pool_t * mp)
{
}
void
mp_unregister (mem_pool_t * mp)
{
}
int
mp_map_count ()
{
}
void
mp_map_count_print (char * buf, size_t max)
{
}
#else
#define mp_register(mp)
#define mp_unregister(mp)
void
mp_map_count_print (char * buf, size_t max)
{
buf[0] = '\0';
}
#endif
void mp_free_all_large (mem_pool_t * mp);
#define DBG_MP_ALLOC_BOX(mp,len,tag) DBG_NAME(mp_alloc_box) (DBG_ARGS (mp), (len), (tag))
#define DBG_MP_ALLOC_BOX_NI(mp,len,tag) DBG_NAME(mp_alloc_box_ni) (DBG_ARGS (mp), (len), (tag))
#define DBG_T_ALLOC_BOX(len,tag) DBG_NAME(t_alloc_box) (DBG_ARGS (len), (tag))
void
mp_uname_free (const void *k, void *data)
{
}
#define MP_BYTES_INCREMENT(mp,sz) do {\
mp->mp_bytes += (sz); \
if ((NULL != mp->mp_size_cap.cbk) && (mp->mp_bytes >= mp->mp_size_cap.limit) && (mp->mp_size_cap.limit >= mp->mp_size_cap.last_cbk_limit)) \
{ \
mp->mp_size_cap.cbk (mp, mp->mp_size_cap.cbk_env); \
mp->mp_size_cap.last_cbk_limit = mp->mp_size_cap.limit+1; \
} \
} while (0);
#ifdef LACERATED_POOL
#if defined (DEBUG) || defined (MALLOC_DEBUG)
mem_pool_t *
dbg_mem_pool_alloc (const char *file, int line)
#else
mem_pool_t *
mem_pool_alloc (void)
#endif
{
NEW_VARZ (mem_pool_t, mp);
mp->mp_size = 0x100;
mp->mp_allocs = (caddr_t *) DK_ALLOC (sizeof (caddr_t) * mp->mp_size);
mp->mp_unames = hash_table_allocate (11);
DBG_NAME(hash_table_init) (DBG_ARGS &mp->mp_large, 121);
mp->mp_large.ht_rehash_threshold = 2;
mp_register (mp);
#if defined (DEBUG) || defined (MALLOC_DEBUG)
mp->mp_alloc_file = (char *) file;
mp->mp_alloc_line = line;
#endif
return mp;
}
void
mp_free (mem_pool_t * mp)
{
#ifdef MALLOC_DEBUG
if (mp->mp_box_to_dc)
hash_table_free (mp->mp_box_to_dc);
#endif
mp_unregister (mp);
if (mp->mp_tlsf)
tlsf_destroy (mp->mp_tlsf); /* supporting structs, the mmaps are part of mp large allocs */
DO_SET (caddr_t, box, &mp->mp_trash)
{
dk_free_tree (box);
}
END_DO_SET ();
while (mp->mp_fill)
{
caddr_t buf;
const char *err;
mp->mp_fill -= 1;
buf = mp->mp_allocs[mp->mp_fill];
err = dk_find_alloc_error (buf, mp);
if (NULL != err)
GPF_T1 (err);
dk_freep (buf, mp);
}
maphash (mp_uname_free, mp->mp_unames);
hash_table_free (mp->mp_unames);
dk_free ((caddr_t) mp->mp_allocs, mp->mp_size * sizeof (caddr_t));
mp_free_all_large (mp);
mp_free_reuse (mp);
dk_free ((caddr_t) mp, sizeof (mem_pool_t));
}
void
mp_check (mem_pool_t * mp)
{
int fill;
if (!mp)
return;
fill = mp->mp_fill;
while (fill)
{
caddr_t buf;
const char *err;
fill -= 1;
buf = mp->mp_allocs[fill];
err = dk_find_alloc_error (buf, mp);
if (NULL != err)
GPF_T1 (err);
}
}
void
mp_alloc_box_assert (mem_pool_t * mp, caddr_t box)
{
#ifdef DOUBLE_ALIGN
const char *err = dk_find_alloc_error (box - 8, mp);
#else
const char *err = dk_find_alloc_error (box - 4, mp);
#endif
if (NULL != err)
{
#ifdef DOUBLE_ALIGN
dk_find_alloc_error (box - 8, mp); /* This is here to put a convenient breakpoint and look at the broken magic bytes with comfort */
#else
dk_find_alloc_error (box - 4, mp); /* You can put only a breakpoint two lines above and not worry about #ifdef-s: if this branch is enabled then the debugger will move the breakpoint down */
#endif
GPF_T1 (err);
}
}
#else
#if defined (DEBUG) || defined (MALLOC_DEBUG)
mem_pool_t *
dbg_mem_pool_alloc (const char *file, int line)
#else
mem_pool_t *
mem_pool_alloc (void)
#endif
{
}
extern size_t mp_large_min;
size_t mp_block_size = 4096 * 20;
void
mp_free (mem_pool_t * mp)
{
}
size_t
mp_size (mem_pool_t * mp)
{
}
#endif
size_t mp_large_min = 80000;
caddr_t DBG_NAME (mp_alloc_box) (DBG_PARAMS mem_pool_t * mp, size_t len1, dtp_t dtp)
{
}
caddr_t
DBG_NAME (mp_alloc_box_ni) (DBG_PARAMS mem_pool_t * mp, int len, dtp_t dtp)
{
}
caddr_t
DBG_NAME (mp_box_string) (DBG_PARAMS mem_pool_t * mp, const char *str)
{
}
caddr_t
DBG_NAME (mp_box_dv_short_nchars) (DBG_PARAMS mem_pool_t * mp, const char *buf, size_t buf_len)
{
box_t box;
box = DBG_MP_ALLOC_BOX (mp, buf_len + 1, DV_SHORT_STRING);
memcpy (box, buf, buf_len);
((char *) box)[buf_len] = '\0';
return box;
}
caddr_t
DBG_NAME (mp_box_substr) (DBG_PARAMS mem_pool_t * mp, ccaddr_t str, int n1, int n2)
{
int lstr = (int) (box_length (str)) - 1;
int lres;
char *res;
if (n2 > lstr)
n2 = lstr;
lres = n2 - n1;
if (lres <= 0)
return (DBG_NAME (mp_box_string) (DBG_ARGS mp, ""));
res = DBG_NAME (mp_alloc_box) (DBG_ARGS mp, lres + 1, DV_SHORT_STRING);
memcpy (res, str + n1, lres);
res[lres] = 0;
return res;
}
caddr_t
DBG_NAME (mp_box_dv_short_concat) (DBG_PARAMS mem_pool_t * mp, ccaddr_t str1, ccaddr_t str2)
{
int len1 = box_length (str1) - 1;
int len2 = box_length (str2);
caddr_t box;
box = DBG_MP_ALLOC_BOX (mp, len1 + len2, DV_SHORT_STRING);
memcpy (box, str1, len1);
memcpy (box+len1, str2, len2);
return (box_t) box;
}
caddr_t
DBG_NAME (mp_box_dv_short_strconcat) (DBG_PARAMS mem_pool_t * mp, const char *str1, const char *str2)
{
int len1 = strlen (str1);
int len2 = strlen (str2) + 1;
caddr_t box;
box = DBG_MP_ALLOC_BOX (mp, len1 + len2, DV_SHORT_STRING);
memcpy (box, str1, len1);
memcpy (box+len1, str2, len2);
return (box_t) box;
}
caddr_t DBG_NAME (mp_box_dv_uname_string) (DBG_PARAMS mem_pool_t * mp, const char *str)
{
}
caddr_t
DBG_NAME (mp_box_dv_uname_nchars) (DBG_PARAMS mem_pool_t * mp, const char *buf, size_t buf_len)
{
}
extern box_copy_f box_copier[256];
extern box_tmp_copy_f box_tmp_copier[256];
caddr_t
DBG_NAME (mp_box_copy) (DBG_PARAMS mem_pool_t * mp, caddr_t box)
{
}
caddr_t
DBG_NAME (mp_box_copy_tree) (DBG_PARAMS mem_pool_t * mp, caddr_t box)
{
}
caddr_t
DBG_NAME (mp_full_box_copy_tree) (DBG_PARAMS mem_pool_t * mp, caddr_t box)
{
}
caddr_t *
mp_list (mem_pool_t * mp, long n, ...)
{
}
caddr_t
DBG_NAME (mp_box_num) (DBG_PARAMS mem_pool_t * mp, boxint n)
{
}
caddr_t
DBG_NAME (t_box_num) (DBG_PARAMS boxint n)
{
}
caddr_t
DBG_NAME (t_box_num_and_zero) (DBG_PARAMS boxint n)
{
}
caddr_t
DBG_NAME (mp_box_double) (DBG_PARAMS mem_pool_t * mp, double n)
{
}
caddr_t
DBG_NAME (mp_box_float) (DBG_PARAMS mem_pool_t * mp, float n)
{
}
caddr_t
DBG_NAME (t_box_iri_id) (DBG_PARAMS int64 n)
{
}
box_t
DBG_NAME (t_box_double) (DBG_PARAMS double d)
{
double *box = (double *) DBG_T_ALLOC_BOX (sizeof (double), DV_DOUBLE_FLOAT);
*box = d;
return (box_t) box;
}
box_t
DBG_NAME (t_box_float) (DBG_PARAMS float d)
{
}
#ifdef MALLOC_DEBUG
caddr_t *
t_list_impl (long n, ...)
{
mem_pool_t *mp = THR_TMP_POOL;
caddr_t *box;
va_list ap;
int inx;
va_start (ap, n);
box = (caddr_t *) dbg_mp_alloc_box (mp->mp_list_alloc_file, mp->mp_list_alloc_line, mp, sizeof (caddr_t) * n, DV_ARRAY_OF_POINTER);
for (inx = 0; inx < n; inx++)
{
caddr_t child = va_arg (ap, caddr_t);
if (IS_BOX_POINTER (child))
mp_alloc_box_assert (THR_TMP_POOL, child);
box[inx] = child;
}
va_end (ap);
return ((caddr_t *) box);
}
t_list_impl_ptr_t
t_list_cock (const char *file, int line)
{
mem_pool_t *mp = THR_TMP_POOL;
mp->mp_list_alloc_file = file;
mp->mp_list_alloc_line = line;
return t_list_impl;
}
#else
caddr_t *
t_list (long n, ...)
{
}
#endif
caddr_t *
t_list_nc (long n, ...)
{
}
caddr_t *
t_list_memcpy (long n, ccaddr_t *src)
{
caddr_t *box;
size_t sz = sizeof (caddr_t) * n;
box = (caddr_t *) t_alloc_box (sz, DV_ARRAY_OF_POINTER);
memcpy (box, src, sz);
return box;
}
caddr_t *
t_list_concat_tail (caddr_t list, long n, ...)
{
}
caddr_t *
t_list_concat (caddr_t list1, caddr_t list2)
{
caddr_t res;
size_t len1, len2;
if (NULL == list1)
return (caddr_t *) list2;
if (NULL == list2)
return (caddr_t *) list1;
len1 = box_length (list1);
len2 = box_length (list2);
res = t_alloc_box (len1 + len2, box_tag (list1));
memcpy (res, list1, len1);
memcpy (res + len1, list2, len2);
return (caddr_t *) res;
}
caddr_t *
t_list_remove_nth (caddr_t list, int pos)
{
}
caddr_t *
t_list_insert_before_nth (caddr_t list, caddr_t new_item, int pos)
{
}
caddr_t *
t_list_insert_many_before_nth (caddr_t list, caddr_t * new_items, int ins_count, int pos)
{
}
caddr_t *
t_sc_list (long n, ...)
{
}
void
DBG_NAME (mp_set_push) (DBG_PARAMS mem_pool_t * mp, dk_set_t * set, void *elt)
{
}
dk_set_t
DBG_NAME (t_cons) (DBG_PARAMS void *car, dk_set_t cdr)
{
}
void
DBG_NAME (t_set_push) (DBG_PARAMS dk_set_t * set, void *elt)
{
*set = DBG_NAME (t_cons) (DBG_ARGS elt, *set);
}
void *
DBG_NAME (t_set_pop) (DBG_PARAMS s_node_t ** set)
{
if (*set)
{
void *item;
s_node_t *old = *set;
*set = old->next;
item = old->data;
return item;
}
return NULL;
}
int
DBG_NAME (t_set_pushnew) (DBG_PARAMS s_node_t ** set, void *item)
{
}
int
DBG_NAME (t_set_push_new_string) (DBG_PARAMS s_node_t ** set, char *item)
{
}
dk_set_t
DBG_NAME (t_set_union) (DBG_PARAMS dk_set_t s1, dk_set_t s2)
{
}
dk_set_t
DBG_NAME (t_set_intersect) (DBG_PARAMS dk_set_t s1, dk_set_t s2)
{
}
dk_set_t
DBG_NAME (t_set_diff) (DBG_PARAMS dk_set_t s1, dk_set_t s2)
{
}
caddr_t *
DBG_NAME (t_list_to_array) (DBG_PARAMS s_node_t * set)
{
}
caddr_t *
DBG_NAME (t_revlist_to_array) (DBG_PARAMS s_node_t * set)
{
}
int
DBG_NAME (t_set_delete) (DBG_PARAMS dk_set_t * set, void *item)
{
s_node_t *node = *set;
dk_set_t *previous = set;
while (node)
{
if (node->data == item)
{
*previous = node->next;
return 1;
}
previous = &(node->next);
node = node->next;
}
return 0;
}
void *
DBG_NAME (t_set_delete_nth) (DBG_PARAMS dk_set_t * set, int idx)
{
s_node_t *node = *set;
dk_set_t *previous = set;
if (0 > idx)
return NULL;
while (node)
{
if (0 == idx)
{
void *res = node->data;
*previous = node->next;
return res;
}
previous = &(node->next);
node = node->next;
idx--;
}
return NULL;
}
dk_set_t
DBG_NAME (t_set_copy) (DBG_PARAMS dk_set_t s)
{
}
#ifdef MALLOC_DEBUG
void
mp_check_tree (mem_pool_t * mp, box_t box)
{
uint32 count;
dtp_t tag;
if (!IS_BOX_POINTER (box))
return;
if (BF_VALID_JSO & box_flags (box))
{
dk_alloc_box_assert (box);
return;
}
mp_alloc_box_assert (mp, (caddr_t) box);
tag = box_tag (box);
if (IS_NONLEAF_DTP (tag))
{
box_t *obj = (box_t *) box;
for (count = box_length ((caddr_t) box) / sizeof (caddr_t); count; count--)
mp_check_tree (mp, *obj++);
}
}
#endif
caddr_t
t_box_vsprintf (size_t buflen_eval, const char *format, va_list tail)
{
}
caddr_t
t_box_vsprintf_uname (size_t buflen_eval, const char *format, va_list tail)
{
}
caddr_t
t_box_sprintf (size_t buflen_eval, const char *format, ...)
{
}
caddr_t
t_box_sprintf_uname (size_t buflen_eval, const char *format, ...)
{
}
void
mp_trash (mem_pool_t * mp, caddr_t box)
{
mp_set_push (mp, &mp->mp_trash, (void *) box);
}
caddr_t
ap_alloc_box (auto_pool_t * ap, int len, dtp_t dtp)
{
}
caddr_t
ap_box_num (auto_pool_t * ap, int64 n)
{
}
caddr_t
ap_box_iri_id (auto_pool_t * ap, int64 n)
{
}
caddr_t *
ap_list (auto_pool_t * apool, long n, ...)
{
}
/* large allocs */
size_t mp_large_in_use;
size_t mp_max_large_in_use;
size_t mp_max_cache = 10000000;
int64 mp_mmap_clocks;
size_t mp_large_warn_threshold;
dk_mutex_t mp_large_g_mtx;
size_t mp_mmap_min = 80000;
size_t mm_page_sz = 4096;
int mm_n_large_sizes;
#define N_LARGE_SIZES 30
size_t mm_sizes[N_LARGE_SIZES];
du_thread_t * mm_after_failed_unmap;
dk_mutex_t map_fail_mtx;
dk_hash_t mm_failed_unmap;
resource_t * mm_rc[N_LARGE_SIZES];
int32 mm_uses[N_LARGE_SIZES + 1];
int mp_local_rc_sz = 1;
size_t mp_large_reserved;
size_t mp_max_large_reserved;
size_t mp_large_reserve_limit;
dk_mutex_t mp_reserve_mtx;
size_t mp_large_soft_cap;
size_t mp_large_hard_cap;
size_t
mm_next_size (size_t n, int * nth)
{
size_t *last = &mm_sizes[mm_n_large_sizes - 1];
size_t *base = mm_sizes;
if (!mm_n_large_sizes || n > *last)
{
*nth = -1;
return n;
}
while (last >= base)
{
size_t *p = &base[(int) ((last - base) >> 1)];
int64 res = (int64) n - *p;
if (res == 0)
{
*nth = p - &mm_sizes[0];
return n;
}
if (res < 0)
last = p - 1;
else
base = p + 1;
}
*nth = (last - &mm_sizes[0]) + 1;
return last[1];
}
void
mm_cache_init (size_t sz, size_t min, size_t max, int steps, float step)
{
}
size_t
mp_block_size_sc (size_t sz)
{
int ign;
if (sz >= mm_sizes[mm_n_large_sizes - 1])
return mm_sizes[mm_n_large_sizes - 1];
if (sz < mm_sizes[0])
return mm_sizes[0];
return mm_next_size (sz, &ign);
}
#ifdef MP_MAP_CHECK
dk_mutex_t mp_mmap_mark_mtx;
dk_pool_4g_t * dk_pool_map[256 * 256];
int dk_pool_map_inited;
void
mp_mmap_mark (void * __ptr, size_t sz, int flag)
{
}
void
mp_check_not_in_pool (int64 __ptr)
{
}
int
mp_list_marks (int first, int n_print)
{
}
void
mp_mark_check ()
{
}
#else
#define mp_mmap_mark(ptr, sz, f)
#endif
void mm_cache_clear ();
int64 dk_n_mmaps;
void *
mp_mmap (size_t sz)
{
}
void
mp_munmap (void* ptr, size_t sz)
{
}
#define MM_FREE_BATCH 100
size_t
mm_free_n (int nth, size_t target_bytes, int age_limit, uint32 now)
{
}
size_t
mm_cache_trim (size_t target_sz, int age_limit, int old_only)
{
}
void*
mm_large_alloc (size_t sz)
{
void
mp_warn (mem_pool_t * mp)
{
}
void *
mp_large_alloc (mem_pool_t * mp, size_t sz)
{
}
void
mp_set_tlsf (mem_pool_t * mp, size_t sz)
{
}
void
mm_free_sized (void* ptr, size_t sz)
{
}
void
mp_free_large (mem_pool_t * mp, void * ptr)
{
}
void
mp_free_all_large (mem_pool_t * mp)
{
}
void
mp_large_report ()
{
uint32 now = approx_msec_real_time ();
int inx;
int64 bytes = 0;
for (inx = 0; inx < mm_n_large_sizes; inx++)
{
int inx2, max_age = 0, min_age = INT32_MAX, age_sum = 0;
resource_t * rc = mm_rc[inx];
int fill = rc->rc_fill;
for (inx2 = 0; inx2 < fill; inx2++)
{
int age = now - rc->rc_item_time[inx2];
if (age > max_age)
max_age = age;
if (age < min_age)
min_age = age;
age_sum += age;
}
printf ("size %lu fill %lu max %lu gets %lu stores %lu full %lu empty %lu ages %d/%d/%d\n",
(unsigned long)(mm_sizes[inx]), (unsigned long)(rc->rc_fill), (unsigned long)(rc->rc_size),
(unsigned long)(rc->rc_gets), (unsigned long)(rc->rc_stores), (unsigned long)(rc->rc_n_full), (unsigned long)(rc->rc_n_empty),
fill ? min_age : 0, fill ? age_sum / fill : 0, max_age);
bytes += mm_sizes[inx] * rc->rc_fill;
}
printf ("total %Ld in reserve\n", bytes);
}
int
mp_reuse_large (mem_pool_t * mp, void * ptr)
{
}
int
mp_reserve (mem_pool_t * mp, size_t inc)
{
int ret = 0;
mutex_enter (&mp_reserve_mtx);
if (mp_large_reserved + inc < mp_large_reserve_limit)
{
mp_large_reserved += inc;
mp->mp_reserved += inc;
if (mp_max_large_reserved < mp_large_reserved)
mp_max_large_reserved = mp_large_reserved;
ret = 1;
}
mutex_leave (&mp_reserve_mtx);
return ret;
}
void
mp_comment (mem_pool_t * mp, const char * str1, const char * str2)
{
}
typedef struct ptr_and_sz_s
{
uptrlong ps_ptr;
uint32 ps_n_pages;
} ptr_and_size_t;
int
ps_compare (const void *s1, const void *s2)
{
uptrlong p1 = ((ptr_and_size_t*)s1)->ps_ptr;
uptrlong p2 = ((ptr_and_size_t*)s2)->ps_ptr;
return p1 < p2 ? -1 : p1 == p2 ? 0 : 1;
}
int
munmap_ck (void* ptr, size_t sz)
{
}
int
mm_unmap_asc (ptr_and_size_t * maps, int low, int high)
{
int inx;
int rc = munmap_ck ((void*)maps[low].ps_ptr, maps[low].ps_n_pages * mm_page_sz);
if (-1 == rc)
return 0;
maps[low].ps_ptr = 0;
for (inx = low + 1; inx < high; inx++)
{
if (0 == munmap_ck ((void*)maps[inx].ps_ptr, maps[inx].ps_n_pages * mm_page_sz))
maps[inx].ps_ptr = 0;
}
return 1;
}
int
mm_unmap_desc (ptr_and_size_t * maps, int low, int high)
{
int inx;
int rc = munmap_ck ((void*)maps[high - 1].ps_ptr, maps[high - 1].ps_n_pages * mm_page_sz);
if (-1 == rc)
return 0;
maps[high - 1].ps_ptr = 0;
for (inx = high - 2; inx >= low; inx--)
{
if (0 == munmap_ck ((void*)maps[inx].ps_ptr, maps[inx].ps_n_pages * mm_page_sz))
maps[inx].ps_ptr = 0;
}
return 1;
}
void
mm_unmap_contiguous (ptr_and_size_t * maps, int n_maps)
{
}
void
mm_cache_clear ()
{
}
}
/* Stubs for plugins */
/* This section _must_ be last in the source file, like any similar section in other files. */
#if defined (DEBUG) || defined (MALLOC_DEBUG)
#undef mem_pool_alloc
mem_pool_t *mem_pool_alloc (void) { return dbg_mem_pool_alloc (__FILE__, __LINE__); }
#endif
#ifdef MALLOC_DEBUG
#undef mp_alloc_box
caddr_t mp_alloc_box (mem_pool_t * mp, size_t len, dtp_t dtp) { return dbg_mp_alloc_box (__FILE__, __LINE__, mp, len, dtp); }
#undef mp_alloc_box_ni
caddr_t mp_alloc_box_ni (mem_pool_t * mp, int len, dtp_t dtp) { return dbg_mp_alloc_box_ni (__FILE__, __LINE__, mp, len, dtp); }
#undef mp_box_string
caddr_t mp_box_string (mem_pool_t * mp, const char *str) { return dbg_mp_box_string (__FILE__, __LINE__, mp, str); }
#undef mp_box_substr
caddr_t mp_box_substr (mem_pool_t * mp, ccaddr_t str, int n1, int n2) { return dbg_mp_box_substr (__FILE__, __LINE__, mp, str, n1, n2); }
#undef mp_box_dv_short_nchars
caddr_t mp_box_dv_short_nchars (mem_pool_t * mp, const char *str, size_t len) { return dbg_mp_box_dv_short_nchars (__FILE__, __LINE__, mp, str, len); }
#undef mp_box_dv_short_concat
caddr_t mp_box_dv_short_concat (mem_pool_t * mp, ccaddr_t str1, ccaddr_t str2) { return dbg_mp_box_dv_short_concat (__FILE__, __LINE__, mp, str1, str2); }
#undef mp_box_dv_short_strconcat
caddr_t mp_box_dv_short_strconcat (mem_pool_t * mp, const char *str1, const char *str2) { return dbg_mp_box_dv_short_strconcat (__FILE__, __LINE__, mp, str1, str2); }
#undef mp_box_dv_uname_string
caddr_t mp_box_dv_uname_string (mem_pool_t * mp, const char *str) { return dbg_mp_box_dv_uname_string (__FILE__, __LINE__, mp, str); }
#undef mp_box_dv_uname_nchars
caddr_t mp_box_dv_uname_nchars (mem_pool_t * mp, const char *str, size_t len) { return dbg_mp_box_dv_uname_nchars (__FILE__, __LINE__, mp, str, len); }
#undef mp_box_copy
caddr_t mp_box_copy (mem_pool_t * mp, caddr_t box) { return dbg_mp_box_copy (__FILE__, __LINE__, mp, box); }
#undef mp_box_copy_tree
caddr_t mp_box_copy_tree (mem_pool_t * mp, caddr_t box) { return dbg_mp_box_copy_tree (__FILE__, __LINE__, mp, box); }
#undef mp_full_box_copy_tree
caddr_t mp_full_box_copy_tree (mem_pool_t * mp, caddr_t box) { return dbg_mp_full_box_copy_tree (__FILE__, __LINE__, mp, box); }
#undef mp_box_num
caddr_t mp_box_num (mem_pool_t * mp, boxint num) { return dbg_mp_box_num (__FILE__, __LINE__, mp, num); }
#undef mp_box_iri_id
caddr_t mp_box_iri_id (mem_pool_t * mp, iri_id_t num) { return dbg_mp_box_iri_id (__FILE__, __LINE__, mp, num); }
#undef mp_box_double
caddr_t mp_box_double (mem_pool_t * mp, double num) { return dbg_mp_box_double (__FILE__, __LINE__, mp, num); }
#undef mp_box_float
caddr_t mp_box_float (mem_pool_t * mp, float num) { return dbg_mp_box_float (__FILE__, __LINE__, mp, num); }
#endif
thread_t * thread_current (void){
}
numeric_t t_numeric_allocate (void){
}
|
andywx/agensgraph
|
src/backend/commands/copyrdf.c
|
#include "postgres.h"
#include "access/xact.h"
#include "catalog/namespace.h"
#include "commands/async.h"
#include "commands/prepare.h"
#include "commands/copyrdf.h"
#include "commands/sequence.h"
#include "utils/guc.h"
#include "utils/portal.h"
#include "stdio.h"
#include "string.h"
#include "stdlib.h"
void
DoCopyRdf(CopyRdfStmt *stmt)
{
freopen("/home/lpk/f1.txt","w",stdout); //输出文件路径,需要根据本地用户实际路径修改
printf("%s\n",stmt->filename);
fclose(stdout);
return 0;
}
|
andywx/agensgraph
|
src/backend/parser/sparqlwords.h
|
<filename>src/backend/parser/sparqlwords.h
/* ANSI-C code produced by gperf version 3.0.4 */
/* Command-line: /usr/bin/gperf -aCDGptr -Kkwd -L ANSI-C -k'1,2,3,5,7,$' --ignore-case -Nsparql_lex_hash_kw sparqlwords.gperf */
#if !((' ' == 32) && ('!' == 33) && ('"' == 34) && ('#' == 35) \
&& ('%' == 37) && ('&' == 38) && ('\'' == 39) && ('(' == 40) \
&& (')' == 41) && ('*' == 42) && ('+' == 43) && (',' == 44) \
&& ('-' == 45) && ('.' == 46) && ('/' == 47) && ('0' == 48) \
&& ('1' == 49) && ('2' == 50) && ('3' == 51) && ('4' == 52) \
&& ('5' == 53) && ('6' == 54) && ('7' == 55) && ('8' == 56) \
&& ('9' == 57) && (':' == 58) && (';' == 59) && ('<' == 60) \
&& ('=' == 61) && ('>' == 62) && ('?' == 63) && ('A' == 65) \
&& ('B' == 66) && ('C' == 67) && ('D' == 68) && ('E' == 69) \
&& ('F' == 70) && ('G' == 71) && ('H' == 72) && ('I' == 73) \
&& ('J' == 74) && ('K' == 75) && ('L' == 76) && ('M' == 77) \
&& ('N' == 78) && ('O' == 79) && ('P' == 80) && ('Q' == 81) \
&& ('R' == 82) && ('S' == 83) && ('T' == 84) && ('U' == 85) \
&& ('V' == 86) && ('W' == 87) && ('X' == 88) && ('Y' == 89) \
&& ('Z' == 90) && ('[' == 91) && ('\\' == 92) && (']' == 93) \
&& ('^' == 94) && ('_' == 95) && ('a' == 97) && ('b' == 98) \
&& ('c' == 99) && ('d' == 100) && ('e' == 101) && ('f' == 102) \
&& ('g' == 103) && ('h' == 104) && ('i' == 105) && ('j' == 106) \
&& ('k' == 107) && ('l' == 108) && ('m' == 109) && ('n' == 110) \
&& ('o' == 111) && ('p' == 112) && ('q' == 113) && ('r' == 114) \
&& ('s' == 115) && ('t' == 116) && ('u' == 117) && ('v' == 118) \
&& ('w' == 119) && ('x' == 120) && ('y' == 121) && ('z' == 122) \
&& ('{' == 123) && ('|' == 124) && ('}' == 125) && ('~' == 126))
/* The character set is not based on ISO-646. */
#error "gperf generated tables don't work with this execution character set. Please report a bug to <<EMAIL>>."
#endif
#line 24 "sparqlwords.gperf"
struct sparql_keyword { char *kwd; int token; int subtype; };
#define TOTAL_KEYWORDS 198
#define MIN_WORD_LENGTH 2
#define MAX_WORD_LENGTH 23
#define MIN_HASH_VALUE 52
#define MAX_HASH_VALUE 1031
/* maximum key range = 980, duplicates = 0 */
#ifndef GPERF_DOWNCASE
#define GPERF_DOWNCASE 1
static unsigned char gperf_downcase[256] =
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
60, 61, 62, 63, 64, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106,
107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
122, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164,
165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179,
180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209,
210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224,
225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239,
240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254,
255
};
#endif
#ifndef GPERF_CASE_STRCMP
#define GPERF_CASE_STRCMP 1
static int
gperf_case_strcmp (register const char *s1, register const char *s2)
{
for (;;)
{
unsigned char c1 = gperf_downcase[(unsigned char)*s1++];
unsigned char c2 = gperf_downcase[(unsigned char)*s2++];
if (c1 != 0 && c1 == c2)
continue;
return (int)c1 - (int)c2;
}
}
#endif
#ifdef __GNUC__
__inline
#else
#ifdef __cplusplus
inline
#endif
#endif
static unsigned int
hash (register const char *str, register unsigned int len)
{
static const unsigned short asso_values[] =
{
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 69,
119, 1032, 48, 232, 224, 1032, 7, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 16, 38, 167, 11, 113,
189, 86, 169, 66, 60, 208, 224, 53, 80, 120,
71, 24, 172, 176, 114, 145, 118, 232, 230, 210,
156, 1032, 1032, 1032, 1032, 189, 1032, 16, 38, 167,
11, 113, 189, 86, 169, 66, 60, 208, 224, 53,
80, 120, 71, 24, 172, 176, 114, 145, 118, 232,
230, 210, 156, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032, 1032,
1032, 1032, 1032, 1032, 1032, 1032
};
register int hval = len;
switch (hval)
{
default:
hval += asso_values[(unsigned char)str[6]];
/*FALLTHROUGH*/
case 6:
case 5:
hval += asso_values[(unsigned char)str[4]];
/*FALLTHROUGH*/
case 4:
case 3:
hval += asso_values[(unsigned char)str[2]];
/*FALLTHROUGH*/
case 2:
hval += asso_values[(unsigned char)str[1]];
/*FALLTHROUGH*/
case 1:
hval += asso_values[(unsigned char)str[0]];
break;
}
return hval + asso_values[(unsigned char)str[len - 1]];
}
static const struct sparql_keyword wordlist[] =
{
#line 27 "sparqlwords.gperf"
{"ADD", ADD_L , 0},
#line 30 "sparqlwords.gperf"
{"AND", _AMP_AMP , 0},
#line 56 "sparqlwords.gperf"
{"DATA", DATA_L , 0},
#line 124 "sparqlwords.gperf"
{"NAMED", NAMED_L , 0},
#line 186 "sparqlwords.gperf"
{"TABID", TABID_L , 0},
#line 38 "sparqlwords.gperf"
{"BIND", BIND_L , 0},
#line 141 "sparqlwords.gperf"
{"QUAD", QUAD_L , 0},
#line 115 "sparqlwords.gperf"
{"MAP", MAP_L , 0},
#line 73 "sparqlwords.gperf"
{"END", END_L , 0},
#line 91 "sparqlwords.gperf"
{"IN", IN_L , 0},
#line 125 "sparqlwords.gperf"
{"NAN", NAN_L , 0},
#line 118 "sparqlwords.gperf"
{"MIN", MIN_L , 0},
#line 142 "sparqlwords.gperf"
{"RAND", SPARQL_BIF , SPAR_BIF_RAND},
#line 36 "sparqlwords.gperf"
{"AVG", AVG_L , 0},
#line 42 "sparqlwords.gperf"
{"BOUND", BOUND_L , 0},
#line 37 "sparqlwords.gperf"
{"BASE", BASE_L , 0},
#line 191 "sparqlwords.gperf"
{"TO", TO_L , 0},
#line 31 "sparqlwords.gperf"
{"AS", AS_L , 0},
#line 216 "sparqlwords.gperf"
{"UUID", SPARQL_BIF , SPAR_BIF_UUID},
#line 97 "sparqlwords.gperf"
{"IRI", IRI_L , 0},
#line 112 "sparqlwords.gperf"
{"LOAD", LOAD_L , 0},
#line 68 "sparqlwords.gperf"
{"DROP", DROP_L , 0},
#line 192 "sparqlwords.gperf"
{"TOP", TOP_L , 0},
#line 96 "sparqlwords.gperf"
{"INTO", INTO_L , 0},
#line 217 "sparqlwords.gperf"
{"VALID", SPARQL_BIF , SPAR_BIF_VALID},
#line 69 "sparqlwords.gperf"
{"EBV", SPARQL_BIF , SPAR_BIF_EBV},
#line 114 "sparqlwords.gperf"
{"MAKE", MAKE_L , 0},
#line 89 "sparqlwords.gperf"
{"IFP", IFP_L , 0},
#line 123 "sparqlwords.gperf"
{"MOVE", MOVE_L , 0},
#line 26 "sparqlwords.gperf"
{"ABS", SPARQL_BIF , SPAR_BIF_ABS},
#line 104 "sparqlwords.gperf"
{"LANG", LANG_L , 0},
#line 166 "sparqlwords.gperf"
{"SHA384", SPARQL_BIF , SPAR_BIF_SHA384},
#line 195 "sparqlwords.gperf"
{"TZ", SPARQL_BIF , SPAR_BIF_TZ},
#line 185 "sparqlwords.gperf"
{"SUM", SUM_L , 0},
#line 127 "sparqlwords.gperf"
{"NOT", NOT_L , 0},
#line 163 "sparqlwords.gperf"
{"SHA1", SPARQL_BIF , SPAR_BIF_SHA1},
#line 211 "sparqlwords.gperf"
{"UNBOUND", UNBOUND_L , 0},
#line 82 "sparqlwords.gperf"
{"GEO", GEO_L , 0},
#line 99 "sparqlwords.gperf"
{"ISIRI", SPARQL_BIF , SPAR_BIF_ISIRI},
#line 88 "sparqlwords.gperf"
{"IF", SPARQL_BIF , SPAR_BIF_IF},
#line 57 "sparqlwords.gperf"
{"DATATYPE", DATATYPE_L , 0},
#line 58 "sparqlwords.gperf"
{"DAY", SPARQL_BIF , SPAR_BIF_DAY},
#line 214 "sparqlwords.gperf"
{"URI", IRI_L , 0},
#line 202 "sparqlwords.gperf"
{"T_IN", T_IN_L , 0},
#line 213 "sparqlwords.gperf"
{"UNION", UNION_L , 0},
#line 43 "sparqlwords.gperf"
{"BY", BY_L , 0},
#line 149 "sparqlwords.gperf"
{"ROUND", SPARQL_BIF , SPAR_BIF_ROUND},
#line 136 "sparqlwords.gperf"
{"OR", _BAR_BAR , 0},
#line 55 "sparqlwords.gperf"
{"CUBE", CUBE_L , 0},
#line 41 "sparqlwords.gperf"
{"BNODE", SPARQL_BIF , SPAR_BIF_BNODE},
#line 64 "sparqlwords.gperf"
{"DESC", DESC_L , 0},
#line 87 "sparqlwords.gperf"
{"HAVING", HAVING_L , 0},
#line 44 "sparqlwords.gperf"
{"CASE", CASE_L , 0},
#line 189 "sparqlwords.gperf"
{"THEN", THEN_L , 0},
#line 113 "sparqlwords.gperf"
{"MACRO", MACRO_L , 0},
#line 40 "sparqlwords.gperf"
{"BIJECTION", BIJECTION_L , 0},
#line 144 "sparqlwords.gperf"
{"REDUCED", REDUCED_L , 0},
#line 187 "sparqlwords.gperf"
{"TABLE_OPTION", TABLE_OPTION_L , 0},
#line 131 "sparqlwords.gperf"
{"OF", OF_L , 0},
#line 49 "sparqlwords.gperf"
{"CONCAT", SPARQL_BIF , SPAR_BIF_CONCAT},
#line 130 "sparqlwords.gperf"
{"OBJECT", OBJECT_L , 0},
#line 135 "sparqlwords.gperf"
{"OPTION", OPTION_L , 0},
#line 60 "sparqlwords.gperf"
{"DEFINE", DEFINE_L , 0},
#line 90 "sparqlwords.gperf"
{"IDENTIFIED", IDENTIFIED_L , 0},
#line 223 "sparqlwords.gperf"
{"YEAR", SPARQL_BIF , SPAR_BIF_YEAR},
#line 39 "sparqlwords.gperf"
{"BINDINGS", BINDINGS_L , 0},
#line 204 "sparqlwords.gperf"
{"T_MIN", T_MIN_L , 0},
#line 103 "sparqlwords.gperf"
{"ISURI", SPARQL_BIF , SPAR_BIF_ISURI},
#line 84 "sparqlwords.gperf"
{"GROUP", GROUP_L , 0},
#line 92 "sparqlwords.gperf"
{"INF", INF_L , 0},
#line 32 "sparqlwords.gperf"
{"ASC", ASC_L , 0},
#line 117 "sparqlwords.gperf"
{"MD5", SPARQL_BIF , SPAR_BIF_MD5},
#line 116 "sparqlwords.gperf"
{"MAX", MAX_L , 0},
#line 164 "sparqlwords.gperf"
{"SHA224", SPARQL_BIF , SPAR_BIF_SHA224},
#line 79 "sparqlwords.gperf"
{"FROM", FROM_L , 0},
#line 34 "sparqlwords.gperf"
{"ASSUME", ASSUME_L , 0},
#line 132 "sparqlwords.gperf"
{"OFFBAND", OFFBAND_L , 0},
#line 194 "sparqlwords.gperf"
{"TRUE", true_L , 0},
#line 167 "sparqlwords.gperf"
{"SHA512", SPARQL_BIF , SPAR_BIF_SHA512},
#line 119 "sparqlwords.gperf"
{"MINUS", MINUS_L , 0},
#line 210 "sparqlwords.gperf"
{"UCASE", SPARQL_BIF , SPAR_BIF_UCASE},
#line 139 "sparqlwords.gperf"
{"PREDICATE", PREDICATE_L , 0},
#line 215 "sparqlwords.gperf"
{"USING", USING_L , 0},
#line 70 "sparqlwords.gperf"
{"EBV_INT", SPARQL_BIF , SPAR_BIF_EBV_INT},
#line 52 "sparqlwords.gperf"
{"COPY", COPY_L , 0},
#line 47 "sparqlwords.gperf"
{"CEIL", SPARQL_BIF , SPAR_BIF_CEIL},
#line 188 "sparqlwords.gperf"
{"TEXT", TEXT_L , 0},
#line 109 "sparqlwords.gperf"
{"LIMIT", LIMIT_L , 0},
#line 138 "sparqlwords.gperf"
{"PRECISION", PRECISION_L , 0},
#line 66 "sparqlwords.gperf"
{"DETACH", DETACH_L , 0},
#line 62 "sparqlwords.gperf"
{"DELETE", DELETE_L , 0},
#line 162 "sparqlwords.gperf"
{"SETS", SETS_L , 0},
#line 221 "sparqlwords.gperf"
{"WITH", WITH_L , 0},
#line 35 "sparqlwords.gperf"
{"ATTACH", ATTACH_L , 0},
#line 158 "sparqlwords.gperf"
{"SAMPLE", SAMPLE_L , 0},
#line 121 "sparqlwords.gperf"
{"MODIFY", MODIFY_L , 0},
#line 190 "sparqlwords.gperf"
{"TIMEZONE", SPARQL_BIF , SPAR_BIF_TIMEZONE},
#line 157 "sparqlwords.gperf"
{"SAMETERM", SPARQL_BIF , SPAR_BIF_SAMETERM},
#line 122 "sparqlwords.gperf"
{"MONTH", SPARQL_BIF , SPAR_BIF_MONTH},
#line 126 "sparqlwords.gperf"
{"NIL", NIL_L , 0},
#line 219 "sparqlwords.gperf"
{"WHEN", WHEN_L , 0},
#line 169 "sparqlwords.gperf"
{"SOFT", SOFT_L , 0},
#line 146 "sparqlwords.gperf"
{"REPLACE", SPARQL_BIF , SPAR_BIF_REPLACE},
#line 67 "sparqlwords.gperf"
{"DISTINCT", DISTINCT_L , 0},
#line 33 "sparqlwords.gperf"
{"ASK", ASK_L , 0},
#line 95 "sparqlwords.gperf"
{"INSERT", INSERT_L , 0},
#line 108 "sparqlwords.gperf"
{"LIKE", LIKE_L , 0},
#line 83 "sparqlwords.gperf"
{"GRAPH", GRAPH_L , 0},
#line 212 "sparqlwords.gperf"
{"UNDEF", UNDEF_L , 0},
#line 93 "sparqlwords.gperf"
{"INDEX", INDEX_L , 0},
#line 86 "sparqlwords.gperf"
{"GROUPING", GROUPING_L , 0},
#line 61 "sparqlwords.gperf"
{"DEFMACRO", DEFMACRO_L , 0},
#line 71 "sparqlwords.gperf"
{"ELSE", ELSE_L , 0},
#line 65 "sparqlwords.gperf"
{"DESCRIBE", DESCRIBE_L , 0},
#line 181 "sparqlwords.gperf"
{"STRUUID", SPARQL_BIF , SPAR_BIF_STRUUID},
#line 173 "sparqlwords.gperf"
{"STR", SPARQL_BIF , SPAR_BIF_STR},
#line 106 "sparqlwords.gperf"
{"LCASE", SPARQL_BIF , SPAR_BIF_LCASE},
#line 72 "sparqlwords.gperf"
{"ENCODE_FOR_URI", SPARQL_BIF , SPAR_BIF_ENCODE_FOR_URI},
#line 51 "sparqlwords.gperf"
{"CONTAINS", SPARQL_BIF , SPAR_BIF_CONTAINS},
#line 184 "sparqlwords.gperf"
{"SUBSTR", SPARQL_BIF , SPAR_BIF_SUBSTR},
#line 137 "sparqlwords.gperf"
{"ORDER", ORDER_L , 0},
#line 218 "sparqlwords.gperf"
{"VALUES", VALUES_L , 0},
#line 205 "sparqlwords.gperf"
{"T_OUT", T_OUT_L , 0},
#line 178 "sparqlwords.gperf"
{"STRLANG", SPARQL_BIF , SPAR_BIF_STRLANG},
#line 140 "sparqlwords.gperf"
{"PREFIX", PREFIX_L , 0},
#line 172 "sparqlwords.gperf"
{"STORAGE", STORAGE_L , 0},
#line 76 "sparqlwords.gperf"
{"FALSE", false_L , 0},
#line 179 "sparqlwords.gperf"
{"STRLEN", SPARQL_BIF , SPAR_BIF_STRLEN},
#line 53 "sparqlwords.gperf"
{"COUNT", COUNT_L , 0},
#line 168 "sparqlwords.gperf"
{"SILENT", SILENT_L , 0},
#line 128 "sparqlwords.gperf"
{"NOW", SPARQL_BIF , SPAR_BIF_NOW},
#line 209 "sparqlwords.gperf"
{"T_STEP", T_STEP_L , 0},
#line 120 "sparqlwords.gperf"
{"MINUTES", SPARQL_BIF , SPAR_BIF_MINUTES},
#line 134 "sparqlwords.gperf"
{"OPTIONAL", OPTIONAL_L , 0},
#line 105 "sparqlwords.gperf"
{"LANGMATCHES", SPARQL_BIF , SPAR_BIF_LANGMATCHES},
#line 129 "sparqlwords.gperf"
{"NULL", NULL_L , 0},
#line 63 "sparqlwords.gperf"
{"DEREF", DEREF_L , 0},
#line 198 "sparqlwords.gperf"
{"T_DISTINCT", T_DISTINCT_L , 0},
#line 54 "sparqlwords.gperf"
{"CREATE", CREATE_L , 0},
#line 154 "sparqlwords.gperf"
{"SAME_AS_P", SAME_AS_P_L , 0},
#line 28 "sparqlwords.gperf"
{"ALL", ALL_L , 0},
#line 59 "sparqlwords.gperf"
{"DEFAULT", DEFAULT_L , 0},
#line 150 "sparqlwords.gperf"
{"SCORE", SCORE_L , 0},
#line 176 "sparqlwords.gperf"
{"STRDT", SPARQL_BIF , SPAR_BIF_STRDT},
#line 29 "sparqlwords.gperf"
{"ALTER", ALTER_L , 0},
#line 48 "sparqlwords.gperf"
{"COALESCE", SPARQL_BIF , SPAR_BIF_COALESCE},
#line 75 "sparqlwords.gperf"
{"EXISTS", EXISTS_L , 0},
#line 183 "sparqlwords.gperf"
{"SUBJECT", SUBJECT_L , 0},
#line 94 "sparqlwords.gperf"
{"INFERENCE", INFERENCE_L , 0},
#line 199 "sparqlwords.gperf"
{"T_END_FLAG", T_END_FLAG_L , 0},
#line 193 "sparqlwords.gperf"
{"TRANSITIVE", TRANSITIVE_L , 0},
#line 98 "sparqlwords.gperf"
{"ISBLANK", SPARQL_BIF , SPAR_BIF_ISBLANK},
#line 101 "sparqlwords.gperf"
{"ISNUMERIC", SPARQL_BIF , SPAR_BIF_ISNUMERIC},
#line 170 "sparqlwords.gperf"
{"SOURCE", GRAPH_L , 0},
#line 133 "sparqlwords.gperf"
{"OFFSET", OFFSET_L , 0},
#line 222 "sparqlwords.gperf"
{"XML", XML_L , 0},
#line 80 "sparqlwords.gperf"
{"FUNCTION", FUNCTION_L , 0},
#line 148 "sparqlwords.gperf"
{"ROLLUP", ROLLUP_L , 0},
#line 153 "sparqlwords.gperf"
{"SAME_AS_O", SAME_AS_O_L , 0},
#line 156 "sparqlwords.gperf"
{"SAME_AS_S_O", SAME_AS_S_O_L , 0},
#line 85 "sparqlwords.gperf"
{"GROUP_CONCAT", GROUP_CONCAT_L , 0},
#line 197 "sparqlwords.gperf"
{"T_DIRECTION", T_DIRECTION_L , 0},
#line 220 "sparqlwords.gperf"
{"WHERE", WHERE_L , 0},
#line 50 "sparqlwords.gperf"
{"CONSTRUCT", CONSTRUCT_L , 0},
#line 161 "sparqlwords.gperf"
{"SERVICE", SERVICE_L , 0},
#line 45 "sparqlwords.gperf"
{"CLASS", CLASS_L , 0},
#line 77 "sparqlwords.gperf"
{"FILTER", FILTER_L , 0},
#line 107 "sparqlwords.gperf"
{"LIBRARY", LIBRARY_L , 0},
#line 200 "sparqlwords.gperf"
{"T_EXISTS", T_EXISTS_L , 0},
#line 81 "sparqlwords.gperf"
{"HOURS", SPARQL_BIF , SPAR_BIF_HOURS},
#line 152 "sparqlwords.gperf"
{"SAME_AS", SAME_AS_L , 0},
#line 155 "sparqlwords.gperf"
{"SAME_AS_S", SAME_AS_S_L , 0},
#line 102 "sparqlwords.gperf"
{"ISREF", SPARQL_BIF , SPAR_BIF_ISREF},
#line 160 "sparqlwords.gperf"
{"SELECT", SELECT_L , 0},
#line 175 "sparqlwords.gperf"
{"STRBEFORE", SPARQL_BIF , SPAR_BIF_STRBEFORE},
#line 203 "sparqlwords.gperf"
{"T_MAX", T_MAX_L , 0},
#line 165 "sparqlwords.gperf"
{"SHA256", SPARQL_BIF , SPAR_BIF_SHA256},
#line 143 "sparqlwords.gperf"
{"REGEX", SPARQL_BIF , SPAR_BIF_REGEX},
#line 74 "sparqlwords.gperf"
{"EXCLUSIVE", EXCLUSIVE_L , 0},
#line 145 "sparqlwords.gperf"
{"REMOVE_UNICODE3_ACCENTS", SPARQL_BIF , SPAR_BIF_REMOVE_UNICODE3_ACCENTS},
#line 46 "sparqlwords.gperf"
{"CLEAR", CLEAR_L , 0},
#line 78 "sparqlwords.gperf"
{"FLOOR", SPARQL_BIF , SPAR_BIF_FLOOR},
#line 159 "sparqlwords.gperf"
{"SECONDS", SPARQL_BIF , SPAR_BIF_SECONDS},
#line 177 "sparqlwords.gperf"
{"STRENDS", SPARQL_BIF , SPAR_BIF_STRENDS},
#line 151 "sparqlwords.gperf"
{"SCORE_LIMIT", SCORE_LIMIT_L , 0},
#line 207 "sparqlwords.gperf"
{"T_NO_ORDER", T_NO_ORDER_L , 0},
#line 147 "sparqlwords.gperf"
{"RETURNS", RETURNS_L , 0},
#line 180 "sparqlwords.gperf"
{"STRSTARTS", SPARQL_BIF , SPAR_BIF_STRSTARTS},
#line 208 "sparqlwords.gperf"
{"T_SHORTEST_ONLY", T_SHORTEST_ONLY_L , 0},
#line 182 "sparqlwords.gperf"
{"SUBCLASS", SUBCLASS_L , 0},
#line 174 "sparqlwords.gperf"
{"STRAFTER", SPARQL_BIF , SPAR_BIF_STRAFTER},
#line 171 "sparqlwords.gperf"
{"SQLQUERY", SQLQUERY_L , 0},
#line 111 "sparqlwords.gperf"
{"LOCAL", LOCAL_L , 0},
#line 206 "sparqlwords.gperf"
{"T_NO_CYCLES", T_NO_CYCLES_L , 0},
#line 196 "sparqlwords.gperf"
{"T_CYCLES_ONLY", T_CYCLES_ONLY_L , 0},
#line 201 "sparqlwords.gperf"
{"T_FINAL_AS", T_FINAL_AS_L , 0},
#line 100 "sparqlwords.gperf"
{"ISLITERAL", SPARQL_BIF , SPAR_BIF_ISLITERAL},
#line 110 "sparqlwords.gperf"
{"LITERAL", LITERAL_L , 0}
};
static const short lookup[] =
{
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, 1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, 2, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, 3, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 4, -1, -1, -1, 5,
6, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, 7, -1, -1, -1, 8, -1,
-1, -1, -1, -1, -1, -1, -1, -1, 9, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, 10,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, 11, 12, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, 13,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
14, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, 15, -1, -1,
-1, -1, -1, -1, -1, -1, 16, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
17, 18, -1, 19, -1, 20, -1, -1, 21, 22,
-1, -1, -1, -1, 23, 24, -1, -1, -1, -1,
25, -1, -1, -1, 26, -1, -1, -1, -1, -1,
27, -1, -1, -1, -1, -1, -1, -1, 28, 29,
30, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, 31, -1, -1, -1, -1, -1, 32, -1,
33, 34, -1, -1, 35, -1, -1, 36, -1, -1,
-1, -1, 37, -1, -1, 38, 39, 40, -1, -1,
41, -1, 42, 43, -1, -1, 44, -1, -1, -1,
45, -1, -1, -1, 46, -1, 47, 48, -1, 49,
-1, 50, -1, -1, -1, 51, 52, -1, -1, -1,
53, 54, -1, -1, -1, -1, 55, -1, -1, -1,
-1, -1, 56, 57, -1, -1, -1, -1, -1, -1,
58, -1, -1, 59, -1, 60, -1, -1, -1, -1,
-1, 61, 62, -1, 63, 64, -1, -1, -1, -1,
65, 66, -1, -1, 67, 68, -1, 69, -1, 70,
-1, 71, 72, -1, 73, -1, -1, -1, 74, -1,
75, -1, -1, 76, -1, -1, -1, -1, 77, -1,
-1, -1, -1, -1, -1, 78, 79, -1, -1, 80,
81, -1, -1, -1, 82, -1, -1, -1, -1, -1,
83, -1, 84, -1, 85, 86, 87, 88, -1, -1,
89, 90, -1, 91, -1, 92, 93, -1, 94, 95,
96, -1, 97, -1, -1, -1, 98, 99, 100, -1,
-1, -1, -1, 101, -1, 102, -1, -1, 103, -1,
-1, 104, -1, -1, 105, 106, -1, 107, -1, 108,
-1, -1, 109, 110, -1, -1, -1, -1, -1, 111,
112, 113, -1, -1, -1, -1, 114, 115, 116, -1,
117, -1, -1, -1, -1, -1, -1, 118, -1, -1,
-1, 119, 120, 121, -1, -1, 122, 123, 124, 125,
126, 127, -1, -1, -1, 128, 129, 130, -1, 131,
-1, -1, 132, 133, 134, -1, -1, 135, -1, 136,
137, -1, -1, -1, -1, 138, -1, -1, -1, -1,
139, 140, -1, 141, 142, 143, -1, -1, -1, -1,
-1, -1, -1, 144, 145, 146, -1, 147, -1, 148,
-1, -1, 149, -1, -1, 150, -1, -1, -1, 151,
-1, -1, -1, 152, -1, -1, -1, 153, -1, -1,
-1, 154, -1, -1, 155, -1, 156, -1, 157, 158,
-1, 159, 160, -1, 161, 162, -1, -1, -1, 163,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
164, -1, -1, -1, 165, -1, -1, -1, -1, -1,
166, 167, -1, -1, -1, -1, -1, -1, -1, -1,
168, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, 169, -1, 170, -1, 171, -1, 172, -1, -1,
173, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, 174, -1, -1,
-1, 175, -1, 176, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, 177, -1, -1, -1,
-1, -1, -1, 178, 179, -1, -1, -1, -1, -1,
-1, -1, -1, 180, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, 181, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 182, -1, -1, -1, -1,
-1, 183, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 184, 185, -1, -1, -1,
186, -1, -1, 187, -1, -1, -1, -1, 188, -1,
-1, -1, -1, 189, 190, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, 191,
-1, -1, -1, -1, 192, -1, -1, -1, -1, 193,
-1, -1, -1, 194, -1, -1, -1, -1, -1, -1,
-1, -1, 195, -1, -1, 196, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, 197
};
#ifdef __GNUC__
__inline
#if defined __GNUC_STDC_INLINE__ || defined __GNUC_GNU_INLINE__
__attribute__ ((__gnu_inline__))
#endif
#endif
const struct sparql_keyword *
sparql_lex_hash_kw (register const char *str, register unsigned int len)
{
if (len <= MAX_WORD_LENGTH && len >= MIN_WORD_LENGTH)
{
register int key = hash (str, len);
if (key <= MAX_HASH_VALUE && key >= 0)
{
register int index = lookup[key];
if (index >= 0)
{
register const char *s = wordlist[index].kwd;
if ((((unsigned char)*str ^ (unsigned char)*s) & ~32) == 0 && !gperf_case_strcmp (str, s))
return &wordlist[index];
}
}
}
return 0;
}
|
andywx/agensgraph
|
src/include/commands/copyrdf.h
|
<gh_stars>1-10
#ifndef COPYRDF_H
#define COPYRDF_H
#include "nodes/execnodes.h"
#include "nodes/parsenodes.h"
#include "parser/parse_node.h"
#include "tcop/dest.h"
extern void DoCopyRdf(CopyRdfStmt *stmt);
#endif /* COPYRDF_H */
|
andywx/agensgraph
|
src/backend/parser/Dk.h
|
<filename>src/backend/parser/Dk.h
/*
* Dksets.h
*
* Created on: 2019年11月16日
* Author: liu
*/
#include "sparql.h"
#include "sparql_l.h"
#ifndef SRC_BACKEND_PARSER_DKSETS_H_
#define SRC_BACKEND_PARSER_DKSETS_H_
struct mem_pool_s;
typedef struct mem_pool_s mem_pool_t;
typedef struct mem_block_s mem_block_t;
struct mem_block_s
{
struct mem_block_s * mb_next;
size_t mb_fill;
size_t mb_size;
};
typedef void *(*rc_constr_t) (void *cdata);
typedef void (*rc_destr_t) (void *item);
typedef struct mutex_s dk_mutex_t;
typedef struct resource_s
{
uint32 rc_fill;
uint32 rc_size;
void ** rc_items;
uint32 * rc_item_time;
void * rc_client_data;
rc_constr_t rc_constructor;
rc_destr_t rc_destructor;
rc_destr_t rc_clear_func;
dk_mutex_t * rc_mtx;
/* Monitoring */
uint32 rc_gets;
uint32 rc_stores;
uint32 rc_n_empty;
uint32 rc_n_full;
uint32 rc_max_size;
#ifdef RC_DBG
struct resource_s **rc_family;
int rc_family_size;
#endif
} resource_t;
typedef void mem_pool_size_cap_cbk_t (mem_pool_t *mp, void *cbk_env);
typedef struct mem_pool_size_cap_s {
mem_pool_size_cap_cbk_t * cbk;
size_t limit;
size_t last_cbk_limit;
void * cbk_env;
} mem_pool_size_cap_t;
struct mem_pool_s
{
mem_block_t * mp_first;
int mp_block_size;
size_t mp_bytes;
size_t mp_max_bytes;
size_t mp_reserved;
dk_hash_t mp_large;
resource_t ** mp_large_reuse;
dk_hash_t * mp_unames;
dk_set_t mp_trash;
#if defined (DEBUG) || defined (MALLOC_DEBUG) || !defined(NDEBUG)
const char * mp_alloc_file;
int mp_alloc_line;
#endif
caddr_t mp_comment;
mem_pool_size_cap_t mp_size_cap;
struct TLSF_struct * mp_tlsf;
};
#ifdef MALLOC_DEBUG
void dbg_mp_set_push (const char *file, int line, mem_pool_t * mp, dk_set_t * set, void *elt);
dk_set_t dbg_t_cons (const char *file, int line, void *car, dk_set_t cdr);
void dbg_t_set_push (const char *file, int line, dk_set_t * set, void *elt);
int dbg_t_set_pushnew (const char *file, int line, s_node_t ** set, void *item);
int dbg_t_set_push_new_string (const char *file, int line, s_node_t ** set, char *item);
void *dbg_t_set_pop (const char *file, int line, dk_set_t * set);
dk_set_t dbg_t_set_union (const char *file, int line, dk_set_t s1, dk_set_t s2);
dk_set_t dbg_t_set_intersect (const char *file, int line, dk_set_t s1, dk_set_t s2);
dk_set_t dbg_t_set_diff (const char *file, int line, dk_set_t s1, dk_set_t s2);
caddr_t *dbg_t_list_to_array (const char *file, int line, dk_set_t list);
caddr_t *dbg_t_revlist_to_array (const char *file, int line, dk_set_t list);
int dbg_t_set_delete (const char *file, int line, dk_set_t * set, void *item);
void * dbg_t_set_delete_nth (const char *file, int line, dk_set_t * set, int nth);
dk_set_t dbg_t_set_copy (const char *file, int line, dk_set_t s);
#define mp_set_push(mp,set,elt) dbg_mp_set_push (__FILE__, __LINE__, (mp), (set), (elt))
#define t_cons(car,cdr) dbg_t_cons (__FILE__, __LINE__, (car), (cdr))
#define t_set_push(set,elt) dbg_t_set_push (__FILE__, __LINE__, (set), (elt))
#define t_set_pushnew(set,item) dbg_t_set_pushnew (__FILE__, __LINE__, (set), (item))
#define t_set_push_new_string(set,item) dbg_t_set_push_new_string (__FILE__, __LINE__, (set), (item))
#define t_set_pop(set) dbg_t_set_pop (__FILE__, __LINE__, (set))
#define t_set_union(s1,s2) dbg_t_set_union (__FILE__, __LINE__, (s1), (s2))
#define t_set_intersect(s1,s2) dbg_t_set_intersect (__FILE__, __LINE__, (s1), (s2))
#define t_set_diff(s1,s2) dbg_t_set_diff (__FILE__, __LINE__, (s1), (s2))
#define t_list_to_array(list) dbg_t_list_to_array (__FILE__, __LINE__, (list))
#define t_revlist_to_array(list) dbg_t_revlist_to_array (__FILE__, __LINE__, (list))
#define t_set_delete(set,item) dbg_t_set_delete (__FILE__, __LINE__, (set), (item))
#define t_set_delete_nth(set,nth) dbg_t_set_delete_nth (__FILE__, __LINE__, (set), (nth))
#define t_set_copy(s) dbg_t_set_copy (__FILE__, __LINE__, (s))
#else
void mp_set_push (mem_pool_t * mp, dk_set_t * set, void *elt);
dk_set_t t_cons (void *car, dk_set_t cdr);
void t_set_push (dk_set_t * set, void *elt);
int t_set_pushnew (s_node_t ** set, void *item);
int t_set_push_new_string (s_node_t ** set, char *item);
void *t_set_pop (dk_set_t * set);
dk_set_t t_set_union (dk_set_t s1, dk_set_t s2);
dk_set_t t_set_intersect (dk_set_t s1, dk_set_t s2);
dk_set_t t_set_diff (dk_set_t s1, dk_set_t s2);
caddr_t *t_list_to_array (dk_set_t list);
caddr_t *t_revlist_to_array (dk_set_t list);
int t_set_delete (dk_set_t * set, void *item);
void * t_set_delete_nth (dk_set_t * set, int nth);
dk_set_t t_set_copy (dk_set_t s);
#endif
uint32 dk_set_length (s_node_t * set);
extern dk_set_t dk_set_nreverse (dk_set_t set);
#endif /* SRC_BACKEND_PARSER_DKSETS_H_ */
|
andywx/agensgraph
|
src/backend/parser/sparql_p.h
|
/* A Bison parser, made by GNU Bison 3.0.4. */
/* Bison interface for Yacc-like parsers in C
Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* As a special exception, you may create a larger work that contains
part or all of the Bison parser skeleton and distribute that work
under terms of your choice, so long as that work isn't itself a
parser generator using the skeleton or a modified version thereof
as a parser skeleton. Alternatively, if you modify or redistribute
the parser skeleton itself, you may (at your option) remove this
special exception, which will cause the skeleton and the resulting
Bison output files to be licensed under the GNU General Public
License without this special exception.
This special exception was added by the Free Software Foundation in
version 2.2 of Bison. */
#ifndef YY_SPARYY_SPARQL_P_H_INCLUDED
# define YY_SPARYY_SPARQL_P_H_INCLUDED
/* Debug traces. */
#ifndef YYDEBUG
# define YYDEBUG 0
#endif
#if YYDEBUG
extern int sparyydebug;
#endif
/* Token type. */
#ifndef YYTOKENTYPE
# define YYTOKENTYPE
enum yytokentype
{
__SPAR_PUNCT_BEGIN = 258,
_AMP_AMP = 259,
_BACKQUOTE = 260,
_BANG = 261,
_BAR = 262,
_BAR_BAR = 263,
_CARET = 264,
_CARET_CARET = 265,
_COMMA = 266,
_DOT = 267,
_EQ = 268,
_GE = 269,
_GT = 270,
_LBRA = 271,
_LE = 272,
_LPAR = 273,
_LSQBRA = 274,
_LT = 275,
_MINUS = 276,
_NOT_EQ = 277,
_PLUS = 278,
_PLUS_GT = 279,
_QMARK = 280,
_RBRA = 281,
_RPAR = 282,
_RSQBRA = 283,
_SEMI = 284,
_SLASH = 285,
_STAR = 286,
_STAR_GT = 287,
a_L = 288,
ADD_L = 289,
ALL_L = 290,
ALTER_L = 291,
AS_L = 292,
ASC_L = 293,
ASK_L = 294,
ASSUME_L = 295,
ATTACH_L = 296,
AVG_L = 297,
BASE_L = 298,
BIJECTION_L = 299,
BIND_L = 300,
BINDINGS_L = 301,
BOUND_L = 302,
BY_L = 303,
CASE_L = 304,
CLASS_L = 305,
CLEAR_L = 306,
CREATE_L = 307,
CONSTRUCT_L = 308,
COPY_L = 309,
COUNT_L = 310,
COUNT_LPAR = 311,
COUNT_DISTINCT_L = 312,
CUBE_L = 313,
DATA_L = 314,
DATATYPE_L = 315,
DEFAULT_L = 316,
DEFINE_L = 317,
DEFMACRO_L = 318,
DELETE_L = 319,
DEREF_L = 320,
DESC_L = 321,
DESCRIBE_L = 322,
DETACH_L = 323,
DISTINCT_L = 324,
DROP_L = 325,
ELSE_L = 326,
END_L = 327,
EXCLUSIVE_L = 328,
EXISTS_L = 329,
false_L = 330,
FILTER_L = 331,
FROM_L = 332,
FUNCTION_L = 333,
GEO_L = 334,
GRAPH_L = 335,
GROUP_L = 336,
GROUP_CONCAT_L = 337,
GROUPING_L = 338,
HAVING_L = 339,
IDENTIFIED_L = 340,
IFP_L = 341,
IN_L = 342,
INF_L = 343,
INDEX_L = 344,
INFERENCE_L = 345,
INSERT_L = 346,
INTO_L = 347,
IRI_L = 348,
LANG_L = 349,
LIBRARY_L = 350,
LIKE_L = 351,
LIMIT_L = 352,
LITERAL_L = 353,
LOCAL_L = 354,
LOAD_L = 355,
MACRO_L = 356,
MAKE_L = 357,
MAP_L = 358,
MAX_L = 359,
MIN_L = 360,
MINUS_L = 361,
MODIFY_L = 362,
MOVE_L = 363,
NAMED_L = 364,
NAN_L = 365,
NIL_L = 366,
NOT_L = 367,
NOT_EXISTS_L = 368,
NOT_FROM_L = 369,
NOT_IN_L = 370,
NOT_NULL_L = 371,
NOT_USING_L = 372,
NULL_L = 373,
OBJECT_L = 374,
OF_L = 375,
OFFBAND_L = 376,
OFFSET_L = 377,
OPTIONAL_L = 378,
OPTION_L = 379,
ORDER_L = 380,
PRECISION_L = 381,
PREDICATE_L = 382,
PREFIX_L = 383,
QUAD_L = 384,
REDUCED_L = 385,
RETURNS_L = 386,
ROLLUP_L = 387,
SAME_AS_L = 388,
SAME_AS_O_L = 389,
SAME_AS_P_L = 390,
SAME_AS_S_L = 391,
SAME_AS_S_O_L = 392,
SAMPLE_L = 393,
SCORE_L = 394,
SCORE_LIMIT_L = 395,
SELECT_L = 396,
SERVICE_L = 397,
SETS_L = 398,
SILENT_L = 399,
SOFT_L = 400,
SQLQUERY_L = 401,
STORAGE_L = 402,
SUBCLASS_L = 403,
SUBJECT_L = 404,
SUM_L = 405,
TABID_L = 406,
TABLE_OPTION_L = 407,
TEXT_L = 408,
THEN_L = 409,
TIES_L = 410,
TO_L = 411,
TOP_L = 412,
TRANSITIVE_L = 413,
T_CYCLES_ONLY_L = 414,
T_DIRECTION_L = 415,
T_DISTINCT_L = 416,
T_END_FLAG_L = 417,
T_EXISTS_L = 418,
T_FINAL_AS_L = 419,
T_IN_L = 420,
T_MAX_L = 421,
T_MIN_L = 422,
T_OUT_L = 423,
T_NO_CYCLES_L = 424,
T_NO_ORDER_L = 425,
T_SHORTEST_ONLY_L = 426,
T_STEP_L = 427,
true_L = 428,
UNBOUND_L = 429,
UNDEF_L = 430,
UNION_L = 431,
USING_L = 432,
VALUES_L = 433,
WHEN_L = 434,
WHERE_L = 435,
WITH_L = 436,
XML_L = 437,
__SPAR_PUNCT_END = 438,
START_OF_SPARQL_TEXT = 439,
END_OF_SPARQL_TEXT = 440,
SPARUL_RUN_SUBTYPE = 441,
SPARUL_INSERT_DATA = 442,
SPARUL_DELETE_DATA = 443,
__SPAR_NONPUNCT_START = 444,
SPARQL_BIF = 445,
SPARQL_INTEGER = 446,
SPARQL_DECIMAL = 447,
SPARQL_DOUBLE = 448,
SPARQL_STRING = 449,
SPARQL_SQLTEXT = 450,
LANGTAG = 451,
QNAME = 452,
QNAME_NS = 453,
BLANK_NODE_LABEL = 454,
Q_IRI_REF = 455,
QD_VARNAME = 456,
QD_COLON_PARAMNAME = 457,
QD_COLON_PARAMNUM = 458,
SPARQL_PLAIN_ID = 459,
SPARQL_SQL_ALIASCOLNAME = 460,
SPARQL_SQL_QTABLENAME = 461,
SPARQL_SQL_QTABLECOLNAME = 462,
__SPAR_NONPUNCT_END = 463,
PRECODE_EXPN_PREC = 464,
_COLON = 465,
MATH_UPLUS = 466,
MATH_UMINUS = 467,
PPATH_ALTERNATIVE = 468,
PPATH_SEQUENCE = 469,
PPATH_CARET = 470,
PPATH_MOD = 471,
PPATH_BANG = 472
};
#endif
/* Value type. */
#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
union YYSTYPE
{
#line 93 "sparql_p.y" /* yacc.c:1909 */
void * box;
void * *boxes;
ptrlong token_type;
ptrlong nonboxed_int;
SPART *tree;
SPART **trees;
dk_set_t list;
dk_set_t backstack;
spar_lexbmk_t *bookmark;
void *nothing;
#line 285 "sparql_p.h" /* yacc.c:1909 */
};
typedef union YYSTYPE YYSTYPE;
# define YYSTYPE_IS_TRIVIAL 1
# define YYSTYPE_IS_DECLARED 1
#endif
int sparyyparse (sparp_t * sparp_arg);
#endif /* !YY_SPARYY_SPARQL_P_H_INCLUDED */
|
andywx/agensgraph
|
src/backend/parser/sparql.h
|
#pragma once
#include <stddef.h>
typedef char *caddr_t;
# ifndef ptrlong
# define ptrlong long
# endif
#define DV_TYPE_OF(x) \
(IS_BOX_POINTER (x) \
? (dtp_t) box_tag(x) \
: ((dtp_t)(DV_LONG_INT)) )
#define SPAR_ALIAS (ptrlong)1001 /*!< Alias, (expn AS ?varname). spar_dealias() is identity function for non-aliases and returns expn for aliases. Alias of alias can be treated as an error. */
#define SPAR_BLANK_NODE_LABEL (ptrlong)1002
#define SPAR_BUILT_IN_CALL (ptrlong)1003
#define SPAR_CONV (ptrlong)1004 /*!< Tree type for temporary use in SQL printer (conversion from one format to other) */
#define SPAR_FUNCALL (ptrlong)1005
#define SPAR_GP (ptrlong)1006 /*!< Tree type for group graph pattern, the subtype could be 0 for plain group, graph group or ctor, SELECT_L for subquery, WHERE_L for top-level, UNION_L for unions, OPTIONAL_L for optionals */
#define SPAR_REQ_TOP (ptrlong)1007
#define SPAR_RETVAL (ptrlong)1008 /*!< Tree type for temporary use in SQL printer; this is similar to variable but does not search for field via equiv */
#define SPAR_LIT (ptrlong)1009
#define SPAR_QNAME (ptrlong)1011
#define SPAR_SQLCOL (ptrlong)1012
#define SPAR_VARIABLE (ptrlong)1013
#define SPAR_TRIPLE (ptrlong)1014
#define SPAR_QM_SQL_FUNCALL (ptrlong)1015
#define SPAR_CODEGEN (ptrlong)1016
#define SPAR_LIST (ptrlong)1017
#define SPAR_GRAPH (ptrlong)1018
#define SPAR_WHERE_MODIFS (ptrlong)1019
#define SPAR_SERVICE_INV (ptrlong)1020 /*!< Tree type for details of invocation of an external service endpoint */
#define SPAR_BINDINGS_INV (ptrlong)1021 /*!< Tree type for details of bindings associated with gp */
#define SPAR_DEFMACRO (ptrlong)1022
#define SPAR_MACROCALL (ptrlong)1023
#define SPAR_MACROPU (ptrlong)1024 /*!< Tree type for macro parameter usage --- the occurence of a variable name in a macro body */
#define SPAR_PPATH (ptrlong)1025 /*!< Tree type for property path */
#define SPAR_MIN_TREE_TYPE (ptrlong)1001
#define SPAR_MAX_TREE_TYPE (ptrlong)1025 /* Don't forget to adjust */
/* Don't forget to update spart_count_specific_elems_by_type(), sparp_tree_full_clone_int(), sparp_tree_full_copy(), spart_dump() and comments inside typedef struct spar_tree_s */
#define SPAR_BOP_EQ_NONOPT (ptrlong)1051 /*!< An equality that is not optimized into an equivalence class */
#define SPAR_BOP_EQNAMES (ptrlong)1052 /*!< A special "equality": arguments are variables whose names are merged into one equivalence class */
#define SPAR_UNION_WO_ALL (ptrlong)1053 /*!< A special union that will become SQL UNION, not SQL UNION ALL as we usually cheat */
#define SPAR_BIF_ABS (ptrlong)1101
#define SPAR_BIF_BNODE (ptrlong)1102
#define SPAR_BIF_CASEWHEN (ptrlong)1103
#define SPAR_BIF_CASEX (ptrlong)1104
#define SPAR_BIF_CEIL (ptrlong)1105
#define SPAR_BIF_COALESCE (ptrlong)1106
#define SPAR_BIF_CONCAT (ptrlong)1107
#define SPAR_BIF_CONTAINS (ptrlong)1108
#define SPAR_BIF_DAY (ptrlong)1109
#define SPAR_BIF_EBV (ptrlong)1110
#define SPAR_BIF_EBV_INT (ptrlong)1111
#define SPAR_BIF_ENCODE_FOR_URI (ptrlong)1112
#define SPAR_BIF_FLOOR (ptrlong)1113
#define SPAR_BIF_HOURS (ptrlong)1114
#define SPAR_BIF_IF (ptrlong)1115
#define SPAR_BIF_ISBLANK (ptrlong)1116
#define SPAR_BIF_ISIRI (ptrlong)1117
#define SPAR_BIF_ISLITERAL (ptrlong)1118
#define SPAR_BIF_ISNUMERIC (ptrlong)1119
#define SPAR_BIF_ISREF (ptrlong)1120
#define SPAR_BIF_ISURI (ptrlong)1121
#define SPAR_BIF_LANGMATCHES (ptrlong)1122
#define SPAR_BIF_LCASE (ptrlong)1123
#define SPAR_BIF_MD5 (ptrlong)1124
#define SPAR_BIF_MINUTES (ptrlong)1125
#define SPAR_BIF_MONTH (ptrlong)1126
#define SPAR_BIF_NOW (ptrlong)1127
#define SPAR_BIF_RAND (ptrlong)1128
#define SPAR_BIF_REGEX (ptrlong)1129
#define SPAR_BIF_REMOVE_UNICODE3_ACCENTS (ptrlong)1130
#define SPAR_BIF_REPLACE (ptrlong)1131
#define SPAR_BIF_ROUND (ptrlong)1132
#define SPAR_BIF_SAMETERM (ptrlong)1133
#define SPAR_BIF_SECONDS (ptrlong)1134
#define SPAR_BIF_SHA1 (ptrlong)1135
#define SPAR_BIF_SHA224 (ptrlong)1136
#define SPAR_BIF_SHA256 (ptrlong)1137
#define SPAR_BIF_SHA384 (ptrlong)1138
#define SPAR_BIF_SHA512 (ptrlong)1139
#define SPAR_BIF_STR (ptrlong)1140
#define SPAR_BIF_STRAFTER (ptrlong)1141
#define SPAR_BIF_STRBEFORE (ptrlong)1142
#define SPAR_BIF_STRDT (ptrlong)1143
#define SPAR_BIF_STRENDS (ptrlong)1144
#define SPAR_BIF_STRLANG (ptrlong)1145
#define SPAR_BIF_STRLEN (ptrlong)1146
#define SPAR_BIF_STRSTARTS (ptrlong)1147
#define SPAR_BIF_STRUUID (ptrlong)1148
#define SPAR_BIF_SUBSTR (ptrlong)1149
#define SPAR_BIF_TIMEZONE (ptrlong)1150
#define SPAR_BIF_TZ (ptrlong)1151
#define SPAR_BIF_UCASE (ptrlong)1152
#define SPAR_BIF_URI (ptrlong)1153
#define SPAR_BIF_UUID (ptrlong)1154
#define SPAR_BIF_VALID (ptrlong)1155
#define SPAR_BIF_YEAR (ptrlong)1156
#define SPAR_BIF__CUBE (ptrlong)1157
#define SPAR_BIF__ITEM_IN_VECTOR (ptrlong)1158
#define SPAR_BIF__GROUPING_LIST (ptrlong)1159
#define SPAR_BIF__GROUPING_SET (ptrlong)1160
#define SPAR_BIF__GROUPING_SETS (ptrlong)1161
#define SPAR_BIF__ROLLUP (ptrlong)1162
#define SPAR_SML_CREATE (ptrlong)1201
#define SPAR_SML_DROP (ptrlong)1202
#define SPAR_SML_ATTACH (ptrlong)1203
#define SPAR_SML_DETACH (ptrlong)1204
#define SPARP_MAX_LEX_DEPTH 150 /*!< Maximum allowed number of any opened parenthesis in SPARQL text. SQL lexer has its own limit of the sort, \c SCN3_MAX_LEX_DEPTH . Note that SCN3_MAX_LEX_DEPTH will stay in effect while SQL lexer is looking for end of SPARQL statement, deeper nesting of SPARQL subquery may mean smaller "remaining" limit on SPARQL. */
#define SPARP_MAX_BRACE_DEPTH 80 /*!< Maximum allowed number of any opened parenthesis outside pair of curly braces in SQL text. SQL lexer has its own limit of the sort, \c SCN3_MAX_BRACE_DEPTH */
#define SPARP_MAX_SYNTDEPTH SPARP_MAX_LEX_DEPTH+10
#define SPARP_CALLARG 1 /*!< The parser reads the macro call */
#define SPARP_DEFARG 2 /*!< The parser reads the arglist of a defmacro and remembers variable names as is in order to know what should be substituted in body */
#define SPARP_DEFBODY 4 /*!< The parser reads the body of a defmacro and remembers positions of variables in argument lists */
#define SPARP_PU_IN_TRIPLE 1
#define SPARP_PU_IN_READ 2
#define SPARP_PU_BGP 3
#define SSG_VALMODE_AUTO ((ssg_valmode_t)((ptrlong)(0x370))) /*!< Something simplest */
#define BOP_NOT (ptrlong)1
#define BOP_OR (ptrlong)3
#define BOP_AND (ptrlong)4
#define BOP_PLUS (ptrlong)5
#define BOP_MINUS (ptrlong)6
#define BOP_TIMES (ptrlong)7
#define BOP_DIV (ptrlong)8
#define BOP_EQ (ptrlong)9
#define BOP_NEQ (ptrlong)10
#define BOP_LT (ptrlong)11
#define BOP_LTE (ptrlong)12
#define BOP_GT (ptrlong)13
#define BOP_GTE (ptrlong)14
#define BOP_LIKE (ptrlong)15
#define BOP_NULL (ptrlong)16
#define BOP_SAME (ptrlong)17
#define BOP_NSAME (ptrlong)18
#define BOP_AS (ptrlong)21
#define BOP_IN_ATOM (ptrlong)22
#define BOP_MOD (ptrlong)23
#define DV_ARRAY_OF_POINTER 193
#define DV_DOUBLE_FLOAT 191
#define DV_LONG_INT 189
#define DV_NUMERIC 219
#define DV_DB_NULL 204
#define OPENLINKSW_BIF_NS_URI "http://www.openlinksw.com/schemas/bif#"
#define OPENLINKSW_SQL_NS_URI "http://www.openlinksw.com/schemas/sql#"
//
#define SPAR_ALIAS (ptrlong)1001 /*!< Alias, (expn AS ?varname). spar_dealias() is identity function for non-aliases and returns expn for aliases. Alias of alias can be treated as an error. */
#define SPAR_BIF__CUBE (ptrlong)1157
#define SPAR_BIF__GROUPING_LIST (ptrlong)1159
#define SPAR_BIF__GROUPING_SET (ptrlong)1160
#define SPAR_BIF__GROUPING_SETS (ptrlong)1161
#define SPAR_BIF__ROLLUP (ptrlong)1162
#define SPAR_BIF_CASEWHEN (ptrlong)1103
#define SPAR_BIF_REGEX (ptrlong)1129
#define SPAR_BIF_CASEX (ptrlong)1104
#define SPAR_LIST (ptrlong)1017
#define SPAR_LIT (ptrlong)1009
#define SPAR_MACROPU (ptrlong)1024 /*!< Tree type for macro parameter usage --- the occurence of a variable name in a macro body */
#define SPAR_QNAME (ptrlong)1011
#define SPAR_REQ_TOP (ptrlong)1007
#define SPAR_SERVICE_INV (ptrlong)1020 /*!< Tree type for details of invocation of an external service endpoint */
#define SPAR_UNION_WO_ALL (ptrlong)1053 /*!< A special union that will become SQL UNION, not SQL UNION ALL as we usually cheat */
#define SPAR_VARIABLE (ptrlong)1013
#define SPARP_CALLARG 1 /*!< The parser reads the macro call */
#define SPARP_DEFARG 2 /*!< The parser reads the arglist of a defmacro and remembers variable names as is in order to know what should be substituted in body */
#define SPARP_DEFBODY 4 /*!< The parser reads the body of a defmacro and remembers positions of variables in argument lists */
#define SPARP_SSRC_FROZEN_BY_PROTOCOL 0x1 /*!< The query can not change the dataset by FROM / FROM NAMED / USING / WITH / dereferencing, because the dataset is specified by protocol parameters. However re-declaration of a URI is permitted (e.g, "define input:named-graph-uri" and FROM for one and the same URI is OK). */
#define SPART_GRAPH_FROM 0x1000
#define SPART_GRAPH_NAMED 0x1010
#define SPART_GRAPH_NOT_FROM 0x1080
#define SPART_GRAPH_NOT_NAMED 0x1090
#define SPART_TRIPLE_FIELDS_COUNT 4
#define tr_graph tr_fields[0]
extern caddr_t uname_rdf_ns_uri_first;
extern caddr_t uname_rdf_ns_uri_nil;
extern caddr_t uname_rdf_ns_uri_rest;
extern caddr_t uname_rdf_ns_uri_type;
extern caddr_t uname_SPECIAL_cc_bif_c_AVG;
extern caddr_t uname_SPECIAL_cc_bif_c_COUNT;
extern caddr_t uname_SPECIAL_cc_bif_c_GROUPING;
extern caddr_t uname_SPECIAL_cc_bif_c_MAX;
extern caddr_t uname_SPECIAL_cc_bif_c_MIN;
extern caddr_t uname_SPECIAL_cc_bif_c_SUM;
extern caddr_t uname_virtrdf_ns_uri_DefaultServiceStorage;
extern caddr_t uname_virtrdf_ns_uri_QuadMapFormat;
extern caddr_t uname_virtrdf_ns_uri_QuadStorage;
extern caddr_t uname_xmlschema_ns_uri_hash_decimal;
extern caddr_t uname_xmlschema_ns_uri_hash_double;
#define SPAR_BIN_OP(dst,op,l,r) (dst) = spartlist (sparp_arg, 3, (op), (l), (r))
#define NUMERIC_PADDING 4
#define t_box_dv_short_string t_box_string
typedef unsigned char dtp_t;
typedef struct spar_tree_s SPART;
typedef struct s_node_s s_node_t, *dk_set_t;
extern dk_set_t dk_set_nreverse (dk_set_t set);
#define t_NEW_DB_NULL t_alloc_box (0, DV_DB_NULL)
typedef struct rdf_grab_config_s {
int rgc_pview_mode; /*!< The query is executed using procedure view that will form a result-set by calling more than one statement via exec() */
int rgc_all; /*!< Automatically add all IRI constants/vars (except P) to spare_src.ssrc_grab_consts */
int rgc_intermediate; /*!< Automatically add all IRI constants/vars (except P) to spare_src.ssrc_grab_consts */
dk_set_t rgc_consts; /*!< Constants to be used as names of additional graphs */
dk_set_t rgc_vars; /*!< Names of variables whose values should be used as names of additional graphs */
dk_set_t rgc_sa_graphs; /*!< SeeAlso graph names. Every time a value can be downloaded, its seeAlso values can also be downloaded */
dk_set_t rgc_sa_preds; /*!< SeeAlso predicate names. Every time a value can be downloaded, its seeAlso values can also be downloaded */
dk_set_t rgc_sa_vars; /*!< Names of variables whose values should be used as names of subjects (not objects!) for seeAlso predicates */
caddr_t rgc_depth; /*!< Number of iterations that can be made to find additional graphs */
caddr_t rgc_limit; /*!< Limit on number of grabbed remote documents */
caddr_t rgc_base; /*!< Base IRI to use as a first argument to the grab IRI resolver */
caddr_t rgc_destination; /*!< IRI of the graph to be extended */
caddr_t rgc_group_destination; /*!< IRI of the commonly used graph to be extended, in addition to usual flow */
caddr_t rgc_resolver_name; /*!< Name of function of the graph IRI resolver */
caddr_t rgc_loader_name; /*!< Name of function that actually loads the resource */
} rdf_grab_config_t;
typedef struct sparp_sources_s
{
rdf_grab_config_t ssrc_grab; /*!< Grabber configuration */
dk_set_t ssrc_common_sponge_options; /*!< Options that are added to every FROM ... OPTION ( ... ) list */
SPART * ssrc_graph_set_by_with; /*!< The precode expression of WITH clause, if exists */
SPART * ssrc_fallback_target; /*!< For debugging purposes, it may be convenient to fallback to virtrdf:DefaultSparul11Target or the like instead of "No default graph specified in the preamble..." error. Set the value of this field to non-NULL (by define input:target-fallback-graph-uri) for this effect. */
SPART * ssrc_fallback_default_graph; /*!< For debugging purposes, this can be used as an equivalent of "default graph specified by Graph Store" from spec. To set the value of this field to non-NULL, use define input:with-fallback-graph-uri. */
dk_set_t ssrc_default_graphs; /*!< Default graphs and NOT FROM graphs as set by protocol or FROM graph-uri-precode. All NOT FROM are after all FROM! */
dk_set_t ssrc_named_graphs; /*!< Named graphs and NOT FROM NAMED graphs as set by protocol or clauses. All NOT FROM NAMED are after all FROM NAMED! */
int ssrc_default_graphs_listed; /*!< At least one default graph was set, so the list of default graphs is exhaustive even if empty or consists of solely NOT FROM (NOT FROM may remove all FROM, making the list empty) */
int ssrc_named_graphs_listed; /*!< At least one named graph was set, so the list of named graphs is exhaustive even if empty or consists of solely NOT FROM NAMED */
int ssrc_freeze_status; /*!< Default and named graphs can not be overwritten if set by protocol or using/with defines in service endpoint config. There's no locking for NOT FROM and NOT FROM NAMED */
caddr_t ssrc_frozen_pragma_example; /*!< An example of name of pragma that prevents the user from dereferencing of variables and the like */
} sparp_sources_t;
#define SPARP_MAX_LEX_DEPTH 150
typedef struct dk_session_s dk_session_t;
#define sparp_env() sparp_arg->sparp_env
struct s_node_s
{
void * data;
s_node_t * next;
};
struct numeric_s{
char n_len; /* The number of digits before the decimal point. */
char n_scale; /* The number of digits after the decimal point. */
char n_invalid; /* NDF_NAN or NDF_INF */
char n_neg; /* 0 or 1 */
char n_value[NUMERIC_PADDING];
};
typedef struct sparp_env_s
{
/*spar_query_t * spare_sparqr;*/
ptrlong spare_start_lineno; /*!< The first line number of the query, may be nonzero if inlined into SQL */
ptrlong * spare_param_counter_ptr; /*!< Pointer to parameter counter used to convert '??' or '$?' to ':nnn' in the query */
dk_set_t spare_namespace_prefixes; /*!< Pairs of ns prefixes and URIs */
dk_set_t spare_namespace_prefixes_outer; /*!< Bookmark in spare_namespace_prefixes that points to the first inherited (not local) namespace */
caddr_t spare_base_uri; /*!< Default base URI for fn:doc and fn:resolve-uri */
caddr_t spare_storage_name; /*!< Name of quad_storage_t JSO object to control the use of quad mapping at input side and maybe at SPARUL output side */
caddr_t spare_inference_name; /*!< Name of inference rule set to control the expansion of types */
struct rdf_inf_ctx_s * spare_inference_ctx; /*!< Pointer to an inference structure, to expand transitive and add unions for inverses */
caddr_t spare_use_ifp; /*!< Non-NULL pointer if the resulting SQL should contain OPTION(IFP) */
caddr_t spare_use_same_as; /*!< Non-NULL pointer if the resulting SQL should contain OPTION(SAME_AS) */
dk_set_t spare_protocol_params; /*!< Names of variables that are used as parameters of SPARQL protocol call */
struct sparp_env_s *spare_parent_env; /*!< Pointer to parent env */
#if 0 /* These will be used when libraries of inference rules are introduced. Don't forget to patch sparp_clone_for_variant()! */
id_hash_t * spare_fundefs; /*!< In-scope function definitions */
id_hash_t * spare_vars; /*!< Known variables as keys, equivs as values */
id_hash_t * spare_global_bindings; /*!< Dictionary of global bindings, varnames as keys, default value expns as values. DV_DB_NULL box for no expn! */
#endif
sparp_sources_t spare_src; /*!< Query sources, temporarily reset to all zeroes when entering SERVICE with nonempty set of sources */
dk_set_t spare_common_sql_table_options; /*!< SQL 'TABLE OPTION' strings that are added to every table */
dk_set_t spare_groupings; /*!< Variables that should be placed in GROUP BY list */
dk_set_t spare_sql_select_options; /*!< SQL 'OPTION' strings that are added at the end of query (right after permanent QUIETCAST) */
caddr_t spare_describe_mode; /*!< Version of DESCRIBE SQL 'OPTION' strings that are added at the end of query (right after permanent QUIETCAST) */
dk_set_t spare_context_sinvs; /*!< Stack of not yet closed service invocations */
dk_set_t spare_context_qms; /*!< IRIs of allowed quad maps (IRI if quad map is restricted, DEFAULT_L if default qm only, _STAR if not restricted) */
dk_set_t spare_context_graphs; /*!< Expressions that are default values for graph field */
dk_set_t spare_context_subjects; /*!< Expressions that are default values for subject field */
dk_set_t spare_context_predicates; /*!< Expressions that are default values for predicate field */
dk_set_t spare_context_objects; /*!< Expressions that are default values for objects field */
dk_set_t spare_context_gp_subtypes; /*!< Subtypes of not-yet-completed graph patterns */
dk_set_t spare_acc_triples; /*!< Sets of accumulated triples of GPs */
dk_set_t spare_acc_movable_filters; /*!< Sets of accumulated position-independent filters of GPs. Position-independent means it can be moved around BIND() clause */
dk_set_t spare_acc_local_filters; /*!< Sets of accumulated position-dependent filters of GPs. Filters of this sort are implicit restrictions on specific triples, like check of value of _::default_xxx bnode for graph. They fall into subquery when BIND divides a BGP on subquery "before" BIND and triples "after" BIND. */
dk_set_t spare_acc_bgp_varnames; /*!< Sets of used BGP names of GPs, sets of children are merged into sets of parent on each pop from the stack */
int spare_ctor_dflt_g_tmpl_count; /*!< For CONSTRUCT and the like --- count of triple templates in the default graph, should be reset to zero after ctor to deal with DELETE{...} INSERT{...} */
int spare_ctor_g_grp_count; /*!< For CONSTRUCT and the like --- count of graph {...} groups of triple templates, should be reset to zero after ctor to deal with DELETE{...} INSERT{...} */
int spare_inline_data_colcount; /*!< Number of variables in VALUES (...) {...} clause, not set for single-variable syntax because it's used only to check the width of data rows */
SPART ** spare_bindings_vars; /*!< List of variables enumerated in local BINDINGS Var+ list */
SPART *** spare_bindings_rowset; /*!< Array of arrays of values in BINDINGS {...} */
dk_set_t spare_good_graph_varnames; /*!< Varnames found in non-optional triples before or outside, (including non-optional inside previous non-optional siblings), but not after or inside */
dk_set_t spare_good_graph_varname_sets; /*!< Pointers to the spare_known_gspo_varnames stack, to pop */
dk_set_t spare_good_graph_bmk; /*!< Varnames found in non-optional triples before or outside, (including non-optional inside previous non-optional siblings), but not after or inside */
dk_set_t spare_global_var_names; /*!< List of all distinct global names used in the query, to know what should be passed to 'rdf grab' procedure view */
int spare_disable_output_formatting; /*!< Indicates that sg_output_xxx_format_name are all ignored, because the query is intermediate in iterative get with "seealso" */
dk_set_t spare_propvar_sets; /*!< Stack of sets of propvars that should form triples */
caddr_t spare_sql_refresh_free_text; /*!< Flags if there's any use of bif:contains or the like, so 'sql:refresh-free-text' 'yes' option should be added to any vector of sponge options. This is a _boxed_ integer even if it's zero; that is used to store a reference to a changing integer in a compiled tree. */
SPART * spare_found_default_sparul_target; /*!< If \c spare_need_for_default_sparul_target is non-NULL, this remembers the result of spare_default_sparul_target() at the end of list of USING clauses. It can also be set after INSERT IN graph_precode, DELETE FROM graph_precode or MODIFY graph_precode */
const char * spare_need_for_default_sparul_target; /*!< When non-NULL, a single default graph should be provided by single USING, WITH or fallback; missing all three means the error */
} sparp_env_t;
typedef struct sparp_e4qm_s {
dk_set_t e4qm_acc_sqls; /*!< Backstack of first-level function calls that change quad maps, items are SPART * with SPAR_QM_SQL_FUNCALL type */
caddr_t e4qm_default_table; /*!< The name of default table (when a single table name is used without an alias for everything. */
caddr_t e4qm_current_table_alias; /*!< The last alias definition, used for processing of 'FROM table AS alias TEXT LITERAL ...' */
dk_set_t e4qm_parent_tables_of_aliases; /*!< get_keyword-style list of aliases of relational tables, aliases are keys, tables are values. */
dk_set_t e4qm_parent_aliases_of_aliases; /*!< get_keyword-style list of aliases of other aliases, parent aliases are values. */
dk_set_t e4qm_descendants_of_aliases; /*!< get_keyword-style list of aliases of other aliases, bases are keys, sets of descendants are values. */
dk_set_t e4qm_ft_indexes_of_columns; /*!< get_keyword-style list of free-text indexes of aliased columns, 'alias.col' are keys, spar_qm_ft_t are values. */
dk_set_t e4qm_where_conditions; /*!< Set of 'where' conditions for tables represented by sparp_qm_table_condition_t structures. */
dk_set_t e4qm_locals; /*!< Parameters in not-yet-closed '{...}' blocks. Names (as keyword ids) and values, with NULLs as bookmarks. */
dk_set_t e4qm_affected_jso_iris; /*!< Backstack of affected JS objects */
dk_set_t e4qm_deleted; /*!< Backstack of deleted JS objects, class IRI pushed first, instance IRI pushed after so it's above) */
} sparp_e4qm_t;
typedef struct sparp_globals_s {
struct sparp_equiv_s **sg_equivs; /*!< All variable equivalences made for the tree, in pointer to a growing buffer */
#ifdef SPARQL_DEBUG
struct sparp_equiv_s **sg_removed_equivs; /*!< Deleted equivalences, in pointer to a growing buffer of size equal to \c sg_equivs */
#endif
ptrlong sg_equiv_count; /*!< A count of used items in the beginning of \c sg_equivs buffer */
ptrlong sg_cloning_serial; /*!< The pointer to the serial used for current \c sparp_gp_full_clone() operation */
struct spar_tree_s ** sg_sinvs; /*!< All descriptions of service invocations, in pointer to a growing buffer */
ptrlong sg_sinv_count; /*!< A count of used items in the beginning of \c sg_sinvs buffer */
dk_set_t sg_invalidated_bnode_labels; /*!< All blank name labels used in basic graph patterns of that are now closed (in the query and all its subqueries) */
dk_set_t sg_bnode_label_sets; /*!< A stack of dk_set_t-s of blank name labels in not-yet-closed basic graph patterns */
int sg_signal_void_variables; /*!< Flag if 'Variable xxx can not be bound...' error (and the like) should be signalled. */
void* sg_input_param_valmode_name; /*!< Name of valmode for global variables, including protocol parameters listed in \c sg_protocol_params */
void* sg_output_valmode_name; /*!< Name of valmode for top-level result-set */
void* sg_output_format_name; /*!< Name of format for serialization of top-level result-set */
void* sg_output_scalar_format_name; /*!< Overrides generic \c sg_output_format_name for scalar result sets, like ASK */
void* sg_output_dict_format_name; /*!< Overrides generic \c sg_output_format_name for "dictionary of triples" result sets, like CONSTRUCT and DESCRIBE */
void* sg_output_route_name; /*!< Name of procedure that makes a decision re. method of writing SPARUL results (quad storage / DAV file / something else) */
void* sg_output_storage_name; /*!< Name of quad_storage_t JSO object to control the use of quad mapping at SPARUL output side */
void* sg_output_maxrows; /*!< boxed maximum expected number of rows to return */
void* sg_output_compose_report; /*!< Boxed non-NULL number that indicates wither a verbose report string should be created (value of 1) or just a number of changes (value of 0) */
void* sg_sparul_log_mode; /*!< log_mode argument of SPARQL_MODIFY_BY_DICT_CONTENTS() and similar procedures; if set then it's a boxed integer or boxed zero */
int sg_comment_sql; /*!< Flags that control storing comments in the resulting SQL text */
int sg_ebv_mode; /*!< Mode for booleans, one of SPARL_EBV_xxx constants */
} sparp_globals_t;
typedef struct spar_lexbmk_s {
s_node_t* sparlb_lexem_bufs_tail;
ptrlong sparlb_offset;
} spar_lexbmk_t;
typedef struct spar_lexem_s {
ptrlong sparl_lex_value;
void* sparl_sem_value;
ptrlong sparl_lineno;
ptrlong sparl_depth;
void* sparl_raw_text;
#ifdef SPARQL_DEBUG
ptrlong sparl_state;
#endif
} spar_lexem_t;
typedef struct scn3_include_frag_s {
dk_session_t *sif_skipped_part;
int sif_saved_lineno;
int sif_saved_plineno;
int sif_saved_lineno_increment;
int sif_saved_lexdepth;
} scn3_include_frag_t;
typedef struct spar_query_env_s
{
scn3_include_frag_t * sparqre_src; /*!< This is not for use in the parser! This is for inliner inside scn3.l only */
int sparqre_direct_client_call; /*!< The result-set produced by the compiled query will go directly to the ODBC/JDBC client */
ptrlong sparqre_start_lineno;
int * sparqre_param_ctr;
const char * sparqre_tail_sql_text;
int sparqre_allow_sql_extensions;
void* sparqre_base_uri;
#if 0
xp_node_t * sparqre_nsctx_xn; /*!< Namespace context as xp_node_t * */
xml_entity_t *sparqre_nsctx_xe; /*!< Namespace context as xml_entity_t * */
#endif
//query_instance_t * sparqre_qi; /*!< NULL if parsing is inside SQL compiler, current qi for runtime */
//client_connection_t * sparqre_cli; /*!< Client connection, can be NULL or what sqlc_client() return */
struct sql_comp_s * sparqre_super_sc; /*!< The context of the compilation, if nested into SQL code */
struct user_s * sparqre_exec_user; /*!< User that will execute the query */
//wcharset_t * sparqre_query_charset;
int sparqre_query_charset_is_set;
dk_set_t sparqre_external_namespaces;
/*dk_set_t * sparqre_checked_functions;*/
/*dk_set_t * sparqre_sql_columns;*/
int sparqre_key_gen;
void* sparqre_compiled_text;
void* sparqre_catched_error;
//rwlock_t * sparqre_metadata_rwlock;
const char * sparqre_dbg_query_text; /*!< A source text as passed to the top-level sparql compilation. For debug purposes and for mem pool callback only. Can be NULL. */
struct sparp_s * sparqre_dbg_sparp; /*!< A top-level instance of sparql compiler. For debug purposes and for mem pool callback only. Can be NULL; when non-NULL then the structure under pointer may be half-full. */
} spar_query_env_t;
typedef struct qm_format_s *ssg_valmode_t;
typedef const char * ccaddr_t;
typedef struct rdf_val_range_s{
ptrlong rvrRestrictions; /*!< Natural restrictions on values stored at the field */
ccaddr_t rvrDatatype; /*!< Datatype of stored values, if fixed */
ccaddr_t rvrLanguage; /*!< Language, if fixed */
ccaddr_t rvrFixedValue; /*!< Value of stored values, if fixed */
ccaddr_t rvrFixedOrigText; /*!< Original text representing fixed value, if value is fixed and the storing it is appriximate (e.g., double), and the text is known */
ccaddr_t * rvrSprintffs; /*!< Sprintf formats that cover possible IRI values */
ptrlong rvrSprintffCount; /*!< Number of used items of rvrSprintffs */
ccaddr_t * rvrIriClasses; /*!< Possible types of the IRI, if the IRI is calculable */
ptrlong rvrIriClassCount; /*!< Number of used items of rvrIRIClasses */
ccaddr_t * rvrRedCuts; /*!< Impossible values, blocked by option (EXCLUSIVE) of earlier quad maps */
ptrlong rvrRedCutCount; /*!< Number of used items of rvrRedCuts */
/* Don't forget to add NULLS to SPART_RVR_LIST_OF_NULLS when adding fields here */
} rdf_val_range_t;
typedef struct triple_case_s{
struct quad_map_s *tc_qm; /*!< Quad map that can generate data that match the triple */
ccaddr_t *tc_red_cuts[SPART_TRIPLE_FIELDS_COUNT]; /*!< Red cuts for values bound by the triple when they are generated by \c tc_qm */
} triple_case_t;
typedef struct quad_map_s * *quad_map_array_t;
typedef struct sparp_equiv_s
{
ptrlong e_own_idx; /*!< Index of this instance (in \c req_top.equivs) */
SPART *e_gp; /*!< Graph pattern where these variable resides */
caddr_t *e_varnames; /*!< Array of distinct names of equivalent variables. Usually one element, if there's no ?x=?y in FILTER */
caddr_t e_front_varname; /*!< it may be ambiguous how to name a result column of an equiv if the equiv is printed as SELECT, this name is treated as preferable */
SPART **e_vars; /*!< Array of all equivalent variables, including different occurrences of same name in different triples */
ptrlong e_var_count; /*!< Number of used items in e_vars. This can be zero if equiv passes top-level var from alias to alias without local uses */
ptrlong e_gspo_uses; /*!< Number of all local uses in members (+1 for each in G, P, S or O in triples). Note that nonzero e_gspo_uses does not imply SPART_VARR_NOT_NULL if some members has triple.subtype == OPTIONAL_L */
ptrlong e_nested_bindings; /*!< Number of all nested uses in members (+1 for each in G, P, S or O in triples, +1 for each sub-gp use, +1 if \c e_gp is of subtype VALUES_L) */
ptrlong e_nested_optionals; /*!< Number of all nested uses in OPTIONAL_L members, VALUES_L memebers with UNDEF for the variable in question and"pure chains" to such OPTIONALs and VALUEs (+1 for each such sub-gp use) */
ptrlong e_const_reads; /*!< Number of constant-read uses in filters and in 'graph' of members */
ptrlong e_optional_reads; /*!< Number of uses in scalar subqueries of filters; both local and member filter are counted */
ptrlong e_subquery_uses; /*!< Number of all local uses in subquery (0 for plain queries, 1 in groups of subtype SELECT_L) */
ptrlong e_replaces_filter; /*!< Bitmask of SPART_RVR_XXX bits, nonzero if a filter has been replaced (and removed) by tightening of this equiv or by merging this and some other equiv, so the equiv is the only bearer of knowledge about the restriction. */
rdf_val_range_t e_rvr; /*!< Restrictions that are common for all variables. They are combined from rvrs of variables and subvalues, however rvrs of variables can be tightened by ancestor equivs, making the dependencies circular. */
ptrlong *e_subvalue_idxs; /*!< Subselects where values of these variables come from, as array of indexes of equivs. The order is not defined, but subvalues from OPTIONALs are after all other. */
ptrlong *e_receiver_idxs; /*!< Aliases of surrounding query where values of variables from this equiv are used, as array of indexes of equivs */
ptrlong e_clone_idx; /*!< Index of the current clone of the equiv */
ptrlong e_cloning_serial; /*!< The serial used when \c e_clone_idx is set, should be equal to \c sparp->sparp_sg->sg_cloning_serial */
ptrlong e_external_src_idx; /*!< Index in \c req_top.equivs of the binding of external variable at ancestor of scalar subquery */
ptrlong *e_uses_as_params; /*!< Equivs where the given equiv is used as an external source, as array of indexes of equivs */
ptrlong e_deprecated; /*!< The equivalence class belongs to a gp that is no longer usable */
ptrlong e_pos1_t_in; /*!< 1-based position of variable in T_IN list */
ptrlong e_pos1_t_out; /*!< 1-based position of variable in T_OUT list */
#ifdef DEBUG
ptrlong e_dbg_merge_dest; /*!< After the merge of equiv into some destination equiv, \c e_dbg_merge_dest keeps destination */
SPART **e_dbg_saved_gp; /*!< \c e_gp that is boxed as ptrlong, to save the pointer after \c e_gp is set to NULL */
sparp_t *e_dbg_allocator; /*!< The sparp where the equiv is created. This is to differentiate equivs with same gp selids from, e.g., three different variants of grabbing query */
#endif
} sparp_equiv_t;
typedef struct id_hash_s id_hash_t;
typedef struct spar_tree_s SPART;
typedef struct encoding_handler_s encoding_handler_t;
typedef struct lang_handler_s lang_handler_t;
typedef struct sparp_s {
/* Generic environment */
spar_query_env_t *sparp_sparqre; /*!< External environment of the query */
void * sparp_err_hdr;
SPART * sparp_entire_query; /*!< The query as a whole, the root of the whole parsed tree. */
encoding_handler_t *sparp_enc;
lang_handler_t *sparp_lang;
int sparp_synthighlight;
dk_set_t *sparp_checked_functions;
int sparp_reject_extensions; /*!< Reject Virtuoso-specific extensions */
int sparp_save_pragmas; /*!< This instructs the lexer to preserve pragmas for future use. This is not in use right now but may be used pretty soon */
int sparp_key_gen; /*!< 0 = do not fill xqr_key, 1 = save source text only, 2 = save source text and custom namespace decls */
#ifdef XPYYDEBUG
int sparp_yydebug;
#endif
ccaddr_t sparp_text;
int sparp_permitted_syntax; /*!< Bitmask of permitted syntax extensions, 0 for default */
int sparp_syntax_exceptions; /*!< Bitmask of syntax exceptions, 0 for default, can be nonzero for remote endpoints or for testing etc. */
int sparp_inner_permitted_syntax; /*!< The value of last define lang:dialect, it will be assigned to sparp_permitted_syntax for the subquery, -1 before set */
int sparp_unictr; /*!< Unique counter for objects */
/* Environment of yacc */
sparp_env_t * sparp_env;
int sparp_lexem_buf_len;
int sparp_total_lexems_parsed;
spar_lexem_t *sparp_curr_lexem;
spar_lexbmk_t sparp_curr_lexem_bmk;
int sparp_in_precode_expn; /*!< If nonzero (usually 1) then the parser reads precode-safe expression so it can not contain non-global variables, if bit 2 is set then even global variables are prohibited (like it is in INSERT DATA statement) */
int sparp_in_ctor_from_where; /*!< If nonzero then the parser reads WHERE clause of CONSTRUCT WHERE or DELETE WHERE statement */
int sparp_allow_aggregates_in_expn; /*!< The parser reads result-set expressions, GROUP BY, ORDER BY, or HAVING. Each bit is responsible for one level of nesting. */
int sparp_scalar_subq_count; /*!< Counter of scalar subqueries. It's primary purpose is to track whether BIND expression contain scalar subqueries and hence is non-repeatable. */
int sparp_query_uses_aggregates; /*!< Nonzero if there is at least one aggregate in the whole source query, (not in the current SELECT!). This is solely for bypassing expanding top retvals for "plain SPARQL" queries, not for other logic of the compiler */
int sparp_query_uses_sinvs; /*!< Nonzero if there is at least one SERVICE invocation in the whole source query, (not in the current SELECT!). This forces (re) composing of \c sinv.param_varnames and \c sinv.rset_varnames lists */
int sparp_disable_big_const; /*!< INSERT DATA requires either an sql_comp_t for ssl or define sql:big-data-const 0. The define sets this value to 1 */
dk_set_t sparp_created_jsos; /*!< Get-keyword style list of created JS objects. Object IRIs are keys, types (as free-text const char *) are values. This is solely for early (and incomplete) detection of probable errors. */
/* Environment of lex */
size_t sparp_text_ofs;
size_t sparp_text_len;
int sparp_lexlineno; /*!< Source line number, starting from 1 */
int sparp_lexdepth; /*!< Lexical depth, it's equal to the current position in \c sparp_lexpars and \c sparp_lexstates */
int sparp_rset_lexdepth_plus_1; /*!< Lexical depth of current result set, increased by 1 (so when it's zero it means not in rset) */
int sparp_lexpars[SPARP_MAX_LEX_DEPTH+2]; /*!< Stack of not-yet-closed parenthesis */
int sparp_lexstates[SPARP_MAX_LEX_DEPTH+2]; /*!< Stack of lexical states */
int sparp_string_literal_lexval; /*!< Lexical value of string literal that is now in process. */
dk_set_t sparp_output_lexem_bufs; /*!< Reversed list of lexem buffers that are 100% filled by lexems */
spar_lexem_t * sparp_curr_lexem_buf; /*!< Lexem buffer that is filled now */
spar_lexem_t * sparp_curr_lexem_buf_fill; /*!< Number of lexems in \c sparp_curr_lexem_buf */
/* Environment of term rewriter of the SPARQL-to-SQL compiler */
dk_set_t sparp_propvars; /*!< Set of propvars with distinct \c sparv_key fields that were ever used in the query */
struct quad_storage_s *sparp_storage; /*!< Default storage that handles arbitrary quads of any sort plus maybe SPMJVs and relational mappings made by user, usually rdf_sys_storage */
int sparp_storage_is_set; /*!< The field sparp_storage is set (or at least tried to set with error and the attempt to set should not be retried) */
dk_set_t sparp_macro_libs; /*!< List of IRIs of used macro libraries. */
int sparp_disable_storage_macro_lib; /*!< If nonzero, the macro library of the quad storage is not used. This is set e.g. when the query to compile is the declaration of the macro lib by itself. */
struct sparp_trav_params_s *sparp_stp; /*!< Parameters of traverse (callbacks in use). It is filled in by sparp_gp_grav() only, not by sparp_gp_grav_int() */
struct sparp_trav_state_s *sparp_stss; /*!< Stack of traverse states. [0] is fake for parent on 'where', [1] is for 'where' etc. */
struct sparp_trav_params_s *sparp_suspended_stps; /*!< Pointer to a chained stack of suspended traversals */
sparp_globals_t *sparp_sg; /*!< Pointer to data common for all sparp_t-s for whole stack of nested sparp-s */
sparp_e4qm_t *sparp_e4qm; /*!< Pointer to data for compilation of quad map metadata manipulation statements */
int sparp_macrolib_ignore_create; /*!< True if define input:macrolib-ignore-create is set */
void * sparp_macrolib_to_create; /*!< IRI of macro lib that should be created, NULL if that's not a CREATE MACRO LIBRARY statement */
int sparp_macro_mode; /*!< Indicator of special mode of parsing DEFMACRO arguments, body, or invocation */
SPART **sparp_macro_defs; /*!< Array of locally defined macro defs, with an unused end */
int sparp_macro_def_count; /*!< Count of used items in \c sparp_macro_defs */
dk_set_t sparp_funnames_in_defmacros; /*!< All names of functions used inside bodies of macro definitions. They should not be used later as names of new macro defs, to avoid confusion. */
SPART * sparp_current_macro; /*!< The body of the macro that is being defined now */
int sparp_macro_call_count; /*!< If nonzero then macroexpansion should be made */
int sparp_first_equiv_idx; /*!< The index of the first equivalence class allocated in this sparp, to avoid integrity checks of incomplete equivs of outer sparps */
int sparp_rewrite_dirty; /*!< An integer that is incremented when any optimization subroutine rewrites the tree. */
ccaddr_t *sparp_sprintff_isect_buf; /*!< Temporary buffer to calculate intersections of value ranges; solely for sparp_rvr_intersect_sprintffs() */
void * sparp_boxed_exec_uid; /*!< Cached value returned by spar_boxed_exec_uid(). Do not use directly, call spar_boxed_exec_uid() instead! */
void * sparp_immortal_exec_uname; /*!< Cached value returned by spar_immortal_exec_uname(). Do not use directly, call spar_immortal_exec_uname() instead! */
void * sparp_gs_app_callback; /*!< NULL or name of application-specific callback function */
void * sparp_gs_app_uid; /*!< NULL or ID (supposedly app user ID) for application-specific callback */
int sparp_internal_error_runs_audit; /*!< Flags whether the sparp_internal_error has called audit so inner sparp_internal_error should not try to re-run audit or signal but should simply report */
int sparp_globals_mode; /*!< Flags if all global parameters are translated into ':N' because they're passed via 'params' argument of exec() inside a procedure view, */
int sparp_global_num_offset; /*!< If \c sparp_globals_mode is set to \c SPARE_GLOBALS_ARE_COLONUMBERED then numbers of 'app-specific' global parameters starts from \c sparp_global_num_offset up, some number of first params are system-specific. */
} sparp_t;
extern caddr_t spar_unescape_strliteral (sparp_t *sparp, const char *sparyytext, int count_of_quotes, int mode);
extern void spar_fill_lexem_bufs (sparp_t *sparp);
typedef struct spar_sqlgen_s
{
/* Query data */
/*spar_query_t *ssg_query;*/ /*!< Query to process */
struct sql_comp_s *ssg_sc; /*!< Environment for sqlc_exp_print and similar functions. */
sparp_t *ssg_sparp; /*!< Pointer to general parser data */
SPART *ssg_tree; /*!< Select tree to process, of type SPAR_REQ_TOP */
sparp_equiv_t **ssg_equivs; /*!< Shorthand for ssg_sparp->sparp_sg->sg_equivs */
ptrlong ssg_equiv_count; /*!< Shorthand for ssg_sparp->sparp_sg->sg_equiv_count */
struct spar_sqlgen_s *ssg_parent_ssg; /*!< Ssg that prints outer subquery */
struct spar_sqlgen_s *ssg_nested_ssg; /*!< Ssg that prints some fragment for the current one, like a text of query to send to a remote service. This is used for GC on abort */
SPART * ssg_wrapping_gp; /*!< A gp of subtype SELECT_L or SERVICE_L that contains the current subquery */
SPART * ssg_wrapping_sinv; /*!< Service invocation description of \c ssg_wrapping_p in case of SERVICE_L gp subtype */
int ssg_comment_sql; /*!< The mode of putting comments into the generated SQL, as set by define sql:comments (default 0 for release, 1 otherwise) */
/* Run-time environment */
SPART **ssg_sources; /*!< Data sources from ssg_tree->_.req_top.sources and/or environment */
/* SQL Codegen temporary values */
dk_session_t *ssg_out; /*!< Output for SQL text */
int ssg_where_l_printed; /*!< Flags what to print before a filter: " WHERE" if 0, " AND" otherwise */
const char * ssg_where_l_text; /*!< Text to print when (0 == ssg_where_l_printed), usually " WHERE" */
int ssg_indent; /*!< Number of whitespaces to indent. Actually, pairs of whitespaces, not singles */
int ssg_line_count; /*!< Number of lines of generated SQL code */
dk_set_t ssg_valid_ret_selids; /*!< stack of selids of GPs that can be safely used to generate SQL code for retvals (i.e. their selids are in current scope) */
dk_set_t ssg_valid_ret_tabids; /*!< stack like ssg_valid_ret_selids, but for tabids */
dk_set_t ssg_outer_valid_ret_selids; /*!< Initial content of \c ssg_valid_ret_selids. This content is passed to sub-ssgs that make non-scalar subqueries, because they do not access selids of neigbours but can access selids outside some surrounding scalar subquery */
dk_set_t ssg_outer_valid_ret_tabids; /*!< Initial content of \c ssg_valid_ret_tabids. */
int ssg_seealso_enabled; /*!< Flags if \c ssg_print_fld_var_restrictions_ex() (or the like) should generate calls of RDF_GRAB_SEEALSO; they should for "init" and "iter" of a pview, but not for "final" */
/* SPARQL-D Codegen temporary values */
SPART * ssg_sd_current_sinv; /*!< Service invocation that will receive the fragment that is printed ATM (for error reporting) */
caddr_t ssg_sd_service_naming; /*!< The text like "SERVICE <iri>" or "SERVICE called via ?var" (for error reporting) */
int ssg_sd_flags; /*!< Bitmask of SSG_SD_xxx flags, see rdf_mapping.jso */
int ssg_sd_no; /*!< Bitmask of SSG_SD_NO_xxx flags, see rdf_mapping.jso */
id_hash_t *ssg_sd_used_namespaces; /*!< Dictionary of namespaces used for prettyprinting of IRIs */
dk_set_t ssg_sd_outer_gps; /*!< Parent GP of the current tree */
int ssg_sd_forgotten_graph; /*!< Flags that a '}' is not printed after the last triple (in hope that the next member of a group is a triple with same graph so '} GRAPH ... {' is not required */
int ssg_sd_forgotten_dot; /*!< Flags that a dot is not printed after the last triple (in hope that the next member of a group is a triple with same subject so ';' or ',' shorthand can be used) */
SPART * ssg_sd_prev_graph; /*!< Graph of the previous triple in a group, to make a decision about avoiding print of '} GRAPH ... {' */
SPART * ssg_sd_prev_subj; /*!< Subject of the previous triple in a group, to make a decision about using ';' or ',' shorthand */
SPART * ssg_sd_prev_pred; /*!< Predicate of the previous triple in a group, to make a decision about using ',' shorthand */
SPART * ssg_sd_req_top; /*!< Current SPAR_RQ_TOP ancestor-or-self, used, e.g., to convert ORDER BY 1 into ORDER_BY ?first_column */
caddr_t ssg_sd_single_from; /*!< The IRI in FROM clause, if there's only one FROM clause, NULL otherwise */
int ssg_sd_graph_gp_nesting; /*!< Count of GRAPH {...} gps that are opened but not yet closed */
dk_set_t ssg_param_pos_set; /*!< revlist of byte offsets of params in text and numbers of params in question, for sinv templates with unsupported named params */
int ssg_inside_t_inouts; /*!< The list of T_IN or T_OUT values is being printed */
dk_set_t ssg_param_t_inouts; /*!< list of variables that are used in T_IN and T_OUT options but passed as parameters to a remote, so the option should use internal name and a separate FILTER should appear later */
/* RDB2RDF Codegen temporary values */
const char * ssg_alias_to_search; /*!< Alias to select for search-and-replace (say, to replace "main alias" with prefixes for old or new columns) */
const char * ssg_alias_to_replace; /*!< Replacing alias for search-and-replace */
} spar_sqlgen_t;
typedef void ssg_codegen_callback_t (struct spar_sqlgen_s *ssg, struct spar_tree_s *spart, ...);
typedef struct quad_storage_s
{
quad_map_array_t qsMjvMaps; /*!< */
quad_map_array_t qsUserMaps; /*!< */
struct quad_map_s * qsDefaultMap; /*!< */
struct sparql_macro_library_s * qsMacroLibrary; /*!< */
ptrlong qsMatchingFlags; /*!< */
ccaddr_t qsAlterInProgress; /*!< */
} quad_storage_t;
typedef struct spar_tree_s
{
ptrlong type;
caddr_t srcline;
union {
struct {
/* #define SPAR_ALIAS (ptrlong)1001 */
SPART *arg;
caddr_t aname;
ssg_valmode_t native; /*!< temporary use in SQL printer */
ptrlong reruns_may_vary; /*!< nonzero for BIND aliases that have scalar subqueries in \c arg so there is no warranty that \c arg will repeatedly return same value */
ptrlong was_expanded; /*!< There was a variable originally, but it's declared before in BIND..AS or other aliasing so it's expanded */
} alias; /*!< only for use in top-level result-set list */
struct {
SPART *left;
SPART *right;
} bin_exp;
struct {
/* #define SPAR_BUILT_IN_CALL (ptrlong)1003 */
ptrlong btype; /*!< Type of particular BIF, as lexem (for lexems other than SPARQL_BIF) or SPAR_BIF_xxx */
ptrlong desc_ofs; /*!< The offset of BIF description in \c sparp_bif_descs array */
SPART **args;
} builtin;
struct {
SPART *arg;
ssg_valmode_t native;
ssg_valmode_t needed;
} conv; /*!< temporary use in SQL printer */
struct {
/* #define SPAR_FUNCALL (ptrlong)1005 */
caddr_t qname;
SPART **argtrees;
ptrlong agg_mode; /*!< Zero for non-aggreagetes */
ptrlong disabled_optimizations; /*!< So far only bit 1 is used, meaning that the run of a function in the sandbox will never be possible */
} funcall;
struct {
/* #define SPAR_GP (ptrlong)1006 */
ptrlong subtype;
SPART **members;
SPART **filters;
SPART *subquery;
caddr_t selid;
ptrlong *equiv_indexes; /*!< Array of indexes of equivs used in triples and filters of this GP, some items at the tail of the array may be spare and temporarily not in use */
ptrlong equiv_count; /*!< Number of items in \c equiv_indexes array that contains valid data. */
ptrlong glued_filters_count; /*!< Last \c glued_filters_count members of \c filters are expressions for ON statement of LEFT OUTER JOIN. They can not be moved to some other GP because they were moved already and next move will break semantics. */
SPART **options;
} gp;
struct {
/* #define SPAR_GRAPH (ptrlong)1018 */
ptrlong subtype; /*!< One of SPART_GRAPH_FROM, SPART_GRAPH_GROUP, SPART_GRAPH_NAMED, SPART_GRAPH_NOT_FROM, SPART_GRAPH_NOT_GROUP, SPART_GRAPH_NOT_NAMED */
caddr_t iri; /*!< Constant IRI of a source */
SPART *expn; /*!< A QNAME with IRI of "plain" source or an expression that returns an IRI (or NULL) and makes some side effects such as sponging */
ptrlong use_expn_in_gs_checks; /*!< Nonzero if \c _.graph.expn acts in such a way that it can change graph-level permissions, so it should be used instead of \c _.graph.iri in run-time security checks */
} graph;
struct { /* Note that all first members of \c lit case should match to \c qname case */
/* #define SPAR_LIT (ptrlong)1009 */
caddr_t val;
caddr_t datatype;
caddr_t language;
caddr_t original_text;
} lit;
struct { /* Note that all first members of \c qname case should match to \c lit case */
/* #define SPAR_QNAME (ptrlong)1011 */
caddr_t val;
} qname;
struct {
/* #define SPAR_REQ_TOP (ptrlong)1007 */
ptrlong subtype;
caddr_t retvalmode_name;
caddr_t formatmode_name;
caddr_t storage_name;
SPART **retvals;
#if 0
SPART **orig_retvals; /*!< Retvals as they were after expanding '*' and wrapping in MAX() */
#endif
SPART **expanded_orig_retvals; /*!< Retvals as they were after expanding '*' and wrapping in MAX() and adding vars to grab */
caddr_t retselid;
SPART **sources; /*!< Ordered list of FROM, FROM NAMED, NOT FROM and NOT FROM NAMED clauses */
SPART *pattern; /*!< Top-level group pattern that comes from WHERE {...} clause */
SPART **groupings; /*!< NULL or array of grouping expressions */
SPART *having; /*!< NULL or HAVING expression */
SPART **order; /*!< NULL or array of column numbers or oby expressions */
SPART *limit; /*!< NULL or limit expression (boxed integer or a precode) */
SPART *offset; /*!< NULL or offset expression (boxed integer or a precode) */
SPART *binv; /*!< NULL or SPAR_BINDINGS_INV */
caddr_t shared_spare_box; /*!< An environment that is shared among all clones of the tree, the pointer to it is wrapped into DV_LONG_INT */
} req_top;
struct {
/* #define SPAR_TRIPLE (ptrlong)1014 */
ptrlong subtype;
SPART *tr_fields[SPART_TRIPLE_FIELDS_COUNT];
SPART **sinv_idx_and_qms; /* Right now this is a list of a serial of a service invocation in first item and either _STAR as second item for no restriction or DEFAULT_L for built-in mapping or an UNAME of top quad map in every item of the list after the first one */
caddr_t selid;
caddr_t tabid;
triple_case_t **tc_list;
struct qm_format_s *native_formats[SPART_TRIPLE_FIELDS_COUNT];
SPART **options;
caddr_t ft_type;
ptrlong src_serial; /*!< Assigned once at parser and preserved in all clone operations */
} triple;
struct { /* Note that all first members of \c retval and bnode cases should match to \c var case */
/* #define SPAR_BLANK_NODE_LABEL (ptrlong)1002 */
/* #define SPAR_VARIABLE (ptrlong)1013 */
caddr_t vname;
caddr_t selid;
caddr_t tabid;
ptrlong tr_idx; /*!< Index in quad (0 = graph ... 3 = obj) */
ptrlong equiv_idx;
rdf_val_range_t rvr;
ptrlong restr_of_col; /*!< Bitmask that indicate which bits of rvr.rvrRestrictions are set by used qmv(s) or actual values of BINDINGS/VALUES */
} var;
struct { /* Note that all first members of \c retval and bnode cases should match to \c var case */
/* #define SPAR_BLANK_NODE_LABEL (ptrlong)1002 */
/* #define SPAR_VARIABLE (ptrlong)1013 */
caddr_t vname;
caddr_t selid;
caddr_t tabid;
ptrlong tr_idx; /*!< Index in quad (0 = graph ... 3 = obj) */
ptrlong equiv_idx;
rdf_val_range_t rvr;
ptrlong restr_of_col; /*!< Bitmask that indicate which bits of rvr.rvrRestrictions are set by used qmv(s) or actual values of BINDINGS/VALUES */
ptrlong bracketed; /*!< 0 for plain, 1 for [...], 2 for fake and bnodes made for default graphs */
} bnode;
struct { /* Note that all first members of \c retval and bnode cases should match to \c var case */
/* #define SPAR_RETVAL (ptrlong)1008 */
caddr_t vname;
caddr_t selid;
caddr_t tabid;
ptrlong tr_idx; /*!< Index in quad (0 = graph ... 3 = obj) */
ptrlong equiv_idx;
rdf_val_range_t rvr;
ptrlong restr_of_col; /*!< Bitmask that indicate which bits of rvr.rvrRestrictions are set by used qmv(s) or actual values of BINDINGS/VALUES */
SPART *gp;
SPART *triple;
ptrlong optional_makes_nullable;
} retval;
struct {
ptrlong direction;
SPART *expn;
} oby;
struct {
/* #define SPAR_QM_SQL_FUNCALL (ptrlong)1015 */
caddr_t fname; /*!< Function to call (bif or Virtuoso/PL) */
SPART **fixed; /*!< Array of 'positional' arguments */
SPART **named; /*!< Array of 'named' arguments that are passed as get-keyword style vector as a last arg */
} qm_sql_funcall;
struct {
/* #define SPAR_SQLCOL (ptrlong)1012 */
caddr_t qtable; /*!< Qualified table name */
caddr_t alias; /*!< Table alias */
caddr_t col; /*!< Column name */
} qm_sqlcol;
struct {
/* #define SPAR_CODEGEN (ptrlong)1016 */
ssg_codegen_callback_t **cgen_cbk; /*!< Pointer to the code generation function as a boxed number */
SPART *args[1]; /*!< Data for the callback, maybe more then one SPART *, depending on structure size */
} codegen;
struct {
/* #define SPAR_LIST (ptrlong)1017 */
SPART **items; /*!< Some trees, say, items of T_IN_L list of variables */
} list;
struct {
/* #define SPAR_WHERE_MODIFS (ptrlong)1019 */
SPART *where_gp; /*!< Group pattern of WHERE clause, or NULL */
SPART **groupings; /*!< Array of groupings */
SPART *having; /*!< Expression of HAVING clause, or NULL */
SPART **obys; /*!< Array of ORDER BY criteria */
SPART *lim; /*!< Boxed LIMIT value or an expression tree */
SPART *ofs; /*!< Boxed OFFSET value or an expression tree */
SPART *binv; /*!< NULL or SPAR_BINDINGS_INV */
} wm;
struct {
/* define SPAR_SERVICE_INV (ptrlong)1020 */
ptrlong own_idx; /*!< Serial of the sinv in the parser */
SPART *endpoint; /*!< An IRI of web service endpoint without static parameters */
SPART **iri_params; /*!< A get_keyword style array of parameters to pass in the IRI, like maxrows */
caddr_t syntax; /*!< Boxed bitmask of SSG_SD_xxx flags of allowed query serialization features */
caddr_t syntax_exceptions; /*!< Boxed bitmask of SSG_SD_NO_xxx flags of exceptions from standard syntax that breaks the standard compliance of the service */
caddr_t *param_varnames; /*!< Names of variables that are passed as parameters */
ptrlong in_list_implicit; /*!< Flags if IN variables were specified using '*' or not specified at all */
caddr_t *rset_varnames; /*!< Names of variables that are returned in the result set from the endpoint, in the order in the rset */
SPART **defines; /*!< List of defines to pass, as a get_keyword style list of qnames and values or arrays of values */
SPART **sources; /*!< List of sources, similar to one in req_top. If NULL then sources of parent req_top are used */
caddr_t storage_uri; /*!< Storage to use: JSO UNAME if specified explicitly for a service IRI, uname_virtrdf_ns_uri_DefaultServiceStorage if unknown service */
ptrlong silent; /*!< nonzero if SERVICE SILENT syntax is used */
} sinv;
struct {
/* define SPAR_BINDINGS_INV (ptrlong)1021 */
ptrlong own_idx; /*!< Serial of the bindings invocation in the parser */
SPART **vars; /*!< Names of variables that are passed as parameters */
SPART ***data_rows; /*!< Rows of data. Note that they're not copied from spare_bindings_rowset and not duplicated if enclosing GP is duplicated. */
char *data_rows_mask; /*!< Characters, one per data row, indicating whether the row is in use (char '/') or not in use due to ban by some cell (char '0' + column index or '\x7f', whatever is less, for debugging) or not in use due to LIMIT (char '.') */
ptrlong *counters_of_unbound; /*!< Counters of unbound values in columns (rows not in use are excluded from counting). Cheating: This array is allocated as DV_STRING, not DV_ARRAY_OF_POINTER */
ptrlong rows_in_use; /*!< Count of rows still in use */
ptrlong rows_last_rvr; /*!< Count of rows in use when rvrs were refreshed last time */
} binv;
struct {
/* define SPAR_DEFMACRO (ptrlong)1022 */
ptrlong subtype;
caddr_t mname; /*!< IRI of the macro */
caddr_t sml_iri; /*!< IRI UNAME of SPARQL macro library where the macro comes from (as a result of define input:macro-lib... ) */
caddr_t *paramnames; /*!< Names of parameters */
caddr_t *localnames; /*!< Names of variables listed in LOCAL (...) clause */
SPART **quad_pattern; /*!< The template of triple (or quad) patterns */
SPART *body; /*!< The body of the macro, as group graph pattern or scalar expression */
caddr_t selid; /*!< Outermost selid of the \c defmacro.body */
ptrlong aggregate_count; /*!< Count of aggregate functions used inside the \c defmacro.body */
} defmacro;
struct {
/* #define SPAR_MACROCALL (ptrlong)1023 */
caddr_t mname;
SPART **argtrees;
SPART *context_graph;
caddr_t mid;
} macrocall;
struct {
/* #define SPAR_MACROPU (ptrlong)1024 */
caddr_t pname;
ptrlong pindex;
ptrlong pumode;
} macropu;
struct {
/* #define SPAR_PPATH (ptrlong)1025 */
ptrlong subtype; /*!< Node subtype: '/', '|', 'D' or '*' for non-leafs ('D' is union of path with T_DISTINCT), 0 or '!' for plain or negative leafs.
Leafs are '|' of iris and ^iris.
There may be a single forward and/or single reverse leaf (SPART *)_STAR, it can't be mixed with IRIs of same direction.
When type is 0, (SPART *)_STAR means that any predicate will do, such as after optimization of x|!x
When type is '!', (SPART *)_STAR _also_ means that any predicate will do; negation for _STAR is no leafs of that direction. */
SPART **parts; /*!< Descendants of type SPAR_PPATH for non-leafs, QNames for leafs. For '|' subtype, the (only) 0 part is always first, the (only) '!' part is either first or next after 0 part */
caddr_t minrepeat; /*!< Minimal number of repetitions for '*' non-leaf node: 0 for '?' and '*' operators, 1 for '+', an M integer for {M,N} modifier */
caddr_t maxrepeat; /*!< Maximal number of repetitions for '*' non-leaf node: 1 for '?', an N integer for {M,N} modifier however it is NEGATIVE for infinity */
ptrlong num_of_invs; /*!< Number of inverted predicates in a leaf. All inverted predicates are always after all forward predicates */
} ppath;
} _;
} sparp_tree_t;
|
andywx/agensgraph
|
src/backend/parser/sparql_l.c
|
<filename>src/backend/parser/sparql_l.c
#line 2 "sparql_l.c"
#line 4 "sparql_l.c"
#define YY_INT_ALIGNED short int
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* characters.
*/
yy_size_t yy_buf_size;
/* Number of characters read into yy_ch_buf, not including EOB
* characters.
*/
yy_size_t yy_n_chars;
/* Whether we "own" the buffer - i.e., we know we created it,
* and can realloc() it to grow it, and should free() it to
* delete it.
*/
int yy_is_our_buffer;
/* Whether this is an "interactive" input source; if so, and
* if we're using stdio for input, then we want to use getc()
* instead of fread(), to make sure we stop fetching input after
* each newline.
*/
int yy_is_interactive;
/* Whether we're considered to be at the beginning of a line.
* If so, '^' rules will be active on the next match, otherwise
* not.
*/
int yy_at_bol;
int yy_bs_lineno; /**< The line count. */
int yy_bs_column; /**< The column count. */
/* Whether to try to fill the input buffer when we reach the
* end of it.
*/
int yy_fill_buffer;
int yy_buffer_status;
#define YY_BUFFER_NEW 0
#define YY_BUFFER_NORMAL 1
/* When an EOF's been seen but there's still some text to process
* then we mark the buffer as YY_EOF_PENDING, to indicate that we
* shouldn't try reading from the input source any more. We might
* still have a bunch of tokens to match, though, because of
* possible backing-up.
*
* When we actually see the EOF, we change the status to "new"
* (via sparyyrestart()), so that the user can continue scanning by
* just pointing yyin at a new input file.
*/
#define YY_BUFFER_EOF_PENDING 2
};
#endif /* !YY_STRUCT_YY_BUFFER_STATE */
/* We provide macros for accessing buffer states in case in the
* future we want to put the buffer states in a more general
* "scanner state".
*
* Returns the top of the stack, or NULL.
*/
#define YY_CURRENT_BUFFER ( yyg->yy_buffer_stack \
? yyg->yy_buffer_stack[yyg->yy_buffer_stack_top] \
: NULL)
/* Same as previous macro, but useful when we know that the buffer stack is not
* NULL or when we need an lvalue. For internal use only.
*/
#define YY_CURRENT_BUFFER_LVALUE yyg->yy_buffer_stack[yyg->yy_buffer_stack_top]
void sparyyrestart (FILE *input_file ,yyscan_t yyscanner );
void sparyy_switch_to_buffer (YY_BUFFER_STATE new_buffer ,yyscan_t yyscanner );
YY_BUFFER_STATE sparyy_create_buffer (FILE *file,int size ,yyscan_t yyscanner );
void sparyy_delete_buffer (YY_BUFFER_STATE b ,yyscan_t yyscanner );
void sparyy_flush_buffer (YY_BUFFER_STATE b ,yyscan_t yyscanner );
void sparyypush_buffer_state (YY_BUFFER_STATE new_buffer ,yyscan_t yyscanner );
void sparyypop_buffer_state (yyscan_t yyscanner );
static void sparyyensure_buffer_stack (yyscan_t yyscanner );
static void sparyy_load_buffer_state (yyscan_t yyscanner );
static void sparyy_init_buffer (YY_BUFFER_STATE b,FILE *file ,yyscan_t yyscanner );
#define YY_FLUSH_BUFFER sparyy_flush_buffer(YY_CURRENT_BUFFER ,yyscanner)
YY_BUFFER_STATE sparyy_scan_buffer (char *base,yy_size_t size ,yyscan_t yyscanner );
YY_BUFFER_STATE sparyy_scan_string (yyconst char *yy_str ,yyscan_t yyscanner );
YY_BUFFER_STATE sparyy_scan_bytes (yyconst char *bytes,yy_size_t len ,yyscan_t yyscanner );
void *sparyyalloc (yy_size_t ,yyscan_t yyscanner );
void *sparyyrealloc (void *,yy_size_t ,yyscan_t yyscanner );
void sparyyfree (void * ,yyscan_t yyscanner );
#define yy_new_buffer sparyy_create_buffer
#define yy_set_interactive(is_interactive) \
{ \
if ( ! YY_CURRENT_BUFFER ){ \
sparyyensure_buffer_stack (yyscanner); \
YY_CURRENT_BUFFER_LVALUE = \
sparyy_create_buffer(yyin,YY_BUF_SIZE ,yyscanner); \
} \
YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
}
#define yy_set_bol(at_bol) \
{ \
if ( ! YY_CURRENT_BUFFER ){\
sparyyensure_buffer_stack (yyscanner); \
YY_CURRENT_BUFFER_LVALUE = \
sparyy_create_buffer(yyin,YY_BUF_SIZE ,yyscanner); \
} \
YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
}
#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
/* Begin user sect3 */
#define sparyywrap(yyscanner) 1
#define YY_SKIP_YYWRAP
typedef unsigned char YY_CHAR;
typedef int yy_state_type;
#define yytext_ptr yytext_r
static yy_state_type yy_get_previous_state (yyscan_t yyscanner );
static yy_state_type yy_try_NUL_trans (yy_state_type current_state ,yyscan_t yyscanner);
static int yy_get_next_buffer (yyscan_t yyscanner );
static void yy_fatal_error (yyconst char msg[] ,yyscan_t yyscanner );
/* Done after the current pattern has been matched and before the
* corresponding action - sets up yytext.
*/
#define YY_DO_BEFORE_ACTION \
yyg->yytext_ptr = yy_bp; \
yyg->yytext_ptr -= yyg->yy_more_len; \
yyleng = (size_t) (yy_cp - yyg->yytext_ptr); \
yyg->yy_hold_char = *yy_cp; \
*yy_cp = '\0'; \
yyg->yy_c_buf_p = yy_cp;
#define YY_NUM_RULES 112
#define YY_END_OF_BUFFER 113
/* This struct is not used in this scanner,
but its presence is necessary. */
struct yy_trans_info
{
flex_int32_t yy_verify;
flex_int32_t yy_nxt;
};
static yyconst flex_int16_t yy_accept[454] =
{ 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 113, 112,
111, 102, 100, 100, 3, 60, 101, 111, 111, 59,
25, 26, 22, 17, 8, 15, 9, 21, 43, 33,
20, 14, 10, 12, 19, 111, 39, 29, 111, 30,
6, 39, 2, 24, 27, 4, 28, 111, 65, 63,
63, 61, 67, 66, 64, 64, 62, 68, 53, 51,
51, 57, 55, 54, 52, 52, 58, 56, 107, 102,
100, 101, 69, 107, 108, 102, 100, 101, 108, 109,
102, 100, 101, 109, 109, 109, 109, 109, 110, 102,
100, 82, 101, 81, 78, 77, 83, 83, 83, 93,
91, 86, 87, 90, 112, 84, 85, 106, 106, 106,
106, 99, 95, 95, 94, 112, 102, 100, 16, 0,
0, 46, 101, 100, 100, 35, 0, 37, 1, 0,
46, 23, 18, 44, 44, 43, 0, 0, 32, 0,
0, 13, 31, 11, 38, 0, 0, 39, 33, 0,
0, 0, 7, 0, 39, 0, 5, 0, 65, 0,
63, 0, 0, 66, 0, 64, 0, 0, 53, 0,
0, 51, 51, 51, 0, 0, 0, 54, 0, 0,
52, 52, 52, 0, 0, 0, 0, 71, 0, 0,
74, 0, 0, 0, 0, 83, 83, 93, 89, 103,
106, 0, 105, 104, 99, 95, 98, 97, 96, 96,
46, 46, 48, 100, 35, 0, 0, 36, 36, 47,
44, 0, 45, 0, 0, 32, 0, 0, 32, 0,
0, 0, 0, 0, 40, 0, 0, 0, 0, 0,
40, 0, 34, 0, 0, 0, 0, 0, 0, 49,
0, 0, 0, 50, 0, 0, 0, 0, 0, 0,
0, 80, 79, 92, 89, 88, 88, 98, 97, 96,
96, 96, 0, 36, 0, 36, 36, 0, 36, 0,
36, 0, 32, 0, 0, 0, 0, 38, 0, 40,
0, 41, 40, 0, 0, 0, 0, 41, 40, 0,
0, 34, 0, 0, 34, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 73, 75, 0,
88, 88, 0, 36, 36, 0, 36, 0, 0, 0,
0, 0, 0, 41, 0, 41, 0, 0, 0, 0,
0, 41, 0, 34, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 76, 0,
36, 36, 0, 0, 0, 0, 0, 42, 0, 0,
0, 0, 42, 0, 0, 0, 0, 0, 0, 0,
0, 0, 72, 0, 0, 0, 0, 42, 42, 0,
0, 42, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 70, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0
} ;
static yyconst flex_int32_t yy_ec[256] =
{ 0,
1, 1, 1, 1, 1, 1, 1, 1, 2, 3,
1, 1, 4, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 2, 5, 6, 7, 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, 18, 19, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 35, 35, 37, 38, 39, 40, 35,
35, 41, 42, 43, 44, 35, 35, 45, 46, 35,
47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 60, 60, 62, 63, 64,
65, 60, 60, 66, 67, 68, 69, 70, 60, 71,
72, 60, 73, 74, 75, 76, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 77, 77, 77, 77, 77, 77,
77, 77, 77, 77, 78
} ;
static yyconst flex_int32_t yy_meta[79] =
{ 0,
1, 1, 2, 3, 4, 5, 4, 4, 6, 4,
7, 8, 8, 4, 4, 4, 9, 10, 11, 12,
13, 4, 1, 4, 14, 15, 4, 16, 16, 16,
16, 16, 16, 17, 17, 17, 17, 17, 17, 17,
17, 17, 17, 18, 17, 17, 14, 19, 14, 1,
20, 1, 21, 21, 16, 16, 16, 21, 17, 17,
17, 17, 17, 22, 17, 22, 17, 22, 18, 22,
17, 17, 23, 1, 23, 4, 24, 14
} ;
static yyconst flex_int16_t yy_base[698] =
{ 0,
0, 0, 0, 0, 76, 78, 80, 87, 91, 93,
95, 102, 107, 113, 127, 144, 197, 265, 155, 172,
202, 240, 118, 151, 149, 183, 0, 0, 1339, 3252,
3252, 1336, 1332, 1331, 1283, 136, 109, 97, 1287, 1285,
3252, 3252, 1269, 1267, 3252, 3252, 1245, 3252, 170, 79,
3252, 147, 3252, 1231, 156, 0, 199, 3252, 120, 3252,
1204, 82, 3252, 217, 3252, 1178, 3252, 174, 1202, 1222,
1220, 3252, 124, 1165, 1208, 1207, 3252, 141, 192, 1204,
1183, 245, 163, 101, 1178, 1178, 276, 168, 3252, 1176,
1167, 220, 3252, 189, 3252, 1167, 1163, 259, 214, 3252,
1158, 1153, 267, 219, 233, 239, 237, 241, 3252, 1153,
1149, 1143, 281, 1130, 3252, 3252, 0, 1136, 1134, 0,
3252, 3252, 3252, 1115, 1094, 3252, 3252, 1091, 3252, 177,
1083, 0, 1092, 1090, 1081, 284, 1089, 3252, 3252, 205,
1084, 127, 288, 1085, 292, 0, 329, 3252, 3252, 1071,
1054, 3252, 3252, 280, 282, 287, 301, 0, 329, 267,
1035, 1030, 3252, 3252, 1006, 307, 396, 328, 308, 283,
0, 0, 3252, 314, 988, 331, 3252, 330, 665, 337,
3252, 0, 0, 663, 359, 3252, 0, 0, 262, 393,
363, 3252, 704, 697, 406, 0, 0, 283, 402, 367,
3252, 694, 687, 415, 0, 0, 370, 3252, 379, 380,
3252, 385, 387, 678, 668, 0, 0, 671, 338, 3252,
655, 652, 3252, 3252, 0, 3252, 0, 0, 631, 630,
607, 3252, 3252, 618, 0, 615, 418, 456, 508, 3252,
407, 600, 598, 0, 0, 417, 424, 386, 434, 0,
0, 0, 611, 549, 487, 0, 0, 0, 0, 604,
583, 0, 547, 387, 0, 0, 0, 0, 551, 3252,
0, 0, 546, 3252, 0, 0, 391, 404, 415, 421,
442, 3252, 3252, 3252, 350, 499, 457, 0, 0, 0,
0, 0, 474, 461, 469, 450, 0, 463, 450, 446,
609, 0, 550, 0, 0, 0, 0, 445, 451, 431,
423, 513, 554, 0, 0, 0, 0, 407, 325, 0,
0, 561, 564, 488, 565, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 497, 517, 3252, 3252, 528,
3252, 329, 324, 3252, 0, 236, 0, 445, 0, 0,
0, 0, 233, 208, 586, 559, 0, 0, 0, 0,
212, 162, 0, 575, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 524, 544, 3252, 130,
3252, 0, 0, 0, 0, 0, 86, 611, 0, 0,
0, 560, 0, 0, 0, 0, 0, 0, 0, 0,
0, 559, 3252, 0, 0, 0, 79, 3252, 639, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
548, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 3252, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 3252, 716, 740, 764, 788, 812, 836, 860,
884, 908, 932, 956, 980, 1004, 1028, 1041, 1063, 1082,
1103, 1112, 1126, 1141, 1155, 1179, 1199, 1221, 1241, 1263,
1283, 1305, 1325, 1347, 1371, 1395, 1419, 1443, 1467, 1480,
1504, 584, 1523, 1544, 1561, 1577, 1595, 1611, 1630, 603,
646, 1650, 1663, 1680, 1704, 1724, 649, 652, 1746, 1766,
659, 660, 1788, 1808, 662, 670, 1830, 1850, 673, 680,
1872, 1896, 1920, 1944, 1968, 1992, 2016, 2040, 2064, 2077,
2101, 2121, 681, 683, 2138, 2159, 691, 693, 2168, 2190,
2210, 2226, 694, 1110, 1193, 1195, 2246, 2259, 1203, 2276,
2297, 1235, 1237, 1245, 1277, 2317, 1279, 1287, 2341, 1319,
1321, 2365, 2389, 2413, 2437, 2461, 2485, 2509, 2522, 2540,
2553, 1545, 2570, 1568, 1575, 1576, 1641, 2586, 2608, 2632,
2648, 2664, 1653, 1666, 1718, 1720, 2679, 2692, 1728, 1760,
2709, 2730, 1762, 1770, 1802, 1804, 1812, 1844, 1846, 2115,
2160, 2166, 2750, 2763, 2785, 2798, 2816, 2237, 2240, 2262,
2298, 2838, 2858, 2874, 2525, 2538, 2556, 2584, 2894, 2907,
2585, 2924, 2682, 2695, 2731, 2766, 2801, 2814, 2885, 2888,
2910, 2935, 2937, 2938, 2959, 2972, 2975, 2983, 2985, 2986,
3007, 3023, 3034, 3036, 3037, 3050, 3063, 3061, 3074, 3075,
3076, 3077, 3087, 3088, 3089, 3090, 3100, 3101, 3102, 3103,
3113, 3114, 3115, 3116, 3126, 3127, 3128, 3129, 3139, 3140,
3141, 3142, 3152, 3153, 3154, 3155, 3165, 3166, 3167, 3168,
3178, 3179, 3180, 3181, 3191, 3192, 3193, 3194, 3204, 3205,
3206, 3207, 3217, 3218, 3219, 3220, 3230
} ;
static yyconst flex_int16_t yy_def[698] =
{ 0,
454, 454, 453, 3, 455, 455, 456, 456, 457, 457,
458, 458, 459, 459, 460, 460, 461, 461, 462, 462,
463, 463, 464, 464, 465, 465, 454, 454, 453, 453,
453, 453, 453, 453, 453, 466, 467, 468, 453, 469,
453, 453, 453, 453, 453, 453, 453, 453, 453, 470,
453, 471, 453, 453, 468, 472, 473, 453, 453, 453,
453, 474, 453, 473, 453, 453, 453, 475, 476, 453,
453, 453, 477, 478, 453, 453, 453, 479, 480, 453,
453, 480, 481, 482, 453, 453, 482, 483, 453, 453,
453, 467, 453, 453, 453, 453, 453, 467, 453, 453,
453, 453, 467, 453, 453, 453, 453, 453, 453, 453,
453, 453, 467, 453, 453, 453, 484, 484, 484, 485,
453, 453, 453, 453, 453, 453, 453, 486, 453, 486,
453, 487, 453, 453, 453, 488, 453, 453, 453, 466,
489, 453, 467, 453, 467, 490, 453, 453, 453, 491,
453, 453, 453, 453, 453, 453, 453, 492, 493, 494,
495, 495, 453, 453, 496, 475, 497, 498, 499, 453,
500, 501, 453, 502, 503, 504, 453, 475, 505, 506,
453, 507, 508, 509, 510, 453, 511, 512, 513, 513,
514, 453, 453, 453, 513, 515, 516, 517, 517, 518,
453, 453, 453, 517, 519, 520, 453, 453, 453, 453,
453, 453, 453, 453, 453, 521, 521, 522, 523, 453,
524, 524, 453, 453, 525, 453, 526, 527, 528, 529,
453, 453, 453, 453, 530, 531, 532, 453, 238, 453,
453, 453, 453, 533, 534, 535, 535, 536, 535, 537,
538, 539, 540, 541, 542, 543, 544, 545, 546, 547,
548, 549, 550, 551, 552, 553, 554, 555, 556, 453,
557, 558, 559, 453, 560, 561, 453, 453, 453, 453,
453, 453, 453, 453, 562, 453, 562, 563, 564, 565,
565, 566, 567, 453, 568, 453, 569, 570, 571, 453,
571, 572, 573, 574, 575, 576, 577, 578, 579, 453,
580, 581, 582, 583, 584, 585, 586, 587, 588, 589,
590, 591, 591, 592, 591, 593, 594, 595, 596, 597,
598, 599, 600, 601, 602, 453, 453, 453, 453, 453,
453, 453, 603, 453, 604, 605, 606, 607, 608, 609,
610, 611, 612, 453, 613, 614, 615, 616, 617, 618,
619, 620, 621, 622, 623, 624, 625, 626, 627, 628,
629, 630, 631, 632, 633, 634, 453, 453, 453, 635,
453, 636, 637, 638, 639, 640, 641, 642, 643, 644,
645, 646, 647, 648, 649, 650, 651, 652, 653, 654,
655, 453, 453, 656, 657, 658, 641, 453, 642, 659,
660, 647, 661, 662, 663, 664, 665, 666, 667, 668,
453, 669, 670, 671, 672, 673, 674, 675, 676, 677,
678, 679, 453, 680, 681, 682, 683, 684, 685, 686,
687, 688, 689, 690, 691, 692, 693, 694, 695, 696,
697, 674, 0, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453
} ;
static yyconst flex_int16_t yy_nxt[3331] =
{ 0,
31, 32, 33, 34, 35, 36, 37, 38, 31, 39,
40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
50, 51, 52, 53, 54, 55, 56, 57, 57, 57,
57, 57, 57, 57, 57, 57, 57, 57, 57, 57,
57, 57, 57, 57, 57, 57, 58, 59, 60, 61,
62, 63, 64, 57, 57, 57, 57, 57, 57, 57,
57, 57, 57, 57, 57, 57, 57, 57, 57, 57,
57, 57, 65, 66, 67, 31, 68, 31, 70, 71,
70, 71, 75, 76, 408, 77, 72, 158, 72, 75,
76, 408, 77, 80, 81, 80, 81, 85, 86, 174,
87, 82, 176, 82, 85, 86, 199, 87, 90, 33,
91, 144, 145, 92, 90, 33, 91, 147, 93, 92,
30, 129, 148, 73, 93, 73, 160, 78, 96, 33,
97, 130, 233, 98, 78, 381, 131, 94, 83, 141,
83, 142, 88, 94, 174, 96, 33, 97, 200, 88,
98, 133, 134, 30, 129, 99, 110, 33, 111, 135,
112, 113, 94, 171, 130, 114, 115, 182, 94, 131,
162, 163, 99, 110, 33, 111, 147, 112, 113, 361,
99, 148, 114, 115, 187, 133, 134, 155, 172, 156,
453, 178, 183, 135, 169, 223, 136, 99, 101, 33,
102, 157, 190, 103, 118, 119, 196, 120, 141, 188,
231, 205, 121, 122, 123, 166, 167, 387, 124, 169,
125, 170, 144, 145, 207, 361, 157, 116, 104, 105,
136, 197, 106, 166, 167, 107, 206, 169, 354, 191,
108, 381, 118, 119, 116, 120, 170, 193, 194, 207,
121, 122, 123, 104, 105, 195, 124, 106, 125, 208,
107, 144, 145, 209, 170, 108, 101, 33, 102, 144,
145, 103, 190, 210, 126, 166, 127, 211, 202, 203,
212, 204, 213, 144, 145, 208, 229, 230, 199, 209,
144, 145, 191, 166, 234, 145, 104, 105, 210, 154,
106, 241, 211, 107, 155, 212, 156, 213, 108, 191,
250, 157, 126, 157, 127, 242, 158, 242, 157, 253,
243, 104, 105, 200, 178, 106, 256, 169, 107, 344,
200, 260, 341, 108, 236, 251, 157, 245, 157, 262,
286, 287, 260, 157, 166, 167, 247, 178, 169, 237,
453, 257, 286, 287, 170, 160, 238, 238, 238, 238,
238, 238, 238, 238, 238, 238, 238, 238, 238, 238,
238, 238, 238, 238, 238, 170, 248, 170, 264, 239,
182, 239, 239, 239, 239, 239, 239, 239, 239, 239,
239, 239, 239, 239, 239, 239, 239, 239, 239, 239,
239, 253, 187, 269, 166, 183, 196, 273, 193, 194,
205, 277, 166, 254, 278, 166, 270, 202, 203, 279,
274, 280, 281, 295, 361, 245, 241, 188, 354, 304,
326, 197, 245, 336, 247, 206, 277, 296, 157, 278,
191, 247, 245, 170, 279, 337, 280, 281, 260, 200,
236, 247, 338, 191, 305, 327, 310, 339, 336, 342,
287, 252, 200, 157, 248, 237, 348, 298, 346, 296,
337, 248, 166, 298, 344, 299, 300, 338, 298, 294,
340, 248, 339, 301, 301, 301, 301, 301, 301, 301,
301, 301, 301, 301, 301, 301, 301, 301, 301, 301,
301, 301, 341, 166, 254, 340, 299, 169, 299, 299,
299, 299, 299, 299, 299, 299, 299, 299, 299, 299,
299, 299, 299, 299, 299, 299, 299, 299, 453, 166,
355, 365, 377, 169, 170, 299, 299, 299, 299, 299,
299, 299, 299, 299, 299, 299, 299, 299, 299, 299,
299, 299, 299, 299, 311, 321, 366, 377, 245, 378,
170, 379, 402, 166, 323, 166, 178, 247, 166, 321,
166, 254, 321, 321, 169, 166, 355, 178, 323, 169,
169, 323, 323, 321, 378, 403, 379, 402, 421, 166,
433, 387, 323, 200, 324, 244, 170, 248, 191, 244,
260, 170, 166, 178, 244, 166, 170, 170, 324, 311,
403, 324, 324, 421, 258, 433, 310, 243, 258, 243,
294, 138, 324, 258, 174, 166, 298, 166, 178, 300,
166, 169, 291, 170, 291, 166, 301, 301, 301, 301,
301, 301, 301, 301, 301, 301, 301, 301, 301, 301,
301, 301, 301, 301, 301, 166, 178, 259, 170, 169,
265, 259, 166, 266, 265, 453, 259, 266, 222, 265,
267, 268, 266, 271, 267, 268, 284, 271, 283, 267,
268, 272, 271, 282, 275, 272, 170, 166, 275, 201,
272, 276, 249, 275, 302, 276, 249, 201, 302, 192,
276, 249, 306, 302, 307, 314, 306, 192, 307, 314,
185, 306, 180, 307, 314, 166, 30, 30, 30, 30,
30, 30, 30, 30, 30, 30, 30, 30, 30, 30,
30, 30, 30, 30, 30, 30, 30, 30, 30, 30,
69, 69, 69, 69, 69, 69, 69, 69, 69, 69,
69, 69, 69, 69, 69, 69, 69, 69, 69, 69,
69, 69, 69, 69, 74, 74, 74, 74, 74, 74,
74, 74, 74, 74, 74, 74, 74, 74, 74, 74,
74, 74, 74, 74, 74, 74, 74, 74, 79, 79,
79, 79, 79, 79, 79, 79, 79, 79, 79, 79,
79, 79, 79, 79, 79, 79, 79, 79, 79, 79,
79, 79, 84, 84, 84, 84, 84, 84, 84, 84,
84, 84, 84, 84, 84, 84, 84, 84, 84, 84,
84, 84, 84, 84, 84, 84, 89, 89, 89, 89,
89, 89, 89, 89, 89, 89, 89, 89, 89, 89,
89, 89, 89, 89, 89, 89, 89, 89, 89, 89,
95, 95, 95, 95, 95, 95, 95, 95, 95, 95,
95, 95, 95, 95, 95, 95, 95, 95, 95, 95,
95, 95, 95, 95, 100, 100, 100, 100, 100, 100,
100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
100, 100, 100, 100, 100, 100, 100, 100, 109, 109,
109, 109, 109, 109, 109, 109, 109, 109, 109, 109,
109, 109, 109, 109, 109, 109, 109, 109, 109, 109,
109, 109, 117, 117, 117, 117, 117, 117, 117, 117,
117, 117, 117, 117, 117, 117, 117, 117, 117, 117,
117, 117, 117, 117, 117, 117, 128, 128, 128, 128,
128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
132, 132, 132, 132, 132, 132, 132, 132, 132, 132,
132, 132, 132, 132, 132, 132, 132, 132, 132, 132,
132, 132, 132, 132, 140, 174, 140, 140, 140, 140,
140, 140, 140, 140, 140, 140, 140, 140, 140, 140,
140, 140, 252, 140, 140, 140, 140, 140, 143, 143,
143, 143, 143, 143, 143, 143, 143, 143, 143, 143,
143, 143, 143, 143, 143, 143, 143, 143, 143, 143,
143, 143, 146, 146, 163, 146, 146, 146, 146, 163,
146, 146, 146, 150, 240, 150, 150, 150, 150, 150,
150, 150, 150, 150, 150, 150, 150, 150, 150, 150,
150, 232, 150, 150, 150, 150, 150, 159, 138, 232,
137, 227, 226, 159, 159, 226, 224, 159, 159, 159,
159, 159, 159, 159, 222, 159, 161, 220, 161, 161,
161, 161, 161, 161, 161, 161, 161, 161, 161, 161,
161, 315, 161, 161, 161, 315, 161, 165, 165, 165,
315, 219, 165, 165, 168, 168, 217, 168, 168, 217,
215, 168, 168, 168, 168, 168, 168, 168, 214, 168,
175, 138, 175, 175, 137, 138, 175, 175, 175, 137,
175, 175, 175, 166, 166, 138, 166, 166, 137, 138,
166, 166, 166, 166, 166, 166, 166, 137, 166, 179,
201, 201, 179, 179, 179, 192, 179, 179, 179, 179,
179, 179, 179, 179, 179, 179, 179, 179, 179, 179,
179, 179, 179, 179, 316, 179, 317, 192, 316, 186,
317, 186, 185, 316, 320, 317, 179, 179, 320, 179,
179, 184, 181, 320, 184, 181, 184, 184, 184, 184,
184, 184, 184, 184, 184, 184, 184, 184, 184, 184,
184, 184, 184, 184, 184, 184, 328, 184, 329, 180,
328, 177, 329, 173, 164, 328, 330, 329, 184, 184,
330, 184, 184, 189, 154, 330, 189, 189, 189, 189,
189, 189, 189, 189, 189, 189, 189, 189, 189, 189,
189, 189, 189, 189, 189, 189, 189, 189, 331, 189,
332, 153, 331, 152, 332, 151, 149, 331, 333, 332,
189, 189, 333, 189, 189, 198, 139, 333, 198, 198,
198, 198, 198, 198, 198, 198, 198, 198, 198, 198,
198, 198, 198, 198, 198, 198, 198, 198, 198, 198,
334, 198, 335, 138, 334, 138, 335, 137, 453, 334,
453, 335, 198, 198, 453, 198, 198, 216, 216, 216,
216, 453, 216, 453, 453, 453, 216, 453, 216, 216,
216, 216, 216, 216, 216, 216, 216, 216, 216, 453,
216, 218, 453, 453, 218, 453, 218, 218, 218, 218,
218, 218, 218, 218, 218, 218, 218, 218, 218, 218,
218, 218, 218, 218, 218, 221, 453, 453, 221, 221,
221, 221, 221, 221, 221, 453, 221, 221, 221, 221,
221, 221, 221, 221, 221, 221, 221, 221, 221, 225,
453, 453, 225, 225, 225, 453, 225, 225, 225, 225,
225, 225, 225, 225, 225, 225, 225, 453, 225, 225,
225, 225, 225, 228, 228, 228, 228, 228, 228, 228,
228, 228, 228, 228, 228, 228, 228, 228, 228, 228,
228, 228, 228, 228, 228, 228, 228, 141, 453, 141,
141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
141, 141, 141, 141, 141, 453, 141, 141, 141, 141,
141, 235, 453, 453, 453, 235, 235, 235, 453, 235,
235, 235, 453, 235, 150, 453, 150, 150, 150, 150,
150, 150, 150, 150, 150, 150, 150, 150, 150, 150,
150, 150, 453, 150, 150, 150, 150, 150, 246, 453,
453, 246, 246, 453, 246, 246, 453, 453, 246, 246,
246, 246, 246, 246, 246, 453, 246, 249, 453, 249,
249, 249, 249, 249, 249, 453, 303, 453, 249, 453,
303, 249, 453, 249, 161, 303, 161, 161, 161, 161,
161, 161, 161, 161, 161, 161, 161, 161, 161, 349,
161, 161, 161, 349, 161, 165, 350, 351, 349, 453,
350, 351, 165, 165, 165, 350, 351, 165, 165, 255,
453, 453, 453, 255, 255, 453, 255, 453, 453, 453,
255, 255, 255, 255, 255, 255, 255, 453, 255, 168,
168, 453, 168, 168, 453, 453, 168, 168, 168, 168,
168, 168, 168, 453, 168, 159, 453, 453, 453, 453,
453, 159, 159, 453, 453, 159, 159, 159, 159, 159,
159, 159, 352, 159, 261, 453, 352, 453, 453, 261,
453, 352, 453, 453, 357, 261, 261, 261, 357, 261,
261, 261, 175, 357, 175, 453, 453, 358, 175, 175,
175, 358, 175, 175, 175, 263, 358, 453, 453, 453,
453, 263, 263, 453, 453, 263, 263, 263, 263, 263,
263, 263, 453, 263, 179, 453, 453, 179, 179, 179,
453, 179, 179, 179, 179, 179, 179, 179, 179, 179,
179, 179, 179, 179, 179, 179, 179, 179, 179, 359,
179, 360, 453, 359, 453, 360, 453, 453, 359, 325,
360, 179, 179, 325, 179, 179, 184, 453, 325, 184,
453, 184, 184, 184, 184, 184, 184, 184, 184, 184,
184, 184, 184, 184, 184, 184, 184, 184, 184, 184,
184, 363, 184, 367, 453, 363, 453, 367, 453, 453,
363, 368, 367, 184, 184, 368, 184, 184, 189, 453,
368, 189, 189, 189, 189, 189, 189, 189, 189, 189,
189, 189, 189, 189, 189, 189, 189, 189, 189, 189,
189, 189, 189, 369, 189, 370, 453, 369, 453, 370,
453, 453, 369, 371, 370, 189, 189, 371, 189, 189,
198, 453, 371, 198, 198, 198, 198, 198, 198, 198,
198, 198, 198, 198, 198, 198, 198, 198, 198, 198,
198, 198, 198, 198, 198, 372, 198, 373, 453, 372,
453, 373, 453, 453, 372, 453, 373, 198, 198, 453,
198, 198, 216, 216, 216, 216, 453, 216, 453, 453,
453, 216, 453, 216, 216, 216, 216, 216, 216, 216,
216, 216, 216, 216, 453, 216, 218, 453, 453, 218,
218, 218, 218, 218, 218, 218, 218, 218, 218, 218,
218, 218, 218, 218, 218, 218, 218, 218, 218, 218,
285, 285, 285, 285, 285, 285, 285, 285, 285, 285,
285, 285, 285, 285, 285, 285, 285, 285, 285, 285,
285, 285, 285, 285, 221, 453, 453, 221, 221, 221,
221, 221, 221, 221, 453, 221, 221, 221, 221, 221,
221, 221, 221, 221, 221, 221, 221, 221, 225, 453,
453, 225, 225, 225, 453, 225, 225, 225, 225, 225,
225, 225, 225, 225, 225, 225, 453, 225, 225, 225,
225, 225, 288, 453, 453, 288, 288, 288, 453, 288,
288, 288, 288, 288, 288, 288, 288, 288, 288, 288,
453, 288, 288, 288, 288, 288, 289, 453, 453, 289,
289, 289, 453, 289, 289, 289, 289, 289, 289, 289,
289, 289, 289, 289, 453, 289, 289, 289, 289, 289,
290, 453, 290, 290, 290, 290, 453, 290, 290, 290,
290, 290, 290, 290, 290, 290, 290, 290, 453, 290,
290, 290, 290, 290, 292, 292, 453, 292, 292, 292,
453, 292, 292, 292, 292, 292, 292, 292, 292, 292,
292, 292, 453, 292, 292, 292, 292, 292, 235, 453,
453, 453, 235, 235, 235, 453, 235, 235, 235, 453,
235, 293, 453, 453, 293, 293, 293, 293, 293, 293,
293, 293, 293, 293, 293, 293, 293, 293, 293, 453,
293, 293, 293, 293, 293, 297, 374, 453, 453, 453,
374, 453, 297, 453, 453, 374, 297, 297, 297, 453,
297, 297, 297, 246, 453, 453, 246, 246, 453, 246,
246, 453, 453, 246, 246, 246, 246, 246, 246, 246,
453, 246, 303, 453, 303, 303, 303, 303, 303, 303,
453, 375, 453, 303, 453, 375, 303, 376, 303, 308,
375, 376, 453, 308, 308, 308, 376, 453, 308, 308,
309, 453, 453, 309, 309, 309, 309, 309, 309, 309,
309, 309, 309, 309, 309, 309, 309, 309, 453, 309,
309, 309, 309, 309, 312, 453, 453, 453, 312, 312,
453, 312, 453, 453, 453, 312, 312, 312, 312, 312,
312, 312, 453, 312, 313, 313, 453, 313, 313, 453,
453, 313, 313, 313, 313, 313, 313, 313, 383, 313,
318, 384, 383, 453, 453, 384, 453, 383, 453, 453,
384, 318, 318, 318, 453, 318, 318, 318, 319, 453,
319, 453, 453, 385, 319, 319, 319, 385, 319, 319,
319, 322, 385, 453, 322, 322, 453, 322, 322, 453,
453, 322, 322, 322, 322, 322, 322, 322, 453, 322,
325, 453, 325, 325, 325, 325, 325, 325, 453, 386,
453, 325, 453, 386, 325, 453, 325, 189, 386, 453,
189, 189, 189, 453, 189, 189, 189, 189, 189, 189,
189, 189, 189, 189, 189, 189, 189, 189, 189, 189,
189, 198, 453, 453, 198, 453, 198, 198, 198, 198,
198, 198, 198, 198, 198, 198, 198, 198, 198, 198,
198, 198, 198, 198, 198, 285, 285, 285, 285, 285,
285, 285, 285, 285, 285, 285, 285, 285, 285, 285,
285, 285, 285, 285, 285, 285, 285, 285, 285, 288,
453, 453, 288, 288, 288, 453, 288, 288, 288, 288,
288, 288, 288, 288, 288, 288, 288, 453, 288, 288,
288, 288, 288, 289, 453, 453, 289, 289, 289, 453,
289, 289, 289, 289, 289, 289, 289, 289, 289, 289,
289, 453, 289, 289, 289, 289, 289, 290, 453, 453,
290, 290, 290, 453, 290, 290, 290, 290, 290, 290,
290, 290, 290, 290, 290, 453, 290, 290, 290, 290,
290, 292, 453, 453, 292, 292, 292, 453, 292, 292,
292, 292, 292, 292, 292, 292, 292, 292, 292, 453,
292, 292, 292, 292, 292, 293, 453, 453, 293, 293,
293, 293, 293, 293, 293, 293, 293, 293, 293, 293,
293, 293, 293, 453, 293, 293, 293, 293, 293, 343,
453, 453, 343, 343, 343, 343, 343, 343, 343, 343,
343, 343, 343, 343, 343, 343, 343, 453, 343, 343,
343, 343, 343, 345, 453, 453, 389, 345, 345, 345,
389, 345, 345, 345, 347, 389, 453, 453, 453, 390,
453, 453, 453, 390, 453, 347, 347, 347, 390, 347,
347, 347, 299, 453, 299, 453, 453, 391, 299, 299,
299, 391, 299, 299, 299, 246, 391, 453, 246, 246,
453, 246, 246, 453, 453, 246, 246, 246, 246, 246,
246, 246, 453, 246, 308, 392, 364, 308, 453, 392,
364, 308, 308, 308, 392, 364, 308, 308, 309, 453,
453, 309, 309, 309, 309, 309, 309, 309, 309, 309,
309, 309, 309, 309, 309, 309, 453, 309, 309, 309,
309, 309, 353, 453, 453, 353, 353, 353, 353, 353,
353, 353, 353, 353, 353, 353, 353, 353, 353, 353,
453, 353, 353, 353, 353, 353, 356, 356, 453, 356,
356, 453, 453, 356, 356, 356, 356, 356, 356, 356,
453, 356, 313, 313, 453, 313, 313, 453, 453, 313,
313, 313, 313, 313, 313, 313, 453, 313, 362, 453,
362, 453, 453, 394, 362, 362, 362, 394, 362, 362,
362, 319, 394, 319, 453, 453, 395, 319, 319, 319,
395, 319, 319, 319, 322, 395, 453, 322, 322, 453,
322, 322, 453, 453, 322, 322, 322, 322, 322, 322,
322, 453, 322, 364, 453, 364, 364, 364, 364, 364,
364, 453, 396, 453, 364, 453, 396, 364, 453, 364,
343, 396, 453, 343, 343, 343, 343, 343, 343, 343,
343, 343, 343, 343, 343, 343, 343, 343, 453, 343,
343, 343, 343, 343, 345, 453, 453, 397, 345, 345,
345, 397, 345, 345, 345, 380, 397, 453, 380, 380,
380, 380, 380, 380, 380, 380, 380, 380, 380, 380,
380, 380, 380, 453, 380, 380, 380, 380, 380, 382,
453, 453, 398, 382, 382, 382, 398, 382, 382, 382,
239, 398, 453, 453, 453, 179, 453, 453, 239, 179,
453, 239, 239, 239, 179, 239, 239, 239, 353, 453,
453, 353, 353, 353, 353, 353, 353, 353, 353, 353,
353, 353, 353, 353, 353, 353, 453, 353, 353, 353,
353, 353, 388, 453, 453, 453, 388, 388, 453, 388,
453, 453, 453, 388, 388, 388, 388, 388, 388, 388,
453, 388, 356, 356, 453, 356, 356, 453, 453, 356,
356, 356, 356, 356, 356, 356, 399, 356, 393, 184,
399, 453, 453, 184, 453, 399, 453, 453, 184, 393,
393, 393, 453, 393, 393, 393, 362, 453, 362, 453,
453, 400, 362, 362, 362, 400, 362, 362, 362, 322,
400, 453, 322, 322, 453, 322, 322, 453, 453, 322,
322, 322, 322, 322, 322, 322, 189, 322, 401, 198,
189, 453, 401, 198, 453, 189, 453, 401, 198, 380,
453, 453, 380, 380, 380, 380, 380, 380, 380, 380,
380, 380, 380, 380, 380, 380, 380, 453, 380, 380,
380, 380, 380, 382, 453, 453, 404, 382, 382, 382,
404, 382, 382, 382, 405, 404, 406, 159, 405, 453,
406, 159, 453, 405, 453, 406, 159, 407, 453, 453,
407, 407, 407, 407, 407, 407, 407, 407, 407, 407,
407, 407, 407, 407, 407, 453, 407, 407, 407, 407,
407, 409, 409, 453, 409, 409, 453, 453, 409, 409,
409, 409, 409, 409, 409, 410, 409, 166, 411, 410,
453, 166, 411, 453, 410, 453, 166, 411, 166, 166,
453, 166, 166, 453, 453, 166, 166, 166, 166, 166,
166, 166, 413, 166, 412, 453, 413, 453, 412, 412,
412, 413, 412, 412, 412, 414, 415, 416, 417, 414,
415, 416, 417, 453, 414, 415, 416, 417, 418, 419,
420, 422, 418, 419, 420, 422, 453, 418, 419, 420,
422, 246, 423, 424, 425, 246, 423, 424, 425, 453,
246, 423, 424, 425, 426, 427, 428, 263, 426, 427,
428, 263, 453, 426, 427, 428, 263, 429, 430, 431,
432, 429, 430, 431, 432, 453, 429, 430, 431, 432,
434, 435, 436, 437, 434, 435, 436, 437, 453, 434,
435, 436, 437, 438, 322, 439, 440, 438, 322, 439,
440, 453, 438, 322, 439, 440, 441, 442, 443, 444,
441, 442, 443, 444, 453, 441, 442, 443, 444, 445,
446, 392, 447, 445, 446, 392, 447, 453, 445, 446,
392, 447, 448, 179, 184, 189, 448, 179, 184, 189,
453, 448, 179, 184, 189, 198, 449, 159, 166, 198,
449, 159, 166, 453, 198, 449, 159, 166, 450, 451,
246, 452, 450, 451, 246, 452, 453, 450, 451, 246,
452, 263, 453, 453, 453, 263, 453, 453, 453, 453,
263, 29, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453
} ;
static yyconst flex_int16_t yy_chk[3331] =
{ 0,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 5, 5,
6, 6, 7, 7, 407, 7, 5, 50, 6, 8,
8, 387, 8, 9, 9, 10, 10, 11, 11, 62,
11, 9, 62, 10, 12, 12, 84, 12, 13, 13,
13, 37, 37, 13, 14, 14, 14, 38, 13, 14,
23, 23, 38, 5, 14, 6, 50, 7, 15, 15,
15, 23, 142, 15, 8, 380, 23, 13, 9, 36,
10, 36, 11, 14, 142, 16, 16, 16, 84, 12,
16, 25, 25, 24, 24, 15, 19, 19, 19, 25,
19, 19, 13, 59, 24, 19, 19, 73, 14, 24,
52, 52, 16, 20, 20, 20, 55, 20, 20, 362,
15, 55, 20, 20, 78, 26, 26, 49, 59, 49,
130, 68, 73, 26, 68, 130, 25, 16, 17, 17,
17, 49, 79, 17, 21, 21, 83, 21, 140, 78,
140, 88, 21, 21, 21, 57, 57, 361, 21, 57,
21, 68, 92, 92, 94, 354, 49, 19, 17, 17,
26, 83, 17, 64, 64, 17, 88, 64, 353, 79,
17, 346, 22, 22, 20, 22, 57, 82, 82, 94,
22, 22, 22, 17, 17, 82, 22, 17, 22, 99,
17, 98, 98, 104, 64, 17, 18, 18, 18, 103,
103, 18, 189, 105, 21, 57, 21, 106, 87, 87,
107, 87, 108, 113, 113, 99, 136, 136, 198, 104,
143, 143, 82, 64, 145, 145, 18, 18, 105, 154,
18, 155, 106, 18, 156, 107, 156, 108, 18, 189,
160, 154, 22, 155, 22, 157, 169, 157, 156, 174,
157, 18, 18, 87, 166, 18, 170, 166, 18, 343,
198, 174, 342, 18, 147, 160, 154, 159, 155, 176,
219, 219, 319, 156, 168, 168, 159, 178, 168, 147,
178, 170, 285, 285, 166, 169, 147, 147, 147, 147,
147, 147, 147, 147, 147, 147, 147, 147, 147, 147,
147, 147, 147, 147, 147, 168, 159, 178, 176, 147,
180, 147, 147, 147, 147, 147, 147, 147, 147, 147,
147, 147, 147, 147, 147, 147, 147, 147, 147, 147,
147, 167, 185, 190, 168, 180, 191, 199, 195, 195,
200, 207, 167, 167, 209, 167, 195, 204, 204, 210,
204, 212, 213, 237, 318, 246, 241, 185, 311, 248,
264, 191, 247, 277, 246, 200, 207, 237, 241, 209,
190, 247, 249, 167, 210, 278, 212, 213, 310, 199,
348, 249, 279, 195, 248, 264, 309, 280, 277, 287,
287, 308, 204, 241, 246, 348, 300, 299, 298, 296,
278, 247, 167, 238, 295, 238, 238, 279, 294, 293,
281, 249, 280, 238, 238, 238, 238, 238, 238, 238,
238, 238, 238, 238, 238, 238, 238, 238, 238, 238,
238, 238, 286, 255, 255, 281, 238, 255, 238, 238,
238, 238, 238, 238, 238, 238, 238, 238, 238, 238,
238, 238, 238, 238, 238, 238, 238, 238, 239, 312,
312, 324, 336, 312, 255, 239, 239, 239, 239, 239,
239, 239, 239, 239, 239, 239, 239, 239, 239, 239,
239, 239, 239, 239, 254, 263, 324, 336, 303, 337,
312, 340, 377, 255, 263, 254, 254, 303, 254, 322,
313, 313, 323, 325, 313, 356, 356, 392, 322, 356,
392, 323, 325, 364, 337, 378, 340, 377, 402, 312,
421, 355, 364, 273, 263, 492, 254, 303, 269, 492,
261, 313, 355, 355, 492, 355, 356, 392, 322, 260,
378, 323, 325, 402, 500, 421, 253, 243, 500, 242,
236, 234, 364, 500, 231, 254, 301, 388, 388, 301,
313, 388, 230, 355, 229, 356, 301, 301, 301, 301,
301, 301, 301, 301, 301, 301, 301, 301, 301, 301,
301, 301, 301, 301, 301, 409, 409, 501, 388, 409,
507, 501, 355, 508, 507, 222, 501, 508, 221, 507,
511, 512, 508, 515, 511, 512, 218, 515, 215, 511,
512, 516, 515, 214, 519, 516, 409, 388, 519, 203,
516, 520, 533, 519, 534, 520, 533, 202, 534, 194,
520, 533, 537, 534, 538, 543, 537, 193, 538, 543,
184, 537, 179, 538, 543, 409, 454, 454, 454, 454,
454, 454, 454, 454, 454, 454, 454, 454, 454, 454,
454, 454, 454, 454, 454, 454, 454, 454, 454, 454,
455, 455, 455, 455, 455, 455, 455, 455, 455, 455,
455, 455, 455, 455, 455, 455, 455, 455, 455, 455,
455, 455, 455, 455, 456, 456, 456, 456, 456, 456,
456, 456, 456, 456, 456, 456, 456, 456, 456, 456,
456, 456, 456, 456, 456, 456, 456, 456, 457, 457,
457, 457, 457, 457, 457, 457, 457, 457, 457, 457,
457, 457, 457, 457, 457, 457, 457, 457, 457, 457,
457, 457, 458, 458, 458, 458, 458, 458, 458, 458,
458, 458, 458, 458, 458, 458, 458, 458, 458, 458,
458, 458, 458, 458, 458, 458, 459, 459, 459, 459,
459, 459, 459, 459, 459, 459, 459, 459, 459, 459,
459, 459, 459, 459, 459, 459, 459, 459, 459, 459,
460, 460, 460, 460, 460, 460, 460, 460, 460, 460,
460, 460, 460, 460, 460, 460, 460, 460, 460, 460,
460, 460, 460, 460, 461, 461, 461, 461, 461, 461,
461, 461, 461, 461, 461, 461, 461, 461, 461, 461,
461, 461, 461, 461, 461, 461, 461, 461, 462, 462,
462, 462, 462, 462, 462, 462, 462, 462, 462, 462,
462, 462, 462, 462, 462, 462, 462, 462, 462, 462,
462, 462, 463, 463, 463, 463, 463, 463, 463, 463,
463, 463, 463, 463, 463, 463, 463, 463, 463, 463,
463, 463, 463, 463, 463, 463, 464, 464, 464, 464,
464, 464, 464, 464, 464, 464, 464, 464, 464, 464,
464, 464, 464, 464, 464, 464, 464, 464, 464, 464,
465, 465, 465, 465, 465, 465, 465, 465, 465, 465,
465, 465, 465, 465, 465, 465, 465, 465, 465, 465,
465, 465, 465, 465, 466, 175, 466, 466, 466, 466,
466, 466, 466, 466, 466, 466, 466, 466, 466, 466,
466, 466, 165, 466, 466, 466, 466, 466, 467, 467,
467, 467, 467, 467, 467, 467, 467, 467, 467, 467,
467, 467, 467, 467, 467, 467, 467, 467, 467, 467,
467, 467, 468, 468, 162, 468, 468, 468, 468, 161,
468, 468, 468, 469, 151, 469, 469, 469, 469, 469,
469, 469, 469, 469, 469, 469, 469, 469, 469, 469,
469, 150, 469, 469, 469, 469, 469, 470, 144, 141,
137, 135, 134, 470, 470, 133, 131, 470, 470, 470,
470, 470, 470, 470, 128, 470, 471, 125, 471, 471,
471, 471, 471, 471, 471, 471, 471, 471, 471, 471,
471, 544, 471, 471, 471, 544, 471, 472, 472, 472,
544, 124, 472, 472, 473, 473, 119, 473, 473, 118,
114, 473, 473, 473, 473, 473, 473, 473, 112, 473,
474, 111, 474, 474, 110, 102, 474, 474, 474, 101,
474, 474, 474, 475, 475, 97, 475, 475, 96, 91,
475, 475, 475, 475, 475, 475, 475, 90, 475, 476,
86, 85, 476, 476, 476, 81, 476, 476, 476, 476,
476, 476, 476, 476, 476, 476, 476, 476, 476, 476,
476, 476, 476, 477, 545, 477, 546, 80, 545, 76,
546, 75, 74, 545, 549, 546, 477, 477, 549, 477,
477, 478, 71, 549, 478, 70, 478, 478, 478, 478,
478, 478, 478, 478, 478, 478, 478, 478, 478, 478,
478, 478, 478, 478, 478, 479, 552, 479, 553, 69,
552, 66, 553, 61, 54, 552, 554, 553, 479, 479,
554, 479, 479, 480, 47, 554, 480, 480, 480, 480,
480, 480, 480, 480, 480, 480, 480, 480, 480, 480,
480, 480, 480, 480, 480, 480, 480, 481, 555, 481,
557, 44, 555, 43, 557, 40, 39, 555, 558, 557,
481, 481, 558, 481, 481, 482, 35, 558, 482, 482,
482, 482, 482, 482, 482, 482, 482, 482, 482, 482,
482, 482, 482, 482, 482, 482, 482, 482, 482, 483,
560, 483, 561, 34, 560, 33, 561, 32, 29, 560,
0, 561, 483, 483, 0, 483, 483, 484, 484, 484,
484, 0, 484, 0, 0, 0, 484, 0, 484, 484,
484, 484, 484, 484, 484, 484, 484, 484, 484, 0,
484, 485, 0, 0, 485, 0, 485, 485, 485, 485,
485, 485, 485, 485, 485, 485, 485, 485, 485, 485,
485, 485, 485, 485, 485, 486, 0, 0, 486, 486,
486, 486, 486, 486, 486, 0, 486, 486, 486, 486,
486, 486, 486, 486, 486, 486, 486, 486, 486, 487,
0, 0, 487, 487, 487, 0, 487, 487, 487, 487,
487, 487, 487, 487, 487, 487, 487, 0, 487, 487,
487, 487, 487, 488, 488, 488, 488, 488, 488, 488,
488, 488, 488, 488, 488, 488, 488, 488, 488, 488,
488, 488, 488, 488, 488, 488, 488, 489, 0, 489,
489, 489, 489, 489, 489, 489, 489, 489, 489, 489,
489, 489, 489, 489, 489, 0, 489, 489, 489, 489,
489, 490, 0, 0, 0, 490, 490, 490, 0, 490,
490, 490, 0, 490, 491, 0, 491, 491, 491, 491,
491, 491, 491, 491, 491, 491, 491, 491, 491, 491,
491, 491, 0, 491, 491, 491, 491, 491, 493, 0,
0, 493, 493, 0, 493, 493, 0, 0, 493, 493,
493, 493, 493, 493, 493, 0, 493, 494, 0, 494,
494, 494, 494, 494, 494, 0, 572, 0, 494, 0,
572, 494, 0, 494, 495, 572, 495, 495, 495, 495,
495, 495, 495, 495, 495, 495, 495, 495, 495, 574,
495, 495, 495, 574, 495, 496, 575, 576, 574, 0,
575, 576, 496, 496, 496, 575, 576, 496, 496, 497,
0, 0, 0, 497, 497, 0, 497, 0, 0, 0,
497, 497, 497, 497, 497, 497, 497, 0, 497, 498,
498, 0, 498, 498, 0, 0, 498, 498, 498, 498,
498, 498, 498, 0, 498, 499, 0, 0, 0, 0,
0, 499, 499, 0, 0, 499, 499, 499, 499, 499,
499, 499, 577, 499, 502, 0, 577, 0, 0, 502,
0, 577, 0, 0, 583, 502, 502, 502, 583, 502,
502, 502, 503, 583, 503, 0, 0, 584, 503, 503,
503, 584, 503, 503, 503, 504, 584, 0, 0, 0,
0, 504, 504, 0, 0, 504, 504, 504, 504, 504,
504, 504, 0, 504, 505, 0, 0, 505, 505, 505,
0, 505, 505, 505, 505, 505, 505, 505, 505, 505,
505, 505, 505, 505, 505, 505, 505, 505, 506, 585,
506, 586, 0, 585, 0, 586, 0, 0, 585, 589,
586, 506, 506, 589, 506, 506, 509, 0, 589, 509,
0, 509, 509, 509, 509, 509, 509, 509, 509, 509,
509, 509, 509, 509, 509, 509, 509, 509, 509, 509,
510, 590, 510, 593, 0, 590, 0, 593, 0, 0,
590, 594, 593, 510, 510, 594, 510, 510, 513, 0,
594, 513, 513, 513, 513, 513, 513, 513, 513, 513,
513, 513, 513, 513, 513, 513, 513, 513, 513, 513,
513, 513, 514, 595, 514, 596, 0, 595, 0, 596,
0, 0, 595, 597, 596, 514, 514, 597, 514, 514,
517, 0, 597, 517, 517, 517, 517, 517, 517, 517,
517, 517, 517, 517, 517, 517, 517, 517, 517, 517,
517, 517, 517, 517, 518, 598, 518, 599, 0, 598,
0, 599, 0, 0, 598, 0, 599, 518, 518, 0,
518, 518, 521, 521, 521, 521, 0, 521, 0, 0,
0, 521, 0, 521, 521, 521, 521, 521, 521, 521,
521, 521, 521, 521, 0, 521, 522, 0, 0, 522,
522, 522, 522, 522, 522, 522, 522, 522, 522, 522,
522, 522, 522, 522, 522, 522, 522, 522, 522, 522,
523, 523, 523, 523, 523, 523, 523, 523, 523, 523,
523, 523, 523, 523, 523, 523, 523, 523, 523, 523,
523, 523, 523, 523, 524, 0, 0, 524, 524, 524,
524, 524, 524, 524, 0, 524, 524, 524, 524, 524,
524, 524, 524, 524, 524, 524, 524, 524, 525, 0,
0, 525, 525, 525, 0, 525, 525, 525, 525, 525,
525, 525, 525, 525, 525, 525, 0, 525, 525, 525,
525, 525, 526, 0, 0, 526, 526, 526, 0, 526,
526, 526, 526, 526, 526, 526, 526, 526, 526, 526,
0, 526, 526, 526, 526, 526, 527, 0, 0, 527,
527, 527, 0, 527, 527, 527, 527, 527, 527, 527,
527, 527, 527, 527, 0, 527, 527, 527, 527, 527,
528, 0, 528, 528, 528, 528, 0, 528, 528, 528,
528, 528, 528, 528, 528, 528, 528, 528, 0, 528,
528, 528, 528, 528, 529, 529, 0, 529, 529, 529,
0, 529, 529, 529, 529, 529, 529, 529, 529, 529,
529, 529, 0, 529, 529, 529, 529, 529, 530, 0,
0, 0, 530, 530, 530, 0, 530, 530, 530, 0,
530, 531, 0, 0, 531, 531, 531, 531, 531, 531,
531, 531, 531, 531, 531, 531, 531, 531, 531, 0,
531, 531, 531, 531, 531, 532, 600, 0, 0, 0,
600, 0, 532, 0, 0, 600, 532, 532, 532, 0,
532, 532, 532, 535, 0, 0, 535, 535, 0, 535,
535, 0, 0, 535, 535, 535, 535, 535, 535, 535,
0, 535, 536, 0, 536, 536, 536, 536, 536, 536,
0, 601, 0, 536, 0, 601, 536, 602, 536, 539,
601, 602, 0, 539, 539, 539, 602, 0, 539, 539,
540, 0, 0, 540, 540, 540, 540, 540, 540, 540,
540, 540, 540, 540, 540, 540, 540, 540, 0, 540,
540, 540, 540, 540, 541, 0, 0, 0, 541, 541,
0, 541, 0, 0, 0, 541, 541, 541, 541, 541,
541, 541, 0, 541, 542, 542, 0, 542, 542, 0,
0, 542, 542, 542, 542, 542, 542, 542, 608, 542,
547, 609, 608, 0, 0, 609, 0, 608, 0, 0,
609, 547, 547, 547, 0, 547, 547, 547, 548, 0,
548, 0, 0, 610, 548, 548, 548, 610, 548, 548,
548, 550, 610, 0, 550, 550, 0, 550, 550, 0,
0, 550, 550, 550, 550, 550, 550, 550, 0, 550,
551, 0, 551, 551, 551, 551, 551, 551, 0, 611,
0, 551, 0, 611, 551, 0, 551, 556, 611, 0,
556, 556, 556, 0, 556, 556, 556, 556, 556, 556,
556, 556, 556, 556, 556, 556, 556, 556, 556, 556,
556, 559, 0, 0, 559, 0, 559, 559, 559, 559,
559, 559, 559, 559, 559, 559, 559, 559, 559, 559,
559, 559, 559, 559, 559, 562, 562, 562, 562, 562,
562, 562, 562, 562, 562, 562, 562, 562, 562, 562,
562, 562, 562, 562, 562, 562, 562, 562, 562, 563,
0, 0, 563, 563, 563, 0, 563, 563, 563, 563,
563, 563, 563, 563, 563, 563, 563, 0, 563, 563,
563, 563, 563, 564, 0, 0, 564, 564, 564, 0,
564, 564, 564, 564, 564, 564, 564, 564, 564, 564,
564, 0, 564, 564, 564, 564, 564, 565, 0, 0,
565, 565, 565, 0, 565, 565, 565, 565, 565, 565,
565, 565, 565, 565, 565, 0, 565, 565, 565, 565,
565, 566, 0, 0, 566, 566, 566, 0, 566, 566,
566, 566, 566, 566, 566, 566, 566, 566, 566, 0,
566, 566, 566, 566, 566, 567, 0, 0, 567, 567,
567, 567, 567, 567, 567, 567, 567, 567, 567, 567,
567, 567, 567, 0, 567, 567, 567, 567, 567, 568,
0, 0, 568, 568, 568, 568, 568, 568, 568, 568,
568, 568, 568, 568, 568, 568, 568, 0, 568, 568,
568, 568, 568, 569, 0, 0, 615, 569, 569, 569,
615, 569, 569, 569, 570, 615, 0, 0, 0, 616,
0, 0, 0, 616, 0, 570, 570, 570, 616, 570,
570, 570, 571, 0, 571, 0, 0, 617, 571, 571,
571, 617, 571, 571, 571, 573, 617, 0, 573, 573,
0, 573, 573, 0, 0, 573, 573, 573, 573, 573,
573, 573, 0, 573, 578, 618, 621, 578, 0, 618,
621, 578, 578, 578, 618, 621, 578, 578, 579, 0,
0, 579, 579, 579, 579, 579, 579, 579, 579, 579,
579, 579, 579, 579, 579, 579, 0, 579, 579, 579,
579, 579, 580, 0, 0, 580, 580, 580, 580, 580,
580, 580, 580, 580, 580, 580, 580, 580, 580, 580,
0, 580, 580, 580, 580, 580, 581, 581, 0, 581,
581, 0, 0, 581, 581, 581, 581, 581, 581, 581,
0, 581, 582, 582, 0, 582, 582, 0, 0, 582,
582, 582, 582, 582, 582, 582, 0, 582, 587, 0,
587, 0, 0, 623, 587, 587, 587, 623, 587, 587,
587, 588, 623, 588, 0, 0, 624, 588, 588, 588,
624, 588, 588, 588, 591, 624, 0, 591, 591, 0,
591, 591, 0, 0, 591, 591, 591, 591, 591, 591,
591, 0, 591, 592, 0, 592, 592, 592, 592, 592,
592, 0, 625, 0, 592, 0, 625, 592, 0, 592,
603, 625, 0, 603, 603, 603, 603, 603, 603, 603,
603, 603, 603, 603, 603, 603, 603, 603, 0, 603,
603, 603, 603, 603, 604, 0, 0, 626, 604, 604,
604, 626, 604, 604, 604, 605, 626, 0, 605, 605,
605, 605, 605, 605, 605, 605, 605, 605, 605, 605,
605, 605, 605, 0, 605, 605, 605, 605, 605, 606,
0, 0, 627, 606, 606, 606, 627, 606, 606, 606,
607, 627, 0, 0, 0, 628, 0, 0, 607, 628,
0, 607, 607, 607, 628, 607, 607, 607, 612, 0,
0, 612, 612, 612, 612, 612, 612, 612, 612, 612,
612, 612, 612, 612, 612, 612, 0, 612, 612, 612,
612, 612, 613, 0, 0, 0, 613, 613, 0, 613,
0, 0, 0, 613, 613, 613, 613, 613, 613, 613,
0, 613, 614, 614, 0, 614, 614, 0, 0, 614,
614, 614, 614, 614, 614, 614, 629, 614, 619, 630,
629, 0, 0, 630, 0, 629, 0, 0, 630, 619,
619, 619, 0, 619, 619, 619, 620, 0, 620, 0,
0, 631, 620, 620, 620, 631, 620, 620, 620, 622,
631, 0, 622, 622, 0, 622, 622, 0, 0, 622,
622, 622, 622, 622, 622, 622, 632, 622, 633, 634,
632, 0, 633, 634, 0, 632, 0, 633, 634, 635,
0, 0, 635, 635, 635, 635, 635, 635, 635, 635,
635, 635, 635, 635, 635, 635, 635, 0, 635, 635,
635, 635, 635, 636, 0, 0, 637, 636, 636, 636,
637, 636, 636, 636, 638, 637, 639, 640, 638, 0,
639, 640, 0, 638, 0, 639, 640, 641, 0, 0,
641, 641, 641, 641, 641, 641, 641, 641, 641, 641,
641, 641, 641, 641, 641, 0, 641, 641, 641, 641,
641, 642, 642, 0, 642, 642, 0, 0, 642, 642,
642, 642, 642, 642, 642, 643, 642, 644, 645, 643,
0, 644, 645, 0, 643, 0, 644, 645, 646, 646,
0, 646, 646, 0, 0, 646, 646, 646, 646, 646,
646, 646, 648, 646, 647, 0, 648, 0, 647, 647,
647, 648, 647, 647, 647, 649, 650, 651, 652, 649,
650, 651, 652, 0, 649, 650, 651, 652, 653, 654,
655, 656, 653, 654, 655, 656, 0, 653, 654, 655,
656, 657, 658, 659, 660, 657, 658, 659, 660, 0,
657, 658, 659, 660, 661, 662, 663, 664, 661, 662,
663, 664, 0, 661, 662, 663, 664, 665, 666, 667,
668, 665, 666, 667, 668, 0, 665, 666, 667, 668,
669, 670, 671, 672, 669, 670, 671, 672, 0, 669,
670, 671, 672, 673, 674, 675, 676, 673, 674, 675,
676, 0, 673, 674, 675, 676, 677, 678, 679, 680,
677, 678, 679, 680, 0, 677, 678, 679, 680, 681,
682, 683, 684, 681, 682, 683, 684, 0, 681, 682,
683, 684, 685, 686, 687, 688, 685, 686, 687, 688,
0, 685, 686, 687, 688, 689, 690, 691, 692, 689,
690, 691, 692, 0, 689, 690, 691, 692, 693, 694,
695, 696, 693, 694, 695, 696, 0, 693, 694, 695,
696, 697, 0, 0, 0, 697, 0, 0, 0, 0,
697, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453,
453, 453, 453, 453, 453, 453, 453, 453, 453, 453
} ;
/* The intent behind this definition is that it'll catch
* any uses of REJECT which flex missed.
*/
#define REJECT reject_used_but_not_detected
#define yymore() (yyg->yy_more_flag = 1)
#define YY_MORE_ADJ yyg->yy_more_len
#define YY_RESTORE_YY_MORE_OFFSET
#line 1 "sparql_l.l"
/*
* $Id$
*
* This file is part of the OpenLink Software Virtuoso Open-Source (VOS)
* project.
*
* Copyright (C) 1998-2019 OpenLink Software
*
* This project is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; only version 2 of the License, dated June 1991.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#line 36 "sparql_l.l"
#include "Dk.h"
#include "sparql_l.h"
#include "sparql_p.h"
#include "sparqlwords.h"
#include "dkpool.h"
struct yyguts_t;
#define sparyyerror(strg) sparyyerror_impl(yyextra, yytext, (strg))
#define sparyylval (((YYSTYPE *)(yylval))[0])
#undef YY_INPUT
#define YY_INPUT(buf,result,max_size) \
do \
{ \
int rest_len = yyextra->sparp_text_len - yyextra->sparp_text_ofs; \
int get_len = (max_size); \
if (get_len > rest_len) \
get_len = rest_len; \
memcpy ((buf), (yyextra->sparp_text + yyextra->sparp_text_ofs), get_len); \
(result) = get_len; \
yyextra->sparp_text_ofs += get_len; \
} while (0);
int sparscn_yy_null = YY_NULL;
#define GET_OUTER_BEGIN ((0 == yyextra->sparp_lexdepth) ? UNREACHEABLE : yyextra->sparp_lexstates[yyextra->sparp_lexdepth-1])
#define GET_CURRENT_BEGIN yyextra->sparp_lexstates[yyextra->sparp_lexdepth]
#define SET_CURRENT_BEGIN(state) yyextra->sparp_lexstates[yyextra->sparp_lexdepth] = (state)
#define SET_INNER_BEGIN(state) yyextra->sparp_lexstates[yyextra->sparp_lexdepth+1] = (state)
#define BEGIN_NEW_CURRENT(state) BEGIN (yyextra->sparp_lexstates[yyextra->sparp_lexdepth] = (state))
#define BEGIN_CURRENT BEGIN (yyextra->sparp_lexstates[yyextra->sparp_lexdepth])
static const char *sparyyerror_msg_toodeep = "The expression is too complex, or some closing parentheses are missing";
static const char *sparyyerror_msg_tooshallow = "Too many closing parentheses";
#define BEGIN_INNER \
do \
{ \
if (SPARP_MAX_LEX_DEPTH <= yyextra->sparp_lexdepth) \
sparyyerror (sparyyerror_msg_toodeep); \
else \
{ \
yyextra->sparp_lexdepth += 1; \
BEGIN_CURRENT; \
} \
} while(0)
#define BEGIN_INNER_1(i) do { SET_INNER_BEGIN((i)); BEGIN_INNER; yyextra->sparp_lexpars[yyextra->sparp_lexdepth-1]='x'; } while (0)
#define BEGIN_INNER_2(i,c) do { SET_CURRENT_BEGIN((c)); SET_INNER_BEGIN((i)); BEGIN_INNER; yyextra->sparp_lexpars[yyextra->sparp_lexdepth-1]='x'; } while (0)
#define BEGIN_OUTER \
do \
{ \
if (0 == yyextra->sparp_lexdepth) \
sparyyerror (sparyyerror_msg_tooshallow); \
else \
{ \
yyextra->sparp_lexdepth -= 1; \
BEGIN_CURRENT; \
} \
} while(0)
/* macro to save the text of a token */
#define SV yylval->box = t_box_dv_short_nchars(yytext, yyleng);
/* macro to save the text and return a token */
#define TOK(name) { /*SV;*/ return name; }
/* macros to save the text of opening parenthesis and return a token */
#define TOKPAR_FAKE_OPEN(closing_char, state_i) \
/*SV;*/ \
if (((closing_char) == '}') && (yyextra->sparp_lexdepth >= SPARP_MAX_BRACE_DEPTH)) \
sparyyerror ("Curly brace is nested too deep"); \
SET_INNER_BEGIN (state_i); \
BEGIN_INNER; \
yyextra->sparp_lexpars[yyextra->sparp_lexdepth-1]=(closing_char)
#define TOKPAR_OPEN(name, closing_char, state_i) \
{ \
TOKPAR_FAKE_OPEN(closing_char, state_i); \
return name; \
}
#define TOKPAR_OPEN_4(name, closing_char, state_i, state_c) \
{ \
/*SV;*/ \
SET_CURRENT_BEGIN (state_c); \
TOKPAR_FAKE_OPEN(closing_char, state_i); \
return name; \
}
/* macros to save the text of closing parenthesis and return a token */
#define TOKPAR_FAKE_CLOSE(closing_char) \
/*SV;*/ BEGIN_OUTER; \
if (closing_char != yyextra->sparp_lexpars[yyextra->sparp_lexdepth]) \
sparyyerror ("Parentheses are not balanced"); \
#define TOKPAR_CLOSE(name, closing_char) \
{ TOKPAR_FAKE_CLOSE(closing_char) \
return name; \
}
/* macro to save the text of closing parenthesis and return a token */
#define TOKPAR_CLOSE_3(name, closing_char, state) \
{ /*SV;*/ BEGIN_OUTER; BEGIN_NEW_CURRENT(state); \
if (closing_char != yyextra->sparp_lexpars[yyextra->sparp_lexdepth]) \
sparyyerror ("Parentheses are not balanced"); \
return name; \
}
#define TOKBOX_L(n,name,lex_type_descr) { \
yylval->box = t_box_dv_uname_string (yytext+n); \
TOKBOX_L_FINAL(name,lex_type_descr) }
/* No more dedicated UNAME case. All names are UNAMES :)
#define TOKBOX_UNAME_L(n,name,lex_type_descr) { yylval->box = t_box_dv_uname_string (yytext+n); \
TOKBOX_L_FINAL(name,lex_type_descr) } */
#define TOKBOX_UPCASE_L(n,name,lex_type_descr) { \
caddr_t tmp = sqlp_box_id_upcase (yytext+n); \
yylval->box = t_box_dv_uname_string (tmp); \
dk_free_box (tmp); \
TOKBOX_L_FINAL(name,lex_type_descr) }
#define TOKBOX_QUOTED_L(n,name,lex_type_descr) { \
caddr_t tmp = sqlp_box_id_quoted (yytext+n); \
yylval->box = t_box_dv_uname_string (tmp); \
dk_free_box (tmp); \
TOKBOX_L_FINAL(name,lex_type_descr) }
#define TOKPAR_OPEN_LNAME(n,name,closing_char,state_i,state_c) \
{ \
SET_CURRENT_BEGIN (state_c); \
TOKPAR_FAKE_OPEN(closing_char, state_i); \
do { \
char *name_begin; \
int name_len; \
name_begin = yytext + (n); \
name_begin += strspn (name_begin, " \t\r"); \
name_len = strcspn (name_begin, " \t\r{"); \
yylval->box = t_box_dv_uname_nchars (name_begin, name_len); \
} while(0); \
TOKBOX_L_FINAL(name,"Node name") }
void sparyyerror_if_long_qname (caddr_t box, const char *lex_type_descr, struct yyguts_t *yyg);
#define TOKBOX_Q_FINAL(name,lex_type_descr) \
if (box_length (yylval->box) > MAX_XML_LNAME_LENGTH) \
sparyyerror_if_long_qname (yylval->box, lex_type_descr, yyg); \
return (name);
#define TOKBOX_Q_ESC(name,lex_type_descr) { \
if (strchr (yytext, '\\')) \
yylval->box = spar_unescape_strliteral (yyextra, yytext, 0, SPAR_STRLITERAL_SPARQL_QNAME); \
else \
yylval->box = t_box_dv_uname_string (yytext); \
TOKBOX_Q_FINAL(name,lex_type_descr) }
#define TOKBOX_Q2(n1,n2,name,lex_type_descr) { \
yylval->box = t_box_dv_uname_nchars (yytext + (n1), strlen(yytext) - ((n1)+(n2))); \
TOKBOX_Q_FINAL(name,lex_type_descr) }
/* No more special UNAME case :)
#define TOKBOX_UNAME_Q(n,name,lex_type_descr) { \
yylval->box = t_box_dv_uname_string (yytext+(n)); \
TOKBOX_Q_FINAL(name,lex_type_descr) } */
int sparscn_NUMBER_int (YYSTYPE *yylval, struct yyguts_t * yyg);
int sparscn_NUMBER_decimal (YYSTYPE *yylval, struct yyguts_t * yyg);
int sparscn_NUMBER_double (YYSTYPE *yylval, struct yyguts_t * yyg);
extern int sparyylex (YYSTYPE *yylval, yyscan_t yyscanner);
#define YY_DECL int sparyylex (YYSTYPE *yylval, yyscan_t yyscanner)
void *
sparyyalloc (yy_size_t size, yyscan_t yyscanner)
{
return (void *) t_alloc_box (size, DV_STRING);
}
void *
sparyyrealloc (void * ptr, yy_size_t sz, yyscan_t yyscanner)
{
int old_sz = ((NULL == ptr) ? 0 : box_length (ptr));
if (old_sz < sz)
{
void *res = t_alloc_box (sz, DV_STRING);
memcpy (res, ptr, old_sz);
return res;
}
if (0 == sz)
return NULL;
return ptr;
}
void
sparyyfree (void * ptr , yyscan_t yyscanner)
{
}
/* Top-level SPARQL state */
/* Internals of single-quoted SPARQL string lit */
/* Internals of double-quoted SPARQL string lit */
/* Internals of triple-single-quoted SPARQL string lit */
/* Internals of triple-double-quoted SPARQL string lit */
/* Whitespace between 'COUNT' keyword and '(' or 'DISTINCT' after it */
/* Whitespace between 'IDENTIFIED' keyword and 'BY' keyword */
/* Whitespace between 'NOT' keyword and 'FROM', 'IN' or 'EXISTS' after it */
/* Whitespace between 'WHERE'/'SQLQUERY' keyword and '(' or '{' after it */
/* A fragment of SQL text between 'WHERE (' and matching ')' */
/* A comment inside SPARQL_SQL_FRAGMENT */
/* Single-quoted string inside SPARQL_SQL_FRAGMENT */
/* Special unreacheable state to fill the first item of yyextra->sparp_lexstates */
#line 1625 "sparql_l.c"
#define INITIAL 0
#define SPARQL 1
#define SPARQL_SQ 2
#define SPARQL_DQ 3
#define SPARQL_SSSQ 4
#define SPARQL_DDDQ 5
#define SPARQL_AFTER_COUNT 6
#define SPARQL_AFTER_IDENTIFIED 7
#define SPARQL_AFTER_NOT 8
#define SPARQL_AFTER_WHERE 9
#define SPARQL_SQL_FRAGMENT 10
#define SPARQL_SQL_COMMENT 11
#define SPARQL_SQL_SQSTRING 12
#define UNREACHEABLE 13
#ifndef YY_NO_UNISTD_H
/* Special case for "unistd.h", since it is non-ANSI. We include it way
* down here because we want the user's section 1 to have been scanned first.
* The user has a chance to override it with an option.
*/
#include <unistd.h>
#endif
#define YY_EXTRA_TYPE struct sparp_s *
/* Holds the entire state of the reentrant scanner. */
struct yyguts_t
{
/* User-defined. Not touched by flex. */
YY_EXTRA_TYPE yyextra_r;
/* The rest are the same as the globals declared in the non-reentrant scanner. */
FILE *yyin_r, *yyout_r;
size_t yy_buffer_stack_top; /**< index of top of stack. */
size_t yy_buffer_stack_max; /**< capacity of stack. */
YY_BUFFER_STATE * yy_buffer_stack; /**< Stack as an array. */
char yy_hold_char;
yy_size_t yy_n_chars;
yy_size_t yyleng_r;
char *yy_c_buf_p;
int yy_init;
int yy_start;
int yy_did_buffer_switch_on_eof;
int yy_start_stack_ptr;
int yy_start_stack_depth;
int *yy_start_stack;
yy_state_type yy_last_accepting_state;
char* yy_last_accepting_cpos;
int yylineno_r;
int yy_flex_debug_r;
char *yytext_r;
int yy_more_flag;
int yy_more_len;
}; /* end struct yyguts_t */
static int yy_init_globals (yyscan_t yyscanner );
int sparyylex_init (yyscan_t* scanner);
int sparyylex_init_extra (YY_EXTRA_TYPE user_defined,yyscan_t* scanner);
/* Accessor methods to globals.
These are made visible to non-reentrant scanners for convenience. */
int sparyylex_destroy (yyscan_t yyscanner );
int sparyyget_debug (yyscan_t yyscanner );
void sparyyset_debug (int debug_flag ,yyscan_t yyscanner );
YY_EXTRA_TYPE sparyyget_extra (yyscan_t yyscanner );
void sparyyset_extra (YY_EXTRA_TYPE user_defined ,yyscan_t yyscanner );
FILE *sparyyget_in (yyscan_t yyscanner );
void sparyyset_in (FILE * in_str ,yyscan_t yyscanner );
FILE *sparyyget_out (yyscan_t yyscanner );
void sparyyset_out (FILE * out_str ,yyscan_t yyscanner );
yy_size_t sparyyget_leng (yyscan_t yyscanner );
char *sparyyget_text (yyscan_t yyscanner );
int sparyyget_lineno (yyscan_t yyscanner );
void sparyyset_lineno (int line_number ,yyscan_t yyscanner );
int sparyyget_column (yyscan_t yyscanner );
void sparyyset_column (int column_no ,yyscan_t yyscanner );
/* Macros after this point can all be overridden by user definitions in
* section 1.
*/
#ifndef YY_SKIP_YYWRAP
#ifdef __cplusplus
extern "C" int sparyywrap (yyscan_t yyscanner );
#else
extern int sparyywrap (yyscan_t yyscanner );
#endif
#endif
#ifndef yytext_ptr
static void yy_flex_strncpy (char *,yyconst char *,int ,yyscan_t yyscanner);
#endif
#ifdef YY_NEED_STRLEN
static int yy_flex_strlen (yyconst char * ,yyscan_t yyscanner);
#endif
#ifndef YY_NO_INPUT
#ifdef __cplusplus
static int yyinput (yyscan_t yyscanner );
#else
static int input (yyscan_t yyscanner );
#endif
#endif
/* Amount of stuff to slurp up with each read. */
#ifndef YY_READ_BUF_SIZE
#define YY_READ_BUF_SIZE 8192
#endif
/* Copy whatever the last rule matched to the standard output. */
#ifndef ECHO
/* This used to be an fputs(), but since the string might contain NUL's,
* we now use fwrite().
*/
#define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0)
#endif
/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL,
* is returned in "result".
*/
#ifndef YY_INPUT
#define YY_INPUT(buf,result,max_size) \
if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
{ \
int c = '*'; \
size_t n; \
for ( n = 0; n < max_size && \
(c = getc( yyin )) != EOF && c != '\n'; ++n ) \
buf[n] = (char) c; \
if ( c == '\n' ) \
buf[n++] = (char) c; \
if ( c == EOF && ferror( yyin ) ) \
YY_FATAL_ERROR( "input in flex scanner failed" ); \
result = n; \
} \
else \
{ \
errno=0; \
while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
{ \
if( errno != EINTR) \
{ \
YY_FATAL_ERROR( "input in flex scanner failed" ); \
break; \
} \
errno=0; \
clearerr(yyin); \
} \
}\
\
#endif
/* No semi-colon after return; correct usage is to write "yyterminate();" -
* we don't want an extra ';' after the "return" because that will cause
* some compilers to complain about unreachable statements.
*/
#ifndef yyterminate
#define yyterminate() return YY_NULL
#endif
/* Number of entries by which start-condition stack grows. */
#ifndef YY_START_STACK_INCR
#define YY_START_STACK_INCR 25
#endif
/* Report a fatal error. */
#ifndef YY_FATAL_ERROR
#define YY_FATAL_ERROR(msg) yy_fatal_error( msg , yyscanner)
#endif
/* end tables serialization structures and prototypes */
/* Default declaration of generated scanner - a define so the user can
* easily add parameters.
*/
#ifndef YY_DECL
#define YY_DECL_IS_OURS 1
extern int sparyylex (yyscan_t yyscanner);
#define YY_DECL int sparyylex (yyscan_t yyscanner)
#endif /* !YY_DECL */
/* Code executed at the beginning of each rule, after yytext and yyleng
* have been set up.
*/
#ifndef YY_USER_ACTION
#define YY_USER_ACTION
#endif
/* Code executed at the end of each rule. */
#ifndef YY_BREAK
#define YY_BREAK break;
#endif
#define YY_RULE_SETUP \
YY_USER_ACTION
/** The main scanner function which does all the work.
*/
YY_DECL
{
register yy_state_type yy_current_state;
register char *yy_cp, *yy_bp;
register int yy_act;
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
#line 334 "sparql_l.l"
/* Plain non-keyword punctuators */
#line 1864 "sparql_l.c"
if ( !yyg->yy_init )
{
yyg->yy_init = 1;
#ifdef YY_USER_INIT
YY_USER_INIT;
#endif
if ( ! yyg->yy_start )
yyg->yy_start = 1; /* first start state */
if ( ! yyin )
yyin = stdin;
if ( ! yyout )
yyout = stdout;
if ( ! YY_CURRENT_BUFFER ) {
sparyyensure_buffer_stack (yyscanner);
YY_CURRENT_BUFFER_LVALUE =
sparyy_create_buffer(yyin,YY_BUF_SIZE ,yyscanner);
}
sparyy_load_buffer_state(yyscanner );
}
while ( 1 ) /* loops until end-of-file is reached */
{
yyg->yy_more_len = 0;
if ( yyg->yy_more_flag )
{
yyg->yy_more_len = yyg->yy_c_buf_p - yyg->yytext_ptr;
yyg->yy_more_flag = 0;
}
yy_cp = yyg->yy_c_buf_p;
/* Support of yytext. */
*yy_cp = yyg->yy_hold_char;
/* yy_bp points to the position in yy_ch_buf of the start of
* the current run.
*/
yy_bp = yy_cp;
yy_current_state = yyg->yy_start;
yy_match:
do
{
register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
if ( yy_accept[yy_current_state] )
{
yyg->yy_last_accepting_state = yy_current_state;
yyg->yy_last_accepting_cpos = yy_cp;
}
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
if ( yy_current_state >= 454 )
yy_c = yy_meta[(unsigned int) yy_c];
}
yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
++yy_cp;
}
while ( yy_current_state != 453 );
yy_cp = yyg->yy_last_accepting_cpos;
yy_current_state = yyg->yy_last_accepting_state;
yy_find_action:
yy_act = yy_accept[yy_current_state];
YY_DO_BEFORE_ACTION;
do_action: /* This label is used only to access EOF actions. */
switch ( yy_act )
{ /* beginning of action switch */
case 0: /* must back up */
/* undo the effects of YY_DO_BEFORE_ACTION */
*yy_cp = yyg->yy_hold_char;
yy_cp = yyg->yy_last_accepting_cpos;
yy_current_state = yyg->yy_last_accepting_state;
goto yy_find_action;
case 1:
YY_RULE_SETUP
#line 338 "sparql_l.l"
{ return _AMP_AMP ; }
YY_BREAK
case 2:
YY_RULE_SETUP
#line 339 "sparql_l.l"
{ return _BACKQUOTE ; }
YY_BREAK
case 3:
YY_RULE_SETUP
#line 340 "sparql_l.l"
{ return _BANG ; }
YY_BREAK
case 4:
YY_RULE_SETUP
#line 341 "sparql_l.l"
{ return _BAR ; }
YY_BREAK
case 5:
YY_RULE_SETUP
#line 342 "sparql_l.l"
{ return _BAR_BAR ; }
YY_BREAK
case 6:
YY_RULE_SETUP
#line 343 "sparql_l.l"
{ return _CARET ; }
YY_BREAK
case 7:
YY_RULE_SETUP
#line 344 "sparql_l.l"
{ return _CARET_CARET ; }
YY_BREAK
case 8:
YY_RULE_SETUP
#line 345 "sparql_l.l"
{ return _COMMA ; }
YY_BREAK
case 9:
YY_RULE_SETUP
#line 346 "sparql_l.l"
{ return _DOT ; }
YY_BREAK
case 10:
YY_RULE_SETUP
#line 347 "sparql_l.l"
{ return _EQ ; }
YY_BREAK
case 11:
YY_RULE_SETUP
#line 348 "sparql_l.l"
{ return _GE ; }
YY_BREAK
case 12:
YY_RULE_SETUP
#line 349 "sparql_l.l"
{ return _GT ; }
YY_BREAK
case 13:
YY_RULE_SETUP
#line 350 "sparql_l.l"
{ return _LE ; }
YY_BREAK
case 14:
YY_RULE_SETUP
#line 351 "sparql_l.l"
{ return _LT ; }
YY_BREAK
case 15:
YY_RULE_SETUP
#line 352 "sparql_l.l"
{ yylval->token_type = yyextra->sparp_lexdepth; return _MINUS ; }
YY_BREAK
case 16:
YY_RULE_SETUP
#line 353 "sparql_l.l"
{ return _NOT_EQ ; }
YY_BREAK
case 17:
YY_RULE_SETUP
#line 354 "sparql_l.l"
{ yylval->token_type = yyextra->sparp_lexdepth; return _PLUS ; }
YY_BREAK
case 18:
YY_RULE_SETUP
#line 355 "sparql_l.l"
{ return _PLUS_GT ; }
YY_BREAK
case 19:
YY_RULE_SETUP
#line 356 "sparql_l.l"
{ return _QMARK ; }
YY_BREAK
case 20:
YY_RULE_SETUP
#line 357 "sparql_l.l"
{ return _SEMI ; }
YY_BREAK
case 21:
YY_RULE_SETUP
#line 358 "sparql_l.l"
{ return _SLASH ; }
YY_BREAK
case 22:
YY_RULE_SETUP
#line 359 "sparql_l.l"
{ return _STAR ; }
YY_BREAK
case 23:
YY_RULE_SETUP
#line 360 "sparql_l.l"
{ return _STAR_GT ; }
YY_BREAK
/* Keyword punctuators */
case 24:
YY_RULE_SETUP
#line 364 "sparql_l.l"
{ return a_L ; }
YY_BREAK
/* Grouping non-keyword punctuators */
case 25:
YY_RULE_SETUP
#line 368 "sparql_l.l"
TOKPAR_OPEN (_LPAR,')', GET_CURRENT_BEGIN)
YY_BREAK
case 26:
YY_RULE_SETUP
#line 369 "sparql_l.l"
TOKPAR_CLOSE (_RPAR,')')
YY_BREAK
case 27:
YY_RULE_SETUP
#line 370 "sparql_l.l"
TOKPAR_OPEN (_LBRA,'}', GET_CURRENT_BEGIN)
YY_BREAK
case 28:
YY_RULE_SETUP
#line 371 "sparql_l.l"
TOKPAR_CLOSE (_RBRA,'}')
YY_BREAK
case 29:
YY_RULE_SETUP
#line 372 "sparql_l.l"
TOKPAR_OPEN (_LSQBRA,']', GET_CURRENT_BEGIN)
YY_BREAK
case 30:
YY_RULE_SETUP
#line 373 "sparql_l.l"
TOKPAR_CLOSE (_RSQBRA,']')
YY_BREAK
/* Name lexems */
case 31:
YY_RULE_SETUP
#line 377 "sparql_l.l"
{
yylval->box = t_box_dv_uname_nchars (yytext + 1, yyleng - 2);
return Q_IRI_REF;
}
YY_BREAK
case 32:
YY_RULE_SETUP
#line 382 "sparql_l.l"
{ TOKBOX_Q_ESC(QNAME,"qualified URI"); }
YY_BREAK
case 33:
YY_RULE_SETUP
#line 383 "sparql_l.l"
{ TOKBOX_Q_ESC(QNAME_NS,"namespace"); }
YY_BREAK
case 34:
YY_RULE_SETUP
#line 384 "sparql_l.l"
{ TOKBOX_Q_ESC(BLANK_NODE_LABEL,"blank node label"); }
YY_BREAK
case 35:
YY_RULE_SETUP
#line 386 "sparql_l.l"
{
yylval->box = t_box_dv_uname_nchars (yytext + 1, yyleng - 1);
return QD_VARNAME;
}
YY_BREAK
case 36:
YY_RULE_SETUP
#line 391 "sparql_l.l"
{
yylval->box = t_box_dv_uname_nchars (yytext + 1, yyleng - 1);
return QD_COLON_PARAMNAME;
}
YY_BREAK
case 37:
YY_RULE_SETUP
#line 396 "sparql_l.l"
{
char buf[20]; sprintf (buf, ":%d", yyextra->sparp_sparqre->sparqre_param_ctr[0]);
yyextra->sparp_sparqre->sparqre_param_ctr[0] += 1;
yylval->box = t_box_dv_uname_string (buf);
return QD_COLON_PARAMNUM;
}
YY_BREAK
case 38:
YY_RULE_SETUP
#line 403 "sparql_l.l"
{
yylval->box = t_box_dv_uname_nchars (yytext + 1, yyleng - 1);
return LANGTAG;
}
YY_BREAK
case 39:
YY_RULE_SETUP
#line 408 "sparql_l.l"
{
const struct sparql_keyword *sk = sparql_lex_hash_kw (yytext, yyleng);
if (NULL == sk)
{
yylval->box = t_box_dv_short_nchars (yytext, yyleng); return SPARQL_PLAIN_ID;
}
switch (sk->token)
{
case COUNT_L: BEGIN SPARQL_AFTER_COUNT; break;
case IDENTIFIED_L: BEGIN SPARQL_AFTER_IDENTIFIED; return IDENTIFIED_L;
case NOT_L: BEGIN SPARQL_AFTER_NOT; break;
case WHERE_L: BEGIN SPARQL_AFTER_WHERE; return WHERE_L;
case SQLQUERY_L: BEGIN SPARQL_AFTER_WHERE; return SQLQUERY_L;
case SPARQL_BIF: yylval->token_type = sk->subtype; return SPARQL_BIF;
default: return sk->token;
} }
YY_BREAK
case 40:
YY_RULE_SETUP
#line 425 "sparql_l.l"
{ yylval->box = t_box_dv_short_nchars (yytext, yyleng); return SPARQL_SQL_ALIASCOLNAME; }
YY_BREAK
case 41:
YY_RULE_SETUP
#line 426 "sparql_l.l"
{ yylval->box = t_box_dv_short_nchars (yytext, yyleng); return SPARQL_SQL_QTABLENAME; }
YY_BREAK
case 42:
YY_RULE_SETUP
#line 427 "sparql_l.l"
{ yylval->box = t_box_dv_short_nchars (yytext, yyleng); return SPARQL_SQL_QTABLECOLNAME; }
YY_BREAK
/* Numeric lexems */
case 43:
YY_RULE_SETUP
#line 431 "sparql_l.l"
{ return sparscn_NUMBER_int (yylval, yyg); }
YY_BREAK
case 44:
YY_RULE_SETUP
#line 432 "sparql_l.l"
{ return sparscn_NUMBER_decimal (yylval, yyg); }
YY_BREAK
case 45:
YY_RULE_SETUP
#line 433 "sparql_l.l"
{ return sparscn_NUMBER_double (yylval, yyg); }
YY_BREAK
/* String lexems */
case 46:
YY_RULE_SETUP
#line 437 "sparql_l.l"
{
yylval->box = t_box_dv_short_nchars (yytext+1, yyleng - 2);
return SPARQL_STRING;
}
YY_BREAK
case 47:
YY_RULE_SETUP
#line 442 "sparql_l.l"
{ yymore(); SET_INNER_BEGIN(SPARQL_SSSQ); BEGIN_INNER; }
YY_BREAK
case 48:
YY_RULE_SETUP
#line 443 "sparql_l.l"
{ yymore(); SET_INNER_BEGIN(SPARQL_DDDQ); BEGIN_INNER; }
YY_BREAK
case 49:
YY_RULE_SETUP
#line 444 "sparql_l.l"
{ yylval->box = spar_unescape_strliteral (yyextra, yytext, 3, SPAR_STRLITERAL_SPARQL_STRING); BEGIN_OUTER; return SPARQL_STRING; }
YY_BREAK
case 50:
YY_RULE_SETUP
#line 445 "sparql_l.l"
{ yylval->box = spar_unescape_strliteral (yyextra, yytext, 3, SPAR_STRLITERAL_SPARQL_STRING); BEGIN_OUTER; return SPARQL_STRING; }
YY_BREAK
case 51:
/* rule 51 can match eol */
YY_RULE_SETUP
#line 446 "sparql_l.l"
{ yyextra->sparp_lexlineno++; yymore(); }
YY_BREAK
case 52:
/* rule 52 can match eol */
YY_RULE_SETUP
#line 447 "sparql_l.l"
{ yyextra->sparp_lexlineno++; yymore(); }
YY_BREAK
case 53:
YY_RULE_SETUP
#line 448 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 54:
YY_RULE_SETUP
#line 449 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 55:
YY_RULE_SETUP
#line 450 "sparql_l.l"
{ sparyyerror ("Bad escape sequence in a long single-quoted string"); }
YY_BREAK
case 56:
YY_RULE_SETUP
#line 451 "sparql_l.l"
{ sparyyerror ("Bad escape sequence in a long double-quoted string"); }
YY_BREAK
case 57:
YY_RULE_SETUP
#line 452 "sparql_l.l"
{ sparyyerror (t_box_sprintf (100, "Bad character '%c' (0x%x) in a long single-quoted string", yytext[0], (unsigned int)((unsigned char)(yytext[0])))); }
YY_BREAK
case 58:
YY_RULE_SETUP
#line 453 "sparql_l.l"
{ sparyyerror (t_box_sprintf (100, "Bad character '%c' (0x%x) in a long double-quoted string", yytext[0], (unsigned int)((unsigned char)(yytext[0])))); }
YY_BREAK
case YY_STATE_EOF(SPARQL_SSSQ):
#line 454 "sparql_l.l"
{ sparyyerror ("Unterminated long single-quoted string"); }
YY_BREAK
case YY_STATE_EOF(SPARQL_DDDQ):
#line 455 "sparql_l.l"
{ sparyyerror ("Unterminated long double-quoted string"); }
YY_BREAK
case 59:
YY_RULE_SETUP
#line 458 "sparql_l.l"
{ yymore(); SET_INNER_BEGIN(SPARQL_SQ); BEGIN_INNER; }
YY_BREAK
case 60:
YY_RULE_SETUP
#line 459 "sparql_l.l"
{ yymore(); SET_INNER_BEGIN(SPARQL_DQ); BEGIN_INNER; }
YY_BREAK
case 61:
YY_RULE_SETUP
#line 460 "sparql_l.l"
{ yylval->box = spar_unescape_strliteral (yyextra, yytext, 1, SPAR_STRLITERAL_SPARQL_STRING); BEGIN_OUTER; return SPARQL_STRING; }
YY_BREAK
case 62:
YY_RULE_SETUP
#line 461 "sparql_l.l"
{ yylval->box = spar_unescape_strliteral (yyextra, yytext, 1, SPAR_STRLITERAL_SPARQL_STRING); BEGIN_OUTER; return SPARQL_STRING; }
YY_BREAK
case 63:
/* rule 63 can match eol */
YY_RULE_SETUP
#line 462 "sparql_l.l"
{ sparyyerror ("End-of-line in a short single-quoted string"); yymore(); }
YY_BREAK
case 64:
/* rule 64 can match eol */
YY_RULE_SETUP
#line 463 "sparql_l.l"
{ sparyyerror ("End-of-line in a short double-quoted string"); yymore(); }
YY_BREAK
case 65:
YY_RULE_SETUP
#line 464 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 66:
YY_RULE_SETUP
#line 465 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 67:
YY_RULE_SETUP
#line 466 "sparql_l.l"
{ sparyyerror ("Bad escape sequence in a short single-quoted string"); }
YY_BREAK
case 68:
YY_RULE_SETUP
#line 467 "sparql_l.l"
{ sparyyerror ("Bad escape sequence in a short double-quoted string"); }
YY_BREAK
case YY_STATE_EOF(SPARQL_SQ):
#line 468 "sparql_l.l"
{ sparyyerror ("Unterminated short single-quoted string"); }
YY_BREAK
case YY_STATE_EOF(SPARQL_DQ):
#line 469 "sparql_l.l"
{ sparyyerror ("Unterminated short double-quoted string"); }
YY_BREAK
/* Whitespace after COUNT keyword */
case 69:
YY_RULE_SETUP
#line 473 "sparql_l.l"
{ BEGIN SPARQL; TOKPAR_OPEN (COUNT_LPAR, ')', GET_CURRENT_BEGIN) }
YY_BREAK
case 70:
YY_RULE_SETUP
#line 474 "sparql_l.l"
{ BEGIN SPARQL; return COUNT_DISTINCT_L; }
YY_BREAK
case YY_STATE_EOF(SPARQL_AFTER_COUNT):
#line 475 "sparql_l.l"
{ sparyyerror ("Unexpected end of SPARQL expression after COUNT keyword"); }
YY_BREAK
/* Whitespace after IDENTIFIED keyword */
case 71:
YY_RULE_SETUP
#line 479 "sparql_l.l"
{ BEGIN SPARQL; return BY_L; }
YY_BREAK
case YY_STATE_EOF(SPARQL_AFTER_IDENTIFIED):
#line 480 "sparql_l.l"
{ sparyyerror ("Unexpected end of SPARQL expression after IDENTIFIED keyword"); }
YY_BREAK
/* Whitespace after NOT keyword */
case 72:
YY_RULE_SETUP
#line 483 "sparql_l.l"
{ BEGIN SPARQL; return NOT_EXISTS_L; }
YY_BREAK
case 73:
YY_RULE_SETUP
#line 484 "sparql_l.l"
{ BEGIN SPARQL; return NOT_FROM_L; }
YY_BREAK
case 74:
YY_RULE_SETUP
#line 485 "sparql_l.l"
{ BEGIN SPARQL; return NOT_IN_L; }
YY_BREAK
case 75:
YY_RULE_SETUP
#line 486 "sparql_l.l"
{ BEGIN SPARQL; return NOT_NULL_L; }
YY_BREAK
case 76:
YY_RULE_SETUP
#line 487 "sparql_l.l"
{ BEGIN SPARQL; return NOT_USING_L; }
YY_BREAK
case YY_STATE_EOF(SPARQL_AFTER_NOT):
#line 488 "sparql_l.l"
{ sparyyerror ("Unexpected end of SPARQL expression after NOT keyword"); }
YY_BREAK
/* SQL fragments */
case 77:
YY_RULE_SETUP
#line 492 "sparql_l.l"
{ BEGIN SPARQL; TOKPAR_OPEN (_LBRA, '}', GET_CURRENT_BEGIN) }
YY_BREAK
case 78:
YY_RULE_SETUP
#line 493 "sparql_l.l"
{ BEGIN SPARQL; TOKPAR_OPEN (_LPAR, ')', SPARQL_SQL_FRAGMENT) }
YY_BREAK
case 79:
YY_RULE_SETUP
#line 494 "sparql_l.l"
{ SET_INNER_BEGIN(SPARQL_SSSQ); BEGIN_INNER; }
YY_BREAK
case 80:
YY_RULE_SETUP
#line 495 "sparql_l.l"
{ SET_INNER_BEGIN(SPARQL_DDDQ); BEGIN_INNER; }
YY_BREAK
case 81:
YY_RULE_SETUP
#line 496 "sparql_l.l"
{ SET_INNER_BEGIN(SPARQL_SQ); BEGIN_INNER; }
YY_BREAK
case 82:
YY_RULE_SETUP
#line 497 "sparql_l.l"
{ SET_INNER_BEGIN(SPARQL_DQ); BEGIN_INNER; }
YY_BREAK
case YY_STATE_EOF(SPARQL_AFTER_WHERE):
#line 498 "sparql_l.l"
{ sparyyerror ("Unexpected end of SPARQL expression after WHERE keyword"); }
YY_BREAK
case 83:
/* rule 83 can match eol */
YY_RULE_SETUP
#line 500 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 84:
YY_RULE_SETUP
#line 502 "sparql_l.l"
{ TOKPAR_FAKE_OPEN('}', SPARQL_SQL_FRAGMENT); yymore(); }
YY_BREAK
case 85:
YY_RULE_SETUP
#line 503 "sparql_l.l"
{ TOKPAR_FAKE_CLOSE('}'); yymore(); }
YY_BREAK
case 86:
YY_RULE_SETUP
#line 504 "sparql_l.l"
{ TOKPAR_FAKE_OPEN(')', SPARQL_SQL_FRAGMENT); yymore(); }
YY_BREAK
case 87:
YY_RULE_SETUP
#line 505 "sparql_l.l"
{
TOKPAR_FAKE_CLOSE(')');
if (SPARQL == GET_CURRENT_BEGIN)
{
yylval->box = t_box_dv_short_nchars (yytext, yyleng-1);
return SPARQL_SQLTEXT;
}
else
yymore();
}
YY_BREAK
case 88:
/* rule 88 can match eol */
YY_RULE_SETUP
#line 516 "sparql_l.l"
{ yyextra->sparp_lexlineno++; yymore(); }
YY_BREAK
case 89:
YY_RULE_SETUP
#line 517 "sparql_l.l"
{ sparyyerror ("Unterminated comment in SQL fragment after WHERE keyword"); }
YY_BREAK
case 90:
YY_RULE_SETUP
#line 518 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 91:
YY_RULE_SETUP
#line 519 "sparql_l.l"
{ BEGIN SPARQL_SQL_SQSTRING; yymore(); }
YY_BREAK
case 92:
YY_RULE_SETUP
#line 520 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 93:
YY_RULE_SETUP
#line 521 "sparql_l.l"
{ sparyyerror ("Unterminated double-quoted identifier in SQL fragment after WHERE keyword"); }
YY_BREAK
case 94:
YY_RULE_SETUP
#line 523 "sparql_l.l"
{ BEGIN SPARQL_SQL_FRAGMENT; yymore(); }
YY_BREAK
case 95:
/* rule 95 can match eol */
YY_RULE_SETUP
#line 524 "sparql_l.l"
{ yyextra->sparp_lexlineno++; yymore(); }
YY_BREAK
case 96:
/* rule 96 can match eol */
YY_RULE_SETUP
#line 525 "sparql_l.l"
{ yyextra->sparp_lexlineno++; yymore(); }
YY_BREAK
case 97:
YY_RULE_SETUP
#line 526 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 98:
YY_RULE_SETUP
#line 527 "sparql_l.l"
{ yymore(); }
YY_BREAK
case 99:
YY_RULE_SETUP
#line 528 "sparql_l.l"
{ yymore(); }
YY_BREAK
case YY_STATE_EOF(SPARQL_SQL_SQSTRING):
#line 529 "sparql_l.l"
{ sparyyerror ("Unterminated single-quoted string in SQL fragment after WHERE keyword"); }
YY_BREAK
/* Whitespace and comments */
case 100:
/* rule 100 can match eol */
YY_RULE_SETUP
#line 533 "sparql_l.l"
{ yyextra->sparp_lexlineno++; }
YY_BREAK
case 101:
YY_RULE_SETUP
#line 534 "sparql_l.l"
{ }
YY_BREAK
case 102:
YY_RULE_SETUP
#line 535 "sparql_l.l"
{ }
YY_BREAK
case 103:
YY_RULE_SETUP
#line 537 "sparql_l.l"
{ BEGIN (SPARQL_SQL_COMMENT); yymore(); }
YY_BREAK
case YY_STATE_EOF(SPARQL_SQL_FRAGMENT):
#line 538 "sparql_l.l"
{ sparyyerror ("Unterminated SQL fragment after WHERE keyword"); }
YY_BREAK
case 104:
YY_RULE_SETUP
#line 540 "sparql_l.l"
{ sparyyerror ("Nested C style comments not supported"); }
YY_BREAK
case 105:
YY_RULE_SETUP
#line 541 "sparql_l.l"
{ BEGIN (SPARQL_SQL_FRAGMENT); yymore(); }
YY_BREAK
case 106:
YY_RULE_SETUP
#line 542 "sparql_l.l"
{ yymore(); }
YY_BREAK
/* Traps; these rules should be latest rules in the file. */
case 107:
YY_RULE_SETUP
#line 546 "sparql_l.l"
{ sparyyerror ("Only '(' and DISTINCT are allowed after COUNT keyword in SPARQL expression"); }
YY_BREAK
case 108:
YY_RULE_SETUP
#line 547 "sparql_l.l"
{ sparyyerror ("Ill formed 'IDENTIFIED BY' term"); }
YY_BREAK
case 109:
YY_RULE_SETUP
#line 548 "sparql_l.l"
{ sparyyerror ("Only EXISTS, FROM, IN, NULL and USING are allowed after NOT keyword in SPARQL expression"); }
YY_BREAK
case 110:
YY_RULE_SETUP
#line 549 "sparql_l.l"
{ sparyyerror ("Only '{', '(' and a string literal are allowed after WHERE or SQLQUERY keyword in SPARQL expression"); }
YY_BREAK
case 111:
YY_RULE_SETUP
#line 550 "sparql_l.l"
{ sparyyerror (t_box_sprintf (100, "Bad character '%c' (0x%x) in SPARQL expression", yytext[0], (unsigned int)((unsigned char)(yytext[0])))); }
YY_BREAK
case 112:
YY_RULE_SETUP
#line 552 "sparql_l.l"
ECHO;
YY_BREAK
#line 2613 "sparql_l.c"
case YY_STATE_EOF(INITIAL):
case YY_STATE_EOF(SPARQL):
case YY_STATE_EOF(SPARQL_SQL_COMMENT):
case YY_STATE_EOF(UNREACHEABLE):
yyterminate();
case YY_END_OF_BUFFER:
{
/* Amount of text matched not including the EOB char. */
int yy_amount_of_matched_text = (int) (yy_cp - yyg->yytext_ptr) - 1;
/* Undo the effects of YY_DO_BEFORE_ACTION. */
*yy_cp = yyg->yy_hold_char;
YY_RESTORE_YY_MORE_OFFSET
if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
{
/* We're scanning a new file or input source. It's
* possible that this happened because the user
* just pointed yyin at a new source and called
* sparyylex(). If so, then we have to assure
* consistency between YY_CURRENT_BUFFER and our
* globals. Here is the right place to do so, because
* this is the first action (other than possibly a
* back-up) that will match for the new input source.
*/
yyg->yy_n_chars = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
}
/* Note that here we test for yy_c_buf_p "<=" to the position
* of the first EOB in the buffer, since yy_c_buf_p will
* already have been incremented past the NUL character
* (since all states make transitions on EOB to the
* end-of-buffer state). Contrast this with the test
* in input().
*/
if ( yyg->yy_c_buf_p <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[yyg->yy_n_chars] )
{ /* This was really a NUL. */
yy_state_type yy_next_state;
yyg->yy_c_buf_p = yyg->yytext_ptr + yy_amount_of_matched_text;
yy_current_state = yy_get_previous_state( yyscanner );
/* Okay, we're now positioned to make the NUL
* transition. We couldn't have
* yy_get_previous_state() go ahead and do it
* for us because it doesn't know how to deal
* with the possibility of jamming (and we don't
* want to build jamming into it because then it
* will run more slowly).
*/
yy_next_state = yy_try_NUL_trans( yy_current_state , yyscanner);
yy_bp = yyg->yytext_ptr + YY_MORE_ADJ;
if ( yy_next_state )
{
/* Consume the NUL. */
yy_cp = ++yyg->yy_c_buf_p;
yy_current_state = yy_next_state;
goto yy_match;
}
else
{
yy_cp = yyg->yy_last_accepting_cpos;
yy_current_state = yyg->yy_last_accepting_state;
goto yy_find_action;
}
}
else switch ( yy_get_next_buffer( yyscanner ) )
{
case EOB_ACT_END_OF_FILE:
{
yyg->yy_did_buffer_switch_on_eof = 0;
if ( sparyywrap(yyscanner ) )
{
/* Note: because we've taken care in
* yy_get_next_buffer() to have set up
* yytext, we can now set up
* yy_c_buf_p so that if some total
* hoser (like flex itself) wants to
* call the scanner after we return the
* YY_NULL, it'll still work - another
* YY_NULL will get returned.
*/
yyg->yy_c_buf_p = yyg->yytext_ptr + YY_MORE_ADJ;
yy_act = YY_STATE_EOF(YY_START);
goto do_action;
}
else
{
if ( ! yyg->yy_did_buffer_switch_on_eof )
YY_NEW_FILE;
}
break;
}
case EOB_ACT_CONTINUE_SCAN:
yyg->yy_c_buf_p =
yyg->yytext_ptr + yy_amount_of_matched_text;
yy_current_state = yy_get_previous_state( yyscanner );
yy_cp = yyg->yy_c_buf_p;
yy_bp = yyg->yytext_ptr + YY_MORE_ADJ;
goto yy_match;
case EOB_ACT_LAST_MATCH:
yyg->yy_c_buf_p =
&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[yyg->yy_n_chars];
yy_current_state = yy_get_previous_state( yyscanner );
yy_cp = yyg->yy_c_buf_p;
yy_bp = yyg->yytext_ptr + YY_MORE_ADJ;
goto yy_find_action;
}
break;
}
default:
YY_FATAL_ERROR(
"fatal flex scanner internal error--no action found" );
} /* end of action switch */
} /* end of scanning one token */
} /* end of sparyylex */
/* yy_get_next_buffer - try to read in a new buffer
*
* Returns a code representing an action:
* EOB_ACT_LAST_MATCH -
* EOB_ACT_CONTINUE_SCAN - continue scanning from current position
* EOB_ACT_END_OF_FILE - end of file
*/
static int yy_get_next_buffer (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
register char *source = yyg->yytext_ptr;
register int number_to_move, i;
int ret_val;
if ( yyg->yy_c_buf_p > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[yyg->yy_n_chars + 1] )
YY_FATAL_ERROR(
"fatal flex scanner internal error--end of buffer missed" );
if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
{ /* Don't try to fill the buffer, so this is an EOF. */
if ( yyg->yy_c_buf_p - yyg->yytext_ptr - YY_MORE_ADJ == 1 )
{
/* We matched a single character, the EOB, so
* treat this as a final EOF.
*/
return EOB_ACT_END_OF_FILE;
}
else
{
/* We matched some text prior to the EOB, first
* process it.
*/
return EOB_ACT_LAST_MATCH;
}
}
/* Try to read more data. */
/* First move last chars to start of buffer. */
number_to_move = (int) (yyg->yy_c_buf_p - yyg->yytext_ptr) - 1;
for ( i = 0; i < number_to_move; ++i )
*(dest++) = *(source++);
if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
/* don't do the read, it's not guaranteed to return an EOF,
* just force an EOF
*/
YY_CURRENT_BUFFER_LVALUE->yy_n_chars = yyg->yy_n_chars = 0;
else
{
yy_size_t num_to_read =
YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
while ( num_to_read <= 0 )
{ /* Not enough room in the buffer - grow it. */
/* just a shorter name for the current buffer */
YY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE;
int yy_c_buf_p_offset =
(int) (yyg->yy_c_buf_p - b->yy_ch_buf);
if ( b->yy_is_our_buffer )
{
yy_size_t new_size = b->yy_buf_size * 2;
if ( new_size <= 0 )
b->yy_buf_size += b->yy_buf_size / 8;
else
b->yy_buf_size *= 2;
b->yy_ch_buf = (char *)
/* Include room in for 2 EOB chars. */
sparyyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 ,yyscanner );
}
else
/* Can't grow it, we don't own it. */
b->yy_ch_buf = 0;
if ( ! b->yy_ch_buf )
YY_FATAL_ERROR(
"fatal error - scanner input buffer overflow" );
yyg->yy_c_buf_p = &b->yy_ch_buf[yy_c_buf_p_offset];
num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
number_to_move - 1;
}
if ( num_to_read > YY_READ_BUF_SIZE )
num_to_read = YY_READ_BUF_SIZE;
/* Read in more data. */
YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
yyg->yy_n_chars, num_to_read );
YY_CURRENT_BUFFER_LVALUE->yy_n_chars = yyg->yy_n_chars;
}
if ( yyg->yy_n_chars == 0 )
{
if ( number_to_move == YY_MORE_ADJ )
{
ret_val = EOB_ACT_END_OF_FILE;
sparyyrestart(yyin ,yyscanner);
}
else
{
ret_val = EOB_ACT_LAST_MATCH;
YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
YY_BUFFER_EOF_PENDING;
}
}
else
ret_val = EOB_ACT_CONTINUE_SCAN;
if ((yy_size_t) (yyg->yy_n_chars + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
/* Extend the array by 50%, plus the number we really need. */
yy_size_t new_size = yyg->yy_n_chars + number_to_move + (yyg->yy_n_chars >> 1);
YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) sparyyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size ,yyscanner );
if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
}
yyg->yy_n_chars += number_to_move;
YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[yyg->yy_n_chars] = YY_END_OF_BUFFER_CHAR;
YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[yyg->yy_n_chars + 1] = YY_END_OF_BUFFER_CHAR;
yyg->yytext_ptr = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
return ret_val;
}
/* yy_get_previous_state - get the state just before the EOB char was reached */
static yy_state_type yy_get_previous_state (yyscan_t yyscanner)
{
register yy_state_type yy_current_state;
register char *yy_cp;
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
yy_current_state = yyg->yy_start;
for ( yy_cp = yyg->yytext_ptr + YY_MORE_ADJ; yy_cp < yyg->yy_c_buf_p; ++yy_cp )
{
register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 78);
if ( yy_accept[yy_current_state] )
{
yyg->yy_last_accepting_state = yy_current_state;
yyg->yy_last_accepting_cpos = yy_cp;
}
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
if ( yy_current_state >= 454 )
yy_c = yy_meta[(unsigned int) yy_c];
}
yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
}
return yy_current_state;
}
/* yy_try_NUL_trans - try to make a transition on the NUL character
*
* synopsis
* next_state = yy_try_NUL_trans( current_state );
*/
static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state , yyscan_t yyscanner)
{
register int yy_is_jam;
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner; /* This var may be unused depending upon options. */
register char *yy_cp = yyg->yy_c_buf_p;
register YY_CHAR yy_c = 78;
if ( yy_accept[yy_current_state] )
{
yyg->yy_last_accepting_state = yy_current_state;
yyg->yy_last_accepting_cpos = yy_cp;
}
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
if ( yy_current_state >= 454 )
yy_c = yy_meta[(unsigned int) yy_c];
}
yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
yy_is_jam = (yy_current_state == 453);
(void)yyg;
return yy_is_jam ? 0 : yy_current_state;
}
#ifndef YY_NO_INPUT
#ifdef __cplusplus
static int yyinput (yyscan_t yyscanner)
#else
static int input (yyscan_t yyscanner)
#endif
{
int c;
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
*yyg->yy_c_buf_p = yyg->yy_hold_char;
if ( *yyg->yy_c_buf_p == YY_END_OF_BUFFER_CHAR )
{
/* yy_c_buf_p now points to the character we want to return.
* If this occurs *before* the EOB characters, then it's a
* valid NUL; if not, then we've hit the end of the buffer.
*/
if ( yyg->yy_c_buf_p < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[yyg->yy_n_chars] )
/* This was really a NUL. */
*yyg->yy_c_buf_p = '\0';
else
{ /* need more input */
yy_size_t offset = yyg->yy_c_buf_p - yyg->yytext_ptr;
++yyg->yy_c_buf_p;
switch ( yy_get_next_buffer( yyscanner ) )
{
case EOB_ACT_LAST_MATCH:
/* This happens because yy_g_n_b()
* sees that we've accumulated a
* token and flags that we need to
* try matching the token before
* proceeding. But for input(),
* there's no matching to consider.
* So convert the EOB_ACT_LAST_MATCH
* to EOB_ACT_END_OF_FILE.
*/
/* Reset buffer status. */
sparyyrestart(yyin ,yyscanner);
/*FALLTHROUGH*/
case EOB_ACT_END_OF_FILE:
{
if ( sparyywrap(yyscanner ) )
return EOF;
if ( ! yyg->yy_did_buffer_switch_on_eof )
YY_NEW_FILE;
#ifdef __cplusplus
return yyinput(yyscanner);
#else
return input(yyscanner);
#endif
}
case EOB_ACT_CONTINUE_SCAN:
yyg->yy_c_buf_p = yyg->yytext_ptr + offset;
break;
}
}
}
c = *(unsigned char *) yyg->yy_c_buf_p; /* cast for 8-bit char's */
*yyg->yy_c_buf_p = '\0'; /* preserve yytext */
yyg->yy_hold_char = *++yyg->yy_c_buf_p;
return c;
}
#endif /* ifndef YY_NO_INPUT */
/** Immediately switch to a different input stream.
* @param input_file A readable stream.
* @param yyscanner The scanner object.
* @note This function does not reset the start condition to @c INITIAL .
*/
void sparyyrestart (FILE * input_file , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
if ( ! YY_CURRENT_BUFFER ){
sparyyensure_buffer_stack (yyscanner);
YY_CURRENT_BUFFER_LVALUE =
sparyy_create_buffer(yyin,YY_BUF_SIZE ,yyscanner);
}
sparyy_init_buffer(YY_CURRENT_BUFFER,input_file ,yyscanner);
sparyy_load_buffer_state(yyscanner );
}
/** Switch to a different input buffer.
* @param new_buffer The new input buffer.
* @param yyscanner The scanner object.
*/
void sparyy_switch_to_buffer (YY_BUFFER_STATE new_buffer , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
/* TODO. We should be able to replace this entire function body
* with
* sparyypop_buffer_state();
* sparyypush_buffer_state(new_buffer);
*/
sparyyensure_buffer_stack (yyscanner);
if ( YY_CURRENT_BUFFER == new_buffer )
return;
if ( YY_CURRENT_BUFFER )
{
/* Flush out information for old buffer. */
*yyg->yy_c_buf_p = yyg->yy_hold_char;
YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = yyg->yy_c_buf_p;
YY_CURRENT_BUFFER_LVALUE->yy_n_chars = yyg->yy_n_chars;
}
YY_CURRENT_BUFFER_LVALUE = new_buffer;
sparyy_load_buffer_state(yyscanner );
/* We don't actually know whether we did this switch during
* EOF (sparyywrap()) processing, but the only time this flag
* is looked at is after sparyywrap() is called, so it's safe
* to go ahead and always set it.
*/
yyg->yy_did_buffer_switch_on_eof = 1;
}
static void sparyy_load_buffer_state (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
yyg->yy_n_chars = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
yyg->yytext_ptr = yyg->yy_c_buf_p = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
yyg->yy_hold_char = *yyg->yy_c_buf_p;
}
/** Allocate and initialize an input buffer state.
* @param file A readable stream.
* @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
* @param yyscanner The scanner object.
* @return the allocated buffer state.
*/
YY_BUFFER_STATE sparyy_create_buffer (FILE * file, int size , yyscan_t yyscanner)
{
YY_BUFFER_STATE b;
b = (YY_BUFFER_STATE) sparyyalloc(sizeof( struct yy_buffer_state ) ,yyscanner );
if ( ! b )
YY_FATAL_ERROR( "out of dynamic memory in sparyy_create_buffer()" );
b->yy_buf_size = size;
/* yy_ch_buf has to be 2 characters longer than the size given because
* we need to put in 2 end-of-buffer characters.
*/
b->yy_ch_buf = (char *) sparyyalloc(b->yy_buf_size + 2 ,yyscanner );
if ( ! b->yy_ch_buf )
YY_FATAL_ERROR( "out of dynamic memory in sparyy_create_buffer()" );
b->yy_is_our_buffer = 1;
sparyy_init_buffer(b,file ,yyscanner);
return b;
}
/** Destroy the buffer.
* @param b a buffer created with sparyy_create_buffer()
* @param yyscanner The scanner object.
*/
void sparyy_delete_buffer (YY_BUFFER_STATE b , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
if ( ! b )
return;
if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
if ( b->yy_is_our_buffer )
sparyyfree((void *) b->yy_ch_buf ,yyscanner );
sparyyfree((void *) b ,yyscanner );
}
/* Initializes or reinitializes a buffer.
* This function is sometimes called more than once on the same buffer,
* such as during a sparyyrestart() or at EOF.
*/
static void sparyy_init_buffer (YY_BUFFER_STATE b, FILE * file , yyscan_t yyscanner)
{
int oerrno = errno;
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
sparyy_flush_buffer(b ,yyscanner);
b->yy_input_file = file;
b->yy_fill_buffer = 1;
/* If b is the current buffer, then sparyy_init_buffer was _probably_
* called from sparyyrestart() or through yy_get_next_buffer.
* In that case, we don't want to reset the lineno or column.
*/
if (b != YY_CURRENT_BUFFER){
b->yy_bs_lineno = 1;
b->yy_bs_column = 0;
}
b->yy_is_interactive = 0;
errno = oerrno;
}
/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
* @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
* @param yyscanner The scanner object.
*/
void sparyy_flush_buffer (YY_BUFFER_STATE b , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
if ( ! b )
return;
b->yy_n_chars = 0;
/* We always need two end-of-buffer characters. The first causes
* a transition to the end-of-buffer state. The second causes
* a jam in that state.
*/
b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
b->yy_buf_pos = &b->yy_ch_buf[0];
b->yy_at_bol = 1;
b->yy_buffer_status = YY_BUFFER_NEW;
if ( b == YY_CURRENT_BUFFER )
sparyy_load_buffer_state(yyscanner );
}
/** Pushes the new state onto the stack. The new state becomes
* the current state. This function will allocate the stack
* if necessary.
* @param new_buffer The new state.
* @param yyscanner The scanner object.
*/
void sparyypush_buffer_state (YY_BUFFER_STATE new_buffer , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
if (new_buffer == NULL)
return;
sparyyensure_buffer_stack(yyscanner);
/* This block is copied from sparyy_switch_to_buffer. */
if ( YY_CURRENT_BUFFER )
{
/* Flush out information for old buffer. */
*yyg->yy_c_buf_p = yyg->yy_hold_char;
YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = yyg->yy_c_buf_p;
YY_CURRENT_BUFFER_LVALUE->yy_n_chars = yyg->yy_n_chars;
}
/* Only push if top exists. Otherwise, replace top. */
if (YY_CURRENT_BUFFER)
yyg->yy_buffer_stack_top++;
YY_CURRENT_BUFFER_LVALUE = new_buffer;
/* copied from sparyy_switch_to_buffer. */
sparyy_load_buffer_state(yyscanner );
yyg->yy_did_buffer_switch_on_eof = 1;
}
/** Removes and deletes the top of the stack, if present.
* The next element becomes the new top.
* @param yyscanner The scanner object.
*/
void sparyypop_buffer_state (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
if (!YY_CURRENT_BUFFER)
return;
sparyy_delete_buffer(YY_CURRENT_BUFFER ,yyscanner);
YY_CURRENT_BUFFER_LVALUE = NULL;
if (yyg->yy_buffer_stack_top > 0)
--yyg->yy_buffer_stack_top;
if (YY_CURRENT_BUFFER) {
sparyy_load_buffer_state(yyscanner );
yyg->yy_did_buffer_switch_on_eof = 1;
}
}
/* Allocates the stack if it does not exist.
* Guarantees space for at least one push.
*/
static void sparyyensure_buffer_stack (yyscan_t yyscanner)
{
yy_size_t num_to_alloc;
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
if (!yyg->yy_buffer_stack) {
/* First allocation is just for 2 elements, since we don't know if this
* scanner will even need a stack. We use 2 instead of 1 to avoid an
* immediate realloc on the next call.
*/
num_to_alloc = 1;
yyg->yy_buffer_stack = (struct yy_buffer_state**)sparyyalloc
(num_to_alloc * sizeof(struct yy_buffer_state*)
, yyscanner);
if ( ! yyg->yy_buffer_stack )
YY_FATAL_ERROR( "out of dynamic memory in sparyyensure_buffer_stack()" );
memset(yyg->yy_buffer_stack, 0, num_to_alloc * sizeof(struct yy_buffer_state*));
yyg->yy_buffer_stack_max = num_to_alloc;
yyg->yy_buffer_stack_top = 0;
return;
}
if (yyg->yy_buffer_stack_top >= (yyg->yy_buffer_stack_max) - 1){
/* Increase the buffer to prepare for a possible push. */
int grow_size = 8 /* arbitrary grow size */;
num_to_alloc = yyg->yy_buffer_stack_max + grow_size;
yyg->yy_buffer_stack = (struct yy_buffer_state**)sparyyrealloc
(yyg->yy_buffer_stack,
num_to_alloc * sizeof(struct yy_buffer_state*)
, yyscanner);
if ( ! yyg->yy_buffer_stack )
YY_FATAL_ERROR( "out of dynamic memory in sparyyensure_buffer_stack()" );
/* zero only the new slots.*/
memset(yyg->yy_buffer_stack + yyg->yy_buffer_stack_max, 0, grow_size * sizeof(struct yy_buffer_state*));
yyg->yy_buffer_stack_max = num_to_alloc;
}
}
/** Setup the input buffer state to scan directly from a user-specified character buffer.
* @param base the character buffer
* @param size the size in bytes of the character buffer
* @param yyscanner The scanner object.
* @return the newly allocated buffer state object.
*/
YY_BUFFER_STATE sparyy_scan_buffer (char * base, yy_size_t size , yyscan_t yyscanner)
{
YY_BUFFER_STATE b;
if ( size < 2 ||
base[size-2] != YY_END_OF_BUFFER_CHAR ||
base[size-1] != YY_END_OF_BUFFER_CHAR )
/* They forgot to leave room for the EOB's. */
return 0;
b = (YY_BUFFER_STATE) sparyyalloc(sizeof( struct yy_buffer_state ) ,yyscanner );
if ( ! b )
YY_FATAL_ERROR( "out of dynamic memory in sparyy_scan_buffer()" );
b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */
b->yy_buf_pos = b->yy_ch_buf = base;
b->yy_is_our_buffer = 0;
b->yy_input_file = 0;
b->yy_n_chars = b->yy_buf_size;
b->yy_is_interactive = 0;
b->yy_at_bol = 1;
b->yy_fill_buffer = 0;
b->yy_buffer_status = YY_BUFFER_NEW;
sparyy_switch_to_buffer(b ,yyscanner );
return b;
}
/** Setup the input buffer state to scan a string. The next call to sparyylex() will
* scan from a @e copy of @a str.
* @param yystr a NUL-terminated string to scan
* @param yyscanner The scanner object.
* @return the newly allocated buffer state object.
* @note If you want to scan bytes that may contain NUL values, then use
* sparyy_scan_bytes() instead.
*/
YY_BUFFER_STATE sparyy_scan_string (yyconst char * yystr , yyscan_t yyscanner)
{
return sparyy_scan_bytes(yystr,strlen(yystr) ,yyscanner);
}
/** Setup the input buffer state to scan the given bytes. The next call to sparyylex() will
* scan from a @e copy of @a bytes.
* @param yybytes the byte buffer to scan
* @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes.
* @param yyscanner The scanner object.
* @return the newly allocated buffer state object.
*/
YY_BUFFER_STATE sparyy_scan_bytes (yyconst char * yybytes, yy_size_t _yybytes_len , yyscan_t yyscanner)
{
YY_BUFFER_STATE b;
char *buf;
yy_size_t n;
yy_size_t i;
/* Get memory for full buffer, including space for trailing EOB's. */
n = _yybytes_len + 2;
buf = (char *) sparyyalloc(n ,yyscanner );
if ( ! buf )
YY_FATAL_ERROR( "out of dynamic memory in sparyy_scan_bytes()" );
for ( i = 0; i < _yybytes_len; ++i )
buf[i] = yybytes[i];
buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
b = sparyy_scan_buffer(buf,n ,yyscanner);
if ( ! b )
YY_FATAL_ERROR( "bad buffer in sparyy_scan_bytes()" );
/* It's okay to grow etc. this buffer, and we should throw it
* away when we're done.
*/
b->yy_is_our_buffer = 1;
return b;
}
#ifndef YY_EXIT_FAILURE
#define YY_EXIT_FAILURE 2
#endif
static void yy_fatal_error (yyconst char* msg , yyscan_t yyscanner)
{
(void) fprintf( stderr, "%s\n", msg );
exit( YY_EXIT_FAILURE );
}
/* Redefine yyless() so it works in section 3 code. */
#undef yyless
#define yyless(n) \
do \
{ \
/* Undo effects of setting up yytext. */ \
int yyless_macro_arg = (n); \
YY_LESS_LINENO(yyless_macro_arg);\
yytext[yyleng] = yyg->yy_hold_char; \
yyg->yy_c_buf_p = yytext + yyless_macro_arg; \
yyg->yy_hold_char = *yyg->yy_c_buf_p; \
*yyg->yy_c_buf_p = '\0'; \
yyleng = yyless_macro_arg; \
} \
while ( 0 )
/* Accessor methods (get/set functions) to struct members. */
/** Get the user-defined data for this scanner.
* @param yyscanner The scanner object.
*/
YY_EXTRA_TYPE sparyyget_extra (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
return yyextra;
}
/** Get the current line number.
* @param yyscanner The scanner object.
*/
int sparyyget_lineno (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
if (! YY_CURRENT_BUFFER)
return 0;
return yylineno;
}
/** Get the current column number.
* @param yyscanner The scanner object.
*/
int sparyyget_column (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
if (! YY_CURRENT_BUFFER)
return 0;
return yycolumn;
}
/** Get the input stream.
* @param yyscanner The scanner object.
*/
FILE *sparyyget_in (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
return yyin;
}
/** Get the output stream.
* @param yyscanner The scanner object.
*/
FILE *sparyyget_out (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
return yyout;
}
/** Get the length of the current token.
* @param yyscanner The scanner object.
*/
yy_size_t sparyyget_leng (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
return yyleng;
}
/** Get the current token.
* @param yyscanner The scanner object.
*/
char *sparyyget_text (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
return yytext;
}
/** Set the user-defined data. This data is never touched by the scanner.
* @param user_defined The data to be associated with this scanner.
* @param yyscanner The scanner object.
*/
void sparyyset_extra (YY_EXTRA_TYPE user_defined , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
yyextra = user_defined ;
}
/** Set the current line number.
* @param line_number
* @param yyscanner The scanner object.
*/
void sparyyset_lineno (int line_number , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
/* lineno is only valid if an input buffer exists. */
if (! YY_CURRENT_BUFFER )
YY_FATAL_ERROR( "sparyyset_lineno called with no buffer" );
yylineno = line_number;
}
/** Set the current column.
* @param line_number
* @param yyscanner The scanner object.
*/
void sparyyset_column (int column_no , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
/* column is only valid if an input buffer exists. */
if (! YY_CURRENT_BUFFER )
YY_FATAL_ERROR( "sparyyset_column called with no buffer" );
yycolumn = column_no;
}
/** Set the input stream. This does not discard the current
* input buffer.
* @param in_str A readable stream.
* @param yyscanner The scanner object.
* @see sparyy_switch_to_buffer
*/
void sparyyset_in (FILE * in_str , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
yyin = in_str ;
}
void sparyyset_out (FILE * out_str , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
yyout = out_str ;
}
int sparyyget_debug (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
return yy_flex_debug;
}
void sparyyset_debug (int bdebug , yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
yy_flex_debug = bdebug ;
}
/* Accessor methods for yylval and yylloc */
/* User-visible API */
/* sparyylex_init is special because it creates the scanner itself, so it is
* the ONLY reentrant function that doesn't take the scanner as the last argument.
* That's why we explicitly handle the declaration, instead of using our macros.
*/
int sparyylex_init(yyscan_t* ptr_yy_globals)
{
if (ptr_yy_globals == NULL){
errno = EINVAL;
return 1;
}
*ptr_yy_globals = (yyscan_t) sparyyalloc ( sizeof( struct yyguts_t ), NULL );
if (*ptr_yy_globals == NULL){
errno = ENOMEM;
return 1;
}
/* By setting to 0xAA, we expose bugs in yy_init_globals. Leave at 0x00 for releases. */
memset(*ptr_yy_globals,0x00,sizeof(struct yyguts_t));
return yy_init_globals ( *ptr_yy_globals );
}
/* sparyylex_init_extra has the same functionality as sparyylex_init, but follows the
* convention of taking the scanner as the last argument. Note however, that
* this is a *pointer* to a scanner, as it will be allocated by this call (and
* is the reason, too, why this function also must handle its own declaration).
* The user defined value in the first argument will be available to sparyyalloc in
* the yyextra field.
*/
int sparyylex_init_extra(YY_EXTRA_TYPE yy_user_defined,yyscan_t* ptr_yy_globals )
{
struct yyguts_t dummy_yyguts;
sparyyset_extra (yy_user_defined, &dummy_yyguts);
if (ptr_yy_globals == NULL){
errno = EINVAL;
return 1;
}
*ptr_yy_globals = (yyscan_t) sparyyalloc ( sizeof( struct yyguts_t ), &dummy_yyguts );
if (*ptr_yy_globals == NULL){
errno = ENOMEM;
return 1;
}
/* By setting to 0xAA, we expose bugs in
yy_init_globals. Leave at 0x00 for releases. */
memset(*ptr_yy_globals,0x00,sizeof(struct yyguts_t));
sparyyset_extra (yy_user_defined, *ptr_yy_globals);
return yy_init_globals ( *ptr_yy_globals );
}
static int yy_init_globals (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
/* Initialization is the same as for the non-reentrant scanner.
* This function is called from sparyylex_destroy(), so don't allocate here.
*/
yyg->yy_buffer_stack = 0;
yyg->yy_buffer_stack_top = 0;
yyg->yy_buffer_stack_max = 0;
yyg->yy_c_buf_p = (char *) 0;
yyg->yy_init = 0;
yyg->yy_start = 0;
yyg->yy_start_stack_ptr = 0;
yyg->yy_start_stack_depth = 0;
yyg->yy_start_stack = NULL;
/* Defined in main.c */
#ifdef YY_STDINIT
yyin = stdin;
yyout = stdout;
#else
yyin = (FILE *) 0;
yyout = (FILE *) 0;
#endif
/* For future reference: Set errno on error, since we are called by
* sparyylex_init()
*/
return 0;
}
/* sparyylex_destroy is for both reentrant and non-reentrant scanners. */
int sparyylex_destroy (yyscan_t yyscanner)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
/* Pop the buffer stack, destroying each element. */
while(YY_CURRENT_BUFFER){
sparyy_delete_buffer(YY_CURRENT_BUFFER ,yyscanner );
YY_CURRENT_BUFFER_LVALUE = NULL;
sparyypop_buffer_state(yyscanner);
}
/* Destroy the stack itself. */
sparyyfree(yyg->yy_buffer_stack ,yyscanner);
yyg->yy_buffer_stack = NULL;
/* Destroy the start condition stack. */
sparyyfree(yyg->yy_start_stack ,yyscanner );
yyg->yy_start_stack = NULL;
/* Reset the globals. This is important in a non-reentrant scanner so the next time
* sparyylex() is called, initialization will occur. */
yy_init_globals( yyscanner);
/* Destroy the main struct (reentrant only). */
sparyyfree ( yyscanner , yyscanner );
yyscanner = NULL;
return 0;
}
/*
* Internal utility routines.
*/
#ifndef yytext_ptr
static void yy_flex_strncpy (char* s1, yyconst char * s2, int n , yyscan_t yyscanner)
{
register int i;
for ( i = 0; i < n; ++i )
s1[i] = s2[i];
}
#endif
#ifdef YY_NEED_STRLEN
static int yy_flex_strlen (yyconst char * s , yyscan_t yyscanner)
{
register int n;
for ( n = 0; s[n]; ++n )
;
return n;
}
#endif
#define YYTABLES_NAME "yytables"
#line 552 "sparql_l.l"
void sparyyerror_if_long_qname (caddr_t box, const char *lex_type_descr, struct yyguts_t * yyg)
{
size_t boxlen = box_length (box);
char buf[100];
char *colon;
if (boxlen > MAX_XML_QNAME_LENGTH)
{
snprintf (buf, sizeof (buf), "%.90s is too long", lex_type_descr);
sparyyerror (buf);
}
colon = strrchr (box, ':');
if (NULL == colon)
{
if (boxlen > MAX_XML_LNAME_LENGTH)
{
snprintf (buf, sizeof (buf), "%.90s is too long", lex_type_descr);
sparyyerror (buf);
}
return;
}
if (colon+1-box > MAX_XML_LNAME_LENGTH)
{
snprintf (buf, sizeof (buf), "%.90s contains abnormally long namespace prefix", lex_type_descr);
sparyyerror (buf);
}
if (boxlen-(colon-box) > MAX_XML_LNAME_LENGTH)
{
snprintf (buf, sizeof (buf), "%.90s contains abnormally long 'local part' after the colon", lex_type_descr);
sparyyerror (buf);
}
}
int sparscn_NUMBER_int (YYSTYPE *yylval, struct yyguts_t * yyg)
{
if (('-' == yytext[0]) ? /* 012345678901234567890 */
((20 > yyleng) || ((20 == yyleng) && (0 >= strcmp (yytext, "-9223372036854775808"))))
: /* 01234567890123456789 */
((19 > yyleng) || ((19 == yyleng) && (0 >= strcmp (yytext, "9223372036854775807")))) )
{
yylval->box = t_box_num_nonull (atol (yytext));
return SPARQL_INTEGER;
}
else
{
numeric_t num = t_numeric_allocate ();
int rc = numeric_from_string (num, yytext);
yylval->box = (caddr_t) num;
if (NULL == yylval->box)
yylval->box = t_box_num_nonull (0);
if(rc != NUMERIC_STS_SUCCESS)
sparyyerror ("The absolute value of numeric constant is too large");
return SPARQL_INTEGER;
}
}
int sparscn_NUMBER_decimal (YYSTYPE *yylval, struct yyguts_t * yyg)
{
numeric_t num = t_numeric_allocate ();
int rc = numeric_from_string (num, yytext);
if (NUMERIC_STS_SUCCESS == rc)
{
if (NULL == (caddr_t) num)
yylval->box = (caddr_t)t_list (2, t_box_num_nonull (0), t_box_string (yytext));
yylval->box = (caddr_t)t_list (2, (caddr_t) num, t_box_string (yytext));
return SPARQL_DECIMAL;
}
yylval->box = (caddr_t)t_list (2, t_box_double (atof (yytext)), t_box_string (yytext));
return SPARQL_DECIMAL;
}
int
sparscn_NUMBER_double (YYSTYPE *yylval, struct yyguts_t * yyg)
{
yylval->box = (caddr_t)t_list (2, t_box_double (atof (yytext)), t_box_string (yytext));
return SPARQL_DOUBLE;
}
#define XP_LEXBUF_ELEMENTS 32
void
spar_fill_lexem_bufs (sparp_t *sparp)
{
yyscan_t scanner;
sparyylex_init_extra (sparp, &scanner);
sparp->sparp_text_len = box_length (sparp->sparp_text)-1;
sparp = sparp;
QR_RESET_CTX
{
int depth = 0;
int fill_ctr = 0;
spar_lexem_t *curr_lex;
#ifdef XPYYDEBUG
sparp->sparp_yydebug = 1;
#endif
sparp->sparp_lexlineno = 1;
sparp->sparp_lexdepth = 0;
sparp->sparp_curr_lexem_buf = (spar_lexem_t *)t_alloc_box (sizeof (spar_lexem_t) * XP_LEXBUF_ELEMENTS, DV_ARRAY_OF_POINTER);
/* Setting initial state and placing appropriate fake lexem to the lexbuffer */
curr_lex = sparp->sparp_curr_lexem_buf + fill_ctr;
curr_lex->sparl_lineno = sparp->sparp_lexlineno;
curr_lex->sparl_depth = depth;
curr_lex->sparl_raw_text = t_box_dv_short_string("");
/* BEGIN_NEW_CURRENT(SPARQL); */ ((struct yyguts_t *)scanner)->yy_start = 1 + 2 * (sparp->sparp_lexstates[sparp->sparp_lexdepth] = SPARQL);
curr_lex->sparl_lex_value = START_OF_SPARQL_TEXT;
sparp->sparp_total_lexems_parsed++;
fill_ctr++;
/* Loop over text */
for (;;)
{
curr_lex = sparp->sparp_curr_lexem_buf + fill_ctr;
curr_lex->sparl_lex_value = sparyylex((YYSTYPE *)(&(curr_lex->sparl_sem_value)), scanner);
curr_lex->sparl_lineno = sparp->sparp_lexlineno;
curr_lex->sparl_depth = depth;
if (0 == curr_lex->sparl_lex_value)
{
curr_lex->sparl_lex_value = END_OF_SPARQL_TEXT;
break;
}
depth = sparp->sparp_lexdepth;
curr_lex->sparl_raw_text = t_box_dv_short_nchars (sparyyget_text(scanner), sparyyget_leng (scanner));
#ifdef XPATHP_DEBUG
/* curr_lex->sparl_state = GET_CURRENT_BEGIN; */ curr_lex->sparl_state = sparp->sparp_lexstates[sparp->sparp_lexdepth];
#endif
fill_ctr++;
sparp->sparp_total_lexems_parsed++;
if (fill_ctr == XP_LEXBUF_ELEMENTS)
{
t_set_push (&(sparp->sparp_output_lexem_bufs), sparp->sparp_curr_lexem_buf);
sparp->sparp_curr_lexem_buf = (spar_lexem_t *)t_alloc_box (sizeof (spar_lexem_t) * XP_LEXBUF_ELEMENTS, DV_ARRAY_OF_POINTER);
fill_ctr = 0;
}
}
}
QR_RESET_CODE
{
du_thread_t *self = THREAD_CURRENT_THREAD;
sparp->sparp_sparqre->sparqre_catched_error = thr_get_error_code (self);
thr_set_error_code (self, NULL);
/*no POP_QR_RESET*/;
}
END_QR_RESET
sparyylex_destroy (scanner);
t_set_push (&(sparp->sparp_output_lexem_bufs), sparp->sparp_curr_lexem_buf);
sparp->sparp_curr_lexem_buf = NULL;
sparp->sparp_curr_lexem_bmk.sparlb_lexem_bufs_tail = sparp->sparp_output_lexem_bufs = dk_set_nreverse (sparp->sparp_output_lexem_bufs);
sparp->sparp_lexem_buf_len = box_length (sparp->sparp_curr_lexem_bmk.sparlb_lexem_bufs_tail->data) / sizeof (spar_lexem_t);
}
|
andywx/agensgraph
|
src/backend/parser/sparql_p.c
|
/* A Bison parser, made by GNU Bison 3.0.4. */
/* Bison implementation for Yacc-like parsers in C
Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* As a special exception, you may create a larger work that contains
part or all of the Bison parser skeleton and distribute that work
under terms of your choice, so long as that work isn't itself a
parser generator using the skeleton or a modified version thereof
as a parser skeleton. Alternatively, if you modify or redistribute
the parser skeleton itself, you may (at your option) remove this
special exception, which will cause the skeleton and the resulting
Bison output files to be licensed under the GNU General Public
License without this special exception.
This special exception was added by the Free Software Foundation in
version 2.2 of Bison. */
/* C LALR(1) parser skeleton written by <NAME>, by
simplifying the original so-called "semantic" parser. */
/* All symbols defined below should begin with yy or YY, to avoid
infringing on user name space. This should be done even for local
variables, as they might otherwise be expanded by user macros.
There are some unavoidable exceptions within include files to
define necessary library symbols; they are noted "INFRINGES ON
USER NAME SPACE" below. */
/* Identify Bison output. */
#define YYBISON 1
/* Bison version. */
#define YYBISON_VERSION "3.0.4"
/* Skeleton name. */
#define YYSKELETON_NAME "yacc.c"
/* Pure parsers. */
#define YYPURE 1
/* Push parsers. */
#define YYPUSH 0
/* Pull parsers. */
#define YYPULL 1
/* Substitute the variable and function names. */
#define yyparse sparyyparse
#define yylex sparyylex
#define yyerror sparyyerror
#define yydebug sparyydebug
#define yynerrs sparyynerrs
/* Copy the first part of user declarations. */
#line 44 "sparql_p.y" /* yacc.c:339 */
#include "dkpool.h"
#include "sparql.h"
#include "sparql_l.h"
#include "sparql_func.h"
#ifdef DEBUG
#define sparyyerror(sparp_arg, strg) sparyyerror_impl_1(sparp_arg, NULL, yystate, yyssa, yyssp, (strg))
#else
#define sparyyerror(sparp_arg, strg) sparyyerror_impl(sparp_arg, NULL, (strg))
#endif
#ifdef XPYYDEBUG
#define YYDEBUG 1
#endif
#define sparyylex(lval_ptr, param) sparyylex_from_sparp_bufs ((void * *)(lval_ptr), ((sparp_t *)(param)))
#define SPAR_BIN_OP(dst,op,l,r) (dst) = spartlist (sparp_arg, 3, (op), (l), (r))
#define bmk_offset sparp_curr_lexem_bmk.sparlb_offset
#define bmk_bufs_tail sparp_curr_lexem_bmk.sparlb_lexem_bufs_tail
int sparyylex_from_sparp_bufs (void * *yylval, sparp_t *sparp)
{
spar_lexem_t *sparl;
while (sparp->bmk_offset >= sparp->sparp_lexem_buf_len)
{
sparp->bmk_bufs_tail = sparp->bmk_bufs_tail->next;
if (NULL == sparp->bmk_bufs_tail)
{
/*sparp->sparp_curr_lexem = NULL; -- commented out to have at least 'some' current lexem */
return 0;
}
sparp->sparp_lexem_buf_len = box_length (sparp->bmk_bufs_tail->data) / sizeof (spar_lexem_t);
sparp->bmk_offset = 0;
}
sparl = ((spar_lexem_t *)(sparp->bmk_bufs_tail->data)) + sparp->bmk_offset;
yylval[0] = sparl->sparl_sem_value;
sparp->sparp_curr_lexem = sparl;
sparp->bmk_offset += 1;
return (int) sparl->sparl_lex_value;
}
#line 120 "sparql_p.c" /* yacc.c:339 */
# ifndef YY_NULLPTR
# if defined __cplusplus && 201103L <= __cplusplus
# define YY_NULLPTR nullptr
# else
# define YY_NULLPTR 0
# endif
# endif
/* Enabling verbose error messages. */
#ifdef YYERROR_VERBOSE
# undef YYERROR_VERBOSE
# define YYERROR_VERBOSE 1
#else
# define YYERROR_VERBOSE 0
#endif
/* In a future release of Bison, this section will be replaced
by #include "sparql_p.h". */
#ifndef YY_SPARYY_SPARQL_P_H_INCLUDED
# define YY_SPARYY_SPARQL_P_H_INCLUDED
/* Debug traces. */
#ifndef YYDEBUG
# define YYDEBUG 0
#endif
#if YYDEBUG
extern int sparyydebug;
#endif
/* Token type. */
#ifndef YYTOKENTYPE
# define YYTOKENTYPE
enum yytokentype
{
__SPAR_PUNCT_BEGIN = 258,
_AMP_AMP = 259,
_BACKQUOTE = 260,
_BANG = 261,
_BAR = 262,
_BAR_BAR = 263,
_CARET = 264,
_CARET_CARET = 265,
_COMMA = 266,
_DOT = 267,
_EQ = 268,
_GE = 269,
_GT = 270,
_LBRA = 271,
_LE = 272,
_LPAR = 273,
_LSQBRA = 274,
_LT = 275,
_MINUS = 276,
_NOT_EQ = 277,
_PLUS = 278,
_PLUS_GT = 279,
_QMARK = 280,
_RBRA = 281,
_RPAR = 282,
_RSQBRA = 283,
_SEMI = 284,
_SLASH = 285,
_STAR = 286,
_STAR_GT = 287,
a_L = 288,
ADD_L = 289,
ALL_L = 290,
ALTER_L = 291,
AS_L = 292,
ASC_L = 293,
ASK_L = 294,
ASSUME_L = 295,
ATTACH_L = 296,
AVG_L = 297,
BASE_L = 298,
BIJECTION_L = 299,
BIND_L = 300,
BINDINGS_L = 301,
BOUND_L = 302,
BY_L = 303,
CASE_L = 304,
CLASS_L = 305,
CLEAR_L = 306,
CREATE_L = 307,
CONSTRUCT_L = 308,
COPY_L = 309,
COUNT_L = 310,
COUNT_LPAR = 311,
COUNT_DISTINCT_L = 312,
CUBE_L = 313,
DATA_L = 314,
DATATYPE_L = 315,
DEFAULT_L = 316,
DEFINE_L = 317,
DEFMACRO_L = 318,
DELETE_L = 319,
DEREF_L = 320,
DESC_L = 321,
DESCRIBE_L = 322,
DETACH_L = 323,
DISTINCT_L = 324,
DROP_L = 325,
ELSE_L = 326,
END_L = 327,
EXCLUSIVE_L = 328,
EXISTS_L = 329,
false_L = 330,
FILTER_L = 331,
FROM_L = 332,
FUNCTION_L = 333,
GEO_L = 334,
GRAPH_L = 335,
GROUP_L = 336,
GROUP_CONCAT_L = 337,
GROUPING_L = 338,
HAVING_L = 339,
IDENTIFIED_L = 340,
IFP_L = 341,
IN_L = 342,
INF_L = 343,
INDEX_L = 344,
INFERENCE_L = 345,
INSERT_L = 346,
INTO_L = 347,
IRI_L = 348,
LANG_L = 349,
LIBRARY_L = 350,
LIKE_L = 351,
LIMIT_L = 352,
LITERAL_L = 353,
LOCAL_L = 354,
LOAD_L = 355,
MACRO_L = 356,
MAKE_L = 357,
MAP_L = 358,
MAX_L = 359,
MIN_L = 360,
MINUS_L = 361,
MODIFY_L = 362,
MOVE_L = 363,
NAMED_L = 364,
NAN_L = 365,
NIL_L = 366,
NOT_L = 367,
NOT_EXISTS_L = 368,
NOT_FROM_L = 369,
NOT_IN_L = 370,
NOT_NULL_L = 371,
NOT_USING_L = 372,
NULL_L = 373,
OBJECT_L = 374,
OF_L = 375,
OFFBAND_L = 376,
OFFSET_L = 377,
OPTIONAL_L = 378,
OPTION_L = 379,
ORDER_L = 380,
PRECISION_L = 381,
PREDICATE_L = 382,
PREFIX_L = 383,
QUAD_L = 384,
REDUCED_L = 385,
RETURNS_L = 386,
ROLLUP_L = 387,
SAME_AS_L = 388,
SAME_AS_O_L = 389,
SAME_AS_P_L = 390,
SAME_AS_S_L = 391,
SAME_AS_S_O_L = 392,
SAMPLE_L = 393,
SCORE_L = 394,
SCORE_LIMIT_L = 395,
SELECT_L = 396,
SERVICE_L = 397,
SETS_L = 398,
SILENT_L = 399,
SOFT_L = 400,
SQLQUERY_L = 401,
STORAGE_L = 402,
SUBCLASS_L = 403,
SUBJECT_L = 404,
SUM_L = 405,
TABID_L = 406,
TABLE_OPTION_L = 407,
TEXT_L = 408,
THEN_L = 409,
TIES_L = 410,
TO_L = 411,
TOP_L = 412,
TRANSITIVE_L = 413,
T_CYCLES_ONLY_L = 414,
T_DIRECTION_L = 415,
T_DISTINCT_L = 416,
T_END_FLAG_L = 417,
T_EXISTS_L = 418,
T_FINAL_AS_L = 419,
T_IN_L = 420,
T_MAX_L = 421,
T_MIN_L = 422,
T_OUT_L = 423,
T_NO_CYCLES_L = 424,
T_NO_ORDER_L = 425,
T_SHORTEST_ONLY_L = 426,
T_STEP_L = 427,
true_L = 428,
UNBOUND_L = 429,
UNDEF_L = 430,
UNION_L = 431,
USING_L = 432,
VALUES_L = 433,
WHEN_L = 434,
WHERE_L = 435,
WITH_L = 436,
XML_L = 437,
__SPAR_PUNCT_END = 438,
START_OF_SPARQL_TEXT = 439,
END_OF_SPARQL_TEXT = 440,
SPARUL_RUN_SUBTYPE = 441,
SPARUL_INSERT_DATA = 442,
SPARUL_DELETE_DATA = 443,
__SPAR_NONPUNCT_START = 444,
SPARQL_BIF = 445,
SPARQL_INTEGER = 446,
SPARQL_DECIMAL = 447,
SPARQL_DOUBLE = 448,
SPARQL_STRING = 449,
SPARQL_SQLTEXT = 450,
LANGTAG = 451,
QNAME = 452,
QNAME_NS = 453,
BLANK_NODE_LABEL = 454,
Q_IRI_REF = 455,
QD_VARNAME = 456,
QD_COLON_PARAMNAME = 457,
QD_COLON_PARAMNUM = 458,
SPARQL_PLAIN_ID = 459,
SPARQL_SQL_ALIASCOLNAME = 460,
SPARQL_SQL_QTABLENAME = 461,
SPARQL_SQL_QTABLECOLNAME = 462,
__SPAR_NONPUNCT_END = 463,
PRECODE_EXPN_PREC = 464,
_COLON = 465,
MATH_UPLUS = 466,
MATH_UMINUS = 467,
PPATH_ALTERNATIVE = 468,
PPATH_SEQUENCE = 469,
PPATH_CARET = 470,
PPATH_MOD = 471,
PPATH_BANG = 472
};
#endif
/* Value type. */
#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
union YYSTYPE
{
#line 93 "sparql_p.y" /* yacc.c:355 */
void * box;
void * *boxes;
ptrlong token_type;
ptrlong nonboxed_int;
SPART *tree;
SPART **trees;
dk_set_t list;
dk_set_t backstack;
spar_lexbmk_t *bookmark;
void *nothing;
#line 391 "sparql_p.c" /* yacc.c:355 */
};
typedef union YYSTYPE YYSTYPE;
# define YYSTYPE_IS_TRIVIAL 1
# define YYSTYPE_IS_DECLARED 1
#endif
int sparyyparse (sparp_t * sparp_arg);
#endif /* !YY_SPARYY_SPARQL_P_H_INCLUDED */
/* Copy the second part of user declarations. */
#line 407 "sparql_p.c" /* yacc.c:358 */
#ifdef short
# undef short
#endif
#ifdef YYTYPE_UINT8
typedef YYTYPE_UINT8 yytype_uint8;
#else
typedef unsigned char yytype_uint8;
#endif
#ifdef YYTYPE_INT8
typedef YYTYPE_INT8 yytype_int8;
#else
typedef signed char yytype_int8;
#endif
#ifdef YYTYPE_UINT16
typedef YYTYPE_UINT16 yytype_uint16;
#else
typedef unsigned short int yytype_uint16;
#endif
#ifdef YYTYPE_INT16
typedef YYTYPE_INT16 yytype_int16;
#else
typedef short int yytype_int16;
#endif
#ifndef YYSIZE_T
# ifdef __SIZE_TYPE__
# define YYSIZE_T __SIZE_TYPE__
# elif defined size_t
# define YYSIZE_T size_t
# elif ! defined YYSIZE_T
# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
# define YYSIZE_T size_t
# else
# define YYSIZE_T unsigned int
# endif
#endif
#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
#ifndef YY_
# if defined YYENABLE_NLS && YYENABLE_NLS
# if ENABLE_NLS
# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
# define YY_(Msgid) dgettext ("bison-runtime", Msgid)
# endif
# endif
# ifndef YY_
# define YY_(Msgid) Msgid
# endif
#endif
#ifndef YY_ATTRIBUTE
# if (defined __GNUC__ \
&& (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \
|| defined __SUNPRO_C && 0x5110 <= __SUNPRO_C
# define YY_ATTRIBUTE(Spec) __attribute__(Spec)
# else
# define YY_ATTRIBUTE(Spec) /* empty */
# endif
#endif
#ifndef YY_ATTRIBUTE_PURE
# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__))
#endif
#ifndef YY_ATTRIBUTE_UNUSED
# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__))
#endif
#if !defined _Noreturn \
&& (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112)
# if defined _MSC_VER && 1200 <= _MSC_VER
# define _Noreturn __declspec (noreturn)
# else
# define _Noreturn YY_ATTRIBUTE ((__noreturn__))
# endif
#endif
/* Suppress unused-variable warnings by "using" E. */
#if ! defined lint || defined __GNUC__
# define YYUSE(E) ((void) (E))
#else
# define YYUSE(E) /* empty */
#endif
#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
/* Suppress an incorrect diagnostic about yylval being uninitialized. */
# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
_Pragma ("GCC diagnostic push") \
_Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
_Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
_Pragma ("GCC diagnostic pop")
#else
# define YY_INITIAL_VALUE(Value) Value
#endif
#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
# define YY_IGNORE_MAYBE_UNINITIALIZED_END
#endif
#ifndef YY_INITIAL_VALUE
# define YY_INITIAL_VALUE(Value) /* Nothing. */
#endif
#if ! defined yyoverflow || YYERROR_VERBOSE
/* The parser invokes alloca or malloc; define the necessary symbols. */
# ifdef YYSTACK_USE_ALLOCA
# if YYSTACK_USE_ALLOCA
# ifdef __GNUC__
# define YYSTACK_ALLOC __builtin_alloca
# elif defined __BUILTIN_VA_ARG_INCR
# include <alloca.h> /* INFRINGES ON USER NAME SPACE */
# elif defined _AIX
# define YYSTACK_ALLOC __alloca
# elif defined _MSC_VER
# include <malloc.h> /* INFRINGES ON USER NAME SPACE */
# define alloca _alloca
# else
# define YYSTACK_ALLOC alloca
# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
/* Use EXIT_SUCCESS as a witness for stdlib.h. */
# ifndef EXIT_SUCCESS
# define EXIT_SUCCESS 0
# endif
# endif
# endif
# endif
# endif
# ifdef YYSTACK_ALLOC
/* Pacify GCC's 'empty if-body' warning. */
# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
# ifndef YYSTACK_ALLOC_MAXIMUM
/* The OS might guarantee only one guard page at the bottom of the stack,
and a page size can be as small as 4096 bytes. So we cannot safely
invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
to allow for a few compiler-allocated temporary stack slots. */
# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
# endif
# else
# define YYSTACK_ALLOC YYMALLOC
# define YYSTACK_FREE YYFREE
# ifndef YYSTACK_ALLOC_MAXIMUM
# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
# endif
# if (defined __cplusplus && ! defined EXIT_SUCCESS \
&& ! ((defined YYMALLOC || defined malloc) \
&& (defined YYFREE || defined free)))
# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
# ifndef EXIT_SUCCESS
# define EXIT_SUCCESS 0
# endif
# endif
# ifndef YYMALLOC
# define YYMALLOC malloc
# if ! defined malloc && ! defined EXIT_SUCCESS
void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
# endif
# endif
# ifndef YYFREE
# define YYFREE free
# if ! defined free && ! defined EXIT_SUCCESS
void free (void *); /* INFRINGES ON USER NAME SPACE */
# endif
# endif
# endif
#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
#if (! defined yyoverflow \
&& (! defined __cplusplus \
|| (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
/* A type that is properly aligned for any stack member. */
union yyalloc
{
yytype_int16 yyss_alloc;
YYSTYPE yyvs_alloc;
};
/* The size of the maximum gap between one aligned stack and the next. */
# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
/* The size of an array large to enough to hold all stacks, each with
N elements. */
# define YYSTACK_BYTES(N) \
((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+ YYSTACK_GAP_MAXIMUM)
# define YYCOPY_NEEDED 1
/* Relocate STACK from its old location to the new one. The
local variables YYSIZE and YYSTACKSIZE give the old and new number of
elements in the stack, and YYPTR gives the new location of the
stack. Advance YYPTR to a properly aligned location for the next
stack. */
# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
do \
{ \
YYSIZE_T yynewbytes; \
YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
Stack = &yyptr->Stack_alloc; \
yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
yyptr += yynewbytes / sizeof (*yyptr); \
} \
while (0)
#endif
#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
/* Copy COUNT objects from SRC to DST. The source and destination do
not overlap. */
# ifndef YYCOPY
# if defined __GNUC__ && 1 < __GNUC__
# define YYCOPY(Dst, Src, Count) \
__builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src)))
# else
# define YYCOPY(Dst, Src, Count) \
do \
{ \
YYSIZE_T yyi; \
for (yyi = 0; yyi < (Count); yyi++) \
(Dst)[yyi] = (Src)[yyi]; \
} \
while (0)
# endif
# endif
#endif /* !YYCOPY_NEEDED */
/* YYFINAL -- State number of the termination state. */
#define YYFINAL 8
/* YYLAST -- Last index in YYTABLE. */
#define YYLAST 5428
/* YYNTOKENS -- Number of terminals. */
#define YYNTOKENS 218
/* YYNNTS -- Number of nonterminals. */
#define YYNNTS 373
/* YYNRULES -- Number of rules. */
#define YYNRULES 857
/* YYNSTATES -- Number of states. */
#define YYNSTATES 1425
/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
by yylex, with out-of-bounds checking. */
#define YYUNDEFTOK 2
#define YYMAXUTOK 472
#define YYTRANSLATE(YYX) \
((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
as returned by yylex, without out-of-bounds checking. */
static const yytype_uint8 yytranslate[] =
{
0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
85, 86, 87, 88, 89, 90, 91, 92, 93, 94,
95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
105, 106, 107, 108, 109, 110, 111, 112, 113, 114,
115, 116, 117, 118, 119, 120, 121, 122, 123, 124,
125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
135, 136, 137, 138, 139, 140, 141, 142, 143, 144,
145, 146, 147, 148, 149, 150, 151, 152, 153, 154,
155, 156, 157, 158, 159, 160, 161, 162, 163, 164,
165, 166, 167, 168, 169, 170, 171, 172, 173, 174,
175, 176, 177, 178, 179, 180, 181, 182, 183, 184,
185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
195, 196, 197, 198, 199, 200, 201, 202, 203, 204,
205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
215, 216, 217
};
#if YYDEBUG
/* YYRLINE[YYN] -- Source line where rule number YYN was defined. */
static const yytype_uint16 yyrline[] =
{
0, 625, 625, 626, 627, 629, 633, 635, 637, 643,
644, 645, 646, 651, 655, 656, 660, 660, 670, 671,
675, 676, 677, 678, 679, 683, 684, 688, 692, 693,
697, 703, 704, 707, 709, 709, 718, 719, 725, 725,
738, 740, 738, 746, 749, 746, 756, 761, 766, 771,
779, 780, 781, 785, 786, 787, 791, 796, 803, 804,
811, 812, 816, 817, 818, 823, 824, 825, 826, 827,
828, 833, 833, 838, 839, 845, 845, 859, 860, 861,
862, 866, 866, 871, 873, 874, 880, 880, 893, 897,
893, 915, 915, 928, 929, 933, 933, 943, 944, 952,
957, 961, 967, 968, 969, 970, 974, 975, 976, 977,
981, 982, 982, 987, 988, 992, 994, 999, 999, 1005,
1008, 1012, 1012, 1020, 1020, 1031, 1032, 1039, 1040, 1041,
1045, 1046, 1046, 1054, 1055, 1059, 1060, 1065, 1066, 1067,
1068, 1069, 1070, 1074, 1075, 1076, 1080, 1081, 1085, 1088,
1091, 1097, 1102, 1104, 1106, 1108, 1113, 1114, 1115, 1119,
1120, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133,
1134, 1138, 1139, 1139, 1147, 1148, 1152, 1153, 1153, 1161,
1162, 1163, 1167, 1168, 1172, 1173, 1178, 1179, 1180, 1181,
1182, 1183, 1187, 1188, 1189, 1193, 1194, 1198, 1202, 1203,
1207, 1211, 1212, 1219, 1222, 1219, 1226, 1234, 1234, 1245,
1246, 1250, 1251, 1255, 1256, 1260, 1261, 1265, 1272, 1273,
1277, 1278, 1279, 1280, 1281, 1282, 1283, 1287, 1290, 1294,
1294, 1330, 1331, 1332, 1333, 1350, 1351, 1352, 1353, 1354,
1355, 1356, 1357, 1358, 1359, 1367, 1367, 1368, 1372, 1373,
1374, 1372, 1381, 1382, 1380, 1389, 1389, 1390, 1390, 1407,
1408, 1412, 1413, 1417, 1417, 1424, 1424, 1430, 1435, 1435,
1443, 1444, 1448, 1449, 1453, 1454, 1458, 1465, 1466, 1470,
1471, 1472, 1473, 1474, 1475, 1476, 1480, 1481, 1482, 1486,
1487, 1491, 1491, 1511, 1527, 1538, 1511, 1561, 1562, 1566,
1567, 1571, 1572, 1582, 1583, 1587, 1587, 1607, 1608, 1609,
1610, 1614, 1615, 1616, 1620, 1621, 1622, 1623, 1627, 1628,
1632, 1633, 1637, 1638, 1637, 1645, 1645, 1647, 1647, 1649,
1653, 1654, 1660, 1660, 1663, 1662, 1665, 1666, 1667, 1671,
1672, 1673, 1674, 1675, 1676, 1680, 1685, 1686, 1687, 1687,
1697, 1698, 1702, 1705, 1708, 1711, 1714, 1717, 1723, 1725,
1730, 1732, 1733, 1734, 1736, 1740, 1742, 1744, 1749, 1751,
1756, 1758, 1760, 1762, 1764, 1766, 1768, 1770, 1772, 1774,
1776, 1778, 1780, 1782, 1784, 1785, 1790, 1791, 1795, 1796,
1797, 1798, 1799, 1803, 1804, 1805, 1806, 1807, 1811, 1812,
1816, 1817, 1821, 1822, 1823, 1824, 1828, 1829, 1830, 1831,
1832, 1836, 1840, 1841, 1842, 1843, 1847, 1848, 1849, 1850,
1851, 1852, 1853, 1857, 1857, 1862, 1862, 1874, 1878, 1879,
1883, 1887, 1900, 1901, 1905, 1906, 1910, 1911, 1915, 1916,
1917, 1918, 1922, 1923, 1924, 1925, 1929, 1930, 1934, 1935,
1939, 1940, 1943, 1944, 1945, 1948, 1951, 1952, 1953, 1961,
1965, 1966, 1967, 1968, 1969, 1970, 1974, 1977, 1978, 1982,
1983, 1987, 2004, 2009, 2017, 2022, 2023, 2028, 2029, 2030,
2031, 2032, 2033, 2034, 2038, 2038, 2063, 2064, 2066, 2069,
2073, 2074, 2074, 2077, 2077, 2092, 2092, 2108, 2109, 2110,
2111, 2112, 2116, 2120, 2122, 2123, 2125, 2127, 2158, 2161,
2161, 2178, 2178, 2199, 2205, 2206, 2206, 2239, 2240, 2241,
2242, 2243, 2244, 2245, 2249, 2266, 2268, 2270, 2272, 2274,
2279, 2284, 2291, 2292, 2293, 2297, 2297, 2328, 2328, 2350,
2351, 2355, 2356, 2357, 2361, 2362, 2363, 2364, 2368, 2369,
2373, 2374, 2375, 2379, 2380, 2381, 2382, 2386, 2387, 2387,
2393, 2394, 2395, 2396, 2399, 2405, 2406, 2407, 2415, 2419,
2420, 2424, 2425, 2426, 2430, 2431, 2435, 2436, 2440, 2441,
2442, 2443, 2447, 2448, 2452, 2456, 2460, 2464, 2468, 2469,
2473, 2474, 2478, 2484, 2490, 2491, 2492, 2501, 2502, 2503,
2504, 2505, 2506, 2507, 2508, 2509, 2510, 2511, 2512, 2513,
2514, 2518, 2525, 2527, 2525, 2540, 2540, 2556, 2558, 2556,
2571, 2571, 2588, 2590, 2588, 2603, 2609, 2611, 2616, 2618,
2623, 2628, 2633, 2634, 2641, 2642, 2646, 2650, 2651, 2655,
2659, 2660, 2661, 2662, 2666, 2667, 2671, 2672, 2676, 2677,
2684, 2685, 2689, 2690, 2699, 2701, 2699, 2715, 2720, 2715,
2737, 2739, 2737, 2748, 2749, 2753, 2759, 2760, 2761, 2767,
2768, 2768, 2774, 2775, 2776, 2782, 2783, 2784, 2785, 2786,
2792, 2801, 2813, 2823, 2826, 2832, 2833, 2834, 2838, 2842,
2849, 2851, 2853, 2855, 2857, 2859, 2865, 2866, 2870, 2884,
2870, 2895, 2896, 2900, 2907, 2900, 2918, 2929, 2935, 2944,
2950, 2959, 2960, 2960, 2965, 2968, 2968, 2974, 2979, 2980,
2984, 2991, 2992, 2996, 2997, 3001, 3002, 3006, 3010, 3017,
3018, 3022, 3023, 3024, 3028, 3029, 3029, 3036, 3037, 3039,
3041, 3043, 3048, 3057, 3063, 3072, 3073, 3074, 3078, 3079,
3079, 3087, 3086, 3089, 3096, 3104, 3103, 3113, 3117, 3119,
3118, 3133, 3147, 3147, 3152, 3153, 3157, 3158, 3159, 3160,
3161, 3160, 3169, 3170, 3170, 3176, 3176, 3181, 3185, 3188,
3188, 3196, 3200, 3202, 3204, 3196, 3207, 3211, 3212, 3216,
3217, 3218, 3219, 3223, 3224, 3225, 3229, 3230, 3231, 3235,
3236, 3240, 3241, 3242, 3243, 3246, 3251, 3252, 3256, 3257,
3261, 3262, 3266, 3267, 3271, 3272, 3273, 3277, 3281, 3288,
3289, 3290, 3291, 3295, 3296, 3300, 3301, 3305, 3306, 3310,
3316, 3320, 3321, 3325, 3326, 3330, 3336, 3337, 3338, 3339,
3343, 3344, 3348, 3349, 3350, 3354, 3355, 3356, 3357, 3358,
3363, 3364, 3369, 3370, 3374, 3375, 3379, 3380
};
#endif
#if YYDEBUG || YYERROR_VERBOSE || 0
/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
First, the terminals, then, starting at YYNTOKENS, nonterminals. */
static const char *const yytname[] =
{
"$end", "error", "$undefined", "__SPAR_PUNCT_BEGIN", "_AMP_AMP",
"_BACKQUOTE", "_BANG", "_BAR", "_BAR_BAR", "_CARET", "_CARET_CARET",
"_COMMA", "_DOT", "_EQ", "_GE", "_GT", "_LBRA", "_LE", "_LPAR",
"_LSQBRA", "_LT", "_MINUS", "_NOT_EQ", "_PLUS", "_PLUS_GT", "_QMARK",
"_RBRA", "_RPAR", "_RSQBRA", "_SEMI", "_SLASH", "_STAR", "_STAR_GT",
"a_L", "ADD_L", "ALL_L", "ALTER_L", "AS_L", "ASC_L", "ASK_L", "ASSUME_L",
"ATTACH_L", "AVG_L", "BASE_L", "BIJECTION_L", "BIND_L", "BINDINGS_L",
"BOUND_L", "BY_L", "CASE_L", "CLASS_L", "CLEAR_L", "CREATE_L",
"CONSTRUCT_L", "COPY_L", "COUNT_L", "COUNT_LPAR", "COUNT_DISTINCT_L",
"CUBE_L", "DATA_L", "DATATYPE_L", "DEFAULT_L", "DEFINE_L", "DEFMACRO_L",
"DELETE_L", "DEREF_L", "DESC_L", "DESCRIBE_L", "DETACH_L", "DISTINCT_L",
"DROP_L", "ELSE_L", "END_L", "EXCLUSIVE_L", "EXISTS_L", "false_L",
"FILTER_L", "FROM_L", "FUNCTION_L", "GEO_L", "GRAPH_L", "GROUP_L",
"GROUP_CONCAT_L", "GROUPING_L", "HAVING_L", "IDENTIFIED_L", "IFP_L",
"IN_L", "INF_L", "INDEX_L", "INFERENCE_L", "INSERT_L", "INTO_L", "IRI_L",
"LANG_L", "LIBRARY_L", "LIKE_L", "LIMIT_L", "LITERAL_L", "LOCAL_L",
"LOAD_L", "MACRO_L", "MAKE_L", "MAP_L", "MAX_L", "MIN_L", "MINUS_L",
"MODIFY_L", "MOVE_L", "NAMED_L", "NAN_L", "NIL_L", "NOT_L",
"NOT_EXISTS_L", "NOT_FROM_L", "NOT_IN_L", "NOT_NULL_L", "NOT_USING_L",
"NULL_L", "OBJECT_L", "OF_L", "OFFBAND_L", "OFFSET_L", "OPTIONAL_L",
"OPTION_L", "ORDER_L", "PRECISION_L", "PREDICATE_L", "PREFIX_L",
"QUAD_L", "REDUCED_L", "RETURNS_L", "ROLLUP_L", "SAME_AS_L",
"SAME_AS_O_L", "SAME_AS_P_L", "SAME_AS_S_L", "SAME_AS_S_O_L", "SAMPLE_L",
"SCORE_L", "SCORE_LIMIT_L", "SELECT_L", "SERVICE_L", "SETS_L",
"SILENT_L", "SOFT_L", "SQLQUERY_L", "STORAGE_L", "SUBCLASS_L",
"SUBJECT_L", "SUM_L", "TABID_L", "TABLE_OPTION_L", "TEXT_L", "THEN_L",
"TIES_L", "TO_L", "TOP_L", "TRANSITIVE_L", "T_CYCLES_ONLY_L",
"T_DIRECTION_L", "T_DISTINCT_L", "T_END_FLAG_L", "T_EXISTS_L",
"T_FINAL_AS_L", "T_IN_L", "T_MAX_L", "T_MIN_L", "T_OUT_L",
"T_NO_CYCLES_L", "T_NO_ORDER_L", "T_SHORTEST_ONLY_L", "T_STEP_L",
"true_L", "UNBOUND_L", "UNDEF_L", "UNION_L", "USING_L", "VALUES_L",
"WHEN_L", "WHERE_L", "WITH_L", "XML_L", "__SPAR_PUNCT_END",
"START_OF_SPARQL_TEXT", "END_OF_SPARQL_TEXT", "SPARUL_RUN_SUBTYPE",
"SPARUL_INSERT_DATA", "SPARUL_DELETE_DATA", "__SPAR_NONPUNCT_START",
"SPARQL_BIF", "SPARQL_INTEGER", "SPARQL_DECIMAL", "SPARQL_DOUBLE",
"SPARQL_STRING", "SPARQL_SQLTEXT", "LANGTAG", "QNAME", "QNAME_NS",
"BLANK_NODE_LABEL", "Q_IRI_REF", "QD_VARNAME", "QD_COLON_PARAMNAME",
"QD_COLON_PARAMNUM", "SPARQL_PLAIN_ID", "SPARQL_SQL_ALIASCOLNAME",
"SPARQL_SQL_QTABLENAME", "SPARQL_SQL_QTABLECOLNAME",
"__SPAR_NONPUNCT_END", "PRECODE_EXPN_PREC", "_COLON", "MATH_UPLUS",
"MATH_UMINUS", "PPATH_ALTERNATIVE", "PPATH_SEQUENCE", "PPATH_CARET",
"PPATH_MOD", "PPATH_BANG", "$accept", "sparql",
"spar_query_or_ul_operations", "spar_query_body", "spar_prolog",
"spar_defines_opt", "spar_define", "$@1", "spar_define_val_commalist",
"spar_define_val", "spar_base_decl_opt", "spar_prefix_decls_opt",
"spar_prefix_decl", "spar_create_macro_lib_opt", "$@2",
"spar_defmacros_opt", "spar_defmacro", "$@3", "spar_dm_args_and_body",
"$@4", "$@5", "$@6", "$@7", "spar_dm_match_template",
"spar_dm_local_args_opt", "spar_dm_args_opt", "spar_dm_arg_commalist",
"spar_dm_args", "spar_dm_patitem_gs", "spar_dm_patitem_p",
"spar_dm_patitem_o", "spar_dm_gp_or_expn", "$@8", "spar_select_query",
"$@9", "spar_select_query_mode", "spar_select_rset", "@10",
"spar_select_rset_1", "spar_construct_query", "$@11", "$@12", "$@13",
"spar_describe_query", "$@14", "spar_describe_rset", "spar_ask_query",
"$@15", "spar_dataset_clauses_opt", "spar_dataset_clause",
"spar_dataset_clause_subtype", "spar_dataset_clause_subtype_from",
"spar_dataset_clause_subtype_using", "spar_sponge_optionlist_opt",
"$@16", "spar_sponge_option_commalist_opt_rpar",
"spar_sponge_option_commalist", "spar_precode_expn", "$@17",
"spar_where_clause_opt", "spar_where_clause", "$@18", "$@19",
"spar_where_clause_tail", "spar_solution_modifier",
"spar_group_clause_opt", "$@20", "spar_group_expns_or_sets",
"spar_group_expns", "spar_group_expn", "spar_grouping_sets",
"spar_grouping_set_list", "spar_grouping_set",
"spar_options_of_top_lpar", "spar_all_distinct_opt", "spar_ties_opt",
"spar_bin_op_sign", "spar_having_clause_opt", "$@21",
"spar_constraint_list_as_and", "spar_order_clause_opt", "$@22",
"spar_order_conditions", "spar_order_condition_nocommalist",
"spar_order_condition_commalist", "spar_order_condition",
"spar_asc_or_desc_opt", "spar_limit_clause_opt", "spar_limit_clause",
"spar_offset_clause_opt", "spar_offset_clause",
"spar_bindings_clause_opt", "spar_bindings_clause_int", "$@23", "$@24",
"$@25", "spar_bindings_vars", "spar_bindings_var", "spar_bindings_opt",
"spar_bindings", "spar_binding", "spar_bindvals", "spar_bindval",
"spar_group_gp", "spar_group_gp_with_subselect", "@26", "spar_gp",
"spar_gp_not_triples", "spar_optional_gp", "$@27", "spar_quad_map_gp",
"$@28", "$@29", "$@30", "spar_graph_gp", "$@31", "$@32",
"spar_group_or_union_gp", "$@33", "$@34", "spar_union_type",
"spar_binds", "spar_bind", "@35", "spar_inline_data", "$@36",
"spar_inline_data_tail", "$@37", "spar_inline_data_vars_opt",
"spar_inline_data_var", "spar_inline_data_rows_opt",
"spar_inline_data_row", "spar_inline_data_values_opt",
"spar_inline_data_value", "spar_constraint", "spar_exists_or_not_exists",
"spar_constraint_exists_int", "$@38", "spar_service_req", "@39", "@40",
"$@41", "spar_service_options_list_opt", "spar_service_options_opt",
"spar_service_option", "spar_ctor_template_nolbra", "$@42",
"spar_ctor_triples_or_quads_opt", "spar_ctor_triples_or_quads_triples",
"spar_ctor_triples_or_quads_quads", "spar_triples_opt", "spar_triples",
"spar_quads1", "$@43", "$@44", "spar_triples1", "$@45", "$@46",
"spar_props_opt", "spar_props", "$@47", "$@48", "spar_objects",
"spar_ograph_node", "spar_triple_optionlist_opt", "$@49",
"spar_triple_option_commalist", "spar_triple_option",
"spar_triple_inference_option", "spar_triple_freetext_option",
"spar_triple_geo_option", "spar_triple_transit_option",
"spar_triple_option_var_commalist", "spar_same_as_option", "spar_verb",
"spar_ppath", "spar_ppath_seq", "spar_ppath_fwd_or_inv",
"spar_ppath_fwd_or_inv_repcounts", "spar_ppath_leaf_or_sub",
"spar_triples_node", "$@50", "$@51", "spar_triples_opt_semi_rsqbra",
"spar_cons_collection", "spar_graph_node", "spar_var_or_term",
"spar_var_or_iriref_or_pexpn_or_backquoteds",
"spar_var_or_iriref_or_pexpn_or_backquoted",
"spar_var_or_blank_node_or_iriref_or_backquoted",
"spar_retcol_commalist", "spar_retcols", "spar_ret_agg_call",
"spar_agg_name", "spar_agg_name_int", "spar_group_concat_begin",
"spar_group_concat_begin_int", "spar_var_or_iriref", "spar_var",
"spar_global_var", "spar_global_var_int", "spar_graph_term",
"spar_backquoted", "@52", "spar_expn", "$@53", "$@54", "$@55", "$@56",
"$@57", "@58", "spar_built_in_call", "spar_caselist",
"spar_function_call", "@59", "spar_macro_call", "@60",
"spar_arg_list_opt", "spar_arg_list", "spar_expns",
"spar_macro_arg_list_opt", "spar_macro_arg_list", "spar_expn_or_ggps",
"spar_expn_or_ggp", "$@61", "spar_nonsigned_numeric_literal",
"spar_optsigned_numeric_literal", "spar_integer_literal",
"spar_optminus_integer_literal", "spar_rdf_literal",
"spar_boolean_literal", "spar_iriref_or_default_list_or_star",
"spar_iriref_or_default_list", "spar_arrow", "spar_arrow_iriref",
"spar_iriref", "spar_qname", "spar_blank_node",
"spar_sparul1x_action_or_drop_macro_libs",
"spar_sparul1x_action_or_drop_macro_lib", "spar_drop_macro_lib",
"spar_sparul_insert", "$@62", "$@63", "spar_sparul_insertdata", "$@64",
"spar_sparul_delete", "$@65", "$@66", "spar_sparul_deletedata", "$@67",
"spar_sparul_modify", "$@68", "$@69", "spar_sparul_clear",
"spar_sparul_load", "spar_sparul_load_service_data",
"spar_sparul_create", "spar_sparul_drop", "spar_action_solution",
"spar_in_graph_precode_opt", "spar_in_graph_precode",
"spar_from_graph_precode_opt", "spar_from_graph_precode",
"spar_all_or_named_or_default_or_graph_precode",
"spar_default_or_graph_precode", "spar_graph_precode_opt",
"spar_with_graph_precode_opt", "spar_in_or_into", "spar_silent_opt",
"spar_sparul11_deleteinsert", "$@70", "$@71", "$@72", "$@73",
"spar_sparul11_insert", "$@74", "$@75", "spar_sparul11_insert_opt",
"spar_sparul11_copymoveadd", "spar_sparul11_copymoveadd_op",
"spar_qm_stmts", "$@76", "spar_qm_stmt", "spar_qm_simple_stmt",
"spar_qm_create_iol_class", "spar_qm_drop_iol_class",
"spar_qm_create_iri_subclass", "spar_qm_iol_class_optionlist_opt",
"spar_qm_iol_class_option_commalist", "spar_qm_iol_class_option",
"spar_qm_sprintff_list", "spar_qm_create_quad_storage", "$@77", "$@78",
"spar_iol", "spar_qm_alter_quad_storage", "$@79", "$@80",
"spar_qm_drop_quad_storage", "spar_qm_drop_quad_map_mapping",
"spar_qm_drop_mapping", "spar_qm_from_where_list_opt", "$@81", "$@82",
"spar_qm_text_literal_list_opt", "spar_qm_text_literal_decl",
"spar_xml_opt", "spar_of_sqlcol_opt", "spar_qm_text_literal_options_opt",
"spar_qm_text_literal_option_commalist", "spar_qm_text_literal_option",
"spar_qm_map_top_group", "spar_qm_map_top_dotlist", "$@83",
"spar_qm_map_top_op", "spar_qm_attach_macro_lib",
"spar_qm_detach_macro_lib", "spar_qm_map_group", "spar_qm_map_dotlist",
"$@84", "spar_qm_map_op", "$@85", "$@86", "spar_qm_map_iddef", "$@87",
"spar_qm_map_single", "spar_qm_triples1", "$@88",
"spar_qm_named_fields_opt", "spar_qm_named_field", "$@89", "$@90",
"spar_qm_props", "$@91", "spar_qm_prop", "$@92",
"spar_qm_obj_field_commalist", "$@93", "spar_qm_obj_field", "$@94",
"$@95", "$@96", "$@97", "spar_qm_as_id_opt", "spar_qm_obj_datatype_opt",
"spar_qm_obj_language_opt", "spar_qm_verb", "spar_qm_field_or_blank",
"spar_qm_field", "spar_qm_where_list_opt", "spar_qm_where_list",
"spar_qm_where", "spar_qm_sqlquery", "spar_qm_options_opt",
"spar_qm_option_commalist", "spar_qm_option",
"spar_qm_sqlcol_commalist_opt", "spar_qm_sqlcol_commalist",
"spar_qm_sqlfunc_header_commalist", "spar_qm_sqlfunc_header",
"spar_qm_sqlfunc_arglist", "spar_qm_sqlfunc_arg_commalist_opt",
"spar_qm_sqlfunc_arg_commalist", "spar_qm_sqlfunc_arg",
"spar_qm_sqltype", "spar_qm_sql_in_out_inout", "spar_qm_sqlcol",
"spar_qm_sql_id", "spar_qm_iriref_const_expn",
"spar_graph_identified_by_opt", "spar_graph_identified_by",
"spar_opt_dot_and_end", YY_NULLPTR
};
#endif
# ifdef YYPRINT
/* YYTOKNUM[NUM] -- (External) token number corresponding to the
(internal) symbol number NUM (which must be that of a token). */
static const yytype_uint16 yytoknum[] =
{
0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
265, 266, 267, 268, 269, 270, 271, 272, 273, 274,
275, 276, 277, 278, 279, 280, 281, 282, 283, 284,
285, 286, 287, 288, 289, 290, 291, 292, 293, 294,
295, 296, 297, 298, 299, 300, 301, 302, 303, 304,
305, 306, 307, 308, 309, 310, 311, 312, 313, 314,
315, 316, 317, 318, 319, 320, 321, 322, 323, 324,
325, 326, 327, 328, 329, 330, 331, 332, 333, 334,
335, 336, 337, 338, 339, 340, 341, 342, 343, 344,
345, 346, 347, 348, 349, 350, 351, 352, 353, 354,
355, 356, 357, 358, 359, 360, 361, 362, 363, 364,
365, 366, 367, 368, 369, 370, 371, 372, 373, 374,
375, 376, 377, 378, 379, 380, 381, 382, 383, 384,
385, 386, 387, 388, 389, 390, 391, 392, 393, 394,
395, 396, 397, 398, 399, 400, 401, 402, 403, 404,
405, 406, 407, 408, 409, 410, 411, 412, 413, 414,
415, 416, 417, 418, 419, 420, 421, 422, 423, 424,
425, 426, 427, 428, 429, 430, 431, 432, 433, 434,
435, 436, 437, 438, 439, 440, 441, 442, 443, 444,
445, 446, 447, 448, 449, 450, 451, 452, 453, 454,
455, 456, 457, 458, 459, 460, 461, 462, 463, 464,
465, 466, 467, 468, 469, 470, 471, 472
};
# endif
#define YYPACT_NINF -1174
#define yypact_value_is_default(Yystate) \
(!!((Yystate) == (-1174)))
#define YYTABLE_NINF -647
#define yytable_value_is_error(Yytable_value) \
(!!((Yytable_value) == (-647)))
/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
STATE-NUM. */
static const yytype_int16 yypact[] =
{
59, -1174, 156, 257, -1174, 111, 3147, 408, -1174, 344,
1252, -1174, -1174, 214, 313, 749, -1174, 134, 313, 109,
313, 370, 94, -1174, 551, 1344, -1174, -1174, -1174, -1174,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174,
-1174, 313, 78, -1174, -1174, -1174, -1174, -1174, -1174, -1174,
-1174, -1174, 36, -1174, -1174, -1174, 267, 287, 313, 252,
-1174, 678, -1174, -1174, 374, 364, 444, 487, -1174, 465,
444, 550, 562, 1028, -1174, 57, -1174, -1174, 571, 444,
463, 340, -1174, -1174, -1174, -1174, -1174, 464, 560, 584,
-1174, -1174, -1174, 677, -1174, 266, -1174, -1174, -1174, -1174,
-1174, -1174, -1174, 313, -1174, 385, 491, -1174, -1174, -1174,
-1174, 547, 621, -1174, 695, 403, -1174, -1174, -1174, -1174,
-1174, 439, 403, -1174, 403, -1174, 738, -1174, -1174, -1174,
-1174, 679, 37, -1174, 736, -1174, 777, -1174, -1174, -1174,
-1174, 57, 4241, 604, 403, 708, 768, 821, -1174, -1174,
-1174, 445, 328, -1174, -1174, -1174, -1174, -1174, -1174, 683,
-1174, -1174, 581, 1044, 22, -1174, 145, 822, -1174, -1174,
-1174, -1174, -1174, 5, 752, 1906, -1174, -1174, 2583, -1174,
-1174, 501, 403, 403, -1174, -1174, -1174, -1174, 787, 444,
4241, 2939, 824, 4241, 4241, 839, 841, 3427, -1174, 848,
-1174, -1174, 867, 877, -1174, 888, 895, 439, 907, 913,
-1174, -1174, 914, 925, -1174, -1174, 237, -1174, -1174, -1174,
28, -1174, -1174, -1174, -1174, -1174, -1174, 3103, -1174, 4241,
-1174, 473, -1174, -1174, 5291, -1174, -1174, -1174, -1174, -1174,
-1174, -1174, 918, 799, 403, -1174, -1174, 400, -1174, 849,
850, 855, 856, 952, -1174, 439, -1174, -1174, -1174, 4241,
-1174, -1174, 395, -1174, 473, -1174, -1174, -1174, 3591, 385,
-1174, 309, 313, -1174, -1174, -1174, -1174, -1174, 959, -1174,
-1174, -1174, 772, 439, 444, -1174, -1174, -1174, 963, -1174,
902, 964, 965, -1174, 969, 824, 617, 617, -1174, -1174,
960, 83, 1906, -1174, -1174, -1174, -1174, 473, -1174, -1174,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, 978, 981,
739, -1174, 979, -1174, -1174, -1174, 403, -1174, -1174, 626,
-1174, -1174, 831, -1174, 3080, -1174, -1174, 4128, -1174, -1174,
-1174, -1174, 721, 4241, 3404, 40, 4241, 942, -1174, 4241,
4241, -1174, -1174, -1174, 3753, -1174, 3915, -1174, -1174, 439,
-1174, -1174, -1174, 986, 4079, 4218, 4628, -1174, -1174, 42,
-1174, 4241, 4241, 4241, 4241, 4241, 4241, 4241, 4241, 4241,
4241, 4241, 4241, 814, -1174, -1174, -1174, 237, -1174, 898,
-1174, -1174, -1174, 1003, -1174, -1174, -1174, -1174, -1174, -1174,
-1174, 896, 4241, 4696, 400, -1174, 400, -1174, -1174, 1014,
4241, 4731, -1174, 361, 1044, -1174, -1174, -1174, 184, -1174,
255, 820, 91, -1174, 751, 905, -1174, 626, -1174, 2774,
1839, -1174, -1174, 534, -1174, 1906, -1174, -1174, -1174, 2438,
1839, -1174, 2583, -1174, -1174, 635, -1174, 635, 534, -1174,
499, 930, 313, -1174, 2512, -1174, -1174, -1174, -11, 1012,
-1174, -1174, -1174, 2677, 626, -1174, 400, -1174, -1174, 626,
906, -1174, -1174, -1174, -1174, 970, 4037, 80, -1174, 4241,
4241, 4767, -1174, 4792, 4822, 311, 4241, 4847, -1174, 5291,
414, -1174, 400, -1174, 1031, 4883, -1174, 4241, -1174, 857,
-1174, -1174, -1174, -1174, 3080, 1454, 3475, 946, 946, 946,
946, 585, 3475, 585, -1174, -1174, -1174, 237, 4241, 237,
-1174, -1174, 403, 968, 2545, -1174, 400, 2583, 1046, -1174,
4918, -1174, 984, -1174, 984, 4241, 5291, 4241, -1174, 639,
896, -1174, 181, 64, -1174, 107, -1174, 964, 902, 1050,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, 1035, 1058, -1174,
-16, -1174, -1174, -1174, -1174, -1174, 2736, -1174, -1174, 1078,
97, 514, 79, -1174, 1052, 696, -1174, 1065, 1051, -1174,
840, 473, -1174, -1174, -1174, -1174, 473, -1174, -1174, -1174,
-1174, -1174, -1174, 1045, 1045, -1174, 984, 2545, 4241, -1174,
-1174, -1174, -1174, 1064, -1174, -1174, -1174, -1174, -1174, -1174,
945, 30, 2583, -1174, 900, -1174, 1067, -1174, -1174, -1174,
984, -1174, -1174, 400, -1174, -1174, 4241, 4241, 4943, 4576,
-1174, -1174, -1174, 3265, -1174, -1174, -1174, 4973, -1174, -1174,
2295, -1174, -5, -1174, -1174, 5004, 1071, -1174, 1024, -1174,
-1174, 1069, -1174, -1174, -1174, 1061, 2545, 984, 1062, -1174,
-1174, 1043, -1174, 1011, -1174, 5291, 5291, -1174, 852, 899,
1017, 852, -1174, -1174, -1174, 4378, 71, 1066, 1068, 915,
-1174, -1174, 4378, 971, -1174, 761, -1174, 751, -16, -1174,
-1174, 79, -1174, -1174, 871, 334, 79, -1174, 466, -1174,
1579, 79, 79, 62, -1174, -1174, -1174, 1093, 1790, -1174,
-1174, -1174, 1087, 5034, 237, 4241, 1101, 2545, 375, -1174,
473, -1174, -1174, -1174, -1174, 1108, -1174, -1174, -1174, -1174,
-1174, -1174, -5, 400, 5291, 5059, -1174, 4241, -1174, -1174,
5291, 619, -1174, -1174, -1174, 5291, 1109, 924, -1174, -1174,
4241, -1174, -1174, -1174, -1174, -1174, -1174, 87, -1174, -1174,
1007, -1174, 360, -1174, 1122, 1111, 1123, 934, 1120, 1124,
1042, 1125, -1174, 1049, 501, 313, 313, -1174, -1174, -1174,
-1174, -1174, -1174, -1174, 195, -1174, -1174, -1174, -1174, -1174,
483, -1174, -1174, -1174, -1174, 1133, 966, -1174, 1126, 958,
961, -1174, -1174, -16, -1174, -1174, 403, -1174, 801, 972,
341, -1174, -1174, -1174, 748, 475, 62, -1174, -1174, -1174,
-1174, 558, 1825, -1174, -1174, -1174, -1174, 1153, -1174, -5,
1051, -1174, 977, 660, -1174, 2677, -5, -1174, -1174, 5095,
-1174, -1174, -1174, -1174, -1174, 276, -1174, 1151, 115, -1174,
2545, 1143, 984, -1174, 5291, 2583, -1174, 1870, -1174, -1174,
-1174, 5120, -1174, -1174, 984, -1174, -1174, -1174, 429, 4289,
635, 1127, 308, -1174, -1174, 830, -1174, 975, -1174, 976,
-1174, 852, 852, 1155, 1163, -1174, 1076, 25, 403, 1079,
411, 1157, -1174, 3126, 3126, 1168, 3126, 3126, -1174, 1165,
1312, 503, -1174, 990, -1174, -1174, -1174, -1174, -1174, -1174,
-1174, 1020, 629, -1174, -1174, 1072, -1174, -1174, -1174, 1579,
2392, -1174, 1164, 27, -1174, 1169, -1174, -1174, 2545, 1187,
-1174, -1174, -1174, -1174, -1174, -1174, 2066, -1174, -1174, -5,
1178, -1174, -1174, 5256, -1174, 626, 400, -1174, -1174, 1008,
-1174, -1174, -1174, -1174, -1174, 4241, 4241, -1174, -1174, -1174,
-1174, -1174, -1174, 1190, 1073, 1194, -1174, 2097, -1174, -1174,
-1174, 473, -1174, -1174, 635, -1174, -1174, -1174, -1174, -1174,
48, 1097, 1118, -1174, -1174, -1174, -1174, 1195, -1174, -1174,
-1174, -1174, -1174, 1042, -1174, 360, 360, 899, -1174, 403,
-1174, 1075, 1047, 1128, 1130, -1174, 403, -1174, 4357, -1174,
-1174, 461, -1174, -1174, -1174, -1174, 1200, -1174, 1201, -1174,
-1174, -1174, 1202, 1223, -1174, -1174, -1174, 1048, -1174, -1174,
1153, -1174, -1174, -1174, -1174, -1174, -1174, 1214, -1174, -1174,
-1174, 77, -1174, 1227, -1174, -1174, -1174, -1174, -1174, -1174,
-1174, -1174, -1174, 1222, -1174, 4241, -1174, 812, 721, 4241,
-1174, -1174, -1174, -1174, -1174, 721, 4241, 1053, 1060, -1174,
-1174, 1070, -1174, 1074, -1174, 721, 1234, 4241, 4241, 1237,
-1174, -1174, -1174, 1240, 651, -1174, -1174, -1174, -1174, -1174,
1244, -1174, 984, -1174, 5150, 5175, 2968, 1245, 2968, -1174,
-1174, 2968, 733, -1174, -1174, -1174, 1248, 110, -1174, 110,
-1174, -1174, -1174, 830, 830, 693, 66, 2583, -1174, 3463,
403, 1119, 403, -1174, -1174, 1208, -1174, -1174, 1080, 1196,
1077, 734, -1174, 3889, -1174, -1174, 1553, -1174, 503, -1174,
1121, -1174, -1174, 2545, -1174, 1082, 353, 1044, -1174, 333,
-1174, -1174, 5291, -1174, -1174, -1174, -1174, 473, 5291, 473,
5291, -1174, -1174, -1174, -1174, 473, 721, 5291, 5291, 721,
718, 5256, -1174, 4241, 1246, -1174, -1174, -1174, -1174, -1174,
1249, 2463, 89, 473, -1174, -1174, 123, 1253, -1174, -1174,
24, -1174, -1174, 259, -1174, -1174, -1174, 2132, 1247, 1257,
-1174, -1174, 1258, -1174, -1174, 483, 2609, 1170, 403, -1174,
565, -1174, -1174, -1174, -1174, 272, -1174, -1174, -1174, 481,
-1174, 1312, -1174, 1276, 1255, -1174, -1174, 1121, 1113, -1174,
-1174, 1044, -1174, 1278, 473, 959, -1174, 724, 762, 767,
1266, 1019, -1174, 791, -5, -1174, 2968, 2807, -1174, 4241,
4241, -1174, 3642, 1254, 786, -1174, -1174, -1174, -1174, -1174,
2174, -1174, -1174, -1174, 5291, -1174, -1174, -1174, 1280, 1553,
-1174, 1170, 1279, -1174, -1174, 1206, -1174, 1275, -1174, -1174,
-1174, 403, -1174, 1208, -1174, 1209, 959, 721, 2545, -1174,
-1174, -1174, -1174, -1174, 1273, 1274, -1174, -1174, 1301, -1174,
-1174, 5211, 5236, -1174, 1288, 397, 123, -1174, 1300, 1303,
-1174, 2583, -1174, -1174, -1174, 1132, 744, -1174, -1174, 4433,
1553, -1174, -1174, 503, 473, -1174, 3069, 721, 721, 2968,
-1174, -1174, -1174, -1174, -1174, 2968, 116, -1174, 2873, 1294,
1300, -1174, -1174, 1295, 3889, 1305, -1174, -1174, -1174, 1255,
1206, 1207, -1174, 473, 473, -1174, 1307, -1174, 81, -1174,
-1174, 3199, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174,
882, -1174, -1174, -1174, -1174, -1174, 1310, 1212, -1174, 4241,
-1174, 117, -1174, -1174, -1174, 1158, 503, 1319, -1174, 4662,
61, 1184, 1323, -1174, 1158, -1174, 790, 1138, 4241, 1166,
1159, -1174, 1166, -1174, -1174, 1170, -1174, -1174, 1150, 809,
-1174, 5266, 1328, -1174, 1330, -1174, -1174, 1138, -1174, 1166,
-1174, -1174, -1174, 1333, -1174
};
/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
Performed when YYTABLE does not specify something else to do. Zero
means the default is an error. */
static const yytype_uint16 yydefact[] =
{
0, 5, 14, 0, 14, 0, 33, 25, 1, 0,
33, 2, 668, 0, 652, 652, 666, 0, 652, 0,
652, 0, 852, 667, 0, 7, 594, 607, 597, 598,
599, 600, 601, 602, 603, 604, 605, 606, 608, 609,
610, 652, 0, 669, 672, 675, 676, 677, 673, 674,
678, 679, 0, 16, 15, 28, 0, 652, 652, 0,
653, 0, 701, 702, 0, 0, 0, 0, 654, 637,
852, 0, 0, 0, 660, 634, 650, 651, 0, 852,
117, 0, 590, 591, 588, 850, 589, 0, 854, 0,
117, 853, 95, 97, 91, 77, 8, 9, 75, 10,
11, 12, 14, 652, 595, 852, 670, 856, 4, 27,
26, 0, 36, 3, 0, 0, 640, 641, 642, 625,
117, 0, 0, 117, 0, 305, 0, 638, 117, 657,
617, 0, 0, 631, 0, 305, 0, 635, 612, 117,
117, 626, 0, 0, 0, 0, 0, 0, 647, 97,
86, 0, 0, 80, 79, 78, 81, 596, 644, 0,
117, 857, 0, 0, 0, 29, 648, 0, 703, 643,
34, 698, 630, 0, 663, 307, 620, 639, 318, 305,
117, 0, 0, 0, 661, 615, 305, 636, 0, 852,
0, 0, 0, 0, 0, 0, 0, 0, 460, 0,
289, 575, 0, 0, 563, 0, 0, 0, 0, 0,
564, 290, 0, 0, 574, 523, 0, 560, 561, 562,
571, 592, 471, 475, 476, 291, 513, 0, 459, 0,
466, 521, 472, 474, 118, 514, 522, 518, 517, 519,
515, 520, 0, 0, 0, 855, 622, 0, 305, 102,
104, 108, 106, 0, 98, 0, 100, 101, 484, 0,
93, 97, 94, 436, 438, 440, 439, 97, 0, 852,
645, 0, 652, 671, 23, 22, 20, 21, 17, 18,
24, 32, 31, 0, 852, 37, 13, 711, 0, 711,
0, 0, 0, 655, 425, 423, 0, 0, 322, 482,
0, 309, 308, 314, 311, 327, 325, 434, 435, 483,
329, 565, 479, 478, 480, 477, 481, 305, 471, 0,
231, 319, 320, 618, 611, 707, 0, 706, 682, 632,
305, 613, 628, 117, 505, 509, 511, 0, 593, 507,
506, 461, 0, 0, 0, 0, 0, 467, 462, 0,
0, 537, 464, 463, 0, 465, 0, 541, 524, 0,
572, 529, 97, 0, 0, 0, 0, 582, 583, 0,
473, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 493, 491, 495, 539, 851, 0,
684, 305, 123, 0, 96, 97, 103, 105, 109, 107,
88, 110, 0, 0, 119, 437, 0, 83, 82, 85,
84, 448, 665, 0, 0, 30, 38, 117, 0, 36,
0, 0, 685, 827, 831, 685, 305, 632, 427, 0,
0, 567, 566, 0, 306, 310, 316, 317, 313, 0,
0, 621, 318, 658, 255, 0, 263, 0, 0, 291,
0, 0, 652, 265, 318, 236, 235, 238, 237, 240,
261, 241, 239, 318, 632, 708, 0, 662, 616, 632,
0, 627, 97, 81, 508, 0, 0, 0, 534, 0,
0, 0, 468, 0, 0, 548, 0, 0, 542, 544,
0, 573, 0, 451, 0, 0, 450, 0, 456, 0,
587, 585, 586, 584, 488, 487, 489, 500, 498, 499,
497, 502, 490, 501, 504, 503, 486, 0, 0, 0,
516, 540, 0, 0, 318, 121, 0, 318, 0, 99,
0, 441, 130, 120, 130, 0, 449, 0, 19, 0,
110, 704, 0, 0, 717, 0, 699, 0, 0, 0,
681, 846, 840, 847, 848, 849, 845, 0, 832, 833,
0, 841, 680, 664, 656, 433, 0, 430, 432, 397,
0, 0, 0, 422, 0, 0, 332, 395, 398, 400,
411, 393, 396, 421, 394, 323, 442, 445, 444, 443,
315, 312, 328, 331, 326, 234, 130, 318, 0, 243,
287, 288, 535, 0, 242, 252, 244, 247, 245, 248,
0, 0, 318, 232, 0, 259, 0, 262, 321, 619,
130, 614, 117, 0, 97, 528, 0, 0, 0, 0,
527, 525, 526, 0, 550, 538, 549, 0, 454, 547,
0, 543, 346, 452, 453, 0, 0, 494, 492, 496,
683, 0, 229, 124, 126, 0, 318, 130, 0, 111,
485, 0, 92, 171, 76, 447, 446, 46, 0, 53,
0, 0, 39, 43, 649, 764, 0, 0, 0, 0,
811, 35, 764, 0, 828, 0, 830, 0, 0, 426,
431, 0, 420, 419, 406, 0, 0, 428, 0, 424,
0, 0, 0, 0, 409, 407, 408, 0, 0, 659,
256, 228, 0, 0, 0, 0, 0, 318, 0, 293,
469, 470, 270, 272, 266, 0, 273, 233, 260, 257,
633, 629, 346, 0, 532, 0, 531, 0, 558, 551,
557, 0, 553, 455, 546, 545, 0, 0, 292, 457,
0, 305, 81, 125, 122, 87, 89, 0, 131, 172,
176, 60, 0, 61, 58, 0, 55, 54, 0, 0,
50, 0, 731, 0, 0, 652, 652, 843, 844, 802,
803, 739, 738, 705, 0, 734, 740, 741, 737, 757,
814, 762, 799, 805, 842, 801, 0, 813, 0, 0,
0, 810, 700, 0, 686, 693, 0, 694, 0, 0,
0, 688, 834, 835, 836, 0, 0, 404, 402, 403,
417, 0, 397, 336, 429, 334, 344, 333, 339, 346,
399, 401, 0, 0, 410, 0, 346, 286, 536, 0,
253, 246, 577, 578, 249, 576, 579, 297, 0, 277,
318, 0, 130, 530, 533, 318, 556, 0, 552, 348,
347, 0, 623, 97, 130, 113, 117, 112, 0, 0,
0, 0, 201, 63, 62, 0, 64, 0, 40, 0,
59, 0, 0, 0, 0, 800, 0, 0, 0, 0,
0, 735, 732, 0, 0, 0, 0, 0, 765, 0,
0, 823, 812, 0, 714, 712, 829, 690, 691, 692,
696, 695, 0, 687, 838, 837, 418, 405, 416, 0,
0, 345, 0, 0, 412, 0, 227, 264, 318, 0,
580, 581, 299, 294, 268, 271, 0, 258, 510, 346,
0, 555, 554, 0, 458, 632, 0, 90, 115, 0,
114, 165, 170, 168, 169, 0, 0, 167, 162, 166,
161, 164, 163, 0, 0, 0, 132, 133, 135, 134,
142, 141, 139, 140, 173, 174, 177, 203, 117, 117,
0, 198, 195, 127, 202, 67, 65, 0, 66, 68,
69, 70, 56, 50, 57, 0, 0, 0, 44, 0,
751, 0, 0, 0, 0, 709, 0, 733, 764, 766,
769, 0, 768, 767, 755, 777, 0, 798, 763, 772,
775, 796, 0, 824, 825, 715, 718, 0, 689, 839,
335, 343, 342, 341, 340, 414, 415, 0, 324, 254,
250, 0, 97, 0, 267, 284, 285, 278, 280, 281,
282, 279, 283, 0, 559, 0, 358, 0, 0, 0,
388, 389, 390, 391, 392, 0, 0, 0, 0, 385,
370, 0, 372, 0, 374, 0, 0, 0, 0, 0,
379, 380, 382, 0, 0, 350, 354, 355, 356, 357,
364, 624, 130, 117, 0, 0, 192, 0, 192, 136,
175, 192, 0, 197, 200, 270, 0, 201, 199, 201,
196, 47, 41, 0, 0, 0, 0, 318, 742, 764,
0, 0, 744, 710, 736, 789, 815, 820, 0, 0,
0, 0, 817, 764, 797, 773, 0, 804, 0, 718,
713, 697, 413, 318, 298, 0, 0, 0, 300, 0,
274, 512, 368, 362, 360, 361, 359, 365, 369, 366,
367, 353, 352, 371, 373, 375, 0, 378, 377, 0,
0, 0, 349, 0, 0, 116, 137, 138, 193, 194,
0, 179, 0, 191, 189, 190, 0, 0, 178, 211,
0, 209, 212, 0, 277, 128, 129, 0, 0, 0,
52, 51, 0, 752, 758, 814, 0, 814, 0, 743,
0, 770, 821, 819, 822, 0, 816, 745, 756, 0,
748, 0, 786, 776, 787, 781, 826, 716, 721, 719,
251, 0, 304, 303, 386, 301, 295, 0, 0, 0,
0, 0, 351, 0, 346, 145, 192, 180, 182, 0,
0, 188, 192, 0, 0, 146, 144, 204, 210, 207,
0, 74, 71, 42, 73, 49, 48, 45, 0, 0,
753, 814, 0, 790, 792, 793, 818, 749, 746, 774,
779, 0, 778, 789, 722, 0, 302, 0, 318, 277,
269, 275, 376, 381, 0, 0, 363, 230, 181, 184,
183, 0, 0, 148, 0, 156, 0, 143, 213, 0,
206, 318, 759, 761, 754, 0, 0, 771, 747, 764,
0, 788, 782, 0, 387, 296, 0, 0, 0, 192,
186, 187, 149, 157, 158, 192, 0, 147, 0, 0,
214, 215, 274, 0, 764, 0, 794, 795, 750, 787,
793, 723, 276, 384, 383, 185, 0, 151, 0, 225,
226, 0, 218, 221, 222, 223, 220, 224, 205, 216,
0, 72, 760, 791, 780, 783, 0, 725, 150, 0,
568, 159, 217, 219, 208, 806, 0, 0, 720, 0,
0, 0, 0, 784, 807, 808, 0, 0, 0, 159,
0, 569, 159, 160, 152, 814, 809, 724, 729, 0,
727, 0, 0, 570, 0, 785, 730, 0, 726, 159,
153, 154, 728, 0, 155
};
/* YYPGOTO[NTERM-NUM]. */
static const yytype_int16 yypgoto[] =
{
-1174, -1174, 1349, -1174, 318, -1174, -1174, -1174, -1042, 940,
-1174, -1174, -1174, -1174, -1174, 936, -1174, -1174, -1174, -1174,
-1174, -1174, -1174, -1174, 363, -1174, 365, 366, -636, -229,
-302, -1174, -1174, -1174, -1174, 100, -469, -1174, -1174, -1174,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -80, -1174,
-1174, -1174, -1174, 817, -1174, -1174, -1174, -89, -1174, -1174,
-394, -1174, -1174, 702, -528, -1174, -1174, -1174, -1174, 398,
-1174, -1174, 58, -1174, -1174, -776, -1174, -1174, -1174, -1174,
-1174, -1174, -1069, -1174, -1174, -1120, -1174, -1174, 384, -1174,
391, -435, -1174, -1174, -1174, -1174, -1174, 185, -1174, -1174,
39, -1174, 16, -714, -353, -1174, -167, -1174, -1174, -1174,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174,
-1174, -1174, 922, -1174, -1174, -1174, -1174, -1174, 277, -594,
41, -1174, -1077, -1174, -431, -1174, 935, -1174, -1174, -1174,
-1174, -1174, -1174, -1174, -1174, -127, -1174, -1174, -1174, -1174,
923, 552, -123, -1174, -1174, -150, -1174, -1174, -1174, 471,
-1174, -1174, 469, 470, -723, -1174, -1174, 218, -1174, -1174,
-1174, -1174, -800, -1174, -563, -486, 684, 690, 587, 826,
-411, -1174, -1174, -1174, -1174, -276, -407, -1174, 1139, 956,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, 1107, -158,
-1174, -1174, -77, -1174, 1, -1174, -1174, -1174, -1174, -1174,
-1174, -210, 1063, -426, -1174, -133, -1174, -1174, -313, 233,
-1174, -1174, -1174, 554, -1174, 317, 595, -1174, -1174, 474,
764, -1174, -1174, -1174, -1174, -21, -1174, -129, -1174, 1387,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -399,
-1174, 1338, -1174, 1346, 1355, 1148, -1174, -1174, 1277, 6,
-1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174, -1174,
-1174, -1174, -1174, 1259, -1174, -1174, -1174, -1174, 994, -1174,
511, -1174, -1174, -1174, -1174, -46, -1174, -1174, -1174, -1174,
51, -1174, 1135, -1174, -1174, 286, -1174, -1174, -1174, -1174,
-1174, 9, 745, -1174, -1174, 420, -1174, -1174, 85, -1174,
-1174, -1097, -1174, -1174, -1174, -1174, -1174, -1174, -1174, 314,
-1174, -1174, -1174, -1174, -1174, 211, -1174, -1174, -1174, -1173,
-1174, -1174, -1174, -1174, 88, 157, 92, 235, -1052, -817,
-1174, -1174, -1054, -1174, -1151, -1174, 224, -1174, 60, -1174,
897, 901, -1174, -1174, 756, 644, -1174, -868, -380, -6,
8, -59, -1174
};
/* YYDEFGOTO[NTERM-NUM]. */
static const yytype_int16 yydefgoto[] =
{
-1, 3, 5, 96, 6, 7, 54, 111, 278, 279,
55, 112, 165, 24, 288, 166, 285, 539, 672, 993,
1197, 770, 1117, 673, 884, 765, 766, 767, 762, 875,
987, 1263, 1311, 97, 156, 652, 267, 268, 408, 99,
248, 527, 864, 100, 152, 261, 101, 149, 466, 254,
255, 256, 257, 529, 757, 867, 868, 141, 142, 532,
394, 656, 524, 653, 662, 663, 869, 966, 967, 968,
969, 1254, 1255, 1335, 1336, 1392, 970, 760, 870, 974,
872, 1101, 1180, 1247, 1298, 1181, 1182, 1109, 981, 1107,
982, 983, 984, 1102, 1308, 1309, 1190, 1191, 1339, 1340,
1341, 1361, 1362, 710, 711, 752, 712, 454, 455, 717,
456, 718, 929, 1143, 457, 716, 928, 458, 597, 850,
616, 459, 460, 603, 461, 611, 724, 1043, 848, 935,
1237, 1291, 936, 1047, 599, 225, 361, 362, 462, 847,
1042, 1288, 933, 1041, 1148, 174, 175, 300, 301, 302,
320, 321, 303, 433, 707, 322, 440, 439, 592, 575,
700, 919, 827, 828, 748, 943, 1084, 1085, 1086, 1087,
1088, 1089, 1233, 1090, 576, 577, 578, 579, 834, 580,
305, 430, 429, 699, 566, 829, 306, 262, 263, 585,
409, 410, 226, 227, 228, 229, 230, 719, 231, 232,
233, 308, 309, 402, 489, 518, 517, 519, 472, 473,
387, 235, 345, 1185, 714, 236, 485, 520, 358, 490,
635, 636, 741, 742, 855, 237, 312, 1381, 1402, 238,
239, 844, 845, 369, 370, 240, 86, 241, 25, 26,
27, 28, 186, 469, 29, 330, 30, 179, 464, 31,
317, 32, 391, 945, 33, 34, 35, 36, 37, 467,
136, 78, 126, 72, 133, 159, 89, 286, 79, 66,
38, 125, 427, 178, 596, 39, 135, 329, 293, 40,
41, 42, 162, 43, 44, 45, 46, 47, 550, 810,
811, 911, 48, 289, 682, 67, 49, 287, 675, 50,
781, 782, 418, 1026, 1139, 1140, 1229, 1285, 1377, 1388,
1409, 1410, 783, 784, 1008, 785, 786, 787, 1218, 1219,
1319, 788, 1119, 1133, 1203, 1344, 1204, 789, 900, 790,
898, 1125, 1275, 1018, 1221, 1019, 1136, 1223, 1320, 1224,
1283, 1350, 1385, 1405, 1282, 1211, 1317, 1020, 791, 792,
1393, 1394, 544, 798, 899, 1131, 1132, 1022, 1023, 422,
423, 425, 557, 558, 559, 813, 560, 793, 794, 795,
160, 91, 108
};
/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
positive, shift that token. If negative, reduce the rule whose
number is the opposite. If YYTABLE_NINF, syntax error. */
static const yytype_int16 yytable[] =
{
85, 148, 120, 841, 624, 280, 664, 123, 184, 851,
533, 319, 534, 151, 120, 87, 604, 725, 565, 601,
61, 601, 568, 281, 73, 304, 80, 134, 564, 1187,
90, 169, 1188, 1024, 172, 769, 1220, 109, 359, 177,
1257, 478, 310, 500, 561, 310, 316, 105, 722, 316,
187, 188, 323, 1036, 1268, 120, 1270, 51, 614, 331,
1, 1248, 1000, 551, 114, 619, 1105, 1206, 709, 247,
621, 270, 620, 832, 521, 265, 1009, 1010, 128, 1012,
1013, 478, 679, 1021, 1225, 570, 695, 139, 571, 796,
106, 324, 730, 1201, 85, 435, 1313, 572, 642, 1379,
170, 85, 548, 85, 1144, 1235, 921, 1249, 1250, 168,
553, 479, 573, 926, 865, 691, 171, 1260, 173, 746,
1314, 395, 326, 85, 98, 74, 1299, 1300, 1390, 755,
692, 266, 657, 681, 1357, 825, 937, 554, 243, 1145,
181, 1252, 934, 234, 76, 825, 747, 1349, 574, 77,
68, 627, 438, 567, 315, 565, 977, 315, -646, 568,
85, 85, 85, 298, 1146, 615, 555, 1400, 75, 310,
283, 654, 4, 316, 88, 325, 327, 328, 436, 437,
688, 404, 290, 1304, 182, 265, 351, 406, 556, 1286,
441, 334, 337, 69, 339, 340, 76, 333, 344, 291,
541, 77, 1001, 468, 647, 815, 649, 891, 283, 1355,
821, 70, 1326, 51, 1039, 549, 1053, 1225, 1037, 480,
282, 892, 1348, 85, 360, 1189, 223, 224, 365, 732,
366, 723, 223, 224, 401, 600, 110, 600, 390, 501,
502, 266, 503, 2, 471, 995, 996, 1220, 1253, 723,
223, 224, 1401, 833, 1415, 356, 280, 8, 680, 480,
403, 542, 416, 107, 523, 797, 1356, 880, 1225, 411,
1226, 546, 1380, 1358, 1147, 595, 82, 83, 413, 84,
1251, 315, 492, 863, 866, 591, 1259, 613, 980, 565,
690, 336, 417, 568, 82, 83, 11, 84, 1391, 563,
316, 584, 310, 654, 589, 85, 316, 561, 814, 310,
584, 584, 590, 316, 71, 526, 723, 223, 224, 589,
465, 310, 10, 153, 939, 316, 284, 676, 540, 633,
310, 1395, 542, 258, 316, 154, 947, 930, 491, 852,
1406, 701, 1274, 59, 476, 1127, 259, 481, 357, 1236,
483, 484, 912, 582, 977, 487, 587, 655, 143, 260,
658, 820, 582, 582, 543, 495, 1238, 134, 913, 1239,
56, 587, 504, 505, 506, 507, 508, 509, 510, 511,
512, 513, 514, 515, 1232, 677, 1106, 678, 64, 1021,
144, 310, 623, 873, 310, 316, 155, 1128, 316, 115,
258, 838, 62, 530, 1021, 978, 842, 63, 315, 583,
249, 536, 588, 259, 315, 639, 392, 1129, 583, 583,
157, 315, 634, 814, 602, 640, 602, 588, 909, 1230,
979, 60, 1333, 315, 915, 543, 843, 316, 65, 975,
949, 641, 315, 973, 601, 727, 158, 250, 1347, 1130,
251, 52, 113, 726, 62, 1351, 950, 60, 610, 63,
723, 223, 224, 81, 310, 88, 1334, 822, 316, 121,
53, 258, 570, 82, 83, 571, 84, 249, 823, 310,
628, 629, 701, 316, 572, 192, 980, 637, 1126, 655,
132, 88, 311, 1277, 824, 311, 167, 367, 645, 573,
607, 85, 916, 315, 167, 368, 315, 1278, 565, 565,
252, 122, 568, 568, 250, 608, 650, 251, 1024, 648,
570, 1297, 249, 310, 88, 82, 83, 316, 84, 222,
223, 224, 572, 731, 1127, 574, 665, 124, 666, 258,
1004, 973, 70, 1100, 733, 315, 1091, 573, 601, 693,
583, 583, 1092, 192, 222, 223, 224, 82, 83, 250,
84, 874, 251, 893, 1174, 701, 129, 82, 83, 584,
84, 316, 82, 83, 1325, 84, 315, 252, 130, 584,
393, 88, 551, 574, 310, 918, 1128, 138, 316, 721,
92, 315, 82, 83, 167, 84, 222, 223, 224, 713,
82, 83, 894, 84, 93, 140, 1129, 895, 82, 83,
896, 84, 145, 431, 432, 381, 382, 13, 94, 311,
856, 582, 252, 1412, 862, 253, 1414, 734, 735, 553,
857, 582, 897, 271, 740, 315, 82, 83, 1130, 84,
667, 745, -97, 1423, 551, 146, 858, 763, 147, 313,
763, 272, 313, 598, 85, 668, 554, 669, 1272, 972,
600, 85, 1171, 82, 83, 221, 84, 222, 223, 224,
583, 923, 1195, 805, 1196, 583, 161, 583, 1172, 315,
583, 583, 196, 21, 197, 555, 924, 583, 940, 806,
726, 553, 95, 150, 807, 199, 315, 846, 82, 83,
670, 84, 310, -97, 879, 204, 316, 556, 777, 200,
778, 82, 83, 116, 84, 888, 839, 310, 554, 671,
1200, 316, 310, 808, 697, 698, 316, 210, 205, 206,
116, 82, 83, 221, 84, 222, 223, 224, 854, 117,
-97, 876, 1289, -97, 163, 1215, 311, 555, 211, 164,
1290, 861, 311, 85, 176, 444, 117, 972, 88, 311,
809, 1216, 82, 83, 600, 84, 1113, 1114, 887, 556,
777, 311, 778, 1287, 180, 88, 313, 948, 1287, 445,
311, 889, 890, 946, 446, 85, 183, 118, 804, 1292,
316, 316, 639, 185, 1293, 310, 131, 1306, 242, 316,
907, 1138, 640, -97, 118, 805, -97, 1052, 217, 218,
219, 1198, 1199, 1307, 315, 447, 245, 1407, 1296, 448,
1417, 806, 726, 551, 931, 216, 807, 551, 244, 315,
551, 1006, 82, 83, 315, 84, 1418, 246, 552, 269,
143, 311, 62, 292, 311, 449, 332, 63, 602, 602,
64, 296, 338, 297, 991, 808, 703, 341, 740, 342,
763, 763, 450, 704, 914, 705, 346, 85, 451, 85,
553, 706, 85, 85, 553, 85, 85, 553, 65, 85,
551, 452, 1002, 311, 1005, 347, 1184, 816, 1184, 1103,
1104, 1184, 809, 60, 817, 348, 818, 554, 315, 315,
1289, 554, 819, 313, 554, 201, 349, 315, 1384, 313,
593, 594, 1240, 350, 311, 1051, 313, 453, 204, 222,
223, 224, 222, 223, 224, 352, 555, 553, 313, 311,
555, 353, 354, 555, 1189, 223, 224, 313, 1346, 314,
210, 985, 314, 355, 1192, 388, 602, 389, 556, 777,
1202, 778, 556, 602, 554, 556, 1094, 1095, 396, 397,
-647, -647, 1149, -647, 398, 399, -647, 378, 400, 380,
414, 1184, 415, 311, 876, 876, 381, 382, 85, 419,
421, 426, 424, 555, 310, 85, 434, 85, 316, 280,
442, 463, 311, 1118, 367, 908, 428, 625, 313, 311,
1123, 313, 368, 214, 1175, 556, 1153, 443, 470, 1154,
310, 482, 1155, 493, 316, 516, 1156, 311, 522, 525,
528, 217, 218, 219, 220, 535, 547, 82, 83, 549,
84, 986, 1192, 609, 311, 726, 1184, 1184, 374, 375,
313, 376, 1184, 367, 377, 378, 1295, 380, 622, 82,
83, 368, 84, 761, 381, 382, 1152, 446, 643, 651,
1158, 646, 686, 116, 659, 661, 314, 1160, 685, 687,
696, 313, 701, 280, 708, 602, 728, 602, 1167, 1168,
602, 702, 715, 729, 750, 751, 313, 753, 756, 117,
-338, 758, 991, 991, -338, 759, 315, 768, 85, 85,
764, 85, 803, 799, -338, 800, -338, -338, 88, 835,
801, -647, 85, 836, 1207, 85, 1209, 840, -338, 1184,
-647, 62, 315, -338, 849, 1184, 63, 859, 860, 131,
313, 1052, 871, 877, 879, 880, 881, 118, 878, -647,
882, 883, 82, 83, 1343, 84, 222, 223, 224, 780,
886, 901, 311, 885, -338, 310, 780, 132, -338, 316,
602, 902, 904, 903, 920, 905, 910, 311, 922, 932,
938, 999, 311, 997, 313, 976, 992, 994, 310, 998,
1003, 1014, 316, 1007, -338, 85, 1011, 85, 1029, 1273,
1035, 313, 311, 314, 1025, 1038, 1027, 1052, 1264, 314,
85, -338, 1271, 1040, 1054, 1093, 314, -338, 1096, 1367,
311, 311, 1098, 311, 311, 978, 1097, 311, 314, 979,
-338, 1111, 1120, 1122, 1121, 602, 602, 314, 1134, 1137,
1135, 602, 1367, 181, 1138, 274, 311, 311, 275, 1051,
1142, 276, 1141, 1150, 277, 311, 223, 224, 85, 1151,
1301, 1302, 1166, 311, 1162, 1169, -338, 1161, 1170, 264,
85, 1163, 1173, 1186, 1194, 1164, 1208, 315, 1210, 1213,
779, 1212, 1244, 1265, 1228, 1321, 1245, 779, -6, 1231,
1256, 1214, 307, 1266, 1267, 307, 12, 1280, 314, 1287,
315, 314, 1281, 1294, 895, 1284, 1312, 1315, 85, 85,
1316, 1318, 1305, 14, 57, 1051, 16, 1323, 602, 313,
1327, 1328, 1329, 1015, 602, 1332, 17, 1366, 1338, 1342,
1368, 1371, 58, 85, 313, 311, 1345, 1376, 1386, 313,
314, 1016, 1373, 296, 1378, 297, 1387, 1397, 543, 1403,
1366, 1404, 1408, 19, 1416, 1017, 1420, 1391, 1421, 989,
1413, 1424, 20, 9, 538, 545, 1112, 674, 754, 22,
23, 314, 1115, 1116, 1337, 1099, 1110, 780, 780, 264,
780, 780, 1108, 102, 780, 1258, 314, 1383, 12, 1369,
1389, 617, 1193, 1370, 606, 830, 618, 925, 1030, 1242,
1034, 551, 831, 313, 313, 14, 103, 694, 16, 1411,
204, 405, 313, 917, 605, 167, 1243, 477, 17, 307,
1049, 942, 104, 137, 58, 127, 119, 412, 189, 562,
314, 273, 210, 1028, 420, 1227, 1422, 802, 1124, 1372,
311, 311, 1279, 1205, 311, 19, 311, 1374, 553, 1276,
1322, 1269, 1375, 812, 20, 684, 1396, 906, 683, 475,
311, 22, 23, 311, 0, 0, 0, 0, 371, 0,
311, 0, 0, 0, 314, 554, 0, 373, 374, 375,
988, 376, 0, 0, 377, 378, 379, 380, 0, 0,
0, 314, 780, 0, 381, 382, 0, 0, 779, 779,
0, 779, 779, 0, 555, 779, 0, 0, 0, 0,
0, 0, 0, 217, 218, 219, 220, 0, 0, 82,
83, 0, 84, 0, 0, 0, 556, 777, 0, 778,
0, 0, 0, 311, 0, 0, 0, 0, 0, 0,
0, 1048, 0, 0, 0, 0, 307, 581, 311, 0,
586, 384, 307, 0, 0, 0, 581, 581, 0, 307,
385, 0, 0, 0, 1222, 586, 0, 0, 0, 0,
0, 307, 0, 0, 0, 0, 0, 0, 0, 386,
307, 0, 771, 0, 296, 0, 297, 311, 0, 0,
826, 0, 0, 0, 258, 0, 311, 989, 989, 0,
0, 313, 0, 780, 0, 0, 0, 294, 295, 314,
296, 0, 297, 779, 0, 311, 0, 780, 0, 0,
780, 0, 0, 0, 314, 0, 0, 313, 0, 314,
0, 0, 0, 0, 0, 0, 0, 0, 311, 0,
0, 307, 551, 0, 307, 0, 311, 311, 0, 990,
0, 204, 0, 311, 0, 0, 167, 0, 0, 0,
0, 0, 0, 0, 201, 311, 0, 0, 0, 0,
0, 311, 0, 210, 0, 0, 0, 204, 0, 0,
0, 0, 0, 307, 0, 0, 0, 0, 311, 553,
780, 0, 0, 314, 314, 0, 0, 0, 0, 210,
299, 0, 314, 0, 0, 780, 0, 0, 0, 0,
1050, 0, 0, 0, 307, 0, 554, 0, 988, 988,
0, 0, 0, 0, 779, 0, 0, 720, 0, 307,
0, 0, 0, 0, 0, 0, 0, 0, 779, 0,
0, 779, 0, 0, 1049, 555, 0, 0, 0, 0,
0, 0, 0, 780, 217, 218, 219, 220, 0, 0,
82, 83, 214, 84, 0, 0, 0, 556, 777, 0,
778, 0, 313, 307, 0, 0, 0, 0, 0, 0,
217, 218, 219, 220, 0, 0, 82, 83, 221, 84,
222, 223, 224, 0, 0, 313, 0, 0, 0, 0,
0, 822, 0, 780, 780, 258, 570, 0, 0, 571,
1049, 779, 823, 0, 0, 581, 0, 307, 572, 192,
0, 0, 1364, 0, 0, 581, 779, 0, 780, 0,
0, 0, 0, 573, 307, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1364, 0, -337, 0, 0,
569, -337, 0, 0, 258, 570, 0, 0, 571, 0,
0, -337, 0, -337, -337, 1048, 0, 572, 192, 574,
0, 0, 0, 0, 779, -337, 0, 0, 0, 0,
-337, 941, 573, 0, 0, 0, 190, 990, 990, 0,
0, 314, 0, 0, 0, 0, 738, 0, 191, 192,
0, 193, 0, 194, 0, 0, 0, 0, 0, 0,
0, -337, 0, 0, 0, -337, 0, 314, 574, 0,
0, 258, 195, 0, 779, 779, 0, 196, 0, 197,
0, 1048, 0, 0, 294, 295, 198, 296, 0, 297,
199, -337, 0, 1363, 0, 0, 0, 0, 0, 779,
0, 0, 307, 0, 200, 201, 0, 0, -337, 0,
0, 0, 202, 203, -337, 0, 1363, 307, 204, 0,
0, 0, 307, 205, 206, 0, 0, -337, 0, 0,
0, 207, 0, 0, 208, 209, 971, 0, 0, 0,
210, 201, 0, 211, 0, 0, 298, 82, 83, 221,
84, 222, 223, 224, 204, 0, 0, 0, 0, 0,
0, 0, 0, -337, 0, 0, 0, 207, 212, 0,
0, 0, 0, 0, 0, 0, 210, 299, 0, 0,
213, 0, 0, 0, 1050, 0, 307, 307, 0, 0,
0, 0, 0, 0, 0, 307, 82, 83, 221, 84,
222, 223, 224, 214, 0, 215, 0, 0, 0, 0,
0, 0, 314, 0, 0, 0, 0, 0, 0, 0,
216, 217, 218, 219, 220, 0, 0, 82, 83, 221,
84, 222, 223, 224, 971, 314, 0, 0, 0, 214,
0, 0, 0, 0, 0, 192, 0, 296, 0, 297,
1050, 0, 1044, 0, 0, 0, 0, 217, 218, 219,
220, 0, 1365, 82, 83, 221, 84, 222, 223, 224,
951, 952, 953, 0, 954, 955, 956, 957, 958, 959,
960, 0, 0, 0, 0, 1365, 0, 961, 962, 0,
0, 0, 0, 1261, 0, 0, 0, 0, 190, 0,
0, 201, 0, 0, 196, 0, 197, 0, 1262, 0,
191, 192, 0, 193, 204, 194, 0, 199, 0, 0,
0, 0, 0, 0, 0, 1157, 0, 0, 0, 0,
0, 200, 1159, 0, 195, 0, 210, 0, 0, 196,
0, 197, 1165, 0, 0, 0, 0, 0, 198, 0,
205, 206, 199, 192, 0, 296, 0, 297, 0, 0,
1310, 0, 0, 1183, 0, 1183, 200, 201, 1183, 0,
211, 0, 0, 0, 202, 203, 0, 0, 0, 0,
204, 0, 0, 0, 307, 205, 206, 0, 0, 0,
0, 0, 0, 207, 0, 0, 208, 209, 0, 214,
1045, 1046, 210, 0, 0, 211, 0, 0, 0, 201,
307, 0, 0, 1234, 0, 0, 0, 217, 218, 219,
220, 0, 204, 82, 83, 221, 84, 0, 0, 0,
212, 0, 0, 1234, 0, 0, 1234, 1241, 0, 0,
0, 0, 213, 0, 210, 0, 0, 216, 1183, 0,
0, 0, 0, 0, 82, 83, 744, 84, 222, 223,
224, 190, 0, 0, 0, 214, 0, 215, 0, 0,
0, 0, 0, 191, 192, 0, 193, 0, 194, 0,
0, 0, 216, 217, 218, 219, 220, 0, 0, 82,
83, 221, 84, 222, 223, 224, 0, 195, 0, 0,
0, 0, 196, 0, 197, 0, 0, 214, 1045, 1046,
0, 198, 0, 1183, 1183, 199, 0, 0, 0, 1183,
0, 0, 0, 0, 0, 217, 218, 219, 220, 200,
201, 82, 83, 221, 84, 0, 0, 202, 203, 0,
0, 0, 0, 204, 0, 0, 0, 0, 205, 206,
0, 0, 0, 1031, 1324, 307, 207, 258, 0, 208,
209, 0, 0, 0, 1032, 210, 0, 0, 211, 0,
294, 295, 0, 296, 0, 297, 0, 0, 307, 0,
0, 1033, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 212, 1353, 1354, 1183, 0, 0, 569,
0, 0, 1183, 258, 570, 213, 0, 571, 0, 0,
-330, 0, 0, 0, -330, 0, 572, 192, 0, 0,
0, 0, 0, 0, -330, 0, 0, 201, 214, 0,
215, 573, 0, 0, 1246, 0, 0, 0, -330, 0,
204, -192, -192, -330, 0, 216, 217, 218, 219, 220,
0, 0, 82, 83, 221, 84, 222, 223, 224, 0,
0, 1178, 210, 299, 0, 0, 0, 574, 0, 0,
196, 0, 197, 0, -330, 0, 0, 258, -330, 0,
0, 0, 0, 199, 612, 0, 0, 0, 0, 1179,
294, 295, 0, 296, 0, 297, 0, 200, 0, 0,
0, 0, 0, 0, -330, 0, 0, 0, 0, 0,
258, 0, 0, 0, 0, 0, 205, 206, 0, 0,
0, -330, 0, 294, 295, 214, 296, -330, 297, 0,
0, 0, 0, 0, 0, 0, 211, 0, 0, 0,
-330, 0, 0, 217, 218, 219, 220, 201, 258, 82,
83, 221, 84, 222, 223, 224, 0, 0, 0, 0,
204, 294, 295, 0, 296, 0, 297, 0, 0, 0,
0, 0, 0, 207, 0, 0, -330, 0, 0, 0,
201, 0, 210, 299, 0, 0, 0, 0, 1016, 0,
296, 0, 297, 204, 0, 82, 83, 221, 84, 222,
223, 224, 1017, 0, 0, 0, 207, 0, 0, 0,
0, 0, 0, 216, -192, 210, 299, 0, 201, 0,
82, 83, 0, 84, 222, 223, 224, 0, 0, 0,
0, 204, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 258, 0, 207, 214, 95, 0, 551, 0,
0, 0, 0, 210, 299, 294, 295, 204, 296, 0,
297, 0, 167, 217, 218, 219, 220, 0, 0, 82,
83, 221, 84, 318, 223, 224, 0, 0, 214, 210,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 553, 217, 218, 219, 220,
0, 258, 82, 83, 221, 84, 318, 223, 224, 0,
0, 0, 201, 0, 294, 295, 214, 296, 0, 297,
0, 0, 554, 689, 0, 204, 0, 0, 0, 0,
0, 0, 0, 0, 217, 218, 219, 220, 207, 258,
82, 83, 221, 84, 318, 223, 224, 210, 299, 0,
0, 555, 294, 295, 0, 296, 0, 297, 0, 0,
217, 218, 219, 220, 0, 0, 82, 83, 0, 84,
0, 201, 0, 556, 777, 0, 778, 0, 0, 0,
0, 0, 0, 0, 204, -192, -192, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1178, 210, 299, 0, 201,
214, 0, 0, 0, 196, 0, 197, 0, 0, 0,
0, 0, 204, 0, 0, 0, 0, 199, 217, 218,
219, 220, 0, 1179, 82, 83, 221, 84, 222, 223,
224, 200, 0, 0, 210, 299, 0, 0, 0, 0,
0, 0, 192, 0, 296, 0, 297, 0, 0, 0,
205, 206, 0, 0, 0, 0, 0, 0, 0, 214,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
211, 0, 0, 0, 0, 0, 0, 217, 218, 219,
220, 0, 0, 82, 83, 221, 84, 222, 223, 224,
0, 0, 0, 0, 0, 190, 0, 214, 201, 0,
0, 0, 0, 0, 0, 0, 0, 191, 192, 0,
193, 204, 194, 0, 0, 217, 218, 219, 220, 0,
0, 82, 83, 221, 84, 222, 223, 224, 335, 0,
0, 195, 0, 210, 0, 0, 196, 0, 197, 0,
0, 0, 0, 0, 0, 198, 0, 216, -192, 199,
0, 0, 0, 0, 82, 83, 1178, 84, 222, 223,
224, 0, 0, 200, 201, 196, 0, 197, 0, 0,
0, 202, 203, 0, 0, 0, 0, 204, 199, 0,
0, 0, 205, 206, 1179, 0, 0, 0, 0, 0,
207, 0, 200, 208, 209, 0, 214, 1359, 1360, 210,
0, 0, 211, 0, 0, 0, 0, 0, 0, 0,
0, 205, 206, 0, 217, 218, 219, 220, 0, 0,
82, 83, 221, 84, 0, 0, 0, 212, 0, 0,
95, 211, 0, 0, 0, 0, 0, 0, 192, 213,
296, 0, 297, 373, 374, 375, 1352, 376, 0, 0,
377, 378, 379, 380, 0, 0, 0, 0, 0, 190,
381, 382, 214, 0, 215, 0, 0, 0, 0, 0,
0, 191, 192, 0, 193, 0, 194, 0, 0, 216,
217, 218, 219, 220, 363, 0, 82, 83, 221, 84,
222, 223, 224, 0, 201, 195, 0, 296, 0, 297,
196, 0, 197, 0, 0, 0, 0, 204, 216, 198,
0, 0, 0, 199, 0, 82, 83, 384, 84, 222,
223, 224, 364, 0, 0, 0, 385, 200, 201, 210,
0, 12, 0, 13, 0, 202, 203, 0, 0, 0,
0, 204, 0, 0, 0, 386, 205, 206, 14, 15,
0, 16, 0, 0, 207, 551, 0, 208, 209, 0,
0, 17, 0, 210, 204, 0, 211, 18, 192, 167,
296, 0, 297, 0, 0, 0, 1382, 0, 0, 0,
0, 0, 0, 0, 0, 0, 210, 0, 19, 0,
0, 212, 214, 1045, 1046, 0, 0, 20, 0, 21,
0, 0, 553, 213, 22, 23, 0, 0, 0, 0,
217, 218, 219, 220, 0, 0, 82, 83, 221, 84,
0, 190, 0, 0, 201, 0, 214, 0, 215, 554,
0, 738, 0, 191, 192, 0, 193, 204, 194, 0,
0, 0, 739, 216, 217, 218, 219, 220, 0, 0,
82, 83, 221, 84, 222, 223, 224, 195, 555, 210,
0, 0, 196, 0, 197, 0, 0, 217, 218, 219,
220, 198, 0, 82, 83, 199, 84, 0, 0, 0,
556, 777, -6, 778, 0, 0, 0, 0, 0, 200,
201, 0, 0, 0, 0, 0, 0, 202, 203, 0,
0, 0, 0, 204, 0, 0, 0, 0, 205, 206,
0, 0, 0, 0, 0, 0, 207, 0, 0, 208,
209, 0, 214, 1359, 1360, 210, 0, 0, 211, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
217, 218, 219, 220, 0, 0, 82, 83, 221, 84,
0, 0, 0, 212, 0, 0, 0, 0, 371, 0,
0, 0, 372, 0, 0, 213, 0, 373, 374, 375,
0, 376, 0, 0, 377, 378, 379, 380, 0, 0,
0, 0, 0, 190, 381, 382, 0, 0, 214, 0,
215, 383, 0, 0, 0, 191, 192, 0, 193, 0,
194, 0, 0, 0, 0, 216, 217, 218, 219, 220,
0, 0, 82, 83, 221, 84, 222, 223, 224, 195,
0, 0, 0, 0, 196, 0, 197, 0, 0, 0,
0, 0, 771, 198, 296, 0, 297, 199, -647, 374,
375, 384, 376, 0, 0, 377, 378, -647, 380, 0,
385, 200, 201, 0, 0, 381, 382, 0, 0, 202,
203, 0, 0, 0, 0, 204, 0, 0, 0, 386,
205, 206, 0, 0, 0, 0, 0, 0, 207, 0,
0, 208, 209, 0, 0, 0, 0, 210, 0, 0,
211, 0, 551, 0, 0, 0, 0, 0, 0, 0,
0, 204, 0, 0, 0, 0, 167, 0, 0, 0,
0, 0, 384, 0, 0, 212, 0, 0, 0, 0,
0, 385, 0, 210, 0, 0, 0, 213, 0, 0,
0, 0, 0, 343, 0, 0, 0, 0, 0, 553,
386, 0, 0, 0, 0, 0, 0, 190, 0, 0,
214, 0, 215, 0, 0, 0, 343, 0, 0, 191,
192, 0, 193, 0, 194, 0, 554, 216, 217, 218,
219, 220, 407, 0, 82, 83, 221, 84, 222, 223,
224, 0, 0, 195, 0, 0, 0, 0, 196, 0,
197, 0, 0, 0, 0, 555, 0, 198, 0, 0,
0, 199, 0, 0, 217, 218, 219, 220, 0, 0,
82, 83, 0, 84, 0, 200, 201, 556, 777, 1303,
778, 0, 0, 202, 203, 0, 0, 0, 0, 204,
1178, 0, 0, 0, 205, 206, 0, 0, 0, 196,
0, 197, 207, 0, 0, 208, 209, 0, 0, 0,
0, 210, 199, 0, 211, 0, 0, 0, 1179, 0,
0, 0, 0, 0, 0, 0, 200, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 212,
0, 0, 0, 0, 0, 205, 206, 0, 0, 0,
0, 213, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 211, 0, 0, 0, 190,
0, 0, 0, 0, 214, 0, 215, 0, 0, 0,
0, 191, 192, 0, 193, 0, 194, 0, 0, 0,
0, 216, 217, 218, 219, 220, 0, 0, 82, 83,
221, 84, 222, 223, 224, 195, 0, 0, 0, 0,
196, 0, 197, 0, 0, 0, 0, 0, 0, 198,
0, 0, 0, 199, 0, 0, 0, 0, 0, 0,
0, 0, 486, 0, 0, 0, 0, 200, 201, 0,
0, 0, 216, 0, 0, 202, 203, 0, 0, 82,
83, 204, 84, 222, 223, 224, 205, 206, 0, 0,
0, 0, 0, 0, 207, 0, 0, 208, 209, 0,
0, 0, 0, 210, 0, 0, 211, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 212, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 213, 0, 0, 0, 0, 771, 0,
296, 0, 297, 0, 0, 1217, 0, 0, 0, 0,
0, 190, 0, 0, 0, 0, 214, 0, 215, 0,
0, 0, 0, 191, 192, 0, 193, 0, 194, 0,
0, 774, 488, 216, 217, 218, 219, 220, 0, 0,
82, 83, 221, 84, 222, 223, 224, 195, 0, 0,
0, 0, 196, 0, 197, 0, 0, 0, 551, 0,
0, 198, 0, 0, 0, 199, 0, 204, 0, 0,
0, 0, 167, 0, 0, 0, 0, 0, 0, 200,
201, 0, 0, 0, 0, 0, 0, 202, 203, 210,
0, 0, 0, 204, 0, 0, 0, 0, 205, 206,
0, 0, 0, 0, 0, 553, 207, 0, 0, 208,
209, 0, 0, 0, 0, 210, 0, 0, 211, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 371, 554, 0, 0, 372, 0, 0, 0, 0,
373, 374, 375, 212, 376, 0, 0, 377, 378, 379,
380, 0, 0, 0, 0, 213, 0, 381, 382, 0,
0, 555, 0, 0, 383, 0, 0, 0, 0, 0,
217, 218, 219, 220, 0, 190, 82, 83, 214, 84,
215, 0, 0, 556, 777, 0, 778, 191, 192, 0,
193, 0, 194, 0, 0, 216, 217, 218, 219, 220,
494, 0, 82, 83, 221, 84, 222, 223, 224, 0,
0, 195, 0, 0, 384, 0, 196, 0, 197, 0,
0, 0, 371, 385, 0, 198, 372, 0, 0, 199,
0, 373, 374, 375, 0, 376, 0, 0, 377, 378,
379, 380, 386, 200, 201, 474, 0, 0, 381, 382,
0, 202, 203, 0, 0, 383, 0, 204, 0, 0,
0, 0, 205, 206, 0, 0, 0, 0, 0, 0,
207, 0, 0, 208, 209, 0, 0, 0, 0, 210,
0, 626, 211, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 384, 0, 212, 0, 0,
0, 0, 371, 0, 385, 0, 372, 0, 0, 213,
0, 373, 374, 375, 0, 376, 0, 0, 377, 378,
379, 380, 0, 386, 0, 496, 0, 190, 381, 382,
0, 0, 214, 0, 215, 383, 0, 0, 0, 191,
192, 0, 193, 0, 194, 0, 0, 0, 0, 216,
217, 218, 219, 220, 0, 0, 82, 83, 221, 84,
222, 223, 224, 195, 0, 0, 0, 0, 196, 0,
197, 0, 0, 0, 0, 0, 0, 198, 0, 0,
0, 199, 951, 952, 953, 384, 954, 955, 956, 957,
958, 959, 960, 0, 385, 200, 201, 0, 0, 961,
962, 0, 0, 202, 203, 0, 0, 0, 0, 204,
0, 0, 0, 386, 205, 206, 196, 0, 197, 0,
0, 0, 207, 0, 0, 208, 209, 963, 0, 199,
0, 210, 0, 0, 211, 0, 0, 0, 0, 0,
0, 0, 0, 200, 0, 0, 0, 0, 0, 0,
0, 0, 964, 0, 0, 0, 771, 0, 296, 212,
297, 0, 205, 206, 0, 0, 0, 0, 0, 0,
0, 213, 0, 0, 0, 0, 0, 771, 773, 296,
0, 297, 211, 0, 772, 0, 0, 0, 0, 774,
0, 0, 0, 0, 214, 0, 215, 0, 0, 773,
0, 965, 0, 0, 0, 775, 0, 776, 0, 0,
774, 216, 217, 218, 219, 220, 551, 0, 82, 83,
221, 84, 222, 223, 224, 204, 775, 0, 776, 0,
167, 0, 771, 0, 296, 0, 297, 551, 0, 0,
0, 0, 0, 0, 0, 0, 204, 210, 0, 0,
0, 167, 0, 0, 0, 0, 0, 0, 0, 216,
0, 0, 0, 553, 0, 774, 82, 83, 210, 84,
222, 223, 224, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 553, 0, 0, 0, 0, 0,
554, 0, 551, 0, 0, 0, 0, 0, 0, 0,
0, 204, 0, 0, 0, 0, 167, 0, 0, 0,
0, 554, 0, 0, 0, 0, 0, 0, 0, 555,
0, 0, 0, 210, 0, 0, 0, 0, 217, 218,
219, 220, 0, 0, 82, 83, 0, 84, 0, 553,
555, 556, 777, 0, 778, 0, 0, 0, 0, 217,
218, 219, 220, 0, 0, 82, 83, 0, 84, 0,
371, 0, 556, 777, 372, 778, 554, 0, 0, 373,
374, 375, 0, 376, 0, 0, 377, 378, 379, 380,
0, 0, 0, 0, 0, 0, 381, 382, 0, 0,
0, 0, 0, 383, 0, 555, 0, 0, 0, 0,
0, 0, 0, 0, 217, 218, 219, 220, 0, 0,
82, 83, 371, 84, 0, 0, 372, 556, 777, 497,
778, 373, 374, 375, 0, 376, 0, 0, 377, 378,
379, 380, 0, 0, 0, 498, 0, 499, 381, 382,
0, 0, 0, 384, 0, 383, 371, 0, 0, 0,
372, 0, 385, 1398, 0, 373, 374, 375, 0, 376,
0, 0, 377, 378, 379, 380, 0, 0, 0, 1399,
0, 386, 381, 382, 0, 0, 0, 0, 0, 383,
371, 0, 0, 0, 372, 0, 0, 0, 0, 373,
374, 375, 0, 376, 0, 384, 377, 378, 379, 380,
0, 0, 0, 531, 385, 0, 381, 382, 0, 0,
737, 0, 0, 383, 0, 371, 0, 0, 0, 372,
0, 0, 537, 386, 373, 374, 375, 0, 376, 384,
0, 377, 378, 379, 380, 0, 0, 0, 385, 0,
0, 381, 382, 0, 0, 0, 0, 0, 383, 0,
0, 371, 0, 0, 0, 372, 0, 386, 0, 0,
373, 374, 375, 384, 376, 0, 0, 377, 378, 379,
380, 0, 385, 0, 630, 0, 371, 381, 382, 0,
372, 0, 0, 0, 383, 373, 374, 375, 0, 376,
0, 386, 377, 378, 379, 380, 0, 0, 384, 631,
0, 0, 381, 382, 0, 0, 371, 385, 0, 383,
372, 0, 0, 0, 0, 373, 374, 375, 0, 376,
0, 0, 377, 378, 379, 380, 386, 0, 0, 632,
0, 371, 381, 382, 384, 372, 0, 0, 0, 383,
373, 374, 375, 385, 376, 0, 0, 377, 378, 379,
380, 0, 0, 0, 638, 0, 0, 381, 382, 384,
0, 0, 386, 0, 383, 0, 0, 371, 385, 0,
0, 372, 0, 0, 0, 0, 373, 374, 375, 0,
376, 0, 0, 377, 378, 379, 380, 386, 0, 384,
644, 0, 0, 381, 382, 0, 0, 0, 385, 0,
383, 0, 371, 660, 0, 0, 372, 0, 0, 0,
0, 373, 374, 375, 384, 376, 0, 386, 377, 378,
379, 380, 0, 385, 0, 0, 0, 371, 381, 382,
0, 372, 0, 0, 0, 383, 373, 374, 375, 0,
376, 0, 386, 377, 378, 379, 380, 0, 0, 0,
384, 0, 0, 381, 382, 0, 0, 371, 0, 385,
383, 372, 0, 0, 0, 0, 373, 374, 375, 0,
376, 0, 0, 377, 378, 379, 380, 0, 386, 0,
743, 0, 0, 381, 382, 384, 0, 0, 371, 0,
383, 0, 372, 0, 385, 736, 0, 373, 374, 375,
0, 376, 0, 0, 377, 378, 379, 380, 0, 0,
384, 749, 0, 386, 381, 382, 0, 0, 371, 385,
0, 383, 372, 0, 0, 0, 0, 373, 374, 375,
0, 376, 0, 0, 377, 378, 379, 380, 386, 0,
384, 837, 0, 371, 381, 382, 0, 372, 0, 385,
0, 383, 373, 374, 375, 0, 376, 0, 0, 377,
378, 379, 380, 0, 0, 0, 0, 0, 386, 381,
382, 384, 0, 0, 0, 0, 383, 0, 0, 371,
385, 0, 0, 372, 0, 0, 0, 0, 373, 374,
375, 0, 376, 0, 0, 377, 378, 379, 380, 386,
0, 384, 927, 0, 371, 381, 382, 0, 372, 0,
385, 853, 383, 373, 374, 375, 0, 376, 0, 0,
377, 378, 379, 380, 0, 0, 384, 944, 0, 386,
381, 382, 0, 0, 371, 385, 0, 383, 372, 0,
0, 0, 0, 373, 374, 375, 0, 376, 0, 0,
377, 378, 379, 380, 386, 0, 0, 1176, 0, 371,
381, 382, 384, 372, 0, 0, 0, 383, 373, 374,
375, 385, 376, 0, 0, 377, 378, 379, 380, 0,
0, 0, 0, 1177, 0, 381, 382, 384, 0, 0,
386, 0, 383, 0, 0, 371, 385, 0, 0, 372,
0, 0, 0, 0, 373, 374, 375, 0, 376, 0,
0, 377, 378, 379, 380, 386, 0, 384, 1330, 0,
371, 381, 382, 0, 372, 0, 385, 0, 383, 373,
374, 375, 0, 376, 0, 0, 377, 378, 379, 380,
0, 0, 384, 0, 1331, 386, 381, 382, 0, 0,
371, 385, 0, 383, 372, 0, 0, 0, 0, 373,
374, 375, 0, 376, 0, 0, 377, 378, 379, 380,
386, 0, 0, 1419, 0, 371, 381, 382, 384, 372,
0, 0, 0, 383, 373, 374, 375, 385, 376, 0,
0, 377, 378, 379, 380, 0, 0, 0, 0, 0,
0, 381, 382, 384, 0, 0, 386, 0, 383, 0,
0, 0, 385, 0, 0, 1055, 0, 0, 0, 0,
0, 0, 1056, 0, 0, 0, 1057, 0, 0, 0,
0, 386, 0, 384, 0, 0, 0, 0, 0, 0,
0, 0, 385, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 1058, 384, 0,
0, 386, 1059, 0, 0, 0, 0, 385, 0, 1060,
1061, 1062, 1063, 1064, 0, 1065, 1066, 0, 0, 0,
0, 0, 0, 0, 0, 0, 386, 1067, 1068, 0,
0, 0, 0, 0, 1069, 1070, 1071, 1072, 1073, 1074,
1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083
};
static const yytype_int16 yycheck[] =
{
21, 90, 61, 717, 473, 163, 534, 66, 135, 732,
404, 178, 406, 93, 73, 21, 447, 611, 429, 445,
14, 447, 429, 1, 18, 175, 20, 73, 427, 1098,
22, 120, 1101, 901, 123, 671, 1133, 1, 10, 128,
16, 1, 175, 1, 424, 178, 175, 41, 18, 178,
139, 140, 179, 26, 1205, 114, 1207, 6, 69, 186,
1, 1181, 37, 79, 58, 464, 18, 1119, 596, 149,
469, 160, 466, 11, 387, 152, 893, 894, 70, 896,
897, 1, 18, 900, 1136, 6, 572, 79, 9, 18,
12, 180, 620, 27, 115, 12, 1269, 18, 492, 18,
121, 122, 11, 124, 27, 1147, 829, 18, 19, 115,
126, 71, 33, 836, 27, 18, 122, 1194, 124, 124,
1271, 248, 181, 144, 24, 16, 1246, 1247, 11, 657,
33, 152, 526, 26, 18, 698, 850, 153, 144, 62,
103, 18, 27, 142, 87, 708, 151, 1320, 69, 92,
16, 71, 302, 429, 175, 566, 46, 178, 64, 566,
181, 182, 183, 80, 87, 176, 182, 106, 59, 302,
63, 524, 16, 302, 80, 181, 182, 183, 301, 302,
560, 261, 177, 1252, 147, 262, 207, 267, 204, 1231,
317, 190, 191, 59, 193, 194, 87, 189, 197, 194,
16, 92, 177, 330, 517, 691, 519, 12, 63, 1329,
696, 77, 1289, 162, 928, 124, 939, 1269, 191, 179,
198, 26, 1319, 244, 196, 201, 202, 203, 227, 623,
229, 201, 202, 203, 255, 445, 200, 447, 244, 197,
198, 262, 200, 184, 333, 881, 882, 1344, 125, 201,
202, 203, 191, 191, 1405, 18, 414, 0, 194, 179,
259, 77, 283, 185, 391, 194, 1335, 201, 1320, 268,
1138, 16, 191, 157, 197, 442, 197, 198, 272, 200,
191, 302, 362, 752, 197, 435, 27, 454, 178, 700,
566, 191, 284, 700, 197, 198, 185, 200, 181, 426,
429, 430, 435, 656, 433, 326, 435, 687, 688, 442,
439, 440, 435, 442, 180, 395, 201, 202, 203, 448,
326, 454, 4, 57, 852, 454, 181, 146, 417, 18,
463, 1385, 77, 5, 463, 69, 864, 61, 359, 733,
1394, 7, 1210, 129, 343, 73, 18, 346, 111, 16,
349, 350, 11, 430, 46, 354, 433, 524, 18, 31,
527, 27, 439, 440, 180, 364, 1166, 413, 27, 1169,
26, 448, 371, 372, 373, 374, 375, 376, 377, 378,
379, 380, 381, 382, 31, 204, 980, 206, 101, 1206,
50, 524, 472, 33, 527, 524, 130, 125, 527, 147,
5, 714, 93, 402, 1221, 97, 31, 98, 429, 430,
77, 410, 433, 18, 435, 1, 16, 145, 439, 440,
102, 442, 111, 803, 445, 11, 447, 448, 808, 1143,
122, 144, 35, 454, 814, 180, 61, 566, 129, 870,
11, 27, 463, 869, 870, 612, 61, 114, 1316, 177,
117, 43, 185, 611, 93, 1323, 27, 144, 452, 98,
201, 202, 203, 93, 597, 80, 69, 1, 597, 95,
62, 5, 6, 197, 198, 9, 200, 77, 12, 612,
479, 480, 7, 612, 18, 19, 178, 486, 27, 656,
129, 80, 175, 12, 28, 178, 93, 24, 497, 33,
1, 522, 27, 524, 93, 32, 527, 26, 919, 920,
177, 147, 919, 920, 114, 16, 522, 117, 1386, 518,
6, 1244, 77, 656, 80, 197, 198, 656, 200, 201,
202, 203, 18, 622, 73, 69, 535, 50, 537, 5,
129, 967, 77, 974, 624, 566, 945, 33, 974, 570,
571, 572, 946, 19, 201, 202, 203, 197, 198, 114,
200, 201, 117, 80, 1092, 7, 16, 197, 198, 698,
200, 700, 197, 198, 1288, 200, 597, 177, 16, 708,
180, 80, 79, 69, 717, 27, 125, 16, 717, 610,
39, 612, 197, 198, 93, 200, 201, 202, 203, 598,
197, 198, 119, 200, 53, 142, 145, 124, 197, 198,
127, 200, 148, 296, 297, 30, 31, 36, 67, 302,
1, 698, 177, 1399, 751, 180, 1402, 626, 627, 126,
11, 708, 149, 52, 633, 656, 197, 198, 177, 200,
1, 640, 16, 1419, 79, 85, 27, 668, 64, 175,
671, 70, 178, 18, 675, 16, 153, 18, 93, 869,
870, 682, 11, 197, 198, 199, 200, 201, 202, 203,
691, 11, 1107, 44, 1109, 696, 185, 698, 27, 700,
701, 702, 47, 102, 49, 182, 26, 708, 855, 60,
848, 126, 141, 16, 65, 60, 717, 718, 197, 198,
61, 200, 835, 77, 11, 88, 835, 204, 205, 74,
207, 197, 198, 35, 200, 774, 715, 850, 153, 80,
27, 850, 855, 94, 28, 29, 855, 110, 93, 94,
35, 197, 198, 199, 200, 201, 202, 203, 737, 61,
114, 762, 18, 117, 197, 11, 429, 182, 113, 128,
26, 750, 435, 774, 16, 16, 61, 967, 80, 442,
131, 27, 197, 198, 974, 200, 995, 996, 774, 204,
205, 454, 207, 11, 95, 80, 302, 866, 11, 40,
463, 775, 776, 863, 45, 806, 50, 109, 27, 27,
919, 920, 1, 16, 27, 928, 101, 11, 194, 928,
806, 11, 11, 177, 109, 44, 180, 936, 191, 192,
193, 1113, 1114, 27, 835, 76, 48, 27, 27, 80,
11, 60, 980, 79, 845, 190, 65, 79, 120, 850,
79, 890, 197, 198, 855, 200, 27, 16, 87, 156,
18, 524, 93, 91, 527, 106, 59, 98, 869, 870,
101, 21, 28, 23, 875, 94, 16, 18, 857, 18,
881, 882, 123, 23, 116, 25, 18, 888, 129, 890,
126, 31, 893, 894, 126, 896, 897, 126, 129, 900,
79, 142, 888, 566, 890, 18, 1096, 16, 1098, 978,
979, 1101, 131, 144, 23, 18, 25, 153, 919, 920,
18, 153, 31, 429, 153, 75, 18, 928, 26, 435,
439, 440, 194, 18, 597, 936, 442, 178, 88, 201,
202, 203, 201, 202, 203, 18, 182, 126, 454, 612,
182, 18, 18, 182, 201, 202, 203, 463, 194, 175,
110, 111, 178, 18, 1102, 27, 967, 148, 204, 205,
1117, 207, 204, 974, 153, 204, 955, 956, 109, 109,
14, 15, 1042, 17, 109, 109, 20, 21, 16, 23,
11, 1181, 200, 656, 995, 996, 30, 31, 999, 16,
78, 16, 18, 182, 1117, 1006, 26, 1008, 1117, 1147,
12, 12, 675, 999, 24, 194, 27, 27, 524, 682,
1006, 527, 32, 173, 1093, 204, 194, 26, 177, 197,
1143, 69, 200, 27, 1143, 201, 204, 700, 120, 16,
124, 191, 192, 193, 194, 11, 206, 197, 198, 124,
200, 201, 1190, 103, 717, 1193, 1246, 1247, 14, 15,
566, 17, 1252, 24, 20, 21, 27, 23, 142, 197,
198, 32, 200, 201, 30, 31, 1055, 45, 27, 91,
1059, 204, 27, 35, 18, 81, 302, 1066, 18, 11,
18, 597, 7, 1231, 29, 1096, 176, 1098, 1077, 1078,
1101, 30, 18, 16, 13, 16, 612, 26, 26, 61,
12, 48, 1113, 1114, 16, 84, 1117, 80, 1119, 1120,
201, 1122, 131, 37, 26, 37, 28, 29, 80, 16,
195, 87, 1133, 26, 1120, 1136, 1122, 16, 40, 1329,
96, 93, 1143, 45, 16, 1335, 98, 18, 204, 101,
656, 1260, 125, 11, 11, 201, 16, 109, 27, 115,
16, 99, 197, 198, 1311, 200, 201, 202, 203, 675,
101, 18, 835, 28, 76, 1288, 682, 129, 80, 1288,
1181, 195, 204, 37, 11, 204, 194, 850, 191, 18,
27, 95, 855, 18, 700, 48, 201, 201, 1311, 16,
101, 16, 1311, 26, 106, 1206, 18, 1208, 116, 1210,
26, 717, 875, 429, 204, 26, 176, 1326, 1197, 435,
1221, 123, 1208, 16, 26, 197, 442, 129, 18, 1338,
893, 894, 18, 896, 897, 97, 143, 900, 454, 122,
142, 26, 147, 95, 177, 1246, 1247, 463, 28, 27,
29, 1252, 1361, 103, 11, 191, 919, 920, 194, 1260,
26, 197, 194, 16, 200, 928, 202, 203, 1269, 27,
1249, 1250, 18, 936, 194, 18, 178, 204, 18, 152,
1281, 191, 18, 18, 16, 191, 147, 1288, 60, 73,
675, 191, 26, 26, 153, 1281, 27, 682, 26, 197,
27, 204, 175, 26, 26, 178, 34, 11, 524, 11,
1311, 527, 37, 27, 124, 182, 16, 18, 1319, 1320,
94, 26, 48, 51, 52, 1326, 54, 98, 1329, 835,
37, 37, 11, 1, 1335, 27, 64, 1338, 18, 16,
26, 26, 70, 1344, 850, 1008, 194, 120, 18, 855,
566, 19, 27, 21, 27, 23, 124, 18, 180, 155,
1361, 18, 204, 91, 194, 33, 18, 181, 18, 875,
191, 18, 100, 4, 414, 419, 993, 540, 656, 107,
108, 597, 997, 997, 1306, 967, 982, 893, 894, 262,
896, 897, 981, 29, 900, 1190, 612, 1361, 34, 1340,
1379, 459, 1105, 1342, 449, 701, 463, 835, 919, 1171,
920, 79, 702, 919, 920, 51, 52, 571, 54, 1398,
88, 262, 928, 816, 448, 93, 1173, 344, 64, 302,
936, 857, 25, 75, 70, 69, 61, 269, 141, 425,
656, 162, 110, 912, 289, 1139, 1417, 682, 1008, 1344,
1113, 1114, 1221, 1119, 1117, 91, 1119, 1349, 126, 1215,
1283, 1206, 1350, 687, 100, 548, 1386, 803, 547, 342,
1133, 107, 108, 1136, -1, -1, -1, -1, 4, -1,
1143, -1, -1, -1, 700, 153, -1, 13, 14, 15,
875, 17, -1, -1, 20, 21, 22, 23, -1, -1,
-1, 717, 1008, -1, 30, 31, -1, -1, 893, 894,
-1, 896, 897, -1, 182, 900, -1, -1, -1, -1,
-1, -1, -1, 191, 192, 193, 194, -1, -1, 197,
198, -1, 200, -1, -1, -1, 204, 205, -1, 207,
-1, -1, -1, 1206, -1, -1, -1, -1, -1, -1,
-1, 936, -1, -1, -1, -1, 429, 430, 1221, -1,
433, 87, 435, -1, -1, -1, 439, 440, -1, 442,
96, -1, -1, -1, 1, 448, -1, -1, -1, -1,
-1, 454, -1, -1, -1, -1, -1, -1, -1, 115,
463, -1, 19, -1, 21, -1, 23, 1260, -1, -1,
1, -1, -1, -1, 5, -1, 1269, 1113, 1114, -1,
-1, 1117, -1, 1119, -1, -1, -1, 18, 19, 835,
21, -1, 23, 1008, -1, 1288, -1, 1133, -1, -1,
1136, -1, -1, -1, 850, -1, -1, 1143, -1, 855,
-1, -1, -1, -1, -1, -1, -1, -1, 1311, -1,
-1, 524, 79, -1, 527, -1, 1319, 1320, -1, 875,
-1, 88, -1, 1326, -1, -1, 93, -1, -1, -1,
-1, -1, -1, -1, 75, 1338, -1, -1, -1, -1,
-1, 1344, -1, 110, -1, -1, -1, 88, -1, -1,
-1, -1, -1, 566, -1, -1, -1, -1, 1361, 126,
1206, -1, -1, 919, 920, -1, -1, -1, -1, 110,
111, -1, 928, -1, -1, 1221, -1, -1, -1, -1,
936, -1, -1, -1, 597, -1, 153, -1, 1113, 1114,
-1, -1, -1, -1, 1119, -1, -1, 610, -1, 612,
-1, -1, -1, -1, -1, -1, -1, -1, 1133, -1,
-1, 1136, -1, -1, 1260, 182, -1, -1, -1, -1,
-1, -1, -1, 1269, 191, 192, 193, 194, -1, -1,
197, 198, 173, 200, -1, -1, -1, 204, 205, -1,
207, -1, 1288, 656, -1, -1, -1, -1, -1, -1,
191, 192, 193, 194, -1, -1, 197, 198, 199, 200,
201, 202, 203, -1, -1, 1311, -1, -1, -1, -1,
-1, 1, -1, 1319, 1320, 5, 6, -1, -1, 9,
1326, 1206, 12, -1, -1, 698, -1, 700, 18, 19,
-1, -1, 1338, -1, -1, 708, 1221, -1, 1344, -1,
-1, -1, -1, 33, 717, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 1361, -1, 12, -1, -1,
1, 16, -1, -1, 5, 6, -1, -1, 9, -1,
-1, 26, -1, 28, 29, 1260, -1, 18, 19, 69,
-1, -1, -1, -1, 1269, 40, -1, -1, -1, -1,
45, 1, 33, -1, -1, -1, 6, 1113, 1114, -1,
-1, 1117, -1, -1, -1, -1, 16, -1, 18, 19,
-1, 21, -1, 23, -1, -1, -1, -1, -1, -1,
-1, 76, -1, -1, -1, 80, -1, 1143, 69, -1,
-1, 5, 42, -1, 1319, 1320, -1, 47, -1, 49,
-1, 1326, -1, -1, 18, 19, 56, 21, -1, 23,
60, 106, -1, 1338, -1, -1, -1, -1, -1, 1344,
-1, -1, 835, -1, 74, 75, -1, -1, 123, -1,
-1, -1, 82, 83, 129, -1, 1361, 850, 88, -1,
-1, -1, 855, 93, 94, -1, -1, 142, -1, -1,
-1, 101, -1, -1, 104, 105, 869, -1, -1, -1,
110, 75, -1, 113, -1, -1, 80, 197, 198, 199,
200, 201, 202, 203, 88, -1, -1, -1, -1, -1,
-1, -1, -1, 178, -1, -1, -1, 101, 138, -1,
-1, -1, -1, -1, -1, -1, 110, 111, -1, -1,
150, -1, -1, -1, 1260, -1, 919, 920, -1, -1,
-1, -1, -1, -1, -1, 928, 197, 198, 199, 200,
201, 202, 203, 173, -1, 175, -1, -1, -1, -1,
-1, -1, 1288, -1, -1, -1, -1, -1, -1, -1,
190, 191, 192, 193, 194, -1, -1, 197, 198, 199,
200, 201, 202, 203, 967, 1311, -1, -1, -1, 173,
-1, -1, -1, -1, -1, 19, -1, 21, -1, 23,
1326, -1, 26, -1, -1, -1, -1, 191, 192, 193,
194, -1, 1338, 197, 198, 199, 200, 201, 202, 203,
13, 14, 15, -1, 17, 18, 19, 20, 21, 22,
23, -1, -1, -1, -1, 1361, -1, 30, 31, -1,
-1, -1, -1, 1, -1, -1, -1, -1, 6, -1,
-1, 75, -1, -1, 47, -1, 49, -1, 16, -1,
18, 19, -1, 21, 88, 23, -1, 60, -1, -1,
-1, -1, -1, -1, -1, 1058, -1, -1, -1, -1,
-1, 74, 1065, -1, 42, -1, 110, -1, -1, 47,
-1, 49, 1075, -1, -1, -1, -1, -1, 56, -1,
93, 94, 60, 19, -1, 21, -1, 23, -1, -1,
26, -1, -1, 1096, -1, 1098, 74, 75, 1101, -1,
113, -1, -1, -1, 82, 83, -1, -1, -1, -1,
88, -1, -1, -1, 1117, 93, 94, -1, -1, -1,
-1, -1, -1, 101, -1, -1, 104, 105, -1, 173,
174, 175, 110, -1, -1, 113, -1, -1, -1, 75,
1143, -1, -1, 1146, -1, -1, -1, 191, 192, 193,
194, -1, 88, 197, 198, 199, 200, -1, -1, -1,
138, -1, -1, 1166, -1, -1, 1169, 1170, -1, -1,
-1, -1, 150, -1, 110, -1, -1, 190, 1181, -1,
-1, -1, -1, -1, 197, 198, 1, 200, 201, 202,
203, 6, -1, -1, -1, 173, -1, 175, -1, -1,
-1, -1, -1, 18, 19, -1, 21, -1, 23, -1,
-1, -1, 190, 191, 192, 193, 194, -1, -1, 197,
198, 199, 200, 201, 202, 203, -1, 42, -1, -1,
-1, -1, 47, -1, 49, -1, -1, 173, 174, 175,
-1, 56, -1, 1246, 1247, 60, -1, -1, -1, 1252,
-1, -1, -1, -1, -1, 191, 192, 193, 194, 74,
75, 197, 198, 199, 200, -1, -1, 82, 83, -1,
-1, -1, -1, 88, -1, -1, -1, -1, 93, 94,
-1, -1, -1, 1, 1287, 1288, 101, 5, -1, 104,
105, -1, -1, -1, 12, 110, -1, -1, 113, -1,
18, 19, -1, 21, -1, 23, -1, -1, 1311, -1,
-1, 29, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, 138, 1327, 1328, 1329, -1, -1, 1,
-1, -1, 1335, 5, 6, 150, -1, 9, -1, -1,
12, -1, -1, -1, 16, -1, 18, 19, -1, -1,
-1, -1, -1, -1, 26, -1, -1, 75, 173, -1,
175, 33, -1, -1, 11, -1, -1, -1, 40, -1,
88, 18, 19, 45, -1, 190, 191, 192, 193, 194,
-1, -1, 197, 198, 199, 200, 201, 202, 203, -1,
-1, 38, 110, 111, -1, -1, -1, 69, -1, -1,
47, -1, 49, -1, 76, -1, -1, 5, 80, -1,
-1, -1, -1, 60, 12, -1, -1, -1, -1, 66,
18, 19, -1, 21, -1, 23, -1, 74, -1, -1,
-1, -1, -1, -1, 106, -1, -1, -1, -1, -1,
5, -1, -1, -1, -1, -1, 93, 94, -1, -1,
-1, 123, -1, 18, 19, 173, 21, 129, 23, -1,
-1, -1, -1, -1, -1, -1, 113, -1, -1, -1,
142, -1, -1, 191, 192, 193, 194, 75, 5, 197,
198, 199, 200, 201, 202, 203, -1, -1, -1, -1,
88, 18, 19, -1, 21, -1, 23, -1, -1, -1,
-1, -1, -1, 101, -1, -1, 178, -1, -1, -1,
75, -1, 110, 111, -1, -1, -1, -1, 19, -1,
21, -1, 23, 88, -1, 197, 198, 199, 200, 201,
202, 203, 33, -1, -1, -1, 101, -1, -1, -1,
-1, -1, -1, 190, 191, 110, 111, -1, 75, -1,
197, 198, -1, 200, 201, 202, 203, -1, -1, -1,
-1, 88, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, 5, -1, 101, 173, 141, -1, 79, -1,
-1, -1, -1, 110, 111, 18, 19, 88, 21, -1,
23, -1, 93, 191, 192, 193, 194, -1, -1, 197,
198, 199, 200, 201, 202, 203, -1, -1, 173, 110,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 126, 191, 192, 193, 194,
-1, 5, 197, 198, 199, 200, 201, 202, 203, -1,
-1, -1, 75, -1, 18, 19, 173, 21, -1, 23,
-1, -1, 153, 27, -1, 88, -1, -1, -1, -1,
-1, -1, -1, -1, 191, 192, 193, 194, 101, 5,
197, 198, 199, 200, 201, 202, 203, 110, 111, -1,
-1, 182, 18, 19, -1, 21, -1, 23, -1, -1,
191, 192, 193, 194, -1, -1, 197, 198, -1, 200,
-1, 75, -1, 204, 205, -1, 207, -1, -1, -1,
-1, -1, -1, -1, 88, 18, 19, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 38, 110, 111, -1, 75,
173, -1, -1, -1, 47, -1, 49, -1, -1, -1,
-1, -1, 88, -1, -1, -1, -1, 60, 191, 192,
193, 194, -1, 66, 197, 198, 199, 200, 201, 202,
203, 74, -1, -1, 110, 111, -1, -1, -1, -1,
-1, -1, 19, -1, 21, -1, 23, -1, -1, -1,
93, 94, -1, -1, -1, -1, -1, -1, -1, 173,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
113, -1, -1, -1, -1, -1, -1, 191, 192, 193,
194, -1, -1, 197, 198, 199, 200, 201, 202, 203,
-1, -1, -1, -1, -1, 6, -1, 173, 75, -1,
-1, -1, -1, -1, -1, -1, -1, 18, 19, -1,
21, 88, 23, -1, -1, 191, 192, 193, 194, -1,
-1, 197, 198, 199, 200, 201, 202, 203, 39, -1,
-1, 42, -1, 110, -1, -1, 47, -1, 49, -1,
-1, -1, -1, -1, -1, 56, -1, 190, 191, 60,
-1, -1, -1, -1, 197, 198, 38, 200, 201, 202,
203, -1, -1, 74, 75, 47, -1, 49, -1, -1,
-1, 82, 83, -1, -1, -1, -1, 88, 60, -1,
-1, -1, 93, 94, 66, -1, -1, -1, -1, -1,
101, -1, 74, 104, 105, -1, 173, 174, 175, 110,
-1, -1, 113, -1, -1, -1, -1, -1, -1, -1,
-1, 93, 94, -1, 191, 192, 193, 194, -1, -1,
197, 198, 199, 200, -1, -1, -1, 138, -1, -1,
141, 113, -1, -1, -1, -1, -1, -1, 19, 150,
21, -1, 23, 13, 14, 15, 27, 17, -1, -1,
20, 21, 22, 23, -1, -1, -1, -1, -1, 6,
30, 31, 173, -1, 175, -1, -1, -1, -1, -1,
-1, 18, 19, -1, 21, -1, 23, -1, -1, 190,
191, 192, 193, 194, 31, -1, 197, 198, 199, 200,
201, 202, 203, -1, 75, 42, -1, 21, -1, 23,
47, -1, 49, -1, -1, -1, -1, 88, 190, 56,
-1, -1, -1, 60, -1, 197, 198, 87, 200, 201,
202, 203, 69, -1, -1, -1, 96, 74, 75, 110,
-1, 34, -1, 36, -1, 82, 83, -1, -1, -1,
-1, 88, -1, -1, -1, 115, 93, 94, 51, 52,
-1, 54, -1, -1, 101, 79, -1, 104, 105, -1,
-1, 64, -1, 110, 88, -1, 113, 70, 19, 93,
21, -1, 23, -1, -1, -1, 27, -1, -1, -1,
-1, -1, -1, -1, -1, -1, 110, -1, 91, -1,
-1, 138, 173, 174, 175, -1, -1, 100, -1, 102,
-1, -1, 126, 150, 107, 108, -1, -1, -1, -1,
191, 192, 193, 194, -1, -1, 197, 198, 199, 200,
-1, 6, -1, -1, 75, -1, 173, -1, 175, 153,
-1, 16, -1, 18, 19, -1, 21, 88, 23, -1,
-1, -1, 27, 190, 191, 192, 193, 194, -1, -1,
197, 198, 199, 200, 201, 202, 203, 42, 182, 110,
-1, -1, 47, -1, 49, -1, -1, 191, 192, 193,
194, 56, -1, 197, 198, 60, 200, -1, -1, -1,
204, 205, 185, 207, -1, -1, -1, -1, -1, 74,
75, -1, -1, -1, -1, -1, -1, 82, 83, -1,
-1, -1, -1, 88, -1, -1, -1, -1, 93, 94,
-1, -1, -1, -1, -1, -1, 101, -1, -1, 104,
105, -1, 173, 174, 175, 110, -1, -1, 113, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
191, 192, 193, 194, -1, -1, 197, 198, 199, 200,
-1, -1, -1, 138, -1, -1, -1, -1, 4, -1,
-1, -1, 8, -1, -1, 150, -1, 13, 14, 15,
-1, 17, -1, -1, 20, 21, 22, 23, -1, -1,
-1, -1, -1, 6, 30, 31, -1, -1, 173, -1,
175, 37, -1, -1, -1, 18, 19, -1, 21, -1,
23, -1, -1, -1, -1, 190, 191, 192, 193, 194,
-1, -1, 197, 198, 199, 200, 201, 202, 203, 42,
-1, -1, -1, -1, 47, -1, 49, -1, -1, -1,
-1, -1, 19, 56, 21, -1, 23, 60, 13, 14,
15, 87, 17, -1, -1, 20, 21, 22, 23, -1,
96, 74, 75, -1, -1, 30, 31, -1, -1, 82,
83, -1, -1, -1, -1, 88, -1, -1, -1, 115,
93, 94, -1, -1, -1, -1, -1, -1, 101, -1,
-1, 104, 105, -1, -1, -1, -1, 110, -1, -1,
113, -1, 79, -1, -1, -1, -1, -1, -1, -1,
-1, 88, -1, -1, -1, -1, 93, -1, -1, -1,
-1, -1, 87, -1, -1, 138, -1, -1, -1, -1,
-1, 96, -1, 110, -1, -1, -1, 150, -1, -1,
-1, -1, -1, 179, -1, -1, -1, -1, -1, 126,
115, -1, -1, -1, -1, -1, -1, 6, -1, -1,
173, -1, 175, -1, -1, -1, 179, -1, -1, 18,
19, -1, 21, -1, 23, -1, 153, 190, 191, 192,
193, 194, 31, -1, 197, 198, 199, 200, 201, 202,
203, -1, -1, 42, -1, -1, -1, -1, 47, -1,
49, -1, -1, -1, -1, 182, -1, 56, -1, -1,
-1, 60, -1, -1, 191, 192, 193, 194, -1, -1,
197, 198, -1, 200, -1, 74, 75, 204, 205, 27,
207, -1, -1, 82, 83, -1, -1, -1, -1, 88,
38, -1, -1, -1, 93, 94, -1, -1, -1, 47,
-1, 49, 101, -1, -1, 104, 105, -1, -1, -1,
-1, 110, 60, -1, 113, -1, -1, -1, 66, -1,
-1, -1, -1, -1, -1, -1, 74, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, 138,
-1, -1, -1, -1, -1, 93, 94, -1, -1, -1,
-1, 150, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 113, -1, -1, -1, 6,
-1, -1, -1, -1, 173, -1, 175, -1, -1, -1,
-1, 18, 19, -1, 21, -1, 23, -1, -1, -1,
-1, 190, 191, 192, 193, 194, -1, -1, 197, 198,
199, 200, 201, 202, 203, 42, -1, -1, -1, -1,
47, -1, 49, -1, -1, -1, -1, -1, -1, 56,
-1, -1, -1, 60, -1, -1, -1, -1, -1, -1,
-1, -1, 69, -1, -1, -1, -1, 74, 75, -1,
-1, -1, 190, -1, -1, 82, 83, -1, -1, 197,
198, 88, 200, 201, 202, 203, 93, 94, -1, -1,
-1, -1, -1, -1, 101, -1, -1, 104, 105, -1,
-1, -1, -1, 110, -1, -1, 113, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, 138, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, 150, -1, -1, -1, -1, 19, -1,
21, -1, 23, -1, -1, 26, -1, -1, -1, -1,
-1, 6, -1, -1, -1, -1, 173, -1, 175, -1,
-1, -1, -1, 18, 19, -1, 21, -1, 23, -1,
-1, 52, 27, 190, 191, 192, 193, 194, -1, -1,
197, 198, 199, 200, 201, 202, 203, 42, -1, -1,
-1, -1, 47, -1, 49, -1, -1, -1, 79, -1,
-1, 56, -1, -1, -1, 60, -1, 88, -1, -1,
-1, -1, 93, -1, -1, -1, -1, -1, -1, 74,
75, -1, -1, -1, -1, -1, -1, 82, 83, 110,
-1, -1, -1, 88, -1, -1, -1, -1, 93, 94,
-1, -1, -1, -1, -1, 126, 101, -1, -1, 104,
105, -1, -1, -1, -1, 110, -1, -1, 113, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, 4, 153, -1, -1, 8, -1, -1, -1, -1,
13, 14, 15, 138, 17, -1, -1, 20, 21, 22,
23, -1, -1, -1, -1, 150, -1, 30, 31, -1,
-1, 182, -1, -1, 37, -1, -1, -1, -1, -1,
191, 192, 193, 194, -1, 6, 197, 198, 173, 200,
175, -1, -1, 204, 205, -1, 207, 18, 19, -1,
21, -1, 23, -1, -1, 190, 191, 192, 193, 194,
31, -1, 197, 198, 199, 200, 201, 202, 203, -1,
-1, 42, -1, -1, 87, -1, 47, -1, 49, -1,
-1, -1, 4, 96, -1, 56, 8, -1, -1, 60,
-1, 13, 14, 15, -1, 17, -1, -1, 20, 21,
22, 23, 115, 74, 75, 27, -1, -1, 30, 31,
-1, 82, 83, -1, -1, 37, -1, 88, -1, -1,
-1, -1, 93, 94, -1, -1, -1, -1, -1, -1,
101, -1, -1, 104, 105, -1, -1, -1, -1, 110,
-1, 154, 113, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 87, -1, 138, -1, -1,
-1, -1, 4, -1, 96, -1, 8, -1, -1, 150,
-1, 13, 14, 15, -1, 17, -1, -1, 20, 21,
22, 23, -1, 115, -1, 27, -1, 6, 30, 31,
-1, -1, 173, -1, 175, 37, -1, -1, -1, 18,
19, -1, 21, -1, 23, -1, -1, -1, -1, 190,
191, 192, 193, 194, -1, -1, 197, 198, 199, 200,
201, 202, 203, 42, -1, -1, -1, -1, 47, -1,
49, -1, -1, -1, -1, -1, -1, 56, -1, -1,
-1, 60, 13, 14, 15, 87, 17, 18, 19, 20,
21, 22, 23, -1, 96, 74, 75, -1, -1, 30,
31, -1, -1, 82, 83, -1, -1, -1, -1, 88,
-1, -1, -1, 115, 93, 94, 47, -1, 49, -1,
-1, -1, 101, -1, -1, 104, 105, 58, -1, 60,
-1, 110, -1, -1, 113, -1, -1, -1, -1, -1,
-1, -1, -1, 74, -1, -1, -1, -1, -1, -1,
-1, -1, 83, -1, -1, -1, 19, -1, 21, 138,
23, -1, 93, 94, -1, -1, -1, -1, -1, -1,
-1, 150, -1, -1, -1, -1, -1, 19, 41, 21,
-1, 23, 113, -1, 26, -1, -1, -1, -1, 52,
-1, -1, -1, -1, 173, -1, 175, -1, -1, 41,
-1, 132, -1, -1, -1, 68, -1, 70, -1, -1,
52, 190, 191, 192, 193, 194, 79, -1, 197, 198,
199, 200, 201, 202, 203, 88, 68, -1, 70, -1,
93, -1, 19, -1, 21, -1, 23, 79, -1, -1,
-1, -1, -1, -1, -1, -1, 88, 110, -1, -1,
-1, 93, -1, -1, -1, -1, -1, -1, -1, 190,
-1, -1, -1, 126, -1, 52, 197, 198, 110, 200,
201, 202, 203, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, 126, -1, -1, -1, -1, -1,
153, -1, 79, -1, -1, -1, -1, -1, -1, -1,
-1, 88, -1, -1, -1, -1, 93, -1, -1, -1,
-1, 153, -1, -1, -1, -1, -1, -1, -1, 182,
-1, -1, -1, 110, -1, -1, -1, -1, 191, 192,
193, 194, -1, -1, 197, 198, -1, 200, -1, 126,
182, 204, 205, -1, 207, -1, -1, -1, -1, 191,
192, 193, 194, -1, -1, 197, 198, -1, 200, -1,
4, -1, 204, 205, 8, 207, 153, -1, -1, 13,
14, 15, -1, 17, -1, -1, 20, 21, 22, 23,
-1, -1, -1, -1, -1, -1, 30, 31, -1, -1,
-1, -1, -1, 37, -1, 182, -1, -1, -1, -1,
-1, -1, -1, -1, 191, 192, 193, 194, -1, -1,
197, 198, 4, 200, -1, -1, 8, 204, 205, 11,
207, 13, 14, 15, -1, 17, -1, -1, 20, 21,
22, 23, -1, -1, -1, 27, -1, 29, 30, 31,
-1, -1, -1, 87, -1, 37, 4, -1, -1, -1,
8, -1, 96, 11, -1, 13, 14, 15, -1, 17,
-1, -1, 20, 21, 22, 23, -1, -1, -1, 27,
-1, 115, 30, 31, -1, -1, -1, -1, -1, 37,
4, -1, -1, -1, 8, -1, -1, -1, -1, 13,
14, 15, -1, 17, -1, 87, 20, 21, 22, 23,
-1, -1, -1, 27, 96, -1, 30, 31, -1, -1,
154, -1, -1, 37, -1, 4, -1, -1, -1, 8,
-1, -1, 11, 115, 13, 14, 15, -1, 17, 87,
-1, 20, 21, 22, 23, -1, -1, -1, 96, -1,
-1, 30, 31, -1, -1, -1, -1, -1, 37, -1,
-1, 4, -1, -1, -1, 8, -1, 115, -1, -1,
13, 14, 15, 87, 17, -1, -1, 20, 21, 22,
23, -1, 96, -1, 27, -1, 4, 30, 31, -1,
8, -1, -1, -1, 37, 13, 14, 15, -1, 17,
-1, 115, 20, 21, 22, 23, -1, -1, 87, 27,
-1, -1, 30, 31, -1, -1, 4, 96, -1, 37,
8, -1, -1, -1, -1, 13, 14, 15, -1, 17,
-1, -1, 20, 21, 22, 23, 115, -1, -1, 27,
-1, 4, 30, 31, 87, 8, -1, -1, -1, 37,
13, 14, 15, 96, 17, -1, -1, 20, 21, 22,
23, -1, -1, -1, 27, -1, -1, 30, 31, 87,
-1, -1, 115, -1, 37, -1, -1, 4, 96, -1,
-1, 8, -1, -1, -1, -1, 13, 14, 15, -1,
17, -1, -1, 20, 21, 22, 23, 115, -1, 87,
27, -1, -1, 30, 31, -1, -1, -1, 96, -1,
37, -1, 4, 5, -1, -1, 8, -1, -1, -1,
-1, 13, 14, 15, 87, 17, -1, 115, 20, 21,
22, 23, -1, 96, -1, -1, -1, 4, 30, 31,
-1, 8, -1, -1, -1, 37, 13, 14, 15, -1,
17, -1, 115, 20, 21, 22, 23, -1, -1, -1,
87, -1, -1, 30, 31, -1, -1, 4, -1, 96,
37, 8, -1, -1, -1, -1, 13, 14, 15, -1,
17, -1, -1, 20, 21, 22, 23, -1, 115, -1,
27, -1, -1, 30, 31, 87, -1, -1, 4, -1,
37, -1, 8, -1, 96, 72, -1, 13, 14, 15,
-1, 17, -1, -1, 20, 21, 22, 23, -1, -1,
87, 27, -1, 115, 30, 31, -1, -1, 4, 96,
-1, 37, 8, -1, -1, -1, -1, 13, 14, 15,
-1, 17, -1, -1, 20, 21, 22, 23, 115, -1,
87, 27, -1, 4, 30, 31, -1, 8, -1, 96,
-1, 37, 13, 14, 15, -1, 17, -1, -1, 20,
21, 22, 23, -1, -1, -1, -1, -1, 115, 30,
31, 87, -1, -1, -1, -1, 37, -1, -1, 4,
96, -1, -1, 8, -1, -1, -1, -1, 13, 14,
15, -1, 17, -1, -1, 20, 21, 22, 23, 115,
-1, 87, 27, -1, 4, 30, 31, -1, 8, -1,
96, 72, 37, 13, 14, 15, -1, 17, -1, -1,
20, 21, 22, 23, -1, -1, 87, 27, -1, 115,
30, 31, -1, -1, 4, 96, -1, 37, 8, -1,
-1, -1, -1, 13, 14, 15, -1, 17, -1, -1,
20, 21, 22, 23, 115, -1, -1, 27, -1, 4,
30, 31, 87, 8, -1, -1, -1, 37, 13, 14,
15, 96, 17, -1, -1, 20, 21, 22, 23, -1,
-1, -1, -1, 28, -1, 30, 31, 87, -1, -1,
115, -1, 37, -1, -1, 4, 96, -1, -1, 8,
-1, -1, -1, -1, 13, 14, 15, -1, 17, -1,
-1, 20, 21, 22, 23, 115, -1, 87, 27, -1,
4, 30, 31, -1, 8, -1, 96, -1, 37, 13,
14, 15, -1, 17, -1, -1, 20, 21, 22, 23,
-1, -1, 87, -1, 28, 115, 30, 31, -1, -1,
4, 96, -1, 37, 8, -1, -1, -1, -1, 13,
14, 15, -1, 17, -1, -1, 20, 21, 22, 23,
115, -1, -1, 27, -1, 4, 30, 31, 87, 8,
-1, -1, -1, 37, 13, 14, 15, 96, 17, -1,
-1, 20, 21, 22, 23, -1, -1, -1, -1, -1,
-1, 30, 31, 87, -1, -1, 115, -1, 37, -1,
-1, -1, 96, -1, -1, 79, -1, -1, -1, -1,
-1, -1, 86, -1, -1, -1, 90, -1, -1, -1,
-1, 115, -1, 87, -1, -1, -1, -1, -1, -1,
-1, -1, 96, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, 121, 87, -1,
-1, 115, 126, -1, -1, -1, -1, 96, -1, 133,
134, 135, 136, 137, -1, 139, 140, -1, -1, -1,
-1, -1, -1, -1, -1, -1, 115, 151, 152, -1,
-1, -1, -1, -1, 158, 159, 160, 161, 162, 163,
164, 165, 166, 167, 168, 169, 170, 171, 172
};
/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
symbol of state STATE-NUM. */
static const yytype_uint16 yystos[] =
{
0, 1, 184, 219, 16, 220, 222, 223, 0, 220,
222, 185, 34, 36, 51, 52, 54, 64, 70, 91,
100, 102, 107, 108, 231, 456, 457, 458, 459, 462,
464, 467, 469, 472, 473, 474, 475, 476, 488, 493,
497, 498, 499, 501, 502, 503, 504, 505, 510, 514,
517, 518, 43, 62, 224, 228, 26, 52, 70, 129,
144, 487, 93, 98, 101, 129, 487, 513, 16, 59,
77, 180, 481, 487, 16, 59, 87, 92, 479, 486,
487, 93, 197, 198, 200, 453, 454, 587, 80, 484,
588, 589, 39, 53, 67, 141, 221, 251, 253, 257,
261, 264, 29, 52, 457, 487, 12, 185, 590, 1,
200, 225, 229, 185, 487, 147, 35, 61, 109, 482,
589, 95, 147, 589, 50, 489, 480, 481, 588, 16,
16, 101, 129, 482, 513, 494, 478, 479, 16, 588,
142, 275, 276, 18, 50, 148, 85, 64, 275, 265,
16, 266, 262, 57, 69, 130, 252, 222, 61, 483,
588, 185, 500, 197, 128, 230, 233, 93, 587, 275,
453, 587, 275, 587, 363, 364, 16, 275, 491, 465,
95, 103, 147, 50, 363, 16, 460, 275, 275, 486,
6, 18, 19, 21, 23, 42, 47, 49, 56, 60,
74, 75, 82, 83, 88, 93, 94, 101, 104, 105,
110, 113, 138, 150, 173, 175, 190, 191, 192, 193,
194, 199, 201, 202, 203, 353, 410, 411, 412, 413,
414, 416, 417, 418, 422, 429, 433, 443, 447, 448,
453, 455, 194, 587, 120, 48, 16, 266, 258, 77,
114, 117, 177, 180, 267, 268, 269, 270, 5, 18,
31, 263, 405, 406, 416, 420, 453, 254, 255, 156,
275, 52, 70, 501, 191, 194, 197, 200, 226, 227,
417, 1, 198, 63, 181, 234, 485, 515, 232, 511,
177, 194, 91, 496, 18, 19, 21, 23, 80, 111,
365, 366, 367, 370, 373, 398, 404, 416, 419, 420,
433, 443, 444, 447, 448, 453, 455, 468, 201, 324,
368, 369, 373, 363, 275, 587, 589, 587, 587, 495,
463, 363, 59, 588, 422, 39, 253, 422, 28, 422,
422, 18, 18, 179, 422, 430, 18, 18, 18, 18,
18, 453, 18, 18, 18, 18, 18, 111, 436, 10,
196, 354, 355, 31, 69, 422, 422, 24, 32, 451,
452, 4, 8, 13, 14, 15, 17, 20, 21, 22,
23, 30, 31, 37, 87, 96, 115, 428, 27, 148,
587, 470, 16, 180, 278, 363, 109, 109, 109, 109,
16, 453, 421, 422, 266, 406, 266, 31, 256, 408,
409, 422, 483, 487, 11, 200, 453, 588, 520, 16,
520, 78, 577, 578, 18, 579, 16, 490, 27, 400,
399, 443, 443, 371, 26, 12, 370, 370, 373, 375,
374, 363, 12, 26, 16, 40, 45, 76, 80, 106,
123, 129, 142, 178, 325, 326, 328, 332, 335, 339,
340, 342, 356, 12, 466, 587, 266, 477, 363, 461,
177, 275, 426, 427, 27, 416, 422, 430, 1, 71,
179, 422, 69, 422, 422, 434, 69, 422, 27, 422,
437, 453, 266, 27, 31, 422, 27, 11, 27, 29,
1, 197, 198, 200, 422, 422, 422, 422, 422, 422,
422, 422, 422, 422, 422, 422, 201, 424, 423, 425,
435, 436, 120, 363, 280, 16, 266, 259, 124, 271,
422, 27, 277, 278, 278, 11, 422, 11, 227, 235,
275, 16, 77, 180, 570, 233, 16, 206, 11, 124,
506, 79, 87, 126, 153, 182, 204, 580, 581, 582,
584, 586, 506, 363, 477, 398, 402, 403, 404, 1,
6, 9, 18, 33, 69, 377, 392, 393, 394, 395,
397, 416, 420, 453, 455, 407, 416, 420, 453, 455,
370, 373, 376, 377, 377, 324, 492, 336, 18, 352,
429, 431, 453, 341, 352, 407, 354, 1, 16, 103,
487, 343, 12, 324, 69, 176, 338, 340, 368, 477,
278, 477, 142, 266, 254, 27, 154, 71, 422, 422,
27, 27, 27, 18, 111, 438, 439, 422, 27, 1,
11, 27, 278, 27, 27, 422, 204, 436, 422, 436,
587, 91, 253, 281, 322, 324, 279, 278, 324, 18,
5, 81, 282, 283, 282, 422, 422, 1, 16, 18,
61, 80, 236, 241, 271, 516, 146, 204, 206, 18,
194, 26, 512, 579, 578, 18, 27, 11, 586, 27,
403, 18, 33, 453, 397, 393, 18, 28, 29, 401,
378, 7, 30, 16, 23, 25, 31, 372, 29, 282,
321, 322, 324, 422, 432, 18, 333, 327, 329, 415,
416, 453, 18, 201, 344, 347, 417, 324, 176, 16,
282, 275, 278, 266, 422, 422, 72, 154, 16, 27,
422, 440, 441, 27, 1, 422, 124, 151, 382, 27,
13, 16, 323, 26, 281, 282, 26, 272, 48, 84,
295, 201, 246, 453, 201, 243, 244, 245, 80, 246,
239, 19, 26, 41, 52, 68, 70, 205, 207, 444,
447, 518, 519, 530, 531, 533, 534, 535, 539, 545,
547, 566, 567, 585, 586, 587, 18, 194, 571, 37,
37, 195, 530, 131, 27, 44, 60, 65, 94, 131,
507, 508, 582, 583, 586, 393, 16, 23, 25, 31,
27, 393, 1, 12, 28, 392, 1, 380, 381, 403,
394, 395, 11, 191, 396, 16, 26, 27, 436, 422,
16, 321, 31, 61, 449, 450, 453, 357, 346, 16,
337, 382, 278, 72, 422, 442, 1, 11, 27, 18,
204, 422, 363, 254, 260, 27, 197, 273, 274, 284,
296, 125, 298, 33, 201, 247, 453, 11, 27, 11,
201, 16, 16, 99, 242, 28, 101, 587, 589, 487,
487, 12, 26, 80, 119, 124, 127, 149, 548, 572,
546, 18, 195, 37, 204, 204, 583, 587, 194, 586,
194, 509, 11, 27, 116, 586, 27, 396, 27, 379,
11, 382, 191, 11, 26, 369, 382, 27, 334, 330,
61, 453, 18, 360, 27, 347, 350, 321, 27, 282,
324, 1, 441, 383, 27, 471, 266, 282, 275, 11,
27, 13, 14, 15, 17, 18, 19, 20, 21, 22,
23, 30, 31, 58, 83, 132, 285, 286, 287, 288,
294, 416, 429, 431, 297, 352, 48, 46, 97, 122,
178, 306, 308, 309, 310, 111, 201, 248, 444, 447,
448, 453, 201, 237, 201, 246, 246, 18, 16, 95,
37, 177, 587, 101, 129, 587, 589, 26, 532, 567,
567, 18, 567, 567, 16, 1, 19, 33, 551, 553,
565, 567, 575, 576, 585, 204, 521, 176, 508, 116,
380, 1, 12, 29, 381, 26, 26, 191, 26, 321,
16, 361, 358, 345, 26, 174, 175, 351, 444, 447,
448, 453, 455, 382, 26, 79, 86, 90, 121, 126,
133, 134, 135, 136, 137, 139, 140, 151, 152, 158,
159, 160, 161, 162, 163, 164, 165, 166, 167, 168,
169, 170, 171, 172, 384, 385, 386, 387, 388, 389,
391, 477, 278, 197, 422, 422, 18, 143, 18, 287,
352, 299, 311, 275, 275, 18, 347, 307, 308, 305,
306, 26, 242, 247, 247, 244, 245, 240, 587, 540,
147, 177, 95, 587, 533, 549, 27, 73, 125, 145,
177, 573, 574, 541, 28, 29, 554, 27, 11, 522,
523, 194, 26, 331, 27, 62, 87, 197, 362, 266,
16, 27, 422, 194, 197, 200, 204, 416, 422, 416,
422, 204, 194, 191, 191, 416, 18, 422, 422, 18,
18, 11, 27, 18, 282, 275, 27, 28, 38, 66,
300, 303, 304, 416, 429, 431, 18, 300, 300, 201,
314, 315, 417, 346, 16, 309, 309, 238, 248, 248,
27, 27, 324, 542, 544, 547, 566, 587, 147, 587,
60, 563, 191, 73, 204, 11, 27, 26, 536, 537,
539, 552, 1, 555, 557, 566, 585, 523, 153, 524,
321, 197, 31, 390, 416, 226, 16, 348, 390, 390,
194, 416, 385, 437, 26, 27, 11, 301, 303, 18,
19, 191, 18, 125, 289, 290, 27, 16, 315, 27,
350, 1, 16, 249, 422, 26, 26, 26, 572, 565,
572, 587, 93, 453, 585, 550, 574, 12, 26, 553,
11, 37, 562, 558, 182, 525, 226, 11, 359, 18,
26, 349, 27, 27, 27, 27, 27, 382, 302, 303,
303, 422, 422, 27, 300, 48, 11, 27, 312, 313,
26, 250, 16, 557, 572, 18, 94, 564, 26, 538,
556, 587, 563, 98, 416, 321, 350, 37, 37, 11,
27, 28, 27, 35, 69, 291, 292, 290, 18, 316,
317, 318, 16, 324, 543, 194, 194, 585, 539, 557,
559, 585, 27, 416, 416, 303, 300, 18, 157, 174,
175, 319, 320, 444, 447, 448, 453, 455, 26, 318,
348, 26, 536, 27, 562, 564, 120, 526, 27, 18,
191, 445, 27, 320, 26, 560, 18, 124, 527, 422,
11, 181, 293, 568, 569, 570, 576, 18, 11, 27,
106, 191, 446, 155, 18, 561, 570, 27, 204, 528,
529, 422, 293, 191, 293, 572, 194, 11, 27, 27,
18, 18, 529, 293, 18
};
/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
static const yytype_uint16 yyr1[] =
{
0, 218, 219, 219, 219, 219, 220, 220, 220, 221,
221, 221, 221, 222, 223, 223, 225, 224, 226, 226,
227, 227, 227, 227, 227, 228, 228, 228, 229, 229,
230, 230, 230, 231, 232, 231, 233, 233, 235, 234,
237, 238, 236, 239, 240, 236, 236, 241, 241, 241,
242, 242, 242, 243, 243, 243, 244, 244, 245, 245,
246, 246, 247, 247, 247, 248, 248, 248, 248, 248,
248, 250, 249, 249, 249, 252, 251, 253, 253, 253,
253, 255, 254, 256, 256, 256, 258, 257, 259, 260,
257, 262, 261, 263, 263, 265, 264, 266, 266, 267,
268, 268, 269, 269, 269, 269, 270, 270, 270, 270,
271, 272, 271, 273, 273, 274, 274, 276, 275, 277,
277, 279, 278, 280, 278, 281, 281, 282, 282, 282,
283, 284, 283, 285, 285, 286, 286, 287, 287, 287,
287, 287, 287, 288, 288, 288, 289, 289, 290, 290,
290, 291, 291, 291, 291, 291, 292, 292, 292, 293,
293, 294, 294, 294, 294, 294, 294, 294, 294, 294,
294, 295, 296, 295, 297, 297, 298, 299, 298, 300,
300, 300, 301, 301, 302, 302, 303, 303, 303, 303,
303, 303, 304, 304, 304, 305, 305, 306, 307, 307,
308, 309, 309, 311, 312, 310, 310, 313, 310, 314,
314, 315, 315, 316, 316, 317, 317, 318, 319, 319,
320, 320, 320, 320, 320, 320, 320, 321, 321, 323,
322, 324, 324, 324, 324, 325, 325, 325, 325, 325,
325, 325, 325, 325, 325, 327, 326, 326, 329, 330,
331, 328, 333, 334, 332, 336, 335, 337, 335, 338,
338, 339, 339, 341, 340, 343, 342, 344, 345, 344,
346, 346, 347, 347, 348, 348, 349, 350, 350, 351,
351, 351, 351, 351, 351, 351, 352, 352, 352, 353,
353, 355, 354, 357, 358, 359, 356, 360, 360, 361,
361, 362, 362, 362, 362, 364, 363, 365, 365, 365,
365, 366, 366, 366, 367, 367, 367, 367, 368, 368,
369, 369, 371, 372, 370, 374, 373, 375, 373, 373,
376, 376, 378, 377, 379, 377, 377, 377, 377, 380,
380, 380, 380, 380, 380, 381, 382, 382, 383, 382,
384, 384, 385, 385, 385, 385, 385, 385, 386, 386,
386, 386, 386, 386, 386, 387, 387, 387, 388, 388,
389, 389, 389, 389, 389, 389, 389, 389, 389, 389,
389, 389, 389, 389, 389, 389, 390, 390, 391, 391,
391, 391, 391, 392, 392, 392, 392, 392, 393, 393,
394, 394, 395, 395, 395, 395, 395, 395, 395, 395,
395, 395, 396, 396, 396, 396, 397, 397, 397, 397,
397, 397, 397, 399, 398, 400, 398, 398, 401, 401,
402, 402, 403, 403, 404, 404, 405, 405, 406, 406,
406, 406, 407, 407, 407, 407, 408, 408, 409, 409,
410, 410, 410, 410, 410, 410, 410, 410, 410, 411,
412, 412, 412, 412, 412, 412, 413, 414, 414, 415,
415, 416, 416, 416, 417, 418, 418, 419, 419, 419,
419, 419, 419, 419, 421, 420, 422, 422, 422, 422,
422, 423, 422, 424, 422, 425, 422, 422, 422, 422,
422, 422, 422, 422, 422, 422, 422, 422, 422, 426,
422, 427, 422, 422, 422, 428, 422, 422, 422, 422,
422, 422, 422, 422, 429, 429, 429, 429, 429, 429,
429, 429, 430, 430, 430, 432, 431, 434, 433, 435,
435, 436, 436, 436, 437, 437, 437, 437, 438, 438,
439, 439, 439, 440, 440, 440, 440, 441, 442, 441,
443, 443, 443, 443, 443, 444, 444, 444, 445, 446,
446, 447, 447, 447, 448, 448, 449, 449, 450, 450,
450, 450, 451, 451, 452, 452, 452, 452, 453, 453,
454, 454, 455, 455, 456, 456, 456, 457, 457, 457,
457, 457, 457, 457, 457, 457, 457, 457, 457, 457,
457, 458, 460, 461, 459, 463, 462, 465, 466, 464,
468, 467, 470, 471, 469, 472, 473, 473, 474, 474,
475, 476, 477, 477, 478, 478, 479, 480, 480, 481,
482, 482, 482, 482, 483, 483, 484, 484, 485, 485,
486, 486, 487, 487, 489, 490, 488, 491, 492, 488,
494, 495, 493, 496, 496, 497, 498, 498, 498, 499,
500, 499, 501, 501, 501, 502, 502, 502, 502, 502,
503, 503, 504, 505, 505, 506, 506, 506, 507, 507,
508, 508, 508, 508, 508, 508, 509, 509, 511, 512,
510, 513, 513, 515, 516, 514, 517, 518, 518, 519,
519, 520, 521, 520, 520, 522, 520, 520, 523, 523,
524, 525, 525, 526, 526, 527, 527, 528, 528, 529,
529, 530, 530, 530, 531, 532, 531, 533, 533, 533,
533, 533, 534, 535, 535, 536, 536, 536, 537, 538,
537, 540, 539, 539, 539, 541, 539, 539, 542, 543,
542, 544, 546, 545, 547, 547, 548, 548, 548, 549,
550, 548, 551, 552, 551, 554, 553, 553, 555, 556,
555, 558, 559, 560, 561, 557, 557, 562, 562, 563,
563, 563, 563, 564, 564, 564, 565, 565, 565, 566,
566, 567, 567, 567, 567, 567, 568, 568, 569, 569,
570, 570, 571, 571, 572, 572, 572, 573, 573, 574,
574, 574, 574, 575, 575, 576, 576, 577, 577, 578,
579, 580, 580, 581, 581, 582, 583, 583, 583, 583,
584, 584, 585, 585, 585, 586, 586, 586, 586, 586,
587, 587, 588, 588, 589, 589, 590, 590
};
/* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
static const yytype_uint8 yyr2[] =
{
0, 2, 3, 5, 4, 1, 1, 2, 3, 1,
1, 1, 1, 5, 0, 2, 0, 4, 1, 3,
1, 1, 1, 1, 1, 0, 2, 2, 0, 2,
3, 2, 2, 0, 0, 8, 0, 2, 0, 4,
0, 0, 7, 0, 0, 7, 1, 5, 7, 7,
0, 4, 4, 0, 1, 1, 3, 3, 1, 2,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 0, 4, 1, 1, 0, 6, 1, 2, 2,
2, 0, 2, 1, 1, 1, 0, 7, 0, 0,
9, 0, 6, 1, 1, 0, 4, 0, 2, 3,
1, 1, 1, 2, 1, 2, 1, 2, 1, 2,
0, 0, 4, 1, 2, 2, 4, 0, 2, 0,
1, 0, 4, 0, 3, 2, 1, 4, 6, 6,
0, 0, 4, 1, 1, 1, 2, 3, 3, 1,
1, 1, 1, 5, 4, 4, 1, 3, 2, 3,
5, 2, 5, 7, 7, 9, 0, 1, 1, 0,
2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 0, 0, 3, 1, 2, 0, 0, 4, 1,
2, 3, 1, 2, 1, 3, 4, 4, 2, 1,
1, 1, 0, 1, 1, 0, 1, 2, 0, 1,
2, 0, 1, 0, 0, 7, 5, 0, 8, 1,
2, 1, 1, 0, 1, 1, 2, 3, 1, 2,
1, 1, 1, 1, 1, 1, 1, 3, 1, 0,
8, 1, 3, 4, 3, 1, 1, 1, 1, 1,
1, 1, 2, 2, 2, 0, 4, 2, 0, 0,
0, 8, 0, 0, 6, 0, 3, 0, 5, 1,
2, 1, 2, 0, 5, 0, 3, 4, 0, 7,
0, 2, 1, 1, 0, 2, 3, 0, 2, 1,
1, 1, 1, 1, 1, 1, 3, 1, 1, 1,
1, 0, 4, 0, 0, 0, 10, 0, 3, 0,
2, 2, 3, 2, 2, 0, 3, 0, 1, 1,
2, 1, 3, 2, 1, 3, 2, 2, 0, 1,
1, 3, 0, 0, 7, 0, 3, 0, 3, 1,
0, 1, 0, 3, 0, 5, 3, 3, 1, 1,
3, 3, 3, 3, 1, 2, 0, 2, 0, 5,
1, 3, 2, 2, 1, 1, 1, 1, 1, 2,
2, 2, 2, 4, 1, 2, 2, 2, 2, 2,
1, 2, 1, 2, 1, 2, 4, 2, 2, 1,
1, 4, 1, 6, 6, 1, 1, 3, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 3,
1, 3, 3, 3, 3, 4, 2, 2, 2, 2,
3, 1, 2, 4, 3, 3, 4, 3, 4, 2,
2, 1, 1, 0, 4, 0, 4, 2, 1, 2,
1, 2, 1, 1, 1, 1, 1, 2, 1, 1,
1, 3, 1, 1, 1, 1, 3, 3, 1, 2,
3, 3, 4, 4, 4, 5, 3, 5, 7, 1,
1, 2, 2, 2, 2, 2, 1, 2, 3, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 0, 4, 3, 3, 3, 3,
3, 0, 4, 0, 4, 0, 4, 3, 3, 3,
3, 3, 3, 3, 3, 2, 2, 2, 3, 0,
7, 0, 9, 1, 1, 0, 3, 1, 1, 1,
1, 1, 1, 1, 2, 4, 4, 4, 4, 2,
6, 5, 4, 5, 2, 0, 3, 0, 4, 0,
1, 1, 2, 3, 1, 3, 3, 2, 0, 1,
1, 2, 3, 1, 3, 3, 2, 1, 0, 4,
1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
2, 1, 2, 3, 1, 1, 1, 1, 1, 1,
2, 2, 1, 1, 2, 2, 2, 2, 1, 1,
1, 1, 1, 2, 1, 2, 3, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 5, 0, 0, 7, 0, 6, 0, 0, 7,
0, 6, 0, 0, 11, 3, 3, 6, 5, 8,
4, 3, 0, 3, 0, 1, 3, 0, 1, 3,
1, 1, 1, 2, 1, 2, 0, 2, 0, 4,
1, 1, 0, 1, 0, 0, 7, 0, 0, 8,
0, 0, 6, 0, 3, 5, 1, 1, 1, 1,
0, 4, 1, 1, 1, 1, 1, 1, 1, 1,
7, 7, 5, 7, 5, 0, 3, 4, 1, 3,
2, 2, 2, 1, 1, 2, 1, 3, 0, 0,
9, 1, 1, 0, 0, 9, 5, 5, 6, 3,
4, 0, 0, 7, 5, 0, 8, 2, 0, 2,
6, 0, 1, 0, 4, 0, 4, 1, 3, 1,
2, 1, 2, 3, 1, 0, 4, 1, 1, 1,
1, 1, 4, 5, 4, 1, 2, 3, 1, 0,
4, 0, 5, 6, 7, 0, 5, 1, 1, 0,
5, 3, 0, 3, 0, 2, 2, 2, 2, 0,
0, 6, 1, 0, 4, 0, 3, 1, 2, 0,
5, 0, 0, 0, 0, 9, 1, 0, 2, 0,
2, 5, 2, 0, 2, 2, 1, 2, 1, 1,
2, 1, 1, 1, 4, 1, 0, 1, 1, 2,
3, 2, 2, 1, 0, 3, 4, 1, 3, 2,
1, 2, 2, 0, 1, 1, 3, 1, 3, 5,
3, 0, 1, 1, 3, 3, 1, 2, 2, 3,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 4, 0, 1, 1, 3, 1, 2
};
#define yyerrok (yyerrstatus = 0)
#define yyclearin (yychar = YYEMPTY)
#define YYEMPTY (-2)
#define YYEOF 0
#define YYACCEPT goto yyacceptlab
#define YYABORT goto yyabortlab
#define YYERROR goto yyerrorlab
#define YYRECOVERING() (!!yyerrstatus)
#define YYBACKUP(Token, Value) \
do \
if (yychar == YYEMPTY) \
{ \
yychar = (Token); \
yylval = (Value); \
YYPOPSTACK (yylen); \
yystate = *yyssp; \
goto yybackup; \
} \
else \
{ \
yyerror (sparp_arg, YY_("syntax error: cannot back up")); \
YYERROR; \
} \
while (0)
/* Error token number */
#define YYTERROR 1
#define YYERRCODE 256
/* Enable debugging if requested. */
#if YYDEBUG
# ifndef YYFPRINTF
# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
# define YYFPRINTF fprintf
# endif
# define YYDPRINTF(Args) \
do { \
if (yydebug) \
YYFPRINTF Args; \
} while (0)
/* This macro is provided for backward compatibility. */
#ifndef YY_LOCATION_PRINT
# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
#endif
# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
do { \
if (yydebug) \
{ \
YYFPRINTF (stderr, "%s ", Title); \
yy_symbol_print (stderr, \
Type, Value, sparp_arg); \
YYFPRINTF (stderr, "\n"); \
} \
} while (0)
/*----------------------------------------.
| Print this symbol's value on YYOUTPUT. |
`----------------------------------------*/
static void
yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, sparp_t * sparp_arg)
{
FILE *yyo = yyoutput;
YYUSE (yyo);
YYUSE (sparp_arg);
if (!yyvaluep)
return;
# ifdef YYPRINT
if (yytype < YYNTOKENS)
YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
# endif
YYUSE (yytype);
}
/*--------------------------------.
| Print this symbol on YYOUTPUT. |
`--------------------------------*/
static void
yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, sparp_t * sparp_arg)
{
YYFPRINTF (yyoutput, "%s %s (",
yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
yy_symbol_value_print (yyoutput, yytype, yyvaluep, sparp_arg);
YYFPRINTF (yyoutput, ")");
}
/*------------------------------------------------------------------.
| yy_stack_print -- Print the state stack from its BOTTOM up to its |
| TOP (included). |
`------------------------------------------------------------------*/
static void
yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
{
YYFPRINTF (stderr, "Stack now");
for (; yybottom <= yytop; yybottom++)
{
int yybot = *yybottom;
YYFPRINTF (stderr, " %d", yybot);
}
YYFPRINTF (stderr, "\n");
}
# define YY_STACK_PRINT(Bottom, Top) \
do { \
if (yydebug) \
yy_stack_print ((Bottom), (Top)); \
} while (0)
/*------------------------------------------------.
| Report that the YYRULE is going to be reduced. |
`------------------------------------------------*/
static void
yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule, sparp_t * sparp_arg)
{
unsigned long int yylno = yyrline[yyrule];
int yynrhs = yyr2[yyrule];
int yyi;
YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
yyrule - 1, yylno);
/* The symbols being reduced. */
for (yyi = 0; yyi < yynrhs; yyi++)
{
YYFPRINTF (stderr, " $%d = ", yyi + 1);
yy_symbol_print (stderr,
yystos[yyssp[yyi + 1 - yynrhs]],
&(yyvsp[(yyi + 1) - (yynrhs)])
, sparp_arg);
YYFPRINTF (stderr, "\n");
}
}
# define YY_REDUCE_PRINT(Rule) \
do { \
if (yydebug) \
yy_reduce_print (yyssp, yyvsp, Rule, sparp_arg); \
} while (0)
/* Nonzero means print parse trace. It is left uninitialized so that
multiple parsers can coexist. */
int yydebug;
#else /* !YYDEBUG */
# define YYDPRINTF(Args)
# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
# define YY_STACK_PRINT(Bottom, Top)
# define YY_REDUCE_PRINT(Rule)
#endif /* !YYDEBUG */
/* YYINITDEPTH -- initial size of the parser's stacks. */
#ifndef YYINITDEPTH
# define YYINITDEPTH 200
#endif
/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
if the built-in stack extension method is used).
Do not make this value too large; the results are undefined if
YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
evaluated with infinite-precision integer arithmetic. */
#ifndef YYMAXDEPTH
# define YYMAXDEPTH 10000
#endif
#if YYERROR_VERBOSE
# ifndef yystrlen
# if defined __GLIBC__ && defined _STRING_H
# define yystrlen strlen
# else
/* Return the length of YYSTR. */
static YYSIZE_T
yystrlen (const char *yystr)
{
YYSIZE_T yylen;
for (yylen = 0; yystr[yylen]; yylen++)
continue;
return yylen;
}
# endif
# endif
# ifndef yystpcpy
# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
# define yystpcpy stpcpy
# else
/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
YYDEST. */
static char *
yystpcpy (char *yydest, const char *yysrc)
{
char *yyd = yydest;
const char *yys = yysrc;
while ((*yyd++ = *yys++) != '\0')
continue;
return yyd - 1;
}
# endif
# endif
# ifndef yytnamerr
/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
quotes and backslashes, so that it's suitable for yyerror. The
heuristic is that double-quoting is unnecessary unless the string
contains an apostrophe, a comma, or backslash (other than
backslash-backslash). YYSTR is taken from yytname. If YYRES is
null, do not copy; instead, return the length of what the result
would have been. */
static YYSIZE_T
yytnamerr (char *yyres, const char *yystr)
{
if (*yystr == '"')
{
YYSIZE_T yyn = 0;
char const *yyp = yystr;
for (;;)
switch (*++yyp)
{
case '\'':
case ',':
goto do_not_strip_quotes;
case '\\':
if (*++yyp != '\\')
goto do_not_strip_quotes;
/* Fall through. */
default:
if (yyres)
yyres[yyn] = *yyp;
yyn++;
break;
case '"':
if (yyres)
yyres[yyn] = '\0';
return yyn;
}
do_not_strip_quotes: ;
}
if (! yyres)
return yystrlen (yystr);
return yystpcpy (yyres, yystr) - yyres;
}
# endif
/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
about the unexpected token YYTOKEN for the state stack whose top is
YYSSP.
Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is
not large enough to hold the message. In that case, also set
*YYMSG_ALLOC to the required number of bytes. Return 2 if the
required number of bytes is too large to store. */
static int
yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
yytype_int16 *yyssp, int yytoken)
{
YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]);
YYSIZE_T yysize = yysize0;
enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
/* Internationalized format string. */
const char *yyformat = YY_NULLPTR;
/* Arguments of yyformat. */
char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
/* Number of reported tokens (one for the "unexpected", one per
"expected"). */
int yycount = 0;
/* There are many possibilities here to consider:
- If this state is a consistent state with a default action, then
the only way this function was invoked is if the default action
is an error action. In that case, don't check for expected
tokens because there are none.
- The only way there can be no lookahead present (in yychar) is if
this state is a consistent state with a default action. Thus,
detecting the absence of a lookahead is sufficient to determine
that there is no unexpected or expected token to report. In that
case, just report a simple "syntax error".
- Don't assume there isn't a lookahead just because this state is a
consistent state with a default action. There might have been a
previous inconsistent state, consistent state with a non-default
action, or user semantic action that manipulated yychar.
- Of course, the expected token list depends on states to have
correct lookahead information, and it depends on the parser not
to perform extra reductions after fetching a lookahead from the
scanner and before detecting a syntax error. Thus, state merging
(from LALR or IELR) and default reductions corrupt the expected
token list. However, the list is correct for canonical LR with
one exception: it will still contain any token that will not be
accepted due to an error action in a later state.
*/
if (yytoken != YYEMPTY)
{
int yyn = yypact[*yyssp];
yyarg[yycount++] = yytname[yytoken];
if (!yypact_value_is_default (yyn))
{
/* Start YYX at -YYN if negative to avoid negative indexes in
YYCHECK. In other words, skip the first -YYN actions for
this state because they are default actions. */
int yyxbegin = yyn < 0 ? -yyn : 0;
/* Stay within bounds of both yycheck and yytname. */
int yychecklim = YYLAST - yyn + 1;
int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
int yyx;
for (yyx = yyxbegin; yyx < yyxend; ++yyx)
if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
&& !yytable_value_is_error (yytable[yyx + yyn]))
{
if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
{
yycount = 1;
yysize = yysize0;
break;
}
yyarg[yycount++] = yytname[yyx];
{
YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]);
if (! (yysize <= yysize1
&& yysize1 <= YYSTACK_ALLOC_MAXIMUM))
return 2;
yysize = yysize1;
}
}
}
}
switch (yycount)
{
# define YYCASE_(N, S) \
case N: \
yyformat = S; \
break
YYCASE_(0, YY_("syntax error"));
YYCASE_(1, YY_("syntax error, unexpected %s"));
YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
# undef YYCASE_
}
{
YYSIZE_T yysize1 = yysize + yystrlen (yyformat);
if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
return 2;
yysize = yysize1;
}
if (*yymsg_alloc < yysize)
{
*yymsg_alloc = 2 * yysize;
if (! (yysize <= *yymsg_alloc
&& *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
*yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
return 1;
}
/* Avoid sprintf, as that infringes on the user's name space.
Don't have undefined behavior even if the translation
produced a string with the wrong number of "%s"s. */
{
char *yyp = *yymsg;
int yyi = 0;
while ((*yyp = *yyformat) != '\0')
if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
{
yyp += yytnamerr (yyp, yyarg[yyi++]);
yyformat += 2;
}
else
{
yyp++;
yyformat++;
}
}
return 0;
}
#endif /* YYERROR_VERBOSE */
/*-----------------------------------------------.
| Release the memory associated to this symbol. |
`-----------------------------------------------*/
static void
yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep, sparp_t * sparp_arg)
{
YYUSE (yyvaluep);
YYUSE (sparp_arg);
if (!yymsg)
yymsg = "Deleting";
YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
YYUSE (yytype);
YY_IGNORE_MAYBE_UNINITIALIZED_END
}
/*----------.
| yyparse. |
`----------*/
int
yyparse (sparp_t * sparp_arg)
{
/* The lookahead symbol. */
int yychar;
/* The semantic value of the lookahead symbol. */
/* Default value used for initialization, for pacifying older GCCs
or non-GCC compilers. */
YY_INITIAL_VALUE (static YYSTYPE yyval_default;)
YYSTYPE yylval YY_INITIAL_VALUE (= yyval_default);
/* Number of syntax errors so far. */
int yynerrs;
int yystate;
/* Number of tokens to shift before error messages enabled. */
int yyerrstatus;
/* The stacks and their tools:
'yyss': related to states.
'yyvs': related to semantic values.
Refer to the stacks through separate pointers, to allow yyoverflow
to reallocate them elsewhere. */
/* The state stack. */
yytype_int16 yyssa[YYINITDEPTH];
yytype_int16 *yyss;
yytype_int16 *yyssp;
/* The semantic value stack. */
YYSTYPE yyvsa[YYINITDEPTH];
YYSTYPE *yyvs;
YYSTYPE *yyvsp;
YYSIZE_T yystacksize;
int yyn;
int yyresult;
/* Lookahead token as an internal (translated) token number. */
int yytoken = 0;
/* The variables used to return semantic value and location from the
action routines. */
YYSTYPE yyval;
#if YYERROR_VERBOSE
/* Buffer for error messages, and its allocated size. */
char yymsgbuf[128];
char *yymsg = yymsgbuf;
YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
#endif
#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
/* The number of symbols on the RHS of the reduced rule.
Keep to zero when no symbol should be popped. */
int yylen = 0;
yyssp = yyss = yyssa;
yyvsp = yyvs = yyvsa;
yystacksize = YYINITDEPTH;
YYDPRINTF ((stderr, "Starting parse\n"));
yystate = 0;
yyerrstatus = 0;
yynerrs = 0;
yychar = YYEMPTY; /* Cause a token to be read. */
goto yysetstate;
/*------------------------------------------------------------.
| yynewstate -- Push a new state, which is found in yystate. |
`------------------------------------------------------------*/
yynewstate:
/* In all cases, when you get here, the value and location stacks
have just been pushed. So pushing a state here evens the stacks. */
yyssp++;
yysetstate:
*yyssp = yystate;
if (yyss + yystacksize - 1 <= yyssp)
{
/* Get the current used size of the three stacks, in elements. */
YYSIZE_T yysize = yyssp - yyss + 1;
#ifdef yyoverflow
{
/* Give user a chance to reallocate the stack. Use copies of
these so that the &'s don't force the real ones into
memory. */
YYSTYPE *yyvs1 = yyvs;
yytype_int16 *yyss1 = yyss;
/* Each stack pointer address is followed by the size of the
data in use in that stack, in bytes. This used to be a
conditional around just the two extra args, but that might
be undefined if yyoverflow is a macro. */
yyoverflow (YY_("memory exhausted"),
&yyss1, yysize * sizeof (*yyssp),
&yyvs1, yysize * sizeof (*yyvsp),
&yystacksize);
yyss = yyss1;
yyvs = yyvs1;
}
#else /* no yyoverflow */
# ifndef YYSTACK_RELOCATE
goto yyexhaustedlab;
# else
/* Extend the stack our own way. */
if (YYMAXDEPTH <= yystacksize)
goto yyexhaustedlab;
yystacksize *= 2;
if (YYMAXDEPTH < yystacksize)
yystacksize = YYMAXDEPTH;
{
yytype_int16 *yyss1 = yyss;
union yyalloc *yyptr =
(union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
if (! yyptr)
goto yyexhaustedlab;
YYSTACK_RELOCATE (yyss_alloc, yyss);
YYSTACK_RELOCATE (yyvs_alloc, yyvs);
# undef YYSTACK_RELOCATE
if (yyss1 != yyssa)
YYSTACK_FREE (yyss1);
}
# endif
#endif /* no yyoverflow */
yyssp = yyss + yysize - 1;
yyvsp = yyvs + yysize - 1;
YYDPRINTF ((stderr, "Stack size increased to %lu\n",
(unsigned long int) yystacksize));
if (yyss + yystacksize - 1 <= yyssp)
YYABORT;
}
YYDPRINTF ((stderr, "Entering state %d\n", yystate));
if (yystate == YYFINAL)
YYACCEPT;
goto yybackup;
/*-----------.
| yybackup. |
`-----------*/
yybackup:
/* Do appropriate processing given the current state. Read a
lookahead token if we need one and don't already have one. */
/* First try to decide what to do without reference to lookahead token. */
yyn = yypact[yystate];
if (yypact_value_is_default (yyn))
goto yydefault;
/* Not known => get a lookahead token if don't already have one. */
/* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */
if (yychar == YYEMPTY)
{
YYDPRINTF ((stderr, "Reading a token: "));
yychar = yylex (&yylval, sparp_arg);
}
if (yychar <= YYEOF)
{
yychar = yytoken = YYEOF;
YYDPRINTF ((stderr, "Now at end of input.\n"));
}
else
{
yytoken = YYTRANSLATE (yychar);
YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
}
/* If the proper action on seeing token YYTOKEN is to reduce or to
detect an error, take that action. */
yyn += yytoken;
if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
goto yydefault;
yyn = yytable[yyn];
if (yyn <= 0)
{
if (yytable_value_is_error (yyn))
goto yyerrlab;
yyn = -yyn;
goto yyreduce;
}
/* Count tokens shifted since error; after three, turn off error
status. */
if (yyerrstatus)
yyerrstatus--;
/* Shift the lookahead token. */
YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
/* Discard the shifted token. */
yychar = YYEMPTY;
yystate = yyn;
YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
*++yyvsp = yylval;
YY_IGNORE_MAYBE_UNINITIALIZED_END
goto yynewstate;
/*-----------------------------------------------------------.
| yydefault -- do the default action for the current state. |
`-----------------------------------------------------------*/
yydefault:
yyn = yydefact[yystate];
if (yyn == 0)
goto yyerrlab;
goto yyreduce;
/*-----------------------------.
| yyreduce -- Do a reduction. |
`-----------------------------*/
yyreduce:
/* yyn is the number of a rule to reduce with. */
yylen = yyr2[yyn];
/* If YYLEN is nonzero, implement the default value of the action:
'$$ = $1'.
Otherwise, the following line sets YYVAL to garbage.
This behavior is undocumented and Bison
users should not rely upon it. Assigning to YYVAL
unconditionally makes the parser a bit smaller, and it avoids a
GCC warning that YYVAL may be used uninitialized. */
yyval = yyvsp[1-yylen];
YY_REDUCE_PRINT (yyn);
switch (yyn)
{
case 2:
#line 625 "sparql_p.y" /* yacc.c:1646 */
{ sparp_arg->sparp_entire_query = (yyval.tree) = (yyvsp[-1].tree); }
#line 3522 "sparql_p.c" /* yacc.c:1646 */
break;
case 3:
#line 626 "sparql_p.y" /* yacc.c:1646 */
{ sparp_arg->sparp_entire_query = (yyval.tree) = (yyvsp[-2].tree); }
#line 3528 "sparql_p.c" /* yacc.c:1646 */
break;
case 4:
#line 627 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_entire_query = (yyval.tree) = spar_make_topmost_qm_sql (sparp_arg); }
#line 3535 "sparql_p.c" /* yacc.c:1646 */
break;
case 5:
#line 629 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "(internal SPARQL processing error) SPARQL mark expected"); }
#line 3541 "sparql_p.c" /* yacc.c:1646 */
break;
case 6:
#line 633 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_topmost_sparul_sql (sparp_arg, (SPART **)t_list (0) ); }
#line 3548 "sparql_p.c" /* yacc.c:1646 */
break;
case 7:
#line 635 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_topmost_sparul_sql (sparp_arg, (SPART **)t_revlist_to_array ((yyvsp[0].backstack)) ); }
#line 3555 "sparql_p.c" /* yacc.c:1646 */
break;
case 8:
#line 637 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 3561 "sparql_p.c" /* yacc.c:1646 */
break;
case 14:
#line 655 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 3567 "sparql_p.c" /* yacc.c:1646 */
break;
case 15:
#line 656 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 3573 "sparql_p.c" /* yacc.c:1646 */
break;
case 16:
#line 660 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0200, "DEFINE"); }
#line 3579 "sparql_p.c" /* yacc.c:1646 */
break;
case 17:
#line 661 "sparql_p.y" /* yacc.c:1646 */
{
dk_set_t vals = (yyvsp[0].backstack);
while (NULL != vals) {
void * *val = (void * *)t_set_pop (&vals);
sparp_define (sparp_arg, (yyvsp[-1].box), (ptrlong)(val[0]), val[1]);
} }
#line 3590 "sparql_p.c" /* yacc.c:1646 */
break;
case 18:
#line 670 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 3596 "sparql_p.c" /* yacc.c:1646 */
break;
case 19:
#line 671 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 3602 "sparql_p.c" /* yacc.c:1646 */
break;
case 20:
#line 675 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)t_list (2, (ptrlong)QNAME, (yyvsp[0].box)); }
#line 3608 "sparql_p.c" /* yacc.c:1646 */
break;
case 21:
#line 676 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)t_list (2, (ptrlong)Q_IRI_REF, (yyvsp[0].box)); }
#line 3614 "sparql_p.c" /* yacc.c:1646 */
break;
case 22:
#line 677 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)t_list (2, (ptrlong)SPARQL_STRING, (yyvsp[0].box)); }
#line 3620 "sparql_p.c" /* yacc.c:1646 */
break;
case 23:
#line 678 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)t_list (2, (ptrlong)SPARQL_INTEGER, (yyvsp[0].box)); }
#line 3626 "sparql_p.c" /* yacc.c:1646 */
break;
case 24:
#line 679 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)t_list (2, (ptrlong)SPAR_VARIABLE, (void *)(yyvsp[0].tree)); }
#line 3632 "sparql_p.c" /* yacc.c:1646 */
break;
case 25:
#line 683 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 3638 "sparql_p.c" /* yacc.c:1646 */
break;
case 26:
#line 684 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != sparp_env()->spare_base_uri)
sparyyerror (sparp_arg, "Only one base declaration is allowed");
sparp_env()->spare_base_uri = (yyvsp[0].box); }
#line 3647 "sparql_p.c" /* yacc.c:1646 */
break;
case 27:
#line 688 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Missing <iri-string> after BASE keyword"); }
#line 3653 "sparql_p.c" /* yacc.c:1646 */
break;
case 28:
#line 692 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 3659 "sparql_p.c" /* yacc.c:1646 */
break;
case 29:
#line 693 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 3665 "sparql_p.c" /* yacc.c:1646 */
break;
case 30:
#line 697 "sparql_p.y" /* yacc.c:1646 */
{
if ((!strcmp ("sql:", (yyvsp[-1].box)) && strcmp ("sql:", (yyvsp[0].box)) && strcmp (OPENLINKSW_SQL_NS_URI, (yyvsp[0].box)))
|| (!strcmp ("bif:", (yyvsp[-1].box)) && strcmp ("bif:", (yyvsp[0].box)) && strcmp (OPENLINKSW_BIF_NS_URI, (yyvsp[0].box))))
sparyyerror (sparp_arg, "Prefixes 'sql:' and 'bif:' are reserved for SQL names");
t_set_push (&(sparp_env()->spare_namespace_prefixes), sparp_expand_q_iri_ref (sparp_arg, (yyvsp[0].box)));
t_set_push (&(sparp_env()->spare_namespace_prefixes), t_box_dv_short_nchars ((yyvsp[-1].box), box_length ((yyvsp[-1].box))-2)); }
#line 3676 "sparql_p.c" /* yacc.c:1646 */
break;
case 31:
#line 703 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Missing <namespace-iri-string> in PREFIX declaration"); }
#line 3682 "sparql_p.c" /* yacc.c:1646 */
break;
case 32:
#line 704 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Missing namespace prefix after PREFIX keyword"); }
#line 3688 "sparql_p.c" /* yacc.c:1646 */
break;
case 34:
#line 709 "sparql_p.y" /* yacc.c:1646 */
{
if (sparp_arg->sparp_macro_def_count)
sparyyerror (sparp_arg, "Some macro are defined before CREATE MACRO LIBRARY");
sparp_arg->sparp_macrolib_to_create = (yyvsp[0].tree)->_.qname.val;
sparp_arg->sparp_disable_storage_macro_lib = 2; }
#line 3698 "sparql_p.c" /* yacc.c:1646 */
break;
case 36:
#line 718 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 3704 "sparql_p.c" /* yacc.c:1646 */
break;
case 37:
#line 719 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 3710 "sparql_p.c" /* yacc.c:1646 */
break;
case 38:
#line 725 "sparql_p.y" /* yacc.c:1646 */
{
SPART *new_macro;
if (!sparp_arg->sparp_storage_is_set)
sparp_configure_storage_and_macro_libs (sparp_arg);
sparp_arg->sparp_macro_mode = SPARP_DEFARG;
new_macro = sparp_arg->sparp_current_macro = sparp_defmacro_init (sparp_arg, (yyvsp[0].tree)->_.qname.val);
sparp_defmacro_store (sparp_arg, new_macro); }
#line 3722 "sparql_p.c" /* yacc.c:1646 */
break;
case 39:
#line 732 "sparql_p.y" /* yacc.c:1646 */
{
sparp_defmacro_finalize (sparp_arg, (yyvsp[0].tree));
sparp_arg->sparp_macro_mode = 0; }
#line 3730 "sparql_p.c" /* yacc.c:1646 */
break;
case 40:
#line 738 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_current_macro->_.defmacro.paramnames = t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 3737 "sparql_p.c" /* yacc.c:1646 */
break;
case 41:
#line 740 "sparql_p.y" /* yacc.c:1646 */
{
SPART *curr = sparp_arg->sparp_current_macro;
if (NULL != (yyvsp[0].backstack))
curr->_.defmacro.localnames = t_revlist_to_array ((yyvsp[0].backstack));
sparp_arg->sparp_macro_mode = SPARP_DEFBODY; }
#line 3747 "sparql_p.c" /* yacc.c:1646 */
break;
case 42:
#line 745 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 3753 "sparql_p.c" /* yacc.c:1646 */
break;
case 43:
#line 746 "sparql_p.y" /* yacc.c:1646 */
{
SPART *curr = sparp_arg->sparp_current_macro;
sparp_make_defmacro_paramnames_from_template (sparp_arg, curr); }
#line 3761 "sparql_p.c" /* yacc.c:1646 */
break;
case 44:
#line 749 "sparql_p.y" /* yacc.c:1646 */
{
SPART *curr = sparp_arg->sparp_current_macro;
if (NULL != (yyvsp[-1].backstack))
curr->_.defmacro.localnames = t_revlist_to_array ((yyvsp[-1].backstack));
sparp_arg->sparp_macro_mode = SPARP_DEFBODY;
spar_gp_init (sparp_arg, DEFMACRO_L); }
#line 3772 "sparql_p.c" /* yacc.c:1646 */
break;
case 45:
#line 755 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_gp_finalize (sparp_arg, NULL); }
#line 3778 "sparql_p.c" /* yacc.c:1646 */
break;
case 46:
#line 756 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "List of arguments or template is expected after macro name"); }
#line 3784 "sparql_p.c" /* yacc.c:1646 */
break;
case 47:
#line 761 "sparql_p.y" /* yacc.c:1646 */
{
SPART *curr = sparp_arg->sparp_current_macro;
curr->_.defmacro.subtype = 0;
curr->_.defmacro.quad_pattern = (SPART **)t_list (4, NULL, (yyvsp[-3].tree), (yyvsp[-2].tree), (yyvsp[-1].tree));
sparp_arg->sparp_macro_mode = SPARP_DEFBODY; }
#line 3794 "sparql_p.c" /* yacc.c:1646 */
break;
case 48:
#line 766 "sparql_p.y" /* yacc.c:1646 */
{
SPART *curr = sparp_arg->sparp_current_macro;
curr->_.defmacro.subtype = GRAPH_L;
curr->_.defmacro.quad_pattern = (SPART **)t_list (4, (yyvsp[-5].tree), (yyvsp[-3].tree), (yyvsp[-2].tree), (yyvsp[-1].tree));
sparp_arg->sparp_macro_mode = SPARP_DEFBODY; }
#line 3804 "sparql_p.c" /* yacc.c:1646 */
break;
case 49:
#line 771 "sparql_p.y" /* yacc.c:1646 */
{
SPART *curr = sparp_arg->sparp_current_macro;
curr->_.defmacro.subtype = DEFAULT_L;
curr->_.defmacro.quad_pattern = (SPART **)t_list (4, NULL, (yyvsp[-3].tree), (yyvsp[-2].tree), (yyvsp[-1].tree));
sparp_arg->sparp_macro_mode = SPARP_DEFBODY; }
#line 3814 "sparql_p.c" /* yacc.c:1646 */
break;
case 50:
#line 779 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 3820 "sparql_p.c" /* yacc.c:1646 */
break;
case 51:
#line 780 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); }
#line 3826 "sparql_p.c" /* yacc.c:1646 */
break;
case 52:
#line 781 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); }
#line 3832 "sparql_p.c" /* yacc.c:1646 */
break;
case 53:
#line 785 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 3838 "sparql_p.c" /* yacc.c:1646 */
break;
case 56:
#line 791 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = NULL;
t_set_push (&((yyval.backstack)), (yyvsp[-2].box));
sparp_check_dm_arg_for_redecl (sparp_arg, (yyval.backstack), (yyvsp[0].box));
t_set_push (&((yyval.backstack)), (yyvsp[0].box)); }
#line 3848 "sparql_p.c" /* yacc.c:1646 */
break;
case 57:
#line 796 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = (yyvsp[-2].backstack);
sparp_check_dm_arg_for_redecl (sparp_arg, (yyval.backstack), (yyvsp[0].box));
t_set_push (&((yyval.backstack)), (yyvsp[0].box)); }
#line 3857 "sparql_p.c" /* yacc.c:1646 */
break;
case 58:
#line 803 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].box)); }
#line 3863 "sparql_p.c" /* yacc.c:1646 */
break;
case 59:
#line 804 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = (yyvsp[-1].backstack);
sparp_check_dm_arg_for_redecl (sparp_arg, (yyval.backstack), (yyvsp[0].box));
t_set_push (&((yyval.backstack)), (yyvsp[0].box)); }
#line 3872 "sparql_p.c" /* yacc.c:1646 */
break;
case 60:
#line 811 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_param_or_variable (sparp_arg, (yyvsp[0].box)); }
#line 3878 "sparql_p.c" /* yacc.c:1646 */
break;
case 62:
#line 816 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_param_or_variable (sparp_arg, (yyvsp[0].box)); }
#line 3884 "sparql_p.c" /* yacc.c:1646 */
break;
case 63:
#line 817 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_type); }
#line 3890 "sparql_p.c" /* yacc.c:1646 */
break;
case 65:
#line 823 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_param_or_variable (sparp_arg, (yyvsp[0].box)); }
#line 3896 "sparql_p.c" /* yacc.c:1646 */
break;
case 67:
#line 825 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_nil); }
#line 3902 "sparql_p.c" /* yacc.c:1646 */
break;
case 71:
#line 833 "sparql_p.y" /* yacc.c:1646 */
{
SPART *curr = sparp_arg->sparp_current_macro;
curr->_.defmacro.subtype = 0;
spar_gp_init (sparp_arg, DEFMACRO_L); }
#line 3911 "sparql_p.c" /* yacc.c:1646 */
break;
case 72:
#line 837 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_gp_finalize (sparp_arg, NULL); }
#line 3917 "sparql_p.c" /* yacc.c:1646 */
break;
case 74:
#line 839 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Graph group pattern or expression is expected as the body of the macro"); }
#line 3923 "sparql_p.c" /* yacc.c:1646 */
break;
case 75:
#line 845 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL);
sparp_arg->sparp_allow_aggregates_in_expn |= 1; }
#line 3931 "sparql_p.c" /* yacc.c:1646 */
break;
case 76:
#line 849 "sparql_p.y" /* yacc.c:1646 */
{
SPART *where_gp = spar_gp_finalize (sparp_arg, NULL);
SPART *wm = (yyvsp[0].tree);
wm->_.wm.where_gp = where_gp;
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, (yyvsp[-5].token_type), (yyvsp[-3].trees), wm );
if (SPAR_REQ_TOP == (yyval.tree)->type)
sparp_expand_top_retvals (sparp_arg, (yyval.tree), 0 /* never cloned, hence 0 == safely_copy_all_vars */, NULL); }
#line 3943 "sparql_p.c" /* yacc.c:1646 */
break;
case 77:
#line 859 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SELECT_L; }
#line 3949 "sparql_p.c" /* yacc.c:1646 */
break;
case 78:
#line 860 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SELECT_L; }
#line 3955 "sparql_p.c" /* yacc.c:1646 */
break;
case 79:
#line 861 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = DISTINCT_L; }
#line 3961 "sparql_p.c" /* yacc.c:1646 */
break;
case 80:
#line 862 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = COUNT_DISTINCT_L; }
#line 3967 "sparql_p.c" /* yacc.c:1646 */
break;
case 81:
#line 866 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = sparp_arg->sparp_rset_lexdepth_plus_1; sparp_arg->sparp_rset_lexdepth_plus_1 = sparp_arg->sparp_lexdepth + 1; }
#line 3973 "sparql_p.c" /* yacc.c:1646 */
break;
case 82:
#line 867 "sparql_p.y" /* yacc.c:1646 */
{ sparp_arg->sparp_rset_lexdepth_plus_1 = (yyvsp[-1].token_type); (yyval.trees) = (yyvsp[0].trees); }
#line 3979 "sparql_p.c" /* yacc.c:1646 */
break;
case 83:
#line 871 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **) _STAR; }
#line 3985 "sparql_p.c" /* yacc.c:1646 */
break;
case 84:
#line 873 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **) t_revlist_to_array ((yyvsp[0].backstack)); }
#line 3991 "sparql_p.c" /* yacc.c:1646 */
break;
case 85:
#line 874 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0200, "comma-delimited list of result set expressions");
(yyval.trees) = (SPART **) t_revlist_to_array ((yyvsp[0].backstack)); }
#line 3999 "sparql_p.c" /* yacc.c:1646 */
break;
case 86:
#line 880 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL); }
#line 4006 "sparql_p.c" /* yacc.c:1646 */
break;
case 87:
#line 883 "sparql_p.y" /* yacc.c:1646 */
{
const char *fmt_mode_name;
const char *formatter, *agg_formatter, *agg_mdata;
SPART *where_gp = spar_gp_finalize (sparp_arg, NULL);
SPART *wm = (yyvsp[0].tree);
wm->_.wm.where_gp = where_gp;
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, CONSTRUCT_L, NULL, wm );
fmt_mode_name = (yyval.tree)->_.req_top.formatmode_name;
ssg_find_formatter_by_name_and_subtype (fmt_mode_name, CONSTRUCT_L, &formatter, &agg_formatter, &agg_mdata);
spar_compose_retvals_of_construct (sparp_arg, (yyval.tree), (yyvsp[-3].tree), formatter, agg_formatter, agg_mdata); }
#line 4021 "sparql_p.c" /* yacc.c:1646 */
break;
case 88:
#line 893 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_allow_aggregates_in_expn &= ~1;
sparp_arg->sparp_in_ctor_from_where = 1;
spar_gp_init (sparp_arg, WHERE_L); }
#line 4030 "sparql_p.c" /* yacc.c:1646 */
break;
case 89:
#line 897 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_in_ctor_from_where = 0; }
#line 4037 "sparql_p.c" /* yacc.c:1646 */
break;
case 90:
#line 899 "sparql_p.y" /* yacc.c:1646 */
{
const char *fmt_mode_name;
const char *formatter, *agg_formatter, *agg_mdata;
SPART *where_gp = spar_gp_finalize (sparp_arg, NULL);
SPART *wm = (yyvsp[0].tree);
SPART *tmpl_gp;
wm->_.wm.where_gp = where_gp;
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, CONSTRUCT_L, NULL, wm );
fmt_mode_name = (yyval.tree)->_.req_top.formatmode_name;
ssg_find_formatter_by_name_and_subtype (fmt_mode_name, CONSTRUCT_L, &formatter, &agg_formatter, &agg_mdata);
tmpl_gp = spar_compose_ctor_gp_from_where_gp (sparp_arg, CONSTRUCT_L, where_gp, NULL);
spar_compose_retvals_of_construct (sparp_arg, (yyval.tree), tmpl_gp, formatter, agg_formatter, agg_mdata); }
#line 4054 "sparql_p.c" /* yacc.c:1646 */
break;
case 91:
#line 915 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL); }
#line 4061 "sparql_p.c" /* yacc.c:1646 */
break;
case 92:
#line 918 "sparql_p.y" /* yacc.c:1646 */
{
SPART * where_gp = spar_gp_finalize (sparp_arg, NULL);
SPART *wm = (yyvsp[0].tree);
wm->_.wm.where_gp = where_gp;
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, DESCRIBE_L, (yyvsp[-3].trees), wm );
if (((SPART **)_STAR == (yyvsp[-3].trees)) && (SPAR_REQ_TOP == (yyval.tree)->type))
sparp_expand_top_retvals (sparp_arg, (yyval.tree), 0 /* never cloned, hence 0 == safely_copy_all_vars */, NULL); }
#line 4073 "sparql_p.c" /* yacc.c:1646 */
break;
case 93:
#line 928 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **) _STAR; }
#line 4079 "sparql_p.c" /* yacc.c:1646 */
break;
case 94:
#line 929 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **) t_list_to_array ((yyvsp[0].backstack)); }
#line 4085 "sparql_p.c" /* yacc.c:1646 */
break;
case 95:
#line 933 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL); }
#line 4092 "sparql_p.c" /* yacc.c:1646 */
break;
case 96:
#line 936 "sparql_p.y" /* yacc.c:1646 */
{
SPART * where_gp = spar_gp_finalize (sparp_arg, NULL);
(yyval.tree) = spar_make_top (sparp_arg, ASK_L, (SPART **)t_list(0),
where_gp, NULL, NULL, NULL, (SPART *)t_box_num(1), (SPART *)t_box_num(0), NULL ); }
#line 4101 "sparql_p.c" /* yacc.c:1646 */
break;
case 97:
#line 943 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4107 "sparql_p.c" /* yacc.c:1646 */
break;
case 98:
#line 944 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4113 "sparql_p.c" /* yacc.c:1646 */
break;
case 99:
#line 952 "sparql_p.y" /* yacc.c:1646 */
{
sparp_make_and_push_new_graph_source (sparp_arg, (yyvsp[-2].token_type), (yyvsp[-1].tree), (yyvsp[0].trees), SPARP_SSRC_FROZEN_BY_PROTOCOL); }
#line 4120 "sparql_p.c" /* yacc.c:1646 */
break;
case 100:
#line 957 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != sparp_arg->sparp_env->spare_src.ssrc_graph_set_by_with)
sparyyerror (sparp_arg, "FROM can not be used in combination with WITH, use either consistent SPARUL syntax or SPARQL 1.1 syntax, not a mix");
(yyval.token_type) = (yyvsp[0].token_type); }
#line 4129 "sparql_p.c" /* yacc.c:1646 */
break;
case 101:
#line 961 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x2000, "USING keyword");
(yyval.token_type) = (yyvsp[0].token_type); }
#line 4137 "sparql_p.c" /* yacc.c:1646 */
break;
case 102:
#line 967 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPART_GRAPH_FROM; }
#line 4143 "sparql_p.c" /* yacc.c:1646 */
break;
case 103:
#line 968 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPART_GRAPH_NAMED; }
#line 4149 "sparql_p.c" /* yacc.c:1646 */
break;
case 104:
#line 969 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPART_GRAPH_NOT_FROM; }
#line 4155 "sparql_p.c" /* yacc.c:1646 */
break;
case 105:
#line 970 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPART_GRAPH_NOT_NAMED; }
#line 4161 "sparql_p.c" /* yacc.c:1646 */
break;
case 106:
#line 974 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPART_GRAPH_FROM; }
#line 4167 "sparql_p.c" /* yacc.c:1646 */
break;
case 107:
#line 975 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPART_GRAPH_NAMED; }
#line 4173 "sparql_p.c" /* yacc.c:1646 */
break;
case 108:
#line 976 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPART_GRAPH_NOT_FROM; }
#line 4179 "sparql_p.c" /* yacc.c:1646 */
break;
case 109:
#line 977 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPART_GRAPH_NOT_NAMED; }
#line 4185 "sparql_p.c" /* yacc.c:1646 */
break;
case 110:
#line 981 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = NULL; }
#line 4191 "sparql_p.c" /* yacc.c:1646 */
break;
case 111:
#line 982 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0002, "OPTION () sponge configuration"); }
#line 4197 "sparql_p.c" /* yacc.c:1646 */
break;
case 112:
#line 983 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (yyvsp[0].trees); }
#line 4203 "sparql_p.c" /* yacc.c:1646 */
break;
case 113:
#line 987 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (0); }
#line 4209 "sparql_p.c" /* yacc.c:1646 */
break;
case 114:
#line 988 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 4215 "sparql_p.c" /* yacc.c:1646 */
break;
case 115:
#line 992 "sparql_p.y" /* yacc.c:1646 */
{ /* [Virt] SpongeOption ::= QNAME PrecodeExpn */
(yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[-1].box)); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4222 "sparql_p.c" /* yacc.c:1646 */
break;
case 116:
#line 994 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = (yyvsp[-3].backstack); t_set_push (&((yyval.backstack)), (yyvsp[-1].box)); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4229 "sparql_p.c" /* yacc.c:1646 */
break;
case 117:
#line 999 "sparql_p.y" /* yacc.c:1646 */
{ sparp_arg->sparp_in_precode_expn = 1; }
#line 4235 "sparql_p.c" /* yacc.c:1646 */
break;
case 118:
#line 1001 "sparql_p.y" /* yacc.c:1646 */
{ sparp_arg->sparp_in_precode_expn = 0; (yyval.tree) = (yyvsp[0].tree); }
#line 4241 "sparql_p.c" /* yacc.c:1646 */
break;
case 119:
#line 1005 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_allow_aggregates_in_expn &= ~1;
spar_gp_init (sparp_arg, WHERE_L); }
#line 4249 "sparql_p.c" /* yacc.c:1646 */
break;
case 120:
#line 1008 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4255 "sparql_p.c" /* yacc.c:1646 */
break;
case 121:
#line 1012 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != sparp_arg->sparp_env->spare_need_for_default_sparul_target) /* trick for bug 16901 */
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, sparp_arg->sparp_env->spare_need_for_default_sparul_target, 0);
if (NULL != sparp_arg->sparp_env->spare_src.ssrc_fallback_default_graph)
spar_apply_fallback_default_graph (sparp_arg, 0);
sparp_arg->sparp_allow_aggregates_in_expn &= ~1;
spar_gp_init (sparp_arg, WHERE_L); }
#line 4267 "sparql_p.c" /* yacc.c:1646 */
break;
case 122:
#line 1019 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4273 "sparql_p.c" /* yacc.c:1646 */
break;
case 123:
#line 1020 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != sparp_arg->sparp_env->spare_need_for_default_sparul_target) /* trick for bug 16901 */
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, sparp_arg->sparp_env->spare_need_for_default_sparul_target, 0);
if (NULL != sparp_arg->sparp_env->spare_src.ssrc_fallback_default_graph)
spar_apply_fallback_default_graph (sparp_arg, 0);
sparp_arg->sparp_allow_aggregates_in_expn &= ~1;
spar_gp_init (sparp_arg, WHERE_L); }
#line 4285 "sparql_p.c" /* yacc.c:1646 */
break;
case 124:
#line 1027 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4291 "sparql_p.c" /* yacc.c:1646 */
break;
case 125:
#line 1031 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4297 "sparql_p.c" /* yacc.c:1646 */
break;
case 126:
#line 1032 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_member (sparp_arg, (yyvsp[0].tree)); }
#line 4303 "sparql_p.c" /* yacc.c:1646 */
break;
case 127:
#line 1039 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_wm (sparp_arg, NULL, (yyvsp[-3].trees), (yyvsp[-2].tree), (yyvsp[-1].trees), NULL, (SPART *)t_box_num (0), (yyvsp[0].tree)); }
#line 4309 "sparql_p.c" /* yacc.c:1646 */
break;
case 128:
#line 1040 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_wm (sparp_arg, NULL, (yyvsp[-5].trees), (yyvsp[-4].tree), (yyvsp[-3].trees), (yyvsp[-2].tree), (yyvsp[-1].tree), (yyvsp[0].tree)); }
#line 4315 "sparql_p.c" /* yacc.c:1646 */
break;
case 129:
#line 1041 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_wm (sparp_arg, NULL, (yyvsp[-5].trees), (yyvsp[-4].tree), (yyvsp[-3].trees), (yyvsp[-1].tree), (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 4321 "sparql_p.c" /* yacc.c:1646 */
break;
case 130:
#line 1045 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = NULL; }
#line 4327 "sparql_p.c" /* yacc.c:1646 */
break;
case 131:
#line 1046 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_allow_aggregates_in_expn |= 1; }
#line 4334 "sparql_p.c" /* yacc.c:1646 */
break;
case 132:
#line 1048 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[0].backstack));
sparp_arg->sparp_allow_aggregates_in_expn &= ~1; }
#line 4342 "sparql_p.c" /* yacc.c:1646 */
break;
case 133:
#line 1054 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[0].backstack); }
#line 4348 "sparql_p.c" /* yacc.c:1646 */
break;
case 134:
#line 1055 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4354 "sparql_p.c" /* yacc.c:1646 */
break;
case 135:
#line 1059 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4360 "sparql_p.c" /* yacc.c:1646 */
break;
case 136:
#line 1060 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4366 "sparql_p.c" /* yacc.c:1646 */
break;
case 137:
#line 1065 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[-1].tree); }
#line 4372 "sparql_p.c" /* yacc.c:1646 */
break;
case 138:
#line 1066 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[-1].tree); }
#line 4378 "sparql_p.c" /* yacc.c:1646 */
break;
case 142:
#line 1070 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "GROUP BY clause contains a binary operator expression that is not enclosed in (...)"); }
#line 4384 "sparql_p.c" /* yacc.c:1646 */
break;
case 143:
#line 1074 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_builtin_call (sparp_arg, SPAR_BIF__GROUPING_SETS, (SPART **)t_revlist_to_array ((yyvsp[-1].backstack))); }
#line 4390 "sparql_p.c" /* yacc.c:1646 */
break;
case 144:
#line 1075 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_builtin_call (sparp_arg, SPAR_BIF__ROLLUP, (SPART **)t_revlist_to_array ((yyvsp[-1].backstack))); }
#line 4396 "sparql_p.c" /* yacc.c:1646 */
break;
case 145:
#line 1076 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_builtin_call (sparp_arg, SPAR_BIF__CUBE, (SPART **)t_revlist_to_array ((yyvsp[-1].backstack))); }
#line 4402 "sparql_p.c" /* yacc.c:1646 */
break;
case 146:
#line 1080 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4408 "sparql_p.c" /* yacc.c:1646 */
break;
case 147:
#line 1081 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4414 "sparql_p.c" /* yacc.c:1646 */
break;
case 148:
#line 1085 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = sparp_make_builtin_call (sparp_arg, SPAR_BIF__GROUPING_SET, (SPART **)t_list (2, NULL,
sparp_make_builtin_call (sparp_arg, SPAR_BIF__GROUPING_LIST, (SPART **)t_list (0)) ) ); }
#line 4422 "sparql_p.c" /* yacc.c:1646 */
break;
case 149:
#line 1088 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = sparp_make_builtin_call (sparp_arg, SPAR_BIF__GROUPING_SET, (SPART **)t_list (2, NULL,
sparp_make_builtin_call (sparp_arg, SPAR_BIF__GROUPING_LIST, (SPART **)t_revlist_to_array ((yyvsp[-1].backstack))) ) ); }
#line 4430 "sparql_p.c" /* yacc.c:1646 */
break;
case 150:
#line 1091 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = sparp_make_builtin_call (sparp_arg, SPAR_BIF__GROUPING_SET, (SPART **)t_list (2, (yyvsp[-2].tree),
sparp_make_builtin_call (sparp_arg, SPAR_BIF__GROUPING_LIST, (SPART **)t_revlist_to_array ((yyvsp[-1].backstack))) ) ); }
#line 4438 "sparql_p.c" /* yacc.c:1646 */
break;
case 151:
#line 1097 "sparql_p.y" /* yacc.c:1646 */
{
if (0 == (yyvsp[-1].token_type))
(yyval.tree) = NULL;
else
(yyval.tree) = sparp_make_builtin_call (sparp_arg, TOP_L, (SPART **)t_list (4, (yyvsp[-1].token_type), NULL, NULL, NULL)); }
#line 4448 "sparql_p.c" /* yacc.c:1646 */
break;
case 152:
#line 1102 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = sparp_make_builtin_call (sparp_arg, TOP_L, (SPART **)t_list (4, (yyvsp[-4].token_type), (yyvsp[-2].tree), NULL, (yyvsp[-1].token_type))); }
#line 4455 "sparql_p.c" /* yacc.c:1646 */
break;
case 153:
#line 1104 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = sparp_make_builtin_call (sparp_arg, TOP_L, (SPART **)t_list (4, (yyvsp[-6].token_type), (yyvsp[-3].tree), NULL, (yyvsp[-1].token_type))); }
#line 4462 "sparql_p.c" /* yacc.c:1646 */
break;
case 154:
#line 1106 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = sparp_make_builtin_call (sparp_arg, TOP_L, (SPART **)t_list (4, (yyvsp[-6].token_type), (yyvsp[-4].tree), (yyvsp[-2].tree), (yyvsp[-1].token_type))); }
#line 4469 "sparql_p.c" /* yacc.c:1646 */
break;
case 155:
#line 1108 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = sparp_make_builtin_call (sparp_arg, TOP_L, (SPART **)t_list (4, (yyvsp[-8].token_type), (yyvsp[-5].tree), (yyvsp[-3].tree), (yyvsp[-1].token_type))); }
#line 4476 "sparql_p.c" /* yacc.c:1646 */
break;
case 156:
#line 1113 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = 0; }
#line 4482 "sparql_p.c" /* yacc.c:1646 */
break;
case 157:
#line 1114 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = ALL_L; }
#line 4488 "sparql_p.c" /* yacc.c:1646 */
break;
case 158:
#line 1115 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = DISTINCT_L; }
#line 4494 "sparql_p.c" /* yacc.c:1646 */
break;
case 159:
#line 1119 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = 0; }
#line 4500 "sparql_p.c" /* yacc.c:1646 */
break;
case 160:
#line 1120 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = 1; }
#line 4506 "sparql_p.c" /* yacc.c:1646 */
break;
case 171:
#line 1138 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 4512 "sparql_p.c" /* yacc.c:1646 */
break;
case 172:
#line 1139 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_allow_aggregates_in_expn |= 1; }
#line 4519 "sparql_p.c" /* yacc.c:1646 */
break;
case 173:
#line 1141 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = (yyvsp[0].tree);
sparp_arg->sparp_allow_aggregates_in_expn &= ~1; }
#line 4527 "sparql_p.c" /* yacc.c:1646 */
break;
case 174:
#line 1147 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 4533 "sparql_p.c" /* yacc.c:1646 */
break;
case 175:
#line 1148 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_BIN_OP ((yyval.tree), BOP_AND, (yyvsp[-1].tree), (yyvsp[0].tree)); }
#line 4539 "sparql_p.c" /* yacc.c:1646 */
break;
case 176:
#line 1152 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = NULL; }
#line 4545 "sparql_p.c" /* yacc.c:1646 */
break;
case 177:
#line 1153 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_allow_aggregates_in_expn |= 1; }
#line 4552 "sparql_p.c" /* yacc.c:1646 */
break;
case 178:
#line 1155 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[0].backstack));
sparp_arg->sparp_allow_aggregates_in_expn &= ~1; }
#line 4560 "sparql_p.c" /* yacc.c:1646 */
break;
case 179:
#line 1161 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4566 "sparql_p.c" /* yacc.c:1646 */
break;
case 180:
#line 1162 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = dk_set_conc ((yyvsp[0].backstack), t_cons ((void*) (yyvsp[-1].tree), NULL)); }
#line 4572 "sparql_p.c" /* yacc.c:1646 */
break;
case 181:
#line 1163 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = dk_set_conc ((yyvsp[0].backstack), t_cons ((void*) (yyvsp[-2].tree), NULL)); }
#line 4578 "sparql_p.c" /* yacc.c:1646 */
break;
case 182:
#line 1167 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4584 "sparql_p.c" /* yacc.c:1646 */
break;
case 183:
#line 1168 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4590 "sparql_p.c" /* yacc.c:1646 */
break;
case 184:
#line 1172 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4596 "sparql_p.c" /* yacc.c:1646 */
break;
case 185:
#line 1173 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4602 "sparql_p.c" /* yacc.c:1646 */
break;
case 186:
#line 1178 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 3, ORDER_L, (ptrlong)(yyvsp[-3].token_type), (yyvsp[-1].tree)); }
#line 4608 "sparql_p.c" /* yacc.c:1646 */
break;
case 187:
#line 1179 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 3, ORDER_L, (ptrlong)(yyvsp[-3].token_type), (yyvsp[-1].tree)); }
#line 4614 "sparql_p.c" /* yacc.c:1646 */
break;
case 188:
#line 1180 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 3, ORDER_L, (ptrlong)(yyvsp[-1].token_type), (yyvsp[0].box)); }
#line 4620 "sparql_p.c" /* yacc.c:1646 */
break;
case 189:
#line 1181 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 3, ORDER_L, (ptrlong)ASC_L, (yyvsp[0].tree)); }
#line 4626 "sparql_p.c" /* yacc.c:1646 */
break;
case 190:
#line 1182 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 3, ORDER_L, (ptrlong)ASC_L, (yyvsp[0].tree)); }
#line 4632 "sparql_p.c" /* yacc.c:1646 */
break;
case 191:
#line 1183 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 3, ORDER_L, (ptrlong)ASC_L, (yyvsp[0].tree)); }
#line 4638 "sparql_p.c" /* yacc.c:1646 */
break;
case 192:
#line 1187 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = 0; }
#line 4644 "sparql_p.c" /* yacc.c:1646 */
break;
case 193:
#line 1188 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = ASC_L; }
#line 4650 "sparql_p.c" /* yacc.c:1646 */
break;
case 194:
#line 1189 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = DESC_L; }
#line 4656 "sparql_p.c" /* yacc.c:1646 */
break;
case 195:
#line 1193 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 4662 "sparql_p.c" /* yacc.c:1646 */
break;
case 197:
#line 1198 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = ((NULL != (yyvsp[0].tree)) ? (yyvsp[0].tree) : (SPART *)(t_box_num_nonull (0))); }
#line 4668 "sparql_p.c" /* yacc.c:1646 */
break;
case 198:
#line 1202 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 4674 "sparql_p.c" /* yacc.c:1646 */
break;
case 200:
#line 1207 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = ((NULL != (yyvsp[0].tree)) ? (yyvsp[0].tree) : ((SPART *)t_box_num_nonull (0))); }
#line 4680 "sparql_p.c" /* yacc.c:1646 */
break;
case 201:
#line 1211 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 4686 "sparql_p.c" /* yacc.c:1646 */
break;
case 202:
#line 1212 "sparql_p.y" /* yacc.c:1646 */
{
if (sparp_arg->sparp_macro_mode)
sparyyerror (sparp_arg, "BINDINGS and trailing VALUES can not be used inside macro");
(yyval.tree) = spar_make_bindings_inv_with_fake_equivs (sparp_arg,
sparp_arg->sparp_env->spare_bindings_vars, sparp_arg->sparp_env->spare_bindings_rowset, NULL); }
#line 4696 "sparql_p.c" /* yacc.c:1646 */
break;
case 203:
#line 1219 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != sparp_arg->sparp_env->spare_bindings_vars)
sparyyerror (sparp_arg, "Only one BINDINGS or trailing VALUES clause per query is allowed"); }
#line 4704 "sparql_p.c" /* yacc.c:1646 */
break;
case 204:
#line 1222 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_env->spare_bindings_vars = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 4711 "sparql_p.c" /* yacc.c:1646 */
break;
case 205:
#line 1224 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_env->spare_bindings_rowset = (SPART ***)t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 4718 "sparql_p.c" /* yacc.c:1646 */
break;
case 206:
#line 1226 "sparql_p.y" /* yacc.c:1646 */
{
SPART ***mtrx = (SPART ***)t_revlist_to_array ((yyvsp[-1].backstack));
int ctr = BOX_ELEMENTS (mtrx);
while (ctr--) mtrx[ctr] = (SPART **)t_list (1, mtrx[ctr]);
if (NULL != sparp_arg->sparp_env->spare_bindings_vars)
sparyyerror (sparp_arg, "Only one BINDINGS or trailing VALUES clause per query is allowed");
sparp_arg->sparp_env->spare_bindings_vars = (SPART **)t_list (1, spar_make_variable (sparp_arg, (yyvsp[-3].box)));
sparp_arg->sparp_env->spare_bindings_rowset = mtrx; }
#line 4731 "sparql_p.c" /* yacc.c:1646 */
break;
case 207:
#line 1234 "sparql_p.y" /* yacc.c:1646 */
{
SPART **vars = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack));
if (NULL != sparp_arg->sparp_env->spare_bindings_vars)
sparyyerror (sparp_arg, "Only one BINDINGS or trailing VALUES clause per query is allowed");
sparp_arg->sparp_env->spare_bindings_vars = vars;
sparp_arg->sparp_env->spare_inline_data_colcount = BOX_ELEMENTS (vars); }
#line 4742 "sparql_p.c" /* yacc.c:1646 */
break;
case 208:
#line 1240 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_env->spare_bindings_rowset = (SPART ***)t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 4749 "sparql_p.c" /* yacc.c:1646 */
break;
case 209:
#line 1245 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), spar_make_variable (sparp_arg, (yyvsp[0].box))); }
#line 4755 "sparql_p.c" /* yacc.c:1646 */
break;
case 210:
#line 1246 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), spar_make_variable (sparp_arg, (yyvsp[0].box))); }
#line 4761 "sparql_p.c" /* yacc.c:1646 */
break;
case 211:
#line 1250 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4767 "sparql_p.c" /* yacc.c:1646 */
break;
case 212:
#line 1251 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Global variable can not be used in the header of BINDINGS"); }
#line 4773 "sparql_p.c" /* yacc.c:1646 */
break;
case 213:
#line 1255 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 4779 "sparql_p.c" /* yacc.c:1646 */
break;
case 215:
#line 1260 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].trees)); }
#line 4785 "sparql_p.c" /* yacc.c:1646 */
break;
case 216:
#line 1261 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].trees)); }
#line 4791 "sparql_p.c" /* yacc.c:1646 */
break;
case 217:
#line 1265 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack));
if (BOX_ELEMENTS ((yyval.trees)) != BOX_ELEMENTS (sparp_arg->sparp_env->spare_bindings_vars))
sparyyerror (sparp_arg, "Number of values in a binding does not match number of variables to bind"); }
#line 4800 "sparql_p.c" /* yacc.c:1646 */
break;
case 218:
#line 1272 "sparql_p.y" /* yacc.c:1646 */
{(yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4806 "sparql_p.c" /* yacc.c:1646 */
break;
case 219:
#line 1273 "sparql_p.y" /* yacc.c:1646 */
{(yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 4812 "sparql_p.c" /* yacc.c:1646 */
break;
case 225:
#line 1282 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "UNBOUND in BINDINGS is deprecated, use UNDEF instead"); (yyval.tree) = NULL; }
#line 4818 "sparql_p.c" /* yacc.c:1646 */
break;
case 226:
#line 1283 "sparql_p.y" /* yacc.c:1646 */
{(yyval.tree) = NULL; }
#line 4824 "sparql_p.c" /* yacc.c:1646 */
break;
case 227:
#line 1287 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_gp_finalize (sparp_arg, (yyvsp[0].trees));
sparp_validate_options_of_tree (sparp_arg, (yyval.tree), (yyval.tree)->_.gp.options); }
#line 4832 "sparql_p.c" /* yacc.c:1646 */
break;
case 228:
#line 1290 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 4838 "sparql_p.c" /* yacc.c:1646 */
break;
case 229:
#line 1294 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.token_type) = (ptrlong)(sparp_env()->spare_context_gp_subtypes->data);
if (NULL == sparp_env()->spare_context_sinvs) { /* There's an exception related to codegen-time optimization SERVICE { SELECT {x}} like it is SERVICE {x}, so no error right here. */
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0111, "subquery"); }
if ((SERVICE_L == (yyval.token_type)) || (OPTIONAL_L == (yyval.token_type)) || (WHERE_L == (yyval.token_type)))
spar_gp_init (sparp_arg, SELECT_L);
spar_env_push (sparp_arg);
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL);
sparp_arg->sparp_allow_aggregates_in_expn <<= 1;
sparp_arg->sparp_allow_aggregates_in_expn |= 1; }
#line 4853 "sparql_p.c" /* yacc.c:1646 */
break;
case 230:
#line 1306 "sparql_p.y" /* yacc.c:1646 */
{
SPART *subselect_top;
SPART *where_gp;
SPART *wm = (yyvsp[-2].tree);
SPART *res;
where_gp = spar_gp_finalize (sparp_arg, NULL);
wm->_.wm.where_gp = where_gp;
subselect_top = spar_make_top_or_special_case_from_wm (sparp_arg, (yyvsp[-7].token_type), (yyvsp[-5].trees), wm );
if (SPAR_REQ_TOP == subselect_top->type)
sparp_expand_top_retvals (sparp_arg, subselect_top, 1 /* safely_copy_all_vars */, NULL);
spar_env_pop (sparp_arg);
if ((NULL != (yyvsp[0].trees)) && (WHERE_L == (yyval.token_type)))
sparyyerror (sparp_arg, "The use of OPTIONS requires WHERE { { SELECT { ... } } OPTIONS (...) } syntax, to avoid ambiguity");
res = spar_gp_finalize_with_subquery (sparp_arg, (yyvsp[0].trees), subselect_top);
if ((SERVICE_L == (yyvsp[-6].token_type)) || (OPTIONAL_L == (yyvsp[-6].token_type)) || (WHERE_L == (yyval.token_type)))
{
spar_gp_add_member (sparp_arg, res);
res = spar_gp_finalize (sparp_arg, NULL);
}
(yyval.tree) = res;
sparp_arg->sparp_allow_aggregates_in_expn >>= 1; }
#line 4879 "sparql_p.c" /* yacc.c:1646 */
break;
case 231:
#line 1330 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4885 "sparql_p.c" /* yacc.c:1646 */
break;
case 232:
#line 1331 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4891 "sparql_p.c" /* yacc.c:1646 */
break;
case 233:
#line 1332 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 4897 "sparql_p.c" /* yacc.c:1646 */
break;
case 234:
#line 1333 "sparql_p.y" /* yacc.c:1646 */
{
if (sparp_arg->sparp_macro_mode & SPARP_DEFBODY)
{
SPART *curmacro = sparp_arg->sparp_current_macro;
SPART *mpu;
int pos = sparp_namesake_macro_param (sparp_arg, curmacro, (yyvsp[-2].box));
if (0 > pos)
spar_error (sparp_arg, "Pattern variable '%.100s' inside the body of a macro '%.100s' is not listed in list of macro parameters",
(yyvsp[-2].box), curmacro->_.defmacro.mname );
mpu = spar_make_macropu (sparp_arg, (yyvsp[-2].box), pos);
spar_gp_add_member (sparp_arg, mpu);
}
else
sparyyerror (sparp_arg, "Ill formed triple pattern or macro pattern variable outside a macro body"); }
#line 4916 "sparql_p.c" /* yacc.c:1646 */
break;
case 235:
#line 1350 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_member (sparp_arg, (yyvsp[0].tree)); }
#line 4922 "sparql_p.c" /* yacc.c:1646 */
break;
case 236:
#line 1351 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_member (sparp_arg, (yyvsp[0].tree)); }
#line 4928 "sparql_p.c" /* yacc.c:1646 */
break;
case 237:
#line 1352 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_member (sparp_arg, (yyvsp[0].tree)); }
#line 4934 "sparql_p.c" /* yacc.c:1646 */
break;
case 238:
#line 1353 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_member (sparp_arg, (yyvsp[0].tree)); }
#line 4940 "sparql_p.c" /* yacc.c:1646 */
break;
case 239:
#line 1354 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_member (sparp_arg, (yyvsp[0].tree)); }
#line 4946 "sparql_p.c" /* yacc.c:1646 */
break;
case 240:
#line 1355 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_finalize_binds (sparp_arg, (yyvsp[0].backstack)); }
#line 4952 "sparql_p.c" /* yacc.c:1646 */
break;
case 241:
#line 1356 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_member (sparp_arg, (yyvsp[0].tree)); }
#line 4958 "sparql_p.c" /* yacc.c:1646 */
break;
case 242:
#line 1357 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_filter (sparp_arg, (yyvsp[0].tree), 1); }
#line 4964 "sparql_p.c" /* yacc.c:1646 */
break;
case 243:
#line 1358 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_filter (sparp_arg, sparp_make_builtin_call (sparp_arg, ASSUME_L, (SPART **)t_list (1, (yyvsp[0].tree))), 1); }
#line 4970 "sparql_p.c" /* yacc.c:1646 */
break;
case 244:
#line 1359 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'MINUS' DatasetClause* WhereClause */
/*!!! Dirty hack! Works wrong if MINUS is at the middle of the GP (before smth or not a 2-nd item) */
SPART *expn;
SPAR_BIN_OP (expn, BOP_NOT, (yyvsp[0].tree), NULL);
spar_gp_add_filter (sparp_arg, expn, 1); }
#line 4980 "sparql_p.c" /* yacc.c:1646 */
break;
case 245:
#line 1367 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_init (sparp_arg, OPTIONAL_L); }
#line 4986 "sparql_p.c" /* yacc.c:1646 */
break;
case 246:
#line 1367 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 4992 "sparql_p.c" /* yacc.c:1646 */
break;
case 247:
#line 1368 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Missing '{' after OPTIONAL keyword"); }
#line 4998 "sparql_p.c" /* yacc.c:1646 */
break;
case 248:
#line 1372 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0001, "QUAD MAP { ... } group pattern"); }
#line 5004 "sparql_p.c" /* yacc.c:1646 */
break;
case 249:
#line 1373 "sparql_p.y" /* yacc.c:1646 */
{ t_set_push (&(sparp_env()->spare_context_qms), (yyvsp[0].trees)); }
#line 5010 "sparql_p.c" /* yacc.c:1646 */
break;
case 250:
#line 1374 "sparql_p.y" /* yacc.c:1646 */
{
spar_gp_init (sparp_arg, 0); }
#line 5017 "sparql_p.c" /* yacc.c:1646 */
break;
case 251:
#line 1376 "sparql_p.y" /* yacc.c:1646 */
{ t_set_pop (&(sparp_env()->spare_context_qms)); (yyval.tree) = (yyvsp[0].tree); }
#line 5023 "sparql_p.c" /* yacc.c:1646 */
break;
case 252:
#line 1381 "sparql_p.y" /* yacc.c:1646 */
{ t_set_push (&(sparp_env()->spare_context_graphs), (yyvsp[0].tree)); }
#line 5029 "sparql_p.c" /* yacc.c:1646 */
break;
case 253:
#line 1382 "sparql_p.y" /* yacc.c:1646 */
{
spar_gp_init (sparp_arg, 0);
spar_gp_add_filters_for_named_graph (sparp_arg); }
#line 5037 "sparql_p.c" /* yacc.c:1646 */
break;
case 254:
#line 1385 "sparql_p.y" /* yacc.c:1646 */
{ t_set_pop (&(sparp_env()->spare_context_graphs)); (yyval.tree) = (yyvsp[0].tree); }
#line 5043 "sparql_p.c" /* yacc.c:1646 */
break;
case 255:
#line 1389 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_init (sparp_arg, 0); }
#line 5049 "sparql_p.c" /* yacc.c:1646 */
break;
case 256:
#line 1389 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 5055 "sparql_p.c" /* yacc.c:1646 */
break;
case 257:
#line 1390 "sparql_p.y" /* yacc.c:1646 */
{
sparp_env()->spare_good_graph_varnames = sparp_env()->spare_good_graph_bmk;
if ((yyvsp[-1].token_type) != (yyvsp[-2].tree)->_.gp.subtype) {
spar_gp_init (sparp_arg, (yyvsp[-1].token_type));
spar_gp_add_member (sparp_arg, (yyvsp[-2].tree)); }
spar_gp_init (sparp_arg, 0); }
#line 5066 "sparql_p.c" /* yacc.c:1646 */
break;
case 258:
#line 1396 "sparql_p.y" /* yacc.c:1646 */
{
if ((yyvsp[-3].token_type) != (yyvsp[-4].tree)->_.gp.subtype) {
spar_gp_add_member (sparp_arg, (yyvsp[0].tree));
(yyval.tree) = spar_gp_finalize (sparp_arg, NULL); }
else {
(yyval.tree)->_.gp.members = (SPART **)t_list_concat_tail ((void *)((yyval.tree)->_.gp.members), 1, (yyvsp[0].tree));
(yyval.tree) = (yyvsp[-4].tree); }
}
#line 5079 "sparql_p.c" /* yacc.c:1646 */
break;
case 259:
#line 1407 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = UNION_L; }
#line 5085 "sparql_p.c" /* yacc.c:1646 */
break;
case 260:
#line 1408 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SPAR_UNION_WO_ALL; }
#line 5091 "sparql_p.c" /* yacc.c:1646 */
break;
case 261:
#line 1412 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 5097 "sparql_p.c" /* yacc.c:1646 */
break;
case 262:
#line 1413 "sparql_p.y" /* yacc.c:1646 */
{ t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 5103 "sparql_p.c" /* yacc.c:1646 */
break;
case 263:
#line 1417 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.nonboxed_int) = sparp_arg->sparp_scalar_subq_count; }
#line 5109 "sparql_p.c" /* yacc.c:1646 */
break;
case 264:
#line 1418 "sparql_p.y" /* yacc.c:1646 */
{
int bind_has_scalar_subqs = ((yyvsp[-3].nonboxed_int) == sparp_arg->sparp_scalar_subq_count);
(yyval.tree) = spar_bind_prepare (sparp_arg, (yyvsp[-1].tree), bind_has_scalar_subqs); }
#line 5117 "sparql_p.c" /* yacc.c:1646 */
break;
case 265:
#line 1424 "sparql_p.y" /* yacc.c:1646 */
{
spar_gp_init (sparp_arg, VALUES_L); }
#line 5124 "sparql_p.c" /* yacc.c:1646 */
break;
case 266:
#line 1426 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 5130 "sparql_p.c" /* yacc.c:1646 */
break;
case 267:
#line 1430 "sparql_p.y" /* yacc.c:1646 */
{
SPART ***mtrx = (SPART ***)t_revlist_to_array ((yyvsp[-1].backstack));
int ctr = BOX_ELEMENTS (mtrx);
while (ctr--) mtrx[ctr] = (SPART **)t_list (1, mtrx[ctr]);
(yyval.tree) = spar_gp_finalize_with_inline_data (sparp_arg, (SPART **)t_list (1, spar_make_variable (sparp_arg, (yyvsp[-3].box))), mtrx); }
#line 5140 "sparql_p.c" /* yacc.c:1646 */
break;
case 268:
#line 1435 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_env->spare_inline_data_colcount = dk_set_length ((yyvsp[-1].backstack)); }
#line 5147 "sparql_p.c" /* yacc.c:1646 */
break;
case 269:
#line 1437 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_gp_finalize_with_inline_data (sparp_arg, (SPART **)t_revlist_to_array ((yyvsp[-5].backstack)), (SPART ***)t_revlist_to_array ((yyvsp[-1].backstack))); }
#line 5154 "sparql_p.c" /* yacc.c:1646 */
break;
case 270:
#line 1443 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 5160 "sparql_p.c" /* yacc.c:1646 */
break;
case 271:
#line 1444 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), spar_make_variable (sparp_arg, (yyvsp[0].box))); }
#line 5166 "sparql_p.c" /* yacc.c:1646 */
break;
case 272:
#line 1448 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = (yyvsp[0].box); }
#line 5172 "sparql_p.c" /* yacc.c:1646 */
break;
case 273:
#line 1449 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Global variable can not be used in the header of VALUES"); }
#line 5178 "sparql_p.c" /* yacc.c:1646 */
break;
case 274:
#line 1453 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 5184 "sparql_p.c" /* yacc.c:1646 */
break;
case 275:
#line 1454 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].trees)); }
#line 5190 "sparql_p.c" /* yacc.c:1646 */
break;
case 276:
#line 1458 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack));
if (BOX_ELEMENTS ((yyval.trees)) != sparp_arg->sparp_env->spare_inline_data_colcount)
sparyyerror (sparp_arg, "Number of values in an inline data row does not match number of variables in the list after VALUES"); }
#line 5199 "sparql_p.c" /* yacc.c:1646 */
break;
case 277:
#line 1465 "sparql_p.y" /* yacc.c:1646 */
{(yyval.backstack) = NULL; }
#line 5205 "sparql_p.c" /* yacc.c:1646 */
break;
case 278:
#line 1466 "sparql_p.y" /* yacc.c:1646 */
{(yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 5211 "sparql_p.c" /* yacc.c:1646 */
break;
case 283:
#line 1474 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "The use of blank nodes in VALUES is not allowed by SPARQL 1.1 specification"); (yyval.tree) = NULL; }
#line 5217 "sparql_p.c" /* yacc.c:1646 */
break;
case 284:
#line 1475 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "UNBOUND in VALUES is deprecated, use UNDEF instead"); (yyval.tree) = NULL; }
#line 5223 "sparql_p.c" /* yacc.c:1646 */
break;
case 285:
#line 1476 "sparql_p.y" /* yacc.c:1646 */
{(yyval.tree) = NULL; }
#line 5229 "sparql_p.c" /* yacc.c:1646 */
break;
case 286:
#line 1480 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[-1].tree); }
#line 5235 "sparql_p.c" /* yacc.c:1646 */
break;
case 287:
#line 1481 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 5241 "sparql_p.c" /* yacc.c:1646 */
break;
case 288:
#line 1482 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 5247 "sparql_p.c" /* yacc.c:1646 */
break;
case 289:
#line 1486 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = 1; }
#line 5253 "sparql_p.c" /* yacc.c:1646 */
break;
case 290:
#line 1487 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = 0; }
#line 5259 "sparql_p.c" /* yacc.c:1646 */
break;
case 291:
#line 1491 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x2000, "SPARQL 1.1 FILTER EXISTS / FILTER NOT EXISTS test");
spar_gp_init (sparp_arg, SELECT_L);
spar_env_push (sparp_arg);
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL);
sparp_arg->sparp_allow_aggregates_in_expn <<= 1; }
#line 5270 "sparql_p.c" /* yacc.c:1646 */
break;
case 292:
#line 1499 "sparql_p.y" /* yacc.c:1646 */
{
SPART *subselect_top;
SPART *where_gp;
where_gp = spar_gp_finalize (sparp_arg, NULL);
subselect_top = spar_make_top (sparp_arg, ASK_L, (SPART **)t_list(0),
where_gp, NULL, NULL, NULL, (SPART *)t_box_num(1), (SPART *)t_box_num(0), NULL );
spar_env_pop (sparp_arg);
(yyval.tree) = spar_gp_finalize_with_subquery (sparp_arg, (yyvsp[0].trees), subselect_top);
sparp_arg->sparp_allow_aggregates_in_expn >>= 1; }
#line 5284 "sparql_p.c" /* yacc.c:1646 */
break;
case 293:
#line 1511 "sparql_p.y" /* yacc.c:1646 */
{
void * sinv_storage_uri;
sparp_arg->sparp_query_uses_sinvs++;
sinv_storage_uri = uname_virtrdf_ns_uri_DefaultServiceStorage; /*!!! TBD config */
/* if config is added above then tweak the check in sparp_gp_trav_add_graph_perm_read_filters and in SPAR_REQ_TOP case of ssg_sdprint_tree() */
(yyval.boxes) = t_list (5,
t_box_num(sparp_arg->sparp_permitted_syntax),
sparp_arg->sparp_env->spare_storage_name,
sparp_arg->sparp_storage,
(ptrlong)(sparp_arg->sparp_storage_is_set),
sinv_storage_uri );
sparp_arg->sparp_inner_permitted_syntax = -1;
sparp_arg->sparp_env->spare_storage_name = sinv_storage_uri;
sparp_arg->sparp_storage = sparp_find_storage_by_name (sparp_arg, sinv_storage_uri);
sparp_arg->sparp_storage_is_set = 1;
}
#line 5305 "sparql_p.c" /* yacc.c:1646 */
break;
case 294:
#line 1527 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.box) = t_alloc (sizeof (sparp_sources_t));
if (-1 == sparp_arg->sparp_inner_permitted_syntax)
{
sparp_find_language_dialect_by_service (sparp_arg, (yyvsp[-2].tree), &(sparp_arg->sparp_permitted_syntax), &(sparp_arg->sparp_syntax_exceptions));
sparp_arg->sparp_permitted_syntax |= 0x0080;
}
else
sparp_arg->sparp_permitted_syntax = 0x0080 | sparp_arg->sparp_inner_permitted_syntax;
memcpy ((yyval.box), &(sparp_arg->sparp_env->spare_src), sizeof (sparp_sources_t));
memset (&(sparp_arg->sparp_env->spare_src), 0, sizeof (sparp_sources_t)); }
#line 5321 "sparql_p.c" /* yacc.c:1646 */
break;
case 295:
#line 1538 "sparql_p.y" /* yacc.c:1646 */
{
void * sinv_storage_uri = (yyvsp[-4].boxes)[4];
SPART **sources;
SPART *sinv;
if ((NULL == sparp_arg->sparp_env->spare_src.ssrc_default_graphs) && (NULL == sparp_arg->sparp_env->spare_src.ssrc_named_graphs))
memcpy (&(sparp_arg->sparp_env->spare_src), (yyvsp[-2].box), sizeof (sparp_sources_t));
sources = spar_make_sources_like_top (sparp_arg, SELECT_L);
sinv = spar_make_service_inv (sparp_arg, (yyvsp[-5].tree), (yyvsp[-3].backstack), sparp_arg->sparp_permitted_syntax, sparp_arg->sparp_syntax_exceptions, sources, sinv_storage_uri, (yyvsp[-6].token_type));
spar_add_service_inv_to_sg (sparp_arg, sinv);
t_set_push (&(sparp_env()->spare_context_sinvs), sinv);
spar_gp_init (sparp_arg, SERVICE_L); }
#line 5337 "sparql_p.c" /* yacc.c:1646 */
break;
case 296:
#line 1549 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_permitted_syntax = unbox((yyvsp[-6].boxes)[0]);
sparp_arg->sparp_env->spare_storage_name = (yyvsp[-6].boxes)[1];
sparp_arg->sparp_storage = (quad_storage_t *)((yyvsp[-6].boxes)[2]);
sparp_arg->sparp_storage_is_set = (ptrlong)((yyvsp[-6].boxes)[3]);
(yyvsp[0].tree)->_.gp.options = (SPART **)t_list_concat_tail (
(void *)((yyvsp[0].tree)->_.gp.options), 2,
SPAR_SERVICE_INV, t_set_pop (&(sparp_env()->spare_context_sinvs)) );
memcpy (&(sparp_arg->sparp_env->spare_src), (yyvsp[-4].box), sizeof (sparp_sources_t));
(yyval.tree) = (yyvsp[0].tree); }
#line 5352 "sparql_p.c" /* yacc.c:1646 */
break;
case 297:
#line 1561 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (SPART *)((ptrlong)IN_L)); t_set_push (&((yyval.backstack)), (SPART *)((ptrlong)_STAR)); }
#line 5358 "sparql_p.c" /* yacc.c:1646 */
break;
case 298:
#line 1562 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); }
#line 5364 "sparql_p.c" /* yacc.c:1646 */
break;
case 299:
#line 1566 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 5370 "sparql_p.c" /* yacc.c:1646 */
break;
case 300:
#line 1567 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[0]); t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[1]); }
#line 5376 "sparql_p.c" /* yacc.c:1646 */
break;
case 301:
#line 1571 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, (yyvsp[-1].box), (yyvsp[0].backstack)); }
#line 5382 "sparql_p.c" /* yacc.c:1646 */
break;
case 302:
#line 1572 "sparql_p.y" /* yacc.c:1646 */
{
void * defname = (yyvsp[-1].box);
dk_set_t defvals = (yyvsp[0].backstack);
if (!strcmp (defname, "lang:dialect"))
{
if ((NULL == defvals) || (NULL != defvals->next) || (SPARQL_INTEGER != ((ptrlong *)(defvals->data))[0]))
sparyyerror (sparp_arg, "define lang:dialect needs an integer");
sparp_arg->sparp_inner_permitted_syntax = unbox (((void * *)(defvals->data))[1]) | 0x0080;
}
(yyval.trees) = (SPART **)t_list (2, (SPART *)((ptrlong)DEFINE_L), t_list (2, defname, t_revlist_to_array(defvals))); }
#line 5397 "sparql_p.c" /* yacc.c:1646 */
break;
case 303:
#line 1582 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, (SPART *)((ptrlong)IN_L), t_revlist_to_array ((yyvsp[0].backstack))); }
#line 5403 "sparql_p.c" /* yacc.c:1646 */
break;
case 304:
#line 1583 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, (SPART *)((ptrlong)IN_L), (SPART *)((ptrlong)_STAR)); }
#line 5409 "sparql_p.c" /* yacc.c:1646 */
break;
case 305:
#line 1587 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_init (sparp_arg, CONSTRUCT_L); }
#line 5415 "sparql_p.c" /* yacc.c:1646 */
break;
case 306:
#line 1588 "sparql_p.y" /* yacc.c:1646 */
{
int g_grp_count = sparp_env()->spare_ctor_g_grp_count;
int g_may_vary = 0;
(yyval.tree) = spar_gp_finalize (sparp_arg, NULL);
if (1 < (g_grp_count + (sparp_env()->spare_ctor_dflt_g_tmpl_count ? 1 : 0)))
g_may_vary = 1;
if ((0 == g_may_vary) && (0 < BOX_ELEMENTS ((yyval.tree)->_.gp.members)))
{
SPART *g = (yyval.tree)->_.gp.members[0]->_.triple.tr_graph;
if ((SPAR_QNAME != SPART_TYPE (g)) && !SPART_IS_DEFAULT_GRAPH_BLANK (g))
g_may_vary = 1;
}
if (g_may_vary)
(yyval.tree)->_.gp.options = (SPART **)t_list (2, (SPART *)((ptrlong)QUAD_L), t_box_num_nonull (g_grp_count));
sparp_env()->spare_ctor_g_grp_count = 0;
sparp_env()->spare_ctor_dflt_g_tmpl_count = 0; }
#line 5436 "sparql_p.c" /* yacc.c:1646 */
break;
case 307:
#line 1607 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5442 "sparql_p.c" /* yacc.c:1646 */
break;
case 308:
#line 1608 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5448 "sparql_p.c" /* yacc.c:1646 */
break;
case 309:
#line 1609 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5454 "sparql_p.c" /* yacc.c:1646 */
break;
case 310:
#line 1610 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5460 "sparql_p.c" /* yacc.c:1646 */
break;
case 311:
#line 1614 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5466 "sparql_p.c" /* yacc.c:1646 */
break;
case 312:
#line 1615 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5472 "sparql_p.c" /* yacc.c:1646 */
break;
case 313:
#line 1616 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5478 "sparql_p.c" /* yacc.c:1646 */
break;
case 314:
#line 1620 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5484 "sparql_p.c" /* yacc.c:1646 */
break;
case 315:
#line 1621 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5490 "sparql_p.c" /* yacc.c:1646 */
break;
case 316:
#line 1622 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5496 "sparql_p.c" /* yacc.c:1646 */
break;
case 317:
#line 1623 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5502 "sparql_p.c" /* yacc.c:1646 */
break;
case 318:
#line 1627 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5508 "sparql_p.c" /* yacc.c:1646 */
break;
case 319:
#line 1628 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5514 "sparql_p.c" /* yacc.c:1646 */
break;
case 320:
#line 1632 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5520 "sparql_p.c" /* yacc.c:1646 */
break;
case 321:
#line 1633 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5526 "sparql_p.c" /* yacc.c:1646 */
break;
case 322:
#line 1637 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x2000, "SPARQL 1.1 quad constructor template"); }
#line 5532 "sparql_p.c" /* yacc.c:1646 */
break;
case 323:
#line 1638 "sparql_p.y" /* yacc.c:1646 */
{
sparp_env()->spare_ctor_g_grp_count++;
t_set_push (&(sparp_env()->spare_context_graphs), (yyvsp[0].tree)); }
#line 5540 "sparql_p.c" /* yacc.c:1646 */
break;
case 324:
#line 1641 "sparql_p.y" /* yacc.c:1646 */
{ t_set_pop (&(sparp_env()->spare_context_graphs)); }
#line 5546 "sparql_p.c" /* yacc.c:1646 */
break;
case 325:
#line 1645 "sparql_p.y" /* yacc.c:1646 */
{ t_set_push (&(sparp_env()->spare_context_subjects), (yyvsp[0].tree)); }
#line 5552 "sparql_p.c" /* yacc.c:1646 */
break;
case 326:
#line 1646 "sparql_p.y" /* yacc.c:1646 */
{ t_set_pop (&(sparp_env()->spare_context_subjects)); (yyval.nothing) = (yyvsp[0].nothing); }
#line 5558 "sparql_p.c" /* yacc.c:1646 */
break;
case 327:
#line 1647 "sparql_p.y" /* yacc.c:1646 */
{ t_set_push (&(sparp_env()->spare_context_subjects), (yyvsp[0].tree)); }
#line 5564 "sparql_p.c" /* yacc.c:1646 */
break;
case 328:
#line 1648 "sparql_p.y" /* yacc.c:1646 */
{ t_set_pop (&(sparp_env()->spare_context_subjects)); }
#line 5570 "sparql_p.c" /* yacc.c:1646 */
break;
case 329:
#line 1649 "sparql_p.y" /* yacc.c:1646 */
{ spar_gp_add_member (sparp_arg, (yyvsp[0].tree)); }
#line 5576 "sparql_p.c" /* yacc.c:1646 */
break;
case 330:
#line 1653 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5582 "sparql_p.c" /* yacc.c:1646 */
break;
case 331:
#line 1654 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5588 "sparql_p.c" /* yacc.c:1646 */
break;
case 332:
#line 1660 "sparql_p.y" /* yacc.c:1646 */
{ t_set_push (&(sparp_env()->spare_context_predicates), (yyvsp[0].tree)); }
#line 5594 "sparql_p.c" /* yacc.c:1646 */
break;
case 333:
#line 1661 "sparql_p.y" /* yacc.c:1646 */
{ t_set_pop (&(sparp_env()->spare_context_predicates)); }
#line 5600 "sparql_p.c" /* yacc.c:1646 */
break;
case 334:
#line 1663 "sparql_p.y" /* yacc.c:1646 */
{ t_set_push (&(sparp_env()->spare_context_predicates), (yyvsp[0].tree)); }
#line 5606 "sparql_p.c" /* yacc.c:1646 */
break;
case 335:
#line 1664 "sparql_p.y" /* yacc.c:1646 */
{ t_set_pop (&(sparp_env()->spare_context_predicates)); }
#line 5612 "sparql_p.c" /* yacc.c:1646 */
break;
case 336:
#line 1665 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Dot immediately after semicolon is permitted in pure SPARQL but not in SPARQL-BI"); }
#line 5618 "sparql_p.c" /* yacc.c:1646 */
break;
case 337:
#line 1666 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Predicate expected after semicolon"); }
#line 5624 "sparql_p.c" /* yacc.c:1646 */
break;
case 338:
#line 1667 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Predicate expected"); }
#line 5630 "sparql_p.c" /* yacc.c:1646 */
break;
case 339:
#line 1671 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5636 "sparql_p.c" /* yacc.c:1646 */
break;
case 340:
#line 1672 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 5642 "sparql_p.c" /* yacc.c:1646 */
break;
case 341:
#line 1673 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Semicolon immediately after colon is permitted in pure SPARQL but not in SPARQL-BI"); }
#line 5648 "sparql_p.c" /* yacc.c:1646 */
break;
case 342:
#line 1674 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Dot immediately after colon is permitted in pure SPARQL but not in SPARQL-BI"); }
#line 5654 "sparql_p.c" /* yacc.c:1646 */
break;
case 343:
#line 1675 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Object expected after comma"); }
#line 5660 "sparql_p.c" /* yacc.c:1646 */
break;
case 344:
#line 1676 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Object expected"); }
#line 5666 "sparql_p.c" /* yacc.c:1646 */
break;
case 345:
#line 1680 "sparql_p.y" /* yacc.c:1646 */
{
spar_gp_add_triplelike (sparp_arg, NULL, NULL, NULL, (yyvsp[-1].tree), NULL, (yyvsp[0].trees), 0x0); }
#line 5673 "sparql_p.c" /* yacc.c:1646 */
break;
case 346:
#line 1685 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = NULL; }
#line 5679 "sparql_p.c" /* yacc.c:1646 */
break;
case 347:
#line 1686 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, TABID_L, (yyvsp[0].box)); }
#line 5685 "sparql_p.c" /* yacc.c:1646 */
break;
case 348:
#line 1687 "sparql_p.y" /* yacc.c:1646 */
{
if (CONSTRUCT_L == SPARP_ENV_CONTEXT_GP_SUBTYPE(sparp_arg))
sparyyerror (sparp_arg, "Triple options are not allowed in constructor template");
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0002, "OPTION () triple matching configuration"); }
#line 5694 "sparql_p.c" /* yacc.c:1646 */
break;
case 349:
#line 1691 "sparql_p.y" /* yacc.c:1646 */
{
SPART **opts = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack));
(yyval.trees) = opts; }
#line 5702 "sparql_p.c" /* yacc.c:1646 */
break;
case 350:
#line 1697 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), ((SPART **)((yyvsp[0].trees)))[0]); t_set_push (&((yyval.backstack)), ((SPART **)((yyvsp[0].trees)))[1]); }
#line 5708 "sparql_p.c" /* yacc.c:1646 */
break;
case 351:
#line 1698 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), ((SPART **)((yyvsp[0].trees)))[0]); t_set_push (&((yyval.backstack)), ((SPART **)((yyvsp[0].trees)))[1]); }
#line 5714 "sparql_p.c" /* yacc.c:1646 */
break;
case 352:
#line 1702 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0200, "TABLE OPTION hint for SQL optimizer");
(yyval.trees) = (SPART **)t_list (2, (ptrlong)TABLE_OPTION_L, (yyvsp[0].box)); }
#line 5722 "sparql_p.c" /* yacc.c:1646 */
break;
case 353:
#line 1705 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0200, "TABID OPTION hint for using in SQL code");
(yyval.trees) = (SPART **)t_list (2, (ptrlong)TABID_L, (yyvsp[0].box)); }
#line 5730 "sparql_p.c" /* yacc.c:1646 */
break;
case 354:
#line 1708 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0200, "inference option");
(yyval.trees) = (yyvsp[0].trees); }
#line 5738 "sparql_p.c" /* yacc.c:1646 */
break;
case 355:
#line 1711 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0200, "free-text option");
(yyval.trees) = (yyvsp[0].trees); }
#line 5746 "sparql_p.c" /* yacc.c:1646 */
break;
case 356:
#line 1714 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0200, "geo/spatial option");
(yyval.trees) = (yyvsp[0].trees); }
#line 5754 "sparql_p.c" /* yacc.c:1646 */
break;
case 357:
#line 1717 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x1000, "TRANSITIVE and related options");
(yyval.trees) = (yyvsp[0].trees); }
#line 5762 "sparql_p.c" /* yacc.c:1646 */
break;
case 358:
#line 1723 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'IFP' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)IFP_L, (ptrlong)1); }
#line 5769 "sparql_p.c" /* yacc.c:1646 */
break;
case 359:
#line 1725 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'INFERENCE' ( QNAME | Q_IRI_REF | SPARQL_STRING ) */
if (strcasecmp ((yyvsp[0].box), "none"))
(yyval.trees) = (SPART **)t_list (2, (ptrlong)INFERENCE_L, (yyvsp[0].box));
else
(yyval.trees) = (SPART **)t_list (2, (ptrlong)INFERENCE_L, (ptrlong)1); }
#line 5779 "sparql_p.c" /* yacc.c:1646 */
break;
case 360:
#line 1730 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.trees) = (SPART **)t_list (2, (ptrlong)INFERENCE_L, sparp_expand_qname_prefix (sparp_arg, (yyvsp[0].box))); }
#line 5786 "sparql_p.c" /* yacc.c:1646 */
break;
case 361:
#line 1732 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, (ptrlong)INFERENCE_L, sparp_expand_q_iri_ref (sparp_arg, (yyvsp[0].box))); }
#line 5792 "sparql_p.c" /* yacc.c:1646 */
break;
case 362:
#line 1733 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, (ptrlong)INFERENCE_L, (yyvsp[0].box)); }
#line 5798 "sparql_p.c" /* yacc.c:1646 */
break;
case 363:
#line 1734 "sparql_p.y" /* yacc.c:1646 */
{ /*... | ( 'SAME_AS' | 'SAME_AS_O' | 'SAME_AS_P_L' | 'SAME_AS_S' | 'SAME_AS_S_O_L' ) ( '(' Expns ')' )? */
(yyval.trees) = (SPART **)t_list (2, (yyvsp[-3].token_type), spartlist (sparp_arg, 2, SPAR_LIST, t_revlist_to_array ((yyvsp[-1].backstack)))); }
#line 5805 "sparql_p.c" /* yacc.c:1646 */
break;
case 364:
#line 1736 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, (yyvsp[0].token_type), (ptrlong)1); }
#line 5811 "sparql_p.c" /* yacc.c:1646 */
break;
case 365:
#line 1740 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'OFFBAND' Var */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)OFFBAND_L, (yyvsp[0].tree)); }
#line 5818 "sparql_p.c" /* yacc.c:1646 */
break;
case 366:
#line 1742 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'SCORE' Var */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)SCORE_L, (yyvsp[0].tree)); }
#line 5825 "sparql_p.c" /* yacc.c:1646 */
break;
case 367:
#line 1744 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'SCORE_LIMIT' Expn */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)SCORE_LIMIT_L, (yyvsp[0].tree)); }
#line 5832 "sparql_p.c" /* yacc.c:1646 */
break;
case 368:
#line 1749 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'GEO' Expn */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)GEO_L, (yyvsp[0].tree)); }
#line 5839 "sparql_p.c" /* yacc.c:1646 */
break;
case 369:
#line 1751 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'PRECISION' Expn */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)PRECISION_L, (yyvsp[0].tree)); }
#line 5846 "sparql_p.c" /* yacc.c:1646 */
break;
case 370:
#line 1756 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_CYCLES_ONLY' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_CYCLES_ONLY_L, (ptrlong)1); }
#line 5853 "sparql_p.c" /* yacc.c:1646 */
break;
case 371:
#line 1758 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_DIRECTION' SPARQL_INTEGER */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_DIRECTION_L, (yyvsp[0].box)); }
#line 5860 "sparql_p.c" /* yacc.c:1646 */
break;
case 372:
#line 1760 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_DISTINCT' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_DISTINCT_L, (ptrlong)1); }
#line 5867 "sparql_p.c" /* yacc.c:1646 */
break;
case 373:
#line 1762 "sparql_p.y" /* yacc.c:1646 */
{ /*... | '' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_END_FLAG_L, (yyvsp[0].box)); }
#line 5874 "sparql_p.c" /* yacc.c:1646 */
break;
case 374:
#line 1764 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_EXISTS' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_EXISTS_L, (ptrlong)1); }
#line 5881 "sparql_p.c" /* yacc.c:1646 */
break;
case 375:
#line 1766 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_FINAL_AS' Var */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_FINAL_AS_L, (yyvsp[0].tree)); }
#line 5888 "sparql_p.c" /* yacc.c:1646 */
break;
case 376:
#line 1768 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_IN' '(' Var ( ',' Var )* ')' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_IN_L, spartlist (sparp_arg, 2, SPAR_LIST, t_revlist_to_array ((yyvsp[-1].backstack)))); }
#line 5895 "sparql_p.c" /* yacc.c:1646 */
break;
case 377:
#line 1770 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_MIN' Expn */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_MIN_L, (yyvsp[0].tree)); }
#line 5902 "sparql_p.c" /* yacc.c:1646 */
break;
case 378:
#line 1772 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_MAX' Expn */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_MAX_L, (yyvsp[0].tree)); }
#line 5909 "sparql_p.c" /* yacc.c:1646 */
break;
case 379:
#line 1774 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_NO_CYCLES' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_NO_CYCLES_L, (ptrlong)1); }
#line 5916 "sparql_p.c" /* yacc.c:1646 */
break;
case 380:
#line 1776 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_NO_ORDER' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_NO_ORDER_L, (ptrlong)1); }
#line 5923 "sparql_p.c" /* yacc.c:1646 */
break;
case 381:
#line 1778 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_OUT' '(' Var ( ',' Var )* ')' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_OUT_L, spartlist (sparp_arg, 2, SPAR_LIST, t_revlist_to_array ((yyvsp[-1].backstack)))); }
#line 5930 "sparql_p.c" /* yacc.c:1646 */
break;
case 382:
#line 1780 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_SHORTEST_ONLY' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_SHORTEST_ONLY_L, (ptrlong)1); }
#line 5937 "sparql_p.c" /* yacc.c:1646 */
break;
case 383:
#line 1782 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'T_STEP' '(' ( Var | SPARQL_STRING ) ')' 'AS' Var */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)T_STEP_L, spartlist (sparp_arg, 6, SPAR_ALIAS, (yyvsp[-3].tree), (yyvsp[0].tree)->_.var.vname, SSG_VALMODE_AUTO, (ptrlong)0, (ptrlong)0)); }
#line 5944 "sparql_p.c" /* yacc.c:1646 */
break;
case 384:
#line 1784 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, (ptrlong)T_STEP_L, spartlist (sparp_arg, 6, SPAR_ALIAS, (yyvsp[-3].box), (yyvsp[0].tree)->_.var.vname, SSG_VALMODE_AUTO, (ptrlong)0, (ptrlong)0)); }
#line 5950 "sparql_p.c" /* yacc.c:1646 */
break;
case 385:
#line 1785 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'TRANSITIVE' */
(yyval.trees) = (SPART **)t_list (2, (ptrlong)TRANSITIVE_L, (ptrlong)1); }
#line 5957 "sparql_p.c" /* yacc.c:1646 */
break;
case 386:
#line 1790 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 5963 "sparql_p.c" /* yacc.c:1646 */
break;
case 387:
#line 1791 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 5969 "sparql_p.c" /* yacc.c:1646 */
break;
case 388:
#line 1795 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SAME_AS_L; }
#line 5975 "sparql_p.c" /* yacc.c:1646 */
break;
case 389:
#line 1796 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SAME_AS_O_L; }
#line 5981 "sparql_p.c" /* yacc.c:1646 */
break;
case 390:
#line 1797 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SAME_AS_P_L; }
#line 5987 "sparql_p.c" /* yacc.c:1646 */
break;
case 391:
#line 1798 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SAME_AS_S_L; }
#line 5993 "sparql_p.c" /* yacc.c:1646 */
break;
case 392:
#line 1799 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = SAME_AS_S_O_L; }
#line 5999 "sparql_p.c" /* yacc.c:1646 */
break;
case 397:
#line 1807 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Predicate expected (i.e., variable or a backquoted expn or IRI ref or 'a' keyword or some property path)"); }
#line 6005 "sparql_p.c" /* yacc.c:1646 */
break;
case 398:
#line 1811 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 6011 "sparql_p.c" /* yacc.c:1646 */
break;
case 399:
#line 1812 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '|', (yyvsp[-2].tree), (yyvsp[0].tree), 0, 0); }
#line 6017 "sparql_p.c" /* yacc.c:1646 */
break;
case 400:
#line 1816 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 6023 "sparql_p.c" /* yacc.c:1646 */
break;
case 401:
#line 1817 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '/', (yyvsp[-2].tree), (yyvsp[0].tree), 0, 0); }
#line 6029 "sparql_p.c" /* yacc.c:1646 */
break;
case 402:
#line 1821 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '*', spar_make_ppath (sparp_arg, '^', (yyvsp[-1].tree), NULL, 0, 0), NULL, 0, 1); }
#line 6035 "sparql_p.c" /* yacc.c:1646 */
break;
case 403:
#line 1822 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '*', spar_make_ppath (sparp_arg, '^', (yyvsp[-1].tree), NULL, 0, 0), NULL, 0, -1); }
#line 6041 "sparql_p.c" /* yacc.c:1646 */
break;
case 404:
#line 1823 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '*', spar_make_ppath (sparp_arg, '^', (yyvsp[-1].tree), NULL, 0, 0), NULL, 1, -1); }
#line 6047 "sparql_p.c" /* yacc.c:1646 */
break;
case 405:
#line 1824 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_ppath (sparp_arg, '*',
spar_make_ppath (sparp_arg, '^', (yyvsp[-2].tree), NULL, 0, 0), NULL,
unbox (((yyvsp[0].boxes))[0]), unbox (((yyvsp[0].boxes))[1]) ); }
#line 6056 "sparql_p.c" /* yacc.c:1646 */
break;
case 406:
#line 1828 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '^', (yyvsp[0].tree), NULL, 0, 0); }
#line 6062 "sparql_p.c" /* yacc.c:1646 */
break;
case 407:
#line 1829 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '*', (yyvsp[-1].tree), NULL, 0, 1); }
#line 6068 "sparql_p.c" /* yacc.c:1646 */
break;
case 408:
#line 1830 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '*', (yyvsp[-1].tree), NULL, 0, -1); }
#line 6074 "sparql_p.c" /* yacc.c:1646 */
break;
case 409:
#line 1831 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '*', (yyvsp[-1].tree), NULL, 1, -1); }
#line 6080 "sparql_p.c" /* yacc.c:1646 */
break;
case 410:
#line 1832 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_ppath (sparp_arg, '*',
(yyvsp[-2].tree), NULL,
unbox (((yyvsp[0].boxes))[0]), unbox (((yyvsp[0].boxes))[1]) ); }
#line 6089 "sparql_p.c" /* yacc.c:1646 */
break;
case 411:
#line 1836 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 6095 "sparql_p.c" /* yacc.c:1646 */
break;
case 412:
#line 1840 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.boxes) = t_list (2, (yyvsp[-1].box), (yyvsp[-1].box)); }
#line 6101 "sparql_p.c" /* yacc.c:1646 */
break;
case 413:
#line 1841 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.boxes) = t_list (2, (yyvsp[-3].box), (yyvsp[-1].box)); }
#line 6107 "sparql_p.c" /* yacc.c:1646 */
break;
case 414:
#line 1842 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.boxes) = t_list (2, (ptrlong)(0), (yyvsp[-1].box)); }
#line 6113 "sparql_p.c" /* yacc.c:1646 */
break;
case 415:
#line 1843 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.boxes) = t_list (2, (yyvsp[-2].box), t_box_num (-1)); }
#line 6119 "sparql_p.c" /* yacc.c:1646 */
break;
case 416:
#line 1847 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, 'D', (yyvsp[-1].tree), NULL, 0, 0); }
#line 6125 "sparql_p.c" /* yacc.c:1646 */
break;
case 417:
#line 1848 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[-1].tree); }
#line 6131 "sparql_p.c" /* yacc.c:1646 */
break;
case 418:
#line 1849 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '!', (yyvsp[-1].tree), NULL, 0, 0); }
#line 6137 "sparql_p.c" /* yacc.c:1646 */
break;
case 419:
#line 1850 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '!', (yyvsp[0].tree), NULL, 0, 0); }
#line 6143 "sparql_p.c" /* yacc.c:1646 */
break;
case 420:
#line 1851 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_ppath (sparp_arg, '!', spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_type), NULL, 0, 0); }
#line 6149 "sparql_p.c" /* yacc.c:1646 */
break;
case 421:
#line 1852 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 6155 "sparql_p.c" /* yacc.c:1646 */
break;
case 422:
#line 1853 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_type); }
#line 6161 "sparql_p.c" /* yacc.c:1646 */
break;
case 423:
#line 1857 "sparql_p.y" /* yacc.c:1646 */
{ /* [35] BlankNodePropertyList ::= '[' PropertyListNotEmpty ']' */
SPART *bn = spar_make_blank_node (sparp_arg, spar_mkid (sparp_arg, "_:lsqbra"), 1);
t_set_push (&(sparp_env()->spare_context_subjects), bn); }
#line 6169 "sparql_p.c" /* yacc.c:1646 */
break;
case 424:
#line 1860 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = t_set_pop (&(sparp_env()->spare_context_subjects)); }
#line 6176 "sparql_p.c" /* yacc.c:1646 */
break;
case 425:
#line 1862 "sparql_p.y" /* yacc.c:1646 */
{ /* [36] Collection ::= '(' GraphNode* ')' */
SPART *bn = spar_make_blank_node (sparp_arg, spar_mkid (sparp_arg, "_:topcons"), 1);
t_set_push (&(sparp_env()->spare_context_subjects), bn);
t_set_push (&(sparp_env()->spare_context_subjects), bn); }
#line 6185 "sparql_p.c" /* yacc.c:1646 */
break;
case 426:
#line 1866 "sparql_p.y" /* yacc.c:1646 */
{
spar_gp_add_triplelike (sparp_arg,
NULL, NULL,
spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_rest),
spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_nil),
NULL, NULL, 0x0 );
t_set_pop (&(sparp_env()->spare_context_subjects));
(yyval.tree) = t_set_pop (&(sparp_env()->spare_context_subjects)); }
#line 6198 "sparql_p.c" /* yacc.c:1646 */
break;
case 427:
#line 1874 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_nil); }
#line 6204 "sparql_p.c" /* yacc.c:1646 */
break;
case 428:
#line 1878 "sparql_p.y" /* yacc.c:1646 */
{}
#line 6210 "sparql_p.c" /* yacc.c:1646 */
break;
case 429:
#line 1879 "sparql_p.y" /* yacc.c:1646 */
{}
#line 6216 "sparql_p.c" /* yacc.c:1646 */
break;
case 430:
#line 1883 "sparql_p.y" /* yacc.c:1646 */
{
spar_gp_add_triplelike (sparp_arg, NULL, NULL,
spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_first),
(yyvsp[0].tree), NULL, NULL, 0x0 ); }
#line 6225 "sparql_p.c" /* yacc.c:1646 */
break;
case 431:
#line 1887 "sparql_p.y" /* yacc.c:1646 */
{
SPART *bn = spar_make_blank_node (sparp_arg, spar_mkid (sparp_arg, "_:cons"), 1);
spar_gp_add_triplelike (sparp_arg,
NULL, NULL,
spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_rest),
bn, NULL, NULL, 0x0 );
sparp_env()->spare_context_subjects->data = bn;
spar_gp_add_triplelike (sparp_arg, NULL, NULL,
spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_first),
(yyvsp[0].tree), NULL, NULL, 0x0 ); }
#line 6240 "sparql_p.c" /* yacc.c:1646 */
break;
case 436:
#line 1910 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 6246 "sparql_p.c" /* yacc.c:1646 */
break;
case 437:
#line 1911 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 6252 "sparql_p.c" /* yacc.c:1646 */
break;
case 441:
#line 1918 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[-1].tree); }
#line 6258 "sparql_p.c" /* yacc.c:1646 */
break;
case 446:
#line 1929 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[-2].tree)); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 6264 "sparql_p.c" /* yacc.c:1646 */
break;
case 447:
#line 1930 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 6270 "sparql_p.c" /* yacc.c:1646 */
break;
case 448:
#line 1934 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 6276 "sparql_p.c" /* yacc.c:1646 */
break;
case 449:
#line 1935 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 6282 "sparql_p.c" /* yacc.c:1646 */
break;
case 450:
#line 1939 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_funcall (sparp_arg, 1, (yyvsp[-2].box), (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6288 "sparql_p.c" /* yacc.c:1646 */
break;
case 451:
#line 1940 "sparql_p.y" /* yacc.c:1646 */
{
SPART *arg = ((uname_SPECIAL_cc_bif_c_COUNT == (yyvsp[-2].box)) ? SPAR_MAKE_INT_LITERAL (sparp_arg, 1) : (SPART *)((ptrlong)_STAR));
(yyval.tree) = spar_make_funcall (sparp_arg, 1, (yyvsp[-2].box), (SPART **)t_list (1, arg)); }
#line 6296 "sparql_p.c" /* yacc.c:1646 */
break;
case 452:
#line 1943 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_funcall (sparp_arg, DISTINCT_L, (yyvsp[-3].box), (SPART **)t_list (1, (ptrlong)_STAR)); }
#line 6302 "sparql_p.c" /* yacc.c:1646 */
break;
case 453:
#line 1944 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_funcall (sparp_arg, DISTINCT_L, (yyvsp[-3].box), (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6308 "sparql_p.c" /* yacc.c:1646 */
break;
case 454:
#line 1945 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x2000, "SAMPLE aggregate function call");
(yyval.tree) = spar_make_funcall (sparp_arg, 1, t_box_dv_uname_string ("sql:SAMPLE"), (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6316 "sparql_p.c" /* yacc.c:1646 */
break;
case 455:
#line 1948 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x2000, "SAMPLE aggregate function call");
(yyval.tree) = spar_make_funcall (sparp_arg, 1, t_box_dv_uname_string ("sql:SAMPLE"), (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6324 "sparql_p.c" /* yacc.c:1646 */
break;
case 456:
#line 1951 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_funcall (sparp_arg, 1, (yyvsp[-2].box), (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6330 "sparql_p.c" /* yacc.c:1646 */
break;
case 457:
#line 1952 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_funcall (sparp_arg, 1, (yyvsp[-4].box), (SPART **)t_list (2, (yyvsp[-3].tree), (yyvsp[-1].tree))); }
#line 6336 "sparql_p.c" /* yacc.c:1646 */
break;
case 458:
#line 1953 "sparql_p.y" /* yacc.c:1646 */
{
if (stricmp ((yyvsp[-3].box), "SEPARATOR"))
spar_error (sparp_arg, "The GROUP_CONCAT contains unsupported parameter '%.100s', only 'SEPARATOR' is supported",
(yyvsp[-3].box) );
(yyval.tree) = spar_make_funcall (sparp_arg, 1, (yyvsp[-6].box), (SPART **)t_list (2, (yyvsp[-5].tree), (yyvsp[-1].tree))); }
#line 6346 "sparql_p.c" /* yacc.c:1646 */
break;
case 459:
#line 1961 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0100, "aggregate function call"); (yyval.box) = (yyvsp[0].box); }
#line 6352 "sparql_p.c" /* yacc.c:1646 */
break;
case 460:
#line 1965 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = uname_SPECIAL_cc_bif_c_COUNT; }
#line 6358 "sparql_p.c" /* yacc.c:1646 */
break;
case 461:
#line 1966 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = uname_SPECIAL_cc_bif_c_AVG; }
#line 6364 "sparql_p.c" /* yacc.c:1646 */
break;
case 462:
#line 1967 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = uname_SPECIAL_cc_bif_c_GROUPING; }
#line 6370 "sparql_p.c" /* yacc.c:1646 */
break;
case 463:
#line 1968 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = uname_SPECIAL_cc_bif_c_MIN; }
#line 6376 "sparql_p.c" /* yacc.c:1646 */
break;
case 464:
#line 1969 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = uname_SPECIAL_cc_bif_c_MAX; }
#line 6382 "sparql_p.c" /* yacc.c:1646 */
break;
case 465:
#line 1970 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = uname_SPECIAL_cc_bif_c_SUM; }
#line 6388 "sparql_p.c" /* yacc.c:1646 */
break;
case 466:
#line 1974 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x2000, "GROUP_CONCAT aggregate function call"); (yyval.box) = (yyvsp[0].box); }
#line 6394 "sparql_p.c" /* yacc.c:1646 */
break;
case 467:
#line 1977 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = t_box_dv_uname_string ("sql:GROUP_CONCAT"); }
#line 6400 "sparql_p.c" /* yacc.c:1646 */
break;
case 468:
#line 1978 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = t_box_dv_uname_string ("sql:GROUP_CONCAT_DISTINCT"); }
#line 6406 "sparql_p.c" /* yacc.c:1646 */
break;
case 471:
#line 1987 "sparql_p.y" /* yacc.c:1646 */
{
if (sparp_arg->sparp_macro_mode & SPARP_DEFBODY)
{
SPART *curmacro = sparp_arg->sparp_current_macro;
int pos = sparp_namesake_macro_param (sparp_arg, curmacro, (yyvsp[0].box));
if (-1 > pos)
{
spar_error (sparp_arg, "Variable '%.100s' inside the body of a macro '%.100s' is not listed in list of macro arguments or list of local names",
(yyvsp[0].box), curmacro->_.defmacro.mname );
}
if (0 <= pos)
(yyval.tree) = spar_make_macropu (sparp_arg, (yyvsp[0].box), pos);
else
(yyval.tree) = spar_make_param_or_variable (sparp_arg, (yyvsp[0].box));
}
else
(yyval.tree) = spar_make_param_or_variable (sparp_arg, (yyvsp[0].box)); }
#line 6428 "sparql_p.c" /* yacc.c:1646 */
break;
case 472:
#line 2004 "sparql_p.y" /* yacc.c:1646 */
{
if (sparp_arg->sparp_macro_mode & SPARP_DEFBODY)
spar_error (sparp_arg, "Global variables are not allowed inside the body of a macro '%.100s'",
sparp_arg->sparp_current_macro->_.defmacro.mname );
(yyval.tree) = (yyvsp[0].tree); }
#line 6438 "sparql_p.c" /* yacc.c:1646 */
break;
case 473:
#line 2009 "sparql_p.y" /* yacc.c:1646 */
{
if (sparp_arg->sparp_macro_mode & SPARP_DEFBODY)
spar_error (sparp_arg, "Property path variables are not allowed inside the body of a macro '%.100s'",
sparp_arg->sparp_current_macro->_.defmacro.mname );
(yyval.tree) = spar_add_propvariable (sparp_arg, (yyvsp[-1].tree), (ptrlong)((yyvsp[0].trees)[0]), (yyvsp[0].trees)[1], (ptrlong)((yyvsp[0].trees)[2]), (void *)((yyvsp[0].trees)[3]) ); }
#line 6448 "sparql_p.c" /* yacc.c:1646 */
break;
case 474:
#line 2017 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0080, "global variable"); (yyval.tree) = (yyvsp[0].tree); }
#line 6454 "sparql_p.c" /* yacc.c:1646 */
break;
case 475:
#line 2022 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_variable (sparp_arg, (yyvsp[0].box)); }
#line 6460 "sparql_p.c" /* yacc.c:1646 */
break;
case 476:
#line 2023 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_variable (sparp_arg, (yyvsp[0].box)); }
#line 6466 "sparql_p.c" /* yacc.c:1646 */
break;
case 482:
#line 2033 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 2, SPAR_QNAME, uname_rdf_ns_uri_nil); }
#line 6472 "sparql_p.c" /* yacc.c:1646 */
break;
case 484:
#line 2038 "sparql_p.y" /* yacc.c:1646 */
{
dk_set_t gp_st = sparp_env()->spare_context_gp_subtypes;
if (2 & sparp_arg->sparp_in_precode_expn)
spar_error (sparp_arg, "Backquoted expressions are not allowed in constant clauses");
(yyval.token_type) = ((NULL == gp_st) ? -1 : (ptrlong)(gp_st->data));
if (CONSTRUCT_L == (yyval.token_type))
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0100, "backquoted expression in CONSTRUCT"); }
#line 6484 "sparql_p.c" /* yacc.c:1646 */
break;
case 485:
#line 2045 "sparql_p.y" /* yacc.c:1646 */
{
if ((-1 == (yyvsp[-2].token_type)) || (CONSTRUCT_L == (yyvsp[-2].token_type)))
(yyval.tree) = (yyvsp[-1].tree); /* redundant backquotes in retlist or backquotes to bypass syntax limitation in CONSTRUCT gp */
else
{
SPART *bn = sparp_arg->sparp_in_ctor_from_where ?
spar_make_variable (sparp_arg, spar_mkid (sparp_arg, "ctor_from_where_calc_var"))
:
spar_make_blank_node (sparp_arg, spar_mkid (sparp_arg, "_:calc"), 1);
SPART *eq;
SPAR_BIN_OP (eq, BOP_EQ, t_full_box_copy_tree ((void *)bn), (yyvsp[-1].tree));
spar_gp_add_filter (sparp_arg, eq, 0);
(yyval.tree) = bn;
}
}
#line 6504 "sparql_p.c" /* yacc.c:1646 */
break;
case 486:
#line 2063 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 6, SPAR_ALIAS, (yyvsp[-2].tree), (yyvsp[0].box), SSG_VALMODE_AUTO, (ptrlong)0, (ptrlong)0); }
#line 6510 "sparql_p.c" /* yacc.c:1646 */
break;
case 487:
#line 2064 "sparql_p.y" /* yacc.c:1646 */
{ /* [44] ConditionalOrExpn ::= ConditionalAndExpn ( '||' ConditionalAndExpn )* */
SPAR_BIN_OP ((yyval.tree), BOP_OR, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6517 "sparql_p.c" /* yacc.c:1646 */
break;
case 488:
#line 2066 "sparql_p.y" /* yacc.c:1646 */
{ /* [45] ConditionalAndExpn ::= ValueLogical ( '&&' ValueLogical )* */
/* [46] ValueLogical ::= RelationalExpn */
SPAR_BIN_OP ((yyval.tree), BOP_AND, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6525 "sparql_p.c" /* yacc.c:1646 */
break;
case 489:
#line 2069 "sparql_p.y" /* yacc.c:1646 */
{ /* [47]* RelationalExpn ::= NumericExpn */
/*... ( ( ('='|'!='|'<'|'>'|'<='|'>='|'LIKE') NumericExpn ) */
/*... | ( 'IN' '(' Expns ')' ) )? */
SPAR_BIN_OP ((yyval.tree), BOP_EQ, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6534 "sparql_p.c" /* yacc.c:1646 */
break;
case 490:
#line 2073 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_BIN_OP ((yyval.tree), BOP_NEQ, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6540 "sparql_p.c" /* yacc.c:1646 */
break;
case 491:
#line 2074 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0040, "LIKE operator"); }
#line 6546 "sparql_p.c" /* yacc.c:1646 */
break;
case 492:
#line 2075 "sparql_p.y" /* yacc.c:1646 */
{ /* Virtuoso-specific extension of [47] */
(yyval.tree) = sparp_make_builtin_call (sparp_arg, LIKE_L, (SPART **)t_list (2, (yyvsp[-3].tree), (yyvsp[0].tree))); }
#line 6553 "sparql_p.c" /* yacc.c:1646 */
break;
case 493:
#line 2077 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0020, "IN operator"); }
#line 6559 "sparql_p.c" /* yacc.c:1646 */
break;
case 494:
#line 2078 "sparql_p.y" /* yacc.c:1646 */
{ /* Virtuoso-specific extension of [47] */
dk_set_t args = (((dk_set_t)NIL_L == (yyvsp[0].backstack)) ? NULL : (yyvsp[0].backstack));
if (1 == dk_set_length (args))
{
SPAR_BIN_OP ((yyval.tree), BOP_EQ, (yyvsp[-3].tree), args->data);
}
else
{
args = dk_set_nreverse (args);
t_set_push (&args, (yyvsp[-3].tree));
(yyval.tree) = sparp_make_builtin_call (sparp_arg, IN_L,
(SPART **)t_list_to_array (args) /* NOT t_revlist_to_array (args), note special first element pushed */ );
}
}
#line 6578 "sparql_p.c" /* yacc.c:1646 */
break;
case 495:
#line 2092 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0X0020, "NOT IN operator"); }
#line 6584 "sparql_p.c" /* yacc.c:1646 */
break;
case 496:
#line 2093 "sparql_p.y" /* yacc.c:1646 */
{ /* Virtuoso-specific extension of [47] */
dk_set_t args = (((dk_set_t)NIL_L == (yyvsp[0].backstack)) ? NULL : (yyvsp[0].backstack));
if (1 == dk_set_length (args))
{
SPAR_BIN_OP ((yyval.tree), BOP_NEQ, (yyvsp[-3].tree), args->data);
}
else
{
SPART *in_call;
t_set_push (&args, (yyvsp[-3].tree));
in_call = sparp_make_builtin_call (sparp_arg, IN_L,
(SPART **)t_list_to_array (args) /* NOT t_revlist_to_array (args), note special first element pushed */ );
SPAR_BIN_OP ((yyval.tree), BOP_NOT, in_call, NULL);
}
}
#line 6604 "sparql_p.c" /* yacc.c:1646 */
break;
case 497:
#line 2108 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_BIN_OP ((yyval.tree), BOP_LT, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6610 "sparql_p.c" /* yacc.c:1646 */
break;
case 498:
#line 2109 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_BIN_OP ((yyval.tree), BOP_LT, (yyvsp[0].tree), (yyvsp[-2].tree)); }
#line 6616 "sparql_p.c" /* yacc.c:1646 */
break;
case 499:
#line 2110 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_BIN_OP ((yyval.tree), BOP_LTE, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6622 "sparql_p.c" /* yacc.c:1646 */
break;
case 500:
#line 2111 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_BIN_OP ((yyval.tree), BOP_LTE, (yyvsp[0].tree), (yyvsp[-2].tree)); }
#line 6628 "sparql_p.c" /* yacc.c:1646 */
break;
case 501:
#line 2112 "sparql_p.y" /* yacc.c:1646 */
{ /* [49] AdditiveExpn ::= MultiplicativeExpn ( ('+'|'-') MultiplicativeExpn )* */
if (sparp_arg->sparp_rset_lexdepth_plus_1 == (yyvsp[-1].token_type) + 1)
sparyyerror (sparp_arg, "Ambiguous (unary or binary) plus operator in result list, please add \"(\" and \")\"");
SPAR_BIN_OP ((yyval.tree), BOP_PLUS, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6637 "sparql_p.c" /* yacc.c:1646 */
break;
case 502:
#line 2116 "sparql_p.y" /* yacc.c:1646 */
{
if (sparp_arg->sparp_rset_lexdepth_plus_1 == (yyvsp[-1].token_type) + 1)
sparyyerror (sparp_arg, "Ambiguous (unary or binary) minus operator in result list, please add \"(\" and \")\"");
SPAR_BIN_OP ((yyval.tree), BOP_MINUS, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6646 "sparql_p.c" /* yacc.c:1646 */
break;
case 503:
#line 2120 "sparql_p.y" /* yacc.c:1646 */
{ /* [50] MultiplicativeExpn ::= UnaryExpn ( ('*'|'/') UnaryExpn )* */
SPAR_BIN_OP ((yyval.tree), BOP_TIMES, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6653 "sparql_p.c" /* yacc.c:1646 */
break;
case 504:
#line 2122 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_BIN_OP ((yyval.tree), BOP_DIV, (yyvsp[-2].tree), (yyvsp[0].tree)); }
#line 6659 "sparql_p.c" /* yacc.c:1646 */
break;
case 505:
#line 2123 "sparql_p.y" /* yacc.c:1646 */
{ /* [51]* UnaryExpn ::= ('!'|'NOT'|'+'|'-')? PrimaryExpn */
SPAR_BIN_OP ((yyval.tree), BOP_NOT, (yyvsp[0].tree), NULL); }
#line 6666 "sparql_p.c" /* yacc.c:1646 */
break;
case 506:
#line 2125 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_BIN_OP ((yyval.tree), BOP_PLUS, SPAR_MAKE_INT_LITERAL (sparp_arg, 0), (yyvsp[0].tree)); }
#line 6673 "sparql_p.c" /* yacc.c:1646 */
break;
case 507:
#line 2127 "sparql_p.y" /* yacc.c:1646 */
{
void * *val_ptr = NULL;
void * *orig_text = NULL;
void * *orig_text_ptr = NULL;
if ((DV_ARRAY_OF_POINTER == DV_TYPE_OF ((yyvsp[0].tree))) && (SPAR_LIT == (yyvsp[0].tree)->type)) {
val_ptr = &((yyvsp[0].tree)->_.lit.val);
orig_text = (yyvsp[0].tree)->_.lit.original_text;
if (NULL != orig_text)
orig_text_ptr = &((yyvsp[0].tree)->_.lit.original_text);
(yyvsp[0].tree)->_.lit.original_text = NULL; }
if (NULL != val_ptr) {
dtp_t val_dtp = DV_TYPE_OF (val_ptr[0]);
if (DV_LONG_INT == val_dtp)
val_ptr[0] = t_box_num_nonull (-unbox (val_ptr[0]));
else if (DV_DOUBLE_FLOAT == val_dtp)
((double *)(val_ptr[0]))[0] = -((double *)(val_ptr[0]))[0];
else if (DV_NUMERIC == val_dtp)
((struct numeric_s *)(val_ptr[0]))->n_neg = (((struct numeric_s *)(val_ptr[0]))->n_neg ? 0 : 1);
else
val_ptr = NULL; }
if (NULL == val_ptr)
SPAR_BIN_OP ((yyval.tree), BOP_MINUS, SPAR_MAKE_INT_LITERAL (sparp_arg, 0), (yyvsp[0].tree));
else
{
(yyval.tree) = (yyvsp[0].tree);
if (NULL != orig_text_ptr)
{
if ('-' == orig_text[0])
orig_text_ptr[0] = t_box_dv_short_string (orig_text+1);
else
orig_text_ptr[0] = t_box_dv_short_strconcat ("-", orig_text); } } }
#line 6709 "sparql_p.c" /* yacc.c:1646 */
break;
case 508:
#line 2158 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[-1].tree); }
#line 6715 "sparql_p.c" /* yacc.c:1646 */
break;
case 509:
#line 2161 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0100, "scalar ASK subquery");
spar_gp_init (sparp_arg, SELECT_L);
spar_env_push (sparp_arg);
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL);
sparp_arg->sparp_allow_aggregates_in_expn <<= 1; }
#line 6726 "sparql_p.c" /* yacc.c:1646 */
break;
case 510:
#line 2169 "sparql_p.y" /* yacc.c:1646 */
{
SPART *subselect_top;
SPART *where_gp;
where_gp = spar_gp_finalize (sparp_arg, NULL);
subselect_top = spar_make_top (sparp_arg, ASK_L, (SPART **)t_list(0),
where_gp, NULL, NULL, NULL, (SPART *)t_box_num(1), (SPART *)t_box_num(0), NULL );
spar_env_pop (sparp_arg);
(yyval.tree) = spar_gp_finalize_with_subquery (sparp_arg, (yyvsp[-1].trees), subselect_top);
sparp_arg->sparp_allow_aggregates_in_expn >>= 1; }
#line 6740 "sparql_p.c" /* yacc.c:1646 */
break;
case 511:
#line 2178 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0100, "scalar subquery");
spar_gp_init (sparp_arg, SELECT_L);
spar_env_push (sparp_arg);
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL);
sparp_arg->sparp_allow_aggregates_in_expn <<= 1;
sparp_arg->sparp_allow_aggregates_in_expn |= 1; }
#line 6752 "sparql_p.c" /* yacc.c:1646 */
break;
case 512:
#line 2187 "sparql_p.y" /* yacc.c:1646 */
{
SPART *subselect_top;
SPART *where_gp;
SPART *wm = (yyvsp[-2].tree);
where_gp = spar_gp_finalize (sparp_arg, NULL);
wm->_.wm.where_gp = where_gp;
subselect_top = spar_make_top_or_special_case_from_wm (sparp_arg, (yyvsp[-7].token_type), (yyvsp[-5].trees), wm );
if (SPAR_REQ_TOP == subselect_top->type)
sparp_expand_top_retvals (sparp_arg, subselect_top, 1 /* safely_copy_all_vars */, NULL);
spar_env_pop (sparp_arg);
(yyval.tree) = spar_gp_finalize_with_subquery (sparp_arg, (yyvsp[-1].trees), subselect_top);
sparp_arg->sparp_allow_aggregates_in_expn >>= 1; }
#line 6769 "sparql_p.c" /* yacc.c:1646 */
break;
case 513:
#line 2199 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = (yyvsp[0].tree);
if (sparp_arg->sparp_in_precode_expn)
sparyyerror (sparp_arg, "Aggregates are not allowed in 'precode' expressions that should be calculated before the result-set of the query");
if (!(sparp_arg->sparp_allow_aggregates_in_expn & 1))
sparyyerror (sparp_arg, "Aggregates are allowed only in result sets"); }
#line 6780 "sparql_p.c" /* yacc.c:1646 */
break;
case 515:
#line 2206 "sparql_p.y" /* yacc.c:1646 */
{ /* [55*] IRIrefOrFunctionOrMacro ::= (( IRIref ArgList? ) | ( 'MACRO' IRIref ArgList )) */
SPART *mdef;
if (!sparp_arg->sparp_storage_is_set)
sparp_configure_storage_and_macro_libs (sparp_arg);
mdef = spar_find_defmacro_by_iri_or_fields (sparp_arg, (yyvsp[0].tree)->_.lit.val, NULL);
(yyval.trees) = (SPART **)t_list (2, (ptrlong)(sparp_arg->sparp_macro_mode), mdef);
if (NULL != mdef)
{
if ((SPARP_DEFBODY & sparp_arg->sparp_macro_mode) && (sparp_arg->sparp_current_macro == mdef))
sparyyerror (sparp_arg, "The macro is recursively used in its own definition");
sparp_arg->sparp_macro_mode |= SPARP_CALLARG;
} }
#line 6797 "sparql_p.c" /* yacc.c:1646 */
break;
case 516:
#line 2218 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL == (yyvsp[0].backstack))
(yyval.tree) = (yyvsp[-2].tree);
else
{
SPART **args = (SPART **)(((dk_set_t)NIL_L == (yyvsp[0].backstack)) ? NULL : t_revlist_to_array ((yyvsp[0].backstack)));
const char *fname = (yyvsp[-2].tree)->_.lit.val;
SPART *mdef = ((yyvsp[-1].trees))[1];
if (NULL != mdef)
{
sparp_arg->sparp_macro_mode = (ptrlong)(((yyvsp[-1].trees))[0]);
(yyval.tree) = sparp_make_macro_call (sparp_arg, fname, 1, args);
if (!(sparp_arg->sparp_macro_mode & SPARP_DEFBODY))
sparp_arg->sparp_macro_call_count++;
}
else
{
int is_agg = 0;
spar_verify_funcall_security (sparp_arg, &is_agg, &fname, args);
(yyval.tree) = spar_make_funcall (sparp_arg, is_agg, fname, args);
} } }
#line 6823 "sparql_p.c" /* yacc.c:1646 */
break;
case 517:
#line 2239 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)((yyvsp[0].tree)); }
#line 6829 "sparql_p.c" /* yacc.c:1646 */
break;
case 518:
#line 2240 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)((yyvsp[0].tree)); }
#line 6835 "sparql_p.c" /* yacc.c:1646 */
break;
case 519:
#line 2241 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)((yyvsp[0].tree)); }
#line 6841 "sparql_p.c" /* yacc.c:1646 */
break;
case 523:
#line 2245 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0200, "UNDEF_L outside VALUES clause"); (yyval.tree) = (SPART *)t_NEW_DB_NULL; }
#line 6847 "sparql_p.c" /* yacc.c:1646 */
break;
case 524:
#line 2249 "sparql_p.y" /* yacc.c:1646 */
{
SPART **args = (SPART **)(((dk_set_t)NIL_L == (yyvsp[0].backstack)) ? NULL : t_revlist_to_array ((yyvsp[0].backstack)));
if ((SPAR_BIF_REGEX == (yyvsp[-1].token_type)) && (2 == BOX_ELEMENTS_0 (args)))
(yyval.tree) = spar_make_regex_or_like_or_eq (sparp_arg, args[0], args[1]);
else
(yyval.tree) = sparp_make_builtin_call (sparp_arg, (yyvsp[-1].token_type), args); }
#line 6858 "sparql_p.c" /* yacc.c:1646 */
break;
case 525:
#line 2267 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_builtin_call (sparp_arg, IRI_L, (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6864 "sparql_p.c" /* yacc.c:1646 */
break;
case 526:
#line 2269 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_builtin_call (sparp_arg, LANG_L, (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6870 "sparql_p.c" /* yacc.c:1646 */
break;
case 527:
#line 2271 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_builtin_call (sparp_arg, DATATYPE_L, (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6876 "sparql_p.c" /* yacc.c:1646 */
break;
case 528:
#line 2273 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_builtin_call (sparp_arg, BOUND_L, (SPART **)t_list (1, (yyvsp[-1].tree))); }
#line 6882 "sparql_p.c" /* yacc.c:1646 */
break;
case 529:
#line 2274 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'NOT'? 'EXISTS' DatasetClause* WhereClause */
if ((yyvsp[-1].token_type))
(yyval.tree) = (yyvsp[0].tree);
else
SPAR_BIN_OP ((yyval.tree), BOP_NOT, (yyvsp[0].tree), NULL); }
#line 6892 "sparql_p.c" /* yacc.c:1646 */
break;
case 530:
#line 2279 "sparql_p.y" /* yacc.c:1646 */
{
dk_set_t a = (yyvsp[-3].backstack);
t_set_push (&a, (yyvsp[-1].tree));
a = dk_set_conc (a, t_cons ((yyvsp[-4].tree), NULL));
(yyval.tree) = sparp_make_builtin_call (sparp_arg, SPAR_BIF_CASEX, (SPART **)t_revlist_to_array (a)); }
#line 6902 "sparql_p.c" /* yacc.c:1646 */
break;
case 531:
#line 2284 "sparql_p.y" /* yacc.c:1646 */
{
dk_set_t a = (yyvsp[-3].backstack);
t_set_push (&a, (yyvsp[-1].tree));
(yyval.tree) = sparp_make_builtin_call (sparp_arg, SPAR_BIF_CASEWHEN, (SPART **)t_revlist_to_array (a)); }
#line 6911 "sparql_p.c" /* yacc.c:1646 */
break;
case 532:
#line 2291 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[-2].tree)); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 6917 "sparql_p.c" /* yacc.c:1646 */
break;
case 533:
#line 2292 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-4].backstack); t_set_push (&((yyval.backstack)), (yyvsp[-2].tree)); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 6923 "sparql_p.c" /* yacc.c:1646 */
break;
case 534:
#line 2293 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "'WHEN' or 'ELSE' expected after end of 'THEN'-expression"); }
#line 6929 "sparql_p.c" /* yacc.c:1646 */
break;
case 535:
#line 2297 "sparql_p.y" /* yacc.c:1646 */
{
SPART *mdef;
if (!sparp_arg->sparp_storage_is_set)
sparp_configure_storage_and_macro_libs (sparp_arg);
mdef = spar_find_defmacro_by_iri_or_fields (sparp_arg, (yyvsp[0].tree)->_.lit.val, NULL);
(yyval.token_type) = sparp_arg->sparp_macro_mode;
if (NULL != mdef)
{
if ((SPARP_DEFBODY & sparp_arg->sparp_macro_mode) && (sparp_arg->sparp_current_macro == mdef))
sparyyerror (sparp_arg, "The macro is recursively used in its own definition");
sparp_arg->sparp_macro_mode |= SPARP_CALLARG;
} }
#line 6946 "sparql_p.c" /* yacc.c:1646 */
break;
case 536:
#line 2309 "sparql_p.y" /* yacc.c:1646 */
{
SPART **args = (SPART **)(((dk_set_t)NIL_L == (yyvsp[0].backstack)) ? NULL : t_revlist_to_array ((yyvsp[0].backstack)));
const char *fname = (yyvsp[-2].tree)->_.lit.val;
if (sparp_arg->sparp_macro_mode & SPARP_CALLARG)
{
sparp_arg->sparp_macro_mode = (yyvsp[-1].token_type);
(yyval.tree) = sparp_make_macro_call (sparp_arg, fname, 1, args);
if (!(sparp_arg->sparp_macro_mode & SPARP_DEFBODY))
sparp_arg->sparp_macro_call_count++;
}
else
{
int is_agg = 0;
spar_verify_funcall_security (sparp_arg, &is_agg, &fname, args);
(yyval.tree) = spar_make_funcall (sparp_arg, is_agg, fname, args);
} }
#line 6967 "sparql_p.c" /* yacc.c:1646 */
break;
case 537:
#line 2328 "sparql_p.y" /* yacc.c:1646 */
{
SPART *mdef;
if (!sparp_arg->sparp_storage_is_set)
sparp_configure_storage_and_macro_libs (sparp_arg);
mdef = spar_find_defmacro_by_iri_or_fields (sparp_arg, (yyvsp[0].tree)->_.qname.val, NULL);
if (NULL == mdef)
sparyyerror (sparp_arg, "Undefined macro IRI");
if ((SPARP_DEFBODY & sparp_arg->sparp_macro_mode) && (sparp_arg->sparp_current_macro == mdef))
sparyyerror (sparp_arg, "The macro is recursively used in its own definition");
(yyval.token_type) = sparp_arg->sparp_macro_mode;
sparp_arg->sparp_macro_mode |= SPARP_CALLARG; }
#line 6983 "sparql_p.c" /* yacc.c:1646 */
break;
case 538:
#line 2339 "sparql_p.y" /* yacc.c:1646 */
{
SPART **args = (SPART **)(((dk_set_t)NIL_L == (yyvsp[0].backstack)) ? NULL : t_revlist_to_array ((yyvsp[0].backstack)));
sparp_arg->sparp_macro_mode = (yyvsp[-1].token_type);
(yyval.tree) = sparp_make_macro_call (sparp_arg, (yyvsp[-2].tree)->_.qname.val, 1, args);
if (!(sparp_arg->sparp_macro_mode & SPARP_DEFBODY))
sparp_arg->sparp_macro_call_count++;
}
#line 6995 "sparql_p.c" /* yacc.c:1646 */
break;
case 539:
#line 2350 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 7001 "sparql_p.c" /* yacc.c:1646 */
break;
case 541:
#line 2355 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (dk_set_t)NIL_L; }
#line 7007 "sparql_p.c" /* yacc.c:1646 */
break;
case 542:
#line 2356 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (dk_set_t)NIL_L; }
#line 7013 "sparql_p.c" /* yacc.c:1646 */
break;
case 543:
#line 2357 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); }
#line 7019 "sparql_p.c" /* yacc.c:1646 */
break;
case 544:
#line 2361 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 7025 "sparql_p.c" /* yacc.c:1646 */
break;
case 545:
#line 2362 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 7031 "sparql_p.c" /* yacc.c:1646 */
break;
case 546:
#line 2363 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Argument expected after comma"); }
#line 7037 "sparql_p.c" /* yacc.c:1646 */
break;
case 547:
#line 2364 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Comma or ')' expected after function argument"); }
#line 7043 "sparql_p.c" /* yacc.c:1646 */
break;
case 548:
#line 2368 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 7049 "sparql_p.c" /* yacc.c:1646 */
break;
case 550:
#line 2373 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (dk_set_t)NIL_L; }
#line 7055 "sparql_p.c" /* yacc.c:1646 */
break;
case 551:
#line 2374 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (dk_set_t)NIL_L; }
#line 7061 "sparql_p.c" /* yacc.c:1646 */
break;
case 552:
#line 2375 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); }
#line 7067 "sparql_p.c" /* yacc.c:1646 */
break;
case 553:
#line 2379 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 7073 "sparql_p.c" /* yacc.c:1646 */
break;
case 554:
#line 2380 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 7079 "sparql_p.c" /* yacc.c:1646 */
break;
case 555:
#line 2381 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Macro argument (an expression or a group pattern) expected after comma"); }
#line 7085 "sparql_p.c" /* yacc.c:1646 */
break;
case 556:
#line 2382 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Comma or ')' expected after macro argument"); }
#line 7091 "sparql_p.c" /* yacc.c:1646 */
break;
case 558:
#line 2387 "sparql_p.y" /* yacc.c:1646 */
{
spar_gp_init (sparp_arg, SPAR_MACROPU); }
#line 7098 "sparql_p.c" /* yacc.c:1646 */
break;
case 559:
#line 2389 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_gp_finalize (sparp_arg, NULL); }
#line 7104 "sparql_p.c" /* yacc.c:1646 */
break;
case 560:
#line 2393 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = SPAR_MAKE_INT_LITERAL (sparp_arg, unbox ((yyvsp[0].box))); }
#line 7110 "sparql_p.c" /* yacc.c:1646 */
break;
case 561:
#line 2394 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 5, SPAR_LIT, ((void * *)(yyvsp[0].box))[0], uname_xmlschema_ns_uri_hash_decimal, NULL, ((void * *)(yyvsp[0].box))[1]); }
#line 7116 "sparql_p.c" /* yacc.c:1646 */
break;
case 562:
#line 2395 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 5, SPAR_LIT, ((void * *)(yyvsp[0].box))[0], uname_xmlschema_ns_uri_hash_double, NULL, ((void * *)(yyvsp[0].box))[1]); }
#line 7122 "sparql_p.c" /* yacc.c:1646 */
break;
case 563:
#line 2396 "sparql_p.y" /* yacc.c:1646 */
{ double myZERO = 0.0;
double myPOSINF_d = 1.0/myZERO;
(yyval.tree) = spartlist (sparp_arg, 5, SPAR_LIT, t_box_double (myPOSINF_d), uname_xmlschema_ns_uri_hash_double, NULL, "INF"); }
#line 7130 "sparql_p.c" /* yacc.c:1646 */
break;
case 564:
#line 2399 "sparql_p.y" /* yacc.c:1646 */
{ double myZERO = 0.0;
double myNAN_d = 0.0/myZERO;
(yyval.tree) = spartlist (sparp_arg, 5, SPAR_LIT, t_box_double (myNAN_d), uname_xmlschema_ns_uri_hash_double, NULL, "NaN"); }
#line 7138 "sparql_p.c" /* yacc.c:1646 */
break;
case 566:
#line 2406 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7144 "sparql_p.c" /* yacc.c:1646 */
break;
case 567:
#line 2407 "sparql_p.y" /* yacc.c:1646 */
{
spar_change_sign (&((yyvsp[0].tree)->_.lit.val));
if (NULL != (yyvsp[0].tree)->_.lit.original_text)
(yyvsp[0].tree)->_.lit.original_text = t_box_dv_short_strconcat ("-", (yyvsp[0].tree)->_.lit.original_text);
(yyval.tree) = (yyvsp[0].tree); }
#line 7154 "sparql_p.c" /* yacc.c:1646 */
break;
case 568:
#line 2415 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = SPAR_MAKE_INT_LITERAL (sparp_arg, unbox ((yyvsp[0].box))); }
#line 7160 "sparql_p.c" /* yacc.c:1646 */
break;
case 569:
#line 2419 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = SPAR_MAKE_INT_LITERAL (sparp_arg, unbox ((yyvsp[0].box))); }
#line 7166 "sparql_p.c" /* yacc.c:1646 */
break;
case 570:
#line 2420 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = SPAR_MAKE_INT_LITERAL (sparp_arg, -unbox((yyvsp[0].box))); }
#line 7172 "sparql_p.c" /* yacc.c:1646 */
break;
case 571:
#line 2424 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 5, SPAR_LIT, (yyvsp[0].box), NULL, NULL, NULL); }
#line 7178 "sparql_p.c" /* yacc.c:1646 */
break;
case 572:
#line 2425 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 5, SPAR_LIT, (yyvsp[-1].box), NULL, (yyvsp[0].box), NULL); }
#line 7184 "sparql_p.c" /* yacc.c:1646 */
break;
case 573:
#line 2426 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_typed_literal (sparp_arg, (yyvsp[-2].box), (yyvsp[0].tree)->_.lit.val, NULL); }
#line 7190 "sparql_p.c" /* yacc.c:1646 */
break;
case 574:
#line 2430 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = SPAR_MAKE_EBV_LITERAL(sparp_arg, 1); }
#line 7196 "sparql_p.c" /* yacc.c:1646 */
break;
case 575:
#line 2431 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = SPAR_MAKE_EBV_LITERAL(sparp_arg, 0); }
#line 7202 "sparql_p.c" /* yacc.c:1646 */
break;
case 576:
#line 2435 "sparql_p.y" /* yacc.c:1646 */
{ dk_set_t lst = (yyvsp[0].backstack); t_set_push (&lst, (ptrlong)0); (yyval.trees) = (SPART **)t_list_to_array (lst); }
#line 7208 "sparql_p.c" /* yacc.c:1646 */
break;
case 577:
#line 2436 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, NULL, ((ptrlong)_STAR)); }
#line 7214 "sparql_p.c" /* yacc.c:1646 */
break;
case 578:
#line 2440 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (SPART *)((ptrlong)DEFAULT_L)); }
#line 7220 "sparql_p.c" /* yacc.c:1646 */
break;
case 579:
#line 2441 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)->_.lit.val); }
#line 7226 "sparql_p.c" /* yacc.c:1646 */
break;
case 580:
#line 2442 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (SPART *)((ptrlong)DEFAULT_L)); }
#line 7232 "sparql_p.c" /* yacc.c:1646 */
break;
case 581:
#line 2443 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)->_.lit.val); }
#line 7238 "sparql_p.c" /* yacc.c:1646 */
break;
case 582:
#line 2447 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0100, "\"variable+>property\""); (yyval.token_type) = _PLUS_GT; }
#line 7244 "sparql_p.c" /* yacc.c:1646 */
break;
case 583:
#line 2448 "sparql_p.y" /* yacc.c:1646 */
{ SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x0100, "\"variable*>property\""); (yyval.token_type) = _STAR_GT; }
#line 7250 "sparql_p.c" /* yacc.c:1646 */
break;
case 584:
#line 2452 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.trees) = (SPART **) t_list ( 4, (yyvsp[-1].token_type),
spartlist (sparp_arg, 2, SPAR_QNAME, sparp_expand_q_iri_ref (sparp_arg, (yyvsp[0].box))),
Q_IRI_REF, (yyvsp[0].box)); }
#line 7259 "sparql_p.c" /* yacc.c:1646 */
break;
case 585:
#line 2456 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.trees) = (SPART **) t_list ( 4, (yyvsp[-1].token_type),
spartlist (sparp_arg, 2, SPAR_QNAME, sparp_expand_qname_prefix (sparp_arg, (yyvsp[0].box))),
QNAME, (yyvsp[0].box)); }
#line 7268 "sparql_p.c" /* yacc.c:1646 */
break;
case 586:
#line 2460 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.trees) = (SPART **) t_list ( 4, (yyvsp[-1].token_type),
spartlist (sparp_arg, 2, SPAR_QNAME, sparp_expand_qname_prefix (sparp_arg, (yyvsp[0].box))),
QNAME_NS, (yyvsp[0].box)); }
#line 7277 "sparql_p.c" /* yacc.c:1646 */
break;
case 587:
#line 2464 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "IRI reference expected after *> or +> operator"); }
#line 7283 "sparql_p.c" /* yacc.c:1646 */
break;
case 588:
#line 2468 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 2, SPAR_QNAME, sparp_expand_q_iri_ref (sparp_arg, (yyvsp[0].box))); }
#line 7289 "sparql_p.c" /* yacc.c:1646 */
break;
case 590:
#line 2473 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 2, SPAR_QNAME, sparp_expand_qname_prefix (sparp_arg, (yyvsp[0].box))); }
#line 7295 "sparql_p.c" /* yacc.c:1646 */
break;
case 591:
#line 2474 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spartlist (sparp_arg, 2, SPAR_QNAME/*_NS*/, sparp_expand_qname_prefix (sparp_arg, (yyvsp[0].box))); }
#line 7301 "sparql_p.c" /* yacc.c:1646 */
break;
case 592:
#line 2478 "sparql_p.y" /* yacc.c:1646 */
{
if (0 < dk_set_position (sparp_arg->sparp_sg->sg_invalidated_bnode_labels, (yyvsp[0].box)))
spar_error (sparp_arg, "Blank node label %s can not be used in two different basic graph patterns", (yyvsp[0].box));
if (NULL != sparp_arg->sparp_sg->sg_bnode_label_sets)
t_set_pushnew ((dk_set_t *)(&(sparp_arg->sparp_sg->sg_bnode_label_sets->data)), (yyvsp[0].box));
(yyval.tree) = spar_make_blank_node (sparp_arg, (yyvsp[0].box), 0); }
#line 7312 "sparql_p.c" /* yacc.c:1646 */
break;
case 593:
#line 2484 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_blank_node (sparp_arg, spar_mkid (sparp_arg, "_:anon"), 1); }
#line 7318 "sparql_p.c" /* yacc.c:1646 */
break;
case 594:
#line 2490 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 7324 "sparql_p.c" /* yacc.c:1646 */
break;
case 595:
#line 2491 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 7330 "sparql_p.c" /* yacc.c:1646 */
break;
case 596:
#line 2492 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); }
#line 7336 "sparql_p.c" /* yacc.c:1646 */
break;
case 611:
#line 2518 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_drop_macro_lib (sparp_arg, (yyvsp[0].tree), (yyvsp[-3].token_type) /* yes, $2 after $5 */); }
#line 7343 "sparql_p.c" /* yacc.c:1646 */
break;
case 612:
#line 2525 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL); }
#line 7350 "sparql_p.c" /* yacc.c:1646 */
break;
case 613:
#line 2527 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != (yyvsp[-3].tree))
sparp_arg->sparp_env->spare_found_default_sparul_target = (yyvsp[-3].tree);
else if (spar_ctor_uses_default_graph ((yyvsp[0].tree)))
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, "triple constructor in INSERT {...} without GRAPH {...}", 1); }
#line 7360 "sparql_p.c" /* yacc.c:1646 */
break;
case 614:
#line 2532 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, INSERT_L, NULL, (yyvsp[0].tree) );
spar_compose_retvals_of_insert_or_delete (sparp_arg, (yyval.tree), sparp_arg->sparp_env->spare_found_default_sparul_target, (yyvsp[-2].tree)); }
#line 7368 "sparql_p.c" /* yacc.c:1646 */
break;
case 615:
#line 2540 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL);
sparp_arg->sparp_in_precode_expn = 2; }
#line 7376 "sparql_p.c" /* yacc.c:1646 */
break;
case 616:
#line 2543 "sparql_p.y" /* yacc.c:1646 */
{
SPART *fake = spar_make_fake_action_solution (sparp_arg);
SPART *dflt_g = (yyvsp[-3].tree);
if ((NULL == dflt_g) && spar_ctor_uses_default_graph ((yyvsp[0].tree)))
dflt_g = spar_default_sparul_target (sparp_arg, "triple in INSERT DATA {...} without GRAPH {...}", 0);
sparp_arg->sparp_in_precode_expn = 0;
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, SPARUL_INSERT_DATA, NULL, fake );
spar_compose_retvals_of_insert_or_delete (sparp_arg, (yyval.tree), dflt_g, (yyvsp[0].tree)); }
#line 7389 "sparql_p.c" /* yacc.c:1646 */
break;
case 617:
#line 2556 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL); }
#line 7396 "sparql_p.c" /* yacc.c:1646 */
break;
case 618:
#line 2558 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != (yyvsp[-3].tree))
sparp_arg->sparp_env->spare_found_default_sparul_target = (yyvsp[-3].tree);
else if (spar_ctor_uses_default_graph ((yyvsp[0].tree)))
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, "triple constructor in DELETE {...} without GRAPH {...}", 1); }
#line 7406 "sparql_p.c" /* yacc.c:1646 */
break;
case 619:
#line 2563 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, DELETE_L, NULL, (yyvsp[0].tree) );
spar_compose_retvals_of_insert_or_delete (sparp_arg, (yyval.tree), sparp_arg->sparp_env->spare_found_default_sparul_target, (yyvsp[-2].tree)); }
#line 7414 "sparql_p.c" /* yacc.c:1646 */
break;
case 620:
#line 2571 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL);
sparp_arg->sparp_in_precode_expn = 2; }
#line 7422 "sparql_p.c" /* yacc.c:1646 */
break;
case 621:
#line 2574 "sparql_p.y" /* yacc.c:1646 */
{
SPART *fake = spar_make_fake_action_solution (sparp_arg);
SPART *dflt_g = (yyvsp[-3].tree);
if ((NULL == dflt_g) && spar_ctor_uses_default_graph ((yyvsp[0].tree)))
dflt_g = spar_default_sparul_target (sparp_arg, "triple in DELETE DATA {...} without GRAPH {...}", 0);
sparp_arg->sparp_in_precode_expn = 0;
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, SPARUL_DELETE_DATA, NULL, fake );
spar_compose_retvals_of_insert_or_delete (sparp_arg, (yyval.tree), dflt_g, (yyvsp[0].tree)); }
#line 7435 "sparql_p.c" /* yacc.c:1646 */
break;
case 622:
#line 2588 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL); }
#line 7442 "sparql_p.c" /* yacc.c:1646 */
break;
case 623:
#line 2590 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != (yyvsp[-7].tree))
sparp_arg->sparp_env->spare_found_default_sparul_target = (yyvsp[-7].tree);
else if (spar_ctor_uses_default_graph ((yyvsp[-3].tree)))
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, "triple constructor in DELETE {...} without GRAPH {...}", 1);
else if (spar_ctor_uses_default_graph ((yyvsp[0].tree)))
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, "triple constructor in INSERT {...} without GRAPH {...}", 1); }
#line 7454 "sparql_p.c" /* yacc.c:1646 */
break;
case 624:
#line 2597 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, MODIFY_L, NULL, (yyvsp[0].tree) );
spar_compose_retvals_of_modify (sparp_arg, (yyval.tree), sparp_arg->sparp_env->spare_found_default_sparul_target, (yyvsp[-5].tree), (yyvsp[-2].tree)); }
#line 7462 "sparql_p.c" /* yacc.c:1646 */
break;
case 625:
#line 2603 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_sparul_clear (sparp_arg, (yyvsp[0].tree), (yyvsp[-1].token_type) /* yes, $2 after $3 */); }
#line 7469 "sparql_p.c" /* yacc.c:1646 */
break;
case 626:
#line 2609 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_sparul_load (sparp_arg, (yyvsp[0].tree), (yyvsp[0].tree), (yyvsp[-1].token_type)); }
#line 7476 "sparql_p.c" /* yacc.c:1646 */
break;
case 627:
#line 2611 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_sparul_load (sparp_arg, (yyvsp[0].tree), (yyvsp[-3].tree) /* yes, $3 after $6 */, (yyvsp[-4].token_type)); }
#line 7483 "sparql_p.c" /* yacc.c:1646 */
break;
case 628:
#line 2616 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_sparul_load_service_data (sparp_arg, (yyvsp[-1].tree), (SPART *)t_NEW_DB_NULL, (yyvsp[-3].token_type)); }
#line 7490 "sparql_p.c" /* yacc.c:1646 */
break;
case 629:
#line 2618 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_sparul_load_service_data (sparp_arg, (yyvsp[-4].tree), (yyvsp[0].tree), (yyvsp[-6].token_type)); }
#line 7497 "sparql_p.c" /* yacc.c:1646 */
break;
case 630:
#line 2623 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_sparul_create (sparp_arg, (yyvsp[0].tree), (yyvsp[-2].token_type) /* yes, $2 after $4 */); }
#line 7504 "sparql_p.c" /* yacc.c:1646 */
break;
case 631:
#line 2628 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_sparul_drop (sparp_arg, (yyvsp[0].tree), (yyvsp[-1].token_type) /* yes, $2 after $3 */); }
#line 7511 "sparql_p.c" /* yacc.c:1646 */
break;
case 632:
#line 2633 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_fake_action_solution (sparp_arg); }
#line 7517 "sparql_p.c" /* yacc.c:1646 */
break;
case 633:
#line 2634 "sparql_p.y" /* yacc.c:1646 */
{
SPART *where_gp = spar_gp_finalize (sparp_arg, NULL);
(yyval.tree) = (yyvsp[0].tree);
(yyvsp[0].tree)->_.wm.where_gp = where_gp; }
#line 7526 "sparql_p.c" /* yacc.c:1646 */
break;
case 634:
#line 2641 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 7532 "sparql_p.c" /* yacc.c:1646 */
break;
case 635:
#line 2642 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7538 "sparql_p.c" /* yacc.c:1646 */
break;
case 636:
#line 2646 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7544 "sparql_p.c" /* yacc.c:1646 */
break;
case 637:
#line 2650 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 7550 "sparql_p.c" /* yacc.c:1646 */
break;
case 638:
#line 2651 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7556 "sparql_p.c" /* yacc.c:1646 */
break;
case 639:
#line 2655 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7562 "sparql_p.c" /* yacc.c:1646 */
break;
case 640:
#line 2659 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)ALL_L; }
#line 7568 "sparql_p.c" /* yacc.c:1646 */
break;
case 641:
#line 2660 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)DEFAULT_L; }
#line 7574 "sparql_p.c" /* yacc.c:1646 */
break;
case 642:
#line 2661 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)NAMED_L; }
#line 7580 "sparql_p.c" /* yacc.c:1646 */
break;
case 643:
#line 2662 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7586 "sparql_p.c" /* yacc.c:1646 */
break;
case 644:
#line 2666 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)DEFAULT_L; }
#line 7592 "sparql_p.c" /* yacc.c:1646 */
break;
case 645:
#line 2667 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7598 "sparql_p.c" /* yacc.c:1646 */
break;
case 646:
#line 2671 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 7604 "sparql_p.c" /* yacc.c:1646 */
break;
case 647:
#line 2672 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7610 "sparql_p.c" /* yacc.c:1646 */
break;
case 648:
#line 2676 "sparql_p.y" /* yacc.c:1646 */
{}
#line 7616 "sparql_p.c" /* yacc.c:1646 */
break;
case 649:
#line 2677 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x2000, "WITH clause");
sparp_arg->sparp_env->spare_src.ssrc_graph_set_by_with = (yyvsp[-1].tree);
sparp_make_and_push_new_graph_source (sparp_arg, SPART_GRAPH_FROM, (yyvsp[-1].tree), (yyvsp[0].trees), SPARP_SSRC_FROZEN_BY_PROTOCOL); }
#line 7625 "sparql_p.c" /* yacc.c:1646 */
break;
case 650:
#line 2684 "sparql_p.y" /* yacc.c:1646 */
{}
#line 7631 "sparql_p.c" /* yacc.c:1646 */
break;
case 651:
#line 2685 "sparql_p.y" /* yacc.c:1646 */
{}
#line 7637 "sparql_p.c" /* yacc.c:1646 */
break;
case 652:
#line 2689 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = 0; }
#line 7643 "sparql_p.c" /* yacc.c:1646 */
break;
case 653:
#line 2690 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = 1; }
#line 7649 "sparql_p.c" /* yacc.c:1646 */
break;
case 654:
#line 2699 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL); }
#line 7656 "sparql_p.c" /* yacc.c:1646 */
break;
case 655:
#line 2701 "sparql_p.y" /* yacc.c:1646 */
{
if (spar_ctor_uses_default_graph ((yyvsp[-1].tree)))
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, "triple constructor in DELETE {...} without GRAPH {...}", 1);
else if ((NULL != (yyvsp[0].tree)) && spar_ctor_uses_default_graph ((yyvsp[0].tree)))
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, "triple constructor in INSERT {...} without GRAPH {...}", 1); }
#line 7666 "sparql_p.c" /* yacc.c:1646 */
break;
case 656:
#line 2706 "sparql_p.y" /* yacc.c:1646 */
{
if (NULL != (yyvsp[-2].tree))
{
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, MODIFY_L, NULL, (yyvsp[0].tree) );
spar_compose_retvals_of_modify (sparp_arg, (yyval.tree), sparp_arg->sparp_env->spare_found_default_sparul_target, (yyvsp[-3].tree), (yyvsp[-2].tree)); }
else
{
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, DELETE_L, NULL, (yyvsp[0].tree) );
spar_compose_retvals_of_insert_or_delete (sparp_arg, (yyval.tree), sparp_arg->sparp_env->spare_found_default_sparul_target, (yyvsp[-3].tree)); } }
#line 7680 "sparql_p.c" /* yacc.c:1646 */
break;
case 657:
#line 2715 "sparql_p.y" /* yacc.c:1646 */
{
spar_apply_fallback_default_graph (sparp_arg, 1);
sparp_arg->sparp_allow_aggregates_in_expn &= ~1;
sparp_arg->sparp_in_ctor_from_where = 1;
spar_gp_init (sparp_arg, WHERE_L); }
#line 7690 "sparql_p.c" /* yacc.c:1646 */
break;
case 658:
#line 2720 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_in_ctor_from_where = 0; }
#line 7697 "sparql_p.c" /* yacc.c:1646 */
break;
case 659:
#line 2722 "sparql_p.y" /* yacc.c:1646 */
{
SPART *where_gp = spar_gp_finalize (sparp_arg, NULL);
SPART *wm = (yyvsp[0].tree);
SPART *dflt_g = NULL;
if (spar_ctor_uses_default_graph (where_gp)) /* To check for errors only, the default graph is set by spar_apply_fallback_default_graph (sparp_arg, 1) above (if set at all) */
spar_default_sparul_target (sparp_arg, "triple in DELETE WHERE {...} without GRAPH {...}", 0);
wm->_.wm.where_gp = where_gp;
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, DELETE_L, NULL, wm);
spar_compose_retvals_of_delete_from_wm (sparp_arg, (yyval.tree), dflt_g); }
#line 7711 "sparql_p.c" /* yacc.c:1646 */
break;
case 660:
#line 2737 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_env->spare_propvar_sets), NULL); }
#line 7718 "sparql_p.c" /* yacc.c:1646 */
break;
case 661:
#line 2739 "sparql_p.y" /* yacc.c:1646 */
{
if (spar_ctor_uses_default_graph ((yyvsp[0].tree)))
sparp_arg->sparp_env->spare_found_default_sparul_target = spar_default_sparul_target (sparp_arg, "triple constructor in INSERT {...} without GRAPH {...}", 1); }
#line 7726 "sparql_p.c" /* yacc.c:1646 */
break;
case 662:
#line 2742 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_top_or_special_case_from_wm (sparp_arg, INSERT_L, NULL, (yyvsp[0].tree) );
spar_compose_retvals_of_insert_or_delete (sparp_arg, (yyval.tree), sparp_arg->sparp_env->spare_found_default_sparul_target, (yyvsp[-2].tree)); }
#line 7734 "sparql_p.c" /* yacc.c:1646 */
break;
case 663:
#line 2748 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 7740 "sparql_p.c" /* yacc.c:1646 */
break;
case 664:
#line 2749 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (yyvsp[0].tree); }
#line 7746 "sparql_p.c" /* yacc.c:1646 */
break;
case 665:
#line 2753 "sparql_p.y" /* yacc.c:1646 */
{
SPAR_ERROR_IF_UNSUPPORTED_SYNTAX (0x2000, "WITH clause");
(yyval.tree) = spar_make_sparul_copymoveadd (sparp_arg, (yyvsp[-4].token_type), (yyvsp[-2].tree), (yyvsp[0].tree), (yyvsp[-3].token_type) /* yes, $2 after $3 */); }
#line 7754 "sparql_p.c" /* yacc.c:1646 */
break;
case 666:
#line 2759 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = COPY_L; }
#line 7760 "sparql_p.c" /* yacc.c:1646 */
break;
case 667:
#line 2760 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = MOVE_L; }
#line 7766 "sparql_p.c" /* yacc.c:1646 */
break;
case 668:
#line 2761 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = ADD_L; }
#line 7772 "sparql_p.c" /* yacc.c:1646 */
break;
case 670:
#line 2768 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_e4qm->e4qm_default_table = NULL; }
#line 7779 "sparql_p.c" /* yacc.c:1646 */
break;
case 672:
#line 2774 "sparql_p.y" /* yacc.c:1646 */
{ t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls), (yyvsp[0].tree)); }
#line 7785 "sparql_p.c" /* yacc.c:1646 */
break;
case 680:
#line 2792 "sparql_p.y" /* yacc.c:1646 */
{
if (dk_set_get_keyword (sparp_arg->sparp_created_jsos, (yyvsp[-3].box), NULL))
spar_error (sparp_arg, "The identifier of %s class %.100s is already used in the previous part of the statement",
((IRI_L == (yyvsp[-5].token_type)) ? "IRI" : "literal"), (yyvsp[-3].box));
t_set_push (&(sparp_arg->sparp_created_jsos), ((IRI_L == (yyvsp[-5].token_type)) ? "IRI class" : "literal class"));
t_set_push (&(sparp_arg->sparp_created_jsos), (yyvsp[-3].box));
(yyval.tree) = spar_make_qm_sql (sparp_arg,
((IRI_L == (yyvsp[-5].token_type)) ? "DB.DBA.RDF_QM_DEFINE_IRI_CLASS_FORMAT" : "DB.DBA.RDF_QM_DEFINE_LITERAL_CLASS_FORMAT"),
(SPART **)t_list (3, (yyvsp[-3].box), (yyvsp[-2].box), (yyvsp[-1].tree)), (yyvsp[0].trees) ); }
#line 7799 "sparql_p.c" /* yacc.c:1646 */
break;
case 681:
#line 2801 "sparql_p.y" /* yacc.c:1646 */
{
if (dk_set_get_keyword (sparp_arg->sparp_created_jsos, (yyvsp[-3].box), NULL))
spar_error (sparp_arg, "The identifier of %s class %.100s is already used in the previous part of the statement",
((IRI_L == (yyvsp[-5].token_type)) ? "IRI" : "literal"), (yyvsp[-3].box));
t_set_push (&(sparp_arg->sparp_created_jsos), ((IRI_L == (yyvsp[-5].token_type)) ? "IRI class" : "literal class"));
t_set_push (&(sparp_arg->sparp_created_jsos), (yyvsp[-3].box));
(yyval.tree) = spar_make_qm_sql (sparp_arg,
((IRI_L == (yyvsp[-5].token_type)) ? "DB.DBA.RDF_QM_DEFINE_IRI_CLASS_FUNCTIONS" : "DB.DBA.RDF_QM_DEFINE_LITERAL_CLASS_FUNCTIONS"),
(SPART **)t_list (2, (yyvsp[-3].box), spar_make_vector_qm_sql (sparp_arg, (SPART **)t_revlist_to_array ((yyvsp[-1].backstack)))), (yyvsp[0].trees) ); }
#line 7813 "sparql_p.c" /* yacc.c:1646 */
break;
case 682:
#line 2813 "sparql_p.y" /* yacc.c:1646 */
{
if (dk_set_get_keyword (sparp_arg->sparp_created_jsos, (yyvsp[0].box), NULL))
spar_error (sparp_arg, "The identifier of %s class %.100s is already used in the previous part of the statement",
((IRI_L == (yyvsp[-2].token_type)) ? "IRI" : "literal"), (yyvsp[0].box));
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DROP_CLASS",
(SPART **)t_list (2, (yyvsp[0].box), (yyvsp[-3].token_type) /* yes, $2 after $5 */), NULL );
sparp_jso_push_deleted (sparp_arg, uname_virtrdf_ns_uri_QuadMapFormat , (yyvsp[0].box)); }
#line 7825 "sparql_p.c" /* yacc.c:1646 */
break;
case 683:
#line 2823 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DEFINE_SUBCLASS",
(SPART **)t_list (2, (yyvsp[-3].box), (yyvsp[0].box)), NULL ); }
#line 7833 "sparql_p.c" /* yacc.c:1646 */
break;
case 684:
#line 2826 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DEFINE_SUBCLASS",
(SPART **)t_list (2, (yyvsp[-3].box), (yyvsp[0].box)), NULL ); }
#line 7841 "sparql_p.c" /* yacc.c:1646 */
break;
case 685:
#line 2832 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (0); }
#line 7847 "sparql_p.c" /* yacc.c:1646 */
break;
case 686:
#line 2833 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (0); }
#line 7853 "sparql_p.c" /* yacc.c:1646 */
break;
case 687:
#line 2834 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 7859 "sparql_p.c" /* yacc.c:1646 */
break;
case 688:
#line 2838 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = NULL;
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[0]);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[1]); }
#line 7868 "sparql_p.c" /* yacc.c:1646 */
break;
case 689:
#line 2842 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = (yyvsp[-2].backstack);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[0]);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[1]); }
#line 7877 "sparql_p.c" /* yacc.c:1646 */
break;
case 690:
#line 2849 "sparql_p.y" /* yacc.c:1646 */
{ /*... ( 'DATATYPE' QmIRIrefConst ) */
(yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("DATATYPE"), t_box_dv_uname_string ((yyvsp[0].box))); }
#line 7884 "sparql_p.c" /* yacc.c:1646 */
break;
case 691:
#line 2851 "sparql_p.y" /* yacc.c:1646 */
{ /*... | ( 'LANG' STRING ) */
(yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("LANG"), t_box_dv_uname_string ((yyvsp[0].box))); }
#line 7891 "sparql_p.c" /* yacc.c:1646 */
break;
case 692:
#line 2853 "sparql_p.y" /* yacc.c:1646 */
{ /*... | ( 'LANG' STRING ) */
(yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("LANG"), t_box_dv_uname_string ((yyvsp[0].box))); }
#line 7898 "sparql_p.c" /* yacc.c:1646 */
break;
case 693:
#line 2855 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'BIJECTION' */
(yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("BIJECTION"), (ptrlong)1); }
#line 7905 "sparql_p.c" /* yacc.c:1646 */
break;
case 694:
#line 2857 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'DEREF' */
(yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("DEREF"), (ptrlong)1); }
#line 7912 "sparql_p.c" /* yacc.c:1646 */
break;
case 695:
#line 2859 "sparql_p.y" /* yacc.c:1646 */
{ /*... | 'RETURNS' STRING ('UNION' STRING)* */
(yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("RETURNS"),
spar_make_vector_qm_sql (sparp_arg, (SPART **)t_revlist_to_array ((yyvsp[0].backstack))) ); }
#line 7920 "sparql_p.c" /* yacc.c:1646 */
break;
case 696:
#line 2865 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].box)); }
#line 7926 "sparql_p.c" /* yacc.c:1646 */
break;
case 697:
#line 2866 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].box)); }
#line 7932 "sparql_p.c" /* yacc.c:1646 */
break;
case 698:
#line 2870 "sparql_p.y" /* yacc.c:1646 */
{
sparp_env()->spare_storage_name = (yyvsp[0].box);
if (dk_set_get_keyword (sparp_arg->sparp_created_jsos, (yyvsp[0].box), NULL))
spar_error (sparp_arg, "The identifier of Quad Storage %.100s is already used in the previous part of the statement", (yyvsp[0].box));
t_set_push (&(sparp_arg->sparp_created_jsos), "Quad Storage");
t_set_push (&(sparp_arg->sparp_created_jsos), (yyvsp[0].box));
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DEFINE_QUAD_STORAGE",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)), NULL ) );
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_BEGIN_ALTER_QUAD_STORAGE",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)), NULL ) );
sparp_jso_push_affected (sparp_arg, (yyvsp[0].box)); }
#line 7950 "sparql_p.c" /* yacc.c:1646 */
break;
case 699:
#line 2884 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_bookmark (sparp_arg); }
#line 7957 "sparql_p.c" /* yacc.c:1646 */
break;
case 700:
#line 2886 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_END_ALTER_QUAD_STORAGE",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)), NULL ) );
spar_qm_pop_bookmark (sparp_arg);
sparp_env()->spare_storage_name = NULL; }
#line 7968 "sparql_p.c" /* yacc.c:1646 */
break;
case 701:
#line 2895 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = IRI_L; }
#line 7974 "sparql_p.c" /* yacc.c:1646 */
break;
case 702:
#line 2896 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.token_type) = LITERAL_L; }
#line 7980 "sparql_p.c" /* yacc.c:1646 */
break;
case 703:
#line 2900 "sparql_p.y" /* yacc.c:1646 */
{
sparp_env()->spare_storage_name = (yyvsp[0].box);
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_BEGIN_ALTER_QUAD_STORAGE",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)), NULL ) );
sparp_jso_push_affected (sparp_arg, (yyvsp[0].box)); }
#line 7991 "sparql_p.c" /* yacc.c:1646 */
break;
case 704:
#line 2907 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_bookmark (sparp_arg); }
#line 7998 "sparql_p.c" /* yacc.c:1646 */
break;
case 705:
#line 2909 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_END_ALTER_QUAD_STORAGE",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)), NULL ) );
spar_qm_pop_bookmark (sparp_arg);
sparp_env()->spare_storage_name = NULL; }
#line 8009 "sparql_p.c" /* yacc.c:1646 */
break;
case 706:
#line 2918 "sparql_p.y" /* yacc.c:1646 */
{
if (dk_set_get_keyword (sparp_arg->sparp_created_jsos, (yyvsp[0].box), NULL))
spar_error (sparp_arg, "The identifier of Quad Storage %.100s is already used in the previous part of the statement", (yyvsp[0].box));
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DROP_QUAD_STORAGE",
(SPART **)t_list (2, (yyvsp[0].box), (yyvsp[-3].token_type) /* yes, $2 after $5 */), NULL ) );
sparp_jso_push_deleted (sparp_arg, uname_virtrdf_ns_uri_QuadStorage , (yyvsp[0].box));
sparp_jso_push_affected (sparp_arg, (yyvsp[0].box)); }
#line 8022 "sparql_p.c" /* yacc.c:1646 */
break;
case 707:
#line 2929 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DROP_MAPPING",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)),
(SPART **)t_list (4, t_box_dv_uname_string ("ID"), (yyvsp[0].box), t_box_dv_uname_string ("SILENT"), (SPART *)t_box_num_nonull ((yyvsp[-3].token_type))) );
if (NULL != sparp_env()->spare_storage_name)
sparp_jso_push_affected (sparp_arg, sparp_env()->spare_storage_name); }
#line 8033 "sparql_p.c" /* yacc.c:1646 */
break;
case 708:
#line 2935 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DROP_MAPPING",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)),
(SPART **)t_list (4, t_box_dv_uname_string ("GRAPH"), (yyvsp[0].box), t_box_dv_uname_string ("SILENT"), (SPART *)t_box_num_nonull ((yyvsp[-4].token_type))) );
if (NULL != sparp_env()->spare_storage_name)
sparp_jso_push_affected (sparp_arg, sparp_env()->spare_storage_name); }
#line 8044 "sparql_p.c" /* yacc.c:1646 */
break;
case 709:
#line 2944 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DROP_MAPPING",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)),
(SPART **)t_list (4, t_box_dv_uname_string ("ID"), (yyvsp[0].box), t_box_dv_uname_string ("SILENT"), (SPART *)t_box_num_nonull ((yyvsp[-1].token_type))) );
if (NULL != sparp_env()->spare_storage_name)
sparp_jso_push_affected (sparp_arg, sparp_env()->spare_storage_name); }
#line 8055 "sparql_p.c" /* yacc.c:1646 */
break;
case 710:
#line 2950 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DROP_MAPPING",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)),
(SPART **)t_list (4, t_box_dv_uname_string ("GRAPH"), (yyvsp[0].box), t_box_dv_uname_string ("SILENT"), (SPART *)t_box_num_nonull ((yyvsp[-2].token_type))) );
if (NULL != sparp_env()->spare_storage_name)
sparp_jso_push_affected (sparp_arg, sparp_env()->spare_storage_name); }
#line 8066 "sparql_p.c" /* yacc.c:1646 */
break;
case 711:
#line 2959 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8072 "sparql_p.c" /* yacc.c:1646 */
break;
case 712:
#line 2960 "sparql_p.y" /* yacc.c:1646 */
{ /*... ( 'FROM' QTABLE 'AS' PLAIN_ID QmTextLiteral* ) */
spar_qm_add_aliased_table_or_sqlquery (sparp_arg, (yyvsp[-2].box), (yyvsp[0].box));
sparp_arg->sparp_e4qm->e4qm_current_table_alias = (yyvsp[0].box); }
#line 8080 "sparql_p.c" /* yacc.c:1646 */
break;
case 713:
#line 2963 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_e4qm->e4qm_current_table_alias = NULL; }
#line 8087 "sparql_p.c" /* yacc.c:1646 */
break;
case 714:
#line 2965 "sparql_p.y" /* yacc.c:1646 */
{ /*... | ( 'FROM' PLAIN_ID 'AS' PLAIN_ID QmTextLiteral* ) */
spar_qm_add_aliased_alias (sparp_arg, (yyvsp[-2].box), (yyvsp[0].box));
sparp_arg->sparp_e4qm->e4qm_current_table_alias = (yyvsp[0].box); }
#line 8095 "sparql_p.c" /* yacc.c:1646 */
break;
case 715:
#line 2968 "sparql_p.y" /* yacc.c:1646 */
{ /*... | ( 'FROM' 'SQLQUERY' QmSqlQuery 'AS' PLAIN_ID QmTextLiteral* ) */
void * qry = t_box_sprintf (100 + strlen((yyvsp[-2].box)), "/*[sqlquery[*/ %s\n/*]sqlquery]*/", (yyvsp[-2].box));
spar_qm_add_aliased_table_or_sqlquery (sparp_arg, qry, (yyvsp[0].box));
sparp_arg->sparp_e4qm->e4qm_current_table_alias = (yyvsp[0].box); }
#line 8104 "sparql_p.c" /* yacc.c:1646 */
break;
case 716:
#line 2972 "sparql_p.y" /* yacc.c:1646 */
{
sparp_arg->sparp_e4qm->e4qm_current_table_alias = NULL; }
#line 8111 "sparql_p.c" /* yacc.c:1646 */
break;
case 717:
#line 2974 "sparql_p.y" /* yacc.c:1646 */
{ /*... | QmCondition */
spar_qm_add_table_filter (sparp_arg, (yyvsp[0].box)); }
#line 8118 "sparql_p.c" /* yacc.c:1646 */
break;
case 718:
#line 2979 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8124 "sparql_p.c" /* yacc.c:1646 */
break;
case 720:
#line 2984 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_add_text_literal (sparp_arg,
sparp_arg->sparp_e4qm->e4qm_current_table_alias,
(yyvsp[-4].box), (yyvsp[-2].tree), (yyvsp[-1].trees), (yyvsp[0].trees) ); }
#line 8133 "sparql_p.c" /* yacc.c:1646 */
break;
case 721:
#line 2991 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = NULL; }
#line 8139 "sparql_p.c" /* yacc.c:1646 */
break;
case 722:
#line 2992 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = (void *)((ptrlong)(XML_L)); }
#line 8145 "sparql_p.c" /* yacc.c:1646 */
break;
case 723:
#line 2996 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = NULL; }
#line 8151 "sparql_p.c" /* yacc.c:1646 */
break;
case 724:
#line 2997 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 8157 "sparql_p.c" /* yacc.c:1646 */
break;
case 725:
#line 3001 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = NULL; }
#line 8163 "sparql_p.c" /* yacc.c:1646 */
break;
case 726:
#line 3002 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 8169 "sparql_p.c" /* yacc.c:1646 */
break;
case 727:
#line 3006 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = NULL;
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[1]);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[0]); }
#line 8178 "sparql_p.c" /* yacc.c:1646 */
break;
case 728:
#line 3010 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = (yyvsp[-2].backstack);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[1]);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[0]); }
#line 8187 "sparql_p.c" /* yacc.c:1646 */
break;
case 729:
#line 3017 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ((yyvsp[0].box)), NULL); }
#line 8193 "sparql_p.c" /* yacc.c:1646 */
break;
case 730:
#line 3018 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ((yyvsp[-1].box)), (yyvsp[0].box)); }
#line 8199 "sparql_p.c" /* yacc.c:1646 */
break;
case 731:
#line 3022 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8205 "sparql_p.c" /* yacc.c:1646 */
break;
case 732:
#line 3023 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8211 "sparql_p.c" /* yacc.c:1646 */
break;
case 733:
#line 3024 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8217 "sparql_p.c" /* yacc.c:1646 */
break;
case 734:
#line 3028 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8223 "sparql_p.c" /* yacc.c:1646 */
break;
case 735:
#line 3029 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_clean_locals (sparp_arg);
sparp_arg->sparp_e4qm->e4qm_default_table = NULL; }
#line 8231 "sparql_p.c" /* yacc.c:1646 */
break;
case 736:
#line 3032 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8237 "sparql_p.c" /* yacc.c:1646 */
break;
case 738:
#line 3037 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls), (yyvsp[0].tree)); }
#line 8244 "sparql_p.c" /* yacc.c:1646 */
break;
case 739:
#line 3039 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls), (yyvsp[0].tree)); }
#line 8251 "sparql_p.c" /* yacc.c:1646 */
break;
case 740:
#line 3041 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls), (yyvsp[0].tree)); }
#line 8258 "sparql_p.c" /* yacc.c:1646 */
break;
case 741:
#line 3043 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls), (yyvsp[0].tree)); }
#line 8265 "sparql_p.c" /* yacc.c:1646 */
break;
case 742:
#line 3048 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_ATTACH_MACRO_LIBRARY",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)),
(SPART **)t_list (2, t_box_dv_uname_string ("ID"), (yyvsp[0].box)) );
if (NULL != sparp_env()->spare_storage_name)
sparp_jso_push_affected (sparp_arg, sparp_env()->spare_storage_name); }
#line 8276 "sparql_p.c" /* yacc.c:1646 */
break;
case 743:
#line 3057 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DETACH_MACRO_LIBRARY",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)),
(SPART **)t_list (4, t_box_dv_uname_string ("ID"), (yyvsp[0].box), t_box_dv_uname_string ("SILENT"), (SPART *)t_box_num_nonull ((yyvsp[-3].token_type))) );
if (NULL != sparp_env()->spare_storage_name)
sparp_jso_push_affected (sparp_arg, sparp_env()->spare_storage_name); }
#line 8287 "sparql_p.c" /* yacc.c:1646 */
break;
case 744:
#line 3063 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_DETACH_MACRO_LIBRARY",
(SPART **)t_list (1, t_box_copy (sparp_env()->spare_storage_name)),
(SPART **)t_list (2, t_box_dv_uname_string ("SILENT"), (SPART *)t_box_num_nonull ((yyvsp[-2].token_type))) );
if (NULL != sparp_env()->spare_storage_name)
sparp_jso_push_affected (sparp_arg, sparp_env()->spare_storage_name); }
#line 8298 "sparql_p.c" /* yacc.c:1646 */
break;
case 745:
#line 3072 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8304 "sparql_p.c" /* yacc.c:1646 */
break;
case 746:
#line 3073 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8310 "sparql_p.c" /* yacc.c:1646 */
break;
case 747:
#line 3074 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8316 "sparql_p.c" /* yacc.c:1646 */
break;
case 749:
#line 3079 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_clean_locals (sparp_arg);
sparp_arg->sparp_e4qm->e4qm_default_table = NULL; }
#line 8324 "sparql_p.c" /* yacc.c:1646 */
break;
case 751:
#line 3087 "sparql_p.y" /* yacc.c:1646 */
{ spar_qm_push_local (sparp_arg, CREATE_L, (SPART *)((yyvsp[-1].box)), 1); }
#line 8330 "sparql_p.c" /* yacc.c:1646 */
break;
case 752:
#line 3088 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 8336 "sparql_p.c" /* yacc.c:1646 */
break;
case 753:
#line 3090 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, CREATE_L, (SPART *)((yyvsp[-4].box)), 1);
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_ATTACH_MAPPING",
(SPART **)t_list (2, t_box_copy (sparp_env()->spare_storage_name), (yyvsp[-1].box)),
t_spartlist_concat ((yyvsp[0].trees), (SPART **)t_list (2, t_box_dv_uname_string ("ID"), (yyvsp[-4].box))) ) ); }
#line 8347 "sparql_p.c" /* yacc.c:1646 */
break;
case 754:
#line 3097 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, GRAPH_L, (SPART *)((yyvsp[-4].box)), 1);
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_make_qm_sql (sparp_arg, "DB.DBA.RDF_QM_ATTACH_MAPPING",
(SPART **)t_list (2, t_box_copy (sparp_env()->spare_storage_name), (yyvsp[-1].box)),
t_spartlist_concat ((yyvsp[0].trees), (SPART **)t_list (2, t_box_dv_uname_string ("GRAPH"), (yyvsp[-4].box))) ) ); }
#line 8358 "sparql_p.c" /* yacc.c:1646 */
break;
case 755:
#line 3104 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_qm_make_empty_mapping (sparp_arg, NULL, (yyvsp[-1].trees)) );
spar_qm_push_local (sparp_arg, _LBRA,
spar_qm_get_local (sparp_arg, CREATE_L, 1), 1 );
spar_qm_push_local (sparp_arg, CREATE_L, NULL, 1);
spar_qm_push_bookmark (sparp_arg); }
#line 8370 "sparql_p.c" /* yacc.c:1646 */
break;
case 756:
#line 3111 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_pop_bookmark (sparp_arg); }
#line 8377 "sparql_p.c" /* yacc.c:1646 */
break;
case 758:
#line 3117 "sparql_p.y" /* yacc.c:1646 */
{ }
#line 8383 "sparql_p.c" /* yacc.c:1646 */
break;
case 759:
#line 3119 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_qm_make_empty_mapping (sparp_arg,
(void *) spar_qm_get_local (sparp_arg, CREATE_L, 1),
(yyvsp[-1].trees) ) );
spar_qm_push_local (sparp_arg, _LBRA,
spar_qm_get_local (sparp_arg, CREATE_L, 1), 1 );
spar_qm_push_local (sparp_arg, CREATE_L, NULL, 1);
spar_qm_push_bookmark (sparp_arg); }
#line 8397 "sparql_p.c" /* yacc.c:1646 */
break;
case 760:
#line 3128 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_pop_bookmark (sparp_arg); }
#line 8404 "sparql_p.c" /* yacc.c:1646 */
break;
case 761:
#line 3133 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, SUBJECT_L,
((NULL != (yyvsp[-2].tree)) ? ((SPART *)((yyvsp[-2].tree))) : spar_qm_get_local (sparp_arg, SUBJECT_L, 1)),
0);
spar_qm_push_local (sparp_arg, PREDICATE_L,
((NULL != (yyvsp[-1].tree)) ? ((SPART *)((yyvsp[-1].tree))) : spar_qm_get_local (sparp_arg, PREDICATE_L, 1)),
0);
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_qm_make_real_mapping (sparp_arg,
(void *)spar_qm_get_local (sparp_arg, CREATE_L, 0),
(yyvsp[0].trees) ) ); }
#line 8420 "sparql_p.c" /* yacc.c:1646 */
break;
case 762:
#line 3147 "sparql_p.y" /* yacc.c:1646 */
{ spar_qm_push_local (sparp_arg, SUBJECT_L, (yyvsp[0].tree), 0); }
#line 8426 "sparql_p.c" /* yacc.c:1646 */
break;
case 763:
#line 3148 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8432 "sparql_p.c" /* yacc.c:1646 */
break;
case 764:
#line 3152 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8438 "sparql_p.c" /* yacc.c:1646 */
break;
case 765:
#line 3153 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8444 "sparql_p.c" /* yacc.c:1646 */
break;
case 766:
#line 3157 "sparql_p.y" /* yacc.c:1646 */
{ spar_qm_push_local (sparp_arg, GRAPH_L, (yyvsp[0].tree), 0); }
#line 8450 "sparql_p.c" /* yacc.c:1646 */
break;
case 767:
#line 3158 "sparql_p.y" /* yacc.c:1646 */
{ spar_qm_push_local (sparp_arg, SUBJECT_L, (yyvsp[0].tree), 0); }
#line 8456 "sparql_p.c" /* yacc.c:1646 */
break;
case 768:
#line 3159 "sparql_p.y" /* yacc.c:1646 */
{ spar_qm_push_local (sparp_arg, PREDICATE_L, (yyvsp[0].tree), 0); }
#line 8462 "sparql_p.c" /* yacc.c:1646 */
break;
case 769:
#line 3160 "sparql_p.y" /* yacc.c:1646 */
{ spar_qm_push_local (sparp_arg, OBJECT_L, (yyvsp[0].tree), 0); }
#line 8468 "sparql_p.c" /* yacc.c:1646 */
break;
case 770:
#line 3161 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, DATATYPE_L, (SPART *)((yyvsp[0].tree)), 0); }
#line 8475 "sparql_p.c" /* yacc.c:1646 */
break;
case 771:
#line 3163 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, LANG_L, (SPART *)((yyvsp[0].tree)), 0); }
#line 8482 "sparql_p.c" /* yacc.c:1646 */
break;
case 772:
#line 3169 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8488 "sparql_p.c" /* yacc.c:1646 */
break;
case 773:
#line 3170 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_pop_key (sparp_arg, PREDICATE_L); }
#line 8495 "sparql_p.c" /* yacc.c:1646 */
break;
case 775:
#line 3176 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, PREDICATE_L,
((NULL != (yyvsp[0].tree)) ? ((SPART *)((yyvsp[0].tree))) : spar_qm_get_local (sparp_arg, PREDICATE_L, 1)),
0 ); }
#line 8504 "sparql_p.c" /* yacc.c:1646 */
break;
case 776:
#line 3180 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8510 "sparql_p.c" /* yacc.c:1646 */
break;
case 777:
#line 3181 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Description of predicate field is expected here"); }
#line 8516 "sparql_p.c" /* yacc.c:1646 */
break;
case 778:
#line 3185 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_qm_make_real_mapping (sparp_arg, (yyvsp[0].box), (yyvsp[-1].trees)) ); }
#line 8524 "sparql_p.c" /* yacc.c:1646 */
break;
case 779:
#line 3188 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_pop_key (sparp_arg, OBJECT_L); }
#line 8531 "sparql_p.c" /* yacc.c:1646 */
break;
case 780:
#line 3190 "sparql_p.y" /* yacc.c:1646 */
{
t_set_push (&(sparp_arg->sparp_e4qm->e4qm_acc_sqls),
spar_qm_make_real_mapping (sparp_arg, (yyvsp[0].box), (yyvsp[-1].trees)) ); }
#line 8539 "sparql_p.c" /* yacc.c:1646 */
break;
case 781:
#line 3196 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, OBJECT_L,
((NULL != (yyvsp[0].tree)) ? ((SPART *)((yyvsp[0].tree))) : spar_qm_get_local (sparp_arg, OBJECT_L, 1)),
0 ); }
#line 8548 "sparql_p.c" /* yacc.c:1646 */
break;
case 782:
#line 3200 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, DATATYPE_L, (SPART *)((yyvsp[0].tree)), 0); }
#line 8555 "sparql_p.c" /* yacc.c:1646 */
break;
case 783:
#line 3202 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, LANG_L, (SPART *)((yyvsp[0].tree)), 0); }
#line 8562 "sparql_p.c" /* yacc.c:1646 */
break;
case 784:
#line 3204 "sparql_p.y" /* yacc.c:1646 */
{
spar_qm_push_local (sparp_arg, WHERE_L, (SPART *)t_revlist_to_array ((yyvsp[0].backstack)), 0); }
#line 8569 "sparql_p.c" /* yacc.c:1646 */
break;
case 785:
#line 3206 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (yyvsp[0].trees); }
#line 8575 "sparql_p.c" /* yacc.c:1646 */
break;
case 786:
#line 3207 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Description of object field is expected here"); }
#line 8581 "sparql_p.c" /* yacc.c:1646 */
break;
case 787:
#line 3211 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = NULL; }
#line 8587 "sparql_p.c" /* yacc.c:1646 */
break;
case 788:
#line 3212 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = (yyvsp[0].box); }
#line 8593 "sparql_p.c" /* yacc.c:1646 */
break;
case 789:
#line 3216 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 8599 "sparql_p.c" /* yacc.c:1646 */
break;
case 790:
#line 3217 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)(yyvsp[0].tree)->_.lit.val; }
#line 8605 "sparql_p.c" /* yacc.c:1646 */
break;
case 791:
#line 3218 "sparql_p.y" /* yacc.c:1646 */
{ sparyyerror (sparp_arg, "Datatype of object field should be either constant IRI or table field, not template IRI (string)"); }
#line 8611 "sparql_p.c" /* yacc.c:1646 */
break;
case 792:
#line 3219 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_qm_col_desc (sparp_arg, (yyvsp[0].tree)); }
#line 8617 "sparql_p.c" /* yacc.c:1646 */
break;
case 793:
#line 3223 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 8623 "sparql_p.c" /* yacc.c:1646 */
break;
case 794:
#line 3224 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)(yyvsp[0].box); }
#line 8629 "sparql_p.c" /* yacc.c:1646 */
break;
case 795:
#line 3225 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_qm_col_desc (sparp_arg, (yyvsp[0].tree)); }
#line 8635 "sparql_p.c" /* yacc.c:1646 */
break;
case 797:
#line 3230 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 8641 "sparql_p.c" /* yacc.c:1646 */
break;
case 798:
#line 3231 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)uname_rdf_ns_uri_type; }
#line 8647 "sparql_p.c" /* yacc.c:1646 */
break;
case 800:
#line 3236 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = NULL; }
#line 8653 "sparql_p.c" /* yacc.c:1646 */
break;
case 801:
#line 3240 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = (SPART *)(yyvsp[0].box); }
#line 8659 "sparql_p.c" /* yacc.c:1646 */
break;
case 804:
#line 3244 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_qm_value (sparp_arg, (yyvsp[-3].box), (SPART **)t_revlist_to_array ((yyvsp[-1].backstack))); }
#line 8666 "sparql_p.c" /* yacc.c:1646 */
break;
case 805:
#line 3246 "sparql_p.y" /* yacc.c:1646 */
{ /*... | QmSqlCol */
(yyval.tree) = spar_make_qm_value (sparp_arg, box_dv_uname_string ("literal"), (SPART **)t_list (1, (yyvsp[0].tree))); }
#line 8673 "sparql_p.c" /* yacc.c:1646 */
break;
case 806:
#line 3251 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 8679 "sparql_p.c" /* yacc.c:1646 */
break;
case 808:
#line 3256 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].box)); }
#line 8685 "sparql_p.c" /* yacc.c:1646 */
break;
case 809:
#line 3257 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-1].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].box)); }
#line 8691 "sparql_p.c" /* yacc.c:1646 */
break;
case 810:
#line 3261 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = (yyvsp[0].box); }
#line 8697 "sparql_p.c" /* yacc.c:1646 */
break;
case 811:
#line 3262 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = (yyvsp[0].box); }
#line 8703 "sparql_p.c" /* yacc.c:1646 */
break;
case 812:
#line 3266 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = (yyvsp[0].box); }
#line 8709 "sparql_p.c" /* yacc.c:1646 */
break;
case 813:
#line 3267 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = (yyvsp[0].box); }
#line 8715 "sparql_p.c" /* yacc.c:1646 */
break;
case 814:
#line 3271 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (0); }
#line 8721 "sparql_p.c" /* yacc.c:1646 */
break;
case 815:
#line 3272 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (0); }
#line 8727 "sparql_p.c" /* yacc.c:1646 */
break;
case 816:
#line 3273 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_revlist_to_array ((yyvsp[-1].backstack)); }
#line 8733 "sparql_p.c" /* yacc.c:1646 */
break;
case 817:
#line 3277 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = NULL;
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[0]);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[1]); }
#line 8742 "sparql_p.c" /* yacc.c:1646 */
break;
case 818:
#line 3281 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.backstack) = (yyvsp[-2].backstack);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[0]);
t_set_push (&((yyval.backstack)), (yyvsp[0].trees)[1]); }
#line 8751 "sparql_p.c" /* yacc.c:1646 */
break;
case 819:
#line 3288 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("SOFT_EXCLUSIVE"), (ptrlong)1); }
#line 8757 "sparql_p.c" /* yacc.c:1646 */
break;
case 820:
#line 3289 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("EXCLUSIVE"), (ptrlong)1); }
#line 8763 "sparql_p.c" /* yacc.c:1646 */
break;
case 821:
#line 3290 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("ORDER"), (yyvsp[0].box)); }
#line 8769 "sparql_p.c" /* yacc.c:1646 */
break;
case 822:
#line 3291 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.trees) = (SPART **)t_list (2, t_box_dv_uname_string ("USING"), (yyvsp[0].box)); }
#line 8775 "sparql_p.c" /* yacc.c:1646 */
break;
case 823:
#line 3295 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 8781 "sparql_p.c" /* yacc.c:1646 */
break;
case 825:
#line 3300 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 8787 "sparql_p.c" /* yacc.c:1646 */
break;
case 826:
#line 3301 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 8793 "sparql_p.c" /* yacc.c:1646 */
break;
case 827:
#line 3305 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 8799 "sparql_p.c" /* yacc.c:1646 */
break;
case 828:
#line 3306 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 8805 "sparql_p.c" /* yacc.c:1646 */
break;
case 829:
#line 3310 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_vector_qm_sql (sparp_arg,
(SPART **)t_list (4, (yyvsp[-3].box), (yyvsp[-2].tree), (yyvsp[0].boxes)[0], (yyvsp[0].boxes)[1]) ); }
#line 8813 "sparql_p.c" /* yacc.c:1646 */
break;
case 830:
#line 3316 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = spar_make_vector_qm_sql (sparp_arg, (SPART **)t_revlist_to_array ((yyvsp[-1].backstack))); }
#line 8819 "sparql_p.c" /* yacc.c:1646 */
break;
case 831:
#line 3320 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; }
#line 8825 "sparql_p.c" /* yacc.c:1646 */
break;
case 833:
#line 3325 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = NULL; t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 8831 "sparql_p.c" /* yacc.c:1646 */
break;
case 834:
#line 3326 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.backstack) = (yyvsp[-2].backstack); t_set_push (&((yyval.backstack)), (yyvsp[0].tree)); }
#line 8837 "sparql_p.c" /* yacc.c:1646 */
break;
case 835:
#line 3330 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.tree) = spar_make_vector_qm_sql (sparp_arg,
(SPART **)t_list (4, (yyvsp[-2].box), (yyvsp[-1].box), (yyvsp[0].boxes)[0], (yyvsp[0].boxes)[1]) ); }
#line 8845 "sparql_p.c" /* yacc.c:1646 */
break;
case 836:
#line 3336 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.boxes) = t_list (2, (yyvsp[0].box), (ptrlong)0); }
#line 8851 "sparql_p.c" /* yacc.c:1646 */
break;
case 837:
#line 3337 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.boxes) = t_list (2, t_box_sprintf (300, "%.100s %.100s", (yyvsp[-1].box), (yyvsp[0].box)), (ptrlong)0); }
#line 8857 "sparql_p.c" /* yacc.c:1646 */
break;
case 838:
#line 3338 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.boxes) = t_list (2, (yyvsp[-1].box), (ptrlong)1); }
#line 8863 "sparql_p.c" /* yacc.c:1646 */
break;
case 839:
#line 3339 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.boxes) = t_list (2, t_box_sprintf (300, "%.100s %.100s", (yyvsp[-2].box), (yyvsp[-1].box)), (ptrlong)1); }
#line 8869 "sparql_p.c" /* yacc.c:1646 */
break;
case 840:
#line 3343 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = t_box_dv_uname_string ("in"); }
#line 8875 "sparql_p.c" /* yacc.c:1646 */
break;
case 841:
#line 3344 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = t_box_dv_uname_string ((yyvsp[0].box)); }
#line 8881 "sparql_p.c" /* yacc.c:1646 */
break;
case 842:
#line 3348 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_qm_sqlcol (sparp_arg, SPARQL_PLAIN_ID, (yyvsp[0].box)); }
#line 8887 "sparql_p.c" /* yacc.c:1646 */
break;
case 843:
#line 3349 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_qm_sqlcol (sparp_arg, SPARQL_SQL_ALIASCOLNAME, (yyvsp[0].box)); }
#line 8893 "sparql_p.c" /* yacc.c:1646 */
break;
case 844:
#line 3350 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.tree) = sparp_make_qm_sqlcol (sparp_arg, SPARQL_SQL_QTABLECOLNAME, (yyvsp[0].box)); }
#line 8899 "sparql_p.c" /* yacc.c:1646 */
break;
case 846:
#line 3355 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = t_box_dv_short_string ("GEO"); }
#line 8905 "sparql_p.c" /* yacc.c:1646 */
break;
case 847:
#line 3356 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = t_box_dv_short_string ("PRECISION"); }
#line 8911 "sparql_p.c" /* yacc.c:1646 */
break;
case 848:
#line 3357 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = t_box_dv_short_string ("TEXT"); }
#line 8917 "sparql_p.c" /* yacc.c:1646 */
break;
case 849:
#line 3358 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = t_box_dv_short_string ("XML"); }
#line 8923 "sparql_p.c" /* yacc.c:1646 */
break;
case 850:
#line 3363 "sparql_p.y" /* yacc.c:1646 */
{ (yyval.box) = (yyvsp[0].tree)->_.lit.val; }
#line 8929 "sparql_p.c" /* yacc.c:1646 */
break;
case 851:
#line 3364 "sparql_p.y" /* yacc.c:1646 */
{
(yyval.box) = spar_make_iri_from_template (sparp_arg, (yyvsp[-1].box)); }
#line 8936 "sparql_p.c" /* yacc.c:1646 */
break;
case 852:
#line 3369 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8942 "sparql_p.c" /* yacc.c:1646 */
break;
case 853:
#line 3370 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8948 "sparql_p.c" /* yacc.c:1646 */
break;
case 854:
#line 3374 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8954 "sparql_p.c" /* yacc.c:1646 */
break;
case 855:
#line 3375 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8960 "sparql_p.c" /* yacc.c:1646 */
break;
case 856:
#line 3379 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8966 "sparql_p.c" /* yacc.c:1646 */
break;
case 857:
#line 3380 "sparql_p.y" /* yacc.c:1646 */
{}
#line 8972 "sparql_p.c" /* yacc.c:1646 */
break;
#line 8976 "sparql_p.c" /* yacc.c:1646 */
default: break;
}
/* User semantic actions sometimes alter yychar, and that requires
that yytoken be updated with the new translation. We take the
approach of translating immediately before every use of yytoken.
One alternative is translating here after every semantic action,
but that translation would be missed if the semantic action invokes
YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an
incorrect destructor might then be invoked immediately. In the
case of YYERROR or YYBACKUP, subsequent parser actions might lead
to an incorrect destructor call or verbose syntax error message
before the lookahead is translated. */
YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
YYPOPSTACK (yylen);
yylen = 0;
YY_STACK_PRINT (yyss, yyssp);
*++yyvsp = yyval;
/* Now 'shift' the result of the reduction. Determine what state
that goes to, based on the state we popped back to and the rule
number reduced by. */
yyn = yyr1[yyn];
yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
yystate = yytable[yystate];
else
yystate = yydefgoto[yyn - YYNTOKENS];
goto yynewstate;
/*--------------------------------------.
| yyerrlab -- here on detecting error. |
`--------------------------------------*/
yyerrlab:
/* Make sure we have latest lookahead translation. See comments at
user semantic actions for why this is necessary. */
yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
/* If not already recovering from an error, report this error. */
if (!yyerrstatus)
{
++yynerrs;
#if ! YYERROR_VERBOSE
yyerror (sparp_arg, YY_("syntax error"));
#else
# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
yyssp, yytoken)
{
char const *yymsgp = YY_("syntax error");
int yysyntax_error_status;
yysyntax_error_status = YYSYNTAX_ERROR;
if (yysyntax_error_status == 0)
yymsgp = yymsg;
else if (yysyntax_error_status == 1)
{
if (yymsg != yymsgbuf)
YYSTACK_FREE (yymsg);
yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
if (!yymsg)
{
yymsg = yymsgbuf;
yymsg_alloc = sizeof yymsgbuf;
yysyntax_error_status = 2;
}
else
{
yysyntax_error_status = YYSYNTAX_ERROR;
yymsgp = yymsg;
}
}
yyerror (sparp_arg, yymsgp);
if (yysyntax_error_status == 2)
goto yyexhaustedlab;
}
# undef YYSYNTAX_ERROR
#endif
}
if (yyerrstatus == 3)
{
/* If just tried and failed to reuse lookahead token after an
error, discard it. */
if (yychar <= YYEOF)
{
/* Return failure if at end of input. */
if (yychar == YYEOF)
YYABORT;
}
else
{
yydestruct ("Error: discarding",
yytoken, &yylval, sparp_arg);
yychar = YYEMPTY;
}
}
/* Else will try to reuse lookahead token after shifting the error
token. */
goto yyerrlab1;
/*---------------------------------------------------.
| yyerrorlab -- error raised explicitly by YYERROR. |
`---------------------------------------------------*/
yyerrorlab:
/* Pacify compilers like GCC when the user code never invokes
YYERROR and the label yyerrorlab therefore never appears in user
code. */
if (/*CONSTCOND*/ 0)
goto yyerrorlab;
/* Do not reclaim the symbols of the rule whose action triggered
this YYERROR. */
YYPOPSTACK (yylen);
yylen = 0;
YY_STACK_PRINT (yyss, yyssp);
yystate = *yyssp;
goto yyerrlab1;
/*-------------------------------------------------------------.
| yyerrlab1 -- common code for both syntax error and YYERROR. |
`-------------------------------------------------------------*/
yyerrlab1:
yyerrstatus = 3; /* Each real token shifted decrements this. */
for (;;)
{
yyn = yypact[yystate];
if (!yypact_value_is_default (yyn))
{
yyn += YYTERROR;
if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
{
yyn = yytable[yyn];
if (0 < yyn)
break;
}
}
/* Pop the current state because it cannot handle the error token. */
if (yyssp == yyss)
YYABORT;
yydestruct ("Error: popping",
yystos[yystate], yyvsp, sparp_arg);
YYPOPSTACK (1);
yystate = *yyssp;
YY_STACK_PRINT (yyss, yyssp);
}
YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
*++yyvsp = yylval;
YY_IGNORE_MAYBE_UNINITIALIZED_END
/* Shift the error token. */
YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
yystate = yyn;
goto yynewstate;
/*-------------------------------------.
| yyacceptlab -- YYACCEPT comes here. |
`-------------------------------------*/
yyacceptlab:
yyresult = 0;
goto yyreturn;
/*-----------------------------------.
| yyabortlab -- YYABORT comes here. |
`-----------------------------------*/
yyabortlab:
yyresult = 1;
goto yyreturn;
#if !defined yyoverflow || YYERROR_VERBOSE
/*-------------------------------------------------.
| yyexhaustedlab -- memory exhaustion comes here. |
`-------------------------------------------------*/
yyexhaustedlab:
yyerror (sparp_arg, YY_("memory exhausted"));
yyresult = 2;
/* Fall through. */
#endif
yyreturn:
if (yychar != YYEMPTY)
{
/* Make sure we have latest lookahead translation. See comments at
user semantic actions for why this is necessary. */
yytoken = YYTRANSLATE (yychar);
yydestruct ("Cleanup: discarding lookahead",
yytoken, &yylval, sparp_arg);
}
/* Do not reclaim the symbols of the rule whose action triggered
this YYABORT or YYACCEPT. */
YYPOPSTACK (yylen);
YY_STACK_PRINT (yyss, yyssp);
while (yyssp != yyss)
{
yydestruct ("Cleanup: popping",
yystos[*yyssp], yyvsp, sparp_arg);
YYPOPSTACK (1);
}
#ifndef yyoverflow
if (yyss != yyssa)
YYSTACK_FREE (yyss);
#endif
#if YYERROR_VERBOSE
if (yymsg != yymsgbuf)
YYSTACK_FREE (yymsg);
#endif
return yyresult;
}
|
susundberg/python-median-filter-2d
|
src/filter_cwrap.h
|
<reponame>susundberg/python-median-filter-2d<filename>src/filter_cwrap.h
#pragma once
#include <stdint.h>
extern "C"
{
int median_filter_2d_float64(int x, int y, int hx, int hy, int blockhint, const double* in, double* out);
int median_filter_2d_float32(int x, int y, int hx, int hy, int blockhint, const float* in, float* out);
int median_filter_2d_uint16(int x, int y, int hx, int hy, int blockhint, const uint16_t* in, uint16_t* out);
}
|
susundberg/python-median-filter-2d
|
src/filter.h
|
<filename>src/filter.h<gh_stars>1-10
#ifndef FILTER_H
#define FILTER_H
// T: float or double.
// x, y: image dimensions, width x pixels and height y pixels.
// hx, hy: window radius in x and y directions.
// blockhint: preferred block size, 0 = pick automatically.
// in: input image.
// out: output image.
//
// Total window size will be (2*hx+1) * (2*hy+1) pixels.
//
// Pixel (i,j) for 0 <= i < x and 0 <= j < y is located at
// in[j*x + i] and out[j*x + i].
template <typename T>
void median_filter_2d(int x, int y, int hx, int hy, int blockhint, const T* in, T* out);
// As above, for the special case y = 1, hy = 0.
template <typename T>
void median_filter_1d(int x, int hx, int blockhint, const T* in, T* out);
#endif
|
kschetan25/project_3_csim
|
main_prog.c
|
#include "csim.h"
#include <stdio.h>
#define DATABASE 1000L
#define CLIENTS 10L
#define SERVERS 1L
#define NODES 11L
#define SIMTIME 100.0
typedef struct msg *msg_t;
struct data_tuple
{
long data_id;
double data_ts;
};
struct msg
{
struct data_tuple bcastData[DATABASE];
double timestamp;
long data_id;
msg_t link;
};
struct s_node
{
double data_items[DATABASE]; //server database
long bcast_data[DATABASE]; //Lbcast
} server;
msg_t msg_queue;
struct nde
{
MBOX mailbox;
};
struct nde node[NODES];
void init();
void serverProc();
void clientProc();
void updateDB();
void rcv_cl_qry();
void bcastIR();
void send_qry();
// void rcv_sv_IR();
msg_t build_msg();
void send_msg();
void sending_message();
msg_t new_msg();
long msg_cnt(MBOX m);
void sim()
{
// create("sim");
init();
// hold(SIMTIME);
}
void init()
{
long i, j;
char str[24];
max_servers(SERVERS * SERVERS + SERVERS);
max_mailboxes(NODES * NODES + NODES);
max_events(2 * NODES * NODES);
msg_queue = NIL;
for (i = 0; i < NODES; i++)
{
sprintf(str, "mailbox.%d", i);
node[i].mailbox = mailbox(str);
}
serverProc();
// clientProc();
}
void serverProc()
{
updateDB();
rcv_cl_qry();
bcastIR();
}
void updateDB()
{
double rand;
long udata;
//create("updateProcess");
//hold(50.0);
while (clock < SIMTIME)
{
rand = random(0, 1);
udata = (rand < 0.33) ? uniform(1, 50) : uniform(51, 1000);
{
server.data_items[udata] = clock;
server.bcast_data[udata] = udata;
}
hold(2.0);
}
}
void rcv_cl_qry()
{
long cnt;
long i;
long clData[DATABASE];
msg_t cl_msg;
cl_msg = build_msg(1);
send(node[CLIENTS].mailbox, (long)cl_msg);
status_mailboxes();
cnt = msg_cnt(node[CLIENTS].mailbox);
if (cnt > 0)
{
for (i = 0; i < cnt; i++)
{
receive(node[CLIENTS].mailbox, (long *)&cl_msg);
server.bcast_data[cl_msg->data_id] = clData[cl_msg->data_id] = cl_msg->data_id;
}
}
}
void bcastIR()
{
printf("\n found here---------------------- \n");
long i;
msg_t irData;
irData = build_msg(0);
irData->timestamp = clock;
for (i = 0; i < CLIENTS; i++)
{
send(node[i].mailbox, (long)irData);
}
status_mailboxes();
}
void send_qry()
{
}
msg_t build_msg(n) long n;
{
msg_t mes;
long i;
if (msg_queue == NIL)
{
mes = (msg_t)do_malloc(sizeof(struct msg));
}
else
{
mes = msg_queue;
msg_queue = msg_queue->link;
}
if (n < 1)
{
for (i = 0; i < DATABASE; i++)
{
mes->bcastData[i].data_id = server.bcast_data[i];
mes->bcastData[i].data_ts = server.data_items[i];
}
}
else
{
mes->data_id = 2;
}
return mes;
}
|
kschetan25/project_3_csim
|
proj_3.c
|
#include "csim.h"
#include <stdio.h>
#define MAX_SIZE 1000
#define MAX_DATABASE 1000L
#define BCAST_INTERVAL 20.0
#define NUM_CLIENTS 10L
#define NUM_SERVERS 1L
#define TRANS_TIME 0.8
#define TOTAL_NODES 101L
#define CACHE_SIZE 100L
#define REQUEST 1L
#define REPLY 2L
typedef struct msg *msg_t;
struct msg
{
} msg_t msg_queue;
struct cdata
{
int valid_bit; //cache valid bit
int data_item_id; //cache data item
double last_updated; //cache last updated time of data item
double last_accessed; //cache last accessed time of data item
};
struct s_node
{
double data_items[MAX_SIZE]; //server database
int data_id; //req data items
int data_tstamp; //timestamp
double bcast_data[MAX_SIZE]; //Lbcast
} server;
struct c_node
{
double data_items[MAX_SIZE];
struct cdata cache[MAX_SIZE];
double last_interval_timestamp;
} client;
struct nde
{
MBOX input;
};
double bcast[MAX_SIZE];
struct nde node[TOTAL_NODES];
struct cdata cache[10];
double simt = 0.0;
double mean_update_time = 0.0;
void getSimTime();
void serverProcess();
void init();
void broadcastIR();
void buildIR();
void updateDataItems();
msg_t new_msg();
void sim()
{
//create("sim");
getSimTime();
printf("\n ----------------------- %lf", simt);
init();
//hold(simt);
}
void init()
{
long i;
char str[24];
max_servers(NUM_SERVERS * NUM_SERVERS + NUM_SERVERS);
max_mailboxes(TOTAL_NODES);
max_events(2 * TOTAL_NODES * TOTAL_NODES);
max_mailboxes(TOTAL_NODES);
msg_queue = NIL;
for (i = 0; i < TOTAL_NODES; i++)
{
sprintf(str, "input.%d", i);
node[i].input = mailbox(str);
}
serverProcess();
// clientProcess();
}
void getSimTime()
{
printf("\n Enter Mean arrival update time(25 to 300): ");
scanf("%lf", &mean_update_time);
simt = CACHE_SIZE * mean_update_time * 10;
printf("====== The aim time ia %lf", simt);
}
void serverProcess()
{
//create("server proc");
while (clock < simt)
{
// broadcastIR();
updateDataItems();
// listenClient();
}
}
void broadcastIR()
{
int bcast[MAX_SIZE] = 0.0;
//create("broadcastProcess");
while (clock < simt)
{
buildIR();
//hold(20.0);
}
}
void buildIR()
{
}
void updateDataItems()
{
long ran;
long uni;
//create("updateProcess");
//hold(50.0);
while (clock < simt)
{
ran = random(0, 1000);
if (ran < 0.33)
{
uni = uniform(1, 50);
server.data_items[uni] = clock;
server.bcast_data[uni] = uni;
}
}
}
void listenClient(items)
long items;
{
}
// msg_t new_msg(from) long from;
// {
// msg_t m;
// long i;
// if (msg_queue == NIL)
// {
// m = (msg_t)do_malloc(sizeof(struct msg));
// }
// else
// {
// m = msg_queue;
// msg_queue = msg_queue->link;
// }
// do
// {
// i = random(0l, NUM_NODES - 1);
// } while (i == from);
// m->to = i;
// m->tag = 0;
// m->from = from;
// m->type = REQUEST;
// m->start_time = clock;
// return (m);
// }
// void return_msg(m)
// msg_t m;
// {
// m->link = msg_queue;
// msg_queue = m;
// }
|
prophecy/Pillar
|
Dependencies/Include/Rocket/Core/Context.h
|
<filename>Dependencies/Include/Rocket/Core/Context.h
/*
* This source file is part of libRocket, the HTML/CSS Interface Middleware
*
* For the latest information, see http://www.librocket.com
*
* Copyright (c) 2008-2010 CodePoint Ltd, Shift Technology Ltd
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
#ifndef ROCKETCORECONTEXT_H
#define ROCKETCORECONTEXT_H
#include "Header.h"
#include "Types.h"
#include "ReferenceCountable.h"
#include "ElementReference.h"
#include "Input.h"
#include "String.h"
#include "ScriptInterface.h"
namespace Rocket {
namespace Core {
class Stream;
class Dictionary;
}
}
namespace Rocket {
namespace Core {
class ContextInstancer;
class ElementDocument;
class EventListener;
class RenderInterface;
/**
A context for storing, rendering and processing RML documents. Multiple contexts can exist simultaneously.
@author <NAME>
*/
class ROCKETCORE_API Context : public ScriptInterface
{
public:
/// Constructs a new, uninitialised context. This should not be called directly, use Core::CreateContext()
/// instead.
/// @param[in] name The name of the context.
Context(const String& name);
/// Destroys a context.
virtual ~Context();
/// Returns the name of the context.
/// @return The context's name.
const String& GetName() const;
/// Changes the dimensions of the context.
/// @param[in] dimensions The new dimensions of the context.
void SetDimensions(const Vector2i& dimensions);
/// Returns the dimensions of the context.
/// @return The current dimensions of the context.
const Vector2i& GetDimensions() const;
/// Updates all elements in the context's documents.
bool Update();
/// Renders all visible elements in the context's documents.
bool Render();
/// Creates a new, empty document and places it into this context.
/// @param[in] tag The document type to create.
/// @return The new document, or NULL if no document could be created. The document is returned with a reference owned by the caller.
ElementDocument* CreateDocument(const String& tag = "body");
/// Load a document into the context.
/// @param[in] document_path The path to the document to load.
/// @return The loaded document, or NULL if no document was loaded. The document is returned with a reference owned by the caller.
ElementDocument* LoadDocument(const String& document_path);
/// Load a document into the context.
/// @param[in] document_stream The opened stream, ready to read.
/// @return The loaded document, or NULL if no document was loaded. The document is returned with a reference owned by the caller.
ElementDocument* LoadDocument(Stream* document_stream);
/// Load a document into the context.
/// @param[in] string The string containing the document RML.
/// @return The loaded document, or NULL if no document was loaded. The document is returned with a reference owned by the caller.
ElementDocument* LoadDocumentFromMemory(const String& string);
/// Unload the given document.
/// @param[in] document The document to unload.
void UnloadDocument(ElementDocument* document);
/// Unloads all loaded documents.
void UnloadAllDocuments();
/// Adds a previously-loaded cursor document as a mouse cursor within this context. This allows you to share
/// cursors between contexts.
/// @param[in] cursor_document The document to add as a cursor into this context.
void AddMouseCursor(ElementDocument* cursor_document);
/// Loads a document as a mouse cursor within this context.
/// @param[in] cursor_document_path The path to the document to load as a cursor.
/// @return The loaded cursor document, or NULL if no document was loaded. The document is returned with a reference owned by the caller.
ElementDocument* LoadMouseCursor(const String& cursor_document_path);
/// Unload the given cursor.
/// @param[in] cursor_name The name of cursor to unload.
void UnloadMouseCursor(const String& cursor_name);
/// Unloads all currently loaded cursors.
void UnloadAllMouseCursors();
/// Sets a cursor as the active cursor.
/// @param[in] cursor_name The name of the cursor to activate.
/// @return True if a cursor exists with the given name, false if not.
bool SetMouseCursor(const String& cursor_name);
/// Shows or hides the cursor.
/// @param[in] show True to show the cursor, false to hide it.
void ShowMouseCursor(bool show);
/// Returns the first document in the context with the given id.
/// @param[in] id The id of the desired document.
/// @return The document (if it was found), or NULL if no document exists with the ID. The document is returned with a borrowed reference.
ElementDocument* GetDocument(const String& id);
/// Returns a document in the context by index.
/// @param[in] index The index of the desired document.
/// @return The document (if one exists with this index), or NULL if the index was invalid. The document is returned with a borrowed reference.
ElementDocument* GetDocument(int index);
/// Returns the number of documents in the context.
/// @return The number of documents in the context.
int GetNumDocuments() const;
/// Returns the hover element.
/// @return The element the mouse cursor is hovering over. The element is returned with a borrowed reference.
Element* GetHoverElement();
/// Returns the focus element.
/// @return The element with input focus. The element is returned with a borrowed reference.
Element* GetFocusElement();
/// Returns the root element that holds all the documents
/// @return The root element. The element is returned with a borrowed reference.
Element* GetRootElement();
/// Brings the document to the front of the document stack.
/// @param[in] document The document to pull to the front of the stack.
void PullDocumentToFront(ElementDocument* document);
/// Sends the document to the back of the document stack.
/// @param[in] document The document to push to the bottom of the stack.
void PushDocumentToBack(ElementDocument* document);
/// Adds an event listener to the context's root element.
/// @param[in] event The name of the event to attach to.
/// @param[in] listener Listener object to be attached.
/// @param[in] in_capture_phase True if the listener is to be attached to the capture phase, false for the bubble phase.
void AddEventListener(const String& event, EventListener* listener, bool in_capture_phase = false);
/// Removes an event listener from the context's root element.
/// @param[in] event The name of the event to detach from.
/// @param[in] listener Listener object to be detached.
/// @param[in] in_capture_phase True to detach from the capture phase, false from the bubble phase.
void RemoveEventListener(const String& event, EventListener* listener, bool in_capture_phase = false);
/// Sends a key down event into this context.
/// @param[in] key_identifier The key pressed.
/// @param[in] key_modifier_state The state of key modifiers (shift, control, caps-lock, etc) keys; this should be generated by ORing together members of the Input::KeyModifier enumeration.
/// @return True if the event was not consumed (ie, was prevented from propagating by an element), false if it was.
bool ProcessKeyDown(Input::KeyIdentifier key_identifier, int key_modifier_state);
/// Sends a key up event into this context.
/// @param[in] key_identifier The key released.
/// @param[in] key_modifier_state The state of key modifiers (shift, control, caps-lock, etc) keys; this should be generated by ORing together members of the Input::KeyModifier enumeration.
/// @return True if the event was not consumed (ie, was prevented from propagating by an element), false if it was.
bool ProcessKeyUp(Input::KeyIdentifier key_identifier, int key_modifier_state);
/// Sends a single character of text as text input into this context.
/// @param[in] character The UCS-2 character to send into this context.
/// @return True if the event was not consumed (ie, was prevented from propagating by an element), false if it was.
bool ProcessTextInput(word character);
/// Sends a string of text as text input into this context.
/// @param[in] string The UCS-2 string to send into this context.
/// @return True if the event was not consumed (ie, was prevented from propagating by an element), false if it was.
bool ProcessTextInput(const String& string);
/// Sends a mouse movement event into this context.
/// @param[in] x The x-coordinate of the mouse cursor, in window-coordinates (ie, 0 should be the left of the client area).
/// @param[in] y The y-coordinate of the mouse cursor, in window-coordinates (ie, 0 should be the top of the client area).
/// @param[in] key_modifier_state The state of key modifiers (shift, control, caps-lock, etc) keys; this should be generated by ORing together members of the Input::KeyModifier enumeration.
void ProcessMouseMove(int x, int y, int key_modifier_state);
/// Sends a mouse-button down event into this context.
/// @param[in] button_index The index of the button that was pressed; 0 for the left button, 1 for right, and any others from 2 onwards.
/// @param[in] key_modifier_state The state of key modifiers (shift, control, caps-lock, etc) keys; this should be generated by ORing together members of the Input::KeyModifier enumeration.
void ProcessMouseButtonDown(int button_index, int key_modifier_state);
/// Sends a mouse-button up event into this context.
/// @param[in] button_index The index of the button that was release; 0 for the left button, 1 for right, and any others from 2 onwards.
/// @param[in] key_modifier_state The state of key modifiers (shift, control, caps-lock, etc) keys; this should be generated by ORing together members of the Input::KeyModifier enumeration.
void ProcessMouseButtonUp(int button_index, int key_modifier_state);
/// Sends a mouse-wheel movement event into this context.
/// @param[in] wheel_delta The mouse-wheel movement this frame. Rocket treats a negative delta as up movement (away from the user), positive as down.
/// @param[in] key_modifier_state The state of key modifiers (shift, control, caps-lock, etc) keys; this should be generated by ORing together members of the Input::KeyModifier enumeration.
/// @return True if the event was not consumed (ie, was prevented from propagating by an element), false if it was.
bool ProcessMouseWheel(int wheel_delta, int key_modifier_state);
/// Gets the context's render interface.
/// @return The render interface the context renders through.
RenderInterface* GetRenderInterface() const;
/// Gets the current clipping region for the render traversal
/// @param[out] origin The clipping origin
/// @param[out] dimensions The clipping dimensions
bool GetActiveClipRegion(Vector2i& origin, Vector2i& dimensions) const;
/// Sets the current clipping region for the render traversal
/// @param[out] origin The clipping origin
/// @param[out] dimensions The clipping dimensions
void SetActiveClipRegion(const Vector2i& origin, const Vector2i& dimensions);
/// Sets the instancer to use for releasing this object.
/// @param[in] instancer The context's instancer.
void SetInstancer(ContextInstancer* instancer);
protected:
virtual void OnReferenceDeactivate();
private:
String name;
Vector2i dimensions;
ContextInstancer* instancer;
typedef std::set< ElementReference > ElementSet;
typedef std::vector< ElementReference > ElementList;
// Set of elements that are currently in hover state.
ElementSet hover_chain;
// List of elements that are currently in active state.
ElementList active_chain;
// History of windows that have had focus
ElementList document_focus_history;
// Documents that have been unloaded from the context but not yet released.
ElementList unloaded_documents;
// Root of the element tree.
Element* root;
// The element that current has input focus.
ElementReference focus;
// The top-most element being hovered over.
ElementReference hover;
// The element that was being hovered over when the primary mouse button was pressed most recently.
ElementReference active;
// The element that was clicked on last.
Element* last_click_element;
// The time the last click occured.
float last_click_time;
typedef std::map< String, ElementDocument* > CursorMap;
CursorMap cursors;
ElementReference default_cursor;
ElementReference active_cursor;
bool show_cursor;
ElementDocument* cursor_proxy;
// The element that is currently being dragged (or about to be dragged).
ElementReference drag;
// True if a drag has begun (ie, the ondragstart event has been fired for the drag element), false otherwise.
bool drag_started;
// True if the current drag is a verbose drag (ie, sends ondragover, ondragout, ondragdrop, etc, events).
bool drag_verbose;
// Used when dragging a cloned object.
Element* drag_clone;
// The element currently being dragged over; this is equivalent to hover, but only set while an element is being
// dragged, and excludes the dragged element.
ElementReference drag_hover;
// Set of elements that are currently being dragged over; this differs from the hover state as the dragged element
// itself can't be part of it.
ElementSet drag_hover_chain;
// Input state; stored from the most recent input events we receive from the application.
Vector2i mouse_position;
// The render interface this context renders through.
RenderInterface* render_interface;
Vector2i clip_origin;
Vector2i clip_dimensions;
// Internal callback for when an element is removed from the hierarchy.
void OnElementRemove(Element* element);
// Internal callback for when a new element gains focus.
bool OnFocusChange(Element* element);
// Generates an event for faking clicks on an element.
void GenerateClickEvent(Element* element);
// Updates the current hover elements, sending required events.
void UpdateHoverChain(const Dictionary& parameters, const Dictionary& drag_parameters, const Vector2i& old_mouse_position);
// Returns the youngest descendent of the given element which is under the given point in screen coordinates.
// @param[in] point The point to test.
// @param[in] ignore_element If set, this element and its descendents will be ignored.
// @param[in] element Used internally.
// @return The element under the point, or NULL if nothing is.
Element* GetElementAtPoint(const Vector2f& point, const Element* ignore_element = NULL, Element* element = NULL);
// Creates the drag clone from the given element. The old drag clone will be released if
// necessary.
// @param[in] element The element to clone.
void CreateDragClone(Element* element);
// Releases the drag clone, if one exists.
void ReleaseDragClone();
// Builds the parameters for a generic key event.
void GenerateKeyEventParameters(Dictionary& parameters, Input::KeyIdentifier key_identifier);
// Builds the parameters for a generic mouse event.
void GenerateMouseEventParameters(Dictionary& parameters, int button_index = -1);
// Builds the parameters for the key modifier state.
void GenerateKeyModifierEventParameters(Dictionary& parameters, int key_modifier_state);
// Builds the parameters for a drag event.
void GenerateDragEventParameters(Dictionary& parameters);
// Releases all unloaded documents pending destruction.
void ReleaseUnloadedDocuments();
// Sends the specified event to all elements in new_items that don't appear in old_items.
static void SendEvents(const ElementSet& old_items, const ElementSet& new_items, const String& event, const Dictionary& parameters, bool interruptible);
friend class Element;
friend ROCKETCORE_API Context* CreateContext(const String&, const Vector2i&, RenderInterface*);
};
}
}
#endif
|
prophecy/Pillar
|
Dependencies/Include/cml/vector/vector_unroller.h
|
<filename>Dependencies/Include/cml/vector/vector_unroller.h
/* -*- C++ -*- ------------------------------------------------------------
Copyright (c) 2007 <NAME> and <NAME> http://cmldev.net/
The Configurable Math Library (CML) is distributed under the terms of the
Boost Software License, v1.0 (see cml/LICENSE for details).
*-----------------------------------------------------------------------*/
/** @file
* @brief
*
* Defines vector unrollers.
*
* @todo Add unrolling for dynamic vectors, and for vectors longer than
* CML_VECTOR_UNROLL_LIMIT.
*
* @todo Does it make sense to unroll an assignment if either side of the
* assignment has a fixed size, or just when the target vector is fixed
* size?
*/
#ifndef vector_unroller_h
#define vector_unroller_h
#include <cml/et/traits.h>
#include <cml/et/size_checking.h>
#include <cml/et/scalar_ops.h>
#if !defined(CML_VECTOR_UNROLL_LIMIT)
#error "CML_VECTOR_UNROLL_LIMIT is undefined."
#endif
namespace cml {
namespace et {
namespace detail {
/** Unroll a binary assignment operator on a fixed-size vector.
*
* This uses forward iteration to make efficient use of the cache.
*
* @sa cml::vector
* @sa cml::et::OpAssign
*
* @bug Need to verify that OpT is actually an assignment operator.
*/
template<class OpT, typename E, class AT, class SrcT>
class VectorAssignmentUnroller
{
protected:
/* Forward declare: */
template<int N, int Last, bool can_unroll> struct Eval;
/* The vector type being assigned to: */
typedef cml::vector<E,AT> vector_type;
/* Record traits for the arguments: */
typedef ExprTraits<vector_type> dest_traits;
typedef ExprTraits<SrcT> src_traits;
/** Evaluate the binary operator for the first Len-1 elements. */
template<int N, int Last> struct Eval<N,Last,true> {
void operator()(vector_type& dest, const SrcT& src) const {
/* Apply to current N: */
OpT().apply(dest[N], src_traits().get(src,N));
/* Note: we don't need get(), since dest is a vector. */
/* Apply to N+1: */
Eval<N+1,Last,true>()(dest, src);
}
};
/** Evaluate the binary operator at element Last. */
template<int Last> struct Eval<Last,Last,true> {
void operator()(vector_type& dest, const SrcT& src) const {
/* Apply to last element: */
OpT().apply(dest[Last], src_traits().get(src,Last));
/* Note: we don't need get(), since dest is a vector. */
}
};
/** Evaluate the binary operator using a loop.
*
* This is used when the vector's length is longer than
* CML_VECTOR_UNROLL_LIMIT
*/
template<int N, int Last> struct Eval<N,Last,false> {
void operator()(vector_type& dest, const SrcT& src) const {
for(size_t i = 0; i <= Last; ++i) {
OpT().apply(dest[i], src_traits().get(src,i));
/* Note: we don't need get(), since dest is a vector. */
}
}
};
public:
/** Unroll assignment to a fixed-sized vector. */
void operator()(vector_type& dest, const SrcT& src, cml::fixed_size_tag)
{
typedef cml::vector<E,AT> vector_type;
enum { Len = vector_type::array_size };
typedef typename VectorAssignmentUnroller<OpT,E,AT,SrcT>::template
Eval<0, Len-1, (Len <= CML_VECTOR_UNROLL_LIMIT)> Unroller;
/* Note: Len is the array size, so Len-1 is the last element. */
/* Use a run-time check if src is a run-time sized expression: */
typedef typename ExprTraits<SrcT>::size_tag src_size;
typedef typename select_if<
same_type<src_size,dynamic_size_tag>::is_true,
dynamic_size_tag, fixed_size_tag>::result size_tag;
/* Check the expression size (the returned size isn't needed): */
CheckedSize(dest,src,size_tag());
/* Note: for two fixed-size expressions, the if-statements and
* comparisons should be completely eliminated as dead code. If src
* is a dynamic-sized expression, the check will still happen.
*/
/* Now, call the unroller: */
Unroller()(dest,src);
}
private:
/* XXX Blah, a temp. hack to fix the auto-resizing stuff below. */
size_t CheckOrResize(
vector_type& dest, const SrcT& src, cml::resizable_tag)
{
#if defined(CML_AUTOMATIC_VECTOR_RESIZE_ON_ASSIGNMENT)
/* Get the size of src. This also causes src to check its size: */
size_t N = std::max(dest.size(),src_traits().size(src));
/* Set the destination vector's size: */
cml::et::detail::Resize(dest,N);
#else
size_t N = CheckedSize(dest,src,dynamic_size_tag());
#endif
return N;
}
size_t CheckOrResize(
vector_type& dest, const SrcT& src, cml::not_resizable_tag)
{
return CheckedSize(dest,src,dynamic_size_tag());
}
/* XXX Blah, a temp. hack to fix the auto-resizing stuff below. */
public:
/** Just use a loop to assign to a runtime-sized vector. */
void operator()(vector_type& dest, const SrcT& src, cml::dynamic_size_tag)
{
/* Shorthand: */
typedef ExprTraits<SrcT> src_traits;
size_t N = this->CheckOrResize(
dest,src,typename vector_type::resizing_tag());
for(size_t i = 0; i < N; ++i) {
OpT().apply(dest[i], src_traits().get(src,i));
/* Note: we don't need get(), since dest is a vector. */
}
}
};
/** Unroll a vector accumulation/reduction operator.
*
* This uses forward iteration to make efficient use of the cache.
*/
template<class AccumT, class OpT, class LeftT, class RightT>
struct VectorAccumulateUnroller
{
/* Forward declare: */
template<int N, int Last, bool can_unroll> struct Eval;
/* Record traits for the arguments: */
typedef ExprTraits<LeftT> left_traits;
typedef ExprTraits<RightT> right_traits;
/* Figure out the return type: */
typedef typename AccumT::value_type result_type;
/** Evaluate for the first Len-1 elements. */
template<int N, int Last> struct Eval<N,Last,true> {
result_type operator()(
const LeftT& left, const RightT& right) const
{
/* Apply to last value: */
return AccumT().apply(
OpT().apply(left[N], right_traits().get(right,N)),
Eval<N+1,Last,true>()(left, right));
/* Note: we don't need get(), since dest is a vector. */
}
};
/** Evaluate the binary operator at element Last. */
template<int Last> struct Eval<Last,Last,true> {
result_type operator()(
const LeftT& left, const RightT& right) const
{
return OpT().apply(left[Last],right_traits().get(right,Last));
/* Note: we don't need get(), since dest is a vector. */
}
};
/** Evaluate using a loop. */
template<int N, int Last> struct Eval<N,Last,false> {
result_type operator()(
const LeftT& left, const RightT& right) const
{
result_type accum = OpT().apply(left[0],right[0]);
for(size_t i = 1; i <= Last; ++i) {
/* XXX This might not be optimized properly by some compilers,
* but to do anything else requires changing the requirements
* of a scalar operator.
*/
accum = AccumT().apply(accum, OpT().apply(
left[i],right_traits().get(right,i)));
/* Note: we don't need get(), since dest is a vector. */
}
}
};
};
}
/** Construct an assignment unroller.
*
* The operator must be an assignment op, otherwise, this doesn't make any
* sense.
*
* @bug Need to verify that OpT is actually an assignment operator.
*/
template<class OpT, class SrcT, typename E, class AT> inline
void UnrollAssignment(cml::vector<E,AT>& dest, const SrcT& src)
{
/* Record the destination vector type, and the expression traits: */
typedef cml::vector<E,AT> vector_type;
/* Record the type of the unroller: */
typedef detail::VectorAssignmentUnroller<OpT,E,AT,SrcT> unroller;
/* Do the unroll call: */
unroller()(dest, src, typename vector_type::size_tag());
/* XXX It may make sense to unroll if either side is a fixed size. */
}
} // namespace et
} // namespace cml
#endif
// -------------------------------------------------------------------------
// vim:ft=cpp
|
prophecy/Pillar
|
Src/Foundation/IInput.h
|
<filename>Src/Foundation/IInput.h
/*
* This source file is part of Wonderland, the C++ Cross-platform middleware for game
*
* For the latest information, see https://github.com/prophecy/Wonderland
*
* The MIT License (MIT)
* Copyright (c) 2015 <NAME>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
#ifndef __I_INPUT_H__
#define __I_INPUT_H__
#include "Utility/Utility.h"
class IInput
{
public:
enum TouchStatus
{
TouchStatusIdle = 0,
TouchStatusBegan,
TouchStatusMoved,
TouchStatusEnded,
};
struct Cursor
{
point2f position;
};
enum KeyState
{
KeystateNone = 0,
KeyStatePressed,
KeyStateReleased,
};
struct KeyField
{
KeyState spacebar;
KeyState a, s, d, w;
KeyField()
{
a = s = d = w =
spacebar = KeystateNone;
}
};
enum MouseButtonState
{
MouseButtonStateNone = 0,
MouseButtonStateDown,
MouseButtonStateUp,
};
struct MouseButtonField
{
MouseButtonState Left;
MouseButtonState Middle;
MouseButtonState Right;
MouseButtonField()
{
Left = Middle = Right = MouseButtonStateNone;
}
};
enum AppState
{
AppStateCreate = 1,
AppStateDestroy = 2,
AppStateStart = 4,
AppStateStop = 8,
AppStateResume = 16,
AppStatePause = 32,
};
struct AppStateField
{
u64 states;
AppStateField()
{
states = 0;
}
bool IsOnState(AppState state)
{
if ( states & state )
return true;
return false;
}
};
public:
// Polling functions
virtual void PollEventStart() = 0;
virtual void PollEventUpdate() = 0;
virtual void PollEventFinish() = 0;
// // Accelerometers
// virtual vector3f* GetAccelerometerValues() = 0;
// // Key
// virtual KeyField* GetKeyField() = 0;
// // Mouse
// virtual MouseButtonField* GetMouseButtonField() = 0;
// // Application state
// virtual AppStateField* GetAppStateField() = 0;
// // Touch
// virtual TouchStatus GetTouchStatus() = 0;
// virtual Cursor* GeCursor() = 0;
};
#endif // __I_INPUT_H__
|
prophecy/Pillar
|
Dependencies/Include/SDL_image/IMG_tif.c
|
<reponame>prophecy/Pillar<filename>Dependencies/Include/SDL_image/IMG_tif.c
/*
SDL_image: An example image loading library for use with SDL
Copyright (C) 1997-2013 <NAME> <<EMAIL>>
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. If you use this software
in a product, an acknowledgment in the product documentation would be
appreciated but is not required.
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
*/
#if !defined(__APPLE__) || defined(SDL_IMAGE_USE_COMMON_BACKEND)
/* This is a TIFF image file loading framework */
#include <stdio.h>
#include "SDL_image.h"
#ifdef LOAD_TIF
#include <tiffio.h>
static struct {
int loaded;
void *handle;
TIFF* (*TIFFClientOpen)(const char*, const char*, thandle_t, TIFFReadWriteProc, TIFFReadWriteProc, TIFFSeekProc, TIFFCloseProc, TIFFSizeProc, TIFFMapFileProc, TIFFUnmapFileProc);
void (*TIFFClose)(TIFF*);
int (*TIFFGetField)(TIFF*, ttag_t, ...);
int (*TIFFReadRGBAImage)(TIFF*, uint32, uint32, uint32*, int);
TIFFErrorHandler (*TIFFSetErrorHandler)(TIFFErrorHandler);
} lib;
#ifdef LOAD_TIF_DYNAMIC
int IMG_InitTIF()
{
if ( lib.loaded == 0 ) {
lib.handle = SDL_LoadObject(LOAD_TIF_DYNAMIC);
if ( lib.handle == NULL ) {
return -1;
}
lib.TIFFClientOpen =
(TIFF* (*)(const char*, const char*, thandle_t, TIFFReadWriteProc, TIFFReadWriteProc, TIFFSeekProc, TIFFCloseProc, TIFFSizeProc, TIFFMapFileProc, TIFFUnmapFileProc))
SDL_LoadFunction(lib.handle, "TIFFClientOpen");
if ( lib.TIFFClientOpen == NULL ) {
SDL_UnloadObject(lib.handle);
return -1;
}
lib.TIFFClose =
(void (*)(TIFF*))
SDL_LoadFunction(lib.handle, "TIFFClose");
if ( lib.TIFFClose == NULL ) {
SDL_UnloadObject(lib.handle);
return -1;
}
lib.TIFFGetField =
(int (*)(TIFF*, ttag_t, ...))
SDL_LoadFunction(lib.handle, "TIFFGetField");
if ( lib.TIFFGetField == NULL ) {
SDL_UnloadObject(lib.handle);
return -1;
}
lib.TIFFReadRGBAImage =
(int (*)(TIFF*, uint32, uint32, uint32*, int))
SDL_LoadFunction(lib.handle, "TIFFReadRGBAImage");
if ( lib.TIFFReadRGBAImage == NULL ) {
SDL_UnloadObject(lib.handle);
return -1;
}
lib.TIFFSetErrorHandler =
(TIFFErrorHandler (*)(TIFFErrorHandler))
SDL_LoadFunction(lib.handle, "TIFFSetErrorHandler");
if ( lib.TIFFSetErrorHandler == NULL ) {
SDL_UnloadObject(lib.handle);
return -1;
}
}
++lib.loaded;
return 0;
}
void IMG_QuitTIF()
{
if ( lib.loaded == 0 ) {
return;
}
if ( lib.loaded == 1 ) {
SDL_UnloadObject(lib.handle);
}
--lib.loaded;
}
#else
int IMG_InitTIF()
{
if ( lib.loaded == 0 ) {
lib.TIFFClientOpen = TIFFClientOpen;
lib.TIFFClose = TIFFClose;
lib.TIFFGetField = TIFFGetField;
lib.TIFFReadRGBAImage = TIFFReadRGBAImage;
lib.TIFFSetErrorHandler = TIFFSetErrorHandler;
}
++lib.loaded;
return 0;
}
void IMG_QuitTIF()
{
if ( lib.loaded == 0 ) {
return;
}
if ( lib.loaded == 1 ) {
}
--lib.loaded;
}
#endif /* LOAD_TIF_DYNAMIC */
/*
* These are the thunking routine to use the SDL_RWops* routines from
* libtiff's internals.
*/
static tsize_t tiff_read(thandle_t fd, tdata_t buf, tsize_t size)
{
return SDL_RWread((SDL_RWops*)fd, buf, 1, size);
}
static toff_t tiff_seek(thandle_t fd, toff_t offset, int origin)
{
return SDL_RWseek((SDL_RWops*)fd, offset, origin);
}
static tsize_t tiff_write(thandle_t fd, tdata_t buf, tsize_t size)
{
return SDL_RWwrite((SDL_RWops*)fd, buf, 1, size);
}
static int tiff_close(thandle_t fd)
{
/*
* We don't want libtiff closing our SDL_RWops*, but if it's not given
* a routine to try, and if the image isn't a TIFF, it'll segfault.
*/
return 0;
}
static int tiff_map(thandle_t fd, tdata_t* pbase, toff_t* psize)
{
return (0);
}
static void tiff_unmap(thandle_t fd, tdata_t base, toff_t size)
{
return;
}
static toff_t tiff_size(thandle_t fd)
{
Sint64 save_pos;
toff_t size;
save_pos = SDL_RWtell((SDL_RWops*)fd);
SDL_RWseek((SDL_RWops*)fd, 0, RW_SEEK_END);
size = SDL_RWtell((SDL_RWops*)fd);
SDL_RWseek((SDL_RWops*)fd, save_pos, RW_SEEK_SET);
return size;
}
int IMG_isTIF(SDL_RWops* src)
{
Sint64 start;
int is_TIF;
Uint8 magic[4];
if ( !src )
return 0;
start = SDL_RWtell(src);
is_TIF = 0;
if ( SDL_RWread(src, magic, 1, sizeof(magic)) == sizeof(magic) ) {
if ( (magic[0] == 'I' &&
magic[1] == 'I' &&
magic[2] == 0x2a &&
magic[3] == 0x00) ||
(magic[0] == 'M' &&
magic[1] == 'M' &&
magic[2] == 0x00 &&
magic[3] == 0x2a) ) {
is_TIF = 1;
}
}
SDL_RWseek(src, start, RW_SEEK_SET);
return(is_TIF);
}
SDL_Surface* IMG_LoadTIF_RW(SDL_RWops* src)
{
Sint64 start;
TIFF* tiff;
SDL_Surface* surface = NULL;
Uint32 img_width, img_height;
Uint32 Rmask, Gmask, Bmask, Amask;
Uint32 x, y;
Uint32 half;
if ( !src ) {
/* The error message has been set in SDL_RWFromFile */
return NULL;
}
start = SDL_RWtell(src);
if ( !IMG_Init(IMG_INIT_TIF) ) {
return NULL;
}
/* turn off memory mapped access with the m flag */
tiff = lib.TIFFClientOpen("SDL_image", "rm", (thandle_t)src,
tiff_read, tiff_write, tiff_seek, tiff_close, tiff_size, tiff_map, tiff_unmap);
if(!tiff)
goto error;
/* Retrieve the dimensions of the image from the TIFF tags */
lib.TIFFGetField(tiff, TIFFTAG_IMAGEWIDTH, &img_width);
lib.TIFFGetField(tiff, TIFFTAG_IMAGELENGTH, &img_height);
Rmask = 0x000000FF;
Gmask = 0x0000FF00;
Bmask = 0x00FF0000;
Amask = 0xFF000000;
surface = SDL_CreateRGBSurface(SDL_SWSURFACE, img_width, img_height, 32,
Rmask, Gmask, Bmask, Amask);
if(!surface)
goto error;
if(!lib.TIFFReadRGBAImage(tiff, img_width, img_height, (uint32 *)surface->pixels, 0))
goto error;
/* libtiff loads the image upside-down, flip it back */
half = img_height / 2;
for(y = 0; y < half; y++)
{
Uint32 *top = (Uint32 *)surface->pixels + y * surface->pitch/4;
Uint32 *bot = (Uint32 *)surface->pixels
+ (img_height - y - 1) * surface->pitch/4;
for(x = 0; x < img_width; x++)
{
Uint32 tmp = top[x];
top[x] = bot[x];
bot[x] = tmp;
}
}
lib.TIFFClose(tiff);
return surface;
error:
SDL_RWseek(src, start, RW_SEEK_SET);
if ( surface ) {
SDL_FreeSurface(surface);
}
return NULL;
}
#else
int IMG_InitTIF()
{
IMG_SetError("TIFF images are not supported");
return(-1);
}
void IMG_QuitTIF()
{
}
/* See if an image is contained in a data source */
int IMG_isTIF(SDL_RWops *src)
{
return(0);
}
/* Load a TIFF type image from an SDL datasource */
SDL_Surface *IMG_LoadTIF_RW(SDL_RWops *src)
{
return(NULL);
}
#endif /* LOAD_TIF */
#endif /* !defined(__APPLE__) || defined(SDL_IMAGE_USE_COMMON_BACKEND) */
|
prophecy/Pillar
|
Dependencies/Include/cml/fixed.h
|
/* -*- C++ -*- ------------------------------------------------------------
Copyright (c) 2007 <NAME> and <NAME> http://cmldev.net/
The Configurable Math Library (CML) is distributed under the terms of the
Boost Software License, v1.0 (see cml/LICENSE for details).
*-----------------------------------------------------------------------*/
/** @file
* @brief
*/
#ifndef fixed_h
#define fixed_h
namespace cml {
/** This is a selector for fixed 1D and 2D arrays.
*
* The fixed<> struct is used only to select a 1D or 2D array as the base
* class of a vector or matrix. The rebind<> template is used by
* quaternion<> to select its vector length in a generic way.
*
* @sa dynamic
* @sa external
*/
template<int Dim1 = -1, int Dim2 = -1> struct fixed {
/** Rebind to a 1D type.
*
* This is used by quaternion<>.
*/
template<int D> struct rebind { typedef fixed<D> other; };
};
} // namespace cml
#endif
// -------------------------------------------------------------------------
// vim:ft=cpp
|
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