source large_stringclasses 2 values | subject large_stringclasses 112 values | code large_stringclasses 112 values | critique large_stringlengths 61 3.04M ⌀ | metadata dict |
|---|---|---|---|---|
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) represented by
platform devices with a separate driver, but the IBI-wakeup is shared by
both, which means runtime PM has to be managed by the parent PCI driver.
To make that work, the PCI driver handles runtime PM, but leverages the
mipi-i3c-hci platform driver's functionality for saving and restoring
controller state.
Adrian Hunter (7):
i3c: mipi-i3c-hci-pci: Set d3hot_delay to 0 for Intel controllers
i3c: master: Allow controller drivers to select runtime PM device
i3c: master: Mark last_busy on IBI when runtime PM is allowed
i3c: mipi-i3c-hci: Add quirk to allow IBI while runtime suspended
i3c: mipi-i3c-hci: Allow parent to manage runtime PM
i3c: mipi-i3c-hci-pci: Add optional ability to manage child runtime PM
i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers
drivers/i3c/master.c | 14 +-
drivers/i3c/master/mipi-i3c-hci/core.c | 30 ++--
drivers/i3c/master/mipi-i3c-hci/hci.h | 7 +
drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 158 ++++++++++++++++++++-
include/linux/i3c/master.h | 2 +
5 files changed, 194 insertions(+), 17 deletions(-)
Regards
Adrian
| On Fri, Jan 30, 2026 at 06:34:37PM +0200, Adrian Hunter wrote:
Does your device Hierarchy look like
PCI device
|
-----------------
HCI1 HCI2
| |
I3C M1 I3C M2
You want HCI1 and HCI2 suspened only when both HCI1 and HCI2 can enter RM
time suspend status?
Device Link can link two devices, but not sure if it can handle cyclic
case, HCI1 and HCI2 depend each other.
Or you create common power domain for HCI1 and HCI2, in power domain to
handle suspend.
It'd better ask run time pm owner to provide better suggestion.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Mon, 2 Feb 2026 11:25:23 -0500",
"thread_id": "20260129181841.130864-1-adrian.hunter@intel.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.
The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.
Bootlog and Async mode tests on AM62D-EVM: [0]
[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
Signed-off-by: Sen Wang <sen@ti.com>
Sen Wang (4):
dt-bindings: sound: davinci-mcasp: Add optional properties for asynchronous mode
ASoC: ti: davinci-mcasp: Disambiguate mcasp_is_synchronous function
ASoC: ti: davinci-mcasp: Streamline pdir behavior across rx & tx streams
ASoC: ti: davinci-mcasp: Add asynchronous mode support
.../bindings/sound/davinci-mcasp-audio.yaml | 71 ++-
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 510 ++++++++++++++----
sound/soc/ti/davinci-mcasp.h | 10 +
4 files changed, 479 insertions(+), 115 deletions(-)
base-commit: dbf8fe85a16a33d6b6bd01f2bc606fc017771465
--
2.43.0
| Simplify the mcasp_set_clk_pdir caller convention in start/stop stream
function, to make it so that set_clk_pdir gets called regardless when
stream starts and also disables when stream ends.
Functionality-wise, everything remains the same as the previously skipped
calls are now either correctly configured
(when McASP is SND_SOC_DAIFMT_BP_FC - pdir needs to be enabled)
or called with a bitmask of zero (when McASP is SND_SOC_DAIFMT_BC_FC - pdir
gets disabled).
On brief regarding McASP Clock and Frame sync configurations, refer to [0].
[0]:TRM Section 12.1.1.4.2 https://www.ti.com/lit/ug/sprujd4a/sprujd4a.pdf
Signed-off-by: Sen Wang <sen@ti.com>
---
sound/soc/ti/davinci-mcasp.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c
index aa14fc1c8011..4f8a2ce6ce78 100644
--- a/sound/soc/ti/davinci-mcasp.c
+++ b/sound/soc/ti/davinci-mcasp.c
@@ -235,8 +235,8 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) {
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
- mcasp_set_clk_pdir(mcasp, true);
}
+ mcasp_set_clk_pdir(mcasp, true);
/* Activate serializer(s) */
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
@@ -311,10 +311,10 @@ static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
* In synchronous mode stop the TX clocks if no other stream is
* running
*/
- if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && !mcasp->streams) {
- mcasp_set_clk_pdir(mcasp, false);
+ if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && !mcasp->streams)
mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
- }
+ if (!mcasp->streams)
+ mcasp_set_clk_pdir(mcasp, false);
mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
@@ -340,7 +340,7 @@ static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
*/
if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && mcasp->streams)
val = TXHCLKRST | TXCLKRST | TXFSRST;
- else
+ if (!mcasp->streams)
mcasp_set_clk_pdir(mcasp, false);
--
2.43.0 | {
"author": "Sen Wang <sen@ti.com>",
"date": "Thu, 29 Jan 2026 23:10:43 -0600",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.
The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.
Bootlog and Async mode tests on AM62D-EVM: [0]
[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
Signed-off-by: Sen Wang <sen@ti.com>
Sen Wang (4):
dt-bindings: sound: davinci-mcasp: Add optional properties for asynchronous mode
ASoC: ti: davinci-mcasp: Disambiguate mcasp_is_synchronous function
ASoC: ti: davinci-mcasp: Streamline pdir behavior across rx & tx streams
ASoC: ti: davinci-mcasp: Add asynchronous mode support
.../bindings/sound/davinci-mcasp-audio.yaml | 71 ++-
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 510 ++++++++++++++----
sound/soc/ti/davinci-mcasp.h | 10 +
4 files changed, 479 insertions(+), 115 deletions(-)
base-commit: dbf8fe85a16a33d6b6bd01f2bc606fc017771465
--
2.43.0
| The current mcasp_is_synchronous() function does more than what it
proclaims, it also checks if McASP is a frame producer.
Therefore split the original function into two separate ones and
replace all occurrences with the new equivalent logic. So the functions
can be re-used when checking async/sync status in light of async mode
enhancements.
Signed-off-by: Sen Wang <sen@ti.com>
---
sound/soc/ti/davinci-mcasp.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c
index 621a9d5f9377..aa14fc1c8011 100644
--- a/sound/soc/ti/davinci-mcasp.c
+++ b/sound/soc/ti/davinci-mcasp.c
@@ -179,10 +179,16 @@ static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
{
- u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
- return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
+ return !(aclkxctl & TX_ASYNC);
+}
+
+static bool mcasp_is_frame_producer(struct davinci_mcasp *mcasp)
+{
+ u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
+
+ return rxfmctl & AFSRE;
}
static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
@@ -226,7 +232,7 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
* synchronously from the transmit clock and frame sync. We need to make
* sure that the TX signlas are enabled when starting reception.
*/
- if (mcasp_is_synchronous(mcasp)) {
+ if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) {
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
mcasp_set_clk_pdir(mcasp, true);
@@ -239,7 +245,7 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
/* Release Frame Sync generator */
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
- if (mcasp_is_synchronous(mcasp))
+ if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp))
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
/* enable receive IRQs */
@@ -305,7 +311,7 @@ static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
* In synchronous mode stop the TX clocks if no other stream is
* running
*/
- if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
+ if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && !mcasp->streams) {
mcasp_set_clk_pdir(mcasp, false);
mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
}
@@ -332,7 +338,7 @@ static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
* In synchronous mode keep TX clocks running if the capture stream is
* still running.
*/
- if (mcasp_is_synchronous(mcasp) && mcasp->streams)
+ if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && mcasp->streams)
val = TXHCLKRST | TXCLKRST | TXFSRST;
else
mcasp_set_clk_pdir(mcasp, false);
@@ -1041,7 +1047,8 @@ static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
* not running already we need to configure the TX slots in
* order to have correct FSX on the bus
*/
- if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
+ if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) &&
+ !mcasp->channels)
mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
FSXMOD(total_slots), FSXMOD(0x1FF));
}
--
2.43.0 | {
"author": "Sen Wang <sen@ti.com>",
"date": "Thu, 29 Jan 2026 23:10:42 -0600",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.
The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.
Bootlog and Async mode tests on AM62D-EVM: [0]
[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
Signed-off-by: Sen Wang <sen@ti.com>
Sen Wang (4):
dt-bindings: sound: davinci-mcasp: Add optional properties for asynchronous mode
ASoC: ti: davinci-mcasp: Disambiguate mcasp_is_synchronous function
ASoC: ti: davinci-mcasp: Streamline pdir behavior across rx & tx streams
ASoC: ti: davinci-mcasp: Add asynchronous mode support
.../bindings/sound/davinci-mcasp-audio.yaml | 71 ++-
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 510 ++++++++++++++----
sound/soc/ti/davinci-mcasp.h | 10 +
4 files changed, 479 insertions(+), 115 deletions(-)
base-commit: dbf8fe85a16a33d6b6bd01f2bc606fc017771465
--
2.43.0
| McASP supports the independent configuration of TX & RX clk and frame
sync registers. By default, the driver is configured in synchronous mode
where RX clock generator is disabled and it uses transmit clock signals as
bit clock and frame sync. Therefore add optional properties needed for
asynchronous mode.
Add ti,async-mode boolean binding to provide a way to decouple the default
behavior and allows for independent TX & RX clocking.
Add tdm-slots-rx uint32 binding to provide an alternative hardware
specifier stating the number of RX serializers.
The existing property tdm-slots will still dictate number of
TX serializers, and RX if tdm-slots-rx isn't given for backwards
compatibility.
Add auxclk-fs-ratio-rx which allows to specify the ratio just for RX.
The driver can be supplied with two different ratios
(auxclk-fs-ratio and auxclk-fs-ratio-rx in tandem) and achieve two
different sampling rates for tx & rx.
Signed-off-by: Sen Wang <sen@ti.com>
---
.../bindings/sound/davinci-mcasp-audio.yaml | 71 +++++++++++++++++--
1 file changed, 66 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml
index beef193aaaeb..87559d0d079a 100644
--- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml
+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml
@@ -40,11 +40,33 @@ properties:
tdm-slots:
$ref: /schemas/types.yaml#/definitions/uint32
description:
- number of channels over one serializer
- the property is ignored in DIT mode
+ Number of channels over one serializer. This property
+ specifies the TX playback TDM slot count, along with default RX slot count
+ if tdm-slots-rx is not specified.
+ The property is ignored in DIT mode.
minimum: 2
maximum: 32
+ tdm-slots-rx:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of RX capture channels over one serializer. If specified,
+ allows independent RX TDM slot count separate from TX. Requires
+ ti,async-mode to be enabled for independent TX/RX clock rates.
+ The property is ignored in DIT mode.
+ minimum: 2
+ maximum: 32
+
+ ti,async-mode:
+ description:
+ Specify to allow independent TX & RX clocking,
+ to enable audio playback & record with different sampling rate,
+ and different number of bits per frame.
+ if property is omitted, TX and RX will share same bit clock and frame clock signals,
+ thus RX need to use same bits per frame and sampling rate as TX in synchronous mode.
+ the property is ignored in DIT mode (as DIT is TX-only)
+ type: boolean
+
serial-dir:
description:
A list of serializer configuration
@@ -125,7 +147,21 @@ properties:
auxclk-fs-ratio:
$ref: /schemas/types.yaml#/definitions/uint32
- description: ratio of AUCLK and FS rate if applicable
+ description:
+ Ratio of AUCLK and FS rate if applicable. This property specifies
+ the TX ratio, along with default RX ratio if auxclk-fs-ratio-rx
+ is not specified.
+ When not specified, the inputted system clock frequency via set_sysclk
+ callback by the machine driver is used for divider calculation.
+
+ auxclk-fs-ratio-rx:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Ratio of AUCLK and FS rate for RX. If specified, allows
+ for a different RX ratio. Requires ti,async-mode to be
+ enabled when the ratio differs from auxclk-fs-ratio.
+ When not specified, it defaults to the value of auxclk-fs-ratio.
+ The property is ignored in DIT mode.
gpio-controller: true
@@ -170,14 +206,38 @@ allOf:
- $ref: dai-common.yaml#
- if:
properties:
- opmode:
+ op-mode:
enum:
- 0
-
then:
required:
- tdm-slots
+ - if:
+ properties:
+ op-mode:
+ const: 1
+ then:
+ properties:
+ tdm-slots: false
+ tdm-slots-rx: false
+ ti,async-mode: false
+ auxclk-fs-ratio-rx: false
+
+ - if:
+ required:
+ - tdm-slots-rx
+ then:
+ required:
+ - ti,async-mode
+
+ - if:
+ required:
+ - auxclk-fs-ratio-rx
+ then:
+ required:
+ - ti,async-mode
+
unevaluatedProperties: false
examples:
@@ -190,6 +250,7 @@ examples:
interrupt-names = "tx", "rx";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
+ ti,async-mode;
dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
dma-names = "tx", "rx";
serial-dir = <
--
2.43.0 | {
"author": "Sen Wang <sen@ti.com>",
"date": "Thu, 29 Jan 2026 23:10:41 -0600",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.
The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.
Bootlog and Async mode tests on AM62D-EVM: [0]
[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
Signed-off-by: Sen Wang <sen@ti.com>
Sen Wang (4):
dt-bindings: sound: davinci-mcasp: Add optional properties for asynchronous mode
ASoC: ti: davinci-mcasp: Disambiguate mcasp_is_synchronous function
ASoC: ti: davinci-mcasp: Streamline pdir behavior across rx & tx streams
ASoC: ti: davinci-mcasp: Add asynchronous mode support
.../bindings/sound/davinci-mcasp-audio.yaml | 71 ++-
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 510 ++++++++++++++----
sound/soc/ti/davinci-mcasp.h | 10 +
4 files changed, 479 insertions(+), 115 deletions(-)
base-commit: dbf8fe85a16a33d6b6bd01f2bc606fc017771465
--
2.43.0
| McASP has dedicated clock & frame sync registers for both transmit
and receive. Currently McASP driver only supports synchronous behavior and
couples both TX & RX settings.
Add logic that enables asynchronous mode via ti,async-mode property. In
async mode, playback & record can be done simultaneously with different
audio configurations (tdm slots, tdm width, audio bit depth).
Note the ability to have different tx/rx DSP formats (i2s, dsp_a, etc.),
while possible in hardware, remains to be a gap as it require changes
to the corresponding machine driver interface.
Existing IIS (sync mode) and DIT mode logic remains mostly unchanged.
Exceptions are IIS mode logic that previously assumed sync mode, which has
now been made aware of the distinction. And shared logic across all modes
also now checks for McASP tx/rx-specific driver attributes. Those
attributes have been populated according to the original extent, ensuring
no divergence in functionality.
Constraints no longer applicable for async mode are skipped.
Clock selection options have also been added to include rx/tx-only clk_ids,
exposing independent configuration via the machine driver as well.
Note that asynchronous mode is not applicable for McASP in DIT mode,
which is a transmitter-only mode to interface w/ self-clocking formats.
Signed-off-by: Sen Wang <sen@ti.com>
---
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 487 +++++++++++++++++-----
sound/soc/ti/davinci-mcasp.h | 10 +
3 files changed, 398 insertions(+), 102 deletions(-)
diff --git a/include/linux/platform_data/davinci_asp.h b/include/linux/platform_data/davinci_asp.h
index b9c8520b4bd3..509c5592aab0 100644
--- a/include/linux/platform_data/davinci_asp.h
+++ b/include/linux/platform_data/davinci_asp.h
@@ -59,7 +59,8 @@ struct davinci_mcasp_pdata {
bool i2s_accurate_sck;
/* McASP specific fields */
- int tdm_slots;
+ int tdm_slots_tx;
+ int tdm_slots_rx;
u8 op_mode;
u8 dismod;
u8 num_serializer;
diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c
index 4f8a2ce6ce78..ef7fa23d30bf 100644
--- a/sound/soc/ti/davinci-mcasp.c
+++ b/sound/soc/ti/davinci-mcasp.c
@@ -70,6 +70,7 @@ struct davinci_mcasp_context {
struct davinci_mcasp_ruledata {
struct davinci_mcasp *mcasp;
int serializers;
+ int stream;
};
struct davinci_mcasp {
@@ -87,21 +88,27 @@ struct davinci_mcasp {
bool missing_audio_param;
/* McASP specific data */
- int tdm_slots;
+ int tdm_slots_tx;
+ int tdm_slots_rx;
u32 tdm_mask[2];
- int slot_width;
+ int slot_width_tx;
+ int slot_width_rx;
u8 op_mode;
u8 dismod;
u8 num_serializer;
u8 *serial_dir;
u8 version;
- u8 bclk_div;
+ u8 bclk_div_tx;
+ u8 bclk_div_rx;
int streams;
u32 irq_request[2];
- int sysclk_freq;
+ unsigned int sysclk_freq_tx;
+ unsigned int sysclk_freq_rx;
bool bclk_master;
- u32 auxclk_fs_ratio;
+ bool async_mode;
+ u32 auxclk_fs_ratio_tx;
+ u32 auxclk_fs_ratio_rx;
unsigned long pdir; /* Pin direction bitfield */
@@ -203,6 +210,27 @@ static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
}
}
+static inline void mcasp_set_clk_pdir_stream(struct davinci_mcasp *mcasp,
+ int stream, bool enable)
+{
+ u32 bit, bit_end;
+
+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ bit = PIN_BIT_ACLKX;
+ bit_end = PIN_BIT_AFSX + 1;
+ } else {
+ bit = PIN_BIT_ACLKR;
+ bit_end = PIN_BIT_AFSR + 1;
+ }
+
+ for_each_set_bit_from(bit, &mcasp->pdir, bit_end) {
+ if (enable)
+ mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
+ else
+ mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
+ }
+}
+
static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
{
u32 bit;
@@ -215,6 +243,36 @@ static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
}
}
+static inline int mcasp_get_tdm_slots(struct davinci_mcasp *mcasp, int stream)
+{
+ return (stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+ mcasp->tdm_slots_tx : mcasp->tdm_slots_rx;
+}
+
+static inline int mcasp_get_slot_width(struct davinci_mcasp *mcasp, int stream)
+{
+ return (stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+ mcasp->slot_width_tx : mcasp->slot_width_rx;
+}
+
+static inline unsigned int mcasp_get_sysclk_freq(struct davinci_mcasp *mcasp, int stream)
+{
+ return (stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+ mcasp->sysclk_freq_tx : mcasp->sysclk_freq_rx;
+}
+
+static inline unsigned int mcasp_get_bclk_div(struct davinci_mcasp *mcasp, int stream)
+{
+ return (stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+ mcasp->bclk_div_tx : mcasp->bclk_div_rx;
+}
+
+static inline unsigned int mcasp_get_auxclk_fs_ratio(struct davinci_mcasp *mcasp, int stream)
+{
+ return (stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+ mcasp->auxclk_fs_ratio_tx : mcasp->auxclk_fs_ratio_rx;
+}
+
static void mcasp_start_rx(struct davinci_mcasp *mcasp)
{
if (mcasp->rxnumevt) { /* enable FIFO */
@@ -230,13 +288,17 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
/*
* When ASYNC == 0 the transmit and receive sections operate
* synchronously from the transmit clock and frame sync. We need to make
- * sure that the TX signlas are enabled when starting reception.
+ * sure that the TX signals are enabled when starting reception.
+ * Else set pin to be output when McASP is the master
*/
if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) {
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
}
- mcasp_set_clk_pdir(mcasp, true);
+ if (mcasp_is_synchronous(mcasp))
+ mcasp_set_clk_pdir(mcasp, true);
+ else
+ mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_CAPTURE, true);
/* Activate serializer(s) */
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
@@ -267,7 +329,10 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
/* Start clocks */
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
- mcasp_set_clk_pdir(mcasp, true);
+ if (mcasp_is_synchronous(mcasp))
+ mcasp_set_clk_pdir(mcasp, true);
+ else
+ mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_PLAYBACK, true);
/* Activate serializer(s) */
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
@@ -310,11 +375,14 @@ static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
/*
* In synchronous mode stop the TX clocks if no other stream is
* running
+ * Otherwise in async mode only stop RX clocks
*/
if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && !mcasp->streams)
mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
- if (!mcasp->streams)
+ if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
mcasp_set_clk_pdir(mcasp, false);
+ else if (!mcasp_is_synchronous(mcasp))
+ mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_CAPTURE, false);
mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
@@ -337,11 +405,14 @@ static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
/*
* In synchronous mode keep TX clocks running if the capture stream is
* still running.
+ * Otherwise in async mode only stop TX clocks
*/
if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && mcasp->streams)
val = TXHCLKRST | TXCLKRST | TXFSRST;
- if (!mcasp->streams)
+ if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
mcasp_set_clk_pdir(mcasp, false);
+ else if (!mcasp_is_synchronous(mcasp))
+ mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_PLAYBACK, false);
mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
@@ -353,7 +424,8 @@ static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
}
- mcasp_set_axr_pdir(mcasp, false);
+ if (!mcasp->streams)
+ mcasp_set_axr_pdir(mcasp, false);
}
static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
@@ -625,13 +697,39 @@ static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
break;
+ case MCASP_CLKDIV_AUXCLK_TXONLY: /* MCLK divider for TX only */
+ mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
+ AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
+ break;
+
+ case MCASP_CLKDIV_AUXCLK_RXONLY: /* MCLK divider for RX only */
+ mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
+ AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
+ break;
+
case MCASP_CLKDIV_BCLK: /* BCLK divider */
mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
ACLKXDIV(div - 1), ACLKXDIV_MASK);
+ mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
+ ACLKRDIV(div - 1), ACLKRDIV_MASK);
+ if (explicit) {
+ mcasp->bclk_div_tx = div;
+ mcasp->bclk_div_rx = div;
+ }
+ break;
+
+ case MCASP_CLKDIV_BCLK_TXONLY: /* BCLK divider for TX only */
+ mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
+ ACLKXDIV(div - 1), ACLKXDIV_MASK);
+ if (explicit)
+ mcasp->bclk_div_tx = div;
+ break;
+
+ case MCASP_CLKDIV_BCLK_RXONLY: /* BCLK divider for RX only */
mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
ACLKRDIV(div - 1), ACLKRDIV_MASK);
if (explicit)
- mcasp->bclk_div = div;
+ mcasp->bclk_div_rx = div;
break;
case MCASP_CLKDIV_BCLK_FS_RATIO:
@@ -645,11 +743,33 @@ static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
* tdm_slot width by dividing the ratio by the
* number of configured tdm slots.
*/
- mcasp->slot_width = div / mcasp->tdm_slots;
- if (div % mcasp->tdm_slots)
+ mcasp->slot_width_tx = div / mcasp->tdm_slots_tx;
+ if (div % mcasp->tdm_slots_tx)
+ dev_warn(mcasp->dev,
+ "%s(): BCLK/LRCLK %d is not divisible by %d tx tdm slots",
+ __func__, div, mcasp->tdm_slots_tx);
+
+ mcasp->slot_width_rx = div / mcasp->tdm_slots_rx;
+ if (div % mcasp->tdm_slots_rx)
+ dev_warn(mcasp->dev,
+ "%s(): BCLK/LRCLK %d is not divisible by %d rx tdm slots",
+ __func__, div, mcasp->tdm_slots_rx);
+ break;
+
+ case MCASP_CLKDIV_BCLK_FS_RATIO_TXONLY:
+ mcasp->slot_width_tx = div / mcasp->tdm_slots_tx;
+ if (div % mcasp->tdm_slots_tx)
+ dev_warn(mcasp->dev,
+ "%s(): BCLK/LRCLK %d is not divisible by %d tx tdm slots",
+ __func__, div, mcasp->tdm_slots_tx);
+ break;
+
+ case MCASP_CLKDIV_BCLK_FS_RATIO_RXONLY:
+ mcasp->slot_width_rx = div / mcasp->tdm_slots_rx;
+ if (div % mcasp->tdm_slots_rx)
dev_warn(mcasp->dev,
- "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
- __func__, div, mcasp->tdm_slots);
+ "%s(): BCLK/LRCLK %d is not divisible by %d rx tdm slots",
+ __func__, div, mcasp->tdm_slots_rx);
break;
default:
@@ -683,6 +803,20 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
AHCLKRE);
clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+ mcasp->sysclk_freq_tx = freq;
+ mcasp->sysclk_freq_rx = freq;
+ break;
+ case MCASP_CLK_HCLK_AHCLK_TXONLY:
+ mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
+ AHCLKXE);
+ clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+ mcasp->sysclk_freq_tx = freq;
+ break;
+ case MCASP_CLK_HCLK_AHCLK_RXONLY:
+ mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
+ AHCLKRE);
+ clear_bit(PIN_BIT_AHCLKR, &mcasp->pdir);
+ mcasp->sysclk_freq_rx = freq;
break;
case MCASP_CLK_HCLK_AUXCLK:
mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
@@ -690,22 +824,56 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
AHCLKRE);
set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+ mcasp->sysclk_freq_tx = freq;
+ mcasp->sysclk_freq_rx = freq;
+ break;
+ case MCASP_CLK_HCLK_AUXCLK_TXONLY:
+ mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
+ AHCLKXE);
+ set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+ mcasp->sysclk_freq_tx = freq;
+ break;
+ case MCASP_CLK_HCLK_AUXCLK_RXONLY:
+ mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
+ AHCLKRE);
+ set_bit(PIN_BIT_AHCLKR, &mcasp->pdir);
+ mcasp->sysclk_freq_rx = freq;
break;
default:
dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
goto out;
}
} else {
- /* Select AUXCLK as HCLK */
- mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
- mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
- set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+ /* McASP is clock master, select AUXCLK as HCLK */
+ switch (clk_id) {
+ case MCASP_CLK_HCLK_AUXCLK_TXONLY:
+ mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
+ AHCLKXE);
+ set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+ mcasp->sysclk_freq_tx = freq;
+ break;
+ case MCASP_CLK_HCLK_AUXCLK_RXONLY:
+ mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
+ AHCLKRE);
+ set_bit(PIN_BIT_AHCLKR, &mcasp->pdir);
+ mcasp->sysclk_freq_rx = freq;
+ break;
+ default:
+ mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
+ AHCLKXE);
+ mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
+ AHCLKRE);
+ set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+ set_bit(PIN_BIT_AHCLKR, &mcasp->pdir);
+ mcasp->sysclk_freq_tx = freq;
+ mcasp->sysclk_freq_rx = freq;
+ break;
+ }
}
/*
* When AHCLK X/R is selected to be output it means that the HCLK is
* the same clock - coming via AUXCLK.
*/
- mcasp->sysclk_freq = freq;
out:
pm_runtime_put(mcasp->dev);
return 0;
@@ -717,9 +885,11 @@ static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
{
struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
unsigned int *list = (unsigned int *) cl->list;
- int slots = mcasp->tdm_slots;
+ int slots;
int i, count = 0;
+ slots = mcasp_get_tdm_slots(mcasp, stream);
+
if (mcasp->tdm_mask[stream])
slots = hweight32(mcasp->tdm_mask[stream]);
@@ -784,27 +954,42 @@ static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
return -EINVAL;
}
- mcasp->tdm_slots = slots;
+ if (mcasp->async_mode) {
+ if (tx_mask) {
+ mcasp->tdm_slots_tx = slots;
+ mcasp->slot_width_tx = slot_width;
+ }
+ if (rx_mask) {
+ mcasp->tdm_slots_rx = slots;
+ mcasp->slot_width_rx = slot_width;
+ }
+ } else {
+ mcasp->tdm_slots_tx = slots;
+ mcasp->tdm_slots_rx = slots;
+ mcasp->slot_width_tx = slot_width;
+ mcasp->slot_width_rx = slot_width;
+ }
+
mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
- mcasp->slot_width = slot_width;
return davinci_mcasp_set_ch_constraints(mcasp);
}
static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
- int sample_width)
+ int sample_width, int stream)
{
u32 fmt;
u32 tx_rotate, rx_rotate, slot_width;
u32 mask = (1ULL << sample_width) - 1;
- if (mcasp->slot_width)
- slot_width = mcasp->slot_width;
- else if (mcasp->max_format_width)
- slot_width = mcasp->max_format_width;
- else
- slot_width = sample_width;
+ slot_width = mcasp_get_slot_width(mcasp, stream);
+ if (!slot_width) {
+ if (mcasp->max_format_width)
+ slot_width = mcasp->max_format_width;
+ else
+ slot_width = sample_width;
+ }
/*
* TX rotation:
* right aligned formats: rotate w/ slot_width
@@ -827,17 +1012,23 @@ static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
fmt = (slot_width >> 1) - 1;
if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
- mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
- RXSSZ(0x0F));
- mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
- TXSSZ(0x0F));
- mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
- TXROT(7));
- mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
- RXROT(7));
- mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
+ if (!mcasp->async_mode || stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
+ TXSSZ(0x0F));
+ mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
+ TXROT(7));
+ mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
+ }
+ if (!mcasp->async_mode || stream == SNDRV_PCM_STREAM_CAPTURE) {
+ mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
+ RXSSZ(0x0F));
+ mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
+ RXROT(7));
+ mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
+ }
} else {
/*
+ * DIT mode only use TX serializers
* according to the TRM it should be TXROT=0, this one works:
* 16 bit to 23-8 (TXROT=6, rotate 24 bits)
* 24 bit to 23-0 (TXROT=0, rotate 0 bits)
@@ -850,10 +1041,9 @@ static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
TXROT(7));
mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15),
TXSSZ(0x0F));
+ mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
}
- mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
-
return 0;
}
@@ -864,11 +1054,13 @@ static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
int i;
u8 tx_ser = 0;
u8 rx_ser = 0;
- u8 slots = mcasp->tdm_slots;
+ int slots;
u8 max_active_serializers, max_rx_serializers, max_tx_serializers;
int active_serializers, numevt;
u32 reg;
+ slots = mcasp_get_tdm_slots(mcasp, stream);
+
/* In DIT mode we only allow maximum of one serializers for now */
if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
max_active_serializers = 1;
@@ -996,7 +1188,7 @@ static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
u32 mask = 0;
u32 busel = 0;
- total_slots = mcasp->tdm_slots;
+ total_slots = mcasp_get_tdm_slots(mcasp, stream);
/*
* If more than one serializer is needed, then use them with
@@ -1027,7 +1219,10 @@ static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
mask |= (1 << i);
}
- mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
+ if (mcasp->async_mode)
+ mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
+ else
+ mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
if (!mcasp->dat_port)
busel = TXSEL;
@@ -1126,16 +1321,33 @@ static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
unsigned int sysclk_freq,
- unsigned int bclk_freq, bool set)
+ unsigned int bclk_freq,
+ int stream,
+ bool set)
{
- u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
int div = sysclk_freq / bclk_freq;
int rem = sysclk_freq % bclk_freq;
int error_ppm;
int aux_div = 1;
+ int bclk_div_id, auxclk_div_id;
+ bool auxclk_enabled;
+
+ if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_CAPTURE) {
+ auxclk_enabled = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG) & AHCLKRE;
+ bclk_div_id = MCASP_CLKDIV_BCLK_RXONLY;
+ auxclk_div_id = MCASP_CLKDIV_AUXCLK_RXONLY;
+ } else if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ auxclk_enabled = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG) & AHCLKXE;
+ bclk_div_id = MCASP_CLKDIV_BCLK_TXONLY;
+ auxclk_div_id = MCASP_CLKDIV_AUXCLK_TXONLY;
+ } else {
+ auxclk_enabled = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG) & AHCLKXE;
+ bclk_div_id = MCASP_CLKDIV_BCLK;
+ auxclk_div_id = MCASP_CLKDIV_AUXCLK;
+ }
if (div > (ACLKXDIV_MASK + 1)) {
- if (reg & AHCLKXE) {
+ if (auxclk_enabled) {
aux_div = div / (ACLKXDIV_MASK + 1);
if (div % (ACLKXDIV_MASK + 1))
aux_div++;
@@ -1165,10 +1377,10 @@ static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
error_ppm);
- __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
- if (reg & AHCLKXE)
- __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
- aux_div, 0);
+ __davinci_mcasp_set_clkdiv(mcasp, bclk_div_id, div, false);
+ if (auxclk_enabled)
+ __davinci_mcasp_set_clkdiv(mcasp, auxclk_div_id,
+ aux_div, false);
}
return error_ppm;
@@ -1219,6 +1431,7 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
int channels = params_channels(params);
int period_size = params_period_size(params);
int ret;
+ unsigned int sysclk_freq = mcasp_get_sysclk_freq(mcasp, substream->stream);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_U8:
@@ -1259,22 +1472,26 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
* If mcasp is BCLK master, and a BCLK divider was not provided by
* the machine driver, we need to calculate the ratio.
*/
- if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
- int slots = mcasp->tdm_slots;
+ if (mcasp->bclk_master && mcasp_get_bclk_div(mcasp, substream->stream) == 0 &&
+ sysclk_freq) {
+ int slots, slot_width;
int rate = params_rate(params);
int sbits = params_width(params);
unsigned int bclk_target;
- if (mcasp->slot_width)
- sbits = mcasp->slot_width;
+ slots = mcasp_get_tdm_slots(mcasp, substream->stream);
+
+ slot_width = mcasp_get_slot_width(mcasp, substream->stream);
+ if (slot_width)
+ sbits = slot_width;
if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
bclk_target = rate * sbits * slots;
else
bclk_target = rate * 128;
- davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
- bclk_target, true);
+ davinci_mcasp_calc_clk_div(mcasp, sysclk_freq,
+ bclk_target, substream->stream, true);
}
ret = mcasp_common_hw_param(mcasp, substream->stream,
@@ -1291,9 +1508,10 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
if (ret)
return ret;
- davinci_config_channel_size(mcasp, word_length);
+ davinci_config_channel_size(mcasp, word_length, substream->stream);
- if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
+ /* Channel constraints are disabled for async mode */
+ if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE && !mcasp->async_mode) {
mcasp->channels = channels;
if (!mcasp->max_format_width)
mcasp->max_format_width = word_length;
@@ -1337,7 +1555,7 @@ static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
snd_pcm_format_t i;
snd_mask_none(&nfmt);
- slot_width = rd->mcasp->slot_width;
+ slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream);
pcm_for_each_format(i) {
if (snd_mask_test_format(fmt, i)) {
@@ -1387,12 +1605,15 @@ static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
struct snd_interval *ri =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
int sbits = params_width(params);
- int slots = rd->mcasp->tdm_slots;
+ int slots, slot_width;
struct snd_interval range;
int i;
- if (rd->mcasp->slot_width)
- sbits = rd->mcasp->slot_width;
+ slots = mcasp_get_tdm_slots(rd->mcasp, rd->stream);
+
+ slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream);
+ if (slot_width)
+ sbits = slot_width;
snd_interval_any(&range);
range.empty = 1;
@@ -1402,16 +1623,17 @@ static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
uint bclk_freq = sbits * slots *
davinci_mcasp_dai_rates[i];
unsigned int sysclk_freq;
+ unsigned int ratio;
int ppm;
- if (rd->mcasp->auxclk_fs_ratio)
- sysclk_freq = davinci_mcasp_dai_rates[i] *
- rd->mcasp->auxclk_fs_ratio;
+ ratio = mcasp_get_auxclk_fs_ratio(rd->mcasp, rd->stream);
+ if (ratio)
+ sysclk_freq = davinci_mcasp_dai_rates[i] * ratio;
else
- sysclk_freq = rd->mcasp->sysclk_freq;
+ sysclk_freq = mcasp_get_sysclk_freq(rd->mcasp, rd->stream);
ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
- bclk_freq, false);
+ bclk_freq, rd->stream, false);
if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
if (range.empty) {
range.min = davinci_mcasp_dai_rates[i];
@@ -1437,30 +1659,34 @@ static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
struct snd_mask nfmt;
int rate = params_rate(params);
- int slots = rd->mcasp->tdm_slots;
+ int slots;
int count = 0;
snd_pcm_format_t i;
+ slots = mcasp_get_tdm_slots(rd->mcasp, rd->stream);
+
snd_mask_none(&nfmt);
pcm_for_each_format(i) {
if (snd_mask_test_format(fmt, i)) {
uint sbits = snd_pcm_format_width(i);
unsigned int sysclk_freq;
- int ppm;
+ unsigned int ratio;
+ int ppm, slot_width;
- if (rd->mcasp->auxclk_fs_ratio)
- sysclk_freq = rate *
- rd->mcasp->auxclk_fs_ratio;
+ ratio = mcasp_get_auxclk_fs_ratio(rd->mcasp, rd->stream);
+ if (ratio)
+ sysclk_freq = rate * ratio;
else
- sysclk_freq = rd->mcasp->sysclk_freq;
+ sysclk_freq = mcasp_get_sysclk_freq(rd->mcasp, rd->stream);
- if (rd->mcasp->slot_width)
- sbits = rd->mcasp->slot_width;
+ slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream);
+ if (slot_width)
+ sbits = slot_width;
ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
sbits * slots * rate,
- false);
+ rd->stream, false);
if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
snd_mask_set_format(&nfmt, i);
count++;
@@ -1497,7 +1723,7 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
&mcasp->ruledata[substream->stream];
u32 max_channels = 0;
int i, dir, ret;
- int tdm_slots = mcasp->tdm_slots;
+ int tdm_slots;
u8 *numevt;
/* Do not allow more then one stream per direction */
@@ -1506,6 +1732,8 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
mcasp->substreams[substream->stream] = substream;
+ tdm_slots = mcasp_get_tdm_slots(mcasp, substream->stream);
+
if (mcasp->tdm_mask[substream->stream])
tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
@@ -1527,6 +1755,7 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
}
ruledata->serializers = max_channels;
ruledata->mcasp = mcasp;
+ ruledata->stream = substream->stream;
max_channels *= tdm_slots;
/*
* If the already active stream has less channels than the calculated
@@ -1534,9 +1763,13 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
* is in use we need to use that as a constraint for the second stream.
* Otherwise (first stream or less allowed channels or more than one
* serializer in use) we use the calculated constraint.
+ *
+ * However, in async mode, TX and RX have independent clocks and can
+ * use different configurations, so don't apply the constraint.
*/
if (mcasp->channels && mcasp->channels < max_channels &&
- ruledata->serializers == 1)
+ ruledata->serializers == 1 &&
+ !mcasp->async_mode)
max_channels = mcasp->channels;
/*
* But we can always allow channels upto the amount of
@@ -1553,10 +1786,10 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
0, SNDRV_PCM_HW_PARAM_CHANNELS,
&mcasp->chconstr[substream->stream]);
- if (mcasp->max_format_width) {
+ if (mcasp->max_format_width && !mcasp->async_mode) {
/*
* Only allow formats which require same amount of bits on the
- * bus as the currently running stream
+ * bus as the currently running stream to ensure sync mode
*/
ret = snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_FORMAT,
@@ -1565,8 +1798,7 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
SNDRV_PCM_HW_PARAM_FORMAT, -1);
if (ret)
return ret;
- }
- else if (mcasp->slot_width) {
+ } else if (mcasp_get_slot_width(mcasp, substream->stream)) {
/* Only allow formats require <= slot_width bits on the bus */
ret = snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_FORMAT,
@@ -1581,7 +1813,8 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
* If we rely on implicit BCLK divider setting we should
* set constraints based on what we can provide.
*/
- if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
+ if (mcasp->bclk_master && mcasp_get_bclk_div(mcasp, substream->stream) == 0 &&
+ mcasp_get_sysclk_freq(mcasp, substream->stream)) {
ret = snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
davinci_mcasp_hw_rule_rate,
@@ -1758,8 +1991,6 @@ static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
.formats = DAVINCI_MCASP_PCM_FMTS,
},
.ops = &davinci_mcasp_dai_ops,
-
- .symmetric_rate = 1,
},
{
.name = "davinci-mcasp.1",
@@ -1921,18 +2152,33 @@ static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,
goto out;
}
+ /* Parse TX-specific TDM slot and use it as default for RX */
if (of_property_read_u32(np, "tdm-slots", &val) == 0) {
if (val < 2 || val > 32) {
- dev_err(&pdev->dev, "tdm-slots must be in rage [2-32]\n");
+ dev_err(&pdev->dev, "tdm-slots must be in range [2-32]\n");
return -EINVAL;
}
- pdata->tdm_slots = val;
+ pdata->tdm_slots_tx = val;
+ pdata->tdm_slots_rx = val;
} else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) {
mcasp->missing_audio_param = true;
goto out;
}
+ /* Parse RX-specific TDM slot count if provided */
+ if (of_property_read_u32(np, "tdm-slots-rx", &val) == 0) {
+ if (val < 2 || val > 32) {
+ dev_err(&pdev->dev, "tdm-slots-rx must be in range [2-32]\n");
+ return -EINVAL;
+ }
+
+ pdata->tdm_slots_rx = val;
+ }
+
+ if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE)
+ mcasp->async_mode = of_property_read_bool(np, "ti,async-mode");
+
of_serial_dir32 = of_get_property(np, "serial-dir", &val);
val /= sizeof(u32);
if (of_serial_dir32) {
@@ -1958,8 +2204,15 @@ static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,
if (of_property_read_u32(np, "rx-num-evt", &val) == 0)
pdata->rxnumevt = val;
- if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0)
- mcasp->auxclk_fs_ratio = val;
+ /* Parse TX-specific auxclk/fs ratio and use it as default for RX */
+ if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0) {
+ mcasp->auxclk_fs_ratio_tx = val;
+ mcasp->auxclk_fs_ratio_rx = val;
+ }
+
+ /* Parse RX-specific auxclk/fs ratio if provided */
+ if (of_property_read_u32(np, "auxclk-fs-ratio-rx", &val) == 0)
+ mcasp->auxclk_fs_ratio_rx = val;
if (of_property_read_u32(np, "dismod", &val) == 0) {
if (val == 0 || val == 2 || val == 3) {
@@ -1988,19 +2241,51 @@ static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,
mcasp->op_mode = pdata->op_mode;
/* sanity check for tdm slots parameter */
if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
- if (pdata->tdm_slots < 2) {
- dev_warn(&pdev->dev, "invalid tdm slots: %d\n",
- pdata->tdm_slots);
- mcasp->tdm_slots = 2;
- } else if (pdata->tdm_slots > 32) {
- dev_warn(&pdev->dev, "invalid tdm slots: %d\n",
- pdata->tdm_slots);
- mcasp->tdm_slots = 32;
+ if (pdata->tdm_slots_tx < 2) {
+ dev_warn(&pdev->dev, "invalid tdm tx slots: %d\n",
+ pdata->tdm_slots_tx);
+ mcasp->tdm_slots_tx = 2;
+ } else if (pdata->tdm_slots_tx > 32) {
+ dev_warn(&pdev->dev, "invalid tdm tx slots: %d\n",
+ pdata->tdm_slots_tx);
+ mcasp->tdm_slots_tx = 32;
} else {
- mcasp->tdm_slots = pdata->tdm_slots;
+ mcasp->tdm_slots_tx = pdata->tdm_slots_tx;
+ }
+
+ if (pdata->tdm_slots_rx < 2) {
+ dev_warn(&pdev->dev, "invalid tdm rx slots: %d\n",
+ pdata->tdm_slots_rx);
+ mcasp->tdm_slots_rx = 2;
+ } else if (pdata->tdm_slots_rx > 32) {
+ dev_warn(&pdev->dev, "invalid tdm rx slots: %d\n",
+ pdata->tdm_slots_rx);
+ mcasp->tdm_slots_rx = 32;
+ } else {
+ mcasp->tdm_slots_rx = pdata->tdm_slots_rx;
}
} else {
- mcasp->tdm_slots = 32;
+ mcasp->tdm_slots_tx = 32;
+ mcasp->tdm_slots_rx = 32;
+ }
+
+ /* Different TX/RX slot counts require async mode */
+ if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE &&
+ mcasp->tdm_slots_tx != mcasp->tdm_slots_rx && !mcasp->async_mode) {
+ dev_err(&pdev->dev,
+ "Different TX (%d) and RX (%d) TDM slots require ti,async-mode\n",
+ mcasp->tdm_slots_tx, mcasp->tdm_slots_rx);
+ return -EINVAL;
+ }
+
+ /* Different TX/RX auxclk-fs-ratio require async mode */
+ if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE &&
+ mcasp->auxclk_fs_ratio_tx && mcasp->auxclk_fs_ratio_rx &&
+ mcasp->auxclk_fs_ratio_tx != mcasp->auxclk_fs_ratio_rx && !mcasp->async_mode) {
+ dev_err(&pdev->dev,
+ "Different TX (%d) and RX (%d) auxclk-fs-ratio require ti,async-mode\n",
+ mcasp->auxclk_fs_ratio_tx, mcasp->auxclk_fs_ratio_rx);
+ return -EINVAL;
}
mcasp->num_serializer = pdata->num_serializer;
diff --git a/sound/soc/ti/davinci-mcasp.h b/sound/soc/ti/davinci-mcasp.h
index 5de2b8a31061..4eba8c918c5f 100644
--- a/sound/soc/ti/davinci-mcasp.h
+++ b/sound/soc/ti/davinci-mcasp.h
@@ -298,10 +298,20 @@
/* Source of High-frequency transmit/receive clock */
#define MCASP_CLK_HCLK_AHCLK 0 /* AHCLKX/R */
#define MCASP_CLK_HCLK_AUXCLK 1 /* Internal functional clock */
+#define MCASP_CLK_HCLK_AHCLK_TXONLY 2 /* AHCLKX for TX only */
+#define MCASP_CLK_HCLK_AHCLK_RXONLY 3 /* AHCLKR for RX only */
+#define MCASP_CLK_HCLK_AUXCLK_TXONLY 4 /* AUXCLK for TX only */
+#define MCASP_CLK_HCLK_AUXCLK_RXONLY 5 /* AUXCLK for RX only */
/* clock divider IDs */
#define MCASP_CLKDIV_AUXCLK 0 /* HCLK divider from AUXCLK */
#define MCASP_CLKDIV_BCLK 1 /* BCLK divider from HCLK */
#define MCASP_CLKDIV_BCLK_FS_RATIO 2 /* to set BCLK FS ration */
+#define MCASP_CLKDIV_AUXCLK_TXONLY 3 /* AUXCLK divider for TX only */
+#define MCASP_CLKDIV_AUXCLK_RXONLY 4 /* AUXCLK divider for RX only */
+#define MCASP_CLKDIV_BCLK_TXONLY 5 /* BCLK divider for TX only */
+#define MCASP_CLKDIV_BCLK_RXONLY 6 /* BCLK divider for RX only */
+#define MCASP_CLKDIV_BCLK_FS_RATIO_TXONLY 7 /* BCLK/FS ratio for TX only */
+#define MCASP_CLKDIV_BCLK_FS_RATIO_RXONLY 8 /* BCLK/FS ratio for RX only */
#endif /* DAVINCI_MCASP_H */
--
2.43.0 | {
"author": "Sen Wang <sen@ti.com>",
"date": "Thu, 29 Jan 2026 23:10:44 -0600",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.
The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.
Bootlog and Async mode tests on AM62D-EVM: [0]
[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
Signed-off-by: Sen Wang <sen@ti.com>
Sen Wang (4):
dt-bindings: sound: davinci-mcasp: Add optional properties for asynchronous mode
ASoC: ti: davinci-mcasp: Disambiguate mcasp_is_synchronous function
ASoC: ti: davinci-mcasp: Streamline pdir behavior across rx & tx streams
ASoC: ti: davinci-mcasp: Add asynchronous mode support
.../bindings/sound/davinci-mcasp-audio.yaml | 71 ++-
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 510 ++++++++++++++----
sound/soc/ti/davinci-mcasp.h | 10 +
4 files changed, 479 insertions(+), 115 deletions(-)
base-commit: dbf8fe85a16a33d6b6bd01f2bc606fc017771465
--
2.43.0
| On Thu, Jan 29, 2026 at 11:10:41PM -0600, Sen Wang wrote:
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resemble what they're doing.
There's no need to resubmit to fix this alone. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Mon, 2 Feb 2026 12:44:32 +0000",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.
The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.
Bootlog and Async mode tests on AM62D-EVM: [0]
[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
Signed-off-by: Sen Wang <sen@ti.com>
Sen Wang (4):
dt-bindings: sound: davinci-mcasp: Add optional properties for asynchronous mode
ASoC: ti: davinci-mcasp: Disambiguate mcasp_is_synchronous function
ASoC: ti: davinci-mcasp: Streamline pdir behavior across rx & tx streams
ASoC: ti: davinci-mcasp: Add asynchronous mode support
.../bindings/sound/davinci-mcasp-audio.yaml | 71 ++-
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 510 ++++++++++++++----
sound/soc/ti/davinci-mcasp.h | 10 +
4 files changed, 479 insertions(+), 115 deletions(-)
base-commit: dbf8fe85a16a33d6b6bd01f2bc606fc017771465
--
2.43.0
| On 30/01/2026 07:10, Sen Wang wrote:
True, the naming was not too precise. It is tasked to decide if the TX
clock needs to be enabled for RX operation, which precisely when McASP
is in synchronous mode _and_ it is clock provider.
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
bool enable)
*mcasp)
*mcasp)
!mcasp->streams) {
mcasp->streams)
davinci_mcasp *mcasp, int stream,
--
Péter | {
"author": "=?UTF-8?Q?P=C3=A9ter_Ujfalusi?= <peter.ujfalusi@gmail.com>",
"date": "Mon, 2 Feb 2026 18:42:20 +0200",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.
The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.
Bootlog and Async mode tests on AM62D-EVM: [0]
[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
Signed-off-by: Sen Wang <sen@ti.com>
Sen Wang (4):
dt-bindings: sound: davinci-mcasp: Add optional properties for asynchronous mode
ASoC: ti: davinci-mcasp: Disambiguate mcasp_is_synchronous function
ASoC: ti: davinci-mcasp: Streamline pdir behavior across rx & tx streams
ASoC: ti: davinci-mcasp: Add asynchronous mode support
.../bindings/sound/davinci-mcasp-audio.yaml | 71 ++-
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 510 ++++++++++++++----
sound/soc/ti/davinci-mcasp.h | 10 +
4 files changed, 479 insertions(+), 115 deletions(-)
base-commit: dbf8fe85a16a33d6b6bd01f2bc606fc017771465
--
2.43.0
| On 30/01/2026 07:10, Sen Wang wrote:
I'm not sure about this, but the sequence should be preserved, PDIR
change first.
--
Péter | {
"author": "=?UTF-8?Q?P=C3=A9ter_Ujfalusi?= <peter.ujfalusi@gmail.com>",
"date": "Mon, 2 Feb 2026 18:49:40 +0200",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.
The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.
Bootlog and Async mode tests on AM62D-EVM: [0]
[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
Signed-off-by: Sen Wang <sen@ti.com>
Sen Wang (4):
dt-bindings: sound: davinci-mcasp: Add optional properties for asynchronous mode
ASoC: ti: davinci-mcasp: Disambiguate mcasp_is_synchronous function
ASoC: ti: davinci-mcasp: Streamline pdir behavior across rx & tx streams
ASoC: ti: davinci-mcasp: Add asynchronous mode support
.../bindings/sound/davinci-mcasp-audio.yaml | 71 ++-
include/linux/platform_data/davinci_asp.h | 3 +-
sound/soc/ti/davinci-mcasp.c | 510 ++++++++++++++----
sound/soc/ti/davinci-mcasp.h | 10 +
4 files changed, 479 insertions(+), 115 deletions(-)
base-commit: dbf8fe85a16a33d6b6bd01f2bc606fc017771465
--
2.43.0
| On 30/01/2026 07:10, Sen Wang wrote:
static void mcasp_start_rx(struct davinci_mcasp *mcasp)
In new code - while it might not match with old code - use producer
instead of master.
Otherwise it looks nice, I trust you have tested the sync and DIT mode.
With this nitpick addressed:
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
--
Péter | {
"author": "=?UTF-8?Q?P=C3=A9ter_Ujfalusi?= <peter.ujfalusi@gmail.com>",
"date": "Mon, 2 Feb 2026 19:02:31 +0200",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH] sched_ext: Fix NULL pointer deref and warnings during scx teardown | When a BPF scheduler is being disabled, scx_root can be set to NULL
while tasks are still associated with the sched_ext class. If a task is
subject to an affinity change, priority adjustment, or policy switch
during this window, sched_class operations will dereference a NULL
scx_root pointer, triggering a BUG like the following:
BUG: kernel NULL pointer dereference, address: 00000000000001c0
...
RIP: 0010:set_cpus_allowed_scx+0x1a/0xa0
...
Call Trace:
__set_cpus_allowed_ptr_locked+0x142/0x1c0
__sched_setaffinity+0x72/0x100
sched_setaffinity+0x281/0x360
Similarly, tasks can be in various states, depending on the timing of
concurrent operations. This causes spurious WARN_ON_ONCE() triggers in
scx_disable_task() and invalid state transitions when tasks are switched
to or from the sched_ext class:
WARNING: kernel/sched/ext.c:3118 at scx_disable_task+0x7c/0x180
...
Call Trace:
sched_change_begin+0xf2/0x270
__sched_setscheduler+0x346/0xc70
Fix by:
- Adding NULL checks at the beginning of sched_class operations
(set_cpus_allowed_scx, reweight_task_scx, switching_to_scx) to skip
BPF scheduler notifications when scx_root is NULL.
- Making the state assertion in scx_disable_task() conditional and only
warn during normal operation. Add early return if task is not in
SCX_TASK_ENABLED state to make the function idempotent.
- In switched_from_scx(), check task state before calling
scx_disable_task() to avoid calling it on tasks in a transitional
state.
Fixes: d310fb4009689 ("sched_ext: Clean up scx_root usages")
Cc: stable@vger.kernel.org # v6.16+
Signed-off-by: Andrea Righi <arighi@nvidia.com>
---
kernel/sched/ext.c | 42 ++++++++++++++++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/kernel/sched/ext.c b/kernel/sched/ext.c
index afe28c04d5aa7..aae5c5141cf1e 100644
--- a/kernel/sched/ext.c
+++ b/kernel/sched/ext.c
@@ -2619,6 +2619,9 @@ static void set_cpus_allowed_scx(struct task_struct *p,
set_cpus_allowed_common(p, ac);
+ if (unlikely(!sch))
+ return;
+
/*
* The effective cpumask is stored in @p->cpus_ptr which may temporarily
* differ from the configured one in @p->cpus_mask. Always tell the bpf
@@ -2920,7 +2923,18 @@ static void scx_disable_task(struct task_struct *p)
struct rq *rq = task_rq(p);
lockdep_assert_rq_held(rq);
- WARN_ON_ONCE(scx_get_task_state(p) != SCX_TASK_ENABLED);
+
+ /*
+ * During disabling, tasks can be in various states due to
+ * concurrent operations, only warn about unexpected state during
+ * normal operation.
+ */
+ if (likely(scx_enable_state() != SCX_DISABLING))
+ WARN_ON_ONCE(scx_get_task_state(p) != SCX_TASK_ENABLED);
+
+ /* If task is not enabled, skip disable */
+ if (scx_get_task_state(p) != SCX_TASK_ENABLED)
+ return;
if (SCX_HAS_OP(sch, disable))
SCX_CALL_OP_TASK(sch, SCX_KF_REST, disable, rq, p);
@@ -3063,6 +3077,9 @@ static void reweight_task_scx(struct rq *rq, struct task_struct *p,
lockdep_assert_rq_held(task_rq(p));
+ if (unlikely(!sch))
+ return;
+
p->scx.weight = sched_weight_to_cgroup(scale_load_down(lw->weight));
if (SCX_HAS_OP(sch, set_weight))
SCX_CALL_OP_TASK(sch, SCX_KF_REST, set_weight, rq,
@@ -3077,6 +3094,21 @@ static void switching_to_scx(struct rq *rq, struct task_struct *p)
{
struct scx_sched *sch = scx_root;
+ /*
+ * We may race with a concurrent disable, skip enabling if scx_root
+ * is NULL or the task is in a transitional state.
+ */
+ if (unlikely(!sch || scx_enable_state() == SCX_DISABLING))
+ return;
+
+ /*
+ * Task might not be properly initialized if it's being switched to
+ * SCX after scx_init_task_enabled was set. Initialize to READY state
+ * first if needed.
+ */
+ if (scx_get_task_state(p) == SCX_TASK_NONE)
+ scx_set_task_state(p, SCX_TASK_READY);
+
scx_enable_task(p);
/*
@@ -3090,7 +3122,13 @@ static void switching_to_scx(struct rq *rq, struct task_struct *p)
static void switched_from_scx(struct rq *rq, struct task_struct *p)
{
- scx_disable_task(p);
+ /*
+ * Only disable if the task is actually enabled. During scheduler
+ * disabling, tasks might already be in READY state if they've been
+ * disabled by concurrent operations.
+ */
+ if (scx_get_task_state(p) == SCX_TASK_ENABLED)
+ scx_disable_task(p);
}
static void wakeup_preempt_scx(struct rq *rq, struct task_struct *p,int wake_flags) {}
--
2.52.0
| Hello,
On Mon, Feb 02, 2026 at 04:13:41PM +0100, Andrea Righi wrote:
I don't quite understand how this would happen. set_cpu_allowed_scx() is
called from do_set_cpus_allowed() with task_rq locked. ie. the task *has* to
be on sched_ext for it to be called. It's straightforward task rq lock
synchronization, so there's no race window.
Combined with the failures in switching_to_scx() and switched_form_scx(), I
wonder whether what's actually broken is more something like the disable
path missing some tasks?
Thanks.
--
tejun | {
"author": "Tejun Heo <tj@kernel.org>",
"date": "Mon, 2 Feb 2026 07:10:02 -1000",
"thread_id": "aYDaao9Xb_Bkv0NH@slm.duckdns.org.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| These parameters can be discovered from a config register. As they will
not be used any more, mark them deprecated, make them optional, and
remove them from the example.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
Documentation/devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/xlnx,i2s.yaml b/Documentation/devicetree/bindings/sound/xlnx,i2s.yaml
index 3c2b0be07c53..180f43f2b230 100644
--- a/Documentation/devicetree/bindings/sound/xlnx,i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/xlnx,i2s.yaml
@@ -29,6 +29,7 @@ properties:
enum:
- 16
- 24
+ deprecated: true
description: |
Sample data width.
@@ -36,14 +37,13 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 4
+ deprecated: true
description: |
Number of I2S streams.
required:
- compatible
- reg
- - xlnx,dwidth
- - xlnx,num-channels
additionalProperties: false
@@ -52,14 +52,10 @@ examples:
i2s@a0080000 {
compatible = "xlnx,i2s-receiver-1.0";
reg = <0xa0080000 0x10000>;
- xlnx,dwidth = <0x18>;
- xlnx,num-channels = <1>;
};
i2s@a0090000 {
compatible = "xlnx,i2s-transmitter-1.0";
reg = <0xa0090000 0x10000>;
- xlnx,dwidth = <0x18>;
- xlnx,num-channels = <1>;
};
...
--
2.35.1.1320.gc452695387.dirty | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:23:14 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++++++---------------------
1 file changed, 11 insertions(+), 21 deletions(-)
diff --git a/sound/soc/xilinx/xlnx_i2s.c b/sound/soc/xilinx/xlnx_i2s.c
index ca915a001ad5..a2b426376676 100644
--- a/sound/soc/xilinx/xlnx_i2s.c
+++ b/sound/soc/xilinx/xlnx_i2s.c
@@ -17,6 +17,9 @@
#define DRV_NAME "xlnx_i2s"
+#define I2S_CORE_CFG 0x04
+#define I2S_CORE_CFG_DATA_24BIT BIT(16)
+#define I2S_CORE_CFG_CHANNELS GENMASK(11, 8)
#define I2S_CORE_CTRL_OFFSET 0x08
#define I2S_CORE_CTRL_32BIT_LRCLK BIT(3)
#define I2S_CORE_CTRL_ENABLE BIT(0)
@@ -172,7 +175,7 @@ static int xlnx_i2s_probe(struct platform_device *pdev)
{
struct xlnx_i2s_drv_data *drv_data;
int ret;
- u32 format;
+ u32 format, cfg;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
@@ -184,27 +187,14 @@ static int xlnx_i2s_probe(struct platform_device *pdev)
if (IS_ERR(drv_data->base))
return PTR_ERR(drv_data->base);
- ret = of_property_read_u32(node, "xlnx,num-channels", &drv_data->channels);
- if (ret < 0) {
- dev_err(dev, "cannot get supported channels\n");
- return ret;
- }
- drv_data->channels *= 2;
-
- ret = of_property_read_u32(node, "xlnx,dwidth", &drv_data->data_width);
- if (ret < 0) {
- dev_err(dev, "cannot get data width\n");
- return ret;
- }
- switch (drv_data->data_width) {
- case 16:
- format = SNDRV_PCM_FMTBIT_S16_LE;
- break;
- case 24:
+ cfg = readl(drv_data->base + I2S_CORE_CFG);
+ drv_data->channels = FIELD_GET(I2S_CORE_CFG_CHANNELS, cfg);
+ if (cfg & I2S_CORE_CFG_DATA_24BIT) {
+ drv_data->data_width = 24;
format = SNDRV_PCM_FMTBIT_S24_LE;
- break;
- default:
- return -EINVAL;
+ } else {
+ drv_data->data_width = 16;
+ format = SNDRV_PCM_FMTBIT_S16_LE;
}
if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
--
2.35.1.1320.gc452695387.dirty | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:23:15 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| On Thu, Jan 29, 2026 at 12:23:15PM -0500, Sean Anderson wrote:
Given that the properties already exist it seems wise to continue to
parse them if available and prefer them over what we read from the
hardware, it would not shock me to discover that hardware exists where
the registers are inaccurate or need overriding due to bugs. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 17:27:58 +0000",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 29 Jan 2026 17:37:09 +0000",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| I don't know this device at all, so i might be asking dumb
questions....
It is possible that the device supports multiple channels, but the use
case is mono, and so xlnx,num-channels is 1 in DT? Would that break
given your change?
Could it be the device supports 24 bits, but the use case only wants
16, and so has this property set to 16?
Andrew | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Thu, 29 Jan 2026 18:37:30 +0100",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| On 1/29/26 12:27, Mark Brown wrote:
I would be surprised if such hardware exists. These properties are
automatically generated by Xilinx's tools based on the HDL core's
properties. This has a few consequences:
- They always exactly match the hardware unless someone has gone in and
modified them. I think this is unlikely in this case because they
directly reflect parameters that should not need to be adjusted.
- Driver authors tend to use them even when there are hardware registers
available with the same information, as Xilinx has not always been
consistent in adding such registers.
I am not aware of any errata regarding incorrect generation of
properties for this device or cases where the number of channels or bit
depth was incorrect.
--Sean | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:46:27 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| On 1/29/26 12:37, Andrew Lunn wrote:
drv_data->channels is multiplied by 2, so there is always an even number
of channels. Pairs of channels are always muxed together and AFAICT
there's no way to disable them individually.
I don't think that's possible. There's an option to output 32-bit audio,
but none to reduce 24-bit audio to 16 bit.
For some perspective, this is a soft core and these properties reflect
the configuration chosen when the core was built. The data path is fixed
and these devicetree properties exist to tell the driver how the core
was configured. If you set xlnx,dwidth to 16 and the core was configured
for 24-bit audio, you will silently get 24-bit audio (and the clocks
will be incorrect).
--Sean | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:51:47 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| On Thu, Jan 29, 2026 at 12:46:27PM -0500, Sean Anderson wrote:
I'm not sure I follow your second point - driver authors tend to use
what?
I'd still rather see the properties get used if present, worst case
they're redundant best case we avoid regressing a currently working
system. The code is already there, it just needs tweaking to make parse
failures non-fatal. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 18:09:28 +0000",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| On 1/29/26 13:09, Mark Brown wrote:
Authors look at the devicetree node and see something like
i2s0_tx: i2s_transmitter@80120000 {
aud_mclk = <99999001>;
clock-names = "aud_mclk", "s_axi_ctrl_aclk", "s_axis_aud_aclk";
clocks = <&zynqmp_clk 74>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
compatible = "xlnx,i2s-transmitter-1.0", "xlnx,i2s-transmitter-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 105 4>;
reg = <0x0 0x80120000 0x0 0x10000>;
xlnx,depth = <0x80>;
xlnx,dwidth = <0x18>;
xlnx,num-channels = <0x1>;
xlnx,snd-pcm = <&i2s0_dma>;
};
and go "Ah, there are the properties I need." On some Xilinx cores this
is the only way to discover certain properties, so people have gotten into
the habit of using them even when these properties can be read from the
device itself.
I would rather remove it for the code size reduction and simplication.
--Sean | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 13:17:45 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| On Thu, Jan 29, 2026 at 01:17:45PM -0500, Sean Anderson wrote:
Oh. If the properties are there it's reasonable and sensible to use
them, them being redundant is a concern when specifying the binding but
once things are there any discrepency should usually be resolved in
favour of the binding.
We're talking a couple of function calls with no error handling here,
I'm not sure anyone concerned about that kind of impact is running
Linux. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 18:46:23 +0000",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| On Thu, Jan 29, 2026 at 12:46:27PM -0500, Sean Anderson wrote:
Does version 0.0 of this IP core have this register? Its not a new
addition?
Is there a synthesis option to disable this register?
Andrew | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Thu, 29 Jan 2026 20:58:19 +0100",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| On 1/29/26 14:58, Andrew Lunn wrote:
As far as I know, this register was present in 1.0 revision 0. I
reviewed the changelog for the core as well as the product guide
changelog and found no mention of any register additions.
No.
--Sean | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 15:13:07 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| Hi Sean,
kernel test robot noticed the following build errors:
[auto build test ERROR on broonie-sound/for-next]
[also build test ERROR on broonie-spi/for-next linus/master v6.19-rc7 next-20260129]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sean-Anderson/dt-bindings-sound-xlnx-i2s-Make-discoverable-parameters-optional/20260130-012955
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
patch link: https://lore.kernel.org/r/20260129172315.3871602-3-sean.anderson%40linux.dev
patch subject: [PATCH 2/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers
config: sh-allyesconfig (https://download.01.org/0day-ci/archive/20260130/202601301436.qPUffKmd-lkp@intel.com/config)
compiler: sh4-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260130/202601301436.qPUffKmd-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601301436.qPUffKmd-lkp@intel.com/
All errors (new ones prefixed by >>):
sound/soc/xilinx/xlnx_i2s.c: In function 'xlnx_i2s_probe':
191 | drv_data->channels = FIELD_GET(I2S_CORE_CFG_CHANNELS, cfg);
| ^~~~~~~~~
vim +/FIELD_GET +191 sound/soc/xilinx/xlnx_i2s.c
173
174 static int xlnx_i2s_probe(struct platform_device *pdev)
175 {
176 struct xlnx_i2s_drv_data *drv_data;
177 int ret;
178 u32 format, cfg;
179 struct device *dev = &pdev->dev;
180 struct device_node *node = dev->of_node;
181
182 drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
183 if (!drv_data)
184 return -ENOMEM;
185
186 drv_data->base = devm_platform_ioremap_resource(pdev, 0);
187 if (IS_ERR(drv_data->base))
188 return PTR_ERR(drv_data->base);
189
190 cfg = readl(drv_data->base + I2S_CORE_CFG);
> 191 drv_data->channels = FIELD_GET(I2S_CORE_CFG_CHANNELS, cfg);
192 if (cfg & I2S_CORE_CFG_DATA_24BIT) {
193 drv_data->data_width = 24;
194 format = SNDRV_PCM_FMTBIT_S24_LE;
195 } else {
196 drv_data->data_width = 16;
197 format = SNDRV_PCM_FMTBIT_S16_LE;
198 }
199
200 if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
201 drv_data->dai_drv.name = "xlnx_i2s_playback";
202 drv_data->dai_drv.playback.stream_name = "Playback";
203 drv_data->dai_drv.playback.formats = format;
204 drv_data->dai_drv.playback.channels_min = drv_data->channels;
205 drv_data->dai_drv.playback.channels_max = drv_data->channels;
206 drv_data->dai_drv.playback.rates = SNDRV_PCM_RATE_8000_192000;
207 drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
208 } else if (of_device_is_compatible(node, "xlnx,i2s-receiver-1.0")) {
209 drv_data->dai_drv.name = "xlnx_i2s_capture";
210 drv_data->dai_drv.capture.stream_name = "Capture";
211 drv_data->dai_drv.capture.formats = format;
212 drv_data->dai_drv.capture.channels_min = drv_data->channels;
213 drv_data->dai_drv.capture.channels_max = drv_data->channels;
214 drv_data->dai_drv.capture.rates = SNDRV_PCM_RATE_8000_192000;
215 drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
216 } else {
217 return -ENODEV;
218 }
219 drv_data->is_32bit_lrclk = readl(drv_data->base + I2S_CORE_CTRL_OFFSET) &
220 I2S_CORE_CTRL_32BIT_LRCLK;
221
222 dev_set_drvdata(&pdev->dev, drv_data);
223
224 ret = devm_snd_soc_register_component(&pdev->dev, &xlnx_i2s_component,
225 &drv_data->dai_drv, 1);
226 if (ret) {
227 dev_err(&pdev->dev, "i2s component registration failed\n");
228 return ret;
229 }
230
231 dev_info(&pdev->dev, "%s DAI registered\n", drv_data->dai_drv.name);
232
233 return ret;
234 }
235
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Fri, 30 Jan 2026 14:35:30 +0800",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| +Katta, Vishal
On 1/29/26 19:46, Mark Brown wrote:
Let me add our driver owner of this device to answer some questions.
Katta: Can you please look at it?
Thanks,
Michal | {
"author": "Michal Simek <michal.simek@amd.com>",
"date": "Fri, 30 Jan 2026 09:19:26 +0100",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameters from registers
.../devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++------------
2 files changed, 13 insertions(+), 27 deletions(-)
--
2.35.1.1320.gc452695387.dirty
| Hi,
>> and go "Ah, there are the properties I need." On some Xilinx cores this
>> is the only way to discover certain properties, so people have gotten into
>> the habit of using them even when these properties can be read from the
>> device itself.
> Oh. If the properties are there it's reasonable and sensible to use
> them, them being redundant is a concern when specifying the binding but
> once things are there any discrepency should usually be resolved in
> favour of the binding.
I also think making the hardware registers take priority over the DTS
makes sense (E.G. what this patch does), as the DTS can get out of sync
with the (programmable) HW configuration if the FPGA config is changed
and a DTS update is forgotten.
>> I would rather remove it for the code size reduction and simplication.
> We're talking a couple of function calls with no error handling here,
> I'm not sure anyone concerned about that kind of impact is running
> Linux.
Agreed, but the HW registers should by definition always be in sync with
the IP block configuration, where the DTS update involves a manual
update so it may not, so the HW registers are more reliable than the DTS.
--
Bye, Peter Korsgaard | {
"author": "Peter Korsgaard <peter@korsgaard.com>",
"date": "Mon, 02 Feb 2026 18:52:27 +0100",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| The implementation of __READ_ONCE() under CONFIG_LTO=y incorrectly
qualified the fallback "once" access for types larger than 8 bytes,
which are not atomic but should still happen "once" and suppress common
compiler optimizations.
The cast `volatile typeof(__x)` applied the volatile qualifier to the
pointer type itself rather than the pointee. This created a volatile
pointer to a non-volatile type, which violated __READ_ONCE() semantics.
Fix this by casting to `volatile typeof(*__x) *`.
With a defconfig + LTO + debug options build, we see the following
functions to be affected:
xen_manage_runstate_time (884 -> 944 bytes)
xen_steal_clock (248 -> 340 bytes)
^-- use __READ_ONCE() to load vcpu_runstate_info structs
Fixes: e35123d83ee3 ("arm64: lto: Strengthen READ_ONCE() to acquire when CONFIG_LTO=y")
Cc: <stable@vger.kernel.org>
Reviewed-by: Boqun Feng <boqun@kernel.org>
Signed-off-by: Marco Elver <elver@google.com>
---
arch/arm64/include/asm/rwonce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/rwonce.h b/arch/arm64/include/asm/rwonce.h
index 78beceec10cd..fc0fb42b0b64 100644
--- a/arch/arm64/include/asm/rwonce.h
+++ b/arch/arm64/include/asm/rwonce.h
@@ -58,7 +58,7 @@
default: \
atomic = 0; \
} \
- atomic ? (typeof(*__x))__u.__val : (*(volatile typeof(__x))__x);\
+ atomic ? (typeof(*__x))__u.__val : (*(volatile typeof(*__x) *)__x);\
})
#endif /* !BUILD_VDSO */
--
2.53.0.rc1.225.gd81095ad13-goog | {
"author": "Marco Elver <elver@google.com>",
"date": "Fri, 30 Jan 2026 14:28:24 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| Rework arm64 LTO __READ_ONCE() to improve code generation as follows:
1. Replace _Generic-based __unqual_scalar_typeof() with more complete
__rwonce_typeof_unqual(). This strips qualifiers from all types, not
just integer types, which is required to be able to assign (must be
non-const) to __u.__val in the non-atomic case (required for #2).
Once our minimum compiler versions are bumped, this just becomes
TYPEOF_UNQUAL() (or typeof_unqual() should we decide to adopt C23
naming). Sadly the fallback version of __rwonce_typeof_unqual() cannot
be used as a general TYPEOF_UNQUAL() fallback (see code comments).
One subtle point here is that non-integer types of __val could be const
or volatile within the union with the old __unqual_scalar_typeof(), if
the passed variable is const or volatile. This would then result in a
forced load from the stack if __u.__val is volatile; in the case of
const, it does look odd if the underlying storage changes, but the
compiler is told said member is "const" -- it smells like UB.
2. Eliminate the atomic flag and ternary conditional expression. Move
the fallback volatile load into the default case of the switch,
ensuring __u is unconditionally initialized across all paths.
The statement expression now unconditionally returns __u.__val.
This refactoring appears to help the compiler improve (or fix) code
generation.
With a defconfig + LTO + debug options builds, we observe different
codegen for the following functions:
btrfs_reclaim_sweep (708 -> 1032 bytes)
btrfs_sinfo_bg_reclaim_threshold_store (200 -> 204 bytes)
check_mem_access (3652 -> 3692 bytes) [inlined bpf_map_is_rdonly]
console_flush_all (1268 -> 1264 bytes)
console_lock_spinning_disable_and_check (180 -> 176 bytes)
igb_add_filter (640 -> 636 bytes)
igb_config_tx_modes (2404 -> 2400 bytes)
kvm_vcpu_on_spin (480 -> 476 bytes)
map_freeze (376 -> 380 bytes)
netlink_bind (1664 -> 1656 bytes)
nmi_cpu_backtrace (404 -> 400 bytes)
set_rps_cpu (516 -> 520 bytes)
swap_cluster_readahead (944 -> 932 bytes)
tcp_accecn_third_ack (328 -> 336 bytes)
tcp_create_openreq_child (1764 -> 1772 bytes)
tcp_data_queue (5784 -> 5892 bytes)
tcp_ecn_rcv_synack (620 -> 628 bytes)
xen_manage_runstate_time (944 -> 896 bytes)
xen_steal_clock (340 -> 296 bytes)
Increase of some functions are due to more aggressive inlining due to
better codegen (in this build, e.g. bpf_map_is_rdonly is no longer
present due to being inlined completely).
Signed-off-by: Marco Elver <elver@google.com>
---
v3:
* Comment.
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
---
arch/arm64/include/asm/rwonce.h | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/rwonce.h b/arch/arm64/include/asm/rwonce.h
index fc0fb42b0b64..42c9e8429274 100644
--- a/arch/arm64/include/asm/rwonce.h
+++ b/arch/arm64/include/asm/rwonce.h
@@ -19,6 +19,20 @@
"ldapr" #sfx "\t" #regs, \
ARM64_HAS_LDAPR)
+#ifdef USE_TYPEOF_UNQUAL
+#define __rwonce_typeof_unqual(x) TYPEOF_UNQUAL(x)
+#else
+/*
+ * Fallback for older compilers (Clang < 19).
+ *
+ * Uses the fact that, for all supported Clang versions, 'auto' correctly drops
+ * qualifiers. Unlike typeof_unqual(), the type must be completely defined, i.e.
+ * no forward-declared struct pointer dereferences. The array-to-pointer decay
+ * case does not matter for usage in READ_ONCE() either.
+ */
+#define __rwonce_typeof_unqual(x) typeof(({ auto ____t = (x); ____t; }))
+#endif
+
/*
* When building with LTO, there is an increased risk of the compiler
* converting an address dependency headed by a READ_ONCE() invocation
@@ -32,8 +46,7 @@
#define __READ_ONCE(x) \
({ \
typeof(&(x)) __x = &(x); \
- int atomic = 1; \
- union { __unqual_scalar_typeof(*__x) __val; char __c[1]; } __u; \
+ union { __rwonce_typeof_unqual(*__x) __val; char __c[1]; } __u; \
switch (sizeof(x)) { \
case 1: \
asm volatile(__LOAD_RCPC(b, %w0, %1) \
@@ -56,9 +69,9 @@
: "Q" (*__x) : "memory"); \
break; \
default: \
- atomic = 0; \
+ __u.__val = *(volatile typeof(*__x) *)__x; \
} \
- atomic ? (typeof(*__x))__u.__val : (*(volatile typeof(*__x) *)__x);\
+ __u.__val; \
})
#endif /* !BUILD_VDSO */
--
2.53.0.rc1.225.gd81095ad13-goog | {
"author": "Marco Elver <elver@google.com>",
"date": "Fri, 30 Jan 2026 14:28:25 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| When enabling Clang's Context Analysis (aka. Thread Safety Analysis) on
kernel/futex/core.o (see Peter's changes at [1]), in arm64 LTO builds we
could see:
| kernel/futex/core.c:982:1: warning: spinlock 'atomic ? __u.__val : q->lock_ptr' is still held at the end of function [-Wthread-safety-analysis]
| 982 | }
| | ^
| kernel/futex/core.c:976:2: note: spinlock acquired here
| 976 | spin_lock(lock_ptr);
| | ^
| kernel/futex/core.c:982:1: warning: expecting spinlock 'q->lock_ptr' to be held at the end of function [-Wthread-safety-analysis]
| 982 | }
| | ^
| kernel/futex/core.c:966:6: note: spinlock acquired here
| 966 | void futex_q_lockptr_lock(struct futex_q *q)
| | ^
| 2 warnings generated.
Where we have:
extern void futex_q_lockptr_lock(struct futex_q *q) __acquires(q->lock_ptr);
..
void futex_q_lockptr_lock(struct futex_q *q)
{
spinlock_t *lock_ptr;
/*
* See futex_unqueue() why lock_ptr can change.
*/
guard(rcu)();
retry:
spin_lock(lock_ptr);
...
}
At the time of the above report (prior to removal of the 'atomic' flag),
Clang Thread Safety Analysis's alias analysis resolved 'lock_ptr' to
'atomic ? __u.__val : q->lock_ptr' (now just '__u.__val'), and used
this as the identity of the context lock given it cannot "see through"
the inline assembly; however, we want 'q->lock_ptr' as the canonical
context lock.
While for code generation the compiler simplified to '__u.__val' for
pointers (8 byte case -> 'atomic' was set), TSA's analysis (a) happens
much earlier on the AST, and (b) would be the wrong deduction.
Now that we've gotten rid of the 'atomic' ternary comparison, we can
return '__u.__val' through a pointer that we initialize with '&x', but
then update via a pointer-to-pointer. When READ_ONCE()'ing a context
lock pointer, TSA's alias analysis does not invalidate the initial alias
when updated through the pointer-to-pointer, and we make it effectively
"see through" the __READ_ONCE().
Code generation is unchanged.
Link: https://lkml.kernel.org/r/20260121110704.221498346@infradead.org [1]
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202601221040.TeM0ihff-lkp@intel.com/
Cc: Peter Zijlstra <peterz@infradead.org>
Tested-by: Boqun Feng <boqun@kernel.org>
Signed-off-by: Marco Elver <elver@google.com>
---
v3:
* Use 'typeof(*__ret)'.
* Commit message.
v2:
* Rebase.
---
arch/arm64/include/asm/rwonce.h | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/rwonce.h b/arch/arm64/include/asm/rwonce.h
index 42c9e8429274..b7de74d4bf07 100644
--- a/arch/arm64/include/asm/rwonce.h
+++ b/arch/arm64/include/asm/rwonce.h
@@ -45,8 +45,12 @@
*/
#define __READ_ONCE(x) \
({ \
- typeof(&(x)) __x = &(x); \
- union { __rwonce_typeof_unqual(*__x) __val; char __c[1]; } __u; \
+ auto __x = &(x); \
+ auto __ret = (__rwonce_typeof_unqual(*__x) *)__x; \
+ /* Hides alias reassignment from Clang's -Wthread-safety. */ \
+ auto __retp = &__ret; \
+ union { typeof(*__ret) __val; char __c[1]; } __u; \
+ *__retp = &__u.__val; \
switch (sizeof(x)) { \
case 1: \
asm volatile(__LOAD_RCPC(b, %w0, %1) \
@@ -71,7 +75,7 @@
default: \
__u.__val = *(volatile typeof(*__x) *)__x; \
} \
- __u.__val; \
+ *__ret; \
})
#endif /* !BUILD_VDSO */
--
2.53.0.rc1.225.gd81095ad13-goog | {
"author": "Marco Elver <elver@google.com>",
"date": "Fri, 30 Jan 2026 14:28:26 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| On Fri, 30 Jan 2026 14:28:24 +0100
Marco Elver <elver@google.com> wrote:
I found this in some testing (on godbolt), so:
Tested-by: David Laight <david.laight.linux@gmail.com> | {
"author": "David Laight <david.laight.linux@gmail.com>",
"date": "Fri, 30 Jan 2026 15:06:58 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| On Fri, 30 Jan 2026 14:28:25 +0100
Marco Elver <elver@google.com> wrote:
Having most of the comment in the commit message and a short one in the
code look good.
I think it will also fix a 'bleat' from min() about a signed v unsigned compare.
The ?: causes 'u8' to be promoted to 'int' with the expected outcome.
Reviewed-by: David Laight <david.laight.linux>@gmail.com | {
"author": "David Laight <david.laight.linux@gmail.com>",
"date": "Fri, 30 Jan 2026 15:11:30 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| On Fri, 30 Jan 2026 14:28:26 +0100
Marco Elver <elver@google.com> wrote:
LGTM (for an obscure definition of G).
Reviewed-by: David Laight <david.laight.linux@gmail.com> | {
"author": "David Laight <david.laight.linux@gmail.com>",
"date": "Fri, 30 Jan 2026 15:13:34 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| On Fri, Jan 30, 2026 at 02:28:25PM +0100, Marco Elver wrote:
I know that CONFIG_LTO practically depends on Clang, but it's a bit
grotty relying on that assumption here. Ideally, it would be
straightforward to enable the strong READ_ONCE() semantics on arm64
regardless of the compiler.
Since we're not providing acquire semantics for the non-atomic case,
what we really want is the generic definition of __READ_ONCE() from
include/asm-generic/rwonce.h here. The header inclusion mess prevents
that, but why can't we just inline that definition here for the
'default' case? If TYPEOF_UNQUAL() leads to better codegen, shouldn't
we use that to implement __unqual_scalar_typeof() when it is available?
I fear I'm missing something here, but it just feels like we're
optimising a pretty niche case (arm64 + LTO + non-atomic __READ_ONCE())
in a way that looks more generally applicable.
Will | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 15:36:40 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| On Fri, Jan 30, 2026 at 02:28:26PM +0100, Marco Elver wrote:
What does GCC do with this? :/
Will | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 15:39:36 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| On Mon, Feb 02, 2026 at 03:36:40PM +0000, Will Deacon wrote:
We are?
---
commit fd69b2f7d5f4e1d89cea4cdfa6f15e7fa53d8358
Author: Peter Zijlstra <peterz@infradead.org>
Date: Fri Jan 16 19:18:16 2026 +0100
compiler: Use __typeof_unqual__() for __unqual_scalar_typeof()
The recent changes to get_unaligned() resulted in a new sparse warning:
net/rds/ib_cm.c:96:35: sparse: sparse: incorrect type in argument 1 (different modifiers) @@ expected void * @@ got restricted __be64 const * @@
net/rds/ib_cm.c:96:35: sparse: expected void *
net/rds/ib_cm.c:96:35: sparse: got restricted __be64 const *
The updated get_unaligned_t() uses __unqual_scalar_typeof() to get an
unqualified type. This works correctly for the compilers, but fails for
sparse when the data type is __be64 (or any other __beNN variant).
On sparse runs (C=[12]) __beNN types are annotated with
__attribute__((bitwise)).
That annotation allows sparse to detect incompatible operations on __beNN
variables, but it also prevents sparse from evaluating the _Generic() in
__unqual_scalar_typeof() and map __beNN to a unqualified scalar type, so it
ends up with the default, i.e. the original qualified type of a 'const
__beNN' pointer. That then ends up as the first pointer argument to
builtin_memcpy(), which obviously causes the above sparse warnings.
The sparse git tree supports typeof_unqual() now, which allows to use it
instead of the _Generic() based __unqual_scalar_typeof(). With that sparse
correctly evaluates the unqualified type and keeps the __beNN logic intact.
The downside is that this requires a top of tree sparse build and an old
sparse version will emit a metric ton of incomprehensible error messages
before it dies with a segfault.
Therefore implement a sanity check which validates that the checker is
available and capable of handling typeof_unqual(). Emit a warning if not so
the user can take informed action.
[ tglx: Move the evaluation of USE_TYPEOF_UNQUAL to compiler_types.h so it is
set before use and implement the sanity checker ]
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Link: https://patch.msgid.link/87ecnp2zh3.ffs@tglx
Closes: https://lore.kernel.org/oe-kbuild-all/202601150001.sKSN644a-lkp@intel.com/
diff --git a/Makefile b/Makefile
index 9d38125263fb..179c9d9a56dd 100644
--- a/Makefile
+++ b/Makefile
@@ -1187,6 +1187,14 @@ CHECKFLAGS += $(if $(CONFIG_CPU_BIG_ENDIAN),-mbig-endian,-mlittle-endian)
# the checker needs the correct machine size
CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32)
+# Validate the checker is available and functional
+ifneq ($(KBUILD_CHECKSRC), 0)
+ ifneq ($(shell $(srctree)/scripts/checker-valid.sh $(CHECK) $(CHECKFLAGS)), 1)
+ $(warning C=$(KBUILD_CHECKSRC) specified, but $(CHECK) is not available or not up to date)
+ KBUILD_CHECKSRC = 0
+ endif
+endif
+
# Default kernel image to build when no specific target is given.
# KBUILD_IMAGE may be overruled on the command line or
# set in the environment
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 04487c9bd751..c601222b495a 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -230,16 +230,6 @@ void ftrace_likely_update(struct ftrace_likely_data *f, int val,
__BUILD_BUG_ON_ZERO_MSG(!__is_noncstr(p), \
"must be non-C-string (not NUL-terminated)")
-/*
- * Use __typeof_unqual__() when available.
- *
- * XXX: Remove test for __CHECKER__ once
- * sparse learns about __typeof_unqual__().
- */
-#if CC_HAS_TYPEOF_UNQUAL && !defined(__CHECKER__)
-# define USE_TYPEOF_UNQUAL 1
-#endif
-
/*
* Define TYPEOF_UNQUAL() to use __typeof_unqual__() as typeof
* operator when available, to return an unqualified type of the exp.
diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h
index d3318a3c2577..377df1e64096 100644
--- a/include/linux/compiler_types.h
+++ b/include/linux/compiler_types.h
@@ -562,6 +562,14 @@ struct ftrace_likely_data {
#define asm_inline asm
#endif
+#ifndef __ASSEMBLY__
+/*
+ * Use __typeof_unqual__() when available.
+ */
+#if CC_HAS_TYPEOF_UNQUAL || defined(__CHECKER__)
+# define USE_TYPEOF_UNQUAL 1
+#endif
+
/* Are two types/vars the same type (ignoring qualifiers)? */
#define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
@@ -569,6 +577,7 @@ struct ftrace_likely_data {
* __unqual_scalar_typeof(x) - Declare an unqualified scalar type, leaving
* non-scalar types unchanged.
*/
+#ifndef USE_TYPEOF_UNQUAL
/*
* Prefer C11 _Generic for better compile-times and simpler code. Note: 'char'
* is not type-compatible with 'signed char', and we define a separate case.
@@ -586,6 +595,10 @@ struct ftrace_likely_data {
__scalar_type_to_expr_cases(long), \
__scalar_type_to_expr_cases(long long), \
default: (x)))
+#else
+#define __unqual_scalar_typeof(x) __typeof_unqual__(x)
+#endif
+#endif /* !__ASSEMBLY__ */
/* Is this type a native word size -- useful for atomic operations */
#define __native_word(t) \
diff --git a/scripts/checker-valid.sh b/scripts/checker-valid.sh
new file mode 100755
index 000000000000..625a789ed1c8
--- /dev/null
+++ b/scripts/checker-valid.sh
@@ -0,0 +1,19 @@
+#!/bin/sh -eu
+# SPDX-License-Identifier: GPL-2.0
+
+[ ! -x "$(command -v "$1")" ] && exit 1
+
+tmp_file=$(mktemp)
+trap "rm -f $tmp_file" EXIT
+
+cat << EOF >$tmp_file
+static inline int u(const int *q)
+{
+ __typeof_unqual__(*q) v = *q;
+ return v;
+}
+EOF
+
+# sparse happily exits with 0 on error so validate
+# there is none on stderr. Use awk as grep is a pain with sh -e
+$@ $tmp_file 2>&1 | awk -v c=1 '/error/{c=0}END{print c}' | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Mon, 2 Feb 2026 17:01:39 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| On Mon, Feb 02, 2026 at 05:01:39PM +0100, Peter Zijlstra wrote:
Great! Then I don't grok why we need to choose between
__unqual_scalar_typeof() and __typeof_unqual__() in the arch code. We
should just use the former and it will DTRT.
Will | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 16:05:38 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
Patch 1 fixes a bug where READ_ONCE() on types larger than 8 bytes (non-atomic
fallback) incorrectly qualified the pointer rather than the pointee as volatile.
This resulted in a lack of "once" semantics for large struct loads.
Patch 2 refactors the macro to use __rwonce_typeof_unqual() and
eliminates the ternary conditional.
Building on the refactor, patch 3 fixes the context analysis false positive, by
helping its alias analysis "see through" the __READ_ONCE despite the inline asm.
## Note on Alternative for Patch 3
An alternative considered for the Context Analysis fix was introducing a helper
function to redirect the pointer alias; specifically passing a pointer to
const-pointer does not invalidate an alias either (casting away the const is a
deliberate escape hatch, albeit somewhat unusual looking). This approach was
slightly more verbose, so the simpler approach was chosen for now. It is
preserved here for future reference in case we need it for something else:
static __always_inline void __set_pointer_opaque(void *const *dst, const void *val)
{
*(void **)dst = (void *)val;
}
...
__set_pointer_opaque((void *const *)&__ret, &__u.__val);
...
[1] https://docs.kernel.org/next/dev-tools/context-analysis.html
[2] https://lore.kernel.org/all/202601221040.TeM0ihff-lkp@intel.com/
---
v3:
* Comments-smithing.
* Use 'typeof(*__ret) __val'
v2:
* Add __rwonce_typeof_unqual() as fallback for old compilers.
Marco Elver (3):
arm64: Fix non-atomic __READ_ONCE() with CONFIG_LTO=y
arm64: Optimize __READ_ONCE() with CONFIG_LTO=y
arm64, compiler-context-analysis: Permit alias analysis through
__READ_ONCE() with CONFIG_LTO=y
arch/arm64/include/asm/rwonce.h | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.53.0.rc1.225.gd81095ad13-goog
| On Mon, Feb 02, 2026 at 03:36:40PM +0000, Will Deacon wrote:
Does it matter for GCC versions that do not support LTO? Because I'm
quite sure that if, one day, we add support for GCC LTO, that GCC
version will be new enough that it'll just take the __typeof_unqual__()
version and it'll "just work".
The problem with older GCC versions was that their __auto_type did not
actually strip qualifiers (which it should have) -- this was fixed at
some point.
On Mon, Feb 02, 2026 at 04:05PM +0000, Will Deacon wrote:
The old __unqual_scalar_typeof() is still broken where
__typeof_unqual__() is unavailable - for the arm64 + LTO case that'd be
Clang <= 18, which we still have to support.
We could probably just ignore the performance issue ('volatile' reload
from stack, rare enough though given volatile variables are not usually
allowed) for these older versions and just say "use the newer compiler
to get better perf", but the 'const' issue will break the build:
| --- a/arch/arm64/include/asm/rwonce.h
| +++ b/arch/arm64/include/asm/rwonce.h
| @@ -46,7 +46,7 @@
| #define __READ_ONCE(x) \
| ({ \
| auto __x = &(x); \
| - auto __ret = (__rwonce_typeof_unqual(*__x) *)__x; \
| + auto __ret = (__unqual_scalar_typeof(*__x) *)__x; \
| /* Hides alias reassignment from Clang's -Wthread-safety. */ \
| auto __retp = &__ret; \
| union { typeof(*__ret) __val; char __c[1]; } __u; \
Results in:
| In file included from arch/arm64/kernel/asm-offsets.c:11:
| In file included from ./include/linux/arm_sdei.h:8:
| In file included from ./include/acpi/ghes.h:5:
| In file included from ./include/acpi/apei.h:9:
| In file included from ./include/linux/acpi.h:15:
| In file included from ./include/linux/device.h:32:
| In file included from ./include/linux/device/driver.h:21:
| In file included from ./include/linux/module.h:20:
| In file included from ./include/linux/elf.h:6:
| In file included from ./arch/arm64/include/asm/elf.h:141:
| ./include/linux/fs.h:1344:9: error: cannot assign to non-static data member '__val' with const-qualified type 'typeof (*__ret)' (aka 'struct fown_struct *const')
| 1344 | return READ_ONCE(file->f_owner);
| | ^~~~~~~~~~~~~~~~~~~~~~~~
| ./include/asm-generic/rwonce.h:50:2: note: expanded from macro 'READ_ONCE'
| 50 | __READ_ONCE(x); \
| | ^~~~~~~~~~~~~~
| ./arch/arm64/include/asm/rwonce.h:76:13: note: expanded from macro '__READ_ONCE'
| 76 | __u.__val = *(volatile typeof(*__x) *)__x; \
| | ~~~~~~~~~ ^
| ./include/linux/fs.h:1344:9: note: non-static data member '__val' declared const here
| 1344 | return READ_ONCE(file->f_owner);
| | ^~~~~~~~~~~~~~~~~~~~~~~~
| ./include/asm-generic/rwonce.h:50:2: note: expanded from macro 'READ_ONCE'
| 50 | __READ_ONCE(x); \
| | ^~~~~~~~~~~~~~
| ./arch/arm64/include/asm/rwonce.h:52:25: note: expanded from macro '__READ_ONCE'
| 52 | union { typeof(*__ret) __val; char __c[1]; } __u; \
| | ~~~~~~~~~~~~~~~^~~~~
... and many many more such errors.
It's an unfortunate mess today, but I hope sooner than later we bump the
minimum compiler versions that we can just unconditionally use
__typeof_unqual__() and delete __unqual_scalar_typeof(),
__rwonce_typeof_unqual() workaround and all the other code that appears
to be conditional on USE_TYPEOF_UNQUAL:
% git grep USE_TYPEOF_UNQUAL
arch/x86/include/asm/percpu.h:#if defined(CONFIG_USE_X86_SEG_SUPPORT) && defined(USE_TYPEOF_UNQUAL) | {
"author": "Marco Elver <elver@google.com>",
"date": "Mon, 2 Feb 2026 18:48:47 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH 0/2] Add HPET NMI Watchdog support | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anything looks abnormal, such as split
locks.
That makes PMCs a precious resource. So any PMC we can free up is a PMC
we can use for something useful. That made me look at the NMI watchdog.
The PMC based NMI watchdog implementation does not actually need any
performance counting. It just needs a per-CPU NMI timer source. X86
systems can make anything that emits an interrupt descriptor (IOAPIC,
MSI(-X), etc) become an NMI source. So any time goes. Including the
HPET. And while they can't really operate per-CPU, in almost all cases
you only really want the NMI on *all* CPUs, rather than per-CPU.
So I took a stab at building an HPET based NMI watchdog. In my (QEMU
based) testing, it's fully functional and can successfully detect when
CPUs get stuck. It even survives suspend/resume cycles.
For now, its enablement is a config time option because the hardlockup
framework does not support dynamic switching of multiple detectors.
That's ok for our use case. But maybe something for the interested
reader to tackle eventually :).
You can enable the HPET watchdog by default by setting
CONFIG_HARDLOCKUP_DETECTOR_HPET_DEFAULT=y
or passing "hpet=watchdog" to the kernel command line. When active, it
will emit a kernel log message to indicate it works:
[ 0.179176] hpet: HPET watchdog initialized on timer 0, GSI 2
The HPET can only be in either watchdog or generic mode. I am a bit
worried about IO-APIC pin allocation logic, so I opted to reuse the
generic timer pin. And that means I'm effectively breaking the normal
interrupt delivery path. so the easy way out was to say when watchdog is
active, PIT and HPET are not available as timer sources. Which is ok on
modern systems. There are way too many (unreliable) timer sources on x86
already. Trimming a few surely won't hurt.
I'm open to inputs on how to make the HPET multi-purpose though, in case
anyone feels strongly about it.
Alex
Alexander Graf (2):
x86/ioapic: Add NMI delivery configuration helper
hpet: Add HPET-based NMI watchdog support
.../admin-guide/kernel-parameters.txt | 5 +-
arch/x86/Kconfig | 19 ++
arch/x86/include/asm/io_apic.h | 2 +
arch/x86/kernel/apic/io_apic.c | 32 ++++
arch/x86/kernel/hpet.c | 172 ++++++++++++++++++
arch/x86/kernel/i8253.c | 9 +
drivers/char/hpet.c | 3 +
include/linux/hpet.h | 14 ++
8 files changed, 255 insertions(+), 1 deletion(-)
--
2.47.1
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597
| The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anything looks abnormal, such as split
locks.
That makes PMCs a precious resource. So any PMC we can free up is a PMC
we can use for something useful. That made me look at the NMI watchdog.
The PMC based NMI watchdog implementation does not actually need any
performance counting. It just needs a per-CPU NMI timer source. X86
systems can make anything that emits an interrupt descriptor (IOAPIC,
MSI(-X), etc) become an NMI source. So any time goes. Including the
HPET. And while they can't really operate per-CPU, in almost all cases
you only really want the NMI on *all* CPUs, rather than per-CPU.
So I took a stab at building an HPET based NMI watchdog. In my (QEMU
based) testing, it's fully functional and can successfully detect when
CPUs get stuck. It even survives suspend/resume cycles.
For now, its enablement is a config time option because the hardlockup
framework does not support dynamic switching of multiple detectors.
That's ok for our use case. But maybe something for the interested
reader to tackle eventually :).
You can enable the HPET watchdog by default by setting
CONFIG_HARDLOCKUP_DETECTOR_HPET_DEFAULT=y
or passing "hpet=watchdog" to the kernel command line. When active, it
will emit a kernel log message to indicate it works:
[ 0.179176] hpet: HPET watchdog initialized on timer 0, GSI 2
The HPET can only be in either watchdog or generic mode. I am a bit
worried about IO-APIC pin allocation logic, so I opted to reuse the
generic timer pin. And that means I'm effectively breaking the normal
interrupt delivery path. so the easy way out was to say when watchdog is
active, PIT and HPET are not available as timer sources. Which is ok on
modern systems. There are way too many (unreliable) timer sources on x86
already. Trimming a few surely won't hurt.
I'm open to inputs on how to make the HPET multi-purpose though, in case
anyone feels strongly about it.
Alex
Alexander Graf (2):
x86/ioapic: Add NMI delivery configuration helper
hpet: Add HPET-based NMI watchdog support
.../admin-guide/kernel-parameters.txt | 5 +-
arch/x86/Kconfig | 19 ++
arch/x86/include/asm/io_apic.h | 2 +
arch/x86/kernel/apic/io_apic.c | 32 ++++
arch/x86/kernel/hpet.c | 172 ++++++++++++++++++
arch/x86/kernel/i8253.c | 9 +
drivers/char/hpet.c | 3 +
include/linux/hpet.h | 14 ++
8 files changed, 255 insertions(+), 1 deletion(-)
--
2.47.1
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597 | {
"author": "Alexander Graf <graf@amazon.com>",
"date": "Mon, 2 Feb 2026 17:48:01 +0000",
"thread_id": "20260202174803.66640-1-graf@amazon.com.mbox.gz"
} |
lkml | [PATCH 0/2] Add HPET NMI Watchdog support | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anything looks abnormal, such as split
locks.
That makes PMCs a precious resource. So any PMC we can free up is a PMC
we can use for something useful. That made me look at the NMI watchdog.
The PMC based NMI watchdog implementation does not actually need any
performance counting. It just needs a per-CPU NMI timer source. X86
systems can make anything that emits an interrupt descriptor (IOAPIC,
MSI(-X), etc) become an NMI source. So any time goes. Including the
HPET. And while they can't really operate per-CPU, in almost all cases
you only really want the NMI on *all* CPUs, rather than per-CPU.
So I took a stab at building an HPET based NMI watchdog. In my (QEMU
based) testing, it's fully functional and can successfully detect when
CPUs get stuck. It even survives suspend/resume cycles.
For now, its enablement is a config time option because the hardlockup
framework does not support dynamic switching of multiple detectors.
That's ok for our use case. But maybe something for the interested
reader to tackle eventually :).
You can enable the HPET watchdog by default by setting
CONFIG_HARDLOCKUP_DETECTOR_HPET_DEFAULT=y
or passing "hpet=watchdog" to the kernel command line. When active, it
will emit a kernel log message to indicate it works:
[ 0.179176] hpet: HPET watchdog initialized on timer 0, GSI 2
The HPET can only be in either watchdog or generic mode. I am a bit
worried about IO-APIC pin allocation logic, so I opted to reuse the
generic timer pin. And that means I'm effectively breaking the normal
interrupt delivery path. so the easy way out was to say when watchdog is
active, PIT and HPET are not available as timer sources. Which is ok on
modern systems. There are way too many (unreliable) timer sources on x86
already. Trimming a few surely won't hurt.
I'm open to inputs on how to make the HPET multi-purpose though, in case
anyone feels strongly about it.
Alex
Alexander Graf (2):
x86/ioapic: Add NMI delivery configuration helper
hpet: Add HPET-based NMI watchdog support
.../admin-guide/kernel-parameters.txt | 5 +-
arch/x86/Kconfig | 19 ++
arch/x86/include/asm/io_apic.h | 2 +
arch/x86/kernel/apic/io_apic.c | 32 ++++
arch/x86/kernel/hpet.c | 172 ++++++++++++++++++
arch/x86/kernel/i8253.c | 9 +
drivers/char/hpet.c | 3 +
include/linux/hpet.h | 14 ++
8 files changed, 255 insertions(+), 1 deletion(-)
--
2.47.1
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597
| To implement an HPET based NMI watchdog, the HPET code will need to
reconfigure an IOAPIC pin to NMI mode. Add a function that allows driver
code to configure an IOAPIC pin for NMI delivery mode.
The caller can choose whether to invoke NMIs on the BSP or broadcast on
all CPUs in the system.
(Disclaimer: Some of this code was written with the help of Kiro, an AI
coding assistant)
Signed-off-by: Alexander Graf <graf@amazon.com>
---
arch/x86/include/asm/io_apic.h | 2 ++
arch/x86/kernel/apic/io_apic.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 0d806513c4b3..58cfb338bf39 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -158,6 +158,8 @@ extern void mp_save_irq(struct mpc_intsrc *m);
extern void disable_ioapic_support(void);
+extern int ioapic_set_nmi(u32 gsi, bool broadcast);
+
extern void __init io_apic_init_mappings(void);
extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
extern void native_restore_boot_irq_mode(void);
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 28f934f05a85..5b303e5d2f3f 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -2951,6 +2951,38 @@ int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
return (int)(long)domain->host_data;
}
+/**
+ * ioapic_set_nmi - Configure an IOAPIC pin for NMI delivery
+ * @gsi: Global System Interrupt number
+ * @broadcast: true to broadcast to all CPUs, false to send to CPU 0 only
+ *
+ * Configures the specified GSI for NMI delivery mode.
+ *
+ * Returns 0 on success, negative error code on failure.
+ */
+int ioapic_set_nmi(u32 gsi, bool broadcast)
+{
+ struct IO_APIC_route_entry entry = { };
+ int ioapic_idx, pin;
+
+ ioapic_idx = mp_find_ioapic(gsi);
+ if (ioapic_idx < 0)
+ return -ENODEV;
+
+ pin = mp_find_ioapic_pin(ioapic_idx, gsi);
+ if (pin < 0)
+ return -ENODEV;
+
+ entry.delivery_mode = APIC_DELIVERY_MODE_NMI;
+ entry.destid_0_7 = broadcast ? 0xFF : boot_cpu_physical_apicid;
+ entry.dest_mode_logical = 0;
+ entry.masked = 0;
+
+ ioapic_write_entry(ioapic_idx, pin, entry);
+
+ return 0;
+}
+
const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
.alloc = mp_irqdomain_alloc,
.free = mp_irqdomain_free,
--
2.47.1
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597 | {
"author": "Alexander Graf <graf@amazon.com>",
"date": "Mon, 2 Feb 2026 17:48:02 +0000",
"thread_id": "20260202174803.66640-1-graf@amazon.com.mbox.gz"
} |
lkml | [PATCH 0/2] Add HPET NMI Watchdog support | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anything looks abnormal, such as split
locks.
That makes PMCs a precious resource. So any PMC we can free up is a PMC
we can use for something useful. That made me look at the NMI watchdog.
The PMC based NMI watchdog implementation does not actually need any
performance counting. It just needs a per-CPU NMI timer source. X86
systems can make anything that emits an interrupt descriptor (IOAPIC,
MSI(-X), etc) become an NMI source. So any time goes. Including the
HPET. And while they can't really operate per-CPU, in almost all cases
you only really want the NMI on *all* CPUs, rather than per-CPU.
So I took a stab at building an HPET based NMI watchdog. In my (QEMU
based) testing, it's fully functional and can successfully detect when
CPUs get stuck. It even survives suspend/resume cycles.
For now, its enablement is a config time option because the hardlockup
framework does not support dynamic switching of multiple detectors.
That's ok for our use case. But maybe something for the interested
reader to tackle eventually :).
You can enable the HPET watchdog by default by setting
CONFIG_HARDLOCKUP_DETECTOR_HPET_DEFAULT=y
or passing "hpet=watchdog" to the kernel command line. When active, it
will emit a kernel log message to indicate it works:
[ 0.179176] hpet: HPET watchdog initialized on timer 0, GSI 2
The HPET can only be in either watchdog or generic mode. I am a bit
worried about IO-APIC pin allocation logic, so I opted to reuse the
generic timer pin. And that means I'm effectively breaking the normal
interrupt delivery path. so the easy way out was to say when watchdog is
active, PIT and HPET are not available as timer sources. Which is ok on
modern systems. There are way too many (unreliable) timer sources on x86
already. Trimming a few surely won't hurt.
I'm open to inputs on how to make the HPET multi-purpose though, in case
anyone feels strongly about it.
Alex
Alexander Graf (2):
x86/ioapic: Add NMI delivery configuration helper
hpet: Add HPET-based NMI watchdog support
.../admin-guide/kernel-parameters.txt | 5 +-
arch/x86/Kconfig | 19 ++
arch/x86/include/asm/io_apic.h | 2 +
arch/x86/kernel/apic/io_apic.c | 32 ++++
arch/x86/kernel/hpet.c | 172 ++++++++++++++++++
arch/x86/kernel/i8253.c | 9 +
drivers/char/hpet.c | 3 +
include/linux/hpet.h | 14 ++
8 files changed, 255 insertions(+), 1 deletion(-)
--
2.47.1
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597
| The traditional NMI watchdog timer uses performance counters to trigger
periodic NMIs. But performance counters are a scarce resource that are
best used for actual performance counting. However, the HPET is another
timer source on most modern x86 systems that can inject NMI interrupts.
Add support for using HPET timer as NMI watchdog source instead of
performance counters. This frees up a PMC for profiling use.
Unlike with the PMU based watchdog where we trigger a per-CPU NMI, APIC
based interrupt descriptors can only target either a specific CPU or
perform a broadcast on all CPUs. To not run into races and allow for
CPU hotplug, the NMI watchdog switches between CPU 0 and broadcast modes
based on whether all CPUs are up or not.
The HPET watchdog always uses IO-APIC line 2. This line is
architecturally defined as the PIT source on PCs and hence always
available as long as we disable the PIT (which we do). We could in
theory try to find a vacant GSI line, but in practice that would create
a big dependency chain on ACPI which I would rather avoid for now.
The implementation uses the standard HARDLOCKUP_DETECTOR_ARCH
infrastructure, following the same pattern as powerpc's arch-specific
hardlockup detector.
With this watchdog present, I can successfully capture system lockups,
verified by adding "local_irq_disable(); while(1) {}" into
mount_root_generic().
(Disclaimer: Some of this code was written with the help of Kiro, an AI
coding assistant)
Signed-off-by: Alexander Graf <graf@amazon.com>
---
.../admin-guide/kernel-parameters.txt | 5 +-
arch/x86/Kconfig | 19 ++
arch/x86/kernel/hpet.c | 208 ++++++++++++++++++
arch/x86/kernel/i8253.c | 9 +
drivers/char/hpet.c | 3 +
include/linux/hpet.h | 14 ++
6 files changed, 257 insertions(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 1058f2a6d6a8..c6a98812a896 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2045,11 +2045,14 @@ Kernel parameters
hpet= [X86-32,HPET] option to control HPET usage
Format: { enable (default) | disable | force |
- verbose }
+ verbose | watchdog }
disable: disable HPET and use PIT instead
force: allow force enabled of undocumented chips (ICH4,
VIA, nVidia)
verbose: show contents of HPET registers during setup
+ watchdog: use HPET timer as NMI watchdog source instead
+ of performance counters. Use nmi_watchdog=1 to enable
+ or nmi_watchdog=panic to panic on hard lockup detection.
hpet_mmap= [X86, HPET_MMAP] Allow userspace to mmap HPET
registers. Default set by CONFIG_HPET_MMAP_DEFAULT.
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 80527299f859..e8873218a803 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -948,6 +948,25 @@ config HPET_EMULATE_RTC
def_bool y
depends on HPET_TIMER && (RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)
+config HARDLOCKUP_DETECTOR_HPET
+ bool "Use HPET for NMI watchdog"
+ depends on HPET_TIMER
+ select HAVE_HARDLOCKUP_DETECTOR_ARCH
+ select HARDLOCKUP_DETECTOR_COUNTS_HRTIMER
+ help
+ Use HPET timer as NMI source instead of performance counters.
+ This frees up a performance counter for profiling.
+ Enable with hpet=watchdog kernel parameter.
+
+config HARDLOCKUP_DETECTOR_HPET_DEFAULT
+ bool "Enable HPET watchdog by default"
+ depends on HARDLOCKUP_DETECTOR_HPET
+ help
+ Say Y here to enable HPET-based NMI watchdog by default without
+ requiring the hpet=watchdog kernel parameter.
+
+ If unsure, say N.
+
# Mark as expert because too many people got it wrong.
# The code disables itself when not needed.
config DMI
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index d6387dde3ff9..c9114997c383 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -6,9 +6,12 @@
#include <linux/hpet.h>
#include <linux/cpu.h>
#include <linux/irq.h>
+#include <linux/nmi.h>
+#include <linux/syscore_ops.h>
#include <asm/cpuid/api.h>
#include <asm/irq_remapping.h>
+#include <asm/io_apic.h>
#include <asm/hpet.h>
#include <asm/time.h>
#include <asm/mwait.h>
@@ -100,6 +103,8 @@ static inline void hpet_clear_mapping(void)
/*
* HPET command line enable / disable
*/
+static bool hpet_watchdog_mode = IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR_HPET_DEFAULT);
+
static int __init hpet_setup(char *str)
{
while (str) {
@@ -113,6 +118,8 @@ static int __init hpet_setup(char *str)
hpet_force_user = true;
if (!strncmp("verbose", str, 7))
hpet_verbose = true;
+ if (!strncmp("watchdog", str, 8))
+ hpet_watchdog_mode = true;
str = next;
}
return 1;
@@ -985,6 +992,200 @@ static bool __init hpet_is_pc10_damaged(void)
return true;
}
+#ifdef CONFIG_HARDLOCKUP_DETECTOR_HPET
+/*
+ * HPET watchdog uses timer 0 routed to GSI 2 (legacy PIT IRQ line).
+ * When using HPET as watchdog, we repurpose this line for NMI delivery.
+ */
+#define HPET_WD_TIMER 0
+#define HPET_WD_GSI 2
+
+bool hpet_watchdog_initialized;
+static bool hpet_watchdog_ioapic_configured;
+static DEFINE_PER_CPU(u32, hpet_watchdog_next_tick);
+
+static int hpet_nmi_handler(unsigned int cmd, struct pt_regs *regs)
+{
+ u32 now, next, delta;
+
+ if (panic_in_progress())
+ return NMI_HANDLED;
+
+ /* Check if this NMI is from our HPET timer by comparing counter value */
+ now = hpet_readl(HPET_COUNTER);
+ next = __this_cpu_read(hpet_watchdog_next_tick);
+ delta = hpet_freq * watchdog_thresh;
+
+ /*
+ * If we have a next tick set and counter hasn't reached it yet,
+ * this NMI is not from our timer. Allow some tolerance for timing.
+ */
+ if (next && (s32)(now - next) < -(s32)(delta / 4))
+ return NMI_DONE;
+
+ /* Update next expected tick */
+ __this_cpu_write(hpet_watchdog_next_tick, now + delta);
+
+ watchdog_hardlockup_check(smp_processor_id(), regs);
+
+ return NMI_HANDLED;
+}
+
+/*
+ * On suspend, clear the configured flag so that the first CPU to come
+ * online after resume will reconfigure the HPET timer and IO-APIC.
+ *
+ * We don't need to explicitly disable the watchdog here because:
+ * 1. The HPET registers are reset by the hibernation/suspend process anyway
+ * 2. The IO-APIC state is saved/restored by ioapic_syscore_ops, but we
+ * need to reconfigure it for NMI delivery after resume
+ * 3. Secondary CPUs are offlined before suspend, so we can't broadcast
+ * NMIs until they're back online - the enable callback handles this
+ */
+static int hpet_watchdog_suspend(void *data)
+{
+ hpet_watchdog_ioapic_configured = false;
+ return 0;
+}
+
+static const struct syscore_ops hpet_watchdog_syscore_ops = {
+ .suspend = hpet_watchdog_suspend,
+};
+
+static struct syscore hpet_watchdog_syscore = {
+ .ops = &hpet_watchdog_syscore_ops,
+};
+
+static int __init hpet_watchdog_init(u32 channels)
+{
+ u32 cfg, i, route_cap;
+
+ if (channels <= HPET_WD_TIMER)
+ return 0;
+
+ /* Verify GSI 2 is available in the route capability bitmap */
+ route_cap = hpet_readl(HPET_Tn_CFG(HPET_WD_TIMER) + 4);
+ if (!(route_cap & (1 << HPET_WD_GSI))) {
+ pr_info("HPET timer 0 cannot route to GSI %d\n", HPET_WD_GSI);
+ return 0;
+ }
+
+ /* Deactivate all timers */
+ for (i = 0; i < channels; i++) {
+ cfg = hpet_readl(HPET_Tn_CFG(i));
+ cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
+ hpet_writel(cfg, HPET_Tn_CFG(i));
+ }
+
+ /* Configure HPET timer for periodic mode */
+ cfg = hpet_readl(HPET_Tn_CFG(HPET_WD_TIMER));
+ cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
+ cfg |= HPET_TN_PERIODIC | HPET_TN_32BIT | HPET_TN_SETVAL | HPET_TN_LEVEL;
+ hpet_writel(cfg, HPET_Tn_CFG(HPET_WD_TIMER));
+
+ /* Route HPET timer to the GSI */
+ cfg = hpet_readl(HPET_Tn_CFG(HPET_WD_TIMER));
+ cfg &= ~(Tn_INT_ROUTE_CNF_MASK | HPET_CFG_ENABLE);
+ cfg |= (HPET_WD_GSI << Tn_INT_ROUTE_CNF_SHIFT) & Tn_INT_ROUTE_CNF_MASK;
+ hpet_writel(cfg, HPET_Tn_CFG(HPET_WD_TIMER));
+
+ if (register_nmi_handler(NMI_LOCAL, hpet_nmi_handler, 0, "hpet_watchdog")) {
+ pr_err("Failed to register NMI_LOCAL handler\n");
+ return 0;
+ }
+ if (register_nmi_handler(NMI_UNKNOWN, hpet_nmi_handler, 0, "hpet_watchdog")) {
+ unregister_nmi_handler(NMI_LOCAL, "hpet_watchdog");
+ pr_err("Failed to register NMI_UNKNOWN handler\n");
+ return 0;
+ }
+
+ hpet_start_counter();
+
+ hpet_watchdog_initialized = true;
+
+ register_syscore(&hpet_watchdog_syscore);
+
+ pr_info("HPET watchdog initialized on timer %d, GSI %d", HPET_WD_TIMER, HPET_WD_GSI);
+
+ return 0;
+}
+
+void watchdog_hardlockup_stop(void)
+{
+ u32 cfg;
+
+ if (!hpet_watchdog_initialized)
+ return;
+
+ cfg = hpet_readl(HPET_Tn_CFG(HPET_WD_TIMER));
+ cfg &= ~HPET_TN_ENABLE;
+ hpet_writel(cfg, HPET_Tn_CFG(HPET_WD_TIMER));
+}
+
+void watchdog_hardlockup_start(void)
+{
+ u32 cfg, delta;
+
+ if (!hpet_watchdog_initialized)
+ return;
+
+ if (!hpet_watchdog_ioapic_configured) {
+ if (ioapic_set_nmi(HPET_WD_GSI, false)) {
+ pr_err("Unable to configure IO-APIC for NMI\n");
+ return;
+ }
+ hpet_watchdog_ioapic_configured = true;
+ }
+
+ delta = hpet_freq * watchdog_thresh;
+
+ cfg = hpet_readl(HPET_Tn_CFG(HPET_WD_TIMER));
+ cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB | HPET_TN_LEVEL);
+ cfg |= HPET_TN_PERIODIC | HPET_TN_32BIT | HPET_TN_SETVAL;
+ hpet_writel(cfg, HPET_Tn_CFG(HPET_WD_TIMER));
+
+ /* Write twice for AMD 81xx with buggy HPET */
+ hpet_writel(delta, HPET_Tn_CMP(HPET_WD_TIMER));
+ hpet_writel(delta, HPET_Tn_CMP(HPET_WD_TIMER));
+
+ cfg |= HPET_TN_ENABLE;
+ hpet_writel(cfg, HPET_Tn_CFG(HPET_WD_TIMER));
+}
+
+void watchdog_hardlockup_enable(unsigned int cpu)
+{
+ if (!hpet_watchdog_ioapic_configured) {
+ /*
+ * First CPU online after resume - reconfigure HPET timer.
+ * This also sets hpet_watchdog_ioapic_configured = true.
+ */
+ watchdog_hardlockup_start();
+ }
+
+ if (num_online_cpus() == num_present_cpus()) {
+ ioapic_set_nmi(HPET_WD_GSI, true);
+ pr_info("switched to broadcast mode (all %d CPUs online)\n",
+ num_online_cpus());
+ }
+}
+
+void watchdog_hardlockup_disable(unsigned int cpu)
+{
+ if (num_online_cpus() < num_present_cpus()) {
+ ioapic_set_nmi(HPET_WD_GSI, false);
+ pr_info("switched to CPU 0 only (%d CPUs online)\n",
+ num_online_cpus() - 1);
+ }
+}
+
+int __init watchdog_hardlockup_probe(void)
+{
+ return hpet_watchdog_mode ? 0 : -ENODEV;
+}
+#else
+static inline int hpet_watchdog_init(u32 channels) { return 0; }
+#endif /* CONFIG_HARDLOCKUP_DETECTOR_HPET */
+
/**
* hpet_enable - Try to setup the HPET timer. Returns 1 on success.
*/
@@ -1031,6 +1232,10 @@ int __init hpet_enable(void)
/* This is the HPET channel number which is zero based */
channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
+ /* If watchdog mode, hand off to watchdog driver */
+ if (hpet_watchdog_mode)
+ return hpet_watchdog_init(channels);
+
/*
* The legacy routing mode needs at least two channels, tick timer
* and the rtc emulation channel.
@@ -1122,6 +1327,9 @@ static __init int hpet_late_init(void)
{
int ret;
+ if (hpet_is_watchdog())
+ return -ENODEV;
+
if (!hpet_address) {
if (!force_hpet_address)
return -ENODEV;
diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c
index cb9852ad6098..36dd948371a4 100644
--- a/arch/x86/kernel/i8253.c
+++ b/arch/x86/kernel/i8253.c
@@ -7,6 +7,7 @@
#include <linux/init.h>
#include <linux/timex.h>
#include <linux/i8253.h>
+#include <linux/hpet.h>
#include <asm/hypervisor.h>
#include <asm/apic.h>
@@ -31,6 +32,14 @@ struct clock_event_device *global_clock_event;
*/
static bool __init use_pit(void)
{
+ if (hpet_is_watchdog()) {
+ /*
+ * The PIT overlaps the HPET IRQ line which we configure to
+ * NMI in watchdog mode, rendering the PIT non functional.
+ */
+ return false;
+ }
+
if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC))
return true;
diff --git a/drivers/char/hpet.c b/drivers/char/hpet.c
index 4f5ccd3a1f56..9d9e4d22ab7f 100644
--- a/drivers/char/hpet.c
+++ b/drivers/char/hpet.c
@@ -977,6 +977,9 @@ static int hpet_acpi_add(struct acpi_device *device)
acpi_status result;
struct hpet_data data;
+ if (hpet_is_watchdog())
+ return -ENODEV;
+
memset(&data, 0, sizeof(data));
result =
diff --git a/include/linux/hpet.h b/include/linux/hpet.h
index 21e69eaf7a36..408b440163cc 100644
--- a/include/linux/hpet.h
+++ b/include/linux/hpet.h
@@ -108,4 +108,18 @@ static inline void hpet_reserve_timer(struct hpet_data *hd, int timer)
int hpet_alloc(struct hpet_data *);
+#ifdef CONFIG_HARDLOCKUP_DETECTOR_HPET
+extern bool hpet_watchdog_initialized;
+
+static inline bool hpet_is_watchdog(void)
+{
+ return hpet_watchdog_initialized;
+}
+#else
+static inline bool hpet_is_watchdog(void)
+{
+ return false;
+}
+#endif
+
#endif /* !__HPET__ */
--
2.47.1
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597 | {
"author": "Alexander Graf <graf@amazon.com>",
"date": "Mon, 2 Feb 2026 17:48:03 +0000",
"thread_id": "20260202174803.66640-1-graf@amazon.com.mbox.gz"
} |
lkml | [PATCH 0/2] Add HPET NMI Watchdog support | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anything looks abnormal, such as split
locks.
That makes PMCs a precious resource. So any PMC we can free up is a PMC
we can use for something useful. That made me look at the NMI watchdog.
The PMC based NMI watchdog implementation does not actually need any
performance counting. It just needs a per-CPU NMI timer source. X86
systems can make anything that emits an interrupt descriptor (IOAPIC,
MSI(-X), etc) become an NMI source. So any time goes. Including the
HPET. And while they can't really operate per-CPU, in almost all cases
you only really want the NMI on *all* CPUs, rather than per-CPU.
So I took a stab at building an HPET based NMI watchdog. In my (QEMU
based) testing, it's fully functional and can successfully detect when
CPUs get stuck. It even survives suspend/resume cycles.
For now, its enablement is a config time option because the hardlockup
framework does not support dynamic switching of multiple detectors.
That's ok for our use case. But maybe something for the interested
reader to tackle eventually :).
You can enable the HPET watchdog by default by setting
CONFIG_HARDLOCKUP_DETECTOR_HPET_DEFAULT=y
or passing "hpet=watchdog" to the kernel command line. When active, it
will emit a kernel log message to indicate it works:
[ 0.179176] hpet: HPET watchdog initialized on timer 0, GSI 2
The HPET can only be in either watchdog or generic mode. I am a bit
worried about IO-APIC pin allocation logic, so I opted to reuse the
generic timer pin. And that means I'm effectively breaking the normal
interrupt delivery path. so the easy way out was to say when watchdog is
active, PIT and HPET are not available as timer sources. Which is ok on
modern systems. There are way too many (unreliable) timer sources on x86
already. Trimming a few surely won't hurt.
I'm open to inputs on how to make the HPET multi-purpose though, in case
anyone feels strongly about it.
Alex
Alexander Graf (2):
x86/ioapic: Add NMI delivery configuration helper
hpet: Add HPET-based NMI watchdog support
.../admin-guide/kernel-parameters.txt | 5 +-
arch/x86/Kconfig | 19 ++
arch/x86/include/asm/io_apic.h | 2 +
arch/x86/kernel/apic/io_apic.c | 32 ++++
arch/x86/kernel/hpet.c | 172 ++++++++++++++++++
arch/x86/kernel/i8253.c | 9 +
drivers/char/hpet.c | 3 +
include/linux/hpet.h | 14 ++
8 files changed, 255 insertions(+), 1 deletion(-)
--
2.47.1
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597
| On 02.02.26 18:43, Alexander Graf wrote:
Sorry for the resend. I caught an issue while sending out the series,
hit ctrl-c before thinking and suddenly had a half sent series. Discard
this one. Happy review on the real, full one :)
Alex
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597 | {
"author": "Alexander Graf <graf@amazon.com>",
"date": "Mon, 2 Feb 2026 18:49:13 +0100",
"thread_id": "20260202174803.66640-1-graf@amazon.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock
operations, such as setting the rate or switching parents. However,
another operation that can and often does touch actual hardware state is
recalc_rate, which may also be affected by such a dependency.
Add parent enables/disables where the recalc_rate op is called directly.
Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/clk/clk.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 85d2f2481acf360f0618a4a382fb51250e9c2fc4..1b0f9d567f48e003497afc98df0c0d2ad244eb90 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1921,7 +1921,14 @@ static unsigned long clk_recalc(struct clk_core *core,
unsigned long rate = parent_rate;
if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
+ if (core->flags & CLK_OPS_PARENT_ENABLE)
+ clk_core_prepare_enable(core->parent);
+
rate = core->ops->recalc_rate(core->hw, parent_rate);
+
+ if (core->flags & CLK_OPS_PARENT_ENABLE)
+ clk_core_disable_unprepare(core->parent);
+
clk_pm_runtime_put(core);
}
return rate;
@@ -4031,6 +4038,9 @@ static int __clk_core_init(struct clk_core *core)
*/
clk_core_update_duty_cycle_nolock(core);
+ if (core->flags & CLK_OPS_PARENT_ENABLE)
+ clk_core_prepare_enable(core->parent);
+
/*
* Set clk's rate. The preferred method is to use .recalc_rate. For
* simple clocks and lazy developers the default fallback is to use the
@@ -4046,6 +4056,9 @@ static int __clk_core_init(struct clk_core *core)
rate = 0;
core->rate = core->req_rate = rate;
+ if (core->flags & CLK_OPS_PARENT_ENABLE)
+ clk_core_disable_unprepare(core->parent);
+
/*
* Enable CLK_IS_CRITICAL clocks so newly added critical clocks
* don't get accidentally disabled when walking the orphan tree and
--
2.51.0 | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:09 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| Passing the struct device pointer to clk_hw_register allows for runtime
power management to work for the registered clock controllers. However,
the mediatek PLL clocks do not do this.
Change this by adding a struct device pointer argument to
mtk_clk_register_pll, and fix up the only other user of it. Also add a
new member to the struct mtk_clk_pll for the struct device pointer,
which is set by mtk_clk_register_pll and is used by
mtk_clk_register_pll_ops.
If mtk_clk_register_pll is called with a NULL struct device pointer,
then everything still works as expected; the clock core will simply
treat them as previously, i.e. without runtime power management.
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/clk/mediatek/clk-pll.c | 9 ++++++---
drivers/clk/mediatek/clk-pll.h | 4 +++-
drivers/clk/mediatek/clk-pllfh.c | 2 +-
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 5caf91ae9ddbe4f4d7052864adf0a5a70bda66bc..c4f9c06e5133dbc5902f261353c197fbde95e54d 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -366,7 +366,7 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
init.parent_names = &parent_name;
init.num_parents = 1;
- ret = clk_hw_register(NULL, &pll->hw);
+ ret = clk_hw_register(pll->dev, &pll->hw);
if (ret)
return ERR_PTR(ret);
@@ -374,7 +374,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
return &pll->hw;
}
-struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
+struct clk_hw *mtk_clk_register_pll(struct device *dev,
+ const struct mtk_pll_data *data,
void __iomem *base)
{
struct mtk_clk_pll *pll;
@@ -385,6 +386,8 @@ struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
if (!pll)
return ERR_PTR(-ENOMEM);
+ pll->dev = dev;
+
hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops);
if (IS_ERR(hw))
kfree(pll);
@@ -428,7 +431,7 @@ int mtk_clk_register_plls(struct device *dev,
continue;
}
- hw = mtk_clk_register_pll(pll, base);
+ hw = mtk_clk_register_pll(dev, pll, base);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", pll->name,
diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index 38fde1a273bff0a7a010a37356ebc715fe0720d3..f6493699c4e367b45038ceede9565ae42a030b47 100644
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -61,6 +61,7 @@ struct mtk_pll_data {
*/
struct mtk_clk_pll {
+ struct device *dev;
struct clk_hw hw;
void __iomem *base_addr;
void __iomem *pd_addr;
@@ -108,7 +109,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
const struct mtk_pll_data *data,
void __iomem *base,
const struct clk_ops *pll_ops);
-struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
+struct clk_hw *mtk_clk_register_pll(struct device *dev,
+ const struct mtk_pll_data *data,
void __iomem *base);
void mtk_clk_unregister_pll(struct clk_hw *hw);
diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c
index 83630ee07ee976bf980c8cf2dd35ea24c1b40821..62bfe4a480f14a0a742fb094aff0e6d1a79fe0c3 100644
--- a/drivers/clk/mediatek/clk-pllfh.c
+++ b/drivers/clk/mediatek/clk-pllfh.c
@@ -220,7 +220,7 @@ int mtk_clk_register_pllfhs(struct device_node *node,
if (use_fhctl)
hw = mtk_clk_register_pllfh(pll, pllfh, base);
else
- hw = mtk_clk_register_pll(pll, base);
+ hw = mtk_clk_register_pll(NULL, pll, base);
if (IS_ERR(hw)) {
pr_err("Failed to register %s clk %s: %ld\n",
--
2.51.0 | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:11 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| After refactoring all of PLL to pass the device, it's now fairly easy to
refactor pllfh and its users, as pllfh registration wraps PLL
registration.
Do this refactor and move all of the pllfh users to pass the device as
well.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
7 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
index 91665d7f125efde4941cc4de881c5b503a935529..123d5d7fea8554676364dc56f5c023e43325d516 100644
--- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
@@ -152,7 +152,7 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
return -ENOMEM;
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
- ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+ ret = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (ret)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
index 95385bb67d5511eda3a851f81986e67eaf81e5fb..d7d416172ab35bc027ae67c163c1dc20dee857b6 100644
--- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
@@ -140,13 +140,13 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed);
static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
{
const u8 *fhctl_node = "mediatek,mt8173-fhctl";
- struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data;
+ struct device *dev = &pdev->dev;
void __iomem *base;
struct clk_hw *hw;
int r;
- base = of_iomap(node, 0);
+ base = of_iomap(dev->of_node, 0);
if (!base)
return -ENOMEM;
@@ -157,25 +157,25 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
}
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
- r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
- pllfhs, ARRAY_SIZE(pllfhs), clk_data);
+ r = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;
hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_REF2USB);
if (IS_ERR(hw)) {
r = PTR_ERR(hw);
- dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r);
+ dev_err(dev, "Failed to register ref2usb_tx: %d\n", r);
goto unregister_plls;
}
clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
- hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0,
+ hw = devm_clk_hw_register_divider(dev, "hdmi_ref", "tvdpll_594m", 0,
base + REGOFF_HDMI_REF, 16, 3,
CLK_DIVIDER_POWER_OF_TWO, NULL);
clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_ref2usb;
diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
index 4b2b16578232d986f78deed4778c5fab7f460184..d35dd2632e43ab535b32b8b99f8d75de02d56fe2 100644
--- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
@@ -151,7 +151,7 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
- r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+ r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;
diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
index 0b66a27e4d5ac68f09dc6a4197fd84ef82342df9..b0563a285bd666d492a7fa940733aad1ab1a0bae 100644
--- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
@@ -162,7 +162,7 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
- r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+ r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
index 282a3137dc89419a6d0b574fd549cee941687900..44917ab034c56f01ef02d1957f17eb0655438d75 100644
--- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
@@ -181,7 +181,7 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
- r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+ r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;
diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c
index 62bfe4a480f14a0a742fb094aff0e6d1a79fe0c3..8ad11023d91127e88900bc6bcabbaeafb1e00664 100644
--- a/drivers/clk/mediatek/clk-pllfh.c
+++ b/drivers/clk/mediatek/clk-pllfh.c
@@ -10,6 +10,7 @@
#include <linux/slab.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
+#include <linux/device.h>
#include "clk-mtk.h"
#include "clk-pllfh.h"
@@ -149,7 +150,7 @@ static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
}
static struct clk_hw *
-mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
+mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_data,
struct mtk_pllfh_data *pllfh_data, void __iomem *base)
{
struct clk_hw *hw;
@@ -166,6 +167,8 @@ mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
goto out;
}
+ fh->clk_pll.dev = dev;
+
hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
&mtk_pllfh_ops);
@@ -194,7 +197,7 @@ static void mtk_clk_unregister_pllfh(struct clk_hw *hw)
kfree(fh);
}
-int mtk_clk_register_pllfhs(struct device_node *node,
+int mtk_clk_register_pllfhs(struct device *dev,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data)
@@ -203,7 +206,7 @@ int mtk_clk_register_pllfhs(struct device_node *node,
int i;
struct clk_hw *hw;
- base = of_iomap(node, 0);
+ base = of_iomap(dev->of_node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return -EINVAL;
@@ -218,9 +221,9 @@ int mtk_clk_register_pllfhs(struct device_node *node,
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
if (use_fhctl)
- hw = mtk_clk_register_pllfh(pll, pllfh, base);
+ hw = mtk_clk_register_pllfh(dev, pll, pllfh, base);
else
- hw = mtk_clk_register_pll(NULL, pll, base);
+ hw = mtk_clk_register_pll(dev, pll, base);
if (IS_ERR(hw)) {
pr_err("Failed to register %s clk %s: %ld\n",
diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pllfh.h
index 5f419c2ec01f988ede4e40289c6e5d5f8070ad14..a4f337acad71389f771187908882b09d0f801868 100644
--- a/drivers/clk/mediatek/clk-pllfh.h
+++ b/drivers/clk/mediatek/clk-pllfh.h
@@ -68,7 +68,7 @@ struct fh_operation {
int (*ssc_enable)(struct mtk_fh *fh, u32 rate);
};
-int mtk_clk_register_pllfhs(struct device_node *node,
+int mtk_clk_register_pllfhs(struct device *dev,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_pllfhs,
struct clk_hw_onecell_data *clk_data);
--
2.51.0 | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:12 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| As it stands, mtk_clk_register_plls takes a struct device_node pointer
as its first argument. This is a tragic happenstance, as it's trivial to
get the device_node from a struct device, but the opposite not so much.
The struct device is a much more useful thing to have passed down.
Refactor mtk_clk_register_plls to take a struct device pointer instead
of a struct device_node pointer, and fix up all users of this function.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 2 +-
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 7 ++++---
drivers/clk/mediatek/clk-pll.h | 10 ++++------
24 files changed, 34 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 1e88ad8b93f4485ad40f842e19c68117e00a2fbe..d9f40fda73d1abc56ebc97ab755bb48bd5f0991f 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -978,7 +978,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
+ mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls),
clk_data);
mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c
index a60622d251ff30fe8db2e596d87986a88f854e61..54b18e9f83f8f403460c77d8f5d4ea0737316774 100644
--- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c
@@ -119,7 +119,7 @@ static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
index e0949911e8f7da7894b204012caefd0404cf8308..9e30c089a2092472bab889ede419c41890c307a0 100644
--- a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
@@ -93,8 +93,8 @@ static int clk_mt6735_apmixed_probe(struct platform_device *pdev)
return -ENOMEM;
platform_set_drvdata(pdev, clk_data);
- ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
- ARRAY_SIZE(apmixedsys_plls), clk_data);
+ ret = mtk_clk_register_plls(&pdev->dev, apmixedsys_plls,
+ ARRAY_SIZE(apmixedsys_plls), clk_data);
if (ret) {
dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
return ret;
diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c
index d53731e7933f46d88ff180e43eb7163e52fb5b1c..60f6f9fa7dcf279631d0fa2eb30a3bcbadef3225 100644
--- a/drivers/clk/mediatek/clk-mt6765.c
+++ b/drivers/clk/mediatek/clk-mt6765.c
@@ -740,7 +740,7 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
index 86732f5acf93407a5aa99bc2f386f0728a06bb9b..4b9dcb910b03f1078212dc7089d7171d05de7e7f 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -1220,7 +1220,7 @@ static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index fb59e71af58e32d9419e036e3dbd28cdaa61cac3..ebf850ac57f540f2317e63dfabe94a953db3ae29 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -655,7 +655,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c
index 2350592d9a934f3ec8efb0cd8197e4c4fee49697..8a29eaab0cfcb7a389e09f8869b572d5886e2eaf 100644
--- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c
@@ -96,7 +96,7 @@ static int clk_mt7622_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index baf94e7bea373c59cb6333fdb483d00240b744c7..e154771b1b8bba7378af8a797c81d0784b626e3b 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -634,7 +634,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls),
clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediatek/clk-mt7981-apmixed.c
index e8211eb4e09e1a645f7e50a1e5814d29030c1757..6606b54fb376983ec7d49b00c2c0d1690c734058 100644
--- a/drivers/clk/mediatek/clk-mt7981-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
@@ -76,7 +76,7 @@ static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c
index 93751abe6be89784a102a0e5ac629d363ab3baaf..1c79418d08a77acf25cee914fb6573ac1707163e 100644
--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
@@ -74,7 +74,7 @@ static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
diff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediatek/clk-mt7988-apmixed.c
index 63d33a78cb48805f71aa6a74f8ed6b83f3b4fe22..416a4b88d100bb47bdb07e4f72bc13208c8707a7 100644
--- a/drivers/clk/mediatek/clk-mt7988-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
@@ -86,7 +86,7 @@ static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_apmixed_data;
diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c
index bdadc35c64cbd8987061c4442b8ff2f5fe50cc32..19e4ee489ec3905e92674ed0813a9f60f9c28209 100644
--- a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c
@@ -57,7 +57,8 @@ static int clk_mt8135_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ ret = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls),
+ clk_data);
if (ret)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c
index adf576786696e0962dfd5147dfc8897bfaa48054..fb6c21bbeef81a383b56c8fada1799e0680676e5 100644
--- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c
@@ -105,7 +105,7 @@ static int clk_mt8167_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
index 551adbfd7ac9309bbc4f9beefe4f26230514f062..6242d4f5376e79346b2219b0a35cf0c5ad755e49 100644
--- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
@@ -155,7 +155,7 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
index 21d7a9a2ab1af64cca6962960418d44c81dc664a..a1de596bff9945ca938504391e3e33a4987d3a63 100644
--- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
@@ -106,7 +106,7 @@ static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_apmixed_data;
diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
index 8b45a3fad02f18df30e4c2ce2ba5b6338eae321f..a2d98ed58e34866b3d68bd0f85bde339c258d822 100644
--- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
+++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
@@ -66,7 +66,8 @@ static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
+ r = mtk_clk_register_plls(&pdev->dev, apusys_plls,
+ ARRAY_SIZE(apusys_plls), clk_data);
if (r)
goto free_apusys_pll_data;
diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c
index 617f5449b88b8bcaf282e8ed8593b52413a233a8..c4ebb0170b82b979fbe7f03925f205325247d55d 100644
--- a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c
@@ -152,7 +152,8 @@ static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_plls(node, mcd->clks, mcd->num_clks, clk_data);
+ r = mtk_clk_register_plls(&pdev->dev, mcd->clks, mcd->num_clks,
+ clk_data);
if (r)
goto free_apmixed_data;
diff --git a/drivers/clk/mediatek/clk-mt8196-mcu.c b/drivers/clk/mediatek/clk-mt8196-mcu.c
index 5cbcc411ae734c82b97bf099a645cb6aaa31d9c3..13642fc673c267a66027d1fa7073c9cfed68c682 100644
--- a/drivers/clk/mediatek/clk-mt8196-mcu.c
+++ b/drivers/clk/mediatek/clk-mt8196-mcu.c
@@ -122,7 +122,7 @@ static int clk_mt8196_mcu_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
+ r = mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data);
if (r)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/clk-mt8196-mfg.c
index ae1eb9de79ae2992b10a400c75e2e0324b100f66..8e09c0f7b7548f8e286671cea2dac64530b8ce47 100644
--- a/drivers/clk/mediatek/clk-mt8196-mfg.c
+++ b/drivers/clk/mediatek/clk-mt8196-mfg.c
@@ -105,7 +105,7 @@ static int clk_mt8196_mfg_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
+ r = mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data);
if (r)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c
index d59a8a9d98550e897d18031d9bb814aa96d3cf57..7dcc164627c578ca93377425c3b21b46da4b4c28 100644
--- a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c
+++ b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c
@@ -664,7 +664,7 @@ static int clk_mt8196_vlp_probe(struct platform_device *pdev)
if (r)
goto unregister_factors;
- r = mtk_clk_register_plls(node, vlp_plls, ARRAY_SIZE(vlp_plls),
+ r = mtk_clk_register_plls(dev, vlp_plls, ARRAY_SIZE(vlp_plls),
clk_data);
if (r)
goto unregister_muxes;
diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c
index f41b991a0178af3067b19a693512ec922af48e07..e331aa28a4bd58baf48a4aae1601cc80fc5661ac 100644
--- a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c
@@ -133,7 +133,7 @@ static int clk_mt8365_apmixed_probe(struct platform_device *pdev)
return PTR_ERR(hw);
clk_data->hws[CLK_APMIXED_USB20_EN] = hw;
- ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
diff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c
index edd9174d2f2ff97a0c1198caa2a0b9c1ca40ffd2..2a6206cae2f087ff06fe60a6cf96a0fa3143e567 100644
--- a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c
@@ -87,7 +87,7 @@ static int clk_mt8516_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index cd2b6ce551c6b0333cbe0a4f0d155ba2411f757a..5caf91ae9ddbe4f4d7052864adf0a5a70bda66bc 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
+#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk-pll.h"
@@ -404,7 +405,7 @@ void mtk_clk_unregister_pll(struct clk_hw *hw)
kfree(pll);
}
-int mtk_clk_register_plls(struct device_node *node,
+int mtk_clk_register_plls(struct device *dev,
const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data)
{
@@ -412,7 +413,7 @@ int mtk_clk_register_plls(struct device_node *node,
int i;
struct clk_hw *hw;
- base = of_iomap(node, 0);
+ base = of_iomap(dev->of_node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return -EINVAL;
@@ -423,7 +424,7 @@ int mtk_clk_register_plls(struct device_node *node,
if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
- node, pll->id);
+ dev->of_node, pll->id);
continue;
}
diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index d71c150ce83e4bb2fe78290c2d5570a90084246d..38fde1a273bff0a7a010a37356ebc715fe0720d3 100644
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -10,9 +10,7 @@
#include <linux/clk-provider.h>
#include <linux/types.h>
-struct clk_ops;
-struct clk_hw_onecell_data;
-struct device_node;
+struct device;
struct mtk_pll_div_table {
u32 div;
@@ -78,9 +76,9 @@ struct mtk_clk_pll {
const struct mtk_pll_data *data;
};
-int mtk_clk_register_plls(struct device_node *node,
- const struct mtk_pll_data *plls, int num_plls,
- struct clk_hw_onecell_data *clk_data);
+int mtk_clk_register_plls(struct device *dev, const struct mtk_pll_data *plls,
+ int num_plls, struct clk_hw_onecell_data *clk_data);
+
void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data);
--
2.51.0 | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:10 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| All the MFGPLL require MFG_EB to be on for any operation on them, and
they only tick when MFG_EB is on as well, therefore making this a
parent-child relationship.
This dependency wasn't clear during the initial upstreaming of these
clock controllers, as it only made itself known when I could observe
the effects of the clock by bringing up a different piece of hardware.
Add a new PLL_PARENT_EN flag to mediatek's clk-pll.h, and check for it
when initialising the pll to then translate it into the actual
CLK_OPS_PARENT_ENABLE flag.
Then add the mfg_eb parent to the mfgpll clocks, and set the new
PLL_PARENT_EN flag.
Fixes: 03dc02f8c7dc ("clk: mediatek: Add MT8196 mfg clock support")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/clk/mediatek/clk-mt8196-mfg.c | 13 +++++++------
drivers/clk/mediatek/clk-pll.c | 3 +++
drivers/clk/mediatek/clk-pll.h | 1 +
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/clk-mt8196-mfg.c
index 8e09c0f7b7548f8e286671cea2dac64530b8ce47..a317183f1681bc6e8167c44b2bbe4a78566ba639 100644
--- a/drivers/clk/mediatek/clk-mt8196-mfg.c
+++ b/drivers/clk/mediatek/clk-mt8196-mfg.c
@@ -58,24 +58,25 @@
.pcw_shift = _pcw_shift, \
.pcwbits = _pcwbits, \
.pcwibits = MT8196_INTEGER_BITS, \
+ .parent_name = "mfg_eb", \
}
static const struct mtk_pll_data mfg_ao_plls[] = {
- PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0,
- BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
+ PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0,
+ PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
MFGPLL_CON1, 0, 22),
};
static const struct mtk_pll_data mfgsc0_ao_plls[] = {
PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
- MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0,
- MFGPLL_SC0_CON1, 0, 22),
+ MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24,
+ 0, 0, 0, MFGPLL_SC0_CON1, 0, 22),
};
static const struct mtk_pll_data mfgsc1_ao_plls[] = {
PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
- MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0,
- MFGPLL_SC1_CON1, 0, 22),
+ MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24,
+ 0, 0, 0, MFGPLL_SC1_CON1, 0, 22),
};
static const struct of_device_id of_match_clk_mt8196_mfg[] = {
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index c4f9c06e5133dbc5902f261353c197fbde95e54d..0f3759fcd9d0228c23f4916d041d17b731a6c838 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -359,6 +359,9 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
init.name = data->name;
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
+ if (data->flags & PLL_PARENT_EN)
+ init.flags |= CLK_OPS_PARENT_ENABLE;
+
init.ops = pll_ops;
if (data->parent_name)
init.parent_names = &data->parent_name;
diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index f6493699c4e367b45038ceede9565ae42a030b47..f49dc2732ffee50ebf023c01b513d74989a6ec7b 100644
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -19,6 +19,7 @@ struct mtk_pll_div_table {
#define HAVE_RST_BAR BIT(0)
#define PLL_AO BIT(1)
+#define PLL_PARENT_EN BIT(2)
#define POSTDIV_MASK GENMASK(2, 0)
struct mtk_pll_data {
--
2.51.0 | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:13 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| Hi Nicolas,
On Fri, Oct 10, 2025 at 10:47:09PM +0200, Nicolas Frattaroli wrote:
clk_change_rate() has the following code:
if (core->flags & CLK_OPS_PARENT_ENABLE)
clk_core_prepare_enable(parent);
...
core->rate = clk_recalc(core, best_parent_rate);
...
if (core->flags & CLK_OPS_PARENT_ENABLE)
clk_core_disable_unprepare(parent);
clk_change_rate() ultimately is called by various clk_set_rate
functions. Will that be a problem for the double calls to
clk_core_prepare_enable()?
Fanning this out to the edge further is going to make the code even
more complicated. What do you think about moving this to
clk_core_enable_lock()? I know the set_parent operation has a special
case that would need to be worked around.
Brian | {
"author": "Brian Masney <bmasney@redhat.com>",
"date": "Thu, 16 Oct 2025 16:52:30 -0400",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Thursday, 16 October 2025 22:52:30 Central European Summer Time Brian Masney wrote:
I don't see how multiple prepares are a problem as long as they're
balanced.
__clk_core_init also needs special code in that case, as it calls the
bare recalc_rate op with no clk_core_enable_lock beforehand. It's also
wrong, in that recalc_rate does not necessitate the clock being on as
far as I'm aware. (if it did, this wouldn't be a problem in the first
place, as enabling it would enable the parent as well). Changing the
semantics of clk_recalc, and therefore clk_get_rate, to also enable
the clock, would be a major change in how the common clock framework
functions.
In my case, the __clk_core_init callback was the one that crashed,
so it really needs to happen there, and I really don't want to
refactor every location where `CLK_OPS_PARENT_ENABLE` is used for
a bugfix just to avoid potentially checking the same flag twice.
Having `CLK_OPS_PARENT_ENABLE` cleaned up such that every clk op
that has potential register access is never directly called by the
clk core except for one place, an accessor function that does both
pmdomain and `CLK_OPS_PARENT_ENABLE` checks, would be nice, e.g.
by keeping the clk_recalc change and then having __clk_core_init
call clk_recalc instead of the recalc op directly. But then the
__clk_core_init logic needs further refactoring as well.
I'm not sure I want to do that in this series, because it's quite
a bit different from just adding the missing check and parent
toggling, and has the chance of me introducing subtle logic bugs
in what is supposed to be a bugfix.
Kind regards,
Nicolas Frattaroli | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 17 Oct 2025 14:21:55 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| Hi Nicolas,
On Fri, Oct 17, 2025 at 02:21:55PM +0200, Nicolas Frattaroli wrote:
I agree and that makes sense. Thanks for the explanation. What you have
is a good compromise.
Reviewed-by: Brian Masney <bmasney@redhat.com> | {
"author": "Brian Masney <bmasney@redhat.com>",
"date": "Mon, 20 Oct 2025 15:36:41 -0400",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Fri, Oct 10, 2025 at 10:47:09PM +0200, Nicolas Frattaroli wrote:
I'm seeing boot regressions in -next on the Avenger96 which bisect to
this patch in -next. The board resets during startup:
[ 0.297034] /soc/display-controller@5a001000: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@5c002000/hdmi-transmitter@3d
[ 0.307482] /soc/bus@5c007000/sai@4400b000/audio-controller@4400b004: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@5c002000/hdmi-transmitter@3d
[ 0.321193] /soc/bus@5c007000/i2c@5c002000/hdmi-transmitter@3d: Fixed dependency cycle(s) with /soc/bus@5c007000/sai@4400b000/audio-controller@4400b004
[ 0.334454] /soc/bus@5c007000/i2c@5c002000/hdmi-transmitter@3d: Fixed dependency cycle(s) with /soc/display-controller@5a001000
U-Boot SPL 2023.07.02-dh-stm32mp1-dhcor-avenger96-20230727.02 (Jul 11 2023 - 15:20:44 +0000)
Model: Arrow Electronics STM32MP15xx Avenger96 board
https://lava.sirena.org.uk/scheduler/job/2409783
bisect log:
# bad: [615aad0f61e0c7a898184a394dc895c610100d4f] Add linux-next specific files for 20260126
# good: [50814c5ce8d8f6751fd49c818abeb8853f8be2df] Merge branch 'for-linux-next-fixes' of https://gitlab.freedesktop.org/drm/misc/kernel.git
# good: [702ce71d32f2c30b4f45b7c6b701d87583c58df8] ASoC: SDCA: Add NO_DIRECT_COMPLETE flag to class driver
# good: [d0ab89951197f0fc509a0cd732d830880e79c2d4] ASoC: cs35l56: Add KUnit testing of cs35l56_set_fw_suffix()
# good: [7f428282fde34f06f3ab898b8a9081bf93a41f22] ALSA: hda: controllers: intel: add support for Nova Lake
# good: [cafadbf430f4b2f3ca4158de48ef6ba4d97fbf17] ASoC: renesas: rz-ssi: Drop goto label
# good: [00ca2dd431fa2acb07b3ecc6ce49fb9a0a4d72cb] ASoC: SOF: Intel: hda: Remove MODULE_SOFTDEP for snd-hda-codec-hdmi
# good: [3495a5df94a9ad7a8940bcb3ebfda58255f5b952] spi: dt-bindings: nxp,imx94-xspi: add nxp,imx952-xspi
# good: [a18467a50eddbd7c6548b53b25b68e5454ceb587] ASoC: realtek: fix misspelling of "minimum" in comments
# good: [c3608162a95a259c669cf9fdccf900782fa8d902] spi: xilinx: make irq optional
# good: [3c5ddd56aa93048314c64533c21e731a44b0f067] ASoC: codecs: es8323: Enable proper DAPM widgets for chip power
# good: [20c4701b75a3d6ce09d61e17125aefe77e7eb333] dt-bindings: regulator: mark regulator-suspend-microvolt as deprecated
# good: [37fbc1ab0f225d23f0839260a11375b4f1f7cf8c] spi: Drop duplicate device_set_node() call
# good: [83ba6efa711fad83a0fbf02178ad64d3906d8d09] spi: rockchip: Use plain request_irq()
# good: [4fbd3b2ec04dc6ef93090ec24733a5c5671fb71f] ASoC: soc-acpi-intel-ptl-match: use aggregated endpoint in ptl_rt722_l0_rt1320_l23
# good: [7a3d1b04d938f31e112fe09c0ffc1af830ba1f6d] ASoC: SDCA: Handle CONFIG_PM_SLEEP not being set
# good: [dccc66b0e92d48d9a1908a3ccb8142e0ee3381f5] regmap: Enable REGMAP when REGMAP_SLIMBUS is enabled
# good: [61d2a7699ab39d448f44919ef15c16187e6f70ec] ASoC: SDCA: Tidy up some memory allocations
# good: [519d0a6b2ca5a891340b6c24a4c40545f518e1a8] ASoC: codecs: aw88261: use dvdd-supply regulator
# good: [da7afdc79cba00f952df12cd579e44832d829c0a] ASoC: SDCA: Add lock to serialise the Function initialisation
# good: [8a98e7f55f975360975083166e21982ef307b8fd] ASoC: tlv320adcx140: add channel sum control
# good: [10303b32519f52a5afd40593a507543143c8ec6a] dt-bindings: sound: google,goldfish-audio: Convert to DT schema
# good: [62b04225e99a5d1c71c5c73d2aa6618bc2c0738f] regulator: dt-bindings: rpi-panel: Mark 7" Raspberry Pi as GPIO controller
# good: [de9f1b1583aecb246b659effb03f2456604fab64] regulator: dt-bindings: mediatek,mt6331: Add missing ldo-vio28 vreg
# good: [a014c203b54d9013ad52ad8a531cf46e71028f2b] spi: fsi: Simplify with scoped for each OF child loop
# good: [e7c30ac379b429d439eb62ae1bb69720a6701e26] ASoC: amd: acp: soc-acpi: add is_device_rt712_vb() helper
# good: [09dc08b396c954820f119e1ab0c7d72333c18323] regulator: dummy, make dummy_regulator_driver static
# good: [6be9ea62afedef0f976eb3dba4c117be0c1d3809] ASoC: codecs: rtq9128: Add compatible changes for rtq9154
# good: [e590752119029d87ce46d725e11245a52d22e1fe] ASoC: wm8962: Don't report a microphone if it's shorted to ground on plug
# good: [77157cb45c66bd652a08a360693fcced558c5ef9] ASoC: codecs: rt1320-sdw: convert to snd_soc_dapm_xxx()
# good: [b0fc1e7701940d12ea2c41f386aa552bc4cc3629] regulator: Add TPS65185 driver
# good: [8618271887ca10ac5108fe7e1d82ba8f1b152cf9] spi: spi-mem: Limit octal DTR constraints to octal DTR situations
# good: [8672e4b51adfc57150f3862b1665faff0acf1bad] spi: dt-bindings: nxp,lpc3220-spi: Add DMA specific properties
# good: [fc6ceb7e4ea746e663ff8c5593e67ad8ccbee34a] ASoC: sof ipc4: Add sof_ipc4_widget_setup_msg_payload() and call it
# good: [83aee46dc2142eed2dc40b5cef0e9e08e14cac42] ASoC: SOF: ipc/ops: Use guard() for spinlocks
# good: [8d38423d9dea7353a8a54a3ab2e0d0aa04ed34d0] regulator: core: don't fail regulator_register() with missing required supply
# good: [b9198ce5c6dfee19b9662dda95ba559af9cdf53f] ASoC: codecs: aw88261: Add devicetree support
# good: [db4371d13f82fb12463fe053f4864980a2af2106] MAINTAINERS: Add entries for the Axiado SPI DB controller
# good: [b6376dbed8e173f9571583b5d358b08ff394e864] spi: Simplify devm_spi_*_controller()
# good: [0cd9bf6a6d9a1861087236cc5c275b3bea83cfdd] ASoC: codecs: da7213: Move comma operator at the end of the line
# good: [22a4776a9ce50aa47f602d28f53ba9d613a38f49] ASoC: codecs: es8375: remove unnecessary format check
# good: [75d208bddcca55ec31481420fbb4d6c9703ba195] spi: stm32: avoid __maybe_unused and use pm_ptr
# good: [04b61513dfe40f80f0dcc795003637b510522b3c] ASoC: SDCA: Replace use of system_wq with system_dfl_wq
# good: [9bf0bd7bdea6c402007ffb784dd0c0f704aa2310] ASoC: nau8821: Sort #include directives
# good: [96d337436fe0921177a6090aeb5bb214753654fc] spi: dt-bindings: at91: add microchip,lan9691-spi
# good: [52ddc0106c77ff0eacf07b309833ae6e6a4e8587] ASoC: es8328: Remove duplicate DAPM routes
# good: [211243b69533e968cc6f0259fb80ffee02fbe0ca] firmware: cs_dsp: test_bin: Add tests for offsets > 0xffff
# good: [420739112e95c9bb286b4e87875706925970abd3] ASoC: rt5575: Add the codec driver for the ALC5575
# good: [4c5e6d5b31bc623d89185d551681ab91cfd037c9] ASoC: codecs: ES8389: Update clock configuration
# good: [25abdc151a448a17d500ea9468ce32582c479faa] ASoC: rt1320: fix the remainder calculation of r0 value
# good: [284853affe73fe1ca9786bd52b934eb9d420a942] ASoC: rt1320: fix size_t format string
# good: [45e9066f3a487e9e26b842644364d045af054775] ASoC: Intel: avs: replace strcmp with sysfs_streq
# good: [0f698d742f628d02ab2a222f8cf5f793443865d0] spi: bcm63xx-hsspi: add support for 1-2-2 read ops
# good: [b0655377aa5a410df02d89170c20141a1a5bbc28] rust: regulator: replace `kernel::c_str!` with C-Strings
# good: [8db50f0fa43efe8799fd40b872dcdd39a90d7549] ASoC: rt1320: fix the warning the string may be truncated
# good: [99a3ef1e81cd1775bc1f8cc2ad188b1fc755d5cd] ASoC: SDCA: Add ASoC jack hookup in class driver
# good: [4ab48cc63e15cb619d641d1edf9a15a0a98875b2] ASoC: qcom: audioreach: Constify function arguments
# good: [c6bca73d699cfe00d3419566fdb2a45e112f44b0] ASoC: rt1320: Fix retry checking in rt1320_rae_load()
# good: [a2a631830deb382a3d27b6f52b2d654a3e6bb427] ASoC: qcom: Constify APR/GPR result structs
# good: [32a708ba5db50cf928a1f1b2039ceef33de2c286] regulator: Add rt8092 support
# good: [b39ef93a2e5b5f4289a3486d8a94a09a1e6a4c67] spi: stm32: perform small transfer in polling mode
# good: [7a8447fc71a09000cee5a2372b6efde45735d2c8] ASoC: codecs: wcd939x-sdw: use devres for regmap allocation
# good: [2a28b5240f2b328495c6565d277f438dbc583d61] ASoC: SOF: ipc4-control: Add support for generic bytes control
# good: [3622dc47a4b13e0ec86358c7b54a0b33bfcaa03c] ASoC: codec: rt286: Use devm_request_threaded_irq to manage IRQ lifetime and fix smatch warning
# good: [02e7af5b6423d2dbf82f852572f2fa8c00aafb19] ASoC: Intel: sof_rt5682: add tas2563 speaker amp support
# good: [29c8c00d9f9db5fb659b6f05f9e8964afc13f3e2] spi: add driver for NXP XSPI controller
# good: [9a6bc0a406608e2520f18d996483c9d2e4a9fb27] ASoC: codecs: ES8326: Add kcontrol for DRE
# good: [f764645cb85a8b8f58067289cdfed28f6c1cdf49] ASoC: codecs: tas2780: tidyup format check in tas2780_set_fmt()
# good: [7f7b350e4a65446f5d52ea8ae99e12eac8a972db] spi: stm32-qspi: Remove unneeded semicolon
# good: [1303c2903889b01d581083ed92e439e7544dd3e5] MAINTAINERS: Add MAINTAINERS entry for the ATCSPI200 SPI controller driver
# good: [524ee559948d8d079b13466e70fa741f909699c0] ASoC: SOF: Intel: hda: Only check SSP MCLK mask in case of IPC3
# good: [f25c7d709b93602ee9a08eba522808a18e1f5d56] ASoC: SOF: Intel: pci-nvl: Set on_demand_dsp_boot for NVL-S
# good: [f4acea9eef704607d1a950909ce3a52a770d6be2] spi: dt-bindings: st,stm32-spi: add 'power-domains' property
# good: [e39011184f23de3d04ca8e80b4df76c9047b4026] ASoC: SDCA: functions: Fix confusing cleanup.h syntax
# good: [fa08b566860bca8ebf9300090b85174c34de7ca5] spi: rzv2h-rspi: add support for DMA mode
# good: [03d281f384768610bf90697bce9e35d3d596de77] rust: regulator: add __rust_helper to helpers
# good: [b884e34994ca41f7b7819f3c41b78ff494787b27] spi: spi-fsl-lpspi: convert min_t() to simple min()
# good: [124f6155f3d97b0e33f178c10a5138a42c8fd207] ASoC: renesas: rz-ssi: Add support for 32 bits sample width
# good: [aa30193af8873b3ccfd70a4275336ab6cbd4e5e6] ASoC: Intel: catpt: Drop superfluous space in PCM code
# good: [0bb160c92ad400c692984763996b758458adea17] ASoC: qcom: Minor readability improve with new lines
# good: [fee876b2ec75dcc18fdea154eae1f5bf14d82659] spi: stm32-qspi: Simplify SMIE interrupt test
# good: [81acbdc51bbbec822a1525481f2f70677c47aee0] ASoC: sdw-mockup: Drop dummy remove function
# good: [9e92c559d49d6fb903af17a31a469aac51b1766d] regulator: max77675: Add MAX77675 regulator driver
# good: [ba9b28652c75b07383e267328f1759195d5430f7] spi: imx: enable DMA mode for target operation
# good: [6c177775dcc5e70a64ddf4ee842c66af498f2c7c] Merge branch 'next/drivers' into for-next
git bisect start '615aad0f61e0c7a898184a394dc895c610100d4f' '50814c5ce8d8f6751fd49c818abeb8853f8be2df' '702ce71d32f2c30b4f45b7c6b701d87583c58df8' 'd0ab89951197f0fc509a0cd732d830880e79c2d4' '7f428282fde34f06f3ab898b8a9081bf93a41f22' 'cafadbf430f4b2f3ca4158de48ef6ba4d97fbf17' '00ca2dd431fa2acb07b3ecc6ce49fb9a0a4d72cb' '3495a5df94a9ad7a8940bcb3ebfda58255f5b952' 'a18467a50eddbd7c6548b53b25b68e5454ceb587' 'c3608162a95a259c669cf9fdccf900782fa8d902' '3c5ddd56aa93048314c64533c21e731a44b0f067' '20c4701b75a3d6ce09d61e17125aefe77e7eb333' '37fbc1ab0f225d23f0839260a11375b4f1f7cf8c' '83ba6efa711fad83a0fbf02178ad64d3906d8d09' '4fbd3b2ec04dc6ef93090ec24733a5c5671fb71f' '7a3d1b04d938f31e112fe09c0ffc1af830ba1f6d' 'dccc66b0e92d48d9a1908a3ccb8142e0ee3381f5' '61d2a7699ab39d448f44919ef15c16187e6f70ec' '519d0a6b2ca5a891340b6c24a4c40545f518e1a8' 'da7afdc79cba00f952df12cd579e44832d829c0a' '8a98e7f55f975360975083166e21982ef307b8fd' '10303b32519f52a5afd40593a507543143c8ec6a' '62b04225e99a5d1c71c5c73d2aa6618bc2c0738f' 'de9f1b1583aecb246b659effb03f2456604fab64' 'a014c203b54d9013ad52ad8a531cf46e71028f2b' 'e7c30ac379b429d439eb62ae1bb69720a6701e26' '09dc08b396c954820f119e1ab0c7d72333c18323' '6be9ea62afedef0f976eb3dba4c117be0c1d3809' 'e590752119029d87ce46d725e11245a52d22e1fe' '77157cb45c66bd652a08a360693fcced558c5ef9' 'b0fc1e7701940d12ea2c41f386aa552bc4cc3629' '8618271887ca10ac5108fe7e1d82ba8f1b152cf9' '8672e4b51adfc57150f3862b1665faff0acf1bad' 'fc6ceb7e4ea746e663ff8c5593e67ad8ccbee34a' '83aee46dc2142eed2dc40b5cef0e9e08e14cac42' '8d38423d9dea7353a8a54a3ab2e0d0aa04ed34d0' 'b9198ce5c6dfee19b9662dda95ba559af9cdf53f' 'db4371d13f82fb12463fe053f4864980a2af2106' 'b6376dbed8e173f9571583b5d358b08ff394e864' '0cd9bf6a6d9a1861087236cc5c275b3bea83cfdd' '22a4776a9ce50aa47f602d28f53ba9d613a38f49' '75d208bddcca55ec31481420fbb4d6c9703ba195' '04b61513dfe40f80f0dcc795003637b510522b3c' '9bf0bd7bdea6c402007ffb784dd0c0f704aa2310' '96d337436fe0921177a6090aeb5bb214753654fc' '52ddc0106c77ff0eacf07b309833ae6e6a4e8587' '211243b69533e968cc6f0259fb80ffee02fbe0ca' '420739112e95c9bb286b4e87875706925970abd3' '4c5e6d5b31bc623d89185d551681ab91cfd037c9' '25abdc151a448a17d500ea9468ce32582c479faa' '284853affe73fe1ca9786bd52b934eb9d420a942' '45e9066f3a487e9e26b842644364d045af054775' '0f698d742f628d02ab2a222f8cf5f793443865d0' 'b0655377aa5a410df02d89170c20141a1a5bbc28' '8db50f0fa43efe8799fd40b872dcdd39a90d7549' '99a3ef1e81cd1775bc1f8cc2ad188b1fc755d5cd' '4ab48cc63e15cb619d641d1edf9a15a0a98875b2' 'c6bca73d699cfe00d3419566fdb2a45e112f44b0' 'a2a631830deb382a3d27b6f52b2d654a3e6bb427' '32a708ba5db50cf928a1f1b2039ceef33de2c286' 'b39ef93a2e5b5f4289a3486d8a94a09a1e6a4c67' '7a8447fc71a09000cee5a2372b6efde45735d2c8' '2a28b5240f2b328495c6565d277f438dbc583d61' '3622dc47a4b13e0ec86358c7b54a0b33bfcaa03c' '02e7af5b6423d2dbf82f852572f2fa8c00aafb19' '29c8c00d9f9db5fb659b6f05f9e8964afc13f3e2' '9a6bc0a406608e2520f18d996483c9d2e4a9fb27' 'f764645cb85a8b8f58067289cdfed28f6c1cdf49' '7f7b350e4a65446f5d52ea8ae99e12eac8a972db' '1303c2903889b01d581083ed92e439e7544dd3e5' '524ee559948d8d079b13466e70fa741f909699c0' 'f25c7d709b93602ee9a08eba522808a18e1f5d56' 'f4acea9eef704607d1a950909ce3a52a770d6be2' 'e39011184f23de3d04ca8e80b4df76c9047b4026' 'fa08b566860bca8ebf9300090b85174c34de7ca5' '03d281f384768610bf90697bce9e35d3d596de77' 'b884e34994ca41f7b7819f3c41b78ff494787b27' '124f6155f3d97b0e33f178c10a5138a42c8fd207' 'aa30193af8873b3ccfd70a4275336ab6cbd4e5e6' '0bb160c92ad400c692984763996b758458adea17' 'fee876b2ec75dcc18fdea154eae1f5bf14d82659' '81acbdc51bbbec822a1525481f2f70677c47aee0' '9e92c559d49d6fb903af17a31a469aac51b1766d' 'ba9b28652c75b07383e267328f1759195d5430f7' '6c177775dcc5e70a64ddf4ee842c66af498f2c7c'
# test job: [702ce71d32f2c30b4f45b7c6b701d87583c58df8] https://lava.sirena.org.uk/scheduler/job/2393428
# test job: [d0ab89951197f0fc509a0cd732d830880e79c2d4] https://lava.sirena.org.uk/scheduler/job/2392919
# test job: [7f428282fde34f06f3ab898b8a9081bf93a41f22] https://lava.sirena.org.uk/scheduler/job/2391339
# test job: [cafadbf430f4b2f3ca4158de48ef6ba4d97fbf17] https://lava.sirena.org.uk/scheduler/job/2389514
# test job: [00ca2dd431fa2acb07b3ecc6ce49fb9a0a4d72cb] https://lava.sirena.org.uk/scheduler/job/2389628
# test job: [3495a5df94a9ad7a8940bcb3ebfda58255f5b952] https://lava.sirena.org.uk/scheduler/job/2389353
# test job: [a18467a50eddbd7c6548b53b25b68e5454ceb587] https://lava.sirena.org.uk/scheduler/job/2386094
# test job: [c3608162a95a259c669cf9fdccf900782fa8d902] https://lava.sirena.org.uk/scheduler/job/2387959
# test job: [3c5ddd56aa93048314c64533c21e731a44b0f067] https://lava.sirena.org.uk/scheduler/job/2386640
# test job: [20c4701b75a3d6ce09d61e17125aefe77e7eb333] https://lava.sirena.org.uk/scheduler/job/2386301
# test job: [37fbc1ab0f225d23f0839260a11375b4f1f7cf8c] https://lava.sirena.org.uk/scheduler/job/2386363
# test job: [83ba6efa711fad83a0fbf02178ad64d3906d8d09] https://lava.sirena.org.uk/scheduler/job/2387001
# test job: [4fbd3b2ec04dc6ef93090ec24733a5c5671fb71f] https://lava.sirena.org.uk/scheduler/job/2386168
# test job: [7a3d1b04d938f31e112fe09c0ffc1af830ba1f6d] https://lava.sirena.org.uk/scheduler/job/2377308
# test job: [dccc66b0e92d48d9a1908a3ccb8142e0ee3381f5] https://lava.sirena.org.uk/scheduler/job/2377141
# test job: [61d2a7699ab39d448f44919ef15c16187e6f70ec] https://lava.sirena.org.uk/scheduler/job/2375730
# test job: [519d0a6b2ca5a891340b6c24a4c40545f518e1a8] https://lava.sirena.org.uk/scheduler/job/2372387
# test job: [da7afdc79cba00f952df12cd579e44832d829c0a] https://lava.sirena.org.uk/scheduler/job/2372298
# test job: [8a98e7f55f975360975083166e21982ef307b8fd] https://lava.sirena.org.uk/scheduler/job/2372505
# test job: [10303b32519f52a5afd40593a507543143c8ec6a] https://lava.sirena.org.uk/scheduler/job/2372322
# test job: [62b04225e99a5d1c71c5c73d2aa6618bc2c0738f] https://lava.sirena.org.uk/scheduler/job/2369376
# test job: [de9f1b1583aecb246b659effb03f2456604fab64] https://lava.sirena.org.uk/scheduler/job/2368867
# test job: [a014c203b54d9013ad52ad8a531cf46e71028f2b] https://lava.sirena.org.uk/scheduler/job/2368397
# test job: [e7c30ac379b429d439eb62ae1bb69720a6701e26] https://lava.sirena.org.uk/scheduler/job/2366032
# test job: [09dc08b396c954820f119e1ab0c7d72333c18323] https://lava.sirena.org.uk/scheduler/job/2365474
# test job: [6be9ea62afedef0f976eb3dba4c117be0c1d3809] https://lava.sirena.org.uk/scheduler/job/2365609
# test job: [e590752119029d87ce46d725e11245a52d22e1fe] https://lava.sirena.org.uk/scheduler/job/2364789
# test job: [77157cb45c66bd652a08a360693fcced558c5ef9] https://lava.sirena.org.uk/scheduler/job/2363794
# test job: [b0fc1e7701940d12ea2c41f386aa552bc4cc3629] https://lava.sirena.org.uk/scheduler/job/2364720
# test job: [8618271887ca10ac5108fe7e1d82ba8f1b152cf9] https://lava.sirena.org.uk/scheduler/job/2364881
# test job: [8672e4b51adfc57150f3862b1665faff0acf1bad] https://lava.sirena.org.uk/scheduler/job/2363802
# test job: [fc6ceb7e4ea746e663ff8c5593e67ad8ccbee34a] https://lava.sirena.org.uk/scheduler/job/2364433
# test job: [83aee46dc2142eed2dc40b5cef0e9e08e14cac42] https://lava.sirena.org.uk/scheduler/job/2363989
# test job: [8d38423d9dea7353a8a54a3ab2e0d0aa04ed34d0] https://lava.sirena.org.uk/scheduler/job/2354063
# test job: [b9198ce5c6dfee19b9662dda95ba559af9cdf53f] https://lava.sirena.org.uk/scheduler/job/2354856
# test job: [db4371d13f82fb12463fe053f4864980a2af2106] https://lava.sirena.org.uk/scheduler/job/2354230
# test job: [b6376dbed8e173f9571583b5d358b08ff394e864] https://lava.sirena.org.uk/scheduler/job/2349545
# test job: [0cd9bf6a6d9a1861087236cc5c275b3bea83cfdd] https://lava.sirena.org.uk/scheduler/job/2348802
# test job: [22a4776a9ce50aa47f602d28f53ba9d613a38f49] https://lava.sirena.org.uk/scheduler/job/2343130
# test job: [75d208bddcca55ec31481420fbb4d6c9703ba195] https://lava.sirena.org.uk/scheduler/job/2337394
# test job: [04b61513dfe40f80f0dcc795003637b510522b3c] https://lava.sirena.org.uk/scheduler/job/2337624
# test job: [9bf0bd7bdea6c402007ffb784dd0c0f704aa2310] https://lava.sirena.org.uk/scheduler/job/2330756
# test job: [96d337436fe0921177a6090aeb5bb214753654fc] https://lava.sirena.org.uk/scheduler/job/2330496
# test job: [52ddc0106c77ff0eacf07b309833ae6e6a4e8587] https://lava.sirena.org.uk/scheduler/job/2330490
# test job: [211243b69533e968cc6f0259fb80ffee02fbe0ca] https://lava.sirena.org.uk/scheduler/job/2330643
# test job: [420739112e95c9bb286b4e87875706925970abd3] https://lava.sirena.org.uk/scheduler/job/2330595
# test job: [4c5e6d5b31bc623d89185d551681ab91cfd037c9] https://lava.sirena.org.uk/scheduler/job/2330948
# test job: [25abdc151a448a17d500ea9468ce32582c479faa] https://lava.sirena.org.uk/scheduler/job/2307350
# test job: [284853affe73fe1ca9786bd52b934eb9d420a942] https://lava.sirena.org.uk/scheduler/job/2298066
# test job: [45e9066f3a487e9e26b842644364d045af054775] https://lava.sirena.org.uk/scheduler/job/2295621
# test job: [0f698d742f628d02ab2a222f8cf5f793443865d0] https://lava.sirena.org.uk/scheduler/job/2295231
# test job: [b0655377aa5a410df02d89170c20141a1a5bbc28] https://lava.sirena.org.uk/scheduler/job/2291689
# test job: [8db50f0fa43efe8799fd40b872dcdd39a90d7549] https://lava.sirena.org.uk/scheduler/job/2292502
# test job: [99a3ef1e81cd1775bc1f8cc2ad188b1fc755d5cd] https://lava.sirena.org.uk/scheduler/job/2290488
# test job: [4ab48cc63e15cb619d641d1edf9a15a0a98875b2] https://lava.sirena.org.uk/scheduler/job/2290397
# test job: [c6bca73d699cfe00d3419566fdb2a45e112f44b0] https://lava.sirena.org.uk/scheduler/job/2290128
# test job: [a2a631830deb382a3d27b6f52b2d654a3e6bb427] https://lava.sirena.org.uk/scheduler/job/2281785
# test job: [32a708ba5db50cf928a1f1b2039ceef33de2c286] https://lava.sirena.org.uk/scheduler/job/2279465
# test job: [b39ef93a2e5b5f4289a3486d8a94a09a1e6a4c67] https://lava.sirena.org.uk/scheduler/job/2269679
# test job: [7a8447fc71a09000cee5a2372b6efde45735d2c8] https://lava.sirena.org.uk/scheduler/job/2271774
# test job: [2a28b5240f2b328495c6565d277f438dbc583d61] https://lava.sirena.org.uk/scheduler/job/2266163
# test job: [3622dc47a4b13e0ec86358c7b54a0b33bfcaa03c] https://lava.sirena.org.uk/scheduler/job/2268465
# test job: [02e7af5b6423d2dbf82f852572f2fa8c00aafb19] https://lava.sirena.org.uk/scheduler/job/2263583
# test job: [29c8c00d9f9db5fb659b6f05f9e8964afc13f3e2] https://lava.sirena.org.uk/scheduler/job/2263419
# test job: [9a6bc0a406608e2520f18d996483c9d2e4a9fb27] https://lava.sirena.org.uk/scheduler/job/2263708
# test job: [f764645cb85a8b8f58067289cdfed28f6c1cdf49] https://lava.sirena.org.uk/scheduler/job/2263393
# test job: [7f7b350e4a65446f5d52ea8ae99e12eac8a972db] https://lava.sirena.org.uk/scheduler/job/2263713
# test job: [1303c2903889b01d581083ed92e439e7544dd3e5] https://lava.sirena.org.uk/scheduler/job/2263162
# test job: [524ee559948d8d079b13466e70fa741f909699c0] https://lava.sirena.org.uk/scheduler/job/2243761
# test job: [f25c7d709b93602ee9a08eba522808a18e1f5d56] https://lava.sirena.org.uk/scheduler/job/2243682
# test job: [f4acea9eef704607d1a950909ce3a52a770d6be2] https://lava.sirena.org.uk/scheduler/job/2243493
# test job: [e39011184f23de3d04ca8e80b4df76c9047b4026] https://lava.sirena.org.uk/scheduler/job/2231781
# test job: [fa08b566860bca8ebf9300090b85174c34de7ca5] https://lava.sirena.org.uk/scheduler/job/2232081
# test job: [03d281f384768610bf90697bce9e35d3d596de77] https://lava.sirena.org.uk/scheduler/job/2231184
# test job: [b884e34994ca41f7b7819f3c41b78ff494787b27] https://lava.sirena.org.uk/scheduler/job/2231834
# test job: [124f6155f3d97b0e33f178c10a5138a42c8fd207] https://lava.sirena.org.uk/scheduler/job/2232196
# test job: [aa30193af8873b3ccfd70a4275336ab6cbd4e5e6] https://lava.sirena.org.uk/scheduler/job/2231987
# test job: [0bb160c92ad400c692984763996b758458adea17] https://lava.sirena.org.uk/scheduler/job/2232057
# test job: [fee876b2ec75dcc18fdea154eae1f5bf14d82659] https://lava.sirena.org.uk/scheduler/job/2231321
# test job: [81acbdc51bbbec822a1525481f2f70677c47aee0] https://lava.sirena.org.uk/scheduler/job/2231999
# test job: [9e92c559d49d6fb903af17a31a469aac51b1766d] https://lava.sirena.org.uk/scheduler/job/2231743
# test job: [ba9b28652c75b07383e267328f1759195d5430f7] https://lava.sirena.org.uk/scheduler/job/2231572
# test job: [6c177775dcc5e70a64ddf4ee842c66af498f2c7c] https://lava.sirena.org.uk/scheduler/job/2058633
# test job: [615aad0f61e0c7a898184a394dc895c610100d4f] https://lava.sirena.org.uk/scheduler/job/2407321
# bad: [615aad0f61e0c7a898184a394dc895c610100d4f] Add linux-next specific files for 20260126
git bisect bad 615aad0f61e0c7a898184a394dc895c610100d4f
# test job: [a85cfbd09f2d2f3bfab8fbe8246d0ae43a0c1628] https://lava.sirena.org.uk/scheduler/job/2407528
# bad: [a85cfbd09f2d2f3bfab8fbe8246d0ae43a0c1628] Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git
git bisect bad a85cfbd09f2d2f3bfab8fbe8246d0ae43a0c1628
# test job: [75fe66db9e85a2fd9743f7598a2aaea9eb5fbfd7] https://lava.sirena.org.uk/scheduler/job/2407694
# bad: [75fe66db9e85a2fd9743f7598a2aaea9eb5fbfd7] Merge branch 'xtensa-for-next' of https://github.com/jcmvbkbc/linux-xtensa.git
git bisect bad 75fe66db9e85a2fd9743f7598a2aaea9eb5fbfd7
# test job: [0578997f52fb9a1b9adfc5fe5a95ceab4bb331d2] https://lava.sirena.org.uk/scheduler/job/2407737
# good: [0578997f52fb9a1b9adfc5fe5a95ceab4bb331d2] Merge branch 'soc_fsl' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux.git
git bisect good 0578997f52fb9a1b9adfc5fe5a95ceab4bb331d2
# test job: [5cd67271caee30972d751ab3763c3de4b1fa73d0] https://lava.sirena.org.uk/scheduler/job/2407794
# good: [5cd67271caee30972d751ab3763c3de4b1fa73d0] Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git
git bisect good 5cd67271caee30972d751ab3763c3de4b1fa73d0
# test job: [039a29817a494720c25222b6daf104bf230583a7] https://lava.sirena.org.uk/scheduler/job/2407855
# good: [039a29817a494720c25222b6daf104bf230583a7] Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
git bisect good 039a29817a494720c25222b6daf104bf230583a7
# test job: [a142a51e64a948a70e8bcd5810fca89cab6347a5] https://lava.sirena.org.uk/scheduler/job/2407950
# bad: [a142a51e64a948a70e8bcd5810fca89cab6347a5] Merge branch 'clk-next' of https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
git bisect bad a142a51e64a948a70e8bcd5810fca89cab6347a5
# test job: [f5b748e97c52c31ad73b3534dfd1905efe664cc1] https://lava.sirena.org.uk/scheduler/job/2408066
# bad: [f5b748e97c52c31ad73b3534dfd1905efe664cc1] Merge branch 'clk-mediatek' into clk-next
git bisect bad f5b748e97c52c31ad73b3534dfd1905efe664cc1
# test job: [df9e5d59dcebe3217f1f5925f51b6beeb780c9b7] https://lava.sirena.org.uk/scheduler/job/2408105
# good: [df9e5d59dcebe3217f1f5925f51b6beeb780c9b7] Merge branch 'clk-spacemit' into clk-next
git bisect good df9e5d59dcebe3217f1f5925f51b6beeb780c9b7
# test job: [e98a16bf3cc49397a0fd88fe48d24e5f5f885707] https://lava.sirena.org.uk/scheduler/job/2408143
# good: [e98a16bf3cc49397a0fd88fe48d24e5f5f885707] Merge branch 'clk-amlogic' into clk-next
git bisect good e98a16bf3cc49397a0fd88fe48d24e5f5f885707
# test job: [e9955171948a226ee834a3092d71684acce84b65] https://lava.sirena.org.uk/scheduler/job/2408163
# good: [e9955171948a226ee834a3092d71684acce84b65] Merge branch 'clk-cleanup' into clk-next
git bisect good e9955171948a226ee834a3092d71684acce84b65
# test job: [ecffd05839b32f17bde1f3701b68ab182a837b07] https://lava.sirena.org.uk/scheduler/job/2408248
# bad: [ecffd05839b32f17bde1f3701b68ab182a837b07] clk: mediatek: Pass device to clk_hw_register for PLLs
git bisect bad ecffd05839b32f17bde1f3701b68ab182a837b07
# test job: [a2ed1aed687a21738a6c8bd4043149c443298e88] https://lava.sirena.org.uk/scheduler/job/2408288
# good: [a2ed1aed687a21738a6c8bd4043149c443298e88] dt-bindings: clock: mediatek,mt7622-pciesys: Remove syscon compatible
git bisect good a2ed1aed687a21738a6c8bd4043149c443298e88
# test job: [c9ced38af56fe6411118c6bc6522eab80849326d] https://lava.sirena.org.uk/scheduler/job/2408615
# bad: [c9ced38af56fe6411118c6bc6522eab80849326d] clk: mediatek: Refactor pll registration to pass device
git bisect bad c9ced38af56fe6411118c6bc6522eab80849326d
# test job: [669917676e93fca5ea3c66fc9539830312bec58e] https://lava.sirena.org.uk/scheduler/job/2409704
# bad: [669917676e93fca5ea3c66fc9539830312bec58e] clk: Respect CLK_OPS_PARENT_ENABLE during recalc
git bisect bad 669917676e93fca5ea3c66fc9539830312bec58e
# first bad commit: [669917676e93fca5ea3c66fc9539830312bec58e] clk: Respect CLK_OPS_PARENT_ENABLE during recalc | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Tue, 27 Jan 2026 17:01:29 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Tue, Jan 27, 2026 at 05:01:35PM +0000, Mark Brown wrote:
I am also seeing some similar regressions even earlier on i.MX8MP
platforms, though they're resetting even earlier before any output is
produced (even with earlycon). Didn't confirm yet with a revert or
anything though. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Tue, 27 Jan 2026 17:25:04 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Tuesday, 27 January 2026 18:25:04 Central European Standard Time Mark Brown wrote:
Someone else seemingly bisected to this commit on i.MX8MP as well
and replied to the RESEND of the series, and confirmed with a
revert[1].
I'm somewhat surprised by this, because to me it doesn't make intuitive
sense that some platforms would rely on CLK_OPS_PARENT_ENABLE to not
enable the parent clock during a recalc.
Can someone let me know which clocks (with which parent) in those
affected devices is causing this? I'm wondering if this change
unmasked some undeclared dependency that it's now stumbling over
because it's enabling the parent earlier than ever.
Would appreciate if we could fix up the affected platforms rather
than revert this, because the platform I added this for was
definitely using a parent-child relationship, and definitely
needed to have the parent clock on during recalc.
I can always bring back the RPM model I went for previously, but
that feels like more of a hack around this caveat than a proper
description of the clock relationship.
To not have me break everyone's -next for days on end, feel free
to drop this patch. MT8196, which this was added for, doesn't boot
with mainline yet anyway.
Kind regards,
Nicolas Frattaroli
https://lore.kernel.org/all/6239343.lOV4Wx5bFT@steina-w/ [1] | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Tue, 27 Jan 2026 19:18:02 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Tue, Jan 27, 2026 at 07:18:02PM +0100, Nicolas Frattaroli wrote:
Do you have a debugging patch we could run which would say which clocks
are impacted? I guess it's more of an issue for the platforms that give
no output but for at least Avenger96 I was getting earlycon output.
Please, this is making my test lab miserable. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Tue, 27 Jan 2026 23:14:29 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Wednesday, 28 January 2026 00:14:29 Central European Standard Time Mark Brown wrote:
Try this one
---
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 1b0f9d567f48..fa1443517768 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1921,13 +1921,21 @@ static unsigned long clk_recalc(struct clk_core *core,
unsigned long rate = parent_rate;
if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
- if (core->flags & CLK_OPS_PARENT_ENABLE)
+ if (core->flags & CLK_OPS_PARENT_ENABLE) {
+ pr_info("%s: enabling parent %s for %s\n", __func__,
+ core->parent ? core->parent->name : "(null)",
+ core->name);
clk_core_prepare_enable(core->parent);
+ }
rate = core->ops->recalc_rate(core->hw, parent_rate);
- if (core->flags & CLK_OPS_PARENT_ENABLE)
+ if (core->flags & CLK_OPS_PARENT_ENABLE) {
+ pr_info("%s: disabling parent %s for %s\n", __func__,
+ core->parent ? core->parent->name : "(null)",
+ core->name);
clk_core_disable_unprepare(core->parent);
+ }
clk_pm_runtime_put(core);
}
@@ -4038,8 +4046,12 @@ static int __clk_core_init(struct clk_core *core)
*/
clk_core_update_duty_cycle_nolock(core);
- if (core->flags & CLK_OPS_PARENT_ENABLE)
+ if (core->flags & CLK_OPS_PARENT_ENABLE) {
+ pr_info("%s: enabling parent %s for %s\n", __func__,
+ core->parent ? core->parent->name : "(null)",
+ core->name);
clk_core_prepare_enable(core->parent);
+ }
/*
* Set clk's rate. The preferred method is to use .recalc_rate. For
@@ -4056,8 +4068,12 @@ static int __clk_core_init(struct clk_core *core)
rate = 0;
core->rate = core->req_rate = rate;
- if (core->flags & CLK_OPS_PARENT_ENABLE)
+ if (core->flags & CLK_OPS_PARENT_ENABLE) {
+ pr_info("%s: disabling parent %s for %s\n", __func__,
+ core->parent ? core->parent->name : "(null)",
+ core->name);
clk_core_disable_unprepare(core->parent);
+ }
/*
* Enable CLK_IS_CRITICAL clocks so newly added critical clocks
---
I don't remember if printk buffers are flushed after each invocation and
couldn't quickly find a kernel parameter to control this, but from
experience I think these prints should show up if it then hangs the SoC
on the very next line.
The good news is that the rest of the series can stay without doing
any harm if this single patch gets dropped, and I can re-attempt
this in the next cycle.
Kind regards,
Nicolas Frattaroli | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Wed, 28 Jan 2026 15:09:46 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Wed, Jan 28, 2026 at 03:09:46PM +0100, Nicolas Frattaroli wrote:
For the Avenger96 that says:
[ 0.347816] __clk_core_init: enabling parent ck_hse for ck_per
[ 0.352230] __clk_core_init: disabling parent ck_hse for ck_per
[ 0.358207] __clk_core_init: enabling parent pll1_p for ck_mpu
[ 0.364005] __clk_core_init: disabling parent pll1_p for ck_mpu
https://lava.sirena.org.uk/scheduler/job/2412562#L563 | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 28 Jan 2026 14:47:08 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| Hi everyone,
Am Mittwoch, 28. Januar 2026, 15:47:08 CET schrieb Mark Brown:
This is for TQMa8MPxL/MBa8MPxL:
[ 1.452788] __clk_core_init: enabling parent audio_pll1_out for clkout1_sel
[ 1.457677] __clk_core_init: disabling parent audio_pll1_out for clkout1_sel
[ 1.464270] __clk_core_init: enabling parent audio_pll1_out for clkout2_sel
[ 1.471760] __clk_core_init: disabling parent audio_pll1_out for clkout2_sel
[ 1.478360] __clk_core_init: enabling parent sys_pll2_500m for arm_a53_div
[ 1.485259] __clk_core_init: disabling parent sys_pll2_500m for arm_a53_div
Best regards,
Alexander
--
TQ-Systems GmbH | Mhlstrae 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht Mnchen, HRB 105018
Geschftsfhrer: Detlef Schneider, Rdiger Stahl, Stefan Schneider
http://www.tq-group.com/ | {
"author": "Alexander Stein <alexander.stein@ew.tq-group.com>",
"date": "Wed, 28 Jan 2026 15:55:54 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Wed, Jan 28, 2026 at 03:55:54PM +0100, Alexander Stein wrote:
As expected same result on i.MX8MP-EVK. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 28 Jan 2026 15:21:47 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Wednesday, 28 January 2026 15:47:08 Central European Standard Time Mark Brown wrote:
Okay, on this one, there may be a problem in the clock tree.
ck_mpu is marked CLK_IS_CRITICAL, but its parent, pll1_p, is not. Clock
core doesn't seem to check whether any children of a clock are marked as
critical before disabling it.
I'm not super familiar with the intended semantics of critical clocks.
If we need to manually mark all parents of critical clocks as critical
as well, then a (potentially partial) fix for the Avenger96 might be:
---
diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 2d9ccd96ec98..6bf3fad1e0dc 100644
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -1783,12 +1783,12 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
/* ODF */
- COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
+ COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), CLK_IS_CRITICAL,
_GATE(RCC_PLL1CR, 4, 0),
_NO_MUX,
_DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
- COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
+ COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), CLK_IS_CRITICAL,
_GATE(RCC_PLL2CR, 4, 0),
_NO_MUX,
_DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
@@ -1803,7 +1803,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_NO_MUX,
_DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
- COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
+ COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), CLK_IS_CRITICAL,
_GATE(RCC_PLL3CR, 4, 0),
_NO_MUX,
_DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
---
I just looked for CLK_IS_CRITICAL clocks in that file that have the
CLK_OPS_PARENT_ENABLE flag, and marked their PLL parents as critical
as well.
An alternate approach would be to skip the parent enable/disable pair
in the problematic patch in __clk_core_init for clocks that are marked
as critical, because if the parent wasn't on for a critical clock then
we wouldn't be in that function, we would be dead.
Kind regards,
Nicolas Frattaroli | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Wed, 28 Jan 2026 17:04:55 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Wednesday, 28 January 2026 16:21:47 Central European Standard Time Mark Brown wrote:
This one puzzles me a little. arm_a53_div is neither marked critical
nor is its parent. If arm_a53_div is required for the system to function,
then I'd have expected at least it to be marked as critical, allowing us
to do the workaround in init I proposed as an alternate solution for the
stm32mp1 in my other reply.
Also, after reading the code some more, I think that alternate solution
has a simpler implementation: move the parent disable to after the
if (core->flags & CLK_IS_CRITICAL) {
check in __clk_core_init.
One explanation is that some other critical clock hangs off sys_pll2_500m,
but we're spoiled for choice here. I can't think of a simple fix right now
that I feel confident in.
Every IMX8MP composite clock that isn't critical seems to set
IMX_COMPOSITE_CLK_FLAGS_DEFAULT, which includes CLK_OPS_PARENT_ENABLE,
which seems like a pretty weird choice to make when you then rely on
the parent not getting touched during __clk_core_init.
I will try to get an RFC fix out tonight (CET). I think STM32MP1 is
falling over because I messed up, and i.MX8MP is falling over due to
a combination of me messing up and its clock driver messing up.
Kind regards,
Nicolas Frattaroli | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Wed, 28 Jan 2026 17:31:35 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Wed, Jan 28, 2026 at 05:31:35PM +0100, Nicolas Frattaroli wrote:
Given that all the cores in the system are A53s I rather fear that it is
in fact critical and should be marked as such. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 28 Jan 2026 17:08:28 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| Quoting Nicolas Frattaroli (2026-01-28 09:04:55)
Marking parents critical hasn't been strictly necessary so far because
we've been relying on the prepare/enable count on a critical child to
keep the parent prepared/enabled.
The parent may not be known yet in __clk_core_init() because we lazily
find parents. Putting it another way, we can get to the recalc_rate()
call in __clk_core_init() for a clk with CLK_OPS_PARENT_ENABLE when the
parent pointer is NULL. This hasn't been a problem because when we adopt
the orphan clk the rate is recalculated (see
clk_core_reparent_orphans_nolock()).
I don't see an easy way out of this problem because in general we need
to know a clk with CLK_OPS_PARENT_ENABLE is parented enough to be able
to read the registers when calling clk_ops like recalc_rate() (and
probably get_parent() as well meaning that clk_op can't touch
hardware?). Maybe the simplest approach is to skip any sort of hardware
access when this flag is set during setup and reparenting.
BTW, I don't know what this patch is actually fixing, so I'm going to
revert it. When it is resubmitted please describe the problem you're
seeing. | {
"author": "Stephen Boyd <sboyd@kernel.org>",
"date": "Wed, 28 Jan 2026 12:01:22 -0700",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Wednesday, 28 January 2026 20:01:22 Central European Standard Time Stephen Boyd wrote:
In this instance, it doesn't seem like the parent pointer is null, since
it does print a parent clock name. I think the problem really is that the
parent gets disabled before the CLK_IS_CRITICAL check re-enables it.
The issue both SoCs seem to run into is that the parent gets disabled
when it shouldn't be, which I fixed in [1]. I don't think any platform
that already worked before this change will stop working with this fix
and the fix for the fix in [1], because if the parent is absent, then
the enable/disables are no-ops anyway. NULL clocks are explicitly
handled by the common clock framework.
The justification got lost in the revisions of the series this was done
in. It's to deal with the MediaTek MT8196's MFGPLL clocks, where the
parent clock needs to be on before the clock registers of the child
clock can be touched in any way. I first modeled this as an RPM clock,
but Angelo didn't like this approach, and with some hackery I could sort
of see that the child clock indeed does not tick if the would-be RPM clock
is off, so it must be a parent clock instead.
The problem with making it a parent clock and adding this flag to it though
is that the flag is not respected in recalc_rate, so it reads from an
unclocked register.
If you want me to make it an RPM clock instead, I can do that, but then
we're leaking that the NXP i.MX8MP has a broken clock driver into the
device tree bindings of the MediaTek MT8196 PLLs, which seems like a hard
sell for the DT bindings maintainers.
So in conclusion, I'm fairly confident I've found a fix for the fix, and
I'm also very confident the problem doesn't go as deep as you fear. I'll
squash the fix for the fix into the fix when I resubmit the fix with a
fix for the i.MX, but that'll have to wait until after -rc1 I think.
Kind regards,
Nicolas Frattaroli
Link: https://lore.kernel.org/all/20260128-ops-parent-enable-fix-v1-1-ff39cc37f98d@collabora.com/ [1] | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Wed, 28 Jan 2026 20:59:24 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and fix the common clock framework core to take
CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
The reason why this is all in the same series is that it grew out of me
first modelling this as an RPM clock for mfgpll, which Angelo disagreed
with, so I did some investigation and it seems MFG_EB indeed is a parent
clock. However, the earlier refactoring to pass the device pointer down
is still useful.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct
clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with
CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
drivers/clk/clk.c | 13 +++++++++++++
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++--
drivers/clk/mediatek/clk-mt6765.c | 2 +-
drivers/clk/mediatek/clk-mt6779.c | 2 +-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 2 +-
drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt7629.c | 2 +-
drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +-
drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++-
drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +-
drivers/clk/mediatek/clk-mt8196-mfg.c | 15 ++++++++-------
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +-
drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +-
drivers/clk/mediatek/clk-pll.c | 19 +++++++++++++------
drivers/clk/mediatek/clk-pll.h | 15 ++++++++-------
drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
drivers/clk/mediatek/clk-pllfh.h | 2 +-
32 files changed, 87 insertions(+), 59 deletions(-)
---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
| On Wed, Jan 28, 2026 at 12:01:22PM -0700, Stephen Boyd wrote:
The patch is still in -next today and the issues it causes are still
visible. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Mon, 2 Feb 2026 16:54:32 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH] tracing: remove __printf() attribute on __ftrace_vbprintk() | From: Arnd Bergmann <arnd@arndb.de>
The sunrpc change to use trace_printk() for debugging caused
a new warning for every instance of dprintk() in some configurations,
when -Wformat-security is enabled:
fs/nfs/getroot.c: In function 'nfs_get_root':
fs/nfs/getroot.c:90:17: error: format not a string literal and no format arguments [-Werror=format-security]
90 | nfs_errorf(fc, "NFS: Couldn't getattr on root");
I've been slowly chipping away at those warnings over time with the
intention of enabling them by default in the future. While I could not
figure out why this only happens for this one instance, I see that the
__trace_bprintk() function is always called with a local variable as
the format string, rather than a literal.
Remove the __printf(2,3) annotation on this function, as this is can
only be validated for literals. The format strings still get checked
because the underlying literal keeps getting passed into __trace_printk()
in the "else" branch, which is not taken but still evaluated for
compile-time warnings.
Fixes: ec7d8e68ef0e ("sunrpc: add a Kconfig option to redirect dfprintk() output to trace buffer")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
include/linux/trace_printk.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/linux/trace_printk.h b/include/linux/trace_printk.h
index bb5874097f24..2670ec7f4262 100644
--- a/include/linux/trace_printk.h
+++ b/include/linux/trace_printk.h
@@ -107,7 +107,6 @@ do { \
__trace_printk(_THIS_IP_, fmt, ##args); \
} while (0)
-extern __printf(2, 3)
int __trace_bprintk(unsigned long ip, const char *fmt, ...);
extern __printf(2, 3)
--
2.39.5
| On Mon, 2026-02-02 at 10:58 +0100, Arnd Bergmann wrote:
Acked-by: Jeff Layton <jlayton@kernel.org> | {
"author": "Jeff Layton <jlayton@kernel.org>",
"date": "Mon, 02 Feb 2026 06:37:56 -0500",
"thread_id": "20260202125959.49ce289f@gandalf.local.home.mbox.gz"
} |
lkml | [PATCH] tracing: remove __printf() attribute on __ftrace_vbprintk() | From: Arnd Bergmann <arnd@arndb.de>
The sunrpc change to use trace_printk() for debugging caused
a new warning for every instance of dprintk() in some configurations,
when -Wformat-security is enabled:
fs/nfs/getroot.c: In function 'nfs_get_root':
fs/nfs/getroot.c:90:17: error: format not a string literal and no format arguments [-Werror=format-security]
90 | nfs_errorf(fc, "NFS: Couldn't getattr on root");
I've been slowly chipping away at those warnings over time with the
intention of enabling them by default in the future. While I could not
figure out why this only happens for this one instance, I see that the
__trace_bprintk() function is always called with a local variable as
the format string, rather than a literal.
Remove the __printf(2,3) annotation on this function, as this is can
only be validated for literals. The format strings still get checked
because the underlying literal keeps getting passed into __trace_printk()
in the "else" branch, which is not taken but still evaluated for
compile-time warnings.
Fixes: ec7d8e68ef0e ("sunrpc: add a Kconfig option to redirect dfprintk() output to trace buffer")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
include/linux/trace_printk.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/linux/trace_printk.h b/include/linux/trace_printk.h
index bb5874097f24..2670ec7f4262 100644
--- a/include/linux/trace_printk.h
+++ b/include/linux/trace_printk.h
@@ -107,7 +107,6 @@ do { \
__trace_printk(_THIS_IP_, fmt, ##args); \
} while (0)
-extern __printf(2, 3)
int __trace_bprintk(unsigned long ip, const char *fmt, ...);
extern __printf(2, 3)
--
2.39.5
| On Mon, Feb 02, 2026 at 10:58:27AM +0100, Arnd Bergmann wrote:
Yeah, it was discussed in the past that binary printf() should not be annotated
as we have BPF code that doesn't compile (with the default WERROR=y).
--
With Best Regards,
Andy Shevchenko | {
"author": "Andy Shevchenko <andriy.shevchenko@linux.intel.com>",
"date": "Mon, 2 Feb 2026 19:57:21 +0200",
"thread_id": "20260202125959.49ce289f@gandalf.local.home.mbox.gz"
} |
lkml | [PATCH] tracing: remove __printf() attribute on __ftrace_vbprintk() | From: Arnd Bergmann <arnd@arndb.de>
The sunrpc change to use trace_printk() for debugging caused
a new warning for every instance of dprintk() in some configurations,
when -Wformat-security is enabled:
fs/nfs/getroot.c: In function 'nfs_get_root':
fs/nfs/getroot.c:90:17: error: format not a string literal and no format arguments [-Werror=format-security]
90 | nfs_errorf(fc, "NFS: Couldn't getattr on root");
I've been slowly chipping away at those warnings over time with the
intention of enabling them by default in the future. While I could not
figure out why this only happens for this one instance, I see that the
__trace_bprintk() function is always called with a local variable as
the format string, rather than a literal.
Remove the __printf(2,3) annotation on this function, as this is can
only be validated for literals. The format strings still get checked
because the underlying literal keeps getting passed into __trace_printk()
in the "else" branch, which is not taken but still evaluated for
compile-time warnings.
Fixes: ec7d8e68ef0e ("sunrpc: add a Kconfig option to redirect dfprintk() output to trace buffer")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
include/linux/trace_printk.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/linux/trace_printk.h b/include/linux/trace_printk.h
index bb5874097f24..2670ec7f4262 100644
--- a/include/linux/trace_printk.h
+++ b/include/linux/trace_printk.h
@@ -107,7 +107,6 @@ do { \
__trace_printk(_THIS_IP_, fmt, ##args); \
} while (0)
-extern __printf(2, 3)
int __trace_bprintk(unsigned long ip, const char *fmt, ...);
extern __printf(2, 3)
--
2.39.5
| On Mon, 2 Feb 2026 10:58:27 +0100
Arnd Bergmann <arnd@kernel.org> wrote:
Acked-by: Steven Rostedt (Google) <rostedt@goodmis.org>
-- Steve | {
"author": "Steven Rostedt <rostedt@goodmis.org>",
"date": "Mon, 2 Feb 2026 12:59:59 -0500",
"thread_id": "20260202125959.49ce289f@gandalf.local.home.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch with this DSA driver.
MxL862xx integrates a firmware running on an embedded processor (based on
Zephyr RTOS). Host interaction uses a simple netlink-like API transported
over MDIO/MMD.
This series includes only what's needed to pass traffic between user
ports and the CPU port: relayed MDIO to internal PHYs, basic port
enable/disable, and CPU-port special tagging.
The SerDes interface of the CPU port is automatically configured by the
switch after reset using a board-specific configuration stored together
with the firmware in the flash chip attached to the switch, so no action
is needed from the driver to setup the interface mode of the CPU port.
Also MAC settings of the PHY ports are automatically configured, which
means the driver works fine with phylink_mac_ops being all no-op stubs.
Multiple follow up series will bring support for setting up the other
SerDes PCS interface (ie. not used for the CPU port), bridge, VLAN, ...
offloading, and support for using an 802.1Q-based special tag instead of
the proprietary 8-byte tag.
---
basic DSA selftests were run, results:
* no_forwarding.sh: all tests PASS
* bridge_vlan_unaware.sh: all tests PASS
* bridge_vlan_mcast.sh: all tests PASS
* bridge_vlan_aware.sh: all tests PASS
* local_termination.sh: all tests PASS or XFAIL, except for
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
As obviously this is mostly testing the Linux software bridge at this
point so I didn't bother to run any of the FDB or MDB related tests.
Some mystery about the relationship between the sub-interface ID and CTP
port assignment remains for now, so I cannot yet fully explain the magic
numbers when calculating the two.
(Why is it neccesary to allocate 23 CTPs when using port 9 as CPU port
while there are at most 17 phyiscal interfaces in total, and only at
most 13 when using one of the two SerDes as CPU interface? Why is there
an offset of 16 when calculating the sub-interface ID? How will a total
of 17 ports be possibly represented in a 4-bit field in the tag RX
path?)
At this point this doesn't impact functionality, and I hope for further
clarification discussing all that with MaxLinear engineers.
I believe the initial driver is anyway in good shape now, a follow-up
series addressing configuring the SerDes interfaces will also have to
take care of CTP assignment and sub-interfaces to not hit the mentioned
4-bit cap in the tag driver.
Changes since v11:
Address comments reported by Jakub Kicinski using netdev-ai
https://patchwork.kernel.org/comment/26767905/
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* list switch variants in Kconfig starting with dash ('-')
* remove the __packed attribute on structs which are
naturally packed according to C rules (ie. one other struct
with only a single byte-aligned member)
* log error in mxl862xx_port_disable()
* introduce !NULL check for return value of dsa_to_port() in
mxl862xx_add_single_port_bridge
* check cpu_dp being non-NULL before dereferencing dp->cpu_dp
* use non-racy and deterministic name for MII bus
* skip ports without cpu_dp assigned in mxl862xx_setup_cpu_bridge()
to avoid potential NULL-pointer dereference
* call dev_set_drvdata() only after dsa_register_switch() has been
successfully completed
Changes since v10:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* arrange local variables in reverse xmas tree order (again)
* use MXL862_NAME as .name in struct dsa_device_ops
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix fatal last-second changes dsa_port_is_unused vs. dsa_is_unused_port
and dsa_port_is_unused vs. dsa_is_unused_port
* use cpu_to_le16 in mxl862xx_configure_ctp_port
* improve formatting of some kerneldoc comments
Changes since v9:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* add microcontroller port 0
2/4 net: dsa: add tag format for MxL862xx switches
* count ports starting from 0
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix indentation in kernel-doc
* remove misleading comment regarding sub-interface IDs
* remove unused macros, set MXL862XX_MAX_PORTS to 17
* count ports starting from 0, 0 being the microcontroller
* improve port setup:
- split tag protocol and CTP port assignment
- use ports cpu_dp instead of relying on single (ie. first) CPU port
- handle CPU port like any other port
- prepare forward DT compatibility with multiple CPU ports
Changes since v8:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* remove practically unused struct hw_info
* lots of kerneldoc improvements in mxl862xx-api.h
* drop .mac_select_pcs() stub
* better handling for firmware error return value
* apply reverse xmas tree in mxl862xx_api_wrap
* guard headers with #ifdef macro
* include net/dsa.h and linux/mdio.h in mxl862xx.h
* call mxl862xx_port_fast_age() only once in .port_setup
* don't create isolation bridges for unused ports
* replace errornous cast with correct range of values denoting firmware errors
Changes since v7
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* use little-endian in bridge_port_config API
* remove duplciate assignment of br_port_cfg.bridge_port_id when setting
up CPU port
Changes since v6
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix kerneldoc style
Changes since RFC v5
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* remove unnecessary check for skb != NULL
* merge consecutively printed warnings into single dev_warn_ratelimited
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* include bridge and bridgeport API needed to isolate ports
* remove warning in .setup as ports are now isolated
* make ready-after-reset check more robust by adding delay
* sort structs in order of struct definitions
* best effort to sort functions without introducing additional prototypes
* always use enums with kerneldoc comments in mxl862xx-api.h
* remove bogus .phy_read and .phy_write DSA ops as the driver anyway registers
a user MDIO bus with Clause-22 and Clause-45 operations
* various small style fixes
Changes since RFC v4
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* drop unused precompiler macros
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* fix indentation
4/4 net: dsa: add basic initial driver for MxL862xx switches
* output warning in .setup regarding unknown pre-configuration
* add comment explaining why CFGGET is used in reset function
Changes since RFC v3
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* remove labels from example
* remove 'bindings for' from commit title
2/4 net: dsa: add tag format for MxL862xx switches
* describe fields and variables with comments
* sub-interface is only 5 bits
* harmonize Kconfig symbol name
* maintain alphabetic order in Kconfig
* fix typo s/beginnig/beginning/
* fix typo s/swtiches/switches/
* arrange local variables in reverse xmas tree order
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* poll switch readiness after reset
* implement driver shutdown
* added port_fast_aging API call and driver op
* unified port setup in new .port_setup op
* improve comment explaining special handlign for unaligned API read
* various typos and formatting improvements
Changes since RFC v2
1/4, 2/4, 3/4: unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix return value being uninitialized on error in mxl862xx_api_wrap()
* add missing description in kerneldoc comment of
struct mxl862xx_ss_sp_tag
Changes since initial RFC
1/4 dt-bindings: net: dsa: add bindings for MaxLinear MxL862xx
* better description in dt-bindings doc
2/4 net: dsa: add tag formats for MxL862xx switches
* make sure all tag fields are initialized
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* new patch
4/4 net: dsa: add basic initial driver for MxL862xx switches
* make use of struct mdio_device
* add phylink_mac_ops stubs
* drop leftover nonsense from mxl862xx_phylink_get_caps()
* fix endian conversions
* use __le32 instead of enum types in over-the-wire structs
* use existing MDIO_* macros whenever possible
* simplify API constants to be more readable
* use readx_poll_timeout instead of open-coding poll timeout loop
* add mxl862xx_reg_read() and mxl862xx_reg_write() helpers
* demystify error codes returned by the firmware
* add #defines for mxl862xx_ss_sp_tag member values
* move reset to dedicated function, clarify magic number being the
reset command ID
Daniel Golle (4):
dt-bindings: net: dsa: add MaxLinear MxL862xx
net: dsa: add tag format for MxL862xx switches
net: mdio: add unlocked mdiodev C45 bus accessors
net: dsa: add basic initial driver for MxL862xx switches
.../bindings/net/dsa/maxlinear,mxl862xx.yaml | 160 +++++
MAINTAINERS | 8 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/mxl862xx/Kconfig | 12 +
drivers/net/dsa/mxl862xx/Makefile | 3 +
drivers/net/dsa/mxl862xx/mxl862xx-api.h | 675 ++++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 49 ++
drivers/net/dsa/mxl862xx/mxl862xx-host.c | 245 +++++++
drivers/net/dsa/mxl862xx/mxl862xx-host.h | 12 +
drivers/net/dsa/mxl862xx/mxl862xx.c | 483 +++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx.h | 16 +
include/linux/mdio.h | 13 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 7 +
net/dsa/Makefile | 1 +
net/dsa/tag_mxl862xx.c | 110 +++
17 files changed, 1799 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
create mode 100644 drivers/net/dsa/mxl862xx/Kconfig
create mode 100644 drivers/net/dsa/mxl862xx/Makefile
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-api.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.h
create mode 100644 net/dsa/tag_mxl862xx.c
--
2.52.0
| Add documentation and an example for MaxLinear MxL86282 and MxL86252
switches.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
v12: no changes
v11: no changes
v10: add microcontroller port 0
v9: no changes
v8: no changes
v7: no changes
v6: no changes
v5: no changes
RFC v4:
* remove labels from example
* remove 'bindings for' from commit title
RFC v3: no changes
RFC v2: better description in dt-bindings doc
---
.../bindings/net/dsa/maxlinear,mxl862xx.yaml | 160 ++++++++++++++++++
MAINTAINERS | 6 +
2 files changed, 166 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
diff --git a/Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml b/Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
new file mode 100644
index 000000000000..6a60e0881a49
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/maxlinear,mxl862xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MaxLinear MxL862xx Ethernet Switch Family
+
+maintainers:
+ - Daniel Golle <daniel@makrotopia.org>
+
+description:
+ The MaxLinear MxL862xx switch family are multi-port Ethernet switches with
+ integrated 2.5GE PHYs. The MxL86252 has five PHY ports and the MxL86282
+ has eight PHY ports. Both models come with two 10 Gigabit/s SerDes
+ interfaces to be used to connect external PHYs or SFP cages, or as CPU
+ port.
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+properties:
+ compatible:
+ enum:
+ - maxlinear,mxl86252
+ - maxlinear,mxl86282
+
+ reg:
+ maxItems: 1
+ description: MDIO address of the switch
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ compatible = "maxlinear,mxl86282";
+ reg = <0>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Microcontroller port */
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ phy-handle = <&phy0>;
+ phy-mode = "internal";
+ };
+
+ port@2 {
+ reg = <2>;
+ phy-handle = <&phy1>;
+ phy-mode = "internal";
+ };
+
+ port@3 {
+ reg = <3>;
+ phy-handle = <&phy2>;
+ phy-mode = "internal";
+ };
+
+ port@4 {
+ reg = <4>;
+ phy-handle = <&phy3>;
+ phy-mode = "internal";
+ };
+
+ port@5 {
+ reg = <5>;
+ phy-handle = <&phy4>;
+ phy-mode = "internal";
+ };
+
+ port@6 {
+ reg = <6>;
+ phy-handle = <&phy5>;
+ phy-mode = "internal";
+ };
+
+ port@7 {
+ reg = <7>;
+ phy-handle = <&phy6>;
+ phy-mode = "internal";
+ };
+
+ port@8 {
+ reg = <8>;
+ phy-handle = <&phy7>;
+ phy-mode = "internal";
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "usxgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 0caa8aee5840..1abcdbc54a3f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15619,6 +15619,12 @@ S: Supported
F: drivers/net/phy/mxl-86110.c
F: drivers/net/phy/mxl-gpy.c
+MAXLINEAR MXL862XX SWITCH DRIVER
+M: Daniel Golle <daniel@makrotopia.org>
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
+
MCAN DEVICE DRIVER
M: Markus Schneider-Pargmann <msp@baylibre.com>
L: linux-can@vger.kernel.org
--
2.52.0 | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Sun, 1 Feb 2026 02:24:47 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch with this DSA driver.
MxL862xx integrates a firmware running on an embedded processor (based on
Zephyr RTOS). Host interaction uses a simple netlink-like API transported
over MDIO/MMD.
This series includes only what's needed to pass traffic between user
ports and the CPU port: relayed MDIO to internal PHYs, basic port
enable/disable, and CPU-port special tagging.
The SerDes interface of the CPU port is automatically configured by the
switch after reset using a board-specific configuration stored together
with the firmware in the flash chip attached to the switch, so no action
is needed from the driver to setup the interface mode of the CPU port.
Also MAC settings of the PHY ports are automatically configured, which
means the driver works fine with phylink_mac_ops being all no-op stubs.
Multiple follow up series will bring support for setting up the other
SerDes PCS interface (ie. not used for the CPU port), bridge, VLAN, ...
offloading, and support for using an 802.1Q-based special tag instead of
the proprietary 8-byte tag.
---
basic DSA selftests were run, results:
* no_forwarding.sh: all tests PASS
* bridge_vlan_unaware.sh: all tests PASS
* bridge_vlan_mcast.sh: all tests PASS
* bridge_vlan_aware.sh: all tests PASS
* local_termination.sh: all tests PASS or XFAIL, except for
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
As obviously this is mostly testing the Linux software bridge at this
point so I didn't bother to run any of the FDB or MDB related tests.
Some mystery about the relationship between the sub-interface ID and CTP
port assignment remains for now, so I cannot yet fully explain the magic
numbers when calculating the two.
(Why is it neccesary to allocate 23 CTPs when using port 9 as CPU port
while there are at most 17 phyiscal interfaces in total, and only at
most 13 when using one of the two SerDes as CPU interface? Why is there
an offset of 16 when calculating the sub-interface ID? How will a total
of 17 ports be possibly represented in a 4-bit field in the tag RX
path?)
At this point this doesn't impact functionality, and I hope for further
clarification discussing all that with MaxLinear engineers.
I believe the initial driver is anyway in good shape now, a follow-up
series addressing configuring the SerDes interfaces will also have to
take care of CTP assignment and sub-interfaces to not hit the mentioned
4-bit cap in the tag driver.
Changes since v11:
Address comments reported by Jakub Kicinski using netdev-ai
https://patchwork.kernel.org/comment/26767905/
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* list switch variants in Kconfig starting with dash ('-')
* remove the __packed attribute on structs which are
naturally packed according to C rules (ie. one other struct
with only a single byte-aligned member)
* log error in mxl862xx_port_disable()
* introduce !NULL check for return value of dsa_to_port() in
mxl862xx_add_single_port_bridge
* check cpu_dp being non-NULL before dereferencing dp->cpu_dp
* use non-racy and deterministic name for MII bus
* skip ports without cpu_dp assigned in mxl862xx_setup_cpu_bridge()
to avoid potential NULL-pointer dereference
* call dev_set_drvdata() only after dsa_register_switch() has been
successfully completed
Changes since v10:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* arrange local variables in reverse xmas tree order (again)
* use MXL862_NAME as .name in struct dsa_device_ops
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix fatal last-second changes dsa_port_is_unused vs. dsa_is_unused_port
and dsa_port_is_unused vs. dsa_is_unused_port
* use cpu_to_le16 in mxl862xx_configure_ctp_port
* improve formatting of some kerneldoc comments
Changes since v9:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* add microcontroller port 0
2/4 net: dsa: add tag format for MxL862xx switches
* count ports starting from 0
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix indentation in kernel-doc
* remove misleading comment regarding sub-interface IDs
* remove unused macros, set MXL862XX_MAX_PORTS to 17
* count ports starting from 0, 0 being the microcontroller
* improve port setup:
- split tag protocol and CTP port assignment
- use ports cpu_dp instead of relying on single (ie. first) CPU port
- handle CPU port like any other port
- prepare forward DT compatibility with multiple CPU ports
Changes since v8:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* remove practically unused struct hw_info
* lots of kerneldoc improvements in mxl862xx-api.h
* drop .mac_select_pcs() stub
* better handling for firmware error return value
* apply reverse xmas tree in mxl862xx_api_wrap
* guard headers with #ifdef macro
* include net/dsa.h and linux/mdio.h in mxl862xx.h
* call mxl862xx_port_fast_age() only once in .port_setup
* don't create isolation bridges for unused ports
* replace errornous cast with correct range of values denoting firmware errors
Changes since v7
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* use little-endian in bridge_port_config API
* remove duplciate assignment of br_port_cfg.bridge_port_id when setting
up CPU port
Changes since v6
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix kerneldoc style
Changes since RFC v5
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* remove unnecessary check for skb != NULL
* merge consecutively printed warnings into single dev_warn_ratelimited
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* include bridge and bridgeport API needed to isolate ports
* remove warning in .setup as ports are now isolated
* make ready-after-reset check more robust by adding delay
* sort structs in order of struct definitions
* best effort to sort functions without introducing additional prototypes
* always use enums with kerneldoc comments in mxl862xx-api.h
* remove bogus .phy_read and .phy_write DSA ops as the driver anyway registers
a user MDIO bus with Clause-22 and Clause-45 operations
* various small style fixes
Changes since RFC v4
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* drop unused precompiler macros
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* fix indentation
4/4 net: dsa: add basic initial driver for MxL862xx switches
* output warning in .setup regarding unknown pre-configuration
* add comment explaining why CFGGET is used in reset function
Changes since RFC v3
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* remove labels from example
* remove 'bindings for' from commit title
2/4 net: dsa: add tag format for MxL862xx switches
* describe fields and variables with comments
* sub-interface is only 5 bits
* harmonize Kconfig symbol name
* maintain alphabetic order in Kconfig
* fix typo s/beginnig/beginning/
* fix typo s/swtiches/switches/
* arrange local variables in reverse xmas tree order
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* poll switch readiness after reset
* implement driver shutdown
* added port_fast_aging API call and driver op
* unified port setup in new .port_setup op
* improve comment explaining special handlign for unaligned API read
* various typos and formatting improvements
Changes since RFC v2
1/4, 2/4, 3/4: unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix return value being uninitialized on error in mxl862xx_api_wrap()
* add missing description in kerneldoc comment of
struct mxl862xx_ss_sp_tag
Changes since initial RFC
1/4 dt-bindings: net: dsa: add bindings for MaxLinear MxL862xx
* better description in dt-bindings doc
2/4 net: dsa: add tag formats for MxL862xx switches
* make sure all tag fields are initialized
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* new patch
4/4 net: dsa: add basic initial driver for MxL862xx switches
* make use of struct mdio_device
* add phylink_mac_ops stubs
* drop leftover nonsense from mxl862xx_phylink_get_caps()
* fix endian conversions
* use __le32 instead of enum types in over-the-wire structs
* use existing MDIO_* macros whenever possible
* simplify API constants to be more readable
* use readx_poll_timeout instead of open-coding poll timeout loop
* add mxl862xx_reg_read() and mxl862xx_reg_write() helpers
* demystify error codes returned by the firmware
* add #defines for mxl862xx_ss_sp_tag member values
* move reset to dedicated function, clarify magic number being the
reset command ID
Daniel Golle (4):
dt-bindings: net: dsa: add MaxLinear MxL862xx
net: dsa: add tag format for MxL862xx switches
net: mdio: add unlocked mdiodev C45 bus accessors
net: dsa: add basic initial driver for MxL862xx switches
.../bindings/net/dsa/maxlinear,mxl862xx.yaml | 160 +++++
MAINTAINERS | 8 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/mxl862xx/Kconfig | 12 +
drivers/net/dsa/mxl862xx/Makefile | 3 +
drivers/net/dsa/mxl862xx/mxl862xx-api.h | 675 ++++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 49 ++
drivers/net/dsa/mxl862xx/mxl862xx-host.c | 245 +++++++
drivers/net/dsa/mxl862xx/mxl862xx-host.h | 12 +
drivers/net/dsa/mxl862xx/mxl862xx.c | 483 +++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx.h | 16 +
include/linux/mdio.h | 13 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 7 +
net/dsa/Makefile | 1 +
net/dsa/tag_mxl862xx.c | 110 +++
17 files changed, 1799 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
create mode 100644 drivers/net/dsa/mxl862xx/Kconfig
create mode 100644 drivers/net/dsa/mxl862xx/Makefile
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-api.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.h
create mode 100644 net/dsa/tag_mxl862xx.c
--
2.52.0
| Add proprietary special tag format for the MaxLinear MXL862xx family of
switches. While using the same Ethertype as MaxLinear's GSW1xx switches,
the actual tag format differs significantly, hence we need a dedicated
tag driver for that.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v12: no changes
v11:
* arrange local variables in reverse xmas tree order (again)
* use MXL862_NAME as .name in struct dsa_device_ops
v10: count ports starting from 0
v9: no changes
v8: no changes
v7: no changes
v6:
* remove unnecessary check for skb != NULL
* merge consecutively printed warnings into single dev_warn_ratelimited
v5:
* remove unused macro definitions
RFC v4:
* describe fields and variables with comments
* sub-interface is only 5 bits
* harmonize Kconfig symbol name
* maintain alphabetic order in Kconfig
* fix typo s/beginnig/beginning/
* fix typo s/swtiches/switches/
* arrange local variables in reverse xmas tree order
RFC v3: no changes
RFC v2: make sure all tag fields are initialized
---
MAINTAINERS | 1 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 7 +++
net/dsa/Makefile | 1 +
net/dsa/tag_mxl862xx.c | 110 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 121 insertions(+)
create mode 100644 net/dsa/tag_mxl862xx.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1abcdbc54a3f..e64f423b3844 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15624,6 +15624,7 @@ M: Daniel Golle <daniel@makrotopia.org>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
+F: net/dsa/tag_mxl862xx.c
MCAN DEVICE DRIVER
M: Markus Schneider-Pargmann <msp@baylibre.com>
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 6b2b5ed64ea4..1e33242b6d94 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -57,6 +57,7 @@ struct tc_action;
#define DSA_TAG_PROTO_BRCM_LEGACY_FCS_VALUE 29
#define DSA_TAG_PROTO_YT921X_VALUE 30
#define DSA_TAG_PROTO_MXL_GSW1XX_VALUE 31
+#define DSA_TAG_PROTO_MXL862_VALUE 32
enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -91,6 +92,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_VSC73XX_8021Q = DSA_TAG_PROTO_VSC73XX_8021Q_VALUE,
DSA_TAG_PROTO_YT921X = DSA_TAG_PROTO_YT921X_VALUE,
DSA_TAG_PROTO_MXL_GSW1XX = DSA_TAG_PROTO_MXL_GSW1XX_VALUE,
+ DSA_TAG_PROTO_MXL862 = DSA_TAG_PROTO_MXL862_VALUE,
};
struct dsa_switch;
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index f86b30742122..efc95759a10e 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -104,6 +104,13 @@ config NET_DSA_TAG_MTK
Say Y or M if you want to enable support for tagging frames for
Mediatek switches.
+config NET_DSA_TAG_MXL_862XX
+ tristate "Tag driver for MxL862xx switches"
+ help
+ Say Y or M if you want to enable support for tagging frames for the
+ Maxlinear MxL86252 and MxL86282 switches using their native 8-byte
+ tagging protocol.
+
config NET_DSA_TAG_MXL_GSW1XX
tristate "Tag driver for MaxLinear GSW1xx switches"
help
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
index 42d173f5a701..bf7247759a64 100644
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_NET_DSA_TAG_HELLCREEK) += tag_hellcreek.o
obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
+obj-$(CONFIG_NET_DSA_TAG_MXL_862XX) += tag_mxl862xx.o
obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o
obj-$(CONFIG_NET_DSA_TAG_NONE) += tag_none.o
obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
diff --git a/net/dsa/tag_mxl862xx.c b/net/dsa/tag_mxl862xx.c
new file mode 100644
index 000000000000..a0ec878e698e
--- /dev/null
+++ b/net/dsa/tag_mxl862xx.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * DSA Special Tag for MaxLinear 862xx switch chips
+ *
+ * Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
+ * Copyright (C) 2024 MaxLinear Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <net/dsa.h>
+#include "tag.h"
+
+#define MXL862_NAME "mxl862xx"
+
+#define MXL862_HEADER_LEN 8
+
+/* Word 0 -> EtherType */
+
+/* Word 2 */
+#define MXL862_SUBIF_ID GENMASK(4, 0)
+
+/* Word 3 */
+#define MXL862_IGP_EGP GENMASK(3, 0)
+
+static struct sk_buff *mxl862_tag_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct dsa_port *dp = dsa_user_to_port(dev);
+ struct dsa_port *cpu_dp = dp->cpu_dp;
+ unsigned int cpu_port, sub_interface;
+ __be16 *mxl862_tag;
+
+ cpu_port = cpu_dp->index;
+
+ /* target port sub-interface ID relative to the CPU port */
+ sub_interface = dp->index + 16 - cpu_port;
+
+ /* provide additional space 'MXL862_HEADER_LEN' bytes */
+ skb_push(skb, MXL862_HEADER_LEN);
+
+ /* shift MAC address to the beginning of the enlarged buffer,
+ * releasing the space required for DSA tag (between MAC address and
+ * Ethertype)
+ */
+ dsa_alloc_etype_header(skb, MXL862_HEADER_LEN);
+
+ /* special tag ingress */
+ mxl862_tag = dsa_etype_header_pos_tx(skb);
+ mxl862_tag[0] = htons(ETH_P_MXLGSW);
+ mxl862_tag[1] = 0;
+ mxl862_tag[2] = htons(FIELD_PREP(MXL862_SUBIF_ID, sub_interface));
+ mxl862_tag[3] = htons(FIELD_PREP(MXL862_IGP_EGP, cpu_port));
+
+ return skb;
+}
+
+static struct sk_buff *mxl862_tag_rcv(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ __be16 *mxl862_tag;
+ int port;
+
+ if (unlikely(!pskb_may_pull(skb, MXL862_HEADER_LEN))) {
+ dev_warn_ratelimited(&dev->dev, "Cannot pull SKB, packet dropped\n");
+ return NULL;
+ }
+
+ mxl862_tag = dsa_etype_header_pos_rx(skb);
+
+ if (unlikely(mxl862_tag[0] != htons(ETH_P_MXLGSW))) {
+ dev_warn_ratelimited(&dev->dev,
+ "Invalid special tag marker, packet dropped, tag: %8ph\n",
+ mxl862_tag);
+ return NULL;
+ }
+
+ /* Get source port information */
+ port = FIELD_GET(MXL862_IGP_EGP, ntohs(mxl862_tag[3]));
+ skb->dev = dsa_conduit_find_user(dev, 0, port);
+ if (unlikely(!skb->dev)) {
+ dev_warn_ratelimited(&dev->dev,
+ "Invalid source port, packet dropped, tag: %8ph\n",
+ mxl862_tag);
+ return NULL;
+ }
+
+ /* remove the MxL862xx special tag between the MAC addresses and the
+ * current ethertype field.
+ */
+ skb_pull_rcsum(skb, MXL862_HEADER_LEN);
+ dsa_strip_etype_header(skb, MXL862_HEADER_LEN);
+
+ return skb;
+}
+
+static const struct dsa_device_ops mxl862_netdev_ops = {
+ .name = MXL862_NAME,
+ .proto = DSA_TAG_PROTO_MXL862,
+ .xmit = mxl862_tag_xmit,
+ .rcv = mxl862_tag_rcv,
+ .needed_headroom = MXL862_HEADER_LEN,
+};
+
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MXL862, MXL862_NAME);
+MODULE_DESCRIPTION("DSA tag driver for MaxLinear MxL862xx switches");
+MODULE_LICENSE("GPL");
+
+module_dsa_tag_driver(mxl862_netdev_ops);
--
2.52.0 | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Sun, 1 Feb 2026 02:24:56 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch with this DSA driver.
MxL862xx integrates a firmware running on an embedded processor (based on
Zephyr RTOS). Host interaction uses a simple netlink-like API transported
over MDIO/MMD.
This series includes only what's needed to pass traffic between user
ports and the CPU port: relayed MDIO to internal PHYs, basic port
enable/disable, and CPU-port special tagging.
The SerDes interface of the CPU port is automatically configured by the
switch after reset using a board-specific configuration stored together
with the firmware in the flash chip attached to the switch, so no action
is needed from the driver to setup the interface mode of the CPU port.
Also MAC settings of the PHY ports are automatically configured, which
means the driver works fine with phylink_mac_ops being all no-op stubs.
Multiple follow up series will bring support for setting up the other
SerDes PCS interface (ie. not used for the CPU port), bridge, VLAN, ...
offloading, and support for using an 802.1Q-based special tag instead of
the proprietary 8-byte tag.
---
basic DSA selftests were run, results:
* no_forwarding.sh: all tests PASS
* bridge_vlan_unaware.sh: all tests PASS
* bridge_vlan_mcast.sh: all tests PASS
* bridge_vlan_aware.sh: all tests PASS
* local_termination.sh: all tests PASS or XFAIL, except for
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
As obviously this is mostly testing the Linux software bridge at this
point so I didn't bother to run any of the FDB or MDB related tests.
Some mystery about the relationship between the sub-interface ID and CTP
port assignment remains for now, so I cannot yet fully explain the magic
numbers when calculating the two.
(Why is it neccesary to allocate 23 CTPs when using port 9 as CPU port
while there are at most 17 phyiscal interfaces in total, and only at
most 13 when using one of the two SerDes as CPU interface? Why is there
an offset of 16 when calculating the sub-interface ID? How will a total
of 17 ports be possibly represented in a 4-bit field in the tag RX
path?)
At this point this doesn't impact functionality, and I hope for further
clarification discussing all that with MaxLinear engineers.
I believe the initial driver is anyway in good shape now, a follow-up
series addressing configuring the SerDes interfaces will also have to
take care of CTP assignment and sub-interfaces to not hit the mentioned
4-bit cap in the tag driver.
Changes since v11:
Address comments reported by Jakub Kicinski using netdev-ai
https://patchwork.kernel.org/comment/26767905/
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* list switch variants in Kconfig starting with dash ('-')
* remove the __packed attribute on structs which are
naturally packed according to C rules (ie. one other struct
with only a single byte-aligned member)
* log error in mxl862xx_port_disable()
* introduce !NULL check for return value of dsa_to_port() in
mxl862xx_add_single_port_bridge
* check cpu_dp being non-NULL before dereferencing dp->cpu_dp
* use non-racy and deterministic name for MII bus
* skip ports without cpu_dp assigned in mxl862xx_setup_cpu_bridge()
to avoid potential NULL-pointer dereference
* call dev_set_drvdata() only after dsa_register_switch() has been
successfully completed
Changes since v10:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* arrange local variables in reverse xmas tree order (again)
* use MXL862_NAME as .name in struct dsa_device_ops
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix fatal last-second changes dsa_port_is_unused vs. dsa_is_unused_port
and dsa_port_is_unused vs. dsa_is_unused_port
* use cpu_to_le16 in mxl862xx_configure_ctp_port
* improve formatting of some kerneldoc comments
Changes since v9:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* add microcontroller port 0
2/4 net: dsa: add tag format for MxL862xx switches
* count ports starting from 0
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix indentation in kernel-doc
* remove misleading comment regarding sub-interface IDs
* remove unused macros, set MXL862XX_MAX_PORTS to 17
* count ports starting from 0, 0 being the microcontroller
* improve port setup:
- split tag protocol and CTP port assignment
- use ports cpu_dp instead of relying on single (ie. first) CPU port
- handle CPU port like any other port
- prepare forward DT compatibility with multiple CPU ports
Changes since v8:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* remove practically unused struct hw_info
* lots of kerneldoc improvements in mxl862xx-api.h
* drop .mac_select_pcs() stub
* better handling for firmware error return value
* apply reverse xmas tree in mxl862xx_api_wrap
* guard headers with #ifdef macro
* include net/dsa.h and linux/mdio.h in mxl862xx.h
* call mxl862xx_port_fast_age() only once in .port_setup
* don't create isolation bridges for unused ports
* replace errornous cast with correct range of values denoting firmware errors
Changes since v7
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* use little-endian in bridge_port_config API
* remove duplciate assignment of br_port_cfg.bridge_port_id when setting
up CPU port
Changes since v6
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix kerneldoc style
Changes since RFC v5
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* remove unnecessary check for skb != NULL
* merge consecutively printed warnings into single dev_warn_ratelimited
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* include bridge and bridgeport API needed to isolate ports
* remove warning in .setup as ports are now isolated
* make ready-after-reset check more robust by adding delay
* sort structs in order of struct definitions
* best effort to sort functions without introducing additional prototypes
* always use enums with kerneldoc comments in mxl862xx-api.h
* remove bogus .phy_read and .phy_write DSA ops as the driver anyway registers
a user MDIO bus with Clause-22 and Clause-45 operations
* various small style fixes
Changes since RFC v4
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* drop unused precompiler macros
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* fix indentation
4/4 net: dsa: add basic initial driver for MxL862xx switches
* output warning in .setup regarding unknown pre-configuration
* add comment explaining why CFGGET is used in reset function
Changes since RFC v3
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* remove labels from example
* remove 'bindings for' from commit title
2/4 net: dsa: add tag format for MxL862xx switches
* describe fields and variables with comments
* sub-interface is only 5 bits
* harmonize Kconfig symbol name
* maintain alphabetic order in Kconfig
* fix typo s/beginnig/beginning/
* fix typo s/swtiches/switches/
* arrange local variables in reverse xmas tree order
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* poll switch readiness after reset
* implement driver shutdown
* added port_fast_aging API call and driver op
* unified port setup in new .port_setup op
* improve comment explaining special handlign for unaligned API read
* various typos and formatting improvements
Changes since RFC v2
1/4, 2/4, 3/4: unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix return value being uninitialized on error in mxl862xx_api_wrap()
* add missing description in kerneldoc comment of
struct mxl862xx_ss_sp_tag
Changes since initial RFC
1/4 dt-bindings: net: dsa: add bindings for MaxLinear MxL862xx
* better description in dt-bindings doc
2/4 net: dsa: add tag formats for MxL862xx switches
* make sure all tag fields are initialized
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* new patch
4/4 net: dsa: add basic initial driver for MxL862xx switches
* make use of struct mdio_device
* add phylink_mac_ops stubs
* drop leftover nonsense from mxl862xx_phylink_get_caps()
* fix endian conversions
* use __le32 instead of enum types in over-the-wire structs
* use existing MDIO_* macros whenever possible
* simplify API constants to be more readable
* use readx_poll_timeout instead of open-coding poll timeout loop
* add mxl862xx_reg_read() and mxl862xx_reg_write() helpers
* demystify error codes returned by the firmware
* add #defines for mxl862xx_ss_sp_tag member values
* move reset to dedicated function, clarify magic number being the
reset command ID
Daniel Golle (4):
dt-bindings: net: dsa: add MaxLinear MxL862xx
net: dsa: add tag format for MxL862xx switches
net: mdio: add unlocked mdiodev C45 bus accessors
net: dsa: add basic initial driver for MxL862xx switches
.../bindings/net/dsa/maxlinear,mxl862xx.yaml | 160 +++++
MAINTAINERS | 8 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/mxl862xx/Kconfig | 12 +
drivers/net/dsa/mxl862xx/Makefile | 3 +
drivers/net/dsa/mxl862xx/mxl862xx-api.h | 675 ++++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 49 ++
drivers/net/dsa/mxl862xx/mxl862xx-host.c | 245 +++++++
drivers/net/dsa/mxl862xx/mxl862xx-host.h | 12 +
drivers/net/dsa/mxl862xx/mxl862xx.c | 483 +++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx.h | 16 +
include/linux/mdio.h | 13 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 7 +
net/dsa/Makefile | 1 +
net/dsa/tag_mxl862xx.c | 110 +++
17 files changed, 1799 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
create mode 100644 drivers/net/dsa/mxl862xx/Kconfig
create mode 100644 drivers/net/dsa/mxl862xx/Makefile
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-api.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.h
create mode 100644 net/dsa/tag_mxl862xx.c
--
2.52.0
| Add helper inline functions __mdiodev_c45_read() and
__mdiodev_c45_write(), which are the C45 equivalents of the existing
__mdiodev_read() and __mdiodev_write() added by commit e6a45700e7e1
("net: mdio: add unlocked mdiobus and mdiodev bus accessors")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v12: no changes
v11: no changes
v10: no changes
v9: no changes
v8: no changes
v7: no changes
v6: no changes
v5: fix indentation
RFC v4: no changes
RFC v3: no changes
RFC v2: add this patch, initial submission
---
include/linux/mdio.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index 42d6d47e445b..52d94b8ae371 100644
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -648,6 +648,19 @@ static inline int mdiodev_modify_changed(struct mdio_device *mdiodev,
mask, set);
}
+static inline int __mdiodev_c45_read(struct mdio_device *mdiodev, int devad,
+ u16 regnum)
+{
+ return __mdiobus_c45_read(mdiodev->bus, mdiodev->addr, devad, regnum);
+}
+
+static inline int __mdiodev_c45_write(struct mdio_device *mdiodev, u32 devad,
+ u16 regnum, u16 val)
+{
+ return __mdiobus_c45_write(mdiodev->bus, mdiodev->addr, devad, regnum,
+ val);
+}
+
static inline int mdiodev_c45_modify(struct mdio_device *mdiodev, int devad,
u32 regnum, u16 mask, u16 set)
{
--
2.52.0 | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Sun, 1 Feb 2026 02:25:03 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch with this DSA driver.
MxL862xx integrates a firmware running on an embedded processor (based on
Zephyr RTOS). Host interaction uses a simple netlink-like API transported
over MDIO/MMD.
This series includes only what's needed to pass traffic between user
ports and the CPU port: relayed MDIO to internal PHYs, basic port
enable/disable, and CPU-port special tagging.
The SerDes interface of the CPU port is automatically configured by the
switch after reset using a board-specific configuration stored together
with the firmware in the flash chip attached to the switch, so no action
is needed from the driver to setup the interface mode of the CPU port.
Also MAC settings of the PHY ports are automatically configured, which
means the driver works fine with phylink_mac_ops being all no-op stubs.
Multiple follow up series will bring support for setting up the other
SerDes PCS interface (ie. not used for the CPU port), bridge, VLAN, ...
offloading, and support for using an 802.1Q-based special tag instead of
the proprietary 8-byte tag.
---
basic DSA selftests were run, results:
* no_forwarding.sh: all tests PASS
* bridge_vlan_unaware.sh: all tests PASS
* bridge_vlan_mcast.sh: all tests PASS
* bridge_vlan_aware.sh: all tests PASS
* local_termination.sh: all tests PASS or XFAIL, except for
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
As obviously this is mostly testing the Linux software bridge at this
point so I didn't bother to run any of the FDB or MDB related tests.
Some mystery about the relationship between the sub-interface ID and CTP
port assignment remains for now, so I cannot yet fully explain the magic
numbers when calculating the two.
(Why is it neccesary to allocate 23 CTPs when using port 9 as CPU port
while there are at most 17 phyiscal interfaces in total, and only at
most 13 when using one of the two SerDes as CPU interface? Why is there
an offset of 16 when calculating the sub-interface ID? How will a total
of 17 ports be possibly represented in a 4-bit field in the tag RX
path?)
At this point this doesn't impact functionality, and I hope for further
clarification discussing all that with MaxLinear engineers.
I believe the initial driver is anyway in good shape now, a follow-up
series addressing configuring the SerDes interfaces will also have to
take care of CTP assignment and sub-interfaces to not hit the mentioned
4-bit cap in the tag driver.
Changes since v11:
Address comments reported by Jakub Kicinski using netdev-ai
https://patchwork.kernel.org/comment/26767905/
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* list switch variants in Kconfig starting with dash ('-')
* remove the __packed attribute on structs which are
naturally packed according to C rules (ie. one other struct
with only a single byte-aligned member)
* log error in mxl862xx_port_disable()
* introduce !NULL check for return value of dsa_to_port() in
mxl862xx_add_single_port_bridge
* check cpu_dp being non-NULL before dereferencing dp->cpu_dp
* use non-racy and deterministic name for MII bus
* skip ports without cpu_dp assigned in mxl862xx_setup_cpu_bridge()
to avoid potential NULL-pointer dereference
* call dev_set_drvdata() only after dsa_register_switch() has been
successfully completed
Changes since v10:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* arrange local variables in reverse xmas tree order (again)
* use MXL862_NAME as .name in struct dsa_device_ops
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix fatal last-second changes dsa_port_is_unused vs. dsa_is_unused_port
and dsa_port_is_unused vs. dsa_is_unused_port
* use cpu_to_le16 in mxl862xx_configure_ctp_port
* improve formatting of some kerneldoc comments
Changes since v9:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* add microcontroller port 0
2/4 net: dsa: add tag format for MxL862xx switches
* count ports starting from 0
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix indentation in kernel-doc
* remove misleading comment regarding sub-interface IDs
* remove unused macros, set MXL862XX_MAX_PORTS to 17
* count ports starting from 0, 0 being the microcontroller
* improve port setup:
- split tag protocol and CTP port assignment
- use ports cpu_dp instead of relying on single (ie. first) CPU port
- handle CPU port like any other port
- prepare forward DT compatibility with multiple CPU ports
Changes since v8:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* remove practically unused struct hw_info
* lots of kerneldoc improvements in mxl862xx-api.h
* drop .mac_select_pcs() stub
* better handling for firmware error return value
* apply reverse xmas tree in mxl862xx_api_wrap
* guard headers with #ifdef macro
* include net/dsa.h and linux/mdio.h in mxl862xx.h
* call mxl862xx_port_fast_age() only once in .port_setup
* don't create isolation bridges for unused ports
* replace errornous cast with correct range of values denoting firmware errors
Changes since v7
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* use little-endian in bridge_port_config API
* remove duplciate assignment of br_port_cfg.bridge_port_id when setting
up CPU port
Changes since v6
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix kerneldoc style
Changes since RFC v5
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* remove unnecessary check for skb != NULL
* merge consecutively printed warnings into single dev_warn_ratelimited
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* include bridge and bridgeport API needed to isolate ports
* remove warning in .setup as ports are now isolated
* make ready-after-reset check more robust by adding delay
* sort structs in order of struct definitions
* best effort to sort functions without introducing additional prototypes
* always use enums with kerneldoc comments in mxl862xx-api.h
* remove bogus .phy_read and .phy_write DSA ops as the driver anyway registers
a user MDIO bus with Clause-22 and Clause-45 operations
* various small style fixes
Changes since RFC v4
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* drop unused precompiler macros
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* fix indentation
4/4 net: dsa: add basic initial driver for MxL862xx switches
* output warning in .setup regarding unknown pre-configuration
* add comment explaining why CFGGET is used in reset function
Changes since RFC v3
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* remove labels from example
* remove 'bindings for' from commit title
2/4 net: dsa: add tag format for MxL862xx switches
* describe fields and variables with comments
* sub-interface is only 5 bits
* harmonize Kconfig symbol name
* maintain alphabetic order in Kconfig
* fix typo s/beginnig/beginning/
* fix typo s/swtiches/switches/
* arrange local variables in reverse xmas tree order
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* poll switch readiness after reset
* implement driver shutdown
* added port_fast_aging API call and driver op
* unified port setup in new .port_setup op
* improve comment explaining special handlign for unaligned API read
* various typos and formatting improvements
Changes since RFC v2
1/4, 2/4, 3/4: unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix return value being uninitialized on error in mxl862xx_api_wrap()
* add missing description in kerneldoc comment of
struct mxl862xx_ss_sp_tag
Changes since initial RFC
1/4 dt-bindings: net: dsa: add bindings for MaxLinear MxL862xx
* better description in dt-bindings doc
2/4 net: dsa: add tag formats for MxL862xx switches
* make sure all tag fields are initialized
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* new patch
4/4 net: dsa: add basic initial driver for MxL862xx switches
* make use of struct mdio_device
* add phylink_mac_ops stubs
* drop leftover nonsense from mxl862xx_phylink_get_caps()
* fix endian conversions
* use __le32 instead of enum types in over-the-wire structs
* use existing MDIO_* macros whenever possible
* simplify API constants to be more readable
* use readx_poll_timeout instead of open-coding poll timeout loop
* add mxl862xx_reg_read() and mxl862xx_reg_write() helpers
* demystify error codes returned by the firmware
* add #defines for mxl862xx_ss_sp_tag member values
* move reset to dedicated function, clarify magic number being the
reset command ID
Daniel Golle (4):
dt-bindings: net: dsa: add MaxLinear MxL862xx
net: dsa: add tag format for MxL862xx switches
net: mdio: add unlocked mdiodev C45 bus accessors
net: dsa: add basic initial driver for MxL862xx switches
.../bindings/net/dsa/maxlinear,mxl862xx.yaml | 160 +++++
MAINTAINERS | 8 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/mxl862xx/Kconfig | 12 +
drivers/net/dsa/mxl862xx/Makefile | 3 +
drivers/net/dsa/mxl862xx/mxl862xx-api.h | 675 ++++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 49 ++
drivers/net/dsa/mxl862xx/mxl862xx-host.c | 245 +++++++
drivers/net/dsa/mxl862xx/mxl862xx-host.h | 12 +
drivers/net/dsa/mxl862xx/mxl862xx.c | 483 +++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx.h | 16 +
include/linux/mdio.h | 13 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 7 +
net/dsa/Makefile | 1 +
net/dsa/tag_mxl862xx.c | 110 +++
17 files changed, 1799 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
create mode 100644 drivers/net/dsa/mxl862xx/Kconfig
create mode 100644 drivers/net/dsa/mxl862xx/Makefile
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-api.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.h
create mode 100644 net/dsa/tag_mxl862xx.c
--
2.52.0
| Add very basic DSA driver for MaxLinear's MxL862xx switches.
In contrast to previous MaxLinear switches the MxL862xx has a built-in
processor that runs a sophisticated firmware based on Zephyr RTOS.
Interaction between the host and the switch hence is organized using a
software API of that firmware rather than accessing hardware registers
directly.
Add descriptions of the most basic firmware API calls to access the
built-in MDIO bus hosting the 2.5GE PHYs, basic port control as well as
setting up the CPU port.
Implement a very basic DSA driver using that API which is sufficient to
get packets flowing between the user ports and the CPU port.
The firmware offers all features one would expect from a modern switch
hardware, they are going to be added one by one in follow-up patch
series.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v12:
* list switch variants in Kconfig starting with dash ('-')
* remove the __packed attribute on structs which are
naturally packed according to C rules (ie. one other struct
with only a single byte-aligned member)
* log error in mxl862xx_port_disable()
* introduce !NULL check for return value of dsa_to_port() in
mxl862xx_add_single_port_bridge
* check cpu_dp being non-NULL before dereferencing dp->cpu_dp
* use non-racy and deterministic name for MII bus
* skip ports without cpu_dp assigned in mxl862xx_setup_cpu_bridge()
to avoid potential NULL-pointer dereference
* call dev_set_drvdata() only after dsa_register_switch() has been
successfully completed
v11:
* fix fatal last-second changes dsa_port_is_unused vs. dsa_is_unused_port
and dsa_port_is_unused vs. dsa_is_unused_port
* use cpu_to_le16 in mxl862xx_configure_ctp_port
* improve formatting of some kerneldoc comments
v10:
* fix indentation in kernel-doc
* remove misleading comment regarding sub-interface IDs
* remove unused macros, set MXL862XX_MAX_PORTS to 17
* count ports starting from 0, 0 being the microcontroller
* improve port setup:
- split tag protocol and CTP port assignment
- use ports cpu_dp instead of relying on single (ie. first) CPU port
- handle CPU port like any other port
- prepare forward DT compatibility with multiple CPU ports
v9:
* remove practically unused struct hw_info
* lots of kerneldoc improvements in mxl862xx-api.h
* drop .mac_select_pcs() stub
* better handling for firmware error return value
* apply reverse xmas tree in mxl862xx_api_wrap
* guard headers with #ifdef macro
* include net/dsa.h and linux/mdio.h in mxl862xx.h
* call mxl862xx_port_fast_age() only once in .port_setup
* don't create isolation bridges for unused ports
* replace errornous cast with correct range of values denoting firmware errors
v8:
* use le32 endian in bridge_port_config API
* remove duplciate assignment of br_port_cfg.bridge_port_id when setting
up CPU port
v7:
* fix kerneldoc style
v6:
* include bridge and bridgeport API needed to isolate ports
* remove warning in .setup as ports are now isolated
* make ready-after-reset check more robust by adding delay
* sort structs in order of struct definitions
* best effort to sort functions without introducing additional prototypes
* always use enums with kerneldoc comments in mxl862xx-api.h
* remove bogus .phy_read and .phy_write DSA ops as the driver anyway registers
a user MDIO bus with Clause-22 and Clause-45 operations
* various small style fixes
v5:
* output warning in .setup regarding unknown pre-configuration
* add comment explaining why CFGGET is used in reset function
RFC v4:
* poll switch readiness after reset
* implement driver shutdown
* added port_fast_aging API call and driver op
* unified port setup in new .port_setup op
* improve comment explaining special handlign for unaligned API read
* various typos
RFC v3:
* fix return value being uninitialized on error in mxl862xx_api_wrap()
* add missing descrition in kerneldoc comment of
struct mxl862xx_ss_sp_tag
RFC v2:
* make use of struct mdio_device
* add phylink_mac_ops stubs
* drop leftover nonsense from mxl862xx_phylink_get_caps()
* use __le32 instead of enum types in over-the-wire structs
* use existing MDIO_* macros whenever possible
* simplify API constants to be more readable
* use readx_poll_timeout instead of open-coding poll timeout loop
* add mxl862xx_reg_read() and mxl862xx_reg_write() helpers
* demystify error codes returned by the firmware
* add #defines for mxl862xx_ss_sp_tag member values
* move reset to dedicated function, clarify magic number being the
reset command ID
---
MAINTAINERS | 1 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/mxl862xx/Kconfig | 12 +
drivers/net/dsa/mxl862xx/Makefile | 3 +
drivers/net/dsa/mxl862xx/mxl862xx-api.h | 675 +++++++++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 49 ++
drivers/net/dsa/mxl862xx/mxl862xx-host.c | 245 ++++++++
drivers/net/dsa/mxl862xx/mxl862xx-host.h | 12 +
drivers/net/dsa/mxl862xx/mxl862xx.c | 483 ++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx.h | 16 +
11 files changed, 1499 insertions(+)
create mode 100644 drivers/net/dsa/mxl862xx/Kconfig
create mode 100644 drivers/net/dsa/mxl862xx/Makefile
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-api.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index e64f423b3844..28449b299f1f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15624,6 +15624,7 @@ M: Daniel Golle <daniel@makrotopia.org>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
+F: drivers/net/dsa/mxl862xx/
F: net/dsa/tag_mxl862xx.c
MCAN DEVICE DRIVER
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 7eb301fd987d..18f6e8b7f4cb 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -74,6 +74,8 @@ source "drivers/net/dsa/microchip/Kconfig"
source "drivers/net/dsa/mv88e6xxx/Kconfig"
+source "drivers/net/dsa/mxl862xx/Kconfig"
+
source "drivers/net/dsa/ocelot/Kconfig"
source "drivers/net/dsa/qca/Kconfig"
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index 16de4ba3fa38..f5a463b87ec2 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -20,6 +20,7 @@ obj-y += hirschmann/
obj-y += lantiq/
obj-y += microchip/
obj-y += mv88e6xxx/
+obj-y += mxl862xx/
obj-y += ocelot/
obj-y += qca/
obj-y += realtek/
diff --git a/drivers/net/dsa/mxl862xx/Kconfig b/drivers/net/dsa/mxl862xx/Kconfig
new file mode 100644
index 000000000000..4db7bab21a71
--- /dev/null
+++ b/drivers/net/dsa/mxl862xx/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_MXL862
+ tristate "MaxLinear MxL862xx"
+ depends on NET_DSA
+ select MAXLINEAR_GPHY
+ select NET_DSA_TAG_MXL_862XX
+ help
+ This enables support for the MaxLinear MxL862xx switch family.
+ These switches have two 10GE SerDes interfaces, one typically
+ used as CPU port.
+ - MxL86282 has eight 2.5 Gigabit PHYs
+ - MxL86252 has five 2.5 Gigabit PHYs
diff --git a/drivers/net/dsa/mxl862xx/Makefile b/drivers/net/dsa/mxl862xx/Makefile
new file mode 100644
index 000000000000..d23dd3cd511d
--- /dev/null
+++ b/drivers/net/dsa/mxl862xx/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_NET_DSA_MXL862) += mxl862xx_dsa.o
+mxl862xx_dsa-y := mxl862xx.o mxl862xx-host.o
diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-api.h b/drivers/net/dsa/mxl862xx/mxl862xx-api.h
new file mode 100644
index 000000000000..a9f599dbca25
--- /dev/null
+++ b/drivers/net/dsa/mxl862xx/mxl862xx-api.h
@@ -0,0 +1,675 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MXL862XX_API_H
+#define __MXL862XX_API_H
+
+#include <linux/if_ether.h>
+
+/**
+ * struct mdio_relay_data - relayed access to the switch internal MDIO bus
+ * @data: data to be read or written
+ * @phy: PHY index
+ * @mmd: MMD device
+ * @reg: register index
+ */
+struct mdio_relay_data {
+ __le16 data;
+ u8 phy;
+ u8 mmd;
+ __le16 reg;
+} __packed;
+
+/**
+ * struct mxl862xx_register_mod - Register access parameter to directly
+ * modify internal registers
+ * @addr: Register address offset for modification
+ * @data: Value to write to the register address
+ * @mask: Mask of bits to be modified (1 to modify, 0 to ignore)
+ *
+ * Used for direct register modification operations.
+ */
+struct mxl862xx_register_mod {
+ __le16 addr;
+ __le16 data;
+ __le16 mask;
+} __packed;
+
+/**
+ * enum mxl862xx_mac_clear_type - MAC table clear type
+ * @MXL862XX_MAC_CLEAR_PHY_PORT: clear dynamic entries based on port_id
+ * @MXL862XX_MAC_CLEAR_DYNAMIC: clear all dynamic entries
+ */
+enum mxl862xx_mac_clear_type {
+ MXL862XX_MAC_CLEAR_PHY_PORT = 0,
+ MXL862XX_MAC_CLEAR_DYNAMIC,
+};
+
+/**
+ * struct mxl862xx_mac_table_clear - MAC table clear
+ * @type: see &enum mxl862xx_mac_clear_type
+ * @port_id: physical port id
+ */
+struct mxl862xx_mac_table_clear {
+ u8 type;
+ u8 port_id;
+} __packed;
+
+/**
+ * enum mxl862xx_age_timer - Aging Timer Value.
+ * @MXL862XX_AGETIMER_1_SEC: 1 second aging time
+ * @MXL862XX_AGETIMER_10_SEC: 10 seconds aging time
+ * @MXL862XX_AGETIMER_300_SEC: 300 seconds aging time
+ * @MXL862XX_AGETIMER_1_HOUR: 1 hour aging time
+ * @MXL862XX_AGETIMER_1_DAY: 24 hours aging time
+ * @MXL862XX_AGETIMER_CUSTOM: Custom aging time in seconds
+ */
+enum mxl862xx_age_timer {
+ MXL862XX_AGETIMER_1_SEC = 1,
+ MXL862XX_AGETIMER_10_SEC,
+ MXL862XX_AGETIMER_300_SEC,
+ MXL862XX_AGETIMER_1_HOUR,
+ MXL862XX_AGETIMER_1_DAY,
+ MXL862XX_AGETIMER_CUSTOM,
+};
+
+/**
+ * struct mxl862xx_bridge_alloc - Bridge Allocation
+ * @bridge_id: If the bridge allocation is successful, a valid ID will be
+ * returned in this field. Otherwise, INVALID_HANDLE is
+ * returned. For bridge free, this field should contain a
+ * valid ID returned by the bridge allocation. ID 0 is not
+ * used for historic reasons.
+ *
+ * Used by MXL862XX_BRIDGE_ALLOC and MXL862XX_BRIDGE_FREE.
+ */
+struct mxl862xx_bridge_alloc {
+ __le16 bridge_id;
+};
+
+/**
+ * enum mxl862xx_bridge_config_mask - Bridge configuration mask
+ * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNING_LIMIT:
+ * Mask for mac_learning_limit_enable and mac_learning_limit.
+ * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNED_COUNT:
+ * Mask for mac_learning_count
+ * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_DISCARD_COUNT:
+ * Mask for learning_discard_event
+ * @MXL862XX_BRIDGE_CONFIG_MASK_SUB_METER:
+ * Mask for sub_metering_enable and traffic_sub_meter_id
+ * @MXL862XX_BRIDGE_CONFIG_MASK_FORWARDING_MODE:
+ * Mask for forward_broadcast, forward_unknown_multicast_ip,
+ * forward_unknown_multicast_non_ip and forward_unknown_unicast.
+ * @MXL862XX_BRIDGE_CONFIG_MASK_ALL: Enable all
+ * @MXL862XX_BRIDGE_CONFIG_MASK_FORCE: Bypass any check for debug purpose
+ */
+enum mxl862xx_bridge_config_mask {
+ MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNING_LIMIT = BIT(0),
+ MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNED_COUNT = BIT(1),
+ MXL862XX_BRIDGE_CONFIG_MASK_MAC_DISCARD_COUNT = BIT(2),
+ MXL862XX_BRIDGE_CONFIG_MASK_SUB_METER = BIT(3),
+ MXL862XX_BRIDGE_CONFIG_MASK_FORWARDING_MODE = BIT(4),
+ MXL862XX_BRIDGE_CONFIG_MASK_ALL = 0x7FFFFFFF,
+ MXL862XX_BRIDGE_CONFIG_MASK_FORCE = BIT(31)
+};
+
+/**
+ * enum mxl862xx_bridge_port_egress_meter - Meters for egress traffic type
+ * @MXL862XX_BRIDGE_PORT_EGRESS_METER_BROADCAST:
+ * Index of broadcast traffic meter
+ * @MXL862XX_BRIDGE_PORT_EGRESS_METER_MULTICAST:
+ * Index of known multicast traffic meter
+ * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_IP:
+ * Index of unknown multicast IP traffic meter
+ * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_NON_IP:
+ * Index of unknown multicast non-IP traffic meter
+ * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_UC:
+ * Index of unknown unicast traffic meter
+ * @MXL862XX_BRIDGE_PORT_EGRESS_METER_OTHERS:
+ * Index of traffic meter for other types
+ * @MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX: Number of index
+ */
+enum mxl862xx_bridge_port_egress_meter {
+ MXL862XX_BRIDGE_PORT_EGRESS_METER_BROADCAST = 0,
+ MXL862XX_BRIDGE_PORT_EGRESS_METER_MULTICAST,
+ MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_IP,
+ MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_NON_IP,
+ MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_UC,
+ MXL862XX_BRIDGE_PORT_EGRESS_METER_OTHERS,
+ MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX,
+};
+
+/**
+ * enum mxl862xx_bridge_forward_mode - Bridge forwarding type of packet
+ * @MXL862XX_BRIDGE_FORWARD_FLOOD: Packet is flooded to port members of
+ * ingress bridge port
+ * @MXL862XX_BRIDGE_FORWARD_DISCARD: Packet is discarded
+ */
+enum mxl862xx_bridge_forward_mode {
+ MXL862XX_BRIDGE_FORWARD_FLOOD = 0,
+ MXL862XX_BRIDGE_FORWARD_DISCARD,
+};
+
+/**
+ * struct mxl862xx_bridge_config - Bridge Configuration
+ * @bridge_id: Bridge ID (FID)
+ * @mask: See &enum mxl862xx_bridge_config_mask
+ * @mac_learning_limit_enable: Enable MAC learning limitation
+ * @mac_learning_limit: Max number of MAC addresses that can be learned in
+ * this bridge (all bridge ports)
+ * @mac_learning_count: Number of MAC addresses learned from this bridge
+ * @learning_discard_event: Number of learning discard events due to
+ * hardware resource not available
+ * @sub_metering_enable: Traffic metering on type of traffic (such as
+ * broadcast, multicast, unknown unicast, etc) applies
+ * @traffic_sub_meter_id: Meter for bridge process with specific type (such
+ * as broadcast, multicast, unknown unicast, etc)
+ * @forward_broadcast: Forwarding mode of broadcast traffic. See
+ * &enum mxl862xx_bridge_forward_mode
+ * @forward_unknown_multicast_ip: Forwarding mode of unknown multicast IP
+ * traffic.
+ * See &enum mxl862xx_bridge_forward_mode
+ * @forward_unknown_multicast_non_ip: Forwarding mode of unknown multicast
+ * non-IP traffic.
+ * See &enum mxl862xx_bridge_forward_mode
+ * @forward_unknown_unicast: Forwarding mode of unknown unicast traffic. See
+ * &enum mxl862xx_bridge_forward_mode
+ */
+struct mxl862xx_bridge_config {
+ __le16 bridge_id;
+ __le32 mask; /* enum mxl862xx_bridge_config_mask */
+ u8 mac_learning_limit_enable;
+ __le16 mac_learning_limit;
+ __le16 mac_learning_count;
+ __le32 learning_discard_event;
+ u8 sub_metering_enable[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX];
+ __le16 traffic_sub_meter_id[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX];
+ __le32 forward_broadcast; /* enum mxl862xx_bridge_forward_mode */
+ __le32 forward_unknown_multicast_ip; /* enum mxl862xx_bridge_forward_mode */
+ __le32 forward_unknown_multicast_non_ip; /* enum mxl862xx_bridge_forward_mode */
+ __le32 forward_unknown_unicast; /* enum mxl862xx_bridge_forward_mode */
+} __packed;
+
+/**
+ * struct mxl862xx_bridge_port_alloc - Bridge Port Allocation
+ * @bridge_port_id: If the bridge port allocation is successful, a valid ID
+ * will be returned in this field. Otherwise, INVALID_HANDLE
+ * is returned. For bridge port free, this field should
+ * contain a valid ID returned by the bridge port allocation.
+ *
+ * Used by MXL862XX_BRIDGE_PORT_ALLOC and MXL862XX_BRIDGE_PORT_FREE.
+ */
+struct mxl862xx_bridge_port_alloc {
+ __le16 bridge_port_id;
+};
+
+/**
+ * enum mxl862xx_bridge_port_config_mask - Bridge Port configuration mask
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_ID:
+ * Mask for bridge_id
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN:
+ * Mask for ingress_extended_vlan_enable,
+ * ingress_extended_vlan_block_id and ingress_extended_vlan_block_size
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN:
+ * Mask for egress_extended_vlan_enable, egress_extended_vlan_block_id
+ * and egress_extended_vlan_block_size
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_MARKING:
+ * Mask for ingress_marking_mode
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_REMARKING:
+ * Mask for egress_remarking_mode
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_METER:
+ * Mask for ingress_metering_enable and ingress_traffic_meter_id
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_SUB_METER:
+ * Mask for egress_sub_metering_enable and egress_traffic_sub_meter_id
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_CTP_MAPPING:
+ * Mask for dest_logical_port_id, pmapper_enable, dest_sub_if_id_group,
+ * pmapper_mapping_mode, pmapper_id_valid and pmapper
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_PORT_MAP:
+ * Mask for bridge_port_map
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_IP_LOOKUP:
+ * Mask for mc_dest_ip_lookup_disable
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_IP_LOOKUP:
+ * Mask for mc_src_ip_lookup_enable
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_MAC_LOOKUP:
+ * Mask for dest_mac_lookup_disable
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_MAC_LEARNING:
+ * Mask for src_mac_learning_disable
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_SPOOFING:
+ * Mask for mac_spoofing_detect_enable
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_PORT_LOCK:
+ * Mask for port_lock_enable
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNING_LIMIT:
+ * Mask for mac_learning_limit_enable and mac_learning_limit
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNED_COUNT:
+ * Mask for mac_learning_count
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN_FILTER:
+ * Mask for ingress_vlan_filter_enable, ingress_vlan_filter_block_id
+ * and ingress_vlan_filter_block_size
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER1:
+ * Mask for bypass_egress_vlan_filter1, egress_vlan_filter1enable,
+ * egress_vlan_filter1block_id and egress_vlan_filter1block_size
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER2:
+ * Mask for egress_vlan_filter2enable, egress_vlan_filter2block_id and
+ * egress_vlan_filter2block_size
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MAC_LEARNING:
+ * Mask for vlan_tag_selection, vlan_src_mac_priority_enable,
+ * vlan_src_mac_dei_enable, vlan_src_mac_vid_enable,
+ * vlan_dst_mac_priority_enable, vlan_dst_mac_dei_enable and
+ * vlan_dst_mac_vid_enable
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MULTICAST_LOOKUP:
+ * Mask for vlan_multicast_priority_enable,
+ * vlan_multicast_dei_enable and vlan_multicast_vid_enable
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_LOOP_VIOLATION_COUNTER:
+ * Mask for loop_violation_count
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_ALL: Enable all
+ * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_FORCE: Bypass any check for debug purpose
+ */
+enum mxl862xx_bridge_port_config_mask {
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_ID = BIT(0),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN = BIT(1),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN = BIT(2),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_MARKING = BIT(3),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_REMARKING = BIT(4),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_METER = BIT(5),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_SUB_METER = BIT(6),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_CTP_MAPPING = BIT(7),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_PORT_MAP = BIT(8),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_IP_LOOKUP = BIT(9),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_IP_LOOKUP = BIT(10),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_MAC_LOOKUP = BIT(11),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_MAC_LEARNING = BIT(12),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_SPOOFING = BIT(13),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_PORT_LOCK = BIT(14),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNING_LIMIT = BIT(15),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNED_COUNT = BIT(16),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN_FILTER = BIT(17),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER1 = BIT(18),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER2 = BIT(19),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MAC_LEARNING = BIT(20),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MULTICAST_LOOKUP = BIT(21),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_LOOP_VIOLATION_COUNTER = BIT(22),
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_ALL = 0x7FFFFFFF,
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_FORCE = BIT(31)
+};
+
+/**
+ * enum mxl862xx_color_marking_mode - Color Marking Mode
+ * @MXL862XX_MARKING_ALL_GREEN: mark packets (except critical) to green
+ * @MXL862XX_MARKING_INTERNAL_MARKING: do not change color and priority
+ * @MXL862XX_MARKING_DEI: DEI mark mode
+ * @MXL862XX_MARKING_PCP_8P0D: PCP 8P0D mark mode
+ * @MXL862XX_MARKING_PCP_7P1D: PCP 7P1D mark mode
+ * @MXL862XX_MARKING_PCP_6P2D: PCP 6P2D mark mode
+ * @MXL862XX_MARKING_PCP_5P3D: PCP 5P3D mark mode
+ * @MXL862XX_MARKING_DSCP_AF: DSCP AF class
+ */
+enum mxl862xx_color_marking_mode {
+ MXL862XX_MARKING_ALL_GREEN = 0,
+ MXL862XX_MARKING_INTERNAL_MARKING,
+ MXL862XX_MARKING_DEI,
+ MXL862XX_MARKING_PCP_8P0D,
+ MXL862XX_MARKING_PCP_7P1D,
+ MXL862XX_MARKING_PCP_6P2D,
+ MXL862XX_MARKING_PCP_5P3D,
+ MXL862XX_MARKING_DSCP_AF,
+};
+
+/**
+ * enum mxl862xx_color_remarking_mode - Color Remarking Mode
+ * @MXL862XX_REMARKING_NONE: values from last process stage
+ * @MXL862XX_REMARKING_DEI: DEI mark mode
+ * @MXL862XX_REMARKING_PCP_8P0D: PCP 8P0D mark mode
+ * @MXL862XX_REMARKING_PCP_7P1D: PCP 7P1D mark mode
+ * @MXL862XX_REMARKING_PCP_6P2D: PCP 6P2D mark mode
+ * @MXL862XX_REMARKING_PCP_5P3D: PCP 5P3D mark mode
+ * @MXL862XX_REMARKING_DSCP_AF: DSCP AF class
+ */
+enum mxl862xx_color_remarking_mode {
+ MXL862XX_REMARKING_NONE = 0,
+ MXL862XX_REMARKING_DEI = 2,
+ MXL862XX_REMARKING_PCP_8P0D,
+ MXL862XX_REMARKING_PCP_7P1D,
+ MXL862XX_REMARKING_PCP_6P2D,
+ MXL862XX_REMARKING_PCP_5P3D,
+ MXL862XX_REMARKING_DSCP_AF,
+};
+
+/**
+ * enum mxl862xx_pmapper_mapping_mode - P-mapper Mapping Mode
+ * @MXL862XX_PMAPPER_MAPPING_PCP: Use PCP for VLAN tagged packets to derive
+ * sub interface ID group
+ * @MXL862XX_PMAPPER_MAPPING_LAG: Use LAG Index for Pmapper access
+ * regardless of IP and VLAN packet
+ * @MXL862XX_PMAPPER_MAPPING_DSCP: Use DSCP for VLAN tagged IP packets to
+ * derive sub interface ID group
+ */
+enum mxl862xx_pmapper_mapping_mode {
+ MXL862XX_PMAPPER_MAPPING_PCP = 0,
+ MXL862XX_PMAPPER_MAPPING_LAG,
+ MXL862XX_PMAPPER_MAPPING_DSCP,
+};
+
+/**
+ * struct mxl862xx_pmapper - P-mapper Configuration
+ * @pmapper_id: Index of P-mapper (0-31)
+ * @dest_sub_if_id_group: Sub interface ID group. Entry 0 is for non-IP and
+ * non-VLAN tagged packets.
+ * Entries 1-8 are PCP mapping entries for VLAN tagged
+ * packets.
+ * Entries 9-72 are DSCP or LAG mapping entries.
+ *
+ * Used by CTP port config and bridge port config. In case of LAG, it is
+ * user's responsibility to provide the mapped entries in given P-mapper
+ * table. In other modes the entries are auto mapped from input packet.
+ */
+struct mxl862xx_pmapper {
+ __le16 pmapper_id;
+ u8 dest_sub_if_id_group[73];
+} __packed;
+
+/**
+ * struct mxl862xx_bridge_port_config - Bridge Port Configuration
+ * @bridge_port_id: Bridge Port ID allocated by bridge port allocation
+ * @mask: See &enum mxl862xx_bridge_port_config_mask
+ * @bridge_id: Bridge ID (FID) to which this bridge port is associated
+ * @ingress_extended_vlan_enable: Enable extended VLAN processing for
+ * ingress traffic
+ * @ingress_extended_vlan_block_id: Extended VLAN block allocated for
+ * ingress traffic
+ * @ingress_extended_vlan_block_size: Extended VLAN block size for ingress
+ * traffic
+ * @egress_extended_vlan_enable: Enable extended VLAN processing for egress
+ * traffic
+ * @egress_extended_vlan_block_id: Extended VLAN block allocated for egress
+ * traffic
+ * @egress_extended_vlan_block_size: Extended VLAN block size for egress
+ * traffic
+ * @ingress_marking_mode: Ingress color marking mode. See
+ * &enum mxl862xx_color_marking_mode
+ * @egress_remarking_mode: Color remarking for egress traffic. See
+ * &enum mxl862xx_color_remarking_mode
+ * @ingress_metering_enable: Traffic metering on ingress traffic applies
+ * @ingress_traffic_meter_id: Meter for ingress Bridge Port process
+ * @egress_sub_metering_enable: Traffic metering on various types of egress
+ * traffic
+ * @egress_traffic_sub_meter_id: Meter for egress Bridge Port process with
+ * specific type
+ * @dest_logical_port_id: Destination logical port
+ * @pmapper_enable: Enable P-mapper
+ * @dest_sub_if_id_group: Destination sub interface ID group when
+ * pmapper_enable is false
+ * @pmapper_mapping_mode: P-mapper mapping mode. See
+ * &enum mxl862xx_pmapper_mapping_mode
+ * @pmapper_id_valid: When true, P-mapper is re-used; when false,
+ * allocation is handled by API
+ * @pmapper: P-mapper configuration used when pmapper_enable is true
+ * @bridge_port_map: Port map defining broadcast domain. Each bit
+ * represents one bridge port. Bridge port ID is
+ * index * 16 + bit offset.
+ * @mc_dest_ip_lookup_disable: Disable multicast IP destination table
+ * lookup
+ * @mc_src_ip_lookup_enable: Enable multicast IP source table lookup
+ * @dest_mac_lookup_disable: Disable destination MAC lookup; packet treated
+ * as unknown
+ * @src_mac_learning_disable: Disable source MAC address learning
+ * @mac_spoofing_detect_enable: Enable MAC spoofing detection
+ * @port_lock_enable: Enable port locking
+ * @mac_learning_limit_enable: Enable MAC learning limitation
+ * @mac_learning_limit: Maximum number of MAC addresses that can be learned
+ * from this bridge port
+ * @loop_violation_count: Number of loop violation events from this bridge
+ * port
+ * @mac_learning_count: Number of MAC addresses learned from this bridge
+ * port
+ * @ingress_vlan_filter_enable: Enable ingress VLAN filter
+ * @ingress_vlan_filter_block_id: VLAN filter block of ingress traffic
+ * @ingress_vlan_filter_block_size: VLAN filter block size for ingress
+ * traffic
+ * @bypass_egress_vlan_filter1: For ingress traffic, bypass VLAN filter 1
+ * at egress bridge port processing
+ * @egress_vlan_filter1enable: Enable egress VLAN filter 1
+ * @egress_vlan_filter1block_id: VLAN filter block 1 of egress traffic
+ * @egress_vlan_filter1block_size: VLAN filter block 1 size
+ * @egress_vlan_filter2enable: Enable egress VLAN filter 2
+ * @egress_vlan_filter2block_id: VLAN filter block 2 of egress traffic
+ * @egress_vlan_filter2block_size: VLAN filter block 2 size
+ * @vlan_tag_selection: VLAN tag selection for MAC address/multicast
+ * learning, lookup and filtering.
+ * 0 - Intermediate outer VLAN tag is used.
+ * 1 - Original outer VLAN tag is used.
+ * @vlan_src_mac_priority_enable: Enable VLAN Priority field for source MAC
+ * learning and filtering
+ * @vlan_src_mac_dei_enable: Enable VLAN DEI/CFI field for source MAC
+ * learning and filtering
+ * @vlan_src_mac_vid_enable: Enable VLAN ID field for source MAC learning
+ * and filtering
+ * @vlan_dst_mac_priority_enable: Enable VLAN Priority field for destination
+ * MAC lookup and filtering
+ * @vlan_dst_mac_dei_enable: Enable VLAN CFI/DEI field for destination MAC
+ * lookup and filtering
+ * @vlan_dst_mac_vid_enable: Enable VLAN ID field for destination MAC lookup
+ * and filtering
+ * @vlan_multicast_priority_enable: Enable VLAN Priority field for IP
+ * multicast lookup
+ * @vlan_multicast_dei_enable: Enable VLAN CFI/DEI field for IP multicast
+ * lookup
+ * @vlan_multicast_vid_enable: Enable VLAN ID field for IP multicast lookup
+ */
+struct mxl862xx_bridge_port_config {
+ __le16 bridge_port_id;
+ __le32 mask; /* enum mxl862xx_bridge_port_config_mask */
+ __le16 bridge_id;
+ u8 ingress_extended_vlan_enable;
+ __le16 ingress_extended_vlan_block_id;
+ __le16 ingress_extended_vlan_block_size;
+ u8 egress_extended_vlan_enable;
+ __le16 egress_extended_vlan_block_id;
+ __le16 egress_extended_vlan_block_size;
+ __le32 ingress_marking_mode; /* enum mxl862xx_color_marking_mode */
+ __le32 egress_remarking_mode; /* enum mxl862xx_color_remarking_mode */
+ u8 ingress_metering_enable;
+ __le16 ingress_traffic_meter_id;
+ u8 egress_sub_metering_enable[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX];
+ __le16 egress_traffic_sub_meter_id[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX];
+ u8 dest_logical_port_id;
+ u8 pmapper_enable;
+ __le16 dest_sub_if_id_group;
+ __le32 pmapper_mapping_mode; /* enum mxl862xx_pmapper_mapping_mode */
+ u8 pmapper_id_valid;
+ struct mxl862xx_pmapper pmapper;
+ __le16 bridge_port_map[8];
+ u8 mc_dest_ip_lookup_disable;
+ u8 mc_src_ip_lookup_enable;
+ u8 dest_mac_lookup_disable;
+ u8 src_mac_learning_disable;
+ u8 mac_spoofing_detect_enable;
+ u8 port_lock_enable;
+ u8 mac_learning_limit_enable;
+ __le16 mac_learning_limit;
+ __le16 loop_violation_count;
+ __le16 mac_learning_count;
+ u8 ingress_vlan_filter_enable;
+ __le16 ingress_vlan_filter_block_id;
+ __le16 ingress_vlan_filter_block_size;
+ u8 bypass_egress_vlan_filter1;
+ u8 egress_vlan_filter1enable;
+ __le16 egress_vlan_filter1block_id;
+ __le16 egress_vlan_filter1block_size;
+ u8 egress_vlan_filter2enable;
+ __le16 egress_vlan_filter2block_id;
+ __le16 egress_vlan_filter2block_size;
+ u8 vlan_tag_selection;
+ u8 vlan_src_mac_priority_enable;
+ u8 vlan_src_mac_dei_enable;
+ u8 vlan_src_mac_vid_enable;
+ u8 vlan_dst_mac_priority_enable;
+ u8 vlan_dst_mac_dei_enable;
+ u8 vlan_dst_mac_vid_enable;
+ u8 vlan_multicast_priority_enable;
+ u8 vlan_multicast_dei_enable;
+ u8 vlan_multicast_vid_enable;
+} __packed;
+
+/**
+ * struct mxl862xx_cfg - Global Switch configuration Attributes
+ * @mac_table_age_timer: See &enum mxl862xx_age_timer
+ * @age_timer: Custom MAC table aging timer in seconds
+ * @max_packet_len: Maximum Ethernet packet length
+ * @learning_limit_action: Automatic MAC address table learning limitation
+ * consecutive action
+ * @mac_locking_action: Accept or discard MAC port locking violation
+ * packets
+ * @mac_spoofing_action: Accept or discard MAC spoofing and port MAC locking
+ * violation packets
+ * @pause_mac_mode_src: Pause frame MAC source address mode
+ * @pause_mac_src: Pause frame MAC source address
+ */
+struct mxl862xx_cfg {
+ __le32 mac_table_age_timer; /* enum mxl862xx_age_timer */
+ __le32 age_timer;
+ __le16 max_packet_len;
+ u8 learning_limit_action;
+ u8 mac_locking_action;
+ u8 mac_spoofing_action;
+ u8 pause_mac_mode_src;
+ u8 pause_mac_src[ETH_ALEN];
+} __packed;
+
+/**
+ * enum mxl862xx_ss_sp_tag_mask - Special tag valid field indicator bits
+ * @MXL862XX_SS_SP_TAG_MASK_RX: valid RX special tag mode
+ * @MXL862XX_SS_SP_TAG_MASK_TX: valid TX special tag mode
+ * @MXL862XX_SS_SP_TAG_MASK_RX_PEN: valid RX special tag info over preamble
+ * @MXL862XX_SS_SP_TAG_MASK_TX_PEN: valid TX special tag info over preamble
+ */
+enum mxl862xx_ss_sp_tag_mask {
+ MXL862XX_SS_SP_TAG_MASK_RX = BIT(0),
+ MXL862XX_SS_SP_TAG_MASK_TX = BIT(1),
+ MXL862XX_SS_SP_TAG_MASK_RX_PEN = BIT(2),
+ MXL862XX_SS_SP_TAG_MASK_TX_PEN = BIT(3),
+};
+
+/**
+ * enum mxl862xx_ss_sp_tag_rx - RX special tag mode
+ * @MXL862XX_SS_SP_TAG_RX_NO_TAG_NO_INSERT: packet does NOT have special
+ * tag and special tag is NOT inserted
+ * @MXL862XX_SS_SP_TAG_RX_NO_TAG_INSERT: packet does NOT have special tag
+ * and special tag is inserted
+ * @MXL862XX_SS_SP_TAG_RX_TAG_NO_INSERT: packet has special tag and special
+ * tag is NOT inserted
+ */
+enum mxl862xx_ss_sp_tag_rx {
+ MXL862XX_SS_SP_TAG_RX_NO_TAG_NO_INSERT = 0,
+ MXL862XX_SS_SP_TAG_RX_NO_TAG_INSERT = 1,
+ MXL862XX_SS_SP_TAG_RX_TAG_NO_INSERT = 2,
+};
+
+/**
+ * enum mxl862xx_ss_sp_tag_tx - TX special tag mode
+ * @MXL862XX_SS_SP_TAG_TX_NO_TAG_NO_REMOVE: packet does NOT have special
+ * tag and special tag is NOT removed
+ * @MXL862XX_SS_SP_TAG_TX_TAG_REPLACE: packet has special tag and special
+ * tag is replaced
+ * @MXL862XX_SS_SP_TAG_TX_TAG_NO_REMOVE: packet has special tag and special
+ * tag is NOT removed
+ * @MXL862XX_SS_SP_TAG_TX_TAG_REMOVE: packet has special tag and special
+ * tag is removed
+ */
+enum mxl862xx_ss_sp_tag_tx {
+ MXL862XX_SS_SP_TAG_TX_NO_TAG_NO_REMOVE = 0,
+ MXL862XX_SS_SP_TAG_TX_TAG_REPLACE = 1,
+ MXL862XX_SS_SP_TAG_TX_TAG_NO_REMOVE = 2,
+ MXL862XX_SS_SP_TAG_TX_TAG_REMOVE = 3,
+};
+
+/**
+ * enum mxl862xx_ss_sp_tag_rx_pen - RX special tag info over preamble
+ * @MXL862XX_SS_SP_TAG_RX_PEN_ALL_0: special tag info inserted from byte 2
+ * to 7 are all 0
+ * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_IS_16: special tag byte 5 is 16, other
+ * bytes from 2 to 7 are 0
+ * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_FROM_PREAMBLE: special tag byte 5 is
+ * from preamble field, others
+ * are 0
+ * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_2_TO_7_FROM_PREAMBLE: special tag byte 2
+ * to 7 are from preamble
+ * field
+ */
+enum mxl862xx_ss_sp_tag_rx_pen {
+ MXL862XX_SS_SP_TAG_RX_PEN_ALL_0 = 0,
+ MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_IS_16 = 1,
+ MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_FROM_PREAMBLE = 2,
+ MXL862XX_SS_SP_TAG_RX_PEN_BYTE_2_TO_7_FROM_PREAMBLE = 3,
+};
+
+/**
+ * struct mxl862xx_ss_sp_tag - Special tag port settings
+ * @pid: port ID (1~16)
+ * @mask: See &enum mxl862xx_ss_sp_tag_mask
+ * @rx: See &enum mxl862xx_ss_sp_tag_rx
+ * @tx: See &enum mxl862xx_ss_sp_tag_tx
+ * @rx_pen: See &enum mxl862xx_ss_sp_tag_rx_pen
+ * @tx_pen: TX special tag info over preamble
+ * 0 - disabled
+ * 1 - enabled
+ */
+struct mxl862xx_ss_sp_tag {
+ u8 pid;
+ u8 mask; /* enum mxl862xx_ss_sp_tag_mask */
+ u8 rx; /* enum mxl862xx_ss_sp_tag_rx */
+ u8 tx; /* enum mxl862xx_ss_sp_tag_tx */
+ u8 rx_pen; /* enum mxl862xx_ss_sp_tag_rx_pen */
+ u8 tx_pen; /* boolean */
+} __packed;
+
+/**
+ * enum mxl862xx_logical_port_mode - Logical port mode
+ * @MXL862XX_LOGICAL_PORT_8BIT_WLAN: WLAN with 8-bit station ID
+ * @MXL862XX_LOGICAL_PORT_9BIT_WLAN: WLAN with 9-bit station ID
+ * @MXL862XX_LOGICAL_PORT_ETHERNET: Ethernet port
+ * @MXL862XX_LOGICAL_PORT_OTHER: Others
+ */
+enum mxl862xx_logical_port_mode {
+ MXL862XX_LOGICAL_PORT_8BIT_WLAN = 0,
+ MXL862XX_LOGICAL_PORT_9BIT_WLAN,
+ MXL862XX_LOGICAL_PORT_ETHERNET,
+ MXL862XX_LOGICAL_PORT_OTHER = 0xFF,
+};
+
+/**
+ * struct mxl862xx_ctp_port_assignment - CTP Port Assignment/association
+ * with logical port
+ * @logical_port_id: Logical Port Id. The valid range is hardware dependent
+ * @first_ctp_port_id: First CTP (Connectivity Termination Port) ID mapped
+ * to above logical port ID
+ * @number_of_ctp_port: Total number of CTP Ports mapped above logical port
+ * ID
+ * @mode: Logical port mode to define sub interface ID format. See
+ * &enum mxl862xx_logical_port_mode
+ * @bridge_port_id: Bridge Port ID (not FID). For allocation, each CTP
+ * allocated is mapped to the Bridge Port given by this field.
+ * The Bridge Port will be configured to use first CTP as
+ * egress CTP.
+ */
+struct mxl862xx_ctp_port_assignment {
+ u8 logical_port_id;
+ __le16 first_ctp_port_id;
+ __le16 number_of_ctp_port;
+ __le32 mode; /* enum mxl862xx_logical_port_mode */
+ __le16 bridge_port_id;
+} __packed;
+
+/**
+ * struct mxl862xx_sys_fw_image_version - Firmware version information
+ * @iv_major: firmware major version
+ * @iv_minor: firmware minor version
+ * @iv_revision: firmware revision
+ * @iv_build_num: firmware build number
+ */
+struct mxl862xx_sys_fw_image_version {
+ u8 iv_major;
+ u8 iv_minor;
+ __le16 iv_revision;
+ __le32 iv_build_num;
+} __packed;
+
+#endif /* __MXL862XX_API_H */
diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-cmd.h b/drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
new file mode 100644
index 000000000000..f6852ade64e7
--- /dev/null
+++ b/drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MXL862XX_CMD_H
+#define __MXL862XX_CMD_H
+
+#define MXL862XX_MMD_DEV 30
+#define MXL862XX_MMD_REG_CTRL 0
+#define MXL862XX_MMD_REG_LEN_RET 1
+#define MXL862XX_MMD_REG_DATA_FIRST 2
+#define MXL862XX_MMD_REG_DATA_LAST 95
+#define MXL862XX_MMD_REG_DATA_MAX_SIZE \
+ (MXL862XX_MMD_REG_DATA_LAST - MXL862XX_MMD_REG_DATA_FIRST + 1)
+
+#define MXL862XX_COMMON_MAGIC 0x100
+#define MXL862XX_BRDG_MAGIC 0x300
+#define MXL862XX_BRDGPORT_MAGIC 0x400
+#define MXL862XX_CTP_MAGIC 0x500
+#define MXL862XX_SWMAC_MAGIC 0xa00
+#define MXL862XX_SS_MAGIC 0x1600
+#define GPY_GPY2XX_MAGIC 0x1800
+#define SYS_MISC_MAGIC 0x1900
+
+#define MXL862XX_COMMON_CFGGET (MXL862XX_COMMON_MAGIC + 0x9)
+#define MXL862XX_COMMON_REGISTERMOD (MXL862XX_COMMON_MAGIC + 0x11)
+
+#define MXL862XX_BRIDGE_ALLOC (MXL862XX_BRDG_MAGIC + 0x1)
+#define MXL862XX_BRIDGE_CONFIGSET (MXL862XX_BRDG_MAGIC + 0x2)
+#define MXL862XX_BRIDGE_CONFIGGET (MXL862XX_BRDG_MAGIC + 0x3)
+#define MXL862XX_BRIDGE_FREE (MXL862XX_BRDG_MAGIC + 0x4)
+
+#define MXL862XX_BRIDGEPORT_ALLOC (MXL862XX_BRDGPORT_MAGIC + 0x1)
+#define MXL862XX_BRIDGEPORT_CONFIGSET (MXL862XX_BRDGPORT_MAGIC + 0x2)
+#define MXL862XX_BRIDGEPORT_CONFIGGET (MXL862XX_BRDGPORT_MAGIC + 0x3)
+#define MXL862XX_BRIDGEPORT_FREE (MXL862XX_BRDGPORT_MAGIC + 0x4)
+
+#define MXL862XX_CTP_PORTASSIGNMENTSET (MXL862XX_CTP_MAGIC + 0x3)
+
+#define MXL862XX_MAC_TABLECLEARCOND (MXL862XX_SWMAC_MAGIC + 0x8)
+
+#define MXL862XX_SS_SPTAG_SET (MXL862XX_SS_MAGIC + 0x02)
+
+#define INT_GPHY_READ (GPY_GPY2XX_MAGIC + 0x01)
+#define INT_GPHY_WRITE (GPY_GPY2XX_MAGIC + 0x02)
+
+#define SYS_MISC_FW_VERSION (SYS_MISC_MAGIC + 0x02)
+
+#define MMD_API_MAXIMUM_ID 0x7fff
+
+#endif /* __MXL862XX_CMD_H */
diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-host.c b/drivers/net/dsa/mxl862xx/mxl862xx-host.c
new file mode 100644
index 000000000000..f2b3c0b1dff1
--- /dev/null
+++ b/drivers/net/dsa/mxl862xx/mxl862xx-host.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Based upon the Maxlinear SDK driver
+ *
+ * Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
+ * Copyright (C) 2025 John Crispin <john@phrozen.org>
+ * Copyright (C) 2024 MaxLinear Inc.
+ */
+
+#include <linux/bits.h>
+#include <linux/iopoll.h>
+#include <linux/limits.h>
+#include <net/dsa.h>
+#include "mxl862xx.h"
+#include "mxl862xx-host.h"
+
+#define CTRL_BUSY_MASK BIT(15)
+
+#define MXL862XX_MMD_REG_CTRL 0
+#define MXL862XX_MMD_REG_LEN_RET 1
+#define MXL862XX_MMD_REG_DATA_FIRST 2
+#define MXL862XX_MMD_REG_DATA_LAST 95
+#define MXL862XX_MMD_REG_DATA_MAX_SIZE \
+ (MXL862XX_MMD_REG_DATA_LAST - MXL862XX_MMD_REG_DATA_FIRST + 1)
+
+#define MMD_API_SET_DATA_0 2
+#define MMD_API_GET_DATA_0 5
+#define MMD_API_RST_DATA 8
+
+#define MXL862XX_SWITCH_RESET 0x9907
+
+static int mxl862xx_reg_read(struct mxl862xx_priv *priv, u32 addr)
+{
+ return __mdiodev_c45_read(priv->mdiodev, MDIO_MMD_VEND1, addr);
+}
+
+static int mxl862xx_reg_write(struct mxl862xx_priv *priv, u32 addr, u16 data)
+{
+ return __mdiodev_c45_write(priv->mdiodev, MDIO_MMD_VEND1, addr, data);
+}
+
+static int mxl862xx_ctrl_read(struct mxl862xx_priv *priv)
+{
+ return mxl862xx_reg_read(priv, MXL862XX_MMD_REG_CTRL);
+}
+
+static int mxl862xx_busy_wait(struct mxl862xx_priv *priv)
+{
+ int val;
+
+ return readx_poll_timeout(mxl862xx_ctrl_read, priv, val,
+ !(val & CTRL_BUSY_MASK), 15, 10000);
+}
+
+static int mxl862xx_set_data(struct mxl862xx_priv *priv, u16 words)
+{
+ int ret;
+ u16 cmd;
+
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_LEN_RET,
+ MXL862XX_MMD_REG_DATA_MAX_SIZE * sizeof(u16));
+ if (ret < 0)
+ return ret;
+
+ cmd = words / MXL862XX_MMD_REG_DATA_MAX_SIZE - 1;
+ if (!(cmd < 2))
+ return -EINVAL;
+
+ cmd += MMD_API_SET_DATA_0;
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_CTRL,
+ cmd | CTRL_BUSY_MASK);
+ if (ret < 0)
+ return ret;
+
+ return mxl862xx_busy_wait(priv);
+}
+
+static int mxl862xx_get_data(struct mxl862xx_priv *priv, u16 words)
+{
+ int ret;
+ u16 cmd;
+
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_LEN_RET,
+ MXL862XX_MMD_REG_DATA_MAX_SIZE * sizeof(u16));
+ if (ret < 0)
+ return ret;
+
+ cmd = words / MXL862XX_MMD_REG_DATA_MAX_SIZE;
+ if (!(cmd > 0 && cmd < 3))
+ return -EINVAL;
+
+ cmd += MMD_API_GET_DATA_0;
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_CTRL,
+ cmd | CTRL_BUSY_MASK);
+ if (ret < 0)
+ return ret;
+
+ return mxl862xx_busy_wait(priv);
+}
+
+static int mxl862xx_firmware_return(int ret)
+{
+ /* Only 16-bit values are valid. */
+ if (WARN_ON(ret & GENMASK(31, 16)))
+ return -EINVAL;
+
+ /* Interpret value as signed 16-bit integer. */
+ return (s16)ret;
+}
+
+static int mxl862xx_send_cmd(struct mxl862xx_priv *priv, u16 cmd, u16 size,
+ bool quiet)
+{
+ int ret;
+
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_LEN_RET, size);
+ if (ret)
+ return ret;
+
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_CTRL,
+ cmd | CTRL_BUSY_MASK);
+ if (ret)
+ return ret;
+
+ ret = mxl862xx_busy_wait(priv);
+ if (ret)
+ return ret;
+
+ ret = mxl862xx_reg_read(priv, MXL862XX_MMD_REG_LEN_RET);
+ if (ret < 0)
+ return ret;
+
+ /* handle errors returned by the firmware as -EIO
+ * The firmware is based on Zephyr OS and uses the errors as
+ * defined in errno.h of Zephyr OS. See
+ * https://github.com/zephyrproject-rtos/zephyr/blob/v3.7.0/lib/libc/minimal/include/errno.h
+ */
+ ret = mxl862xx_firmware_return(ret);
+ if (ret < 0) {
+ if (!quiet)
+ dev_err(&priv->mdiodev->dev,
+ "CMD %04x returned error %d\n", cmd, ret);
+ return -EIO;
+ }
+
+ return ret;
+}
+
+int mxl862xx_api_wrap(struct mxl862xx_priv *priv, u16 cmd, void *_data,
+ u16 size, bool read, bool quiet)
+{
+ __le16 *data = _data;
+ int ret, cmd_ret;
+ u16 max, i;
+
+ dev_dbg(&priv->mdiodev->dev, "CMD %04x DATA %*ph\n", cmd, size, data);
+
+ mutex_lock_nested(&priv->mdiodev->bus->mdio_lock, MDIO_MUTEX_NESTED);
+
+ max = (size + 1) / 2;
+
+ ret = mxl862xx_busy_wait(priv);
+ if (ret < 0)
+ goto out;
+
+ for (i = 0; i < max; i++) {
+ u16 off = i % MXL862XX_MMD_REG_DATA_MAX_SIZE;
+
+ if (i && off == 0) {
+ /* Send command to set data when every
+ * MXL862XX_MMD_REG_DATA_MAX_SIZE of WORDs are written.
+ */
+ ret = mxl862xx_set_data(priv, i);
+ if (ret < 0)
+ goto out;
+ }
+
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_DATA_FIRST + off,
+ le16_to_cpu(data[i]));
+ if (ret < 0)
+ goto out;
+ }
+
+ ret = mxl862xx_send_cmd(priv, cmd, size, quiet);
+ if (ret < 0 || !read)
+ goto out;
+
+ /* store result of mxl862xx_send_cmd() */
+ cmd_ret = ret;
+
+ for (i = 0; i < max; i++) {
+ u16 off = i % MXL862XX_MMD_REG_DATA_MAX_SIZE;
+
+ if (i && off == 0) {
+ /* Send command to fetch next batch of data when every
+ * MXL862XX_MMD_REG_DATA_MAX_SIZE of WORDs are read.
+ */
+ ret = mxl862xx_get_data(priv, i);
+ if (ret < 0)
+ goto out;
+ }
+
+ ret = mxl862xx_reg_read(priv, MXL862XX_MMD_REG_DATA_FIRST + off);
+ if (ret < 0)
+ goto out;
+
+ if ((i * 2 + 1) == size) {
+ /* Special handling for last BYTE if it's not WORD
+ * aligned to avoid writing beyond the allocated data
+ * structure.
+ */
+ *(uint8_t *)&data[i] = ret & 0xff;
+ } else {
+ data[i] = cpu_to_le16((u16)ret);
+ }
+ }
+
+ /* on success return the result of the mxl862xx_send_cmd() */
+ ret = cmd_ret;
+
+ dev_dbg(&priv->mdiodev->dev, "RET %d DATA %*ph\n", ret, size, data);
+
+out:
+ mutex_unlock(&priv->mdiodev->bus->mdio_lock);
+
+ return ret;
+}
+
+int mxl862xx_reset(struct mxl862xx_priv *priv)
+{
+ int ret;
+
+ mutex_lock_nested(&priv->mdiodev->bus->mdio_lock, MDIO_MUTEX_NESTED);
+
+ /* Software reset */
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_LEN_RET, 0);
+ if (ret)
+ goto out;
+
+ ret = mxl862xx_reg_write(priv, MXL862XX_MMD_REG_CTRL, MXL862XX_SWITCH_RESET);
+out:
+ mutex_unlock(&priv->mdiodev->bus->mdio_lock);
+
+ return ret;
+}
diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-host.h b/drivers/net/dsa/mxl862xx/mxl862xx-host.h
new file mode 100644
index 000000000000..7cc496f6be5c
--- /dev/null
+++ b/drivers/net/dsa/mxl862xx/mxl862xx-host.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MXL862XX_HOST_H
+#define __MXL862XX_HOST_H
+
+#include "mxl862xx.h"
+
+int mxl862xx_api_wrap(struct mxl862xx_priv *priv, u16 cmd, void *data, u16 size,
+ bool read, bool quiet);
+int mxl862xx_reset(struct mxl862xx_priv *priv);
+
+#endif /* __MXL862XX_HOST_H */
diff --git a/drivers/net/dsa/mxl862xx/mxl862xx.c b/drivers/net/dsa/mxl862xx/mxl862xx.c
new file mode 100644
index 000000000000..43d2a6120898
--- /dev/null
+++ b/drivers/net/dsa/mxl862xx/mxl862xx.c
@@ -0,0 +1,483 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for MaxLinear MxL862xx switch family
+ *
+ * Copyright (C) 2024 MaxLinear Inc.
+ * Copyright (C) 2025 John Crispin <john@phrozen.org>
+ * Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/of_device.h>
+#include <linux/of_mdio.h>
+#include <linux/phy.h>
+#include <linux/phylink.h>
+#include <net/dsa.h>
+
+#include "mxl862xx.h"
+#include "mxl862xx-api.h"
+#include "mxl862xx-cmd.h"
+#include "mxl862xx-host.h"
+
+#define MXL862XX_API_WRITE(dev, cmd, data) \
+ mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), false, false)
+#define MXL862XX_API_READ(dev, cmd, data) \
+ mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), true, false)
+#define MXL862XX_API_READ_QUIET(dev, cmd, data) \
+ mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), true, true)
+
+#define MXL862XX_SDMA_PCTRLP(p) (0xbc0 + ((p) * 0x6))
+#define MXL862XX_SDMA_PCTRL_EN BIT(0)
+
+#define MXL862XX_FDMA_PCTRLP(p) (0xa80 + ((p) * 0x6))
+#define MXL862XX_FDMA_PCTRL_EN BIT(0)
+
+#define MXL862XX_READY_TIMEOUT_MS 10000
+#define MXL862XX_READY_POLL_MS 100
+
+static enum dsa_tag_protocol mxl862xx_get_tag_protocol(struct dsa_switch *ds,
+ int port,
+ enum dsa_tag_protocol m)
+{
+ return DSA_TAG_PROTO_MXL862;
+}
+
+/* PHY access via firmware relay */
+static int mxl862xx_phy_read_mmd(struct mxl862xx_priv *priv, int port,
+ int devadd, int reg)
+{
+ struct mdio_relay_data param = {
+ .phy = port,
+ .mmd = devadd,
+ .reg = cpu_to_le16(reg),
+ };
+ int ret;
+
+ ret = MXL862XX_API_READ(priv, INT_GPHY_READ, param);
+ if (ret)
+ return ret;
+
+ return le16_to_cpu(param.data);
+}
+
+static int mxl862xx_phy_write_mmd(struct mxl862xx_priv *priv, int port,
+ int devadd, int reg, u16 data)
+{
+ struct mdio_relay_data param = {
+ .phy = port,
+ .mmd = devadd,
+ .reg = cpu_to_le16(reg),
+ .data = cpu_to_le16(data),
+ };
+
+ return MXL862XX_API_WRITE(priv, INT_GPHY_WRITE, param);
+}
+
+static int mxl862xx_phy_read_mii_bus(struct mii_bus *bus, int port, int regnum)
+{
+ return mxl862xx_phy_read_mmd(bus->priv, port, 0, regnum);
+}
+
+static int mxl862xx_phy_write_mii_bus(struct mii_bus *bus, int port,
+ int regnum, u16 val)
+{
+ return mxl862xx_phy_write_mmd(bus->priv, port, 0, regnum, val);
+}
+
+static int mxl862xx_phy_read_c45_mii_bus(struct mii_bus *bus, int port,
+ int devadd, int regnum)
+{
+ return mxl862xx_phy_read_mmd(bus->priv, port, devadd, regnum);
+}
+
+static int mxl862xx_phy_write_c45_mii_bus(struct mii_bus *bus, int port,
+ int devadd, int regnum, u16 val)
+{
+ return mxl862xx_phy_write_mmd(bus->priv, port, devadd, regnum, val);
+}
+
+static int mxl862xx_configure_ctp_port(struct dsa_switch *ds, int port,
+ u16 first_ctp_port_id,
+ u16 number_of_ctp_ports)
+{
+ struct mxl862xx_ctp_port_assignment ctp_assign = {
+ .logical_port_id = port,
+ .first_ctp_port_id = cpu_to_le16(first_ctp_port_id),
+ .number_of_ctp_port = cpu_to_le16(number_of_ctp_ports),
+ .mode = cpu_to_le32(MXL862XX_LOGICAL_PORT_ETHERNET),
+ };
+
+ return MXL862XX_API_WRITE(ds->priv, MXL862XX_CTP_PORTASSIGNMENTSET,
+ ctp_assign);
+}
+
+static int mxl862xx_configure_sp_tag_proto(struct dsa_switch *ds, int port,
+ bool enable)
+{
+ struct mxl862xx_ss_sp_tag tag = {
+ .pid = port,
+ .mask = MXL862XX_SS_SP_TAG_MASK_RX | MXL862XX_SS_SP_TAG_MASK_TX,
+ .rx = enable ? MXL862XX_SS_SP_TAG_RX_TAG_NO_INSERT :
+ MXL862XX_SS_SP_TAG_RX_NO_TAG_INSERT,
+ .tx = enable ? MXL862XX_SS_SP_TAG_TX_TAG_NO_REMOVE :
+ MXL862XX_SS_SP_TAG_TX_TAG_REMOVE,
+ };
+
+ return MXL862XX_API_WRITE(ds->priv, MXL862XX_SS_SPTAG_SET, tag);
+}
+
+static int mxl862xx_port_state(struct dsa_switch *ds, int port, bool enable)
+{
+ struct mxl862xx_register_mod sdma = {
+ .addr = cpu_to_le16(MXL862XX_SDMA_PCTRLP(port)),
+ .data = cpu_to_le16(enable ? MXL862XX_SDMA_PCTRL_EN : 0),
+ .mask = cpu_to_le16(MXL862XX_SDMA_PCTRL_EN),
+ };
+ struct mxl862xx_register_mod fdma = {
+ .addr = cpu_to_le16(MXL862XX_FDMA_PCTRLP(port)),
+ .data = cpu_to_le16(enable ? MXL862XX_FDMA_PCTRL_EN : 0),
+ .mask = cpu_to_le16(MXL862XX_FDMA_PCTRL_EN),
+ };
+ int ret;
+
+ ret = MXL862XX_API_WRITE(ds->priv, MXL862XX_COMMON_REGISTERMOD, sdma);
+ if (ret)
+ return ret;
+
+ return MXL862XX_API_WRITE(ds->priv, MXL862XX_COMMON_REGISTERMOD, fdma);
+}
+
+static int mxl862xx_port_enable(struct dsa_switch *ds, int port,
+ struct phy_device *phydev)
+{
+ return mxl862xx_port_state(ds, port, true);
+}
+
+static void mxl862xx_port_disable(struct dsa_switch *ds, int port)
+{
+ if (mxl862xx_port_state(ds, port, false))
+ dev_err(ds->dev, "failed to disable port %d\n", port);
+}
+
+static void mxl862xx_port_fast_age(struct dsa_switch *ds, int port)
+{
+ struct mxl862xx_mac_table_clear param = {
+ .type = MXL862XX_MAC_CLEAR_PHY_PORT,
+ .port_id = port,
+ };
+
+ if (MXL862XX_API_WRITE(ds->priv, MXL862XX_MAC_TABLECLEARCOND, param))
+ dev_err(ds->dev, "failed to clear fdb on port %d\n", port);
+}
+
+static int mxl862xx_add_single_port_bridge(struct dsa_switch *ds, int port)
+{
+ struct mxl862xx_bridge_port_config br_port_cfg = {};
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct mxl862xx_bridge_alloc br_alloc = {};
+ int ret;
+
+ if (!dp)
+ return -ENODEV;
+
+ ret = MXL862XX_API_READ(ds->priv, MXL862XX_BRIDGE_ALLOC, br_alloc);
+ if (ret) {
+ dev_err(ds->dev, "failed to allocate a bridge for port %d\n", port);
+ return ret;
+ }
+
+ br_port_cfg.bridge_id = br_alloc.bridge_id;
+ br_port_cfg.bridge_port_id = cpu_to_le16(port);
+ br_port_cfg.mask = cpu_to_le32(MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_ID |
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_PORT_MAP |
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_MAC_LEARNING |
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MAC_LEARNING);
+ br_port_cfg.src_mac_learning_disable = true;
+ br_port_cfg.vlan_src_mac_vid_enable = false;
+ br_port_cfg.vlan_dst_mac_vid_enable = false;
+ if (dp->cpu_dp)
+ br_port_cfg.bridge_port_map[0] = cpu_to_le16(BIT(dp->cpu_dp->index));
+
+ return MXL862XX_API_WRITE(ds->priv, MXL862XX_BRIDGEPORT_CONFIGSET, br_port_cfg);
+}
+
+static int mxl862xx_setup_mdio(struct dsa_switch *ds)
+{
+ struct mxl862xx_priv *priv = ds->priv;
+ struct device *dev = ds->dev;
+ struct device_node *mdio_np;
+ struct mii_bus *bus;
+ int ret;
+
+ bus = devm_mdiobus_alloc(dev);
+ if (!bus)
+ return -ENOMEM;
+
+ bus->priv = priv;
+ ds->user_mii_bus = bus;
+ bus->name = KBUILD_MODNAME "-mii";
+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
+ bus->read_c45 = mxl862xx_phy_read_c45_mii_bus;
+ bus->write_c45 = mxl862xx_phy_write_c45_mii_bus;
+ bus->read = mxl862xx_phy_read_mii_bus;
+ bus->write = mxl862xx_phy_write_mii_bus;
+ bus->parent = dev;
+ bus->phy_mask = ~ds->phys_mii_mask;
+
+ mdio_np = of_get_child_by_name(dev->of_node, "mdio");
+ if (!mdio_np)
+ return -ENODEV;
+
+ ret = devm_of_mdiobus_register(dev, bus, mdio_np);
+ of_node_put(mdio_np);
+
+ return ret;
+}
+
+static int mxl862xx_wait_ready(struct dsa_switch *ds)
+{
+ struct mxl862xx_sys_fw_image_version ver = {};
+ unsigned long start = jiffies, timeout;
+ struct mxl862xx_priv *priv = ds->priv;
+ struct mxl862xx_cfg cfg = {};
+ int ret;
+
+ timeout = start + msecs_to_jiffies(MXL862XX_READY_TIMEOUT_MS);
+ msleep(2000); /* it always takes at least 2 seconds */
+ do {
+ ret = MXL862XX_API_READ_QUIET(priv, SYS_MISC_FW_VERSION, ver);
+ if (ret || !ver.iv_major)
+ goto not_ready_yet;
+
+ /* being able to perform CFGGET indicates that
+ * the firmware is ready
+ */
+ ret = MXL862XX_API_READ_QUIET(priv,
+ MXL862XX_COMMON_CFGGET,
+ cfg);
+ if (ret)
+ goto not_ready_yet;
+
+ dev_info(ds->dev, "switch ready after %ums, firmware %u.%u.%u (build %u)\n",
+ jiffies_to_msecs(jiffies - start),
+ ver.iv_major, ver.iv_minor,
+ le16_to_cpu(ver.iv_revision),
+ le32_to_cpu(ver.iv_build_num));
+ return 0;
+
+not_ready_yet:
+ msleep(MXL862XX_READY_POLL_MS);
+ } while (time_before(jiffies, timeout));
+
+ dev_err(ds->dev, "switch not responding after reset\n");
+ return -ETIMEDOUT;
+}
+
+static int mxl862xx_setup_cpu_bridge(struct dsa_switch *ds, int port)
+{
+ struct mxl862xx_bridge_port_config br_port_cfg = {};
+ struct mxl862xx_priv *priv = ds->priv;
+ u16 bridge_port_map = 0;
+ struct dsa_port *dp;
+
+ /* CPU port bridge setup */
+ br_port_cfg.mask = cpu_to_le32(MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_PORT_MAP |
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_MAC_LEARNING |
+ MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MAC_LEARNING);
+
+ br_port_cfg.bridge_port_id = cpu_to_le16(port);
+ br_port_cfg.src_mac_learning_disable = false;
+ br_port_cfg.vlan_src_mac_vid_enable = true;
+ br_port_cfg.vlan_dst_mac_vid_enable = true;
+
+ /* include all assigned user ports in the CPU portmap */
+ dsa_switch_for_each_user_port(dp, ds) {
+ if (!dp->cpu_dp)
+ continue;
+
+ if (dp->cpu_dp->index != port)
+ continue;
+
+ bridge_port_map |= BIT(dp->index);
+ }
+ br_port_cfg.bridge_port_map[0] |= cpu_to_le16(bridge_port_map);
+
+ return MXL862XX_API_WRITE(priv, MXL862XX_BRIDGEPORT_CONFIGSET, br_port_cfg);
+}
+
+static int mxl862xx_setup(struct dsa_switch *ds)
+{
+ struct mxl862xx_priv *priv = ds->priv;
+ int ret;
+
+ ret = mxl862xx_reset(priv);
+ if (ret)
+ return ret;
+
+ ret = mxl862xx_wait_ready(ds);
+ if (ret)
+ return ret;
+
+ return mxl862xx_setup_mdio(ds);
+}
+
+static int mxl862xx_port_setup(struct dsa_switch *ds, int port)
+{
+ bool is_cpu_port = dsa_is_cpu_port(ds, port);
+ int ret;
+
+ /* disable port and flush MAC entries */
+ ret = mxl862xx_port_state(ds, port, false);
+ if (ret)
+ return ret;
+
+ mxl862xx_port_fast_age(ds, port);
+
+ /* skip setup for unused and DSA ports */
+ if (dsa_is_unused_port(ds, port) ||
+ dsa_is_dsa_port(ds, port))
+ return 0;
+
+ /* configure tag protocol */
+ ret = mxl862xx_configure_sp_tag_proto(ds, port, is_cpu_port);
+ if (ret)
+ return ret;
+
+ /* assign CTP port IDs */
+ ret = mxl862xx_configure_ctp_port(ds, port, port,
+ is_cpu_port ? 32 - port : 1);
+ if (ret)
+ return ret;
+
+ if (is_cpu_port)
+ /* assign user ports to CPU port bridge */
+ return mxl862xx_setup_cpu_bridge(ds, port);
+
+ /* setup single-port bridge for user ports */
+ return mxl862xx_add_single_port_bridge(ds, port);
+}
+
+static void mxl862xx_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+{
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 |
+ MAC_100 | MAC_1000 | MAC_2500FD;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+}
+
+static const struct dsa_switch_ops mxl862xx_switch_ops = {
+ .get_tag_protocol = mxl862xx_get_tag_protocol,
+ .setup = mxl862xx_setup,
+ .port_setup = mxl862xx_port_setup,
+ .phylink_get_caps = mxl862xx_phylink_get_caps,
+ .port_enable = mxl862xx_port_enable,
+ .port_disable = mxl862xx_port_disable,
+ .port_fast_age = mxl862xx_port_fast_age,
+};
+
+static void mxl862xx_phylink_mac_config(struct phylink_config *config,
+ unsigned int mode,
+ const struct phylink_link_state *state)
+{
+}
+
+static void mxl862xx_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+{
+}
+
+static void mxl862xx_phylink_mac_link_up(struct phylink_config *config,
+ struct phy_device *phydev,
+ unsigned int mode,
+ phy_interface_t interface,
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+{
+}
+
+static const struct phylink_mac_ops mxl862xx_phylink_mac_ops = {
+ .mac_config = mxl862xx_phylink_mac_config,
+ .mac_link_down = mxl862xx_phylink_mac_link_down,
+ .mac_link_up = mxl862xx_phylink_mac_link_up,
+};
+
+static int mxl862xx_probe(struct mdio_device *mdiodev)
+{
+ struct device *dev = &mdiodev->dev;
+ struct mxl862xx_priv *priv;
+ struct dsa_switch *ds;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mdiodev = mdiodev;
+
+ ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
+ if (!ds)
+ return -ENOMEM;
+
+ priv->ds = ds;
+ ds->dev = dev;
+ ds->priv = priv;
+ ds->ops = &mxl862xx_switch_ops;
+ ds->phylink_mac_ops = &mxl862xx_phylink_mac_ops;
+ ds->num_ports = MXL862XX_MAX_PORTS;
+
+ ret = dsa_register_switch(ds);
+ if (ret)
+ return ret;
+
+ dev_set_drvdata(dev, ds);
+
+ return 0;
+}
+
+static void mxl862xx_remove(struct mdio_device *mdiodev)
+{
+ struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
+
+ if (!ds)
+ return;
+
+ dsa_unregister_switch(ds);
+}
+
+static void mxl862xx_shutdown(struct mdio_device *mdiodev)
+{
+ struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
+
+ if (!ds)
+ return;
+
+ dsa_switch_shutdown(ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static const struct of_device_id mxl862xx_of_match[] = {
+ { .compatible = "maxlinear,mxl86282" },
+ { .compatible = "maxlinear,mxl86252" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxl862xx_of_match);
+
+static struct mdio_driver mxl862xx_driver = {
+ .probe = mxl862xx_probe,
+ .remove = mxl862xx_remove,
+ .shutdown = mxl862xx_shutdown,
+ .mdiodrv.driver = {
+ .name = "mxl862xx",
+ .of_match_table = mxl862xx_of_match,
+ },
+};
+
+mdio_module_driver(mxl862xx_driver);
+
+MODULE_DESCRIPTION("Driver for MaxLinear MxL862xx switch family");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/mxl862xx/mxl862xx.h b/drivers/net/dsa/mxl862xx/mxl862xx.h
new file mode 100644
index 000000000000..bfeb436942d5
--- /dev/null
+++ b/drivers/net/dsa/mxl862xx/mxl862xx.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MXL862XX_H
+#define __MXL862XX_H
+
+#include <linux/mdio.h>
+#include <net/dsa.h>
+
+#define MXL862XX_MAX_PORTS 17
+
+struct mxl862xx_priv {
+ struct dsa_switch *ds;
+ struct mdio_device *mdiodev;
+};
+
+#endif /* __MXL862XX_H */
--
2.52.0 | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Sun, 1 Feb 2026 02:25:13 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch with this DSA driver.
MxL862xx integrates a firmware running on an embedded processor (based on
Zephyr RTOS). Host interaction uses a simple netlink-like API transported
over MDIO/MMD.
This series includes only what's needed to pass traffic between user
ports and the CPU port: relayed MDIO to internal PHYs, basic port
enable/disable, and CPU-port special tagging.
The SerDes interface of the CPU port is automatically configured by the
switch after reset using a board-specific configuration stored together
with the firmware in the flash chip attached to the switch, so no action
is needed from the driver to setup the interface mode of the CPU port.
Also MAC settings of the PHY ports are automatically configured, which
means the driver works fine with phylink_mac_ops being all no-op stubs.
Multiple follow up series will bring support for setting up the other
SerDes PCS interface (ie. not used for the CPU port), bridge, VLAN, ...
offloading, and support for using an 802.1Q-based special tag instead of
the proprietary 8-byte tag.
---
basic DSA selftests were run, results:
* no_forwarding.sh: all tests PASS
* bridge_vlan_unaware.sh: all tests PASS
* bridge_vlan_mcast.sh: all tests PASS
* bridge_vlan_aware.sh: all tests PASS
* local_termination.sh: all tests PASS or XFAIL, except for
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
As obviously this is mostly testing the Linux software bridge at this
point so I didn't bother to run any of the FDB or MDB related tests.
Some mystery about the relationship between the sub-interface ID and CTP
port assignment remains for now, so I cannot yet fully explain the magic
numbers when calculating the two.
(Why is it neccesary to allocate 23 CTPs when using port 9 as CPU port
while there are at most 17 phyiscal interfaces in total, and only at
most 13 when using one of the two SerDes as CPU interface? Why is there
an offset of 16 when calculating the sub-interface ID? How will a total
of 17 ports be possibly represented in a 4-bit field in the tag RX
path?)
At this point this doesn't impact functionality, and I hope for further
clarification discussing all that with MaxLinear engineers.
I believe the initial driver is anyway in good shape now, a follow-up
series addressing configuring the SerDes interfaces will also have to
take care of CTP assignment and sub-interfaces to not hit the mentioned
4-bit cap in the tag driver.
Changes since v11:
Address comments reported by Jakub Kicinski using netdev-ai
https://patchwork.kernel.org/comment/26767905/
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* list switch variants in Kconfig starting with dash ('-')
* remove the __packed attribute on structs which are
naturally packed according to C rules (ie. one other struct
with only a single byte-aligned member)
* log error in mxl862xx_port_disable()
* introduce !NULL check for return value of dsa_to_port() in
mxl862xx_add_single_port_bridge
* check cpu_dp being non-NULL before dereferencing dp->cpu_dp
* use non-racy and deterministic name for MII bus
* skip ports without cpu_dp assigned in mxl862xx_setup_cpu_bridge()
to avoid potential NULL-pointer dereference
* call dev_set_drvdata() only after dsa_register_switch() has been
successfully completed
Changes since v10:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* arrange local variables in reverse xmas tree order (again)
* use MXL862_NAME as .name in struct dsa_device_ops
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix fatal last-second changes dsa_port_is_unused vs. dsa_is_unused_port
and dsa_port_is_unused vs. dsa_is_unused_port
* use cpu_to_le16 in mxl862xx_configure_ctp_port
* improve formatting of some kerneldoc comments
Changes since v9:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* add microcontroller port 0
2/4 net: dsa: add tag format for MxL862xx switches
* count ports starting from 0
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix indentation in kernel-doc
* remove misleading comment regarding sub-interface IDs
* remove unused macros, set MXL862XX_MAX_PORTS to 17
* count ports starting from 0, 0 being the microcontroller
* improve port setup:
- split tag protocol and CTP port assignment
- use ports cpu_dp instead of relying on single (ie. first) CPU port
- handle CPU port like any other port
- prepare forward DT compatibility with multiple CPU ports
Changes since v8:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* remove practically unused struct hw_info
* lots of kerneldoc improvements in mxl862xx-api.h
* drop .mac_select_pcs() stub
* better handling for firmware error return value
* apply reverse xmas tree in mxl862xx_api_wrap
* guard headers with #ifdef macro
* include net/dsa.h and linux/mdio.h in mxl862xx.h
* call mxl862xx_port_fast_age() only once in .port_setup
* don't create isolation bridges for unused ports
* replace errornous cast with correct range of values denoting firmware errors
Changes since v7
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* use little-endian in bridge_port_config API
* remove duplciate assignment of br_port_cfg.bridge_port_id when setting
up CPU port
Changes since v6
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix kerneldoc style
Changes since RFC v5
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* remove unnecessary check for skb != NULL
* merge consecutively printed warnings into single dev_warn_ratelimited
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* include bridge and bridgeport API needed to isolate ports
* remove warning in .setup as ports are now isolated
* make ready-after-reset check more robust by adding delay
* sort structs in order of struct definitions
* best effort to sort functions without introducing additional prototypes
* always use enums with kerneldoc comments in mxl862xx-api.h
* remove bogus .phy_read and .phy_write DSA ops as the driver anyway registers
a user MDIO bus with Clause-22 and Clause-45 operations
* various small style fixes
Changes since RFC v4
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* drop unused precompiler macros
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* fix indentation
4/4 net: dsa: add basic initial driver for MxL862xx switches
* output warning in .setup regarding unknown pre-configuration
* add comment explaining why CFGGET is used in reset function
Changes since RFC v3
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* remove labels from example
* remove 'bindings for' from commit title
2/4 net: dsa: add tag format for MxL862xx switches
* describe fields and variables with comments
* sub-interface is only 5 bits
* harmonize Kconfig symbol name
* maintain alphabetic order in Kconfig
* fix typo s/beginnig/beginning/
* fix typo s/swtiches/switches/
* arrange local variables in reverse xmas tree order
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* poll switch readiness after reset
* implement driver shutdown
* added port_fast_aging API call and driver op
* unified port setup in new .port_setup op
* improve comment explaining special handlign for unaligned API read
* various typos and formatting improvements
Changes since RFC v2
1/4, 2/4, 3/4: unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix return value being uninitialized on error in mxl862xx_api_wrap()
* add missing description in kerneldoc comment of
struct mxl862xx_ss_sp_tag
Changes since initial RFC
1/4 dt-bindings: net: dsa: add bindings for MaxLinear MxL862xx
* better description in dt-bindings doc
2/4 net: dsa: add tag formats for MxL862xx switches
* make sure all tag fields are initialized
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* new patch
4/4 net: dsa: add basic initial driver for MxL862xx switches
* make use of struct mdio_device
* add phylink_mac_ops stubs
* drop leftover nonsense from mxl862xx_phylink_get_caps()
* fix endian conversions
* use __le32 instead of enum types in over-the-wire structs
* use existing MDIO_* macros whenever possible
* simplify API constants to be more readable
* use readx_poll_timeout instead of open-coding poll timeout loop
* add mxl862xx_reg_read() and mxl862xx_reg_write() helpers
* demystify error codes returned by the firmware
* add #defines for mxl862xx_ss_sp_tag member values
* move reset to dedicated function, clarify magic number being the
reset command ID
Daniel Golle (4):
dt-bindings: net: dsa: add MaxLinear MxL862xx
net: dsa: add tag format for MxL862xx switches
net: mdio: add unlocked mdiodev C45 bus accessors
net: dsa: add basic initial driver for MxL862xx switches
.../bindings/net/dsa/maxlinear,mxl862xx.yaml | 160 +++++
MAINTAINERS | 8 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/mxl862xx/Kconfig | 12 +
drivers/net/dsa/mxl862xx/Makefile | 3 +
drivers/net/dsa/mxl862xx/mxl862xx-api.h | 675 ++++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 49 ++
drivers/net/dsa/mxl862xx/mxl862xx-host.c | 245 +++++++
drivers/net/dsa/mxl862xx/mxl862xx-host.h | 12 +
drivers/net/dsa/mxl862xx/mxl862xx.c | 483 +++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx.h | 16 +
include/linux/mdio.h | 13 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 7 +
net/dsa/Makefile | 1 +
net/dsa/tag_mxl862xx.c | 110 +++
17 files changed, 1799 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
create mode 100644 drivers/net/dsa/mxl862xx/Kconfig
create mode 100644 drivers/net/dsa/mxl862xx/Makefile
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-api.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.h
create mode 100644 net/dsa/tag_mxl862xx.c
--
2.52.0
| On Sun, Feb 01, 2026 at 02:25:13AM +0000, Daniel Golle wrote:
I have nothing else to comment except to request you to undo some of the
changes requested by AI review. Sorry I didn't have time to comment on v11.
I'm sorry, I can't accept code that fears its own shadow. Some people,
when they see a defensive NULL check think there is a valid reason
behind it and will try to see what that reason is.
If dsa_to_port() would have possibly returned NULL, mxl862xx_port_setup() ->
dsa_is_cpu_port(), which _is_ implemented using dsa_to_port(), would
have already crashed the kernel and this test here would have been too
little, too late.
But the kernel doesn't crash there, because calling dsa_to_port() is
safe for these arguments, and this test is simply logically inconsistent
with previous unconditional in this call path.
As per the dt-bindings patch, the "mdio" child node is not required.
But here it is.
All user ports are given a valid non-NULL dp->cpu_dp pointer. I strongly
oppose introducing FUD in the code. If there are valid reasons behind
this I'm all ears, but there aren't.
Each of dsa_is_cpu_port(), dsa_is_unused_port(), dsa_is_dsa_port() are
implemented using dsa_to_port(), and that loops over dst->ports in order
to find "dp" just to return dp->index.
OTOH if you call dsa_to_port() only once, we have dsa_port_is_cpu(),
dsa_port_is_unused(), dsa_port_is_dsa() which can be called on that and
have lower complexity. Please do that.
You do _not_ need to test whether dsa_to_port() returns NULL, if "ds"
and "port" were passed to you by DSA in the context of a DSA callback.
Any exception to this rule will be explicitly noted in the documentation.
There is no point in doing this, calling dev_set_drvdata() before and
then simply "return dsa_register_switch()" is perfectly fine. You also
won't need the "ret" variable. | {
"author": "Vladimir Oltean <olteanv@gmail.com>",
"date": "Mon, 2 Feb 2026 12:23:26 +0200",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch with this DSA driver.
MxL862xx integrates a firmware running on an embedded processor (based on
Zephyr RTOS). Host interaction uses a simple netlink-like API transported
over MDIO/MMD.
This series includes only what's needed to pass traffic between user
ports and the CPU port: relayed MDIO to internal PHYs, basic port
enable/disable, and CPU-port special tagging.
The SerDes interface of the CPU port is automatically configured by the
switch after reset using a board-specific configuration stored together
with the firmware in the flash chip attached to the switch, so no action
is needed from the driver to setup the interface mode of the CPU port.
Also MAC settings of the PHY ports are automatically configured, which
means the driver works fine with phylink_mac_ops being all no-op stubs.
Multiple follow up series will bring support for setting up the other
SerDes PCS interface (ie. not used for the CPU port), bridge, VLAN, ...
offloading, and support for using an 802.1Q-based special tag instead of
the proprietary 8-byte tag.
---
basic DSA selftests were run, results:
* no_forwarding.sh: all tests PASS
* bridge_vlan_unaware.sh: all tests PASS
* bridge_vlan_mcast.sh: all tests PASS
* bridge_vlan_aware.sh: all tests PASS
* local_termination.sh: all tests PASS or XFAIL, except for
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
As obviously this is mostly testing the Linux software bridge at this
point so I didn't bother to run any of the FDB or MDB related tests.
Some mystery about the relationship between the sub-interface ID and CTP
port assignment remains for now, so I cannot yet fully explain the magic
numbers when calculating the two.
(Why is it neccesary to allocate 23 CTPs when using port 9 as CPU port
while there are at most 17 phyiscal interfaces in total, and only at
most 13 when using one of the two SerDes as CPU interface? Why is there
an offset of 16 when calculating the sub-interface ID? How will a total
of 17 ports be possibly represented in a 4-bit field in the tag RX
path?)
At this point this doesn't impact functionality, and I hope for further
clarification discussing all that with MaxLinear engineers.
I believe the initial driver is anyway in good shape now, a follow-up
series addressing configuring the SerDes interfaces will also have to
take care of CTP assignment and sub-interfaces to not hit the mentioned
4-bit cap in the tag driver.
Changes since v11:
Address comments reported by Jakub Kicinski using netdev-ai
https://patchwork.kernel.org/comment/26767905/
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* list switch variants in Kconfig starting with dash ('-')
* remove the __packed attribute on structs which are
naturally packed according to C rules (ie. one other struct
with only a single byte-aligned member)
* log error in mxl862xx_port_disable()
* introduce !NULL check for return value of dsa_to_port() in
mxl862xx_add_single_port_bridge
* check cpu_dp being non-NULL before dereferencing dp->cpu_dp
* use non-racy and deterministic name for MII bus
* skip ports without cpu_dp assigned in mxl862xx_setup_cpu_bridge()
to avoid potential NULL-pointer dereference
* call dev_set_drvdata() only after dsa_register_switch() has been
successfully completed
Changes since v10:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* arrange local variables in reverse xmas tree order (again)
* use MXL862_NAME as .name in struct dsa_device_ops
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix fatal last-second changes dsa_port_is_unused vs. dsa_is_unused_port
and dsa_port_is_unused vs. dsa_is_unused_port
* use cpu_to_le16 in mxl862xx_configure_ctp_port
* improve formatting of some kerneldoc comments
Changes since v9:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* add microcontroller port 0
2/4 net: dsa: add tag format for MxL862xx switches
* count ports starting from 0
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix indentation in kernel-doc
* remove misleading comment regarding sub-interface IDs
* remove unused macros, set MXL862XX_MAX_PORTS to 17
* count ports starting from 0, 0 being the microcontroller
* improve port setup:
- split tag protocol and CTP port assignment
- use ports cpu_dp instead of relying on single (ie. first) CPU port
- handle CPU port like any other port
- prepare forward DT compatibility with multiple CPU ports
Changes since v8:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* remove practically unused struct hw_info
* lots of kerneldoc improvements in mxl862xx-api.h
* drop .mac_select_pcs() stub
* better handling for firmware error return value
* apply reverse xmas tree in mxl862xx_api_wrap
* guard headers with #ifdef macro
* include net/dsa.h and linux/mdio.h in mxl862xx.h
* call mxl862xx_port_fast_age() only once in .port_setup
* don't create isolation bridges for unused ports
* replace errornous cast with correct range of values denoting firmware errors
Changes since v7
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* use little-endian in bridge_port_config API
* remove duplciate assignment of br_port_cfg.bridge_port_id when setting
up CPU port
Changes since v6
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix kerneldoc style
Changes since RFC v5
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* remove unnecessary check for skb != NULL
* merge consecutively printed warnings into single dev_warn_ratelimited
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* include bridge and bridgeport API needed to isolate ports
* remove warning in .setup as ports are now isolated
* make ready-after-reset check more robust by adding delay
* sort structs in order of struct definitions
* best effort to sort functions without introducing additional prototypes
* always use enums with kerneldoc comments in mxl862xx-api.h
* remove bogus .phy_read and .phy_write DSA ops as the driver anyway registers
a user MDIO bus with Clause-22 and Clause-45 operations
* various small style fixes
Changes since RFC v4
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* drop unused precompiler macros
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* fix indentation
4/4 net: dsa: add basic initial driver for MxL862xx switches
* output warning in .setup regarding unknown pre-configuration
* add comment explaining why CFGGET is used in reset function
Changes since RFC v3
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* remove labels from example
* remove 'bindings for' from commit title
2/4 net: dsa: add tag format for MxL862xx switches
* describe fields and variables with comments
* sub-interface is only 5 bits
* harmonize Kconfig symbol name
* maintain alphabetic order in Kconfig
* fix typo s/beginnig/beginning/
* fix typo s/swtiches/switches/
* arrange local variables in reverse xmas tree order
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* poll switch readiness after reset
* implement driver shutdown
* added port_fast_aging API call and driver op
* unified port setup in new .port_setup op
* improve comment explaining special handlign for unaligned API read
* various typos and formatting improvements
Changes since RFC v2
1/4, 2/4, 3/4: unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix return value being uninitialized on error in mxl862xx_api_wrap()
* add missing description in kerneldoc comment of
struct mxl862xx_ss_sp_tag
Changes since initial RFC
1/4 dt-bindings: net: dsa: add bindings for MaxLinear MxL862xx
* better description in dt-bindings doc
2/4 net: dsa: add tag formats for MxL862xx switches
* make sure all tag fields are initialized
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* new patch
4/4 net: dsa: add basic initial driver for MxL862xx switches
* make use of struct mdio_device
* add phylink_mac_ops stubs
* drop leftover nonsense from mxl862xx_phylink_get_caps()
* fix endian conversions
* use __le32 instead of enum types in over-the-wire structs
* use existing MDIO_* macros whenever possible
* simplify API constants to be more readable
* use readx_poll_timeout instead of open-coding poll timeout loop
* add mxl862xx_reg_read() and mxl862xx_reg_write() helpers
* demystify error codes returned by the firmware
* add #defines for mxl862xx_ss_sp_tag member values
* move reset to dedicated function, clarify magic number being the
reset command ID
Daniel Golle (4):
dt-bindings: net: dsa: add MaxLinear MxL862xx
net: dsa: add tag format for MxL862xx switches
net: mdio: add unlocked mdiodev C45 bus accessors
net: dsa: add basic initial driver for MxL862xx switches
.../bindings/net/dsa/maxlinear,mxl862xx.yaml | 160 +++++
MAINTAINERS | 8 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/mxl862xx/Kconfig | 12 +
drivers/net/dsa/mxl862xx/Makefile | 3 +
drivers/net/dsa/mxl862xx/mxl862xx-api.h | 675 ++++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 49 ++
drivers/net/dsa/mxl862xx/mxl862xx-host.c | 245 +++++++
drivers/net/dsa/mxl862xx/mxl862xx-host.h | 12 +
drivers/net/dsa/mxl862xx/mxl862xx.c | 483 +++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx.h | 16 +
include/linux/mdio.h | 13 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 7 +
net/dsa/Makefile | 1 +
net/dsa/tag_mxl862xx.c | 110 +++
17 files changed, 1799 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
create mode 100644 drivers/net/dsa/mxl862xx/Kconfig
create mode 100644 drivers/net/dsa/mxl862xx/Makefile
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-api.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.h
create mode 100644 net/dsa/tag_mxl862xx.c
--
2.52.0
| On Sun, Feb 01, 2026 at 02:25:03AM +0000, Daniel Golle wrote:
Sigh, there's too many versions of this patch series. While netdev has
a 24H period, there is also this - note the last sentence. The reason
this exists is to stop this exact problem, where ongoing discussion is
split across multiple different versions of the same series.
Resending after review
~~~~~~~~~~~~~~~~~~~~~~
Allow at least 24 hours to pass between postings. This will ensure reviewers
from all geographical locations have a chance to chime in. Do not wait
too long (weeks) between postings either as it will make it harder for reviewers
to recall all the context.
Make sure you address all the feedback in your new posting. *Do not post a new
version of the code if the discussion about the previous version is still
ongoing, unless directly instructed by a reviewer.*
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last! | {
"author": "\"Russell King (Oracle)\" <linux@armlinux.org.uk>",
"date": "Mon, 2 Feb 2026 11:08:39 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch with this DSA driver.
MxL862xx integrates a firmware running on an embedded processor (based on
Zephyr RTOS). Host interaction uses a simple netlink-like API transported
over MDIO/MMD.
This series includes only what's needed to pass traffic between user
ports and the CPU port: relayed MDIO to internal PHYs, basic port
enable/disable, and CPU-port special tagging.
The SerDes interface of the CPU port is automatically configured by the
switch after reset using a board-specific configuration stored together
with the firmware in the flash chip attached to the switch, so no action
is needed from the driver to setup the interface mode of the CPU port.
Also MAC settings of the PHY ports are automatically configured, which
means the driver works fine with phylink_mac_ops being all no-op stubs.
Multiple follow up series will bring support for setting up the other
SerDes PCS interface (ie. not used for the CPU port), bridge, VLAN, ...
offloading, and support for using an 802.1Q-based special tag instead of
the proprietary 8-byte tag.
---
basic DSA selftests were run, results:
* no_forwarding.sh: all tests PASS
* bridge_vlan_unaware.sh: all tests PASS
* bridge_vlan_mcast.sh: all tests PASS
* bridge_vlan_aware.sh: all tests PASS
* local_termination.sh: all tests PASS or XFAIL, except for
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
As obviously this is mostly testing the Linux software bridge at this
point so I didn't bother to run any of the FDB or MDB related tests.
Some mystery about the relationship between the sub-interface ID and CTP
port assignment remains for now, so I cannot yet fully explain the magic
numbers when calculating the two.
(Why is it neccesary to allocate 23 CTPs when using port 9 as CPU port
while there are at most 17 phyiscal interfaces in total, and only at
most 13 when using one of the two SerDes as CPU interface? Why is there
an offset of 16 when calculating the sub-interface ID? How will a total
of 17 ports be possibly represented in a 4-bit field in the tag RX
path?)
At this point this doesn't impact functionality, and I hope for further
clarification discussing all that with MaxLinear engineers.
I believe the initial driver is anyway in good shape now, a follow-up
series addressing configuring the SerDes interfaces will also have to
take care of CTP assignment and sub-interfaces to not hit the mentioned
4-bit cap in the tag driver.
Changes since v11:
Address comments reported by Jakub Kicinski using netdev-ai
https://patchwork.kernel.org/comment/26767905/
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* list switch variants in Kconfig starting with dash ('-')
* remove the __packed attribute on structs which are
naturally packed according to C rules (ie. one other struct
with only a single byte-aligned member)
* log error in mxl862xx_port_disable()
* introduce !NULL check for return value of dsa_to_port() in
mxl862xx_add_single_port_bridge
* check cpu_dp being non-NULL before dereferencing dp->cpu_dp
* use non-racy and deterministic name for MII bus
* skip ports without cpu_dp assigned in mxl862xx_setup_cpu_bridge()
to avoid potential NULL-pointer dereference
* call dev_set_drvdata() only after dsa_register_switch() has been
successfully completed
Changes since v10:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* arrange local variables in reverse xmas tree order (again)
* use MXL862_NAME as .name in struct dsa_device_ops
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix fatal last-second changes dsa_port_is_unused vs. dsa_is_unused_port
and dsa_port_is_unused vs. dsa_is_unused_port
* use cpu_to_le16 in mxl862xx_configure_ctp_port
* improve formatting of some kerneldoc comments
Changes since v9:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* add microcontroller port 0
2/4 net: dsa: add tag format for MxL862xx switches
* count ports starting from 0
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix indentation in kernel-doc
* remove misleading comment regarding sub-interface IDs
* remove unused macros, set MXL862XX_MAX_PORTS to 17
* count ports starting from 0, 0 being the microcontroller
* improve port setup:
- split tag protocol and CTP port assignment
- use ports cpu_dp instead of relying on single (ie. first) CPU port
- handle CPU port like any other port
- prepare forward DT compatibility with multiple CPU ports
Changes since v8:
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* remove practically unused struct hw_info
* lots of kerneldoc improvements in mxl862xx-api.h
* drop .mac_select_pcs() stub
* better handling for firmware error return value
* apply reverse xmas tree in mxl862xx_api_wrap
* guard headers with #ifdef macro
* include net/dsa.h and linux/mdio.h in mxl862xx.h
* call mxl862xx_port_fast_age() only once in .port_setup
* don't create isolation bridges for unused ports
* replace errornous cast with correct range of values denoting firmware errors
Changes since v7
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* use little-endian in bridge_port_config API
* remove duplciate assignment of br_port_cfg.bridge_port_id when setting
up CPU port
Changes since v6
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* no changes
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix kerneldoc style
Changes since RFC v5
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* remove unnecessary check for skb != NULL
* merge consecutively printed warnings into single dev_warn_ratelimited
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* no changes
4/4 net: dsa: add basic initial driver for MxL862xx switches
* include bridge and bridgeport API needed to isolate ports
* remove warning in .setup as ports are now isolated
* make ready-after-reset check more robust by adding delay
* sort structs in order of struct definitions
* best effort to sort functions without introducing additional prototypes
* always use enums with kerneldoc comments in mxl862xx-api.h
* remove bogus .phy_read and .phy_write DSA ops as the driver anyway registers
a user MDIO bus with Clause-22 and Clause-45 operations
* various small style fixes
Changes since RFC v4
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* no changes
2/4 net: dsa: add tag format for MxL862xx switches
* drop unused precompiler macros
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* fix indentation
4/4 net: dsa: add basic initial driver for MxL862xx switches
* output warning in .setup regarding unknown pre-configuration
* add comment explaining why CFGGET is used in reset function
Changes since RFC v3
1/4 dt-bindings: net: dsa: add MaxLinear MxL862xx
* remove labels from example
* remove 'bindings for' from commit title
2/4 net: dsa: add tag format for MxL862xx switches
* describe fields and variables with comments
* sub-interface is only 5 bits
* harmonize Kconfig symbol name
* maintain alphabetic order in Kconfig
* fix typo s/beginnig/beginning/
* fix typo s/swtiches/switches/
* arrange local variables in reverse xmas tree order
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* poll switch readiness after reset
* implement driver shutdown
* added port_fast_aging API call and driver op
* unified port setup in new .port_setup op
* improve comment explaining special handlign for unaligned API read
* various typos and formatting improvements
Changes since RFC v2
1/4, 2/4, 3/4: unchanged
4/4 net: dsa: add basic initial driver for MxL862xx switches
* fix return value being uninitialized on error in mxl862xx_api_wrap()
* add missing description in kerneldoc comment of
struct mxl862xx_ss_sp_tag
Changes since initial RFC
1/4 dt-bindings: net: dsa: add bindings for MaxLinear MxL862xx
* better description in dt-bindings doc
2/4 net: dsa: add tag formats for MxL862xx switches
* make sure all tag fields are initialized
3/4 net: mdio: add unlocked mdiodev C45 bus accessors
* new patch
4/4 net: dsa: add basic initial driver for MxL862xx switches
* make use of struct mdio_device
* add phylink_mac_ops stubs
* drop leftover nonsense from mxl862xx_phylink_get_caps()
* fix endian conversions
* use __le32 instead of enum types in over-the-wire structs
* use existing MDIO_* macros whenever possible
* simplify API constants to be more readable
* use readx_poll_timeout instead of open-coding poll timeout loop
* add mxl862xx_reg_read() and mxl862xx_reg_write() helpers
* demystify error codes returned by the firmware
* add #defines for mxl862xx_ss_sp_tag member values
* move reset to dedicated function, clarify magic number being the
reset command ID
Daniel Golle (4):
dt-bindings: net: dsa: add MaxLinear MxL862xx
net: dsa: add tag format for MxL862xx switches
net: mdio: add unlocked mdiodev C45 bus accessors
net: dsa: add basic initial driver for MxL862xx switches
.../bindings/net/dsa/maxlinear,mxl862xx.yaml | 160 +++++
MAINTAINERS | 8 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/mxl862xx/Kconfig | 12 +
drivers/net/dsa/mxl862xx/Makefile | 3 +
drivers/net/dsa/mxl862xx/mxl862xx-api.h | 675 ++++++++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 49 ++
drivers/net/dsa/mxl862xx/mxl862xx-host.c | 245 +++++++
drivers/net/dsa/mxl862xx/mxl862xx-host.h | 12 +
drivers/net/dsa/mxl862xx/mxl862xx.c | 483 +++++++++++++
drivers/net/dsa/mxl862xx/mxl862xx.h | 16 +
include/linux/mdio.h | 13 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 7 +
net/dsa/Makefile | 1 +
net/dsa/tag_mxl862xx.c | 110 +++
17 files changed, 1799 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml
create mode 100644 drivers/net/dsa/mxl862xx/Kconfig
create mode 100644 drivers/net/dsa/mxl862xx/Makefile
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-api.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-cmd.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-host.h
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.c
create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx.h
create mode 100644 net/dsa/tag_mxl862xx.c
--
2.52.0
| On Mon, Feb 02, 2026 at 12:23:26PM +0200, Vladimir Oltean wrote:
Now that ports are counted from 0, and 0 being the microcontroller, the
port number no longer matches the PHY ID, so I suppose I got to change
the dt-bindigns as that kinda makes the mdio node mandatory for anything
to work.
Looking at other drivers I thought that, and regret not having challenged the
AI commenting on this... | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Mon, 2 Feb 2026 18:09:17 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.
The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optional and
skipped when not present in the device tree.
Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v1->v2:
Bjorn:
- Updated commit text.
- Used local variable for more readable.
---
drivers/soc/qcom/qcom-geni-se.c | 36 +++++++++++++++++----------------
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index cd1779b6a91a..b6167b968ef6 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -899,30 +899,32 @@ EXPORT_SYMBOL_GPL(geni_se_rx_dma_unprep);
int geni_icc_get(struct geni_se *se, const char *icc_ddr)
{
- int i, err;
- const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
+ struct geni_icc_path *icc_paths = se->icc_paths;
if (has_acpi_companion(se->dev))
return 0;
- for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
- if (!icc_names[i])
- continue;
-
- se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);
- if (IS_ERR(se->icc_paths[i].path))
- goto err;
+ icc_paths[GENI_TO_CORE].path = devm_of_icc_get(se->dev, "qup-core");
+ if (IS_ERR(icc_paths[GENI_TO_CORE].path))
+ return dev_err_probe(se->dev, PTR_ERR(icc_paths[GENI_TO_CORE].path),
+ "Failed to get 'qup-core' ICC path\n");
+
+ icc_paths[CPU_TO_GENI].path = devm_of_icc_get(se->dev, "qup-config");
+ if (IS_ERR(icc_paths[CPU_TO_GENI].path))
+ return dev_err_probe(se->dev, PTR_ERR(icc_paths[CPU_TO_GENI].path),
+ "Failed to get 'qup-config' ICC path\n");
+
+ /* The DDR path is optional, depending on protocol and hw capabilities */
+ icc_paths[GENI_TO_DDR].path = devm_of_icc_get(se->dev, "qup-memory");
+ if (IS_ERR(icc_paths[GENI_TO_DDR].path)) {
+ if (PTR_ERR(icc_paths[GENI_TO_DDR].path) == -ENODATA)
+ icc_paths[GENI_TO_DDR].path = NULL;
+ else
+ return dev_err_probe(se->dev, PTR_ERR(icc_paths[GENI_TO_DDR].path),
+ "Failed to get 'qup-memory' ICC path\n");
}
return 0;
-
-err:
- err = PTR_ERR(se->icc_paths[i].path);
- if (err != -EPROBE_DEFER)
- dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",
- icc_names[i], err);
- return err;
-
}
EXPORT_SYMBOL_GPL(geni_icc_get);
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:10 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.
This provides a more convenient API for drivers that need to configure
specific average bandwidth values.
Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
drivers/soc/qcom/qcom-geni-se.c | 22 ++++++++++++++++++++++
include/linux/soc/qcom/geni-se.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index b6167b968ef6..b0542f836453 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -946,6 +946,28 @@ int geni_icc_set_bw(struct geni_se *se)
}
EXPORT_SYMBOL_GPL(geni_icc_set_bw);
+/**
+ * geni_icc_set_bw_ab() - Set average bandwidth for all ICC paths and apply
+ * @se: Pointer to the concerned serial engine.
+ * @core_ab: Average bandwidth in kBps for GENI_TO_CORE path.
+ * @cfg_ab: Average bandwidth in kBps for CPU_TO_GENI path.
+ * @ddr_ab: Average bandwidth in kBps for GENI_TO_DDR path.
+ *
+ * Sets bandwidth values for all ICC paths and applies them. DDR path is
+ * optional and only set if it exists.
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 ddr_ab)
+{
+ se->icc_paths[GENI_TO_CORE].avg_bw = core_ab;
+ se->icc_paths[CPU_TO_GENI].avg_bw = cfg_ab;
+ se->icc_paths[GENI_TO_DDR].avg_bw = ddr_ab;
+
+ return geni_icc_set_bw(se);
+}
+EXPORT_SYMBOL_GPL(geni_icc_set_bw_ab);
+
void geni_icc_set_tag(struct geni_se *se, u32 tag)
{
int i;
diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h
index 0a984e2579fe..980aabea2157 100644
--- a/include/linux/soc/qcom/geni-se.h
+++ b/include/linux/soc/qcom/geni-se.h
@@ -528,6 +528,7 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
int geni_icc_get(struct geni_se *se, const char *icc_ddr);
int geni_icc_set_bw(struct geni_se *se);
+int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 ddr_ab);
void geni_icc_set_tag(struct geni_se *se, u32 tag);
int geni_icc_enable(struct geni_se *se);
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:11 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.
Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v1 -> v2:
- Updated proper return value for devm_pm_opp_set_clkname()
---
drivers/soc/qcom/qcom-geni-se.c | 47 ++++++++++++++++++++++++++++++++
include/linux/soc/qcom/geni-se.h | 6 ++++
2 files changed, 53 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index b0542f836453..75e722cd1a94 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -19,6 +19,7 @@
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
#include <linux/soc/qcom/geni-se.h>
/**
@@ -1012,6 +1013,52 @@ int geni_icc_disable(struct geni_se *se)
}
EXPORT_SYMBOL_GPL(geni_icc_disable);
+/**
+ * geni_se_resources_init() - Initialize resources for a GENI SE device.
+ * @se: Pointer to the geni_se structure representing the GENI SE device.
+ *
+ * This function initializes various resources required by the GENI Serial Engine
+ * (SE) device, including clock resources (core and SE clocks), interconnect
+ * paths for communication.
+ * It retrieves optional and mandatory clock resources, adds an OF-based
+ * operating performance point (OPP) table, and sets up interconnect paths
+ * with default bandwidths. The function also sets a flag (`has_opp`) to
+ * indicate whether OPP support is available for the device.
+ *
+ * Return: 0 on success, or a negative errno on failure.
+ */
+int geni_se_resources_init(struct geni_se *se)
+{
+ int ret;
+
+ se->core_clk = devm_clk_get_optional(se->dev, "core");
+ if (IS_ERR(se->core_clk))
+ return dev_err_probe(se->dev, PTR_ERR(se->core_clk),
+ "Failed to get optional core clk\n");
+
+ se->clk = devm_clk_get(se->dev, "se");
+ if (IS_ERR(se->clk) && !has_acpi_companion(se->dev))
+ return dev_err_probe(se->dev, PTR_ERR(se->clk),
+ "Failed to get SE clk\n");
+
+ ret = devm_pm_opp_set_clkname(se->dev, "se");
+ if (ret)
+ return ret;
+
+ ret = devm_pm_opp_of_add_table(se->dev);
+ if (ret && ret != -ENODEV)
+ return dev_err_probe(se->dev, ret, "Failed to add OPP table\n");
+
+ se->has_opp = (ret == 0);
+
+ ret = geni_icc_get(se, "qup-memory");
+ if (ret)
+ return ret;
+
+ return geni_icc_set_bw_ab(se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, GENI_DEFAULT_BW);
+}
+EXPORT_SYMBOL_GPL(geni_se_resources_init);
+
/**
* geni_find_protocol_fw() - Locate and validate SE firmware for a protocol.
* @dev: Pointer to the device structure.
diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h
index 980aabea2157..c182dd0f0bde 100644
--- a/include/linux/soc/qcom/geni-se.h
+++ b/include/linux/soc/qcom/geni-se.h
@@ -60,18 +60,22 @@ struct geni_icc_path {
* @dev: Pointer to the Serial Engine device
* @wrapper: Pointer to the parent QUP Wrapper core
* @clk: Handle to the core serial engine clock
+ * @core_clk: Auxiliary clock, which may be required by a protocol
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
* @icc_paths: Array of ICC paths for SE
+ * @has_opp: Indicates if OPP is supported
*/
struct geni_se {
void __iomem *base;
struct device *dev;
struct geni_wrapper *wrapper;
struct clk *clk;
+ struct clk *core_clk;
unsigned int num_clk_levels;
unsigned long *clk_perf_tbl;
struct geni_icc_path icc_paths[3];
+ bool has_opp;
};
/* Common SE registers */
@@ -535,6 +539,8 @@ int geni_icc_enable(struct geni_se *se);
int geni_icc_disable(struct geni_se *se);
+int geni_se_resources_init(struct geni_se *se);
+
int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol);
#endif
#endif
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:12 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.
Core clk is now properly managed alongside the other clocks (se->clk
and wrapper clocks) in the fundamental clock control functions,
eliminating the need for individual protocol drivers to handle this
clock separately.
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
drivers/soc/qcom/qcom-geni-se.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 75e722cd1a94..2e41595ff912 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -583,6 +583,7 @@ static void geni_se_clks_off(struct geni_se *se)
clk_disable_unprepare(se->clk);
clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks);
+ clk_disable_unprepare(se->core_clk);
}
/**
@@ -619,7 +620,18 @@ static int geni_se_clks_on(struct geni_se *se)
ret = clk_prepare_enable(se->clk);
if (ret)
- clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks);
+ goto err_bulk_clks;
+
+ ret = clk_prepare_enable(se->core_clk);
+ if (ret)
+ goto err_se_clk;
+
+ return 0;
+
+err_se_clk:
+ clk_disable_unprepare(se->clk);
+err_bulk_clks:
+ clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks);
return ret;
}
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:13 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.
Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactivate function disables resources in reverse order
including OPP rate reset, clocks, ICC and TLMM.
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v3 -> v4
Konrad
- Removed core clk.
v2 -> v3
- Added export symbol for new APIs.
v1 -> v2
Bjorn
- Updated commit message based code changes.
- Removed geni_se_resource_state() API.
- Utilized code snippet from geni_se_resources_off()
---
drivers/soc/qcom/qcom-geni-se.c | 67 ++++++++++++++++++++++++++++++++
include/linux/soc/qcom/geni-se.h | 4 ++
2 files changed, 71 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 2e41595ff912..17ab5bbeb621 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -1025,6 +1025,73 @@ int geni_icc_disable(struct geni_se *se)
}
EXPORT_SYMBOL_GPL(geni_icc_disable);
+/**
+ * geni_se_resources_deactivate() - Deactivate GENI SE device resources
+ * @se: Pointer to the geni_se structure
+ *
+ * Deactivates device resources for power saving: OPP rate to 0, pin control
+ * to sleep state, turns off clocks, and disables interconnect. Skips ACPI devices.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int geni_se_resources_deactivate(struct geni_se *se)
+{
+ int ret;
+
+ if (has_acpi_companion(se->dev))
+ return 0;
+
+ if (se->has_opp)
+ dev_pm_opp_set_rate(se->dev, 0);
+
+ ret = pinctrl_pm_select_sleep_state(se->dev);
+ if (ret)
+ return ret;
+
+ geni_se_clks_off(se);
+
+ return geni_icc_disable(se);
+}
+EXPORT_SYMBOL_GPL(geni_se_resources_deactivate);
+
+/**
+ * geni_se_resources_activate() - Activate GENI SE device resources
+ * @se: Pointer to the geni_se structure
+ *
+ * Activates device resources for operation: enables interconnect, prepares clocks,
+ * and sets pin control to default state. Includes error cleanup. Skips ACPI devices.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int geni_se_resources_activate(struct geni_se *se)
+{
+ int ret;
+
+ if (has_acpi_companion(se->dev))
+ return 0;
+
+ ret = geni_icc_enable(se);
+ if (ret)
+ return ret;
+
+ ret = geni_se_clks_on(se);
+ if (ret)
+ goto out_icc_disable;
+
+ ret = pinctrl_pm_select_default_state(se->dev);
+ if (ret) {
+ geni_se_clks_off(se);
+ goto out_icc_disable;
+ }
+
+ return ret;
+
+out_icc_disable:
+ geni_icc_disable(se);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(geni_se_resources_activate);
+
/**
* geni_se_resources_init() - Initialize resources for a GENI SE device.
* @se: Pointer to the geni_se structure representing the GENI SE device.
diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h
index c182dd0f0bde..36a68149345c 100644
--- a/include/linux/soc/qcom/geni-se.h
+++ b/include/linux/soc/qcom/geni-se.h
@@ -541,6 +541,10 @@ int geni_icc_disable(struct geni_se *se);
int geni_se_resources_init(struct geni_se *se);
+int geni_se_resources_activate(struct geni_se *se);
+
+int geni_se_resources_deactivate(struct geni_se *se);
+
int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol);
#endif
#endif
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:14 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle
the attachment of power domains. This often leads to duplicated code
logic across different driver probe functions.
Introduce a new helper API, geni_se_domain_attach(), to centralize
the logic for attaching "power" and "perf" domains to the GENI SE
device.
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v3->v4
Konrad
- Updated function documentation
---
drivers/soc/qcom/qcom-geni-se.c | 29 +++++++++++++++++++++++++++++
include/linux/soc/qcom/geni-se.h | 4 ++++
2 files changed, 33 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 17ab5bbeb621..d80ae6c36582 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -19,6 +19,7 @@
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
#include <linux/pm_opp.h>
#include <linux/soc/qcom/geni-se.h>
@@ -1092,6 +1093,34 @@ int geni_se_resources_activate(struct geni_se *se)
}
EXPORT_SYMBOL_GPL(geni_se_resources_activate);
+/**
+ * geni_se_domain_attach() - Attach power domains to a GENI SE device.
+ * @se: Pointer to the geni_se structure representing the GENI SE device.
+ *
+ * This function attaches the power domains ("power" and "perf") required
+ * in the SCMI auto-VM environment to the GENI Serial Engine device. It
+ * initializes se->pd_list with the attached domains.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int geni_se_domain_attach(struct geni_se *se)
+{
+ struct dev_pm_domain_attach_data pd_data = {
+ .pd_flags = PD_FLAG_DEV_LINK_ON,
+ .pd_names = (const char*[]) { "power", "perf" },
+ .num_pd_names = 2,
+ };
+ int ret;
+
+ ret = dev_pm_domain_attach_list(se->dev,
+ &pd_data, &se->pd_list);
+ if (ret <= 0)
+ return -EINVAL;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(geni_se_domain_attach);
+
/**
* geni_se_resources_init() - Initialize resources for a GENI SE device.
* @se: Pointer to the geni_se structure representing the GENI SE device.
diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h
index 36a68149345c..5f75159c5531 100644
--- a/include/linux/soc/qcom/geni-se.h
+++ b/include/linux/soc/qcom/geni-se.h
@@ -64,6 +64,7 @@ struct geni_icc_path {
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
* @icc_paths: Array of ICC paths for SE
+ * @pd_list: Power domain list for managing power domains
* @has_opp: Indicates if OPP is supported
*/
struct geni_se {
@@ -75,6 +76,7 @@ struct geni_se {
unsigned int num_clk_levels;
unsigned long *clk_perf_tbl;
struct geni_icc_path icc_paths[3];
+ struct dev_pm_domain_list *pd_list;
bool has_opp;
};
@@ -546,5 +548,7 @@ int geni_se_resources_activate(struct geni_se *se);
int geni_se_resources_deactivate(struct geni_se *se);
int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol);
+
+int geni_se_domain_attach(struct geni_se *se);
#endif
#endif
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:15 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently
manage performance levels and operating points directly. This resulting
in code duplication across drivers. such as configuring a specific level
or find and apply an OPP based on a clock frequency.
Introduce two new helper APIs, geni_se_set_perf_level() and
geni_se_set_perf_opp(), addresses this issue by providing a streamlined
method for the GENI Serial Engine (SE) drivers to find and set the OPP
based on the desired performance level, thereby eliminating redundancy.
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
drivers/soc/qcom/qcom-geni-se.c | 50 ++++++++++++++++++++++++++++++++
include/linux/soc/qcom/geni-se.h | 4 +++
2 files changed, 54 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index d80ae6c36582..2241d1487031 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -282,6 +282,12 @@ struct se_fw_hdr {
#define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr)
#define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr)
+enum domain_idx {
+ DOMAIN_IDX_POWER,
+ DOMAIN_IDX_PERF,
+ DOMAIN_IDX_MAX
+};
+
/**
* geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
* @se: Pointer to the corresponding serial engine.
@@ -1093,6 +1099,50 @@ int geni_se_resources_activate(struct geni_se *se)
}
EXPORT_SYMBOL_GPL(geni_se_resources_activate);
+/**
+ * geni_se_set_perf_level() - Set performance level for GENI SE.
+ * @se: Pointer to the struct geni_se instance.
+ * @level: The desired performance level.
+ *
+ * Sets the performance level by directly calling dev_pm_opp_set_level
+ * on the performance device associated with the SE.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int geni_se_set_perf_level(struct geni_se *se, unsigned long level)
+{
+ return dev_pm_opp_set_level(se->pd_list->pd_devs[DOMAIN_IDX_PERF], level);
+}
+EXPORT_SYMBOL_GPL(geni_se_set_perf_level);
+
+/**
+ * geni_se_set_perf_opp() - Set performance OPP for GENI SE by frequency.
+ * @se: Pointer to the struct geni_se instance.
+ * @clk_freq: The requested clock frequency.
+ *
+ * Finds the nearest operating performance point (OPP) for the given
+ * clock frequency and applies it to the SE's performance device.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq)
+{
+ struct device *perf_dev = se->pd_list->pd_devs[DOMAIN_IDX_PERF];
+ struct dev_pm_opp *opp;
+ int ret;
+
+ opp = dev_pm_opp_find_freq_floor(perf_dev, &clk_freq);
+ if (IS_ERR(opp)) {
+ dev_err(se->dev, "failed to find opp for freq %lu\n", clk_freq);
+ return PTR_ERR(opp);
+ }
+
+ ret = dev_pm_opp_set_opp(perf_dev, opp);
+ dev_pm_opp_put(opp);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(geni_se_set_perf_opp);
+
/**
* geni_se_domain_attach() - Attach power domains to a GENI SE device.
* @se: Pointer to the geni_se structure representing the GENI SE device.
diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h
index 5f75159c5531..c5e6ab85df09 100644
--- a/include/linux/soc/qcom/geni-se.h
+++ b/include/linux/soc/qcom/geni-se.h
@@ -550,5 +550,9 @@ int geni_se_resources_deactivate(struct geni_se *se);
int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol);
int geni_se_domain_attach(struct geni_se *se);
+
+int geni_se_set_perf_level(struct geni_se *se, unsigned long level);
+
+int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq);
#endif
#endif
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:16 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| Add DT bindings for the QUP GENI I2C controller on sa8255p platforms.
SA8255p platform abstracts resources such as clocks, interconnect and
GPIO pins configuration in Firmware. SCMI power and perf protocol
are utilized to request resource configurations.
SA8255p platform does not require the Serial Engine (SE) common properties
as the SE firmware is loaded and managed by the TrustZone (TZ) secure
environment.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Co-developed-by: Nikunj Kela <quic_nkela@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v2->v3:
- Added Reviewed-by tag
v1->v2:
Krzysztof:
- Added dma properties in example node
- Removed minItems from power-domains property
- Added in commit text about common property
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml b/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
new file mode 100644
index 000000000000..a61e40b5cbc1
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/qcom,sa8255p-geni-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SA8255p QUP GENI I2C Controller
+
+maintainers:
+ - Praveen Talari <praveen.talari@oss.qualcomm.com>
+
+properties:
+ compatible:
+ const: qcom,sa8255p-geni-i2c
+
+ reg:
+ maxItems: 1
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 2
+
+ power-domain-names:
+ items:
+ - const: power
+ - const: perf
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/dma/qcom-gpi.h>
+
+ i2c@a90000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ reg = <0xa90000 0x4000>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>;
+ power-domain-names = "power", "perf";
+ };
+...
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:17 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| Moving the serial engine setup to geni_i2c_init() API for a cleaner
probe function and utilizes the PM runtime API to control resources
instead of direct clock-related APIs for better resource management.
Enables reusability of the serial engine initialization like
hibernation and deep sleep features where hardware context is lost.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v3->v4:
viken:
- Added Acked-by tag
- Removed extra space before invoke of geni_i2c_init().
v1->v2:
Bjorn:
- Updated commit text.
---
drivers/i2c/busses/i2c-qcom-geni.c | 158 ++++++++++++++---------------
1 file changed, 75 insertions(+), 83 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index ae609bdd2ec4..81ed1596ac9f 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -977,10 +977,77 @@ static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
return ret;
}
+static int geni_i2c_init(struct geni_i2c_dev *gi2c)
+{
+ const struct geni_i2c_desc *desc = NULL;
+ u32 proto, tx_depth;
+ bool fifo_disable;
+ int ret;
+
+ ret = pm_runtime_resume_and_get(gi2c->se.dev);
+ if (ret < 0) {
+ dev_err(gi2c->se.dev, "error turning on device :%d\n", ret);
+ return ret;
+ }
+
+ proto = geni_se_read_proto(&gi2c->se);
+ if (proto == GENI_SE_INVALID_PROTO) {
+ ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C);
+ if (ret) {
+ dev_err_probe(gi2c->se.dev, ret, "i2c firmware load failed ret: %d\n", ret);
+ goto err;
+ }
+ } else if (proto != GENI_SE_I2C) {
+ ret = dev_err_probe(gi2c->se.dev, -ENXIO, "Invalid proto %d\n", proto);
+ goto err;
+ }
+
+ desc = device_get_match_data(gi2c->se.dev);
+ if (desc && desc->no_dma_support) {
+ fifo_disable = false;
+ gi2c->no_dma = true;
+ } else {
+ fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
+ }
+
+ if (fifo_disable) {
+ /* FIFO is disabled, so we can only use GPI DMA */
+ gi2c->gpi_mode = true;
+ ret = setup_gpi_dma(gi2c);
+ if (ret)
+ goto err;
+
+ dev_dbg(gi2c->se.dev, "Using GPI DMA mode for I2C\n");
+ } else {
+ gi2c->gpi_mode = false;
+ tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
+
+ /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */
+ if (!tx_depth && desc)
+ tx_depth = desc->tx_fifo_depth;
+
+ if (!tx_depth) {
+ ret = dev_err_probe(gi2c->se.dev, -EINVAL,
+ "Invalid TX FIFO depth\n");
+ goto err;
+ }
+
+ gi2c->tx_wm = tx_depth - 1;
+ geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
+ geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
+ PACKING_BYTES_PW, true, true, true);
+
+ dev_dbg(gi2c->se.dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
+ }
+
+err:
+ pm_runtime_put(gi2c->se.dev);
+ return ret;
+}
+
static int geni_i2c_probe(struct platform_device *pdev)
{
struct geni_i2c_dev *gi2c;
- u32 proto, tx_depth, fifo_disable;
int ret;
struct device *dev = &pdev->dev;
const struct geni_i2c_desc *desc = NULL;
@@ -1060,102 +1127,27 @@ static int geni_i2c_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_prepare_enable(gi2c->core_clk);
- if (ret)
- return ret;
-
- ret = geni_se_resources_on(&gi2c->se);
- if (ret) {
- dev_err_probe(dev, ret, "Error turning on resources\n");
- goto err_clk;
- }
- proto = geni_se_read_proto(&gi2c->se);
- if (proto == GENI_SE_INVALID_PROTO) {
- ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C);
- if (ret) {
- dev_err_probe(dev, ret, "i2c firmware load failed ret: %d\n", ret);
- goto err_resources;
- }
- } else if (proto != GENI_SE_I2C) {
- ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto);
- goto err_resources;
- }
-
- if (desc && desc->no_dma_support) {
- fifo_disable = false;
- gi2c->no_dma = true;
- } else {
- fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
- }
-
- if (fifo_disable) {
- /* FIFO is disabled, so we can only use GPI DMA */
- gi2c->gpi_mode = true;
- ret = setup_gpi_dma(gi2c);
- if (ret)
- goto err_resources;
-
- dev_dbg(dev, "Using GPI DMA mode for I2C\n");
- } else {
- gi2c->gpi_mode = false;
- tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
-
- /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */
- if (!tx_depth && desc)
- tx_depth = desc->tx_fifo_depth;
-
- if (!tx_depth) {
- ret = dev_err_probe(dev, -EINVAL,
- "Invalid TX FIFO depth\n");
- goto err_resources;
- }
-
- gi2c->tx_wm = tx_depth - 1;
- geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
- geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
- PACKING_BYTES_PW, true, true, true);
-
- dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
- }
-
- clk_disable_unprepare(gi2c->core_clk);
- ret = geni_se_resources_off(&gi2c->se);
- if (ret) {
- dev_err_probe(dev, ret, "Error turning off resources\n");
- goto err_dma;
- }
-
- ret = geni_icc_disable(&gi2c->se);
- if (ret)
- goto err_dma;
-
gi2c->suspended = 1;
pm_runtime_set_suspended(gi2c->se.dev);
pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
pm_runtime_use_autosuspend(gi2c->se.dev);
pm_runtime_enable(gi2c->se.dev);
+ ret = geni_i2c_init(gi2c);
+ if (ret < 0) {
+ pm_runtime_disable(gi2c->se.dev);
+ return ret;
+ }
+
ret = i2c_add_adapter(&gi2c->adap);
if (ret) {
dev_err_probe(dev, ret, "Error adding i2c adapter\n");
pm_runtime_disable(gi2c->se.dev);
- goto err_dma;
+ return ret;
}
dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
- return ret;
-
-err_resources:
- geni_se_resources_off(&gi2c->se);
-err_clk:
- clk_disable_unprepare(gi2c->core_clk);
-
- return ret;
-
-err_dma:
- release_gpi_dma(gi2c);
-
return ret;
}
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:18 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| Refactor the resource initialization in geni_i2c_probe() by introducing
a new geni_i2c_resources_init() function and utilizing the common
geni_se_resources_init() framework and clock frequency mapping, making the
probe function cleaner.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v3->v4:
- Added Acked-by tag.
v1->v2:
- Updated commit text.
---
drivers/i2c/busses/i2c-qcom-geni.c | 53 ++++++++++++------------------
1 file changed, 21 insertions(+), 32 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 81ed1596ac9f..56eebefda75f 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -1045,6 +1045,23 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c)
return ret;
}
+static int geni_i2c_resources_init(struct geni_i2c_dev *gi2c)
+{
+ int ret;
+
+ ret = geni_se_resources_init(&gi2c->se);
+ if (ret)
+ return ret;
+
+ ret = geni_i2c_clk_map_idx(gi2c);
+ if (ret)
+ return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n",
+ gi2c->clk_freq_out);
+
+ return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW,
+ Bps_to_icc(gi2c->clk_freq_out));
+}
+
static int geni_i2c_probe(struct platform_device *pdev)
{
struct geni_i2c_dev *gi2c;
@@ -1064,16 +1081,6 @@ static int geni_i2c_probe(struct platform_device *pdev)
desc = device_get_match_data(&pdev->dev);
- if (desc && desc->has_core_clk) {
- gi2c->core_clk = devm_clk_get(dev, "core");
- if (IS_ERR(gi2c->core_clk))
- return PTR_ERR(gi2c->core_clk);
- }
-
- gi2c->se.clk = devm_clk_get(dev, "se");
- if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
- return PTR_ERR(gi2c->se.clk);
-
ret = device_property_read_u32(dev, "clock-frequency",
&gi2c->clk_freq_out);
if (ret) {
@@ -1088,16 +1095,15 @@ static int geni_i2c_probe(struct platform_device *pdev)
if (gi2c->irq < 0)
return gi2c->irq;
- ret = geni_i2c_clk_map_idx(gi2c);
- if (ret)
- return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n",
- gi2c->clk_freq_out);
-
gi2c->adap.algo = &geni_i2c_algo;
init_completion(&gi2c->done);
spin_lock_init(&gi2c->lock);
platform_set_drvdata(pdev, gi2c);
+ ret = geni_i2c_resources_init(gi2c);
+ if (ret)
+ return ret;
+
/* Keep interrupts disabled initially to allow for low-power modes */
ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN,
dev_name(dev), gi2c);
@@ -1110,23 +1116,6 @@ static int geni_i2c_probe(struct platform_device *pdev)
gi2c->adap.dev.of_node = dev->of_node;
strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
- ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory");
- if (ret)
- return ret;
- /*
- * Set the bus quota for core and cpu to a reasonable value for
- * register access.
- * Set quota for DDR based on bus speed.
- */
- gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
- gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
- if (!desc || desc->icc_ddr)
- gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
-
- ret = geni_icc_set_bw(&gi2c->se);
- if (ret)
- return ret;
-
gi2c->suspended = 1;
pm_runtime_set_suspended(gi2c->se.dev);
pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:19 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| To manage GENI serial engine resources during runtime power management,
drivers currently need to call functions for ICC, clock, and
SE resource operations in both suspend and resume paths, resulting in
code duplication across drivers.
The new geni_se_resources_activate() and geni_se_resources_deactivate()
helper APIs addresses this issue by providing a streamlined method to
enable or disable all resources based, thereby eliminating redundancy
across drivers.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v3->v4:
- Added Acked-by tag.
v1->v2:
Bjorn:
- Remove geni_se_resources_state() API.
- Used geni_se_resources_activate() and geni_se_resources_deactivate()
to enable/disable resources.
---
drivers/i2c/busses/i2c-qcom-geni.c | 28 +++++-----------------------
1 file changed, 5 insertions(+), 23 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 56eebefda75f..4ff84bb0fff5 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -1163,18 +1163,15 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
disable_irq(gi2c->irq);
- ret = geni_se_resources_off(&gi2c->se);
+
+ ret = geni_se_resources_deactivate(&gi2c->se);
if (ret) {
enable_irq(gi2c->irq);
return ret;
-
- } else {
- gi2c->suspended = 1;
}
- clk_disable_unprepare(gi2c->core_clk);
-
- return geni_icc_disable(&gi2c->se);
+ gi2c->suspended = 1;
+ return ret;
}
static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
@@ -1182,28 +1179,13 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
int ret;
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
- ret = geni_icc_enable(&gi2c->se);
+ ret = geni_se_resources_activate(&gi2c->se);
if (ret)
return ret;
- ret = clk_prepare_enable(gi2c->core_clk);
- if (ret)
- goto out_icc_disable;
-
- ret = geni_se_resources_on(&gi2c->se);
- if (ret)
- goto out_clk_disable;
-
enable_irq(gi2c->irq);
gi2c->suspended = 0;
- return 0;
-
-out_clk_disable:
- clk_disable_unprepare(gi2c->core_clk);
-out_icc_disable:
- geni_icc_disable(&gi2c->se);
-
return ret;
}
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:20 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| To avoid repeatedly fetching and checking platform data across various
functions, store the struct of_device_id data directly in the i2c
private structure. This change enhances code maintainability and reduces
redundancy.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v3->v4
- Added Acked-by tag.
Konrad
- Removed icc_ddr from platfrom data struct
---
drivers/i2c/busses/i2c-qcom-geni.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 4ff84bb0fff5..8fd62d659c2a 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -77,6 +77,12 @@ enum geni_i2c_err_code {
#define XFER_TIMEOUT HZ
#define RST_TIMEOUT HZ
+struct geni_i2c_desc {
+ bool has_core_clk;
+ bool no_dma_support;
+ unsigned int tx_fifo_depth;
+};
+
#define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2
/**
@@ -122,13 +128,7 @@ struct geni_i2c_dev {
bool is_tx_multi_desc_xfer;
u32 num_msgs;
struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config;
-};
-
-struct geni_i2c_desc {
- bool has_core_clk;
- char *icc_ddr;
- bool no_dma_support;
- unsigned int tx_fifo_depth;
+ const struct geni_i2c_desc *dev_data;
};
struct geni_i2c_err_log {
@@ -979,7 +979,6 @@ static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
static int geni_i2c_init(struct geni_i2c_dev *gi2c)
{
- const struct geni_i2c_desc *desc = NULL;
u32 proto, tx_depth;
bool fifo_disable;
int ret;
@@ -1002,8 +1001,7 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c)
goto err;
}
- desc = device_get_match_data(gi2c->se.dev);
- if (desc && desc->no_dma_support) {
+ if (gi2c->dev_data->no_dma_support) {
fifo_disable = false;
gi2c->no_dma = true;
} else {
@@ -1023,8 +1021,8 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c)
tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
/* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */
- if (!tx_depth && desc)
- tx_depth = desc->tx_fifo_depth;
+ if (!tx_depth && gi2c->dev_data->has_core_clk)
+ tx_depth = gi2c->dev_data->tx_fifo_depth;
if (!tx_depth) {
ret = dev_err_probe(gi2c->se.dev, -EINVAL,
@@ -1067,7 +1065,6 @@ static int geni_i2c_probe(struct platform_device *pdev)
struct geni_i2c_dev *gi2c;
int ret;
struct device *dev = &pdev->dev;
- const struct geni_i2c_desc *desc = NULL;
gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
if (!gi2c)
@@ -1079,7 +1076,7 @@ static int geni_i2c_probe(struct platform_device *pdev)
if (IS_ERR(gi2c->se.base))
return PTR_ERR(gi2c->se.base);
- desc = device_get_match_data(&pdev->dev);
+ gi2c->dev_data = device_get_match_data(&pdev->dev);
ret = device_property_read_u32(dev, "clock-frequency",
&gi2c->clk_freq_out);
@@ -1218,15 +1215,16 @@ static const struct dev_pm_ops geni_i2c_pm_ops = {
NULL)
};
+static const struct geni_i2c_desc geni_i2c = {};
+
static const struct geni_i2c_desc i2c_master_hub = {
.has_core_clk = true,
- .icc_ddr = NULL,
.no_dma_support = true,
.tx_fifo_depth = 16,
};
static const struct of_device_id geni_i2c_dt_match[] = {
- { .compatible = "qcom,geni-i2c" },
+ { .compatible = "qcom,geni-i2c", .data = &geni_i2c },
{ .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub },
{}
};
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:21 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power states(on/off).
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Praveen Talari (13):
soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC
path optional
soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
soc: qcom: geni-se: Introduce helper API for resource initialization
soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and
geni_se_clks_on()
soc: qcom: geni-se: Add resources activation/deactivation helpers
soc: qcom: geni-se: Introduce helper API for attaching power domains
soc: qcom: geni-se: Introduce helper APIs for performance control
dt-bindings: i2c: Describe SA8255p
i2c: qcom-geni: Isolate serial engine setup
i2c: qcom-geni: Move resource initialization to separate function
i2c: qcom-geni: Use resources helper APIs in runtime PM functions
i2c: qcom-geni: Store of_device_id data in driver private struct
i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms
---
v3->v4
- Added a new patch(4/13) to handle core clk as part of
geni_se_clks_off/on().
---
.../bindings/i2c/qcom,sa8255p-geni-i2c.yaml | 64 ++++
drivers/i2c/busses/i2c-qcom-geni.c | 303 +++++++++---------
drivers/soc/qcom/qcom-geni-se.c | 265 +++++++++++++--
include/linux/soc/qcom/geni-se.h | 19 ++
4 files changed, 476 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml
base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d
--
2.34.1
| The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs,
such as resume/suspend, to control power on/off.
The SCMI performance protocol manages I2C frequency, with each
frequency rate represented by a performance level. The driver uses
geni_se_set_perf_opp() API to request the desired frequency rate..
As part of geni_se_set_perf_opp(), the OPP for the requested frequency
is obtained using dev_pm_opp_find_freq_floor() and the performance
level is set using dev_pm_opp_set_opp().
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
---
v3->v4:
- Added Acked-by tag.
V1->v2:
- Initialized ret to "0" in resume/suspend callbacks.
Bjorn:
- Used seperate APIs for the resouces enable/disable.
---
drivers/i2c/busses/i2c-qcom-geni.c | 56 ++++++++++++++++++++++--------
1 file changed, 42 insertions(+), 14 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 8fd62d659c2a..2ad31e412b96 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -81,6 +81,10 @@ struct geni_i2c_desc {
bool has_core_clk;
bool no_dma_support;
unsigned int tx_fifo_depth;
+ int (*resources_init)(struct geni_se *se);
+ int (*set_rate)(struct geni_se *se, unsigned long freq);
+ int (*power_on)(struct geni_se *se);
+ int (*power_off)(struct geni_se *se);
};
#define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2
@@ -203,8 +207,9 @@ static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
return -EINVAL;
}
-static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
+static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq)
{
+ struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev);
const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
u32 val;
@@ -217,6 +222,7 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
val |= itr->t_cycle_cnt;
writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
+ return 0;
}
static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
@@ -908,7 +914,9 @@ static int geni_i2c_xfer(struct i2c_adapter *adap,
return ret;
}
- qcom_geni_i2c_conf(gi2c);
+ ret = gi2c->dev_data->set_rate(&gi2c->se, gi2c->clk_freq_out);
+ if (ret)
+ return ret;
if (gi2c->gpi_mode)
ret = geni_i2c_gpi_xfer(gi2c, msgs, num);
@@ -1043,8 +1051,9 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c)
return ret;
}
-static int geni_i2c_resources_init(struct geni_i2c_dev *gi2c)
+static int geni_i2c_resources_init(struct geni_se *se)
{
+ struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev);
int ret;
ret = geni_se_resources_init(&gi2c->se);
@@ -1097,7 +1106,7 @@ static int geni_i2c_probe(struct platform_device *pdev)
spin_lock_init(&gi2c->lock);
platform_set_drvdata(pdev, gi2c);
- ret = geni_i2c_resources_init(gi2c);
+ ret = gi2c->dev_data->resources_init(&gi2c->se);
if (ret)
return ret;
@@ -1156,15 +1165,17 @@ static void geni_i2c_shutdown(struct platform_device *pdev)
static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
{
- int ret;
+ int ret = 0;
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
disable_irq(gi2c->irq);
- ret = geni_se_resources_deactivate(&gi2c->se);
- if (ret) {
- enable_irq(gi2c->irq);
- return ret;
+ if (gi2c->dev_data->power_off) {
+ ret = gi2c->dev_data->power_off(&gi2c->se);
+ if (ret) {
+ enable_irq(gi2c->irq);
+ return ret;
+ }
}
gi2c->suspended = 1;
@@ -1173,12 +1184,14 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
{
- int ret;
+ int ret = 0;
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
- ret = geni_se_resources_activate(&gi2c->se);
- if (ret)
- return ret;
+ if (gi2c->dev_data->power_on) {
+ ret = gi2c->dev_data->power_on(&gi2c->se);
+ if (ret)
+ return ret;
+ }
enable_irq(gi2c->irq);
gi2c->suspended = 0;
@@ -1215,17 +1228,32 @@ static const struct dev_pm_ops geni_i2c_pm_ops = {
NULL)
};
-static const struct geni_i2c_desc geni_i2c = {};
+static const struct geni_i2c_desc geni_i2c = {
+ .resources_init = geni_i2c_resources_init,
+ .set_rate = qcom_geni_i2c_conf,
+ .power_on = geni_se_resources_activate,
+ .power_off = geni_se_resources_deactivate,
+};
static const struct geni_i2c_desc i2c_master_hub = {
.has_core_clk = true,
.no_dma_support = true,
.tx_fifo_depth = 16,
+ .resources_init = geni_i2c_resources_init,
+ .set_rate = qcom_geni_i2c_conf,
+ .power_on = geni_se_resources_activate,
+ .power_off = geni_se_resources_deactivate,
+};
+
+static const struct geni_i2c_desc sa8255p_geni_i2c = {
+ .resources_init = geni_se_domain_attach,
+ .set_rate = geni_se_set_perf_opp,
};
static const struct of_device_id geni_i2c_dt_match[] = {
{ .compatible = "qcom,geni-i2c", .data = &geni_i2c },
{ .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub },
+ { .compatible = "qcom,sa8255p-geni-i2c", .data = &sa8255p_geni_i2c },
{}
};
MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
--
2.34.1 | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:22 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical address
0xfbd59c0000000020
KASAN: maybe wild-memory-access in range
[0xdead000000000100-0xdead000000000107]
RIP: 0010:__do_sys_swapoff+0x1151/0x1860
RBP: dead0000000000f8
R13: dead000000000100
The crash occurs when free_swap_count_continuations() iterates over a
list_head containing LIST_POISON values from a previous list_del().
== Root Cause ==
The swap subsystem uses vmalloc_to_page() to get struct page pointers for
the swap_map array, then uses page->private and page->lru for swap count
continuation lists.
When vmalloc allocates high-order pages without __GFP_COMP and splits them
via split_page(), the resulting pages may contain stale data:
1. post_alloc_hook() only clears page->private for the head page (page[0])
2. split_page() only calls set_page_refcounted() for tail pages
3. Tail pages retain whatever was in page->private and page->lru from
previous use - including LIST_POISON values from prior list_del() calls
In add_swap_count_continuation() (mm/swapfile.c):
if (!page_private(head)) {
INIT_LIST_HEAD(&head->lru);
set_page_private(head, SWP_CONTINUED);
}
If head is a vmalloc tail page with stale non-zero page->private, the
INIT_LIST_HEAD is skipped, leaving page->lru with poison values. When
free_swap_count_continuations() later iterates this list, it crashes.
The comment at line 3862 says "Page allocation does not initialize the
page's lru field, but it does always reset its private field" - this
assumption is incorrect for vmalloc pages obtained via split_page().
== Proposed Fix ==
Initialize page->private and page->lru for all pages in split_page().
This matches the documented expectation in mm/vmalloc.c:
"High-order allocations must be able to be treated as independent
small pages by callers... Some drivers do their own refcounting
on vmalloc_to_page() pages, some use page->mapping, page->lru, etc."
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,6 +3122,16 @@ void split_page(struct page *page, unsigned int order)
VM_BUG_ON_PAGE(PageCompound(page), page);
VM_BUG_ON_PAGE(!page_count(page), page);
+ /*
+ * Split pages may contain stale data from previous use. Initialize
+ * page->private and page->lru which may have LIST_POISON values.
+ */
+ INIT_LIST_HEAD(&page->lru);
+ for (i = 1; i < (1 << order); i++) {
+ set_page_private(page + i, 0);
+ INIT_LIST_HEAD(&page[i].lru);
+ }
+
for (i = 1; i < (1 << order); i++)
set_page_refcounted(page + i);
split_page_owner(page, order, 0);
== Testing ==
Reproduced with a stress test cycling swapon/swapoff on 8GB zram under
memory pressure:
- Without patch: crash within ~50 iterations
- With patch: 1154+ iterations, no crash
The bug was originally discovered on Fedora 44 with kernel 6.19.0-rc7
during normal system shutdown after extended use.
== Questions ==
1. Is split_page() the right place for this fix, or should the swap code
be more defensive about uninitialized vmalloc pages?
2. Should prep_new_page()/post_alloc_hook() initialize all pages in
high-order allocations, not just the head?
3. Are there other fields besides page->private and page->lru that
callers of split_page() might expect to be initialized?
Thoughts?
--
Best Regards,
Mike Gavrilov.
| On Fri, Jan 30, 2026 at 06:49:00PM +0500, Mikhail Gavrilov wrote:
Why add a second loop instead of using the existing one? | {
"author": "Matthew Wilcox <willy@infradead.org>",
"date": "Fri, 30 Jan 2026 13:59:47 +0000",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical address
0xfbd59c0000000020
KASAN: maybe wild-memory-access in range
[0xdead000000000100-0xdead000000000107]
RIP: 0010:__do_sys_swapoff+0x1151/0x1860
RBP: dead0000000000f8
R13: dead000000000100
The crash occurs when free_swap_count_continuations() iterates over a
list_head containing LIST_POISON values from a previous list_del().
== Root Cause ==
The swap subsystem uses vmalloc_to_page() to get struct page pointers for
the swap_map array, then uses page->private and page->lru for swap count
continuation lists.
When vmalloc allocates high-order pages without __GFP_COMP and splits them
via split_page(), the resulting pages may contain stale data:
1. post_alloc_hook() only clears page->private for the head page (page[0])
2. split_page() only calls set_page_refcounted() for tail pages
3. Tail pages retain whatever was in page->private and page->lru from
previous use - including LIST_POISON values from prior list_del() calls
In add_swap_count_continuation() (mm/swapfile.c):
if (!page_private(head)) {
INIT_LIST_HEAD(&head->lru);
set_page_private(head, SWP_CONTINUED);
}
If head is a vmalloc tail page with stale non-zero page->private, the
INIT_LIST_HEAD is skipped, leaving page->lru with poison values. When
free_swap_count_continuations() later iterates this list, it crashes.
The comment at line 3862 says "Page allocation does not initialize the
page's lru field, but it does always reset its private field" - this
assumption is incorrect for vmalloc pages obtained via split_page().
== Proposed Fix ==
Initialize page->private and page->lru for all pages in split_page().
This matches the documented expectation in mm/vmalloc.c:
"High-order allocations must be able to be treated as independent
small pages by callers... Some drivers do their own refcounting
on vmalloc_to_page() pages, some use page->mapping, page->lru, etc."
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,6 +3122,16 @@ void split_page(struct page *page, unsigned int order)
VM_BUG_ON_PAGE(PageCompound(page), page);
VM_BUG_ON_PAGE(!page_count(page), page);
+ /*
+ * Split pages may contain stale data from previous use. Initialize
+ * page->private and page->lru which may have LIST_POISON values.
+ */
+ INIT_LIST_HEAD(&page->lru);
+ for (i = 1; i < (1 << order); i++) {
+ set_page_private(page + i, 0);
+ INIT_LIST_HEAD(&page[i].lru);
+ }
+
for (i = 1; i < (1 << order); i++)
set_page_refcounted(page + i);
split_page_owner(page, order, 0);
== Testing ==
Reproduced with a stress test cycling swapon/swapoff on 8GB zram under
memory pressure:
- Without patch: crash within ~50 iterations
- With patch: 1154+ iterations, no crash
The bug was originally discovered on Fedora 44 with kernel 6.19.0-rc7
during normal system shutdown after extended use.
== Questions ==
1. Is split_page() the right place for this fix, or should the swap code
be more defensive about uninitialized vmalloc pages?
2. Should prep_new_page()/post_alloc_hook() initialize all pages in
high-order allocations, not just the head?
3. Are there other fields besides page->private and page->lru that
callers of split_page() might expect to be initialized?
Thoughts?
--
Best Regards,
Mike Gavrilov.
| On Fri, Jan 30, 2026 at 6:59 PM Matthew Wilcox <willy@infradead.org> wrote:
You're right, no good reason for a separate loop.
Here's v2:
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index cbf758e27aa2..306493d76ea4 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,8 +3122,17 @@ void split_page(struct page *page, unsigned int order)
VM_BUG_ON_PAGE(PageCompound(page), page);
VM_BUG_ON_PAGE(!page_count(page), page);
- for (i = 1; i < (1 << order); i++)
+ /*
+ * Split pages may contain stale data from previous use. Initialize
+ * page->private and page->lru which may have LIST_POISON values.
+ */
+ INIT_LIST_HEAD(&page->lru);
+ for (i = 1; i < (1 << order); i++) {
set_page_refcounted(page + i);
+ set_page_private(page + i, 0);
+ INIT_LIST_HEAD(&page[i].lru);
+ }
+
split_page_owner(page, order, 0);
pgalloc_tag_split(page_folio(page), order, 0);
split_page_memcg(page, order);
Should I send a formal v2 patch?
--
Best Regards,
Mike Gavrilov. | {
"author": "Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>",
"date": "Fri, 30 Jan 2026 19:16:37 +0500",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical address
0xfbd59c0000000020
KASAN: maybe wild-memory-access in range
[0xdead000000000100-0xdead000000000107]
RIP: 0010:__do_sys_swapoff+0x1151/0x1860
RBP: dead0000000000f8
R13: dead000000000100
The crash occurs when free_swap_count_continuations() iterates over a
list_head containing LIST_POISON values from a previous list_del().
== Root Cause ==
The swap subsystem uses vmalloc_to_page() to get struct page pointers for
the swap_map array, then uses page->private and page->lru for swap count
continuation lists.
When vmalloc allocates high-order pages without __GFP_COMP and splits them
via split_page(), the resulting pages may contain stale data:
1. post_alloc_hook() only clears page->private for the head page (page[0])
2. split_page() only calls set_page_refcounted() for tail pages
3. Tail pages retain whatever was in page->private and page->lru from
previous use - including LIST_POISON values from prior list_del() calls
In add_swap_count_continuation() (mm/swapfile.c):
if (!page_private(head)) {
INIT_LIST_HEAD(&head->lru);
set_page_private(head, SWP_CONTINUED);
}
If head is a vmalloc tail page with stale non-zero page->private, the
INIT_LIST_HEAD is skipped, leaving page->lru with poison values. When
free_swap_count_continuations() later iterates this list, it crashes.
The comment at line 3862 says "Page allocation does not initialize the
page's lru field, but it does always reset its private field" - this
assumption is incorrect for vmalloc pages obtained via split_page().
== Proposed Fix ==
Initialize page->private and page->lru for all pages in split_page().
This matches the documented expectation in mm/vmalloc.c:
"High-order allocations must be able to be treated as independent
small pages by callers... Some drivers do their own refcounting
on vmalloc_to_page() pages, some use page->mapping, page->lru, etc."
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,6 +3122,16 @@ void split_page(struct page *page, unsigned int order)
VM_BUG_ON_PAGE(PageCompound(page), page);
VM_BUG_ON_PAGE(!page_count(page), page);
+ /*
+ * Split pages may contain stale data from previous use. Initialize
+ * page->private and page->lru which may have LIST_POISON values.
+ */
+ INIT_LIST_HEAD(&page->lru);
+ for (i = 1; i < (1 << order); i++) {
+ set_page_private(page + i, 0);
+ INIT_LIST_HEAD(&page[i].lru);
+ }
+
for (i = 1; i < (1 << order); i++)
set_page_refcounted(page + i);
split_page_owner(page, order, 0);
== Testing ==
Reproduced with a stress test cycling swapon/swapoff on 8GB zram under
memory pressure:
- Without patch: crash within ~50 iterations
- With patch: 1154+ iterations, no crash
The bug was originally discovered on Fedora 44 with kernel 6.19.0-rc7
during normal system shutdown after extended use.
== Questions ==
1. Is split_page() the right place for this fix, or should the swap code
be more defensive about uninitialized vmalloc pages?
2. Should prep_new_page()/post_alloc_hook() initialize all pages in
high-order allocations, not just the head?
3. Are there other fields besides page->private and page->lru that
callers of split_page() might expect to be initialized?
Thoughts?
--
Best Regards,
Mike Gavrilov.
| On Fri, Jan 30, 2026 at 9:49 PM Mikhail Gavrilov
<mikhail.v.gavrilov@gmail.com> wrote:
Hi Mikhail,
Thanks for reporting this issue.
So the problem starts with `swap_map = vzalloc(maxpages);` right? Will
it be enough if we just pass GFP_COMP here?
And worth noting, mm/swapfile.c already have following code:
/*
* Page allocation does not initialize the page's lru field,
* but it does always reset its private field.
*/
if (!page_private(head)) {
BUG_ON(count & COUNT_CONTINUED);
INIT_LIST_HEAD(&head->lru);
set_page_private(head, SWP_CONTINUED);
si->flags |= SWP_CONTINUED;
} | {
"author": "Kairui Song <ryncsn@gmail.com>",
"date": "Fri, 30 Jan 2026 23:30:33 +0800",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical address
0xfbd59c0000000020
KASAN: maybe wild-memory-access in range
[0xdead000000000100-0xdead000000000107]
RIP: 0010:__do_sys_swapoff+0x1151/0x1860
RBP: dead0000000000f8
R13: dead000000000100
The crash occurs when free_swap_count_continuations() iterates over a
list_head containing LIST_POISON values from a previous list_del().
== Root Cause ==
The swap subsystem uses vmalloc_to_page() to get struct page pointers for
the swap_map array, then uses page->private and page->lru for swap count
continuation lists.
When vmalloc allocates high-order pages without __GFP_COMP and splits them
via split_page(), the resulting pages may contain stale data:
1. post_alloc_hook() only clears page->private for the head page (page[0])
2. split_page() only calls set_page_refcounted() for tail pages
3. Tail pages retain whatever was in page->private and page->lru from
previous use - including LIST_POISON values from prior list_del() calls
In add_swap_count_continuation() (mm/swapfile.c):
if (!page_private(head)) {
INIT_LIST_HEAD(&head->lru);
set_page_private(head, SWP_CONTINUED);
}
If head is a vmalloc tail page with stale non-zero page->private, the
INIT_LIST_HEAD is skipped, leaving page->lru with poison values. When
free_swap_count_continuations() later iterates this list, it crashes.
The comment at line 3862 says "Page allocation does not initialize the
page's lru field, but it does always reset its private field" - this
assumption is incorrect for vmalloc pages obtained via split_page().
== Proposed Fix ==
Initialize page->private and page->lru for all pages in split_page().
This matches the documented expectation in mm/vmalloc.c:
"High-order allocations must be able to be treated as independent
small pages by callers... Some drivers do their own refcounting
on vmalloc_to_page() pages, some use page->mapping, page->lru, etc."
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,6 +3122,16 @@ void split_page(struct page *page, unsigned int order)
VM_BUG_ON_PAGE(PageCompound(page), page);
VM_BUG_ON_PAGE(!page_count(page), page);
+ /*
+ * Split pages may contain stale data from previous use. Initialize
+ * page->private and page->lru which may have LIST_POISON values.
+ */
+ INIT_LIST_HEAD(&page->lru);
+ for (i = 1; i < (1 << order); i++) {
+ set_page_private(page + i, 0);
+ INIT_LIST_HEAD(&page[i].lru);
+ }
+
for (i = 1; i < (1 << order); i++)
set_page_refcounted(page + i);
split_page_owner(page, order, 0);
== Testing ==
Reproduced with a stress test cycling swapon/swapoff on 8GB zram under
memory pressure:
- Without patch: crash within ~50 iterations
- With patch: 1154+ iterations, no crash
The bug was originally discovered on Fedora 44 with kernel 6.19.0-rc7
during normal system shutdown after extended use.
== Questions ==
1. Is split_page() the right place for this fix, or should the swap code
be more defensive about uninitialized vmalloc pages?
2. Should prep_new_page()/post_alloc_hook() initialize all pages in
high-order allocations, not just the head?
3. Are there other fields besides page->private and page->lru that
callers of split_page() might expect to be initialized?
Thoughts?
--
Best Regards,
Mike Gavrilov.
| On Fri, Jan 30, 2026 at 8:31 PM Kairui Song <ryncsn@gmail.com> wrote:
No, __GFP_COMP won't help here. vmalloc always calls split_page() for
high-order allocations to treat them as independent pages (see
mm/vmalloc.c around line 3730). The compound page would be split
anyway.
Yes, this comment is the root of the problem - the assumption is
incorrect for vmalloc pages obtained via split_page().
post_alloc_hook() only clears page->private for the head page
(page[0]). When split_page() breaks a high-order page into individual
pages, tail pages keep their stale page->private values.
We could fix this in swapfile.c by always calling INIT_LIST_HEAD(),
but that would only fix swap. The comment in vmalloc.c suggests other
users also rely on these fields:
"Some drivers do their own refcounting on vmalloc_to_page() pages,
some use page->mapping, page->lru, etc."
So fixing it in split_page() seems like the right place to ensure all
callers get properly initialized pages.
What do you think?
--
Best Regards,
Mike Gavrilov. | {
"author": "Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>",
"date": "Fri, 30 Jan 2026 20:47:39 +0500",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical address
0xfbd59c0000000020
KASAN: maybe wild-memory-access in range
[0xdead000000000100-0xdead000000000107]
RIP: 0010:__do_sys_swapoff+0x1151/0x1860
RBP: dead0000000000f8
R13: dead000000000100
The crash occurs when free_swap_count_continuations() iterates over a
list_head containing LIST_POISON values from a previous list_del().
== Root Cause ==
The swap subsystem uses vmalloc_to_page() to get struct page pointers for
the swap_map array, then uses page->private and page->lru for swap count
continuation lists.
When vmalloc allocates high-order pages without __GFP_COMP and splits them
via split_page(), the resulting pages may contain stale data:
1. post_alloc_hook() only clears page->private for the head page (page[0])
2. split_page() only calls set_page_refcounted() for tail pages
3. Tail pages retain whatever was in page->private and page->lru from
previous use - including LIST_POISON values from prior list_del() calls
In add_swap_count_continuation() (mm/swapfile.c):
if (!page_private(head)) {
INIT_LIST_HEAD(&head->lru);
set_page_private(head, SWP_CONTINUED);
}
If head is a vmalloc tail page with stale non-zero page->private, the
INIT_LIST_HEAD is skipped, leaving page->lru with poison values. When
free_swap_count_continuations() later iterates this list, it crashes.
The comment at line 3862 says "Page allocation does not initialize the
page's lru field, but it does always reset its private field" - this
assumption is incorrect for vmalloc pages obtained via split_page().
== Proposed Fix ==
Initialize page->private and page->lru for all pages in split_page().
This matches the documented expectation in mm/vmalloc.c:
"High-order allocations must be able to be treated as independent
small pages by callers... Some drivers do their own refcounting
on vmalloc_to_page() pages, some use page->mapping, page->lru, etc."
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,6 +3122,16 @@ void split_page(struct page *page, unsigned int order)
VM_BUG_ON_PAGE(PageCompound(page), page);
VM_BUG_ON_PAGE(!page_count(page), page);
+ /*
+ * Split pages may contain stale data from previous use. Initialize
+ * page->private and page->lru which may have LIST_POISON values.
+ */
+ INIT_LIST_HEAD(&page->lru);
+ for (i = 1; i < (1 << order); i++) {
+ set_page_private(page + i, 0);
+ INIT_LIST_HEAD(&page[i].lru);
+ }
+
for (i = 1; i < (1 << order); i++)
set_page_refcounted(page + i);
split_page_owner(page, order, 0);
== Testing ==
Reproduced with a stress test cycling swapon/swapoff on 8GB zram under
memory pressure:
- Without patch: crash within ~50 iterations
- With patch: 1154+ iterations, no crash
The bug was originally discovered on Fedora 44 with kernel 6.19.0-rc7
during normal system shutdown after extended use.
== Questions ==
1. Is split_page() the right place for this fix, or should the swap code
be more defensive about uninitialized vmalloc pages?
2. Should prep_new_page()/post_alloc_hook() initialize all pages in
high-order allocations, not just the head?
3. Are there other fields besides page->private and page->lru that
callers of split_page() might expect to be initialized?
Thoughts?
--
Best Regards,
Mike Gavrilov.
| On Fri, Jan 30, 2026 at 11:47 PM Mikhail Gavrilov
<mikhail.v.gavrilov@gmail.com> wrote:
Right, but with __GFP_COMP, prep_compound_page clears the tail pages'
private too, so the code snip I posted will clear their lru on use?
I took a look at the history, commit 3b8000ae185c ("mm/vmalloc: huge
vmalloc backing pages should be split rather than compound") dropped
__GFP_COMP and added split_page, that's the commit added the comment
you mentioned.
Fixing it with this patch you posted seems could result in other
issues, e.g. split_free_pages / split_free_frozen_pages would call
split_page while the page is on a list, so at least clearing head
page's LRU seems incorrect? | {
"author": "Kairui Song <ryncsn@gmail.com>",
"date": "Mon, 2 Feb 2026 11:17:57 +0800",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical address
0xfbd59c0000000020
KASAN: maybe wild-memory-access in range
[0xdead000000000100-0xdead000000000107]
RIP: 0010:__do_sys_swapoff+0x1151/0x1860
RBP: dead0000000000f8
R13: dead000000000100
The crash occurs when free_swap_count_continuations() iterates over a
list_head containing LIST_POISON values from a previous list_del().
== Root Cause ==
The swap subsystem uses vmalloc_to_page() to get struct page pointers for
the swap_map array, then uses page->private and page->lru for swap count
continuation lists.
When vmalloc allocates high-order pages without __GFP_COMP and splits them
via split_page(), the resulting pages may contain stale data:
1. post_alloc_hook() only clears page->private for the head page (page[0])
2. split_page() only calls set_page_refcounted() for tail pages
3. Tail pages retain whatever was in page->private and page->lru from
previous use - including LIST_POISON values from prior list_del() calls
In add_swap_count_continuation() (mm/swapfile.c):
if (!page_private(head)) {
INIT_LIST_HEAD(&head->lru);
set_page_private(head, SWP_CONTINUED);
}
If head is a vmalloc tail page with stale non-zero page->private, the
INIT_LIST_HEAD is skipped, leaving page->lru with poison values. When
free_swap_count_continuations() later iterates this list, it crashes.
The comment at line 3862 says "Page allocation does not initialize the
page's lru field, but it does always reset its private field" - this
assumption is incorrect for vmalloc pages obtained via split_page().
== Proposed Fix ==
Initialize page->private and page->lru for all pages in split_page().
This matches the documented expectation in mm/vmalloc.c:
"High-order allocations must be able to be treated as independent
small pages by callers... Some drivers do their own refcounting
on vmalloc_to_page() pages, some use page->mapping, page->lru, etc."
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,6 +3122,16 @@ void split_page(struct page *page, unsigned int order)
VM_BUG_ON_PAGE(PageCompound(page), page);
VM_BUG_ON_PAGE(!page_count(page), page);
+ /*
+ * Split pages may contain stale data from previous use. Initialize
+ * page->private and page->lru which may have LIST_POISON values.
+ */
+ INIT_LIST_HEAD(&page->lru);
+ for (i = 1; i < (1 << order); i++) {
+ set_page_private(page + i, 0);
+ INIT_LIST_HEAD(&page[i].lru);
+ }
+
for (i = 1; i < (1 << order); i++)
set_page_refcounted(page + i);
split_page_owner(page, order, 0);
== Testing ==
Reproduced with a stress test cycling swapon/swapoff on 8GB zram under
memory pressure:
- Without patch: crash within ~50 iterations
- With patch: 1154+ iterations, no crash
The bug was originally discovered on Fedora 44 with kernel 6.19.0-rc7
during normal system shutdown after extended use.
== Questions ==
1. Is split_page() the right place for this fix, or should the swap code
be more defensive about uninitialized vmalloc pages?
2. Should prep_new_page()/post_alloc_hook() initialize all pages in
high-order allocations, not just the head?
3. Are there other fields besides page->private and page->lru that
callers of split_page() might expect to be initialized?
Thoughts?
--
Best Regards,
Mike Gavrilov.
| On Mon, Feb 2, 2026 at 8:18 AM Kairui Song <ryncsn@gmail.com> wrote:
You're right that prep_compound_tail() clears page->private for tail
pages. But the issue is that vmalloc explicitly avoids __GFP_COMP -
see commit 3b8000ae185c ("mm/vmalloc: huge vmalloc backing pages
should be split rather than compound"). So prep_compound_page() is
never called for these allocations.
Good find! That's exactly where the problem was introduced.
You're absolutely right, that's a problem I missed. split_free_page()
calls split_page() on pages that are still on the buddy free list -
initializing head->lru there would corrupt the list.
So the fix should only initialize tail pages, not the head page:
/*
* Split pages may contain stale data from previous use. Initialize
* page->private and page->lru for tail pages which may have
* LIST_POISON values. Head page is left alone as callers like
* split_free_page() may have it on a list.
*/
for (i = 1; i < (1 << order); i++) {
set_page_refcounted(page + i);
set_page_private(page + i, 0);
INIT_LIST_HEAD(&page[i].lru);
}
But then we still have the problem for head page in vmalloc case.
Maybe the fix should be in vmalloc.c instead, after split_page()
returns?
Or alternatively, fix it in swapfile.c by unconditionally calling
INIT_LIST_HEAD() - the comment there is already wrong, so we should
fix both the comment and the code?
What do you think is the cleanest approach?
--
Best Regards,
Mike Gavrilov. | {
"author": "Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>",
"date": "Mon, 2 Feb 2026 10:27:01 +0500",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical address
0xfbd59c0000000020
KASAN: maybe wild-memory-access in range
[0xdead000000000100-0xdead000000000107]
RIP: 0010:__do_sys_swapoff+0x1151/0x1860
RBP: dead0000000000f8
R13: dead000000000100
The crash occurs when free_swap_count_continuations() iterates over a
list_head containing LIST_POISON values from a previous list_del().
== Root Cause ==
The swap subsystem uses vmalloc_to_page() to get struct page pointers for
the swap_map array, then uses page->private and page->lru for swap count
continuation lists.
When vmalloc allocates high-order pages without __GFP_COMP and splits them
via split_page(), the resulting pages may contain stale data:
1. post_alloc_hook() only clears page->private for the head page (page[0])
2. split_page() only calls set_page_refcounted() for tail pages
3. Tail pages retain whatever was in page->private and page->lru from
previous use - including LIST_POISON values from prior list_del() calls
In add_swap_count_continuation() (mm/swapfile.c):
if (!page_private(head)) {
INIT_LIST_HEAD(&head->lru);
set_page_private(head, SWP_CONTINUED);
}
If head is a vmalloc tail page with stale non-zero page->private, the
INIT_LIST_HEAD is skipped, leaving page->lru with poison values. When
free_swap_count_continuations() later iterates this list, it crashes.
The comment at line 3862 says "Page allocation does not initialize the
page's lru field, but it does always reset its private field" - this
assumption is incorrect for vmalloc pages obtained via split_page().
== Proposed Fix ==
Initialize page->private and page->lru for all pages in split_page().
This matches the documented expectation in mm/vmalloc.c:
"High-order allocations must be able to be treated as independent
small pages by callers... Some drivers do their own refcounting
on vmalloc_to_page() pages, some use page->mapping, page->lru, etc."
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,6 +3122,16 @@ void split_page(struct page *page, unsigned int order)
VM_BUG_ON_PAGE(PageCompound(page), page);
VM_BUG_ON_PAGE(!page_count(page), page);
+ /*
+ * Split pages may contain stale data from previous use. Initialize
+ * page->private and page->lru which may have LIST_POISON values.
+ */
+ INIT_LIST_HEAD(&page->lru);
+ for (i = 1; i < (1 << order); i++) {
+ set_page_private(page + i, 0);
+ INIT_LIST_HEAD(&page[i].lru);
+ }
+
for (i = 1; i < (1 << order); i++)
set_page_refcounted(page + i);
split_page_owner(page, order, 0);
== Testing ==
Reproduced with a stress test cycling swapon/swapoff on 8GB zram under
memory pressure:
- Without patch: crash within ~50 iterations
- With patch: 1154+ iterations, no crash
The bug was originally discovered on Fedora 44 with kernel 6.19.0-rc7
during normal system shutdown after extended use.
== Questions ==
1. Is split_page() the right place for this fix, or should the swap code
be more defensive about uninitialized vmalloc pages?
2. Should prep_new_page()/post_alloc_hook() initialize all pages in
high-order allocations, not just the head?
3. Are there other fields besides page->private and page->lru that
callers of split_page() might expect to be initialized?
Thoughts?
--
Best Regards,
Mike Gavrilov.
| On Mon, Feb 2, 2026 at 1:27 PM Mikhail Gavrilov
<mikhail.v.gavrilov@gmail.com> wrote:
Right, then I think we need a Fixes tag, and is swap really the only
victim of that change? BTW, swap's usage of page->lru will be gone
soon. Still this definitely needs to be fixed first for stable branch, but
it looks strange why nothing else ever hit this.
Or maybe clean page->private instead? The problem is triggered by
free_swap_count_continuations which checks page_private to tell if the
page has list data, and ignores the list if not. So the pages should
have their private cleaned upon allocation.
The old comment in swapfile: "Page allocation does not initialize the
page's lru field, but it does always reset its private field" does
suggest that vmalloc should take care of the private field, not sure
if that suppose to be an convention, but if swap is really the only
user of that, patching from swap side looks cleaner. | {
"author": "Kairui Song <ryncsn@gmail.com>",
"date": "Tue, 3 Feb 2026 01:54:26 +0800",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/platform/x86/dell/dell-wmi-base.c b/drivers/platform/x86/dell/dell-wmi-base.c
index 28076929d6af..62cf28d1fe19 100644
--- a/drivers/platform/x86/dell/dell-wmi-base.c
+++ b/drivers/platform/x86/dell/dell-wmi-base.c
@@ -86,6 +86,9 @@ static const struct key_entry dell_wmi_keymap_type_0000[] = {
/* Meta key unlock */
{ KE_IGNORE, 0xe001, { KEY_RIGHTMETA } },
+ { KE_KEY, 0x0109, { KEY_MUTE } },
+ { KE_KEY, 0x0150, { KEY_MICMUTE } },
+
/* Key code is followed by brightness level */
{ KE_KEY, 0xe005, { KEY_BRIGHTNESSDOWN } },
{ KE_KEY, 0xe006, { KEY_BRIGHTNESSUP } },
---
base-commit: 008bec8ffe6e7746588d1e12c5b3865fa478fc91
change-id: 20260126-mute-keys-7f8a27cd317f
--
~ Kurt
| On Sunday 01 February 2026 23:37:37 Kurt Borja wrote:
Hello, please keep codes in the array sorted. | {
"author": "Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>",
"date": "Mon, 2 Feb 2026 09:12:47 +0100",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/platform/x86/dell/dell-wmi-base.c b/drivers/platform/x86/dell/dell-wmi-base.c
index 28076929d6af..62cf28d1fe19 100644
--- a/drivers/platform/x86/dell/dell-wmi-base.c
+++ b/drivers/platform/x86/dell/dell-wmi-base.c
@@ -86,6 +86,9 @@ static const struct key_entry dell_wmi_keymap_type_0000[] = {
/* Meta key unlock */
{ KE_IGNORE, 0xe001, { KEY_RIGHTMETA } },
+ { KE_KEY, 0x0109, { KEY_MUTE } },
+ { KE_KEY, 0x0150, { KEY_MICMUTE } },
+
/* Key code is followed by brightness level */
{ KE_KEY, 0xe005, { KEY_BRIGHTNESSDOWN } },
{ KE_KEY, 0xe006, { KEY_BRIGHTNESSUP } },
---
base-commit: 008bec8ffe6e7746588d1e12c5b3865fa478fc91
change-id: 20260126-mute-keys-7f8a27cd317f
--
~ Kurt
| On 2/1/26 10:37 PM, Kurt Borja wrote:
Make sure that you include Dell.Client.Kernel@dell.com in case they have
any comments.
I added them to CC. | {
"author": "Mario Limonciello <mario.limonciello@amd.com>",
"date": "Mon, 2 Feb 2026 08:17:16 -0600",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/platform/x86/dell/dell-wmi-base.c b/drivers/platform/x86/dell/dell-wmi-base.c
index 28076929d6af..62cf28d1fe19 100644
--- a/drivers/platform/x86/dell/dell-wmi-base.c
+++ b/drivers/platform/x86/dell/dell-wmi-base.c
@@ -86,6 +86,9 @@ static const struct key_entry dell_wmi_keymap_type_0000[] = {
/* Meta key unlock */
{ KE_IGNORE, 0xe001, { KEY_RIGHTMETA } },
+ { KE_KEY, 0x0109, { KEY_MUTE } },
+ { KE_KEY, 0x0150, { KEY_MICMUTE } },
+
/* Key code is followed by brightness level */
{ KE_KEY, 0xe005, { KEY_BRIGHTNESSDOWN } },
{ KE_KEY, 0xe006, { KEY_BRIGHTNESSUP } },
---
base-commit: 008bec8ffe6e7746588d1e12c5b3865fa478fc91
change-id: 20260126-mute-keys-7f8a27cd317f
--
~ Kurt
| On Mon Feb 2, 2026 at 3:12 AM -05, Pali Rohár wrote:
Hi Pali,
I thought I sorted it... I'll fix it, thanks!
--
Thanks,
~ Kurt | {
"author": "\"Kurt Borja\" <kuurtb@gmail.com>",
"date": "Mon, 02 Feb 2026 12:34:19 -0500",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/platform/x86/dell/dell-wmi-base.c b/drivers/platform/x86/dell/dell-wmi-base.c
index 28076929d6af..62cf28d1fe19 100644
--- a/drivers/platform/x86/dell/dell-wmi-base.c
+++ b/drivers/platform/x86/dell/dell-wmi-base.c
@@ -86,6 +86,9 @@ static const struct key_entry dell_wmi_keymap_type_0000[] = {
/* Meta key unlock */
{ KE_IGNORE, 0xe001, { KEY_RIGHTMETA } },
+ { KE_KEY, 0x0109, { KEY_MUTE } },
+ { KE_KEY, 0x0150, { KEY_MICMUTE } },
+
/* Key code is followed by brightness level */
{ KE_KEY, 0xe005, { KEY_BRIGHTNESSDOWN } },
{ KE_KEY, 0xe006, { KEY_BRIGHTNESSUP } },
---
base-commit: 008bec8ffe6e7746588d1e12c5b3865fa478fc91
change-id: 20260126-mute-keys-7f8a27cd317f
--
~ Kurt
| On Mon Feb 2, 2026 at 9:17 AM -05, Mario Limonciello wrote:
Hi Mario,
Thanks, I'll add it.
--
Thanks,
~ Kurt | {
"author": "\"Kurt Borja\" <kuurtb@gmail.com>",
"date": "Mon, 02 Feb 2026 12:35:49 -0500",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/platform/x86/dell/dell-wmi-base.c b/drivers/platform/x86/dell/dell-wmi-base.c
index 28076929d6af..62cf28d1fe19 100644
--- a/drivers/platform/x86/dell/dell-wmi-base.c
+++ b/drivers/platform/x86/dell/dell-wmi-base.c
@@ -86,6 +86,9 @@ static const struct key_entry dell_wmi_keymap_type_0000[] = {
/* Meta key unlock */
{ KE_IGNORE, 0xe001, { KEY_RIGHTMETA } },
+ { KE_KEY, 0x0109, { KEY_MUTE } },
+ { KE_KEY, 0x0150, { KEY_MICMUTE } },
+
/* Key code is followed by brightness level */
{ KE_KEY, 0xe005, { KEY_BRIGHTNESSDOWN } },
{ KE_KEY, 0xe006, { KEY_BRIGHTNESSUP } },
---
base-commit: 008bec8ffe6e7746588d1e12c5b3865fa478fc91
change-id: 20260126-mute-keys-7f8a27cd317f
--
~ Kurt
| On Monday 02 February 2026 12:34:19 Kurt Borja wrote:
Before is value 0xe001 and your new values are 0x01xx. Most of values
are 0xeXXX, so it is quite unusual that Dell allocated values with
different pattern.
Also, could you please include into commit message for which Alienware
devices is change needed? It would help to detect devices which will be
fixed by your change.
And please add some comment into source file above those two new codes
for which are needed, in similar way how we have commented/documented
other key codes. | {
"author": "Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>",
"date": "Mon, 2 Feb 2026 18:43:22 +0100",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH v2] docs: filesystems: ensure proc pid substitutable is
complete | The entry in proc.rst for 3.14 is missing the closing ">" of the "pid"
field for the ksm_stat file. Add this for both the table of contents and
the actual header for the "ksm_stat" file.
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Thomas Böhler <witcher@wiredspace.de>
---
Changes in v2:
- Also adjust title underline to match the new length
- Link to v1: https://lore.kernel.org/r/20260130-ksm_stat-v1-1-a6aa0da78de6@wiredspace.de
---
Documentation/filesystems/proc.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/filesystems/proc.rst b/Documentation/filesystems/proc.rst
index 8256e857e2d7..b0c0d1b45b99 100644
--- a/Documentation/filesystems/proc.rst
+++ b/Documentation/filesystems/proc.rst
@@ -48,7 +48,7 @@ fixes/update part 1.1 Stefani Seibold <stefani@seibold.net> June 9 2009
3.11 /proc/<pid>/patch_state - Livepatch patch operation state
3.12 /proc/<pid>/arch_status - Task architecture specific information
3.13 /proc/<pid>/fd - List of symlinks to open files
- 3.14 /proc/<pid/ksm_stat - Information about the process's ksm status.
+ 3.14 /proc/<pid>/ksm_stat - Information about the process's ksm status.
4 Configuring procfs
4.1 Mount options
@@ -2289,8 +2289,8 @@ The number of open files for the process is stored in 'size' member
of stat() output for /proc/<pid>/fd for fast access.
-------------------------------------------------------
-3.14 /proc/<pid/ksm_stat - Information about the process's ksm status
----------------------------------------------------------------------
+3.14 /proc/<pid>/ksm_stat - Information about the process's ksm status
+----------------------------------------------------------------------
When CONFIG_KSM is enabled, each process has this file which displays
the information of ksm merging status.
---
base-commit: 6b8edfcd661b569f077cc1ea1f7463ec38547779
change-id: 20260130-ksm_stat-4d14366630ea
Best regards,
--
Thomas Böhler <witcher@wiredspace.de>
| Thomas Böhler <witcher@wiredspace.de> writes:
Applied, thanks.
jon | {
"author": "Jonathan Corbet <corbet@lwn.net>",
"date": "Mon, 02 Feb 2026 09:49:51 -0700",
"thread_id": "87wm0vrsy8.fsf@trenco.lwn.net.mbox.gz"
} |
lkml | [PATCH v2 00/14] Add SPDX SBOM generation tool | This patch series introduces a Python-based tool for generating SBOM
documents in the SPDX 3.0.1 format for kernel builds.
A Software Bill of Materials (SBOM) describes the individual components
of a software product. For the kernel, the goal is to describe the
distributable build outputs (typically the kernel image and modules),
the source files involved in producing these outputs, and the build
process that connects the source and output files.
To achieve this, the SBOM tool generates three SPDX documents:
- sbom-output.spdx.json
Describes the final build outputs together with high-level
build metadata.
- sbom-source.spdx.json
Describes all source files involved in the build, including
licensing information and additional file metadata.
- sbom-build.spdx.json
Describes the entire build process, linking source files
from the source SBOM to output files in the output SBOM.
The sbom tool is optional and runs only when CONFIG_SBOM is enabled. It
is invoked after the build, once all output artifacts have been
generated. Starting from the kernel image and modules as root nodes,
the tool reconstructs the dependency graph up to the original source
files. Build dependencies are primarily derived from the .cmd files
generated by Kbuild, which record the full command used to build
each output file.
Currently, the tool only supports x86 and arm64 architectures.
Co-developed-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Luis Augenstein <luis.augenstein@tngtech.com>
---
Changes in v2:
- regenerate sbom documents when build configuration changes
---
Luis Augenstein (14):
tools/sbom: integrate tool in make process
tools/sbom: setup sbom logging
tools/sbom: add command parsers
tools/sbom: add cmd graph generation
tools/sbom: add additional dependency sources for cmd graph
tools/sbom: add SPDX classes
tools/sbom: add JSON-LD serialization
tools/sbom: add shared SPDX elements
tools/sbom: collect file metadata
tools/sbom: add SPDX output graph
tools/sbom: add SPDX source graph
tools/sbom: add SPDX build graph
tools/sbom: add unit tests for command parsers
tools/sbom: add unit tests for SPDX-License-Identifier parsing
.gitignore | 1 +
MAINTAINERS | 6 +
Makefile | 15 +-
lib/Kconfig.debug | 9 +
tools/Makefile | 3 +-
tools/sbom/Makefile | 42 ++
tools/sbom/README | 208 ++++++
tools/sbom/sbom.py | 129 ++++
tools/sbom/sbom/__init__.py | 0
tools/sbom/sbom/cmd_graph/__init__.py | 7 +
tools/sbom/sbom/cmd_graph/cmd_file.py | 149 ++++
tools/sbom/sbom/cmd_graph/cmd_graph.py | 46 ++
tools/sbom/sbom/cmd_graph/cmd_graph_node.py | 142 ++++
tools/sbom/sbom/cmd_graph/deps_parser.py | 52 ++
.../sbom/cmd_graph/hardcoded_dependencies.py | 83 +++
tools/sbom/sbom/cmd_graph/incbin_parser.py | 42 ++
tools/sbom/sbom/cmd_graph/savedcmd_parser.py | 664 ++++++++++++++++++
tools/sbom/sbom/config.py | 335 +++++++++
tools/sbom/sbom/environment.py | 164 +++++
tools/sbom/sbom/path_utils.py | 11 +
tools/sbom/sbom/sbom_logging.py | 88 +++
tools/sbom/sbom/spdx/__init__.py | 7 +
tools/sbom/sbom/spdx/build.py | 17 +
tools/sbom/sbom/spdx/core.py | 182 +++++
tools/sbom/sbom/spdx/serialization.py | 56 ++
tools/sbom/sbom/spdx/simplelicensing.py | 20 +
tools/sbom/sbom/spdx/software.py | 71 ++
tools/sbom/sbom/spdx/spdxId.py | 36 +
tools/sbom/sbom/spdx_graph/__init__.py | 7 +
.../sbom/sbom/spdx_graph/build_spdx_graphs.py | 82 +++
tools/sbom/sbom/spdx_graph/kernel_file.py | 310 ++++++++
.../sbom/spdx_graph/shared_spdx_elements.py | 32 +
.../sbom/sbom/spdx_graph/spdx_build_graph.py | 317 +++++++++
.../sbom/sbom/spdx_graph/spdx_graph_model.py | 36 +
.../sbom/sbom/spdx_graph/spdx_output_graph.py | 188 +++++
.../sbom/sbom/spdx_graph/spdx_source_graph.py | 126 ++++
tools/sbom/tests/__init__.py | 0
tools/sbom/tests/cmd_graph/__init__.py | 0
.../tests/cmd_graph/test_savedcmd_parser.py | 383 ++++++++++
tools/sbom/tests/spdx_graph/__init__.py | 0
.../sbom/tests/spdx_graph/test_kernel_file.py | 32 +
41 files changed, 4096 insertions(+), 2 deletions(-)
create mode 100644 tools/sbom/Makefile
create mode 100644 tools/sbom/README
create mode 100644 tools/sbom/sbom.py
create mode 100644 tools/sbom/sbom/__init__.py
create mode 100644 tools/sbom/sbom/cmd_graph/__init__.py
create mode 100644 tools/sbom/sbom/cmd_graph/cmd_file.py
create mode 100644 tools/sbom/sbom/cmd_graph/cmd_graph.py
create mode 100644 tools/sbom/sbom/cmd_graph/cmd_graph_node.py
create mode 100644 tools/sbom/sbom/cmd_graph/deps_parser.py
create mode 100644 tools/sbom/sbom/cmd_graph/hardcoded_dependencies.py
create mode 100644 tools/sbom/sbom/cmd_graph/incbin_parser.py
create mode 100644 tools/sbom/sbom/cmd_graph/savedcmd_parser.py
create mode 100644 tools/sbom/sbom/config.py
create mode 100644 tools/sbom/sbom/environment.py
create mode 100644 tools/sbom/sbom/path_utils.py
create mode 100644 tools/sbom/sbom/sbom_logging.py
create mode 100644 tools/sbom/sbom/spdx/__init__.py
create mode 100644 tools/sbom/sbom/spdx/build.py
create mode 100644 tools/sbom/sbom/spdx/core.py
create mode 100644 tools/sbom/sbom/spdx/serialization.py
create mode 100644 tools/sbom/sbom/spdx/simplelicensing.py
create mode 100644 tools/sbom/sbom/spdx/software.py
create mode 100644 tools/sbom/sbom/spdx/spdxId.py
create mode 100644 tools/sbom/sbom/spdx_graph/__init__.py
create mode 100644 tools/sbom/sbom/spdx_graph/build_spdx_graphs.py
create mode 100644 tools/sbom/sbom/spdx_graph/kernel_file.py
create mode 100644 tools/sbom/sbom/spdx_graph/shared_spdx_elements.py
create mode 100644 tools/sbom/sbom/spdx_graph/spdx_build_graph.py
create mode 100644 tools/sbom/sbom/spdx_graph/spdx_graph_model.py
create mode 100644 tools/sbom/sbom/spdx_graph/spdx_output_graph.py
create mode 100644 tools/sbom/sbom/spdx_graph/spdx_source_graph.py
create mode 100644 tools/sbom/tests/__init__.py
create mode 100644 tools/sbom/tests/cmd_graph/__init__.py
create mode 100644 tools/sbom/tests/cmd_graph/test_savedcmd_parser.py
create mode 100644 tools/sbom/tests/spdx_graph/__init__.py
create mode 100644 tools/sbom/tests/spdx_graph/test_kernel_file.py
--
2.34.1
| Add CONFIG_SBOM option and integrate SBOM tool into the kernel build
process.
Co-developed-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Luis Augenstein <luis.augenstein@tngtech.com>
---
.gitignore | 1 +
MAINTAINERS | 6 ++
Makefile | 15 +++-
lib/Kconfig.debug | 9 ++
tools/Makefile | 3 +-
tools/sbom/Makefile | 35 ++++++++
tools/sbom/README | 208 ++++++++++++++++++++++++++++++++++++++++++++
tools/sbom/sbom.py | 16 ++++
8 files changed, 291 insertions(+), 2 deletions(-)
create mode 100644 tools/sbom/Makefile
create mode 100644 tools/sbom/README
create mode 100644 tools/sbom/sbom.py
diff --git a/.gitignore b/.gitignore
index 3a7241c941f5..f3372f15eb1b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -48,6 +48,7 @@
*.s
*.so
*.so.dbg
+*.spdx.json
*.su
*.symtypes
*.tab.[ch]
diff --git a/MAINTAINERS b/MAINTAINERS
index f1b020588597..03d7d93d8e63 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23365,6 +23365,12 @@ R: Marc Murphy <marc.murphy@sancloud.com>
S: Supported
F: arch/arm/boot/dts/ti/omap/am335x-sancloud*
+SBOM
+M: Luis Augenstein <luis.augenstein@tngtech.com>
+M: Maximilian Huber <maximilian.huber@tngtech.com>
+S: Maintained
+F: tools/sbom/
+
SC1200 WDT DRIVER
M: Zwane Mwaikambo <zwanem@gmail.com>
S: Maintained
diff --git a/Makefile b/Makefile
index 9d38125263fb..a1c0cbd110e5 100644
--- a/Makefile
+++ b/Makefile
@@ -1457,6 +1457,19 @@ prepare: tools/bpf/resolve_btfids
endif
endif
+ifdef CONFIG_SBOM
+all: tools/sbom
+tools/sbom: $(notdir $(KBUILD_IMAGE)) modules
+ $(Q)mkdir -p $(objtree)/tools
+ $(Q)$(MAKE) \
+ O=$(abspath $(objtree)) \
+ subdir=tools \
+ -C $(srctree)/tools/ \
+ sbom \
+ srctree=$(abspath $(srctree)) \
+ CONFIG_MODULES=$(CONFIG_MODULES)
+endif
+
# The tools build system is not a part of Kbuild and tends to introduce
# its own unique issues. If you need to integrate a new tool into Kbuild,
# please consider locating that tool outside the tools/ tree and using the
@@ -1612,7 +1625,7 @@ CLEAN_FILES += vmlinux.symvers modules-only.symvers \
modules.builtin.ranges vmlinux.o.map vmlinux.unstripped \
compile_commands.json rust/test \
rust-project.json .vmlinux.objs .vmlinux.export.c \
- .builtin-dtbs-list .builtin-dtb.S
+ .builtin-dtbs-list .builtin-dtb.S sbom-*.spdx.json
# Directories & files removed with 'make mrproper'
MRPROPER_FILES += include/config include/generated \
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index ba36939fda79..9d03ef854f61 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -563,6 +563,15 @@ config OBJTOOL_WERROR
If unsure, say Y.
+config SBOM
+ bool "Generate Software Bill of Materials"
+ help
+ If enabled, the kernel build will generate SPDX SBOM documents
+ describing all source files, and build artifacts involved in the build.
+ The SBOM documents are generated in SPDX 3.0.1 format and saved to the build output
+ directory after the build completes.
+ For more information, see tools/sbom/README
+
config STACK_VALIDATION
bool "Compile-time stack metadata validation"
depends on HAVE_STACK_VALIDATION && UNWINDER_FRAME_POINTER
diff --git a/tools/Makefile b/tools/Makefile
index cb40961a740f..7b4b1c96dcd5 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -27,6 +27,7 @@ help:
@echo ' nolibc - nolibc headers testing and installation'
@echo ' objtool - an ELF object analysis tool'
@echo ' perf - Linux performance measurement and analysis tool'
+ @echo ' sbom - SBOM generation tool'
@echo ' selftests - various kernel selftests'
@echo ' sched_ext - sched_ext example schedulers'
@echo ' bootconfig - boot config tool'
@@ -70,7 +71,7 @@ acpi: FORCE
cpupower: FORCE
$(call descend,power/$@)
-counter dma firewire hv guest bootconfig spi usb virtio mm bpf iio gpio objtool leds wmi firmware debugging tracing: FORCE
+counter dma firewire hv guest bootconfig spi usb virtio mm bpf iio gpio objtool leds wmi firmware debugging tracing sbom: FORCE
$(call descend,$@)
bpf/%: FORCE
diff --git a/tools/sbom/Makefile b/tools/sbom/Makefile
new file mode 100644
index 000000000000..8be7f2f3e631
--- /dev/null
+++ b/tools/sbom/Makefile
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-only OR MIT
+# Copyright (C) 2025 TNG Technology Consulting GmbH
+
+SBOM_SOURCE_FILE := $(objtree)/sbom-source.spdx.json
+SBOM_BUILD_FILE := $(objtree)/sbom-build.spdx.json
+SBOM_OUTPUT_FILE := $(objtree)/sbom-output.spdx.json
+SBOM_ROOTS_FILE := $(objtree)/sbom-roots.txt
+
+
+ifeq ($(srctree),$(objtree))
+ SBOM_TARGETS := $(SBOM_BUILD_FILE) $(SBOM_OUTPUT_FILE)
+else
+ SBOM_TARGETS := $(SBOM_SOURCE_FILE) $(SBOM_BUILD_FILE) $(SBOM_OUTPUT_FILE)
+endif
+
+SBOM_DEPS := $(objtree)/$(KBUILD_IMAGE) $(objtree)/include/generated/autoconf.h
+ifdef CONFIG_MODULES
+ SBOM_DEPS += $(objtree)/modules.order
+endif
+
+sbom: $(SBOM_TARGETS)
+
+$(SBOM_TARGETS) &: $(SBOM_DEPS)
+ @echo " GEN $(notdir $(SBOM_TARGETS))"
+
+ @printf "%s\n" "$(KBUILD_IMAGE)" > $(SBOM_ROOTS_FILE)
+ @if [ "$(CONFIG_MODULES)" = "y" ]; then \
+ sed 's/\.o$$/.ko/' $(objtree)/modules.order >> $(SBOM_ROOTS_FILE); \
+ fi
+
+ @python3 sbom.py
+
+ @rm $(SBOM_ROOTS_FILE)
+
+.PHONY: sbom
diff --git a/tools/sbom/README b/tools/sbom/README
new file mode 100644
index 000000000000..5d157a1f9af8
--- /dev/null
+++ b/tools/sbom/README
@@ -0,0 +1,208 @@
+<!--
+SPDX-License-Identifier: GPL-2.0-only OR MIT
+Copyright (C) 2025 TNG Technology Consulting GmbH
+-->
+
+KernelSbom
+==========
+
+Introduction
+------------
+
+The kernel `CONFIG_SBOM` option enables the KernelSbom tool,
+a Python script `sbom.py` that runs during the kernel build process
+after all build outputs have been generated.
+KernelSbom analyzes every file involved in the build and produces
+Software Bill of Materials (SBOM) documents in SPDX 3.0.1 format.
+The generated SBOM documents capture:
+- **Final output artifacts**, typically the kernel image and modules
+- **All source files** that contributed to the build with metadata
+ and licensing information
+- **Details of the build process**, including intermediate artifacts
+ and the build commands linking source files to the final output
+ artifacts
+
+KernelSbom is originally developed in the
+[KernelSbom repository](https://github.com/TNG/KernelSbom).
+
+Requirements
+------------
+
+Python 3.10 or later. No libraries or other dependencies are required.
+
+Basic Usage
+-----------
+
+Enable the `CONFIG_SBOM` option and start a kernel build.
+For example:
+
+ $ make defconfig O=kernel_build
+ $ scripts/config --file kernel_build/.config --enable SBOM
+ $ make O=kernel_build -j$(nproc)
+
+After all build outputs have been generated, KernelSbom produces three
+SPDX documents in the root directory of the object tree:
+
+- `sbom-source.spdx.json`
+ Describes all source files involved in the build and
+ associates each file with its corresponding license expression.
+
+- `sbom-output.spdx.json`
+ Captures all final build outputs (kernel image and `.ko` module files)
+ and includes build metadata such as environment variables and
+ a hash of the `.config` file used for the build.
+
+- `sbom-build.spdx.json`
+ Imports files from the source and output documents and describes every
+ intermediate build artifact. For each artifact, it records the exact
+ build command used and establishes the relationship between
+ input files and generated outputs.
+
+When enabling the KernelSbom tool, it is recommended to perform
+out-of-tree builds using `O=<objtree>`. KernelSbom classifies files as
+source files when they are located in the source tree and not in the
+object tree. For in-tree builds, where the source and object trees are
+the same directory, this distinction can no longer be made reliably.
+In that case, KernelSbom does not generate a dedicated source SBOM.
+Instead, source files are included in the build SBOM.
+
+Standalone Usage
+----------------
+
+KernelSbom can also be used as a standalone script to generate
+SPDX documents for specific build outputs. For example, after a
+successful x86 kernel build, KernelSbom can generate SPDX documents
+for the `bzImage` kernel image:
+
+ $ SRCARCH=x86 python3 tools/sbom/sbom.py \
+ --src-tree . \
+ --obj-tree ./kernel_build \
+ --roots arch/x86/boot/bzImage \
+ --generate-spdx \
+ --generate-used-files \
+ --prettify-json \
+ --debug
+
+Note that when KernelSbom is invoked outside of the `make` process,
+the environment variables used during compilation are not available and
+therefore cannot be included in the generated SPDX documents. It is
+recommended to set at least the `SRCARCH` environment variable to the
+architecture for which the build was performed.
+
+For a full list of command-line options, run:
+
+ $ python3 tools/sbom/sbom.py --help
+
+Output Format
+-------------
+
+KernelSbom generates documents conforming to the
+[SPDX 3.0.1 specification](https://spdx.github.io/spdx-spec/v3.0.1/)
+serialized as JSON-LD.
+
+To reduce file size, the output documents use the JSON-LD `@context`
+to define custom prefixes for `spdxId` values. While this is compliant
+with the SPDX specification, only a limited number of tools in the
+current SPDX ecosystem support custom JSON-LD contexts. To use such
+tools with the generated documents, the custom JSON-LD context must
+be expanded before providing the documents.
+See https://lists.spdx.org/g/Spdx-tech/message/6064 for more information.
+
+How it Works
+------------
+
+KernelSbom operates in two major phases:
+1. **Generate the cmd graph**, an acyclic directed dependency graph.
+2. **Generate SPDX documents** based on the cmd graph.
+
+KernelSbom begins from the root artifacts specified by the user, e.g.,
+`arch/x86/boot/bzImage`. For each root artifact, it collects all
+dependencies required to build that artifact. The dependencies come
+from multiple sources:
+
+- **`.cmd` files**: The primary source is the `.cmd` file of the
+ generated artifact, e.g., `arch/x86/boot/.bzImage.cmd`. These files
+ contain the exact command used to build the artifact and often include
+ an explicit list of input dependencies. By parsing the `.cmd` file,
+ the full list of dependencies can be obtained.
+
+- **`.incbin` statements**: The second source are include binary
+ `.incbin` statements in `.S` assembly files.
+
+- **Hardcoded dependencies**: Unfortunately, not all build dependencies
+ can be found via `.cmd` files and `.incbin` statements. Some build
+ dependencies are directly defined in Makefiles or Kbuild files.
+ Parsing these files is considered too complex for the scope of this
+ project. Instead, the remaining gaps of the graph are filled using a
+ list of manually defined dependencies, see
+ `sbom/cmd_graph/hardcoded_dependencies.py`. This list is known to be
+ incomplete. However, analysis of the cmd graph indicates a ~99%
+ completeness. For more information about the completeness analysis,
+ see [KernelSbom #95](https://github.com/TNG/KernelSbom/issues/95).
+
+Given the list of dependency files, KernelSbom recursively processes
+each file, expanding the dependency chain all the way to the version
+controlled source files. The result is a complete dependency graph
+where nodes represent files, and edges represent "file A was used to
+build file B" relationships.
+
+Using the cmd graph, KernelSbom produces three SPDX documents.
+For every file in the graph, KernelSbom:
+
+- Parses `SPDX-License-Identifier` headers,
+- Computes file hashes,
+- Estimates the file type based on extension and path,
+- Records build relationships between files.
+
+Each root output file is additionally associated with an SPDX Package
+element that captures version information, license data, and copyright.
+
+Advanced Usage
+--------------
+
+Including Kernel Modules
+------------------------
+
+The list of all `.ko` kernel modules produced during a build can be
+extracted from the `modules.order` file within the object tree.
+For example:
+
+ $ echo "arch/x86/boot/bzImage" > sbom-roots.txt
+ $ sed 's/\.o$/.ko/' ./kernel_build/modules.order >> sbom-roots.txt
+
+Then use the generated roots file:
+
+ $ SRCARCH=x86 python3 tools/sbom/sbom.py \
+ --src-tree . \
+ --obj-tree ./kernel_build \
+ --roots-file sbom-roots.txt \
+ --generate-spdx
+
+
+Equal Source and Object Trees
+------------------------------
+
+When the source tree and object tree are identical (for example, when
+building in-tree), source files can no longer be reliably distinguished
+from generated files.
+In this scenario, KernelSbom does not produce a dedicated
+`sbom-source.spdx.json` document. Instead, both source files and build
+artifacts are included together in `sbom-build.spdx.json`, and
+`sbom.used-files.txt` lists all files referenced in the build document.
+
+Unknown Build Commands
+----------------------
+
+Because the kernel supports a wide range of configurations and versions,
+KernelSbom may encounter build commands in `.cmd` files that it does
+not yet support. By default, KernelSbom will fail if an unknown build
+command is encountered.
+
+If you still wish to generate SPDX documents despite unsupported
+commands, you can use the `--do-not-fail-on-unknown-build-command`
+option. KernelSbom will continue and produce the documents, although
+the resulting SBOM will be incomplete.
+
+This option should only be used when the missing portion of the
+dependency graph is small and an incomplete SBOM is acceptable for
+your use case.
diff --git a/tools/sbom/sbom.py b/tools/sbom/sbom.py
new file mode 100644
index 000000000000..9c2e4c7f17ce
--- /dev/null
+++ b/tools/sbom/sbom.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0-only OR MIT
+# Copyright (C) 2025 TNG Technology Consulting GmbH
+
+"""
+Compute software bill of materials in SPDX format describing a kernel build.
+"""
+
+
+def main():
+ pass
+
+
+# Call main method
+if __name__ == "__main__":
+ main()
--
2.34.1 | {
"author": "Luis Augenstein <luis.augenstein@tngtech.com>",
"date": "Tue, 20 Jan 2026 12:53:39 +0100",
"thread_id": "6ed0fe99-3724-40c2-8d98-3309a3cf0104@tngtech.com.mbox.gz"
} |
lkml | [PATCH v2 00/14] Add SPDX SBOM generation tool | This patch series introduces a Python-based tool for generating SBOM
documents in the SPDX 3.0.1 format for kernel builds.
A Software Bill of Materials (SBOM) describes the individual components
of a software product. For the kernel, the goal is to describe the
distributable build outputs (typically the kernel image and modules),
the source files involved in producing these outputs, and the build
process that connects the source and output files.
To achieve this, the SBOM tool generates three SPDX documents:
- sbom-output.spdx.json
Describes the final build outputs together with high-level
build metadata.
- sbom-source.spdx.json
Describes all source files involved in the build, including
licensing information and additional file metadata.
- sbom-build.spdx.json
Describes the entire build process, linking source files
from the source SBOM to output files in the output SBOM.
The sbom tool is optional and runs only when CONFIG_SBOM is enabled. It
is invoked after the build, once all output artifacts have been
generated. Starting from the kernel image and modules as root nodes,
the tool reconstructs the dependency graph up to the original source
files. Build dependencies are primarily derived from the .cmd files
generated by Kbuild, which record the full command used to build
each output file.
Currently, the tool only supports x86 and arm64 architectures.
Co-developed-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Luis Augenstein <luis.augenstein@tngtech.com>
---
Changes in v2:
- regenerate sbom documents when build configuration changes
---
Luis Augenstein (14):
tools/sbom: integrate tool in make process
tools/sbom: setup sbom logging
tools/sbom: add command parsers
tools/sbom: add cmd graph generation
tools/sbom: add additional dependency sources for cmd graph
tools/sbom: add SPDX classes
tools/sbom: add JSON-LD serialization
tools/sbom: add shared SPDX elements
tools/sbom: collect file metadata
tools/sbom: add SPDX output graph
tools/sbom: add SPDX source graph
tools/sbom: add SPDX build graph
tools/sbom: add unit tests for command parsers
tools/sbom: add unit tests for SPDX-License-Identifier parsing
.gitignore | 1 +
MAINTAINERS | 6 +
Makefile | 15 +-
lib/Kconfig.debug | 9 +
tools/Makefile | 3 +-
tools/sbom/Makefile | 42 ++
tools/sbom/README | 208 ++++++
tools/sbom/sbom.py | 129 ++++
tools/sbom/sbom/__init__.py | 0
tools/sbom/sbom/cmd_graph/__init__.py | 7 +
tools/sbom/sbom/cmd_graph/cmd_file.py | 149 ++++
tools/sbom/sbom/cmd_graph/cmd_graph.py | 46 ++
tools/sbom/sbom/cmd_graph/cmd_graph_node.py | 142 ++++
tools/sbom/sbom/cmd_graph/deps_parser.py | 52 ++
.../sbom/cmd_graph/hardcoded_dependencies.py | 83 +++
tools/sbom/sbom/cmd_graph/incbin_parser.py | 42 ++
tools/sbom/sbom/cmd_graph/savedcmd_parser.py | 664 ++++++++++++++++++
tools/sbom/sbom/config.py | 335 +++++++++
tools/sbom/sbom/environment.py | 164 +++++
tools/sbom/sbom/path_utils.py | 11 +
tools/sbom/sbom/sbom_logging.py | 88 +++
tools/sbom/sbom/spdx/__init__.py | 7 +
tools/sbom/sbom/spdx/build.py | 17 +
tools/sbom/sbom/spdx/core.py | 182 +++++
tools/sbom/sbom/spdx/serialization.py | 56 ++
tools/sbom/sbom/spdx/simplelicensing.py | 20 +
tools/sbom/sbom/spdx/software.py | 71 ++
tools/sbom/sbom/spdx/spdxId.py | 36 +
tools/sbom/sbom/spdx_graph/__init__.py | 7 +
.../sbom/sbom/spdx_graph/build_spdx_graphs.py | 82 +++
tools/sbom/sbom/spdx_graph/kernel_file.py | 310 ++++++++
.../sbom/spdx_graph/shared_spdx_elements.py | 32 +
.../sbom/sbom/spdx_graph/spdx_build_graph.py | 317 +++++++++
.../sbom/sbom/spdx_graph/spdx_graph_model.py | 36 +
.../sbom/sbom/spdx_graph/spdx_output_graph.py | 188 +++++
.../sbom/sbom/spdx_graph/spdx_source_graph.py | 126 ++++
tools/sbom/tests/__init__.py | 0
tools/sbom/tests/cmd_graph/__init__.py | 0
.../tests/cmd_graph/test_savedcmd_parser.py | 383 ++++++++++
tools/sbom/tests/spdx_graph/__init__.py | 0
.../sbom/tests/spdx_graph/test_kernel_file.py | 32 +
41 files changed, 4096 insertions(+), 2 deletions(-)
create mode 100644 tools/sbom/Makefile
create mode 100644 tools/sbom/README
create mode 100644 tools/sbom/sbom.py
create mode 100644 tools/sbom/sbom/__init__.py
create mode 100644 tools/sbom/sbom/cmd_graph/__init__.py
create mode 100644 tools/sbom/sbom/cmd_graph/cmd_file.py
create mode 100644 tools/sbom/sbom/cmd_graph/cmd_graph.py
create mode 100644 tools/sbom/sbom/cmd_graph/cmd_graph_node.py
create mode 100644 tools/sbom/sbom/cmd_graph/deps_parser.py
create mode 100644 tools/sbom/sbom/cmd_graph/hardcoded_dependencies.py
create mode 100644 tools/sbom/sbom/cmd_graph/incbin_parser.py
create mode 100644 tools/sbom/sbom/cmd_graph/savedcmd_parser.py
create mode 100644 tools/sbom/sbom/config.py
create mode 100644 tools/sbom/sbom/environment.py
create mode 100644 tools/sbom/sbom/path_utils.py
create mode 100644 tools/sbom/sbom/sbom_logging.py
create mode 100644 tools/sbom/sbom/spdx/__init__.py
create mode 100644 tools/sbom/sbom/spdx/build.py
create mode 100644 tools/sbom/sbom/spdx/core.py
create mode 100644 tools/sbom/sbom/spdx/serialization.py
create mode 100644 tools/sbom/sbom/spdx/simplelicensing.py
create mode 100644 tools/sbom/sbom/spdx/software.py
create mode 100644 tools/sbom/sbom/spdx/spdxId.py
create mode 100644 tools/sbom/sbom/spdx_graph/__init__.py
create mode 100644 tools/sbom/sbom/spdx_graph/build_spdx_graphs.py
create mode 100644 tools/sbom/sbom/spdx_graph/kernel_file.py
create mode 100644 tools/sbom/sbom/spdx_graph/shared_spdx_elements.py
create mode 100644 tools/sbom/sbom/spdx_graph/spdx_build_graph.py
create mode 100644 tools/sbom/sbom/spdx_graph/spdx_graph_model.py
create mode 100644 tools/sbom/sbom/spdx_graph/spdx_output_graph.py
create mode 100644 tools/sbom/sbom/spdx_graph/spdx_source_graph.py
create mode 100644 tools/sbom/tests/__init__.py
create mode 100644 tools/sbom/tests/cmd_graph/__init__.py
create mode 100644 tools/sbom/tests/cmd_graph/test_savedcmd_parser.py
create mode 100644 tools/sbom/tests/spdx_graph/__init__.py
create mode 100644 tools/sbom/tests/spdx_graph/test_kernel_file.py
--
2.34.1
| Add logging infrastructure for warnings and errors.
Errors and warnings are accumulated and summarized in the end.
Co-developed-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Luis Augenstein <luis.augenstein@tngtech.com>
---
tools/sbom/sbom.py | 24 ++++++++-
tools/sbom/sbom/__init__.py | 0
tools/sbom/sbom/config.py | 47 ++++++++++++++++++
tools/sbom/sbom/sbom_logging.py | 88 +++++++++++++++++++++++++++++++++
4 files changed, 158 insertions(+), 1 deletion(-)
create mode 100644 tools/sbom/sbom/__init__.py
create mode 100644 tools/sbom/sbom/config.py
create mode 100644 tools/sbom/sbom/sbom_logging.py
diff --git a/tools/sbom/sbom.py b/tools/sbom/sbom.py
index 9c2e4c7f17ce..c7f23d6eb300 100644
--- a/tools/sbom/sbom.py
+++ b/tools/sbom/sbom.py
@@ -6,9 +6,31 @@
Compute software bill of materials in SPDX format describing a kernel build.
"""
+import logging
+import sys
+import sbom.sbom_logging as sbom_logging
+from sbom.config import get_config
+
def main():
- pass
+ # Read config
+ config = get_config()
+
+ # Configure logging
+ logging.basicConfig(
+ level=logging.DEBUG if config.debug else logging.INFO,
+ format="[%(levelname)s] %(message)s",
+ )
+
+ # Report collected warnings and errors in case of failure
+ warning_summary = sbom_logging.summarize_warnings()
+ error_summary = sbom_logging.summarize_errors()
+
+ if warning_summary:
+ logging.warning(warning_summary)
+ if error_summary:
+ logging.error(error_summary)
+ sys.exit(1)
# Call main method
diff --git a/tools/sbom/sbom/__init__.py b/tools/sbom/sbom/__init__.py
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tools/sbom/sbom/config.py b/tools/sbom/sbom/config.py
new file mode 100644
index 000000000000..3dc569ae0c43
--- /dev/null
+++ b/tools/sbom/sbom/config.py
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only OR MIT
+# Copyright (C) 2025 TNG Technology Consulting GmbH
+
+import argparse
+from dataclasses import dataclass
+
+
+@dataclass
+class KernelSbomConfig:
+ debug: bool
+ """Whether to enable debug logging."""
+
+
+def _parse_cli_arguments() -> dict[str, bool]:
+ """
+ Parse command-line arguments using argparse.
+
+ Returns:
+ Dictionary of parsed arguments.
+ """
+ parser = argparse.ArgumentParser(
+ description="Generate SPDX SBOM documents for kernel builds",
+ )
+ parser.add_argument(
+ "--debug",
+ action="store_true",
+ default=False,
+ help="Enable debug logs (default: False)",
+ )
+
+ args = vars(parser.parse_args())
+ return args
+
+
+def get_config() -> KernelSbomConfig:
+ """
+ Parse command-line arguments and construct the configuration object.
+
+ Returns:
+ KernelSbomConfig: Configuration object with all settings for SBOM generation.
+ """
+ # Parse cli arguments
+ args = _parse_cli_arguments()
+
+ debug = args["debug"]
+
+ return KernelSbomConfig(debug=debug)
diff --git a/tools/sbom/sbom/sbom_logging.py b/tools/sbom/sbom/sbom_logging.py
new file mode 100644
index 000000000000..3460c4d84626
--- /dev/null
+++ b/tools/sbom/sbom/sbom_logging.py
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only OR MIT
+# Copyright (C) 2025 TNG Technology Consulting GmbH
+
+import logging
+import inspect
+from typing import Any, Literal
+
+
+class MessageLogger:
+ """Logger that prints the first occurrence of each message immediately
+ and keeps track of repeated messages for a final summary."""
+
+ messages: dict[str, list[str]]
+ repeated_logs_limit: int
+ """Maximum number of repeated messages of the same type to log before suppressing further output."""
+
+ def __init__(self, level: Literal["error", "warning"], repeated_logs_limit: int = 3) -> None:
+ self._level = level
+ self.messages = {}
+ self.repeated_logs_limit = repeated_logs_limit
+
+ def log(self, template: str, /, **kwargs: Any) -> None:
+ """Log a message based on a template and optional variables."""
+ message = template.format(**kwargs)
+ if template not in self.messages:
+ self.messages[template] = []
+ if len(self.messages[template]) < self.repeated_logs_limit:
+ if self._level == "error":
+ logging.error(message)
+ elif self._level == "warning":
+ logging.warning(message)
+ self.messages[template].append(message)
+
+ def get_summary(self) -> str:
+ """Return summary of collected messages."""
+ if len(self.messages) == 0:
+ return ""
+ summary: list[str] = [f"Summarize {self._level}s:"]
+ for msgs in self.messages.values():
+ for i, msg in enumerate(msgs):
+ if i < self.repeated_logs_limit:
+ summary.append(msg)
+ continue
+ summary.append(
+ f"... (Found {len(msgs) - i} more {'instances' if (len(msgs) - i) != 1 else 'instance'} of this {self._level})"
+ )
+ break
+ return "\n".join(summary)
+
+
+_warning_logger: MessageLogger
+_error_logger: MessageLogger
+
+
+def warning(msg_template: str, /, **kwargs: Any) -> None:
+ """Log a warning message."""
+ _warning_logger.log(msg_template, **kwargs)
+
+
+def error(msg_template: str, /, **kwargs: Any) -> None:
+ """Log an error message including file, line, and function context."""
+ frame = inspect.currentframe()
+ caller_frame = frame.f_back if frame else None
+ info = inspect.getframeinfo(caller_frame) if caller_frame else None
+ if info:
+ msg_template = f'File "{info.filename}", line {info.lineno}, in {info.function}\n{msg_template}'
+ _error_logger.log(msg_template, **kwargs)
+
+
+def summarize_warnings() -> str:
+ return _warning_logger.get_summary()
+
+
+def summarize_errors() -> str:
+ return _error_logger.get_summary()
+
+
+def has_errors() -> bool:
+ return len(_error_logger.messages) > 0
+
+
+def init() -> None:
+ global _warning_logger, _error_logger
+ _warning_logger = MessageLogger("warning")
+ _error_logger = MessageLogger("error")
+
+
+init()
--
2.34.1 | {
"author": "Luis Augenstein <luis.augenstein@tngtech.com>",
"date": "Tue, 20 Jan 2026 12:53:40 +0100",
"thread_id": "6ed0fe99-3724-40c2-8d98-3309a3cf0104@tngtech.com.mbox.gz"
} |
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