source large_stringclasses 2
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lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Fri, Jan 30, 2026 at 06:34:37PM +0200, Adrian Hunter wrote:
Does your device Hierarchy look like
PCI device
|
-----------------
HCI1 HCI2
| |
I3C M1 I3C M2
You want HCI1 and HCI2 suspened only when both HCI1 and HCI2 can enter R... | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Mon, 2 Feb 2026 11:25:23 -0500",
"thread_id": "20260129181841.130864-1-adrian.hunter@intel.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McAS... | Simplify the mcasp_set_clk_pdir caller convention in start/stop stream
function, to make it so that set_clk_pdir gets called regardless when
stream starts and also disables when stream ends.
Functionality-wise, everything remains the same as the previously skipped
calls are now either correctly configured
(when McASP ... | {
"author": "Sen Wang <sen@ti.com>",
"date": "Thu, 29 Jan 2026 23:10:43 -0600",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McAS... | The current mcasp_is_synchronous() function does more than what it
proclaims, it also checks if McASP is a frame producer.
Therefore split the original function into two separate ones and
replace all occurrences with the new equivalent logic. So the functions
can be re-used when checking async/sync status in light of ... | {
"author": "Sen Wang <sen@ti.com>",
"date": "Thu, 29 Jan 2026 23:10:42 -0600",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McAS... | McASP supports the independent configuration of TX & RX clk and frame
sync registers. By default, the driver is configured in synchronous mode
where RX clock generator is disabled and it uses transmit clock signals as
bit clock and frame sync. Therefore add optional properties needed for
asynchronous mode.
Add ti,asyn... | {
"author": "Sen Wang <sen@ti.com>",
"date": "Thu, 29 Jan 2026 23:10:41 -0600",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McAS... | McASP has dedicated clock & frame sync registers for both transmit
and receive. Currently McASP driver only supports synchronous behavior and
couples both TX & RX settings.
Add logic that enables asynchronous mode via ti,async-mode property. In
async mode, playback & record can be done simultaneously with different
au... | {
"author": "Sen Wang <sen@ti.com>",
"date": "Thu, 29 Jan 2026 23:10:44 -0600",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McAS... | On Thu, Jan 29, 2026 at 11:10:41PM -0600, Sen Wang wrote:
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resembl... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Mon, 2 Feb 2026 12:44:32 +0000",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McAS... | On 30/01/2026 07:10, Sen Wang wrote:
True, the naming was not too precise. It is tasked to decide if the TX
clock needs to be enabled for RX operation, which precisely when McASP
is in synchronous mode _and_ it is clock provider.
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
davinci_mcasp *mcasp, u32 ctl_reg,... | {
"author": "=?UTF-8?Q?P=C3=A9ter_Ujfalusi?= <peter.ujfalusi@gmail.com>",
"date": "Mon, 2 Feb 2026 18:42:20 +0200",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McAS... | On 30/01/2026 07:10, Sen Wang wrote:
I'm not sure about this, but the sequence should be preserved, PDIR
change first.
--
Péter | {
"author": "=?UTF-8?Q?P=C3=A9ter_Ujfalusi?= <peter.ujfalusi@gmail.com>",
"date": "Mon, 2 Feb 2026 18:49:40 +0200",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH 0/4] ASoC: ti: davinci-mcasp: Add asynchronous mode support for McASP | This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.
It also adds two clean up patches to the McAS... | On 30/01/2026 07:10, Sen Wang wrote:
static void mcasp_start_rx(struct davinci_mcasp *mcasp)
In new code - while it might not match with old code - use producer
instead of master.
Otherwise it looks nice, I trust you have tested the sync and DIT mode.
With this nitpick addressed:
Acked-by: Peter Ujfalusi <peter.u... | {
"author": "=?UTF-8?Q?P=C3=A9ter_Ujfalusi?= <peter.ujfalusi@gmail.com>",
"date": "Mon, 2 Feb 2026 19:02:31 +0200",
"thread_id": "ffcbbe3b-3a1b-4986-8b4c-b0f7e309ccbb@gmail.com.mbox.gz"
} |
lkml | [PATCH] sched_ext: Fix NULL pointer deref and warnings during scx teardown | When a BPF scheduler is being disabled, scx_root can be set to NULL
while tasks are still associated with the sched_ext class. If a task is
subject to an affinity change, priority adjustment, or policy switch
during this window, sched_class operations will dereference a NULL
scx_root pointer, triggering a BUG like the ... | Hello,
On Mon, Feb 02, 2026 at 04:13:41PM +0100, Andrea Righi wrote:
I don't quite understand how this would happen. set_cpu_allowed_scx() is
called from do_set_cpus_allowed() with task_rq locked. ie. the task *has* to
be on sched_ext for it to be called. It's straightforward task rq lock
synchronization, so there's ... | {
"author": "Tejun Heo <tj@kernel.org>",
"date": "Mon, 2 Feb 2026 07:10:02 -1000",
"thread_id": "aYDaao9Xb_Bkv0NH@slm.duckdns.org.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | These parameters can be discovered from a config register. As they will
not be used any more, mark them deprecated, make them optional, and
remove them from the example.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
Documentation/devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++------
1 file changed, 2 in... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:23:14 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++++++---------------------
1 file... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:23:15 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On Thu, Jan 29, 2026 at 12:23:15PM -0500, Sean Anderson wrote:
Given that the properties already exist it seems wise to continue to
parse them if available and prefer them over what we read from the
hardware, it would not shock me to discover that hardware exists where
the registers are inaccurate or need overriding... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 17:27:58 +0000",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 29 Jan 2026 17:37:09 +0000",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | I don't know this device at all, so i might be asking dumb
questions....
It is possible that the device supports multiple channels, but the use
case is mono, and so xlnx,num-channels is 1 in DT? Would that break
given your change?
Could it be the device supports 24 bits, but the use case only wants
16, and so has th... | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Thu, 29 Jan 2026 18:37:30 +0100",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On 1/29/26 12:27, Mark Brown wrote:
I would be surprised if such hardware exists. These properties are
automatically generated by Xilinx's tools based on the HDL core's
properties. This has a few consequences:
- They always exactly match the hardware unless someone has gone in and
modified them. I think this is unl... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:46:27 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On 1/29/26 12:37, Andrew Lunn wrote:
drv_data->channels is multiplied by 2, so there is always an even number
of channels. Pairs of channels are always muxed together and AFAICT
there's no way to disable them individually.
I don't think that's possible. There's an option to output 32-bit audio,
but none to reduce 24... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:51:47 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On Thu, Jan 29, 2026 at 12:46:27PM -0500, Sean Anderson wrote:
I'm not sure I follow your second point - driver authors tend to use
what?
I'd still rather see the properties get used if present, worst case
they're redundant best case we avoid regressing a currently working
system. The code is already there, ... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 18:09:28 +0000",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On 1/29/26 13:09, Mark Brown wrote:
Authors look at the devicetree node and see something like
i2s0_tx: i2s_transmitter@80120000 {
aud_mclk = <99999001>;
clock-names = "aud_mclk", "s_axi_ctrl_aclk", "s_axis_aud_aclk";
clocks = <&zynqmp_clk 74>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
compatible = "xlnx,i2s-tran... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 13:17:45 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On Thu, Jan 29, 2026 at 01:17:45PM -0500, Sean Anderson wrote:
Oh. If the properties are there it's reasonable and sensible to use
them, them being redundant is a concern when specifying the binding but
once things are there any discrepency should usually be resolved in
favour of the binding.
We're talking a ... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 18:46:23 +0000",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On Thu, Jan 29, 2026 at 12:46:27PM -0500, Sean Anderson wrote:
Does version 0.0 of this IP core have this register? Its not a new
addition?
Is there a synthesis option to disable this register?
Andrew | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Thu, 29 Jan 2026 20:58:19 +0100",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On 1/29/26 14:58, Andrew Lunn wrote:
As far as I know, this register was present in 1.0 revision 0. I
reviewed the changelog for the core as well as the product guide
changelog and found no mention of any register additions.
No.
--Sean | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 15:13:07 -0500",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | Hi Sean,
kernel test robot noticed the following build errors:
[auto build test ERROR on broonie-sound/for-next]
[also build test ERROR on broonie-spi/for-next linus/master v6.19-rc7 next-20260129]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when su... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Fri, 30 Jan 2026 14:35:30 +0800",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | +Katta, Vishal
On 1/29/26 19:46, Mark Brown wrote:
Let me add our driver owner of this device to answer some questions.
Katta: Can you please look at it?
Thanks,
Michal | {
"author": "Michal Simek <michal.simek@amd.com>",
"date": "Fri, 30 Jan 2026 09:19:26 +0100",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | Hi,
>> and go "Ah, there are the properties I need." On some Xilinx cores this
>> is the only way to discover certain properties, so people have gotten into
>> the habit of using them even when these properties can be read from the
>> device itself.
> Oh. If the properties are there it's reasonable and sensible... | {
"author": "Peter Korsgaard <peter@korsgaard.com>",
"date": "Mon, 02 Feb 2026 18:52:27 +0100",
"thread_id": "20260129172315.3871602-1-sean.anderson@linux.dev.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | The implementation of __READ_ONCE() under CONFIG_LTO=y incorrectly
qualified the fallback "once" access for types larger than 8 bytes,
which are not atomic but should still happen "once" and suppress common
compiler optimizations.
The cast `volatile typeof(__x)` applied the volatile qualifier to the
pointer type itsel... | {
"author": "Marco Elver <elver@google.com>",
"date": "Fri, 30 Jan 2026 14:28:24 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | Rework arm64 LTO __READ_ONCE() to improve code generation as follows:
1. Replace _Generic-based __unqual_scalar_typeof() with more complete
__rwonce_typeof_unqual(). This strips qualifiers from all types, not
just integer types, which is required to be able to assign (must be
non-const) to __u.__val in the no... | {
"author": "Marco Elver <elver@google.com>",
"date": "Fri, 30 Jan 2026 14:28:25 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | When enabling Clang's Context Analysis (aka. Thread Safety Analysis) on
kernel/futex/core.o (see Peter's changes at [1]), in arm64 LTO builds we
could see:
| kernel/futex/core.c:982:1: warning: spinlock 'atomic ? __u.__val : q->lock_ptr' is still held at the end of function [-Wthread-safety-analysis]
| 982 | }
| ... | {
"author": "Marco Elver <elver@google.com>",
"date": "Fri, 30 Jan 2026 14:28:26 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | On Fri, 30 Jan 2026 14:28:24 +0100
Marco Elver <elver@google.com> wrote:
I found this in some testing (on godbolt), so:
Tested-by: David Laight <david.laight.linux@gmail.com> | {
"author": "David Laight <david.laight.linux@gmail.com>",
"date": "Fri, 30 Jan 2026 15:06:58 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | On Fri, 30 Jan 2026 14:28:25 +0100
Marco Elver <elver@google.com> wrote:
Having most of the comment in the commit message and a short one in the
code look good.
I think it will also fix a 'bleat' from min() about a signed v unsigned compare.
The ?: causes 'u8' to be promoted to 'int' with the expected outcome.
Revi... | {
"author": "David Laight <david.laight.linux@gmail.com>",
"date": "Fri, 30 Jan 2026 15:11:30 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | On Fri, 30 Jan 2026 14:28:26 +0100
Marco Elver <elver@google.com> wrote:
LGTM (for an obscure definition of G).
Reviewed-by: David Laight <david.laight.linux@gmail.com> | {
"author": "David Laight <david.laight.linux@gmail.com>",
"date": "Fri, 30 Jan 2026 15:13:34 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | On Fri, Jan 30, 2026 at 02:28:25PM +0100, Marco Elver wrote:
I know that CONFIG_LTO practically depends on Clang, but it's a bit
grotty relying on that assumption here. Ideally, it would be
straightforward to enable the strong READ_ONCE() semantics on arm64
regardless of the compiler.
Since we're not providing acqui... | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 15:36:40 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | On Fri, Jan 30, 2026 at 02:28:26PM +0100, Marco Elver wrote:
What does GCC do with this? :/
Will | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 15:39:36 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | On Mon, Feb 02, 2026 at 03:36:40PM +0000, Will Deacon wrote:
We are?
---
commit fd69b2f7d5f4e1d89cea4cdfa6f15e7fa53d8358
Author: Peter Zijlstra <peterz@infradead.org>
Date: Fri Jan 16 19:18:16 2026 +0100
compiler: Use __typeof_unqual__() for __unqual_scalar_typeof()
The recent changes to get_unalign... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Mon, 2 Feb 2026 17:01:39 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | On Mon, Feb 02, 2026 at 05:01:39PM +0100, Peter Zijlstra wrote:
Great! Then I don't grok why we need to choose between
__unqual_scalar_typeof() and __typeof_unqual__() in the arch code. We
should just use the former and it will DTRT.
Will | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 16:05:38 +0000",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] arm64: Fixes for __READ_ONCE() with CONFIG_LTO=y | While investigating a Clang Context Analysis [1] false positive [2], I started
to dig deeper into arm64's __READ_ONCE() implementation with LTO. That rabbit
hole led me to find one critical bug with the current implementation (patch 1),
and subtle improvements that then enabled me to fix the original false positive.
P... | On Mon, Feb 02, 2026 at 03:36:40PM +0000, Will Deacon wrote:
Does it matter for GCC versions that do not support LTO? Because I'm
quite sure that if, one day, we add support for GCC LTO, that GCC
version will be new enough that it'll just take the __typeof_unqual__()
version and it'll "just work".
The problem with ol... | {
"author": "Marco Elver <elver@google.com>",
"date": "Mon, 2 Feb 2026 18:48:47 +0100",
"thread_id": "aYDjf8apiadheFuM@elver.google.com.mbox.gz"
} |
lkml | [PATCH 0/2] Add HPET NMI Watchdog support | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anyt... | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anyt... | {
"author": "Alexander Graf <graf@amazon.com>",
"date": "Mon, 2 Feb 2026 17:48:01 +0000",
"thread_id": "20260202174803.66640-1-graf@amazon.com.mbox.gz"
} |
lkml | [PATCH 0/2] Add HPET NMI Watchdog support | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anyt... | To implement an HPET based NMI watchdog, the HPET code will need to
reconfigure an IOAPIC pin to NMI mode. Add a function that allows driver
code to configure an IOAPIC pin for NMI delivery mode.
The caller can choose whether to invoke NMIs on the BSP or broadcast on
all CPUs in the system.
(Disclaimer: Some of this ... | {
"author": "Alexander Graf <graf@amazon.com>",
"date": "Mon, 2 Feb 2026 17:48:02 +0000",
"thread_id": "20260202174803.66640-1-graf@amazon.com.mbox.gz"
} |
lkml | [PATCH 0/2] Add HPET NMI Watchdog support | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anyt... | The traditional NMI watchdog timer uses performance counters to trigger
periodic NMIs. But performance counters are a scarce resource that are
best used for actual performance counting. However, the HPET is another
timer source on most modern x86 systems that can inject NMI interrupts.
Add support for using HPET timer... | {
"author": "Alexander Graf <graf@amazon.com>",
"date": "Mon, 2 Feb 2026 17:48:03 +0000",
"thread_id": "20260202174803.66640-1-graf@amazon.com.mbox.gz"
} |
lkml | [PATCH 0/2] Add HPET NMI Watchdog support | The current NMI watchdog relies on performance counters and consistently
occupies one on each CPU. When running virtual machines, we want to pass
performance counters to virtual machines so they can make use of them.
In addition the host system wants to use performance counters to check
the system to identify when anyt... | On 02.02.26 18:43, Alexander Graf wrote:
Sorry for the resend. I caught an issue while sending out the series,
hit ctrl-c before thinking and suddenly had a half sent series. Discard
this one. Happy review on the real, full one :)
Alex
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10... | {
"author": "Alexander Graf <graf@amazon.com>",
"date": "Mon, 2 Feb 2026 18:49:13 +0100",
"thread_id": "20260202174803.66640-1-graf@amazon.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock
operations, such as setting the rate or switching parents. However,
another operation that can and often does touch actual hardware state is
recalc_rate, which may also be affected by such a dependency.
Add parent enables/disables where the recalc_rat... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:09 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | Passing the struct device pointer to clk_hw_register allows for runtime
power management to work for the registered clock controllers. However,
the mediatek PLL clocks do not do this.
Change this by adding a struct device pointer argument to
mtk_clk_register_pll, and fix up the only other user of it. Also add a
new me... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:11 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | After refactoring all of PLL to pass the device, it's now fairly easy to
refactor pllfh and its users, as pllfh registration wraps PLL
registration.
Do this refactor and move all of the pllfh users to pass the device as
well.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:12 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | As it stands, mtk_clk_register_plls takes a struct device_node pointer
as its first argument. This is a tragic happenstance, as it's trivial to
get the device_node from a struct device, but the opposite not so much.
The struct device is a much more useful thing to have passed down.
Refactor mtk_clk_register_plls to ta... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:10 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | All the MFGPLL require MFG_EB to be on for any operation on them, and
they only tick when MFG_EB is on as well, therefore making this a
parent-child relationship.
This dependency wasn't clear during the initial upstreaming of these
clock controllers, as it only made itself known when I could observe
the effects of the... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 10 Oct 2025 22:47:13 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | Hi Nicolas,
On Fri, Oct 10, 2025 at 10:47:09PM +0200, Nicolas Frattaroli wrote:
clk_change_rate() has the following code:
if (core->flags & CLK_OPS_PARENT_ENABLE)
clk_core_prepare_enable(parent);
...
core->rate = clk_recalc(core, best_parent_rate);
...
if (core->flags &... | {
"author": "Brian Masney <bmasney@redhat.com>",
"date": "Thu, 16 Oct 2025 16:52:30 -0400",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Thursday, 16 October 2025 22:52:30 Central European Summer Time Brian Masney wrote:
I don't see how multiple prepares are a problem as long as they're
balanced.
__clk_core_init also needs special code in that case, as it calls the
bare recalc_rate op with no clk_core_enable_lock beforehand. It's also
wrong, in th... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Fri, 17 Oct 2025 14:21:55 +0200",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | Hi Nicolas,
On Fri, Oct 17, 2025 at 02:21:55PM +0200, Nicolas Frattaroli wrote:
I agree and that makes sense. Thanks for the explanation. What you have
is a good compromise.
Reviewed-by: Brian Masney <bmasney@redhat.com> | {
"author": "Brian Masney <bmasney@redhat.com>",
"date": "Mon, 20 Oct 2025 15:36:41 -0400",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Fri, Oct 10, 2025 at 10:47:09PM +0200, Nicolas Frattaroli wrote:
I'm seeing boot regressions in -next on the Avenger96 which bisect to
this patch in -next. The board resets during startup:
[ 0.297034] /soc/display-controller@5a001000: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@5c002000/hdmi-transmitt... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Tue, 27 Jan 2026 17:01:29 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Tue, Jan 27, 2026 at 05:01:35PM +0000, Mark Brown wrote:
I am also seeing some similar regressions even earlier on i.MX8MP
platforms, though they're resetting even earlier before any output is
produced (even with earlycon). Didn't confirm yet with a revert or
anything though. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Tue, 27 Jan 2026 17:25:04 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Tuesday, 27 January 2026 18:25:04 Central European Standard Time Mark Brown wrote:
Someone else seemingly bisected to this commit on i.MX8MP as well
and replied to the RESEND of the series, and confirmed with a
revert[1].
I'm somewhat surprised by this, because to me it doesn't make intuitive
sense that some platf... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Tue, 27 Jan 2026 19:18:02 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Tue, Jan 27, 2026 at 07:18:02PM +0100, Nicolas Frattaroli wrote:
Do you have a debugging patch we could run which would say which clocks
are impacted? I guess it's more of an issue for the platforms that give
no output but for at least Avenger96 I was getting earlycon output.
Please, this is making my test lab ... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Tue, 27 Jan 2026 23:14:29 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Wednesday, 28 January 2026 00:14:29 Central European Standard Time Mark Brown wrote:
Try this one
---
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 1b0f9d567f48..fa1443517768 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1921,13 +1921,21 @@ static unsigned long clk_recalc(struct clk_core *co... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Wed, 28 Jan 2026 15:09:46 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Wed, Jan 28, 2026 at 03:09:46PM +0100, Nicolas Frattaroli wrote:
For the Avenger96 that says:
[ 0.347816] __clk_core_init: enabling parent ck_hse for ck_per
[ 0.352230] __clk_core_init: disabling parent ck_hse for ck_per
[ 0.358207] __clk_core_init: enabling parent pll1_p for ck_mpu
[ 0.364005] __clk... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 28 Jan 2026 14:47:08 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | Hi everyone,
Am Mittwoch, 28. Januar 2026, 15:47:08 CET schrieb Mark Brown:
This is for TQMa8MPxL/MBa8MPxL:
[ 1.452788] __clk_core_init: enabling parent audio_pll1_out for clkout1_sel
[ 1.457677] __clk_core_init: disabling parent audio_pll1_out for clkout1_sel
[ 1.464270] __clk_core_init: enabling parent au... | {
"author": "Alexander Stein <alexander.stein@ew.tq-group.com>",
"date": "Wed, 28 Jan 2026 15:55:54 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Wed, Jan 28, 2026 at 03:55:54PM +0100, Alexander Stein wrote:
As expected same result on i.MX8MP-EVK. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 28 Jan 2026 15:21:47 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Wednesday, 28 January 2026 15:47:08 Central European Standard Time Mark Brown wrote:
Okay, on this one, there may be a problem in the clock tree.
ck_mpu is marked CLK_IS_CRITICAL, but its parent, pll1_p, is not. Clock
core doesn't seem to check whether any children of a clock are marked as
critical before disabling... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Wed, 28 Jan 2026 17:04:55 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Wednesday, 28 January 2026 16:21:47 Central European Standard Time Mark Brown wrote:
This one puzzles me a little. arm_a53_div is neither marked critical
nor is its parent. If arm_a53_div is required for the system to function,
then I'd have expected at least it to be marked as critical, allowing us
to do the worka... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Wed, 28 Jan 2026 17:31:35 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Wed, Jan 28, 2026 at 05:31:35PM +0100, Nicolas Frattaroli wrote:
Given that all the cores in the system are A53s I rather fear that it is
in fact critical and should be marked as such. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 28 Jan 2026 17:08:28 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | Quoting Nicolas Frattaroli (2026-01-28 09:04:55)
Marking parents critical hasn't been strictly necessary so far because
we've been relying on the prepare/enable count on a critical child to
keep the parent prepared/enabled.
The parent may not be known yet in __clk_core_init() because we lazily
find parents. Putting ... | {
"author": "Stephen Boyd <sboyd@kernel.org>",
"date": "Wed, 28 Jan 2026 12:01:22 -0700",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Wednesday, 28 January 2026 20:01:22 Central European Standard Time Stephen Boyd wrote:
In this instance, it doesn't seem like the parent pointer is null, since
it does print a parent clock name. I think the problem really is that the
parent gets disabled before the CLK_IS_CRITICAL check re-enables it.
The issue b... | {
"author": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>",
"date": "Wed, 28 Jan 2026 20:59:24 +0100",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH v3 0/5] MediaTek PLL Refactors and Fixes | This series refactors all users of mtk-pll, just so we can enable
runtime power management for the clock controllers that want it. It's
also generally more useful to have the struct device in the pll code,
rather than the device node.
Also fix up MT8196 mfgpll to declare its parent-child relationship with
mfg_eb, and ... | On Wed, Jan 28, 2026 at 12:01:22PM -0700, Stephen Boyd wrote:
The patch is still in -next today and the issues it causes are still
visible. | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Mon, 2 Feb 2026 16:54:32 +0000",
"thread_id": "20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com.mbox.gz"
} |
lkml | [PATCH] tracing: remove __printf() attribute on __ftrace_vbprintk() | From: Arnd Bergmann <arnd@arndb.de>
The sunrpc change to use trace_printk() for debugging caused
a new warning for every instance of dprintk() in some configurations,
when -Wformat-security is enabled:
fs/nfs/getroot.c: In function 'nfs_get_root':
fs/nfs/getroot.c:90:17: error: format not a string literal and no form... | On Mon, 2026-02-02 at 10:58 +0100, Arnd Bergmann wrote:
Acked-by: Jeff Layton <jlayton@kernel.org> | {
"author": "Jeff Layton <jlayton@kernel.org>",
"date": "Mon, 02 Feb 2026 06:37:56 -0500",
"thread_id": "20260202125959.49ce289f@gandalf.local.home.mbox.gz"
} |
lkml | [PATCH] tracing: remove __printf() attribute on __ftrace_vbprintk() | From: Arnd Bergmann <arnd@arndb.de>
The sunrpc change to use trace_printk() for debugging caused
a new warning for every instance of dprintk() in some configurations,
when -Wformat-security is enabled:
fs/nfs/getroot.c: In function 'nfs_get_root':
fs/nfs/getroot.c:90:17: error: format not a string literal and no form... | On Mon, Feb 02, 2026 at 10:58:27AM +0100, Arnd Bergmann wrote:
Yeah, it was discussed in the past that binary printf() should not be annotated
as we have BPF code that doesn't compile (with the default WERROR=y).
--
With Best Regards,
Andy Shevchenko | {
"author": "Andy Shevchenko <andriy.shevchenko@linux.intel.com>",
"date": "Mon, 2 Feb 2026 19:57:21 +0200",
"thread_id": "20260202125959.49ce289f@gandalf.local.home.mbox.gz"
} |
lkml | [PATCH] tracing: remove __printf() attribute on __ftrace_vbprintk() | From: Arnd Bergmann <arnd@arndb.de>
The sunrpc change to use trace_printk() for debugging caused
a new warning for every instance of dprintk() in some configurations,
when -Wformat-security is enabled:
fs/nfs/getroot.c: In function 'nfs_get_root':
fs/nfs/getroot.c:90:17: error: format not a string literal and no form... | On Mon, 2 Feb 2026 10:58:27 +0100
Arnd Bergmann <arnd@kernel.org> wrote:
Acked-by: Steven Rostedt (Google) <rostedt@goodmis.org>
-- Steve | {
"author": "Steven Rostedt <rostedt@goodmis.org>",
"date": "Mon, 2 Feb 2026 12:59:59 -0500",
"thread_id": "20260202125959.49ce289f@gandalf.local.home.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch wit... | Add documentation and an example for MaxLinear MxL86282 and MxL86252
switches.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
v12: no changes
v11: no changes
v10: add microcontroller port 0
v9: no changes
v8: no changes
v7: no changes
v6: no changes
v5: no chan... | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Sun, 1 Feb 2026 02:24:47 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch wit... | Add proprietary special tag format for the MaxLinear MXL862xx family of
switches. While using the same Ethertype as MaxLinear's GSW1xx switches,
the actual tag format differs significantly, hence we need a dedicated
tag driver for that.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v12: no changes
v11:
* ar... | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Sun, 1 Feb 2026 02:24:56 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch wit... | Add helper inline functions __mdiodev_c45_read() and
__mdiodev_c45_write(), which are the C45 equivalents of the existing
__mdiodev_read() and __mdiodev_write() added by commit e6a45700e7e1
("net: mdio: add unlocked mdiobus and mdiodev bus accessors")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v12: no cha... | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Sun, 1 Feb 2026 02:25:03 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch wit... | Add very basic DSA driver for MaxLinear's MxL862xx switches.
In contrast to previous MaxLinear switches the MxL862xx has a built-in
processor that runs a sophisticated firmware based on Zephyr RTOS.
Interaction between the host and the switch hence is organized using a
software API of that firmware rather than accessi... | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Sun, 1 Feb 2026 02:25:13 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch wit... | On Sun, Feb 01, 2026 at 02:25:13AM +0000, Daniel Golle wrote:
I have nothing else to comment except to request you to undo some of the
changes requested by AI review. Sorry I didn't have time to comment on v11.
I'm sorry, I can't accept code that fears its own shadow. Some people,
when they see a defensive NULL chec... | {
"author": "Vladimir Oltean <olteanv@gmail.com>",
"date": "Mon, 2 Feb 2026 12:23:26 +0200",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch wit... | On Sun, Feb 01, 2026 at 02:25:03AM +0000, Daniel Golle wrote:
Sigh, there's too many versions of this patch series. While netdev has
a 24H period, there is also this - note the last sentence. The reason
this exists is to stop this exact problem, where ongoing discussion is
split across multiple different versions of t... | {
"author": "\"Russell King (Oracle)\" <linux@armlinux.org.uk>",
"date": "Mon, 2 Feb 2026 11:08:39 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v12 0/4] net: dsa: initial support for MaxLinear MxL862xx
switches | This series adds very basic DSA support for the MaxLinear MxL86252
(5x 2500Base-T PHYs) and MxL86282 (8x 2500Base-T PHYs) switches.
In addition to the 2.5G TP ports both switches also come with two
SerDes interfaces which can be used either to connect external PHYs
or SFP cages, or as CPU port when using the switch wit... | On Mon, Feb 02, 2026 at 12:23:26PM +0200, Vladimir Oltean wrote:
Now that ports are counted from 0, and 0 being the microcontroller, the
port number no longer matches the PHY ID, so I suppose I got to change
the dt-bindigns as that kinda makes the mdio node mandatory for anything
to work.
Looking at other drivers I ... | {
"author": "Daniel Golle <daniel@makrotopia.org>",
"date": "Mon, 2 Feb 2026 18:09:17 +0000",
"thread_id": "cover.1769908155.git.daniel@makrotopia.org.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.
The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optio... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:10 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.
This provides a more convenient API for... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:11 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.
Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.
Signed-off-by:... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:12 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.
Core clk is now properly managed alongside the other ... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:13 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.
Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactiva... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:14 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle
the attachment of power domains. This often leads to duplicated code
logic across different driver probe functions.
Introduce a new helper API, geni_se_domain_attach(), to centralize
the logic for attaching "power" and "perf" domains to the GENI SE... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:15 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently
manage performance levels and operating points directly. This resulting
in code duplication across drivers. such as configuring a specific level
or find and apply an OPP based on a clock frequency.
Introduce two new helper APIs, geni_se_set_perf_leve... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:16 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add DT bindings for the QUP GENI I2C controller on sa8255p platforms.
SA8255p platform abstracts resources such as clocks, interconnect and
GPIO pins configuration in Firmware. SCMI power and perf protocol
are utilized to request resource configurations.
SA8255p platform does not require the Serial Engine (SE) common... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:17 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Moving the serial engine setup to geni_i2c_init() API for a cleaner
probe function and utilizes the PM runtime API to control resources
instead of direct clock-related APIs for better resource management.
Enables reusability of the serial engine initialization like
hibernation and deep sleep features where hardware co... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:18 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Refactor the resource initialization in geni_i2c_probe() by introducing
a new geni_i2c_resources_init() function and utilizing the common
geni_se_resources_init() framework and clock frequency mapping, making the
probe function cleaner.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Pravee... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:19 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To manage GENI serial engine resources during runtime power management,
drivers currently need to call functions for ICC, clock, and
SE resource operations in both suspend and resume paths, resulting in
code duplication across drivers.
The new geni_se_resources_activate() and geni_se_resources_deactivate()
helper APIs... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:20 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To avoid repeatedly fetching and checking platform data across various
functions, store the struct of_device_id data directly in the i2c
private structure. This change enhances code maintainability and reduces
redundancy.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <prave... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:21 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:22 +0530",
"thread_id": "20260202180922.1692428-10-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical ad... | On Fri, Jan 30, 2026 at 06:49:00PM +0500, Mikhail Gavrilov wrote:
Why add a second loop instead of using the existing one? | {
"author": "Matthew Wilcox <willy@infradead.org>",
"date": "Fri, 30 Jan 2026 13:59:47 +0000",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical ad... | On Fri, Jan 30, 2026 at 6:59 PM Matthew Wilcox <willy@infradead.org> wrote:
You're right, no good reason for a separate loop.
Here's v2:
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index cbf758e27aa2..306493d76ea4 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -3122,8 +3122,17 @@ void split_page(struct page... | {
"author": "Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>",
"date": "Fri, 30 Jan 2026 19:16:37 +0500",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical ad... | On Fri, Jan 30, 2026 at 9:49 PM Mikhail Gavrilov
<mikhail.v.gavrilov@gmail.com> wrote:
Hi Mikhail,
Thanks for reporting this issue.
So the problem starts with `swap_map = vzalloc(maxpages);` right? Will
it be enough if we just pass GFP_COMP here?
And worth noting, mm/swapfile.c already have following code:
/*
* P... | {
"author": "Kairui Song <ryncsn@gmail.com>",
"date": "Fri, 30 Jan 2026 23:30:33 +0800",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical ad... | On Fri, Jan 30, 2026 at 8:31 PM Kairui Song <ryncsn@gmail.com> wrote:
No, __GFP_COMP won't help here. vmalloc always calls split_page() for
high-order allocations to treat them as independent pages (see
mm/vmalloc.c around line 3730). The compound page would be split
anyway.
Yes, this comment is the root of the prob... | {
"author": "Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>",
"date": "Fri, 30 Jan 2026 20:47:39 +0500",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical ad... | On Fri, Jan 30, 2026 at 11:47 PM Mikhail Gavrilov
<mikhail.v.gavrilov@gmail.com> wrote:
Right, but with __GFP_COMP, prep_compound_page clears the tail pages'
private too, so the code snip I posted will clear their lru on use?
I took a look at the history, commit 3b8000ae185c ("mm/vmalloc: huge
vmalloc backing pages ... | {
"author": "Kairui Song <ryncsn@gmail.com>",
"date": "Mon, 2 Feb 2026 11:17:57 +0800",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical ad... | On Mon, Feb 2, 2026 at 8:18 AM Kairui Song <ryncsn@gmail.com> wrote:
You're right that prep_compound_tail() clears page->private for tail
pages. But the issue is that vmalloc explicitly avoids __GFP_COMP -
see commit 3b8000ae185c ("mm/vmalloc: huge vmalloc backing pages
should be split rather than compound"). So prep_... | {
"author": "Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>",
"date": "Mon, 2 Feb 2026 10:27:01 +0500",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [RFC PATCH] mm/page_alloc: fix use-after-free in swap due to stale
page data after split_page() | Hi,
I've been debugging a use-after-free bug in the swap subsystem that manifests
as a crash in free_swap_count_continuations() during swapoff on zram devices.
== Problem ==
KASAN reports wild-memory-access at address 0xdead000000000100 (LIST_POISON1):
Oops: general protection fault, probably for non-canonical ad... | On Mon, Feb 2, 2026 at 1:27 PM Mikhail Gavrilov
<mikhail.v.gavrilov@gmail.com> wrote:
Right, then I think we need a Fixes tag, and is swap really the only
victim of that change? BTW, swap's usage of page->lru will be gone
soon. Still this definitely needs to be fixed first for stable branch, but
it looks strange why n... | {
"author": "Kairui Song <ryncsn@gmail.com>",
"date": "Tue, 3 Feb 2026 01:54:26 +0800",
"thread_id": "CAMgjq7COo_-xJwXvy4sLjRHmb6VohMHub0TctS3M+gKwrfjPSg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
... | On Sunday 01 February 2026 23:37:37 Kurt Borja wrote:
Hello, please keep codes in the array sorted. | {
"author": "Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>",
"date": "Mon, 2 Feb 2026 09:12:47 +0100",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
... | On 2/1/26 10:37 PM, Kurt Borja wrote:
Make sure that you include Dell.Client.Kernel@dell.com in case they have
any comments.
I added them to CC. | {
"author": "Mario Limonciello <mario.limonciello@amd.com>",
"date": "Mon, 2 Feb 2026 08:17:16 -0600",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
... | On Mon Feb 2, 2026 at 3:12 AM -05, Pali Rohár wrote:
Hi Pali,
I thought I sorted it... I'll fix it, thanks!
--
Thanks,
~ Kurt | {
"author": "\"Kurt Borja\" <kuurtb@gmail.com>",
"date": "Mon, 02 Feb 2026 12:34:19 -0500",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
... | On Mon Feb 2, 2026 at 9:17 AM -05, Mario Limonciello wrote:
Hi Mario,
Thanks, I'll add it.
--
Thanks,
~ Kurt | {
"author": "\"Kurt Borja\" <kuurtb@gmail.com>",
"date": "Mon, 02 Feb 2026 12:35:49 -0500",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH] platform/x86: dell-wmi: Add audio/mic mute key codes | Add audio/mic mute key codes found in some Alienware devices.
Cc: stable@vger.kernel.org
Tested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Suggested-by: Olexa Bilaniuk <obilaniu@gmail.com>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
---
drivers/platform/x86/dell/dell-wmi-base.c | 3 +++
1 file changed, 3 insertions(+)
... | On Monday 02 February 2026 12:34:19 Kurt Borja wrote:
Before is value 0xe001 and your new values are 0x01xx. Most of values
are 0xeXXX, so it is quite unusual that Dell allocated values with
different pattern.
Also, could you please include into commit message for which Alienware
devices is change needed? It would he... | {
"author": "Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>",
"date": "Mon, 2 Feb 2026 18:43:22 +0100",
"thread_id": "DG4NOQRW8MOE.25YALP6C6UTWZ@gmail.com.mbox.gz"
} |
lkml | [PATCH v2] docs: filesystems: ensure proc pid substitutable is
complete | The entry in proc.rst for 3.14 is missing the closing ">" of the "pid"
field for the ksm_stat file. Add this for both the table of contents and
the actual header for the "ksm_stat" file.
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Thomas Böhler <witcher@wiredspace.de>
---
Changes in v2:
- Also adjust... | Thomas Böhler <witcher@wiredspace.de> writes:
Applied, thanks.
jon | {
"author": "Jonathan Corbet <corbet@lwn.net>",
"date": "Mon, 02 Feb 2026 09:49:51 -0700",
"thread_id": "87wm0vrsy8.fsf@trenco.lwn.net.mbox.gz"
} |
lkml | [PATCH v2 00/14] Add SPDX SBOM generation tool | This patch series introduces a Python-based tool for generating SBOM
documents in the SPDX 3.0.1 format for kernel builds.
A Software Bill of Materials (SBOM) describes the individual components
of a software product. For the kernel, the goal is to describe the
distributable build outputs (typically the kernel image a... | Add CONFIG_SBOM option and integrate SBOM tool into the kernel build
process.
Co-developed-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Luis Augenstein <luis.augenstein@tngtech.com>
---
.gitignore | 1 +
MAINTAINERS ... | {
"author": "Luis Augenstein <luis.augenstein@tngtech.com>",
"date": "Tue, 20 Jan 2026 12:53:39 +0100",
"thread_id": "6ed0fe99-3724-40c2-8d98-3309a3cf0104@tngtech.com.mbox.gz"
} |
lkml | [PATCH v2 00/14] Add SPDX SBOM generation tool | This patch series introduces a Python-based tool for generating SBOM
documents in the SPDX 3.0.1 format for kernel builds.
A Software Bill of Materials (SBOM) describes the individual components
of a software product. For the kernel, the goal is to describe the
distributable build outputs (typically the kernel image a... | Add logging infrastructure for warnings and errors.
Errors and warnings are accumulated and summarized in the end.
Co-developed-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Maximilian Huber <maximilian.huber@tngtech.com>
Signed-off-by: Luis Augenstein <luis.augenstein@tngtech.com>
---
tools/sbom... | {
"author": "Luis Augenstein <luis.augenstein@tngtech.com>",
"date": "Tue, 20 Jan 2026 12:53:40 +0100",
"thread_id": "6ed0fe99-3724-40c2-8d98-3309a3cf0104@tngtech.com.mbox.gz"
} |
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