source large_stringclasses 2
values | subject large_stringclasses 112
values | code large_stringclasses 112
values | critique large_stringlengths 61 3.04M ⌀ | metadata dict |
|---|---|---|---|---|
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | On Sun, Feb 01, 2026 at 04:50:17PM -0800, Usama Arif wrote:
I suggest this has not had enough testing. There are dozens of places
in the MM which assume that if a folio is at leaast PMD size then it is
exactly PMD size. Everywhere that calls folio_test_pmd_mappable() needs
to be audited to make sure that it will wor... | {
"author": "Matthew Wilcox <willy@infradead.org>",
"date": "Mon, 2 Feb 2026 04:00:06 +0000",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | On 2/2/26 05:00, Matthew Wilcox wrote:
I think the hack (ehm trick) in this patch set is to do it just like dax
PUDs: only map through a PUD or through PTEs, not through PMDs.
That also avoids dealing with mapcounts until I sorted that out.
--
Cheers
David | {
"author": "\"David Hildenbrand (arm)\" <david@kernel.org>",
"date": "Mon, 2 Feb 2026 10:06:14 +0100",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | On Sun, Feb 01, 2026 at 04:50:18PM -0800, Usama Arif wrote:
This is ugly.
Sounds like you want to use llist_node/head instead of list_head for this.
You might able to avoid taking the lock in some cases. Note that
pud_lockptr() is mm->page_table_lock as of now.
Remove the ifdef and make mm_find_pmd() call it.
And... | {
"author": "Kiryl Shutsemau <kas@kernel.org>",
"date": "Mon, 2 Feb 2026 10:44:54 +0000",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | OK so this is somewhat unexpected :)
It would have been nice to discuss it in the THP cabal or at a conference
etc. so we could discuss approaches ahead of time. Communication is important,
especially with major changes like this.
And PUD THP is especially problematic in that it requires pages that the page
allocator... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Mon, 2 Feb 2026 11:20:57 +0000",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | On Sun, Feb 01, 2026 at 09:44:12PM -0500, Rik van Riel wrote:
That link doesn't work?
Did a quick search for CMA balancing on lore, couldn't find anything, could you
provide a lore link?
I'm not really in favour of this kind of approach. There's plenty of things that
were considered 'temporary' upstream that became... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Mon, 2 Feb 2026 11:30:27 +0000",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | On Sun, Feb 01, 2026 at 04:50:19PM -0800, Usama Arif wrote:
Yeah we really need to be basing this on mm-unstable once Nico's series is
landed.
I think it's quite important as well for you to check that khugepaged mTHP works
with all of this.
Err what is this change doing in a 'stats' change? This quietly updates
__... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Mon, 2 Feb 2026 11:56:44 +0000",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | I think I'm going to have to do several passes on this, so this is just a
first one :)
On Sun, Feb 01, 2026 at 04:50:18PM -0800, Usama Arif wrote:
This feels like you're hacking this support in, honestly. The list_head
abuse only adds to that feeling.
And are we now not required to store rather a lot of memory to ke... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Mon, 2 Feb 2026 12:15:38 +0000",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | On 2 Feb 2026, at 6:30, Lorenzo Stoakes wrote:
https://lwn.net/Articles/1038263/
I also would like to hear David’s opinion on using CMA for 1GB THP.
He did not like it[1] when I posted my patch back in 2020, but it has
been more than 5 years. :)
The other direction I explored is to get 1GB THP from buddy allocator... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Mon, 02 Feb 2026 10:50:35 -0500",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | On 2 Feb 2026, at 5:44, Kiryl Shutsemau wrote:
<snip>
I agree. I used llist_node/head in my implementation[1] and it works.
I have an illustration at[2] to show the concept. Feel free to reuse the code.
[1] https://lore.kernel.org/all/20200928193428.GB30994@casper.infradead.org/
[2] https://normal.zone/blog/2021-... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Mon, 02 Feb 2026 11:01:00 -0500",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [RFC 00/12] mm: PUD (1GB) THP implementation | This is an RFC series to implement 1GB PUD-level THPs, allowing
applications to benefit from reduced TLB pressure without requiring
hugetlbfs. The patches are based on top of
f9b74c13b773b7c7e4920d7bc214ea3d5f37b422 from mm-stable (6.19-rc6).
Motivation: Why 1GB THP over hugetlbfs?
====================================... | On 1 Feb 2026, at 19:50, Usama Arif wrote:
It is nice to see you are working on 1GB THP.
But you are using CMA, the same allocation mechanism as hugetlb_cma. What
is the difference?
True.
Since you have PUD THP implementation, have you run any workload on it?
How often you see a PUD THP split?
Oh, you actually... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Mon, 02 Feb 2026 11:24:19 -0500",
"thread_id": "3561FD10-664D-42AA-8351-DE7D8D49D42E@nvidia.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Add verify-only public key crypto support for ML-DSA so that the
X.509/PKCS#7 signature verification code, as used by module signing,
amongst other things, can make use of it through the common crypto_sig API.
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
cc: Eric ... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:06 +0000",
"thread_id": "20260202170216.2467036-6-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Calculate the SHA256 hash for blacklisting purposes independently of the
signature hash (which may be something other than SHA256).
This is necessary because when ML-DSA is used, no digest is calculated.
Note that this represents a change of behaviour in that the hash used for
the blacklist check would previously hav... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:07 +0000",
"thread_id": "20260202170216.2467036-6-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Rename ->digest and ->digest_len to ->m and ->m_size to represent the input
to the signature verification algorithm, reflecting that ->digest may no
longer actually *be* a digest.
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
cc: Lukas Wunner <lukas@wunner.de>
cc: ... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:08 +0000",
"thread_id": "20260202170216.2467036-6-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow the data to be verified in a PKCS#7 or CMS message to be passed
directly to an asymmetric cipher algorithm (e.g. ML-DSA) if it wants to do
whatever passes for hashing/digestion itself. The normal digestion of the
data is then skipped as that would be ignored unless another signed info in
the message has some oth... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:09 +0000",
"thread_id": "20260202170216.2467036-6-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Add support for ML-DSA keys and signatures to the CMS/PKCS#7 and X.509
implementations. ML-DSA-44, -65 and -87 are all supported. For X.509
certificates, the TBSCertificate is required to be signed directly; for
CMS, direct signing of the data is preferred, though use of SHA512 (and
only that) as an intermediate hash... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:10 +0000",
"thread_id": "20260202170216.2467036-6-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow ML-DSA module signing to be enabled.
Note that OpenSSL's CMS_*() function suite does not, as of OpenSSL-3.6,
support the use of CMS_NOATTR with ML-DSA, so the prohibition against using
signedAttrs with module signing has to be removed. The selected digest
then applies only to the algorithm used to calculate the... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:11 +0000",
"thread_id": "20260202170216.2467036-6-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow the rejection of authenticatedAttributes in PKCS#7 (signedAttrs in
CMS) to be waived in the kernel config for ML-DSA when used for module
signing. This reflects the issue that openssl < 4.0 cannot do this and
openssl-4 has not yet been released.
This does not permit RSA, ECDSA or ECRDSA to be so waived (behavio... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:12 +0000",
"thread_id": "20260202170216.2467036-6-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH 0/2] idpf: skip NULL pointers during deallocation. | In idpf txq and rxq error paths, some pointers are not allocated in the
first place. In the corresponding deallocation logic, we should not
deallocate them to prevent kernel panics.
Li Li (2):
idpf: skip deallocating bufq_sets from rx_qgrp if it is NULL.
idpf: skip deallocating txq group's txqs if it is NULL.
dr... | In idpf_rxq_group_alloc(), if rx_qgrp->splitq.bufq_sets failed to get
allocated:
rx_qgrp->splitq.bufq_sets = kcalloc(vport->num_bufqs_per_qgrp,
sizeof(struct idpf_bufq_set),
GFP_KERNEL);
if (!rx_qgrp->splitq.bufq_sets) {
err = -ENOMEM;
goto err_alloc;
}
idpf_rxq_group_rel() would attempt to d... | {
"author": "Li Li <boolli@google.com>",
"date": "Mon, 12 Jan 2026 23:09:43 +0000",
"thread_id": "SJ1PR11MB62974489C265924B9206E58C9B9AA@SJ1PR11MB6297.namprd11.prod.outlook.com.mbox.gz"
} |
lkml | [PATCH 0/2] idpf: skip NULL pointers during deallocation. | In idpf txq and rxq error paths, some pointers are not allocated in the
first place. In the corresponding deallocation logic, we should not
deallocate them to prevent kernel panics.
Li Li (2):
idpf: skip deallocating bufq_sets from rx_qgrp if it is NULL.
idpf: skip deallocating txq group's txqs if it is NULL.
dr... | In idpf_txq_group_alloc(), if any txq group's txqs failed to
allocate memory:
for (j = 0; j < tx_qgrp->num_txq; j++) {
tx_qgrp->txqs[j] = kzalloc(sizeof(*tx_qgrp->txqs[j]),
GFP_KERNEL);
if (!tx_qgrp->txqs[j])
goto err_alloc;
}
It would cause a NULL ptr kernel panic in idpf_txq_group_rel():
for (j =... | {
"author": "Li Li <boolli@google.com>",
"date": "Mon, 12 Jan 2026 23:09:44 +0000",
"thread_id": "SJ1PR11MB62974489C265924B9206E58C9B9AA@SJ1PR11MB6297.namprd11.prod.outlook.com.mbox.gz"
} |
lkml | [PATCH 0/2] idpf: skip NULL pointers during deallocation. | In idpf txq and rxq error paths, some pointers are not allocated in the
first place. In the corresponding deallocation logic, we should not
deallocate them to prevent kernel panics.
Li Li (2):
idpf: skip deallocating bufq_sets from rx_qgrp if it is NULL.
idpf: skip deallocating txq group's txqs if it is NULL.
dr... | Dear Li,
Thank you for your patch.
Am 13.01.26 um 00:09 schrieb Li Li via Intel-wired-lan:
Is it easy to reproduce?
(Just for the future, a blank in the “tag section” is uncommon.)
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Kind regards,
Paul | {
"author": "Paul Menzel <pmenzel@molgen.mpg.de>",
"date": "Tue, 13 Jan 2026 07:31:26 +0100",
"thread_id": "SJ1PR11MB62974489C265924B9206E58C9B9AA@SJ1PR11MB6297.namprd11.prod.outlook.com.mbox.gz"
} |
lkml | [PATCH 0/2] idpf: skip NULL pointers during deallocation. | In idpf txq and rxq error paths, some pointers are not allocated in the
first place. In the corresponding deallocation logic, we should not
deallocate them to prevent kernel panics.
Li Li (2):
idpf: skip deallocating bufq_sets from rx_qgrp if it is NULL.
idpf: skip deallocating txq group's txqs if it is NULL.
dr... | Dear Li,
Thank you for your patch.
Am 13.01.26 um 00:09 schrieb Li Li:
The reproduction steps would be nice to have documented.
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Kind regards,
Paul | {
"author": "Paul Menzel <pmenzel@molgen.mpg.de>",
"date": "Tue, 13 Jan 2026 07:43:07 +0100",
"thread_id": "SJ1PR11MB62974489C265924B9206E58C9B9AA@SJ1PR11MB6297.namprd11.prod.outlook.com.mbox.gz"
} |
lkml | [PATCH 0/2] idpf: skip NULL pointers during deallocation. | In idpf txq and rxq error paths, some pointers are not allocated in the
first place. In the corresponding deallocation logic, we should not
deallocate them to prevent kernel panics.
Li Li (2):
idpf: skip deallocating bufq_sets from rx_qgrp if it is NULL.
idpf: skip deallocating txq group's txqs if it is NULL.
dr... | Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> | {
"author": "\"Loktionov, Aleksandr\" <aleksandr.loktionov@intel.com>",
"date": "Tue, 13 Jan 2026 07:34:09 +0000",
"thread_id": "SJ1PR11MB62974489C265924B9206E58C9B9AA@SJ1PR11MB6297.namprd11.prod.outlook.com.mbox.gz"
} |
lkml | [PATCH 0/2] idpf: skip NULL pointers during deallocation. | In idpf txq and rxq error paths, some pointers are not allocated in the
first place. In the corresponding deallocation logic, we should not
deallocate them to prevent kernel panics.
Li Li (2):
idpf: skip deallocating bufq_sets from rx_qgrp if it is NULL.
idpf: skip deallocating txq group's txqs if it is NULL.
dr... | Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> | {
"author": "\"Loktionov, Aleksandr\" <aleksandr.loktionov@intel.com>",
"date": "Tue, 13 Jan 2026 07:34:57 +0000",
"thread_id": "SJ1PR11MB62974489C265924B9206E58C9B9AA@SJ1PR11MB6297.namprd11.prod.outlook.com.mbox.gz"
} |
lkml | [PATCH 0/2] idpf: skip NULL pointers during deallocation. | In idpf txq and rxq error paths, some pointers are not allocated in the
first place. In the corresponding deallocation logic, we should not
deallocate them to prevent kernel panics.
Li Li (2):
idpf: skip deallocating bufq_sets from rx_qgrp if it is NULL.
idpf: skip deallocating txq group's txqs if it is NULL.
dr... | On Mon, Jan 12, 2026 at 10:31 PM Paul Menzel <pmenzel@molgen.mpg.de> wrote:
In our internal environments, we have the idpf driver running on
machines with small RAM, and it's not uncommon for
them to run out of memory and encounter kalloc issues, especially in
kcallocs where we allocate higher order memory.
To reliab... | {
"author": "Li Li <boolli@google.com>",
"date": "Thu, 15 Jan 2026 12:07:12 -0800",
"thread_id": "SJ1PR11MB62974489C265924B9206E58C9B9AA@SJ1PR11MB6297.namprd11.prod.outlook.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Extend the DPLL core to support associating a DPLL pin with a firmware
node. This association is required to allow other subsystems (such as
network drivers) to locate and request specific DPLL pins defined in
the Device Tree or ACPI.
* Add a .fwnode field to the struct dpll_pin
* Introduce dpll_pin_fwnode_set() helpe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:30 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Associate the registered DPLL pin with its firmware node by calling
dpll_pin_fwnode_set().
This links the created pin object to its corresponding DT/ACPI node
in the DPLL core. Consequently, this enables consumer drivers (such as
network drivers) to locate and request this specific pin using the
fwnode_dpll_pin_find()... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:31 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Petr Oros <poros@redhat.com>
Currently, the DPLL subsystem reports events (creation, deletion, changes)
to userspace via Netlink. However, there is no mechanism for other kernel
components to be notified of these events directly.
Add a raw notifier chain to the DPLL core protected by dpll_lock. This
allows othe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:32 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Allow drivers to register DPLL pins without manually specifying a pin
index.
Currently, drivers must provide a unique pin index when calling
dpll_pin_get(). This works well for hardware-mapped pins but creates
friction for drivers handling virtual pins or those without a strict
hardware indexing scheme.
Introduce DPL... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:33 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add parsing for the "mux" string in the 'connection-type' pin property
mapping it to DPLL_PIN_TYPE_MUX.
Recognizing this type in the driver allows these pins to be taken as
parent pins for pin-on-pin pins coming from different modules (e.g.
network drivers).
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:34 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Refactor the reference counting mechanism for DPLL devices and pins to
improve consistency and prevent potential lifetime issues.
Introduce internal helpers __dpll_{device,pin}_{hold,put}() to
centralize reference management.
Update the internal XArray reference helpers (dpll_xa_ref_*) to
automatically grab a referen... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:35 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add support for the REF_TRACKER infrastructure to the DPLL subsystem.
When enabled, this allows developers to track and debug reference counting
leaks or imbalances for dpll_device and dpll_pin objects. It records stack
traces for every get/put operation and exposes this information via
debugfs at:
/sys/kernel/debug... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:36 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Update existing DPLL drivers to utilize the DPLL reference count
tracking infrastructure.
Add dpll_tracker fields to the drivers' internal device and pin
structures. Pass pointers to these trackers when calling
dpll_device_get/put() and dpll_pin_get/put().
This allows developers to inspect the specific references hel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:37 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Implement SyncE support for the E825-C Ethernet controller using the
DPLL subsystem. Unlike E810, the E825-C architecture relies on platform
firmware (ACPI) to describe connections between the NIC's recovered clock
outputs and external DPLL inputs.
Implement... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:38 +0100",
"thread_id": "20260202171638.17427-2-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | From: Andreea Pintilie <anpintil@microsoft.com>
Update the partition VMM capability structure to match the hypervisor
representation to bring it to the up to date state. A precursor patch for
Root-on-Core scheduler feature support.
Signed-off-by: Andreea Pintilie <anpintil@microsoft.com>
Signed-off-by: Stanislav Kins... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Wed, 21 Jan 2026 22:35:54 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | From: Andreea Pintilie <anpintil@microsoft.com>
Query the hypervisor for integrated scheduler support and use it if
configured.
Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slici... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Wed, 21 Jan 2026 22:35:59 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | From: Stanislav Kinsburskii <skinsburskii@linux.microsoft.com> Sent: Wednesday, January 21, 2026 2:36 PM
The tag_hv_message_from_child field is not used in the 2nd patch of this
patch set, so it is added but never used. Is it added just to be a placeholder
so that field vmm_enable_integrated_scheduler can be added... | {
"author": "Michael Kelley <mhklinux@outlook.com>",
"date": "Thu, 29 Jan 2026 17:46:21 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | From: Stanislav Kinsburskii <skinsburskii@linux.microsoft.com> Sent: Wednesday, January 21, 2026 2:36 PM
hv_call_get_partition_property_ex() makes a hypercall, and then copies
back the number of bytes indicated by the 4th argument above; i.e.,
sizeof(root_sched_enabled). But using the size of a Linux type (size_t)... | {
"author": "Michael Kelley <mhklinux@outlook.com>",
"date": "Thu, 29 Jan 2026 17:47:02 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Thu, Jan 29, 2026 at 05:47:02PM +0000, Michael Kelley wrote:
<snip>
This was originally done to support kexec.
Here is the original commit message:
mshv: perform synic cleanup during kexec
Register a reboot notifier that performs synic cleanup when a kexec
is in progress.
One notable issue this... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Thu, 29 Jan 2026 11:09:46 -0800",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | From: Stanislav Kinsburskii <skinsburskii@linux.microsoft.com> Sent: Thursday, January 29, 2026 11:10 AM
FWIW, I don't see that commit message anywhere in a public source code
tree. The calls to register/unregister_reboot_notifier() were in the original
introduction of mshv_root_main.c in upstream commit 621191d709b14... | {
"author": "Michael Kelley <mhklinux@outlook.com>",
"date": "Fri, 30 Jan 2026 01:24:34 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Fri, Jan 30, 2026 at 01:24:34AM +0000, Michael Kelley wrote:
Yes, for now it's the best we have.
This code can be dropped later if we get a better way to handle kexec.
Yes. Thank you for the review and feedback!
Stanislav | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Fri, 30 Jan 2026 07:49:05 -0800",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Thu, Jan 29, 2026 at 11:09:46AM -0800, Stanislav Kinsburskii wrote:
I don't think we need to fail here. If we don't find vmm caps, that
means we are on an older hypervisor that supports l1vh but not
integrated scheduler (yes, such a version exists). In this case since
integrated scheduler is not supported by the hy... | {
"author": "Anirudh Rayabharam <anirudh@anirudhrb.com>",
"date": "Fri, 30 Jan 2026 17:30:25 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Fri, Jan 30, 2026 at 01:24:34AM +0000, Michael Kelley wrote:
While that commit wasn't individually sent upstream but all the code
from that commit did land upstream probably bundled with other commits
when the mshv driver was introduced. So the reboot notifier is indeed
currently used for resetting the synic correc... | {
"author": "Anirudh Rayabharam <anirudh@anirudhrb.com>",
"date": "Fri, 30 Jan 2026 17:37:24 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | From: Anirudh Rayabharam <anirudh@anirudhrb.com> Sent: Friday, January 30, 2026 9:37 AM
Indeed, you are right. I confused the "mshv_root_sched_online" and
"mshv_cpuhp_online" cpuhp states. The reboot notifier removes the latter,
not the former. And the latter does substantive cleanup work on the SynIC
when the state ... | {
"author": "Michael Kelley <mhklinux@outlook.com>",
"date": "Fri, 30 Jan 2026 17:49:02 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Fri, Jan 30, 2026 at 05:30:25PM +0000, Anirudh Rayabharam wrote:
<snip>
The older hypervisor version won't have the integrated scheduler
capabity bit.
And we can't operate in core schedule mode if the integrated is enabled
underneath us.
Thanks,
Stanislav | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Fri, 30 Jan 2026 10:37:38 -0800",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Fri, Jan 30, 2026 at 10:37:38AM -0800, Stanislav Kinsburskii wrote:
The older hypervisor won't have the integrated scheduler capability bit.
This means that the older hypervisor doesn't support integrated
scheduler (this is how vmm caps work: if the bit doesn't exist or
vmm caps themselves don't exist the feature s... | {
"author": "Anirudh Rayabharam <anirudh@anirudhrb.com>",
"date": "Fri, 30 Jan 2026 18:43:09 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Fri, Jan 30, 2026 at 06:43:09PM +0000, Anirudh Rayabharam wrote:
We can’t tell whether the hypervisor is older and simply doesn’t have
the VMM caps bit, or whether we just failed to fetch the VMM caps.
In other words, we can’t distinguish between “an older hypervisor
without integrated scheduler support” and “a ne... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Fri, 30 Jan 2026 10:51:10 -0800",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Fri, Jan 30, 2026 at 10:51:10AM -0800, Stanislav Kinsburskii wrote:
If we failed to fetch the VMM caps i.e. the hypervisor doesn't support
the vmm caps property, we must assume that all the bits in vmm caps are
0 (i.e. no features are available). This is how vmm capabilities are
supposed to be interpreted. This is ... | {
"author": "Anirudh Rayabharam <anirudh@anirudhrb.com>",
"date": "Fri, 30 Jan 2026 20:22:34 +0000",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] Introduce Hyper-V integrated scheduler support | Microsoft Hypervisor originally provided two schedulers: root and core. The
root scheduler allows the root partition to schedule guest vCPUs across
physical cores, supporting both time slicing and CPU affinity (e.g., via
cgroups). In contrast, the core scheduler delegates vCPU-to-physical-core
scheduling entirely to th... | On Fri, Jan 30, 2026 at 08:22:34PM +0000, Anirudh Rayabharam wrote:
We don't need to support interim hypervisor versions in the upstream
kernel: these version will go away, and then this logic will become not
only a dead code path but also incorrect.
We can keep the existing logic that treats failure to fetch VMM as
... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 2 Feb 2026 09:19:39 -0800",
"thread_id": "176903475057.166619.9437539561789960983.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.
The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optio... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:10 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.
This provides a more convenient API for... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:11 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.
Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.
Signed-off-by:... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:12 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.
Core clk is now properly managed alongside the other ... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:13 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.
Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactiva... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:14 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle
the attachment of power domains. This often leads to duplicated code
logic across different driver probe functions.
Introduce a new helper API, geni_se_domain_attach(), to centralize
the logic for attaching "power" and "perf" domains to the GENI SE... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:15 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently
manage performance levels and operating points directly. This resulting
in code duplication across drivers. such as configuring a specific level
or find and apply an OPP based on a clock frequency.
Introduce two new helper APIs, geni_se_set_perf_leve... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:16 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add DT bindings for the QUP GENI I2C controller on sa8255p platforms.
SA8255p platform abstracts resources such as clocks, interconnect and
GPIO pins configuration in Firmware. SCMI power and perf protocol
are utilized to request resource configurations.
SA8255p platform does not require the Serial Engine (SE) common... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:17 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Moving the serial engine setup to geni_i2c_init() API for a cleaner
probe function and utilizes the PM runtime API to control resources
instead of direct clock-related APIs for better resource management.
Enables reusability of the serial engine initialization like
hibernation and deep sleep features where hardware co... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:18 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Refactor the resource initialization in geni_i2c_probe() by introducing
a new geni_i2c_resources_init() function and utilizing the common
geni_se_resources_init() framework and clock frequency mapping, making the
probe function cleaner.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Pravee... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:19 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To manage GENI serial engine resources during runtime power management,
drivers currently need to call functions for ICC, clock, and
SE resource operations in both suspend and resume paths, resulting in
code duplication across drivers.
The new geni_se_resources_activate() and geni_se_resources_deactivate()
helper APIs... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:20 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To avoid repeatedly fetching and checking platform data across various
functions, store the struct of_device_id data directly in the i2c
private structure. This change enhances code maintainability and reduces
redundancy.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <prave... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:21 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:22 +0530",
"thread_id": "20260202180922.1692428-5-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH 6.1.y 1/2] wifi: mac80211: use wiphy work for sdata->work | From: Johannes Berg <johannes.berg@intel.com>
[ Upstream commit 16114496d684a3df4ce09f7c6b7557a8b2922795 ]
We'll need this later to convert other works that might
be cancelled from here, so convert this one first.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
(cherry picked from commit 16114496d684a3df4ce09... | From: Johannes Berg <johannes.berg@intel.com>
[ Upstream commit 777b26002b73127e81643d9286fadf3d41e0e477 ]
Again, to have the wiphy locked for it.
Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
[ Summary of conflict resolutions:
- In mlme.c, move... | {
"author": "=?UTF-8?q?Hanne-Lotta=20M=C3=A4enp=C3=A4=C3=A4?= <hannelotta@gmail.com>",
"date": "Mon, 2 Feb 2026 18:49:24 +0200",
"thread_id": "20260202164924.215621-1-hannelotta@gmail.com.mbox.gz"
} |
lkml | [PATCH v4 0/2] soundwire: amd: clock related changes | Refactor clock init sequence to support different bus clock frequencies
other than 12Mhz. Modify the bandwidth calculation logic to support 12Mhz,
6Mhz with different frame sizes.
Vijendar Mukunda (2):
soundwire: amd: add clock init control function
soundwire: amd: refactor bandwidth calculation logic
Changes sin... | Add generic SoundWire clock initialization sequence to support
different SoundWire bus clock frequencies for ACP6.3/7.0/7.1/7.2
platforms and remove hard coding initializations for 12Mhz bus
clock frequency.
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
drivers/soundwire/amd_manager.c | 52 ++++++++++... | {
"author": "Vijendar Mukunda <Vijendar.Mukunda@amd.com>",
"date": "Thu, 29 Jan 2026 11:44:11 +0530",
"thread_id": "5c12f4d8-e518-45fd-b4f7-12fe6f81e0ec@amd.com.mbox.gz"
} |
lkml | [PATCH v4 0/2] soundwire: amd: clock related changes | Refactor clock init sequence to support different bus clock frequencies
other than 12Mhz. Modify the bandwidth calculation logic to support 12Mhz,
6Mhz with different frame sizes.
Vijendar Mukunda (2):
soundwire: amd: add clock init control function
soundwire: amd: refactor bandwidth calculation logic
Changes sin... | For current platforms(ACP6.3/ACP7.0/ACP7.1/ACP7.2), AMD SoundWire manager
doesn't have banked registers for data port programming on Manager's side.
Need to use fixed block offsets, hstart & hstop for manager ports.
Earlier amd manager driver has support for 12MHz as a bus clock frequency
with frame size as 50 x 10 wit... | {
"author": "Vijendar Mukunda <Vijendar.Mukunda@amd.com>",
"date": "Thu, 29 Jan 2026 11:44:12 +0530",
"thread_id": "5c12f4d8-e518-45fd-b4f7-12fe6f81e0ec@amd.com.mbox.gz"
} |
lkml | [PATCH v4 0/2] soundwire: amd: clock related changes | Refactor clock init sequence to support different bus clock frequencies
other than 12Mhz. Modify the bandwidth calculation logic to support 12Mhz,
6Mhz with different frame sizes.
Vijendar Mukunda (2):
soundwire: amd: add clock init control function
soundwire: amd: refactor bandwidth calculation logic
Changes sin... | On 1/29/26 12:14 AM, Vijendar Mukunda wrote:
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> | {
"author": "Mario Limonciello <superm1@kernel.org>",
"date": "Thu, 29 Jan 2026 13:34:01 -0600",
"thread_id": "5c12f4d8-e518-45fd-b4f7-12fe6f81e0ec@amd.com.mbox.gz"
} |
lkml | [PATCH v4 0/2] soundwire: amd: clock related changes | Refactor clock init sequence to support different bus clock frequencies
other than 12Mhz. Modify the bandwidth calculation logic to support 12Mhz,
6Mhz with different frame sizes.
Vijendar Mukunda (2):
soundwire: amd: add clock init control function
soundwire: amd: refactor bandwidth calculation logic
Changes sin... | On 1/29/26 07:14, Vijendar Mukunda wrote:
the two frame shapes don't carry the same number of bits (500 v. 250). There's probably an additional variable at play, maybe frame rate? Or is 50x10 for 12 MHz and 125x2 for 6 MHz? | {
"author": "Pierre-Louis Bossart <pierre-louis.bossart@linux.dev>",
"date": "Mon, 2 Feb 2026 18:05:33 +0100",
"thread_id": "5c12f4d8-e518-45fd-b4f7-12fe6f81e0ec@amd.com.mbox.gz"
} |
lkml | [PATCH v4 0/2] soundwire: amd: clock related changes | Refactor clock init sequence to support different bus clock frequencies
other than 12Mhz. Modify the bandwidth calculation logic to support 12Mhz,
6Mhz with different frame sizes.
Vijendar Mukunda (2):
soundwire: amd: add clock init control function
soundwire: amd: refactor bandwidth calculation logic
Changes sin... | On 02/02/26 22:35, Pierre-Louis Bossart wrote:
We need to support 12Mhz as bus clock frequency where frame rate is 48000
and number of bits is 500, frame shape as 50 x 10.
For 6Mhz bus clock frequency we need to support two different frame shapes
i.e number of bits as 250 with frame rate as 48000 and frame shape as
125... | {
"author": "\"Mukunda,Vijendar\" <vijendar.mukunda@amd.com>",
"date": "Mon, 2 Feb 2026 22:55:01 +0530",
"thread_id": "5c12f4d8-e518-45fd-b4f7-12fe6f81e0ec@amd.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Extend the DPLL core to support associating a DPLL pin with a firmware
node. This association is required to allow other subsystems (such as
network drivers) to locate and request specific DPLL pins defined in
the Device Tree or ACPI.
* Add a .fwnode field to the struct dpll_pin
* Introduce dpll_pin_fwnode_set() helpe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:30 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Associate the registered DPLL pin with its firmware node by calling
dpll_pin_fwnode_set().
This links the created pin object to its corresponding DT/ACPI node
in the DPLL core. Consequently, this enables consumer drivers (such as
network drivers) to locate and request this specific pin using the
fwnode_dpll_pin_find()... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:31 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Petr Oros <poros@redhat.com>
Currently, the DPLL subsystem reports events (creation, deletion, changes)
to userspace via Netlink. However, there is no mechanism for other kernel
components to be notified of these events directly.
Add a raw notifier chain to the DPLL core protected by dpll_lock. This
allows othe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:32 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Allow drivers to register DPLL pins without manually specifying a pin
index.
Currently, drivers must provide a unique pin index when calling
dpll_pin_get(). This works well for hardware-mapped pins but creates
friction for drivers handling virtual pins or those without a strict
hardware indexing scheme.
Introduce DPL... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:33 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add parsing for the "mux" string in the 'connection-type' pin property
mapping it to DPLL_PIN_TYPE_MUX.
Recognizing this type in the driver allows these pins to be taken as
parent pins for pin-on-pin pins coming from different modules (e.g.
network drivers).
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:34 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Refactor the reference counting mechanism for DPLL devices and pins to
improve consistency and prevent potential lifetime issues.
Introduce internal helpers __dpll_{device,pin}_{hold,put}() to
centralize reference management.
Update the internal XArray reference helpers (dpll_xa_ref_*) to
automatically grab a referen... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:35 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add support for the REF_TRACKER infrastructure to the DPLL subsystem.
When enabled, this allows developers to track and debug reference counting
leaks or imbalances for dpll_device and dpll_pin objects. It records stack
traces for every get/put operation and exposes this information via
debugfs at:
/sys/kernel/debug... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:36 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Update existing DPLL drivers to utilize the DPLL reference count
tracking infrastructure.
Add dpll_tracker fields to the drivers' internal device and pin
structures. Pass pointers to these trackers when calling
dpll_device_get/put() and dpll_pin_get/put().
This allows developers to inspect the specific references hel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:37 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Implement SyncE support for the E825-C Ethernet controller using the
DPLL subsystem. Unlike E810, the E825-C architecture relies on platform
firmware (ACPI) to describe connections between the NIC's recovered clock
outputs and external DPLL inputs.
Implement... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:38 +0100",
"thread_id": "20260202171638.17427-9-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Extend the DPLL core to support associating a DPLL pin with a firmware
node. This association is required to allow other subsystems (such as
network drivers) to locate and request specific DPLL pins defined in
the Device Tree or ACPI.
* Add a .fwnode field to the struct dpll_pin
* Introduce dpll_pin_fwnode_set() helpe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:30 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Associate the registered DPLL pin with its firmware node by calling
dpll_pin_fwnode_set().
This links the created pin object to its corresponding DT/ACPI node
in the DPLL core. Consequently, this enables consumer drivers (such as
network drivers) to locate and request this specific pin using the
fwnode_dpll_pin_find()... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:31 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Petr Oros <poros@redhat.com>
Currently, the DPLL subsystem reports events (creation, deletion, changes)
to userspace via Netlink. However, there is no mechanism for other kernel
components to be notified of these events directly.
Add a raw notifier chain to the DPLL core protected by dpll_lock. This
allows othe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:32 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Allow drivers to register DPLL pins without manually specifying a pin
index.
Currently, drivers must provide a unique pin index when calling
dpll_pin_get(). This works well for hardware-mapped pins but creates
friction for drivers handling virtual pins or those without a strict
hardware indexing scheme.
Introduce DPL... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:33 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add parsing for the "mux" string in the 'connection-type' pin property
mapping it to DPLL_PIN_TYPE_MUX.
Recognizing this type in the driver allows these pins to be taken as
parent pins for pin-on-pin pins coming from different modules (e.g.
network drivers).
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:34 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Refactor the reference counting mechanism for DPLL devices and pins to
improve consistency and prevent potential lifetime issues.
Introduce internal helpers __dpll_{device,pin}_{hold,put}() to
centralize reference management.
Update the internal XArray reference helpers (dpll_xa_ref_*) to
automatically grab a referen... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:35 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add support for the REF_TRACKER infrastructure to the DPLL subsystem.
When enabled, this allows developers to track and debug reference counting
leaks or imbalances for dpll_device and dpll_pin objects. It records stack
traces for every get/put operation and exposes this information via
debugfs at:
/sys/kernel/debug... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:36 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Update existing DPLL drivers to utilize the DPLL reference count
tracking infrastructure.
Add dpll_tracker fields to the drivers' internal device and pin
structures. Pass pointers to these trackers when calling
dpll_device_get/put() and dpll_pin_get/put().
This allows developers to inspect the specific references hel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:37 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Implement SyncE support for the E825-C Ethernet controller using the
DPLL subsystem. Unlike E810, the E825-C architecture relies on platform
firmware (ACPI) to describe connections between the NIC's recovered clock
outputs and external DPLL inputs.
Implement... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:38 +0100",
"thread_id": "20260202171638.17427-3-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH 0/2] Fix port enumeration failure and NULL endpoint issue | I ran CXL mock testing with next branch, I usually hit the following
call trace.
Oops: general protection fault, probably for non-canonical address 0xdffffc0000000092: 0000 [#1] SMP KASAN NOPTI
KASAN: null-ptr-deref in range [0x0000000000000490-0x0000000000000497]
CPU: 3 UID: 0 PID: 42 Comm: kworker/u16:1 Tainted: ... | CXL testing environment can trigger following trace
Oops: general protection fault, probably for non-canonical address 0xdffffc0000000092: 0000 [#1] SMP KASAN NOPTI
KASAN: null-ptr-deref in range [0x0000000000000490-0x0000000000000497]
RIP: 0010:cxl_dpa_to_region+0x105/0x1f0 [cxl_core]
Call Trace:
<TASK>
cxl_e... | {
"author": "Li Ming <ming.li@zohomail.com>",
"date": "Sun, 1 Feb 2026 17:30:01 +0800",
"thread_id": "aYDRcU0dZjwCRb4y@gourry-fedora-PF4VCD3F.mbox.gz"
} |
lkml | [PATCH 0/2] Fix port enumeration failure and NULL endpoint issue | I ran CXL mock testing with next branch, I usually hit the following
call trace.
Oops: general protection fault, probably for non-canonical address 0xdffffc0000000092: 0000 [#1] SMP KASAN NOPTI
KASAN: null-ptr-deref in range [0x0000000000000490-0x0000000000000497]
CPU: 3 UID: 0 PID: 42 Comm: kworker/u16:1 Tainted: ... | When CXL subsystem adds a cxl port to a hierarchy, there is a small
window where the new port becomes visible before it is bound to a
driver. This happens because device_add() adds a device to bus device
list before bus_probe_device() binds it to a driver.
So if two cxl memdevs are trying to add a dport to a same port ... | {
"author": "Li Ming <ming.li@zohomail.com>",
"date": "Sun, 1 Feb 2026 17:30:02 +0800",
"thread_id": "aYDRcU0dZjwCRb4y@gourry-fedora-PF4VCD3F.mbox.gz"
} |
lkml | [PATCH 0/2] Fix port enumeration failure and NULL endpoint issue | I ran CXL mock testing with next branch, I usually hit the following
call trace.
Oops: general protection fault, probably for non-canonical address 0xdffffc0000000092: 0000 [#1] SMP KASAN NOPTI
KASAN: null-ptr-deref in range [0x0000000000000490-0x0000000000000497]
CPU: 3 UID: 0 PID: 42 Comm: kworker/u16:1 Tainted: ... | On Sun, 1 Feb 2026 17:30:01 +0800
Li Ming <ming.li@zohomail.com> wrote:
I had a look at whether it made sense to use use IS_ERR_OR_NULL() to check
for validity of the endpoint, but it would be somewhat fiddly and I think
you are correct that convention here seems to be NULL means not set.
We don't need the error cod... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Mon, 2 Feb 2026 14:41:03 +0000",
"thread_id": "aYDRcU0dZjwCRb4y@gourry-fedora-PF4VCD3F.mbox.gz"
} |
lkml | [PATCH 0/2] Fix port enumeration failure and NULL endpoint issue | I ran CXL mock testing with next branch, I usually hit the following
call trace.
Oops: general protection fault, probably for non-canonical address 0xdffffc0000000092: 0000 [#1] SMP KASAN NOPTI
KASAN: null-ptr-deref in range [0x0000000000000490-0x0000000000000497]
CPU: 3 UID: 0 PID: 42 Comm: kworker/u16:1 Tainted: ... | On Sun, 1 Feb 2026 17:30:02 +0800
Li Ming <ming.li@zohomail.com> wrote:
Indenting not consistent here as this call is in devm_cxl_enumerate_ports()
Spell check. Guarantees
Analysis looks reasonable to me, but I'm not hugely confident on this
one so would like others to take a close look as well.
Question inline.... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Mon, 2 Feb 2026 15:39:24 +0000",
"thread_id": "aYDRcU0dZjwCRb4y@gourry-fedora-PF4VCD3F.mbox.gz"
} |
lkml | [PATCH 0/2] Fix port enumeration failure and NULL endpoint issue | I ran CXL mock testing with next branch, I usually hit the following
call trace.
Oops: general protection fault, probably for non-canonical address 0xdffffc0000000092: 0000 [#1] SMP KASAN NOPTI
KASAN: null-ptr-deref in range [0x0000000000000490-0x0000000000000497]
CPU: 3 UID: 0 PID: 42 Comm: kworker/u16:1 Tainted: ... | On Mon, Feb 02, 2026 at 02:41:03PM +0000, Jonathan Cameron wrote:
doing validity checks on pointers by checking for null is a pretty
common convention kernel-wide, I would consider setting some structure's
value to an ERR_PTR to be the aberration.
So yeah, good catch
Reviewed-by: Gregory Price <gourry@gourry.net>
~... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Mon, 2 Feb 2026 10:48:14 -0500",
"thread_id": "aYDRcU0dZjwCRb4y@gourry-fedora-PF4VCD3F.mbox.gz"
} |
lkml | [PATCH 0/2] Fix port enumeration failure and NULL endpoint issue | I ran CXL mock testing with next branch, I usually hit the following
call trace.
Oops: general protection fault, probably for non-canonical address 0xdffffc0000000092: 0000 [#1] SMP KASAN NOPTI
KASAN: null-ptr-deref in range [0x0000000000000490-0x0000000000000497]
CPU: 3 UID: 0 PID: 42 Comm: kworker/u16:1 Tainted: ... | On Sun, Feb 01, 2026 at 05:30:02PM +0800, Li Ming wrote:
With just a a cursory look, I'm immediately concerned that you're fixing
a race condition with a lock inversion.
Can you guarantee the following is not happening
Thread A Thread B
----------------------------
lock(parent) lock(port)
lock(po... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Mon, 2 Feb 2026 11:31:45 -0500",
"thread_id": "aYDRcU0dZjwCRb4y@gourry-fedora-PF4VCD3F.mbox.gz"
} |
lkml | [PATCH] staging: sm750fb: rename Bpp to bpp | Rename the Bpp parameter to bpp to avoid CamelCase, as reported by
checkpatch.pl.
Signed-off-by: yehudis9982 <y0533159982@gmail.com>
---
drivers/staging/sm750fb/sm750_accel.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/sm750fb/sm750_accel.c b/drivers/st... | On Mon, Feb 02, 2026 at 04:54:13PM +0200, yehudis9982 wrote:
What does "bpp" stand for? Perhaps spell it out further?
thanks,
greg k-h | {
"author": "Greg KH <gregkh@linuxfoundation.org>",
"date": "Mon, 2 Feb 2026 16:01:17 +0100",
"thread_id": "2026020201-monogamy-sash-4866@gregkh.mbox.gz"
} |
lkml | [PATCH] staging: sm750fb: rename Bpp to bpp | Rename the Bpp parameter to bpp to avoid CamelCase, as reported by
checkpatch.pl.
Signed-off-by: yehudis9982 <y0533159982@gmail.com>
---
drivers/staging/sm750fb/sm750_accel.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/sm750fb/sm750_accel.c b/drivers/st... | Rename the Bpp parameter to bytes_per_pixel for clarity and to avoid CamelCase, as reported by checkpatch.pl.
Signed-off-by: yehudis9982 <y0533159982@gmail.com>
---
drivers/staging/sm750fb/sm750_accel.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/sm... | {
"author": "yehudis9982 <y0533159982@gmail.com>",
"date": "Mon, 2 Feb 2026 18:46:45 +0200",
"thread_id": "2026020201-monogamy-sash-4866@gregkh.mbox.gz"
} |
lkml | [PATCH] staging: sm750fb: rename Bpp to bpp | Rename the Bpp parameter to bpp to avoid CamelCase, as reported by
checkpatch.pl.
Signed-off-by: yehudis9982 <y0533159982@gmail.com>
---
drivers/staging/sm750fb/sm750_accel.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/sm750fb/sm750_accel.c b/drivers/st... | Rename the Bpp parameter to bytes_per_pixel for clarity and to avoid CamelCase, as reported by checkpatch.pl.
Signed-off-by: yehudis9982 <y0533159982@gmail.com>
---
drivers/staging/sm750fb/sm750_accel.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/sm... | {
"author": "yehudis9982 <y0533159982@gmail.com>",
"date": "Mon, 2 Feb 2026 18:57:18 +0200",
"thread_id": "2026020201-monogamy-sash-4866@gregkh.mbox.gz"
} |
lkml | [PATCH] staging: sm750fb: rename Bpp to bpp | Rename the Bpp parameter to bpp to avoid CamelCase, as reported by
checkpatch.pl.
Signed-off-by: yehudis9982 <y0533159982@gmail.com>
---
drivers/staging/sm750fb/sm750_accel.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/sm750fb/sm750_accel.c b/drivers/st... | Rename the Bpp parameter to bytes_per_pixel for clarity and to avoid CamelCase, as reported by checkpatch.pl.
Signed-off-by: yehudis9982 <y0533159982@gmail.com>
---
drivers/staging/sm750fb/sm750_accel.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/sm... | {
"author": "yehudis9982 <y0533159982@gmail.com>",
"date": "Mon, 2 Feb 2026 19:12:43 +0200",
"thread_id": "2026020201-monogamy-sash-4866@gregkh.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.
The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optio... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:10 +0530",
"thread_id": "20260202180922.1692428-1-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.
This provides a more convenient API for... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:11 +0530",
"thread_id": "20260202180922.1692428-1-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.
Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.
Signed-off-by:... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:12 +0530",
"thread_id": "20260202180922.1692428-1-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.
Core clk is now properly managed alongside the other ... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:13 +0530",
"thread_id": "20260202180922.1692428-1-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.
Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactiva... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:14 +0530",
"thread_id": "20260202180922.1692428-1-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
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