source large_stringclasses 2
values | subject large_stringclasses 112
values | code large_stringclasses 112
values | critique large_stringlengths 61 3.04M ⌀ | metadata dict |
|---|---|---|---|---|
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Niklas,
On Fri, 3 Jan 2025 at 19:55, Niklas Cassel <cassel@kernel.org> wrote:
I am unable to reproduce this issue on my end. Could you share your
config file with me?
Additionally, if we build most of the ROCKCHIP components as modules..."
You will see this warning, which is the main reason for this patch
[ 34.... | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Sun, 5 Jan 2025 23:16:05 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Andrew,
On Fri, 3 Jan 2025 at 21:34, Andrew Lunn <andrew@lunn.ch> wrote:
According to the RKRK3588 TRM-Part1 (section 25.6.11 Clock
Architecture), in RGMII mode,
the TX clock source is exclusively derived from the CRU (Clock Request Unit).
To dynamically adjust the timing alignment between TX/RX clocks and
data, de... | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Sun, 5 Jan 2025 23:16:21 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Sun, Jan 05, 2025 at 11:16:21PM +0530, Anand Moon wrote:
O.K, let me repeat what i have said a number of times over the last
couple of years.
phy-mode = "rgmii" means the PCB has extra long clock lines on the
PCB, so the 2ns delay is provided by them.
phy-mode = "rgmii-id" means the MAC/PHY pair need to arrange t... | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Sun, 5 Jan 2025 18:57:23 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Andrew,
On Sun, 5 Jan 2025 at 23:27, Andrew Lunn <andrew@lunn.ch> wrote:
Thanks for this tip, I am no expert in hardware design.
Here is the schematic design of the board, it looks like RTL8125B page 24
is controlled by a PCIe 2.0 bus
[0] https://dl.radxa.com/rock5/5b/docs/hw/radxa_rock5b_v13_sch.pdf
PERSTB ... | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Mon, 6 Jan 2025 13:28:27 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Mon, Jan 06, 2025 at 01:28:27PM +0530, Anand Moon wrote:
As both me an Manivannan said earlier in this thread,
PCIe endpoint devices should not be described in device tree
(the exception is an FPGA, and when you need to describe devices
within the FPGA).
So I think that adding a "ethernet-phy" device tree node in ... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Mon, 6 Jan 2025 13:02:38 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | There are other cases when PCIe devices need a DT node. One is when
you have an onboard ethernet switch connected to the Ethernet
device. The switch has to be described in DT, and it needs a phandle
to the ethernet interface. Hence you need a DT node the phandle points
to.
You are also making the assumption that the P... | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Mon, 6 Jan 2025 14:44:19 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Andrewm,
On Mon, 6 Jan 2025 at 19:14, Andrew Lunn <andrew@lunn.ch> wrote:
Ok Thanks for clarifying.
I was just trying to understand the call trace for mdio bus which got
me confused.
[0] https://lore.kernel.org/all/Z3fKkTSFFcU9gQLg@ryzen/
Thanks
-Anand | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Tue, 7 Jan 2025 16:43:38 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | There is nothing particularly unusual in there. We see PCI bus
enumeration has found a device and bound a driver to it. The driver
has instantiated an MDIO bus, which has scanned the MDIO bus and found
a PHY. The phylib core then tried to load the kernel module needed to
drive the PHY.
Just because it is a PCI device ... | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Tue, 7 Jan 2025 14:13:34 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Andrew
On Tue, 7 Jan 2025 at 18:43, Andrew Lunn <andrew@lunn.ch> wrote:
Thanks for clarifying.
-Anand | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Tue, 7 Jan 2025 20:27:58 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Tue, Jan 07, 2025 at 02:13:34PM +0100, Andrew Lunn wrote:
Most of the time, it would be hard to define the properties of the PCI device's
internal bus in devicetree. For instance, the pinctrl/clock properties which
linux expects are to be connected to the host SoC, and not to the PCI device's
SoC (unless the whole ... | {
"author": "Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>",
"date": "Wed, 15 Jan 2025 23:19:48 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hello Anand,
I have tested this patch.
Hardware/Kernel information:
- radxa rock 5c lite
- rk3588s CPU, arm64
- defconfig NixOS kernel
- picked onto 6.18.7
- DT: rockchip/rk3588s-rock-5c.dtb
- tested both uboot (mainline) and edk2 (vendor)
On Fri, Aug 09, 2024 at 01:06:09PM +0530, Anand Moon wrote:
I found that with... | {
"author": "Grimmauld <grimmauld@grimmauld.de>",
"date": "Thu, 29 Jan 2026 15:06:59 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hello Grimmauld,
On Thu, Jan 29, 2026 at 03:06:59PM +0100, Grimmauld wrote:
I tested this patch again on the latest kernel, and it still results in
the "requesting loading a module with wait allowed while being called from
async context can result in a deadlock" warning from the modules code.
(With the calling code b... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Fri, 30 Jan 2026 11:25:37 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Niklas/ Grimmauld,
On Fri, 30 Jan 2026 at 15:55, Niklas Cassel <cassel@kernel.org> wrote:
Thanks for testing this patch.
I’ve attempted to reproduce the warning but was unable to trigger it locally.
But both CONFIG_PHYLIB and CONFIG_REALTEK_PHY are selected as buildin
for R8169 module.
I have tested with the buil... | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Sat, 31 Jan 2026 15:08:42 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Sat, Jan 31, 2026 at 03:08:42PM +0530, Anand Moon wrote:
I'm running with:
CONFIG_R8169=y
CONFIG_PHYLIB=y
CONFIG_REALTEK_PHY=y
CONFIG_REALTEK_PHY_HWMON=y
CONFIG_PCIE_ROCKCHIP_DW=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
(PHY for the PCIe 2x)
$ cat /proc/cmdline
root=/dev/nfs nfsroot=... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Mon, 2 Feb 2026 10:54:58 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Fri, Jan 30, 2026 at 11:25:37AM +0100, Niklas Cassel wrote:
FWIW, the reason why PHYLIB tries to load the module even though it is built
as built-in (i.e. is already loaded) is explained by the following comment:
https://github.com/torvalds/linux/blob/v6.19-rc8/drivers/net/phy/phy_device.c#L852-L855
Kind regards,... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Mon, 2 Feb 2026 11:02:09 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Niklas,
On Mon, 2 Feb 2026 at 15:25, Niklas Cassel <cassel@kernel.org> wrote:
I feel CONFIG_R8169 should not be built into the kernel image.
Since the driver is registered via module_pci_driver(rtl8169_pci_driver),
it is intended to be loaded as a module. In addition, this driver
requires external firmware
during i... | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Mon, 2 Feb 2026 23:35:48 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Niklas
On Mon, 2 Feb 2026 at 15:32, Niklas Cassel <cassel@kernel.org> wrote:
Yes, I have gone through the history of changes.
Thanks
-Anand | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Mon, 2 Feb 2026 23:37:50 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | These parameters can be discovered from a config register. As they will
not be used any more, mark them deprecated, make them optional, and
remove them from the example.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
Documentation/devicetree/bindings/sound/xlnx,i2s.yaml | 8 ++------
1 file changed, 2 in... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:23:14 -0500",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
sound/soc/xilinx/xlnx_i2s.c | 32 +++++++++++---------------------
1 file... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:23:15 -0500",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On Thu, Jan 29, 2026 at 12:23:15PM -0500, Sean Anderson wrote:
Given that the properties already exist it seems wise to continue to
parse them if available and prefer them over what we read from the
hardware, it would not shock me to discover that hardware exists where
the registers are inaccurate or need overriding... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 17:27:58 +0000",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 29 Jan 2026 17:37:09 +0000",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | I don't know this device at all, so i might be asking dumb
questions....
It is possible that the device supports multiple channels, but the use
case is mono, and so xlnx,num-channels is 1 in DT? Would that break
given your change?
Could it be the device supports 24 bits, but the use case only wants
16, and so has th... | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Thu, 29 Jan 2026 18:37:30 +0100",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On 1/29/26 12:27, Mark Brown wrote:
I would be surprised if such hardware exists. These properties are
automatically generated by Xilinx's tools based on the HDL core's
properties. This has a few consequences:
- They always exactly match the hardware unless someone has gone in and
modified them. I think this is unl... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:46:27 -0500",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On 1/29/26 12:37, Andrew Lunn wrote:
drv_data->channels is multiplied by 2, so there is always an even number
of channels. Pairs of channels are always muxed together and AFAICT
there's no way to disable them individually.
I don't think that's possible. There's an option to output 32-bit audio,
but none to reduce 24... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 12:51:47 -0500",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On Thu, Jan 29, 2026 at 12:46:27PM -0500, Sean Anderson wrote:
I'm not sure I follow your second point - driver authors tend to use
what?
I'd still rather see the properties get used if present, worst case
they're redundant best case we avoid regressing a currently working
system. The code is already there, ... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 18:09:28 +0000",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On 1/29/26 13:09, Mark Brown wrote:
Authors look at the devicetree node and see something like
i2s0_tx: i2s_transmitter@80120000 {
aud_mclk = <99999001>;
clock-names = "aud_mclk", "s_axi_ctrl_aclk", "s_axis_aud_aclk";
clocks = <&zynqmp_clk 74>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
compatible = "xlnx,i2s-tran... | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 13:17:45 -0500",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On Thu, Jan 29, 2026 at 01:17:45PM -0500, Sean Anderson wrote:
Oh. If the properties are there it's reasonable and sensible to use
them, them being redundant is a concern when specifying the binding but
once things are there any discrepency should usually be resolved in
favour of the binding.
We're talking a ... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Thu, 29 Jan 2026 18:46:23 +0000",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On Thu, Jan 29, 2026 at 12:46:27PM -0500, Sean Anderson wrote:
Does version 0.0 of this IP core have this register? Its not a new
addition?
Is there a synthesis option to disable this register?
Andrew | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Thu, 29 Jan 2026 20:58:19 +0100",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | On 1/29/26 14:58, Andrew Lunn wrote:
As far as I know, this register was present in 1.0 revision 0. I
reviewed the changelog for the core as well as the product guide
changelog and found no mention of any register additions.
No.
--Sean | {
"author": "Sean Anderson <sean.anderson@linux.dev>",
"date": "Thu, 29 Jan 2026 15:13:07 -0500",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | Hi Sean,
kernel test robot noticed the following build errors:
[auto build test ERROR on broonie-sound/for-next]
[also build test ERROR on broonie-spi/for-next linus/master v6.19-rc7 next-20260129]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when su... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Fri, 30 Jan 2026 14:35:30 +0800",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | +Katta, Vishal
On 1/29/26 19:46, Mark Brown wrote:
Let me add our driver owner of this device to answer some questions.
Katta: Can you please look at it?
Thanks,
Michal | {
"author": "Michal Simek <michal.simek@amd.com>",
"date": "Fri, 30 Jan 2026 09:19:26 +0100",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers | Xilinx helpfully included a read-only "config" register that contains
configuration parameters. Discover our parameters from this register
instead of reading them from the device tree.
Sean Anderson (2):
dt-bindings: sound: xlnx,i2s: Make discoverable parameters optional
ASoC: xilinx: xlnx_i2s: Discover parameter... | Hi,
>> and go "Ah, there are the properties I need." On some Xilinx cores this
>> is the only way to discover certain properties, so people have gotten into
>> the habit of using them even when these properties can be read from the
>> device itself.
> Oh. If the properties are there it's reasonable and sensible... | {
"author": "Peter Korsgaard <peter@korsgaard.com>",
"date": "Mon, 02 Feb 2026 18:52:27 +0100",
"thread_id": "87jywvvxr8.fsf@dell.be.48ers.dk.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | Modify online_memory_block() to accept the online type through its arg
parameter rather than calling mhp_get_default_online_type() internally.
This prepares for allowing callers to specify explicit online types.
Update the caller in add_memory_resource() to pass the default online
type via a local variable.
No functi... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:34 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | Enable dax kmem driver to select how to online the memory rather than
implicitly depending on the system default. This will allow users of
dax to plumb through a preferred auto-online policy for their region.
Refactor and new interface:
Add __add_memory_driver_managed() which accepts an explicit online_type
and expor... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:35 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | There is no way for drivers leveraging dax_kmem to plumb through a
preferred auto-online policy - the system default policy is forced.
Add online_type field to DAX device creation path to allow drivers
to specify an auto-online policy when using the kmem driver.
Current callers initialize online_type to mhp_get_defau... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:36 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | Move the pmem region driver logic from region.c into pmem_region.c.
No functional changes.
Signed-off-by: Gregory Price <gourry@gourry.net>
---
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/core.h | 1 +
drivers/cxl/core/pmem_region.c | 191 +++++++++++++++++++++++++++++++++
drivers/cxl/core/regi... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:38 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | Move the CXL DAX region device infrastructure from region.c into a
new dax_region.c file.
No functional changes.
Signed-off-by: Gregory Price <gourry@gourry.net>
---
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/core.h | 1 +
drivers/cxl/core/dax_region.c | 113 ++++++++++++++++++++++++++++++++++
d... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:39 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | Add a new cxl_devdax_region driver that probes CXL regions in device
dax mode and creates dax_region devices. This allows explicit binding to
the device_dax dax driver instead of the kmem driver.
Exports to_cxl_region() to core.h so it can be used by the driver.
Signed-off-by: Gregory Price <gourry@gourry.net>
---
d... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:40 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | CXL regions may wish not to auto-configure their memory as dax kmem,
but the current plumbing defaults all cxl-created dax devices to the
kmem driver. This exposes them to hotplug policy, even if the user
intends to use the memory as a dax device.
Add plumbing to allow CXL drivers to select whether a DAX region shoul... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:37 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | Explain the binding process for sysram and daxdev regions which are
explicit about which dax driver to use during region creation.
Jonathan Corbet <corbet@lwn.net>
Signed-off-by: Gregory Price <gourry@gourry.net>
---
.../driver-api/cxl/linux/cxl-driver.rst | 43 +++++++++++++++++++
.../driver-api/cxl/linux/dax... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:42 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | In the current kmem driver binding process, the only way for users
to define hotplug policy is via a build-time option, or by not
onlining memory by default and setting each individual memory block
online after hotplug occurs. We can solve this with a configuration
step between region-probe and dax-probe.
Add the inf... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:04:41 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | Annoyingly, my email client has been truncating my titles:
cxl: explicit DAX driver selection and hotplug policy for CXL regions
~Gregory | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Thu, 29 Jan 2026 16:17:55 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Thu, Jan 29, 2026 at 04:04:33PM -0500, Gregory Price wrote:
Looks like build regression on configs without hotplug
MMOP_ defines and mhp_get_default_online_type() undefined
Will let this version sit for a bit before spinning a v2
~Gregory | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Fri, 30 Jan 2026 12:34:33 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On 1/29/2026 3:04 PM, Gregory Price wrote:
This technically comes up in the devdax_region driver patch first, but I noticed it here
so this is where I'm putting it:
I like the idea here, but the implementation is all off. Firstly, devm_cxl_add_sysram_region()
is never called outside of sysram_region_driver::probe(), ... | {
"author": "\"Cheatham, Benjamin\" <benjamin.cheatham@amd.com>",
"date": "Fri, 30 Jan 2026 15:27:12 -0600",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Fri, Jan 30, 2026 at 03:27:12PM -0600, Cheatham, Benjamin wrote:
I originally tried doing with region0/region_driver, but that design
pattern is also confusing - and it creates differently bad patterns.
echo region0 > decoder0.0/create_ram_region -> creates region0
# Current pattern
echo region > dr... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Fri, 30 Jan 2026 17:12:50 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On 1/30/2026 4:12 PM, Gregory Price wrote:
Ok, that makes sense. I think I just got lost in the sauce while looking at this last
week and this explanation helped a lot.>
I think this was the source of my misunderstanding. I was trying to understand how it
works for auto regions when it's never meant to apply to them... | {
"author": "\"Cheatham, Benjamin\" <benjamin.cheatham@amd.com>",
"date": "Mon, 2 Feb 2026 11:02:37 -0600",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Thu, 29 Jan 2026 16:04:34 -0500
Gregory Price <gourry@gourry.net> wrote:
Trivial comment inline. I don't really care either way.
Pushing the policy up to the caller and ensuring it's explicitly constant
for all the memory blocks (as opposed to relying on locks) seems sensible to me
even without anything else.
Rev... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Mon, 2 Feb 2026 17:10:29 +0000",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Thu, 29 Jan 2026 16:04:35 -0500
Gregory Price <gourry@gourry.net> wrote:
Hi Gregory,
I think maybe I'd have left the export for the first user outside of
memory_hotplug.c. Not particularly important however.
Maybe talk about why a caller of __add_memory_driver_managed() might want
the default? Feels like that's... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Mon, 2 Feb 2026 17:25:24 +0000",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Mon, Feb 02, 2026 at 11:02:37AM -0600, Cheatham, Benjamin wrote:
Auto regions explicitly use the dax_kmem path (all existing code,
unchanged)- which auto-plugs into dax/hotplug.
I do get what you're saying that everything binds on a region type,
I will look a little closer at this and see if there's something more... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Mon, 2 Feb 2026 12:41:31 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Mon, Feb 02, 2026 at 05:10:29PM +0000, Jonathan Cameron wrote:
ack. will update for next version w/ Ben's notes and the build fix.
Thanks!
~Gregory | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Mon, 2 Feb 2026 12:46:25 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Thu, 29 Jan 2026 16:04:37 -0500
Gregory Price <gourry@gourry.net> wrote:
LGTM
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Mon, 2 Feb 2026 17:54:17 +0000",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Thu, 29 Jan 2026 16:04:38 -0500
Gregory Price <gourry@gourry.net> wrote:
Needs to answer the question: Why?
Minor stuff inline.
Maybe sneak in dropping that trailing comma whilst you are moving it.
...
Bonus line... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Mon, 2 Feb 2026 17:56:40 +0000",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Thu, 29 Jan 2026 16:04:39 -0500
Gregory Price <gourry@gourry.net> wrote:
Likewise. Why? | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Mon, 2 Feb 2026 17:57:11 +0000",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [PATCH 0/9] cxl: explicit DAX driver selection and hotplug | Currently, CXL regions that create DAX devices have no mechanism to
control select the hotplug online policy for kmem regions at region
creation time. Users must either rely on a build-time default or
manually configure each memory block after hotplug occurs.
Additionally, there is no explicit way to choose between de... | On Mon, Feb 02, 2026 at 05:25:24PM +0000, Jonathan Cameron wrote:
Less about why they want the default, more about maintaining backward
compatibility.
In the cxl driver, Ben pointed out something that made me realize we can
change `region/bind()` to actually use the new `sysram/bind` path by
just adding a one line `s... | {
"author": "Gregory Price <gourry@gourry.net>",
"date": "Mon, 2 Feb 2026 13:02:10 -0500",
"thread_id": "20260129210442.3951412-1-gourry@gourry.net.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | The page allocated in io_mem_alloc_compound() is actually used as a folio
later in io_region_mmap(). So allocate a folio instead of a compound page
and rename io_mem_alloc_compound() to io_mem_alloc_folio().
This prepares for code separation of compound page and folio in a follow-up
commit.
Signed-off-by: Zi Yan <ziy... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Thu, 29 Jan 2026 22:48:14 -0500",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | Current code uses folio_set_large_rmappable() on after-split folios, but
these folios should be treated as compound pages and converted to folios
with page_rmappable_folio().
This prepares for code separation of compound page and folio in a follow-up
commit.
Signed-off-by: Zi Yan <ziy@nvidia.com>
---
mm/huge_memory.... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Thu, 29 Jan 2026 22:48:15 -0500",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | Commit f708f6970cc9 ("mm/hugetlb: fix kernel NULL pointer dereference when
migrating hugetlb folio") fixed a NULL pointer dereference when
folio_undo_large_rmappable(), now folio_unqueue_deferred_list(), is used on
hugetlb to clear deferred_list. It cleared large_rmappable flag on hugetlb.
hugetlb is rmappable, thus cl... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Thu, 29 Jan 2026 22:48:16 -0500",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | A compound page is not a folio. Using struct folio in compound_nr() and
compound_order() is misleading. Use struct page and refer to the right
subpage of a compound page to set compound page order. compound_nr() is
calculated using compound_order() instead of reading folio->_nr_pages.
Signed-off-by: Zi Yan <ziy@nvidia... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Thu, 29 Jan 2026 22:48:17 -0500",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | A compound page is not a folio. Using struct folio in prep_compound_head()
causes confusion, since the input page is not a folio. The compound page to
folio conversion happens in page_rmappable_folio(). So move folio code from
prep_compound_head() to page_rmappable_folio().
After the change, a compound page no longer ... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Thu, 29 Jan 2026 22:48:18 -0500",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | syzbot ci has tested the following series
[v1] Separate compound page from folio
https://lore.kernel.org/all/20260130034818.472804-1-ziy@nvidia.com
* [RFC PATCH 1/5] io_uring: allocate folio in io_mem_alloc_compound() and function rename
* [RFC PATCH 2/5] mm/huge_memory: use page_rmappable_folio() to convert after-spl... | {
"author": "syzbot ci <syzbot+ci7f632827e1b1c91b@syzkaller.appspotmail.com>",
"date": "Fri, 30 Jan 2026 00:15:47 -0800",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | On 30 Jan 2026, at 3:15, syzbot ci wrote:
The issue comes from alloc_one_pg_vec_page() in net/packet/af_packet.c.
It allocates a compound page with __GFP_COMP, but latter does vm_insert_page()
in packet_mmap(), using it as a folio.
The fix below is a hack. We will need a get_free_folios() instead.
I will check all _... | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Fri, 30 Jan 2026 11:39:40 -0500",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | On 2026/1/30 11:48, Zi Yan wrote:
Nit:
Since we're switching to folio_alloc(), which already adds __GFP_COMP
internally, the "else if (order)" part above can be dropped while at it.
IIUC, for order == 0, __GFP_COMP gets ignored anyway:
- prep_new_page() won't call prep_compound_page() (since order is zero)
- p... | {
"author": "Lance Yang <lance.yang@linux.dev>",
"date": "Sat, 31 Jan 2026 23:30:35 +0800",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | On 31 Jan 2026, at 10:30, Lance Yang wrote:
Sure. Will update it in the next version. Thanks.
--
Best Regards,
Yan, Zi | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Sat, 31 Jan 2026 21:04:53 -0500",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | On 1/30/26 11:48 AM, Zi Yan wrote:
IIUC, this will break the semantics of the is_transparent_hugepage() and
might trigger a split of a hugetlb folio, right?
static inline bool is_transparent_hugepage(const struct folio *folio)
{
if (!folio_test_large(folio))
return false;
return is_huge_zero_folio(folio) ||
f... | {
"author": "Baolin Wang <baolin.wang@linux.alibaba.com>",
"date": "Mon, 2 Feb 2026 11:59:39 +0800",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [RFC PATCH 0/5] Separate compound page from folio | Hi all,
Based on my discussion with Jason about device private folio
reinitialization[1], I realize that the concepts of compound page and folio
are mixed together and confusing, as people think a compound page is equal
to a folio. This is not true, since a compound page means a group of
pages is managed as a whole an... | On 1 Feb 2026, at 22:59, Baolin Wang wrote:
Oh, I missed this. I will check all folio_test_large_rmappable() callers
and filter out hugetlb if necessary.
Thank you for pointing this out.
Best Regards,
Yan, Zi | {
"author": "Zi Yan <ziy@nvidia.com>",
"date": "Mon, 02 Feb 2026 12:11:45 -0500",
"thread_id": "21EACA83-C358-4FE7-BE2F-415A7EDC1485@nvidia.com.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | Replace direct comparisons of hv_result(status) against
HV_STATUS_INSUFFICIENT_MEMORY with a new hv_result_needs_memory() helper
function.
This improves code readability and provides a consistent and extendable
interface for checking out-of-memory conditions in hypercall results.
No functional changes intended.
Signe... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:58:57 +0000",
"thread_id": "177005514346.120041.5702271891856790910.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | Introduce hv_deposit_memory_node() and hv_deposit_memory() helper
functions to handle memory deposition with proper error handling.
The new hv_deposit_memory_node() function takes the hypervisor status
as a parameter and validates it before depositing pages. It checks for
HV_STATUS_INSUFFICIENT_MEMORY specifically and... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:03 +0000",
"thread_id": "177005514346.120041.5702271891856790910.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | The HV_STATUS_INSUFFICIENT_CONTIGUOUS_MEMORY status indicates that the
hypervisor lacks sufficient contiguous memory for its internal allocations.
When this status is encountered, allocate and deposit
HV_MAX_CONTIGUOUS_ALLOCATION_PAGES contiguous pages to the hypervisor.
HV_MAX_CONTIGUOUS_ALLOCATION_PAGES is defined i... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:09 +0000",
"thread_id": "177005514346.120041.5702271891856790910.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | When creating guest partition objects, the hypervisor may fail to
allocate root partition pages and return an insufficient memory status.
In this case, deposit memory using the root partition ID instead.
Note: This error should never occur in a guest of L1VH partition context.
Signed-off-by: Stanislav Kinsburskii <sk... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:14 +0000",
"thread_id": "177005514346.120041.5702271891856790910.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Add verify-only public key crypto support for ML-DSA so that the
X.509/PKCS#7 signature verification code, as used by module signing,
amongst other things, can make use of it through the common crypto_sig API.
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
cc: Eric ... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:06 +0000",
"thread_id": "20260202170216.2467036-2-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Calculate the SHA256 hash for blacklisting purposes independently of the
signature hash (which may be something other than SHA256).
This is necessary because when ML-DSA is used, no digest is calculated.
Note that this represents a change of behaviour in that the hash used for
the blacklist check would previously hav... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:07 +0000",
"thread_id": "20260202170216.2467036-2-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Rename ->digest and ->digest_len to ->m and ->m_size to represent the input
to the signature verification algorithm, reflecting that ->digest may no
longer actually *be* a digest.
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
cc: Lukas Wunner <lukas@wunner.de>
cc: ... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:08 +0000",
"thread_id": "20260202170216.2467036-2-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow the data to be verified in a PKCS#7 or CMS message to be passed
directly to an asymmetric cipher algorithm (e.g. ML-DSA) if it wants to do
whatever passes for hashing/digestion itself. The normal digestion of the
data is then skipped as that would be ignored unless another signed info in
the message has some oth... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:09 +0000",
"thread_id": "20260202170216.2467036-2-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Add support for ML-DSA keys and signatures to the CMS/PKCS#7 and X.509
implementations. ML-DSA-44, -65 and -87 are all supported. For X.509
certificates, the TBSCertificate is required to be signed directly; for
CMS, direct signing of the data is preferred, though use of SHA512 (and
only that) as an intermediate hash... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:10 +0000",
"thread_id": "20260202170216.2467036-2-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow ML-DSA module signing to be enabled.
Note that OpenSSL's CMS_*() function suite does not, as of OpenSSL-3.6,
support the use of CMS_NOATTR with ML-DSA, so the prohibition against using
signedAttrs with module signing has to be removed. The selected digest
then applies only to the algorithm used to calculate the... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:11 +0000",
"thread_id": "20260202170216.2467036-2-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow the rejection of authenticatedAttributes in PKCS#7 (signedAttrs in
CMS) to be waived in the kernel config for ML-DSA when used for module
signing. This reflects the issue that openssl < 4.0 cannot do this and
openssl-4 has not yet been released.
This does not permit RSA, ECDSA or ECRDSA to be so waived (behavio... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:12 +0000",
"thread_id": "20260202170216.2467036-2-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | jbd2_inode fields are updated under journal->j_list_lock, but some
paths read them without holding the lock (e.g. fast commit
helpers and the ordered truncate fast path).
Use READ_ONCE() for these lockless reads to correct the
concurrency assumptions.
Suggested-by: Jan Kara <jack@suse.com>
Signed-off-by: Li Chen <me@... | {
"author": "Li Chen <me@linux.beauty>",
"date": "Fri, 30 Jan 2026 11:12:30 +0800",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | ext4 journal commit callbacks access jbd2_inode fields such as
i_transaction and i_dirty_start/end without holding journal->j_list_lock.
Use READ_ONCE() for these reads to correct the concurrency assumptions.
Suggested-by: Jan Kara <jack@suse.com>
Signed-off-by: Li Chen <me@linux.beauty>
---
fs/ext4/inode.c | 6 +++... | {
"author": "Li Chen <me@linux.beauty>",
"date": "Fri, 30 Jan 2026 11:12:31 +0800",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | ocfs2 journal commit callback reads jbd2_inode dirty range fields without
holding journal->j_list_lock.
Use READ_ONCE() for these reads to correct the concurrency assumptions.
Suggested-by: Jan Kara <jack@suse.com>
Signed-off-by: Li Chen <me@linux.beauty>
---
fs/ocfs2/journal.c | 7 +++++--
1 file changed, 5 inserti... | {
"author": "Li Chen <me@linux.beauty>",
"date": "Fri, 30 Jan 2026 11:12:32 +0800",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | On Fri, Jan 30, 2026 at 11:12:32AM +0800, Li Chen wrote:
I don't think this is the right solution to the problem. If it is,
there needs to be much better argumentation in the commit message.
As I understand it, jbd2_journal_file_inode() initialises jinode,
then adds it to the t_inode_list, then drops the j_list_lock... | {
"author": "Matthew Wilcox <willy@infradead.org>",
"date": "Fri, 30 Jan 2026 05:27:59 +0000",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | Hi Matthew,
> On Fri, Jan 30, 2026 at 11:12:32AM +0800, Li Chen wrote:
> > ocfs2 journal commit callback reads jbd2_inode dirty range fields without
> > holding journal->j_list_lock.
> >
> > Use READ_ONCE() for these reads to correct the concurrency assumptions.
>
> I don't think this is the right solution to... | {
"author": "Li Chen <me@linux.beauty>",
"date": "Fri, 30 Jan 2026 20:26:40 +0800",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | On Fri, Jan 30, 2026 at 08:26:40PM +0800, Li Chen wrote:
I think that's the only issue that exists ...
I don't think that's true. I think what you're asserting is that:
int *pi;
int **ppi;
spin_lock(&lock);
*pi = 1;
*ppi = pi;
spin_unlock(&lock);
that the store to *pi must be observed before the store to *... | {
"author": "Matthew Wilcox <willy@infradead.org>",
"date": "Fri, 30 Jan 2026 16:36:28 +0000",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | Hi Matthew,
Thank you very much for the detailed explanation and for your patience.
On Sat, 31 Jan 2026 00:36:28 +0800,
Matthew Wilcox wrote:
Understood.
Yes, agreed $B!=(B thank you. I was implicitly assuming the reader had taken the same lock
at some point, which is not a valid assumption for a lockless reader... | {
"author": "Li Chen <me@linux.beauty>",
"date": "Sun, 01 Feb 2026 12:37:36 +0800",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | On Fri 30-01-26 11:12:30, Li Chen wrote:
Just one nit below. With that fixed feel free to add:
Reviewed-by: Jan Kara <jack@suse.cz>
i_vfs_inode never changes so READ_ONCE is pointless here.
Honza
--
Jan Kara <jack@suse.com>
SUSE Labs, CR | {
"author": "Jan Kara <jack@suse.cz>",
"date": "Mon, 2 Feb 2026 17:40:45 +0100",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | On Fri 30-01-26 11:12:31, Li Chen wrote:
Looks good. Feel free to add:
Reviewed-by: Jan Kara <jack@suse.cz>
Honza
--
Jan Kara <jack@suse.com>
SUSE Labs, CR | {
"author": "Jan Kara <jack@suse.cz>",
"date": "Mon, 2 Feb 2026 17:41:39 +0100",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | On Mon 02-02-26 17:40:45, Jan Kara wrote:
One more note: I've realized that for this to work you also need to make
jbd2_journal_file_inode() use WRITE_ONCE() when updating i_dirty_start,
i_dirty_end and i_flags.
Honza
--
Jan Kara <jack@suse.com>
SUSE Labs, CR | {
"author": "Jan Kara <jack@suse.cz>",
"date": "Mon, 2 Feb 2026 17:52:30 +0100",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH 0/3] jbd2/ext4/ocfs2: READ_ONCE for lockless jinode reads | This series adds READ_ONCE() for existing lockless reads of
jbd2_inode fields in jbd2 and filesystem callbacks used by ext4 and ocfs2.
This is based on Jan's suggestion in the review of the ext4 jinode
publication race fix. [1]
[1]: https://lore.kernel.org/all/4jxwogttddiaoqbstlgou5ox6zs27ngjjz5ukrxafm2z5ijxod@so4eqn... | On Fri 30-01-26 16:36:28, Matthew Wilcox wrote:
Well, the above reasonably accurately describes the code making jinode
visible. The reader code is like:
spin_lock(&lock);
pi = *ppi;
spin_unlock(&lock);
work with pi
so it is guaranteed to see pi properly initialized. The problem is that
"work with pi" can... | {
"author": "Jan Kara <jack@suse.cz>",
"date": "Mon, 2 Feb 2026 18:17:49 +0100",
"thread_id": "emoxxh6xn5mm5dl2ra5vz2g7t553z4kxricolekz6umiwcu5ys@ogxvdjfq66u3.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Extend the DPLL core to support associating a DPLL pin with a firmware
node. This association is required to allow other subsystems (such as
network drivers) to locate and request specific DPLL pins defined in
the Device Tree or ACPI.
* Add a .fwnode field to the struct dpll_pin
* Introduce dpll_pin_fwnode_set() helpe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:30 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Associate the registered DPLL pin with its firmware node by calling
dpll_pin_fwnode_set().
This links the created pin object to its corresponding DT/ACPI node
in the DPLL core. Consequently, this enables consumer drivers (such as
network drivers) to locate and request this specific pin using the
fwnode_dpll_pin_find()... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:31 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Petr Oros <poros@redhat.com>
Currently, the DPLL subsystem reports events (creation, deletion, changes)
to userspace via Netlink. However, there is no mechanism for other kernel
components to be notified of these events directly.
Add a raw notifier chain to the DPLL core protected by dpll_lock. This
allows othe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:32 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Allow drivers to register DPLL pins without manually specifying a pin
index.
Currently, drivers must provide a unique pin index when calling
dpll_pin_get(). This works well for hardware-mapped pins but creates
friction for drivers handling virtual pins or those without a strict
hardware indexing scheme.
Introduce DPL... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:33 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add parsing for the "mux" string in the 'connection-type' pin property
mapping it to DPLL_PIN_TYPE_MUX.
Recognizing this type in the driver allows these pins to be taken as
parent pins for pin-on-pin pins coming from different modules (e.g.
network drivers).
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:34 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Refactor the reference counting mechanism for DPLL devices and pins to
improve consistency and prevent potential lifetime issues.
Introduce internal helpers __dpll_{device,pin}_{hold,put}() to
centralize reference management.
Update the internal XArray reference helpers (dpll_xa_ref_*) to
automatically grab a referen... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:35 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add support for the REF_TRACKER infrastructure to the DPLL subsystem.
When enabled, this allows developers to track and debug reference counting
leaks or imbalances for dpll_device and dpll_pin objects. It records stack
traces for every get/put operation and exposes this information via
debugfs at:
/sys/kernel/debug... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:36 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Update existing DPLL drivers to utilize the DPLL reference count
tracking infrastructure.
Add dpll_tracker fields to the drivers' internal device and pin
structures. Pass pointers to these trackers when calling
dpll_device_get/put() and dpll_pin_get/put().
This allows developers to inspect the specific references hel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:37 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Implement SyncE support for the E825-C Ethernet controller using the
DPLL subsystem. Unlike E810, the E825-C architecture relies on platform
firmware (ACPI) to describe connections between the NIC's recovered clock
outputs and external DPLL inputs.
Implement... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:38 +0100",
"thread_id": "20260202171638.17427-7-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCHSET v12 sched_ext/for-6.20] Add a deadline server for sched_ext tasks | sched_ext tasks can be starved by long-running RT tasks, especially since
RT throttling was replaced by deadline servers to boost only SCHED_NORMAL
tasks.
Several users in the community have reported issues with RT stalling
sched_ext tasks. This is fairly common on distributions or environments
where applications like... | From: Joel Fernandes <joelagnelf@nvidia.com>
The defer params were not cleared in __dl_clear_params. Clear them.
Without this is some of my test cases are flaking and the DL timer is
not starting correctly AFAICS.
Fixes: a110a81c52a9 ("sched/deadline: Deferrable dl server")
Tested-by: Christian Loehle <christian.loe... | {
"author": "Andrea Righi <arighi@nvidia.com>",
"date": "Mon, 26 Jan 2026 10:58:59 +0100",
"thread_id": "aYDUqdQquFcqj7rQ@slm.duckdns.org.mbox.gz"
} |
lkml | [PATCHSET v12 sched_ext/for-6.20] Add a deadline server for sched_ext tasks | sched_ext tasks can be starved by long-running RT tasks, especially since
RT throttling was replaced by deadline servers to boost only SCHED_NORMAL
tasks.
Several users in the community have reported issues with RT stalling
sched_ext tasks. This is fairly common on distributions or environments
where applications like... | From: Joel Fernandes <joelagnelf@nvidia.com>
Updating "ppos" on error conditions does not make much sense. The pattern
is to return the error code directly without modifying the position, or
modify the position on success and return the number of bytes written.
Since on success, the return value of apply is 0, there ... | {
"author": "Andrea Righi <arighi@nvidia.com>",
"date": "Mon, 26 Jan 2026 10:59:00 +0100",
"thread_id": "aYDUqdQquFcqj7rQ@slm.duckdns.org.mbox.gz"
} |
lkml | [PATCHSET v12 sched_ext/for-6.20] Add a deadline server for sched_ext tasks | sched_ext tasks can be starved by long-running RT tasks, especially since
RT throttling was replaced by deadline servers to boost only SCHED_NORMAL
tasks.
Several users in the community have reported issues with RT stalling
sched_ext tasks. This is fairly common on distributions or environments
where applications like... | From: Joel Fernandes <joelagnelf@nvidia.com>
Currently the DL server interface for applying parameters checks
CFS-internals to identify if the server is active. This is error-prone
and makes it difficult when adding new servers in the future.
Fix it, by using dl_server_active() which is also used by the DL server
cod... | {
"author": "Andrea Righi <arighi@nvidia.com>",
"date": "Mon, 26 Jan 2026 10:59:01 +0100",
"thread_id": "aYDUqdQquFcqj7rQ@slm.duckdns.org.mbox.gz"
} |
lkml | [PATCHSET v12 sched_ext/for-6.20] Add a deadline server for sched_ext tasks | sched_ext tasks can be starved by long-running RT tasks, especially since
RT throttling was replaced by deadline servers to boost only SCHED_NORMAL
tasks.
Several users in the community have reported issues with RT stalling
sched_ext tasks. This is fairly common on distributions or environments
where applications like... | sched_ext currently suffers starvation due to RT. The same workload when
converted to EXT can get zero runtime if RT is 100% running, causing EXT
processes to stall. Fix it by adding a DL server for EXT.
A kselftest is also included later to confirm that both DL servers are
functioning correctly:
# ./runner -t rt_st... | {
"author": "Andrea Righi <arighi@nvidia.com>",
"date": "Mon, 26 Jan 2026 10:59:02 +0100",
"thread_id": "aYDUqdQquFcqj7rQ@slm.duckdns.org.mbox.gz"
} |
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