source large_stringclasses 2
values | subject large_stringclasses 112
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values | critique large_stringlengths 61 3.04M ⌀ | metadata dict |
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lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | On Tue 2025-11-25 14:08:40, Francesco Valla wrote:
Honestly, I am not sure if it would break anything. The fact is
that printk() always used monotonic timers. And it is possible
that some userspace depends on it.
I personally thing that non-monotonic time stamps might be confusing
but they should not cause any seriou... | {
"author": "Petr Mladek <pmladek@suse.com>",
"date": "Wed, 26 Nov 2025 13:55:32 +0100",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | I worried about this, but I'm skeptical it's a big deal. Humans might be
a little confused, but it's not difficult to see what's going on just by looking
at the timestamps. If a tool breaks, especially something that's used
in automation, e.g. it's used to report results, or is in some sort of CI
loop where the ... | {
"author": "\"Bird, Tim\" <Tim.Bird@sony.com>",
"date": "Thu, 27 Nov 2025 00:03:32 +0000",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | I thought about this while I was creating this.
It wouldn't require the extra configuration for MULT and SHIFT (which would be nice),
and it would be, as you say, very obvious that this was not a regular timestamp.
This means it could be enabled on a generic kernel (making more likely it could be
enabled by defaul... | {
"author": "\"Bird, Tim\" <Tim.Bird@sony.com>",
"date": "Thu, 27 Nov 2025 00:16:23 +0000",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | Hi Tim,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.18-rc7]
[cannot apply to akpm-mm/mm-everything next-20251127]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base'... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Thu, 27 Nov 2025 10:13:23 +0100",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | On Thu 2025-11-27 00:16:23, Bird, Tim wrote:
I guess that it might break even basic tools, like dmesg, journalctl,
or crash.
A solution might be to pass it as an extra information to the official
timestamp, for example:
+ on console:
<level>[timestamp][callerid][cl cycles] message
<6>[ 0.000000][ ... | {
"author": "Petr Mladek <pmladek@suse.com>",
"date": "Thu, 27 Nov 2025 17:16:48 +0100",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | During early boot, printk timestamps are reported as zero before
kernel timekeeping starts (e.g. before time_init()). This
hinders boot-time optimization efforts. This period is about 400
milliseconds for many current desktop and embedded machines
running Linux.
Add support to save cycles during early boot, and outp... | {
"author": "Tim Bird <tim.bird@sony.com>",
"date": "Sat, 24 Jan 2026 12:40:27 -0700",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | Hi Tim,
I tested this both on X86_64 QEMU and on a i.MX93 (ARM64) and can
confirm it is working as expected. Auto-calc of calibration data is far
better than the configuration parameters in v1.
It is slightly confusing to see a time value printed to serial output
and another one inside kmsg, but that's a human thing ... | {
"author": "Francesco Valla <francesco@valla.it>",
"date": "Sun, 25 Jan 2026 15:41:35 +0100",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | Hi Tim,
On Sat, 24 Jan 2026 at 20:41, Tim Bird <tim.bird@sony.com> wrote:
Thanks for the update!
No need to cast to u64, as the second operand of the OR is u64 anyway.
BIT_ULL(63)
I think it would be good to have a #define for this at the top.
Please use the mul_u64_u32_shr() helper.
Please wrap this block in c... | {
"author": "Geert Uytterhoeven <geert@linux-m68k.org>",
"date": "Mon, 26 Jan 2026 11:12:42 +0100",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | Agreed. I wasn't too worried about it, because most serious developers working
on boot-time will not be watching early messages over serial console. (Usually they
use 'quiet' or some lower log level). But on qemu, it does look strange to see 0s
on the first output sequence, and then non-zeroes when using dmesg la... | {
"author": "\"Bird, Tim\" <Tim.Bird@sony.com>",
"date": "Mon, 26 Jan 2026 16:52:57 +0000",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | I'll look at this. Is BIT_ULL(63) preferred over (1ULL << 63)?
Do you think something like "HIGH_BIT63" would be good enough?
OK. I did not know about that.
I can check, but do you know offhand if timestamps from local_clock() on 32-bit systems are
always 64-bit nanoseconds? I assume so looking at the prin... | {
"author": "\"Bird, Tim\" <Tim.Bird@sony.com>",
"date": "Mon, 26 Jan 2026 17:11:40 +0000",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | Hi Tim,
On Mon, 26 Jan 2026 at 18:11, Bird, Tim <Tim.Bird@sony.com> wrote:
When you refer to the bit value, yes: BIT() for unsigned long, BIT_ULL()
for unsigned long long; recently we got BIT_U{8,16,32,64}(), too).
I'd name it for what it means, not what it does, e.g. EARLY_TS_FLAG?
I am not 100% sure, but I thin... | {
"author": "Geert Uytterhoeven <geert@linux-m68k.org>",
"date": "Tue, 27 Jan 2026 09:10:31 +0100",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH] printk: add early_counter_ns routine for printk blind spot | From: Tim Bird <tim.bird@sony.com>
During early boot, printk timestamps are reported as zero,
which creates a blind spot in early boot timings. This blind
spot hinders timing and optimization efforts for code that
executes before time_init(), which is when local_clock() is
initialized sufficiently to start returning ... | On Mon 2026-01-26 16:52:57, Bird, Tim wrote:
I see the following in the serial console output:
[ 3.288049][ T1] Write protecting the kernel read-only data: 36864k
[ 3.298554][ T1] Freeing unused kernel image (text/rodata gap) memory: 1656K
[ 3.318942][ T1] Freeing unused kernel image (rodata/data ga... | {
"author": "Petr Mladek <pmladek@suse.com>",
"date": "Mon, 2 Feb 2026 17:23:59 +0100",
"thread_id": "aYDPn2EJgJIWGDhM@pathway.mbox.gz"
} |
lkml | [PATCH v4 0/3] bpf/verifier: Expand the usage scenarios of bpf_kptr_xchg | From: Chengkaitao <chengkaitao@kylinos.cn>
When using bpf_kptr_xchg, we triggered the following error:
31: (85) call bpf_kptr_xchg#194
function calls are not allowed while holding a lock
bpf_kptr_xchg can now be used in lock-held contexts, so we extended
its usage scope in [patch 1/2].
When writing test cases... | From: Chengkaitao <chengkaitao@kylinos.cn>
For the following scenario:
struct tree_node {
struct bpf_rb_node node;
struct request __kptr *req;
u64 key;
};
struct bpf_rb_root tree_root __contains(tree_node, node);
struct bpf_spin_lock tree_lock;
If we need to traverse all nodes in the rbtree, retrieve the ... | {
"author": "Chengkaitao <pilgrimtao@gmail.com>",
"date": "Mon, 2 Feb 2026 17:00:49 +0800",
"thread_id": "CAADnVQJPFANbYvYYyG3OQdXh4174bGwsamAzD8HZ5f=noS=BnQ@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v4 0/3] bpf/verifier: Expand the usage scenarios of bpf_kptr_xchg | From: Chengkaitao <chengkaitao@kylinos.cn>
When using bpf_kptr_xchg, we triggered the following error:
31: (85) call bpf_kptr_xchg#194
function calls are not allowed while holding a lock
bpf_kptr_xchg can now be used in lock-held contexts, so we extended
its usage scope in [patch 1/2].
When writing test cases... | From: Chengkaitao <chengkaitao@kylinos.cn>
When traversing an rbtree using bpf_rbtree_left/right, if bpf_kptr_xchg
is used to access the __kptr pointer contained in a node, it currently
requires first removing the node with bpf_rbtree_remove and clearing the
NON_OWN_REF flag, then re-adding the node to the original rb... | {
"author": "Chengkaitao <pilgrimtao@gmail.com>",
"date": "Mon, 2 Feb 2026 17:00:50 +0800",
"thread_id": "CAADnVQJPFANbYvYYyG3OQdXh4174bGwsamAzD8HZ5f=noS=BnQ@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v4 0/3] bpf/verifier: Expand the usage scenarios of bpf_kptr_xchg | From: Chengkaitao <chengkaitao@kylinos.cn>
When using bpf_kptr_xchg, we triggered the following error:
31: (85) call bpf_kptr_xchg#194
function calls are not allowed while holding a lock
bpf_kptr_xchg can now be used in lock-held contexts, so we extended
its usage scope in [patch 1/2].
When writing test cases... | From: Chengkaitao <chengkaitao@kylinos.cn>
1. Allow using bpf_kptr_xchg while holding a lock.
2. When the rb_node contains a __kptr pointer, we do not need to
perform a remove-read-add operation.
This patch implements the following workflow:
1. Construct a rbtree with 16 elements.
2. Traverse the rbtree, locate th... | {
"author": "Chengkaitao <pilgrimtao@gmail.com>",
"date": "Mon, 2 Feb 2026 17:00:51 +0800",
"thread_id": "CAADnVQJPFANbYvYYyG3OQdXh4174bGwsamAzD8HZ5f=noS=BnQ@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v4 0/3] bpf/verifier: Expand the usage scenarios of bpf_kptr_xchg | From: Chengkaitao <chengkaitao@kylinos.cn>
When using bpf_kptr_xchg, we triggered the following error:
31: (85) call bpf_kptr_xchg#194
function calls are not allowed while holding a lock
bpf_kptr_xchg can now be used in lock-held contexts, so we extended
its usage scope in [patch 1/2].
When writing test cases... | On Mon, Feb 2, 2026 at 1:01 AM Chengkaitao <pilgrimtao@gmail.com> wrote:
You ignored earlier feedback. This is not ok.
pw-bot: cr | {
"author": "Alexei Starovoitov <alexei.starovoitov@gmail.com>",
"date": "Mon, 2 Feb 2026 09:56:50 -0800",
"thread_id": "CAADnVQJPFANbYvYYyG3OQdXh4174bGwsamAzD8HZ5f=noS=BnQ@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.
The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optio... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:10 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.
This provides a more convenient API for... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:11 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.
Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.
Signed-off-by:... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:12 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.
Core clk is now properly managed alongside the other ... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:13 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.
Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactiva... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:14 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle
the attachment of power domains. This often leads to duplicated code
logic across different driver probe functions.
Introduce a new helper API, geni_se_domain_attach(), to centralize
the logic for attaching "power" and "perf" domains to the GENI SE... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:15 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently
manage performance levels and operating points directly. This resulting
in code duplication across drivers. such as configuring a specific level
or find and apply an OPP based on a clock frequency.
Introduce two new helper APIs, geni_se_set_perf_leve... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:16 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add DT bindings for the QUP GENI I2C controller on sa8255p platforms.
SA8255p platform abstracts resources such as clocks, interconnect and
GPIO pins configuration in Firmware. SCMI power and perf protocol
are utilized to request resource configurations.
SA8255p platform does not require the Serial Engine (SE) common... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:17 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Moving the serial engine setup to geni_i2c_init() API for a cleaner
probe function and utilizes the PM runtime API to control resources
instead of direct clock-related APIs for better resource management.
Enables reusability of the serial engine initialization like
hibernation and deep sleep features where hardware co... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:18 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Refactor the resource initialization in geni_i2c_probe() by introducing
a new geni_i2c_resources_init() function and utilizing the common
geni_se_resources_init() framework and clock frequency mapping, making the
probe function cleaner.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Pravee... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:19 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To manage GENI serial engine resources during runtime power management,
drivers currently need to call functions for ICC, clock, and
SE resource operations in both suspend and resume paths, resulting in
code duplication across drivers.
The new geni_se_resources_activate() and geni_se_resources_deactivate()
helper APIs... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:20 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To avoid repeatedly fetching and checking platform data across various
functions, store the struct of_device_id data directly in the i2c
private structure. This change enhances code maintainability and reduces
redundancy.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <prave... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:21 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:22 +0530",
"thread_id": "20260202180922.1692428-2-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Extend the DPLL core to support associating a DPLL pin with a firmware
node. This association is required to allow other subsystems (such as
network drivers) to locate and request specific DPLL pins defined in
the Device Tree or ACPI.
* Add a .fwnode field to the struct dpll_pin
* Introduce dpll_pin_fwnode_set() helpe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:30 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Associate the registered DPLL pin with its firmware node by calling
dpll_pin_fwnode_set().
This links the created pin object to its corresponding DT/ACPI node
in the DPLL core. Consequently, this enables consumer drivers (such as
network drivers) to locate and request this specific pin using the
fwnode_dpll_pin_find()... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:31 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Petr Oros <poros@redhat.com>
Currently, the DPLL subsystem reports events (creation, deletion, changes)
to userspace via Netlink. However, there is no mechanism for other kernel
components to be notified of these events directly.
Add a raw notifier chain to the DPLL core protected by dpll_lock. This
allows othe... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:32 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Allow drivers to register DPLL pins without manually specifying a pin
index.
Currently, drivers must provide a unique pin index when calling
dpll_pin_get(). This works well for hardware-mapped pins but creates
friction for drivers handling virtual pins or those without a strict
hardware indexing scheme.
Introduce DPL... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:33 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add parsing for the "mux" string in the 'connection-type' pin property
mapping it to DPLL_PIN_TYPE_MUX.
Recognizing this type in the driver allows these pins to be taken as
parent pins for pin-on-pin pins coming from different modules (e.g.
network drivers).
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:34 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Refactor the reference counting mechanism for DPLL devices and pins to
improve consistency and prevent potential lifetime issues.
Introduce internal helpers __dpll_{device,pin}_{hold,put}() to
centralize reference management.
Update the internal XArray reference helpers (dpll_xa_ref_*) to
automatically grab a referen... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:35 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Add support for the REF_TRACKER infrastructure to the DPLL subsystem.
When enabled, this allows developers to track and debug reference counting
leaks or imbalances for dpll_device and dpll_pin objects. It records stack
traces for every get/put operation and exposes this information via
debugfs at:
/sys/kernel/debug... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:36 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | Update existing DPLL drivers to utilize the DPLL reference count
tracking infrastructure.
Add dpll_tracker fields to the drivers' internal device and pin
structures. Pass pointers to these trackers when calling
dpll_device_get/put() and dpll_pin_get/put().
This allows developers to inspect the specific references hel... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:37 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support | This series introduces Synchronous Ethernet (SyncE) support for the Intel
E825-C Ethernet controller. Unlike previous generations where DPLL
connections were implicitly assumed, the E825-C architecture relies
on the platform firmware (ACPI) to describe the physical connections
between the Ethernet controller and extern... | From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Implement SyncE support for the E825-C Ethernet controller using the
DPLL subsystem. Unlike E810, the E825-C architecture relies on platform
firmware (ACPI) to describe connections between the NIC's recovered clock
outputs and external DPLL inputs.
Implement... | {
"author": "Ivan Vecera <ivecera@redhat.com>",
"date": "Mon, 2 Feb 2026 18:16:38 +0100",
"thread_id": "20260202171638.17427-8-ivecera@redhat.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] Convert 64-bit x86/mm/pat to ptdescs | x86/mm/pat should be using ptdescs. One line has already been
converted to pagetable_free(), while the allocation sites use
get_free_pages(). This causes issues separately allocating ptdescs
from struct page.
These patches convert the allocation/free sites to use ptdescs. In
the short term, this helps enable Matthew's... | In order to separately allocate ptdescs from pages, we need all allocation
and free sites to use the appropriate functions. Convert these pte
allocation/free sites to use ptdescs.
Signed-off-by: Vishal Moola (Oracle) <vishal.moola@gmail.com>
---
arch/x86/mm/pat/set_memory.c | 15 +++++++++------
1 file changed, 9 ins... | {
"author": "\"Vishal Moola (Oracle)\" <vishal.moola@gmail.com>",
"date": "Mon, 2 Feb 2026 09:20:03 -0800",
"thread_id": "20260202172005.683870-3-vishal.moola@gmail.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] Convert 64-bit x86/mm/pat to ptdescs | x86/mm/pat should be using ptdescs. One line has already been
converted to pagetable_free(), while the allocation sites use
get_free_pages(). This causes issues separately allocating ptdescs
from struct page.
These patches convert the allocation/free sites to use ptdescs. In
the short term, this helps enable Matthew's... | In order to separately allocate ptdescs from pages, we need all allocation
and free sites to use the appropriate functions.
split_large_page() allocates a page to be used as a page table. This
should be allocating a ptdesc, so convert it.
Signed-off-by: Vishal Moola (Oracle) <vishal.moola@gmail.com>
---
arch/x86/mm/... | {
"author": "\"Vishal Moola (Oracle)\" <vishal.moola@gmail.com>",
"date": "Mon, 2 Feb 2026 09:20:05 -0800",
"thread_id": "20260202172005.683870-3-vishal.moola@gmail.com.mbox.gz"
} |
lkml | [PATCH v3 0/3] Convert 64-bit x86/mm/pat to ptdescs | x86/mm/pat should be using ptdescs. One line has already been
converted to pagetable_free(), while the allocation sites use
get_free_pages(). This causes issues separately allocating ptdescs
from struct page.
These patches convert the allocation/free sites to use ptdescs. In
the short term, this helps enable Matthew's... | In order to separately allocate ptdescs from pages, we need all allocation
and free sites to use the appropriate functions. Convert these pmd
allocation/free sites to use ptdescs.
populate_pgd() also allocates pagetables that may later be freed by
try_to_free_pmd_page(), so allocate ptdescs there as well.
Signed-off-... | {
"author": "\"Vishal Moola (Oracle)\" <vishal.moola@gmail.com>",
"date": "Mon, 2 Feb 2026 09:20:04 -0800",
"thread_id": "20260202172005.683870-3-vishal.moola@gmail.com.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | Remote DMA users may need to map or otherwise correlate DMA resources on
a per-hardware-channel basis (e.g. DWC EP eDMA linked-list windows).
However, struct dma_chan does not expose a provider-defined hardware
channel identifier.
Add an optional dma_slave_caps.hw_id field to allow DMA engine drivers
to report a provi... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 27 Jan 2026 12:34:14 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | Expose the DesignWare eDMA per-channel identifier (chan->id) via
dma_get_slave_caps(). Note that the id space is separated for each read
or write channels.
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
drivers/dma/dw-edma/dw-edma-core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/dw-edma/dw-... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 27 Jan 2026 12:34:15 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | DesignWare EP eDMA can generate interrupts both locally and remotely
(LIE/RIE). Remote eDMA users need to decide, per channel, whether
completions should be handled locally, remotely, or both. Unless
carefully configured, the endpoint and host would race to ack the
interrupt.
Introduce a dw_edma_peripheral_config that... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 27 Jan 2026 12:34:16 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | Poll completion for channels where local done/abort IRQ handling is
disabled (e.g. remote ACK scenarios).
This is useful when transaction descriptor is prepared and submitted
locally, while irq_mode is configured so that the peer is supposed to
ack the interrupts. Without polling mechanism, locally submitted
transacti... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 27 Jan 2026 12:34:17 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | Remote eDMA users may want to prepare descriptors on the remote side while
the local side only needs completion notifications.
Provide a lightweight per-channel notification callback infrastructure.
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
drivers/dma/dw-edma/dw-edma-core.c | 41 ++++++++++++++++++++++++++... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 27 Jan 2026 12:34:18 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | Some DesignWare PCIe endpoint controllers integrate a DesignWare eDMA
instance. Remote-eDMA providers (e.g. vNTB) need to expose the eDMA
register block to the host through a memory window so the host can
ioremap it and run dw_edma_probe() against the remote view.
Record the physical base and size of the eDMA register... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 27 Jan 2026 12:34:19 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | Some DesignWare PCIe endpoint controllers integrate a DesignWare eDMA
instance and allocate per-channel linked-list (LL) regions. Remote eDMA
providers may need to expose those LL regions to the host so it can
build descriptors against the remote view.
Export dwc_pcie_edma_get_ll_region() to allow higher-level code to... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 27 Jan 2026 12:34:20 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | On Tue, Jan 27, 2026 at 12:34:20PM +0900, Koichiro Den wrote:
These APIs need an user, A simple method is that add one test case in
pci-epf-test.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 28 Jan 2026 10:48:04 -0500",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | On Wed, Jan 28, 2026 at 10:48:04AM -0500, Frank Li wrote:
Thanks for the feedback.
I'm unsure whether adding DesignWare-specific coverage to pci-epf-test
would be acceptable. I'd appreciate your guidance on the preferred
approach.
One possible direction I had in mind is to keep pci-epf-test.c generic and
add an opti... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Thu, 29 Jan 2026 01:25:30 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | On Thu, Jan 29, 2026 at 01:25:30AM +0900, Koichiro Den wrote:
Add a EPC/EPF API, so dynatmic check if support DMA region or other feature.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 28 Jan 2026 22:42:29 -0500",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | On Wed, Jan 28, 2026 at 10:42:29PM -0500, Frank Li wrote:
Thank you for the comment.
Ok, I have drafted an API ([1] below).
One thing I'm unsure about is how far the pci-epf-test validation should
go. Since the API (pci_epc_get_remote_resources() in [1]) is generic and
only returns a list of (type, phys_addr, size, ... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Fri, 30 Jan 2026 16:16:11 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | On Fri, Jan 30, 2026 at 04:16:11PM +0900, Koichiro Den wrote:
Smoke test should be enough now.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Fri, 30 Jan 2026 10:07:02 -0500",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | On Fri, Jan 30, 2026 at 10:07:02AM -0500, Frank Li wrote:
I'll prepare v3 accordingly. Thanks.
Koichiro | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Sat, 31 Jan 2026 02:27:01 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | On Tue, Jan 27, 2026 at 12:34:13PM +0900, Koichiro Den wrote:
Hi Mani, Vinod (and others),
I'd appreciate your thoughts on the overall design of patches 3–5/7 when
you have a moment.
- [PATCH v2 3/7] dmaengine: dw-edma: Add per-channel interrupt routing control
https://lore.kernel.org/dmaengine/20260127033420... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Sun, 1 Feb 2026 11:32:23 +0900",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/7] dmaengine: dw-edma, PCI: dwc: Enable remote use of integrated DesignWare eDMA | Hi,
Per Frank Li's suggestion [1], this revision combines the previously posted
PCI/dwc helper series and the dmaengine/dw-edma series into a single
7-patch set. This series therefore supersedes the two earlier postings:
- [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
https://lore.ke... | On Sun, Feb 01, 2026 at 11:32:23AM +0900, Koichiro Den wrote:
According to RM:
WR_DONE_INT_STATUS
Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For
more information, see "Interrupts and Error Handling". Each bit corresponds to a DMA channel. Bit
[0] corresponds to channel 0... | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Mon, 2 Feb 2026 11:59:05 -0500",
"thread_id": "aYDX2Y0n8lD%2FiUcJ@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.
The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optio... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:10 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.
This provides a more convenient API for... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:11 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.
Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.
Signed-off-by:... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:12 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.
Core clk is now properly managed alongside the other ... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:13 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.
Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactiva... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:14 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle
the attachment of power domains. This often leads to duplicated code
logic across different driver probe functions.
Introduce a new helper API, geni_se_domain_attach(), to centralize
the logic for attaching "power" and "perf" domains to the GENI SE... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:15 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently
manage performance levels and operating points directly. This resulting
in code duplication across drivers. such as configuring a specific level
or find and apply an OPP based on a clock frequency.
Introduce two new helper APIs, geni_se_set_perf_leve... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:16 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add DT bindings for the QUP GENI I2C controller on sa8255p platforms.
SA8255p platform abstracts resources such as clocks, interconnect and
GPIO pins configuration in Firmware. SCMI power and perf protocol
are utilized to request resource configurations.
SA8255p platform does not require the Serial Engine (SE) common... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:17 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Moving the serial engine setup to geni_i2c_init() API for a cleaner
probe function and utilizes the PM runtime API to control resources
instead of direct clock-related APIs for better resource management.
Enables reusability of the serial engine initialization like
hibernation and deep sleep features where hardware co... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:18 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Refactor the resource initialization in geni_i2c_probe() by introducing
a new geni_i2c_resources_init() function and utilizing the common
geni_se_resources_init() framework and clock frequency mapping, making the
probe function cleaner.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Pravee... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:19 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To manage GENI serial engine resources during runtime power management,
drivers currently need to call functions for ICC, clock, and
SE resource operations in both suspend and resume paths, resulting in
code duplication across drivers.
The new geni_se_resources_activate() and geni_se_resources_deactivate()
helper APIs... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:20 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To avoid repeatedly fetching and checking platform data across various
functions, store the struct of_device_id data directly in the i2c
private structure. This change enhances code maintainability and reduces
redundancy.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <prave... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:21 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:22 +0530",
"thread_id": "20260202180922.1692428-3-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH] perf: arm_spe: Add barrier before enabling profiling
buffer | The Arm ARM known issues document [1] states that the architecture will
be relaxed so that the profiling buffer must be correctly configured
when ProfilingBufferEnabled() && !SPEProfilingStopped() &&
PMBLIMITR_EL1.FM != DISCARD:
R24557
While the Profiling Buffer is enabled, profiling is not stopped, and
Discard... | On Fri, Jan 23, 2026 at 04:03:53PM +0000, James Clark wrote:
Makes sense.
The isb() in the interrupt handler is useful and should not be removed.
See the sequence in the interrupt handler:
arm_spe_perf_aux_output_begin() {
write_sysreg_s(base, SYS_PMBPTR_EL1);
// Ensure the write pointer is or... | {
"author": "Leo Yan <leo.yan@arm.com>",
"date": "Fri, 30 Jan 2026 20:24:37 +0000",
"thread_id": "aYDWpc8Jh4SqMcD5@willie-the-truck.mbox.gz"
} |
lkml | [PATCH] perf: arm_spe: Add barrier before enabling profiling
buffer | The Arm ARM known issues document [1] states that the architecture will
be relaxed so that the profiling buffer must be correctly configured
when ProfilingBufferEnabled() && !SPEProfilingStopped() &&
PMBLIMITR_EL1.FM != DISCARD:
R24557
While the Profiling Buffer is enabled, profiling is not stopped, and
Discard... | On Fri, Jan 30, 2026 at 08:24:37PM +0000, Leo Yan wrote:
Oh nice, since when was it ok to relax the architecture and break
existing drivers that were perfectly fine before? The SPE spec's not
worth the paper it's written on...
Anyway, we're not changing the driver without a comment next to the new
isb() explaining th... | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 16:53:57 +0000",
"thread_id": "aYDWpc8Jh4SqMcD5@willie-the-truck.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.
The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optio... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:10 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.
This provides a more convenient API for... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:11 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.
Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.
Signed-off-by:... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:12 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.
Core clk is now properly managed alongside the other ... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:13 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.
Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactiva... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:14 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle
the attachment of power domains. This often leads to duplicated code
logic across different driver probe functions.
Introduce a new helper API, geni_se_domain_attach(), to centralize
the logic for attaching "power" and "perf" domains to the GENI SE... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:15 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently
manage performance levels and operating points directly. This resulting
in code duplication across drivers. such as configuring a specific level
or find and apply an OPP based on a clock frequency.
Introduce two new helper APIs, geni_se_set_perf_leve... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:16 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Add DT bindings for the QUP GENI I2C controller on sa8255p platforms.
SA8255p platform abstracts resources such as clocks, interconnect and
GPIO pins configuration in Firmware. SCMI power and perf protocol
are utilized to request resource configurations.
SA8255p platform does not require the Serial Engine (SE) common... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:17 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Moving the serial engine setup to geni_i2c_init() API for a cleaner
probe function and utilizes the PM runtime API to control resources
instead of direct clock-related APIs for better resource management.
Enables reusability of the serial engine initialization like
hibernation and deep sleep features where hardware co... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:18 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | Refactor the resource initialization in geni_i2c_probe() by introducing
a new geni_i2c_resources_init() function and utilizing the common
geni_se_resources_init() framework and clock frequency mapping, making the
probe function cleaner.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Pravee... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:19 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To manage GENI serial engine resources during runtime power management,
drivers currently need to call functions for ICC, clock, and
SE resource operations in both suspend and resume paths, resulting in
code duplication across drivers.
The new geni_se_resources_activate() and geni_se_resources_deactivate()
helper APIs... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:20 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | To avoid repeatedly fetching and checking platform data across various
functions, store the struct of_device_id data directly in the i2c
private structure. This change enhances code maintainability and reduces
redundancy.
Acked-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Signed-off-by: Praveen Talari <prave... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:21 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v4 00/13] Enable I2C on SA8255p Qualcomm platforms | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | The Qualcomm automotive SA8255p SoC relies on firmware to configure
platform resources, including clocks, interconnects and TLMM.
The driver requests resources operations over SCMI using power
and performance protocols.
The SCMI power protocol enables or disables resources like clocks,
interconnect paths, and TLMM (GP... | {
"author": "Praveen Talari <praveen.talari@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 23:39:22 +0530",
"thread_id": "20260202180922.1692428-9-praveen.talari@oss.qualcomm.com.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | Replace direct comparisons of hv_result(status) against
HV_STATUS_INSUFFICIENT_MEMORY with a new hv_result_needs_memory() helper
function.
This improves code readability and provides a consistent and extendable
interface for checking out-of-memory conditions in hypercall results.
No functional changes intended.
Signe... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:58:57 +0000",
"thread_id": "177005499596.120041.5908089206606113719.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | Introduce hv_deposit_memory_node() and hv_deposit_memory() helper
functions to handle memory deposition with proper error handling.
The new hv_deposit_memory_node() function takes the hypervisor status
as a parameter and validates it before depositing pages. It checks for
HV_STATUS_INSUFFICIENT_MEMORY specifically and... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:03 +0000",
"thread_id": "177005499596.120041.5908089206606113719.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | The HV_STATUS_INSUFFICIENT_CONTIGUOUS_MEMORY status indicates that the
hypervisor lacks sufficient contiguous memory for its internal allocations.
When this status is encountered, allocate and deposit
HV_MAX_CONTIGUOUS_ALLOCATION_PAGES contiguous pages to the hypervisor.
HV_MAX_CONTIGUOUS_ALLOCATION_PAGES is defined i... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:09 +0000",
"thread_id": "177005499596.120041.5908089206606113719.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | When creating guest partition objects, the hypervisor may fail to
allocate root partition pages and return an insufficient memory status.
In this case, deposit memory using the root partition ID instead.
Note: This error should never occur in a guest of L1VH partition context.
Signed-off-by: Stanislav Kinsburskii <sk... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:14 +0000",
"thread_id": "177005499596.120041.5908089206606113719.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH net-next v2] net: bridge: use sysfs_emit instead of sprintf | Replace sprintf with sysfs_emit in sysfs show() methods as outlined in
Documentation/filesystems/sysfs.rst.
sysfs_emit is preferred to sprintf in sysfs show() methods as it is safer
with buffer handling.
Signed-off-by: David Corvaglia <david@corvaglia.dev>
---
v2: Fix alignment of sysfs_emit arguments.
v1: https://lo... | On Mon, Feb 02, 2026 at 07:07:12AM +0000, David Corvaglia wrote:
I get:
$ b4 shazam -k 0100019c1d2d46e0-a083f912-ac82-47e8-8cbb-ac9d70355ed3-000000@email.amazonses.com
[...]
● checkpatch.pl: 392: ERROR: code indent should use tabs where possible
[...]
$ scripts/checkpatch.pl -g HEAD
ERROR: code indent should use... | {
"author": "Ido Schimmel <idosch@nvidia.com>",
"date": "Mon, 2 Feb 2026 19:44:09 +0200",
"thread_id": "20260202174409.GA127339@shredder.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Fri, Aug 09, 2024 at 01:06:09PM +0530, Anand Moon wrote:
Hello Anand,
I tried this patch.
It gives me the following splat on rock5b (rk3588):
[ 1.412108] WARNING: CPU: 5 PID: 59 at kernel/module/kmod.c:143 __request_module+0x1c0/0x298
[ 1.412853] Modules linked in:
[ 1.413125] CPU: 5 UID: 0 PID: 59 Comm... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Fri, 3 Jan 2025 12:31:29 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Niklas,
On Fri, 3 Jan 2025 at 17:01, Niklas Cassel <cassel@kernel.org> wrote:
Thanks for testing this patch.
This patch should have been tested on hardware that includes all the
relevant controllers,
such as PCI 2.0, PCI 3.0, and the SATA controller.
I will test this patch again on all the Radxa devices I have.
... | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Fri, 3 Jan 2025 19:24:07 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hello Anand,
On Fri, Jan 03, 2025 at 07:24:07PM +0530, Anand Moon wrote:
Note that the splat, as reported in this thread, and in:
https://lore.kernel.org/netdev/20250101235122.704012-1-francesco@valla.it/T/
is related to the network PHY (CONFIG_REALTEK_PHY) on the RTL8125 NIC,
which is connected to one of the PCIe ... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Fri, 3 Jan 2025 15:25:45 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Niklas
On Fri, 3 Jan 2025 at 19:55, Niklas Cassel <cassel@kernel.org> wrote:
We need to enable the GMAC PHY and reset it using the proper GPIO pin
(PCIE_PERST_L).
Please refer to the schematic for more details.
These changes also apply to other device tree nodes for different boards.
Thanks
-Anand | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Fri, 3 Jan 2025 20:10:17 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Fri, Jan 03, 2025 at 08:10:17PM +0530, Anand Moon wrote:
The PERST# GPIO is already asserted + deasserted from the PCIe Root Complex
(host) driver:
https://github.com/torvalds/linux/blob/v6.13-rc5/drivers/pci/controller/dwc/pcie-dw-rockchip.c#L191-L206
which will cause the endpoint device (a RTL8125 NIC in this ca... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Fri, 3 Jan 2025 15:45:57 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Niklas
On Fri, 3 Jan 2025 at 20:16, Niklas Cassel <cassel@kernel.org> wrote:
Thanks for letting me know. It seems like a workaround.
I'll try to disable this and test it again.
My point is that we haven't enabled the GMAC PHY (device nodes)
and must properly reset the GMAC.
We're relying on the code above hack to... | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Fri, 3 Jan 2025 20:36:18 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Fri, Jan 03, 2025 at 08:36:18PM +0530, Anand Moon wrote:
I do not think it is a hack.
If you look in most PCIe controller drivers, they toggle PERST before
enumerating the bus:
$ git grep gpiod_set_value drivers/pci/controller/
Kind regards,
Niklas | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Fri, 3 Jan 2025 16:10:29 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | Hi Niklas
On Fri, 3 Jan 2025 at 20:40, Niklas Cassel <cassel@kernel.org> wrote:
Ok, understood. However, we have multiple reset lines per controller,
so the PCIe driver will reset these lines using gpiod_set_value.
PCIE30X4_PERSTn_M1_L
PCIE30x1_0_PERSTn_M1_L
PCIE_PERST_L
Thanks
-Anand | {
"author": "Anand Moon <linux.amoon@gmail.com>",
"date": "Fri, 3 Jan 2025 20:59:51 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Fri, Jan 03, 2025 at 08:59:51PM +0530, Anand Moon wrote:
If you look in Documentation/devicetree/bindings/pci/pci.txt
You will see:
"""
- reset-gpios:
If present this property specifies PERST# GPIO. Host drivers can parse the
GPIO and apply fundamental reset to endpoints.
"""
For rock5b, reset-gpios/PERST# ... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Fri, 3 Jan 2025 16:45:06 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | rgmii is wrong. Please search the archives about this topic, it comes
up every month. You need to remove the tx_delay and rx_delay
properties, and use rgmii-id.
Andrew | {
"author": "Andrew Lunn <andrew@lunn.ch>",
"date": "Fri, 3 Jan 2025 17:04:55 +0100",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v2] PCI: dw-rockchip: Enable async probe by default | Rockchip DWC PCIe driver currently waits for the combo PHY link
(PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training
during boot, it also waits for the link to be up, which could consume
several milliseconds during boot.
To optimize boot time, this commit allows asynchronous probing.
This change enables ... | On Fri, Jan 03, 2025 at 08:59:51PM +0530, Anand Moon wrote:
PERST# gpio is unique per controller instance and will be asserted/deasserted
by the PCIe controller driver itself. Endpoint drivers should not touch these.
And most of the PCIe endpoint devices do not need to be described in devicetree
as PCIe is a discover... | {
"author": "Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>",
"date": "Sun, 5 Jan 2025 22:05:11 +0530",
"thread_id": "CANAwSgQtWifFNFe-rK7s9VCPJ68A7LSP+va2zZWr8W+vgZOjYw@mail.gmail.com.mbox.gz"
} |
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