data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | The UFFDIO_MOVE ioctl's move_pages() loop splits a huge PMD when the
folio is pinned and can't be moved at PMD granularity.
If the split fails, the PMD stays huge and move_pages_pte() can't
process individual pages. Break out of the loop on split failure
and return -ENOMEM to the caller. This is similar to how other
a... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:40 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Device memory migration has two call sites that split huge PMDs:
migrate_vma_split_unmapped_folio():
Called from migrate_vma_pages() when migrating a PMD-mapped THP to a
destination that doesn't support compound pages. It splits the PMD
then splits the folio via folio_split_unmapped().
If the PMD split fails... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:41 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Mark __split_huge_pmd(), split_huge_pmd() and split_huge_pmd_address()
with __must_check so the compiler warns if any caller ignores the return
value. Not checking return value and operating on the basis that the pmd
is split could result in a kernel bug. The possibility of an order-0
allocation failing for page table ... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:42 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | When the kernel creates a PMD-level THP mapping for anonymous pages,
it pre-allocates a PTE page table and deposits it via
pgtable_trans_huge_deposit(). This deposited table is withdrawn during
PMD split or zap. The rationale was that split must not fail—if the
kernel decides to split a THP, it needs a PTE table to pop... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:43 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Since the previous commit made deposit/withdraw only needed for
architectures where arch_needs_pgtable_deposit() returns true (currently
only powerpc hash MMU), the generic implementation in pgtable-generic.c
and the s390/sparc overrides are now dead code — all call sites are
guarded by arch_needs_pgtable_deposit() whi... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:44 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Add a vmstat counter to track PTE allocation failures during PMD split.
This enables monitoring of split failures due to memory pressure after
the lazy PTE page table allocation change.
The counter is incremented in three places:
- __split_huge_pmd(): Main entry point for splitting a PMD
- try_to_unmap_one(): When rec... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:45 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Add test infrastructure for verifying THP PMD split behavior with lazy
PTE allocation. This includes:
- Test fixture with PMD-aligned memory allocation
- Helper functions for reading vmstat counters
- log_and_check_pmd_split() macro for logging counters and checking
if thp_split_pmd has incremented and thp_split_pmd... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:46 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Add test for partial mprotect on THP which exercises change_pmd_range().
This verifies that partial mprotect correctly splits the PMD, applies
protection only to the requested portion, and leaves the rest of the
mapping writable.
Signed-off-by: Usama Arif <usama.arif@linux.dev>
---
.../testing/selftests/mm/thp_pmd_sp... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:47 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Add test for partial mlock on THP which exercises walk_page_range()
with a subset of the THP. This should trigger a PMD split since
mlock operates at page granularity.
Signed-off-by: Usama Arif <usama.arif@linux.dev>
---
.../testing/selftests/mm/thp_pmd_split_test.c | 26 +++++++++++++++++++
1 file changed, 26 insert... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:48 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Add test for partial mremap on THP which exercises move_page_tables().
This verifies that partial mremap correctly splits the PMD, moves
only the requested page, and preserves data integrity in both the
moved region and the original mapping.
Signed-off-by: Usama Arif <usama.arif@linux.dev>
---
.../testing/selftests/m... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:49 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | Add test for partial MADV_DONTNEED on THP. This verifies that
MADV_DONTNEED correctly triggers a PMD split, discards only the
requested page (which becomes zero-filled), and preserves data
in the surrounding pages.
Signed-off-by: Usama Arif <usama.arif@linux.dev>
---
.../testing/selftests/mm/thp_pmd_split_test.c | 34... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 03:23:50 -0800",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | On 26/02/2026 11:23, Usama Arif wrote:
This will need to be guarded by CONFIG_TRANSPARENT_HUGEPAGE. Will need below diff in next series..
diff --git a/mm/rmap.c b/mm/rmap.c
index 2dae46fff08ae..9d74600951cf6 100644
--- a/mm/rmap.c
+++ b/mm/rmap.c
@@ -2070,7 +2070,9 @@ static bool try_to_unmap_one(struct folio *folio, ... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Thu, 26 Feb 2026 14:22:35 +0000",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | On Thu, Feb 26, 2026 at 4:33 AM Usama Arif <usama.arif@linux.dev> wrote:
Hi Usama,
Thanks for tackling this, it seems like an interesting problem. Im
trying to get more into reviewing, so bare with me I may have some
stupid comments or questions. Where I can really help out is with
testing. I will build this for all ... | {
"author": "Nico Pache <npache@redhat.com>",
"date": "Thu, 26 Feb 2026 14:01:04 -0700",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | On 26/02/2026 21:01, Nico Pache wrote:
Thanks for the build and looking into reviewing this. All comments
and questions are welcome! I had only tested on x86, and I had a look
at the link you shared so its great to know that powerPC and s390 are fine. | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Fri, 27 Feb 2026 11:13:55 +0000",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm | When the kernel creates a PMD-level THP mapping for anonymous pages, it
pre-allocates a PTE page table via pgtable_trans_huge_deposit(). This
page table sits unused in a deposit list for the lifetime of the THP
mapping, only to be withdrawn when the PMD is split or zapped. Every
anonymous THP therefore wastes 4KB of me... | null | null | null | [RFC v2 00/21] mm: thp: lazy PTE page table allocation at PMD split | On 26/02/2026 11:23, Usama Arif wrote:
Kernel test bot reported that I missed one split_huge_pmd call. I will include
the below patch in the next revision.
commit 9e1bb250ea8ef0a39c738cd4137ed6c98131ebb0 (HEAD)
Author: Usama Arif <usama.arif@linux.dev>
Date: Thu Feb 26 10:45:35 2026 -0800
mm: proc: handle sp... | {
"author": "Usama Arif <usama.arif@linux.dev>",
"date": "Fri, 27 Feb 2026 12:11:46 +0000",
"is_openbsd": false,
"thread_id": "4672053f-c9d9-4694-81ad-9b5fe741013a@linux.dev.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | From: Anshuman Khandual <anshuman.khandual@arm.com>
Replace READ_ONCE() with standard page table accessors i.e pxdp_get()
which anyways default into READ_ONCE() in cases where platform does not
override. Also convert ptep_get_lockless() into ptep_get() as well.
Link: https://lkml.kernel.org/r/20251001042502.1400726-... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:14 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | From: Anshuman Khandual <anshuman.khandual@arm.com>
Replace all READ_ONCE() with a standard page table accessors i.e
pxdp_get() that defaults into READ_ONCE() in cases where platform does not
override.
Link: https://lkml.kernel.org/r/20251007063100.2396936-1-anshuman.khandual@arm.com
Signed-off-by: Anshuman Khandual ... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:15 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | From: Anshuman Khandual <anshuman.khandual@arm.com>
Replace READ_ONCE() with a standard page table accessor i.e pudp_get() that
anyways defaults into READ_ONCE() in cases where platform does not override
Link: https://lkml.kernel.org/r/20251006055214.1845342-1-anshuman.khandual@arm.com
Signed-off-by: Anshuman Khandua... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:16 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | From: Anshuman Khandual <anshuman.khandual@arm.com>
Replace READ_ONCE() with standard page table accessors i.e pxdp_get() which
anyways default into READ_ONCE() in cases where platform does not override.
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ke... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:17 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Some platforms need to fix up the values when reading or writing page
tables. Because of this, the accessors must always be used; it is not
valid to simply dereference a pXX_t pointer.
Move these definitions up by a few lines, so they will be in scope
everywhere that currently dereferences a pXX_t pointer.
Signed-off... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:18 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Architectures may have special rules for accessing the hardware page
tables (for example, atomicity/ordering requirements), so the generic MM
code provides the pXXp_get() and set_pXX() hooks for architectures to
implement. These accessor functions are often omitted where a raw
pointer dereference is believed to be safe... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:20 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Some platforms need to fix up the values when reading or writing page
tables. Because of this, the accessors must always be used; it is not
valid to simply dereference a pXX_t pointer.
Fix all of the instances of this pattern in generic code, mostly by
applying the below coccinelle semantic patch, repeated for each pa... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:19 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Currently, some functions such as pte_offset_map() are passed both
pointers to hardware page tables, and pointers to previously-read PMD
entries on the stack. To ensure correctness in the first case, these
functions must use the page table accessor function (pmdp_get()) to
dereference the supplied pointer. However, thi... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:21 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Use the semantically appropriate accessor function instead of open
coding the implementation. This will become important once these
functions start transforming the PTE value on some platforms.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v2)
Changes in v2:
- New patch for v2
ar... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:22 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Use the semantically appropriate accessor function instead of a raw
pointer dereference. This will become important once these functions
start transforming the PTE value on some platforms.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v2)
Changes in v2:
- New patch for v2
arch/ri... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:23 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | RISC-V uses the same page table entry format and has the same atomicity
requirements at all page table levels, so these setter functions use the
same underlying implementation at all levels. Checking the translation
mode to pick between two identical branches only serves to make these
functions less efficient.
Signed-... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:24 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | The two existing definitions are equivalent because _PAGE_MTMASK is
defined as 0 on riscv32.
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v1)
arch/riscv/include/asm/pgtable-32.h | 5 -----
arch/riscv/include/asm/pgtable-64.h | ... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:25 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | When the Svnapot or Svpbmt extension is not implemented, the
corresponding page table bits are reserved, and must be zero. There is
no need to show them in the ptdump output.
When the Kconfig option for an extension is disabled, we assume it is
not implemented. In that case, the kernel may provide a fallback
definitio... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:26 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Currently, Linux on RISC-V has three ways to specify the cacheability
and ordering PMAs of a page:
1) Do nothing; assume the system is entirely cache-coherent and rely on
the hardware for any ordering requirements
2) Use the page table bits specified by Svpbmt
3) Use the page table bits specified by XTheadMae
T... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:27 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | pgtable-32.h and pgtable-64.h are not usable by assembly code files, so
move all page table field definitions to pgtable-bits.h. This allows
handling more complex PTE transformations in out-of-line assembly code.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v1)
arch/riscv/include/... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:28 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | ALT_FIXUP_MT() is already using ALTERNATIVE_2(), but it needs to be
extended to handle a fourth case. Add ALTERNATIVE_3(), which extends
ALTERNATIVE_2() with another block of new content.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes sinc... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:29 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Alternative assembly code may wish to use an alternate link register to
minimize the number of clobbered registers. Apply the offset fix to all
jalr (not jr) instructions, i.e. where rd is not x0.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v1)
arch/riscv/kernel/alternative.c | 4... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:30 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | DMA_DIRECT_REMAP allows the kernel to make pages coherent for DMA by
remapping them in the page tables with a different pgprot_t value. On
RISC-V, this is supported by the page-based memory type extensions
(Svpbmt and Xtheadmae). It is independent from the software cache
maintenance extensions (Zicbom and Xtheadcmo).
... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:31 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Information about physical memory regions is needed by both the kernel
and M-mode firmware. For example, the kernel needs to know about
noncacheable aliases of cacheable memory in order to allocate coherent
memory pages for DMA. M-mode firmware needs to know about those aliases
so it can protect itself from lower-privi... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:32 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On some RISC-V platforms, RAM is mapped simultaneously to multiple
physical address ranges, with each alias having a different set of
statically-determined Physical Memory Attributes (PMAs). Software alters
the PMAs for a particular page at runtime by selecting a PFN from among
the aliases of that page's physical addre... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:33 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | JH7100 provides a physical memory region which is a noncached alias of
normal cacheable DRAM. Now that Linux can apply PMAs by selecting
between aliases of a physical memory region, any page of DRAM can be
marked as noncached for use with DMA, and the preallocated DMA pool is
no longer needed. This allows portable kern... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:34 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | EIC7700 provides a physical memory region which is a noncached alias of
normal cacheable DRAM. Declare this alias in the devicetree so Linux can
allocate noncached pages for noncoherent DMA, and M-mode firmware can
protect the noncached alias with PMPs.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
Ch... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 17:45:35 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, 2025-11-12 at 17:45 -0800, Samuel Holland wrote:
[]
[]
Seems like a lot of matches
$ git grep -P '(?<!pte_t |p[mu4g]d_t |izeof\()\*\(?(vmf(\.|->))?(pte|p[mu4g]d)p?\b' | \
grep -v '^arch/' | wc -l
766
Is this really appropriate?
trivia:
izeof is really odd looking. I'd prefer sizeof. | {
"author": "Joe Perches <joe@perches.com>",
"date": "Wed, 12 Nov 2025 18:21:01 -0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 2025-11-12 8:21 PM, Joe Perches wrote:
Other patches in this series remove 277 of these matches. But it looks like a
couple of driver systems (iommu, dm) use variables that match this pattern as
well. Limiting the check to include/ and mm/ avoids the false positives.
I agree, but my perl complains "Variable lengt... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Wed, 12 Nov 2025 20:36:03 -0600",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hi Samuel,
kernel test robot noticed the following build errors:
[auto build test ERROR on 24172e0d79900908cf5ebf366600616d29c9b417]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/mm-ptdump-replace-READ_ONCE-with-standard-page-table-accessors/20251113-095117
base: 24172e0d79900908cf5ebf36660... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Thu, 13 Nov 2025 12:53:18 +0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hi Samuel,
kernel test robot noticed the following build errors:
[auto build test ERROR on 24172e0d79900908cf5ebf366600616d29c9b417]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/mm-ptdump-replace-READ_ONCE-with-standard-page-table-accessors/20251113-095117
base: 24172e0d79900908cf5ebf36660... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Thu, 13 Nov 2025 13:46:28 +0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hi Samuel,
kernel test robot noticed the following build errors:
[auto build test ERROR on 24172e0d79900908cf5ebf366600616d29c9b417]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/mm-ptdump-replace-READ_ONCE-with-standard-page-table-accessors/20251113-095117
base: 24172e0d79900908cf5ebf36660... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Thu, 13 Nov 2025 15:19:38 +0800",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13.11.25 02:45, Samuel Holland wrote:
Acked-by: David Hildenbrand (Red Hat) <david@kernel.org>
--
Cheers
David | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 13 Nov 2025 20:10:33 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13.11.25 02:45, Samuel Holland wrote:
It is not immediately clear to me from the description why that is
required. Can you summarize the core problem here, and why we have to
route everything through these accessors?
--
Cheers
David | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 13 Nov 2025 20:13:52 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13.11.25 03:36, Samuel Holland wrote:
That is indeed concerning.
I recall that we discussed an alternative approach with Ryan in the
past: I don't remember all the details, but essentially it was about
using separate types, such that dereferencing would not get you the type
the other functions would be expectin... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 13 Nov 2025 20:17:22 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Le 13/11/2025 à 02:45, Samuel Holland a écrit :
...
And this commit has the same problem as the series from Anshuman, see [2]:
Before the patch, as an exemple on powerpc/32 mm_find_pmd() was:
00001860 <mm_find_pmd>:
1860: 80 63 00 18 lwz r3,24(r3)
1864: 54 84 65 3a rlwinm r4,r4,12... | {
"author": "\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>",
"date": "Wed, 26 Nov 2025 12:08:19 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13/11/2025 01:45, Samuel Holland wrote:
There should absolutely never be any instances of core code directly setting an
entry at any level. This *must* always go via the arch code helpers. Did you
find any instances of this? If so, I would consider these bugs and suggest
sending as a separate bugfix patch. Bad thin... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 11:09:48 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 12:09, Ryan Roberts wrote:
We do have mm_pmd_folded()/p4d_folded() etc, could that help to sort
this out internally?
--
Cheers
David | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 13:16:35 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 13:16, David Hildenbrand (Red Hat) wrote:
Just stumbled over the reply from Christope:
https://lkml.kernel.org/r/0019d675-ce3d-4a5c-89ed-f126c45145c9@kernel.org
And wonder if we could handle that somehow directly in the pgdp_get() etc.
--
Cheers
David | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 13:19:00 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 01:19:00PM +0100, David Hildenbrand (Red Hat) wrote:
I find that kind of gross to be honest. Isn't the whole point of folding that we
don't have to think about it...
And we're now modifying how we do things for ppc32 specifically? Or are there
arches with fewer cobwebs on them that are actuall... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Wed, 26 Nov 2025 12:27:56 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 13:27, Lorenzo Stoakes wrote:
If we could adjust generic pgdp_get() and friends to not do a
READ_ONCE() once folded we might not have to think about that in the
callers.
Just an idea, though, not sure if that would fly the way I envision it.
--
Cheers
David | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 13:35:17 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 26/11/2025 12:35, David Hildenbrand (Red Hat) wrote:
I certainly don't like the suggestion of doing the is_folded() test outside the
helper, but if we can push that logic down into pXdp_get() that would be pretty
neat. Anshuman and I did briefly play with the idea of doing a C dereference if
the level is folded and... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 13:03:42 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 01:03:42PM +0000, Ryan Roberts wrote:
[...]
You mean sth like:
static inline pmd_t pmdp_get(pmd_t *pmdp)
{
#ifdef __PAGETABLE_PMD_FOLDED
return *pmdp;
#else
return READ_ONCE(*pmdp);
#endif
}
--
Wei Yang
Help you, Help me | {
"author": "Wei Yang <richard.weiyang@gmail.com>",
"date": "Wed, 26 Nov 2025 13:47:26 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 26/11/2025 13:47, Wei Yang wrote:
Yes. But I'm not convinced it's correct.
I *think* (but please correct me if I'm wrong) if the PMD is folded, the PUD and
P4D must also be folded, and you effectively have a 2 level pgtable consisting
of the PGD table and the PTE table. p4dp_get(), pudp_get() and pmdp_get() are
al... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 14:22:13 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 02:22:13PM +0000, Ryan Roberts wrote:
Yeah, it kinda sucks to bake that assumption in too even if we can prove it
currently _is_ correct, and it becomes tricky because to somebody observing this
they might well think 'oh so we don't need to think about tearing here' but in
reality we are just a... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Wed, 26 Nov 2025 14:37:10 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 15:22, Ryan Roberts wrote:
Yeah, I'm also still trying to understand how it could work.
With __PAGETABLE_PMD_FOLDED we treat the PUD to be fake-present, like
static inline int pud_present(pud_t pud) { return 1; }
And obtaining the pmd_t* is essentially cast of the pud_t*
static inline pmd_t * pmd_offs... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 15:46:40 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 03:46:40PM +0100, David Hildenbrand (Red Hat) wrote:
Would the pmdp_get() never get invoked then? Or otherwise wouldn't that end up
requiring a READ_ONCE() further up the stack?
Even if we could make this work, I don't love that there's some implicit
assumption there that could easily break l... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Wed, 26 Nov 2025 14:52:15 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 15:37, Lorenzo Stoakes wrote:
Looking at include/asm-generic/pgtable-nopmd.h, PUD entries there are
* always present (pud_present() == 1)
* always a page table (pud_leaf() == 0)
And pmd_offset() is just a typecast.
So I wonder if that means that we can make pudp_get() be a simple load
(!READ_ONCE) beca... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 15:53:30 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 15:52, Lorenzo Stoakes wrote:
See my other reply, I think the pmdp_get() is required because all pud_*
functions are just simple stubs.
Looking at include/asm-generic/pgtable-nopmd.h I am not sure we are
talking about implicit assumptions here. It's kind-of the design that
the pud_t values are dummies... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 15:56:13 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 03:56:13PM +0100, David Hildenbrand (Red Hat) wrote:
OK, thought you were saying we should push further down the stack? Or up
depending on how you view these things :P as in READ_ONCE at leaf?
Anyway. I am now designating you the expert at this ;)
I mean I'm waving my hands around like I'm w... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Wed, 26 Nov 2025 15:08:43 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 16:08, Lorenzo Stoakes wrote:
I think at leaf because I think the previous ones should essentially be
only used by stubs.
But I haven't fully digested how this is all working. Or supposed to work.
I'm trying to chew through the arch/arm/include/asm/pgtable-2level.h
example to see if I can make sense of... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 16:12:59 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 26/11/2025 15:12, David Hildenbrand (Red Hat) wrote:
I wonder if we can think about this slightly differently;
READ_ONCE() has two important properties:
- It guarrantees that a load will be issued, *even if output is unused*
- It guarrantees that the read will be single-copy-atomic (no tearing)
I think for the... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 16:07:23 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 26/11/2025 16:07, Ryan Roberts wrote:
I'm not sure this works. It looks like the compiler is free to move non-volatile
asm sections which might be problematic for places where we are currently using
READ_ONCE() in lockless algorithms, (e.g. GUP?). We wouldn't want to end up with
a stale value.
Another idea:
Given... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 16:34:51 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 17:34, Ryan Roberts wrote:
Let's take a step back and realize that with __PAGETABLE_PMD_FOLDED
(a) *pudp does not make any sense
For a folded PMD, *pudp == *pmdp and consequently we would actually
get a PMD, not a PUD.
For this reason all these pud_* helpers ignore the passed value
completely. It would ... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 21:31:59 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 21:31, David Hildenbrand (Red Hat) wrote:
Staring at GUP-fast and perf_get_pgtable_size()---which should better be
converted to pudp_get() etc--I guess we might have to rework
p4d_offset_lockless() to do something that doesn't rely on
passing variables of local variables.
We might have to enlighten thes... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 27 Nov 2025 08:14:45 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/27/25 08:14, David Hildenbrand (Red Hat) wrote:
Talking to myself (I know), handling this might be as simple as having
diff --git a/include/asm-generic/pgtable-nopmd.h b/include/asm-generic/pgtable-nopmd.h
index 8ffd64e7a24cb..60e5ba02bcf06 100644
--- a/include/asm-generic/pgtable-nopmd.h
+++ b/include/asm-gene... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 27 Nov 2025 08:31:52 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Le 26/11/2025 à 15:22, Ryan Roberts a écrit :
I think you can't assume pgdp_get() was already called, because some
parts of code will directly descend to PMD level using pmd_off() or
pmd_off_k()
static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va)
{
return pmd_offset(pud_offset(p4d_offset(pgd_offse... | {
"author": "\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>",
"date": "Thu, 27 Nov 2025 09:26:39 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/27/25 09:26, Christophe Leroy (CS GROUP) wrote:
I'll note that these (nesty) helpers only work when you know that you
have folded page tables.
And that's why I am arguing that the pmdp_get() must actually be kept as is.
--
Cheers
David | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 27 Nov 2025 09:35:37 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 27/11/2025 07:31, David Hildenbrand (Red Hat) wrote:
I'm struggling with this statement. The PMD is folded, not the PUD. So the PMD
table consists of a single entry, which overlays the entry in the PUD, right? So
the PUD exists and *pudp must be valid?
Now, pgtable-nopmd.h includes pgtable-nopud.h so actually the ... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Thu, 27 Nov 2025 15:32:34 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13/11/2025 01:45, Samuel Holland wrote:
I don't think this is a good solution.
arm64, at least, expects and requires that only pointers to entries in pgtables
are passed to the arch helpers (e.g. set_pte(), ptep_get(), etc). For PTEs,
arm64 accesses adjacent entries within the page table to manage contiguous
mappi... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Thu, 27 Nov 2025 16:57:06 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/27/25 17:57, Ryan Roberts wrote:
Agreed,
set_pmd(&pmd, pmd);
is rather horrible.
--
Cheers
David | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 27 Nov 2025 18:47:38 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Le 26/11/2025 à 17:34, Ryan Roberts a écrit :
Take care about macros with unused parameters, it can be a problem
sometimes, see commit 05a4ab823983 ("powerpc/uaccess: fix warning/error
with access_ok()")
Christophe | {
"author": "\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>",
"date": "Thu, 27 Nov 2025 20:39:01 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Le 26/11/2025 à 17:34, Ryan Roberts a écrit :
What about adding a memory clobber to the non-volatile asm ? Compiler
shouldn't move the asm section in that case.
Christophe | {
"author": "\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>",
"date": "Thu, 27 Nov 2025 20:44:16 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 12, 2025 at 05:45:32PM -0800, Samuel Holland wrote:
I'm not sure how I feel about this. So here are my random thoughts on
it.
I wonder if another arch may need something similar. I don't think
arm64 ever would as aliases are not allowed. That may have happened on
arm32, but that's all pretty mature at ... | {
"author": "Rob Herring <robh@kernel.org>",
"date": "Thu, 4 Dec 2025 09:12:32 -0600",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 2025-11-14 4:17 AM, David Hildenbrand (Red Hat) wrote:
Even if some functions a new incompatible pointer type, don't we still have the
problem that neither type would be safe to dereference?
A similar option to a new type would be to add a sparse annotation to the
pointers that reference hardware page tables, simi... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Thu, 11 Dec 2025 09:29:28 +0900",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 2025-11-28 2:47 AM, David Hildenbrand (Red Hat) wrote:
I agree that this patch is ugly. The only way I see to avoid code like this is
to refactor (or duplicate) the functions so no function takes pointers to both
hardware page tables and on-stack page table entries. Is that sort of
refactoring the right direction to... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Thu, 11 Dec 2025 09:33:41 +0900",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/12/2025 00:33, Samuel Holland wrote:
refactoring to pass the value instead of the pointer, and leave it to the higher
level decide how to read the value from the pointer - it knows if it is pointing
to HW pgtable or if it's a (e.g) stack value.
But the more I look at the code, the more instances I find where po... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Thu, 11 Dec 2025 13:59:53 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Thu, Dec 11, 2025 at 01:59:53PM +0000, Ryan Roberts wrote:
Ugh. We do need to nip this in the bud I think!
I think we've got ourselves in a jumble with pte vs ptep vs pteval
vs. etc. etc. and we aren't always consistent with it.
So I think we ought to put 'hw' somewhere in the name.
And we can also now get away... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Tue, 16 Dec 2025 10:29:13 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 16/12/2025 10:29, Lorenzo Stoakes wrote:
Yeah that would probably give the best end result. I was thinking that ptep/pXdp
might reduce churn since we already use it in function names. Stack pointers are
definitely a small minority so easier to change their convention.
But having an explicit "hw" would probably be ... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Tue, 16 Dec 2025 17:46:57 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 12/11/25 14:59, Ryan Roberts wrote:
This is what I had in mind when we last discussed this topic and I
suggested a way forward to not play whack-a-mole with new users that do
*ptep showing up.
Agreed that we ideally indicate that this is a HW PTE pointer that must
be de-referenced through ptep_get() or similar.... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 18 Dec 2025 10:49:26 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Tue, Dec 16, 2025 at 05:46:57PM +0000, Ryan Roberts wrote:
Yeah, unfortunately I think the existing inconsistencies call for a clean
break.
Sure hw_pte_t works!
Right.
Yeah it's nice to be able to hide properties like this, I did think the use
of an incomplete type pointer was quite nice there :)
NIce.
Ye... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Thu, 18 Dec 2025 17:27:13 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hello:
This series was applied to riscv/linux.git (fixes)
by Andrew Morton <akpm@linux-foundation.org>:
On Wed, 12 Nov 2025 17:45:13 -0800 you wrote:
Here is the summary with links:
- [v3,01/22] mm/ptdump: replace READ_ONCE() with standard page table accessors
https://git.kernel.org/riscv/c/11119b19f62d
- [v... | {
"author": "patchwork-bot+linux-riscv@kernel.org",
"date": "Fri, 19 Dec 2025 08:10:01 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hi Samuel
On Fri, 2025-12-19 at 08:10 +0000, patchwork-bot+linux-riscv@kernel.org wrote:
Any idea what happened to patches 04-22 as I don't think anything other than patches 01-03 ever got applied
anywhere. Or am I missing anything?
For what it's worth I carried an updated patch set through up to v6.19.4 [1] and lat... | {
"author": "Marcel Ziswiler <marcel@ziswiler.com>",
"date": "Fri, 27 Feb 2026 11:54:54 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-mm | mshare is a new form of shared memory that shares resources between
processes, namely the page tables entries and VMAs of the shared
objects. Advantages include reduced memory consumption through
eliminating the need for duplicated PTEs in each process, reduced
overhead needed to fault shared pages into multiple pr... | null | null | null | [LSF/MM/BPF TOPIC] mshare - sharing page tables across processes | On Mon, Feb 23, 2026 at 6:12 PM <anthony.yznaga@oracle.com> wrote:
Hi Anthony,
I would be very interested in participating in this discussion at LSF/MM.
As mentioned on the mailing list, we are currently exploring similar
optimizations to deduplicate page tables for Android's Zygote process.
I'd love to join the ses... | {
"author": "Kalesh Singh <kaleshsingh@google.com>",
"date": "Wed, 25 Feb 2026 16:59:32 -0800",
"is_openbsd": false,
"thread_id": "6dfb6mndousbfpsaa5ndcytjcpdnixo6yczjduogs6f7kb4ewr@zx23tvriuj2z.mbox.gz"
} |
lkml_critique | linux-mm | mshare is a new form of shared memory that shares resources between
processes, namely the page tables entries and VMAs of the shared
objects. Advantages include reduced memory consumption through
eliminating the need for duplicated PTEs in each process, reduced
overhead needed to fault shared pages into multiple pr... | null | null | null | [LSF/MM/BPF TOPIC] mshare - sharing page tables across processes | On Wed, Feb 25, 2026 at 04:59:32PM -0800, Kalesh Singh wrote:
Hello Anthony,
I'm also working on optimizing pagetable usage in Android with Kalesh,
so I'm definitely interested in participating in this discussion as
well.
Thanks,
Isaac | {
"author": "Isaac Manjarres <isaacmanjarres@google.com>",
"date": "Thu, 26 Feb 2026 15:48:01 -0800",
"is_openbsd": false,
"thread_id": "6dfb6mndousbfpsaa5ndcytjcpdnixo6yczjduogs6f7kb4ewr@zx23tvriuj2z.mbox.gz"
} |
lkml_critique | linux-mm | mshare is a new form of shared memory that shares resources between
processes, namely the page tables entries and VMAs of the shared
objects. Advantages include reduced memory consumption through
eliminating the need for duplicated PTEs in each process, reduced
overhead needed to fault shared pages into multiple pr... | null | null | null | [LSF/MM/BPF TOPIC] mshare - sharing page tables across processes | On Mon, Feb 23, 2026 at 06:11:49PM -0800, anthony.yznaga@oracle.com wrote:
Hi Anthony,
As always, would love to talk about this in person :)
--
Pedro | {
"author": "Pedro Falcato <pfalcato@suse.de>",
"date": "Fri, 27 Feb 2026 10:36:32 +0000",
"is_openbsd": false,
"thread_id": "6dfb6mndousbfpsaa5ndcytjcpdnixo6yczjduogs6f7kb4ewr@zx23tvriuj2z.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | On Fri, Oct 24, 2025 at 10:27:11AM +0800, Jiayuan Chen wrote:
Can you share the numa configuration of your system? How many nodes are
there?
Am I understanding this correctly that watermark boost increase the
chances of this issue but it can still happen?
In general I think not incrementing the failure for boosted... | {
"author": "Shakeel Butt <shakeel.butt@linux.dev>",
"date": "Fri, 7 Nov 2025 17:11:58 -0800",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | 2025/11/8 09:11, "Shakeel Butt" <shakeel.butt@linux.dev mailto:shakeel.butt@linux.dev?to=%22Shakeel%20Butt%22%20%3Cshakeel.butt%40linux.dev%3E > wrote:
[...]
My system has 2 nodes.
[...]
Yes. In the case of watermark_boost, due to the priority having a lower limit,
the scanning intensity is relatively low, maki... | {
"author": "\"Jiayuan Chen\" <jiayuan.chen@linux.dev>",
"date": "Wed, 12 Nov 2025 02:21:37 +0000",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | On Fri 07-11-25 17:11:58, Shakeel Butt wrote:
Our current documention gives us some room for interpretation. I am
wondering whether we need to change the existing implemnetation though.
If kswapd is not able to make progress then we surely have direct
reclaim happening. So I would only change this if we had examples o... | {
"author": "Michal Hocko <mhocko@suse.com>",
"date": "Thu, 13 Nov 2025 11:02:41 +0100",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | On Thu, Nov 13, 2025 at 11:02:41AM +0100, Michal Hocko wrote:
Yes, I think any change here will need much more brainstorming and
experimentation. There are definitely corner cases which the right
solution might not be in kernel. One such case I was thinking about is
unbalanced (memory) numa node where I don't think ks... | {
"author": "Shakeel Butt <shakeel.butt@linux.dev>",
"date": "Thu, 13 Nov 2025 11:28:58 -0800",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | On Wed, Nov 12, 2025 at 02:21:37AM +0000, Jiayuan Chen wrote:
[...]
Basically whenever the amount of reclaimable memory is low (i.e. in the
range where it is very hard to satisfy the watermarks), this issue can
happen. 'This' as in kswapd failures. This functionality was added to
detect such scenarios where kswapd hog... | {
"author": "Shakeel Butt <shakeel.butt@linux.dev>",
"date": "Thu, 13 Nov 2025 15:41:00 -0800",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | On Fri, Oct 24, 2025 at 10:27:11AM +0800, Jiayuan Chen wrote:
Please resolve Andrew's comment and add couple of lines on boosted
watermark increasing the chances of kswapd failures and the patch only
targets that particular scenario, the general solution TBD in the commit
message.
With that, you can add:
Reviewed-by... | {
"author": "Shakeel Butt <shakeel.butt@linux.dev>",
"date": "Thu, 13 Nov 2025 15:47:01 -0800",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | 2025/11/14 03:28, "Shakeel Butt" <shakeel.butt@linux.dev mailto:shakeel.butt@linux.dev?to=%22Shakeel%20Butt%22%20%3Cshakeel.butt%40linux.dev%3E > wrote:
Can I ask for a link or some keywords to search the mailing list regarding the NUMA
imbalance you mentioned?
I'm not sure if it's similar to a problem I encounter... | {
"author": "\"Jiayuan Chen\" <jiayuan.chen@linux.dev>",
"date": "Fri, 14 Nov 2025 02:23:50 +0000",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | November 14, 2025 at 07:47, "Shakeel Butt" <shakeel.butt@linux.dev mailto:shakeel.butt@linux.dev?to=%22Shakeel%20Butt%22%20%3Cshakeel.butt%40linux.dev%3E > wrote:
[...]
I see this patch is already in mm-next. I'm not sure how to proceed.
Perhaps Andrew needs to do a git rebase and then reword the commit message?
But... | {
"author": "\"Jiayuan Chen\" <jiayuan.chen@linux.dev>",
"date": "Fri, 14 Nov 2025 04:17:40 +0000",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | On Fri, 14 Nov 2025 04:17:40 +0000 "Jiayuan Chen" <jiayuan.chen@linux.dev> wrote:
A rebase would be needed if the patch had been placed in mm.git's
mm-stable branch. But it's still in the mm-unstable branch where
patches are kept in quilt form and are imported into git for each
mm.git release.
Which is why I do th... | {
"author": "Andrew Morton <akpm@linux-foundation.org>",
"date": "Fri, 14 Nov 2025 16:40:37 -0800",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | On Fri, 24 Oct 2025 10:27:11 +0800 Jiayuan Chen <jiayuan.chen@linux.dev> wrote:
> We encountered a scenario where direct memory reclaim was triggered,
> leading to increased system latency:
Who is "we", if I may ask?
> 1. The memory.low values set on host pods are actually quite large, some
> pods are set to 10GB... | null | null | null | Re: [PATCH v2] mm/vmscan: skip increasing kswapd_failures when
reclaim was boosted | On Fri, Nov 07, 2025 at 05:11:58PM +0800, Shakeel Butt wrote:
Hi all,
Sorry to bring this up late, but I've been thinking about a potential
corner case with this patch and would appreciate some input.
Since steal_suitable_fallback() triggers boost_watermark() whenever
pages are stolen across migrate types, and t... | {
"author": "Jiayuan Chen <jiayuan.chen@linux.dev>",
"date": "Fri, 27 Feb 2026 10:15:09 +0800",
"is_openbsd": false,
"thread_id": "6sx72x4eulir6hxacg7wlxpprv4hwszsvqsmz2qst2gjgd5s25@47sizxwwyrzh.mbox.gz"
} |
lkml_critique | linux-mm | MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This series introduces two new DAMON quota goal metrics for controlling
memory migration in heterogeneous memory systems (e.g., DRAM and CXL
memory tiering) using physical address (PA) mode monitoring.
v2: https://lore.kernel.or... | null | null | null | [RFC PATCH v3 0/4] mm/damon: Introduce node_eligible_mem_bp and node_ineligible_mem_bp Quota Goal Metrics | damon_new_scheme() always sets quota.goal_tuner to CONSIST (the default)
regardless of what was passed in the quota struct. This caused the sysfs
goal_tuner setting to be ignored.
The comment in damon_new_scheme() says "quota.goals and .goal_tuner
should be separately set by caller", but the sysfs code wasn't doing
th... | {
"author": "Ravi Jonnalagadda <ravis.opensrc@gmail.com>",
"date": "Mon, 23 Feb 2026 12:32:29 +0000",
"is_openbsd": false,
"thread_id": "20260227020443.91984-1-sj@kernel.org.mbox.gz"
} |
lkml_critique | linux-mm | MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This series introduces two new DAMON quota goal metrics for controlling
memory migration in heterogeneous memory systems (e.g., DRAM and CXL
memory tiering) using physical address (PA) mode monitoring.
v2: https://lore.kernel.or... | null | null | null | [RFC PATCH v3 0/4] mm/damon: Introduce node_eligible_mem_bp and node_ineligible_mem_bp Quota Goal Metrics | When the TEMPORAL goal tuner sets esz_bp=0 to signal that a goal has
been achieved, the quota check was not actually stopping migration.
The condition:
if (quota->esz && quota->charged_sz >= quota->esz)
When esz=0, this evaluates to (false && ...) = false, so the continue
is never executed and migration proceeds ... | {
"author": "Ravi Jonnalagadda <ravis.opensrc@gmail.com>",
"date": "Mon, 23 Feb 2026 12:32:30 +0000",
"is_openbsd": false,
"thread_id": "20260227020443.91984-1-sj@kernel.org.mbox.gz"
} |
lkml_critique | linux-mm | MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This series introduces two new DAMON quota goal metrics for controlling
memory migration in heterogeneous memory systems (e.g., DRAM and CXL
memory tiering) using physical address (PA) mode monitoring.
v2: https://lore.kernel.or... | null | null | null | [RFC PATCH v3 0/4] mm/damon: Introduce node_eligible_mem_bp and node_ineligible_mem_bp Quota Goal Metrics | Add new quota goal metrics for memory tiering that track scheme-eligible
(hot) memory distribution across NUMA nodes:
- DAMOS_QUOTA_NODE_ELIGIBLE_MEM_BP: ratio of hot memory on a node
- DAMOS_QUOTA_NODE_INELIGIBLE_MEM_BP: ratio of hot memory NOT on a node
These complementary metrics enable push-pull migration schemes... | {
"author": "Ravi Jonnalagadda <ravis.opensrc@gmail.com>",
"date": "Mon, 23 Feb 2026 12:32:31 +0000",
"is_openbsd": false,
"thread_id": "20260227020443.91984-1-sj@kernel.org.mbox.gz"
} |
lkml_critique | linux-mm | MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This series introduces two new DAMON quota goal metrics for controlling
memory migration in heterogeneous memory systems (e.g., DRAM and CXL
memory tiering) using physical address (PA) mode monitoring.
v2: https://lore.kernel.or... | null | null | null | [RFC PATCH v3 0/4] mm/damon: Introduce node_eligible_mem_bp and node_ineligible_mem_bp Quota Goal Metrics | In PA-mode, DAMON needs time to re-detect hot memory at new physical
addresses after migration. This causes the goal metrics to temporarily
show incorrect values until detection catches up.
Add an eligible cache mechanism to compensate for this detection lag:
- Track migration deltas per node using a rolling window t... | {
"author": "Ravi Jonnalagadda <ravis.opensrc@gmail.com>",
"date": "Mon, 23 Feb 2026 12:32:32 +0000",
"is_openbsd": false,
"thread_id": "20260227020443.91984-1-sj@kernel.org.mbox.gz"
} |
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