data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Power management.
use spin::Once;
use crate::{arch::irq::disable_local_and_halt, cpu::CpuSet};
/// An exit code that denotes the reason for restarting or powering off.
///
/// Whether or not the code is used depends on the hardware. In a virtualization environment, it
/// can... | ostd/src/power.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The prelude.
/// A specialized [`Result`] type for this crate.
///
/// [`Result`]: core::result::Result
pub type Result<T> = core::result::Result<T, crate::error::Error>;
pub(crate) use alloc::{boxed::Box, sync::Arc, vec::Vec};
#[cfg(ktest)]
pub use ostd_macros::ktest;
pub u... | ostd/src/prelude.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Symmetric Multi-Processing (SMP) support.
//!
//! This module provides a way to execute code on other processors via inter-
//! processor interrupts.
use alloc::{boxed::Box, collections::VecDeque};
use spin::Once;
use crate::{
arch::{irq::HwCpuId, trap::TrapFrame},
cp... | ostd/src/smp.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! User mode.
use crate::arch::{cpu::context::UserContext, trap::TrapFrame};
/// Specific architectures need to implement this trait. This should only used in [`UserMode`]
///
/// Only visible in `ostd`.
pub(crate) trait UserContextApiInternal {
/// Starts executing in the us... | ostd/src/user.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::vec::Vec;
use crate::{boot::memory_region::MemoryRegionType, io::IoMemAllocatorBuilder};
/// Initializes the allocatable MMIO area based on the LoongArch memory
/// distribution map.
///
/// Here we consider all the holes (filtering usable RAM) in the physical
/// addre... | ostd/src/arch/loongarch/io.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Platform-specific code for the LoongArch platform.
#![expect(dead_code)]
pub mod boot;
pub mod cpu;
pub mod device;
mod io;
pub(crate) mod iommu;
pub(crate) mod irq;
pub(crate) mod mm;
pub mod serial;
pub(crate) mod task;
mod timer;
pub mod trap;
#[cfg(feature = "cvm_guest")]... | ostd/src/arch/loongarch/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The console I/O.
use spin::Once;
use crate::{
arch::{boot::DEVICE_TREE, mm::paddr_to_daddr},
console::uart_ns16650a::{Ns16550aAccess, Ns16550aRegister, Ns16550aUart},
sync::{LocalIrqDisabled, SpinLock},
};
/// The primary serial port, which serves as an early cons... | ostd/src/arch/loongarch/serial.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.equ LOONGARCH_CSR_CRMD, 0x0 /* Current mode */
.equ LOONGARCH_CSR_PRMD, 0x1 /* Previous mode */
.equ LOONGARCH_CSR_EUEN, 0x2 /* Extended unit enable */
.equ LOONGARCH_CSR_PGDL, 0x19 /* Page table base address when VA[47]... | ostd/src/arch/loongarch/boot/bsp_boot.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use crate::mm::{Paddr, paddr_to_vaddr};
macro_rules! efi_guid {
($a:expr, $b:expr, $c:expr, $d:expr) => {{
let a = ($a as u32).to_le_bytes(); // u32 -> [u8; 4]
let b = ($b as u16).to_le_bytes(); // u16 -> [u8; 2]
let c = ($c as u16).to_le_bytes(); // u16... | ostd/src/arch/loongarch/boot/efi.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The LoongArch boot module defines the entrypoints of Asterinas.
mod efi;
pub(crate) mod smp;
use core::{arch::global_asm, ffi::CStr};
use fdt::Fdt;
use spin::Once;
use crate::{
arch::boot::efi::EfiSystemTable,
boot::{
BootloaderAcpiArg, BootloaderFramebufferA... | ostd/src/arch/loongarch/boot/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Multiprocessor Boot Support
use crate::{boot::smp::PerApRawInfo, mm::Paddr};
pub(crate) fn count_processors() -> Option<u32> {
Some(1)
}
pub(crate) unsafe fn bringup_all_aps(
_info_ptr: *const PerApRawInfo,
_pr_ptr: Paddr,
_num_cpus: u32,
) {
unimplemented... | ostd/src/arch/loongarch/boot/smp.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU execution context control.
use core::fmt::Debug;
use loongArch64::register::estat::{Exception, Interrupt, Trap};
use crate::{
arch::{
irq::HwIrqLine,
mm::tlb_flush_addr,
trap::{RawUserContext, TrapFrame},
},
cpu::PrivilegeLevel,
irq... | ostd/src/arch/loongarch/cpu/context.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Architecture dependent CPU-local information utilities.
pub(crate) fn get_base() -> u64 {
let mut gp;
unsafe {
core::arch::asm!(
"move {gp}, $r21",
gp = out(reg) gp,
options(preserves_flags, nostack)
);
}
gp
} | ostd/src/arch/loongarch/cpu/local.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU context & state control and CPU local memory.
pub mod context;
pub mod local; | ostd/src/arch/loongarch/cpu/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! I/O port access.
/// An access marker type indicating that a port is only allowed to write values.
pub struct WriteOnlyAccess;
/// An access marker type indicating that a port is allowed to read or write values.
pub struct ReadWriteAccess;
/// A marker trait for access types w... | ostd/src/arch/loongarch/device/io_port.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The IOMMU support.
use crate::mm::{Daddr, Paddr};
/// An enumeration representing possible errors related to IOMMU.
#[derive(Debug)]
pub(crate) enum IommuError {
/// No IOMMU is available.
NoIommu,
}
///
/// # Safety
///
/// Mapping an incorrect address may lead to a ... | ostd/src/arch/loongarch/iommu/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Inter-processor interrupts.
use crate::cpu::PinCurrentCpu;
/// Hardware-specific, architecture-dependent CPU ID.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub(crate) struct HwCpuId(u32);
impl HwCpuId {
pub(crate) fn read_current(_guard: &dyn PinCurrentCpu) -> Self {
... | ostd/src/arch/loongarch/irq/ipi.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Interrupts.
pub(super) mod chip;
mod ipi;
mod ops;
mod remapping;
pub(crate) use ipi::{HwCpuId, send_ipi};
pub(crate) use ops::{
disable_local, disable_local_and_halt, enable_local, enable_local_and_halt, is_local_enabled,
};
pub(crate) use remapping::IrqRemapping;
pub(cr... | ostd/src/arch/loongarch/irq/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Interrupt operations.
// FIXME: Mark this as unsafe. See
// <https://github.com/asterinas/asterinas/issues/1120#issuecomment-2748696592>.
pub(crate) fn enable_local() {
loongArch64::register::crmd::set_ie(true);
}
/// Enables local IRQs and halts the CPU to wait for interr... | ostd/src/arch/loongarch/irq/ops.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
pub(crate) struct IrqRemapping {
_private: (),
}
impl IrqRemapping {
pub(crate) const fn new() -> Self {
Self { _private: () }
}
/// Initializes the remapping entry for the specific IRQ number.
///
/// This will do nothing if the entry is already in... | ostd/src/arch/loongarch/irq/remapping.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use loongArch64::iocsr::{iocsr_read_d, iocsr_write_b, iocsr_write_d, iocsr_write_h};
/// Reference: <https://loongson.github.io/LoongArch-Documentation/Loongson-3A5000-usermanual-EN.html#other-function-configuration-register>
const OTHER_FUNCTION_SETTING_REG: usize = 0x420;
/// Ex... | ostd/src/arch/loongarch/irq/chip/eiointc.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
mod eiointc;
use loongArch64::register::ecfg::LineBasedInterrupt;
use self::eiointc::Eiointc;
use crate::arch::irq;
pub(in crate::arch) fn init() {
// FIXME: Support SMP in LoongArch
Eiointc::init(1);
for i in irq::IRQ_NUM_MIN..=irq::IRQ_NUM_MAX {
Eiointc::ena... | ostd/src/arch/loongarch/irq/chip/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::{arch::asm, intrinsics::AtomicOrdering::Relaxed, ops::Range};
use crate::mm::{
PAGE_SIZE, Paddr, PagingConstsTrait, PagingLevel, PodOnce, Vaddr,
dma::DmaDirection,
page_prop::{
CachePolicy, PageFlags, PageProperty, PageTableFlags, PrivilegedPageFlags a... | ostd/src/arch/loongarch/mm/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The architecture support of context switch.
use crate::task::TaskContextApi;
core::arch::global_asm!(include_str!("switch.S"));
#[derive(Debug, Clone)]
#[repr(C)]
pub(crate) struct TaskContext {
regs: CalleeRegs,
ra: usize,
}
impl TaskContext {
/// Creates a new ... | ostd/src/arch/loongarch/task/mod.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
.global context_switch
.type context_switch, @function
context_switch: # (nxt: *const TaskContext, cur: *mut TaskContext)
# Save cur's register
st.d $sp, $a1, 0x0
st.d $fp, $a1, 0x8
st.d $s0, $a1, 0x10
st.d $s1, $a1, 0x18
st.d $s2, $a1, 0x20
st.d $s3, $... | ostd/src/arch/loongarch/task/switch.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The timer support.
use super::trap::TrapFrame;
// TODO: Add LoongArch timer support and call this method.
#[expect(dead_code)]
fn timer_callback(trapframe: &TrapFrame) {
crate::timer::call_timer_callback_functions(trapframe);
} | ostd/src/arch/loongarch/timer/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Handles trap.
#[expect(clippy::module_inception)]
mod trap;
use loongArch64::register::estat::{self, Exception, Interrupt, Trap};
use spin::Once;
pub(super) use trap::RawUserContext;
pub use trap::TrapFrame;
use crate::{
arch::{cpu::context::CpuExceptionInfo, irq::HwIrqLi... | ostd/src/arch/loongarch/trap/mod.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.equ XLENB, 8
.macro LOAD_SP a1, a2
ld.d \a1, $sp, \a2*XLENB
.endm
.macro STORE_SP a1, a2
st.d \a1, $sp, \a2*XLENB
.endm
.equ LOONGARCH_CSR_PRMD, 0x1 /* Previous mode */
.equ LOONGARCH_CSR_EUEN, 0x2 /* Extended unit enable */
.equ LOONGARCH_C... | ostd/src/arch/loongarch/trap/trap.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::arch::global_asm;
use crate::arch::cpu::context::GeneralRegs;
global_asm!(include_str!("trap.S"));
/// Initializes exception and interrupt handling for the current core.
///
/// # Safety
///
/// On the current CPU, this function must be called
/// - only once and
/// - ... | ostd/src/arch/loongarch/trap/trap.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::vec::Vec;
use crate::{boot::memory_region::MemoryRegionType, io::IoMemAllocatorBuilder};
/// Initializes the allocatable MMIO area based on the RISC-V memory
/// distribution map.
///
/// Here we consider all the holes (filtering usable RAM) in the physical
/// address ... | ostd/src/arch/riscv/io.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Platform-specific code for the RISC-V platform.
#![expect(dead_code)]
pub mod boot;
pub mod cpu;
pub mod device;
mod io;
pub(crate) mod iommu;
pub mod irq;
pub(crate) mod mm;
mod power;
pub(crate) mod serial;
pub(crate) mod task;
mod timer;
pub mod trap;
#[cfg(feature = "cvm_... | ostd/src/arch/riscv/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Power management.
use crate::power::{ExitCode, inject_poweroff_handler, inject_restart_handler};
fn try_poweroff(code: ExitCode) {
let _ = match code {
ExitCode::Success => sbi_rt::system_reset(sbi_rt::Shutdown, sbi_rt::NoReason),
ExitCode::Failure => sbi_r... | ostd/src/arch/riscv/power.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The console I/O.
use core::fmt;
use spin::Once;
use crate::sync::{LocalIrqDisabled, SpinLock};
/// The primary serial port, which serves as an early console.
pub(crate) static SERIAL_PORT: Once<SpinLock<SbiSerial, LocalIrqDisabled>> =
Once::initialized(SpinLock::new(SbiS... | ostd/src/arch/riscv/serial.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
// The boot routine executed by application processors (APs) on RISC-V.
SATP_MODE_SV39 = 8 << 60
SATP_MODE_SV48 = 9 << 60
SATP_PPN_SHIFT = 0
PAGE_SHIFT = 12
KERNEL_VMA_OFFSET = 0xffffffff00000000
# This is to workaround <https://github.c... | ostd/src/arch/riscv/boot/ap_boot.S | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
// The boot routine executed by the bootstrap processor (BSP) on RISC-V.
SATP_MODE_SV39 = 8 << 60
SATP_MODE_SV48 = 9 << 60
SATP_PPN_SHIFT = 0
PTE_V = 0x01
PTE_R = 0x02
PTE_W = 0x04
PTE_X ... | ostd/src/arch/riscv/boot/bsp_boot.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The RISC-V boot module defines the entrypoints of Asterinas.
pub(crate) mod smp;
use core::arch::global_asm;
use fdt::Fdt;
use spin::Once;
use crate::{
boot::{
BootloaderAcpiArg, BootloaderFramebufferArg,
memory_region::{MemoryRegion, MemoryRegionArray, M... | ostd/src/arch/riscv/boot/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Multiprocessor Boot Support
use core::arch::global_asm;
use crate::{
boot::smp::{PerApRawInfo, ap_early_entry},
cpu_local_cell,
mm::{Paddr, Vaddr},
};
// Include the AP boot assembly code
global_asm!(include_str!("ap_boot.S"));
pub(crate) fn count_processors() ->... | ostd/src/arch/riscv/boot/smp.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU execution context control.
use alloc::boxed::Box;
use core::{arch::global_asm, fmt::Debug};
use ostd_pod::IntoBytes;
use riscv::{
interrupt::supervisor::{Exception, Interrupt},
register::scause::Trap,
};
use crate::{
arch::{
cpu::extension::{IsaExtensi... | ostd/src/arch/riscv/cpu/context.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! RISC-V ISA extensions.
use bitflags::bitflags;
use spin::Once;
use crate::arch::boot::DEVICE_TREE;
/// Detects available RISC-V ISA extensions.
pub(in crate::arch) fn init() {
let mut global_isa_extensions = IsaExtensions::all();
let device_tree = DEVICE_TREE.get().e... | ostd/src/arch/riscv/cpu/extension.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.macro SAVE_FPU_CONTEXT base, store_insn, reg_size
# Enable FPU
li t1, {SSTATUS_FS_MASK}
csrs sstatus, t1
.if \reg_size == 16
# Q extension - use manual encoding
FSQ 0, 0, 10 # a0 is register x10
FSQ 1, 16, 10
FSQ 2, 32, 10
... | ostd/src/arch/riscv/cpu/fpu.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Architecture dependent CPU-local information utilities.
pub(crate) fn get_base() -> u64 {
let mut gp;
unsafe {
core::arch::asm!(
"mv {gp}, gp",
gp = out(reg) gp,
options(preserves_flags, nostack)
);
}
gp
} | ostd/src/arch/riscv/cpu/local.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU context & state control and CPU local memory.
pub mod context;
pub mod extension;
pub mod local; | ostd/src/arch/riscv/cpu/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The IOMMU support.
use crate::mm::{Daddr, Paddr};
/// An enumeration representing possible errors related to IOMMU.
#[derive(Debug)]
pub(crate) enum IommuError {
/// No IOMMU is available.
NoIommu,
}
///
/// # Safety
///
/// Mapping an incorrect address may lead to a ... | ostd/src/arch/riscv/iommu/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Inter-processor interrupts.
use spin::Once;
use crate::{cpu::PinCurrentCpu, irq::IrqLine};
/// Hardware-specific, architecture-dependent CPU ID.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub(crate) struct HwCpuId(u32);
impl HwCpuId {
pub(crate) fn read_current(_guard:... | ostd/src/arch/riscv/irq/ipi.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Interrupts.
pub(super) mod chip;
pub(super) mod ipi;
mod ops;
mod remapping;
pub use chip::{IRQ_CHIP, InterruptSourceInFdt, IrqChip, MappedIrqLine};
pub(crate) use ipi::{HwCpuId, send_ipi};
pub(crate) use ops::{
disable_local, disable_local_and_halt, enable_local, enable_l... | ostd/src/arch/riscv/irq/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Interrupt operations.
// FIXME: Mark this as unsafe. See
// <https://github.com/asterinas/asterinas/issues/1120#issuecomment-2748696592>.
pub(crate) fn enable_local() {
// SAFETY: The safety is upheld by the caller.
unsafe { riscv::interrupt::enable() }
}
/// Enables l... | ostd/src/arch/riscv/irq/ops.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Interrupts.
mod plic;
use alloc::boxed::Box;
use core::{
fmt,
ops::{Deref, DerefMut},
};
use spin::Once;
use crate::{
Result,
arch::{
boot::DEVICE_TREE,
irq::{HwIrqLine, InterruptSource, chip::plic::Plic},
},
io::IoMemAllocatorBuilder,... | ostd/src/arch/riscv/irq/chip/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Platform-Level Interrupt Controller (PLIC) for RISC-V.
use alloc::{boxed::Box, collections::btree_map::BTreeMap, vec::Vec};
use bit_field::BitField;
use fdt::Fdt;
use crate::{
Error, Result,
io::{IoMem, IoMemAllocatorBuilder, Sensitive},
irq::IrqLine,
};
/// The ... | ostd/src/arch/riscv/irq/chip/plic.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
.option push
# We explicitly add this directive due to a known bug in how rustc treats target
# features in `global_asm`. Check https://github.com/rust-lang/rust/issues/111637#issuecomment-1870096878
# for details.
.option arch, rv64imac
# Atomically compares and exchange... | ostd/src/arch/riscv/mm/atomic_cmpxchg_fallible.S | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
# Atomically loads a 32-bit integer value. This function works with exception
# handling and can recover from a page fault.
#
# Returns the loaded value or `!0u64` if failed to load.
.global __atomic_load_fallible
.type __atomic_load_fallible, @function
__atomic_load_falli... | ostd/src/arch/riscv/mm/atomic_load_fallible.S | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
# Copies `size` bytes from `src` to `dst`. This function works with exception
# handling and can recover from a page fault. The source range must not overlap
# with the destination range (In virtual address level. Their corresponding
# physical addresses can be overlapped)... | ostd/src/arch/riscv/mm/memcpy_fallible.S | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
# Sets `size` bytes of memory at `dst` to the byte value given by `value`.
# This function works with exception handling and can recover from a page fault.
#
# Returns number of bytes that failed to set.
.global __memset_fallible
.type __memset_fallible, @function
__memset... | ostd/src/arch/riscv/mm/memset_fallible.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::ops::Range;
use spin::Once;
pub(crate) use util::{
__atomic_cmpxchg_fallible, __atomic_load_fallible, __memcpy_fallible, __memset_fallible,
};
use crate::{
arch::{
boot::DEVICE_TREE,
cpu::extension::{IsaExtensions, has_extensions},
},
mm::... | ostd/src/arch/riscv/mm/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use crate::arch::trap::SSTATUS_SUM;
core::arch::global_asm!(include_str!("memcpy_fallible.S"), SSTATUS_SUM = const SSTATUS_SUM);
core::arch::global_asm!(include_str!("memset_fallible.S"), SSTATUS_SUM = const SSTATUS_SUM);
core::arch::global_asm!(include_str!("atomic_load_fallible.... | ostd/src/arch/riscv/mm/util.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The architecture support of context switch.
use crate::task::TaskContextApi;
core::arch::global_asm!(include_str!("switch.S"));
#[derive(Debug, Clone)]
#[repr(C)]
pub(crate) struct TaskContext {
regs: CalleeRegs,
ra: usize,
}
impl TaskContext {
/// Creates a new ... | ostd/src/arch/riscv/task/mod.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
.global context_switch
.type context_switch, @function
context_switch: # (nxt: *const TaskContext, cur: *mut TaskContext)
# Save cur's register
sd ra, 0x68(a1) # return address
sd sp, 0x0(a1)
sd s0, 0x8(a1)
sd s1, 0x10(a1)
sd s2, 0x18(a1)
sd s3, 0x20(a1... | ostd/src/arch/riscv/task/switch.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The timer support.
use core::{
arch::asm,
sync::atomic::{AtomicU64, Ordering},
};
use spin::Once;
use crate::{
arch::{self, boot::DEVICE_TREE, cpu::extension::IsaExtensions, trap::TrapFrame},
irq::IrqLine,
timer::TIMER_FREQ,
};
pub(super) static TIMER_IRQ... | ostd/src/arch/riscv/timer/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Handles trap.
#[expect(clippy::module_inception)]
mod trap;
use riscv::{
interrupt::supervisor::{Exception, Interrupt},
register::scause::Trap,
};
use spin::Once;
pub use trap::TrapFrame;
pub(super) use trap::{RawUserContext, SSTATUS_FS_MASK, SSTATUS_SUM};
use crate::... | ostd/src/arch/riscv/trap/mod.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 OR MIT
*
* The original source code is from [trapframe-rs](https://github.com/rcore-os/trapframe-rs),
* which is released under the following license:
*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2020 - 2024 Runji Wang
*
* We make the following new changes:
* * Adjust... | ostd/src/arch/riscv/trap/trap.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0 OR MIT
//
// The original source code is from [trapframe-rs](https://github.com/rcore-os/trapframe-rs),
// which is released under the following license:
//
// SPDX-License-Identifier: MIT
//
// Copyright (c) 2020 - 2024 Runji Wang
//
// We make the following new changes:
// * Implem... | ostd/src/arch/riscv/trap/trap.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::vec::Vec;
use align_ext::AlignExt;
use crate::{boot::memory_region::MemoryRegionType, io::IoMemAllocatorBuilder};
/// Initializes the allocatable MMIO area based on the x86-64 memory distribution map.
///
/// In x86-64, the available physical memory area is divided int... | ostd/src/arch/x86/io.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Platform-specific code for the x86 platform.
pub(crate) mod boot;
pub mod cpu;
pub mod device;
pub(crate) mod io;
pub(crate) mod iommu;
pub mod irq;
pub mod kernel;
pub(crate) mod mm;
mod power;
pub mod serial;
pub(crate) mod task;
mod timer;
pub mod trap;
#[cfg(feature = "cvm... | ostd/src/arch/x86/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Power management.
mod qemu_isa_debug {
//! The isa-debug-exit device in QEMU.
//!
//! Reference: <https://elixir.bootlin.com/qemu/v10.1.2/source/hw/misc/debugexit.c>
use spin::Once;
use crate::{
arch::device::io_port::WriteOnlyAccess,
io::I... | ostd/src/arch/x86/power.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The console I/O.
use spin::Once;
use x86_64::instructions::port::ReadWriteAccess;
use crate::{
console::uart_ns16650a::{Ns16550aAccess, Ns16550aRegister, Ns16550aUart},
io::{IoPort, reserve_io_port_range},
sync::{LocalIrqDisabled, SpinLock},
};
/// The primary ser... | ostd/src/arch/x86/serial.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use tdx_guest::{TdxTrapFrame, tdcall::accept_page, tdvmcall::map_gpa};
use super::trap::TrapFrame;
use crate::{mm::PAGE_SIZE, prelude::Paddr};
const SHARED_BIT: u8 = 51;
const SHARED_MASK: u64 = 1u64 << SHARED_BIT;
#[derive(Debug)]
pub enum PageConvertError {
TdCall,
TdVm... | ostd/src/arch/x86/tdx_guest.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
// The boot routine executed by the application processor.
IA32_EFER_MSR = 0xC0000080
IA32_EFER_BIT_LME = 1 << 8
IA32_EFER_BIT_NXE = 1 << 11
IA32_GS_BASE_MSR = 0xC0000101
CR0_BIT_PE = 1 << 0
CR0_BIT_PG = 1 << 31
CR4_BIT_PAE = 1 << 5
CR4_BIT_PGE ... | ostd/src/arch/x86/boot/ap_boot.S | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
// The boot routine executed by the bootstrap processor.
IA32_EFER_MSR = 0xC0000080
IA32_EFER_BIT_LME = 1 << 8
IA32_GS_BASE_MSR = 0xC0000101
CR0_BIT_PG = 1 << 31
CR4_BIT_PAE = 1 << 5
CR4_BIT_PGE = 1 << 7
KERNEL_VMA = 0xffffffff80000000
// The ... | ostd/src/arch/x86/boot/bsp_boot.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The x86 boot module defines the entrypoints of Asterinas and
//! the corresponding headers for different x86 boot protocols.
//!
//! We directly support
//!
//! - Multiboot
//! - Multiboot2
//! - Linux x86 Boot Protocol
//!
//! without any additional configurations.
//!
//! A... | ostd/src/arch/x86/boot/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Multiprocessor Boot Support
//!
//! The MP initialization protocol defines two classes of processors:
//! the bootstrap processor (BSP) and the application processors (APs).
//! Following a power-up or RESET of an MP system, system hardware dynamically
//! selects one of the pro... | ostd/src/arch/x86/boot/smp.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The Linux 64-bit Boot Protocol supporting module.
//!
use linux_boot_params::{BootParams, E820Type, LINUX_BOOT_HEADER_MAGIC};
#[cfg(feature = "cvm_guest")]
use crate::arch::init_cvm_guest;
use crate::{
arch::if_tdx_enabled,
boot::{
BootloaderAcpiArg, Bootloader... | ostd/src/arch/x86/boot/linux_boot/mod.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
// This is the GNU Multiboot header.
// Reference: https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section ".multiboot_header", "a"
MB_MAGIC = 0x1BADB002
MB_FLAGS = 0
MB_CHECKSUM = -(MB_MAGIC + MB_FLAGS)
.code32
multiboot_header:
.align 8
.long MB_MAG... | ostd/src/arch/x86/boot/multiboot/header.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::arch::global_asm;
use crate::{
boot::{
BootloaderAcpiArg, BootloaderFramebufferArg,
memory_region::{MemoryRegion, MemoryRegionArray, MemoryRegionType},
},
mm::{Paddr, kspace::paddr_to_vaddr},
};
global_asm!(include_str!("header.S"));
const MU... | ostd/src/arch/x86/boot/multiboot/mod.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
// This is the GNU Multiboot 2 header.
// Reference: https://www.gnu.org/software/grub/manual/multiboot2/html_node/Index.html//Index
.section ".multiboot2_header", "a"
.code32
// Macros for cleaner code in the header fields.
MB2_MAGIC = 0xE85250D6
MB2_ARCHITECTURE = 0 // 32-bit ... | ostd/src/arch/x86/boot/multiboot2/header.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::arch::global_asm;
use multiboot2::{BootInformation, BootInformationHeader, MemoryAreaType};
use crate::{
boot::{
BootloaderAcpiArg, BootloaderFramebufferArg,
memory_region::{MemoryRegion, MemoryRegionArray, MemoryRegionType},
},
mm::{Paddr, ks... | ostd/src/arch/x86/boot/multiboot2/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU information from the CPUID instruction.
use core::arch::x86_64::CpuidResult;
use spin::Once;
static MAX_LEAF: Once<u32> = Once::new();
static MAX_HYPERVISOR_LEAF: Once<u32> = Once::new();
static MAX_EXTENDED_LEAF: Once<u32> = Once::new();
#[repr(u32)]
enum Leaf {
Bas... | ostd/src/arch/x86/cpu/cpuid.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! x86 ISA extensions.
use core::arch::x86_64::CpuidResult;
use bitflags::bitflags;
use spin::Once;
use super::cpuid::cpuid;
/// Detects available x86 ISA extensions.
pub(in crate::arch) fn init() {
let mut global_isa_extensions = IsaExtensions::empty();
for ext_leaf i... | ostd/src/arch/x86/cpu/extension.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Architecture dependent CPU-local information utilities.
use x86_64::registers::segmentation::{GS, Segment64};
/// Gets the base address for the CPU local storage by reading the GS base model-specific register.
pub(crate) fn get_base() -> u64 {
GS::read_base().as_u64()
}
u... | ostd/src/arch/x86/cpu/local.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU context & state control and CPU local memory.
pub mod context;
pub mod cpuid;
pub mod extension;
pub mod local; | ostd/src/arch/x86/cpu/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU execution context control.
use alloc::boxed::Box;
use core::arch::x86_64::{_fxrstor64, _fxsave64, _xrstor64, _xsave64};
use bitflags::bitflags;
use cfg_if::cfg_if;
use log::debug;
use ostd_pod::{FromZeros, IntoBytes};
use spin::Once;
use x86::bits64::segmentation::wrfsbase... | ostd/src/arch/x86/cpu/context/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use tdx_guest::{
TdgVeInfo, TdxTrapFrame, handle_virtual_exception as do_handle_virtual_exception, tdcall,
};
use super::{GeneralRegs, UserContext};
pub(crate) struct VirtualizationExceptionHandler {
ve_info: TdgVeInfo,
}
impl VirtualizationExceptionHandler {
/// Crea... | ostd/src/arch/x86/cpu/context/tdx.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! I/O port access.
pub use x86_64::{
instructions::port::{
PortReadAccess as IoPortReadAccess, PortWriteAccess as IoPortWriteAccess, ReadOnlyAccess,
ReadWriteAccess, WriteOnlyAccess,
},
structures::port::{PortRead, PortWrite},
}; | ostd/src/arch/x86/device/io_port.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::vec::Vec;
use core::{fmt::Debug, ptr::NonNull};
use bitflags::bitflags;
use log::{error, info};
use spin::Once;
use volatile::{VolatileRef, access::ReadWrite};
use super::registers::Capability;
use crate::{
arch::trap::TrapFrame,
irq::IrqLine,
sync::{LocalIr... | ostd/src/arch/x86/iommu/fault.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The IOMMU support.
mod dma_remapping;
mod fault;
mod interrupt_remapping;
mod invalidate;
mod registers;
pub(crate) use dma_remapping::{IommuPtConfig, has_dma_remapping, map, unmap};
pub(in crate::arch) use interrupt_remapping::{
IrtEntryHandle, alloc_irt_entry, has_interr... | ostd/src/arch/x86/iommu/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
#![expect(dead_code)]
use alloc::collections::BTreeMap;
use log::trace;
use super::second_stage::IommuPtConfig;
use crate::{
arch::iommu::dma_remapping::PciDeviceLocation,
mm::{
Daddr, Frame, FrameAllocOptions, HasPaddr, PAGE_SIZE, Paddr, PageFlags, PageTable, VmI... | ostd/src/arch/x86/iommu/dma_remapping/context_table.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
pub use context_table::RootTable;
use log::{info, warn};
pub use second_stage::IommuPtConfig;
use spin::Once;
use super::IommuError;
use crate::{
arch::iommu::registers::{CapabilitySagaw, IOMMU_REGS},
mm::{Daddr, PageTable},
prelude::Paddr,
sync::{LocalIrqDisabled, ... | ostd/src/arch/x86/iommu/dma_remapping/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::ops::Range;
use crate::mm::{
Paddr, PageProperty, PagingConstsTrait, PagingLevel, PodOnce,
page_prop::{CachePolicy, PageFlags, PageTableFlags, PrivilegedPageFlags as PrivFlags},
page_table::{PageTableConfig, PteScalar, PteTrait},
};
/// The page table used by... | ostd/src/arch/x86/iommu/dma_remapping/second_stage.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
mod table;
use core::fmt::Debug;
use log::{info, warn};
use spin::Once;
pub(super) use table::IntRemappingTable;
use crate::arch::iommu::registers::{ExtendedCapabilityFlags, IOMMU_REGS};
pub struct IrtEntryHandle {
index: u16,
table: &'static IntRemappingTable,
}
impl I... | ostd/src/arch/x86/iommu/interrupt_remapping/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::fmt::Debug;
use bitflags::bitflags;
use id_alloc::IdAlloc;
use int_to_c_enum::TryFromInt;
use super::IrtEntryHandle;
use crate::{
mm::{FrameAllocOptions, HasPaddr, PAGE_SIZE, Segment, io_util::HasVmReaderWriter},
sync::{LocalIrqDisabled, SpinLock},
};
#[expect(d... | ostd/src/arch/x86/iommu/interrupt_remapping/table.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use log::{info, warn};
use queue::Queue;
use spin::Once;
use super::registers::{ExtendedCapabilityFlags, IOMMU_REGS};
use crate::sync::SpinLock;
pub mod descriptor;
pub mod queue;
pub(super) fn init() {
let mut iommu_regs = IOMMU_REGS.get().unwrap().lock();
if !iommu_regs... | ostd/src/arch/x86/iommu/invalidate/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use crate::{
mm::{FrameAllocOptions, PAGE_SIZE, Segment, VmIo},
prelude::*,
};
pub struct Queue {
segment: Segment<()>,
queue_size: usize,
tail: usize,
}
impl Queue {
pub fn append_descriptor(&mut self, descriptor: u128) {
if self.tail == self.queue... | ostd/src/arch/x86/iommu/invalidate/queue.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
pub struct InterruptEntryCache(pub u128);
impl InterruptEntryCache {
const INVALIDATION_TYPE: u128 = 4;
pub fn global_invalidation() -> Self {
Self(Self::INVALIDATION_TYPE)
}
}
pub struct InvalidationWait(pub u128);
impl InvalidationWait {
const INVALIDAT... | ostd/src/arch/x86/iommu/invalidate/descriptor/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::fmt::Debug;
use bitflags::bitflags;
/// Capability in IOMMU.
pub struct Capability(u64);
impl Capability {
/// Create Capability from `value`
pub const fn new(value: u64) -> Self {
Self(value)
}
/// Capability flags
pub const fn flags(&self)... | ostd/src/arch/x86/iommu/registers/capability.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use bitflags::bitflags;
bitflags! {
/// Global Command to enable functions in IOMMU. All field is write-only.
pub struct GlobalCommand: u32{
/// Compatibility Format Interrupt, only valid if interrupt-remapping is supported.
///
/// Interrupt remappi... | ostd/src/arch/x86/iommu/registers/command.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::fmt::Debug;
use bitflags::bitflags;
pub struct ExtendedCapability(u64);
impl ExtendedCapability {
/// Creates ExtendedCapability from `value`
pub const fn new(value: u64) -> Self {
Self(value)
}
/// Extended capability flags
pub const fn fla... | ostd/src/arch/x86/iommu/registers/extended_cap.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Invalidation-related registers
use core::ptr::NonNull;
use volatile::{
VolatileRef,
access::{ReadOnly, ReadWrite, WriteOnly},
};
use super::ExtendedCapability;
#[derive(Debug)]
pub struct InvalidationRegisters {
pub(super) _queue_head: VolatileRef<'static, u64, R... | ostd/src/arch/x86/iommu/registers/invalidation.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Registers and their definition used by IOMMU.
mod capability;
mod command;
mod extended_cap;
mod invalidation;
mod status;
use core::ptr::NonNull;
use bit_field::BitField;
pub use capability::{Capability, CapabilitySagaw};
use command::GlobalCommand;
use extended_cap::Extende... | ostd/src/arch/x86/iommu/registers/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use bitflags::bitflags;
bitflags! {
/// Global Status of the IOMMU. All fields is read-only. Some description of the fields
/// is related to the fields in `GlobalCommand`.
pub struct GlobalStatus: u32{
/// Compatibility Format Interrupt Status. The value report... | ostd/src/arch/x86/iommu/registers/status.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Inter-processor interrupts.
use spin::Once;
use crate::{cpu::PinCurrentCpu, irq::IrqLine, smp::do_inter_processor_call};
/// Hardware-specific, architecture-dependent CPU ID.
///
/// This is the Local APIC ID in the x86_64 architecture.
#[derive(Debug, Clone, Copy, PartialEq,... | ostd/src/arch/x86/irq/ipi.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Interrupts.
pub(super) mod chip;
pub(super) mod ipi;
mod ops;
mod remapping;
pub use chip::{IRQ_CHIP, IrqChip, MappedIrqLine};
pub(crate) use ipi::{HwCpuId, send_ipi};
pub(crate) use ops::{
disable_local, disable_local_and_halt, enable_local, enable_local_and_halt, is_loca... | ostd/src/arch/x86/irq/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Interrupt operations.
use x86_64::registers::rflags::{self, RFlags};
// FIXME: Mark this as unsafe. See
// <https://github.com/asterinas/asterinas/issues/1120#issuecomment-2748696592>.
pub(crate) fn enable_local() {
x86_64::instructions::interrupts::enable();
// When e... | ostd/src/arch/x86/irq/ops.rs | null | null | null | null | null |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.