data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use spin::once::Once;
use crate::arch::iommu::{IrtEntryHandle, alloc_irt_entry, has_interrupt_remapping};
pub(crate) struct IrqRemapping {
entry: Once<IrtEntryHandle>,
}
impl IrqRemapping {
pub(crate) const fn new() -> Self {
Self { entry: Once::new() }
}
... | ostd/src/arch/x86/irq/remapping.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use bit_field::BitField;
use log::info;
use crate::{
Error, Result,
io::{IoMem, IoMemAllocatorBuilder, Sensitive},
irq::IrqLine,
};
/// I/O Advanced Programmable Interrupt Controller (APIC).
///
/// It is used to distribute external interrupts in a more advanced manner... | ostd/src/arch/x86/irq/chip/ioapic.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::{boxed::Box, vec::Vec};
use core::{
fmt,
ops::{Deref, DerefMut},
};
use ioapic::IoApic;
use log::info;
use spin::Once;
use crate::{
Error, Result, arch::kernel::acpi::get_acpi_tables, io::IoMemAllocatorBuilder, irq::IrqLine,
sync::SpinLock,
};
mod ioapi... | ostd/src/arch/x86/irq/chip/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use log::info;
use crate::{
arch::device::io_port::WriteOnlyAccess,
io::{IoPort, sensitive_io_port},
};
sensitive_io_port! {
unsafe {
static MASTER_CMD: IoPort<u8, WriteOnlyAccess> = IoPort::new(0x20);
static MASTER_DATA: IoPort<u8, WriteOnlyAccess> = I... | ostd/src/arch/x86/irq/chip/pic.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Architecture kernel module.
//
// TODO: The purpose of this module is too ambiguous. We should split it up and move its submodules
// to more suitable locations.
pub(super) mod acpi;
pub(super) mod apic;
pub(super) mod tsc;
pub use acpi::{ACPI_INFO, AcpiInfo}; | ostd/src/arch/x86/kernel/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::sync::atomic::{AtomicBool, AtomicU64, Ordering};
use log::info;
use crate::{
arch::{
timer::pit::{self, OperatingMode},
trap::TrapFrame,
},
irq::IrqLine,
timer::TIMER_FREQ,
};
/// The frequency in Hz of the Time Stamp Counter (TSC).
pub(i... | ostd/src/arch/x86/kernel/tsc.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
#![expect(dead_code)]
use alloc::vec::Vec;
use core::{fmt::Debug, slice::Iter};
use acpi::{
AcpiTable,
sdt::{SdtHeader, Signature},
};
use super::remapping::{Andd, Atsr, Drhd, Rhsa, Rmrr, Satc, Sidp};
/// DMA Remapping structure.
///
/// When IOMMU is enabled, the struct... | ostd/src/arch/x86/kernel/acpi/dmar.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
pub(in crate::arch) mod dmar;
pub(in crate::arch) mod remapping;
use core::{num::NonZeroU8, ptr::NonNull};
use acpi::{
AcpiHandler, AcpiTables,
address::AddressSpace,
fadt::{Fadt, IaPcBootArchFlags},
mcfg::Mcfg,
rsdp::Rsdp,
};
use log::warn;
use spin::Once;
us... | ostd/src/arch/x86/kernel/acpi/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
#![expect(dead_code)]
//! Remapping structures of DMAR table.
//!
//! This file defines these structures and provides a `Debug` implementation to see the value
//! inside these structures.
//!
//! Most of the introduction are copied from Intel vt-directed-io-specification.
use all... | ostd/src/arch/x86/kernel/acpi/remapping.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::boxed::Box;
use bit_field::BitField;
use spin::Once;
use crate::{
cpu::PinCurrentCpu,
cpu_local,
io::{IoMem, IoMemAllocatorBuilder, Sensitive},
};
mod x2apic;
mod xapic;
static APIC_TYPE: Once<ApicType> = Once::new();
/// Returns a reference to the local ... | ostd/src/arch/x86/kernel/apic/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use x86::msr::{
IA32_APIC_BASE, IA32_X2APIC_APICID, IA32_X2APIC_CUR_COUNT, IA32_X2APIC_DIV_CONF,
IA32_X2APIC_EOI, IA32_X2APIC_ESR, IA32_X2APIC_ICR, IA32_X2APIC_INIT_COUNT,
IA32_X2APIC_LVT_TIMER, IA32_X2APIC_SIVR, IA32_X2APIC_VERSION, rdmsr, wrmsr,
};
use super::ApicTime... | ostd/src/arch/x86/kernel/apic/x2apic.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use x86::{
apic::xapic,
msr::{IA32_APIC_BASE, rdmsr, wrmsr},
};
use super::ApicTimer;
use crate::{
io::{IoMem, Sensitive},
mm::{HasPaddr, HasSize},
};
#[derive(Debug)]
pub(super) struct XApic {
io_mem: IoMem<Sensitive>,
}
// The APIC instance can be shared amo... | ostd/src/arch/x86/kernel/apic/xapic.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
.code64
// Atomically compares and exchanges a 32-bit integer value. This function works with
// exception handling and can recover from a page fault.
//
// Returns the previous value or `!0u64` if failed to update.
.global __atomic_cmpxchg_fallible
.type __atomic_cmpxchg_... | ostd/src/arch/x86/mm/atomic_cmpxchg_fallible.S | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
.code64
// Atomically loads a 32-bit integer value. This function works with exception handling
// and can recover from a page fault.
//
// Returns the loaded value or `!0u64` if failed to load.
.global __atomic_load_fallible
.type __atomic_load_fallible, @function
__atomi... | ostd/src/arch/x86/mm/atomic_load_fallible.S | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
.code64
// Copies `size` bytes from `src` to `dst`. This function works with exception handling
// and can recover from a page fault. The source range must not overlap with the destination range
// (In virtual address level. Their corresponding physical addresses can be ov... | ostd/src/arch/x86/mm/memcpy_fallible.S | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
.code64
// Sets `size` bytes of memory at `dst` to the byte value given by `value`.
// This function works with exception handling and can recover from a page fault.
//
// Returns number of bytes that failed to set.
//
// Ref: [https://github.com/torvalds/linux/blob/2ab79... | ostd/src/arch/x86/mm/memset_fallible.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::ops::Range;
use cfg_if::cfg_if;
pub(crate) use util::{
__atomic_cmpxchg_fallible, __atomic_load_fallible, __memcpy_fallible, __memset_fallible,
};
use x86_64::{
VirtAddr,
instructions::tlb,
registers::model_specific::{Efer, EferFlags},
structures::pagi... | ostd/src/arch/x86/mm/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use x86::msr::{IA32_PAT, wrmsr};
use super::PteFlags;
use crate::{const_assert, mm::page_prop::CachePolicy};
/// Software-defined mapping from PAT (page attribute table) bit combinations
/// to cache policies.
///
/// Index encoding: `(PAT << 2) | (PCD << 1) | PWT`.
///
/// Indice... | ostd/src/arch/x86/mm/pat.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
core::arch::global_asm!(include_str!("memcpy_fallible.S"));
core::arch::global_asm!(include_str!("memset_fallible.S"));
core::arch::global_asm!(include_str!("atomic_load_fallible.S"));
core::arch::global_asm!(include_str!("atomic_cmpxchg_fallible.S"));
unsafe extern "C" {
/// ... | ostd/src/arch/x86/mm/util.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The architecture support of context switch.
use crate::task::TaskContextApi;
core::arch::global_asm!(include_str!("switch.S"));
#[derive(Debug, Clone)]
#[repr(C)]
pub(crate) struct TaskContext {
regs: CalleeRegs,
rip: usize,
fsbase: usize,
}
impl TaskContext {
... | ostd/src/arch/x86/task/mod.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 */
.text
.code64
.global context_switch
.type context_switch, @function
context_switch: # (nxt: *const TaskContext, cur: *mut TaskContext)
# Save cur's register
mov rax, [rsp] # return address
mov [rsi + 56], rax # 56 = offsetof(TaskContext, rip)
mov [rsi + 0], rsp
mov [r... | ostd/src/arch/x86/task/switch.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::sync::atomic::{AtomicU64, Ordering};
use log::info;
use crate::{
arch::{
kernel::apic::{self, Apic, DivideConfig},
timer::pit::OperatingMode,
trap::TrapFrame,
tsc_freq,
},
irq::IrqLine,
task::disable_preempt,
timer::TIM... | ostd/src/arch/x86/timer/apic.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::vec::Vec;
use core::ptr::NonNull;
use acpi::{AcpiError, HpetInfo};
use spin::Once;
use volatile::{
VolatileRef,
access::{ReadOnly, ReadWrite},
};
use crate::{
arch::{
irq::{IRQ_CHIP, MappedIrqLine},
kernel::acpi::get_acpi_tables,
},
i... | ostd/src/arch/x86/timer/hpet.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The timer support.
mod apic;
mod hpet;
pub(in crate::arch) mod pit;
use spin::Once;
use super::trap::TrapFrame;
use crate::irq::IrqLine;
static TIMER_IRQ: Once<IrqLine> = Once::new();
/// Initializes the timer state and enable timer interrupts on BSP.
pub(super) fn init_on_... | ostd/src/arch/x86/timer/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
#![expect(dead_code)]
//! The Programmable Interval Timer (PIT) chip (Intel 8253/8254) basically consists of an oscillator,
//! a prescaler and 3 independent frequency dividers. Each frequency divider has an output, which is
//! used to allow the timer to control external circuitry... | ostd/src/arch/x86/timer/pit.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Configure the Global Descriptor Table (GDT).
use alloc::boxed::Box;
use x86_64::{
PrivilegeLevel, VirtAddr,
instructions::tables::{lgdt, load_tss},
registers::{
model_specific::Star,
segmentation::{CS, Segment},
},
structures::{
Desc... | ostd/src/arch/x86/trap/gdt.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Configure the Interrupt Descriptor Table (IDT).
use alloc::boxed::Box;
use core::arch::global_asm;
use spin::Once;
use x86_64::{
PrivilegeLevel, VirtAddr,
instructions::tables::lidt,
structures::{DescriptorTablePointer, idt::Entry},
};
global_asm!(include_str!("tr... | ostd/src/arch/x86/trap/idt.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0 OR MIT
//
// The original source code is from [trapframe-rs](https://github.com/rcore-os/trapframe-rs),
// which is released under the following license:
//
// SPDX-License-Identifier: MIT
//
// Copyright (c) 2020 - 2024 Runji Wang
//
// We make the following new changes:
// * Implem... | ostd/src/arch/x86/trap/mod.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 OR MIT
*
* The original source code is from [trapframe-rs](https://github.com/rcore-os/trapframe-rs),
* which is released under the following license:
*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2020 - 2024 Runji Wang
*
* We make the following new changes:
* * Skip s... | ostd/src/arch/x86/trap/syscall.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0 OR MIT
//
// The original source code is from [trapframe-rs](https://github.com/rcore-os/trapframe-rs),
// which is released under the following license:
//
// SPDX-License-Identifier: MIT
//
// Copyright (c) 2020 - 2024 Runji Wang
//
// We make the following new changes:
// * Revise... | ostd/src/arch/x86/trap/syscall.rs | null | null | null | null | null |
source | asterinas | /* SPDX-License-Identifier: MPL-2.0 OR MIT
*
* The original source code is from [trapframe-rs](https://github.com/rcore-os/trapframe-rs),
* which is released under the following license:
*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2020 - 2024 Runji Wang
*
* We make the following new changes:
* * Add th... | ostd/src/arch/x86/trap/trap.S | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Information of memory regions in the boot phase.
use core::ops::Deref;
use align_ext::AlignExt;
use crate::mm::{PAGE_SIZE, Paddr, Vaddr, kspace::kernel_loaded_offset};
/// The type of initial memory regions that are needed for the kernel.
#[derive(Clone, Copy, PartialEq, Eq,... | ostd/src/boot/memory_region.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The architecture-independent boot module, which provides
//! 1. a universal information getter interface from the bootloader to the
//! rest of OSTD;
//! 2. the routine booting into the actual kernel;
//! 3. the routine booting the other processors in the SMP context.
#!... | ostd/src/boot/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Symmetric multiprocessing (SMP) boot support.
use alloc::{boxed::Box, collections::btree_map::BTreeMap, vec::Vec};
use spin::Once;
use crate::{
arch::irq::HwCpuId,
mm::{
FrameAllocOptions, HasPaddrRange, PAGE_SIZE,
frame::{Segment, meta::KernelMeta},
... | ostd/src/boot/smp.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Console output.
use core::fmt::{Arguments, Write};
use crate::arch::serial::SERIAL_PORT;
pub mod uart_ns16650a;
/// Prints formatted arguments to the console.
pub fn early_print(args: Arguments) {
let Some(serial) = SERIAL_PORT.get() else {
return;
};
#[... | ostd/src/console/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! NS16550A UART.
//!
//! This is used as an early console in x86 and LoongArch. It also exists on some (but not all)
//! RISC-V and ARM platforms.
//!
//! Reference: <https://bitsavers.trailing-edge.com/components/national/_appNotes/AN-0491.pdf>
use core::fmt;
use bitflags::bitf... | ostd/src/console/uart_ns16650a.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU identification numbers.
pub use current::PinCurrentCpu;
pub use set::{AtomicCpuSet, CpuSet};
use crate::util::id_set::Id;
/// The ID of a CPU in the system.
///
/// If converting from/to an integer, the integer must start from 0 and be less
/// than the number of CPUs.
#[... | ostd/src/cpu/id.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU-related definitions.
mod id;
pub mod local;
pub use id::{AtomicCpuSet, CpuId, CpuIdFromIntError, CpuSet, PinCurrentCpu, all_cpus, num_cpus};
/// The CPU privilege level: user mode or kernel mode.
#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord)]
#[repr(u8)]
pu... | ostd/src/cpu/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The implementation of CPU-local variables that have inner mutability.
use core::cell::UnsafeCell;
use super::{__cpu_local_end, __cpu_local_start, single_instr::*};
use crate::arch;
/// Defines an inner-mutable CPU-local variable.
///
/// The accessors of the CPU-local variabl... | ostd/src/cpu/local/cell.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Dynamically-allocated CPU-local objects.
use core::{marker::PhantomData, mem::ManuallyDrop, ptr::NonNull};
use bitvec::prelude::{BitVec, bitvec};
use super::{AnyStorage, CpuLocal};
use crate::{
Result,
cpu::{CpuId, PinCurrentCpu, all_cpus, num_cpus},
irq::Disabled... | ostd/src/cpu/local/dyn_cpu_local.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! CPU local storage.
//!
//! This module provides a mechanism to define CPU-local objects. Users can
//! define a statically-allocated CPU-local object by the macro
//! [`crate::cpu_local!`], or allocate a dynamically-allocated CPU-local
//! object with the function `osdk_heap_all... | ostd/src/cpu/local/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Extensions for CPU-local types that allows single-instruction operations.
//!
//! For some per-CPU objects, fetching or modifying the values of them can be
//! done in a single instruction. Then we would avoid turning off interrupts
//! when accessing them, which incurs non-triv... | ostd/src/cpu/local/single_instr.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Statically-allocated CPU-local objects.
#![cfg_attr(
any(target_arch = "riscv64", target_arch = "loongarch64"),
expect(dead_code)
)]
use core::marker::PhantomData;
use super::{__cpu_local_end, __cpu_local_start, AnyStorage, CpuLocal};
use crate::{arch, cpu::CpuId, irq... | ostd/src/cpu/local/static_cpu_local.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Device I/O access and corresponding allocator.
//!
//! This module allows device drivers to access the device I/O they need
//! through _allocators_. There are two types of device I/O:
//! - `IoMem` for memory I/O (MMIO).
//! - `IoPort` for port I/O (PIO).
mod io_mem;
pub us... | ostd/src/io/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! I/O Memory allocator.
use alloc::vec::Vec;
use core::ops::Range;
use log::{debug, info};
use spin::Once;
use crate::{
io::io_mem::{Insensitive, IoMem, Sensitive},
mm::{CachePolicy, PageFlags},
util::range_alloc::RangeAllocator,
};
/// I/O memory allocator that al... | ostd/src/io/io_mem/allocator.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! I/O memory and its allocator that allocates memory I/O (MMIO) to device drivers.
mod allocator;
use core::{
marker::PhantomData,
ops::{Deref, Range},
};
use align_ext::AlignExt;
pub(crate) use self::allocator::IoMemAllocatorBuilder;
pub(super) use self::allocator::in... | ostd/src/io/io_mem/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! I/O port allocator.
use core::ops::Range;
use id_alloc::IdAlloc;
use log::debug;
use spin::Once;
use super::IoPort;
use crate::{
io::RawIoPortRange,
sync::{LocalIrqDisabled, SpinLock},
};
/// I/O port allocator that allocates port I/O access to device drivers.
pub(sup... | ostd/src/io/io_port/allocator.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! I/O port and its allocator that allocates port I/O (PIO) to device drivers.
use crate::arch::device::io_port::{IoPortReadAccess, IoPortWriteAccess, PortRead, PortWrite};
mod allocator;
use core::marker::PhantomData;
pub(super) use self::allocator::init;
use crate::{Error, pre... | ostd/src/io/io_port/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The bottom half of interrupt handling.
use spin::Once;
use super::{DisabledLocalIrqGuard, InterruptLevel, disable_local};
use crate::task::disable_preempt;
/// Registers a bottom half callback to be executed at interrupt level 1.
///
/// The callback takes a [`DisabledLocalIr... | ostd/src/irq/bottom_half.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The IRQ disabling guard.
use crate::{arch::irq as arch_irq, sync::GuardTransfer, task::atomic_mode::InAtomicMode};
/// Disables all IRQs on the current CPU (i.e., locally).
///
/// This function returns a guard object, which will automatically enable local IRQs again when
/// ... | ostd/src/irq/guard.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The interrupt level.
use crate::{cpu::PrivilegeLevel, cpu_local_cell};
/// The current interrupt level on a CPU.
///
/// This type tracks the current nesting depth on the CPU
/// where the code is executing.
/// There are three levels:
/// * Level 0 (the task context);
/// * L... | ostd/src/irq/level.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Handling of Interrupt ReQuests (IRQs).
//!
//! # Top vs bottom half
//!
//! OSTD divides the handling of an IRQ into two parts:
//! **top half** and **bottom half**.
//!
//! A driver can assign to a target device an IRQ line, [`IrqLine`],
//! to which a callback function may be ... | ostd/src/irq/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The top half of interrupt handling.
use core::{fmt::Debug, ops::Deref};
use id_alloc::IdAlloc;
use spin::Once;
use crate::{
Error,
arch::{
irq::{HwIrqLine, IRQ_NUM_MAX, IRQ_NUM_MIN, IrqRemapping},
trap::TrapFrame,
},
prelude::*,
sync::{RwLo... | ostd/src/irq/top_half.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Abstractions for reading and writing virtual memory (VM) objects.
//!
//! # Safety
//!
//! The core virtual memory (VM) access APIs provided by this module are [`VmReader`] and
//! [`VmWriter`], which allow for writing to or reading from a region of memory _safely_.
//! `VmReade... | ostd/src/mm/io.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Utilities for types in [`super::io`].
use inherit_methods_macro::inherit_methods;
use ostd_pod::Pod;
use super::{Infallible, PodOnce, VmIo, VmIoFill, VmIoOnce, VmReader, VmWriter};
use crate::{
Error,
mm::{FallibleVmRead, FallibleVmWrite},
prelude::*,
};
/// A hel... | ostd/src/mm/io_util.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Traits for memory objects.
use alloc::{boxed::Box, rc::Rc, sync::Arc};
use core::ops::Range;
use super::Paddr;
use crate::mm::Daddr;
/// Memory objects that have a start physical address.
pub trait HasPaddr {
/// Returns the start physical address of the memory object.
... | ostd/src/mm/mem_obj.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Virtual memory (VM).
#![cfg_attr(
any(target_arch = "riscv64", target_arch = "loongarch64"),
expect(unused_imports)
)]
pub mod dma;
pub mod frame;
pub mod heap;
pub mod io;
pub mod io_util;
pub(crate) mod kspace;
pub(crate) mod mem_obj;
pub(crate) mod page_prop;
pub(cr... | ostd/src/mm/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Definitions of page mapping properties.
use core::fmt::Debug;
use bitflags::bitflags;
/// The property of a mapped virtual memory page.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct PageProperty {
/// The flags associated with the page,
pub flags: PageFlags,... | ostd/src/mm/page_prop.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::vec;
use crate::{
Error,
io::IoMem,
mm::{
CachePolicy, FallibleVmRead, FallibleVmWrite, FrameAllocOptions, PageFlags, PageProperty,
UFrame, VmSpace,
io::{VmIo, VmIoFill, VmReader, VmWriter},
io_util::HasVmReaderWriter,
... | ostd/src/mm/test.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! TLB flush operations.
use alloc::vec::Vec;
use core::{
mem::MaybeUninit,
ops::Range,
sync::atomic::{AtomicBool, Ordering},
};
use super::{
PAGE_SIZE, Vaddr,
frame::{Frame, meta::AnyFrameMeta},
};
use crate::{
arch::irq,
const_assert,
cpu::{Atomi... | ostd/src/mm/tlb.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Virtual memory space management.
//!
//! The [`VmSpace`] struct is provided to manage the virtual memory space of a
//! user. Cursors are used to traverse and modify over the virtual memory space
//! concurrently. The VM space cursor [`self::Cursor`] is just a wrapper over
//! t... | ostd/src/mm/vm_space.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::{fmt::Debug, mem::ManuallyDrop};
use super::util::{
alloc_kva, cvm_need_private_protection, prepare_dma, split_daddr, unprepare_dma,
};
use crate::{
error::Error,
mm::{
Daddr, FrameAllocOptions, HasDaddr, HasPaddr, HasPaddrRange, HasSize, Infallible,
... | ostd/src/mm/dma/dma_coherent.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::{fmt::Debug, marker::PhantomData, mem::ManuallyDrop, ops::Range};
use super::util::{
alloc_kva, cvm_need_private_protection, prepare_dma, split_daddr, unprepare_dma,
};
use crate::{
arch::mm::can_sync_dma,
error::Error,
mm::{
Daddr, FrameAllocOptio... | ostd/src/mm/dma/dma_stream.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Direct Memory Access (DMA).
//!
//! This module provides [`DmaCoherent`] and [`DmaStream`] abstractions for
//! managing DMA memory regions with different remapping, caching and
//! synchronization requirements.
#[cfg(ktest)]
mod test;
mod dma_coherent;
mod dma_stream;
mod uti... | ostd/src/mm/dma/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::vec;
use crate::{
mm::{
FrameAllocOptions, HasPaddr, PAGE_SIZE, VmReader, VmWriter,
dma::*,
io::{VmIo, VmIoOnce},
io_util::HasVmReaderWriter,
},
prelude::*,
};
mod dma_coherent {
use super::*;
#[ktest]
fn alloc_wi... | ostd/src/mm/dma/test.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::ops::Range;
use crate::{
Error,
arch::iommu::{self, has_dma_remapping},
cpu::{AtomicCpuSet, CpuSet},
impl_frame_meta_for,
mm::{
CachePolicy, Daddr, FrameAllocOptions, HasPaddr, HasSize, PAGE_SIZE, Paddr, PageFlags,
PageProperty, Privile... | ostd/src/mm/dma/util.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The physical memory allocator.
use core::{alloc::Layout, ops::Range};
use align_ext::AlignExt;
use super::{Frame, meta::AnyFrameMeta, segment::Segment};
use crate::{
boot::memory_region::MemoryRegionType,
error::Error,
impl_frame_meta_for,
mm::{PAGE_SIZE, Padd... | ostd/src/mm/frame/allocator.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::{marker::PhantomData, mem::ManuallyDrop, ops::Deref, ptr::NonNull};
use super::{
Frame,
meta::{AnyFrameMeta, MetaSlot},
};
use crate::{mm::Paddr, sync::non_null::NonNullPtr};
/// A struct that can work as `&'a Frame<M>`.
#[derive(Debug)]
pub struct FrameRef<'a, M... | ostd/src/mm/frame/frame_ref.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Enabling linked lists of frames without heap allocation.
//!
//! This module leverages the customizability of the metadata system (see
//! [super::meta]) to allow any type of frame to be used in a linked list.
use core::{
ops::{Deref, DerefMut},
ptr::NonNull,
sync::... | ostd/src/mm/frame/linked_list.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Metadata management of frames.
//!
//! You can picture a globally shared, static, gigantic array of metadata
//! initialized for each frame.
//! Each entry in this array holds the metadata for a single frame.
//! There would be a dedicated small
//! "heap" space in each slot for... | ostd/src/mm/frame/meta.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Frame (physical memory page) management.
//!
//! A frame is an aligned, contiguous range of bytes in physical memory. The
//! sizes of base frames and huge frames (that are mapped as "huge pages") are
//! architecture-dependent. A frame can be mapped to virtual address spaces
//... | ostd/src/mm/frame/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! A contiguous range of frames.
use core::{fmt::Debug, mem::ManuallyDrop, ops::Range};
use super::{
Frame, inc_frame_ref_count,
meta::{AnyFrameMeta, GetFrameError},
};
use crate::mm::{AnyUFrameMeta, HasPaddr, HasSize, PAGE_SIZE, Paddr, Split};
/// A contiguous range of ... | ostd/src/mm/frame/segment.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use super::{allocator::FrameAllocOptions, *};
use crate::{
impl_frame_meta_for, impl_untyped_frame_meta_for,
mm::{HasPaddrRange, Split, io_util::HasVmReaderWriter},
prelude::*,
};
/// Typed mock metadata struct for testing
#[derive(Debug, Default)]
struct MockFrameMeta ... | ostd/src/mm/frame/test.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The unique frame pointer that is not shared with others.
use core::{marker::PhantomData, mem::ManuallyDrop, sync::atomic::Ordering};
use super::{
AnyFrameMeta, Frame, MetaSlot,
meta::{GetFrameError, REF_COUNT_UNIQUE},
};
use crate::mm::{HasPaddr, HasSize, PAGE_SIZE, Pa... | ostd/src/mm/frame/unique.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Untyped physical memory management.
//!
//! As detailed in [`crate::mm::frame`], untyped memory can be accessed with
//! relaxed rules but we cannot create references to them. This module provides
//! the declaration of untyped frames and segments, and the implementation of
//! ... | ostd/src/mm/frame/untyped.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Manages the kernel heap using slab or buddy allocation strategies.
use core::{
alloc::{AllocError, GlobalAlloc, Layout},
ptr::NonNull,
};
use crate::mm::Vaddr;
mod slab;
mod slot;
mod slot_list;
pub use self::{
slab::{Slab, SlabMeta},
slot::{HeapSlot, SlotInf... | ostd/src/mm/heap/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Slabs for implementing the slab allocator.
use core::{alloc::AllocError, ptr::NonNull};
use super::{slot::HeapSlot, slot_list::SlabSlotList};
use crate::mm::{
FrameAllocOptions, HasPaddr, HasSize, PAGE_SIZE, UniqueFrame,
frame::{linked_list::Link, meta::AnyFrameMeta},
... | ostd/src/mm/heap/slab.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Heap slots for allocations.
use core::{alloc::AllocError, ptr::NonNull};
use crate::{
impl_frame_meta_for,
mm::{
FrameAllocOptions, PAGE_SIZE, Paddr, Segment, Vaddr, kspace::LINEAR_MAPPING_BASE_VADDR,
paddr_to_vaddr,
},
};
/// A slot that will beco... | ostd/src/mm/heap/slot.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Implementation of the free heap slot list.
use core::ptr::NonNull;
use super::HeapSlot;
/// A singly-linked list of [`HeapSlot`]s from [`super::Slab`]s.
///
/// The slots inside this list will have a size of `SLOT_SIZE`. They can come
/// from different slabs.
#[derive(Debug)... | ostd/src/mm/heap/slot_list.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Kernel virtual memory allocation
use core::ops::Range;
use super::{KERNEL_PAGE_TABLE, VMALLOC_VADDR_RANGE};
use crate::{
mm::{
HasSize, PAGE_SIZE, Paddr, Split, Vaddr,
frame::{Frame, meta::AnyFrameMeta},
kspace::{KernelPtConfig, MappedItem},
... | ostd/src/mm/kspace/kvirt_area.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Kernel memory space management.
//!
//! The kernel memory space is currently managed as follows, if the
//! address width is 48 bits (with 47 bits kernel space).
//!
//! TODO: the cap of linear mapping (the start of vm alloc) are raised
//! to workaround for high IO in TDX. We n... | ostd/src/mm/kspace/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use crate::{
mm::{
Frame, FrameAllocOptions, PAGE_SIZE, Paddr,
frame::max_paddr,
kspace::{
LINEAR_MAPPING_BASE_VADDR, MappedItem, VMALLOC_VADDR_RANGE, kvirt_area::KVirtArea,
paddr_to_vaddr,
},
page_prop::{CachePolic... | ostd/src/mm/kspace/test.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Because that the page table implementation requires metadata initialized
//! and mapped, the boot page table is needed to do early stage page table setup
//! in order to initialize the running phase page tables.
use core::{
alloc::Layout,
result::Result,
sync::atomi... | ostd/src/mm/page_table/boot_pt.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
#![cfg_attr(
any(target_arch = "riscv64", target_arch = "loongarch64"),
expect(dead_code)
)]
use core::{
fmt::Debug,
intrinsics::transmute_unchecked,
ops::{Range, RangeInclusive},
sync::atomic::{AtomicUsize, Ordering},
};
use ostd_pod::Pod;
use super::{
... | ostd/src/mm/page_table/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use ostd_pod::FromZeros;
use super::*;
use crate::{
mm::{
FrameAllocOptions, MAX_USERSPACE_VADDR, PAGE_SIZE,
kspace::{KernelPtConfig, LINEAR_MAPPING_BASE_VADDR},
page_prop::{CachePolicy, PageFlags},
vm_space::VmItem,
},
prelude::*,
ta... | ostd/src/mm/page_table/test.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Implementation of the locking protocol.
use core::{marker::PhantomData, mem::ManuallyDrop, ops::Range, sync::atomic::Ordering};
use align_ext::AlignExt;
use super::Cursor;
use crate::{
mm::{
HasPaddr, Vaddr, nr_subpage_per_huge, paddr_to_vaddr,
page_table:... | ostd/src/mm/page_table/cursor/locking.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! The page table cursor for mapping and querying over the page table.
//!
//! # The page table lock protocol
//!
//! We provide a fine-grained ranged mutual-exclusive lock protocol to allow
//! concurrent accesses to non-overlapping virtual ranges in the page table.
//!
//! [`Curs... | ostd/src/mm/page_table/cursor/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! This module specifies the type of the children of a page table node.
use core::mem::ManuallyDrop;
use ostd_pod::FromZeros;
use super::{PageTableNode, PageTableNodeRef, PteTrait};
use crate::{
mm::{
HasPaddr, Paddr, PageTableFlags, PagingLevel,
page_prop::P... | ostd/src/mm/page_table/node/child.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! This module provides accessors to the page table entries in a node.
use super::{Child, ChildRef, PageTableGuard, PageTableNode, PteTrait};
use crate::{
mm::{
HasPaddr, nr_subpage_per_huge,
page_prop::PageProperty,
page_size,
page_table::{Page... | ostd/src/mm/page_table/node/entry.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! This module defines page table node abstractions and the handle.
//!
//! The page table node is also frequently referred to as a page table in many architectural
//! documentations. It is essentially a page that contains page table entries (PTEs) that map
//! to child page table... | ostd/src/mm/page_table/node/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use crate::{
irq::{DisabledLocalIrqGuard, disable_local},
task::{DisabledPreemptGuard, atomic_mode::AsAtomicModeGuard, disable_preempt},
};
/// A guardian that denotes the guard behavior for holding a spin-based lock.
///
/// It at least ensures that the atomic mode is main... | ostd/src/sync/guard.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Useful synchronization primitives.
mod guard;
mod mutex;
mod rcu;
mod rwarc;
mod rwlock;
mod rwmutex;
mod spin;
mod wait;
pub(crate) use self::rcu::finish_grace_period;
pub use self::{
guard::{GuardTransfer, LocalIrqDisabled, PreemptDisabled, SpinGuardian, WriteIrqDisabled... | ostd/src/sync/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::{
cell::UnsafeCell,
fmt,
ops::{Deref, DerefMut},
sync::atomic::{AtomicBool, Ordering},
};
use super::WaitQueue;
/// A mutex with waitqueue.
pub struct Mutex<T: ?Sized> {
lock: AtomicBool,
queue: WaitQueue,
val: UnsafeCell<T>,
}
impl<T> Mutex<... | ostd/src/sync/mutex.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::sync::Arc;
use core::sync::atomic::{AtomicUsize, Ordering, fence};
use super::{PreemptDisabled, RwLock, RwLockReadGuard, RwLockWriteGuard};
/// A reference-counting pointer with read-write capabilities.
///
/// This is essentially `Arc<RwLock<T>>`, so it can provide rea... | ostd/src/sync/rwarc.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::{
cell::UnsafeCell,
fmt,
marker::PhantomData,
ops::{Deref, DerefMut},
sync::atomic::{
AtomicUsize,
Ordering::{AcqRel, Acquire, Relaxed, Release},
},
};
use super::{
PreemptDisabled,
guard::{GuardTransfer, SpinGuardian},
};
u... | ostd/src/sync/rwlock.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::{
cell::UnsafeCell,
fmt,
ops::{Deref, DerefMut},
sync::atomic::{
AtomicUsize,
Ordering::{AcqRel, Acquire, Relaxed, Release},
},
};
use super::WaitQueue;
/// A mutex that provides data access to either one writer or many readers.
///
//... | ostd/src/sync/rwmutex.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use core::{
cell::UnsafeCell,
fmt,
marker::PhantomData,
ops::{Deref, DerefMut},
sync::atomic::{AtomicBool, Ordering},
};
use super::{LocalIrqDisabled, PreemptDisabled, guard::SpinGuardian};
use crate::task::atomic_mode::AsAtomicModeGuard;
/// A spin lock.
///
/... | ostd/src/sync/spin.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::{collections::VecDeque, sync::Arc};
use core::sync::atomic::{AtomicBool, AtomicU32, Ordering};
use super::{LocalIrqDisabled, SpinLock};
use crate::task::{Task, scheduler};
// # Explanation on the memory orders
//
// ```
// [CPU 1 (the waker)] [CPU 2 (the waiter)]
//... | ostd/src/sync/wait.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
//! Read-copy update (RCU).
use core::{
marker::PhantomData,
mem::ManuallyDrop,
ops::Deref,
ptr::NonNull,
sync::atomic::{
AtomicPtr,
Ordering::{AcqRel, Acquire},
},
};
use non_null::NonNullPtr;
use spin::once::Once;
use self::monitor::RcuMo... | ostd/src/sync/rcu/mod.rs | null | null | null | null | null |
source | asterinas | // SPDX-License-Identifier: MPL-2.0
use alloc::collections::VecDeque;
use core::sync::atomic::{
AtomicBool,
Ordering::{self, Relaxed},
};
use crate::{
cpu::{AtomicCpuSet, CpuId, CpuSet, PinCurrentCpu},
prelude::*,
sync::SpinLock,
task::atomic_mode::AsAtomicModeGuard,
};
/// A RCU monitor ensu... | ostd/src/sync/rcu/monitor.rs | null | null | null | null | null |
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