text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
int status; //status of the last command
size_t reports_len;
esp_hidh_dev_report_t *reports;
void *tmp;
size_t tmp_len;
SemaphoreHandle_t semaphore;
SemaphoreHandle_t mutex;
esp_err_t (*... | 3,452 |
/*
*/
#pragma once
#include "esp_hidh.h"
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_GATTC_ENABLE || CONFIG_BT_NIMBLE_ENABLED
esp_err_t esp_ble_hidh_init(const esp_hidh_config_t *config);
esp_err_t esp_ble_hidh_deinit(void);
#if CONFIG_BT_NIMBLE_ENABLED
esp_hidh_dev_t *esp_ble_hidh_dev_open(uint8_t *bda, u... | 3,454 |
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 3,455 |
/*
*/
#pragma once
#include "esp_hidd.h"
#include "esp_err.h"
#include "esp_hid_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_GATTS_ENABLE || CONFIG_BT_NIMBLE_ENABLED
esp_err_t esp_ble_hidd_dev_init(esp_hidd_dev_t *dev, const esp_hid_device_config_t *config, esp_event_handler_t callback);
#endif /*... | 3,456 |
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 3,457 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/gpio_types.h"
#include "hal/rtc_io_ll.h"
#define RTCIO_OUTPUT_NORMAL _Pragma ("GCC warning \"'RTCIO_OUTPUT_NORMAL' macro is deprecated\"") RTCIO_LL_OUTPUT_NORMAL
#define RTCIO_OUTPUT_OD _Pragma ("GCC warning \"'RTCIO_OUTPUT_OD' macro is de... | 3,458 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
/**
*/
void ulp_lp_core_update_wakeup_cause(void);
/**
*/
uint32_t ulp_lp_core_get_wakeup_cause(void);
/**
*/
void ulp_lp_core_wakeup_main_processor(void);
/**
*/
void ulp_lp_core_delay_us(uint32_t us);
/**
*/
void ulp_lp_core_d... | 3,459 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/i2c_types.h"
#include "esp_err.h"
/**
*/
esp_err_t lp_core_i2c_master_read_from_device(i2c_port_t lp_i2c_num, uint16_t device_addr,
uint8_t *data_rd, size_t size,
... | 3,460 |
/*
*/
/**
void lp_core_printf(const char* format, ...);
| 3,461 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include "esp_err.h"
#include "hal/uart_types.h"
/**
*/
int lp_core_uart_tx_chars(uart_port_t lp_uart_num, const void *src, size_t size);
/**
*/
esp_err_t lp_core_uart_write_bytes(uart_port_t lp_uart_num, const void *src, size_t size, int32_t t... | 3,462 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include "esp_err.h"
#include "hal/uart_types.h"
#include "hal/gpio_types.h"
/**
*/
typedef struct {
gpio_num_t tx_io_num; /*!< GPIO pin for UART Tx signal. Only GPIO#5 can be used as the UART Tx pin */
gpio_num_t rx_io_num;... | 3,463 |
< LP UART HW flow control mode (cts/rts) */
uint8_t rx_flow_ctrl_thresh; /*!< LP UART HW RTS threshold */
} lp_core_uart_proto_cfg_t;
/**
*/
typedef struct {
lp_core_uart_pin_cfg_t uart_pin_cfg; /*!< LP UART pin configuration */
lp_core_uart_proto_cfg_t uart_proto_cfg; /*!< LP UART protoc... | 3,463 |
parity = UART_PARITY_DISABLE, \
.uart_proto_cfg.stop_bits = UART_STOP_BITS_1, \
.uart_proto_cfg.flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \
.uart_proto_cfg.rx_flow_ctrl_thresh = 0, \
/* Default LP UART source clock config */
#define LP_UART_DEFAULT_CLOCK_CON... | 3,463 |
/*
*/
#pragma once
#include
#include
#include
#include
#include "esp_err.h"
#include "ulp_common.h"
#include "esp_rom_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup)
#define ULP_LP_CORE_WAKEUP_SOURCE_LP_UART BIT(1) // En... | 3,464 |
g. of UART */
#endif //ESP_ROM_HAS_LP_ROM
} ulp_lp_core_cfg_t;
/**
*/
esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg);
/**
*/
esp_err_t ulp_lp_core_load_binary(const uint8_t* program_binary, size_t program_size_bytes);
/**
*/
void ulp_lp_core_stop(void);
#ifdef __cplusplus
}
#endif
| 3,464 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/i2c_types.h"
#include "hal/gpio_types.h"
#include "esp_err.h"
/**
*/
typedef struct {
gpio_num_t sda_io_num; /*!< GPIO pin for SDA signal. Only GPIO#6 can be used as the SDA pin. */
gpio_num_t scl_io_num; ... | 3,465 |
< LP I2C source clock type */
} lp_core_i2c_cfg_t;
/* Default LP I2C GPIO settings */
#define LP_I2C_DEFAULT_GPIO_CONFIG() \
.i2c_pin_cfg.sda_io_num = GPIO_NUM_6, \
.i2c_pin_cfg.scl_io_num = GPIO_NUM_7, \
.i2c_pin_cfg.sda_pullup_en = true, \
.i2c_pin_cfg.scl_pullup_e... | 3,465 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint64_t sleep_duration_us; /* Configured sleep duration for periodic wakeup, if set the ulp will automatically schedule the next wakeup */
} ulp_lp_core_memory_shared_cfg_t;
/**
*/
ulp_lp_core_memory_shared_cfg_t* ulp_lp_co... | 3,466 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
uint64_t ulp_lp_core_lp_timer_get_cycle_count(void);
/**
*/
void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us);
/**
void ulp_lp_core_lp_timer_disable(void);
#ifdef __cplusplus
}
#endif
| 3,467 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/gpio_types.h"
#include "esp_err.h"
/**
*/
typedef struct {
uint32_t sda_io_num; /*!< GPIO pin for SDA signal. Only GPIO#1 or GPIO#3 can be used as the SDA pin. */
uint32_t scl_io_num; /*!< GPIO pin for SCL ... | 3,468 |
< Waiting time before the END condition in micro seconds */
float i2c_trans_timeout; /*!< I2C transaction timeout in micro seconds */
} ulp_riscv_i2c_timing_cfg_t;
/**
*/
typedef struct {
ulp_riscv_i2c_pin_cfg_t i2c_pin_cfg; /*!< RTC I2C pin configuration */
ulp_riscv_i2c_timing_cfg_t i2c_timing_cf... | 3,468 |
scl_start_period = 2, \
.i2c_timing_cfg.scl_stop_period = 1.3, \
.i2c_timing_cfg.i2c_trans_timeout = 20,
#elif CONFIG_IDF_TARGET_ESP32S2
/* Nominal I2C bus timing parameters for I2C fast mode. Max SCL freq on S2 is about 233 KHz due to timing constraints. */
#define ULP_RISCV_I2C_FAST_MODE_CONFIG() ... | 3,468 |
i2c_timing_cfg.i2c_trans_timeout = 20, \
/* Default RTC I2C configuration settings. Uses I2C fast mode. */
//TODO: Move to smaller units of time in the future like nano seconds to avoid floating point operations.
#define ULP_RISCV_I2C_DEFAULT_CONFIG() \
{ \
... | 3,468 |
/*
*/
#pragma once
#include
#include
#include
#include "esp_err.h"
#include "ulp_common.h"
#include "esp_intr_alloc.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ULP_RISCV_WAKEUP_SOURCE_TIMER,
ULP_RISCV_WAKEUP_SOURCE_GPIO,
} ulp_riscv_wakeup_source_t;
/**
typedef struct {
ulp_riscv_wakeup... | 3,469 |
"
#endif /* (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3) */
/**
*/
esp_err_t ulp_riscv_isr_register(intr_handler_t fn, void *arg, uint32_t mask);
/**
*/
esp_err_t ulp_riscv_isr_deregister(intr_handler_t fn, void *arg, uint32_t mask);
/**
*/
esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg);
/*... | 3,469 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "ulp_riscv_lock_shared.h"
/**
/**
*/
void ulp_riscv_lock_acquire(ulp_riscv_lock_t *lock);
/**
*/
void ulp_riscv_lock_release(ulp_riscv_lock_t *lock);
#ifdef __cplusplus
}
#endif
| 3,470 |
/*
*/
#pragma once
#include "hal/adc_types.h"
#include "esp_err.h"
#include "ulp_adc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Kept for backwards compatibilty */
#define ulp_riscv_adc_cfg_t ulp_adc_cfg_t
#define ulp_riscv_adc_init ulp_adc_init
#ifdef __cplusplus
}
#endif
| 3,471 |
/*
*/
#pragma once
#warning ulp_riscv_register_ops.h has been moved. Please include the file without the ulp_riscv prefix.
#include "../../ulp_core/include/ulp_riscv_register_ops.h"
| 3,472 |
/*
*/
#pragma once
#warning Contents of ulp_riscv/ulp_riscv.h have been deprecated. Please include the header which contains the actual definitions you are trying to use, e.g. "ulp_riscv_register_ops.h".
#include "../../ulp_core/include/ulp_riscv_register_ops.h"
| 3,473 |
/*
*/
#pragma once
#warning "ulp_riscv_gpio.h has been moved. Please include the file without the ulp_riscv prefix."
#include "../../ulp_core/include/ulp_riscv_gpio.h"
| 3,474 |
/*
*/
#pragma once
#warning ulp_riscv_utils.h has been moved. Please include the file without the ulp_riscv prefix.
#include "../../ulp_core/include/ulp_riscv_utils.h"
| 3,475 |
/*
*/
#pragma once
#warning Contents of esp32s2/ulp_riscv.h have been merged with ulp_riscv.h. Please include the later to avoid the warning.
#include "../ulp_riscv.h"
| 3,476 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef enum {
ULP_RISCV_LOCK_TURN_ULP, /*!< ULP's turn to enter the critical section */
ULP_RISCV_LOCK_TURN_MAIN_CPU, /*!< Main CPU's turn to enter the critical section */
} ulp_riscv_lock_turn_t;
/**
typedef struct {
vol... | 3,477 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
//Registers Operation {{
/*
*/
#define WRITE_RTC_MEM(addr, val) (*((volatile int*)(addr))) = (int) (val)
#define READ_RTC_MEM(addr) (*(volatile int*)(addr))
/*
*/
#define RISCV_REG_CONV(addr) (((addr&0xffff)> (_f##_S)) & (_f##_V)); ... | 3,478 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/* Underlying driver function for printing a char, e.g. over UART */
typedef void (*putc_fn_t)(const void *ctx, const char c);
/**
*/
void ulp_riscv_print_install(putc_fn_t putc, void *putc_ctx);
/**
*/
void ulp_riscv_print_str(const char *str);
/**
*/... | 3,479 |
/*
*/
#pragma once
#include "ulp_riscv_lock_shared.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
/**
*/
void ulp_riscv_lock_acquire(ulp_riscv_lock_t *lock);
/**
*/
void ulp_riscv_lock_release(ulp_riscv_lock_t *lock);
#ifdef __cplusplus
}
#endif
| 3,480 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
/**
*/
void ulp_riscv_i2c_master_set_slave_addr(uint8_t slave_addr);
/**
*/
void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr);
/**
*/
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
/**... | 3,481 |
/*
*/
#pragma once
#include "esp_err.h"
#include "ulp_riscv_register_ops.h"
#include "hal/touch_sensor_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
esp_err_t ulp_riscv_touch_pad_read_raw_data(touch_pad_t touch_num, uint32_t *raw_data);
/**
*/
esp_err_t ulp_riscv_touch_pad_read_benchmark(touch_pad_t to... | 3,482 |
/*
*/
#pragma once
#include "ulp_riscv_register_ops.h"
#include "hal/adc_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
int32_t ulp_riscv_adc_read_channel(adc_unit_t adc_n, int channel);
#ifdef __cplusplus
}
#endif
| 3,483 |
/*
*/
#pragma once
#include "ulp_riscv_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
typedef struct {
gpio_num_t tx_pin; // TX pin number
} ulp_riscv_uart_cfg_t; // Config for the driver
typedef struct {
uint32_t bit_duration_cycles; // Number of cycles to hold the line for each bit
gpio_num_t tx_pi... | 3,484 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "sdkconfig.h"
#include "soc/rtc_io_reg.h"
#include "soc/sens_reg.h"
#include "ulp_riscv_register_ops.h"
#include "ulp_riscv_interrupt.h"
typedef enum {
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, inpu... | 3,485 |
< GPIO14, input and output */
GPIO_NUM_15 = 15, /*!< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
G... | 3,485 |
< RTC GPIO interrupt type : input high level trigger */
ULP_RISCV_GPIO_INTR_MAX
} ulp_riscv_gpio_int_type_t;
typedef enum {
RTCIO_MODE_OUTPUT = 0,
RTCIO_MODE_OUTPUT_OD = 1,
} rtc_io_out_mode_t;
static inline void ulp_riscv_gpio_init(gpio_num_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32S2
SET_PERI_REG... | 3,485 |
1 : 0);
}
static inline void ulp_riscv_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode)
{
REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_DRV, mode);
}
static inline void ulp_riscv_gpio_pullup(gpio_num_t gpio_num)
{
SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4... | 3,485 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "sdkconfig.h"
#include
#include "ulp_riscv_register_ops.h"
#include "ulp_riscv_interrupt.h"
/**
*/
void ulp_riscv_wakeup_main_processor(void);
/**
*/
void ulp_riscv_rescue_from_monitor(void);
/**
void __attribute__((__noreturn__)) ulp_riscv_ha... | 3,486 |
word 0x0602e00b" \
); \
/**
*/
#define ULP_RISCV_EXIT_CRITICAL() asm volatile (".word 0x0600600b");
#else /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */
#define ULP_RISCV_ENTER_CRITICAL()
#define ULP_RISCV_EXIT_CRITICAL()
#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */
#ifdef _... | 3,486 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
/* Define encoding for all general purpose RISC-V registers */
#define regnum_zero 0
#define regnum_ra 1
#define regnum_sp 2
#define regnum_gp 3
#define regnum_tp 4
#define regnum_t0 5
#define regnum_t1 6
#define regnum_t2 7
#define re... | 3,487 |
word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
/**
*/
#define getq_insn(_rd, _qs) \
r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
/**
*/
#define setq_insn(_qd, _rs) \
r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd,... | 3,487 |
/*
*/
#pragma once
#include
#include "esp_err.h"
#include "riscv/interrupt.h"
#ifdef __cplusplus
extern "C"
{
#endif
#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE
/* ULP RISC-V Interrupt sources */
typedef enum {
ULP_RISCV_SW_INTR_SOURCE = 0, /**< Interrupt triggered by SW */
ULP_RISCV_RTCIO0_INTR_SOURC... | 3,488 |
/*
*/
#pragma once
#define XOR_MASK 0xDEADBEEF
/* I2C test params */
#define I2C_SLAVE_ADDRESS 0x28
#define DATA_LENGTH 200
#define RW_TEST_LENGTH 129 /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
typedef enum {
LP_CORE_READ_WRITE_TEST = 1,
LP_CORE_DELAY_TEST,
LP_CORE_DEEP_SLEEP_WA... | 3,489 |
/*
*/
#pragma once
#define MUTEX_TEST_ITERATIONS 100000
#define XOR_MASK 0xDEADBEEF
/* I2C test params */
#define I2C_SLAVE_ADDRESS 0x28
#define DATA_LENGTH 200
// TODO: Updated the test to perform multi-byte read/write (IDFGH-11056)
#define RW_TEST_LENGTH 1 /*!<Data length for r/w test, any value from 0-DATA... | 3,490 |
/*
*/
#pragma once
/* This file contains definitions that are common between esp32/ulp.h,
esp32s2/ulp.h and esp32s3/ulp.h
*/
#include "esp_intr_alloc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**@{*/
#define ESP_ERR_ULP_BASE 0x1200 /*!< Offset for ULP-related error codes */
#defi... | 3,491 |
h header
typedef union ulp_insn ulp_insn_t;
/**
*/
esp_err_t ulp_isr_register(intr_handler_t fn, void *arg);
/**
*/
esp_err_t ulp_isr_deregister(intr_handler_t fn, void *arg);
/**
*/
esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* program, size_t* psize);
/**
*/
esp_err_t ulp_load_b... | 3,491 |
/*
*/
#pragma once
#include
#include
#include
#include "esp_err.h"
#include "ulp_common.h"
#include "ulp_fsm_common.h"
#include "soc/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define R0 0 /*!= */
#define JUMPS_LE 2 /*! */
uint32_t label : 16; /*!= 0) ? 0 : 1, \
... | 3,492 |
sub_opcode = SUB_OPCODE_BX, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_BXZR(reg_pc) { .bx = { \
.dreg = reg_pc, \
.addr = 0, \
.unused = 0, \
.reg = 1, \
.type = BX_JUMP_TYPE_ZERO, \
.sub_opcode = SUB_OPCODE_BX, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_BXZI(imm_pc) { .bx = ... | 3,492 |
dreg = reg_dest, \
.sreg = reg_src1, \
.treg = reg_src2, \
.unused = 0, \
.sel = ALU_SEL_ADD, \
.sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \
.dreg = reg_dest, \
.sreg = reg_src1, \
.treg = reg_src2... | 3,492 |
dreg = reg_dest, \
.sreg = reg_src, \
.treg = 0, \
.unused = 0, \
.sel = ALU_SEL_MOV, \
.sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \
.dreg = reg_dest, \
.sreg = reg_src, \
.treg = reg_shift, \
... | 3,492 |
sreg = reg_src, \
.imm = imm_, \
.unused = 0, \
.sel = ALU_SEL_AND, \
.sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_ORI(reg_dest, reg_src, imm_) { .alu_imm = { \
.dreg = reg_dest, \
.sreg = reg_src, \
.imm = imm_, \
.unused = 0, \
.sel = ALU_SEL_... | 3,492 |
opcode = OPCODE_MACRO } }
/**
*/
#define M_BRANCH(label_num) { .macro = { \
.dreg = 0, \
.label = label_num, \
.unused = 0, \
.sub_opcode = SUB_OPCODE_MACRO_BRANCH, \
.opcode = OPCODE_MACRO } }
/**
*/
#define M_LABELPC(label_num) { .macro = { \
.dreg = 0, \
.label = label_num, \
.unu... | 3,492 |
imm = imm_, \
.unused2 = 0, \
.sel = ALU_SEL_SINC, \
.sub_opcode = SUB_OPCODE_ALU_CNT, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_STAGE_DEC(imm_) { .alu_reg_s = { \
.unused1 = 0, \
.imm = imm_, \
.unused2 = 0, \
.sel = ALU_SEL_SDEC, \
.sub_opcode = SUB_OPCODE_ALU_CNT, \
.opcod... | 3,492 |
sub_opcode = SUB_OPCODE_BS, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_I2C_RW(sub_addr, val, low_bit, high_bit, slave_sel, rw_bit) { .i2c = {\
.i2c_addr = sub_addr, \
.data = val, \
.low_bits = low_bit, \
.high_bits = high_bit, \
.i2c_sel = slave_sel, \
.unused ... | 3,492 |
/*
*/
#pragma once
#include
#include
#include
#include "esp_err.h"
#include "ulp_common.h"
#include "ulp_fsm_common.h"
#include "soc/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define R0 0 /*!= 0) ? 0 : 1, \
.sub_opcode = SUB_OPCODE_B, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_... | 3,493 |
bx = { \
.dreg = 0, \
.addr = imm_pc, \
.unused1 = 0, \
.reg = 0, \
.type = BX_JUMP_TYPE_DIRECT, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_BX, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_BXZR(reg_pc) { .bx = { \
.dreg = reg_pc, \
.addr = 0, \
.unused1 = 0, \
.reg = ... | 3,493 |
unused1 = 0, \
.reg = 0, \
.type = BX_JUMP_TYPE_OVF, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_BX, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_BSLE(pc_offset, imm_value) { .b = { \
.imm = imm_value, \
.cmp = BS_CMP_LE, \
.offset = abs(pc_offset), \
.sign = (pc_offset >= 0) ? 0 ... | 3,493 |
treg = reg_src2, \
.unused1 = 0, \
.sel = ALU_SEL_ADD, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \
.dreg = reg_dest, \
.sreg = reg_src1, \
.treg = reg_src2, \
.unused1 = 0, \
... | 3,493 |
alu_reg = { \
.dreg = reg_dest, \
.sreg = reg_src, \
.treg = 0, \
.unused1 = 0, \
.sel = ALU_SEL_MOV, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \
.dreg = reg_dest, \
.sreg =... | 3,493 |
opcode = OPCODE_ALU } }
/**
*/
#define I_ANDI(reg_dest, reg_src, imm_) { .alu_imm = { \
.dreg = reg_dest, \
.sreg = reg_src, \
.imm = imm_, \
.unused1 = 0, \
.sel = ALU_SEL_AND, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_ORI(reg_de... | 3,493 |
sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_STAGE_INC(reg_dest, reg_src, imm_) { .alu_cnt = { \
.unused1 = 0, \
.imm = imm_, \
.unused2 = 0, \
.sel = ALU_SEL_STAGE_INC, \
.unused3 = 0, \
.sub_opcode = SUB_OPCODE_ALU_CNT, \
.opcode = OPCODE_ALU } }
/**
... | 3,493 |
macro = { \
.label = label_num, \
.unused = 0, \
.sub_opcode = SUB_OPCODE_MACRO_BRANCH, \
.opcode = OPCODE_MACRO } }
/**
*/
#define M_BL(label_num, imm_value) \
M_BRANCH(label_num), \
I_BL(0, imm_value)
/**
*/
#define M_BG(label_num, imm_value) \
M_BRANCH(label_num), \
I_BG(0, imm_va... | 3,493 |
/*
*/
#pragma once
#include
#include
#include
#include "esp_err.h"
#include "ulp_common.h"
#include "ulp_fsm_common.h"
#include "soc/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define R0 0 /*!= 0) ? 0 : 1, \
.sub_opcode = SUB_OPCODE_B, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_... | 3,494 |
bx = { \
.dreg = 0, \
.addr = imm_pc, \
.unused1 = 0, \
.reg = 0, \
.type = BX_JUMP_TYPE_DIRECT, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_BX, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_BXZR(reg_pc) { .bx = { \
.dreg = reg_pc, \
.addr = 0, \
.unused1 = 0, \
.reg = ... | 3,494 |
unused1 = 0, \
.reg = 0, \
.type = BX_JUMP_TYPE_OVF, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_BX, \
.opcode = OPCODE_BRANCH } }
/**
*/
#define I_BSLE(pc_offset, imm_value) { .b = { \
.imm = imm_value, \
.cmp = BS_CMP_LE, \
.offset = abs(pc_offset), \
.sign = (pc_offset >= 0) ? 0 ... | 3,494 |
treg = reg_src2, \
.unused1 = 0, \
.sel = ALU_SEL_ADD, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \
.dreg = reg_dest, \
.sreg = reg_src1, \
.treg = reg_src2, \
.unused1 = 0, \
... | 3,494 |
alu_reg = { \
.dreg = reg_dest, \
.sreg = reg_src, \
.treg = 0, \
.unused1 = 0, \
.sel = ALU_SEL_MOV, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \
.dreg = reg_dest, \
.sreg =... | 3,494 |
opcode = OPCODE_ALU } }
/**
*/
#define I_ANDI(reg_dest, reg_src, imm_) { .alu_imm = { \
.dreg = reg_dest, \
.sreg = reg_src, \
.imm = imm_, \
.unused1 = 0, \
.sel = ALU_SEL_AND, \
.unused2 = 0, \
.sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_ORI(reg_de... | 3,494 |
sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } }
/**
*/
#define I_STAGE_INC(reg_dest, reg_src, imm_) { .alu_cnt = { \
.unused1 = 0, \
.imm = imm_, \
.unused2 = 0, \
.sel = ALU_SEL_STAGE_INC, \
.unused3 = 0, \
.sub_opcode = SUB_OPCODE_ALU_CNT, \
.opcode = OPCODE_ALU } }
/**
... | 3,494 |
macro = { \
.label = label_num, \
.unused = 0, \
.sub_opcode = SUB_OPCODE_MACRO_BRANCH, \
.opcode = OPCODE_MACRO } }
/**
*/
#define M_BL(label_num, imm_value) \
M_BRANCH(label_num), \
I_BL(0, imm_value)
/**
*/
#define M_BG(label_num, imm_value) \
M_BRANCH(label_num), \
I_BG(0, imm_va... | 3,494 |
/*
*/
#ifndef __ULP_COMMON_H__
#define __ULP_COMMON_H__
#ifdef __cplusplus
extern "C" {
#endif
#include
#include "esp_err.h"
#include "ulp_common_defs.h"
/**
*/
esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us);
/**
*/
void ulp_timer_stop(void);
/**
void ulp_timer_resume(void);
#ifdef _... | 3,495 |
/*
*/
#pragma once
#include "hal/adc_types.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
adc_unit_t adc_n; // ADC Unit
adc_channel_t channel; // ADC channel
adc_atten_t atten; // ADC channel attenuation
adc_bitwidth_t width; // ADC bit width, only... | 3,496 |
/*
*/
#ifndef __ULP_COMMON_DEFS_H__
#define __ULP_COMMON_DEFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */
#ifdef __cplusplus
}
#endif
#endif // __ULP_COMMON_DEFS_H__
| 3,497 |
/*
*/
#ifndef __ULP_COMMON_DEFS_H__
#define __ULP_COMMON_DEFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< LP memory, 16k size */
#ifdef __cplusplus
}
#endif
#endif // __ULP_COMMON_DEFS_H__
| 3,498 |
/*
*/
#ifndef __ULP_COMMON_DEFS_H__
#define __ULP_COMMON_DEFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */
#ifdef __cplusplus
}
#endif
#endif // __ULP_COMMON_DEFS_H__
| 3,499 |
/*
*/
#ifndef __ULP_COMMON_DEFS_H__
#define __ULP_COMMON_DEFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */
#ifdef __cplusplus
}
#endif
#endif // __ULP_COMMON_DEFS_H__
| 3,500 |
/*
*/
#ifndef __ULP_COMMON_DEFS_H__
#define __ULP_COMMON_DEFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RTC_SLOW_MEM (0x50108000) /*!< LP memory, 32k size */
#ifdef __cplusplus
}
#endif
#endif // __ULP_COMMON_DEFS_H__
| 3,501 |
/*
*/
#pragma once
#include
#include
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define RV_EXTERNAL_INT_COUNT 32
#define RV_EXTERNAL_INT_OFFSET 16
FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)
{
assert(rv_int_num < RV_EXTERNAL_INT_COUNT && "Invalid CPU interr... | 3,502 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
/* Need a way to signal which core caused the INT WDT like we do with EXCAUSE on xtensa.
Choosing a large number that is unlikely to conflict with any actual riscv mcauses
bit 12 and above are always zero on the CPU used by P4
*/
#define PANIC_RSN_INTWDT_CPU0 ETS_I... | 3,503 |
/*
*/
#pragma once
/**
*/
#define VECTORS_MCAUSE_INTBIT_MASK (0x80000000)
#if SOC_INT_CLIC_SUPPORTED
/* When using the CLIC as their interrupt controller, the `mcause` register contains more information than
*/
#define VECTORS_MCAUSE_REASON_MASK (0x00000fff)
#else // !if SOC_INT_CLIC_SUPPORTED
/**
*/
#d... | 3,504 |
/*
*/
#pragma once
#include
#include
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define RV_EXTERNAL_INT_COUNT 32
#define RV_EXTERNAL_INT_OFFSET 0
FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)
{
assert(rv_int_num != 0 && "Invalid CPU interrupt number");
}
#if... | 3,505 |
/*
*/
#pragma once
#include
#include
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define RV_EXTERNAL_INT_COUNT 32
#define RV_EXTERNAL_INT_OFFSET 0
FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)
{
assert(rv_int_num != 0 && "Invalid CPU interrupt number");
}
#if... | 3,506 |
/*
*/
#pragma once
#include
#include "riscv/interrupt.h"
#ifdef __cplusplus
extern "C" {
#endif
/ Former API / Backport compatibility /
/**
*/
void esprv_intc_int_enable(uint32_t unmask) __attribute__((deprecated("please use esprv_int_enable instead")));
/**
*/
void esprv_intc_int_disable(uint32_t mask) _... | 3,507 |
// Copyright (c) 2013, The Regents of the University of California (Regents).
// Copyright (c) 2018-2019, The libfemto authors
// Copyright (c) 2020 Espressif Systems (Shanghai) PTE LTD
// All Rights Reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided... | 3,508 |
// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
// MAINTENANCE, SU... | 3,508 |
Note this macro is only needed for calculations like (CSR_PMPCFG0 + 1), which must
still be constant at compile time. Use the assembler name pmpcfg0, pmpcfg1, pmpcfg2, etc. in other cases */
#define CSR_PMPCFG0 0x3A0
/* Value of pmpaddr0 CSR. Note, as above, this macro is only needed for calculations and the assem... | 3,508 |
- ENTRY is number of the PMP entry to set. This must be a compile-time constant because it's used to
generate specific assembly instructions.
- ADDR is the address to write to the PMPADDRx register. Note this is the unshifted address.
- CFG is the configuration value to write to the correct CFG entry re... | 3,508 |
/* Copyright (c) 2010-2017, The Regents of the University of California
(Regents). All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
notice, this list of conditions and the following discla... | 3,509 |
THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*/
/* Adapted from https://github.com/riscv/riscv-opcodes/blob/master/encoding.h */
#pragma once
#define MSTAT... | 3,509 |
/*
*/
#ifndef __RVRUNTIME_FRAMES_H__
#define __RVRUNTIME_FRAMES_H__
#include "soc/soc_caps.h"
/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
#define ALIGNUP(n, val) (((val) + (n) - 1) & -(n))
#ifdef STRUCT_BEGIN
#undef STRUCT_BEGIN
#undef STRUCT_FIELD
#undef STRUCT_AFIELD
#undef STRUCT... | 3,510 |
space (size)*(n)
#define STRUCT_END(sname) sname##Size:; .popsection
#endif // __clang__
#else
#define STRUCT_BEGIN typedef struct {
#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
#define STRUCT_END(sname) } sname;
#... | 3,510 |
/*
*/
#ifndef __RVSLEEP_FRAMES_H__
#define __RVSLEEP_FRAMES_H__
#include "sdkconfig.h"
/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
#define ALIGNUP(n, val) (((val) + (n) - 1) & -(n))
#ifdef STRUCT_BEGIN
#undef STRUCT_BEGIN
#undef STRUCT_FIELD
#undef STRUCT_AFIELD
#undef STRUCT_END
#e... | 3,511 |
space (size)*(n)
#define STRUCT_END(sname) sname##Size:; .popsection
#endif // __clang__
#else
#define STRUCT_BEGIN typedef struct {
#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
#define STRUCT_END(sname) } sname;
#... | 3,511 |
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