text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
We can achieve atomicity by disabling interrupts
uint32_t intr_level;
__asm__ __volatile__ ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) "\n"
: "=r"(intr_level));
// Compare and set
uint32_t old_value;
old_value = *addr;
if (old_value == compare_value) {
*addr = new_val... | 112 |
/*
*/
/*
*/
/*
*/
#ifndef XTENSA_CONFIG_H
#define XTENSA_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include /* required for XSHAL_CLIB */
#include "xtensa_context.h"
/*
/* Extra space required for interrupt/exception hooks. */
#ifdef XT_INTEXC_HOOKS
#ifdef __XTENSA_CALL0_ABI__
... | 113 |
defined __ASSEMBLER__
#include
#define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16))
#define XT_CLIB_GLOBAL_PTR _reent_ptr
#define _REENT_INIT_PTR _init_reent
#define _impure_ptr _reent_ptr
void _reclaim_reent(void *... | 113 |
NOTE: This number can be adjusted to suit your needs. You must verify that the
amount of space you reserve is adequate for the worst-case conditions in your
application.
NOTE: The windowed ABI requires more stack, since space has to be reserved
for spilling register windows.
*/
#ifdef __XTENSA_CALL0_ABI__
... | 113 |
/*
*/
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */
/* Copyright (c) 2004-2008 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software wit... | 114 |
*/
#ifndef __H_LIBDB_MACROS
#define __H_LIBDB_MACROS
/*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef uint32
#define uint32 unsigned int
#endif
#ifndef int32
#define int32 int
#endif
/*
*/
#define XTENSA_DBREGN_INVALID -1 /* not a valid target number */
#define XTENSA_DBREGN_A(n) (0x0000+(n)) /* addr... | 114 |
.u3 */
#define XTENSA_DBREGN_VCOEFF(n) (0x005C+(n)) /* Vectra I vcoeff regs c0..c1 */
/* 0x005E..0x005F RESERVED for use by Tensilica */
#define XTENSA_DBREGN_AEP(n) (0x0060+(n)) /* HiFi2 Audio Engine regs aep0..aep7 */
#define XTENSA_DBREGN_AEQ(n) (0x0068+(n)) /* HiFi2 Audio Engine regs aeq0..aeq3 */
... | 114 |
.0xEFFF other states (and regfiles) */
#define XTENSA_DBREGN_DBAGENT(n) (0xF000+(n)) /* non-processor "registers" 0..4095 for
3rd-party debugger agent defined use */
/* > 0xFFFF (32-bit) RESERVED for use by Tensilica */
/*#define XTENSA_DBREGN_CONTEXT(n) (0x02000000+((n)> 20) & 0x1F)*/ /* 0..31 ... | 114 |
/*
*/
/*
*/
#ifndef XTENSA_CACHEASM_H
#define XTENSA_CACHEASM_H
#include
#include
#include
#include
/*
/ GENERIC -- ALL CACHES /
/*
*/
/*
*/
.macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0
// Number of indices in cache (lines per way):
.set .Lind... | 115 |
ifne (\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497)
movi \aa, .Lindices / .Lperloop // number of loop iterations
// Possible improvement: need only loop if \aa > 1 ;
// however \aa == 1 is highly unlikely.
movi \ab, 0 // to iterate over cache
loop \aa, .Lend_cachex\@
.set .Li, 0 ; .rept .Lperloop
... | 115 |
endif
addi \ab, \ab, .Lperloop*\linesize // move to next line
bltu \ab, \aa, .Lstart_cachex\@
.endif
.endm
/*
*/
.macro cache_hit_region cainst, linesize_log2, addr, asize, askew, awb=a0
// Make \asize the number of iterations:
extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr
a... | 115 |
endm
/*
*/
.macro icache_lock_line ar, offset
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
ipfl \ar, \offset /* prefetch and lock icache line */
icache_sync \ar
#endif
.endm
/*
*/
.macro icache_lock_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction... | 115 |
endm
/ DATA CACHE /
/*
*/
.macro dcache_reset aa, ab, loopokay=0
dcache_unlock_all \aa, \ab, \loopokay
dcache_invalidate_all \aa, \ab, \loopokay
.endm
/*
*/
.macro dcache_sync ar, wbtype=0
#if XCHAL_DCACHE_SIZE > 0
// No synchronization is needed.
// (memw may be desired e.g. after writeback ... | 115 |
macro cache_coherence_off ar at
#if XCHAL_DCACHE_IS_COHERENT
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
/* Have MEMCTL. Disable snoop responses. */
rsr.memctl \ar
movi \at, ~MEMCTL_SNOOP_EN
and \ar, \ar, \at
wsr.memctl \ar
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
/* Opt out of coherence, f... | 115 |
endm
/*
*/
.macro dcache_invalidate_all aa, ab, loopokay=1
#if XCHAL_DCACHE_SIZE > 0
// Data cache invalidation:
cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
dcache_sync \aa
// End of data cache invalidation
#endif
.endm
/*
*/
.macro dcach... | 115 |
endm
/*
*/
.macro dcache_writeback_inv_line ar, offset
#if XCHAL_DCACHE_SIZE > 0
dhwbi \ar, \offset /* writeback and invalidate dcache line */
dcache_sync \ar, wbtype=1
#endif
.endm
/*
*/
.macro dcache_writeback_inv_region astart, asize, ac, awb
#if XCHAL_DCACHE_SIZE > 0
// Data cache region writeback an... | 115 |
endm
/*
*/
.macro dcache_lock_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
dpfl \ar, \offset /* prefetch and lock dcache line */
dcache_sync \ar
#endif
.endm
/*
*/
.macro dcache_lock_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache... | 115 |
endm
/*
*/
.macro icache_get_ways aa
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr.memctl \aa
extui \aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
blti \aa, XCHAL_ICACHE_WAYS, .Licgw
movi \aa, XCHAL_ICACHE_WAYS
.Licgw:
#else
// All ways are always enabled
mo... | 115 |
Ldcgw
movi \aa, XCHAL_DCACHE_WAYS
.Ldcgw:
#else
// All ways are always enabled
movi \aa, XCHAL_DCACHE_WAYS
#endif
#else
// No dcache
movi \aa, 0
#endif
.endm
/*
*/
.macro dcache_set_ways aa, ab, ac
#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
movi \ac, MEMCTL_DCWA_CLR_MASK // set up to clear b... | 115 |
memctl \ab
#else
// No dcache or no way disable support
#endif
.endm
#endif /*XTENSA_CACHEASM_H*/
| 115 |
/* $Id: //depot/dev/Foxhill/Xtensa/OS/include/xtensa/mpuasm.h#5 $ */
/*
*/
#ifndef _MPUASM_H_
#define _MPUASM_H_
#include
/*
*/
.macro mpu_write_map a_map, a_num_entries, a_temp1, a_temp2, a_temp3, a_temp4
#if XCHAL_HAVE_MPU
movi \a_temp1, 0
wsr.cacheadrdis \a_temp1 // enable the cache in all regions
wsr.mpue... | 116 |
These statements should be
// properly conditionalized when that restriction is removed from the HW
wptlb \a_temp2, \a_temp1
addi \a_temp2, \a_temp2, 1
bltu \a_temp2, \a_temp3, 1b
// Write the new entries.
//
beqz \a_num_entries, 4f // if no entries, skip loop
addx8 \a_map, \a_num_entries, \a_map ... | 116 |
endm
/*
*/
.macro mpu_read_map a_map_ptr, a_temp1, a_temp2
#if XCHAL_HAVE_MPU
movi \a_temp1, XCHAL_MPU_ENTRIES // set index to last entry + 1
addx8 \a_map_ptr, \a_temp1, \a_map_ptr // set map ptr to last entry + 1
1: addi \a_temp1, \a_temp1, -1 // decrement index
addi \a_map_ptr, \a_map_ptr, -8 // decrement index
... | 116 |
/*
*/
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/coreasm.h#1 $ */
/*
*/
#ifndef XTENSA_COREASM_H
#define XTENSA_COREASM_H
/*
*/
#ifndef _ASMLANGUAGE /* conditionalize to avoid cpp warnings (3rd parties might use same macro) */
#define _ASMLANGUAGE
#endif
#include
#include
#include
/*
*/
/*... | 117 |
(if so, check lower 8 bits)
addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
srli \as, \as, 8 // shift right to check upper 8 bits
1: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
srli \as, \as, 4 // shi... | 117 |
macro find_ls_setbit ad, as, at, base
neg \at, \as // keep only the least-significant bit that is set...
and \as, \at, \as // ... in \as
find_ms_setbit \ad, \as, \at, \base
.endm // find_ls_setbit
/*
*/
.macro find_ls_one ad, as
find_ls_setbit \ad, \as, \ad, 0
.endm // find_ls_one
/*
*/
/* Named label ve... | 117 |
endm
#endif /*0*/
/* Underlying version of the macros: */
.macro floop_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floop cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loop \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
\startlabel:
addi \ar, \ar, -1
#... | 117 |
endm // floopgtz_
.macro floopend_ ar, startlabelref, endlabel
.ifndef _infloop_
.err // Error: floopend without matching floopXXX
.endif
.ifeq _infloop_
.err // Error: floopend without matching floopXXX
.endif
.set _infloop_, 0
#if ! XCHAL_HAVE_LOOPS
bnez \ar, \startlabelref
#endif /* XCHAL_HAVE_LOOPS */
\e... | 117 |
endm
/*
*/
.macro window_spill4
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call4 .L__wdwspill_assist28 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call4 .L__wdwspill... | 117 |
L__wdwspill_assist20 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call12 .L__wdwspill_assist52 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill12
/*
*/
.macro window_spill_function
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 32
entry s... | 117 |
l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
movi a7, 0 // called with call8
retw
1: movi a11, 0 // called with call4
2: retw // if called with call12, everything already spilled
// movi a15, 0 // trick to spill all but the direct caller
// j 1f
// // The entry... | 117 |
L__wdwspill_assist52:
entry sp, 48
call12 .L__wdwspill_assist40
retw
.L__wdwspill_assist40:
entry sp, 48
call12 .L__wdwspill_assist28
retw
# endif
.L__wdwspill_assist28:
entry sp, 48
call12 .L__wdwspill_assist16
retw
.L__wdwspill_assist24:
entry sp, 32
call8 .L__wdwspill_assist16
retw
.L__wdwspill_assist20... | 117 |
endm
/*
*/
.macro isync_return_nop
#ifdef __XTENSA_WINDOWED_ABI__
isync_retw_nop
#endif
.endm
/*
*/
.macro isync_erratum453
#if XCHAL_ERRATUM_453
isync
#endif
.endm
/*
*/
.macro readsr reg suf ar
rsr.\reg\suf \ar
.endm
/*
*/
.macro writesr reg suf ar
wsr.\reg\suf \ar
.endm
... | 117 |
ifc \arr, \ars
// addx2 a, a, a (not common)
.err
.else
add \arr, \ars, \art
add \arr, \ars, \art
.endif
.else
//addx2 a, b, c
//addx2 a, a, b
//addx2 a, b, b
slli \arr, \ars, 1
add \arr, \arr, \art
.endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*
#if !XCHAL_HAVE_ADDX
.macro addx4 arr, ars, art
.ifc... | 117 |
endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*
*/
#if XCHAL_HAVE_XEA1
.macro rfe_rfue
rfue
.endm
#elif XCHAL_HAVE_XEA2
.macro rfe_rfue
rfe
.endm
#endif
/*
*/
/*
*/
.macro abi_entry_size locsize=0, callsize=0
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
.ifeq \callsize
.set .callsz, 16
.else
.... | 117 |
ifgt .locsz - 32760 /* .locsz > 32760 (ENTRY's max range)? */
/* Funky computation to try to have assembler use addmi efficiently if possible: */
entry sp, 0x7F00 + (.locsz & 0xF0)
addi a12, sp, - ((.locsz & -0x100) - 0x7F00)
movsp sp, a12
.else
entry sp, .locsz
.endif
#else
# define ABI_ENTRY_MINSIZE 0 /* siz... | 117 |
locsz
add sp, sp, a9
.endif /* end */
.endif
ret
#endif
.endm
/*
*/
.macro hw_erratum_487_fix
#if defined XSHAL_ERRATUM_487_FIX
isync
#endif
.endm
/*
*/
#define _GBL(x) .global x
#define _TYP(x) .type x,@function
#define _ALN(x) .align x
#define _SIZ(x) .size x, . - x
#define _MKEND(x) .p... | 117 |
/*
*/
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/corebits.h#1 $ */
/*
*/
#ifndef XTENSA_COREBITS_H
#define XTENSA_COREBITS_H
/* EXCCAUSE register fields: */
#define EXCCAUSE_EXCCAUSE_SHIFT 0
#define EXCCAUSE_EXCCAUSE_MASK 0x3F
/* EXCCAUSE register values: */
/*
*/
#define EXCCAUSE_ILLEGAL 0 ... | 118 |
.23 */
#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
/* Reserved 27 */ /* Size Restriction on Load/S... | 118 |
.63 */
/* PS register fields: */
#define PS_WOE_SHIFT 18
#define PS_WOE_MASK 0x00040000
#define PS_WOE PS_WOE_MASK
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_MASK 0x00030000
#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
#define PS_OWB_SHIFT 8
#define PS_OWB_MASK 0x00000F00
#define PS_O... | 118 |
N instruction */
#define DEBUGCAUSE_BREAK_SHIFT 3
#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
#define DEBUGCAUSE_DBREAK_SHIFT 2
#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
#define DEBUGCAUSE_IBREAK_SHIFT 1
#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
#define DEBUGCAUSE_ICOUNT_S... | 118 |
buffer (default 1) */
#define MEMCTL_INV_EN_SHIFT 23
#define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */
#define MEMCTL_DCWU_SHIFT 8
#define MEMCTL_DCWU_BITS 5
#define MEMCTL_DCWA_SHIFT 13
#define MEMCTL_DCWA_BITS 5
#define MEMCTL_ICWU_SHIFT 18
#define MEMCTL_ICWU_BITS 5
#define MEMCTL_DCWU_M... | 118 |
/*
xtensa/hal.h -- contains a definition of the Core HAL interface
All definitions in this header file are independent of any specific
Xtensa processor configuration. Thus software (eg. OS, application,
etc) can include this header file and be compiled into configuration-
independent objects that can b... | 119 |
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILIT... | 119 |
.......E 2345789 exception */
/*efine XTHAL_FAM_ISOLATE*/ /*0x012*/ /* .---I.-C- ....... isolate */
#define XTHAL_FAM_BYPASS 0x000 /* ..--- 2345789 bypass */
/*efine XTHAL_FAM_NACACHED*/ /*0x002*/ /* ..-C- ....... cached no-allocate (frozen) */
#define XTHAL_FAM_CACHED 0x006 /* ..AC- 2345789 cached */
/* ... | 119 |
.......E 2345789 exception */
#define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 2345789 isolate */
#define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 2345789 bypass */
#define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 2345789 writethrough */
/*efine XTHAL_SAM_WRITETHRU_ALLOC*/ /*0x02E*/ /* -O-G-WAC- ....... writethrough allocate... | 119 |
..9 writeback (WB) */
/*efine XTHAL_PAM_NORMAL*/ /*0x050*/ /* xxx0010bxxxx .... (unimplemented) */
/*efine XTHAL_PAM_WRITETHRU_WA*/ /*0x130*/ /* xxx1001bxxxx .... (unimplemented, less likely) */
/*efine XTHAL_PAM_WRITETHRU_RWA*/ /*0x1B0*/ /* xxx1101bxxxx .... (unimplemented, less likely) */
/*efine XTHAL... | 119 |
.D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved)
0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate
0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal
*/
#endif /*0*/
#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
#ifdef __cplusplus
extern "C" {
#endif
/*
Register Wi... | 119 |
Use the newer functions
xthal_interrupt_trigger and xthal_interrupt_clear instead. */
extern void xthal_set_intset( unsigned );
extern void xthal_set_intclear( unsigned );
/*
Debug
*/
/* Number of instruction and data break registers: */
extern const int Xthal_num_ibreak;
extern const int ... | 119 |
INTLEVEL) and virtual interrupt priorities: */
extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
/* These functions are deprecated. Use xthal_interrupt_e... | 119 |
. 8 */
extern const unsigned char Xthal_mmu_asid_kernel;
extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
extern const unsigned char Xthal_mmu_ring_bits;
extern const unsigned char Xthal_mmu_sr_bits;
extern const unsigned char Xthal_mmu_ca_bits;
extern const unsigned... | 119 |
*/
#define XTHAL_INEXACT -2
/* The supplied address doesn't correspond to the start of a region. */
#define XTHAL_INVALID_ADDRESS -3
/* This functionality is not available on this architecture. */
#define XTHAL_UNSUPPORTED -4
/* ... | 119 |
*/
#define XTHAL_OUT_OF_ORDER_MAP -11
/* an invalid argument such as a null pointer was supplied to the function */
#define XTHAL_INVALID -12
/* specified region is of zero size, therefore no mapping is done. */
#define XTHAL_ZERO_SIZED_REGION ... | 119 |
*/
#define XTHAL_AR_NONE 0 /* no access */
#define XTHAL_AR_R 4 /* Kernel read, User no access*/
#define XTHAL_AR_RX 5 /* Kernel read/execute, User no access */
#define XTHAL_AR_RW 6 /* Kernel read/write, User no access */
#define XTHAL_AR_RWX 7 /* Kernel read/write/execute, User no access */
#... | 119 |
Only applicable to devices */
#define XTHAL_MEM_INTERRUPTIBLE 0x08000000
/* Indicates if writes to this memory are bufferable ... only applicable
*/
#define XTHAL_MEM_BUFFERABLE 0x01000000
/* The following group of constants indicates the scope of the sharing of
*/
#define XTHA... | 119 |
These should not
*/
/*
*/
#define _XTHAL_SYSTEM_CACHE_BITS 0x000f0000
#define _XTHAL_LOCAL_CACHE_BITS 0x00f00000
#define _XTHAL_MEM_SYSTEM_RWC_MASK 0x00070000
#define _XTHAL_MEM_LOCAL_RWC_MASK 0x00700000
#define _XTHAL_SHIFT_RWC 16
#define _XTHAL_MEM_ANY_SHAREABLE(x) (((x) & XTHAL_MEM_SYSTEM_SHAREABLE) ? 1 : 0)
... | 119 |
1 : 0)
#define _XTHAL_ENCODE_DEVICE(x) \
(((((x) & XTHAL_MEM_INTERRUPTIBLE) ? 1 : 0) > 4) & XTHAL_MEM_NON_CACHEABLE) == \
XTHAL_MEM_NON_CACHEABLE) ? 1 : 0) ? \
(_XTHAL_CACHEABLE_DOMAIN(x) > _XTHAL_SHIFT_RWC)
#define _XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x) \
((_XTHA... | 119 |
_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
/
EXPERIMENTAL and DEPRECATED Definitions
/
#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
#ifdef __cplusplus
extern "C" {
#endif
#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
#define X... | 119 |
_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
#endif /*XTENSA_HAL_H*/
| 119 |
/* $Id: //depot/dev/Foxhill/Xtensa/OS/include/xtensa/mpuasm.h#5 $ */
/*
*/
#ifndef _IDMAASM_H_
#define _IDMAASM_H_
#if XCHAL_HAVE_IDMA
#include
#endif
/*
*/
// IDMA_REG_SETTINGS,
// IDMA_REG_TIMEOUT,
// IDMA_REG_DESC_START,
// IDMA_REG_CONTROL,
// IDMA_REG_USERPRIV,
.macro _idma_restore a_save, a_temp... | 120 |
/* xer-constants.h -- various constants describing external registers accessed
via wer and rer.
TODO: find a better prefix. Also conditionalize certain constants based
on number of cores and interrupts actually present.
*/
/*
*/
#include
#define NUM_INTERRUPTS 27
#define NUM_CORES 4
/* Ro... | 121 |
/*
*/
/*
*/
#ifndef XTENSA_CACHEATTRASM_H
#define XTENSA_CACHEATTRASM_H
#include
/* Determine whether cache attributes are controlled using eight 512MB entries: */
#define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPAN... | 122 |
// Just return zero.
movi a2, 0
#endif
.endm
.macro icacheattr_get
_cacheattr_get itlb
.endm
.macro dcacheattr_get
_cacheattr_get dtlb
.endm
/* Default (powerup/reset) value of CACHEATTR,
all BYPASS mode (ie. disabled/bypassed caches): */
#if XCHAL_HAVE_PTP_MMU
# define XCHAL_CACHEATTR_ALL_BYPASS 0x33... | 122 |
macro _cacheattr_is_enabled label
movi a4, 8 // loop 8 times
.Lcaife\@:
extui a5, a2, 0, 4 // get CA nibble
ssr a5 // index into mask according to CA...
srl a5, a3 // ...and get CA's mask bit in a5 bit 0
bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
srli a2, a2, 4 // next nibble
addi a4... | 122 |
endm
/*
*/
#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
/*
*/
.macro icacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a6, 3f // PC where ITLB is set
movi a3, XCHAL_SPANNING_... | 122 |
end no-transform
nop
nop
sub a3, a3, a5 // next segment (add 0x20000000)
bltui a3, 16, 4f // done?
// Note that in the WITLB loop, we don't do any load/stores
// (may not be an issue here, but it is important in the DTLB case).
2: srli a7, a7, 4 // next CA
3:
# if XCHAL_HAVE_MIMIC_CACHEATTR
extui a4, a7, 0, ... | 122 |
. 7)
mov a7, a2 // copy a2 so it doesn't get clobbered
// Note that in the WDTLB loop, we don't do any load/stores
2: // (including implicit l32r via movi) because it isn't safe.
# if XCHAL_HAVE_MIMIC_CACHEATTR
extui a4, a7, 0, 4 // extract CA to set
# else /* have translation, preserve it: */
rdtlb1 a8, a3 // ... | 122 |
with the CACHEATTR register)
// allows changing the cache attributes of the running code
// using the following exact sequence aligned to be within
// an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
// alignment actually causes problems because that can be greater
// than the alignment of the ... | 122 |
/*
*/
#ifndef __XT_PERF_CONSTS_H__
#define __XT_PERF_CONSTS_H__
#include
/*
*/
#define XTPERF_CNT_COMMITTED_INSN 0x8002 /* Instructions committed */
#define XTPERF_CNT_BRANCH_PENALTY 0x8003 /* Branch penalty cycles */
#define XTPERF_CNT_PIPELINE_INTERLOCKS 0x8004 /* Pipeline... | 123 |
e. RET, RETW */
#define XTPERF_MASK_INSN_RF 0x0008 /* supervisor return i.e. RFDE, RFE, RFI, RFWO, RFWU */
#define XTPERF_MASK_INSN_BRANCH_TAKEN 0x0010 /* Conditional branch taken, or loopgtz/loopnez skips loop */
#define XTPERF_MASK_INSN_J 0x0020 /* J */
#define XT... | 123 |
e. excludes $ miss etc.) */
#define XTPERF_MASK_EXR_LEVEL1_INT 0x0002 /* Level-1 interrupt */
#define XTPERF_MASK_EXR_LEVELH_INT 0x0004 /* Greater-than-level-1 interrupt */
#define XTPERF_MASK_EXR_DEBUG 0x0008 /* Debug exception */
#define XTPERF_MASK_EXR_NMI ... | 123 |
g. branch delay slot) */
#define XTPERF_MASK_BUBBLES_WAITI 0x0100 /* WAITI bubble */
/*
*/
#define XTPERF_MASK_I_TLB_ALL 0x000F
#define XTPERF_MASK_I_TLB_HITS 0x0001 /* Hit */
#define XTPERF_MASK_I_TLB_REPLAYS 0x0002 /* Replay of instruction due... | 123 |
e. uncached) load */
/*
*/
#define XTPERF_MASK_D_STORE_ALL 0x000F
#define XTPERF_MASK_D_STORE_CACHE_HITS 0x0001 /* DCache Hit */
#define XTPERF_MASK_D_STORE_CACHE_MISSES 0x0002 /* DCache Miss */
#define XTPERF_MASK_D_STORE_LOCAL_MEM 0x0004 /* Local memory hit */... | 123 |
/*
*/
#ifndef XTRUNTIME_H
#define XTRUNTIME_H
#include
#include
#include
#ifndef XTSTR
#define _XTSTR(x) # x
#define XTSTR(x) _XTSTR(x)
#endif
/* _xtos_core_shutoff() flags parameter values: */
#define XTOS_KEEPON_MEM 0x00000100 /* ==PWRCTL_MEM_WAKEUP */
#define XTOS_KEEPON_MEM_SHIFT 8
#define XTOS_KEEPON_DE... | 124 |
..);
#else
typedef void (_xtos_handler_func)(void);
#endif
typedef _xtos_handler_func *_xtos_handler;
/*
*/
#if !XCHAL_HAVE_INTERRUPTS
# define XTOS_SET_INTLEVEL(intlevel) 0
# define XTOS_SET_MIN_INTLEVEL(intlevel) 0
# define XTOS_RESTORE_INTLEVEL(restoreval)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
#elif XCH... | 124 |
ps %0 ; rsync\n" \
: : "a" (__tmp) : "memory" ); \
}while(0)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval)
#else
/* In XEA1, we have to rely on INTENABLE register virtualization: */
extern unsigned _xtos_set_vpri( unsigned vpri );
extern unsigned _xtos_vpri_enabled; /* curr... | 124 |
Use the newer functions below. */
extern unsigned int _xtos_ints_off( unsigned int mask );
extern unsigned int _xtos_ints_on( unsigned int mask );
/* Newer functions to enable/disable the specified interrupt. */
static inline void _xtos_interrupt_enable(unsigned int intnum)
{
_xtos_ints_on(1U = 1
extern void _... | 124 |
*/
extern int _xtos_core_shutoff(unsigned flags);
extern int _xtos_core_save(unsigned flags, XtosCoreState *savearea, void *code);
extern void _xtos_core_restore(unsigned retvalue, XtosCoreState *savearea);
#if XCHAL_NUM_CONTEXTS > 1
extern unsigned _xtos_init_context(int context_num, int stack_size,
_... | 124 |
/* TRAX register definitions
Copyright (c) 2006-2012 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to ... | 125 |
*/
#ifndef _TRAX_REGISTERS_H_
#define _TRAX_REGISTERS_H_
#define SHOW 1
#define HIDE 0
#define RO 0
#define RW 1
/* TRAX Register Numbers (from possible range of 0..127) */
#if 0
#define TRAXREG_ID 0
#define TRAXREG_CONTROL 1
#define TRAXREG_STATUS 2
#define TRAXREG_DATA 3
#define TRAXREG_ADDRESS 4
#define... | 125 |
/* xdm-regs.h - Common register and related definitions for the XDM
(Xtensa Debug Module) */
/* Copyright (c) 2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"),... | 126 |
*/
#ifndef _XDM_REGS_H_
#define _XDM_REGS_H_
/* NOTE: This header file is included by C, assembler, and other sources.
So any C-specific or asm-specific content must be appropriately #ifdef'd. */
/*
*/
/* FIXME: maybe provide only MISC+CS registers here, and leave specific
subsystem registers in separ... | 126 |
mon. global control register */
#define XDM_PERF_INTPC 0x101010 /*[0x24] perf. mon. interrupt PC */
#define XDM_PERF_PM0 0x101080 /*[0x28] perf. mon. counter 0 value */
#define XDM_PERF_PM1 0x101084 /*[0x29] perf. mon. counter 1 value */
#define XDM_PERF_PM2 0x101088 /*[0x2A] perf. mon. counter 2 value */
#def... | 126 |
(0x60 | (((a)>>2) & 0x1F)) \
: -1 )
#define XDM_ERI_TO_NAR(a) _XDM_ERI_TO_NAR(a & 0xFFFF)
/* Convert 7-bit NAR address back to ERI/APB address/offset: */
#define _XDM_NAR_TO_APB(a) ((a) = 0x20 && (a) = 0x40 && (a) = 0x58 && (a) = 0x68 && (a) <= 0x7F ? (0x3F80 | (((a)&0x1F) << 2)) \
: -1)
#define XDM_NAR_TO... | 126 |
! */
/* ERI/APB: */
#define PWRSTAT_CORE_DOMAIN_ON 0x00000001 /* set if core is powered on */
#define PWRSTAT_CORE_DOMAIN_ON_SHIFT 0
#define PWRSTAT_WAKEUP_RESET 0x00000002 /* [ERI only] 0=cold start, 1=PSO wakeup */
#define PWRSTAT_WAKEUP_RESET_SHIFT 1
#define PWRSTAT_CACHES_LOST_POWER 0x00000004 /* [ERI only] ... | 126 |
NOTE: different bit positions in JTAG vs. ERI/APB !! */
/* ERI/APB: */
#define PWRCTL_CORE_SHUTOFF 0x00000001 /* [ERI only] core wants to shut off on WAITI */
#define PWRCTL_CORE_SHUTOFF_SHIFT 0
#define PWRCTL_CORE_WAKEUP 0x00000001 /* [APB only] set to force core to stay powered on */
#define PWRCTL_CORE_WAKE... | 126 |
8-bit NAR / 32-bit NDR (Nexus-style) */
#define XDM_IR_NDR_SEL 0x1d /* select altern. 32-bit NDR / 8-bit NAR
(FIXME - functionality not yet in HW) */
#define XDM_IR_IDCODE 0x1e /* select 32-bit JTAG IDCODE */
#define XDM_IR_BYPASS 0x1f /* select 1-bit bypass */
#define XDM_IR_WIDTH 5 /* width of IR for Xt... | 126 |
reg != -1) {
if (list[i].reg == reg)
break;
i++;
}
return list[i].name;
}
#if defined (USE_XDM_REGNAME)
static regdef_t xdm_reglist[] =
{
{XDM_OCD_DSR ,"DOSR" },
{XDM_OCD_DDR ,"DDR" },
{XDM_OCD_DDREXEC ,"DDREXEC" },
{XDM_OCD_DIR0EXEC ,"DIR0EXEC"},
{XDM_OCD_DCR_CLR ... | 126 |
" },
{XDM_TRAX_FSM_STATUS,"FSM STAT." },
{XDM_TRAX_IB_STATUS ,"IB STAT." },
{XDM_OCD_ID ,"OCD_ID" },
{XDM_OCD_DIR0 ,"DIR0" },
{XDM_OCD_DIR1 ,"DIR1" },
{XDM_OCD_DIR2 ,"DIR2" },
{XDM_OCD_DIR3 ,"DIR3" },
{XDM_OCD_DIR4 ,"DIR4" },
{XDM_OCD_DI... | 126 |
??" },
};
#endif
#endif
#endif /* _XDM_REGS_H_ */
| 126 |
/*
*/
/*
*/
#ifndef XTENSA_CACHE_H
#define XTENSA_CACHE_H
#include
/* Only define things for C code. */
#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
/ CACHE /
/* All the macros are in the lower case now and some of them
*/
/*** INSTRUCTION CACHE ***/
#define XT... | 127 |
*/:::"memory")
# define xthal_dcache_line_prefetch_for_read(addr) do { \
XT_DPFR((const int*)addr, 0); \
} while(0)
#else
# define xthal_dcache_line_invalidate(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_writeback(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_writeback_inv(addr)... | 127 |
\
XCHAL_DCACHE_SIZE : _s; \
type((const int*)_a, __s); \
_s -= __s; \
_a += __s; \
} while(_s > 0);
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \
if (max 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
# define xthal_dcache_block_prefetch_for_write(addr, si... | 127 |
intenable %0" : "=a"(__intenable)); \
__intenable; })
# define XTHAL_SET_INTENABLE(v) do { int __intenable = (int)(v); \
__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
} while(0)
# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
__asm__ __volatile__("rsr.interrupt %0" : "=a"(... | 127 |
ccount %0" : "=a"(__ccount)); \
__ccount; })
# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
} while(0)
# define _XTHAL_GET_CCOMPARE(n) ({ int __ccompare; \
__asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
__ccompar... | 127 |
For this release they just map to the older ones. */
/* Enables the specified interrupt. */
static inline void xthal_interrupt_enable(unsigned intnum)
{
xthal_int_enable(1 = 2200
__asm__ __volatile__ (
" wsr.scompare1 %2 \n"
" s32c1i %0, %3, 0 \n"
: "=a"(result) : "0" (setval), "a" (testval), "a... | 127 |
align 8\n\t1: memw\n\twptlb %0, %1\n\t" : : "a" (entry.at), "a"(entry.as));
#endif
}
/* Same as xthal_mpu_set_entry except that this function must not be used to change the MPU entry
static inline void xthal_mpu_set_entry_ (xthal_MPU_entry entry)
{
#if XCHAL_HAVE_MPU
__asm__ __volatile__("wptlb %0, %1\n\t" : : "a" (... | 127 |
/*
xtensa-versions.h -- definitions of Xtensa version and release numbers
This file defines most Xtensa-related product versions and releases
that exist so far.
It also provides a bit of information about which ones are current.
This file changes every release, as versions/releases get added.
*/
// $... | 128 |
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILIT... | 128 |
2b */
#define XTENSA_HWCIDSCHEME_T1020_2B 10
#define XTENSA_HWCIDVERS_T1020_2B 5
#define XTENSA_HWVERSION_T1020_3 102003 /* versions T1020.3 */
#define XTENSA_HWCIDSCHEME_T1020_3 10
#define XTENSA_HWCIDVERS_T1020_3 6
#define XTENSA_HWVERSION_T1020_4 102004 /* versions T1020.4 */
#define XTENSA_HWCIDSCHEME_T102... | 128 |
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