text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
1 */
#define XTENSA_HWCIDSCHEME_T1040_1 1
#define XTENSA_HWCIDVERS_T1040_1 32
#define XTENSA_HWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
#define XTENSA_HWCIDSCHEME_T1040_1P 10
#define XTENSA_HWCIDVERS_T1040_1P 16
#define XTENSA_HWVERSION_T1040_2 104002 /* versions T1040.2 */
#define XTENSA_HWCID... | 128 |
3 */
#define XTENSA_HWCIDSCHEME_T1050_3 1100
#define XTENSA_HWCIDVERS_T1050_3 6
#define XTENSA_HWVERSION_T1050_4 105004 /* versions T1050.4 */
#define XTENSA_HWCIDSCHEME_T1050_4 1100
#define XTENSA_HWCIDVERS_T1050_4 7
#define XTENSA_HWVERSION_T1050_5 105005 /* versions T1050.5 */
#define XTENSA_HWCIDSCHEME_T10... | 128 |
0.4, X6.0.4 */
#define XTENSA_HWCIDSCHEME_RA_2006_4 1100
#define XTENSA_HWCIDVERS_RA_2006_4 23
#define XTENSA_HWVERSION_RA_2006_5 210005 /* versions LX1.0.5, X6.0.5 */
#define XTENSA_HWCIDSCHEME_RA_2006_5 1100
#define XTENSA_HWCIDVERS_RA_2006_5 24
#define XTENSA_HWVERSION_RA_2006_6 210006 /* versions LX1.0.6, X... | 128 |
1.0, X7.1.0 */
#define XTENSA_HWCIDSCHEME_RB_2007_2 1100
#define XTENSA_HWCIDVERS_RB_2007_2 52
#define XTENSA_HWVERSION_RB_2008_3 221001 /* versions LX2.1.1, X7.1.1 */
#define XTENSA_HWCIDSCHEME_RB_2008_3 1100
#define XTENSA_HWCIDVERS_RB_2008_3 53
#define XTENSA_HWVERSION_RB_2008_4 221002 /* versions LX2.1.2, X... | 128 |
0.2, X8.0.2, MX1.0.2 */
#define XTENSA_HWCIDSCHEME_RC_2010_2 1100
#define XTENSA_HWCIDVERS_RC_2010_2 67
#define XTENSA_HWVERSION_RC_2011_3 230003 /* versions LX3.0.3, X8.0.3, MX1.0.3 */
#define XTENSA_HWCIDSCHEME_RC_2011_3 1100
#define XTENSA_HWCIDVERS_RC_2011_3 68
#define XTENSA_HWVERSION_RD_2010_0 240000 /* v... | 128 |
0.4, X9.0.4, MX1.1.4, TX1.0.4 */
#define XTENSA_HWCIDSCHEME_RD_2012_4 1100
#define XTENSA_HWCIDVERS_RD_2012_4 84
#define XTENSA_HWVERSION_RD_2012_5 240005 /* versions LX4.0.5, X9.0.5, MX1.1.5, TX1.0.5 */
#define XTENSA_HWCIDSCHEME_RD_2012_5 1100
#define XTENSA_HWCIDVERS_RD_2012_5 85
#define XTENSA_HWVERSION_RE_... | 128 |
0.4, X10.0.4, MX1.2.4 */
#define XTENSA_HWCIDSCHEME_RE_2013_4 1100
#define XTENSA_HWCIDVERS_RE_2013_4 100
#define XTENSA_HWVERSION_RE_2014_5 250005 /* versions LX5.0.5, X10.0.5, MX1.2.5 */
#define XTENSA_HWCIDSCHEME_RE_2014_5 1100
#define XTENSA_HWCIDVERS_RE_2014_5 101
#define XTENSA_HWVERSION_RE_2015_6 250006 ... | 128 |
3 */
#define XTENSA_HWCIDSCHEME_RF_2015_3 1100
#define XTENSA_HWCIDVERS_RF_2015_3 115
#define XTENSA_HWVERSION_RF_2016_4 260004 /* versions LX6.0.4, X11.0.4 */
#define XTENSA_HWCIDSCHEME_RF_2016_4 1100
#define XTENSA_HWCIDVERS_RF_2016_4 116
#define XTENSA_HWVERSION_RG_2015_0 270000 /* versions LX7.0.0 */
#defin... | 128 |
0.5 */
#define XTENSA_HWCIDSCHEME_RG_2017_5 1100
#define XTENSA_HWCIDVERS_RG_2017_5 133
#define XTENSA_HWVERSION_RG_2017_6 270006 /* versions LX7.0.6 */
#define XTENSA_HWCIDSCHEME_RG_2017_6 1100
#define XTENSA_HWCIDVERS_RG_2017_6 134
#define XTENSA_HWVERSION_RG_2017_7 270007 /* versions LX7.0.7 */
#define XTEN... | 128 |
1 */
#define XTENSA_SWVERSION_T1020_2 102002 /* versions T1020.2 */
#define XTENSA_SWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_SWVERSION_T1020_3 102003 /* versions T1020.3 */
#define XTENSA_SWVERSION_T1020_4 102004 /* versions T1020.4 */
#define XTENSA_SWVERSION_T1030_0 103000 /* versions T1030.0 *... | 128 |
2 */
#define XTENSA_SWVERSION_T1050_3 105003 /* versions T1050.3 */
#define XTENSA_SWVERSION_T1050_4 105004 /* versions T1050.4 */
#define XTENSA_SWVERSION_T1050_5 105005 /* versions T1050.5 */
#define XTENSA_SWVERSION_RA_2004_1 600000 /* versions 6.0.0 */
#define XTENSA_SWVERSION_RA_2005_1 600001 /* versions 6.0.1 */
... | 128 |
1.1 */
#define XTENSA_SWVERSION_RB_2008_4 701002 /* versions 7.1.2 */
#define XTENSA_SWVERSION_RB_2009_5 701003 /* versions 7.1.3 */
#define XTENSA_SWVERSION_RB_2007_2_MP 701100 /* versions 7.1.8-MP */
#define XTENSA_SWVERSION_RC_2009_0 800000 /* versions 8.0.0 */
#define XTENSA_SWVERSION_RC_2010_1 800001 /* versions 8... | 128 |
0.2 */
#define XTENSA_SWVERSION_RE_2013_3 1000003 /* versions 10.0.3 */
#define XTENSA_SWVERSION_RE_2013_4 1000004 /* versions 10.0.4 */
#define XTENSA_SWVERSION_RE_2014_5 1000005 /* versions 10.0.5 */
#define XTENSA_SWVERSION_RE_2015_6 1000006 /* versions 10.0.6 */
#define XTENSA_SWVERSION_RF_2014_0 1100000 /* version... | 128 |
0.6 */
#define XTENSA_SWVERSION_RG_2017_7 1200007 /* versions 12.0.7 */
#define XTENSA_SWVERSION_RG_2017_8 1200008 /* versions 12.0.8 */
#define XTENSA_SWVERSION_RG_2018_9 1200009 /* versions 12.0.9 */
#define XTENSA_SWVERSION_RH_2016_0 1300000 /* versions 13.0.0 */
#define XTENSA_SWVERSION_T1040_1_PREHOTFIX XTENSA_SWV... | 128 |
0.0 */
#define XTENSA_SWVERSION_7_0_1 XTENSA_SWVERSION_RB_2007_1 /* 7.0.1 */
#define XTENSA_SWVERSION_7_1_0 XTENSA_SWVERSION_RB_2007_2 /* 7.1.0 */
#define XTENSA_SWVERSION_7_1_1 XTENSA_SWVERSION_RB_2008_3 /* 7.1.1 */
#define XTENSA_SWVERSION_7_1_2 XTENSA_SWVERSION_RB_2008_4 /* 7.1.2 */
#define XTENSA_SWVERSION_7_1_3 XT... | 128 |
0.4 */
#define XTENSA_SWVERSION_9_0_5 XTENSA_SWVERSION_RD_2012_5 /* 9.0.5 */
#define XTENSA_SWVERSION_10_0_0 XTENSA_SWVERSION_RE_2012_0 /* 10.0.0 */
#define XTENSA_SWVERSION_10_0_1 XTENSA_SWVERSION_RE_2012_1 /* 10.0.1 */
#define XTENSA_SWVERSION_10_0_2 XTENSA_SWVERSION_RE_2013_2 /* 10.0.2 */
#define XTENSA_SWVERSION_10... | 128 |
0.0 */
#define XTENSA_SWVERSION_12_0_1 XTENSA_SWVERSION_RG_2015_1 /* 12.0.1 */
#define XTENSA_SWVERSION_12_0_2 XTENSA_SWVERSION_RG_2015_2 /* 12.0.2 */
#define XTENSA_SWVERSION_12_0_3 XTENSA_SWVERSION_RG_2016_3 /* 12.0.3 */
#define XTENSA_SWVERSION_12_0_4 XTENSA_SWVERSION_RG_2016_4 /* 12.0.4 */
#define XTENSA_SWVERSION_... | 128 |
0.9"
#define XTENSA_SWVERSION_MAJORMID_NAME "12.0"
#define XTENSA_SWVERSION_MAJOR_NAME "12"
/* For product licensing (not necessarily same as *_MAJORMID_NAME): */
#define XTENSA_SWVERSION_LICENSE_NAME "12.0"
/* Note: there may be multiple hardware products in one release,
and software can target older hardware... | 128 |
/*
*/
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/specreg.h#1 $ */
/*
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define LITBASE 5
#define SCOMPARE1 12
#define ACCLO 16
#define ACCH... | 129 |
.. 21..24 */ /* (545CK) */
/*#define ... 140..143 */ /* (545CK) */
#define EXPSTATE 230 /* Diamond */
#define THREADPTR 231 /* threadptr option */
#define FCR 232 /* FPU */
#define FSR 233 /* FPU */
#define AE_OVF_SAR 240 /* HiFi2 */
#define AE_BITHEAD 241 /* HiFi2 */
#define AE_TS_FTS_BU_BP 242 /* HiFi2 */
#define ... | 129 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline long semihosting_call_noerrno(long id, long *data)
{
register long a2 asm ("a2") = id;
register long a3 asm ("a3") = (long)data;
__asm__ __volatile__ (
"break 1, 14\n"
: "+r"(a2) : "r"(a3)
: "memory"... | 130 |
/* xtruntime-frames.h - exception stack frames for single-threaded run-time */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */
/*
*/
#ifndef _XTRUNTIME_FRAMES_H_
#define _XTRUNTIME_FRAMES_H_
#include
/* Macros that help define structures for both C and assembler: */
#if ... | 131 |
endif\
.set XT_STRUCT_OFFSET, pre##name + (size)*(n);
#define STRUCT_END(sname) .set sname##Size, XT_STRUCT_OFFSET;
#else /* __clang__ */
#define STRUCT_BEGIN .pushsection .text; .struct 0
#define STRUCT_FIELD(ctype,size,pre,name) pre##n... | 131 |
. a15 */
STRUCT_FIELD (long,4,KEXC_,sar) /* "save" */
#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long,4,KEXC_,lcount)
STRUCT_FIELD (long,4,KEXC_,lbeg)
STRUCT_FIELD (long,4,KEXC_,lend)
#endif
#if XCHAL_HAVE_MAC16
STRUCT_FIELD (long,4,KEXC_,acclo)
STRUCT_FIELD (long,4,KEXC_,acchi)
STRUCT_AFIELD(long,4,KEXC_,mr, 4)
#endif
STRUCT... | 131 |
*/
#ifdef __XTENSA_CALL0_ABI__
# define CALL0_ABI 1
#else
# define CALL0_ABI 0
#endif
#define ALIGNPAD ((3 + XCHAL_HAVE_LOOPS*1 + XCHAL_HAVE_MAC16*2 + CALL0_ABI*1) & 3)
#if ALIGNPAD
STRUCT_AFIELD(long,4,UEXC_,pad, ALIGNPAD) /* 16-byte alignment padding */
#endif
/*STRUCT_AFIELD_A(char,1,XCHAL_CPEXTRA_SA_ALIGN,UEXC_,u... | 131 |
/* xtruntime-core-state.h - core state save area (used eg. by PSO) */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */
/*
*/
#ifndef _XTOS_CORE_STATE_H_
#define _XTOS_CORE_STATE_H_
/* Import STRUCT_xxx macros for defining structures: */
#include
#include
#include
#if ... | 132 |
*/
STRUCT_FIELD (long,4,CS_SA_,atomctl)
#endif
#if XCHAL_HAVE_PREFETCH
STRUCT_FIELD (long,4,CS_SA_,prefctl)
#endif
#if XCHAL_USE_MEMCTL
STRUCT_FIELD (long,4,CS_SA_,memctl)
#endif
#if XCHAL_HAVE_CCOUNT
STRUCT_FIELD (long,4,CS_SA_,ccount)
STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS)
#endif
#if XCHAL_HAVE_INTE... | 132 |
*/
#if XCHAL_HAVE_CP
STRUCT_FIELD (long,4,CS_SA_,cpenable)
#endif
/* TLB state */
#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
STRUCT_AFIELD(long,4,CS_SA_,tlbs,8*2)
#endif
#if XCHAL_HAVE_PTP_MMU
/* Compute number of auto-refill (ARF) entries as max of I and D,
to simplify TLB save logic. On the... | 132 |
*/
STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE)
#if XCHAL_HAVE_CP
#if XCHAL_CP0_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
#endif
#if XCHAL_CP1_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE)
#endif
#if XCHAL_CP2... | 132 |
?
// DEBUGCAUSE ??
// EXCVADDR ??
// DDR
// INTERRUPT
// ... locked cache lines ...
#endif /* _XTOS_CORE_STATE_H_ */
| 132 |
#pragma once
#define PANIC_RSN_NONE 0
#define PANIC_RSN_DEBUGEXCEPTION 1
#define PANIC_RSN_DOUBLEEXCEPTION 2
#define PANIC_RSN_KERNELEXCEPTION 3
#define PANIC_RSN_COPROCEXCEPTION 4
#define PANIC_RSN_INTWDT_CPU0 5
#define PANIC_RSN_INTWDT_CPU1 6
#define PANIC_RSN_CACHEERR 7
#define PANIC_RSN_MAX 7
| 133 |
/*
*/
/*
*/
/*
*/
#ifndef XTENSA_RTOS_H
#define XTENSA_RTOS_H
#ifdef __ASSEMBLER__
#include
#else
#include
#endif
#include
#include
/*
Include any RTOS specific definitions that are needed by this header.
*/
#define XT_BOARD 1 /* Board mode */
#if (!XT_SIMULATOR) && (!XT_BOARD... | 134 |
h .
/
/*
Inform RTOS of entry into an interrupt handler that will affect it.
Allows RTOS to manage switch to any system stack and count nesting level.
Called after minimal context has been saved, with interrupts disabled.
RTOS port can call0 _xt_context_save to save the rest of the context.
May only be called from as... | 134 |
*/
// void XT_RTOS_INT_EXIT(void)
#define XT_RTOS_INT_EXIT _bmxt_int_exit
/*
Inform RTOS of the occurrence of a tick timer interrupt.
If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
May be coded in or called from C or assembly, per ABI conventions.
RTOS may optionally define XT_TICK_PER_SEC in its ow... | 134 |
*/
// void* XT_RTOS_CP_STATE(void)
#define XT_RTOS_CP_STATE _bmxt_task_coproc_state
/
HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
This Xtensa RTOS port provides hooks for dynamically installing exception
and interrupt handlers to facilitate automated testing where each test
case can... | 134 |
This allows a test
case to either pre-handle or override the default handling for the exception
or interrupt level (see xtensa_vectors.S).
High priority handlers (including NMI) must be coded in assembly, are always
called by 'call0' regardless of ABI, must preserve all registers except a0,
and must not use or modify... | 134 |
Ensures RTOS specific files need only include this one Xtensa-generic header.
These headers are included last so they can use the RTOS definitions above.
/
#include "xtensa_context.h"
#ifdef XT_RTOS_TIMER_INT
#include "xtensa_timer.h"
#endif
/
Xtensa Port Version.
/
#define XTENSA_PORT_VERSION ... | 134 |
/* Definitions for Xtensa instructions, types, and protos. */
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2003-2004 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software ... | 135 |
*/
/* NOTE: This file exists only for backward compatibility with T1050
and earlier Xtensa releases. It includes only a subset of the
available header files. */
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#include
#include
#include
#endif /* __XTENSA__ */
#endif /* !_XTEN... | 135 |
/*
*/
/*
*/
#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H
/* CONFIGURATION INDEPENDENT DEFINITIONS: */
#ifdef __XTENSA__
#include
#include
#else
#include "xtensa/hal.h"
#include "xtensa/xtensa-versions.h"
#endif
/* CONFIGURATION SPECIFIC DEFINITIONS: */
#ifdef __XTENSA__
#include
#include
#in... | 136 |
. 15 */
#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM
#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */
#define _XC... | 136 |
.15 reserved*/
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */
#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */
#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */
#define... | 136 |
.63 reserved*/
/*
*/
/* DBREAKC (special register number 160): */
#define XCHAL_DBREAKC_VALIDMASK 0xC000003F
#define XCHAL_DBREAKC_MASK_BITS 6
#define XCHAL_DBREAKC_MASK_NUM 64
#define XCHAL_DBREAKC_MASK_SHIFT 0
#define XCHAL_DBREAKC_MASK_MASK 0x0000003F
#define XCHAL_DBREAKC_LOADBREAK_BITS 1
#define XCHAL_... | 136 |
*/
#if XCHAL_HW_MIN_VERSION = 16
#define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */
#elif XCHAL_PREFETCH_ENTRIES >= 8
#define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */
#else
#define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* 0 entries for block ops */
#endif
/* Max for b... | 136 |
*/
#define XCHAL_CACHE_MEMCTL_DEFAULT 0xFFFFFF00 /* Init all possible ways */
#else
#define XCHAL_CACHE_MEMCTL_DEFAULT 0x00000000 /* Nothing to do */
#endif
#if XCHAL_DCACHE_IS_COHERENT
#define _MEMCTL_SNOOP_EN 0x02 /* Enable snoop */
#else
#define _MEMCTL_SNOOP_EN 0x00 /* Don't enable snoop */
#endif
#if (XCHAL... | 136 |
XCHAL_HAVE_SPANNING_WAY
#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
#define XCHAL_KSEG_BYPASS_V... | 136 |
!!) */
#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
#endif
/*
MISC
*/
/* Data align... | 136 |
macro xchal_sa_start continue totofs
.ifeq \continue
.set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */
.set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */
.endif
.if \totofs + 1 /* if totofs specified (not -1) */
.set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* sp... | 136 |
defined(_NO_ERRATUM_497) \
)
#define XCHAL_ERRATUM_497 1
#else
#define XCHAL_ERRATUM_497 0
#endif
/*
*/
#if ( XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 )
#define XCHAL_ERRATUM_572 1
#else
#define XCHAL_ERRATUM_572 0
#endif
#endif /*XTENSA_CONFIG_CORE_H*/
| 136 |
/*
*/
/* This header file describes this specific Xtensa processor's TIE extensions
that extend basic Xtensa core functionality. It is customized to this
Xtensa processor configuration.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
Permission is hereby granted, f... | 137 |
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_H
#define _XTENSA_... | 137 |
*/
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
/* Byte length of instruction from its first byte, per FLIX. */
#define XCHAL_BYTE0_FORMAT_LENGTHS \
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3... | 137 |
/*
*/
/* This header file contains assembly-language definitions (assembly
macros, etc.) for this specific Xtensa processor's TIE extensions
and options. It is customized to this Xtensa processor configuration.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
Permis... | 138 |
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_ASM_H
#define _XTE... | 138 |
macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rur.THREADPTR \at1 // thread... | 138 |
set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
rsr.BR \at1 // boolean option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.SCOMPARE1 \at1 // conditiona... | 138 |
F64R_LO \at1 // ureg 234
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.F64R_HI \at1 // ureg 235
s32i \at1, \ptr, .Lxchal_ofs_+4
rur.F64S \at1 // ureg 236
s32i \at1, \ptr, .Lxchal_ofs_+8
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr... | 138 |
ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.ACCLO \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.ACCHI \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_S... | 138 |
set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CAL... | 138 |
ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
rur.FCR \at1 // ureg 232
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.FSR \at1 // ureg 233
s32i \at1, \ptr, .Lxchal_ofs_+4
ssi f0, \ptr, .Lxchal_ofs_+8
ssi f1, \ptr, .Lxchal_ofs_+12
ssi f2, \ptr, .Lxchal_ofs_+16
ssi ... | 138 |
macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
l32i \at1, \ptr, .Lxc... | 138 |
set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_load
#define XCHAL_CP0_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
/* Empty macros for unconfigured coprocessors: */
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .... | 138 |
endm
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
#endif /*_XTENSA_CORE_TIE_ASM_H*/
| 138 |
/*
*/
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation th... | 139 |
*/
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*#include */
/*
CONFIGURED SOFTWARE OPTIONS
*/
#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both... | 139 |
..not configured...*/
/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
/* Some available location in which to place devices in a simulation (eg. XTMP): */
#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
#define XSHAL_SIMIO_PADDR 0xC0000000
#define XSHAL_SIMIO_SIZE 0x20000... | 139 |
..
*/
/* For now, ISS defaults to the TRAPNULL settings: */
#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
#define XSHAL_ISS_CACHEATTR_BYPASS... | 139 |
/*
*/
/* Xtensa processor core configuration information.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software wi... | 140 |
*/
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
/
Parameters Useful for Any Code, USER or PRIVILEGED
/
/*
*/
/*
ISA
*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 64 /... | 140 |
W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
#define XCH... | 140 |
unit clock gating */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
... | 140 |
castout bufsz */
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
#define XCHAL_HAVE_DCACHE_TEST 0 /* D... | 140 |
ROMs */
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
/* Instr... | 140 |
interrupts */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */... | 140 |
.n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFF... | 140 |
) */
/*
*/
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (i... | 140 |
*/
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_... | 140 |
*/
#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
/* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
/*
MMU
*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS... | 140 |
.4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */
| 140 |
/*
*/
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation th... | 141 |
/*
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal... | 142 |
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
#include
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define SCOMPARE1 12
#define ACCLO 16
#define ACCHI 17
#de... | 142 |
/*
*/
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by ... | 143 |
/*
*/
#pragma once
#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead"
#include
| 144 |
/*
*/
#pragma once
#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead"
#include
| 145 |
/*
*/
#pragma once
#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead"
#include
| 146 |
/*
*/
#pragma once
#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead"
#include
| 147 |
/*
*/
#pragma once
#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead"
#include
| 148 |
/*
*/
#pragma once
#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead"
#include
| 149 |
/* Definitions for Xtensa instructions, types, and protos. */
/* Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2004 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software ... | 150 |
*/
/* NOTE: This file exists only for backward compatibility with T1050
and earlier Xtensa releases. It includes only a subset of the
available header files. */
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#include
#include
#include
#endif /* __XTENSA__ */
#endif /* !_XTEN... | 150 |
/*
*/
/*
*/
#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H
/* CONFIGURATION INDEPENDENT DEFINITIONS: */
#ifdef __XTENSA__
#include
#include
#else
#include "../hal.h"
#include "../xtensa-versions.h"
#endif
/* CONFIGURATION SPECIFIC DEFINITIONS: */
#ifdef __XTENSA__
#include
#include
#include
#... | 151 |
= 0 \
|| XCHAL_HW_RELEASE_AT(1050,0)))
/*
*/
#if ( XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \
XCHAL_HW_MIN_VERSION = XTENSA_HWVERSION_RE_2012_0 && \
XCHAL_HW_MIN_VERSION = XTENSA_HWVERSION_RG_2015_0 && \
XCHAL_HW_MIN_VERSION . (Not... | 151 |
.15 reserved*/
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */
#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */
#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb S... | 151 |
.63 reserved*/
/*
*/
/* DBREAKC (special register number 160): */
#define XCHAL_DBREAKC_VALIDMASK 0xC000003F
#define XCHAL_DBREAKC_MASK_BITS 6
#define XCHAL_DBREAKC_MASK_NUM 64
#define XCHAL_DBREAKC_MASK_SHIFT 0
#define XCHAL_DBREAKC_MASK_MASK 0x0000003F
#define XCHAL_DBREAKC_LOADBREAK_BITS ... | 151 |
*/
#if XCHAL_HW_MIN_VERSION = 16) && XCHAL_HAVE_CACHE_BLOCKOPS)
#define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */
#elif ((XCHAL_PREFETCH_ENTRIES >= 8) && XCHAL_HAVE_CACHE_BLOCKOPS)
#define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */
#else
#define XCHAL_CACHE_PREFCTL_DEFA... | 151 |
*/
/* Has different semantic in open source headers (where it means HAVE_PTP_MMU),
so comment out starting with RB-2008.3 release; later, might get
get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead: */
/*#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS*/ /* (DEPRECATED; use XCHAL_HAVE_TLBS instea... | 151 |
XCHAL_HAVE_SPANNING_WAY
#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
#define XCHAL_... | 151 |
addr of kio_bypass */
#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
/* define... | 151 |
macro xchal_sa_start continue totofs
.ifeq \continue
.set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */
.set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */
.endif
.if \totofs + 1 /* if totofs specified (not -1) */
.set .Lxchal_ofs_, \totofs - .Lxchal_... | 151 |
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