text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
self_rx_request = 1;
}
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_cmd_self_rx_single_shot(twai_dev_t *hw)
{
hw->cmd.val = 0x12; //Set cmd.self_rx_request and cmd.abort_tx simultaneously for single shot self reception request
}
/* Status Register */
/**
*/
__attribute__((always_inlin... | 693 |
val = intr_mask;
}
/* Bus Timing Registers */
/**
*/
__attribute__((always_inline))
static inline bool twai_ll_check_brp_validation(uint32_t brp)
{
bool valid = (brp >= SOC_TWAI_BRP_MIN) && (brp bus_timing_0.baud_presc = (brp / 2) - 1;
hw->bus_timing_0.sync_jump_width = sjw - 1;
hw->bus_timing_1.time_s... | 693 |
val;
}
/* RX Error Count Register */
/**
*/
__attribute__((always_inline))
static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
{
return hw->rx_err_cnt.val;
}
/**
*/
__attribute__((always_inline))
static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_e... | 693 |
acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
}
hw->mode.acceptance_filter_mode = single_filter;
}
/* TX/RX Buffer Registers */
/**
*/
__attribute__((always_inline))
static inline void twai_... | 693 |
1 : 0;
tx_frame->single_shot = (flags & TWAI_MSG_FLAG_SS) ? 1 : 0;
//Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required
if (is_extd) {
uint32_t id_temp = HAL_SWAP32((id & TWAI_EXTD_ID_MASK) > 8*(3-i))
for (int i = 0; i extended.id[i] = (id_temp >> ... | 693 |
The ID registers are big endian and left aligned, therefore a bswap will be required
if (rx_frame->frame_format) {
uint32_t id_temp = 0;
for (int i = 0; i extended.id[i] > 3; //((byte[i] > 3)
*id = id_temp & TWAI_EXTD_ID_MASK;
} else {
uint32_t id_temp = 0;
for (int i =... | 693 |
clock_off = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, 255);
} else {
hw->clock_divider.clock_off = 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, 0);
}
}
#ifdef __cplusplus
}
#endif
| 693 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "soc/pcr_struct.h"
#inc... | 694 |
wdt_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
hw->wdtconfig0.wdt_en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
return (hw->wdtconfig0.wdt_en) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_... | 694 |
wdt_conf_update_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
... | 694 |
wdt_sys_reset_length = length;
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
{
hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
//Config registers are updated asynchronou... | 694 |
wdt_wkey = 0;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
{
hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
{
hw->int_clr_timers.wdt_int_clr = 1;
}
/**
*/
FORCE_INLINE_ATTR void mwdt_ll_set_intr_ena... | 694 |
timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en;
} else {
PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en;
}
}
#ifdef __cplusplus
}
#endif
| 694 |
/*
*/
#pragma once
#include
#include
#include "soc/hwcrypto_reg.h"
#include "hal/aes_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
typedef enum {
ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */
ESP_AES_STATE_BUSY, /* Transform in progress */
ESP_AES_STATE_DONE, /* Transform comple... | 695 |
0 : MODE_DECRYPT_BIT;
/* See TRM for the mapping between keylength and mode bit */
REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2));
}
/**
*/
static inline void aes_ll_write_block(const void *input)
{
uint32_t input_word;
for (int i = 0; i < AES_BLOCK_WORDS; i++) {
memcpy(&inp... | 695 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include // For MIN/MAX
#include
#include
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
#include "hal/assert.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs... | 696 |
flash_ce = 1;
}
/**
*/
static inline void spimem_flash_ll_erase_sector(spi_mem_dev_t *dev)
{
dev->ctrl.val = 0;
dev->cmd.flash_se = 1;
}
/**
*/
static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev)
{
dev->cmd.flash_be = 1;
}
/**
*/
static inline void spimem_flash_ll_suspend(spi_mem_dev_t ... | 696 |
sus_timeout_cnt = 5;
dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en;
}
/**
static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en)
{
dev->flash_sus_ctrl.sus_timeout_cnt = 5;
dev->flash_sus_ctrl.per_end_en = res_check_sus_en;
}
/**
*/
static inline void spimem_... | 696 |
flash_per_wait_en = auto_waiti;
dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti;
}
/**
*/
static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy)
{
// Not supported on this chip.
}
/**
*/
static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
{
... | 696 |
usr_dummy = 0;
spimem_flash_ll_set_buffer_data(dev, buffer, length);
dev->cmd.flash_pp = 1;
}
/**
*/
static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev, bool pe_ops)
{
uint32_t usr_pe = (pe_ops ? 0x60000 : 0x40000);
dev->cmd.val |= usr_pe;
}
/**
*/
static inline bool spimem_flash_ll_ho... | 696 |
val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
break;
case SPI_FLASH_QIO:
ctrl.fread_qio = 1;
break;
case SPI_FLASH_QOUT:
ctrl.fread_quad = 1;
break;
case SPI_FLASH_DIO:
ctrl.fread_dio = 1;
... | 696 |
val = *clock_val;
}
/**
*/
static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_miso = bitlen > 0;
dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0;
}
/**
*/
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
... | 696 |
usr_addr = bitlen ? 1 : 0;
}
/**
*/
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.usr_addr_4byte = 0;
dev->rd_status.wb_mode = extra_addr;
}
/**
*/
static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr)
{
dev->... | 696 |
1 : 0);
dev->ctrl2.cs_setup_time = cs_setup_time - 1;
}
/**
*/
static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
{
uint8_t clock_val = 0;
switch (PCR.mspi_conf.mspi_clk_sel) {
case 0:
clock_val = 32;
break;
case 1:
clock_val = 8;
break;
case 2:
... | 696 |
/*
*/
// The LL layer for I2C register operations
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2c_periph.h"
#include "soc/soc_caps.h"
#include "soc/i2c_struct.h"
#include "soc/pcr_struct.h"
#include "hal/i2c_types.h"
#include "soc/clk_tree_defs.h"
#include "hal/misc.h"
#ifdef... | 697 |
conf_upgate = 1;
}
/**
*/
static inline void i2c_ll_enable_bus_clock(int i2c_port, bool enable)
{
PCR.i2c[i2c_port].i2c_conf.i2c_clk_en = enable;
}
/**
*/
static inline void i2c_ll_reset_register(int i2c_port)
{
PCR.i2c[i2c_port].i2c_conf.i2c_rst_en = 1;
PCR.i2c[i2c_port].i2c_conf.i2c_rst_en = 0;
}
/**... | 697 |
scl_rstart_setup_time = bus_cfg->setup - 1;
hw->scl_stop_setup.scl_stop_setup_time = bus_cfg->setup - 1;
//hold
hw->scl_start_hold.scl_start_hold_time = bus_cfg->hold - 1;
hw->scl_stop_hold.scl_stop_hold_time = bus_cfg->hold - 1;
hw->to.time_out_value = bus_cfg->tout;
hw->to.time_out_en = 1;
}
... | 697 |
rx_fifo_rst = 0;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask)
{
hw->int_clr.val = mask;
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
}
/**
*/
__... | 697 |
stretch_cause) {
case 0:
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
break;
case 1:
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_TX_EMPTY;
break;
case 2:
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_RX_FULL;
break;
case 3:
*stretch_cause = I2C_... | 697 |
val = cmd.val;
}
/**
*/
static inline void i2c_ll_master_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
{
hw->scl_rstart_setup.scl_rstart_setup_time = start_setup;
hw->scl_start_hold.scl_start_hold_time = start_hold - 1;
}
/**
*/
static inline void i2c_ll_master_set_stop_timing(i2c_dev_t *... | 697 |
tx_lsb_first = tx_mode;
hw->ctr.rx_lsb_first = rx_mode;
}
/**
*/
static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sda_hold)
{
*sda_hold = hw->sda_hold.sda_hold_time;
*sda_sample = hw->sda_sample.sda_sample_time;
}
/**
*/
static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t... | 697 |
trans_start = 1;
}
/**
*/
static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
{
*setup_time = hw->scl_rstart_setup.scl_rstart_setup_time;
*hold_time = hw->scl_start_hold.scl_start_hold_time + 1;
}
/**
*/
static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *set... | 697 |
fifo_addr_cfg_en = addr_wr_en;
}
/**
*/
static inline void i2c_ll_master_set_filter(i2c_dev_t *hw, uint8_t filter_num)
{
if (filter_num > 0) {
hw->filter_cfg.scl_filter_thres = filter_num;
hw->filter_cfg.sda_filter_thres = filter_num;
hw->filter_cfg.scl_filter_en = 1;
hw->filter_cf... | 697 |
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
}
/**
*/
static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_clk)
{
// src_clk : (1) for RTC_CLK, (0) for XTAL
PCR.i2c[I2C_LL_GET_NUM(hw)].i2c_sclk_conf.i2c_sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0;... | 697 |
slv_tx_auto_start_en = slv_ex_auto_en;
}
/**
*/
static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev)
{
return &dev->int_status;
}
/**
*/
static inline void i2c_ll_slave_enable_scl_stretch(i2c_dev_t *dev, bool enable)
{
dev->scl_stretch_conf.slave_scl_stretch_en = enable;
}
/**
*/
_... | 697 |
2)
*/
static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int low_period, int wait_high_period)
{
hw->scl_low_period.scl_low_period = low_period;
hw->scl_high_period.scl_high_period = high_period;
hw->scl_high_period.scl_wait_high_period = wait_high_period;
}
/**
*/
static inlin... | 697 |
end_detect_int_st) {
*event = I2C_INTR_EVENT_END_DET;
} else if (int_sts.trans_complete_int_st) {
*event = I2C_INTR_EVENT_TRANS_DONE;
} else {
*event = I2C_INTR_EVENT_ERR;
}
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_ev... | 697 |
val = UINT32_MAX;
hw->int_ena.val = I2C_LL_MASTER_RX_INT;
}
/**
*/
static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT);
}
/**
*/
__attribute__((always_inline))
static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
{
hw->int_ena.val &= (~I2C_... | 697 |
scl_high_period = hight_period - 10;
hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.scl_high_period;
}
/**
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*... | 697 |
/*
*/
#pragma once
#include /* Required for NULL constant */
#include
#include
#include "hal/gdma_types.h"
#include "soc/gdma_struct.h"
#include "soc/gdma_reg.h"
#include "soc/soc_etm_source.h"
#include "soc/pcr_struct.h"
#include "soc/retention_periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GDMA_... | 698 |
ena.val &= ~mask;
}
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->in_intr[channel].clr.val = mask;
}
/**
*/
static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t chann... | 698 |
in.in_conf0.in_rst = 1;
dev->channel[channel].in.in_conf0.in_rst = 0;
}
/**
*/
static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->channel[channel].in.infifo_status.val & 0x01;
}
/**
*/
static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, ... | 698 |
in.in_link.inlink_start = 1;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].in.in_link.inlink_stop = 1;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
{
de... | 698 |
in.in_err_eof_des_addr.val;
}
/**
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->channel[channel].in.in_dscr.val;
}
/**
*/
static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{... | 698 |
in.in_conf0.in_etm_en = enable;
}
///////////////////////////////////// TX /////////////////////////////////////////
/**
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
if (raw) {
return dev->out_intr[channel].raw.val;... | 698 |
out.out_conf1.out_check_owner = enable;
}
/**
*/
static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->channel[channel].out.out_conf0.out_data_burst_en = enable;
}
/**
*/
static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, boo... | 698 |
out.outfifo_status.val & 0x01;
}
/**
*/
static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->channel[channel].out.outfifo_status.val & 0x02;
}
/**
*/
static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_lev... | 698 |
out.out_link.outlink_stop = 1;
}
/**
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_link.outlink_restart = 1;
}
/**
*/
static inline bool gdma_ll_tx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
return dev->c... | 698 |
out.out_peri_sel.peri_out_sel = periph_id;
}
/**
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
{
dev->channel[channel].out.out_peri_sel.peri_out_sel = GDMA_LL_INVALID_PERIPH_ID;
}
/**
*/
static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel,... | 698 |
/*
*/
#pragma once
#include
#include "hal/ieee802154_common_ll.h"
#define IEEE802154_TXPOWER_VALUE_MAX 20
#define IEEE802154_TXPOWER_VALUE_MIN -24
#define IEEE802154_TXPOWER_INDEX_MIN 0
#define IEEE802154_RSSI_COMPENSATION_VALUE 10
| 699 |
/*
*/
// The LL layer of the USB-serial-jtag controller
#pragma once
#include
#include "esp_attr.h"
#include "soc/pcr_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
//The in and out endpoints are this long.
#define USB_SERIAL_JTAG_PACK... | 700 |
int_ena.val |= mask;
}
/**
*/
static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask)
{
USB_SERIAL_JTAG.int_ena.val &= (~mask);
}
/**
*/
static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void)
{
return USB_SERIAL_JTAG.int_st.val;
}
/**
*/
static inline __attribute__((always_inline))... | 700 |
USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
}
return i;
}
/**
*/
static inline int usb_serial_jtag_ll_rxfifo_data_available(void)
{
return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail;
}
/**
*/
static inline int usb_serial_jtag_ll_txfifo_w... | 700 |
usb_device_clk_en = clk_en;
}
/**
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void)
{
PCR.usb_device_conf.usb_device_rst_en = 1;
PCR.usb_device_conf.usb_device_rst_en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void)
{
return (PCR.usb_device_conf.usb_device_... | 700 |
/*
*/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/ana_cmpr_struct.h"
#define ANALOG_CMPR_LL_GET_HW(unit) (&ANALOG_CMPR[unit])
#define ANALOG_CMPR_LL_EVENT_CROSS (1 pad_comp_config->xpd_comp = en;
}
/**
*/
__attribute__((always_inline))
static inline void analog_cmpr... | 701 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include_next "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
uint32_t efuse_hal_get_chip_revision(void);
/**
*/
void efuse_hal_set_timing(uint32_t apb_freq_hz);
/**
*/
void efuse_hal_read(void);
/**
... | 702 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash Encryption.
#include
#include
#include "soc/hp_system_reg.h"
#include "soc/xts_aes_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Choose type of chip you want to encrypt manully
typedef enum
... | 703 |
= 0x3) {
}
}
/**
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
REG_SET_BIT(XTS_AES_DESTROY_REG(0), XTS_AES_DESTROY);
}
/**
*/
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
{
return ((address % length) == 0) ? true : false;
}
#ifdef __cplusplus
}
#endif
| 703 |
/*
*/
/**
*/
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/apb_saradc_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
... | 704 |
saradc_ctrl.saradc_saradc2_pwdet_drv = force;
}
#ifdef __cplusplus
}
#endif
| 704 |
/*
*/
// The LL layer for ESP32-H2 LP CLKRST register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/lp_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(lp_clkrst_dev_t *hw, bool en)... | 705 |
lp_bletimer_div_num = value;
}
__attribute__((always_inline))
static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw)
{
return hw->lpperi.lp_bletimer_div_num;
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32... | 705 |
/*
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/hal_utils.h"
#include "soc/pcr_struct.h"
#include "soc/parl_io_struct.h"
#include "hal/parlio_types.h"
#define PARLIO_LL_RX_MAX_BY... | 706 |
parl_clk_rx_conf.parl_clk_rx_en = en;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_rx_eof_cond_t cond)
{
dev->rx_genrl_cfg.rx_eof_gen_sel = cond;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_start(parl_io_dev_t... | 706 |
end_inc) {
submode += 1;
}
}
if (!start_inc) {
submode += step;
}
dev->rx_mode_cfg.rx_smp_mode_sel = 1;
dev->rx_mode_cfg.rx_pulse_submode_sel = submode;
dev->rx_mode_cfg.rx_ext_en_inv = pulse_inv;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_... | 706 |
rx_bus_wid_sel = width_sel;
}
/**
*/
static inline void parlio_ll_rx_reset_fifo(parl_io_dev_t *dev)
{
dev->fifo_cfg.rx_fifo_srst = 1;
dev->fifo_cfg.rx_fifo_srst = 0;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32_t line_num)
{
dev... | 706 |
rx_reg_update);
}
///////////////////////////////////TX Unit///////////////////////////////////////
/**
*/
static inline void parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
{
(void)dev;
uint32_t clk_sel = 0;
switch (src) {
case PARLIO_CLK_SRC_XTAL:
clk_sel = 0;
... | 706 |
parl_clk_tx_conf.parl_tx_rst_en = 1;
PCR.parl_clk_tx_conf.parl_tx_rst_en = 0;
}
/**
*/
__attribute__((always_inline))
static inline void parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
{
(void)dev;
PCR.parl_clk_tx_conf.parl_clk_tx_en = en;
}
/**
*/
__attribute__((always_inline))
static inline voi... | 706 |
tx_clk_o_inv = edge;
}
/**
*/
static inline void parlio_ll_tx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
{
dev->tx_data_cfg.tx_data_order_inv = order;
}
/**
*/
static inline void parlio_ll_tx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
{
uint32_t width_sel = 0;
switch (w... | 706 |
tx_ready;
}
////////////////////////////////////Interrupt////////////////////////////////////////////////
/**
*/
static inline void parlio_ll_enable_interrupt(parl_io_dev_t *dev, uint32_t mask, bool enable)
{
if (enable) {
dev->int_ena.val |= mask;
} else {
dev->int_ena.val &= ~mask;
}
}
... | 706 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/lpwdt_ll.h"
typedef lp_wdt_dev_t rwdt_dev_t;
#define RWDT_DEV_GET() &LP_WDT
#define rwdt_ll_enable(hw... | 707 |
/*
*/
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "esp_attr.h"
#include "hal/misc.h"
#include "hal/uart_types.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/pcr_struct.h"... | 708 |
uart1_##reg_suffix, uart1_##field_suffix, (val)) \
}
#define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? \
HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \
HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix))
#defin... | 708 |
clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
{
typeof(hw->clkdiv_sync) div_reg;
... | 708 |
val;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{
for (int i = 0; i fifo.rxfifo_rd_byte;
}
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involv... | 708 |
rxfifo_cnt;
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
{
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
{
hw->conf0_sync.stop_bit_num = stop_bit;
uart_ll_update(hw);
}
... | 708 |
rxfifo_full_thrhd = full_thrhd;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
{
hw->conf1.txfifo_empty_thrhd = empty_thrhd;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
{
hw->idle_conf_sync.rx_idle_thrhd = ... | 708 |
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs;
hw->hwfc_conf_sync.rx_flow_en = 1;
} else {
hw->hwfc_conf_sync.rx_flow_en = 0;
}
if (flow_ctrl & UART_HW_FLOWCTRL_CTS) {
hw->conf0_sync.tx_flow_en = 1;
} else {
hw->conf0_sync... | 708 |
xonoff_del = 1;
hw->swfc_conf0_sync.sw_flow_con_en = 1;
hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw-... | 708 |
bit_num = data_bit;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
{
hw->conf0_sync.sw_rts = level & 0x1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
{
hw->conf1.sw_dtr = leve... | 708 |
irda_en = 0;
hw->rs485_conf_sync.dl0_en = 1;
hw->rs485_conf_sync.dl1_en = 1;
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
{
// Enable receiver, sw_rts = 1 generates low level on RTS pin
hw->conf0_sync.... | 708 |
rs485rxby_tx_en = 1;
hw->rs485_conf_sync.dl0_en = 1;
hw->rs485_conf_sync.dl1_en = 1;
hw->conf0_sync.sw_rts = 0;
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
{
hw->rs485_conf_sync.rs485_en = 0;
hw->rs485_conf_syn... | 708 |
active_threshold + UART_LL_MIN_WAKEUP_THRESH;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
{
*data_bit = (uart_word_length_t)hw->conf0_sync.bit_num;
}
/**
*/
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
{
return ((hw->status.txfifo_cnt =... | 708 |
val = hw->conf0_sync.val;
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0;
conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0;
conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0;
hw->conf0_... | 708 |
rx_tout_en = 0;
}
uart_ll_update(hw);
}
/**
*/
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->tout_conf_sync.rx_tout_en > 0) {
tout_thrd = hw->tout_conf_sync.rx_tout_thrhd;
}
return tout_thrd;
}
/**
*/
FORCE_INLINE_ATTR uint16_t ua... | 708 |
highpulse_min_cnt;
}
/**
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
{
return hw->lowpulse.lowpulse_min_cnt;
}
/**
*/
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
{
REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
REG_SET_BIT(UART_SWFC_CONF0... | 708 |
err_wr_mask = discard ? 1 : 0;
uart_ll_update(hw);
}
#ifdef __cplusplus
}
#endif
| 708 |
/*
*/
// The LL layer for ESP32-H2 MODEM SYSCON register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "hal/assert.h"
#include "modem/modem_syscon_struct.h"
#include "hal/modem_clock_types.h"
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void modem... | 709 |
clk_zb_mac_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_modem_sec_en = en;
hw->clk_conf.clk_modem_sec_ecb_en = en;
hw->clk_conf.clk_modem_sec_ccm_en = en;
hw->clk_conf.clk_modem_sec_bah_en = en;
... | 709 |
clk_etm_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_modem_sec_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw)
{
hw->... | 709 |
rst_btmac = 1;
hw->modem_rst_conf.rst_btmac = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btbb_apb = 1;
hw->modem_rst_conf.rst_btbb_apb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_... | 709 |
rst_modem_bah = 1;
hw->modem_rst_conf.rst_modem_sec = 1;
hw->modem_rst_conf.rst_modem_ecb = 0;
hw->modem_rst_conf.rst_modem_ccm = 0;
hw->modem_rst_conf.rst_modem_bah = 0;
hw->modem_rst_conf.rst_modem_sec = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_ble_timer(modem_... | 709 |
val = hw->clk_conf1.val & ~mask;
}
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_16m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_16m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_32m_clock(modem_syscon_dev_t *hw, bool e... | 709 |
clk_bt_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_force_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1_force_on.clk_fe_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en)
{
hw->c... | 709 |
/*
*/
/
/
// The LL layer for SPI register operations
#pragma once
#include //for abs()
#include
#include "esp_attr.h"
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "soc/lldesc.h"
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/spi_types.h"
#include "soc/pcr... | 710 |
cs_hold_time = 0;
//use all 64 bytes of the buffer
hw->user.usr_miso_highpart = 0;
hw->user.usr_mosi_highpart = 0;
//Disable unneeded ints
hw->slave.val = 0;
hw->user.val = 0;
PCR.spi2_clkm_conf.spi2_clkm_sel = 0;
hw->dma_conf.val = 0;
hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
... | 710 |
val &= ~SPI_LL_UNUSED_INT_MASK;
}
/**
*/
static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
{
hw->clock.val = 0;
hw->user.val = 0;
hw->ctrl.val = 0;
hw->user.doutdin = 0;
hw->user.sio = 0;
hw->slave.soft_reset = 1;
hw->slave.soft_reset = 0;
hw->slave.slave_mode = 1;
}
/**
*/
sta... | 710 |
soft_reset = 0;
}
/**
*/
static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
{
hw->dma_conf.buf_afifo_rst = 1;
hw->dma_conf.buf_afifo_rst = 0;
}
/**
*/
static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw)
{
hw->dma_conf.rx_afifo_rst = 1;
hw->dma_conf.rx_afifo_rst = 0;
}
/**
*/
static ... | 710 |
dma_tx_ena = enable;
}
/**
*/
static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable)
{
hw->dma_conf.rx_eof_en = enable;
}
/*
**/
/**
*/
static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen)
{
for (int x = 0; x data_buf[(x / 32)].buf0 = ... | 710 |
buf0;
int len = bitlen - x;
if (len > 32) {
len = 32;
}
memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8);
}
}
/**
*/
static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len)
{
while (len > 0) {
uint32_t word = hw-... | 710 |
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