text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
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/*
*/
/
/
#pragma once
#include "soc/lp_aon_struct.h"
#include "soc/pmu_struct.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTCIO_LL_GPIO_NUM_OFFSET 7 // rtcio 0-7 correspond to gpio 7-14
typedef enum {
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
... | 728 |
gpio_mux, gpio_mux_sel);
sel_mask &= ~BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
}
}
/**
*/
static inline void rtcio_ll_force_hold_enable(int rtcio_num)
{
LP_AON.gpio_hold0.gpio_hold0 |= BIT(rtcio_num + RTCIO_LL_GPIO_NUM_OFFSET);
}
/**
*/
static ... | 728 |
/*
*/
// The LL layer for ESP32-H2 PAU(Power Assist Unit) register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/pau_reg.h"
#include "soc/pau_struct.h"
#include "hal/pau_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline __attribute__((always_inl... | 729 |
start = 0;
}
static inline __attribute__((always_inline)) void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_0_addr.val = (uint32_t)link_addr;
}
static inline __attribute__((always_inline)) void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link... | 729 |
val;
}
static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
{
return dev->int_raw.val;
}
static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
{
return dev->int_st.val;
}
static inline __attribute__((always_inlin... | 729 |
done_int_clr = 1;
}
static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
{
dev->int_clr.error_int_clr = 1;
}
#ifdef __cplusplus
}
#endif
| 729 |
/*
*/
// The LL layer for I2S register operations
/
/
#pragma once
#include
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/pcr_struct.h"
#include "hal/i2s_types.h"
#include "hal/hal_utils.h"
#ifdef __cplusplus
extern "C" {
#endif
#define I2S_L... | 730 |
i2s_conf.i2s_clk_en = enable;
}
/**
*/
static inline void i2s_ll_reset_register(int i2s_id)
{
(void)i2s_id;
PCR.i2s_conf.i2s_rst_en = 1;
PCR.i2s_conf.i2s_rst_en = 0;
}
/**
*/
static inline void i2s_ll_enable_core_clock(i2s_dev_t *hw, bool enable)
{
(void)hw;
(void)enable;
// No need to do an... | 730 |
i2s_rx_clkm_conf.i2s_mclk_sel = 1;
}
/**
*/
static inline void i2s_ll_tx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
{
hw->tx_conf.tx_slave_mod = slave_en;
}
/**
*/
static inline void i2s_ll_rx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
{
hw->rx_conf.rx_slave_mod = slave_en;
}
/**
*/
static inline void i... | 730 |
i2s_tx_clkm_conf.i2s_tx_clkm_sel = 1;
break;
case I2S_CLK_SRC_PLL_64M:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 2;
break;
case I2S_CLK_SRC_EXTERNAL:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 3;
break;
default:
HAL_ASSERT(false && "unsupported clock source");
... | 730 |
tx_bck_div_num = val - 1;
}
/**
*/
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{
(void)hw;
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, div_int);
typeof(PCR.i2s_tx_clkm_div_conf) div = {};
... | 730 |
mclk_div->denominator - mclk_div->numerator : mclk_div->numerator;
div_x = mclk_div->denominator / div_z - 1;
div_y = mclk_div->denominator % div_z;
}
i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integer, div_x, div_y, div_z, div_yn1);
}
/**
*/
static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_... | 730 |
tx_update = 1;
while (hw->tx_conf.tx_update);
hw->tx_conf.tx_start = 1;
}
/**
*/
static inline void i2s_ll_rx_start(i2s_dev_t *hw)
{
// Have to update registers before start
hw->rx_conf.rx_update = 1;
while (hw->rx_conf.rx_update);
hw->rx_conf.rx_start = 1;
}
/**
*/
static inline void i2s_ll... | 730 |
tx_tdm_chan_bits = chan_bit - 1;
}
/**
*/
static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit)
{
hw->rx_conf1.rx_bits_mod = data_bit - 1;
hw->rx_conf1.rx_tdm_chan_bits = chan_bit - 1;
}
/**
*/
static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_samp... | 730 |
tx_tdm_tot_chan_num = total_num - 1;
}
/**
*/
static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
{
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1;
}
/**
*/
static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
{
uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val... | 730 |
rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
case I2S_STD_SLOT_RIGHT:
chan_mask |= 0x02;
break;
case I2S_STD_SLOT_BOTH:
chan_mask |= 0x03;
... | 730 |
pcm2pdm_conv_en = false;
}
/**
*/
static inline void i2s_ll_rx_enable_tdm(i2s_dev_t *hw)
{
hw->rx_conf.rx_pdm_en = false;
hw->rx_conf.rx_tdm_en = true;
}
/**
*/
static inline void i2s_ll_tx_enable_std(i2s_dev_t *hw)
{
i2s_ll_tx_enable_tdm(hw);
}
/**
*/
static inline void i2s_ll_rx_enable_std(i2s_dev_t... | 730 |
tx_pdm_lp_in_shift = sig_scale;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_sinc_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
{
hw->tx_pcm2pdm_conf.tx_pdm_sinc_in_shift = sig_scale;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_sd_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
{
hw->tx_pcm2pdm... | 730 |
tx_pdm_sigmadelta_dither2 = dither2;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_over_sample_ratio(i2s_dev_t *hw, uint32_t ovr)
{
hw->tx_pcm2pdm_conf.tx_pdm_sinc_osr2 = ovr;
}
/**
*/
static inline void i2s_ll_tx_set_pdm_fpfs(i2s_dev_t *hw, uint32_t fp, uint32_t fs)
{
hw->tx_pcm2pdm_conf1.tx_pdm_fp = fp;
... | 730 |
tx_pcm_bypass = !pcm_cfg;
}
/**
*/
static inline void i2s_ll_rx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg)
{
hw->rx_conf.rx_pcm_conf = pcm_cfg;
hw->rx_conf.rx_pcm_bypass = !pcm_cfg;
}
/**
*/
static inline void i2s_ll_tx_enable_left_align(i2s_dev_t *hw, bool ena)
{
hw->tx_conf.tx_left_align ... | 730 |
tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
*/
static inline void i2s_ll_set_single_data(i2s_dev_t *hw, uint32_t data)
{
hw->conf_single_data.val = data;
}
/**
*/
static inline void i2s_ll_tx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena)
{
hw->tx_conf.tx_mono = mono_ena;
hw->tx_conf.tx_chan_equal = mono... | 730 |
tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 1 : 2;
} else {
hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 4 : 3;
}
} else {
hw->tx_conf.tx_chan_mod = 0;
}
}
/**
*/
static inline void i2s_ll_tx_pdm_line_mode(i2s_dev_t *hw, i2s_pdm_tx_line_mode_t line_mode)
{
hw->tx... | 730 |
/*
*/
/
/
// The LL for temperature sensor
#pragma once
#include
#include
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/pcr_struct.h"
#include "soc/interrupts.h"
#include... | 731 |
saradc_apb_tsens_ctrl.saradc_tsens_pu = enable;
}
/**
*/
static inline void temperature_sensor_ll_bus_clk_enable(bool enable)
{
PCR.tsens_clk_conf.tsens_clk_en = enable;
}
/**
*/
static inline void temperature_sensor_ll_reset_module(void)
{
PCR.tsens_clk_conf.tsens_rst_en = 1;
PCR.tsens_clk_conf.tsens_r... | 731 |
saradc_apb_tsens_ctrl, saradc_tsens_out);
}
/**
*/
static inline uint32_t temperature_sensor_ll_get_offset(void)
{
return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC);
}
/**
*/
static inline uint32_t temperature_sensor_ll_get_clk_div(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.saradc_apb_t... | 731 |
tsens_wake, saradc_wakeup_th_low, th_low);
}
/**
*/
static inline void temperature_sensor_ll_set_th_high_val(uint8_t th_high)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_high, th_high);
}
/**
*/
static inline void temperature_sensor_ll_enable_intr(bool enable)
{
APB_SARADC.sarad... | 731 |
/*
*/
// The LL layer for ESP32-H2 LP_AON register operations
#pragma once
#include
#include "soc/soc.h"
#include "soc/lp_aon_struct.h"
#include "hal/misc.h"
#include "esp32h2/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
{
return HA... | 732 |
ext_wakeup_cntl, ext_wakeup_sel);
}
/**
*/
static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
{
if (dslp) {
REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
} else {
REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */... | 732 |
/*
*/
// The LL layer for LEDC register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "hal/ledc_types.h"
#include "soc/ledc_struct.h"
#include "soc/ledc_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "hal/assert.h"... | 733 |
timer[timer_sel].conf.rst = 1;
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
}
/**
*/
static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1;
}
/**
*/
static inline void ledc_ll_timer_r... | 733 |
timer[timer_sel].conf.tick_sel == 0);
*clk_src = LEDC_SCLK;
}
/**
*/
static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution)
{
hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res = duty_resolution;
}
/**
*/
static inline... | 733 |
channel[channel_num].hpoint.hpoint;
}
/**
*/
static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_val)
{
hw->channel_group[speed_mode].channel[channel_num].duty.duty = duty_val channel_group[speed_mode].channel[channel_num].duty_rd.duty_r >... | 733 |
channel[channel_num].wr.gamma_duty_cycle = duty_cycle;
}
/**
*/
static inline void ledc_ll_set_duty_scale(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_scale)
{
hw->channel_gamma_group[speed_mode].channel[channel_num].wr.gamma_scale = duty_scale;
}
/**
*/
static inline void l... | 733 |
gamma_conf[channel_num].gamma_entry_num = range_num;
}
/**
*/
static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num)
{
*range_num = hw->channel_gamma_conf_group[speed_mode].gamma_conf[channel_num].gamma_entry_num;
}
/**
*/
static inli... | 733 |
channel[channel_num].conf0.sig_out_en = sig_out_en;
}
/**
*/
static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool duty_start)
{
hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start;
}
/**
*/
__attribute__((always_inline))
... | 733 |
val;
uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
*intr_status = (value >> int_en_base) & 0xff;
}
/**
*/
static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num)
{
uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
hw->... | 733 |
/*
*/
#pragma once
#include
#include
#include "soc/systimer_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no gc... | 734 |
systimer_conf.systimer_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_... | 734 |
val |= 1 conf.val &= ~(1 conf.val |= 1 conf.val &= ~(1 unit_op[counter_id].timer_unit_update = 1;
}
__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id)
{
return dev->unit_op[counter_id].timer_unit_value_valid;
}
__attribute__((always_inlin... | 734 |
val = 0x01;
}
/ Alarm /
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
{
dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF;
}
__attribute__((alwa... | 734 |
target_period_mode = 1;
}
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
{
HAL_ASSERT(period target_conf[alarm_id].target_period = period;
}
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(s... | 734 |
/*
*/
// The LL layer for ESP32-H2 LP_Timer register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_aon_reg.h"
#include "hal/lp_timer_types.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_ala... | 735 |
update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.alarm = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow = 1;
}
#ifdef __cplusplus
}
#endif
| 735 |
/*
*/
#pragma once
#include
#include "riscv/csr.h"
/*fast gpio*/
#define CSR_GPIO_OEN_USER 0x803
#define CSR_GPIO_IN_USER 0x804
#define CSR_GPIO_OUT_USER 0x805
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
{
RV_W... | 736 |
/*
*/
// The LL layer for Cache register operations
#pragma once
#include
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32h2/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //T... | 737 |
Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask... | 737 |
CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
}
/**
*/
__attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
bool valid = false;
uint32_t vaddr_end = vaddr_start + l... | 737 |
/*
*/
// The HAL layer for PMU
#pragma once
#include "soc/soc_caps.h"
#include "hal/pmu_ll.h"
#include "hal/pmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
pmu_dev_t *dev;
} pmu_hal_context_t;
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_w... | 738 |
/*
*/
#include
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/* This LL is currently unused for ESP32-H2 - cleanup is TODO ESP32-H2 IDF-2375 */
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{
abort();
}
static inline void mpu_ll_set_region_rw(uint32_t addr)... | 739 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include "gpspi_flash_ll.h"
#include "spimem_flash_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
... | 740 |
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (8)
typedef union {
gpspi_flash_ll_clock_reg_t gpspi;
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_... | 740 |
/*
*/
/
/
#pragma once
#include
#include "hal/assert.h"
#include "soc/gpio_ext_struct.h"
// the max window size is expected to be 64, but due to a hardware issue, we need to limit it to 63
#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 63
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void gpio_ll_gli... | 741 |
/*
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void etm_ll_enable_bus_clock(int... | 742 |
/*
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/gpio_ext_struct.h"
#include "soc/soc_etm_source.h"
#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch))
#define GPIO_LL... | 743 |
etm_chn_event_en = enable;
}
/**
*/
static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
{
int g_p = gpio_num / 4;
int g_idx = gpio_num % 4;
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
reg_val &= ~(0x07 etm_task_pn_cfg[g_p].val = reg_val;
}
... | 743 |
/*
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
#include
#include "hal/misc.h"
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "soc/ef... | 744 |
wdt_en = 1;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
{
hw->config0.wdt_en = 0;
}
/**
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
{
return (hw->config0.wdt_en) ? true : false;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_sta... | 744 |
val = timeout_ticks;
break;
default:
abort();
}
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->config0.w... | 744 |
wdt_flashboot_mod_en = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
hw->config0.wdt_appcpu_rese... | 744 |
val = LP_WDT_WKEY_VALUE;
}
/**
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
{
hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
}
/**
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
{
return (hw->int_st.lp_wdt_int_st) ? true : false;
}
/**
*/
FORCE_... | 744 |
/*
*/
#pragma once
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Dev... | 745 |
= 0;
}
static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
{
// DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);// ESP32H2-TODO: IDF-6400
// DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
{
... | 746 |
/*
*/
#pragma once
#include
#include
#include "hal/assert.h"
#include "soc/ecdsa_reg.h"
#include "soc/pcr_struct.h"
#include "hal/ecdsa_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
ECDSA_PARAM_R,
ECDSA_PARAM_S,
ECDSA_PARAM_Z,
ECDSA_PARAM_QAX,
ECDSA_PARAM_QAY
} ecdsa_l... | 747 |
ecdsa_conf.ecdsa_rst_en = 1;
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
/**
*/
static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
{
switch (type) {
case ECDSA_INT_CALC_DONE:
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 1);
break;
case ECDSA_INT_SHA_... | 747 |
/*
*/
#pragma once
#include
#include
#include "hal/assert.h"
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"
#include "soc/pcr_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ECC_PARAM_PX = 0x0,
ECC_PARAM_PY,
ECC_PARAM_K,
ECC_PARAM_QX,
ECC_PARAM_QY,
ECC_PARAM_QZ,
}... | 748 |
/*
*/
#pragma once
#include
#include
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/adc_types.h"
#inc... | 749 |
APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
/*
Oneshot
*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5)
/*
DMA
*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_N... | 749 |
> offset)); // Clear old data
tab |= ((uint32_t)(pattern.val & 0x3F) > offset; // Fill in the new data
APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = tab; // Write back
} else {
tab = APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt... | 749 |
saradc_ctrl2.saradc_saradc_sar1_inv = inv_en; // Enable / Disable ADC data invert
}
}
/**
*/
static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
{
APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
}
/**
*/
static inline void adc_ll_digi_trigger_enable(void)
{
APB_SARADC.sarad... | 749 |
saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
APB_SARADC.sara... | 749 |
saradc_filter_ctrl0.saradc_apb_saradc_filter_channel0 = ((adc_n + 1) > 8;
uint8_t lsb = param & 0xFF;
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
}
/*
Oneshot Read
*/
/**
*/
static inline voi... | 749 |
saradc_onetime_sample.saradc_saradc_onetime_start = val;
}
/**
*/
static inline void adc_oneshot_ll_clear_event(uint32_t event_mask)
{
APB_SARADC.saradc_int_clr.val |= event_mask;
}
/**
*/
static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
{
return (APB_SARADC.saradc_int_raw.val & event_mask);... | 749 |
saradc_onetime_sample.saradc_saradc1_onetime_sample = 1;
}
/**
*/
static inline void adc_oneshot_ll_disable_all_unit(void)
{
APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0;
APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0;
}
/**
*/
static inline void adc_oneshot_ll_set_... | 749 |
/*
*/
/
/
// The LL layer for ESP32-H2 PCNT register operations
#pragma once
#include
#include
#include
#include "soc/pcnt_struct.h"
#include "hal/pcnt_types.h"
#include "soc/pcr_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PCNT_LL_GET_HW(num) (((num) == 0) ? (&PCNT) : NULL)
#define PCNT_LL_... | 750 |
conf0.ch0_hctrl_mode = high_act;
hw->conf_unit[unit].conf0.ch0_lctrl_mode = low_act;
} else {
hw->conf_unit[unit].conf0.ch1_hctrl_mode = high_act;
hw->conf_unit[unit].conf0.ch1_lctrl_mode = low_act;
}
}
/**
*/
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_... | 750 |
val = status;
}
/**
*/
static inline void pcnt_ll_enable_high_limit_event(pcnt_dev_t *hw, uint32_t unit, bool enable)
{
hw->conf_unit[unit].conf0.thr_h_lim_en = enable;
}
/**
*/
static inline void pcnt_ll_enable_low_limit_event(pcnt_dev_t *hw, uint32_t unit, bool enable)
{
hw->conf_unit[unit].conf0.thr_l_li... | 750 |
conf2.val = conf2_reg.val;
}
/**
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim = value;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
*/
static in... | 750 |
val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim ;
return value;
}
/**
*/
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres ... | 750 |
conf0.filter_thres = filter_val;
}
/**
*/
static inline uint32_t pcnt_ll_get_glitch_filter_thres(pcnt_dev_t *hw, uint32_t unit)
{
return hw->conf_unit[unit].conf0.filter_thres ;
}
/**
*/
static inline void pcnt_ll_enable_glitch_filter(pcnt_dev_t *hw, uint32_t unit, bool enable)
{
hw->conf_unit[unit].conf0.f... | 750 |
/*
*/
/
/
// The Lowlevel layer for SPI Flash
#pragma once
#include
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include // For MIN/MAX
#include
#include
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
//NOTE: These macros ... | 751 |
rx_seg_trans_clr_en = 1;
// dev->dma_conf.dma_seg_trans_en = 0;
}
/**
*/
static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
{
return (dev->cmd.usr == 0);
}
/**
*/
static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
{
// if (((intptr_t)buffe... | 751 |
update = 1;
while (dev->cmd.update);
dev->cmd.usr = 1;
}
/**
*/
static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
{
// Not supported on GPSPI
}
/**
*/
static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
{
dev->ctrl.hold_pol = pol_val;
}
/**
*/
static inline ... | 751 |
val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
case SPI_FLASH_SLOWRD:
... | 751 |
val = *clock_val;
}
/**
*/
static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_miso = bitlen > 0;
if (bitlen) {
dev->ms_dlen.ms_data_bitlen = bitlen - 1;
}
}
/**
*/
static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
{... | 751 |
usr_addr = bitlen ? 1 : 0;
}
/**
*/
static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
// The blank region should be all ones
// uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
// dev->addr = (addr addr = addr;
}
/**
*/
static inline voi... | 751 |
1 : 0);
dev->user1.cs_setup_time = cs_setup_time - 1;
}
/**
*/
static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
{
uint32_t div_parameter;
// See comments of `clock` in `spi_struct.h`
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((... | 751 |
/*
*/
/
/
#pragma once
#include
#include "soc/lp_analog_peri_struct.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_brownout.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void brownout_ll_enable_flash_power_down(bool enable)
{
LP_ANA_PERI.bod_mode0_cntl.bod_mode0_close_flash_ena = enab... | 752 |
bod_mode0_intr_ena = bod_enable;
}
/**
*/
static inline void brownout_ll_set_intr_wait_cycles(uint8_t cycle)
{
LP_ANA_PERI.bod_mode0_cntl.bod_mode0_intr_wait = cycle;
}
/**
*/
static inline void brownout_ll_intr_enable(bool enable)
{
LP_ANA_PERI.int_ena.bod_mode0_int_ena = enable;
}
/**
*/
static inline v... | 752 |
/*
*/
/
/
// The LL layer for ESP32-H2 GPIO register operations
#pragma once
#include
#include
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/pmu_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/... | 753 |
val & bit_mask) >> gpio_num;
*od = hw->pin[gpio_num].pad_driver;
*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
}
/**
*/
static inline voi... | 753 |
If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_M... | 753 |
status_w1tc = mask;
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
{
// Less than 32 GPIOs on ESP32-H2 Do nothing.
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, g... | 753 |
enable_w1tc = (0x1 enable_w1ts.enable_w1ts = (0x1 pin[gpio_num].pad_driver = 0;
}
/**
*/
static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
{
hw->pin[gpio_num].pad_driver = 1;
}
/**
*/
__attribute__((always_inline))
static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num... | 753 |
gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num];
}
/**
*/
static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
{
LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num];
}
/**
*/
__attribute__((always_inline))
static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_... | 753 |
oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_func_sel(hw, gpio_num, func);
}
/**
*/
static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift);
}
/**
*/
static inline vo... | 753 |
imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
}
/**
*/
static inline void gpio_ll_force_unhold_all(void)
{
// WT flags, they get self-cleared after the configuration is done
PMU.imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
PMU.imm.pad_hold_all.tie_... | 753 |
ext_wakeup_cntl, ext_wakeup_sel);
return wakeup_sel_mask & BIT(gpio_num - 7);
}
#ifdef __cplusplus
}
#endif
| 753 |
/*
*/
#pragma once
#include
#include
#include
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/hwcrypto_periph.h"
#include "soc/dport_reg.h"
#include "soc/mpi_periph.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
static inline void mpi_ll_enable_bus_clock(bool e... | 754 |
..) (void)__DECLARE_RCC_ATOMIC_ENV; mpi_ll_reset_register(__VA_ARGS__)
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;
}
static inline void mpi_ll_clear_power_control_bit(void)
{
REG_CLR_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD);
}
static inline void mpi_ll_set_power_c... | 754 |
If num_words is higher than the number of words (n) in the bignum then
these additional words will be zeroed in the memory buffer.
*/
static inline void mpi_ll_write_to_mem_block(mpi_param_t param, size_t offset, const uint32_t* p, size_t n, size_t num_words)
{
uint32_t mem_base = MPI_LL_BLOCK_BASES[param] ... | 754 |
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