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*/
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0))
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (BIT(0))
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x1
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG ... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
#defi... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S))
#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V 0x... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK (BIT(0))
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_M (BIT(0))
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V 0x1
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S 0
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG ... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
#defi... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S))
#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V 0x... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0))
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (BIT(0))
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x1
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_R... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
#define S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S))
#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK (BIT(0))
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M (BIT(0))
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V 0x1
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S 0
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S))
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_P... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S))
#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_P... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003
#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
#define S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003
#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S))
#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S))
#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003
#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
#define S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003
#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S))
#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S))
#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003
#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003
#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S))
#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003
#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S))
#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK (BIT(0))
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_M (BIT(0))
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_V 0x1
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_S 0
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_REG (DR_R... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
#define S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S))
#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK (BIT(0))
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_M (BIT(0))
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V 0x1
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S 0
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S))
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S))
#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003
#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
#define S... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003
#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S))
#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S))
#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003
#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
#define SENSI... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003
#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S))
#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S))
#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003
#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
#defi... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003
#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S))
#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V 0x... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003
#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S))
#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V 0x... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0))
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (BIT(0))
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x1
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG... | 2,057 |
*/
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0))
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (BIT(0))
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x1
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0
#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0))
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (BIT(0))
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x1
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0
#define SENS... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 0x00000003
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S))
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V 0x3
#define SENSI... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 0x00000003
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S))
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V 0x3
#define SENSI... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S))
#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x3
#define SENSI... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 0x00000003
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S))
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V 0x3
#define SENSITIVE_CORE_X_IRA... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 0x00000003
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S))
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V 0x3
#define SENSITIVE_CORE_X_IRA... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S))
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x3
#define SENSITIVE_CORE_X_IRA... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 0x00000003
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S))
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V 0x3
#define SENSITIVE_CORE_X_IRA... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 0x00000003
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S))
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V 0x3
#define SENSITIVE_CORE_X_IRA... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S))
#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x3
#define SENSITIVE_CORE_X_IRA... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 0x00000003
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S))
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 0x00000003
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S))
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S))
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 0x00000003
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S))
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 0x00000003
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S))
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S))
#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000007
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM... | 2,057 |
*/
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM... | 2,057 |
*/
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0))
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (BIT(0))
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x1
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xE8)... | 2,057 |
*/
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_ST... | 2,057 |
*/
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2))
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2))
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1
#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2
/* SENSIT... | 2,057 |
*/
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK (BIT(0))
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_M (BIT(0))
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V 0x1
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S 0
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xF4)... | 2,057 |
*/
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_ST... | 2,057 |
*/
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2))
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2))
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1
#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2
/* SENSIT... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0))
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0))
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x1
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BA... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM... | 2,057 |
*/
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM... | 2,057 |
*/
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0))
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (BIT(0))
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x1
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x108... | 2,057 |
*/
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_ST... | 2,057 |
*/
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1))
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1))
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1
/* SENSITIVE_CORE_0_DRAM0_PMS... | 2,057 |
*/
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0))
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0))
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1
#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0
#define SENSITIVE_CORE_1_DRAM0_PMS_M... | 2,057 |
*/
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0))
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0))
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG (D... | 2,057 |
*/
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1))
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1))
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1
/* SENSITIVE_CORE_1_DRAM0_PMS... | 2,057 |
*/
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0))
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0))
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1
#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0
#define SENSITIVE_CORE_0_PIF_PMS_CON... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3
#define SENSITIVE_... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x3
#define SENSITIVE_... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3
#define SENSITIVE_CORE_0_PIF... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3
#de... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERG... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V 0x3
#define ... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x3
#define SENSITIVE_... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3
#define SENSI... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3
#define SENSITIVE_CORE_... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x3
#define SENSI... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V 0x3
#define SENSITIVE_CORE_... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
#define SENSITIVE_CORE_0_PIF_PMS_... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3
#define SENSITIVE_CORE_0_PIF... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_... | 2,057 |
*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3
#define ... | 2,057 |
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