text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
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*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007FF
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S))
#define SENSITIVE_CORE_1_... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007FF
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S))
#define SENSITIVE_CORE_1_... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_ARE... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 0x3FFFFFFF
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3FFFFFFF
#define SENSITIVE_CORE_1_R... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 0x3FFFFFFF
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3FFFFFFF
#define SENSITIVE_CORE_1_R... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 0x3FFFFFFF
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3FFFFFFF
#define SENSITIVE_CORE_1_R... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 0x3FFFFFFF
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3FFFFFFF
#define SENSITIVE_CORE_1_R... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 0x3FFFFFFF
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V 0x3FFFFFFF
#define SENSITIVE_CORE_1_R... | 2,057 |
*/
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 0x3FFFFFFF
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S))
#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V 0x3FFFFFFF
#define SENSITIVE_COR... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK (BIT(0))
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_M (BIT(0))
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V 0x1
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S 0
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x24C)
/* SENSI... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STAT... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1))
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1))
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1
/* SENSITIVE_CORE_1_PIF_P... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1))
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1))
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1
/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWO... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
#define SENSITIVE_CORE_1_... | 2,057 |
*/
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF
#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
#define SENSITIVE_CORE_1_... | 2,057 |
*/
#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK (BIT(0))
#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_M (BIT(0))
#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_V 0x1
#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_S 0
#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x26C)
/* SENSITIVE_CO... | 2,057 |
*/
#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE 0x003FFFFF
#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_M ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S))
#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V 0x3FFFFF
#define SENSITIVE_... | 2,057 |
*/
#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0))
#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_M (BIT(0))
#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x1
#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_RE... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S 28
/* S... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S 20
/* S... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S 10
/* SENSITIVE_BAC... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONST... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S 24
/* S... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S 16
/* S... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S 10
/* SENSITI... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONST... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14
/* S... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S 2... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S 28
/* SENSITI... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONST... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTE... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V 0x3
#define SENSITIVE_BACKU... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR 0x000007FF
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V 0x... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L 0x00000007
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V 0x7
#define SENSITIVE_BACKUP_BUS_PMS_... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR (BIT(0))
#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M (BIT(0))
#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V 0x1
#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S 0
#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENS... | 2,057 |
*/
#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S))
#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STAT... | 2,057 |
*/
#define SENSITIVE_EDMA_BOUNDARY_LOCK (BIT(0))
#define SENSITIVE_EDMA_BOUNDARY_LOCK_M (BIT(0))
#define SENSITIVE_EDMA_BOUNDARY_LOCK_V 0x1
#define SENSITIVE_EDMA_BOUNDARY_LOCK_S 0
#define SENSITIVE_EDMA_BOUNDARY_0_REG (DR_REG_SENSITIVE_BASE + 0x2AC)
/* SENSITIVE_EDMA_BOUNDARY_0 : R/W ;bitpos:[13:0] ;de... | 2,057 |
*/
#define SENSITIVE_EDMA_BOUNDARY_2 0x00003FFF
#define SENSITIVE_EDMA_BOUNDARY_2_M ((SENSITIVE_EDMA_BOUNDARY_2_V)<<(SENSITIVE_EDMA_BOUNDARY_2_S))
#define SENSITIVE_EDMA_BOUNDARY_2_V 0x3FFF
#define SENSITIVE_EDMA_BOUNDARY_2_S 0
#define SENSITIVE_EDMA_PMS_SPI2_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2B8)
/* ... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_SPI2_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_M ((SENSITIVE_EDMA_PMS_SPI2_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR1_S))
#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_SPI3_LOCK_REG (DR_REG_SENSIT... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_SPI3_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_M ((SENSITIVE_EDMA_PMS_SPI3_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR1_S))
#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_REG (DR_REG_SENSI... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_M ((SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S))
#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_I2S0_LOCK_REG (DR_REG_... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_I2S0_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_M ((SENSITIVE_EDMA_PMS_I2S0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR1_S))
#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_I2S1_LOCK_REG (DR_REG_SENSIT... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_I2S1_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_M ((SENSITIVE_EDMA_PMS_I2S1_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR1_S))
#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_REG (DR_REG_SEN... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_M ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S))
#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_AES_LOCK_REG ... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_AES_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_AES_ATTR1_M ((SENSITIVE_EDMA_PMS_AES_ATTR1_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR1_S))
#define SENSITIVE_EDMA_PMS_AES_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_AES_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_SHA_LOCK_REG (DR_REG_SENSITIVE_BAS... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_SHA_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_SHA_ATTR1_M ((SENSITIVE_EDMA_PMS_SHA_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR1_S))
#define SENSITIVE_EDMA_PMS_SHA_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_SHA_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_REG (DR_REG_SENSITIVE... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_M ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S))
#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S 0
#define SENSITIVE_EDMA_PMS_RMT_LOCK_REG ... | 2,057 |
*/
#define SENSITIVE_EDMA_PMS_RMT_ATTR1 0x00000003
#define SENSITIVE_EDMA_PMS_RMT_ATTR1_M ((SENSITIVE_EDMA_PMS_RMT_ATTR1_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR1_S))
#define SENSITIVE_EDMA_PMS_RMT_ATTR1_V 0x3
#define SENSITIVE_EDMA_PMS_RMT_ATTR1_S 0
#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x3... | 2,057 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32S3 Root Clock Source
*/
/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!, F
/**
*/
typedef enum {
// For CPU doma... | 2,058 |
< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_D2, /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to ... | 2,058 |
< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
/**
*/
#define SOC_GPTI... | 2,058 |
< Select PLL_F160M as the source clock */
LCD_CLK_SRC_PLL240M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the source clock */
LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
} ... | 2,058 |
< RMT source clock is APB */
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor////////////////////////////... | 2,058 |
< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
} soc_periph_uart_clk_src_legacy_t;
//////////////////////////////////////////////////MCPWM//////////////////////////////... | 2,058 |
< Select PLL_F160M as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
... | 2,058 |
< Select APB as SPI source clock */
SPI_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM///////////////////////////... | 2,058 |
< Select APB as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
*/
#define SOC_ADC_DIGI_CLKS {SOC_MO... | 2,058 |
< Select APB as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK... | 2,058 |
< Select PLL_160M as the default choice */
SDMMC_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */
SDMMC_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_sdmmc_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT/... | 2,058 |
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,059 |
When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.*/
};
uint32_... | 2,059 |
*/
uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when SOF frame is received.*/
uint32_t serial_out_recv_pkt_int_raw: 1; /*The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.*/
uint32_t serial_in_em... | 2,059 |
*/
uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when usb bus reset is detected.*/
uint32_t out_ep1_zero_payload_int_raw: 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.*/
uint32_t ou... | 2,059 |
*/
uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
uint32_t pid_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
uint32_t crc5_err_int_st ... | 2,059 |
*/
uint32_t out_ep2_zero_payload_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t j... | 2,059 |
*/
uint32_t crc16_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
uint32_t stuff_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
uint32_t in_token_rec_in_ep1_int_ena: 1; /*... | 2,059 |
*/
uint32_t sof_int_clr : 1; /*Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.*/
uint32_t serial_out_recv_pkt_int_clr: 1; /*Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
uint32_t serial_in_empty_int_clr : 1; /*Set t... | 2,059 |
*/
uint32_t out_ep1_zero_payload_int_clr: 1; /*Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
uint32_t out_ep2_zero_payload_int_clr: 1; /*Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 ... | 2,059 |
*/
uint32_t dp_pulldown : 1; /*Control USB D+ pull down.*/
uint32_t dm_pullup : 1; /*Control USB D- pull up.*/
uint32_t dm_pulldown : 1; /*Control USB D- pull down.*/
uint32_t pullup_value : 1; /*Con... | 2,059 |
*/
uint32_t in_fifo_empty : 1; /*1: JTAG in fifo is empty.*/
uint32_t in_fifo_full : 1; /*1: JTAG in fifo is full.*/
uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/
uint32_t out_fifo_empty : 1; /*1: JT... | 2,059 |
*/
uint32_t in_ep0_wr_addr : 7; /*Write data address of IN endpoint 0.*/
uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep0_st;
... | 2,059 |
*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep2_st;
union {
struct {
uint32_t in_ep3_state : 2; /*State of IN Endpoint 3.*/
uint32_t in_ep3_wr_addr : 7; /*Write data address of ... | 2,059 |
*/
uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT endpoint 1.*/
... | 2,059 |
1'h0: Support clock only when application writes registers.*/
uint32_t reserved1 : 31;
};
uint32_t val;
} misc_conf;
union {
struct {
uint32_t usb_mem_pd : 1; /*1: power down usb memory.*/
uint32_t usb_mem_clk... | 2,059 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,060 |
Can not b
e changed by CONF_buf..*/
#define SPI_USR (BIT(24))
#define SPI_USR_M (BIT(24))
#define SPI_USR_V 0x1
#define SPI_USR_S 24
/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
clock domain, which is only used ... | 2,060 |
Can be con
figured in CONF state..*/
#define SPI_WR_BIT_ORDER 0x00000003
#define SPI_WR_BIT_ORDER_M ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
#define SPI_WR_BIT_ORDER_V 0x3
#define SPI_WR_BIT_ORDER_S 25
/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
/*description: In read-data (MISO) phase 1: L... | 2,060 |
.*/
#define SPI_HOLD_POL (BIT(20))
#define SPI_HOLD_POL_M (BIT(20))
#define SPI_HOLD_POL_V 0x1
#define SPI_HOLD_POL_S 20
/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
CONF state..*/
#define SPI_D_POL (BIT(19))
... | 2,060 |
1: enable 0: disable. C
an be configured in CONF state..*/
#define SPI_FREAD_QUAD (BIT(15))
#define SPI_FREAD_QUAD_M (BIT(15))
#define SPI_FREAD_QUAD_V 0x1
#define SPI_FREAD_QUAD_S 15
/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: In the read operations, read-data phase apply 2 signals.... | 2,060 |
Can be configured in C
ONF state..*/
#define SPI_FCMD_DUAL (BIT(8))
#define SPI_FCMD_DUAL_M (BIT(8))
#define SPI_FCMD_DUAL_V 0x1
#define SPI_FCMD_DUAL_S 8
/* SPI_FADDR_OCT : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
state.... | 2,060 |
1: In the dummy phas
e, the FSPI bus signals are output. Can be configured in CONF state..*/
#define SPI_DUMMY_OUT (BIT(3))
#define SPI_DUMMY_OUT_M (BIT(3))
#define SPI_DUMMY_OUT_V 0x1
#define SPI_DUMMY_OUT_S 3
#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC)
/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;d... | 2,060 |
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