repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 1,303 | sim/testsuite/bfin/c_dsp32shiftim_rot.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp
// Spec Reference: dsp32shiftimm rot:
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x9... |
tactcomplabs/xbgas-binutils-gdb | 7,342 | sim/testsuite/bfin/c_interr_disable_enable.S | //Original:/proj/frio/dv/testcases/core/c_interr_disable_enable/c_interr_disable_enable.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)... |
tactcomplabs/xbgas-binutils-gdb | 2,922 | sim/testsuite/bfin/c_dsp32mac_dr_a0_m.s | //Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp
// Spec Reference: dsp32mac dr_a0 m
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0... |
tactcomplabs/xbgas-binutils-gdb | 3,881 | sim/testsuite/bfin/c_alu2op_conv_neg.s | //Original:/testcases/core/c_alu2op_conv_neg/c_alu2op_conv_neg.dsp
// Spec Reference: alu2op (-) negative
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0... |
tactcomplabs/xbgas-binutils-gdb | 1,180 | sim/testsuite/bfin/ashift_flags.s | # mach: bfin
.include "testutils.inc"
start
// load r1=0x7fffffff
// load r2=0x80000000
// load r3=0x000000ff
// load r4=0x00000000
loadsym p0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
_dbg r0;
_dbg r1;
_dbg r2;
_dbg r3;
_dbg r4;
R7 = 0;
ASTAT = R7;... |
tactcomplabs/xbgas-binutils-gdb | 4,138 | sim/testsuite/bfin/c_alu2op_arith_r_sft.s | //Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp
// Spec Reference: alu2op arith right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 ... |
tactcomplabs/xbgas-binutils-gdb | 7,121 | sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_j_mv_pop/c_seq_ex1_raise_j_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen... |
tactcomplabs/xbgas-binutils-gdb | 1,181 | sim/testsuite/bfin/algnbug2.s | # mach: bfin
.include "testutils.inc"
start
M0 = 1 (X);
loadsym I0, blocka;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP |... |
tactcomplabs/xbgas-binutils-gdb | 6,170 | sim/testsuite/bfin/dbg_tr_umode.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp
// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
// Supervisor mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfche... |
tactcomplabs/xbgas-binutils-gdb | 7,005 | sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh2.s | //Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh2/c_comp3op_pr_plus_pr_sh2.dsp
// Spec Reference: comp3op pregs + pregs << 2
# mach: bfin
.include "testutils.inc"
start
imm32 p1, 0x89ab1def;
imm32 p2, 0x56781abc;
imm32 p3, 0xdef01234;
imm32 p4, 0x23451899;
imm32 p5, 0x78911345;
imm32 sp, 0x98... |
tactcomplabs/xbgas-binutils-gdb | 5,551 | sim/testsuite/bfin/random_0030.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x00a0cc80 | _VS | _AV1S | _AQ | _CC | _AN);
dmm32 A1.w, 0x8f7fea28;
dmm32 A1.x, 0x00000005;
imm32 R2, 0x000014f2;
imm32 R4, 0x7fff7fff;
imm32 R7, 0x14d3a258;
R7.H = (A1 -= R4.L * R2.H) (M, T);
checkreg R7, 0x7fffa258;
checkreg A1.w... |
tactcomplabs/xbgas-binutils-gdb | 7,996 | sim/testsuite/bfin/c_comp3op_dr_minus_dr.s | //Original:/testcases/core/c_comp3op_dr_minus_dr/c_comp3op_dr_minus_dr.dsp
// Spec Reference: comp3op dregs - dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
... |
tactcomplabs/xbgas-binutils-gdb | 6,681 | sim/testsuite/bfin/c_dsp32mac_dr_a1_t.s | //Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp
// Spec Reference: dsp32mac dr a1 t (truncation)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0... |
tactcomplabs/xbgas-binutils-gdb | 1,189 | sim/testsuite/bfin/se_ssync.S | //Original:/proj/frio/dv/testcases/seq/se_ssync/se_ssync.dsp
// Description: Test SSYNC by writing a bunch of MMRs and verifying read
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
i... |
tactcomplabs/xbgas-binutils-gdb | 1,791 | sim/testsuite/bfin/c_progctrl_except_rtx.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_except_rtx/c_progctrl_except_rtx.dsp
// Spec Reference: c_progctrl_except_rtx
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
//CHECK_INIT(p5, 0xe0000... |
tactcomplabs/xbgas-binutils-gdb | 10,594 | sim/testsuite/bfin/c_dsp32shift_ahalf_ln_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_ln_s/c_dsp32shift_ahalf_ln_s.dsp
// Spec Reference: <a pointer to reference the section of the spec>
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1,... |
tactcomplabs/xbgas-binutils-gdb | 1,125 | sim/testsuite/bfin/issue83.s | # mach: bfin
.include "testutils.inc"
start
R0.H = -32768;
R0.L = 0;
R0 >>= 0x1;
_DBG R0;
R7 = ASTAT;
_DBG R7;
//DBGA ( R7.H , 0x0000 );
//DBGA ( R7.L , 0x0000 );
cc = az;
r0 = cc;
dbga( r0.l, 0);
cc = an;
r0 = cc;
dbga( r0.l, 0);
cc = av0;
r0 = cc;
dbga( r0.l, 0);
cc = av0s;
r0 = cc;
dbga( r0.l... |
tactcomplabs/xbgas-binutils-gdb | 2,415 | sim/testsuite/bfin/c_compi2opp_pr_eq_i7_n.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_n/c_compi2opp_pr_eq_i7_n.dsp
// Spec Reference: compi2opp pregs = imm7 negative
# mach: bfin
.include "testutils.inc"
start
R0 = -0;
P1 = -1;
P2 = -2;
P3 = -3;
P4 = -4;
P5 = -5;
SP = -6;
FP = -7;
CHECKREG r0, -0;
CHECKREG p1, -1;
CHECKREG p2, ... |
tactcomplabs/xbgas-binutils-gdb | 11,001 | sim/testsuite/bfin/c_ldstidxl_st_dr_h.s | //Original:testcases/core/c_ldstidxl_st_dr_h/c_ldstidxl_st_dr_h.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 5,401 | sim/testsuite/bfin/c_ccflag_dr_dr.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr/c_ccflag_dr_dr.dsp
// Spec Reference: ccflags dr-dr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00110022;
imm32 r1, 0x00110022;
imm32 r2, 0x00330044;
imm32 r3, 0x00550066;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, ... |
tactcomplabs/xbgas-binutils-gdb | 4,328 | sim/testsuite/bfin/c_cc2stat_cc_av0.S | //Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp
// Spec Reference: cc2stat cc av0
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x000... |
tactcomplabs/xbgas-binutils-gdb | 2,825 | sim/testsuite/bfin/c_dsp32alu_byteunpack.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteunpack/c_dsp32alu_byteunpack.dsp
// Spec Reference: dsp32alu byteunpack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 3,203 | sim/testsuite/bfin/random_0011.S | # test acc shifts larger than they should be, and ASTAT flags
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x7cc0c090 | _VS | _V | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x1890bdbc;
dmm32 A0.x, 0x00000079;
A0 = A0 << 0x2;
checkreg A0.w, 0x6242f6f0;
checkreg A0.x,... |
tactcomplabs/xbgas-binutils-gdb | 1,688 | sim/testsuite/bfin/s3.s | // SHIFT test program.
// Test A0 = ASHIFT (A0 by r3);
# mach: bfin
.include "testutils.inc"
start
// load r0=0x0000001f
// load r1=0x00000020
// load r2=0x00000000
// load r3=0x00000000
// load r4=0x00000001
// load r5=0x00000080
loadsym P0, data0;
P1 = P0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R... |
tactcomplabs/xbgas-binutils-gdb | 10,799 | sim/testsuite/bfin/se_loop_lr.S | //Original:/proj/frio/dv/testcases/seq/se_loop_lr/se_loop_lr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
////... |
tactcomplabs/xbgas-binutils-gdb | 6,402 | sim/testsuite/bfin/c_ldst_st_p_p_pp.s | //Original:/testcases/core/c_ldst_st_p_p_pp/c_ldst_st_p_p_pp.dsp
// Spec Reference: c_ldst st p++ p
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, ... |
tactcomplabs/xbgas-binutils-gdb | 5,801 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_xb.s | //Original:testcases/core/c_ldst_ld_d_p_mm_xb/c_ldst_ld_d_p_mm_xb.dsp
// Spec Reference: c_ldst ld d [p--] xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP ... |
tactcomplabs/xbgas-binutils-gdb | 4,681 | sim/testsuite/bfin/c_regmv_pr_dep_nostall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_nostall/c_regmv_pr_dep_nostall.dsp
// Spec Reference: regmv pr-dep no stall
# mach: bfin
.include "testutils.inc"
start
//imm32 p0, 0x00001111;
imm32 p1, 0x32213330;
imm32 p2, 0x34415550;
imm32 p3, 0x36617770;
imm32 p4, 0x38819990;
imm32 p5, 0x3aa1bbb0;
im... |
tactcomplabs/xbgas-binutils-gdb | 8,410 | sim/testsuite/bfin/c_ldst_st_p_d_mm_b.s | //Original:testcases/core/c_ldst_st_p_d_mm_b/c_ldst_st_p_d_mm_b.dsp
// Spec Reference: c_ldst st_p-- b byte
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729... |
tactcomplabs/xbgas-binutils-gdb | 4,611 | sim/testsuite/bfin/c_dsp32shift_signbits_rh.s | //Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp
// Spec Reference: dsp32shift signbits dregs_hi
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xd1000000;
imm32 r1, 0xd2000001;
imm32 r2, 0xd3000002;
imm32 r3, 0xd4000003;
imm32 r4, 0xd5000004;
imm32 r5, 0xd6000005;
imm32 r6,... |
tactcomplabs/xbgas-binutils-gdb | 4,778 | sim/testsuite/bfin/c_dsp32shift_align8.s | //Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp
// Spec Reference: dsp32shift align8
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0... |
tactcomplabs/xbgas-binutils-gdb | 6,546 | sim/testsuite/bfin/c_mode_user.S | //Original:/proj/frio/dv/testcases/core/c_mode_user/c_mode_user.dsp
// Spec Reference: mode_user
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize t... |
tactcomplabs/xbgas-binutils-gdb | 2,019 | sim/testsuite/bfin/c_ldst_st_p_p.s | //Original:/testcases/core/c_ldst_st_p_p/c_ldst_st_p_p.dsp
// Spec Reference: c_ldst st_p_p
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7... |
tactcomplabs/xbgas-binutils-gdb | 3,937 | sim/testsuite/bfin/c_dsp32mac_dr_a1a0_iutsh.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_iutsh/c_dsp32mac_dr_a1a0_iutsh.dsp
// Spec Reference: dsp32mac dr_a1a0 iutsh
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0x... |
tactcomplabs/xbgas-binutils-gdb | 1,159 | sim/testsuite/bfin/m6.s | // Test result extraction of mac instructions.
// Test basic edge values
// SIGNED INTEGER mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000001
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P... |
tactcomplabs/xbgas-binutils-gdb | 5,429 | sim/testsuite/bfin/c_dsp32alu_rpm.s | //Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp
// Spec Reference: dsp32alu dreg = +/- ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x65678911;
imm... |
tactcomplabs/xbgas-binutils-gdb | 6,280 | sim/testsuite/bfin/c_dsp32mac_pair_a0_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_is/c_dsp32mac_pair_a0_is.dsp
// Spec Reference: dsp32mac pair a0 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa864567... |
tactcomplabs/xbgas-binutils-gdb | 5,752 | sim/testsuite/bfin/m2.s | // MAC test program.
// Test basic edge values
// SIGNED FRACTIONAL mode
// test ops: "+=" "-=" "=" "NOP"
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ]... |
tactcomplabs/xbgas-binutils-gdb | 13,148 | sim/testsuite/bfin/c_ldst_ld_d_p_ppmm_hbx.s | //Original:/testcases/core/c_ldst_ld_d_p_ppmm_hbx/c_ldst_ld_d_p_ppmm_hbx.dsp
// Spec Reference: c_ldst ld d [p++/--] h b xh xb
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6... |
tactcomplabs/xbgas-binutils-gdb | 1,661 | sim/testsuite/bfin/c_loopsetup_preg_lc1.s | //Original:/testcases/core/c_loopsetup_preg_lc1/c_loopsetup_preg_lc1.dsp
// Spec Reference: loopsetup preg lc1
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P1 = 12;
P2 = 14;
P3 = 16;
P4 = 18;
P5 = 20;
SP = 22;
FP = 24;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50... |
tactcomplabs/xbgas-binutils-gdb | 2,438 | sim/testsuite/bfin/c_compi2opd_dr_add_i7_p.s | //Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp
// Spec Reference: compi2opd dregs += imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 += 0;
R1 += 1;
R2 += 2;
R3 += 3;
R4 += 4;
R5 += 5;
R6 += 6;
R7 += 7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHE... |
tactcomplabs/xbgas-binutils-gdb | 2,312 | sim/testsuite/bfin/random_0018.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x40204090 | _AV1S | _AV0S | _AV0 | _AQ | _AN | _AZ);
imm32 R1, 0x33e91405;
imm32 R4, 0x3fa1377c;
R4.H = R1.H >>> 0x1d;
checkreg R4, 0x9f48377c;
checkreg ASTAT, (0x40204090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AN);
dm... |
tactcomplabs/xbgas-binutils-gdb | 2,080 | sim/testsuite/bfin/cec-snen-reti.S | # Blackfin testcase for having RETI LSB set correctly when self nested
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set our handler
imm32 P5, EVT11;
loadsym R1, _ivg11;
[P5] = R1;
loadsym R1, _fail_lvl;
[P5 + 4] = R1; /* IVG12 */
[P5 + 12] = R1; /* IVG14 */
... |
tactcomplabs/xbgas-binutils-gdb | 3,100 | sim/testsuite/bfin/a5.s | // ALU test program.
// Test instructions
// rL4= L+L (r2,r3);
// rH4= L+H (r2,r3) S;
// rL4= L-L (r2,r3);
// rH4= L-H (r2,r3) S;
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// overflow positive
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x7fff;
R1.H = 0x0000;
R7 = 0;
ASTAT =... |
tactcomplabs/xbgas-binutils-gdb | 7,129 | sim/testsuite/bfin/c_ldstpmod_st_dr_hi.s | //Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp
// Spec Reference: c_ldstpmod store dreg hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;... |
tactcomplabs/xbgas-binutils-gdb | 7,994 | sim/testsuite/bfin/c_comp3op_dr_plus_dr.s | //Original:/testcases/core/c_comp3op_dr_plus_dr/c_comp3op_dr_plus_dr.dsp
// Spec Reference: comp3op dregs + dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
im... |
tactcomplabs/xbgas-binutils-gdb | 23,117 | sim/testsuite/bfin/se_undefinedinstruction4.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction4/se_undefinedinstruction4.dsp
// Description: 64 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
... |
tactcomplabs/xbgas-binutils-gdb | 5,691 | sim/testsuite/bfin/se_excpt_ssstep.S | //Original:/proj/frio/dv/testcases/seq/se_excpt_ssstep/se_excpt_ssstep.dsp
// Description: EXCPT instruction vs Single Step Exception Priority
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
includ... |
tactcomplabs/xbgas-binutils-gdb | 7,992 | sim/testsuite/bfin/c_comp3op_dr_and_dr.s | //Original:/testcases/core/c_comp3op_dr_and_dr/c_comp3op_dr_and_dr.dsp
// Spec Reference: comp3op dregs & dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 6,562 | sim/testsuite/bfin/c_dsp32alu_rrpm.s | //Original:/testcases/core/c_dsp32alu_rrpm/c_dsp32alu_rrpm.dsp
// Spec Reference: dsp32alu (dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x75678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34745515;
imm32 r3, 0x46677717;
imm32 r0, 0x5567a91b;
imm32 r1, 0x6789aa1d;
imm32 r2, 0x744455a5;
imm32 r3, 0x... |
tactcomplabs/xbgas-binutils-gdb | 10,244 | sim/testsuite/bfin/se_mv2lp.S | //Original:/proj/frio/dv/testcases/seq/se_mv2lp/se_mv2lp.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
////////... |
tactcomplabs/xbgas-binutils-gdb | 3,444 | sim/testsuite/bfin/cec-multi-pending.S | # Blackfin testcase for multiple pending IVGs vs masked state
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym;
[P5 + 4 * \lvl\()] = R1;
.endm
.macro check_cec mmr:req, val... |
tactcomplabs/xbgas-binutils-gdb | 6,112 | sim/testsuite/bfin/c_dsp32alu_rh_rnd12_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_m/c_dsp32alu_rh_rnd12_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x45678ad1;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xf4445545;
imm32 r3, 0x46667767;
imm32 r4, 0xe678891b;
imm32 r5, 0x6f89ab1d;
imm32... |
tactcomplabs/xbgas-binutils-gdb | 6,686 | sim/testsuite/bfin/c_dsp32alu_rrpmmp.s | //Original:/testcases/core/c_dsp32alu_rrpmmp/c_dsp32alu_rrpmmp.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) amod0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x67889b1d;
... |
tactcomplabs/xbgas-binutils-gdb | 4,072 | sim/testsuite/bfin/c_alu2op_log_r_sft.s | //Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp
// Spec Reference: alu2op logical right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0x... |
tactcomplabs/xbgas-binutils-gdb | 5,800 | sim/testsuite/bfin/c_dsp32mult_dr.s | //Original:/testcases/core/c_dsp32mult_dr/c_dsp32mult_dr.dsp
// Spec Reference: dsp32mult single dr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd246702... |
tactcomplabs/xbgas-binutils-gdb | 9,982 | sim/testsuite/bfin/se_loop_nest_ppm_1.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_1/se_loop_nest_ppm_1.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////... |
tactcomplabs/xbgas-binutils-gdb | 4,076 | sim/testsuite/bfin/c_ccflag_pr_imm3_uu.s | //Original:/testcases/core/c_ccflag_pr_imm3_uu/c_ccflag_pr_imm3_uu.dsp
// Spec Reference: ccflag pr-imm3 (uu)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00000001;
imm32 p1, 0x00000001;
imm32 p2, 0x00000002;
imm32 p3, 0x00000003;
imm32 p4, 0x00000004;
imm32 p5, 0x00000005;
imm32 sp, ... |
tactcomplabs/xbgas-binutils-gdb | 7,480 | sim/testsuite/bfin/c_seq_ex2_raise_mmr_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmr_mvpop/c_seq_ex2_raise_mmr_mvpop.dsp
// Spec Reference: sequencer stage ex2 (raise+ mmr + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(g... |
tactcomplabs/xbgas-binutils-gdb | 5,477 | sim/testsuite/bfin/c_dsp32mult_dr_mix.s | //Original:/testcases/core/c_dsp32mult_dr_mix/c_dsp32mult_dr_mix.dsp
// Spec Reference: dsp32mult single dr (mix) u i t is tu ih
# mach: bfin
.include "testutils.inc"
start
// test the default (signed fraction) rounding U=0 I=0 T=0
imm32 r0, 0xab235615;
imm32 r1, 0xcfba5117;
imm32 r2, 0x13246715;
imm32 r3, 0x0006001... |
tactcomplabs/xbgas-binutils-gdb | 1,849 | sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s | //Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp
// Spec Reference: compi2opd dregs = imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
R4 = 4;
R5 = 5;
R6 = 6;
R7 = 7;
CHECKREG r0, 0;
CHECKREG r1, 1;
CHECKREG r2, 2;
CHECKREG r3, 3;
... |
tactcomplabs/xbgas-binutils-gdb | 8,752 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_lp.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY imm5)
// RLx by imm5
imm32 r0, 0x00100a... |
tactcomplabs/xbgas-binutils-gdb | 21,914 | sim/testsuite/bfin/c_dsp32mac_a1a0_iuw32.s | //Original:/testcases/core/c_dsp32mac_a1a0_iuw32/c_dsp32mac_a1a0_iuw32.dsp
// Spec Reference: dsp32mac a1 a0 iuw32 MNOP
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the (signed integer: no ) I=1
imm32 r0, 0x22345628;
imm32 r1, 0x23456729;
im... |
tactcomplabs/xbgas-binutils-gdb | 1,910 | sim/testsuite/bfin/hwloop-branch-in.s | # Blackfin testcase for branching into the middle of a hardware loop
# mach: bfin
.include "testutils.inc"
.macro test_prep lc:req
loadsym P5, 1f;
dmm32 LC0, \lc
R5 = 0;
R6 = 0;
R7 = 0;
.endm
.macro test_check exp5:req, exp6:req, exp7:req, expLC:req
1:
imm32 R4, \exp5;
CC = R4 == R5;
IF !CC JUMP 2f;
imm... |
tactcomplabs/xbgas-binutils-gdb | 4,973 | sim/testsuite/bfin/c_regmv_imlb_dr.s | //Original:/testcases/core/c_regmv_imlb_dr/c_regmv_imlb_dr.dsp
// Spec Reference: regmv imlb to dr
# mach: bfin
.include "testutils.inc"
start
// initialize source regs
imm32 i0, 0x11111111;
imm32 i1, 0x22222222;
imm32 i2, 0x33333333;
imm32 i3, 0x44444444;
// i to dreg
R0 = I0;
R1 = I0;
R2 = I0;
R3 = I0;
R4 =... |
tactcomplabs/xbgas-binutils-gdb | 5,300 | sim/testsuite/bfin/c_ldst_ld_p_p.s | //Original:/testcases/core/c_ldst_ld_p_p/c_ldst_ld_p_p.dsp
// Spec Reference: c_ldst ld p [p]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
P2 = [ P1 ];
P4 = [ P1 ];
P5... |
tactcomplabs/xbgas-binutils-gdb | 4,029 | sim/testsuite/bfin/c_dsp32mult_pair_m_s.s | //Original:/testcases/core/c_dsp32mult_pair_m_s/c_dsp32mult_pair_m_s.dsp
// Spec Reference: dsp32mult pair MUNOP s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 7,994 | sim/testsuite/bfin/c_comp3op_dr_xor_dr.s | //Original:/testcases/core/c_comp3op_dr_xor_dr/c_comp3op_dr_xor_dr.dsp
// Spec Reference: comp3op dregs xor dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
im... |
tactcomplabs/xbgas-binutils-gdb | 1,990 | sim/testsuite/bfin/l0.s | // simple test to ensure that we can load data from memory.
# mach: bfin
.include "testutils.inc"
start
loadsym P0, tab;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
R6 = [ P0 ++ ];
R7 = [ P0 ++ ];
DBGA ( R0.H , 0x1111 );
DBGA ( R1.H , 0x2222 );
DBGA ( ... |
tactcomplabs/xbgas-binutils-gdb | 3,312 | sim/testsuite/bfin/random_0009.S | # Verify ASTAT bits are set correctly during dsp mac insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x16ba2677;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x80007fff;
A0 -= R4.H * R4.H (... |
tactcomplabs/xbgas-binutils-gdb | 5,034 | sim/testsuite/bfin/c_ldst_st_p_d_h.s | //Original:/testcases/core/c_ldst_st_p_d_h/c_ldst_st_p_d_h.dsp
// Spec Reference: c_ldst st_p d h
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6... |
tactcomplabs/xbgas-binutils-gdb | 1,531 | sim/testsuite/bfin/c_dagmodim_lz_inc_dec.s | //Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp
// Spec Reference: dagmodim L=0, I incremented & decremented (by M)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x10001000;
imm32 i1, 0x02001100;
imm32 i2, 0x00301010;
imm32 i3, 0x00041001;
imm32 m0, 0x00000005;
im... |
tactcomplabs/xbgas-binutils-gdb | 2,876 | sim/testsuite/bfin/c_dsp32mac_dr_a0_tu.s | //Original:/testcases/core/c_dsp32mac_dr_a0_tu/c_dsp32mac_dr_a0_tu.dsp
// Spec Reference: dsp32mac dr a0 tu (truncate unsigned fraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfec7;
imm32 r2, 0xc7fff... |
tactcomplabs/xbgas-binutils-gdb | 3,192 | sim/testsuite/bfin/c_dsp32mac_pair_a1.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1/c_dsp32mac_pair_a1.dsp
// Spec Reference: dsp32mac pair a1
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 ... |
tactcomplabs/xbgas-binutils-gdb | 1,403 | sim/testsuite/bfin/m7.s | // Test result extraction of mac instructions.
// Test basic edge values
// UNSIGNED FRACTIONAL mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000001
// load r1=0x80007fff
// load r2=0xf000ffff
// load r3=0x0000007f
// load r4=0x00000080
loads... |
tactcomplabs/xbgas-binutils-gdb | 4,150 | sim/testsuite/bfin/c_ccflag_pr_pr_uu.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr_uu/c_ccflag_pr_pr_uu.dsp
// Spec Reference: ccflag pr-pr (uu)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00110022;
imm32 p1, 0x00110022;
imm32 p2, 0x00330044;
imm32 p3, 0x00550066;
imm32 p4, 0x00770088;
imm32 p5, 0x009900aa;
imm32... |
tactcomplabs/xbgas-binutils-gdb | 6,993 | sim/testsuite/bfin/c_ldst_st_p_p_mm.s | //Original:testcases/core/c_ldst_st_p_p_mm/c_ldst_st_p_p_mm.dsp
// Spec Reference: c_ldst st p-- p
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 ... |
tactcomplabs/xbgas-binutils-gdb | 1,919 | sim/testsuite/bfin/c_dsp32alu_byteop3.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop3/c_dsp32alu_byteop3.dsp
// Spec Reference: dsp32alu byteop3
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444... |
tactcomplabs/xbgas-binutils-gdb | 1,856 | sim/testsuite/bfin/byteop2p.s | # Blackfin testcase for BYTEOP2P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop2p i0:req, resRL:req, resRH:req, resTL:req, resTH:req, resRLr:req, resRHr:req, resTLr:req, resTHr:req
dmm32 I0, \i0
R6 = BYTEOP2P (R1:0... |
tactcomplabs/xbgas-binutils-gdb | 12,527 | sim/testsuite/bfin/c_ldstidxl_st_preg.s | //Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp
// Spec Reference: c_ldstidxl store preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 1,530 | sim/testsuite/bfin/c_ldimmhalf_drlo.s | //Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp
// Spec Reference: ldimmhalf dreg lo
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.L = 0x0001;
R1.L = 0x0003;
R2.L = 0x0005;
R3.L = 0x0007;
R4.L = 0x0009;
R5.L = 0x000b;
R6.L = 0x000d;
R7.L = 0x000f;
CHECKREG r0, 0xFFFF... |
tactcomplabs/xbgas-binutils-gdb | 2,782 | sim/testsuite/bfin/random_0014.S | # Test a few corner cases with various shift insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0xf53d356e;
dmm32 A0.x, 0xffffffff;
imm32 R5, 0xaa156b54;
A0 = ASHIFT A0 BY R5.L;
checkreg A0.w, 0x56e0000... |
tactcomplabs/xbgas-binutils-gdb | 5,485 | sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_raise_rt_i_n/c_progctrl_raise_rt_i_n.dsp
// Spec Reference: progctrl raise rti rtn
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0)... |
tactcomplabs/xbgas-binutils-gdb | 11,066 | sim/testsuite/bfin/c_ldstidxl_st_dr_b.s | //Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f5080;
imm32 r1, 0x204e6091;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 6,097 | sim/testsuite/bfin/c_dsp32mult_dr_iu.s | //Original:/testcases/core/c_dsp32mult_dr_iu/c_dsp32mult_dr_iu.dsp
// Spec Reference: dsp32mult single dr iu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00010002;
imm32 r1, 0x00023004;
imm32 r2, 0x03843725;
imm32 r3, 0x00084027;
imm32 r4, 0x00ab5d29;
imm32 r5, 0x00ac682b;
imm32 r6, 0x000c708d;
imm32 r7, ... |
tactcomplabs/xbgas-binutils-gdb | 5,691 | sim/testsuite/bfin/c_dspldst_ld_dr_ippm.s | //Original:/testcases/core/c_dspldst_ld_dr_ippm/c_dspldst_ld_dr_ippm.dsp
// Spec Reference: c_dspldst ld_dr_i++m
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
M0 = 0 (X);
M1 = 0x4 (X);
M2 = 0x0 (X);
M3 = 0x4 (X);
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loads... |
tactcomplabs/xbgas-binutils-gdb | 1,701 | sim/testsuite/bfin/c_loopsetup_preg_div2_lc0.s | //Original:/testcases/core/c_loopsetup_preg_div2_lc0/c_loopsetup_preg_div2_lc0.dsp
// Spec Reference: loopsetup preg lc0 / 2
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P5 = 20;
P1 = 30;
P2 = 40;
P3 = 50;
P4 = 60;
//p5 = 7;
SP = 80 (X);
FP = 90 (X);
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 ... |
tactcomplabs/xbgas-binutils-gdb | 5,717 | sim/testsuite/bfin/se_excpt_ifprotviol.S | //Original:/proj/frio/dv/testcases/seq/se_excpt_ifprotviol/se_excpt_ifprotviol.dsp
// Description: EXCPT instruction and IF Prot Viol priority
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
inc... |
tactcomplabs/xbgas-binutils-gdb | 1,453 | sim/testsuite/bfin/loop_strncpy.s | # Blackfin testcase for loop counter values when jumping out from the last insn
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
loadsym r1, dest;
r0 = r1;
loadsym r1, src;
r2 = 0x10;
_strncpy:
CC = R2 == 0;
if CC JUMP 4f;
P2 = R2 ; /* size */
P0 = R0 ; /* dst*/
P1 = R... |
tactcomplabs/xbgas-binutils-gdb | 5,619 | sim/testsuite/bfin/c_dspldst_st_dr_ipp.s | //Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp
// Spec Reference: c_dspldst st_dr_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
//INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x... |
tactcomplabs/xbgas-binutils-gdb | 5,915 | sim/testsuite/bfin/c_ldst_ld_d_p_xh.s | //Original:/testcases/core/c_ldst_ld_d_p_xh/c_ldst_ld_d_p_xh.dsp
// Spec Reference: c_ldst ld d [p] xh
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_... |
tactcomplabs/xbgas-binutils-gdb | 2,738 | sim/testsuite/bfin/c_dspldst_ld_dr_i.s | //Original:/testcases/core/c_dspldst_ld_dr_i/c_dspldst_ld_dr_i.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: c_dspldst ld_dr_i
// set all regs
INIT_R_REGS 0;
// initial values
loadsym I0, DATA1
loadsym I1, DATA2
loadsym I2, DATA3
loadsym I3, DATA4
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I... |
tactcomplabs/xbgas-binutils-gdb | 5,171 | sim/testsuite/bfin/se_more_ret_haz.S | //Original:/proj/frio/dv/testcases/seq/se_more_ret_haz/se_more_ret_haz.dsp
// Description: Return insts following pop, move.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include... |
tactcomplabs/xbgas-binutils-gdb | 3,151 | sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s | //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp
// Spec Reference: ptr2op preg -= preg
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0xf0021003;
imm32 p2, 0x2e041005;
imm32 p3, 0x20d61007;
imm32 p4, 0x200a1009;
imm32 p5, 0x200a300b;
imm32 ... |
tactcomplabs/xbgas-binutils-gdb | 5,720 | sim/testsuite/bfin/c_mmr_timer.S | //Original:/proj/frio/dv/testcases/core/c_mmr_timer/c_mmr_timer.dsp
// Spec Reference: mmr timer
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
... |
tactcomplabs/xbgas-binutils-gdb | 1,347 | sim/testsuite/bfin/c_dsp32alu_saa.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_saa/c_dsp32alu_saa.dsp
// Spec Reference: dsp32alu saa
# mach: bfin
.include "testutils.inc"
start
A1 = 0;
A0 = 0;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6,... |
tactcomplabs/xbgas-binutils-gdb | 1,432 | sim/testsuite/bfin/m14.s | // Test extraction from accumulators:
// UNSIGNED FRACTIONAL and SIGNED INT mode into register PAIR
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffffff0
// load r1=0xfffffff0
// load r2=0x0fffffff
// load r3=0x00000001
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = ... |
tactcomplabs/xbgas-binutils-gdb | 7,214 | sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_brcc_mv_pop/c_seq_ex1_raise_brcc_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
inclu... |
tactcomplabs/xbgas-binutils-gdb | 8,498 | sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_brcc_mvp/c_seq_ex3_ls_brcc_mvp.dsp
// Spec Reference: sequencer stage ex3 (ldst + brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.i... |
tactcomplabs/xbgas-binutils-gdb | 8,188 | sim/testsuite/bfin/c_ldstpmod_ld_lohi.s | //Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp
// Spec Reference: c_ldstpmod load dreg lo & hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0002;
P2 = 0x0002;
... |
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