repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 9,418 | sim/testsuite/bfin/c_ldstidxl_ld_dreg.s | //Original:testcases/core/c_ldstidxl_ld_dreg/c_ldstidxl_ld_dreg.dsp
// Spec Reference: c_ldstidxl load dreg (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
// initial values
loadsym p1, DATA_ADDR_1,... |
tactcomplabs/xbgas-binutils-gdb | 5,702 | sim/testsuite/bfin/c_dsp32alu_min.s | //Original:/testcases/core/c_dsp32alu_min/c_dsp32alu_min.dsp
// Spec Reference: dsp32alu dregs = min ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x35678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0xf6667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;... |
tactcomplabs/xbgas-binutils-gdb | 1,042 | sim/testsuite/bfin/m8.s | // MAC test program.
// Test result extraction of mac instructions.
// Test basic edge values
// UNSIGNED INTEGER mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000002
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r... |
tactcomplabs/xbgas-binutils-gdb | 2,770 | sim/testsuite/bfin/c_dspldst_st_drhi_i.s | //Original:/testcases/core/c_dspldst_st_drhi_i/c_dspldst_st_drhi_i.dsp
// Spec Reference: c_dspldst st_drhi_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
i... |
tactcomplabs/xbgas-binutils-gdb | 6,136 | sim/testsuite/bfin/c_dsp32alu_rl_rnd12_p.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_p/c_dsp32alu_rl_rnd12_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x85678011;
imm32 r1, 0x9189a11d;
imm32 r2, 0xa4245235;
imm32 r3, 0xb6637747;
imm32 r4, 0xc67849db;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 3,020 | sim/testsuite/bfin/c_dsp32shiftim_lmix.s | //Original:/testcases/core/c_dsp32shiftim_lmix/c_dsp32shiftim_lmix.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: mix
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// Lshift (Logical )
// Lshift : positive data, count (+)=left... |
tactcomplabs/xbgas-binutils-gdb | 9,629 | sim/testsuite/bfin/c_ldst_st_p_d_mm_h.s | //Original:testcases/core/c_ldst_st_p_d_mm_h/c_ldst_st_p_d_mm_h.dsp
// Spec Reference: c_ldst st_p-- h half
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 ... |
tactcomplabs/xbgas-binutils-gdb | 11,060 | sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_nostall/c_regmv_imlb_dep_nostall.dsp
// Spec Reference: regmv imlb-dep no stall
# mach: bfin
.include "testutils.inc"
start
// P-reg to I,M-reg to R-reg: no stall
//imm32 p0, 0x00001111;
imm32 p1, 0x12213330;
imm32 p2, 0x14415550;
imm32 p3, 0x16617770;
imm... |
tactcomplabs/xbgas-binutils-gdb | 2,889 | sim/testsuite/bfin/byteop16p.s | # Blackfin testcase for BYTEOP16P
# mach: bfin
.include "testutils.inc"
start
.macro check_it resL:req, resH:req
imm32 R6, \resL
CC = R4 == R6;
IF !CC JUMP 1f;
imm32 R7, \resH
CC = R5 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop16p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0... |
tactcomplabs/xbgas-binutils-gdb | 4,523 | sim/testsuite/bfin/c_dsp32alu_disalnexcpt.s | //Original:/testcases/core/c_dsp32alu_disalnexcpt/c_dsp32alu_disalnexcpt.dsp
// Spec Reference: c_dsp32alu_disalgnexcpt
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym P0, DATA1;
P0 += 1; I0 = P0;
loadsym P0, DATA2;
P0 += 1; I1 = P0;
loadsym P0, DATA3;
P0 += 1; I2 = P0;
loadsym P0, DATA4;... |
tactcomplabs/xbgas-binutils-gdb | 11,054 | sim/testsuite/bfin/se_loop_kill.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill/se_loop_kill.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
... |
tactcomplabs/xbgas-binutils-gdb | 5,532 | sim/testsuite/bfin/c_interr_nested.S | //Original:/proj/frio/dv/testcases/core/c_interr_nested/c_interr_nested.dsp
// Spec Reference: interrupt nested using raises
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_... |
tactcomplabs/xbgas-binutils-gdb | 11,033 | sim/testsuite/bfin/c_ldstiifp_st_dreg.s | //Original:testcases/core/c_ldstiifp_st_dreg/c_ldstiifp_st_dreg.dsp
// Spec Reference: c_ldstiifp store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 2,571 | sim/testsuite/bfin/c_dsp32shift_vmax.s | //Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp
// Spec Reference: dsp32shift vmax
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x11001001;
imm32 r1, 0x11001001;
imm32 r2, 0x12345678;
imm32 r3, 0x11001003;
imm32 r4, 0x11001004;
imm32 r5, 0x11001005;
imm32 r6, 0x11001006;
imm32 r7, 0x110... |
tactcomplabs/xbgas-binutils-gdb | 5,483 | sim/testsuite/bfin/c_regmv_pr_imlb.s | //Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp
// Spec Reference: regmv preg-to-imlb reg
# mach: bfin
.include "testutils.inc"
start
// check R-reg to imlb-reg move
imm32 r0, 0x00000001;
imm32 p1, 0x00020003;
imm32 p2, 0x00040005;
imm32 p3, 0x00060007;
imm32 p4, 0x00080009;
imm32 p5, 0x000a000b;
imm... |
tactcomplabs/xbgas-binutils-gdb | 1,052 | sim/testsuite/bfin/c_brcc_bp1.s | //Original:/testcases/core/c_brcc_bp1/c_brcc_bp1.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT =... |
tactcomplabs/xbgas-binutils-gdb | 6,030 | sim/testsuite/bfin/c_dsp32mult_dr_t.s | //Original:/testcases/core/c_dsp32mult_dr_t/c_dsp32mult_dr_t.dsp
// Spec Reference: dsp32mult single dr t
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd... |
tactcomplabs/xbgas-binutils-gdb | 3,441 | sim/testsuite/bfin/disalnexcpt_implicit.S | # Blackfin testcase for insns that implicitly have DISALGNEXCPT behavior
# when used in parallel insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
LINK 0x100;
# Set up I0/I1/I2/I3 to be unaligned by 0/1/2/3 bytes
init_l_regs 0
init_m_regs 0
R0 = SP;
BITCLR (R0, 0);
BITCLR (R0, 1);
I0 = R... |
tactcomplabs/xbgas-binutils-gdb | 1,605 | sim/testsuite/bfin/addsub_flags.S | // ACP 5.17 Dual ALU ops
// AZ, AN, AC0, AC1, V and VS are affected
// AV0, AV0S, AV1, AV1S are unaffected
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
A0 = A1 = 0;
r0=0;
r0.h=0x7fff;
r2=0;
r2.h=0x7000;
r1=r0+r2,r3=r0-r2;
r7=astat;
_dbg r1;
_dbg r3;
_dbg astat... |
tactcomplabs/xbgas-binutils-gdb | 1,384 | sim/testsuite/bfin/issue139.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
ASTAT = R0;
R0.L = 0x33;
R0.H = 0x55;
R1.L = 0x66;
R1.H = 0x77;
R7 = R1 +|+ R0, R6 = R1 -|- R0 (SCO , ASR);
_DBG R7;
CHECKREG R7, 0x0066004c;
CHECKREG R6, 0x00190011;
R7 = ... |
tactcomplabs/xbgas-binutils-gdb | 1,669 | sim/testsuite/bfin/c_dsp32alu_search.s | //Original:/testcases/core/c_dsp32alu_search/c_dsp32alu_search.dsp
// Spec Reference: dsp32alu search
# mach: bfin
.include "testutils.inc"
start
imm32 p0, 0x11234556;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444... |
tactcomplabs/xbgas-binutils-gdb | 4,211 | sim/testsuite/bfin/c_dsp32shiftim_a0alr.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp
// Spec Reference: dsp32shift a0 ashift, lshift, rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x11140000;
imm32 r1, 0x012C003E;
imm32 r2, 0x81359E24;
imm32 r3, 0x81459E24;
imm32 r4, 0xD159E2... |
tactcomplabs/xbgas-binutils-gdb | 6,857 | sim/testsuite/bfin/c_dsp32mac_a1a0_m.s | //Original:/testcases/core/c_dsp32mac_a1a0_m/c_dsp32mac_a1a0_m.dsp
// Spec Reference: dsp32mac a1 a0 m MNOP
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1
imm32 r0, 0... |
tactcomplabs/xbgas-binutils-gdb | 5,857 | sim/testsuite/bfin/c_dsp32alu_rh_rnd20_p.s | //Original:/testcases/core/c_dsp32alu_rh_rnd20_p/c_dsp32alu_rh_rnd20_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 1,075 | sim/testsuite/bfin/c_brcc_brf_brt_nbp.s | //Original:/testcases/core/c_brcc_brf_brt_nbp/c_brcc_brf_brt_nbp.dsp
// Spec Reference: brcc brf brt no bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7,... |
tactcomplabs/xbgas-binutils-gdb | 1,177 | sim/testsuite/bfin/m12.s | // Test extraction from accumulators:
// SCALE in SIGNED INTEGER mode
# mach: bfin
.include "testutils.inc"
start
// load r0=0x00000fff
// load r1=0x00007fff
// load r2=0xffffffff
// load r3=0xffff0fff
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R... |
tactcomplabs/xbgas-binutils-gdb | 1,750 | sim/testsuite/bfin/a21.s | // Test ALU RND RND12 RND20
# mach: bfin
.include "testutils.inc"
start
// positive saturation
R0 = 0xffffffff;
A0.w = R0;
A1.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// n... |
tactcomplabs/xbgas-binutils-gdb | 8,568 | sim/testsuite/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_rtn_lsmmrj_mvp/c_seq_wb_rtn_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( rtn ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.in... |
tactcomplabs/xbgas-binutils-gdb | 4,196 | sim/testsuite/bfin/s4.s | // Immediate SHIFT test program.
// Test r4 = ASHIFT (r2 by 10);
// Test r4 = LSHIFT (r2 by 10);
// Test r4 = ROT (r2 by 10);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// load r0=0x80000001
// load r1=0x00000000
// load r2=0x00000000
// load r3=0x00000000
// load r4=0x00000... |
tactcomplabs/xbgas-binutils-gdb | 5,543 | sim/testsuite/bfin/viterbi2.s | # mach: bfin
// The assembly program uses two instructions to speed the decoder inner loop:
// R6= VMAX/VMAX (R5, R4) A0>>2;
// R2 =H+L (SGN(R0)*R1);
// VMAX is a 2-way parallel comparison of four updated path metrics, resulting
// in 2 new path metrics as well as a 2 bit field indicating the selection
// res... |
tactcomplabs/xbgas-binutils-gdb | 6,056 | sim/testsuite/bfin/se_ssstep_dagprotviol.S | //Original:/proj/frio/dv/testcases/seq/se_ssstep_dagprotviol/se_ssstep_dagprotviol.dsp
// Description: prioritize DAG Protection Violation and Supervisor Single Step
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
includ... |
tactcomplabs/xbgas-binutils-gdb | 2,330 | sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_s1.s | //Original:/testcases/core/c_cc_regmvlogi_mvbrsft_s1/c_cc_regmvlogi_mvbrsft_s1.dsp
// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
A0 = 0;
A1 = 0;
imm32 r0, 0x00000020; // cc=1
imm32 r1, 0x00000000; // cc=0
imm32 r2, 0x62b61557;
imm32 r3, 0x073... |
tactcomplabs/xbgas-binutils-gdb | 3,298 | sim/testsuite/bfin/c_loopsetup_preg_stld.s | //Original:/testcases/core/c_loopsetup_preg_stld/c_loopsetup_preg_stld.dsp
// Spec Reference: loopsetup preg st & ld
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
A0 = 0;
A1 = 0;
ASTAT = r0;
P1 = 9;
P2 = 8;
P0 = 7;
P4 = 6;
P5 = 5;
FP = 3;
imm32 r0, 0x00200005;
imm32 r1, 0x00300010;
imm32... |
tactcomplabs/xbgas-binutils-gdb | 9,484 | sim/testsuite/bfin/c_ldstii_ld_dr_h.s | //Original:testcases/core/c_ldstii_ld_dr_h/c_ldstii_ld_dr_h.dsp
// Spec Reference: c_ldstii load dreg h
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
lo... |
tactcomplabs/xbgas-binutils-gdb | 1,517 | sim/testsuite/bfin/stk4.s | // load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R1 = 2;
R2 = 3;
R3 = ... |
tactcomplabs/xbgas-binutils-gdb | 4,425 | sim/testsuite/bfin/c_alu2op_divs.s | //Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp
// Spec Reference: alu2op divide s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R... |
tactcomplabs/xbgas-binutils-gdb | 3,649 | sim/testsuite/bfin/pushpopreg_1.s | # mach: bfin
.include "testutils.inc"
start
r0.l = 0x1111;
r0.h = 0x0011;
r1.l = 0x2222;
r1.h = 0x0022;
r2.l = 0x3333;
r2.h = 0x0033;
r3.l = 0x4444;
r3.h = 0x0044;
r4.l = 0x5555;
r4.h = 0x0055;
r5.l = 0x6666;
r5.h = 0x0066;
r6.l = 0x7777;
r6.h = 0x0077;
r7.l = 0x8888;
r7.h = 0x0088;
p1.l = 0x5a5a;
... |
tactcomplabs/xbgas-binutils-gdb | 1,850 | sim/testsuite/bfin/c_compi2opp_pr_eq_i7_p.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_p/c_compi2opp_pr_eq_i7_p.dsp
// Spec Reference: compi2opd pregs = imm7 positive
# mach: bfin
.include "testutils.inc"
start
//R0 = 0;
P1 = 1;
P2 = 2;
P3 = 3;
P4 = 4;
P5 = 5;
SP = 6;
FP = 7;
CHECKREG p1, 1;
CHECKREG p2, 2;
CHECKREG p3, 3;
CHE... |
tactcomplabs/xbgas-binutils-gdb | 6,433 | sim/testsuite/bfin/c_mode_user_superivsor.S | //Original:/proj/frio/dv/testcases/core/c_mode_user_superivsor/c_mode_user_superivsor.dsp
// Spec Reference: mode_user_supervisor
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
IN... |
tactcomplabs/xbgas-binutils-gdb | 1,777 | sim/testsuite/bfin/dsp_a8.s | /* ALU test program.
* Test instructions
* (r7,r6) = +/- (r0,r1);
* (r7,r6) = +/- (r0,r1)s;
*/
# mach: bfin
.include "testutils.inc"
start
// test positive overflow
R0.L = 0xffff;
R0.H = 0x7fff;
R1.L = 0x0001;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R6 = R0 + R1, R7 = R0 - R1 (NS);
DBGA ( R6.L , 0x0000 )... |
tactcomplabs/xbgas-binutils-gdb | 3,520 | sim/testsuite/bfin/c_dsp32mac_dr_a1_ih.s | //Original:/testcases/core/c_dsp32mac_dr_a1_ih/c_dsp32mac_dr_a1_ih.dsp
// Spec Reference: dsp32mac dr_a1 ih (int multiplication with word extraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x1dbcfec7;
imm... |
tactcomplabs/xbgas-binutils-gdb | 14,926 | sim/testsuite/bfin/c_compi2opd_flags.S | //Original:/proj/frio/dv/testcases/core/c_compi2opd_flags/c_compi2opd_flags.dsp
// Spec Reference: compi2opd dregs += imm7 flags (az, an, ac, av0)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = R0; // initialize astat
// AZ for R0
imm32 r0, 0x00000000;
R0 += 0; // az = 1 a... |
tactcomplabs/xbgas-binutils-gdb | 7,450 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_i.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_i/c_dsp32mac_pair_a1a0_i.dsp
// Spec Reference: dsp32mac pair a1a0 I
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645... |
tactcomplabs/xbgas-binutils-gdb | 4,974 | sim/testsuite/bfin/c_dsp32shift_expadj_r.s | //Original:/testcases/core/c_dsp32shift_expadj_r/c_dsp32shift_expadj_r.dsp
// Spec Reference: dsp32shift expadj r
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x08000800;
imm32 r1, 0x08000801;
imm32 r2, 0x08000802;
imm32 r3, 0x08000803;
imm32 r4, 0x08000804;
imm32 r5, 0x08000805;
imm32 r6, 0x08000806;
imm... |
tactcomplabs/xbgas-binutils-gdb | 9,187 | sim/testsuite/bfin/c_ldstii_ld_dreg.s | //Original:testcases/core/c_ldstii_ld_dreg/c_ldstii_ld_dreg.dsp
// Spec Reference: c_ldstii load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loads... |
tactcomplabs/xbgas-binutils-gdb | 10,540 | sim/testsuite/bfin/se_oneins_zoff.S | //Original:/proj/frio/dv/testcases/seq/se_oneins_zoff/se_oneins_zoff.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////////////... |
tactcomplabs/xbgas-binutils-gdb | 9,517 | sim/testsuite/bfin/c_dsp32shift_pack.s | //Original:/testcases/core/c_dsp32shift_pack/c_dsp32shift_pack.dsp
// Spec Reference: dsp32shift pack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01230000;
imm32 r1, 0x02345678;
imm32 r2, 0x03456789;
imm32 r3, 0x0456789a;
imm32 r4, 0x056789ab;
imm32 r5, 0x06789abc;
imm32 r6, 0x0789abcd;
imm32 r7, 0x089... |
tactcomplabs/xbgas-binutils-gdb | 1,411 | sim/testsuite/bfin/stk2.s | // load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R1 = 2;
R2 = 3;
R3 =... |
tactcomplabs/xbgas-binutils-gdb | 9,384 | sim/testsuite/bfin/se_rts_rti.S | //Original:/proj/frio/dv/testcases/seq/se_rts_rti/se_rts_rti.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
////... |
tactcomplabs/xbgas-binutils-gdb | 10,475 | sim/testsuite/bfin/c_ldstiifp_st_preg.s | //Original:testcases/core/c_ldstiifp_st_preg/c_ldstiifp_st_preg.dsp
// Spec Reference: c_ldstiifp store preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
... |
tactcomplabs/xbgas-binutils-gdb | 9,932 | sim/testsuite/bfin/c_dsp32shift_ahalf_rp.s | //Original:/testcases/core/c_dsp32shift_ahalf_rp/c_dsp32shift_ahalf_rp.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00000001;
imm32... |
tactcomplabs/xbgas-binutils-gdb | 3,408 | sim/testsuite/bfin/s19.s | // REG-BASED dual 16b SHIFT test program.
// Test r4 = ASHIFT/ASHIFT (r2 by rl1);
// Test r4 = ASHIFT/ASHIFT (r2 by rl1) S;
// Test r4 = LSHIFT/LSHIFT (r2 by rl1);
# mach: bfin
.include "testutils.inc"
start
// arithmetic
// left by largest positive magnitude of 15 (0xf)
// 8001 -> 8000
R7 = 0;
ASTAT = R7... |
tactcomplabs/xbgas-binutils-gdb | 1,637 | sim/testsuite/bfin/c_loopsetup_preg_lc0.s | //Original:/testcases/core/c_loopsetup_preg_lc0/c_loopsetup_preg_lc0.dsp
// Spec Reference: loopsetup preg lc0
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0... |
tactcomplabs/xbgas-binutils-gdb | 2,555 | sim/testsuite/bfin/c_brcc_kills_dhits.s | //Original:/testcases/core/c_brcc_kills_dhits/c_brcc_kills_dhits.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x000000... |
tactcomplabs/xbgas-binutils-gdb | 3,885 | sim/testsuite/bfin/c_dsp32mac_dr_a1a0_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_m/c_dsp32mac_dr_a1a0_m.dsp
// Spec Reference: dsp32mac dr_a1a0 m
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xb2bcfec7;
i... |
tactcomplabs/xbgas-binutils-gdb | 1,570,263 | sim/testsuite/bfin/se_all32bitopcodes.S | /*
* Blackfin testcase for testing illegal/legal 32-bit opcodes from userspace
* we track all instructions which cause some sort of exception when run from
* userspace, this is normally EXCAUSE :
* - 0x21 : illegal instruction
* - 0x22 : illegal instruction combination
* - 0x2e : use of supervisor resource fro... |
tactcomplabs/xbgas-binutils-gdb | 6,094 | sim/testsuite/bfin/c_dsp32mult_dr_i.s | //Original:/testcases/core/c_dsp32mult_dr_i/c_dsp32mult_dr_i.dsp
// Spec Reference: dsp32mult single dr i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd... |
tactcomplabs/xbgas-binutils-gdb | 96,673 | sim/testsuite/bfin/lmu_cplb_multiple1.S | //Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple1/lmu_cplb_multiple1.dsp
// Description: Multiple CPLB Hit exceptions (DAG1)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------... |
tactcomplabs/xbgas-binutils-gdb | 3,994 | sim/testsuite/bfin/c_pushpopmultiple_dp.s | //Original:/testcases/core/c_pushpopmultiple_dp/c_pushpopmultiple_dp.dsp
// Spec Reference: pushpopmultiple dreg preg single group
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08... |
tactcomplabs/xbgas-binutils-gdb | 2,096 | sim/testsuite/bfin/hwloop-branch-out.s | # Blackfin testcase for branching out of the middle of a hardware loop
# mach: bfin
.include "testutils.inc"
.macro test_prep lc:req, sym:req
imm32 P0, \lc
loadsym P1, \sym
R5 = 0;
R6 = 0;
R7 = 0;
LSETUP (1f, 2f) LC0 = P0;
.endm
.macro test_check exp5:req, exp6:req, exp7:req, expLC
imm32 R4, \exp5;
CC = ... |
tactcomplabs/xbgas-binutils-gdb | 10,005 | sim/testsuite/bfin/c_ldstii_st_preg.s | //Original:/testcases/core/c_ldstii_st_preg/c_ldstii_st_preg.dsp
// Spec Reference: c_ldstii store preg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 1,240 | sim/testsuite/bfin/c_dsp32shiftim_ahh.s | //Original:/testcases/core/c_dsp32shiftim_ahh/c_dsp32shiftim_ahh.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift / ashift
imm32 r0, 0x01230abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0... |
tactcomplabs/xbgas-binutils-gdb | 5,756 | sim/testsuite/bfin/dbg_tr_basic.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_basic/dbg_tr_basic.dsp
// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
// Supervisor mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfche... |
tactcomplabs/xbgas-binutils-gdb | 5,610 | sim/testsuite/bfin/c_ccflag_dr_dr_uu.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr_uu/c_ccflag_dr_dr_uu.dsp
// Spec Reference: ccflags dr-dr_uu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00110022;
imm32 r1, 0x00110022;
imm32 r2, 0x00330044;
imm32 r3, 0x00550066;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
i... |
tactcomplabs/xbgas-binutils-gdb | 4,138 | sim/testsuite/bfin/c_dsp32mac_dr_a1_u.s | //Original:/testcases/core/c_dsp32mac_dr_a1_u/c_dsp32mac_dr_a1_u.dsp
// Spec Reference: dsp32mac dr_a1 u (unsigned fraction & unsigned int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbabcfec7;
imm32 r2, 0xc... |
tactcomplabs/xbgas-binutils-gdb | 1,335 | sim/testsuite/bfin/add_sub_acc.s | // ACP 5.9 A0 -= A1 doesn't set flags
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x0);
dbga (r7.l, 0x1006);
A1 = A0 = 0;
R0 = 0x1 (z);
astat=r0;
... |
tactcomplabs/xbgas-binutils-gdb | 8,348 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_ln.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_ln/c_dsp32shiftim_lhalf_ln.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : neg data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
im... |
tactcomplabs/xbgas-binutils-gdb | 7,285 | sim/testsuite/bfin/c_seq_ex1_raise_call_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_call_mv_pop/c_seq_ex1_raise_call_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ call + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
inclu... |
tactcomplabs/xbgas-binutils-gdb | 8,454 | sim/testsuite/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_raise_ls_mmrj_mvp/c_seq_ex3_raise_ls_mmrj_mvp.dsp
// Spec Reference: sequencer stage ex3 (raise+ ldst + mmr + jump+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfchec... |
tactcomplabs/xbgas-binutils-gdb | 7,160 | sim/testsuite/bfin/c_ldstpmod_ld_dr_lo.s | //Original:testcases/core/c_ldstpmod_ld_dr_lo/c_ldstpmod_ld_dr_lo.dsp
// Spec Reference: c_ldstpmod load dr lo
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS(0);
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = ... |
tactcomplabs/xbgas-binutils-gdb | 3,495 | sim/testsuite/bfin/cc-alu.S | # Blackfin testcase for CC/A0/A1 compares
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
/* Clear ASTAT before test */
#define CHECK_ASTAT(op, exp) ASTAT = R2; CC = A0 op A1; check_astat exp
.macro check_astat exp:req
R5 = ASTAT;
R6 = \exp;
CC = R5 == R6;
IF !CC JUMP 1f;
.endm
.macro _acc_te... |
tactcomplabs/xbgas-binutils-gdb | 8,819 | sim/testsuite/bfin/c_ccflag_pr_imm3.s | //Original:/testcases/core/c_ccflag_pr_imm3/c_ccflag_pr_imm3.dsp
// Spec Reference: ccflag pr-imm3
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00000001;
imm32 p1, 0x00000001;
imm32 p2, 0x00000002;
imm32 p3, 0x00000003;
imm32 p4, 0x00000001;
imm32 p5, 0x00000002;
imm32 sp, 0x00000003;
i... |
tactcomplabs/xbgas-binutils-gdb | 2,920 | sim/testsuite/bfin/c_loopsetup_nested.s | //Original:/testcases/core/c_loopsetup_nested/c_loopsetup_nested.dsp
// Spec Reference: loopsetup nested inside
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = ... |
tactcomplabs/xbgas-binutils-gdb | 1,672 | sim/testsuite/bfin/random_0007.S | # Make sure the acc regs are updated even when the search criteria is not met
# (this implicitly affects the top 8 bits)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x08e00690 | _VS | _AC1 | _AN);
dmm32 A0.w, 0x42357aea;
dmm32 A0.x, 0x00000001;
dmm32 A1.w, 0x3a3f0000;
dmm32 A1.x,... |
tactcomplabs/xbgas-binutils-gdb | 9,660 | sim/testsuite/bfin/c_ldstidxl_ld_dr_b.s | //Original:testcases/core/c_ldstidxl_ld_dr_b/c_ldstidxl_ld_dr_b.dsp
// Spec Reference: c_ldstidxl load dreg B (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
// initial values
loadsym p1, DATA_ADDR_... |
tactcomplabs/xbgas-binutils-gdb | 1,523 | sim/testsuite/bfin/s7.s | // Test r4 = VMAX/VMAX (r5,r1) A0>>2;
# mach: bfin
.include "testutils.inc"
start
// Both max values are in high half, hence both bits
// into A0 are 1
A0 = 0;
R1.L = 0x2; // max in r1 is 3
R1.H = 0x3;
R0.L = 0x6; // max in r0 is 7
R0.H = 0x7;
R6 = VIT_MAX( R1 , R0 ) (ASR);
DBGA ( R6.L , 0x0007 );
DBG... |
tactcomplabs/xbgas-binutils-gdb | 1,513 | sim/testsuite/bfin/c_dsp32alu_rrpm_aa.s | //Original:/testcases/core/c_dsp32alu_rrpm_aa/c_dsp32alu_rrpm_aa.dsp
// Spec Reference: dsp32alu (dregs, dregs) = +/- (a, a) amod1
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
imm32 r0, 0x75678911;
imm32 r1, 0xa789ab2d;
imm32 r2, 0x34745515;
imm32 r3, 0x46677757;
imm32 r4, 0xb567a96b;
imm32 r5, 0x6789... |
tactcomplabs/xbgas-binutils-gdb | 2,713 | sim/testsuite/bfin/se_regmv_usp_sysreg.S | //Original:/proj/frio/dv/testcases/seq/se_regmv_usp_sysreg/se_regmv_usp_sysreg.dsp
// Description: RegMV USP to SYSREG
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(selfcheck.inc)
include(std.inc)
include(symtable.inc)
//*********... |
tactcomplabs/xbgas-binutils-gdb | 4,844 | sim/testsuite/bfin/c_dsp32mult_dr_m_u.s | //Original:/testcases/core/c_dsp32mult_dr_m_u/c_dsp32mult_dr_m_u.dsp
// Spec Reference: dsp32mult single dr munop u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm... |
tactcomplabs/xbgas-binutils-gdb | 8,862 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_rp_s/c_dsp32shiftim_ahalf_rp_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32... |
tactcomplabs/xbgas-binutils-gdb | 11,453 | sim/testsuite/bfin/c_ldstpmod_st_dreg.s | //Original:testcases/core/c_ldstpmod_st_dreg/c_ldstpmod_st_dreg.dsp
// Spec Reference: c_ldstpmod store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 2,875 | sim/testsuite/bfin/c_dsp32mac_dr_a0_ih.s | //Original:/testcases/core/c_dsp32mac_dr_a0_ih/c_dsp32mac_dr_a0_ih.dsp
// Spec Reference: dsp32mac dr a0 ih (integer mutiplication with high word extraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfe... |
tactcomplabs/xbgas-binutils-gdb | 8,717 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_rn.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_rn/c_dsp32shiftim_lhalf_rn.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : neg data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0... |
tactcomplabs/xbgas-binutils-gdb | 5,914 | sim/testsuite/bfin/c_dsp32alu_rl_p.s | //Original:/testcases/core/c_dsp32alu_rl_p/c_dsp32alu_rl_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x19678911;
imm32 r1, 0x2799ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x8... |
tactcomplabs/xbgas-binutils-gdb | 3,546 | sim/testsuite/bfin/c_logi2op_alshft_mix.s | //Original:/testcases/core/c_logi2op_alshft_mix/c_logi2op_alshft_mix.dsp
// Spec Reference: Logi2op >>>=, >>=, <<=
# mach: bfin
.include "testutils.inc"
start
// Arithmetic >>>= : positive data
imm32 r0, 0x40000000;
imm32 r1, 0x01111111;
imm32 r2, 0x22222222;
imm32 r3, 0x33333333;
imm32 r4, 0x44444444;
imm32 r5, 0x5... |
tactcomplabs/xbgas-binutils-gdb | 9,855 | sim/testsuite/bfin/lmu_excpt_prot1.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot1/lmu_excpt_prot1.dsp
// Description: LMU protection exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
// Test ... |
tactcomplabs/xbgas-binutils-gdb | 4,247 | sim/testsuite/bfin/c_multi_issue_dsp_ldst_1.s | //Original:/testcases/core/c_multi_issue_dsp_ldst_1/c_multi_issue_dsp_ldst_1.dsp
// Spec Reference: dsp32mac and 2 load/store
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0;
loadsym I1, DATA1;
loadsym P1, DATA0;
loadsym P2, ... |
tactcomplabs/xbgas-binutils-gdb | 3,068 | sim/testsuite/bfin/c_dsp32mac_mix.s | //Original:/testcases/core/c_dsp32mac_mix/c_dsp32mac_mix.dsp
// Spec Reference: dsp32mac mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246700f;
A1 ... |
tactcomplabs/xbgas-binutils-gdb | 1,575 | sim/testsuite/bfin/push-pop.s | # Blackfin testcase for push/pop instructions
# mach: bfin
.include "testutils.inc"
start
# This uses R0/R1 as scratch ... assume those work fine in general
.macro check loader:req, reg:req
\loader \reg, 0x12345678
[--SP] = \reg;
R0 = [SP];
R1 = \reg;
CC = R0 == R1;
IF !CC JUMP 8f;
\loader \reg, 0x8765432... |
tactcomplabs/xbgas-binutils-gdb | 7,291 | sim/testsuite/bfin/c_seq_ex1_call_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_call_mv_pop/c_seq_ex1_call_mv_pop.dsp
// Spec Reference: sequencer stage ex1 ( call + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
IN... |
tactcomplabs/xbgas-binutils-gdb | 7,990 | sim/testsuite/bfin/c_comp3op_dr_or_dr.s | //Original:/testcases/core/c_comp3op_dr_or_dr/c_comp3op_dr_or_dr.dsp
// Spec Reference: comp3op dregs | dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 ... |
tactcomplabs/xbgas-binutils-gdb | 10,646 | sim/testsuite/bfin/c_ldstidxl_ld_dr_xh.s | //Original:testcases/core/c_ldstidxl_ld_dr_xh/c_ldstidxl_ld_dr_xh.dsp
// Spec Reference: c_ldstidxl load dreg XH (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I... |
tactcomplabs/xbgas-binutils-gdb | 11,801 | sim/testsuite/bfin/se_loop_mv2lt_stall.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lt_stall/se_loop_mv2lt_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////... |
tactcomplabs/xbgas-binutils-gdb | 11,826 | sim/testsuite/bfin/se_loop_mv2lc_stall.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc_stall/se_loop_mv2lc_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////... |
tactcomplabs/xbgas-binutils-gdb | 1,166 | sim/testsuite/bfin/c_dsp32shiftim_af.s | //Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
i... |
tactcomplabs/xbgas-binutils-gdb | 5,096 | sim/testsuite/bfin/c_dsp32shift_fextx.s | //Original:/testcases/core/c_dsp32shift_fextx/c_dsp32shift_fextx.dsp
// Spec Reference: dsp32shift fext x
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x0... |
tactcomplabs/xbgas-binutils-gdb | 5,510 | sim/testsuite/bfin/c_progctrl_csync_mmr.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_csync_mmr/c_progctrl_csync_mmr.dsp
// Spec Reference: csync mmr timer
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS... |
tactcomplabs/xbgas-binutils-gdb | 5,857 | sim/testsuite/bfin/c_dsp32alu_rl_rnd20_p.s | //Original:/testcases/core/c_dsp32alu_rl_rnd20_p/c_dsp32alu_rl_rnd20_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x75678911;
imm32 r1, 0xa789ab1d;
imm32 r2, 0x34745515;
imm32 r3, 0x4b677717;
imm32 r4, 0x5678791b;
imm32 r5, 0xc789a71d;
imm32 r6, 0x74445515;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 2,761 | sim/testsuite/bfin/c_dsp32mac_dr_a0_iu.s | //Original:/testcases/core/c_dsp32mac_dr_a0_iu/c_dsp32mac_dr_a0_iu.dsp
// Spec Reference: dsp32mac dr a0 iu (unsigned int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x83545abd;
imm32 r1, 0x78bcfec7;
imm32 r2, 0xc7948679;
imm32 r3,... |
tactcomplabs/xbgas-binutils-gdb | 14,252 | sim/testsuite/bfin/random_0013.S | # Ensure that dsp insns with IH modifiers saturate first, then round
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x24304400 | _VS | _AV1S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x3883de11;
dmm32 A0.x, 0x00000025;
imm32 R2, 0xeb641947;
imm32 R3, 0x66d10863;
imm... |
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