repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 11,845 | sim/testsuite/bfin/dbg_brtkn_nprd_src_kill.S | //Original:/proj/frio/dv/testcases/debug/dbg_brtkn_nprd_src_kill/dbg_brtkn_nprd_src_kill.dsp
// Description: This test checks that the trace buffer keeps track of a
// branch source instruction that is taken but not predicted getting killed
// at each stage in the pipe. The test consists of 8 instances of an EXCPT
// ... |
tactcomplabs/xbgas-binutils-gdb | 10,384 | sim/testsuite/bfin/c_dsp32shift_ahalf_rp_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_rp_s/c_dsp32shift_ahalf_rp_s.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00000001;
im... |
tactcomplabs/xbgas-binutils-gdb | 7,005 | sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh1.s | //Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh1/c_comp3op_pr_plus_pr_sh1.dsp
// Spec Reference: comp3op pregs + pregs << 1
# mach: bfin
.include "testutils.inc"
start
imm32 p1, 0x89ab1def;
imm32 p2, 0x56781abc;
imm32 p3, 0xdef01234;
imm32 p4, 0x23451899;
imm32 p5, 0x78911345;
imm32 sp, 0x98... |
tactcomplabs/xbgas-binutils-gdb | 2,905 | sim/testsuite/bfin/byteop16m.s | # Blackfin testcase for BYTEOP16M
# mach: bfin
.include "testutils.inc"
start
.macro check_it resL:req, resH:req
imm32 R6, \resL
CC = R4 == R6;
IF !CC JUMP 1f;
#DBG R4
imm32 R7, \resH
CC = R5 == R7;
IF !CC JUMP 1f;
#DBG R5
.endm
.macro test_byteop16m i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:re... |
tactcomplabs/xbgas-binutils-gdb | 4,341 | sim/testsuite/bfin/c_dsp32shift_af.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_af/c_dsp32shift_af.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// ashift : mix data, count (+)= (half reg)
// d_reg = ashift (d BY d_lo)
// Rx by ... |
tactcomplabs/xbgas-binutils-gdb | 4,914 | sim/testsuite/bfin/fir.s | # mach: bfin
// FIR FILTER COMPTUED DIRECTLY ON INPUT WITH NO
// INTERNAL STATE
// TWO OUTPUTS PER ITERATION
// This program computes a FIR filter without maintaining a buffer of internal
// state.
// This example computes two output samples per inner loop. The following
// diagram shows the alignment required for... |
tactcomplabs/xbgas-binutils-gdb | 4,640 | sim/testsuite/bfin/c_alu2op_shadd_2.s | //Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp
// Spec Reference: alu2op shadd 2
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bc... |
tactcomplabs/xbgas-binutils-gdb | 10,070 | sim/testsuite/bfin/c_dsp32shift_lhalf_ln.s | //Original:/testcases/core/c_dsp32shift_lhalf_ln/c_dsp32shift_lhalf_ln.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : neg data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;... |
tactcomplabs/xbgas-binutils-gdb | 8,478 | sim/testsuite/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_raisecs_lsmmrj_mvp/c_seq_wb_raisecs_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb (raise csync ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
inc... |
tactcomplabs/xbgas-binutils-gdb | 8,302 | sim/testsuite/bfin/c_ldstpmod_ld_h_xh.s | //Original:testcases/core/c_ldstpmod_ld_h_xh/c_ldstpmod_ld_h_xh.dsp
// Spec Reference: c_ldstpmod load dreg h & xh
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0002;
P2 = 0x0002;
P... |
tactcomplabs/xbgas-binutils-gdb | 1,217 | sim/testsuite/bfin/c_ccmv_cc_dr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccmv_cc_dr_pr/c_ccmv_cc_dr_pr.dsp
// Spec Reference: ccmv cc dpreg = dpreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x138d2301;
imm32 r1, 0x20421053;
imm32 r2, 0x3f051405;
imm32 r3, 0x40b66507;
imm32 r4, 0x50487709;
imm32 r5, 0x60059... |
tactcomplabs/xbgas-binutils-gdb | 4,000 | sim/testsuite/bfin/c_dsp32alu_mix.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_mix/c_dsp32alu_mix.dsp
// Spec Reference: dsp32alu mix
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// ALU operations include parallel addition, subtraction, MAX, MIN, ABS on 16-bit
// and 32-bit data. If an operation use a single ALU only, it ... |
tactcomplabs/xbgas-binutils-gdb | 3,814 | sim/testsuite/bfin/c_dsp32mac_dr_a1a0.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0/c_dsp32mac_dr_a1a0.dsp
// Spec Reference: dsp32mac dr_a1a0
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xb2bcfec7;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 6,303 | sim/testsuite/bfin/c_dsp32mac_pair_a0_s.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_s/c_dsp32mac_pair_a0_s.dsp
// Spec Reference: dsp32mac pair a0 S
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
... |
tactcomplabs/xbgas-binutils-gdb | 7,970 | sim/testsuite/bfin/c_ldstpmod_ld_dreg.s | //Original:testcases/core/c_ldstpmod_ld_dreg/c_ldstpmod_ld_dreg.dsp
// Spec Reference: c_ldstpmod load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0004;
P2 = 0x0004;
P3 = 0x0004;
P4 = 0x00... |
tactcomplabs/xbgas-binutils-gdb | 13,476 | sim/testsuite/bfin/c_regmv_imlb_imlb.s | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_imlb/c_regmv_imlb_imlb.dsp
// Spec Reference: regmv imlb-imlb
# mach: bfin
.include "testutils.inc"
start
// initialize source regs
imm32 i0, 0x11111111;
imm32 i1, 0x22222222;
imm32 i2, 0x33333333;
imm32 i3, 0x44444444;
imm32 m0, 0x55555555;
imm32 m1, 0x6666... |
tactcomplabs/xbgas-binutils-gdb | 1,219 | sim/testsuite/bfin/s10.s | // Shifter test program.
// Test instructions
// RL0 = SIGNBITS R1;
// RL0 = SIGNBITS RL1;
// RL0 = SIGNBITS RH1;
# mach: bfin
.include "testutils.inc"
start
// on 32-b word
R1.L = 0xffff;
R1.H = 0x7fff;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0000 );
R1.L = 0xffff;
R1.H = 0x30ff;
R0.L = SIGNBITS R1;
DB... |
tactcomplabs/xbgas-binutils-gdb | 9,029 | sim/testsuite/bfin/c_ldstiifp_ld_dreg.s | //Original:testcases/core/c_ldstiifp_ld_dreg/c_ldstiifp_ld_dreg.dsp
// Spec Reference: c_ldstiifp load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0000;
P2 = 0x0004;
P3 = 0x0... |
tactcomplabs/xbgas-binutils-gdb | 3,104 | sim/testsuite/bfin/c_dspldst_st_dr_i.s | //Original:/testcases/core/c_dspldst_st_dr_i/c_dspldst_st_dr_i.dsp
// Spec Reference: c_dspldst st_dr_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 ... |
tactcomplabs/xbgas-binutils-gdb | 4,845 | sim/testsuite/bfin/c_dsp32shift_align16.s | //Original:/testcases/core/c_dsp32shift_align16/c_dsp32shift_align16.dsp
// Spec Reference: dsp32shift align16
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7... |
tactcomplabs/xbgas-binutils-gdb | 1,239 | sim/testsuite/bfin/c_dsp32alu_rlh_rnd.s | //Original:/testcases/core/c_dsp32alu_rlh_rnd/c_dsp32alu_rlh_rnd.dsp
// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cd... |
tactcomplabs/xbgas-binutils-gdb | 1,693 | sim/testsuite/bfin/c_dagmodim_lnz_imgebl.s | //Original:/testcases/core/c_dagmodim_lnz_imgebl/c_dagmodim_lnz_imgebl.dsp
// Spec Reference: dagmodim l not zero & i+m >= b+l
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x00001000;
imm32 b1, 0x000010... |
tactcomplabs/xbgas-binutils-gdb | 7,100 | sim/testsuite/bfin/random_0028.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x44004010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0x851fa4fc;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x00000000;
imm32 R2, 0x80000000;
imm32 R5, 0x139d77b4;
R5.H = (A1 += R2.L * R0.L) (M, S2RND);
checkre... |
tactcomplabs/xbgas-binutils-gdb | 10,643 | sim/testsuite/bfin/c_ldstidxl_ld_dr_h.s | //Original:testcases/core/c_ldstidxl_ld_dr_h/c_ldstidxl_ld_dr_h.dsp
// Spec Reference: c_ldstidxl load dreg H (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 =... |
tactcomplabs/xbgas-binutils-gdb | 13,554 | sim/testsuite/bfin/c_ldstidxl_st_dreg.s | //Original:testcases/core/c_ldstidxl_st_dreg/c_ldstidxl_st_dreg.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 6,911 | sim/testsuite/bfin/random_0022.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2090c600 | _VS | _AC1 | _AQ | _CC | _AN);
dmm32 A0.w, 0xf041e418;
dmm32 A0.x, 0xffffffff;
imm32 R4, 0x51296cc2;
imm32 R7, 0xca05cb74;
R4.L = (A0 += R7.H * R4.L) (TFU);
checkreg R4, 0x5129ffff;
checkreg A0.w, 0xffffffff;
checkreg A... |
tactcomplabs/xbgas-binutils-gdb | 4,351 | sim/testsuite/bfin/c_multi_issue_dsp_ldst_2.s | //Original:/testcases/core/c_multi_issue_dsp_ldst_2/c_multi_issue_dsp_ldst_2.dsp
// Spec Reference: dsp32mac and 2 load/store
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0;
loadsym I1, DATA1;
loadsym P1, DATA0... |
tactcomplabs/xbgas-binutils-gdb | 1,288 | sim/testsuite/bfin/random_0008.S | # check ASTAT ac/av flags are handled correctly when doing Acc = -Acc
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5020ca80 | _VS | _AV1S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x549e07b3;
dmm32 A1.x, 0x0000002a;
A1 = -A1;
checkreg A1.w, 0xab61f84d;
checkreg ... |
tactcomplabs/xbgas-binutils-gdb | 6,210 | sim/testsuite/bfin/c_dsp32mac_pair_a0_u.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_u/c_dsp32mac_pair_a0_u.dsp
// Spec Reference: dsp32mac pair a0 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
... |
tactcomplabs/xbgas-binutils-gdb | 10,611 | sim/testsuite/bfin/c_dsp32shift_ahh_s.s | //Original:/testcases/core/c_dsp32shift_ahh_s/c_dsp32shift_ahh_s.dsp
// Spec Reference: dsp32shift ashift/ashift s
# mach: bfin
.include "testutils.inc"
start
// ashift/ashift s : positive data, count (+)=left (half reg)
// d_reg = ashift/ashift (d BY d_lo) saturation
// Rx by RLx
imm32 r0, 0x01230000;
imm32 r1, 0... |
tactcomplabs/xbgas-binutils-gdb | 6,583 | sim/testsuite/bfin/c_seq_dec_raise_pushpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_dec_raise_pushpop/c_seq_dec_raise_pushpop.dsp
// Spec Reference: sequencer stage DEC (raise + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_... |
tactcomplabs/xbgas-binutils-gdb | 6,520 | sim/testsuite/bfin/c_dspldst_ld_drlo_ipp.s | //Original:/testcases/core/c_dspldst_ld_drlo_ipp/c_dspldst_ld_drlo_ipp.dsp
// Spec Reference: c_dspldst ld_drlo_i++/--
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load Lower half of Dregs
R0.... |
tactcomplabs/xbgas-binutils-gdb | 2,246 | sim/testsuite/bfin/cec-no-snen-reti.S | # Blackfin testcase for having RETI LSB set correctly when not self nested
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set our handler
imm32 P5, EVT11;
loadsym R1, _ivg11;
[P5] = R1;
loadsym R1, _fail_lvl;
[P5 + 4] = R1; /* IVG12 */
[P5 + 12] = R1; /* IVG14... |
tactcomplabs/xbgas-binutils-gdb | 2,606 | sim/testsuite/bfin/random_0037.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x1880c200 | _VS | _AV1S | _AV0S | _AC1);
dmm32 A0.w, 0x2b9a5661;
dmm32 A0.x, 0x00000032;
dmm32 A1.w, 0x1a0c4c8c;
dmm32 A1.x, 0xffffff80;
imm32 R0, 0x694a9cb0;
imm32 R6, 0x651cc0dd;
A1 += R0.L * R0.H (M), R6.L = (A0 += R0.L * R0.H) (... |
tactcomplabs/xbgas-binutils-gdb | 2,252 | sim/testsuite/bfin/c_regmv_acc_acc.s | //Original:/testcases/core/c_regmv_acc_acc/c_regmv_acc_acc.dsp
// Spec Reference: regmv acc-acc
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa9627911;
imm32 r1, 0xd0158978;
imm32 r2, 0xc1234567;
imm32 r3, 0x10060007;
imm32 r4, 0x02080009;
imm32 r5, 0x003a000b;
imm32 r6, 0x0004000d;
imm32 r7, 0x000... |
tactcomplabs/xbgas-binutils-gdb | 14,915 | sim/testsuite/bfin/c_compi2opd_flags_2.S | //Original:/proj/frio/dv/testcases/core/c_compi2opd_flags_2/c_compi2opd_flags_2.dsp
// Spec Reference: compi2opd dregs += imm7 flags_2 (az, an, ac, av0)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = R0; // initialize astat
// AZ for R0
imm32 r0, 0x00000000;
R0 += 0; // az... |
tactcomplabs/xbgas-binutils-gdb | 2,930 | sim/testsuite/bfin/c_loopsetup_overlap.s | //Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp
// Spec Reference: loopsetup overlap
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50... |
tactcomplabs/xbgas-binutils-gdb | 3,637 | sim/testsuite/mips/r6.s | # mips r6 tests (non FPU)
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.data
dval1: .word 0xabcd1234
dval2: .word 0x1234eeff
.fill 248,1,0
dval3: .word 0x55555555
.fill 260,1,0
dval4: .word 0xaa... |
tactcomplabs/xbgas-binutils-gdb | 6,187 | sim/testsuite/mips/fpu64-ps.s | # mips test sanity, expected to pass.
# mach: mips64 sb1
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.macro check_ps psval, upperval, lowerval
.set push
.set noreorder
cvt.s.pu $f0, \psval # upper
cvt.s.pl $f2, \psval # lower
li.s $f4, \upperval
li.s... |
tactcomplabs/xbgas-binutils-gdb | 2,209 | sim/testsuite/mips/mdmx-ob-sb1.s | # MDMX .OB op tests.
# mach: sb1
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-mdmx.inc"
setup
.set noreorder
.ent DIAG
DIAG:
enable_mdmx
# set Status.SBX to enable SB-1 extensions.
mfc0 $2, $12
or $2, $2, (1 << 16)
mtc0 $2, $12
###
###... |
tactcomplabs/xbgas-binutils-gdb | 21,770 | sim/testsuite/mips/r6-fpu.s | # mips r6 fpu test for FMADD/FMSUB etc.
# mach: mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.set noreorder
.ent DIAG
DIAG:
writemsg "[1] Test qNaN format is 754-2008"
li $4, 0x0
li $5, 0x0
li $6, 0x7fc000... |
tactcomplabs/xbgas-binutils-gdb | 1,017,027 | sim/testsuite/mips/mips32-dsp2.s | # MIPS32 DSP REV 2 ASE test
# mach: mips32r2 mips64r2
#as: -mdspr2
#ld: -N -Ttext=0x80010000
#output: *\\npass\\n
# Copyright (C) 2006 MIPS Technologies, Inc.
# All rights reserved.
# Contributed by Chao-ying Fu (fu@mips.com).
#
# This file is part of the GNU simulators.
#
# This program is free software; you can r... |
tactcomplabs/xbgas-binutils-gdb | 3,397 | sim/testsuite/mips/r6-64.s | # mips64 specific r6 tests (non FPU)
# mach: mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
.data
d0: .dword 0
dval: .dword 0xaa55bb66cc77dd88
d1: .dword 0xaaaabbbbccccdddd
d2: .dword 256
dlo: .dword 0xa... |
tactcomplabs/xbgas-binutils-gdb | 3,374 | sim/testsuite/mips/r6-branch.s | # mips r6 branch tests (non FPU)
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.set noreorder
.ent DIAG
DIAG:
li $14, 0xffffffff
li $13, 0x123
li $12, 0x45
li $7, 0x45
li $8, 0xfffffffe
li ... |
tactcomplabs/xbgas-binutils-gdb | 1,054 | sim/testsuite/mips/hilo-hazard-4.s | # Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
#
# mach: all
# as: -mabi=eabi -mmicromips
# ld: -N -Ttext=0x80010000
# output: pass\\n
# Copyright (C) 2013-2022 Free Software Foundation, Inc.
# Contributed by Andrew Bennett (andrew.bennett@imgtec.com)
#
# This file is part of the MIPS sim.
#
# Th... |
tactcomplabs/xbgas-binutils-gdb | 36,048 | sim/testsuite/mips/mips32-dsp.s | # MIPS32 DSP ASE test
# mach: mips32r2 mips64r2
#as: -mdsp
#ld: -N -Ttext=0x80010000
#output: *\\npass\\n
# Copyright (C) 2005-2022 Free Software Foundation, Inc.
# Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.
#
# This file is part of the GNU simulators.
#
# This program is free software; you ca... |
tactcomplabs/xbgas-binutils-gdb | 1,089 | sim/testsuite/mips/fpu64-ps-sb1.s | # mips test sanity, expected to pass.
# mach: sb1
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.macro check_ps psval, upperval, lowerval
.set push
.set noreorder
cvt.s.pu $f0, \psval # upper
cvt.s.pl $f2, \psval # lower
li.s $f4, \upperval
li.s $f6, ... |
tactcomplabs/xbgas-binutils-gdb | 15,703 | sim/testsuite/mips/mdmx-ob.s | # MDMX .OB op tests.
# mach: mips64 sb1
# as: -mabi=eabi
# as(mips64): -mabi=eabi -mdmx
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-mdmx.inc"
setup
.set noreorder
.ent DIAG
DIAG:
enable_mdmx
###
### Non-accumulator, non-CC-using .ob format ops.
###
### K... |
tactcomplabs/xbgas-binutils-gdb | 4,321 | sim/testsuite/d10v/t-mod-ld-pre.s | # mach: all
# output:
# sim: --environment operating
.include "t-macros.i"
start
mvfc r0, PSW || ldi.s r14, #0
ldi.l r2, 0x100 ; MOD_E
ldi.l r3, 0x108 ; MOD_S
test_mod_dec_ld:
mvtc r2, MOD_E || bseti r0, #7... |
tactcomplabs/xbgas-binutils-gdb | 1,118 | sim/testsuite/d10v/t-mac.s | # mach: all
# output:
# sim: --environment operating
.include "t-macros.i"
start
;; clear FX
loadpsw2 0x8005
loadacc2 a1 0x7f 0xffff 0xffff
load r8 0xffff
load r9 0x8001
test_macu1:
MACU a1, r9, r8
checkacc2 1 a1 0x80 0x8000 0x7FFE
;; set FX
loadpsw2 0x8085
loadacc2 a1 0x7f 0xffff 0xffff
load r8 0xffff
... |
tactcomplabs/xbgas-binutils-gdb | 1,820 | sim/testsuite/d10v/t-mvtc.s | # mach: all
# output:
# sim: --environment operating
# as: -W
.include "t-macros.i"
start
;;; Try out each bit in the PSW
loadpsw2 PSW_SM
checkpsw2 1 PSW_SM
loadpsw2 PSW_01
checkpsw2 2 0 ;; PSW_01
loadpsw2 PSW_EA
checkpsw2 3 PSW_EA
loadpsw2 PSW_DB
checkpsw2 4 PSW_DB
loadpsw2 PSW_DM
checkpsw2 5 0 ;; P... |
tactcomplabs/xbgas-binutils-gdb | 10,261 | sim/testsuite/h8300/biand.s | # Hitachi H8 testcase 'biand', 'bior', 'bixor', 'bild', 'bist', 'bistz'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.i... |
tactcomplabs/xbgas-binutils-gdb | 38,858 | sim/testsuite/h8300/rotr.s | # Hitachi H8 testcase 'rotr'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte ... |
tactcomplabs/xbgas-binutils-gdb | 2,209 | sim/testsuite/h8300/movmd.s | # Hitachi H8 testcase 'movmd'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src:
.byte 1, 2, 3, 4, 5,... |
tactcomplabs/xbgas-binutils-gdb | 1,997 | sim/testsuite/h8300/subw.s | # Hitachi H8 testcase 'sub.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit i... |
tactcomplabs/xbgas-binutils-gdb | 41,951 | sim/testsuite/h8300/movw.s | # Hitachi H8 testcase 'mov.w'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 2
word_dst_dec:
.word 0
word_sr... |
tactcomplabs/xbgas-binutils-gdb | 18,401 | sim/testsuite/h8300/addb.s | # Hitachi H8 testcase 'add.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.b #xx:8,... |
tactcomplabs/xbgas-binutils-gdb | 8,171 | sim/testsuite/h8300/shll.s | # Hitachi H8 testcase 'shll'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte ... |
tactcomplabs/xbgas-binutils-gdb | 1,551 | sim/testsuite/h8300/tas.s | # Hitachi H8 testcase 'tas'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_dst: .byte 0
star... |
tactcomplabs/xbgas-binutils-gdb | 20,865 | sim/testsuite/h8300/not.s | # Hitachi H8 testcase 'not.b, not.w, not.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:... |
tactcomplabs/xbgas-binutils-gdb | 11,255 | sim/testsuite/h8300/extw.s | # Hitachi H8 testcase 'exts.w, extu.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data... |
tactcomplabs/xbgas-binutils-gdb | 23,825 | sim/testsuite/h8300/cmpb.s | # Hitachi H8 testcase 'cmp.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# cmp.b #xx:... |
tactcomplabs/xbgas-binutils-gdb | 7,295 | sim/testsuite/h8300/mul.s | # Hitachi H8 testcase 'muls', 'muls/u', mulu', 'mulu/u', 'mulxs', 'mulxu'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.... |
tactcomplabs/xbgas-binutils-gdb | 2,015 | sim/testsuite/h8300/brabc.s | # Hitachi H8 testcase 'bra/bc'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src: .byte 0xa5
start
... |
tactcomplabs/xbgas-binutils-gdb | 51,202 | sim/testsuite/h8300/movb.s | # Hitachi H8 testcase 'mov.b'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 4
byte_dst_dec:
.byte 0
byte_sr... |
tactcomplabs/xbgas-binutils-gdb | 20,967 | sim/testsuite/h8300/neg.s | # Hitachi H8 testcase 'neg.b, neg.w, neg.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:... |
tactcomplabs/xbgas-binutils-gdb | 4,679 | sim/testsuite/h8300/bfld.s | # Hitachi H8 testcase 'bfld', 'bfst'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src: .byte 0xa5
byt... |
tactcomplabs/xbgas-binutils-gdb | 1,514 | sim/testsuite/h8300/xorw.s | # Hitachi H8 testcase 'xor.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ... |
tactcomplabs/xbgas-binutils-gdb | 48,429 | sim/testsuite/h8300/movl.s | # Hitachi H8 testcase 'mov.l'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 4
long_dst_dec:
.long 0
long_sr... |
tactcomplabs/xbgas-binutils-gdb | 1,503 | sim/testsuite/h8300/orw.s | # Hitachi H8 testcase 'or.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ... |
tactcomplabs/xbgas-binutils-gdb | 2,570 | sim/testsuite/h8300/cmpw.s | # Hitachi H8 testcase 'cmp.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit ... |
tactcomplabs/xbgas-binutils-gdb | 22,700 | sim/testsuite/h8300/subx.s | # Hitachi H8 testcase 'subx'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# subx.b #xx:8... |
tactcomplabs/xbgas-binutils-gdb | 1,441 | sim/testsuite/h8300/subs.s | # Hitachi H8 testcase 'subs'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
... |
tactcomplabs/xbgas-binutils-gdb | 6,902 | sim/testsuite/h8300/subb.s | # Hitachi H8 testcase 'sub.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# sub.b #xx... |
tactcomplabs/xbgas-binutils-gdb | 42,164 | sim/testsuite/h8300/shar.s | # Hitachi H8 testcase 'shar'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte ... |
tactcomplabs/xbgas-binutils-gdb | 2,599 | sim/testsuite/h8300/dec.s | # Hitachi H8 testcase 'dec.b, dec.w, dec.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
dec_b:
set_grs_... |
tactcomplabs/xbgas-binutils-gdb | 42,455 | sim/testsuite/h8300/rotxr.s | # Hitachi H8 testcase 'rotxr'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte... |
tactcomplabs/xbgas-binutils-gdb | 2,168 | sim/testsuite/h8300/addw.s | # Hitachi H8 testcase 'add.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.w xx:3, ... |
tactcomplabs/xbgas-binutils-gdb | 8,117 | sim/testsuite/h8300/stack.s | # Hitachi H8 testcase 'ldc'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 4
stack:
.if (sim_... |
tactcomplabs/xbgas-binutils-gdb | 87,156 | sim/testsuite/h8300/shlr.s | # Hitachi H8 testcase 'shlr'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte ... |
tactcomplabs/xbgas-binutils-gdb | 12,009 | sim/testsuite/h8300/andb.s | # Hitachi H8 testcase 'and.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# and.b #xx... |
tactcomplabs/xbgas-binutils-gdb | 5,946 | sim/testsuite/h8300/div.s | # Hitachi H8 testcase 'divs', 'divu', 'divxs', 'divxu'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (... |
tactcomplabs/xbgas-binutils-gdb | 41,115 | sim/testsuite/h8300/addl.s | # Hitachi H8 testcase 'add.l'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.l xx:3, erd
# add.l xx:... |
tactcomplabs/xbgas-binutils-gdb | 1,820 | sim/testsuite/h8300/movsd.s | # Hitachi H8 testcase 'movsd'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
src: .byte 'h', 'e', 'l', 'l', '... |
tactcomplabs/xbgas-binutils-gdb | 3,566 | sim/testsuite/h8300/shal.s | # Hitachi H8 testcase 'shal'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte ... |
tactcomplabs/xbgas-binutils-gdb | 11,981 | sim/testsuite/h8300/orb.s | # Hitachi H8 testcase 'or.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# or.b #xx:8... |
tactcomplabs/xbgas-binutils-gdb | 4,684 | sim/testsuite/h8300/mac.s | # Hitachi H8 testcase 'mac'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
src1: .word 0
src2: .word ... |
tactcomplabs/xbgas-binutils-gdb | 1,441 | sim/testsuite/h8300/adds.s | # Hitachi H8 testcase 'adds'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
... |
tactcomplabs/xbgas-binutils-gdb | 25,098 | sim/testsuite/h8300/mova.s | # Hitachi H8 testcase 'mova'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
foo: .long 0x01010101
.long 0x1... |
tactcomplabs/xbgas-binutils-gdb | 8,647 | sim/testsuite/h8300/xorb.s | # Hitachi H8 testcase 'xor.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# xor.b #xx... |
tactcomplabs/xbgas-binutils-gdb | 3,531 | sim/testsuite/h8300/rotxl.s | # Hitachi H8 testcase 'rotxl'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte... |
tactcomplabs/xbgas-binutils-gdb | 3,129 | sim/testsuite/h8300/bra.s | # Hitachi H8 testcase 'bra'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx)
.data
.al... |
tactcomplabs/xbgas-binutils-gdb | 1,994 | sim/testsuite/h8300/cmpl.s | # Hitachi H8 testcase 'cmp.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu ==... |
tactcomplabs/xbgas-binutils-gdb | 11,552 | sim/testsuite/h8300/band.s | # Hitachi H8 testcase 'band', 'bor', 'bxor', 'bld', 'bst', 'bstz'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
... |
tactcomplabs/xbgas-binutils-gdb | 1,726 | sim/testsuite/h8300/andl.s | # Hitachi H8 testcase 'and.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu =... |
tactcomplabs/xbgas-binutils-gdb | 1,727 | sim/testsuite/h8300/xorl.s | # Hitachi H8 testcase 'xor.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu =... |
tactcomplabs/xbgas-binutils-gdb | 1,514 | sim/testsuite/h8300/andw.s | # Hitachi H8 testcase 'and.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ... |
tactcomplabs/xbgas-binutils-gdb | 14,357 | sim/testsuite/h8300/bset.s | # Hitachi H8 testcase 'bset', 'bclr'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
#
# ... |
tactcomplabs/xbgas-binutils-gdb | 23,163 | sim/testsuite/h8300/extl.s | # Hitachi H8 testcase 'exts.l, extu.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data... |
tactcomplabs/xbgas-binutils-gdb | 2,231 | sim/testsuite/h8300/jmp.s | # Hitachi H8 testcase 'jmp'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
vector_area:
.fill 0x400, 1, 0
... |
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