repo_name stringclasses 10
values | file_path stringlengths 29 222 | content stringlengths 24 926k | extention stringclasses 5
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|---|---|---|---|
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/multi_kernel.hpp | //
// This file contains all of the FPGA device code for the multi-kernel design
//
#ifndef __MULTI_KERNEL_HPP__
#define __MULTI_KERNEL_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
// Forward declare the kernel names to reduce name mangling
class K0;
class K1;
c... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/single_kernel.hpp | //
// This file contains all of the FPGA device code for the single-kernel design
//
#ifndef __SINGLE_KERNEL_HPP__
#define __SINGLE_KERNEL_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
// Forward declare the kernel names to reduce name mangling
class K;
// submi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp | #include <assert.h>
#include <algorithm>
#include <chrono>
#include <iomanip>
#include <numeric>
#include <random>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include <type_traits>
#include "exception_handler.hpp"
// Forward declare the kernel names in the global scope.
// This FPGA best ... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <algorithm>
#include <chrono>
#include "onc... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/optimize_inner_loop.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <algorithm>
#include <array>
#include <iomanip>
#include <iostream>
#include <numeric>
#include <random>
#include <... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <cmath>
#include <iomanip>
#include <random>... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/src/pipe_array.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip>
#include <iostream>
#include <stri... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/HostStreamer.hpp | #ifndef __HOSTSTREAMER_HPP__
#define __HOSTSTREAMER_HPP__
#include <assert.h>
#include <array>
#include <atomic>
#include <condition_variable>
#include <deque>
#include <exception>
#include <map>
#include <mutex>
#include <functional>
#include <queue>
#include <stdexcept>
#include <thread>
#include <tuple>
#include <... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/streaming_without_api.hpp | #ifndef __STREAMING_WITHOUT_API_HPP__
#define __STREAMING_WITHOUT_API_HPP__
#include <algorithm>
#include <numeric>
#include <atomic>
#include <queue>
#include <thread>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "common.hpp"
using namespace sycl;
using namespac... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/streaming_with_api.hpp | #ifndef __STREAMING_WITH_API_HPP__
#define __STREAMING_WITH_API_HPP__
#include <algorithm>
#include <numeric>
#include <queue>
#include <thread>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "common.hpp"
#include "HostStreamer.hpp"
using namespace sycl;
using name... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp | #include <assert.h>
#include <algorithm>
#include <array>
#include <chrono>
#include <iomanip>
#include <numeric>
#include <functional>
#include <string>
#include <thread>
#include <type_traits>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
#include "streamin... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/common.hpp | #ifndef __COMMON_HPP__
#define __COMMON_HPP__
#include <algorithm>
#include <chrono>
#include <numeric>
#include <vector>
#include <thread>
// A multithreaded version of memcpy.
// On modern processors with multiple cores and threads, a single-threaded
// memcpy cannot saturate the memory bandwidth (not even close). ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/buffer_kernel.hpp | #ifndef __BUFFER_KERNEL_HPP__
#define __BUFFER_KERNEL_HPP__
#pragma once
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
using namespace std::chrono;
// Forward declare the kernel name in the global scope.
// This FPGA best practice reduces name manglin... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/zero_copy_data_transfer.cpp | #include <assert.h>
#include <algorithm>
#include <chrono>
#include <iomanip>
#include <numeric>
#include <random>
#include <type_traits>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
#include "buffer_kernel.hpp"
#include "zero_copy_kernel.hpp"
using namespa... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/zero_copy_kernel.hpp | #ifndef __ZERO_COPY_KERNEL_HPP__
#define __ZERO_COPY_KERNEL_HPP__
#pragma once
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
using namespace std::chrono;
//
// The structure of the kernels in this design is shown in the diagram below.
// The Producer ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/loop_carried_dependency.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <string>
#include "exception_handler.hpp"
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/IntersectionKernel.hpp | #ifndef __INTERSECTIONKERNEL_HPP__
#define __INTERSECTIONKERNEL_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// the kernel class names
// templated on the version of the kernel
// Best practice: forward declare the kernel names in the global scope
// to reduce compiler name mangling in... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp | #include <algorithm>
#include <numeric>
#include <string>
#include <type_traits>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "IntersectionKernel.hpp"
#include "exception_handler.hpp"
using namespace sycl;
//
// print the usage
//
void Usage() {
std::cout
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/src/triangular_loop.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <chrono>
#include "exception_handler.hpp"
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/src/autorun.hpp | #ifndef __AUTORUN_HPP__
#define __AUTORUN_HPP__
#include <sycl/sycl.hpp>
#include <type_traits>
/*
This header defines the Autorun kernel utility. This utility is used to
launch kernels that are submitted before main begins. It is typically used
to launch kernels that run forever.
Two classes are defined in this hea... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/src/autorun.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
#include "autorun.hpp"
#include <algorithm>
#include <iostream>
#include <vector>
using namespace sycl;
// choose the device selector based on emulation or actual hardware
// we make this a global variable so it... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/HostSideChannel.hpp | #ifndef __HOSTSIDECHANNEL_HPP__
#define __HOSTSIDECHANNEL_HPP__
#include <iostream>
#include <type_traits>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "FakeIOPipes.hpp"
using namespace sycl;
//
// This class provides a convenient, but low-bandwidth and relatively high
// latency... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/SideChannelTest.hpp | #ifndef __SIDECHANNELTEST_HPP__
#define __SIDECHANNELTEST_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "FakeIOPipes.hpp"
#include "HostSideChannel.hpp"
using namespace sycl;
using namespace std::chrono_literals;
// declare the kernel and pipe ID stucts globally to reduce nam... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/LoopbackTest.hpp | #ifndef __LOOPBACKTEST_HPP__
#define __LOOPBACKTEST_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "FakeIOPipes.hpp"
// If the 'USE_REAL_IO_PIPES' macro is defined, this test will use real IO pipes.
// To use this, ensure you have a BSP that supports IO pipes.
// NOTE: define t... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/FakeIOPipes.hpp | #ifndef __FAKEIOPIPES_HPP__
#define __FAKEIOPIPES_HPP__
#include <iostream>
#include <type_traits>
#include <utility>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// the "detail" namespace is commonly used in C++ as an internal namespace
// (to a file) that is not meant to be visible to the... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp | #include <algorithm>
#include <chrono>
#include <iostream>
#include <numeric>
#include <chrono>
#include <thread>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
// The type that will stream through the IO pipe. When using real IO pipes,
// make sure the width ... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <cmath>
#include <iomanip>
#include <random>... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp | #include <iostream>
// oneAPI headers
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// Forward declare the kernel name in the global scope. This is an FPGA best
// practice that reduces name mangling in the optimization reports.
class VectorAddID;
struct Vec... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part1_cpp/src/vector_add.cpp | #include <iostream>
void VectorAdd(const int *a_in, const int *b_in, int *c_out, int len) {
for (int idx = 0; idx < len; idx++) {
int a_val = a_in[idx];
int b_val = b_in[idx];
int sum = a_val + b_val;
c_out[idx] = sum;
}
}
constexpr int kVectSize = 256;
int main() {
// declare arrays and fill t... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part3_dpcpp_lambda_usm/src/vector_add.cpp | #include <iostream>
#include <vector>
// oneAPI headers
#include <CL/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
// Forward declare the kernel name in the global scope. This is an FPGA best
// practice that reduces name mangling in the optimization reports.
class VectorAddID;
void ... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part4_dpcpp_lambda_buffers/src/vector_add.cpp | #include <iostream>
// oneAPI headers
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
// Forward declare the kernel name in the global scope. This is an FPGA best
// practice that reduces name mangling in the optimization reports.
class VectorAddID;
void VectorAdd(const int *vec_a_in, const in... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part2_dpcpp_functor_usm/src/vector_add.cpp | #include <iostream>
// oneAPI headers
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
// Forward declare the kernel name in the global scope. This is an FPGA best
// practice that reduces name mangling in the optimization reports.
class VectorAddID;
struct VectorAdd {
int *const vec_a_in;
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/kernel.hpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
using namespace sycl;
void RunKernel(queue& q, buffer<float,1>& buf_a, buffer<float,1>& buf_b,
... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/kernel.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "kernel.hpp"
// This file contains 'almost' exclusively device cod... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <iostream>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "ex... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/src/loop_fusion.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <iomanip>
#include <iostream>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exc... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/src/ac_int.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <bitset>
#include "exception_handler.hpp"
using namespace sycl;
// Forward declare the kernel names in the global scope.
// This FPGA best practice reduces name mangling in the optimization ... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/src/private_copies.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <math.h>
#include <array>
#include <iomanip>
#include <iostream>
#include <sycl/ext/intel/fpga_extensions.hpp>
#in... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/src/dsp_control.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
using namespace sy... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/lsu_control/src/lsu_control.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <numeric>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
using namespace sy... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/stall_enable.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip>
#include <iostream>
#include "exception_handler.hpp"
using namespace sycl;
// Forward declare the kernel name in the global scope.
// This FPGA best practice reduces name mangling in the optimization reports.
class KernelComput... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip>
#include <iostream>
#include <stri... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/printf.cpp | #include <sycl/sycl.hpp>
#include <iostream>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
// According to the OpenCL C spec, the format string must be in the constant
// address space. To simplify code when invoking printf, the following macros
// are defined.
#ifdef __SYCL_DEVICE_ON... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <array>
#include <iomanip>
#include <iostrea... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_reinvocation_delay/src/max_reinvocation_delay.cpp | #include <iostream>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
constexpr int kFactors = 5;
// Forward declare the kernel and pipe names
// (This prevents unwanted name mangling in the optimization report.)
class ArithmeticSequence;
class ResultsPipe;
// R... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/src/mem_channel.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <chrono>
#include <numeric>
#include "exce... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/hostpipes.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/experimental/pipes.hpp>
#include <algorithm>
#include <iomanip>
#include <iostream>
#include <numeric>
#include <vector>
// dpc_common.hpp can be found in the dev-utilities include folder.
// e.g., $ONEAPI_ROOT/dev-utiliti... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/device_global/src/device_global.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <math.h>
#include <iostream>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exc... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/src/latency_control.cpp | #include <sycl/sycl.hpp>
#include <numeric>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
using BurstCoalescedLSU = sycl::ext::intel::experimental::lsu<
sycl::ext::intel::experimental::burst_coalesce<true>,
sycl::ext::intel::experimental::statically_coalesce<false>>;
int Oper... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/src/kernel_args_restrict.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <algorithm>
#include <numeric>
#include <vector>
#include "exception_handler.hpp"
#include <sycl/sycl.hpp>
#inclu... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/src/loop_ivdep.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip>
#include <iostream>
#include "exc... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/src/fpga_reg.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip>
#include <iostream>
#include <stri... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/optimization_targets/src/optimization_targets.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include "exception_handler.hpp"
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include <vector>
c... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/src/loop_coalesce.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip>
#include <iostream>
#include "exc... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/src/read_only_cache.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <chrono>
#include "exception_handler.hpp"
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/src/pipes.cpp | #include <iomanip>
#include <iostream>
#include <numeric>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
using namespace sycl;
using ProducerToConsumerPipe = ext::intel::pipe< // Defined in the SYCL headers.
class ProducerConsumerPipeId,... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/src/scheduler_target_fmax.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
using namespace sy... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <vector>
#include "exception_handler.hpp"
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/src/max_interleaving.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <array>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip>
#include <iostrea... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/streaming_data_interfaces/src/streaming_data_interfaces.cpp | #include <iostream>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/prototype/pipes_ext.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// limit pixel values to this value, or less
constexpr int kThreshold = 200;
// Forward declare the kernel and pipe names
// (this prevents unw... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/invocation_interfaces/src/reg_map_lambda.cpp | // oneAPI headers
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
using MyUInt5 = ac_int<5, false>;
// Forward declare the kernel names in the global scope.
// This FPGA best practice reduces name mangling in the op... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/invocation_interfaces/src/stream_functor.cpp | // oneAPI headers
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// Forward declare the kernel names in the global scope.
// This FPGA best practice reduces name mangling in the optimization reports.
class FunctorStream;
struct Point {
int x;
char y;
};
/... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/invocation_interfaces/src/stream_rm_stall.cpp | // oneAPI headers
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// Forward declare the kernel names in the global scope.
// This FPGA best practice reduces name mangling in the optimization reports.
class StreamRmS... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/invocation_interfaces/src/reg_map_functor.cpp | // oneAPI headers
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
using MyUInt5 = ac_int<5, false>;
// Forward declare the kernel names in the global scope.
// This FPGA best practice reduces name mangling in the op... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/invocation_interfaces/src/stream_lambda.cpp | // oneAPI headers
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// Forward declare the kernel names in the global scope.
// This FPGA best practice reduces name mangling in the optimization reports.
class LambdaStream;
////////////////////////////////////////... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/invocation_interfaces/src/stream_pipelined.cpp | // oneAPI headers
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// Forward declare the kernel names in the global scope.
// This FPGA best practice reduces name mangling in the optimization reports.
class StreamPip... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/mmhost/part3_hosts/src/mmhost.cpp | #include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
constexpr int kBL1 = 1;
constexpr int kBL2 = 2;
constexpr int kBL3 = 3;
constexpr int kAlignment = 4;
struct MultiMMIP {
// Each annotated pointer is configured with a unique `buffer_location`,
// resulting in... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/mmhost/part2_single_host/src/mmhost.cpp | #include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
struct SingleMMIP {
// This kernel has 3 annotated pointers, but since they have no properties
// specified, this kernel will result in the same IP component as Example 1.
sycl::ext::oneapi::experimental::ann... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/mmhost/part1_pointers/src/mmhost.cpp | #include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
struct PointerIP {
// Pointer kernel arguments will be passed through the component's CSR. They
// will refer to data accessible through a shared Avalon memory-mapped host
// interface.
int *x;
int *y;
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/mmhost/part4_ddr_hosts/src/mmhost.cpp | #include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
constexpr int kBL1 = 1;
constexpr int kBL2 = 2;
constexpr int kAlignment = 32;
struct DDRIP {
using ParamsBl1 = decltype(sycl::ext::oneapi::experimental::properties{
sycl::ext::intel::experimental::buffer_... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/component_interfaces_comparison/streaming-invocation/src/vector_add.cpp | #include <iostream>
// oneAPI headers
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
// Forward declare the kernel name in the global scope. This is an FPGA best
// practice that reduces name mangling in the optimization reports.
class IDSimpleVAdd;
struct Sim... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/component_interfaces_comparison/csr-pipes/src/vector_add.cpp | #include <iostream>
// oneAPI headers
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
// Forward declare the kernel name in the global scope. This is an FPGA best
// practice that reduces name mangling in the optimization reports.
class SimpleVAddPipes;
// Forw... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/component_interfaces_comparison/naive/src/vector_add.cpp | #include <iostream>
// oneAPI headers
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
// Forward declare the kernel name in the global scope. This is an FPGA best
// practice that reduces name mangling in the optimization reports.
class IDSimpleVAdd;
struct Simp... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/component_interfaces_comparison/mm-host/src/vector_add.cpp | #include <iostream>
// oneAPI headers
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
// Buffer locations for MM Host interfaces
constexpr int kBL1 = 1;
constexpr int kBL2 = 2;
constexpr int kBL3 = 3;
// Forward declare the kernel name in the global scope. This... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/component_interfaces_comparison/pipes/src/vector_add.cpp | #include <iostream>
// oneAPI headers
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
constexpr int kVectorSize = 256;
// Forward declare the kernel name in the global scope. This is an FPGA best
// practice that reduces name mangling in the optimization reports... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/ac_fixed.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_fixed.hpp>
#include <sycl/ext/intel/ac_types/ac_fixed_math.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip> // for std::setprecision
#include "exception_handler.hpp"
using namespace sycl;
// Type aliases for ac_fixed types
using fix... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/src/double_buffering.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <cmath>
#include <iomanip>
#include <random... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/platform_designer/add-oneapi/src/add.cpp | // Copyright (c) 2023 Intel Corporation
// SPDX-License-Identifier: MIT
#include <stdlib.h>
#include <iostream>
// oneAPI headers
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// use pipes to write into registers in the CSR address space
class OutputPipeI... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/src/use_library.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/ext/intel/ac_types/ac_int.hpp>
// oneAPI headers
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/src/lib_rtl.hpp | // =============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
using MyInt27 = ac_int<27, false>;
using MyInt54 = ac... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/src/lib_rtl_model.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include "lib_rtl.hpp"
// This emulation model is only used during emulation, so it should functionally
// match the RTL in... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/src/dynamic_profiler.cpp | /*
Please refer to the README file for information on how and why the
Intel(r) Dynamic Profiler for DPC++ should be used. This code sample
does not explain the tool, rather it is an artificial example that
demonstates the sort of code changes the profiler data can guide.
The main content of this sample is in ... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/streaming_eigen.hpp | #ifndef __STREAMING_QRD_HPP__
#define __STREAMING_QRD_HPP__
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
namespace fpga_linalg {
/*
Computes 1e-Is as a constexpr
*/
template <typename T, std::size_t... Is>
constexpr T negPow10(std::i... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/onchip_memory_with_cache.hpp | #ifndef __ONCHIP_MEMORY_WITH_CACHE_HPP__
#define __ONCHIP_MEMORY_WITH_CACHE_HPP__
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include "constexpr_math.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
namespace fpga_tools {
template <typename ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/metaprogramming_utils.hpp | #ifndef __METAPROGRAMMING_UTILS_HPP__
#define __METAPROGRAMMING_UTILS_HPP__
#include <type_traits>
namespace fpga_tools {
//
// The code below creates the constexprs 'make_integer_range'
// and 'make_index_range' these are akin to 'std::make_integer_sequence'
// and 'std::make_index_sequence', respectively.
// Howev... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/pipe_utils.hpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#ifndef __PIPE_UTILS_HPP__
#define __PIPE_UTILS_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/streaming_qrd.hpp | #ifndef __STREAMING_QRD_HPP__
#define __STREAMING_QRD_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
namespace fpga_linalg {
/*
QRD (QR decomposition) - Computes Q and R matrices such that A=QR where:
- A is the input matrix
- Q is a unitary/orthogonal matrix
- R is an ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/rom_base.hpp | #ifndef __ROM_BASE_HPP__
#define __ROM_BASE_HPP__
#include <type_traits>
//
// A base class for creating a constexpr ROM.
//
// TEMPLATE PARAMETERS
// T: the datatype stored in the ROM
// _depth: the depth of the ROM
//
// EXAMPLE USAGE
// To use the ROM, you must create a class that inherits from this cl... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/streaming_qri.hpp | #ifndef __STREAMING_QRI_HPP__
#define __STREAMING_QRI_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
namespace fpga_linalg {
/*
QRI (QR inversion) - Given two matrices Q and R from the QR decomposition
of a matrix A such that A=QR, this function computes the inverse of A.
... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/streaming_cholesky_inversion.hpp | #ifndef __STREAMING_CHOLESKY_INVERSION_HPP__
#define __STREAMING_CHOLESKY_INVERSION_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
namespace fpga_linalg {
/*
Cholesky decomposition - Computes L such that A=LL* where:
- A is the input matrix (hermitian, positive definite)
... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/streaming_matmul.hpp | #ifndef __STREAMING_MATMUL_HPP__
#define __STREAMING_MATMUL_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
namespace fpga_linalg {
/**
* Matrix multiply kernel.
*
* Repeatedly reads matrix tiles of A and B from input pipes and computes A * B
* using a systolic array of PEs.... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/memory_utils.hpp | #ifndef __MEMORY_UTILS_HPP__
#define __MEMORY_UTILS_HPP__
#include <type_traits>
#include "metaprogramming_utils.hpp"
//
// The utilities in this file are used for converting streaming data to/from
// memory from/to a pipe.
//
namespace fpga_tools {
namespace detail {
//
// Helper to check if a SYCL pipe and poin... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/streaming_cholesky.hpp | #ifndef __STREAMING_CHOLESKY_HPP__
#define __STREAMING_CHOLESKY_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
namespace fpga_linalg {
/*
Cholesky decomposition - Computes L such that A=LL* where:
- A is the input matrix (hermitian, positive definite)
- L is a lower trian... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/unrolled_loop.hpp | #ifndef __UNROLLEDLOOP_HPP__
#define __UNROLLEDLOOP_HPP__
#include <type_traits>
#include <utility>
#include "metaprogramming_utils.hpp"
namespace fpga_tools {
///////////////////////////////////////////////////////////////////////////////
//
// Example usage for UnrolledLoop constexpr:
//
// Base
// UnrolledLoop... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/streaming_covariance_matrix.hpp | #ifndef __STREAMING_COVARIANCE_MATRIX_HPP__
#define __STREAMING_COVARIANCE_MATRIX_HPP__
namespace fpga_linalg {
// This functor computes the columns x columns covariance matrix of a rows x
// columns input matrix A
// It uses the following formula:
// COV[i][j] = (T[i][j] - rows*mean[i]*mean[j]) /
// ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/exception_handler.hpp | #ifndef __EXCEPTIONHANDLER_HPP__
#define __EXCEPTIONHANDLER_HPP__
#include <sycl/sycl.hpp>
#include <exception>
#include <iostream>
namespace fpga_tools {
void exception_handler(sycl::exception_list exceptions) {
for (std::exception_ptr const &e : exceptions) {
try {
std::rethrow_exception(e);
} catch... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/tuple.hpp | #ifndef __TUPLE_HPP__
#define __TUPLE_HPP__
#include <type_traits>
namespace fpga_tools {
//
// Generic tuple
//
// USAGE EXAMPLE:
// Tuple<char,short,int,long> my_tuple;
// char a = my_tuple.get<0>();
// short b = my_tuple.get<1>();
// int c = my_tuple.get<2>();
// long d = my_tuple.get<3>();
//
temp... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/include/constexpr_math.hpp | #ifndef __CONSTEXPR_MATH__
#define __CONSTEXPR_MATH__
//
// This file contains various helper C++ metaprogramming math functions that
// are useful across various designs.
//
#include <limits>
namespace fpga_tools {
// returns the absolute value of 'x'
template <typename T>
constexpr T Abs(T x) { return (x < 0) ? -... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/usm_speed.hpp | #include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
// NOTE: sycl::ulong8 was picked for this test because it is 64 bytes in size
// and that is the width of the interconnect to global memory.
// Arbitrary value used for testing/initialization
#define TEST_VAL 5
// Forward declare the kernel names... | hpp |
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