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oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/board_test.hpp | #include <sycl/sycl.hpp>
#include <vector>
#include "host_speed.hpp"
#if defined(SUPPORTS_USM)
#include "usm_speed.hpp"
#endif
// Pre-declare kernel name to prevent name mangling
// This is an FPGA best practice that makes it easier to identify the kernel in
// the optimization reports.
class NopNDRange;
class NopSi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/host_speed.hpp | // Header file to accompany hostspeed tests
#include <sycl/sycl.hpp>
#include <iomanip>
#include <iostream>
#include "helper.hpp"
// struct used in ReadSpeed & WriteSpeed functions to store transfer speeds
struct Speed {
float fastest;
float slowest;
float average;
float total;
};
///////////////////////////... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/board_test.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iostream>
#include "exception_handler.hpp"
// Test related header files
#include "board_test.hpp"
int main(int argc, char* argv[]) {
// Always print small help at the beginning of board test
PrintHelp(0);
// Default is to run all... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/helper.hpp | // Header file to accompany board_test
#include <sycl/sycl.hpp>
constexpr size_t kKB = 1024;
constexpr size_t kMB = 1024 * 1024;
constexpr size_t kGB = 1024 * 1024 * 1024;
constexpr size_t kRandomSeed = 1009;
#if defined(_WIN32) || defined(_WIN64)
std::string kBinaryName = "board_test.fpga.exe";
#elif __linux__
s... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky_demo.cpp | #include <math.h>
#include <sycl/sycl.hpp>
#include <list>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "cholesky.hpp"
#include "exception_handler.hpp"
// Use "#define DEBUG" to print debugging information such as matrices content
/*
COMPLEX, MATRIX_DIME... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matric... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp | #ifndef __CHOLESKY_HPP__
#define __CHOLESKY_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <type_traits>
#include <vector>
#include "memory_transfers.hpp"
// Included from DirectProg... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/fft2d/src/fft2d_demo.cpp | #include <math.h>
#define _USE_MATH_DEFINES
#include <cmath>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
#include "fft2d.hpp"
// Forward declarations
void TestFFT(bool mangle, bool inverse);
template <int n... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/fft2d/src/twiddle_factors.hpp | #define COS8 { \
{ \
{1.0f, 0.9999952912f, 0.9999811649f, 0.9999576211f, 0.9999247193f, 0.9998823404f, 0.9998306036f, 0.9997693896f, 0.9996988177f, 0.9996188283f, 0.9995294213f, 0.9994305968f, 0.9993223548f, 0.9992047548f, 0.9990777373f, 0.9989413023f, 0.9987954497f, 0.9986402392f, 0.9984755516f, 0.998301... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/fft2d/src/fft2d.hpp | #ifndef __FFT2D_HPP__
#define __FFT2D_HPP__
#define _USE_MATH_DEFINES
#include <cmath>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
// Large twiddle factors tables
#include "twiddle_factors.hpp"
// Complex single-precision floating-point fe... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/src/simple_dma.cpp | // Copyright (c) 2022 Intel Corporation
// SPDX-License-Identifier: MIT
#include <stdlib.h>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// define buffer locations so the IP can have two unique Avalon memory-mapped
// host interfaces
static constexpr int k... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/software/simple_dma_test/src/simple_dma_test.c | // Copyright (c) 2022 Intel Corporation
// SPDX-License-Identifier: MIT
//
// This design leverages a simple DMA oneAPI kernel that has had its RTL
// generated and integrated into the Nios V test system that will be used to
// control the accelerator. The DMA kernel has been configured to read from
// memory in memo... | c |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp | #ifndef __QRD_HPP__
#define __QRD_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <chrono>
#include <cstring>
#include <type_traits>
#include <vector>
#include "memory_transfers.hpp"
... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd_demo.cpp | #include <math.h>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <list>
#include "exception_handler.hpp"
#include "qrd.hpp"
#ifdef FPGA_SIMULATOR
#define ROWS_COMPONENT_V 8
#define COLS_COMPONENT_V 8
#else
#define ROWS_COMPONENT_V R... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
#include "tuple.hpp"
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matrices to the "MatrixPipe" pipe num_elem_per_bank by
num_el... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/main.cpp | #include <algorithm>
#include <array>
#include <chrono>
#include <limits>
#include <numeric>
#include <type_traits>
#include <utility>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
#include "merge_sort.hpp"
// Included from DirectProgrammin... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/consume.hpp | #ifndef __CONSUME_HPP__
#define __CONSUME_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
//
// Streams in 'k_width' elements of data per cycle from a SYCL pipe and either
// writes it to memory (to_pipe==false) or writes it to a pipe (to_pipe==true)
//
template <ty... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/sorting_networks.hpp | #ifndef __SORTINGNETWORKS_HPP__
#define __SORTINGNETWORKS_HPP__
#include <algorithm>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
using namespace sycl;
//
// Creates a merge sort network.
// Takes in tw... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/produce.hpp | #ifndef __PRODUCE_HPP__
#define __PRODUCE_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
//
// Produces 'k_width' elements of data per cycle into the merge unit from
// device memory
//
template<typename Id, typename ValueT, typename IndexT, typename OutPipe,
... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/merge.hpp | #ifndef __MERGE_HPP__
#define __MERGE_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "sorting_networks.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
using namespace sycl;
//
// Streams in two sorted list of size 'in_count`, 'k_wid... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/merge_sort.hpp | #ifndef __MERGESORT_HPP__
#define __MERGESORT_HPP__
#include <array>
#include <iostream>
#include <limits>
#include <type_traits>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "consume.hpp"
#include "merge.hpp"
#include "produce.hpp"
#include "sorting_networks.hpp"... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzip.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <chrono>
#include <fstream>
#include <string>
#include "CompareGzip.hpp"
#include "WriteGzip.hpp"
#include "crc32.hpp"
#include "gzipkernel.hpp"
#include "kernels.hpp"
#include "exception_handler.hpp"
using namespace sycl;
// The minim... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/crc32.cpp | #include "crc32.hpp"
// This table is CRC32s for all single byte values created by using the
// makecrc.c utility from gzip for compatibility with gzip. makecrc.c can be
// found in the gzip source code project found at
// https://git.savannah.gnu.org/git/gzip.git. The polynomial 0xedb88320 is used
// for gzip, and th... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/WriteGzip.cpp | #define _CRT_SECURE_NO_WARNINGS
#include "WriteGzip.hpp"
#include <fcntl.h>
#include <memory.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <sycl/sycl.hpp>
#include <chrono>
#include <string>
constexpr int kDeflated = 8;
#define GZIP_MAGIC "\037\21... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/kernels.hpp | #ifndef __KERNELS_H__
#define __KERNELS_H__
#pragma once
#ifndef NUM_ENGINES
#define NUM_ENGINES 1
#endif
// BATCH_SIZE is the number of input files the kernel should be capable of
// compressing per invocation of the GZIP engine. This is a compile time
// constant so that hardware is built to support this number. ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CompareGzip.cpp | #include "CompareGzip.hpp"
#include <sys/stat.h>
// returns 0 on success, otherwise failure
int CompareGzipFiles(
const std::string
&original_file, // original input file to compare gzip uncompressed
const std::string &input_gzfile) // gzip file to check
{
#ifdef _MSC_VER
std::cout
<< "Info: ... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzipkernel.hpp | #ifndef __GZIPKERNEL_H__
#define __GZIPKERNEL_H__
#pragma once
#include <sycl/sycl.hpp>
using namespace sycl;
extern "C" void SubmitGzipTasks(
queue &sycl_device,
size_t block_size, // size of block to compress.
buffer<char, 1> *pibuf, buffer<char, 1> *pobuf,
buffer<struct GzipOutInfo, 1> *gzip_out_... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzipkernel_ll.cpp | /*
** Batching **
This is the "low-latency" variant of the GZIP reference design. It differs
from the "high-bandwidth" variant in that it tries to minimize the latency
from when the input file is available in host memory to when the compressed
result is available in host memory, particulary for small (< 128KB... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzipkernel_ll.hpp | #ifndef __GZIPKERNEL_H__
#define __GZIPKERNEL_H__
#pragma once
#include <sycl/sycl.hpp>
#include "kernels.hpp"
using namespace sycl;
//extern "C"
std::vector<event> SubmitGzipTasks(queue &q, size_t block_size,
struct GzipOutInfo *gzip_out_buf,
ui... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/crc32.hpp | #ifndef __CRC32_H__
#define __CRC32_H__
#pragma once
#include <stdint.h>
#include <stdlib.h>
uint32_t Crc32Host(
const char *pbuf, // pointer to the buffer to crc
size_t sz, // number of bytes
uint32_t previous_crc); // previous CRC, allows combining. First invocation
... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzip_ll.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <chrono>
#include <fstream>
#include <string>
#include "CompareGzip.hpp"
#include "WriteGzip.hpp"
#include "crc32.hpp"
#include "gzipkernel_ll.hpp"
#include "kernels.hpp"
#include "exception_handler.hpp"
using namespace sycl;
// The mi... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/WriteGzip.hpp | #ifndef __WRITEGZIP_H__
#define __WRITEGZIP_H__
#pragma once
#include <iostream>
#include <string>
// returns 0 on success, otherwise failure
int WriteBlockGzip(
std::string &original_filename, // Original file name being compressed
std::string &out_filename, // gzip filename
char *obuf, ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CompareGzip.hpp | #ifndef __COMPAREGZIP_H__
#define __COMPAREGZIP_H__
#pragma once
#include <iostream>
#include <string>
int CompareGzipFiles(
const std::string
&original_file, // original input file to compare gzip uncompressed
const std::string &input_gzfile); // gzip file to check
#endif //__COMPAREGZIP_H__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzipkernel.cpp | #include <sycl/sycl.hpp>
#include "gzipkernel.hpp"
#include "kernels.hpp"
using namespace sycl;
// This reference design uses a template-based unroller. It's also possible
// to specify this in a more concise way using a pragma. See the loop unroll
// tutorial for more information.
template <int Begin, int End>
str... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/matmul/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
/**
* Feeder A Kernel.
*
* Reads all "num_matrices" matrices from FPGA DDR "elems_per_ddr_access"
* elements at a time and stores to on-chip memory. Then writes out mat... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/matmul/src/matmul.hpp | #ifndef __MATMUL_HPP__
#define __MATMUL_HPP__
#include <iostream>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "memory_transfers.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "streaming_matmul.hpp"
#if not defi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/matmul/src/matmul_demo.cpp | #include <iomanip>
#include <iostream>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
#include "matmul.hpp"
// Fills a matrix with random numbers within the range [l_bound, u_bound).
void FillRand(std::vector<float> &m_matrix, int l_bound, int u_bound,
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/MVDR.hpp | #ifndef __MVDR_HPP__
#define __MVDR_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <array>
// utility classes
#include "mvdr_complex.hpp"
#include "pipe_utils.hpp" // Included from DirectProgramming/C++SYCL_FPGA/include/
// MVDR processing kernels
#include "BackwardSubstitution... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/StreamingQRDWrapper.hpp | #ifndef __STREAMING_QRD_WRAPPER_HPP__
#define __STREAMING_QRD_WRAPPER_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "mvdr_complex.hpp"
// utility classes found in DirectProgramming/C++SYCL_FPGA/include
#include "streaming_qrd.hpp"
#include "tuple.hpp"
#include "unrolled_loop.h... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/UDP.hpp | #ifndef __UDP_HPP__
#define __UDP_HPP__
#include <chrono>
#include <cstdlib>
#include <iostream>
#include <thread>
#include <arpa/inet.h>
#include <net/if.h>
#include <netinet/in.h>
#include <sys/ioctl.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <unistd.h>
#include <uuid/uuid.h>
#include <opae/access.... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_complex.hpp | #ifndef __MVDR_COMPLEX_HPP__
#define __MVDR_COMPLEX_HPP__
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
using ComplexBaseType = float;
using ComplexType = ac_complex<ComplexBaseType>;
#endif // ifndef __MVDR_COMPLEX_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/ForwardSubstitution.hpp | #ifndef __FORWARD_SUBSTITUTION_HPP__
#define __FORWARD_SUBSTITUTION_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// utility classes
#include "ParallelCopyArray.hpp"
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "mvdr_complex.hpp"
using namespace syc... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/InputDemux.hpp | #ifndef __INPUT_DEMUX_HPP__
#define __INPUT_DEMUX_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <cmath>
// utility classes
#include "tuple.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/Transpose.hpp | #ifndef __TRANSPOSE_HPP__
#define __TRANSPOSE_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "tuple.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
using namespace sycl;
// the generic transpose cl... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CalcWeights.hpp | #ifndef __CALC_WEIGHTS_HPP__
#define __CALC_WEIGHTS_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "mvdr_complex.hpp"
using namespace sycl;
// SubmitCalcWeightsKernel
// Accept y vector (= Rtranspose * R * Ccomplex_conj, calculated using QRD and
// forward/backward substitutio... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/DiagReciprocal.hpp | #ifndef __DIAG_RECIPROCAL__
#define __DIAG_RECIPROCAL__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "mvdr_complex.hpp"
// SubmitDiagReciprocalKernel
// Accept an upper-triangular square R Matrix from QR Decomposition from
// StreamingQRD. Compute the reciprocals of the square diag... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/BackwardSubstitution.hpp | #ifndef __BACKWARD_SUBSTITUTION_HPP__
#define __BACKWARD_SUBSTITUTION_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// utility classes
#include "ParallelCopyArray.hpp"
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "mvdr_complex.hpp"
using namespace s... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/udp_loopback_test.cpp | #include <algorithm>
#include <chrono>
#include <cstdlib>
#include <iostream>
#include <numeric>
#include <string>
#include <thread>
#include <sys/mman.h>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "Tuple.hpp"
#include "UDP.hpp"
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/FakeIOPipes.hpp | #ifndef __FAKEIOPIPES_HPP__
#define __FAKEIOPIPES_HPP__
#include <iostream>
#include <type_traits>
#include <utility>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// the "detail" namespace is commonly used in C++ as an internal namespace
// (to a file) that is not meant to be visible to the... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/SteeringVectorGenerator.hpp | #ifndef __STEERING_VECTOR_GENERATOR_HPP__
#define __STEERING_VECTOR_GENERATOR_HPP__
#define _USE_MATH_DEFINES
#include <cmath>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "mvdr_complex.hpp"
using namespace sycl;
// SubmitSteeringVectorGeneratorKernel
// Accept the value sin(thet... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/Constants.hpp | #ifndef __CONSTANTS_HPP__
#define __CONSTANTS_HPP__
// Allow design parameters to be defined on the command line
// check is USM host allocations are enabled
#ifdef USM_HOST_ALLOCATIONS
constexpr bool kUseUSMHostAllocation = true;
#else
constexpr bool kUseUSMHostAllocation = false;
#endif
// Large array is 64 sensor... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp | #define _USE_MATH_DEFINES
#include <cmath>
#include <chrono>
#include <cstring>
#include <iomanip>
#include <thread>
#include <vector>
#include <fstream>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "tuple.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "mvdr_complex.hpp"
... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/ParallelCopyArray.hpp | #ifndef __PARALLEL_COPY_ARRAY_HPP__
#define __PARALLEL_COPY_ARRAY_HPP__
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
// ParallelCopyArray
// Defines a struct with a single element data, which is an array of type T.
// Defies the copy and = operators to do an unrolled (parallel) assignment ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/Beamformer.hpp | #ifndef __BEAMFORMER_HPP__
#define __BEAMFORMER_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// utility classes
#include "ParallelCopyArray.hpp"
#include "tuple.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/inclu... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matric... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion.hpp | #ifndef __CHOLESKY_INVERSION_HPP__
#define __CHOLESKY_INVERSION_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <type_traits>
#include <vector>
#include "memory_transfers.hpp"
// Incl... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion_demo.cpp | #include <math.h>
#include <sycl/sycl.hpp>
#include <list>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
// included from ../../../../include
#include "cholesky_inversion.hpp"
// Use "#define DEBUG" to print debugging information such... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/main.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <algorithm>
#include <array>
#include <chrono>
#include <limits>
#include <numeric>
#include <sstream>
#include <string>
#include <type_traits>
#include <utility>
#include <vector>
#include "anr.hpp"
#include "anr_params.hpp"
#include "con... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/intensity_sigma_lut.hpp | #ifndef __INTENSITY_SIGMA_LUT_HPP__
#define __INTENSITY_SIGMA_LUT_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <type_traits>
#include "anr_params.hpp"
#include "constants.hpp"
//
// A LUT for computing the intensity sigma value of a pixel
//
class IntensitySigmaLUT {
public:... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/shift_reg.hpp | #ifndef __SHIFT_REG_HPP__
#define __SHIFT_REG_HPP__
#include "data_bundle.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "unrolled_loop.hpp"
namespace fpga_tools {
//
// A class to represent a shift register of depth 'depth' holding elements
// of type 'T'.
//
template <typename T, int depth... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/anr.hpp | #ifndef __ANR_HPP__
#define __ANR_HPP__
//
// This file contains a bulk of the functionality for the ANR design on the
// on the device. It contains the logic to submit the various kernels for the
// ANR pipeline.
//
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_ty... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/row_stencil.hpp | #ifndef __ROW_STENCIL_HPP__
#define __ROW_STENCIL_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <limits>
#include "data_bundle.hpp"
#include "shift_reg.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
usi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/data_bundle.hpp | #ifndef __DATA_BUNDLE_HPP__
#define __DATA_BUNDLE_HPP__
namespace fpga_tools {
//
// A class used to group together 'bundle_size' elements of type 'T' into a
// struct. Similar to an array but with the copyer constructor and operator=()
// overridden to avoid expensive copys.
//
template <typename T, int bundle_size>... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/qfp.hpp | #ifndef __QFP_HPP__
#define __QFP_HPP__
#include <array>
#include <limits>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
//
// A static class that is used to convert to/from 32-bit floating point
// and quantized floating point (... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/constants.hpp | #ifndef __CONSTANTS_HPP__
#define __CONSTANTS_HPP__
#include <sycl/ext/intel/ac_types/ac_int.hpp>
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
// The size of the filter can be changed at the command line
#ifndef FILTER_SIZE
#define FILTER_SIZE 9
#endif
constexpr unsigned kFi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/anr_params.hpp | #ifndef __ANR_PARAMS_HPP__
#define __ANR_PARAMS_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_fixed.hpp>
#include <iostream>
#include <fstream>
#include <string>
#include <utility>
//
// A struct to hold the ANR configuration paremeters
//
struct ANR... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/column_stencil.hpp | #ifndef __COLUMN_STENCIL_HPP__
#define __COLUMN_STENCIL_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "data_bundle.hpp"
#include "shift_reg.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
using namespace... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/qfp_inv_lut.hpp | #ifndef __QFP_INV_LUT_HPP__
#define __QFP_INV_LUT_HPP__
#include "qfp.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "rom_base.hpp"
// the QFP bits for the Pow2LUT
constexpr unsigned kInvQFPTotalBits = 10;
constexpr unsigned kInvQFPExponentBits = 3;
constexpr unsigned kInvLutDepth = (1 << kIn... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/qfp_exp_lut.hpp | #ifndef __QFP_EXP_LUT_HPP__
#define __QFP_EXP_LUT_HPP__
#include "qfp.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "rom_base.hpp"
// the QFP bits for the ExpLUT
constexpr unsigned kExpQFPTotalBits = 10;
constexpr unsigned kExpQFPExponentBits = 6;
constexpr unsi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/dma_kernels.hpp | #ifndef __DMA_KERNELS_HPP__
#define __DMA_KERNELS_HPP__
//
// This file contains the kernels for reading from device memory and
// streaming into the ANR input pipe, as well as the kernels for reading from
// the ANR output pipe and writing to device memory.
//
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_e... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/pca/src/golden_pca.hpp | #include <math.h>
#include <iomanip>
#include <random>
#include <fstream>
/*
This file implements the steps to
identify principal components (Eigen vectors)
of a matrix and finally transform input matrix
along the directions of the principal components
Following are the main steps in order to transform an
matrix A m... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/pca/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matrices to the "MatrixPipe" pipe num_elem_per_bank by
num_el... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/pca/src/pca_demo.cpp | #include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include <vector>
#define DEBUG 0
#include "exception_handler.hpp"
#include "golden_pca.hpp"
#include "pca.hpp"
int main(int argc, char *argv[]) {
#if defined(FPGA_SIMULATOR)
// Only read a few line... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/pca/src/pca.hpp | #ifndef __PCA_HPP__
#define __PCA_HPP__
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include <vector>
#include "memory_transfers.hpp"
#include "streaming_covariance_matrix.hpp"
#include "streaming_eigen.hpp"
#include "tuple.hpp"
// Forward decl... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/qri_demo.cpp | #include <math.h>
#include <sycl/sycl.hpp>
#include <chrono>
#include <iomanip>
#include <list>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
#include "qri.hpp"
#ifdef FPGA_SIMULATOR
#define ROWS_COMPONENT_V 8
#define COLS_COMPONENT_V... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/qri.hpp | #pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <chrono>
#include <cstring>
#include <type_traits>
#include <vector>
#include "memory_transfers.hpp"
#include "streaming_qrd.hpp... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
#include "tuple.hpp"
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matrices to the "MatrixPipe" pipe num_elem_per_bank by
num_el... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <assert.h>
#include <fcntl.h>
#include <limits.h>
#include <memory.h>
#include <stdint.h>
#include <stdio.h>
#incl... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/dbdata.cpp | #include <assert.h>
#include <algorithm>
#include <cctype>
#include <cmath>
#include <iomanip>
#include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <stdio.h>
#include <vector>
#include "dbdata.hpp"
#include "db_utils/Date.hpp"
// choose a file separator based on the platform (Windows o... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/dbdata.hpp | #ifndef __DBDATA_HPP__
#define __DBDATA_HPP__
#pragma once
#include <array>
#include <string>
#include <type_traits>
#include <unordered_map>
#include <vector>
// database types
using DBIdentifier = unsigned int;
using DBUint = unsigned int;
using DBInt = unsigned int;
using DBDecimal = long long;
using DBDate = unsi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Date.hpp | #ifndef __DATE_HPP__
#define __DATE_HPP__
#pragma once
#include <fstream>
#include <sstream>
#include <string>
//
// Class for storing and computing operations on a date
//
class Date {
public:
Date(const int y, const int m, const int d) : year(y), month(m), day(d) {}
Date(std::string date_str) {
// parse mo... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/LikeRegex.hpp | #ifndef __LIKEREGEX_HPP__
#define __LIKEREGEX_HPP__
#pragma once
#include <array>
#include <type_traits>
//
// Regex LIKE engine that can match: *WORD*, *WORD and WORD*
// where the string has max_str_length words or length at most max_word_length.
// If words are shorter than max_word_length, they are padded with '\... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/MapJoin.hpp | #ifndef __MAPJOIN_HPP__
#define __MAPJOIN_HPP__
#pragma once
#include <functional>
#include <set>
#include <tuple>
#include <type_traits>
#include <utility>
#include "Unroller.hpp"
#include "Tuple.hpp"
#include "StreamingData.hpp"
//
// MapJoin implementation
//
template<typename MapType, typename T2Pipe, typename T... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Accumulator.hpp | #ifndef __ACCUMULATOR_HPP__
#define __ACCUMULATOR_HPP__
#pragma once
#include <limits>
#include <type_traits>
#include "Tuple.hpp"
#include "Unroller.hpp"
///////////////////////////////////////////////////////
//
// Register-based accumulator
// Accumulates into size bins of type StorageType
//
template <typename S... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/ShannonIterator.hpp | #ifndef __SHANNONITERATOR_HPP__
#define __SHANNONITERATOR_HPP__
#pragma once
#include <array>
#include <type_traits>
#include "Tuple.hpp"
#include "Unroller.hpp"
//
// This class is intended to improve iterator performance for the FPGA.
// It optimizes the critical by precomputing the iterator change and comparison
... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Unroller.hpp | #ifndef __UNROLLER_HPP__
#define __UNROLLER_HPP__
#pragma once
#include <type_traits>
#include <utility>
//
// The code below creates the constexprs 'make_integer_range'
// and 'make_index_range' these are akin to 'std::make_integer_sequence'
// and 'std::make_index_sequence', respectively.
// However they allow you ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Misc.hpp | #ifndef __MISC_HPP__
#define __MISC_HPP__
#pragma once
#include <type_traits>
//// Some useful math functions
//
// computes 2^n where 'n' is a compile time constant
//
template <typename T>
static constexpr T Pow2(T n) {
return T(1) << n;
}
//
// base-2 logarithm
//
template <typename T>
static constexpr T Log2(... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/StreamingData.hpp | #ifndef __STREAMINGDATA_HPP__
#define __STREAMINGDATA_HPP__
#pragma once
#include <type_traits>
#include "Tuple.hpp"
//
// Generic datatype for streaming data that holds 'Size' elements of type 'Type'
//
template <typename Type, int Size>
class StreamingData {
// static asserts
static_assert(Size > 0, "Size posi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/fifo_sort.hpp | #ifndef __FIFO_SORT_H__
#define __FIFO_SORT_H__
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iostream>
#include <tuple>
#include <utility>
#include "Misc.hpp"
/*
The sort() function in this header implements a local-memory-based FIFO-Based
Merge Sorter, which has been based on the architecture shown in Fi... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/MergeJoin.hpp | #ifndef __MERGE_JOIN_HPP__
#define __MERGE_JOIN_HPP__
#pragma once
#include <functional>
#include <set>
#include <tuple>
#include <type_traits>
#include <utility>
#include "Unroller.hpp"
#include "Tuple.hpp"
#include "StreamingData.hpp"
#include "ShannonIterator.hpp"
using namespace sycl;
//
// Joins two tables int... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/CachedMemory.hpp | #ifndef __CACHED_MEMORY_HPP__
#define __CACHED_MEMORY_HPP__
template <typename StorageType, int n, int cache_n,
typename IndexType = int>
class CachedMemory {
// static asserts
static_assert(n > 0);
static_assert(cache_n >= 0);
static_assert(std::is_arithmetic<StorageType>::value,
"St... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Tuple.hpp | #ifndef __TUPLE_HPP__
#define __TUPLE_HPP__
#pragma once
#include <type_traits>
//
// Generic tuple
//
// USAGE EXAMPLE:
// Tuple<char,short,int,long> my_tuple;
// char a = my_tuple.get<0>();
// short b = my_tuple.get<1>();
// int c = my_tuple.get<2>();
// long d = my_tuple.get<3>();
//
template <typen... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query9/query9_kernel.hpp | #ifndef __QUERY9_KERNEL_HPP__
#define __QUERY9_KERNEL_HPP__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../dbdata.hpp"
using namespace sycl;
bool SubmitQuery9(queue& q, Database& dbinfo,
std::string colour,
std::array<DBDecimal, 2... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query9/query9_kernel.cpp | #include <array>
#include <stdio.h>
#include <type_traits>
#include <vector>
#include "query9_kernel.hpp"
#include "pipe_types.hpp"
#include "onchip_memory_with_cache.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "../db_utils/Accumulator.hpp"
#include "../db_utils/LikeRegex.hpp"
#include "../db_utils/MapJo... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query9/pipe_types.hpp | #ifndef __PIPE_TYPES_H__
#define __PIPE_TYPES_H__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../db_utils/StreamingData.hpp"
#include "../dbdata.hpp"
using namespace sycl;
//
// A single row of the PARTSUPPLIER table
// with a subset of the columns (needed for this ... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query12/query12_kernel.cpp | #include <array>
#include <limits>
#include <stdio.h>
#include "query12_kernel.hpp"
#include "pipe_types.hpp"
#include "../db_utils/MergeJoin.hpp"
#include "../db_utils/Unroller.hpp"
#include "../db_utils/Tuple.hpp"
using namespace std::chrono;
// kernel class names
class LineItemProducer;
class OrdersProducer;
cla... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query12/pipe_types.hpp | #ifndef __PIPE_TYPES_H__
#define __PIPE_TYPES_H__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../db_utils/StreamingData.hpp"
#include "../dbdata.hpp"
using namespace sycl;
//
// A single row of the ORDERS table
// with a subset of the columns (needed for this query)... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query12/query12_kernel.hpp | #ifndef __QUERY12_KERNEL_HPP__
#define __QUERY12_KERNEL_HPP__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../dbdata.hpp"
using namespace sycl;
bool SubmitQuery12(queue& q, Database& dbinfo,
DBDate low_date, DBDate high_date,
int... | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query11/query11_kernel.cpp | #include <stdio.h>
#include <type_traits>
#include "query11_kernel.hpp"
#include "pipe_types.hpp"
#include "../db_utils/CachedMemory.hpp"
#include "../db_utils/MapJoin.hpp"
#include "../db_utils/Misc.hpp"
#include "../db_utils/Tuple.hpp"
#include "../db_utils/Unroller.hpp"
#include "../db_utils/fifo_sort.hpp"
#inclu... | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query11/query11_kernel.hpp | #ifndef __QUERY11_KERNEL_HPP__
#define __QUERY11_KERNEL_HPP__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../dbdata.hpp"
using namespace sycl;
bool SubmitQuery11(queue& q, Database& dbinfo,
std::string& nation,
std::vector<DBIde... | hpp |
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