repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
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stringlengths 590
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|---|---|---|---|
32bitmicro/newlib-nano-1.0
| 1,509
|
libgloss/rx/unlink.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "rxsys.h"
S(unlink)
|
32bitmicro/newlib-nano-1.0
| 3,370
|
libgloss/m68k/cf-isv.S
|
/* The interrupt table.
*
* Copyright (c) 2006 CodeSourcery Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
.macro SLOT,n,prefix=,suffix=
.long __\prefix\n\suffix
.endm
.macro ISR n
SLOT \n,interrupt,
.endm
.macro TRAP n
SLOT \n,trap,
.endm
.macro FP n
SLOT \n,fp_,
.endm
.macro UNIMP_OPCODE n
SLOT \n,unimplemented_,_opcode
.endm
.macro BREAKPOINT_DEBUG n
SLOT \n,,_breakpoint_debug_interrupt
.endm
.section .interrupt_vector,"a"
.globl __interrupt_vector
__interrupt_vector:
.long __stack /* 0 */
.long __reset /* 1 */
.long __access_error /* 2 */
.long __address_error /* 3 */
.long __illegal_instruction /* 4 */
.long __divide_by_zero /* 5 */
ISR 6
ISR 7
.long __privilege_violation /* 8 */
.long __trace /* 9 */
UNIMP_OPCODE line_a /* 10 */
UNIMP_OPCODE line_f /* 11 */
BREAKPOINT_DEBUG non_pc /* 12 */
BREAKPOINT_DEBUG pc /* 13 */
.long __format_error /* 14 */
.irp N,15,16,17,18,19,20,21,22,23
ISR \N /* [15,24) */
.endr
.long __spurious_interrupt /* 24 */
.irp N,25,26,27,28,29,30,31
ISR \N /* [25,32) */
.endr
.irp N,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TRAP \N /* [32,48) */
.endr
FP branch_unordered /* 48 */
FP inexact_result /* 49 */
FP divide_by_zero /* 50 */
FP underflow /* 51 */
FP operand_error /* 52 */
FP overflow /* 53 */
FP input_not_a_number /* 54 */
FP input_denormalized_number /* 55 */
.irp N,56,57,58,59,60
ISR \N /* [56,61) */
.endr
.long __unsupported_instruction /* 61 */
.irp N,62,63
ISR \N /* [62,64) */
.endr
.irp N,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79
ISR \N /* [64,80) */
.endr
.irp N,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
ISR \N /* [80,96) */
.endr
.irp N,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111
ISR \N /* [96,112) */
.endr
.irp N,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127
ISR \N /* [112,128) */
.endr
.irp N,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143
ISR \N /* [128,144) */
.endr
.irp N,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159
ISR \N /* [144,160) */
.endr
.irp N,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175
ISR \N /* [160,176) */
.endr
.irp N,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191
ISR \N /* [176,192) */
.endr
.irp N,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207
ISR \N /* [192,208) */
.endr
.irp N,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223
ISR \N /* [208,224) */
.endr
.irp N,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239
ISR \N /* [224,240) */
.endr
.irp N,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255
ISR \N /* [240,256) */
.endr
|
32bitmicro/newlib-nano-1.0
| 2,780
|
libgloss/m68k/sim-crt0.S
|
/*
* crt0.S -- startup file for m68k-coff
*
* Copyright (c) 1995, 1996, 1998, 2001 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
.title "crt0.S for m68k-coff"
#define STACKSIZE 0x4000
/*
* Define an empty environment.
*/
.data
.align 2
SYM (environ):
.long 0
.align 2
.text
/*
* These symbols are defined in C code, so they need to always be
* named with SYM because of the difference between object file formats.
*/
/* These are defined in C code. */
.extern SYM (main)
.extern SYM (exit)
.extern SYM (atexit)
.extern SYM(__do_global_dtors)
/*
* These values are set in the linker script, so they must be
* explicitly named here without SYM.
*/
.extern __stack
.extern __bss_start
.extern _end
/*
* set things up so the application will run. This *must* be called start.
*/
.global SYM (start)
SYM (start):
/* See if user supplied their own stack (__stack != 0). If not, then
* default to using the value of %sp as set by the ROM monitor.
*/
movel IMM(__stack), a0
cmpl IMM(0), a0
jbeq 1f
movel a0, sp
1:
/* set up initial stack frame */
link a6, IMM(-8)
/*
* zero out the bss section.
*/
movel IMM(__bss_start), d1
movel IMM(_end), d0
cmpl d0, d1
jbeq 3f
movl d1, a0
subl d1, d0
subql IMM(1), d0
2:
clrb (a0)+
#if !defined(__mcoldfire__) && !defined(__mcf5200__)
dbra d0, 2b
clrw d0
subql IMM(1), d0
jbcc 2b
#else
subql IMM(1), d0
jbpl 2b
#endif
3:
/*
* call the main routine from the application to get it going.
* main (argc, argv, environ)
* we pass argv as a pointer to NULL.
*/
#ifdef ADD_DTORS
/* put __do_global_dtors in the atexit list so the destructors get run */
movel IMM (SYM(__do_global_dtors)),(sp)
PICCALL SYM (atexit)
#endif
movel IMM (__FINI_SECTION__),(sp)
PICCALL SYM (atexit)
PICCALL __INIT_SECTION__
pea 0
PICPEA SYM (environ),a0
pea sp@(4)
pea 0
PICCALL SYM (main)
movel d0, sp@-
/*
* drop down into exit incase the user doesn't. This should drop
* control back to the ROM monitor, if there is one. This calls the
* exit() from the C library so the C++ tables get cleaned up right.
*/
PICCALL SYM (exit)
|
32bitmicro/newlib-nano-1.0
| 1,693
|
libgloss/m68k/simulator.S
|
/*
* simulator.S -- m68k simulator system calls.
*
* Copyright (c) 1995, 2001 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
#define SYSCALL(x) .word 0x4afc, x
#define FUNC_START(x) .globl x; x:
#define FUNC_END(x)
#define FUNC_NAME(x) SYM(x)
FUNC_START(_exit)
SYSCALL(1)
/*
* Insure that the debugger tells the client that the PC is in _exit,
* not whatever function happens to follow this function.
*/
0: nop
jmp 0b /* we never should return, but... */
FUNC_END(_exit)
FUNC_START(read)
SYSCALL(3)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(read)
FUNC_START(write)
SYSCALL(4)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(write)
FUNC_START(open)
SYSCALL(5)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(open)
FUNC_START(close)
SYSCALL(6)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(close)
FUNC_START(brk)
SYSCALL(17)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(brk)
FUNC_START(lseek)
SYSCALL(199)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(lseek)
FUNC_START(fstat)
SYSCALL(28)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(lseek)
FUNC_START(isatty)
SYSCALL(29)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(isatty)
|
32bitmicro/newlib-nano-1.0
| 1,146
|
libgloss/m68k/fido-hosted.S
|
/*
* fido-hosted.S --
*
* Copyright (c) 2006 CodeSourcery Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* Semihosting function. The debugger intercepts the halt, and
determines that it is followed by the sentinel pattern. */
.globl __hosted
__hosted:
linkw %fp,#0
movel %fp@(8),%d0
movel %fp@(12),%d1
.align 4
nop
bkpt #0
/* This sentinel instruction value must be immediately after
the bkpt instruction. The debugger will adjust the pc, so
that it is never executed. This instruction is
'movec %sp,0'. */
.long 0x4e7bf000
unlk %fp
rts
|
32bitmicro/newlib-nano-1.0
| 14,877
|
libgloss/m68k/mvme135-asm.S
|
/*
* mvme135-asm.S -- assembler routines for the MVME stub.
*
* This code was pulled out of mvme135-stub.c by Ian Taylor so that I
* could handle different register and label prefixes in a sensible
* way.
*/
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
#include "asm.h"
.title "mvme135-asm.S for m68k"
.globl SYM (registers)
.globl SYM (lastFrame)
.globl SYM (superStack)
.globl SYM (exceptionHook)
.globl SYM (_returnFromException)
.globl SYM (stackPtr)
.globl SYM (handle_exception)
.globl SYM (exceptionSize)
.globl SYM (exceptionHandler)
.text
/*
* Create a new exception vector table and populates it. Vectors from the
* boot monitor are spliced in so I/O and the abort button will continue
* to work. We also use the monitor's generalized vector for anything the
* debugger doesn't want.
*/
.global SYM (setup_vectors)
SYM (setup_vectors):
link fp, IMM (-8)
/* copy monitor vector table */
movecl vbr, a0
lea SYM (vbr_table), a1
movel 0x8(a0), d0 /* get generalized vector */
movew IMM (0x3fc), d1 /* load vector count */
loop: /* fill table to gen. vector */
movel d0, (a1,d1)
subqw IMM (4), d1
bne loop
movel 0x10(a0), 0x10(a1) /* breakpoint */
movel 0x24(a0), 0x24(a1) /* trace */
movel 0xbc(a0), 0xbc(a1) /* system call */
/* add stub vectors to table */
movel SYM (_catchException), 0x8(a1) /* vector = 2, Access Fault */
movel SYM (_catchException), 0xc(a1) /* vector = 3, Address Error */
movel SYM (_catchException), 0x10(a1) /* vector = 4, Illegal instruction */
movel SYM (_catchException), 0x14(a1) /* vector = 5, divide by 0 */
movel SYM (_catchException), 0x18(a1) /* vector = 6, chk, chk2 instruction */
movel SYM (_catchException), 0x1c(a1) /* vector = 7, ftrap, trap, trapv ins */
movel SYM (_catchException), 0x20(a1) /* vector = 8, priviledge violation */
movel SYM (_catchException), 0x24(a1) /* vector = 9, trace */
movel SYM (_catchException), 0x28(a1) /* vector = 10, Aline opcode */
movel SYM (_catchException), 0x2c(a1) /* vector = 11, fline opcode */
movel SYM (_catchException), 0x30(a1) /* vector = 12, reserved */
movel SYM (_catchException), 0x34(a1) /* vector = 13, coprocessor protocol violation */
movel SYM (_catchException), 0x38(a1) /* vector = 14, format error */
movel SYM (_catchException), 0x3c(a1) /* vector = 15, unitialized interupt */
/* unassigned, reserved */
movel SYM (_catchException), 0x40(a1) /* vector = 16 */
movel SYM (_catchException), 0x44(a1) /* vector = 17 */
movel SYM (_catchException), 0x48(a1) /* vector = 18 */
movel SYM (_catchException), 0x4c(a1) /* vector = 19 */
movel SYM (_catchException), 0x50(a1) /* vector = 20 */
movel SYM (_catchException), 0x54(a1) /* vector = 21 */
movel SYM (_catchException), 0x58(a1) /* vector = 22 */
movel SYM (_catchException), 0x5c(a1) /* vector = 23 */
movel SYM (_catchException), 0x84(a1) /* vector = 33, breakpoint, trap #1 */
movel SYM (_catchException), 0xa0(a1) /* vector = 40 , trap #8*/
/* floating point traps */
movel SYM (_catchException), 0xc0(a1) /* vector = 48 */
movel SYM (_catchException), 0xc4(a1) /* vector = 49 */
movel SYM (_catchException), 0xc8(a1) /* vector = 50 */
movel SYM (_catchException), 0xcc(a1) /* vector = 51 */
movel SYM (_catchException), 0xd0(a1) /* vector = 52 */
movel SYM (_catchException), 0xd4(a1) /* vector = 53 */
movel SYM (_catchException), 0xd8(a1) /* vector = 54 */
movel SYM (_catchException), 0xdc(a1) /* vector = 55 */
movel SYM (_catchException), 0xe0(a1) /* vector = 56 */
movel SYM (_catchException), 0xe4(a1) /* vector = 57 */
movel SYM (_catchException), 0xe8(a1) /* vector = 58 */
/*** movel &__debug_level7, 0x7c(a1) /* level7 interupt vector */
movecl a1, vbr /* change VBR to new table */
unlk fp
rts
/*
* exceptionHandler -- sets up exception vector table.
* First arg is an integer vector number
* Second arg is the function pointer for the vector
*/
SYM (exceptionHandler):
# link a6, IMM (-8)
#str1: .ascii "Exception Handler Called\n"
# moveal IMM (str1), a0
# moveal IMM (str1+25), a1
# jsr SYM (outln)
# unlk a6
rts
/* this never gets called */
movel fp@(8), d0 /* get vector number */
movel fp@(12), a0 /* get function address */
moveal &SYM (vbr_table), a1 /* FIXME */
addl d0, d0
addl d0, d0
addal d0, a1
movel a0, (a1)
movecl a1, vbr
unlk a6
rts
.globl SYM (return_to_super)
SYM (return_to_super):
movel SYM (registers)+60,sp /* get new stack pointer */
movel SYM (lastFrame),a0 /* get last frame info */
bra return_to_any
.globl SYM (return_to_user)
SYM (return_to_user):
movel SYM (registers)+60,a0 /* get usp */
movel a0,usp /* set usp */
movel SYM (superStack),sp /* get original stack pointer */
return_to_any:
movel SYM (lastFrame),a0 /* get last frame info */
movel a0@+,SYM (lastFrame) /* link in previous frame */
addql IMM (8),a0 /* skip over pc, vector#*/
movew a0@+,d0 /* get # of words in cpu frame */
addw d0,a0 /* point to end of data */
addw d0,a0 /* point to end of data */
movel a0,a1
/* copy the stack frame */
subql IMM (1),d0
copyUserLoop:
movew a1@-,sp@-
dbf d0,copyUserLoop
#ifdef __HAVE_68881__
fmoveml SYM (registers)+168,fpcr/fpsr/fpi
fmovemx SYM (registers)+72,fp0-fp7
cmpl IMM (-1),a0@ /* skip frestore flag set ? */
beq skip_frestore
frestore a0@+
skip_frestore:
#endif
moveml SYM (registers),d0-d7/a0-a6
rte /* pop and go! */
/* this function is called immediately when a level 7 interrupt occurs */
/* if the previous interrupt level was 7 then we're already servicing */
/* this interrupt and an rte is in order to return to the debugger. */
/* For the 68000, the offset for sr is 6 due to the jsr return address */
.text
.globl SYM (_debug_level7)
SYM (_debug_level7):
movew d0,sp@-
#ifdef mc68020
movew sp@(2),d0
#else
movew sp@(6),d0
#endif
andiw IMM (0x700),d0
cmpiw IMM (0x700),d0
beq _already7
movew sp@+,d0
bra SYM (_catchException)
_already7:
movew sp@+,d0
#ifndef mc68020
lea sp@(4),sp /* pull off 68000 return address */
#endif
rte
#ifdef mc68020
/* This function is called when a 68020 exception occurs. It saves
* all the cpu and fpcp regs in the _registers array, creates a frame on a
* linked list of frames which has the cpu and fpcp stack frames needed
* to properly restore the context of these processors, and invokes
* an exception handler (remcom_handler).
*
* stack on entry: stack on exit:
* N bytes of junk exception # MSWord
* Exception Format Word exception # MSWord
* Program counter LSWord
* Program counter MSWord
* Status Register
*
*
*/
.text
.globl SYM (_catchException)
SYM (_catchException):
oriw IMM (0x0700),sr /* Disable interrupts */
moveml d0-d7/a0-a6,SYM (registers) /* save registers */
movel SYM (lastFrame),a0 /* last frame pointer */
#ifdef __HAVE_68881__
/* do an fsave, then remember the address to begin a restore from */
fsave a0@-
fmovemx fp0-fp7, SYM (registers)+72
fmoveml fpcr/fpsr/fpi, SYM (registers)+168
#endif
lea SYM (registers),a5 /* get address of registers */
movew sp@,d1 /* get status register */
movew d1,a5@(66) /* save sr */
movel sp@(2),a4 /* save pc in a4 for later use */
movel a4,a5@(68) /* save pc in _regisers[] */
/* figure out how many bytes in the stack frame */
movew sp@(6),d0 /* get '020 exception format */
movew d0,d2 /* make a copy of format word */
andiw IMM (0xf000),d0 /* mask off format type */
rolw IMM (5),d0 /* rotate into the low byte *2 */
lea SYM (exceptionSize),a1
addw d0,a1 /* index into the table */
movew a1@,d0 /* get number of words in frame */
movew d0,d3 /* save it */
subw d0,a0 /* adjust save pointer */
subw d0,a0 /* adjust save pointer(bytes) */
movel a0,a1 /* copy save pointer */
subql IMM (1),d0 /* predecrement loop counter */
/* copy the frame */
saveFrameLoop:
movew sp@+,a1@+
dbf d0,saveFrameLoop
/* now that the stack has been clenaed,
* save the a7 in use at time of exception
*/
movel sp,SYM (superStack) /* save supervisor sp */
andiw IMM (0x2000),d1 /* were we in supervisor mode ? */
beq userMode
movel a7,a5@(60) /* save a7 */
bra a7saveDone
userMode:
movel usp,a1
movel a1,a5@(60) /* save user stack pointer */
a7saveDone:
/* save size of frame */
movew d3,a0@-
/* compute exception number */
andl IMM (0xfff),d2 /* mask off vector offset */
lsrw IMM (2),d2 /* divide by 4 to get vect num */
movel d2,a0@- /* save it */
/* save pc causing exception */
movel a4,a0@-
/* save old frame link and set the new value*/
movel SYM (lastFrame),a1 /* last frame pointer */
movel a1,a0@- /* save pointer to prev frame */
movel a0,SYM (lastFrame)
movel d2,sp@- /* push exception num */
#ifdef TMP_HACK
movel SYM (exceptionHook),a0 /* get address of handler */
jbsr a0@ /* and call it */
#else
jbsr SYM (remcomHandler)
#endif
clrl sp@ /* replace exception num parm with frame ptr */
jbsr SYM (_returnFromException) /* jbsr, but never returns */
#else /* mc68000 */
/* This function is called when an exception occurs. It translates the
* return address found on the stack into an exception vector # which
* is then handled by either handle_exception or a system handler.
* _catchException provides a front end for both.
*
* stack on entry: stack on exit:
* Program counter MSWord exception # MSWord
* Program counter LSWord exception # MSWord
* Status Register
* Return Address MSWord
* Return Address LSWord
*/
.text
.globl SYM (_catchException)
SYM (_catchException):
oriw IMM (0x0700),sr /* Disable interrupts */
moveml d0-d7/a0-a6,SYM (registers) /* save registers */
movel SYM (lastFrame),a0 /* last frame pointer */
#ifdef __HAVE_68881__
/* do an fsave, then remember the address to begin a restore from */
fsave a0@-
fmovemx fp0-fp7, SYM (registers)+72
fmoveml fpcr/fpsr/fpi, SYM (registers)+168
#endif
lea SYM (registers),a5 /* get address of registers */
movel sp@+,d2 /* pop return address */
addl IMM (1530),d2 /* convert return addr to */
divs IMM (6),d2 /* exception number */
extl d2
moveql IMM (3),d3 /* assume a three word frame */
cmpiw IMM (3),d2 /* bus error or address error ? */
bgt normal /* if >3 then normal error */
movel sp@+,a0@- /* copy error info to frame buff*/
movel sp@+,a0@- /* these are never used */
moveql IMM (7),d3 /* this is a 7 word frame */
normal:
movew sp@+,d1 /* pop status register */
movel sp@+,a4 /* pop program counter */
movew d1,a5@(66) /* save sr */
movel a4,a5@(68) /* save pc in _regisers[] */
movel a4,a0@- /* copy pc to frame buffer */
movew d1,a0@- /* copy sr to frame buffer */
movel sp,SYM (superStack) /* save supervisor sp */
andiw IMM (0x2000),d1 /* were we in supervisor mode ? */
beq userMode
movel a7,a5@(60) /* save a7 */
bra saveDone
userMode:
movel usp,a1 /* save user stack pointer */
movel a1,a5@(60) /* save user stack pointer */
saveDone:
movew d3,a0@- /* push frame size in words */
movel d2,a0@- /* push vector number */
movel a4,a0@- /* push exception pc */
/* save old frame link and set the new value */
movel SYM (lastFrame),a1 /* last frame pointer */
movel a1,a0@- /* save pointer to prev frame */
movel a0,SYM (lastFrame)
movel d2,sp@- /* push exception num */
movel SYM (exceptionHook),a0 /* get address of handler */
jbsr a0@ /* and call it */
clrl sp@ /* replace exception num parm with frame ptr */
jbsr SYM (_returnFromException) /* jbsr, but never returns */
#endif /* m68000 */
/*
* remcomHandler is a front end for handle_exception. It moves the
* stack pointer into an area reserved for debugger use in case the
* breakpoint happened in supervisor mode.
*/
.globl SYM (remcomHandler)
SYM (remcomHandler):
addl IMM (4),sp /* pop off return address */
movel sp@+,d0 /* get the exception number */
movel SYM (stackPtr),sp /* move to remcom stack area */
movel d0,sp@- /* push exception onto stack */
jbsr SYM (handle_exception) /* this never returns */
rts /* return */
|
32bitmicro/newlib-nano-1.0
| 2,590
|
libgloss/m68k/cpu32bug.S
|
/*
* cpu32bug.S -- board support for the CPU32BUG monitor.
*
* Copyright (c) 1995, 1996 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
#include "cpu32bug.h"
.title "cpu32bug.S for m68k-coff"
.text
.global SYM (_exit)
.global SYM (outln)
.global SYM (outbyte)
.global SYM (putDebugChar)
.global SYM (inbyte)
.global SYM (getDebugChar)
.global SYM (havebyte)
/*
* _exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run.
*/
.text
.align 2
SYM (_exit):
link fp, IMM(0)
trap IMM(15)
.word RETURN
/*
* inbyte -- get a byte from the serial port
* d0 - contains the byte read in
*/
.text
.align 2
SYM (getDebugChar): /* symbol name used by m68k-stub */
SYM (inbyte):
link fp, IMM(-8)
trap IMM(15)
.word INCHR
moveb sp@, d0
extw d0
extl d0
unlk fp
rts
/*
* outbyte -- sends a byte out the serial port
* d0 - contains the byte to be sent
*/
.text
.align 2
SYM (putDebugChar): /* symbol name used by m68k-stub */
SYM (outbyte):
link fp, IMM(-4)
moveb fp@(11), sp@
trap IMM(15)
.word OUTCHR
unlk fp
rts
/*
* outln -- sends a string of bytes out the serial port with a CR/LF
* a0 - contains the address of the string's first byte
* a1 - contains the address of the string's last byte
*/
.text
.align 2
SYM (outln):
link fp, IMM(-8)
moveml a0/a1, sp@
trap IMM(15)
.word OUTLN
unlk fp
rts
/*
* outstr -- sends a string of bytes out the serial port without a CR/LF
* a0 - contains the address of the string's first byte
* a1 - contains the address of the string's last byte
*/
.text
.align 2
SYM (outstr):
link fp, IMM(-8)
moveml a0/a1, sp@
trap IMM(15)
.word OUTSTR
unlk fp
rts
/*
* havebyte -- checks to see if there is a byte in the serial port,
* returns 1 if there is a byte, 0 otherwise.
*/
.text
.align 2
SYM (havebyte):
trap IMM(15)
.word INSTAT
beqs empty
movel IMM(1), d0
rts
empty:
movel IMM(0), d0
rts
|
32bitmicro/newlib-nano-1.0
| 28,115
|
libgloss/m68k/fido-crt0.S
|
/**
* fido-crt0.S -- Simple startup code
*
* Copyright (c) 1995, 1996, 1998 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
* Copyright 2006 Innovasic Semiconductor, All Rights Reserved.
* Part of the fido Realtime Support Library
*
* Description:
* This routine performs initializations assuming a Fido
* development board. In order, the following functions are performed:
*
* -- memory offset register initialization
* -- chip select register initialization for external memory
* -- SDRAM ctrl register initialization for external memory
* -- in line test of external SRAM
* -- sets user SP for MasterContext0 (main)
* -- copies the bss section to RAM
* -- transfers control to MasterContext0 (main)
*
*/
#include "asm.h"
#include "fido.h"
.title "fido-crt0.S for Fido"
/*----------------------------------------------------------------------------*/
//--------- 66 MHz values --------
// set up CS0 for flash
#define CS0_CTRL_VAL 0x0000024A
#define CS0_TIMING_VAL 0x01000000
// set up CS1 for SDRAM
#define CS1_CTRL_VAL 0x0200030A /* selects SDRAM ctrl instead of CS1 */
#define CS1_TIMING_VAL 0x00000000 /* N/A for SDRAM operation */
#define SDRAM_TIMING_0_VAL 0x00022522 /* TRP=0x2, TRCD=0x2, TRF=0x5, TWR=0x5 TCL=0x5 */
#define SDRAM_TIMING_1_VAL 0x00120407 /* INI_PREC=0x1, INI_REFT=0x2, REF_INTV=0x407 */
#define SDRAM_CONFIG_0_VAL 0x00002113 /* MA2T=0, DDW=x16device=0x2, dsz=64MBit, mbw=16bit, bnksz=8Mbyte */
#define SDRAM_CONFIG_1_VAL 0x00000000 /* IPREC=0, IREF=0, ISMR=0, PWDN=0, SREF=0 */
#define SDRAM_EXT_BANK_1_VAL 0x00001020 /* SDRAM memory bank 0 at addr 0x0200_0000 */
// set up CS2 for SRAM
#define CS2_CTRL_VAL 0x03000267
#define CS2_TIMING_VAL 0x08400000
/*----------------------------------------------------------------------------*/
#define EXT_SRAM_END_ADDR 0x30FFFFC /* 1 MB of ext. SRAM (2-512Kx8 chips) */
#define PERP_PWRUP_MASK 0x0000 /* turn on all peripherals */
/*
* Define an empty environment.
*/
.data 2
.align 2
SYM (environ):
.long 0
.align 2
.text 2
/*
* These symbols are defined in C code, so they need to always be
* named with SYM because of the difference between object file formats.
*/
/* These are defined in C code. */
/* .extern SYM (main) */
.extern SYM (exit)
.extern SYM (hardware_init_hook)
.extern SYM (software_init_hook)
.extern SYM (atexit)
.extern SYM (__do_global_dtors)
/*
* These values are set in the linker script, so they must be
* explicitly named here without SYM.
*/
#ifdef FIDO_rom
.extern __stack
#endif
.extern __bss_start
.extern _end
/*
* set things up so application will run. This *must* be called _start.
*/
.global SYM (_start)
SYM (_start):
#ifdef FIDO_rom
/* save initial value of base offset register */
movec mbb,d7
/* Initialize memory offset register to offset value in FIDOmemmap.h */
movel #FIDO_MEM_OFFSET,d0 /* Load memory offset into REG d0 */
movec d0,mbb
movel #0x011, FIDO_DBG_CTRL /* set the debug control reg */
/* At POR the PerpPowerCtrlReg is set to 0x3F0F, all peripherals off
See PerpPowerCtrlReg definition, this example turns ON everything */
movel #PERP_PWRUP_MASK,FIDO_CLOCK_MASK_REGISTER
/* Set up chip selects for ROM, SRAM, and SDRAM (all external mem.) */
movel #CS0_CTRL_VAL, FIDO_BIU_CS0_CONTROL /* flash memory CS0 */
movel #CS0_TIMING_VAL, FIDO_BIU_CS0_TIMING
movel #CS2_CTRL_VAL, FIDO_BIU_CS2_CONTROL /* SRAM memory CS2 */
movel #CS2_TIMING_VAL, FIDO_BIU_CS2_TIMING
/* if this is not POR then say so */
movel FIDO_POR_REG,d6
/* test external SRAM -- */
/* a0 == working pointer */
/* a1 == pointer to base of memory */
/* a2 == pointer to end of memory */
/* d0,d1,d2,d3 working registers */
moveal #0x3000000,a1
moveal #0x30FFFFC,a2
movel a1,a0
/* walking ones */
movel #1,d0
.LWalkOnes:
movel d0, (a0) /* write value out */
cmpl (a0), d0 /* read it back */
bne .LFailOnes
lsl.l #1, d0 /* move to next value */
bne .LWalkOnes /* when it goes to zero you're done */
bra .LValTest
.LFailOnes:
movel #0x01, d0
bra .LMemTestEnd
.LValTest:
/* ffff's */
/* 5555's */
/* aaaa's */
/* 0000's */
movel a1,a0
movel #0xFFFFFFFF,d0
.LValLoop:
movel d0,(a0) /* write value out */
cmpl (a0)+, d0 /* compare and move to next */
bne .LFailVal
cmpl a0,a2 /* at end of memory? */
bge .LValLoop
movel d0,d0 /* done writing zeros? */
beq .LAddrTest
movel a1,a0 /* go back to start with next value */
subl #0x55555555,d0 /* get next value (f->a->5->0) */
bra .LValLoop
.LFailVal:
movel #0x02, d0
bra .LMemTestEnd
.LAddrTest:
/* unique values */
movel a1,a0
.LWriteLoop:
movel a0, (a0)+ /* write value out and move one */
cmpl a0,a2 /* look for end of memory */
bge .LWriteLoop
movel a1,a0
.LReadLoop:
cmpl (a0), a0 /* compare value and move on */
bne .LFailAddr
addql #4,a0
cmpl a0,a2 /* look for end of memory */
bge .LReadLoop
clrl d0 /* everything passed */
bra .LMemTestEnd
.LFailAddr:
movel #0x03, d0
.LMemTestEnd:
movel d0,d4 /* mem test result in d4 0 == pass */
#endif /* ROM */
/* See if user supplied their own stack (__stack != 0). If not, then
* default to using the value of %sp as set by the ROM monitor */
movel IMM(__stack), a0
cmpl IMM(0), a0
jbeq .Lloc1
movel a0, sp
.Lloc1:
/* set up initial stack frame */
link a6, IMM(-8)
#ifdef FIDO_rom
/*
* Now set up the SDRAM (waited to let the controller spin up)
*/
/* always initialize SDRAM regs, they're cleared by any reset */
/* SDRAM enbl bit set in CS1 re-directs to SDRAM controller regs */
movel #CS1_CTRL_VAL, FIDO_BIU_CS1_CONTROL /* SDRAM memory CS1 */
movel #SDRAM_TIMING_0_VAL, FIDO_SDRAM_TIMING_0 /* SDRAM TIMING REG0 */
movel #SDRAM_TIMING_1_VAL, FIDO_SDRAM_TIMING_1 /* SDRAM TIMING REG1 */
movel #SDRAM_CONFIG_0_VAL, FIDO_SDRAM_CONFIG_0 /* SDRAM CONFIG REG */
movel #0x0000001c, FIDO_SDRAM_CONFIG_1 /* SDRAM CONFIG REG */
.LsdConfigLoop:
movel FIDO_SDRAM_CONFIG_1,d0
cmpl #0x00000000,d0
bne .LsdConfigLoop
movel #SDRAM_EXT_BANK_1_VAL, FIDO_SDRAM_EXT_BANK_1 /* BANK 1 REG */
/*
* copy data from ROM to RAM
*/
moval IMM(__start_romdata),a0 /* begin data in ROM */
moval IMM(_data), a1 /* begin data in RAM */
moval IMM(_edata),a2 /* end of data in RAM */
/* while(a1 < a2) *a1++ = *a0++; */
.LdataCopyLoop:
movel (a0)+,(a1)+
cmpal a1,a2
bgt .LdataCopyLoop
#endif /* ROM */
#ifdef FIDO_ram
/* For ROM configs, the linker script ensures that
_vector_table is placed at the proper place. For RAM
configs, we have to adjust it ourselves. */
movel IMM (SYM (_vector_table)), FIDO_CTX0_VBR
#endif
#ifndef FIDO_redboot
/* Setup interrupt vectors for secondary contexts. */
movel IMM (SYM (_vector_table1)), FIDO_CTX1_VBR
movel IMM (SYM (_vector_table2)), FIDO_CTX2_VBR
movel IMM (SYM (_vector_table3)), FIDO_CTX3_VBR
movel IMM (SYM (_vector_table4)), FIDO_CTX4_VBR
#endif
/*
* zero out the bss section.
*/
movel IMM(__bss_start), d1
movel IMM(_end), d0
cmpl d0, d1
jbeq .Lloc3
movl d1, a0
subl d1, d0
subql IMM(1), d0
2:
clrb (a0)+
#ifndef __mcf5200__
dbra d0, 2b
clrw d0
subql IMM(1), d0
jbcc 2b
#else
subql IMM(1), d0
jbpl 2b
#endif
.Lloc3:
#ifdef ADD_DTORS
/* put __do_global_dtors in the atexit list so the destructors get run */
movel IMM (SYM(__do_global_dtors)),(sp)
jsr SYM (atexit)
#endif
movel IMM (_fini),(sp)
jsr SYM (atexit)
jsr _init
/*
* call the main routine from the application to get it going.
* main (argc, argv, environ)
* we pass argv as a pointer to NULL.
*/
pea 0
pea SYM (environ)
pea sp@(4)
pea 0
jsr SYM (main) /* call to main */
movel d0, sp@-
/*
* drop down into exit in case the user doesn't. This should drop
* control back to the ROM monitor, if there is one. This calls the
* exit() from the C library so the C++ tables get cleaned up right.
*/
jsr SYM (exit)
#ifndef FIDO_redboot
/* Define the interrupt vector table. The linker script
ensures that the table is placed at address zero. */
.section .vector_table,"a"
.global SYM (_vector_table)
SYM (_vector_table):
dc.l __stack /* 000 Initial Stack */
dc.l _start /* 001 Context 0 Start */
dc.l _BusErrorHandler /* 002 Bus Error */
dc.l _AddressErrorHandler /* 003 Address Error */
dc.l _IllegalInstructionHandler /* 004 Illegal Instruction */
dc.l _DivideByZeroHandler /* 005 Divide by Zero */
dc.l _ChkHandler /* 006 CHK, CHK2 Instructions */
dc.l _TrapccHandler /* 007 TRAPcc, TRAPV Instructions */
dc.l _PrivilegeViolationHandler /* 008 Privilege Violation */
dc.l _TraceHandler /* 009 Trace */
dc.l _ALineHandler /* 010 A-Line Unimplemented Instr */
dc.l _FLineHandler /* 011 F-Line Unimplemented Instr */
dc.l _HwBreakpointHandler /* 012 Hardware Breakpoint */
dc.l _Reserved0Handler /* 013 Reserved */
dc.l _FormatErrorHandler /* 014 Format Error */
dc.l _UnitializedIntHandler /* 015 Unitialized Interrupt */
dc.l _SoftwareIntHandler /* 016 Software Interrupt */
dc.l _Unassigned0Handler /* 017 Unassigned */
dc.l _Unassigned1Handler /* 018 Unassigned */
dc.l _Unassigned2Handler /* 019 Unassigned */
dc.l _Unassigned3Handler /* 020 Unassigned */
dc.l _Unassigned4Handler /* 021 Unassigned */
dc.l _Unassigned5Handler /* 022 Unassigned */
dc.l _Unassigned6Handler /* 023 Unassigned */
dc.l _Int0Handler /* 024 Interrupt 0 */
dc.l _Int1Handler /* 025 Interrupt 1 */
dc.l _Int2Handler /* 026 Interrupt 2 */
dc.l _Int3Handler /* 027 Interrupt 3 */
dc.l _Int4Handler /* 028 Interrupt 4 */
dc.l _Int5Handler /* 029 Interrupt 5 */
dc.l _Int6Handler /* 030 Interrupt 6 */
dc.l _Int7Handler /* 031 Interrupt 7 */
dc.l _Trap00Handler /* 032 Trap #00 Instruction */
dc.l _Trap01Handler /* 033 Trap #01 Instruction */
dc.l _Trap02Handler /* 034 Trap #02 Instruction */
dc.l _Trap03Handler /* 035 Trap #03 Instruction */
dc.l _Trap04Handler /* 036 Trap #04 Instruction */
dc.l _Trap05Handler /* 037 Trap #05 Instruction */
dc.l _Trap06Handler /* 038 Trap #06 Instruction */
dc.l _Trap07Handler /* 039 Trap #07 Instruction */
dc.l _Trap08Handler /* 040 Trap #08 Instruction */
dc.l _Trap09Handler /* 041 Trap #09 Instruction */
dc.l _Trap10Handler /* 042 Trap #10 Instruction */
dc.l _Trap11Handler /* 043 Trap #11 Instruction */
dc.l _Trap12Handler /* 044 Trap #12 Instruction */
dc.l _Trap13Handler /* 045 Trap #13 Instruction */
dc.l _Trap14Handler /* 046 Trap #14 Instruction */
dc.l _Trap15Handler /* 047 Trap #15 Instruction */
dc.l _Reserved048Handler /* 048 Reserved */
dc.l _Reserved049Handler /* 049 Reserved */
dc.l _Reserved050Handler /* 050 Reserved */
dc.l _Reserved051Handler /* 051 Reserved */
dc.l _Reserved052Handler /* 052 Reserved */
dc.l _Reserved053Handler /* 053 Reserved */
dc.l _Reserved054Handler /* 054 Reserved */
dc.l _Reserved055Handler /* 055 Reserved */
dc.l _Reserved056Handler /* 056 Reserved */
dc.l _Reserved057Handler /* 057 Reserved */
dc.l _Reserved058Handler /* 058 Reserved */
dc.l _Reserved059Handler /* 059 Reserved */
dc.l _Reserved060Handler /* 060 Reserved */
dc.l _Reserved061Handler /* 061 Reserved */
dc.l _Reserved062Handler /* 062 Reserved */
dc.l _Reserved063Handler /* 063 Reserved */
dc.l _ContextOvertimeHandler /* 064 Context Overtime */
dc.l _MpuErrorHandler /* 065 MPU Error */
dc.l _SystemTimer0Handler /* 066 System Timer 0 */
dc.l _SystemTimer1Handler /* 067 System Timer 1 */
dc.l _SystemTimer2Handler /* 068 System Timer 2 */
dc.l _SystemTimer3Handler /* 069 System Timer 3 */
dc.l _SystemTimer4Handler /* 070 System Timer 4 */
dc.l _WatchdogTimerHandler /* 071 Watchdog Timer */
dc.l _TimerCounter0Handler /* 072 Timer Counter 1 */
dc.l _TimerCounter1Handler /* 073 Timer Counter 2 */
dc.l _DMA0Handler /* 074 DMA Channel 0 */
dc.l _DMA1Handler /* 075 DMA Channel 1 */
dc.l _AtoDConversionHandler /* 076 A/D Conversion Complete */
dc.l _Pdma0Handler /* 077 PDMA Ch 0 Interrupt */
dc.l _Pdma1Handler /* 078 PDMA Ch 1 Interrupt */
dc.l _Pdma2Handler /* 079 PDMA Ch 2 Interrupt */
dc.l _Pdma3Handler /* 080 PDMA Ch 3 Interrupt */
dc.l _Reserved081Handler /* 081 Reserved */
dc.l _Reserved082Handler /* 082 Reserved */
dc.l _Reserved083Handler /* 083 Reserved */
dc.l _Reserved084Handler /* 084 Reserved */
dc.l _Reserved085Handler /* 085 Reserved */
dc.l _Reserved086Handler /* 086 Reserved */
dc.l _Reserved087Handler /* 087 Reserved */
dc.l _Reserved088Handler /* 088 Reserved */
dc.l _Reserved089Handler /* 089 Reserved */
dc.l _Reserved090Handler /* 090 Reserved */
dc.l _Reserved091Handler /* 091 Reserved */
dc.l _Reserved092Handler /* 092 Reserved */
dc.l _Reserved093Handler /* 093 Reserved */
dc.l _Reserved094Handler /* 094 Reserved */
dc.l _Reserved095Handler /* 095 Reserved */
dc.l _Trapx00Handler /* 096 Trapx 00 Instruction */
dc.l _Trapx01Handler /* 097 Trapx 01 Instruction */
dc.l _Trapx02Handler /* 098 Trapx 02 Instruction */
dc.l _Trapx03Handler /* 099 Trapx 03 Instruction */
dc.l _Trapx04Handler /* 100 Trapx 04 Instruction */
dc.l _Trapx05Handler /* 101 Trapx 05 Instruction */
dc.l _Trapx06Handler /* 102 Trapx 06 Instruction */
dc.l _Trapx07Handler /* 103 Trapx 07 Instruction */
dc.l _Trapx08Handler /* 104 Trapx 08 Instruction */
dc.l _Trapx09Handler /* 105 Trapx 09 Instruction */
dc.l _Trapx10Handler /* 106 Trapx 10 Instruction */
dc.l _Trapx11Handler /* 107 Trapx 11 Instruction */
dc.l _Trapx12Handler /* 108 Trapx 12 Instruction */
dc.l _Trapx13Handler /* 109 Trapx 13 Instruction */
dc.l _Trapx14Handler /* 110 Trapx 14 Instruction */
dc.l _Trapx15Handler /* 111 Trapx 15 Instruction */
dc.l _DummyHandler /* 112 */
dc.l _DummyHandler /* 113 */
dc.l _DummyHandler /* 114 */
dc.l _DummyHandler /* 115 */
dc.l _DummyHandler /* 116 */
dc.l _DummyHandler /* 117 */
dc.l _DummyHandler /* 118 */
dc.l _DummyHandler /* 119 */
dc.l _DummyHandler /* 120 */
dc.l _DummyHandler /* 121 */
dc.l _DummyHandler /* 122 */
dc.l _DummyHandler /* 123 */
dc.l _DummyHandler /* 124 */
dc.l _DummyHandler /* 125 */
dc.l _DummyHandler /* 126 */
dc.l _DummyHandler /* 127 */
dc.l _DummyHandler /* 128 */
dc.l _DummyHandler /* 129 */
dc.l _DummyHandler /* 130 */
dc.l _DummyHandler /* 131 */
dc.l _DummyHandler /* 132 */
dc.l _DummyHandler /* 133 */
dc.l _DummyHandler /* 134 */
dc.l _DummyHandler /* 135 */
dc.l _DummyHandler /* 136 */
dc.l _DummyHandler /* 137 */
dc.l _DummyHandler /* 138 */
dc.l _DummyHandler /* 139 */
dc.l _DummyHandler /* 140 */
dc.l _DummyHandler /* 141 */
dc.l _DummyHandler /* 142 */
dc.l _DummyHandler /* 143 */
dc.l _DummyHandler /* 144 */
dc.l _DummyHandler /* 145 */
dc.l _DummyHandler /* 146 */
dc.l _DummyHandler /* 147 */
dc.l _DummyHandler /* 148 */
dc.l _DummyHandler /* 149 */
dc.l _DummyHandler /* 150 */
dc.l _DummyHandler /* 151 */
dc.l _DummyHandler /* 152 */
dc.l _DummyHandler /* 153 */
dc.l _DummyHandler /* 154 */
dc.l _DummyHandler /* 155 */
dc.l _DummyHandler /* 156 */
dc.l _DummyHandler /* 157 */
dc.l _DummyHandler /* 158 */
dc.l _DummyHandler /* 159 */
dc.l _DummyHandler /* 160 */
dc.l _DummyHandler /* 161 */
dc.l _DummyHandler /* 162 */
dc.l _DummyHandler /* 163 */
dc.l _DummyHandler /* 164 */
dc.l _DummyHandler /* 165 */
dc.l _DummyHandler /* 166 */
dc.l _DummyHandler /* 167 */
dc.l _DummyHandler /* 168 */
dc.l _DummyHandler /* 169 */
dc.l _DummyHandler /* 170 */
dc.l _DummyHandler /* 171 */
dc.l _DummyHandler /* 172 */
dc.l _DummyHandler /* 173 */
dc.l _DummyHandler /* 174 */
dc.l _DummyHandler /* 175 */
dc.l _DummyHandler /* 176 */
dc.l _DummyHandler /* 177 */
dc.l _DummyHandler /* 178 */
dc.l _DummyHandler /* 179 */
dc.l _DummyHandler /* 180 */
dc.l _DummyHandler /* 181 */
dc.l _DummyHandler /* 182 */
dc.l _DummyHandler /* 183 */
dc.l _DummyHandler /* 184 */
dc.l _DummyHandler /* 185 */
dc.l _DummyHandler /* 186 */
dc.l _DummyHandler /* 187 */
dc.l _DummyHandler /* 188 */
dc.l _DummyHandler /* 189 */
dc.l _DummyHandler /* 190 */
dc.l _DummyHandler /* 191 */
dc.l _DummyHandler /* 192 */
dc.l _DummyHandler /* 193 */
dc.l _DummyHandler /* 194 */
dc.l _DummyHandler /* 195 */
dc.l _DummyHandler /* 196 */
dc.l _DummyHandler /* 197 */
dc.l _DummyHandler /* 198 */
dc.l _DummyHandler /* 199 */
dc.l _DummyHandler /* 200 */
dc.l _DummyHandler /* 201 */
dc.l _DummyHandler /* 202 */
dc.l _DummyHandler /* 203 */
dc.l _DummyHandler /* 204 */
dc.l _DummyHandler /* 205 */
dc.l _DummyHandler /* 206 */
dc.l _DummyHandler /* 207 */
dc.l _DummyHandler /* 208 */
dc.l _DummyHandler /* 209 */
dc.l _DummyHandler /* 210 */
dc.l _DummyHandler /* 211 */
dc.l _DummyHandler /* 212 */
dc.l _DummyHandler /* 213 */
dc.l _DummyHandler /* 214 */
dc.l _DummyHandler /* 215 */
dc.l _DummyHandler /* 216 */
dc.l _DummyHandler /* 217 */
dc.l _DummyHandler /* 218 */
dc.l _DummyHandler /* 219 */
dc.l _DummyHandler /* 220 */
dc.l _DummyHandler /* 221 */
dc.l _DummyHandler /* 222 */
dc.l _DummyHandler /* 223 */
dc.l _DummyHandler /* 224 */
dc.l _DummyHandler /* 225 */
dc.l _DummyHandler /* 226 */
dc.l _DummyHandler /* 227 */
dc.l _DummyHandler /* 228 */
dc.l _DummyHandler /* 229 */
dc.l _DummyHandler /* 230 */
dc.l _DummyHandler /* 231 */
dc.l _DummyHandler /* 232 */
dc.l _DummyHandler /* 233 */
dc.l _DummyHandler /* 234 */
dc.l _DummyHandler /* 235 */
dc.l _DummyHandler /* 236 */
dc.l _DummyHandler /* 237 */
dc.l _DummyHandler /* 238 */
dc.l _DummyHandler /* 239 */
dc.l _DummyHandler /* 240 */
dc.l _DummyHandler /* 241 */
dc.l _DummyHandler /* 242 */
dc.l _DummyHandler /* 243 */
dc.l _DummyHandler /* 244 */
dc.l _DummyHandler /* 245 */
dc.l _DummyHandler /* 246 */
dc.l _DummyHandler /* 247 */
dc.l _DummyHandler /* 248 */
dc.l _DummyHandler /* 249 */
dc.l _DummyHandler /* 250 */
dc.l _DummyHandler /* 251 */
dc.l _DummyHandler /* 252 */
dc.l _DummyHandler /* 253 */
dc.l _DummyHandler /* 254 */
dc.l _DummyHandler /* 255 */
/*
* Define weak symbols for four alternate interrupt vectors.
* These will be used as the interrupt vectors for the four
* secondary contexts.
*/
.section .data
.global SYM (_vector_table1)
.weak SYM (_vector_table1)
.set SYM (_vector_table1), SYM (_vector_table)
.global SYM (_vector_table2)
.weak SYM (_vector_table2)
.set SYM (_vector_table2), SYM (_vector_table)
.global SYM (_vector_table3)
.weak SYM (_vector_table3)
.set SYM (_vector_table3), SYM (_vector_table)
.global SYM (_vector_table4)
.weak SYM (_vector_table4)
.set SYM (_vector_table4), SYM (_vector_table)
#endif
|
32bitmicro/newlib-nano-1.0
| 1,570
|
libgloss/m68k/cf-crt0.S
|
/* Initial boot
*
* Copyright (c) 2006 CodeSourcery Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
.text
.extern __stack
.extern __heap_end
.weak __heap_end
.extern __start1
/* __reset should cause a HALT in a hosted executable and
fall into __start for an unhosted executable. The user is
free to override this with their own declaration. */
.globl __reset
.weak __reset
__reset:
#if HOSTED
HALT
#endif
.globl __start
__start:
/* Initialize stack */
move.l IMM(__stack), sp
move.l IMM(0), fp
move.l IMM(__heap_end), d1
#if HOSTED
/* INIT_SIM syscall. Allows changing sp & d1. */
move.l IMM(1),d0
/* The semihosting sequence is 'nop; halt;sentinel' aligned to
a 4 byte boundary. The sentinel is an ill formed instruction
(movec %sp,0). The debugger will adjust the pc, so it is never
executed. */
.balignw 4,0x4e71
nop
halt
.long 0x4e7bf000
#endif
move.l d1,sp@-
move.l fp,sp@- /* Dummy return address */
jmp __start1
|
32bitmicro/newlib-nano-1.0
| 1,167
|
libgloss/m68k/cf-hosted.S
|
/*
* cf-hosted.S --
*
* Copyright (c) 2006 CodeSourcery Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* Semihosting function. The debugger intercepts the halt, and
determines that it is followed by the sentinel pattern. */
.globl __hosted
__hosted:
linkw %fp,#0
movel %fp@(8),%d0
movel %fp@(12),%d1
/* The semihosting sequence is 'nop; halt;sentinel' aligned to
a 4 byte boundary. The sentinel is an ill formed instruction
(movec %sp,0). The debugger will adjust the pc, so it is never
executed. */
.balignw 4,0x4e71
nop
halt
.long 0x4e7bf000
unlk %fp
rts
|
32bitmicro/newlib-nano-1.0
| 3,363
|
libgloss/m68k/mvme.S
|
/* mvme.S -- board support for m68k
*
* Copyright (c) 1995, 1996 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
.title "mvme.S for m68k-coff"
.align 2
.text
.global SYM (_exit)
.global SYM (outln)
.global SYM (outbyte)
.global SYM (putDebugChar)
.global SYM (inbyte)
.global SYM (getDebugChar)
.global SYM (havebyte)
.global SYM (exceptionHandler)
.set vbr_size, 0x400
.comm SYM (vbr_table), vbr_size
/*
* _exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run.
*/
SYM (_exit):
unlk a6
trap IMM(15)
.word return
.align 2
/*
* inbyte -- get a byte from the serial port
* d0 - contains the byte read in
*/
.align 2
SYM (getDebugChar): /* symbol name used by m68k-stub */
SYM (inbyte):
link a6, IMM(-8)
trap IMM(15)
.word inchr
moveb sp@, d0
extw d0
extl d0
unlk a6
rts
/*
* outbyte -- sends a byte out the serial port
* d0 - contains the byte to be sent
*/
.align 2
SYM (putDebugChar): /* symbol name used by m68k-stub */
SYM (outbyte):
link fp, IMM(-4)
moveb fp@(11), sp@
trap IMM(15)
.word outchr
unlk fp
rts
/*
* outln -- sends a string of bytes out the serial port with a CR/LF
* a0 - contains the address of the string's first byte
* a1 - contains the address of the string's last byte
*/
.align 2
SYM (outln):
link a6, IMM(-8)
moveml a0/a1, sp@
trap IMM(15)
.word outln
unlk a6
rts
/*
* outstr -- sends a string of bytes out the serial port without a CR/LF
* a0 - contains the address of the string's first byte
* a1 - contains the address of the string's last byte
*/
.align 2
SYM (outstr):
link a6, IMM(-8)
moveml a0/a1, sp@
trap IMM(15)
.word outstr
unlk a6
rts
/*
* havebyte -- checks to see if there is a byte in the serial port,
* returns 1 if there is a byte, 0 otherwise.
*/
SYM (havebyte):
trap IMM(15)
.word instat
beqs empty
movel IMM(1), d0
rts
empty:
movel IMM(0), d0
rts
/*
* These constants are for the MVME-135 board's boot monitor. They
* are used with a TRAP 15 call to access the monitor's I/O routines.
* they must be in the word following the trap call.
*/
.set inchr, 0x0
.set instat, 0x1
.set inln, 0x2
.set readstr, 0x3
.set readln, 0x4
.set chkbrk, 0x5
.set outchr, 0x20
.set outstr, 0x21
.set outln, 0x22
.set write, 0x23
.set writeln, 0x24
.set writdln, 0x25
.set pcrlf, 0x26
.set eraseln, 0x27
.set writd, 0x28
.set sndbrk, 0x29
.set tm_ini, 0x40
.set dt_ini, 0x42
.set tm_disp, 0x43
.set tm_rd, 0x44
.set redir, 0x60
.set redir_i, 0x61
.set redir_o, 0x62
.set return, 0x63
.set bindec, 0x64
.set changev, 0x67
.set strcmp, 0x68
.set mulu32, 0x69
.set divu32, 0x6A
.set chk_sum, 0x6B
|
32bitmicro/newlib-nano-1.0
| 3,367
|
libgloss/m68k/crt0.S
|
/*
* crt0.S -- startup file for m68k-coff
*
* Copyright (c) 1995, 1996, 1998 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
.title "crt0.S for m68k-coff"
#define STACKSIZE 0x4000
/*
* Define an empty environment.
*/
.data
.align 2
SYM (environ):
.long 0
.align 2
.text
/*
* These symbols are defined in C code, so they need to always be
* named with SYM because of the difference between object file formats.
*/
/* These are defined in C code. */
.extern SYM (main)
.extern SYM (exit)
.extern SYM (hardware_init_hook)
.extern SYM (software_init_hook)
.extern SYM (atexit)
.extern SYM(__do_global_dtors)
/*
* These values are set in the linker script, so they must be
* explicitly named here without SYM.
*/
.extern __stack
.extern __bss_start
.extern _end
/*
* Set things up so the application will run. For historical reasons
* this is called 'start'. We set things up to provide '_start'
* as with other systems, but also provide a weak alias called
* 'start' for compatibility with existing linker scripts.
*/
.global SYM (start)
.weak SYM (start)
.set SYM (start),SYM(_start)
.global SYM (_start)
SYM (_start):
/*
* put any hardware init code here
*/
/* See if user supplied their own stack (__stack != 0). If not, then
* default to using the value of %sp as set by the ROM monitor.
*/
movel IMM(__stack), a0
cmpl IMM(0), a0
jbeq 1f
movel a0, sp
1:
/* set up initial stack frame */
link a6, IMM(-8)
/*
* zero out the bss section.
*/
movel IMM(__bss_start), d1
movel IMM(_end), d0
cmpl d0, d1
jbeq 3f
movl d1, a0
subl d1, d0
subql IMM(1), d0
2:
clrb (a0)+
#if !defined(__mcoldfire__)
dbra d0, 2b
clrw d0
subql IMM(1), d0
jbcc 2b
#else
subql IMM(1), d0
jbpl 2b
#endif
3:
/*
* initialize target specific stuff. Only execute these
* functions it they exist.
*/
PICLEA SYM (hardware_init_hook), a0
cmpl IMM(0),a0
jbeq 4f
jsr (a0)
4:
PICLEA SYM (software_init_hook), a0
cmpl IMM(0),a0
jbeq 5f
jsr (a0)
5:
/*
* call the main routine from the application to get it going.
* main (argc, argv, environ)
* we pass argv as a pointer to NULL.
*/
#ifdef ADD_DTORS
/* put __do_global_dtors in the atexit list so the destructors get run */
movel IMM (SYM(__do_global_dtors)),(sp)
PICCALL SYM (atexit)
#endif
movel IMM (__FINI_SECTION__),(sp)
PICCALL SYM (atexit)
PICCALL __INIT_SECTION__
pea 0
PICPEA SYM (environ),a0
pea sp@(4)
pea 0
PICCALL SYM (main)
movel d0, sp@-
/*
* drop down into exit incase the user doesn't. This should drop
* control back to the ROM monitor, if there is one. This calls the
* exit() from the C library so the C++ tables get cleaned up right.
*/
PICCALL SYM (exit)
|
32bitmicro/newlib-nano-1.0
| 10,693
|
libgloss/m68k/mvme162lx-asm.S
|
/*
* mvme162lx-asm.S -- assembler routines for the MVME stub.
*
* This code was pulled out of mvme162lx-stub.c by Ian Taylor so that I
* could handle different register and label prefixes in a sensible
* way.
*/
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
#include "asm.h"
.title "mvme162lx-asm.S for m68k"
.globl SYM (registers)
.globl SYM (lastFrame)
.globl SYM (superStack)
.globl SYM (exceptionHook)
.globl SYM (_returnFromException)
.globl SYM (stackPtr)
.globl SYM (handle_exception)
.globl SYM (exceptionSize)
.text
.globl SYM (return_to_super)
SYM (return_to_super):
movel SYM (registers)+60,sp /* get new stack pointer */
movel SYM (lastFrame),a0 /* get last frame info */
bra return_to_any
.globl SYM (return_to_user)
SYM (return_to_user):
movel SYM (registers)+60,a0 /* get usp */
movel a0,usp /* set usp */
movel SYM (superStack),sp /* get original stack pointer */
return_to_any:
movel SYM (lastFrame),a0 /* get last frame info */
movel a0@+,SYM (lastFrame) /* link in previous frame */
addql IMM (8),a0 /* skip over pc, vector#*/
movew a0@+,d0 /* get # of words in cpu frame */
addw d0,a0 /* point to end of data */
addw d0,a0 /* point to end of data */
movel a0,a1
/* copy the stack frame */
subql IMM (1),d0
copyUserLoop:
movew a1@-,sp@-
dbf d0,copyUserLoop
#ifdef __HAVE_68881__
fmoveml SYM (registers)+168,fpcr/fpsr/fpi
fmovemx SYM (registers)+72,fp0-fp7
cmpl IMM (-1),a0@ /* skip frestore flag set ? */
beq skip_frestore
frestore a0@+
skip_frestore:
#endif
moveml SYM (registers),d0-d7/a0-a6
rte /* pop and go! */
/* this function is called immediately when a level 7 interrupt occurs */
/* if the previous interrupt level was 7 then we're already servicing */
/* this interrupt and an rte is in order to return to the debugger. */
/* For the 68000, the offset for sr is 6 due to the jsr return address */
.text
.globl SYM (_debug_level7)
SYM (_debug_level7):
movew d0,sp@-
#ifdef mc68020
movew sp@(2),d0
#else
movew sp@(6),d0
#endif
andiw IMM (0x700),d0
cmpiw IMM (0x700),d0
beq _already7
movew sp@+,d0
bra SYM (_catchException)
_already7:
movew sp@+,d0
#ifndef mc68020
lea sp@(4),sp /* pull off 68000 return address */
#endif
rte
#ifdef mc68020
/* This function is called when a 68020 exception occurs. It saves
* all the cpu and fpcp regs in the _registers array, creates a frame on a
* linked list of frames which has the cpu and fpcp stack frames needed
* to properly restore the context of these processors, and invokes
* an exception handler (remcom_handler).
*
* stack on entry: stack on exit:
* N bytes of junk exception # MSWord
* Exception Format Word exception # MSWord
* Program counter LSWord
* Program counter MSWord
* Status Register
*
*
*/
.text
.globl SYM (_catchException)
SYM (_catchException):
oriw IMM (0x0700),sr /* Disable interrupts */
moveml d0-d7/a0-a6,SYM (registers) /* save registers */
movel SYM (lastFrame),a0 /* last frame pointer */
#ifdef __HAVE_68881__
/* do an fsave, then remember the address to begin a restore from */
fsave a0@-
fmovemx fp0-fp7, SYM (registers)+72
fmoveml fpcr/fpsr/fpi, SYM (registers)+168
#endif
lea SYM (registers),a5 /* get address of registers */
movew sp@,d1 /* get status register */
movew d1,a5@(66) /* save sr */
movel sp@(2),a4 /* save pc in a4 for later use */
movel a4,a5@(68) /* save pc in _regisers[] */
/* figure out how many bytes in the stack frame */
movew sp@(6),d0 /* get '020 exception format */
movew d0,d2 /* make a copy of format word */
andiw IMM (0xf000),d0 /* mask off format type */
rolw IMM (5),d0 /* rotate into the low byte *2 */
lea SYM (exceptionSize),a1
addw d0,a1 /* index into the table */
movew a1@,d0 /* get number of words in frame */
movew d0,d3 /* save it */
subw d0,a0 /* adjust save pointer */
subw d0,a0 /* adjust save pointer(bytes) */
movel a0,a1 /* copy save pointer */
subql IMM (1),d0 /* predecrement loop counter */
/* copy the frame */
saveFrameLoop:
movew sp@+,a1@+
dbf d0,saveFrameLoop
/* now that the stack has been clenaed,
* save the a7 in use at time of exception
*/
movel sp,SYM (superStack) /* save supervisor sp */
andiw IMM (0x2000),d1 /* were we in supervisor mode ? */
beq userMode
movel a7,a5@(60) /* save a7 */
bra a7saveDone
userMode:
movel usp,a1
movel a1,a5@(60) /* save user stack pointer */
a7saveDone:
/* save size of frame */
movew d3,a0@-
/* compute exception number */
andl IMM (0xfff),d2 /* mask off vector offset */
lsrw IMM (2),d2 /* divide by 4 to get vect num */
movel d2,a0@- /* save it */
/* save pc causing exception */
movel a4,a0@-
/* save old frame link and set the new value*/
movel SYM (lastFrame),a1 /* last frame pointer */
movel a1,a0@- /* save pointer to prev frame */
movel a0,SYM (lastFrame)
movel d2,sp@- /* push exception num */
#ifdef TMP_HACK
movel SYM (exceptionHook),a0 /* get address of handler */
jbsr a0@ /* and call it */
#else
jbsr SYM (remcomHandler)
#endif
clrl sp@ /* replace exception num parm with frame ptr */
jbsr SYM (_returnFromException) /* jbsr, but never returns */
#else /* mc68000 */
/* This function is called when an exception occurs. It translates the
* return address found on the stack into an exception vector # which
* is then handled by either handle_exception or a system handler.
* _catchException provides a front end for both.
*
* stack on entry: stack on exit:
* Program counter MSWord exception # MSWord
* Program counter LSWord exception # MSWord
* Status Register
* Return Address MSWord
* Return Address LSWord
*/
.text
.globl SYM (_catchException)
SYM (_catchException):
oriw IMM (0x0700),sr /* Disable interrupts */
moveml d0-d7/a0-a6,SYM (registers) /* save registers */
movel SYM (lastFrame),a0 /* last frame pointer */
#ifdef __HAVE_68881__
/* do an fsave, then remember the address to begin a restore from */
fsave a0@-
fmovemx fp0-fp7, SYM (registers)+72
fmoveml fpcr/fpsr/fpi, SYM (registers)+168
#endif
lea SYM (registers),a5 /* get address of registers */
movel sp@+,d2 /* pop return address */
addl IMM (1530),d2 /* convert return addr to */
divs IMM (6),d2 /* exception number */
extl d2
moveql IMM (3),d3 /* assume a three word frame */
cmpiw IMM (3),d2 /* bus error or address error ? */
bgt normal /* if >3 then normal error */
movel sp@+,a0@- /* copy error info to frame buff*/
movel sp@+,a0@- /* these are never used */
moveql IMM (7),d3 /* this is a 7 word frame */
normal:
movew sp@+,d1 /* pop status register */
movel sp@+,a4 /* pop program counter */
movew d1,a5@(66) /* save sr */
movel a4,a5@(68) /* save pc in _regisers[] */
movel a4,a0@- /* copy pc to frame buffer */
movew d1,a0@- /* copy sr to frame buffer */
movel sp,SYM (superStack) /* save supervisor sp */
andiw IMM (0x2000),d1 /* were we in supervisor mode ? */
beq userMode
movel a7,a5@(60) /* save a7 */
bra saveDone
userMode:
movel usp,a1 /* save user stack pointer */
movel a1,a5@(60) /* save user stack pointer */
saveDone:
movew d3,a0@- /* push frame size in words */
movel d2,a0@- /* push vector number */
movel a4,a0@- /* push exception pc */
/* save old frame link and set the new value */
movel SYM (lastFrame),a1 /* last frame pointer */
movel a1,a0@- /* save pointer to prev frame */
movel a0,SYM (lastFrame)
movel d2,sp@- /* push exception num */
movel SYM (exceptionHook),a0 /* get address of handler */
jbsr a0@ /* and call it */
clrl sp@ /* replace exception num parm with frame ptr */
jbsr SYM (_returnFromException) /* jbsr, but never returns */
#endif /* m68000 */
/*
* remcomHandler is a front end for handle_exception. It moves the
* stack pointer into an area reserved for debugger use in case the
* breakpoint happened in supervisor mode.
*/
.globl SYM (remcomHandler)
SYM (remcomHandler):
addl IMM (4),sp /* pop off return address */
movel sp@+,d0 /* get the exception number */
movel SYM (stackPtr),sp /* move to remcom stack area */
movel d0,sp@- /* push exception onto stack */
jbsr SYM (handle_exception) /* this never returns */
rts /* return */
|
32bitmicro/newlib-nano-1.0
| 2,903
|
libgloss/mt/crt0-16-002.S
|
; crt0_2.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
; Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
;
; The authors hereby grant permission to use, copy, modify, distribute,
; and license this software and its documentation for any purpose, provided
; that existing copyright notices are retained in all copies and that this
; notice is included verbatim in any distributions. No written agreement,
; license, or royalty fee is required for any of the authorized uses.
; Modifications to this software may be copyrighted by their authors
; and need not follow the licensing terms described here, provided that
; the new terms are clearly indicated on the first page of each file where
; they apply.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
|
32bitmicro/newlib-nano-1.0
| 2,903
|
libgloss/mt/crt0-16-003.S
|
; crt0.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
;
; Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
;
; The authors hereby grant permission to use, copy, modify, distribute,
; and license this software and its documentation for any purpose, provided
; that existing copyright notices are retained in all copies and that this
; notice is included verbatim in any distributions. No written agreement,
; license, or royalty fee is required for any of the authorized uses.
; Modifications to this software may be copyrighted by their authors
; and need not follow the licensing terms described here, provided that
; the new terms are clearly indicated on the first page of each file where
; they apply.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
|
32bitmicro/newlib-nano-1.0
| 2,798
|
libgloss/mt/crt0-ms2.S
|
; crt0.s - Startup code for the ms2. This code initializes the C
; run-time model.
;
;
; Copyright 2001, 2002, 2003, 2004 Morpho Technologies
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Copy data from ROM to SRAM (another on-chip memory)
ldui r9, #%hi16(_sram_data_start)
ori r9, r9, #%lo16(_sram_data_start)
ldui r10, #%hi16(_sram_data_end)
ori r10, r10, #%lo16(_sram_data_end)
ldui r11, #%hi16(_sram_data_vma)
brle r10, r9, .Lnext4
ori r11, r11, #%lo16(_sram_data_vma)
.Lcpy3:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy3
addi r11, r11, #$4
.Lnext4:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
or r0, r0, r0 ; nop, added 06Sep05
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
or r0, r0, r0 ; nop, added 06Sep05
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
or r0, r0, r0 ; nop, added 06Sep05
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
|
32bitmicro/newlib-nano-1.0
| 9,095
|
libgloss/mt/startup-64-001.S
|
/*
* $Header: /cvs/src/src/libgloss/mt/startup-64-001.S,v 1.1 2005/12/12 11:16:41 nathan Exp $
*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
*
* 26Sep01 (DJK) The memory map is changed and the device interrupts are
* now memory-mapped.
*
* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
* space is now reserved for memory-mapped I/O devices.
* (There is over 2K unused, reserved space in this area.)
*
* 27Jul02 (DJK) Fixed the address for the interrupt mask register. Old
* documentation stated the port address as 0x140, but
* the implementation uses 0x13c.
*
* 30Jul02 (DJK) Added support for printf. This only supports output to
* stderr and stdout. Using the message box interface,
* a (newly defined) message or series of messages is
* passed to the controller to output bytes as text to
* the debug console. These messages are constructed in
* the interrupt handler for the SI instruction.
* With this implementation, the user is unable to
* utilize the message box interface in applications as
* specialized interrupt handlers for the external
* interrupts are necessary.
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
*
*/
.section .startup, "a", @progbits
.global __boot_start
_INTERRUPT_VECTOR_TABLE:
__boot_start:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
.org 0x100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
; 60 bytes minus eight registers (four bytes per register)
.fill (60 - 8 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
; 256 bytes minus sixteen registers (four bytes per register)
.fill (256 - 16 * 4)
.org 0x200
; MorphoSys Decoder Registers
.global _MS_DEC_AUTO_INCREMENT_REG
_MS_DEC_AUTO_INCREMENT_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERMUTATION_REG
_MS_DEC_CUSTOM_PERMUTATION_REG:
.word 0x00000000
.global _MS_DEC_CONTEXT_BASE_REG
_MS_DEC_CONTEXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TABLE_BASE_REG
_MS_DEC_LOOKUP_TABLE_BASE_REG:
.word 0x00000000
.global _MS_CIRCULAR_BUFFER_END_REG
_MS_CIRCULAR_BUFFER_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRCULAR_BUFFER_SIZE_REG
_MS_CIRCULAR_BUFFER_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLOCK_END_REG
_MS_DATA_BLOCK_END_REG:
.word 0x00000000
.global _MS_DATA_BLOCK_SIZE_REG
_MS_DATA_BLOCK_SIZE_REG:
.word 0x00000000
; 256 bytes minus nine registers (four bytes per register)
.fill (256 - 9 * 4)
.org 0x300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED0_REG
_DEBUG_HW_RESERVED0_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED1_REG
_DEBUG_HW_RESERVED1_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED2_REG
_DEBUG_HW_RESERVED2_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED3_REG
_DEBUG_HW_RESERVED3_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED4_REG
_DEBUG_HW_RESERVED4_REG:
.word 0x00000000
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
.org 0x400
; Sequence Generator Registers
_SEQ_GEN_REGS:
.fill 256
.org 0x500
_RESERVED_SEQ_GEN_REGS:
.fill 256
.org 0x600
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER0_CTRL_REG
_TIMER0_CTRL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER1_CTRL_REG
_TIMER1_CTRL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER2_CTRL_REG
_TIMER2_CTRL_REG:
.word 0x00000000
; 256 bytes minus six registers (four bytes per register)
.fill (256 - 6 * 4)
.org 0x700
.global _OUTPUT0_CONTROL
_OUTPUT0_CONTROL:
.word 0x00000000
.global _OUTPUT1_CONTROL
_OUTPUT1_CONTROL:
.word 0x00000000
.global _OUTPUT2_CONTROL
_OUTPUT2_CONTROL:
.word 0x00000000
.global _OUTPUT3_CONTROL
_OUTPUT3_CONTROL:
.word 0x00000000
.global _OUTPUT4_CONTROL
_OUTPUT4_CONTROL:
.word 0x00000000
.global _OUTPUT5_CONTROL
_OUTPUT5_CONTROL:
.word 0x00000000
.global _OUTPUT6_CONTROL
_OUTPUT6_CONTROL:
.word 0x00000000
.global _OUTPUT7_CONTROL
_OUTPUT7_CONTROL:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
.org 0x800
; Reserved memory-mapped space.
.fill (0x1000 - 0x800)
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
; for devices zero through seven.
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed, a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x31C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
;
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
; SYS_call is handled by simulator here...
or r0, r0, r0
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
ldw r10, sp, #$0
subi r15, r15, #$4 ; Backup to address of break
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
|
32bitmicro/newlib-nano-1.0
| 17,327
|
libgloss/mt/startup-ms2.S
|
/*
*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
* 28Apr05 (DJK) Added support for the overflow vector.
*
* XXXXXXX (DJK) Modified for the MS2 target
*
* 09Jan04 (DJK) Modified internal I/O port definitions for the
* MS1-16-003.
*
* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
* space is now reserved for memory-mapped I/O devices.
* (There is over 2K unused, reserved space in this area.)
*
* 26Sep01 (DJK) The memory map is changed and the device interrupts are
* now memory-mapped.
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
*
*/
.section .startup, "a", @progbits
.global __boot_start
__boot_start:
_INTERRUPT_VECTOR_TABLE:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0, r0, r0
jmp _BRKIVEC ; Vector for Break instruction
or r0, r0, r0
; The illegal instruction trap is not implemented.
_RESERVED1_IVEC:
jmp _RESERVED1_IVEC
or r0, r0, r0
jmp _OVFIVEC
or r0, r0, r0
_RESERVED2_IVEC:
jmp _RESERVED2_IVEC
or r0, r0, r0
_RESERVED3_IVEC:
jmp _RESERVED3_IVEC
or r0, r0, r0
_RESERVED4_IVEC:
jmp _RESERVED4_IVEC
or r0, r0, r0
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
; Statically initialized data must be copied from ROM to RAM.
; This is done in the C run-time start-up code (crt0.o).
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x00031C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
; SYS_call is handled by simulator here...
or r0, r0, r0
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
ldw r10, sp, #$0
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
.global _OVFIVEC
_OVFIVEC:
addi r15, r15, #$4
or r0, r0, r0
or r0, r0, r0 ; added 06Sep05
reti r15
or r0, r0, r0
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
.section .internal_io, "a", @nobits
.fill 256 ; Fill the first page.
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
;.org 0xfffff100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_REG
_DEV8_INTERRUPT_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_REG
_DEV9_INTERRUPT_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_REG
_DEV10_INTERRUPT_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_REG
_DEV11_INTERRUPT_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_REG
_DEV12_INTERRUPT_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_REG
_DEV13_INTERRUPT_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_REG
_DEV14_INTERRUPT_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_REG
_DEV15_INTERRUPT_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_REG
_DEV16_INTERRUPT_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_REG
_DEV17_INTERRUPT_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_REG
_DEV18_INTERRUPT_REG:
.word 0x00000000
; 128 bytes minus nineteen registers (four bytes per register)
.fill (128 - 19 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
.global _INTERRUPT_PENDING_REG
_INTERRUPT_PENDING_REG:
.word 0x00000000
; 16 bytes minus two registers (four bytes per register)
.fill (16 - 2 * 4)
.global _DEV0_INTERRUPT_LEVEL_REG
_DEV0_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_LEVEL_REG
_DEV1_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_LEVEL_REG
_DEV2_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_LEVEL_REG
_DEV3_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_LEVEL_REG
_DEV4_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_LEVEL_REG
_DEV5_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_LEVEL_REG
_DEV6_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_LEVEL_REG
_DEV7_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_LEVEL_REG
_DEV8_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_LEVEL_REG
_DEV9_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_LEVEL_REG
_DEV10_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_LEVEL_REG
_DEV11_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_LEVEL_REG
_DEV12_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_LEVEL_REG
_DEV13_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_LEVEL_REG
_DEV14_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_LEVEL_REG
_DEV15_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_LEVEL_REG
_DEV16_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_LEVEL_REG
_DEV17_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_LEVEL_REG
_DEV18_INTERRUPT_LEVEL_REG:
.word 0x00000000
; 128 bytes minus twenty-three registers (four bytes per register)
.fill (128 - 23 * 4)
;.org 0xfffff200
; MorphoSys Decoder Registers
.global _MS_DEC_CIRC_BUFF_SEL_REG
_MS_DEC_CIRC_BUFF_SEL_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERM_REG
_MS_DEC_CUSTOM_PERM_REG:
.word 0x00000000
.global _MS_DEC_CTXT_BASE_REG
_MS_DEC_CTXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TBL_REG
_MS_DEC_LOOKUP_TBL_REG:
.word 0x00000000
.global _MS_CIRC_BUFF0_I_REG
_MS_CIRC_BUFF0_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF0_P_REG
_MS_CIRC_BUFF0_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF0_B_REG
_MS_DATA_BUFF0_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF0_S_REG
_MS_DATA_BUFF0_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF1_I_REG
_MS_CIRC_BUFF1_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF1_P_REG
_MS_CIRC_BUFF1_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF1_B_REG
_MS_DATA_BUFF1_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF1_S_REG
_MS_DATA_BUFF1_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF2_I_REG
_MS_CIRC_BUFF2_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF2_P_REG
_MS_CIRC_BUFF2_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF2_B_REG
_MS_DATA_BUFF2_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF2_S_REG
_MS_DATA_BUFF2_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF3_I_REG
_MS_CIRC_BUFF3_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF3_P_REG
_MS_CIRC_BUFF3_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF3_B_REG
_MS_DATA_BUFF3_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF3_S_REG
_MS_DATA_BUFF3_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF4_I_REG
_MS_CIRC_BUFF4_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF4_P_REG
_MS_CIRC_BUFF4_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF4_B_REG
_MS_DATA_BUFF4_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF4_S_REG
_MS_DATA_BUFF4_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF5_I_REG
_MS_CIRC_BUFF5_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF5_P_REG
_MS_CIRC_BUFF5_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF5_B_REG
_MS_DATA_BUFF5_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF5_S_REG
_MS_DATA_BUFF5_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF6_I_REG
_MS_CIRC_BUFF6_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF6_P_REG
_MS_CIRC_BUFF6_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF6_B_REG
_MS_DATA_BUFF6_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF6_S_REG
_MS_DATA_BUFF6_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF7_I_REG
_MS_CIRC_BUFF7_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF7_P_REG
_MS_CIRC_BUFF7_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF7_B_REG
_MS_DATA_BUFF7_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF7_S_REG
_MS_DATA_BUFF7_S_REG:
.word 0x00000000
.global _MS_OMEGA_PERM1_REG
_MS_OMEGA_PERM1_REG:
.word 0x00000000
.global _MS_WRITE_FB_ADDR_REG
_MS_WRITE_FB_ADDR_REG:
.word 0x00000000
.global _MS_OMEGA_PERM2_REG
_MS_OMEGA_PERM2_REG:
.word 0x00000000
; 256 bytes minus forty registers (four bytes per register)
.fill (256 - 40 * 4)
;.org 0xfffff300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
.global _DEBUG_CRITICAL_REG
_DEBUG_OWNERSHIP_REG:
.word 0x00000000
.global _DEBUG_KERNEL_ID_REG
_DEBUG_KERNEL_ID_REG:
.word 0x00000000
.global _DEBUG_IRQ_STATUS_REG
_DEBUG_IRQ_STATUS_REG:
.word 0x00000000
; There are two reserved registers.
.fill (2 * 4)
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 128 bytes minus eight registers (four bytes per register)
.fill (128 - 8 * 4)
.global _EXTENDED_GP0_REG
_EXTENDED_GP0_REG:
.word 0x00000000
.global _EXTENDED_GP1_REG
_EXTENDED_GP1_REG:
.word 0x00000000
.global _EXTENDED_GP2_REG
_EXTENDED_GP2_REG:
.word 0x00000000
.global _EXTENDED_GP3_REG
_EXTENDED_GP3_REG:
.word 0x00000000
.global _EXTENDED_GP4_REG
_EXTENDED_GP4_REG:
.word 0x00000000
.global _EXTENDED_GP5_REG
_EXTENDED_GP5_REG:
.word 0x00000000
.global _EXTENDED_GP6_REG
_EXTENDED_GP6_REG:
.word 0x00000000
.global _EXTENDED_GP7_REG
_EXTENDED_GP7_REG:
.word 0x00000000
.global _MEM_CTRL_EN_NC_MEM_REG
_MEM_CTRL_EN_NC_MEM_REG:
.word 0x00000000
.global _MEM_CTRL_BASE0_ADDR_REG
_MEM_CTRL_BASE0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK0_ADDR_REG
_MEM_CTRL_MASK0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE1_ADDR_REG
_MEM_CTRL_BASE1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK1_ADDR_REG
_MEM_CTRL_MASK1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE2_ADDR_REG
_MEM_CTRL_BASE2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK2_ADDR_REG
_MEM_CTRL_MASK2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE3_ADDR_REG
_MEM_CTRL_BASE3_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK3_ADDR_REG
_MEM_CTRL_MASK3_ADDR_REG:
.word 0x00000000
; 128 bytes minus seventeen registers (four bytes per register)
.fill (128 - 17 * 4)
; Reserved memory-map space
.fill (256 + 256)
;.org 0xfffff600
; Timer Registers
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER3_VAL_REG
_TIMER3_VAL_REG:
.word 0x00000000
; 256 bytes minus four registers (four bytes per register)
.fill (256 - 4 * 4)
;.org 0xfffff700
; Output Line Control Registers
.global _OUTPUT0_CTRL
_OUTPUT0_CTRL:
.word 0x00000000
.global _OUTPUT1_CTRL
_OUTPUT1_CTRL:
.word 0x00000000
.global _OUTPUT2_CTRL
_OUTPUT2_CTRL:
.word 0x00000000
.global _OUTPUT3_CTRL
_OUTPUT3_CTRL:
.word 0x00000000
.global _OUTPUT4_CTRL
_OUTPUT4_CTRL:
.word 0x00000000
.global _OUTPUT5_CTRL
_OUTPUT5_CTRL:
.word 0x00000000
.global _OUTPUT6_CTRL
_OUTPUT6_CTRL:
.word 0x00000000
; 128 bytes minus seven registers (four bytes per register)
.fill (128 - 7 * 4)
.global _INPUT0_CTRL
_INPUT0_CTRL:
.word 0x00000000
; 128 bytes minus one register (four bytes per register)
.fill (128 - 1 * 4)
;.org 0xfffff800
; IQ Buffer Registers
.global _IQ_BUFF_CTRL_REG
_IQ_BUFF_CTRL_REG:
.word 0x00000000
.global _IQ_BUFF_STATUS_REG
_IQ_BUFF_STATUS_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER1_REG
_IQ_BUFF_PARAMETER1_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE1_REG
_IQ_BUFF_TRANSFER_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE1_REG
_IQ_BUFF_FB_BASE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE1_REG
_IQ_BUFF_FB_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER2_REG
_IQ_BUFF_PARAMETER2_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE2_REG
_IQ_BUFF_TRANSFER_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE2_REG
_IQ_BUFF_FB_BASE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE2_REG
_IQ_BUFF_FB_SIZE2_REG:
.word 0x00000000
; 256 bytes minus ten registers (four bytes per register)
.fill (256 - 10 * 4)
;.org 0xfffff900
; DMA Controller
.global _DMA_CTRL_REG
_DMA_CTRL_REG:
.word 0x00000000
.global _DMA_STATUS_REG
_DMA_STATUS_REG:
.word 0x00000000
.global _DMA_CH0_EADDR_REG
_DMA_CH0_EADDR_REG:
.word 0x00000000
.global _DMA_CH0_IADDR_REG
_DMA_CH0_IADDR_REG:
.word 0x00000000
.global _DMA_CH0_SIZE_REG
_DMA_CH0_SIZE_REG:
.word 0x00000000
.global _DMA_CH1_EADDR_REG
_DMA_CH1_EADDR_REG:
.word 0x00000000
.global _DMA_CH1_IADDR_REG
_DMA_CH1_IADDR_REG:
.word 0x00000000
.global _DMA_CH1_SIZE_REG
_DMA_CH1_SIZE_REG:
.word 0x00000000
.global _DMA_CH2_EADDR_REG
_DMA_CH2_EADDR_REG:
.word 0x00000000
.global _DMA_CH2_IADDR_REG
_DMA_CH2_IADDR_REG:
.word 0x00000000
.global _DMA_CH2_SIZE_REG
_DMA_CH2_SIZE_REG:
.word 0x00000000
.global _DMA_CH3_EADDR_REG
_DMA_CH3_EADDR_REG:
.word 0x00000000
.global _DMA_CH3_IADDR_REG
_DMA_CH3_IADDR_REG:
.word 0x00000000
.global _DMA_CH3_SIZE_REG
_DMA_CH3_SIZE_REG:
.word 0x00000000
; 256 bytes minus fourteen registers (four bytes per register)
.fill (256 - 14 * 4)
;.org 0xfffffa00
; Sequence Generator
.global _SEQ_GEN_CTRL_STATUS_REG
_SEQ_GEN_CTRL_STATUS_REG:
.word 0x00000000
.global _SEQ_GEN_MASK_REGS
_SEQ_GEN_MASK_REGS:
.fill (302 * 4)
.global _SEQ_GEN_SHIFT_REG
_SEQ_GEN_SHIFT_REG:
.word 0x00000000
; 256 bytes minus seven registers (four bytes per register)
.fill (256 - 48 * 4)
; Reserved memory-map space
.fill (0x1000 - 0xf00)
|
32bitmicro/newlib-nano-1.0
| 17,473
|
libgloss/mt/startup-16-003.S
|
/*
* $Header: /cvs/src/src/libgloss/mt/startup-16-003.S,v 1.2 2006/03/22 12:47:59 nathan Exp $
*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
* 09Jan04 (DJK) Modified internal I/O port definitions for the
* MS1-16-003.
*
* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
* space is now reserved for memory-mapped I/O devices.
* (There is over 2K unused, reserved space in this area.)
*
* 26Sep01 (DJK) The memory map is changed and the device interrupts are
* now memory-mapped.
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
*
*/
.section .startup, "a", @progbits
.global __boot_start
__boot_start:
_INTERRUPT_VECTOR_TABLE:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; The illegal instruction trap is not implemented.
;jmp _ILLIVEC ; Vector for illegal instruction
or r0,r0,r0
or r0,r0,r0
_RESERVED1_IVEC:
jmp _RESERVED1_IVEC
or r0,r0,r0
_RESERVED2_IVEC:
jmp _RESERVED2_IVEC
or r0,r0,r0
_RESERVED3_IVEC:
jmp _RESERVED3_IVEC
or r0,r0,r0
_RESERVED4_IVEC:
jmp _RESERVED4_IVEC
or r0,r0,r0
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
; Statically initialized data must be copied from ROM to RAM.
; This is done in the C run-time start-up code (crt0.o).
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x00031C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
; SYS_call is handled by simulator here...
or r0, r0, r0
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
ldw r10, sp, #$0
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
.if 0
; Handler for illegal instruction.
.global _ILLIVEC
_ILLIVEC:
reti r15
or r0, r0, r0
.endif
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
.section .internal_io, "a", @nobits
.fill 256 ; Fill the first page.
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
;.org 0xfffff100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_REG
_DEV8_INTERRUPT_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_REG
_DEV9_INTERRUPT_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_REG
_DEV10_INTERRUPT_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_REG
_DEV11_INTERRUPT_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_REG
_DEV12_INTERRUPT_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_REG
_DEV13_INTERRUPT_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_REG
_DEV14_INTERRUPT_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_REG
_DEV15_INTERRUPT_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_REG
_DEV16_INTERRUPT_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_REG
_DEV17_INTERRUPT_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_REG
_DEV18_INTERRUPT_REG:
.word 0x00000000
; 128 bytes minus nineteen registers (four bytes per register)
.fill (128 - 19 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
.global _INTERRUPT_PENDING_REG
_INTERRUPT_PENDING_REG:
.word 0x00000000
; 16 bytes minus two registers (four bytes per register)
.fill (16 - 2 * 4)
.global _DEV0_INTERRUPT_LEVEL_REG
_DEV0_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_LEVEL_REG
_DEV1_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_LEVEL_REG
_DEV2_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_LEVEL_REG
_DEV3_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_LEVEL_REG
_DEV4_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_LEVEL_REG
_DEV5_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_LEVEL_REG
_DEV6_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_LEVEL_REG
_DEV7_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_LEVEL_REG
_DEV8_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_LEVEL_REG
_DEV9_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_LEVEL_REG
_DEV10_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_LEVEL_REG
_DEV11_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_LEVEL_REG
_DEV12_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_LEVEL_REG
_DEV13_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_LEVEL_REG
_DEV14_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_LEVEL_REG
_DEV15_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_LEVEL_REG
_DEV16_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_LEVEL_REG
_DEV17_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_LEVEL_REG
_DEV18_INTERRUPT_LEVEL_REG:
.word 0x00000000
; 128 bytes minus twenty-three registers (four bytes per register)
.fill (128 - 23 * 4)
;.org 0xfffff200
; MorphoSys Decoder Registers
.global _MS_DEC_CIRC_BUFF_SEL_REG
_MS_DEC_CIRC_BUFF_SEL_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERM_REG
_MS_DEC_CUSTOM_PERM_REG:
.word 0x00000000
.global _MS_DEC_CTXT_BASE_REG
_MS_DEC_CTXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TBL_REG
_MS_DEC_LOOKUP_TBL_REG:
.word 0x00000000
.global _MS_CIRC_BUFF0_I_REG
_MS_CIRC_BUFF0_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF0_P_REG
_MS_CIRC_BUFF0_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF0_B_REG
_MS_DATA_BUFF0_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF0_S_REG
_MS_DATA_BUFF0_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF1_I_REG
_MS_CIRC_BUFF1_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF1_P_REG
_MS_CIRC_BUFF1_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF1_B_REG
_MS_DATA_BUFF1_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF1_S_REG
_MS_DATA_BUFF1_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF2_I_REG
_MS_CIRC_BUFF2_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF2_P_REG
_MS_CIRC_BUFF2_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF2_B_REG
_MS_DATA_BUFF2_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF2_S_REG
_MS_DATA_BUFF2_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF3_I_REG
_MS_CIRC_BUFF3_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF3_P_REG
_MS_CIRC_BUFF3_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF3_B_REG
_MS_DATA_BUFF3_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF3_S_REG
_MS_DATA_BUFF3_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF4_I_REG
_MS_CIRC_BUFF4_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF4_P_REG
_MS_CIRC_BUFF4_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF4_B_REG
_MS_DATA_BUFF4_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF4_S_REG
_MS_DATA_BUFF4_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF5_I_REG
_MS_CIRC_BUFF5_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF5_P_REG
_MS_CIRC_BUFF5_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF5_B_REG
_MS_DATA_BUFF5_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF5_S_REG
_MS_DATA_BUFF5_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF6_I_REG
_MS_CIRC_BUFF6_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF6_P_REG
_MS_CIRC_BUFF6_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF6_B_REG
_MS_DATA_BUFF6_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF6_S_REG
_MS_DATA_BUFF6_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF7_I_REG
_MS_CIRC_BUFF7_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF7_P_REG
_MS_CIRC_BUFF7_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF7_B_REG
_MS_DATA_BUFF7_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF7_S_REG
_MS_DATA_BUFF7_S_REG:
.word 0x00000000
.global _MS_OMEGA_PERM1_REG
_MS_OMEGA_PERM1_REG:
.word 0x00000000
.global _MS_WRITE_FB_ADDR_REG
_MS_WRITE_FB_ADDR_REG:
.word 0x00000000
.global _MS_OMEGA_PERM2_REG
_MS_OMEGA_PERM2_REG:
.word 0x00000000
; 256 bytes minus forty registers (four bytes per register)
.fill (256 - 40 * 4)
;.org 0xfffff300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
.global _DEBUG_CRITICAL_REG
_DEBUG_OWNERSHIP_REG:
.word 0x00000000
.global _DEBUG_KERNEL_ID_REG
_DEBUG_KERNEL_ID_REG:
.word 0x00000000
.global _DEBUG_IRQ_STATUS_REG
_DEBUG_IRQ_STATUS_REG:
.word 0x00000000
; There are two reserved registers.
.fill (2 * 4)
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 128 bytes minus eight registers (four bytes per register)
.fill (128 - 8 * 4)
.global _EXTENDED_GP0_REG
_EXTENDED_GP0_REG:
.word 0x00000000
.global _EXTENDED_GP1_REG
_EXTENDED_GP1_REG:
.word 0x00000000
.global _EXTENDED_GP2_REG
_EXTENDED_GP2_REG:
.word 0x00000000
.global _EXTENDED_GP3_REG
_EXTENDED_GP3_REG:
.word 0x00000000
.global _EXTENDED_GP4_REG
_EXTENDED_GP4_REG:
.word 0x00000000
.global _EXTENDED_GP5_REG
_EXTENDED_GP5_REG:
.word 0x00000000
.global _EXTENDED_GP6_REG
_EXTENDED_GP6_REG:
.word 0x00000000
.global _EXTENDED_GP7_REG
_EXTENDED_GP7_REG:
.word 0x00000000
.global _MEM_CTRL_EN_NC_MEM_REG
_MEM_CTRL_EN_NC_MEM_REG:
.word 0x00000000
.global _MEM_CTRL_BASE0_ADDR_REG
_MEM_CTRL_BASE0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK0_ADDR_REG
_MEM_CTRL_MASK0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE1_ADDR_REG
_MEM_CTRL_BASE1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK1_ADDR_REG
_MEM_CTRL_MASK1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE2_ADDR_REG
_MEM_CTRL_BASE2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK2_ADDR_REG
_MEM_CTRL_MASK2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE3_ADDR_REG
_MEM_CTRL_BASE3_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK3_ADDR_REG
_MEM_CTRL_MASK3_ADDR_REG:
.word 0x00000000
; 128 bytes minus seventeen registers (four bytes per register)
.fill (128 - 17 * 4)
; Reserved memory-map space
.fill (256 + 256)
;.org 0xfffff600
; Timer Registers
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER3_VAL_REG
_TIMER3_VAL_REG:
.word 0x00000000
; 256 bytes minus four registers (four bytes per register)
.fill (256 - 4 * 4)
;.org 0xfffff700
; Output Line Control Registers
.global _OUTPUT0_CTRL
_OUTPUT0_CTRL:
.word 0x00000000
.global _OUTPUT1_CTRL
_OUTPUT1_CTRL:
.word 0x00000000
.global _OUTPUT2_CTRL
_OUTPUT2_CTRL:
.word 0x00000000
.global _OUTPUT3_CTRL
_OUTPUT3_CTRL:
.word 0x00000000
.global _OUTPUT4_CTRL
_OUTPUT4_CTRL:
.word 0x00000000
.global _OUTPUT5_CTRL
_OUTPUT5_CTRL:
.word 0x00000000
.global _OUTPUT6_CTRL
_OUTPUT6_CTRL:
.word 0x00000000
; 128 bytes minus seven registers (four bytes per register)
.fill (128 - 7 * 4)
.global _INPUT0_CTRL
_INPUT0_CTRL:
.word 0x00000000
; 128 bytes minus one register (four bytes per register)
.fill (128 - 1 * 4)
;.org 0xfffff800
; IQ Buffer Registers
.global _IQ_BUFF_CTRL_REG
_IQ_BUFF_CTRL_REG:
.word 0x00000000
.global _IQ_BUFF_STATUS_REG
_IQ_BUFF_STATUS_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER1_REG
_IQ_BUFF_PARAMETER1_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE1_REG
_IQ_BUFF_TRANSFER_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE1_REG
_IQ_BUFF_FB_BASE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE1_REG
_IQ_BUFF_FB_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER2_REG
_IQ_BUFF_PARAMETER2_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE2_REG
_IQ_BUFF_TRANSFER_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE2_REG
_IQ_BUFF_FB_BASE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE2_REG
_IQ_BUFF_FB_SIZE2_REG:
.word 0x00000000
; 256 bytes minus ten registers (four bytes per register)
.fill (256 - 10 * 4)
;.org 0xfffff900
; DMA Controller
.global _DMA_CTRL_REG
_DMA_CTRL_REG:
.word 0x00000000
.global _DMA_STATUS_REG
_DMA_STATUS_REG:
.word 0x00000000
.global _DMA_CH0_EADDR_REG
_DMA_CH0_EADDR_REG:
.word 0x00000000
.global _DMA_CH0_IADDR_REG
_DMA_CH0_IADDR_REG:
.word 0x00000000
.global _DMA_CH0_SIZE_REG
_DMA_CH0_SIZE_REG:
.word 0x00000000
.global _DMA_CH1_EADDR_REG
_DMA_CH1_EADDR_REG:
.word 0x00000000
.global _DMA_CH1_IADDR_REG
_DMA_CH1_IADDR_REG:
.word 0x00000000
.global _DMA_CH1_SIZE_REG
_DMA_CH1_SIZE_REG:
.word 0x00000000
.global _DMA_CH2_EADDR_REG
_DMA_CH2_EADDR_REG:
.word 0x00000000
.global _DMA_CH2_IADDR_REG
_DMA_CH2_IADDR_REG:
.word 0x00000000
.global _DMA_CH2_SIZE_REG
_DMA_CH2_SIZE_REG:
.word 0x00000000
.global _DMA_CH3_EADDR_REG
_DMA_CH3_EADDR_REG:
.word 0x00000000
.global _DMA_CH3_IADDR_REG
_DMA_CH3_IADDR_REG:
.word 0x00000000
.global _DMA_CH3_SIZE_REG
_DMA_CH3_SIZE_REG:
.word 0x00000000
; 256 bytes minus fourteen registers (four bytes per register)
.fill (256 - 14 * 4)
;.org 0xfffffa00
; Sequence Generator
.global _SEQ_GEN_CTRL_STATUS_REG
_SEQ_GEN_CTRL_STATUS_REG:
.word 0x00000000
.global _SEQ_GEN_MASK_REGS
_SEQ_GEN_MASK_REGS:
.fill (302 * 4)
.global _SEQ_GEN_SHIFT_REG
_SEQ_GEN_SHIFT_REG:
.word 0x00000000
; 256 bytes minus seven registers (four bytes per register)
.fill (256 - 48 * 4)
; Reserved memory-map space
.fill (0x1000 - 0xf00)
|
32bitmicro/newlib-nano-1.0
| 1,289
|
libgloss/mt/crt0.S
|
# Startup Code for the Morpho mt
# Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.section .text
.global _start
_start:
;; Initialise the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the data space
ldui r9, #%hi16(_edata)
addui r9, r9, #%lo16(_edata)
ldui r10, #%hi16(_end)
addui r10, r10, #%lo16(_end)
addi r5, r0, #0
.L0:
stw r5, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .L0
or r0, r0, r0 ; nop
;; Call global and static constructors
ldui r10, #%hi16(_init)
addui r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Setup destructors to be called from exit.
;; (Just in case main never returns....)
ldui r10, #%hi16(atexit)
addui r10, r10, #%lo16(atexit)
ldui r1, #%hi16(_fini)
addui r1, r1, #%lo16(_fini)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Initialise argc, argv and envp to empty
addi r1, r0, #0
addi r2, r0, #0
addi r3, r0, #0
;; Call main
ldui r10, #%hi16(main)
addui r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Jump to exit
ldui r10, #%hi16(exit)
addui r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
|
32bitmicro/newlib-nano-1.0
| 13,997
|
libgloss/mt/startup-16-002.S
|
/*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
*
*/
.section .startup, "a", @progbits
.global __boot_start
__boot_start:
_INTERRUPT_VECTOR_TABLE:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; The illegal instruction trap is not implemented.
_RESERVED1_IVEC:
jmp _RESERVED1_IVEC ; Vector for illegal instruction
or r0,r0,r0
jmp _OVFIVEC ; Vector for overflow exception
or r0,r0,r0
_RESERVED2_IVEC:
jmp _RESERVED2_IVEC
or r0,r0,r0
_RESERVED3_IVEC:
jmp _RESERVED3_IVEC
or r0,r0,r0
_RESERVED4_IVEC:
jmp _RESERVED4_IVEC
or r0,r0,r0
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
; Statically initialized data must be copied from ROM to RAM.
; This is done in the C run-time start-up code (crt0.o).
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x00031C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0 ; SYS_call is handled by simulator here...
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
; Handler for BREAK instruction. This handler triggers the simulator
; to send a SIGTRAP signal to gdb by writing to the I/O register at
; address $40005, setting bit #0 (0x1).
;
; The above address has been changed to 0x000304 and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
ldw r10, sp, #$0
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
; The documentation is lacking in the specification of the Overflow
; Exception generation. The address of the instruction causing the
; overflow is placed into R15 and the overflow exception interrupt
; is triggered. So, to continue execution, return to the address
; of the next instruction (i.e., R15 + one instruction).
_OVFIVEC:
addi r15, r15, #$4
or r0, r0, r0
reti r15
or r0, r0, r0
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
.section .internal_io, "a", @nobits
.fill 256 ; Fill the first page.
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
;.org 0xfff100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_REG
_DEV8_INTERRUPT_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_REG
_DEV9_INTERRUPT_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_REG
_DEV10_INTERRUPT_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_REG
_DEV11_INTERRUPT_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_REG
_DEV12_INTERRUPT_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_REG
_DEV13_INTERRUPT_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_REG
_DEV14_INTERRUPT_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_REG
_DEV15_INTERRUPT_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_REG
_DEV16_INTERRUPT_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_REG
_DEV17_INTERRUPT_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_REG
_DEV18_INTERRUPT_REG:
.word 0x00000000
; 128 bytes minus ten registers (four bytes per register)
.fill (128 - 19 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
; 128 bytes minus one register (four bytes per register)
.fill (128 - 1 * 4)
;.org 0xfff200
; MorphoSys Decoder Registers
.global _MS_DEC_CIRC_BUFF_SEL_REG
_MS_DEC_CIRC_BUFF_SEL_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERM_REG
_MS_DEC_CUSTOM_PERM_REG:
.word 0x00000000
.global _MS_DEC_CTXT_BASE_REG
_MS_DEC_CTXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TBL_REG
_MS_DEC_LOOKUP_TBL_REG:
.word 0x00000000
.global _MS_CIRC_BUFF0_END_REG
_MS_CIRC_BUFF0_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF0_SIZE_REG
_MS_CIRC_BUFF0_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK0_END_REG
_MS_DATA_BLK0_END_REG:
.word 0x00000000
.global _MS_DATA_BLK0_SIZE_REG
_MS_DATA_BLK0_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF1_END_REG
_MS_CIRC_BUFF1_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF1_SIZE_REG
_MS_CIRC_BUFF1_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK1_END_REG
_MS_DATA_BLK1_END_REG:
.word 0x00000000
.global _MS_DATA_BLK1_SIZE_REG
_MS_DATA_BLK1_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF2_END_REG
_MS_CIRC_BUFF2_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF2_SIZE_REG
_MS_CIRC_BUFF2_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK2_END_REG
_MS_DATA_BLK2_END_REG:
.word 0x00000000
.global _MS_DATA_BLK2_SIZE_REG
_MS_DATA_BLK2_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF3_END_REG
_MS_CIRC_BUFF3_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF3_SIZE_REG
_MS_CIRC_BUFF3_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK3_END_REG
_MS_DATA_BLK3_END_REG:
.word 0x00000000
.global _MS_DATA_BLK3_SIZE_REG
_MS_DATA_BLK3_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF4_END_REG
_MS_CIRC_BUFF4_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF4_SIZE_REG
_MS_CIRC_BUFF4_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK4_END_REG
_MS_DATA_BLK4_END_REG:
.word 0x00000000
.global _MS_DATA_BLK4_SIZE_REG
_MS_DATA_BLK4_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF5_END_REG
_MS_CIRC_BUFF5_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF5_SIZE_REG
_MS_CIRC_BUFF5_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK5_END_REG
_MS_DATA_BLK5_END_REG:
.word 0x00000000
.global _MS_DATA_BLK5_SIZE_REG
_MS_DATA_BLK5_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF6_END_REG
_MS_CIRC_BUFF6_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF6_SIZE_REG
_MS_CIRC_BUFF6_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK6_END_REG
_MS_DATA_BLK6_END_REG:
.word 0x00000000
.global _MS_DATA_BLK6_SIZE_REG
_MS_DATA_BLK6_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF7_END_REG
_MS_CIRC_BUFF7_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF7_SIZE_REG
_MS_CIRC_BUFF7_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK7_END_REG
_MS_DATA_BLK7_END_REG:
.word 0x00000000
.global _MS_DATA_BLK7_SIZE_REG
_MS_DATA_BLK7_SIZE_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC0_REG
_MS_DEC_AUTO_INC0_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC1_REG
_MS_DEC_AUTO_INC1_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC2_REG
_MS_DEC_AUTO_INC2_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC3_REG
_MS_DEC_AUTO_INC3_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC4_REG
_MS_DEC_AUTO_INC4_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC5_REG
_MS_DEC_AUTO_INC5_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC6_REG
_MS_DEC_AUTO_INC6_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC7_REG
_MS_DEC_AUTO_INC7_REG:
.word 0x00000000
; 256 bytes minus forty-five registers (four bytes per register)
.fill (256 - 45 * 4)
;.org 0xfff300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
; There are five reserved registers.
.fill (5 * 4)
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
;.org 0xfff400
; Sequence Generator Registers
.global _SEQ_GEN_CTRL_REG
_SEQ_GEN_CTRL_REG:
.word 0x00000000
.global _SEQ_GEN_MASK_REGS
_SEQ_GEN_MASK_REGS:
; The mask registers consume two pages (less one control register).
; 512 bytes minus one register (four bytes per register).
.fill (256 + 256 - 1 * 4)
;.org 0xfff600
; Timer Registers
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER3_VAL_REG
_TIMER3_VAL_REG:
.word 0x00000000
; 256 bytes minus four registers (four bytes per register)
.fill (256 - 4 * 4)
;.org 0xfff700
; Output Line Control Registers
.global _OUTPUT0_CTRL
_OUTPUT0_CTRL:
.word 0x00000000
.global _OUTPUT1_CTRL
_OUTPUT1_CTRL:
.word 0x00000000
.global _OUTPUT2_CTRL
_OUTPUT2_CTRL:
.word 0x00000000
.global _OUTPUT3_CTRL
_OUTPUT3_CTRL:
.word 0x00000000
.global _OUTPUT4_CTRL
_OUTPUT4_CTRL:
.word 0x00000000
.global _OUTPUT5_CTRL
_OUTPUT5_CTRL:
.word 0x00000000
.global _OUTPUT6_CTRL
_OUTPUT6_CTRL:
.word 0x00000000
.global _OUTPUT7_CTRL
_OUTPUT7_CTRL:
.word 0x00000000
.global _OUTPUT8_CTRL
_OUTPUT8_CTRL:
.word 0x00000000
.global _OUTPUT9_CTRL
_OUTPUT9_CTRL:
.word 0x00000000
.global _OUTPUT10_CTRL
_OUTPUT10_CTRL:
.word 0x00000000
;; 128 bytes minus eleven registers (four bytes per register)
;.fill (128 - 11 * 4)
.global _INPUT0_CTRL
_INPUT0_CTRL:
.word 0x00000000
;; 128 bytes minus one register (four bytes per register)
;.fill (128 - 1 * 4)
; 256 bytes minus twelve registers (four bytes per register)
.fill (256 - 12 * 4)
;.org 0xfff800
; IQ Buffer Registers
.global _IQ_BUFF_CTRL_REG
_IQ_BUFF_CTRL_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER1_REG
_IQ_BUFF_PARAMETER1_REG:
.word 0x00000000
.global _IQ_BUFF_DATA_SIZE1_REG
_IQ_BUFF_DATA_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE1_REG
_IQ_BUFF_TRANSFER_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_ADDR1_REG
_IQ_BUFF_FB_ADDR1_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER2_REG
_IQ_BUFF_PARAMETER2_REG:
.word 0x00000000
.global _IQ_BUFF_DATA_SIZE2_REG
_IQ_BUFF_DATA_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE2_REG
_IQ_BUFF_TRANSFER_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_ADDR2_REG
_IQ_BUFF_FB_ADDR2_REG:
.word 0x00000000
; 256 bytes minus nine registers (four bytes per register)
.fill (256 - 9 * 4)
;.org 0xfff900
; Reserved memory-mapped space.
.fill (0x1000 - 0x900)
|
32bitmicro/newlib-nano-1.0
| 3,499
|
libgloss/mt/crt0-64-001.S
|
; crt0_2.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
; 12Nov01 (DJK) - The return code from main was not being passed to exit().
; Now it is passed as a parameter in R1.
;
; 10Sep01 (DJK) - The function exit() does not return. However, in the
; the case of device error (if the halt bit does not
; function properly, for instance), then a catch loop
; has been added.
;
;
; Copyright 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.equ HALT_REG, 0x300
.section .text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(__FRAME_BUFFER_START)
brle r10, r9, .Lnext1
ori r11, r11, #%lo16(__FRAME_BUFFER_START)
.Lcpy0:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy0
addi r11, r11, #$4
.Lnext1:
;; Copy data from ROM to External Memory (off-chip memory)
ldui r9, #%hi16(_extdata_start)
ori r9, r9, #%lo16(_extdata_start)
ldui r10, #%hi16(_extdata_end)
ori r10, r10, #%lo16(_extdata_end)
ldui r11, #%hi16(__EXTERNAL_MEMORY_START)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(__EXTERNAL_MEMORY_START)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy2
or r0, r0, r0 ; nop
.Lnext3:
;; Zero the external memory bss section
ldui r9, #%hi16(_extbss_start)
ori r9, r9, #%lo16(_extbss_start)
ldui r10, #%hi16(_extbss_end)
ori r10, r10, #%lo16(_extbss_end)
or r0, r0, r0
brle r10, r9, .Lnext4
or r0, r0, r0
.Lcpy3:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy3
or r0, r0, r0
.Lnext4:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Setup destructors to be called from exit.
;; (Just in case main never returns....)
ldui r10, #%hi16(atexit)
ori r10, r10, #%lo16(atexit)
ldui r1, #%hi16(_fini)
ori r1, r1, #%lo16(_fini)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Initialise argc, argv and envp to empty
addi r1, r0, #0
addi r2, r0, #0
addi r3, r0, #0
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #HALT_REG
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
|
32bitmicro/newlib-nano-1.0
| 1,610
|
libgloss/mn10200/crt0.S
|
##==============================================================================
##
## crt0.S
##
## MN10200 startup code
##
##==============================================================================
##
## Copyright (c) 1995, 1996, 1997, 1998 Cygnus Solutions
##
## The authors hereby grant permission to use, copy, modify, distribute,
## and license this software and its documentation for any purpose, provided
## that existing copyright notices are retained in all copies and that this
## notice is included verbatim in any distributions. No written agreement,
## license, or royalty fee is required for any of the authorized uses.
## Modifications to this software may be copyrighted by their authors
## and need not follow the licensing terms described here, provided that
## the new terms are clearly indicated on the first page of each file where
## they apply.
##
##------------------------------------------------------------------------------
.file "crt0.S"
##------------------------------------------------------------------------------
## Startup code
.section .text
.global _start
_start:
mov _stack,a3 # Load up the stack pointer and allocate
# our current frame.
mov _edata,a0 # Get the start/end of bss
mov _end,a1
cmp a0,a1 # If no bss, then do nothing
beqx .L0
sub d0,d0 # clear d0
.L1:
movb d0,(a0) # Clear a byte and bump pointer
add 1,a0
cmp a0,a1
bnex .L1
.L0:
jsr ___main
sub d0,d0
mov d0,d1
mov d0,(a3)
jsr _main # Call main program
jmp _exit # All done, no need to return or
# deallocate our stack.
.section .stack
_stack: .long 1
|
32bitmicro/newlib-nano-1.0
| 1,553
|
libgloss/crx/crtn.S
|
/* Specialized code needed to support construction and destruction of
file-scope objects in C++ and Java code, and to support exception handling.
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* As a special exception, if you link this library with files
compiled with GCC to produce an executable, this does not cause
the resulting executable to be covered by the GNU General Public License.
This exception does not however invalidate any other reasons why
the executable file might be covered by the GNU General Public License. */
/*
* This file supplies function epilogues for the .init and .fini sections.
* It is linked in after all other files.
*/
.file "crtn.o"
.ident "GNU C crtn.o"
.section .init
popret ra
.section .fini
popret ra
|
32bitmicro/newlib-nano-1.0
| 1,646
|
libgloss/crx/crti.S
|
/* Specialized code needed to support construction and destruction of
file-scope objects in C++ and Java code, and to support exception handling.
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* As a special exception, if you link this library with files
compiled with GCC to produce an executable, this does not cause
the resulting executable to be covered by the GNU General Public License.
This exception does not however invalidate any other reasons why
the executable file might be covered by the GNU General Public License. */
/*
* This file just supplies function prologues for the .init and .fini
* sections. It is linked in before crtbegin.o.
*/
.file "crti.o"
.ident "GNU C crti.o"
.section .init
.globl _init
.type _init,@function
_init:
push ra
.section .fini
.globl _fini
.type _fini,@function
_fini:
push ra
|
32bitmicro/newlib-nano-1.0
| 4,414
|
libgloss/crx/crt0.S
|
##############################################################################
# crt0.S -- CRX default start-up routine #
# #
# Copyright (c) 2004 National Semiconductor Corporation #
# #
# The authors hereby grant permission to use, copy, modify, distribute, #
# and license this software and its documentation for any purpose, provided #
# that existing copyright notices are retained in all copies and that this #
# notice is included verbatim in any distributions. No written agreement, #
# license, or royalty fee is required for any of the authorized uses. #
# Modifications to this software may be copyrighted by their authors #
# and need not follow the licensing terms described here, provided that #
# the new terms are clearly indicated on the first page of each file where #
# they apply. #
# #
# This is the start routine of your CRX program. #
# It is linked with your application automatically. You can use #
# this routine as a template and modify it to your needs, yet this #
# file must be supplied for the compiler. #
# It is assumed that the following symbols are defined in your linker #
# script: __STACK_START, __ISTACK_START, __DATA_START, __DATA_END, #
# __DATA_IMAGE_START, __BSS_START, __BSS_END. #
##############################################################################
.text
.align 4
.globl _main
.globl _start
.globl _atexit
.globl _exit
.globl __dispatch_table
_start:
#----------------------------------------------------------------------------#
# Initialize the stack pointers. The constants __STACK_START and #
# __ISTACK_START should be defined in the linker script. #
movd $__STACK_START, sp
movd $__ISTACK_START, r0
mtpr r0, isp
#----------------------------------------------------------------------------#
# Initialize the default sections according to the linker script. #
movd $__DATA_END, r4
subd $__DATA_START, r4
movd $__DATA_START, r2
movd $__DATA_IMAGE_START, r3
bal ra, _memcpy
movd $__BSS_END, r4
subd $__BSS_START, r4
movd $__BSS_START, r2
movd $0, r3
bal ra, _memset
#----------------------------------------------------------------------------#
# Initialize the intbase (pointer to the dispatch table). #
movd $__dispatch_table, r0
mtpr r0, intbase
#----------------------------------------------------------------------------#
# Handle global and static constructurs execution and setup #
# destructors to be called from exit. #
bal ra, _init
movd $_fini, r2
bal ra, _atexit
#----------------------------------------------------------------------------#
# Here you may add initializations that are specific to your #
# environment. For example: #
# 1. Configure wait states and other BIU parameters in order to get #
# the best performance out of your target (see the specification #
# document). #
# 2. Enable maskable interrupts that should be enabled when your #
# program starts to execute. #
#----------------------------------------------------------------------------#
# Jump to the main function in your application. #
bal ra, _main
#----------------------------------------------------------------------------#
# Upon returning from the main function (if it isn't an infinite loop), #
# jump to the exit function. The exit function is located in the #
# library 'libc.a'. #
movd r0, r2 # _main return value is passed as a
# parameter to exit.
br _exit # returns control to the debugger.
|
32bitmicro/newlib-nano-1.0
| 1,767
|
libgloss/i386/cygmon-crt0.S
|
/*
* crt0 startup code for user programs running under Cygmon
*
* Copyright (c) 1998, 2000 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#define _S2(P,X) P ## X
#define _S1(P,X) _S2(P,X)
#define SYM(X) _S1(__USER_LABEL_PREFIX__,X)
.data
.align 8
SYM(environ):
.long 0
SYM(argc):
.long 0
.text
.align 4
.globl __start
__start:
/* see if the stack is already setup. if not, then default
* to using the value of %sp as set by the ROM monitor
*/
movl $__stack, %eax
testl %eax, %eax
jz 1f
movl %eax, %esp
1:
mov $0, %ebp
movl $__bss_start, %edi
movl $__bss_end, %ecx
subl %edi, %ecx
xorl %eax, %eax
rep; stosb
pushl $SYM(__sigtramp)
pushl $0
call SYM(__install_signal_handler)
popl %eax
pushl $SYM(__do_global_dtors)
call SYM(atexit)
popl %eax
call SYM(__do_global_ctors)
pushl $SYM(argc)
call SYM(__get_program_arguments)
popl %ecx
movl SYM(argc), %ecx
pushl %eax
pushl %ecx
call SYM(main)
popl %ecx
popl %edx
/* call exit from the C library so atexit gets called, and the
* C++ destructors get run. This calls our exit routine below
* when it's done.
*/
pushl %eax
call SYM(exit)
3:
jmp 3b
|
32bitmicro/newlib-nano-1.0
| 1,460
|
libgloss/d30v/crt0.S
|
/*
* crt0.S -- startup file for D30V systems.
*
* Copyright (c) 1997 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
.file "crt0.S"
.text
.globl _start
.extern main
.extern exit
.extern __stack
.extern __sbss_start
.extern __sbss_end
.extern __ebss_start
.extern __ebss_end
.extern __bss_start
.extern __bss_end
.extern memset
.type _start,@function
_start: or.l sp,r0,__stack
/* Zero the .sbss area */
or.l r2,r0,__sbss_start
or.l r4,r0,__sbss_end
sub r4,r4,r2 || or.s r3,r0,0
bsrtnz.l r4,(memset)
/* Zero the .ebss area */
or.l r2,r0,__ebss_start
or.l r4,r0,__ebss_end
sub r4,r4,r2 || or.s r3,r0,0
bsrtnz.l r4,(memset)
/* Zero the .bss area */
or.l r2,r0,__bss_start
or.l r4,r0,__bss_end
sub r4,r4,r2 || or.s r3,r0,0
bsrtnz.l r4,(memset)
or.s r2,r0,0 || or.s r3,r0,0
or r4,r0,0 || nop
jsr.l (main)
jsr.l (exit)
.size _start,.-_start
|
32bitmicro/newlib-nano-1.0
| 1,250
|
libgloss/m32r/crt0.S
|
.text
.balign 4
.global _start
_start:
seth sp, #shigh(_stack)
add3 sp, sp, #low(_stack)
ldi fp, #0
# Clear the BSS. Do it in two parts for efficiency: longwords first
# for most of it, then the remaining 0 to 3 bytes.
seth r2, #shigh(__bss_start)
add3 r2, r2, #low(__bss_start); R2 = start of BSS
seth r3, #shigh(_end)
add3 r3, r3, #low(_end) ; R3 = end of BSS + 1
sub r3, r2 ; R3 = BSS size in bytes
mv r4, r3
srli r4, #2 ; R4 = BSS size in longwords (rounded down)
ldi r1, #0 ; clear R1 for longword store
addi r2, #-4 ; account for pre-inc store
beqz r4, .Lendloop1 ; any more to go?
.Lloop1:
st r1, @+r2 ; yep, zero out another longword
addi r4, #-1 ; decrement count
bnez r4, .Lloop1 ; go do some more
.Lendloop1:
and3 r4, r3, #3 ; get no. of remaining BSS bytes to clear
addi r2, #4 ; account for pre-inc store
beqz r4, .Lendloop2 ; any more to go?
.Lloop2:
stb r1, @r2 ; yep, zero out another byte
addi r2, #1 ; bump address
addi r4, #-1 ; decrement count
bnez r4, .Lloop2 ; go do some more
.Lendloop2:
# Run code in the .init section.
# This will queue the .fini section to be run with atexit.
bl __init
# Call main, then exit.
bl main
bl exit
# If that fails just loop.
.Lexit:
bra .Lexit
|
32bitmicro/newlib-nano-1.0
| 1,071
|
libgloss/frv/sim-unlink.S
|
/*
* sim-unlink.S -- write interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- Filename
*
* Output:
* gr8 -- Zero on success, -1 on failure.
* errno -- Set if an error
*/
.globl EXT(_unlink)
.type EXT(_unlink),@function
.weak EXT(unlink)
.text
EXT(_unlink):
EXT(unlink):
setlos #SYS_unlink,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_unlink),.Lend-EXT(_unlink)
|
32bitmicro/newlib-nano-1.0
| 1,118
|
libgloss/frv/sim-read.S
|
/*
* sim-read.S -- read interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File descriptor.
* gr9 -- Buffer to be read into.
* gr10 -- Length of the buffer.
*
* Output:
* gr8 -- Length read or -1.
* errno -- Set if an error
*/
.globl EXT(_read)
.type EXT(_read),@function
.weak EXT(read)
.text
EXT(_read):
EXT(read):
setlos #SYS_read,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_read),.Lend-EXT(_read)
|
32bitmicro/newlib-nano-1.0
| 1,141
|
libgloss/frv/sim-open.S
|
/*
* sim-open.S -- open interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File name to open.
* gr9 -- open mode.
* gr10 -- optionally, the permission bits to set the file to.
*
* Output:
* gr8 -- file descriptor or -1.
* errno -- Set if an error
*/
.globl EXT(_open)
.type EXT(_open),@function
.weak EXT(open)
.text
EXT(_open):
EXT(open):
setlos #SYS_open,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_open),.Lend-EXT(_open)
|
32bitmicro/newlib-nano-1.0
| 1,129
|
libgloss/frv/sim-write.S
|
/*
* sim-write.S -- write interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File descriptor.
* gr9 -- String to be printed.
* gr10 -- Length of the string.
*
* Output:
* gr8 -- Length written or -1.
* errno -- Set if an error
*/
.globl EXT(_write)
.type EXT(_write),@function
.weak EXT(write)
.text
EXT(_write):
EXT(write):
setlos #SYS_write,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_write),.Lend-EXT(_write)
|
32bitmicro/newlib-nano-1.0
| 7,636
|
libgloss/frv/crt0.S
|
/* crt0.S -- startup file for frv.
*
* Copyright (c) 2002, 2003 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
/* statically store .Lcall's address so we can see if we are running
at the location we were linked for or a different location. */
.data
.type EXT(__start_cmp),@object
.size EXT(__start_cmp),4
.p2align 2
EXT(__start_cmp):
.picptr .Lcall
.globl __start
.weak _start
.text
.type __start,@function
__start:
_start:
call .Lcall /* set up _gp in a pic-friendly manor */
.Lcall: movsg lr, gr4
P(sethi) #gprelhi(.Lcall), gr5
setlo #gprello(.Lcall), gr5
P(sub) gr4, gr5, gr16
#if ! __FRV_FDPIC__
sethi #gprelhi(EXT(_stack)), sp /* load up stack pointer */
P(setlo) #gprello(EXT(_stack)), sp
setlos #0, fp /* zero fp to allow unwinders to stop */
P(add) sp, gr16, sp
#define FDPIC(...)
#else
#define FDPIC(...) __VA_ARGS__
/* The assembler will rightfully claim that
#hi/lo(__stacksize) are unsafe for PIC, but since __stacksize
is absolute, and we don't want it to be relocated, we should
be fine. */
sethi #gprelhi(EXT(__end)), gr6
P(sethi) #hi(EXT(__stacksize+7)), gr5
setlo #gprello(EXT(__end)), gr6
P(setlo) #lo(EXT(__stacksize+7)), gr5
add gr6, gr16, gr6
add gr6, gr5, gr5
andi gr5, -8, sp
/* Using GPREL to compute _GLOBAL_OFFSET_TABLE_'s will force
the entire program to relocate as a unit, which is fine for
frv-elf. */
P(sethi) #gprelhi(EXT(_GLOBAL_OFFSET_TABLE_)), gr15
setlo #gprello(EXT(_GLOBAL_OFFSET_TABLE_)), gr15
/* We compute the value in a call-saved register (that happens
to be the PIC register in the EABI, and copy it to gr15 before
every call. */
add gr15, gr16, gr17
#endif
sethi #gprelhi(EXT(__start_cmp)), gr5
setlo #gprello(EXT(__start_cmp)), gr5
ld @(gr5,gr16), gr6
subcc gr4, gr6, gr8, icc0
beq icc0, 0, .Lfixed
P(st) gr4, @(gr5, gr16) /* update so if we restart no need to fixup */
setlos 4, gr11
#if ! __FRV_FDPIC__
/* fixup the .ctors list */
sethi #gprelhi(EXT(__CTOR_LIST__)), gr9
P(sethi) #gprelhi(EXT(__CTOR_END__)), gr10
setlo #gprello(EXT(__CTOR_LIST__)), gr9
P(setlo) #gprello(EXT(__CTOR_END__)), gr10
add gr9, gr16, gr9
P(add) gr10, gr16, gr10
addi gr9, 4, gr9
P(subi) gr10, 4, gr10
call EXT(__frv_fixptrs)
/* fixup the .dtors list */
P(sethi) #gprelhi(EXT(__DTOR_LIST__)), gr9
sethi #gprelhi(EXT(__DTOR_END__)), gr10
P(setlo) #gprello(EXT(__DTOR_LIST__)), gr9
setlo #gprello(EXT(__DTOR_END__)), gr10
P(add) gr9, gr16, gr9
add gr10, gr16, gr10
P(addi) gr9, 4, gr9
subi gr10, 4, gr10
call EXT(__frv_fixptrs)
#endif /* ! __FRV_FDPIC__ */
/* fixup the user .rofixup list */
P(sethi) #gprelhi(EXT(__ROFIXUP_LIST__)), gr9
sethi #gprelhi(EXT(__ROFIXUP_END__)), gr10
P(setlo) #gprello(EXT(__ROFIXUP_LIST__)), gr9
setlo #gprello(EXT(__ROFIXUP_END__)), gr10
P(add) gr9, gr16, gr9
add gr10, gr16, gr10
FDPIC(mov gr17, gr15)
call EXT(__frv_fix_usrptrs)
.Lfixed:
/* HSR flags */
#define HSR_ICE 0x80000000 /* Instruction cache enable */
#define HSR_DCE 0x40000000 /* Data cache enable */
#define HSR_CBM 0x08000000 /* Cache copy back mode */
#define HSR_EIMM 0x04000000 /* Enable Instruction MMU */
#define HSR_EDMM 0x02000000 /* Enable Data MMU */
#define HSR_EMEM 0x00800000 /* Enable MMU miss exception mask */
#define HSR_RME 0x00400000 /* Ram mode enable */
#define HSR_SA 0x00001000 /* Start address */
#define HSR_FRN 0x00000800 /* Number of FPRs */
#define HSR_GRN 0x00000400 /* Number of GPRs */
#define HSR_FRHE 0x00000200 /* FR Higher Enable */
#define HSR_FRLE 0x00000100 /* FR Lower Enable */
#define HSR_GRHE 0x00000080 /* GR Higher Enable */
#define HSR_GRLE 0x00000040 /* GR Lower Enable */
#ifndef HSR_CLEAR
#define HSR_CLEAR 0
#endif
#ifndef HSR_SET
#ifndef FRV_NO_CACHE
#define HSR_SET (HSR_ICE|HSR_DCE|HSR_FRHE|HSR_FRLE|HSR_GRHE|HSR_GRLE)
#else
#define HSR_SET (HSR_FRHE|HSR_FRLE|HSR_GRHE|HSR_GRLE)
#endif
#endif
/* PSR flags */
#define PSR_ICE 0x00010000 /* In circuit emulation mode */
#define PSR_NEM 0x00004000 /* Non-exception mode */
#define PSR_CM 0x00002000 /* Conditional mode */
#define PSR_BE 0x00001000 /* Big endian mode */
#define PSR_EF 0x00000100 /* Enable floating point */
#define PSR_EM 0x00000080 /* Enable media instructions */
#define PSR_S 0x00000004 /* Enable supervisor mode */
#define PSR_PS 0x00000002 /* Previous supervisor mode */
#define PSR_ET 0x00000001 /* Enable interrupts */
#ifndef PSR_CLEAR
#if __FRV_FPR__
#define PSR_CLEAR 0
#else
#define PSR_CLEAR (PSR_EF|PSR_EM)
#endif
#endif
#ifndef PSR_SET
#if __FRV_FPR__
#define PSR_SET (PSR_NEM|PSR_CM|PSR_EF|PSR_EM)
#else
#define PSR_SET (PSR_NEM|PSR_CM)
#endif
#endif
/* Enable floating point */
movsg hsr0, gr4
P(sethi) #hi(HSR_SET), gr5
setlo #lo(HSR_SET), gr5
P(sethi) #hi(~HSR_CLEAR), gr6
setlo #lo(~HSR_CLEAR), gr6
or gr4, gr5, gr4
and gr4, gr6, gr4
movgs gr4, hsr0
movsg psr, gr4
P(sethi) #hi(PSR_SET), gr5
setlo #lo(PSR_SET), gr5
P(sethi) #hi(~PSR_CLEAR), gr6
setlo #lo(~PSR_CLEAR), gr6
or gr4, gr5, gr4
and gr4, gr6, gr4
movgs gr4, psr
/* zero the bss area */
P(sethi) #gprelhi(__bss_start), gr8
sethi #gprelhi(__end), gr4
P(setlo) #gprello(__bss_start), gr8
setlo #gprello(__end), gr4
P(add) gr8, gr16, gr8
add gr4, gr16, gr4
P(setlos) #0, gr9
sub gr4, gr8, gr10
FDPIC(mov gr17, gr15)
call EXT(memset)
P(setlos) #0, gr8 /* zero argc, argv, envp */
setlos #0, gr9
P(setlos) #0, gr10
FDPIC(mov gr17, gr15)
call EXT(main)
FDPIC(mov gr17, gr15)
call EXT(exit)
.Lend:
.size __start,(.Lend-__start)
#if ! __FRV_FDPIC__
/* Routine to adjust pointers
gr8 = difference to adjust by
gr9 = starting address
gr10 = ending address + 4
gr11 = amount to add to the pointer each iteration. */
.globl EXT(__frv_fixptrs)
.type EXT(__frv_fixptrs),@function
EXT(__frv_fixptrs):
P(sub) gr9, gr11, gr9
sub gr10, gr11, gr10
.Lloop2:
cmp gr10, gr9, icc0
bls icc0, 0, .Lret2
ldu @(gr9,gr11), gr5
add gr8, gr5, gr5
P(st) gr5, @(gr9,gr0)
bra .Lloop2
.Lret2: ret
.Lend2:
.size EXT(__frv_fixptrs),.Lend2-EXT(__frv_fixptrs)
#endif /* ! __FRV_FDPIC__ */
/* Routine to adjust statically initialized pointers
Note since these are pointers to pointers, they
need to be adjusted themsevles.
gr8 = difference to adjust by
gr9 = starting address
gr10 = ending address + 4
gr11 = amount to add to the pointer each iteration. */
.globl EXT(__frv_fix_usrptrs)
.type EXT(__frv_fix_usrptrs),@function
EXT(__frv_fix_usrptrs):
P(sub) gr9, gr11, gr9
sub gr10, gr11, gr10
.Lloop3:
cmp gr10, gr9, icc0
bls icc0, 0, .Lret3
ldu @(gr9,gr11), gr5
ld @(gr5, gr8), gr6
cmp gr6, gr0, icc0 /* skip pointers initialized to 0 */
beq icc0, 0, .Lloop3
add gr8, gr6, gr6
P(st) gr6, @(gr5,gr8)
bra .Lloop3
.Lret3: ret
.Lend3:
.size EXT(__frv_fix_usrptrs),.Lend2-EXT(__frv_fix_usrptrs)
.section .data
.global __dso_handle
.weak __dso_handle
__dso_handle:
.long 0
|
32bitmicro/newlib-nano-1.0
| 1,056
|
libgloss/frv/sim-close.S
|
/*
* sim-close.S -- close interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File descriptor to close.
*
* Output:
* gr8 -- 0 or -1.
* errno -- Set if an error
*/
.globl EXT(_close)
.type EXT(_close),@function
.weak EXT(close)
.text
EXT(_close):
EXT(close):
setlos #SYS_close,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_close),.Lend-EXT(_close)
|
32bitmicro/newlib-nano-1.0
| 1,140
|
libgloss/frv/sim-lseek.S
|
/*
* sim-lseek.S -- write interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File descriptor
* gr9 -- Offset
* gr10 -- Base from which offset should be taken
*
* Output:
* gr8 -- Zero on success, -1 on failure.
* errno -- Set if an error
*/
.globl EXT(_lseek)
.type EXT(_lseek),@function
.weak EXT(lseek)
.text
EXT(_lseek):
EXT(lseek):
setlos #SYS_lseek,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_lseek),.Lend-EXT(_lseek)
|
32bitmicro/newlib-nano-1.0
| 3,619
|
libgloss/lm32/scall.S
|
/*
* Lattice Mico32 system calls.
* Contributed by Jon Beniston <jon@beniston.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <syscall.h>
/*
* System call convention (as implemented in simulator:
* - System call number in register r8
* - Return value in r1 and r2 (only if 64-bit value)
* - errno in r3
*/
.extern errno
.global _write
_write:
mvi r8, SYS_write
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _read
_read:
mvi r8, SYS_read
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _open
_open:
mvi r8, SYS_open
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _close
_close:
mvi r8, SYS_close
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _lseek
_lseek:
mvi r8, SYS_lseek
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _fstat
_fstat:
mvi r8, SYS_fstat
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _stat
_stat:
mvi r8, SYS_stat
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _link
_link:
mvi r8, SYS_link
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _unlink
_unlink:
mvi r8, SYS_unlink
scall
mvhi r4, hi(errno)
ori r4, r4, lo(errno)
sw (r4+0), r3
ret
.global _exit
_exit:
/* This call doesn't return */
mvi r8, SYS_exit
scall
|
32bitmicro/newlib-nano-1.0
| 2,401
|
libgloss/lm32/crt0.S
|
/*
* Lattice Mico32 C startup code.
* Contributed by Jon Beniston <jon@beniston.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
.section .boot, "ax", @progbits
/* Program starts here */
.global _start
_start:
/* Setup stack and global pointer */
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
mvhi gp, hi(_gp)
ori gp, gp, lo(_gp)
/* Clear BSS */
mvhi r1, hi(_fbss)
ori r1, r1, lo(_fbss)
mvi r2, 0
mvhi r3, hi(_ebss)
ori r3, r3, lo(_ebss)
sub r3, r3, r1
calli memset
/* Call C++ constructors */
calli _init
/* Call C++ destructors on exit */
mvhi r1, hi(_fini)
ori r1, r1, lo(_fini)
calli atexit
/* Call main program */
mvi r1, 0
mvi r2, 0
mvi r3, 0
calli main
/* Call exit, which doesn't return, to perform any clean up */
calli exit
|
32bitmicro/newlib-nano-1.0
| 1,055
|
libgloss/moxie/sim-read.S
|
/*
* sim-read.S -- read interface for moxie simulator
*
* Copyright (c) 2008 Anthony Green
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "syscall.h"
/*
* Input:
* $r0 -- File descriptor.
* $r1 -- Buffer to be read into.
* -0x12($fp) -- Length of the buffer.
*
* Output:
* $r0 -- Length read or -1.
* errno -- Set if an error
*/
.globl _read
.type _read,@function
.weak read
.text
_read:
read:
swi SYS_read
ret
.Lend:
.size _read,.Lend-_read
|
32bitmicro/newlib-nano-1.0
| 1,075
|
libgloss/moxie/sim-open.S
|
/*
* sim-open.S -- open interface for moxie simulator
*
* Copyright (c) 2008 Anthony Green
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "syscall.h"
/*
* Input:
* $r0 -- File name to open.
* $r1 -- open mode.
* -0x12($fp) -- optionally, the permission bits to set the file to.
*
* Output:
* $r0 -- file descriptor or -1.
* errno -- Set if an error
*/
.globl _open
.type _open,@function
.weak open
.text
_open:
open:
swi SYS_open
ret
.Lend:
.size _open,.Lend-_open
|
32bitmicro/newlib-nano-1.0
| 1,062
|
libgloss/moxie/sim-write.S
|
/*
* sim-write.S -- write interface for moxie simulator
*
* Copyright (c) 2008 Anthony Green
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "syscall.h"
/*
* Input:
* $r0 -- File descriptor.
* $r1 -- String to be printed.
* -0x12($fp) -- Length of the string.
*
* Output:
* $r0 -- Length written or -1.
* errno -- Set if an error
*/
.globl _write
.type _write,@function
.weak write
.text
_write:
write:
swi SYS_write
ret
.Lend:
.size _write,.Lend-_write
|
32bitmicro/newlib-nano-1.0
| 1,409
|
libgloss/moxie/crt0.S
|
/* crt0.S -- startup file for moxie
*
* Copyright (c) 2008, 2009 Anthony Green
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
.globl __start
.weak _start
.text
.type __start,@function
__start:
_start:
ldi.l $sp, (_stack-12)/* load up stack pointer with space
for stack frame. */
xor $fp, $fp /* zero fp to allow unwinders to stop */
/* zero the bss area */
ldi.l $r0, __bss_start__
ldi.l $r1, __bss_end__
sub.l $r1, $r0
sto.l 8($sp), $r1
ldi.l $r1, 0
jsra memset
inc $sp, 12
/* Call _init to invoke static constructors, etc. */
jsra _init
/* Call _fini at exit time for static destructors. */
ldi.l $r0, _fini
jsra atexit
/* Set argc and argv. These are populated by the simulator. */
lda.l $r0, 0x4
ldi.l $r1, 0x8
jsra main
jsra exit
.Lend:
.size __start,(.Lend-__start)
|
32bitmicro/newlib-nano-1.0
| 3,152
|
libgloss/microblaze/pgcrtinit.S
|
## Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are
## met:
##
## 1. Redistributions source code must retain the above copyright notice,
## this list of conditions and the following disclaimer.
##
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## 3. Neither the name of Xilinx nor the names of its contributors may be
## used to endorse or promote products derived from this software without
## specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
## TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
## PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
## HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
## TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
.globl _crtinit
.align 2
.ent _crtinit
_crtinit:
addi r1, r1, -20 /* Save Link register */
swi r15, r1, 0
addi r6, r0, __sbss_start /* clear SBSS */
addi r7, r0, __sbss_end
rsub r18, r6, r7
blei r18, .Lendsbss
.Lloopsbss:
swi r0, r6, 0
addi r6, r6, 4
rsub r18, r6, r7
bgti r18, .Lloopsbss
.Lendsbss:
addi r6, r0, __bss_start /* clear BSS */
addi r7, r0, __bss_end
rsub r18, r6, r7
blei r18, .Lendbss
.Lloopbss:
swi r0, r6, 0
addi r6, r6, 4
rsub r18, r6, r7
bgti r18, .Lloopbss
.Lendbss:
brlid r15, _program_init /* Initialize the program */
nop
brlid r15, _profile_init /* Initialize profiling library */
nop
brlid r15, __init /* Invoke language initialization functions */
nop
addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */
addi r7, r0, 0
brlid r15, main /* Execute the program */
addi r5, r0, 0
addik r19, r3, 0 /* Save return value */
brlid r15, __fini /* Invoke language cleanup functions */
nop
brlid r15, _profile_clean /* Cleanup profiling library */
nop
brlid r15, _program_clean /* Cleanup the program */
nop
lw r15, r1, r0 /* Return back to CRT */
addik r3, r19, 0 /* Restore return value */
rtsd r15, 8
addi r1, r1, 20
.end _crtinit
|
32bitmicro/newlib-nano-1.0
| 1,696
|
libgloss/microblaze/_hw_exception_handler.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.text
.globl _hw_exception_handler # HW Exception Handler Label
.align 2
_hw_exception_handler:
rted r17, 0
nop
|
32bitmicro/newlib-nano-1.0
| 3,158
|
libgloss/microblaze/crt4.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
MicroBlaze Vector Map for Xilkernel ELF process images
Address Vector type Label
------- ----------- ------
# 0x00 # (-- IMM --)
# 0x04 # Reset (-- Don't Care --)
# 0x08 # (-- IMM --)
# 0x0c # Software Exception (-- Don't Care --)
# 0x10 # (-- IMM --)
# 0x14 # Hardware Interrupt (-- Don't Care --)
# 0x18 # (-- IMM --)
# 0x1C # Breakpoint Exception (-- Don't Care --)
# 0x20 # (-- IMM --)
# 0x24 # Hardware Exception (-- Don't Care --)
*/
.section .text
.globl _start
.align 2
.ent _start
.type _start, @function
_start:
la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */
la r2, r0, _SDA2_BASE_
la r1, r0, _stack-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */
brlid r15, _crtinit /* Initialize BSS and run program */
nop
brlid r15, exit /* Call exit with the return value of main */
addik r5, r3, 0
/* Control does not reach here */
.end _start
/*
_exit
Our simple _exit
*/
.globl _exit
.align 2
.ent _exit
.type _exit, @function
_exit:
brlid r15,elf_process_exit
nop
.end _exit
|
32bitmicro/newlib-nano-1.0
| 1,745
|
libgloss/microblaze/_program_clean.S
|
## Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are
## met:
##
## 1. Redistributions source code must retain the above copyright notice,
## this list of conditions and the following disclaimer.
##
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## 3. Neither the name of Xilinx nor the names of its contributors may be
## used to endorse or promote products derived from this software without
## specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
## TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
## PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
## HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
## TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# _program_clean.s
#
# Dummy file to be replaced by LibGen
#
.text
.align 2
.globl _program_clean
.ent _program_clean
_program_clean:
rtsd r15,8
nop
.end _program_clean
|
32bitmicro/newlib-nano-1.0
| 3,007
|
libgloss/microblaze/crtinit.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.globl _crtinit
.align 2
.ent _crtinit
.type _crtinit, @function
_crtinit:
addi r1, r1, -20 /* Save Link register */
swi r15, r1, 0
addi r6, r0, __sbss_start /* clear SBSS */
addi r7, r0, __sbss_end
rsub r18, r6, r7
blei r18, .Lendsbss
.Lloopsbss:
swi r0, r6, 0
addi r6, r6, 4
rsub r18, r6, r7
bgti r18, .Lloopsbss
.Lendsbss:
addi r6, r0, __bss_start /* clear BSS */
addi r7, r0, __bss_end
rsub r18, r6, r7
blei r18, .Lendbss
.Lloopbss:
swi r0, r6, 0
addi r6, r6, 4
rsub r18, r6, r7
bgti r18, .Lloopbss
.Lendbss:
brlid r15, _program_init /* Initialize the program */
nop
brlid r15, __init /* Invoke language initialization functions */
nop
addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */
addi r7, r0, 0
brlid r15, main /* Execute the program */
addi r5, r0, 0
addik r19, r3, 0 /* Save return value */
brlid r15, __fini /* Invoke language cleanup functions */
nop
brlid r15, _program_clean /* Cleanup the program */
nop
lw r15, r1, r0 /* Return back to CRT */
addik r3, r19, 0 /* Restore return value */
rtsd r15, 8
addi r1, r1, 20
.end _crtinit
|
32bitmicro/newlib-nano-1.0
| 3,537
|
libgloss/microblaze/crt2.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
MicroBlaze Vector Map for standalone executables that are boot-strapped
Address Vector type Label
------- ----------- ------
# 0x00 # (-- IMM --)
# 0x04 # Reset (-- Don't Care --)
# 0x08 # (-- IMM --)
# 0x0c # Software Exception _exception_handler
# 0x10 # (-- IMM --)
# 0x14 # Hardware Interrupt _interrupt_handler
# 0x18 # (-- IMM --)
# 0x1C # Breakpoint Exception (-- Don't Care --)
# 0x20 # (-- IMM --)
# 0x24 # Hardware Exception _hw_exception_handler
*/
.section .vectors.sw_exception, "ax"
.align 2
_vector_sw_exception:
brai _exception_handler
.section .vectors.interrupt, "ax"
.align 2
_vector_interrupt:
brai _interrupt_handler
.section .vectors.hw_exception, "ax"
.align 2
_vector_hw_exception:
brai _hw_exception_handler
.section .text
.globl _start
.align 2
.ent _start
.type _start, @function
_start:
la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */
la r2, r0, _SDA2_BASE_
la r1, r0, _stack-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */
brlid r15, _crtinit /* Initialize BSS and run program */
nop
brlid r15, exit /* Call exit with the return value of main */
addik r5, r3, 0
/* Control does not reach here */
.end _start
/*
_exit
Our simple _exit
*/
.globl _exit
.align 2
.ent _exit
.type _exit, @function
_exit:
bri 0
.end _exit
|
32bitmicro/newlib-nano-1.0
| 1,738
|
libgloss/microblaze/_program_init.S
|
## Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are
## met:
##
## 1. Redistributions source code must retain the above copyright notice,
## this list of conditions and the following disclaimer.
##
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## 3. Neither the name of Xilinx nor the names of its contributors may be
## used to endorse or promote products derived from this software without
## specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
## TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
## PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
## HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
## TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# _program_init.s
#
# Dummy file to be replaced by LibGen
.text
.align 2
.globl _program_init
.ent _program_init
_program_init:
rtsd r15,8
nop
.end _program_init
|
32bitmicro/newlib-nano-1.0
| 3,674
|
libgloss/microblaze/crt0.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
MicroBlaze Vector Map for standalone executables
Address Vector type Label
------- ----------- ------
# 0x00 # (-- IMM --)
# 0x04 # Reset _start1
# 0x08 # (-- IMM --)
# 0x0c # Software Exception _exception_handler
# 0x10 # (-- IMM --)
# 0x14 # Hardware Interrupt _interrupt_handler
# 0x18 # (-- IMM --)
# 0x1C # Breakpoint Exception (-- Don't Care --)
# 0x20 # (-- IMM --)
# 0x24 # Hardware Exception _hw_exception_handler
*/
.globl _start
.section .vectors.reset, "ax"
.align 2
.ent _start
.type _start, @function
_start:
brai _start1
.end _start
.section .vectors.sw_exception, "ax"
.align 2
_vector_sw_exception:
brai _exception_handler
.section .vectors.interrupt, "ax"
.align 2
_vector_interrupt:
brai _interrupt_handler
.section .vectors.hw_exception, "ax"
.align 2
_vector_hw_exception:
brai _hw_exception_handler
.section .text
.globl _start1
.align 2
.ent _start1
.type _start1, @function
_start1:
la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */
la r2, r0, _SDA2_BASE_
la r1, r0, _stack-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */
brlid r15, _crtinit /* Initialize BSS and run program */
nop
brlid r15, exit /* Call exit with the return value of main */
addik r5, r3, 0
/* Control does not reach here */
.end _start1
/*
_exit
Our simple _exit
*/
.globl _exit
.align 2
.ent _exit
.type _exit, @function
_exit:
bri 0
.end _exit
|
32bitmicro/newlib-nano-1.0
| 1,687
|
libgloss/microblaze/_exception_handler.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.text
.globl _exception_handler # Exception Handler Label
.align 2
_exception_handler:
rtsd r17, 0
nop
|
32bitmicro/newlib-nano-1.0
| 2,767
|
libgloss/microblaze/sim-pgcrtinit.S
|
## Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are
## met:
##
## 1. Redistributions source code must retain the above copyright notice,
## this list of conditions and the following disclaimer.
##
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## 3. Neither the name of Xilinx nor the names of its contributors may be
## used to endorse or promote products derived from this software without
## specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
## TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
## PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
## HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
## TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# sim-pgcrtinit.s
#
# Default second stage of C run-time initialization for use with software
# intrusive profiling. Does not peform BSS initialization to zero.
# (Typical use is on a simulator)
#
.globl _crtinit
.align 2
.ent _crtinit
_crtinit:
addi r1, r1, -20 /* Save Link register */
swi r15, r1, 0
brlid r15, _program_init /* Initialize the program */
nop
brlid r15, _profile_init /* Initialize profiling library */
nop
brlid r15, __init /* Invoke language initialization functions */
nop
addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */
addi r7, r0, 0
brlid r15, main /* Execute the program */
addi r5, r0, 0
brlid r15, __fini /* Invoke language cleanup functions */
nop
brlid r15, _profile_clean /* Cleanup profiling library */
nop
brlid r15, _program_clean /* Cleanup the program */
nop
lw r15, r1, r0 /* Return back to CRT */
rtsd r15, 8
addi r1, r1, 20
.end _crtinit
|
32bitmicro/newlib-nano-1.0
| 3,633
|
libgloss/microblaze/crt1.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
MicroBlaze Vector Map for standalone executables
downloaded and executed with XMDSTUB
Address Vector type Label
------- ----------- ------
# 0x00 # (-- IMM --)
# 0x04 # Reset (-- Don't Care --)
# 0x08 # (-- IMM --)
# 0x0c # Software Exception _exception_handler
# 0x10 # (-- IMM --)
# 0x14 # Hardware Interrupt _interrupt_handler
# 0x18 # (-- IMM --)
# 0x1C # Breakpoint Exception (-- Don't Care --)
# 0x20 # (-- IMM --)
# 0x24 # Hardware Exception _hw_exception_handler
*/
.section .vectors.sw_exception, "ax"
.align 2
_vector_sw_exception:
brai _exception_handler
.section .vectors.interrupt, "ax"
.align 2
_vector_interrupt:
brai _interrupt_handler
.section .vectors.hw_exception, "ax"
.align 2
_vector_hw_exception:
brai _hw_exception_handler
.section .text
.globl _start
.align 2
.ent _start
.type _start, @function
_start:
la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */
la r2, r0, _SDA2_BASE_
la r1, r0, _stack-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */
brlid r15, _crtinit /* Initialize BSS and run program */
nop
brlid r15, exit /* Call exit with the return value of main */
addik r5, r3, 0
/* Control does not reach here */
.end _start
/*
_exit
Our simple _exit
*/
.globl _exit
.align 2
.ent _exit
.type _exit, @function
_exit:
add r3, r0, r5
brki r16, 0x4 /* Return to hook in XMDSTUB */
.end _exit
|
32bitmicro/newlib-nano-1.0
| 1,686
|
libgloss/microblaze/_interrupt_handler.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.text
.globl _interrupt_handler # Interrupt Handler Label
.align 2
_interrupt_handler:
rtid r14, 0
nop
|
32bitmicro/newlib-nano-1.0
| 2,699
|
libgloss/microblaze/sim-crtinit.S
|
## Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are
## met:
##
## 1. Redistributions source code must retain the above copyright notice,
## this list of conditions and the following disclaimer.
##
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## 3. Neither the name of Xilinx nor the names of its contributors may be
## used to endorse or promote products derived from this software without
## specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
## TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
## PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
## HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
## TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# sim-crtinit.s
#
# Default second stage of C run-time initialization that does not peform
# BSS initialization to zero. Typical use is on a simulator.
#
.globl _crtinit
.align 2
.ent _crtinit
_crtinit:
addi r1, r1, -20 /* Save Link register */
swi r15, r1, 0
brlid r15, _program_init /* Initialize the program */
nop
brlid r15, __init /* Invoke language initialization functions */
nop
addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */
addi r7, r0, 0
brlid r15, main /* Execute the program */
addi r5, r0, 0
addik r19, r3, 0 /* Save return value */
brlid r15, __fini /* Invoke language cleanup functions */
nop
brlid r15, _program_clean /* Cleanup the program */
nop
lw r15, r1, r0 /* Return back to CRT */
addik r3, r19, 0 /* Restore return value */
rtsd r15, 8
addi r1, r1, 20
.end _crtinit
|
32bitmicro/newlib-nano-1.0
| 3,124
|
libgloss/microblaze/crt3.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
MicroBlaze Vector Map for vector-less ELF images
Address Vector type Label
------- ----------- ------
# 0x00 # (-- IMM --)
# 0x04 # Reset (-- Don't Care --)
# 0x08 # (-- IMM --)
# 0x0c # Software Exception (-- Don't Care --)
# 0x10 # (-- IMM --)
# 0x14 # Hardware Interrupt (-- Don't Care --)
# 0x18 # (-- IMM --)
# 0x1C # Breakpoint Exception (-- Don't Care --)
# 0x20 # (-- IMM --)
# 0x24 # Hardware Exception (-- Don't Care --)
*/
.section .text
.globl _start
.align 2
.ent _start
.type _start, @function
_start:
la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */
la r2, r0, _SDA2_BASE_
la r1, r0, _stack-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */
brlid r15, _crtinit /* Initialize BSS and run program */
nop
brlid r15, exit /* Call exit with the return value of main */
addik r5, r3, 0
/* Control does not reach here */
.end _start
/*
_exit
Our simple _exit
*/
.globl _exit
.align 2
.ent _exit
.type _exit, @function
_exit:
bri 0
.end _exit
|
32bitmicro/newlib-nano-1.0
| 1,301
|
libgloss/v850/crt0.S
|
# NEC V850 startup code
.section .text
.global _start
_start:
#if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__)
movea 255, r0, r20
mov 65535, r21
mov hilo(_stack), sp
mov hilo(__ep), ep
mov hilo(__gp), gp
mov hilo(__ctbp), r6
ldsr r6, ctbp
mov hilo(_edata), r6
mov hilo(_end), r7
.L0:
st.w r0, 0[r6]
addi 4, r6, r6
cmp r7, r6
bl .L0
.L1:
jarl ___main, r31
addi -16, sp, sp
mov 0, r6
mov 0, r7
mov 0, r8
jarl _main, r31
mov r10, r6
jarl _exit, r31
# else
movea 255, r0, r20
mov r0, r21
ori 65535, r0, r21
movhi hi(_stack), r0, sp
movea lo(_stack), sp, sp
movhi hi(__ep), r0, ep
movea lo(__ep), ep, ep
movhi hi(__gp), r0, gp
movea lo(__gp), gp, gp
movhi hi(_edata), r0, r6
movea lo(_edata), r6, r6
movhi hi(_end), r0, r7
movea lo(_end), r7, r7
.L0:
st.b r0, 0[r6]
addi 1, r6, r6
cmp r7, r6
bl .L0
.L1:
jarl ___main, r31
addi -16, sp, sp
mov 0, r6
mov 0, r7
mov 0, r8
jarl _main, r31
mov r10, r6
jarl _exit, r31
# endif
.section .stack
_stack: .long 1
.section .data
.global ___dso_handle
.weak ___dso_handle
___dso_handle:
.long 0
|
32bitmicro/newlib-nano-1.0
| 1,856
|
libgloss/m32c/crtn.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
#define A16
#define A(n,w) n
#define W w
#else
#define A24
#define A(n,w) w
#define W l
#endif
.section .init,"ax",@progbits
jsr.a _m32c_run_preinit_array
jsr.a _m32c_run_init_array
exitd
.global __m32c_init_end
__m32c_init_end:
.section .fini,"ax",@progbits
exitd
.global __m32c_fini_end
__m32c_fini_end:
.text
|
32bitmicro/newlib-nano-1.0
| 1,509
|
libgloss/m32c/stat.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(stat)
|
32bitmicro/newlib-nano-1.0
| 1,510
|
libgloss/m32c/lseek.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(lseek)
|
32bitmicro/newlib-nano-1.0
| 1,509
|
libgloss/m32c/time.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(time)
|
32bitmicro/newlib-nano-1.0
| 1,510
|
libgloss/m32c/write.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(write)
|
32bitmicro/newlib-nano-1.0
| 1,510
|
libgloss/m32c/times.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(times)
|
32bitmicro/newlib-nano-1.0
| 1,510
|
libgloss/m32c/utime.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(utime)
|
32bitmicro/newlib-nano-1.0
| 1,510
|
libgloss/m32c/chdir.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(chdir)
|
32bitmicro/newlib-nano-1.0
| 1,525
|
libgloss/m32c/isatty.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.global _isatty
_isatty:
mov.w #1,r0
rts
|
32bitmicro/newlib-nano-1.0
| 1,509
|
libgloss/m32c/open.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(open)
|
32bitmicro/newlib-nano-1.0
| 1,509
|
libgloss/m32c/link.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(link)
|
32bitmicro/newlib-nano-1.0
| 1,588
|
libgloss/m32c/exit.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
.global __exit
__exit:
pushm r0,r1
jsr.a __m32c_fini
popm r0,r1
SYSCALL(SYS_exit)
|
32bitmicro/newlib-nano-1.0
| 1,509
|
libgloss/m32c/argv.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(argv)
|
32bitmicro/newlib-nano-1.0
| 1,509
|
libgloss/m32c/kill.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(kill)
|
32bitmicro/newlib-nano-1.0
| 1,509
|
libgloss/m32c/read.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(read)
|
32bitmicro/newlib-nano-1.0
| 1,510
|
libgloss/m32c/close.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(close)
|
32bitmicro/newlib-nano-1.0
| 1,511
|
libgloss/m32c/getpid.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(getpid)
|
32bitmicro/newlib-nano-1.0
| 1,545
|
libgloss/m32c/heaptop.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
#define SYS__set_heaptop 11
S(_set_heaptop)
|
32bitmicro/newlib-nano-1.0
| 4,301
|
libgloss/m32c/crt0.S
|
/*
Copyright (c) 2005,2008 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
#define A16
#define A(n,w) n
#define W w
#define ALIGN 1
#else
#define A24
#define A(n,w) w
#define W l
#define ALIGN 2
#endif
.section ".resetvec","ax",@progbits
.long _start
.text
.global _start
_start:
.LFB2:
fclr U /* One stack for user and interrupts */
ldc #__stack,sp
#ifdef A16
mov.b #%hi8(__romdatastart),r1h
mov.w #%lo16(__romdatastart),a0
mov.w #__datastart,a1
#else
mov.l #__romdatastart,a0
mov.l #__datastart,a1
#endif
mov.w #__romdatacopysize,r3
shl.w #-1,r3
smovf.w
#ifdef A16
mov.w #__bssstart,a1
#else
mov.l #__bssstart,a1
#endif
mov.w #__bsssize,r3
shl.w #-1,r3
mov.w #0,r0
sstr.w
#ifdef A16
ldc #%lo16(__var_vects),intbl
ldc #%hi16(__var_vects),intbh
#else
ldc #__var_vects,intb
#endif
fset I
jsr.a __m32c_init
jsr.a _main
.LFE2:
#ifdef A24
/* rv in r0, ok for arg0 */
#else
mov.w r0,r1
#endif
jsr.a _exit
.text
.global _m32c_run_preinit_array
.type _m32c_run_preinit_array,@function
_m32c_run_preinit_array:
mov.W #__preinit_array_start,a0
mov.W #__preinit_array_end,a1
jmp.w _m32c_run_inilist
.global _m32c_run_init_array
.type _m32c_run_init_array,@function
_m32c_run_init_array:
mov.W #__init_array_start,a0
mov.W #__init_array_end,a1
jmp.w _m32c_run_inilist
.global _m32c_run_fini_array
.type _m32c_run_fini_array,@function
_m32c_run_fini_array:
mov.W #__fini_array_start,a0
mov.W #__fini_array_end,a1
/* fall through */
_m32c_run_inilist:
next_inilist:
cmp.W a0,a1
jeq done_inilist
pushm a0,a1
mov.W [a0],a0
#ifdef A16
mov.b:s #0,a1 /* zero extends */
jsri.a a1a0
#else
jsri.a a0
#endif
popm a0,a1
add.W A(#2,#4),a0
jmp.b next_inilist
done_inilist:
rts
.section .init,"ax",@progbits
.global __m32c_init
__m32c_init:
enter #0
.section .fini,"ax",@progbits
.global __m32c_fini
__m32c_fini:
enter #0
jsr.a _m32c_run_fini_array
;;; Provide Dwarf unwinding information that will help GDB stop
;;; backtraces at the right place. This is stolen from assembly
;;; code generated by GCC with -dA.
.section .debug_frame,"",@progbits
.Lframe0:
.4byte .LECIE0-.LSCIE0 ; Length of Common Information Entry
.LSCIE0:
.4byte 0xffffffff ; CIE Identifier Tag
.byte 0x1 ; CIE Version
.ascii "\0" ; CIE Augmentation
.uleb128 0x1 ; CIE Code Alignment Factor
.sleb128 -1 ; CIE Data Alignment Factor
.byte 0xd ; CIE RA Column
.byte 0xc ; DW_CFA_def_cfa
.uleb128 0xc
.uleb128 0x3
.byte 0x8d ; DW_CFA_offset, column 0xd
.uleb128 0x3
.p2align ALIGN
.LECIE0:
.LSFDE0:
.4byte .LEFDE0-.LASFDE0 ; FDE Length
.LASFDE0:
.4byte .Lframe0 ; FDE CIE offset
.4byte .LFB2 ; FDE initial location
.4byte .LFE2-.LFB2 ; FDE address range
.byte 0xf ; DW_CFA_def_cfa_expression
.uleb128 1 ; length of expression
.byte 0x30 ; DW_OP_lit0
.p2align ALIGN
.LEFDE0:
.text
|
32bitmicro/newlib-nano-1.0
| 1,655
|
libgloss/m32c/varvects.S
|
/*
Copyright (c) 2008 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* This works with varvects.h
*/
.section ".var_vects","aw",@progbits
.global __var_vects
.type __var_vects,@object
.size __var_vects, 256
__var_vects:
.zero 256
.text
|
32bitmicro/newlib-nano-1.0
| 1,512
|
libgloss/m32c/argvlen.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(argvlen)
|
32bitmicro/newlib-nano-1.0
| 1,510
|
libgloss/m32c/fstat.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(fstat)
|
32bitmicro/newlib-nano-1.0
| 1,517
|
libgloss/m32c/gettimeofday.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(gettimeofday)
|
32bitmicro/newlib-nano-1.0
| 1,799
|
libgloss/m32c/abort.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
.global _abort
_abort:
/* This is for debuggers. The simulator stops here too. */
brk
/* Else, fall back on the simulator's "kill me" option. */
#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
mov.w #42,r1
#else
mov.w #42,r0
#endif
SYSCALL(SYS_kill)
/* Else, exit. */
jmp.a __exit
|
32bitmicro/newlib-nano-1.0
| 1,510
|
libgloss/m32c/chmod.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(chmod)
|
32bitmicro/newlib-nano-1.0
| 1,511
|
libgloss/m32c/unlink.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(unlink)
|
32bitmicro/newlib-nano-1.0
| 2,536
|
libgloss/spu/crtn.S
|
# (C) Copyright IBM Corp. 2005, 2006
#
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# * Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of IBM nor the names of its contributors may be
# used to endorse or promote products derived from this software without
# specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This file just makes sure that the .fini and .init sections do in
# fact return. Users may put any desired instructions in those sections.
# This file is the last thing linked into any executable.
# Note - this macro is complimented by the FUNC_START macro
# in crti.S. If you change this macro you must also change
# that macro match.
#
# Note - we do not try any fancy optimisations of the return
# sequences here, it is just not worth it. Instead keep things
# simple. The link register is restored and then the correct
# function return instruction is performed.
.macro FUNC_END
ai $sp, $sp, 32
lqd $lr, 16($sp)
bi $lr
.endm
.file "crtn.S"
.section ".init"
FUNC_END
.section ".fini"
FUNC_END
# To ensure nothing is linked at address 0, provide a dummy
# .interrupt section. This is in crtn.S to make sure any
# user-provided real .interrupt section will get linked
# in front of this dummy.
.section ".interrupt","ax"
.align 2
heq $0,$0
# end of crtn.S
|
32bitmicro/newlib-nano-1.0
| 2,289
|
libgloss/spu/crti.S
|
# (C) Copyright IBM Corp. 2005, 2006
#
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# * Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of IBM nor the names of its contributors may be
# used to endorse or promote products derived from this software without
# specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# This file just make a stack frame for the contents of the .fini and
# .init sections. Users may put any desired instructions in those
# sections.
# Note - this macro is complimented by the FUNC_END macro
# in crtn.S. If you change this macro you must also change
# that macro match.
.macro FUNC_START
# Create a stack frame with two slots: LR and BC
# The .init and .fini section don't change the call-preserved
# registes, therefore no need to save them.
stqd $lr, 16($sp)
stqd $sp, -32($sp)
ai $sp, $sp, -32
.endm
.file "crti.S"
.section ".init"
.align 2
.global _init
.type _init, @function
_init:
FUNC_START
.section ".fini"
.align 2
.global _fini
.type _fini, @function
_fini:
FUNC_START
|
32bitmicro/newlib-nano-1.0
| 4,926
|
libgloss/spu/crt0.S
|
/* (C) Copyright IBM Corp. 2005, 2006
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of IBM nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* crt0.S - entry function for C Runtime.
*
* With _STD_MAIN switch, the crt0.S will be compiled to crt2.o.
* The crt2.o sets up a C99-style interface for the SPU application's
* main() function, including a local copy of argv strings.
*
* The number of argument strings is passed in R3. The size and EA
* location of the argument vector region is passed in R4. Once the
* argv region is copied to the highest range of LS, and $SP is set
* just below it.
*
* Without _STD_MAIN, the crt0.S is compiled to crt1.o.
* The crt1.o prepares the entry for an SPU module. The main() function
* is called with different parameter list: spu_id, param and env
* are passed by R3, R4 and R5 respectively.
*/
#ifdef _STD_MAIN
#define MFC_TAG_UPDATE_ALL 2
#define MFC_GET_CMD 0x40
#define TAGID 0
#define TAGMASK 1
#endif
.comm __ea_local_store,16,16
.text
.global _start
.type _start, @function
_start:
/* Save the local store base from $6. */
stqr $6, __ea_local_store
#ifdef _STD_MAIN
/*
* Copy the argument vector region from EA to LS. The DMA
* parameters are passed in R4:
*
* +-------+-------+-------+-------+
* R4 | LS | EA-HI | EA-LO | SIZE |
* +-------+-------+-------+-------+
* word 0 1 2 3
*
* By the end of this sequence, the prefered slot (word 0) of
* R4 will contain the LS offset of argv region, which also
* serves as the base offset for $SP.
*/
wrch $MFC_LSA, $4
rotqbyi $4, $4, 4
wrch $MFC_EAH, $4
rotqbyi $4, $4, 4
wrch $MFC_EAL, $4
rotqbyi $4, $4, 4
wrch $MFC_Size, $4
rotqbyi $4, $4, 4
il $LR, TAGID
wrch $MFC_TagID, $LR
/* Issue MFC_GET_CMD, then wait for transfer of argument
* vector region to complete.
*/
il $LR, MFC_GET_CMD
wrch $MFC_Cmd, $LR
il $LR, TAGMASK
wrch $MFC_WrTagMask, $LR
il $LR, MFC_TAG_UPDATE_ALL
wrch $MFC_WrTagUpdate, $LR
rdch $LR, $MFC_RdTagStat
#endif
/* Save parameter list of main function to the non-volatile
* registers. spu_thread module has three parameters, while
* spulet only has two.
*/
ori $80, $3, 0
ori $81, $4, 0
#ifndef _STD_MAIN
ori $82, $5, 0
#endif
/* The Link Register is initialized to NULL.
*/
il $LR, 0
#ifdef _STD_MAIN
/* For spulet, initialize stack pointer just below the argv region.
*/
ai $SP,$4,-16
#else
/* For spe_thread module, the stack pointer is initialized
* below the area where __stack points to.
*/
ila $SP,__stack
#endif
/* Initialize back chain to NULL.
*/
stqd $LR,0($SP)
/* Allocate 2 slots for stack frame.
*/
stqd $SP,-32($SP)
ai $SP,$SP,-32
/* Save the Link Register in Link Register Save Area.
*/
stqd $LR,16($SP)
/* Calculate stack size.
*/
ila $3,_end
sf $3,$3,$SP
rotqbyi $3,$3,12
/* The BE Linux ABI passes the stack size in $2, or use
* the default if $2 == 0.
*/
rotqbyi $4,$2,12
ceqi $5,$4,0
selb $3,$4,$3,$5
fsmbi $4,3840
selb $SP,$SP,$3,$4
/* Call the _init function.
*/
brsl $LR, _init
/* Call the _fini function at exit time.
*/
ila $3, _fini
brsl $LR, atexit
#ifdef _PROFILE
/* Call monstartup if profiling is enabled
*/
#ifdef _STD_MAIN
ila $3,0
#else
ori $3,$80,0
#endif
brsl $LR, __monstartup
#endif
ori $3,$80,0
ori $4,$81,0
#ifndef _STD_MAIN
ori $5,$82,0
#endif
/* Call the programs main.
*/
brsl $LR, main
/* Call exit.
*/
brsl $LR, exit
|
32bitmicro/newlib-nano-1.0
| 1,322
|
libgloss/sparc/crt0-701.S
|
/* crt0.S for the sparclet 701.
At the moment, all the necessary syscalls are here.
Convention has them in a separate file but libgloss is still in
too much flux. */
.text
.global start
start:
! zero bss
sethi %hi(_end), %o1
or %o1, %lo(_end), %o1
sethi %hi(_edata), %o0
or %o0, %lo (_edata), %o0
sub %o1, %o0, %o1
Lzero_bss:
subcc %o1, 4, %o1
clr [%o0]
bne Lzero_bss
add %o0, 4, %o0
! set up argc, argv, envp (?)
ld [%sp+64], %o0
sll %o0, 2, %o2
add %o2, 4, %o2
add %sp, 68, %o1
add %o1, %o2, %o2
sethi %hi(_environ), %o3
st %o2, [%o3+%lo(_environ)]
! call main, exit
call _main
sub %sp, 32, %sp
call _exit
nop
! void _exit (int rc)
.global __exit
__exit:
mov 1, %g1
ta 0
! If that does not work, just loop forever.
Lloop_forever:
b Lloop_forever
nop
! int _open (char *, int)
.global _open
_open:
mov 5, %g1
ta 0
bcc Lnoerr
nop
b Lcerror
nop
! int _close (int)
.global _close
_close:
mov 6, %g1
ta 0
bcc Lnoerr
nop
b Lcerror
nop
! int read (int, char *, int)
.global _read
_read:
mov 3, %g1
ta 0
bcc Lnoerr
nop
b Lcerror
nop
! int write (int, char *, int)
.global _write
_write:
mov 4, %g1
ta 0
bcc Lnoerr
nop
b Lcerror
nop
Lnoerr:
retl
nop
Lcerror:
sethi %hi(__impure_ptr), %g1
st %o0, [%g1+%lo(__impure_ptr)]
retl
mov -1, %o0
|
32bitmicro/newlib-nano-1.0
| 4,341
|
libgloss/sparc/crt0.S
|
/*
* C startup code for the Fujitsu SPARClite demo board
*
* Copyright (c) 1995, 1996 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
.data
.align 8
.ascii "DaTa" ! this is the first address in the data section
.long SYM(sdata)
SYM(environ):
.long 0
.text
.align 8
.globl SYM(_start)
SYM(_start):
.globl SYM(start)
SYM(start):
/* see if the stack is already setup. if not, then default
* to using the value of %sp as set by the ROM monitor
*/
sethi %hi(__stack), %g1
or %g1,%lo(__stack),%g1
cmp %g0,%g1
be 1f
mov %g1, %sp ! set the stack pointer
mov %sp, %fp
1:
/* zero the bss section */
sethi %hi(__bss_start),%g2
or %g2,%lo(__bss_start),%g2 ! start of bss
sethi %hi(_end),%g3
or %g3,%lo(_end),%g3 ! end of bss
mov %g0,%g1 ! so std has two zeros
zerobss:
std %g0,[%g2]
add %g2,8,%g2
cmp %g2,%g3
bleu,a zerobss
nop
/*
* copy prom & trap vectors to sram.
*/
set 0x30000000, %l0
set 0xfff8, %l1
tst %l1 ! Set condition codes
copyloop:
ldd [%l1], %l2
std %l2, [%l0 + %l1]
bg copyloop
deccc 8, %l1
set 0x30000000, %l0 ! Base of new trap vector
mov %l0, %tbr ! Install the new tbr
set SYM(win_ovf_trap), %l1 ! Setup window overflow trap
ldd [%l1], %l2
std %l2, [%l0 + 5 * 16]
ldd [%l1 + 8], %l2
std %l2, [%l0 + 5 * 16 + 8]
set SYM(win_unf_trap), %l1 ! Setup window underflow trap
ldd [%l1], %l2
std %l2, [%l0 + 6 * 16]
ldd [%l1 + 8], %l2
std %l2, [%l0 + 6 * 16 + 8]
/*
* Try enabling the FPU by setting EF. If that causes a trap, then we probably
* don't have an FPU.
*/
ldd [%l0 + 2 * 16], %l4 ! Save original trap routine
set SYM(no_fpu_trap), %l1 ! Install new one
ldd [%l1], %l2
std %l2, [%l0 + 2 * 16]
mov %psr, %l0
sethi %hi(0x1000), %l1
bset %l1, %l0
! mov %l0, %psr
std %l4, [2 * 16] ! Restore original trap routine
/*
* Move the data segment from it's ROM address to RAM where it
* belongs.
*/
relocd:
#if 0 /* This code is broken. FIXME */
set (_sdata),%g2 ! %g2 = start of data in aout file
set SYM(environ),%g4 ! %g4 = actual data base address
set (_edata),%g3 ! %g3 = end of where data should go
subcc %g3, %g4, %g5 ! %g5 = length of data
subcc %g4, %g2, %g0 ! need to relocate data ?
ble init
ld [%g4], %g6
subcc %g6, 1, %g0
be init
mvdata:
subcc %g5, 8, %g5
ldd [%g2 + %g5], %g6
bg mvdata
#endif
/*
* initialize target specific stuff. Only execute these
* functions it they exist.
*/
init:
sethi %hi(SYM(hardware_init_hook)), %g1
or %g1,%lo(SYM(hardware_init_hook)),%g1
cmp %g0,%g1
be 1f
nop
call SYM(hardware_init_hook)
nop
1:
sethi %hi(SYM(software_init_hook)), %g1
or %g1,%lo(SYM(software_init_hook)),%g1
cmp %g0,%g1
be 2f
nop
call SYM(software_init_hook)
nop
2:
call SYM(main)
nop
/* call exit from the C library so atexit gets called, and the
* C++ destructors get run. This calls our exit routine below
* when it's done.
*/
call SYM(exit)
nop
/*
* This should drop control back to the ROM monitor, if there is
* one.
*/
.globl SYM(_exit)
SYM(_exit):
call 0
nop
/*
* Trap handlers.
*/
.align 8
SYM(win_ovf_trap):
sethi %hi(SYM(win_ovf)), %l3
jmpl %lo(SYM(win_ovf))+%l3, %g0
mov %wim, %l0
nop
SYM(win_unf_trap):
sethi %hi(SYM(win_unf)), %l3
jmpl %lo(SYM(win_unf))+%l3, %g0
mov %wim, %l0
nop
SYM(no_fpu_trap): ! Come here when no fpu exists.
jmpl %l2, %g0 ! This just skips the
rett %l2+4 ! offending instruction.
|
32bitmicro/newlib-nano-1.0
| 19,177
|
libgloss/sparc/traps.S
|
/*
* Copyright (c) 1995, 1996, 1998 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
#include "slite.h"
.text
.align 4
/*
* The trap table has to be the first code in a boot PROM. But because
* the Memory Configuration comes up thinking we only have 4K of PROM, we
* cannot have a full trap table and still have room left over to
* reprogram the Memory Configuration register correctly. This file
* uses an abbreviated trap which has every entry which might be used
* before RTEMS installs its own trap table.
*/
.globl _trap_table
_trap_table:
TRAP(SYM(ercinit)); ! 00 reset trap
BAD_TRAP; ! 01 instruction access exception
TRAP(SYM(no_fpu)); ! 02 illegal instruction
BAD_TRAP; ! 03 privileged instruction
BAD_TRAP; ! 04 fp disabled
TRAP(SYM(win_overflow)); ! 05 window overflow
TRAP(SYM(win_underflow)); ! 06 window underflow
BAD_TRAP; ! 07 memory address not aligned
BAD_TRAP; ! 08 fp exception
BAD_TRAP; ! 09 data access exception
BAD_TRAP; ! 0A tag overflow
/* Trap levels from 0B to 0x10 are not defined (used for MEC init) */
SYM(ercinit):
sethi %hi(_ERC32_MEC), %g1 ! 0B
sethi %hi(0x001C1000), %g2
or %g1,%lo(0x001C1000),%g1
st %g2, [%g1 + 0x10]
st %g0, [%g1 + 0x18] ! 0C
nop
nop
nop
TRAP(SYM(hard_reset)); ! 0D undefined
BAD_TRAP; ! 0E undefined
BAD_TRAP; ! 0F undefined
BAD_TRAP; ! 10 undefined
/*
* ERC32 defined traps
*/
BAD_TRAP; ! 11 masked errors
BAD_TRAP; ! 12 external 1
BAD_TRAP; ! 13 external 2
BAD_TRAP; ! 14 UART A RX/TX
BAD_TRAP; ! 15 UART B RX/TX
BAD_TRAP; ! 16 correctable memory error
BAD_TRAP; ! 17 UART error
BAD_TRAP; ! 18 DMA access error
BAD_TRAP; ! 19 DMA timeout
BAD_TRAP; ! 1A external 3
BAD_TRAP; ! 1B external 4
BAD_TRAP; ! 1C general purpose timer
BAD_TRAP; ! 1D real time clock
BAD_TRAP; ! 1E external 5
BAD_TRAP; ! 1F watchdog timeout
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined
BAD_TRAP; ! 24 cp_disabled
BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 25 - 27 undefined
BAD_TRAP; ! 28 cp_exception
BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 29 - 2B undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7C - 7F undefined
/*
* Software traps
*
* NOTE: At the risk of being redundant... this is not a full
* table. The setjmp on the SPARC requires a window flush trap
* handler and RTEMS will preserve the entries that were
* installed before.
*/
SOFT_TRAP; ! 80
#if 0
SOFT_TRAP; ! 81
#else
TRAP(SYM(trap_low)) ! 81
#endif
SOFT_TRAP; ! 82
TRAP(SYM(win_flush)); ! 83 flush windows SW trap
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB
SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF
/*
* Startup code for standalone system. Wash IU and FPU (if present)
* registers. The registers have to be written to initiate the parity
* bits.
*/
.globl SYM(hard_reset)
SYM(hard_reset):
sethi %hi(0x01FE0),%o0
or %o0,%lo(0x01FE0),%o0
mov %o0, %psr ! Set valid PSR
nop
mov %g0, %wim ! Set window invalid mask register
mov %g0, %y ! Init Y-register
nop
sethi %hi(SYM(hard_reset)), %g1
mov %g1, %tbr ! Set TBR
sethi %hi(SP_INIT),%sp
or %g0, 1, %o0
ld [%g0], %f0 ! Check if FPU is present
tst %o0
bz fixiu
nop
ba fixfpu
! FPU disabled trap address
clr %i0
jmpl %l2, %g0
rett %l2 + 4
nop
! Wash register files (fix for 90C601E & 90C602E)
fixfpu:
ld [%g0], %f0
ld [%g0], %f1
ld [%g0], %f2
ld [%g0], %f3
ld [%g0], %f4
ld [%g0], %f5
ld [%g0], %f6
ld [%g0], %f7
ld [%g0], %f8
ld [%g0], %f9
ld [%g0], %f10
ld [%g0], %f11
ld [%g0], %f12
ld [%g0], %f13
ld [%g0], %f14
ld [%g0], %f15
ld [%g0], %f16
ld [%g0], %f17
ld [%g0], %f18
ld [%g0], %f19
ld [%g0], %f20
ld [%g0], %f21
ld [%g0], %f22
ld [%g0], %f23
ld [%g0], %f24
ld [%g0], %f25
ld [%g0], %f26
ld [%g0], %f27
ld [%g0], %f28
ld [%g0], %f29
ld [%g0], %f30
ld [%g0], %f31
fixiu:
clr %g1
clr %g2
clr %g3
clr %g4
clr %g5
clr %g6
clr %g7
set 8,%g1
wl0:
clr %i0
clr %i1
clr %i2
clr %i3
clr %i4
clr %i5
clr %i6
clr %i7
clr %l0
clr %l1
clr %l2
clr %l3
clr %l4
clr %l5
clr %l6
clr %l7
save
subcc %g1, 1, %g1
bne wl0
nop
!
! Start the real-time clock with a tick of 150 clocks
!
rtc:
set 0x1f80000, %l0 ! MEC register base
set 149, %l1
st %l1, [%l0 + 0x84] ! RTC scaler = 149
set 0x0d00, %l1
st %l1, [%l0 + 0x98] ! Start RTC
st %g0, [%l0 + 0x64] ! Disable watchdog for now
ld [%l0], %g1
or %g1, 1, %g1
st %g1, [%l0] ! Enable power-down mode
_init:
set PSR_INIT, %g1 ! Initialize psr
mov %g1, %psr
set WIM_INIT, %g1 ! Initialize WIM
mov %g1, %wim
set _trap_table, %g1 ! Initialize TBR
mov %g1, %tbr
nop;nop;nop
set PSR_INIT, %g1
wr %g1, 0x20, %psr ! enable traps
nop; nop; nop;
call SYM(start)
nop
/*
* Register window overflow handler. Come here when save would move us
* into the invalid window. This routine runs with traps disabled, and
* must be careful not to touch the condition codes, as PSR is never
* restored.
*
* We are called with %l0 = wim, %l1 = pc, %l2 = npc
*/
.globl SYM(win_overflow)
SYM(win_overflow):
mov %g1, %l3 ! Save g1, we use it to hold the wim
srl %l0, 1, %g1 ! Rotate wim right
sll %l0, NUMBER_OF_REGISTER_WINDOWS - 1, %l0
or %l0, %g1, %g1
save %g0, %g0, %g0 ! Slip into next window
mov %g1, %wim ! Install the new wim
nop
nop
nop
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
restore ! Go back to trap window.
mov %l3, %g1 ! Restore %g1
jmpl %l1, %g0
rett %l2
/*
* Register window underflow handler. Come here when restore would move us
* into the invalid window. This routine runs with traps disabled, and
* must be careful not to touch the condition codes, as PSR is never
* restored.
*
* We are called with %l0 = wim, %l1 = pc, %l2 = npc
*/
.globl SYM(win_underflow)
SYM(win_underflow):
sll %l0, 1, %l3 ! Rotate wim left
srl %l0, NUMBER_OF_REGISTER_WINDOWS - 1, %l0
or %l0, %l3, %l0
mov %l0, %wim ! Install the new wim
restore ! Users window
restore ! His callers window
ldd [%sp + 0 * 4], %l0 ! restore L & I registers
ldd [%sp + 2 * 4], %l2
ldd [%sp + 4 * 4], %l4
ldd [%sp + 6 * 4], %l6
ldd [%sp + 8 * 4], %i0
ldd [%sp + 10 * 4], %i2
ldd [%sp + 12 * 4], %i4
ldd [%sp + 14 * 4], %i6
save %g0, %g0, %g0 ! Back to trap window
save %g0, %g0, %g0
jmpl %l1, %g0
rett %l2
/*
* Register window flush handler, triggered by a "ta 3" instruction.
* We are called with %l0 = wim, %l1 = pc, %l2 = npc
*/
.globl SYM(win_flush)
SYM(win_flush):
mov %psr, %l0
or %l0,0xf00,%l3 ! Disable interrupts
mov %l3,%psr
nop
nop
nop
mov %wim, %l3
srl %l3, %l0, %l4 ! wim >> cwp
cmp %l4, 1
bne flush_window_fine ! Branch if not in the invalid window
nop
/* Handle window overflow. We can't trap here. */
mov %g1, %l4 ! Save g1, we use it to hold the wim
srl %l3, 1, %g1 ! Rotate wim right
sll %l3, NUMBER_OF_REGISTER_WINDOWS - 1, %l3
or %l3, %g1, %g1
mov %g0, %wim ! Clear wim so that subsequent save
nop ! wont trap
nop
nop
save %g0, %g0, %g0 ! Slip into next window
mov %g1, %wim ! Install the new wim
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
restore ! Go back to trap window.
mov %l4, %g1 ! Restore %g1
flush_window_fine:
mov %psr,%l5 ! enable traps
or %l5,0x20,%l5
mov %l5, %psr
nop
nop
nop
set save_buf,%l5
st %l2,[%l5]
! The stack pointer currently contains a bogus value [when a trap
! occurs CWP is decremented and points to an unused window].
! Give it something useful before we flush every window.
! This does what a "save %sp,-64,$sp" would, except that CWP has
! already been decremented.
add %fp, -64, %sp
save %sp, -64, %sp ! Flush user register window to stack
save %sp, -64, %sp
save %sp, -64, %sp
save %sp, -64, %sp
save %sp, -64, %sp
save %sp, -64, %sp
save %sp, -64, %sp
save %sp, -64, %sp
restore
restore
restore
restore
restore
restore
restore
restore
restore ! Make sure we have a valid window
save %g0, %g0, %g0
set save_buf, %l2 ! Get our return address back
ld [%l2],%l2
mov %psr,%l5 ! disable traps for rett
andn %l5,0x20,%l5
mov %l5,%psr
nop
nop
nop
jmpl %l2, %g0
rett %l2+4
/*
* Read the TBR.
*/
.globl SYM(rdtbr)
SYM(rdtbr):
mov %tbr, %o0
nop
retl
nop
/*
* Read the psr
*/
.globl SYM(read_psr)
SYM(read_psr):
mov %psr, %o0
nop
retl
nop
/*
* Write the PSR.
*/
.globl SYM(write_psr)
SYM(write_psr):
mov %i0, %psr
nop
nop
nop
retl
nop
/*
* Come here when no fpu exists. This just skips the offending
* instruction.
*/
.globl SYM(no_fpu)
SYM(no_fpu):
jmpl %l2, %g0
rett %l2+4
.globl SYM(fltr_proto)
.align 4
SYM(fltr_proto): ! First level trap routine prototype
sethi 0, %l0
jmpl 0+%l0, %g0
nop
nop
/*
* Trap handler for memory errors. This just sets mem_err to be
* non-zero. It assumes that l1 is non-zero. This should be safe,
* as it is doubtful that 0 would ever contain code that could mem
* fault. This routine will skip past the faulting instruction after
* setting mem_err.
*/
.globl SYM(fltr_set_mem_err)
SYM(fltr_set_mem_err):
sethi %hi(SYM(mem_err)), %l0
st %l1, [%l0 + %lo(SYM(mem_err))]
jmpl %l2, %g0
rett %l2+4
.data
.align 4
.ascii "DaTa"
.long SYM(sdata)
in_trap_handler:
.word 0
save_buf:
.word 0 /* place to save %g1 */
.word 0 /* place to save %g2 */
.text
.align 4
/*
* This function is called when any SPARC trap (except window overflow
* or underflow) occurs. It makes sure that the invalid register
* window is still available before jumping into C code. It will also
* restore the world if you return from handle_exception.
*/
.globl SYM(trap_low)
SYM(trap_low):
mov %psr, %l0
mov %wim, %l3
srl %l3, %l0, %l4 ! wim >> cwp
cmp %l4, 1
bne window_fine ! Branch if not in the invalid window
nop
mov %g1, %l4 ! Save g1, we use it to hold the wim
srl %l3, 1, %g1 ! Rotate wim right
sll %l3, 8-1, %l5
or %l5, %g1, %g1
save %g0, %g0, %g0 ! Slip into next window
mov %g1, %wim ! Install the new wim
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
restore ! Go back to trap window.
mov %l4, %g1 ! Restore g1
window_fine:
sethi %hi(in_trap_handler), %l4
ld [%lo(in_trap_handler) + %l4], %l5
tst %l5
bg recursive_trap
inc %l5
/* use the stack we set in the linker script */
sethi %hi(__trap_stack), %l6
or %l6,%lo(__trap_stack),%l6
mov %l6, %sp ! set the stack pointer
recursive_trap:
st %l5, [%lo(in_trap_handler) + %l4]
sub %sp,(16+1+6+1+72)*4,%sp ! Make room for input & locals
! + hidden arg + arg spill
! + doubleword alignment
! + registers[72] local var
std %g0, [%sp + (24 + 0) * 4] ! registers[Gx]
std %g2, [%sp + (24 + 2) * 4]
std %g4, [%sp + (24 + 4) * 4]
std %g6, [%sp + (24 + 6) * 4]
std %i0, [%sp + (24 + 8) * 4] ! registers[Ox]
std %i2, [%sp + (24 + 10) * 4]
std %i4, [%sp + (24 + 12) * 4]
std %i6, [%sp + (24 + 14) * 4]
! F0->F31 not implemented
mov %y, %l4
mov %tbr, %l5
st %l4, [%sp + (24 + 64) * 4] ! Y
st %l0, [%sp + (24 + 65) * 4] ! PSR
st %l3, [%sp + (24 + 66) * 4] ! WIM
st %l5, [%sp + (24 + 67) * 4] ! TBR
st %l1, [%sp + (24 + 68) * 4] ! PC
st %l2, [%sp + (24 + 69) * 4] ! NPC
! CPSR and FPSR not implemented
or %l0, 0xf20, %l4
mov %l4, %psr ! Turn on traps, disable interrupts
call SYM(handle_exception)
add %sp, 24 * 4, %o0 ! Pass address of registers
/* Reload all of the registers that aren't on the stack */
ld [%sp + (24 + 1) * 4], %g1 ! registers[Gx]
ldd [%sp + (24 + 2) * 4], %g2
ldd [%sp + (24 + 4) * 4], %g4
ldd [%sp + (24 + 6) * 4], %g6
ldd [%sp + (24 + 8) * 4], %i0 ! registers[Ox]
ldd [%sp + (24 + 10) * 4], %i2
ldd [%sp + (24 + 12) * 4], %i4
ldd [%sp + (24 + 14) * 4], %i6
ldd [%sp + (24 + 64) * 4], %l0 ! Y & PSR
ldd [%sp + (24 + 68) * 4], %l2 ! PC & NPC
restore ! Ensure that previous window is valid
save %g0, %g0, %g0 ! by causing a window_underflow trap
mov %l0, %y
mov %l1, %psr ! Make sure that traps are disabled
! for rett
sethi %hi(in_trap_handler), %l4
ld [%lo(in_trap_handler) + %l4], %l5
dec %l5
st %l5, [%lo(in_trap_handler) + %l4]
jmpl %l2, %g0 ! Restore old PC
rett %l3 ! Restore old nPC
|
32bitmicro/newlib-nano-1.0
| 2,896
|
libgloss/sparc/cygmon-crt0.S
|
/*
* C startup code for the Fujitsu SPARClite demo board
*
* Copyright (c) 1995, 1996 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
#ifdef TARGET_CPU_SPARC64
#define STACK_BIAS 2047
#define SAVE_SIZE -128
#else
#define SAVE_SIZE -64
#endif
.data
.align 8
SYM(environ): ! this is the first address in the data section
.long 0
SYM(argc):
.long 0
.text
.align 8
.globl SYM(start)
.globl start
SYM(start):
start:
/* see if the stack is already setup. if not, then default
* to using the value of %sp as set by the ROM monitor
*/
sethi %hi(__stack), %g1
or %g1,%lo(__stack),%g1
cmp %g0,%g1
be 1f
nop
#ifdef STACK_BIAS
sub %g1, STACK_BIAS, %g1
#endif
mov %g1, %sp ! set the stack pointer
mov 0, %fp
1:
/* zero the bss section */
sethi %hi(__bss_start),%g2
or %g2,%lo(__bss_start),%g2 ! start of bss
sethi %hi(_end),%g3
or %g3,%lo(_end),%g3 ! end of bss
mov %g0,%g1 ! so std has two zeros
zerobss:
std %g0,[%g2]
add %g2,8,%g2
cmp %g2,%g3
bleu,a zerobss
nop
/*
* initialize target specific stuff. Only execute these
* functions it they exist.
*/
init:
sethi %hi(SYM(hardware_init_hook)), %g1
or %g1,%lo(SYM(hardware_init_hook)),%g1
cmp %g0,%g1
be 1f
nop
call SYM(hardware_init_hook)
nop
1:
sethi %hi(SYM(software_init_hook)), %g1
or %g1,%lo(SYM(software_init_hook)),%g1
cmp %g0,%g1
be 2f
nop
call SYM(software_init_hook)
nop
2:
set SYM(__sigtramp), %o0
call SYM(__install_signal_handler)
nop
set do_dtors,%o0
call SYM(atexit)
nop
call do_ctors
nop
set SYM(argc), %o0
call SYM(__getProgramArgs)
nop
mov %o0, %o1
set SYM(argc), %o0
ld [%o0], %o0
call SYM(main)
nop
/* call exit from the C library so atexit gets called, and the
* C++ destructors get run. This calls our exit routine below
* when it's done.
*/
call SYM(exit)
nop
do_ctors:
save %sp,SAVE_SIZE,%sp
set __CTOR_LIST__,%l0
our_entry:
ld [%l0],%l1
add %l0,4,%l0
tst %l1
1:
beq 2f
nop
ld [%l0],%l2
add %l0,4,%l0
call %l2
nop
deccc %l1
b 1b
nop
2:
ret
restore
do_dtors:
save %sp,SAVE_SIZE,%sp
set __DTOR_LIST__,%l0
b our_entry
nop
|
32bitmicro/newlib-nano-1.0
| 1,791
|
libgloss/sparc/erc32-crt0.S
|
/*
* This is based on the file srt0.s provided with the binary
* distribution of the SPARC Instruction Simulator (SIS) found
* at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
*/
#include "asm.h"
.data
.align 8
SYM(environ):
.long 0
.text
.globl SYM(start)
SYM(start):
sethi %hi(__stack), %g1
or %g1,%lo(__stack),%g1
mov %g1, %sp ! set the stack pointer
mov %sp, %fp
/* clear the bss */
sethi %hi(__bss_start),%g2
or %g2,%lo(__bss_start),%g2 ! start of bss
sethi %hi(_end),%g3
or %g3,%lo(_end),%g3 ! end of bss
mov %g0,%g1 ! so std has two zeros
zerobss:
std %g0,[%g2]
add %g2,8,%g2
cmp %g2,%g3
bleu,a zerobss
nop
/* move data segment to proper location */
#if 0
relocd:
set (_endtext),%g2 ! g2 = start of data in aout file
set (_environ),%g4 ! g4 = start of where data should go
set (_edata),%g3 ! g3 = end of where data should go
subcc %g3, %g4, %g5 ! g5 = length of data
subcc %g4, %g2, %g0 ! need to relocate data ?
ble initok
ld [%g4], %g6
subcc %g6, 1, %g0
be initok
mvdata:
subcc %g5, 8, %g5
ldd [%g2 + %g5], %g6
bg mvdata
std %g6, [%g4 + %g5]
initok:
#endif
call SYM(__fix_ctors)
nop
call SYM(main)
nop
/* call exit from the C library so atexit gets called, and the
* C++ destructors get run. This calls our exit routine below * when it's done.
*/
call SYM(exit)
nop
.globl SYM(_exit)
SYM(_exit):
set 0xdeadd00d, %o1 ! Magic number for simulator.
ta 0 ! Halt if _main returns ...
nop
|
32bitmicro/newlib-nano-1.0
| 2,693
|
libgloss/mn10300/crt0_cygmon.S
|
/*
* crt0_cygmon.S -- Minimal startup file for MN10300 targets running Cygmon.
*
* Copyright (c) 1995, 1996, 1997, 2000 Red Hat, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* This file contains the minimal startup code necessary.
* This will not do any hardware initialization. It is assumed that we are talking to Cygmon
* and therefore the hardware will be initialized properly.
*/
/*
* Set up some room for a stack. We just grab a chunk of memory.
*/
#define STACK_SIZE 0x4000
#define GLOBAL_SIZE 0x2000
#define STARTUP_STACK_SIZE 0x0100
.comm __memsize, 12
.comm __lstack, STARTUP_STACK_SIZE
.comm __stackbase,4
.section .text
.global _start
_start:
/*
* Setup a small stack so we can run some C code,
* and get the usable memory size.
*/
mov __lstack,a0
add STARTUP_STACK_SIZE-4,a0
mov a0,sp
/*
* zero out the bss section.
*/
.global __memsize
.global _get_mem_info
zerobss:
mov __bss_start, a0 # These variables are defined in the linker script
mov _end, a1
cmp a0, a1 # If no bss, then do nothing
beq 7f
clr d0
3:
movbu d0,(a0) # Clear a byte and bump pointer
inc a0
cmp a0, a1
bne 3b
7:
/*
* Setup the stack pointer --
* get_mem_info returns the top of memory, so just use that In
* addition, we must subtract 24 bytes for the 3 8 byte
* arguments to main, in case main wants to write them back to
* the stack. The caller is supposed to allocate stack space
* for parameters in registers in the old MIPS ABIs. We must
* do this even though we aren't passing arguments, because
* main might be declared to have them.
* Some ports need a larger alignment for the stack, so we
* subtract 32, which satisifes the stack for the arguments and
* keeps the stack pointer better aligned.
*/
mov __memsize, d0
call _get_mem_info,[],0
sub 32, a0
mov a0, sp
mov __stackbase, a1
mov a0, (a1) # keep this for future ref
call ___main,[],0 # Call __main to run ctors/dtors
clr d0
clr d1
mov d0, (4,sp)
call _main,[],0 # Call main program
call _exit,[],0
/* EOF crt0_cygmon.S */
|
32bitmicro/newlib-nano-1.0
| 1,712
|
libgloss/mn10300/crt0.S
|
##==============================================================================
##
## crt0.S
##
## MN10300 startup code
##
##==============================================================================
##
## Copyright (c) 1995, 1996, 1997, 1998 Cygnus Solutions
##
## The authors hereby grant permission to use, copy, modify, distribute,
## and license this software and its documentation for any purpose, provided
## that existing copyright notices are retained in all copies and that this
## notice is included verbatim in any distributions. No written agreement,
## license, or royalty fee is required for any of the authorized uses.
## Modifications to this software may be copyrighted by their authors
## and need not follow the licensing terms described here, provided that
## the new terms are clearly indicated on the first page of each file where
## they apply.
##
##------------------------------------------------------------------------------
.file "crt0.S"
##------------------------------------------------------------------------------
## Startup code
.section .text
.global _start
_start:
mov _stack-8,a0 # Load up the stack pointer
mov a0,sp
mov _edata,a0 # Get the start/end of bss
mov _end,a1
cmp a0,a1 # If no bss, then do nothing
beq .L0
clr d0 # clear d0
.L1:
movbu d0,(a0) # Clear a byte and bump pointer
inc a0
cmp a0,a1
bne .L1
.L0:
call ___main,[],0 # Call __main to run ctors/dtors
clr d0
clr d1
mov d0,(4,sp)
call _main,[],0 # Call main program
call _exit,[],0 # All done, no need to return or
# deallocate our stack.
.section .stack
_stack: .long 1
.section .data
.global ___dso_handle
.weak ___dso_handle
___dso_handle:
.long 0
|
32bitmicro/newlib-nano-1.0
| 1,810
|
libgloss/mn10300/crt0-eval.S
|
##==============================================================================
##
## crt0-eval.S
##
## MN10300 Series Evaluation Board C startup code
##
##==============================================================================
######COPYRIGHTBEGIN####
##
## Copyright (c) 1995, 1996, 1997, 1998 Cygnus Solutions
##
## The authors hereby grant permission to use, copy, modify, distribute,
## and license this software and its documentation for any purpose, provided
## that existing copyright notices are retained in all copies and that this
## notice is included verbatim in any distributions. No written agreement,
## license, or royalty fee is required for any of the authorized uses.
## Modifications to this software may be copyrighted by their authors
## and need not follow the licensing terms described here, provided that
## the new terms are clearly indicated on the first page of each file where
## they apply.
##
######COPYRIGHTEND####
##------------------------------------------------------------------------------
.file "crt0-eval.S"
##------------------------------------------------------------------------------
## Startup code
.equ DRAM_TOP,0x48100000
.text
.globl __start
__start:
# Set up stack. Leave 4K at top for use by Cygmon.
mov DRAM_TOP - 0x1000,a0
sub 8,a0
mov a0,sp
# Clear BSS
mov __bss_start,a0
mov _end,a1
cmp a0,a1
beq 8f
clr d0
1:
movbu d0,(a0)
inc a0
cmp a0,a1
bne 1b
8:
# Call constructors
.extern ___main
call ___main,[],0
# Call main
clr d0
clr d1
mov d0,(4,sp)
9:
or 0x0800,psw # Enable interrupts
.extern _main
call _main,[],0
.extern __exit
call __exit,[],0
# bra 9b # Loop if we return
##------------------------------------------------------------------------------
## end of crt0-eval.S
|
32bitmicro/newlib-nano-1.0
| 2,801
|
libgloss/mn10300/crt0_redboot.S
|
/*
* crt0_redboot.S -- Minimal startup file for MN10300 targets running Redboot.
*
* Copyright (c) 2001 Red Hat, Inc.
* Derived from crt0_cygmon.S - Copyright (c) 1995, 1996, 1997, 2000 Red Hat, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* This file contains the minimal startup code necessary.
* This will not do any hardware initialization. It is assumed that we are talking to Redboot
* and therefore the hardware will be initialized properly.
*/
/*
* Set up some room for a stack. We just grab a chunk of memory.
*/
#define STACK_SIZE 0x4000
#define GLOBAL_SIZE 0x2000
#define STARTUP_STACK_SIZE 0x0100
.comm __memsize, 12
.comm __lstack, STARTUP_STACK_SIZE
.comm __stackbase,4
.section .text
.global _start
_start:
/*
* Setup a small stack so we can run some C code,
* and get the usable memory size.
*/
mov __lstack,a0
add STARTUP_STACK_SIZE-4,a0
mov a0,sp
/*
* zero out the bss section.
*/
.global __memsize
.global _get_mem_info
zerobss:
mov __bss_start, a0 # These variables are defined in the linker script
mov _end, a1
cmp a0, a1 # If no bss, then do nothing
beq 7f
clr d0
3:
movbu d0,(a0) # Clear a byte and bump pointer
inc a0
cmp a0, a1
bne 3b
7:
/*
* Setup the stack pointer --
* get_mem_info returns the top of memory, so just use that In
* addition, we must subtract 24 bytes for the 3 8 byte
* arguments to main, in case main wants to write them back to
* the stack. The caller is supposed to allocate stack space
* for parameters in registers in the old MIPS ABIs. We must
* do this even though we aren't passing arguments, because
* main might be declared to have them.
* Some ports need a larger alignment for the stack, so we
* subtract 32, which satisifes the stack for the arguments and
* keeps the stack pointer better aligned.
*/
mov __memsize, d0
call _get_mem_info,[],0
sub 32, a0
mov a0, sp
mov __stackbase, a1
mov a0, (a1) # keep this for future ref
call ___main,[],0 # Call __main to run ctors/dtors
clr d0
clr d1
mov d0, (4,sp)
or 0x0800,psw # Enable interrupts
call _main,[],0 # Call main program
call _exit,[],0
/* EOF crt0_redboot.S */
|
32bitmicro/newlib-nano-1.0
| 4,595
|
libgloss/hp74x/crt0.s
|
/*
* crt0.S -- startup file for hppa.
* rob@cygnus.com (Rob Savoye)
*/
.VERSION "0.2"
.COPYRIGHT "crt0.S for hppa"
;sp .equ %r30 ; stack pointer
;dp .equ %r27 ; global data pointer
;arg0 .equ %r26 ; argument
;arg1 .equ %r25 ; argument or high part of double argument
;arg2 .equ %r24 ; argument
;arg3 .equ %r23 ; argument or high part of double argument
#define IMM(a,b) ldil L%a,b ! ldo R%a(b),b
#define imm(i,t) ldil LS%i,t ! addi RS%i,t,t
.DATA
/****
* FIXME: these are just a gross hack so this will assemble
****/
_bss_start .WORD
_bss_end .WORD
_foobar
.STRINGZ "Foo Bar...\r\n"
;;_SYSTEM_ID .WORD
;; .EXPORT _SYSTEM_ID ; FIXME this is only so it'll
; link
/*
* Set up the standard spaces (sections) These definitions come
* from /lib/pcc_prefix.s.
*/
.space $TEXT$,0
.SUBSPA $BOOT$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=4
.IMPORT _start
/*
* stuff we need that's defined elsewhere.
*/
.IMPORT main, CODE
.IMPORT _bss_start, DATA
.IMPORT _bss_end, DATA
.IMPORT environ, DATA
/*
* start -- set things up so the application will run.
*
*/
.PROC
.CALLINFO SAVE_SP, FRAME=48
.EXPORT $START$,ENTRY
$START$
/* FIXME: this writes to page zero */
;; setup the %30 (stack pointer) with some memory
ldil L%_stack+48,%r30
ldo R%_stack+48(%r30),%r30 ; should be %r30 (sp) but then
; we'd kill our test program :-)
;; we need to set %r27 (global data pointer) here too
ldil L%$global$,%r27
ldo R%$global$(%r27),%r27 ; same problem as above
/*
* zerobss -- zero out the bss section
*/
; load the start of bss
ldil L%_bss_start,%r4
ldo R%_bss_start(%r4),%r4
; load the end of bss
ldil L%_bss_end,%r5
ldo R%_bss_end(%r5),%r5
bssloop
addi -1,%r5,%r5 ; decrement _bss_end
stb %r0,0(0,%r5) ; we do this by bytes for now even
; though it's slower, it's safer
combf,= %r4,%r5, bssloop
nop
ldi 1,%ret0
/*
* Call the main routine from the application to get it going.
* main (argc, argv, environ)
* We pass argv as a pointer to NULL.
*/
bl main,%r2
nop
.PROCEND
/*
* _exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run, but with
* this monitor we can't. Still, "C" wants this symbol, it
* should be here. Jumping to 0xF0000004 jumps back into the
* firmware, while writing a 5 to 0xFFFE0030 causes a reset.
*/
.EXPORT _exit, ENTRY
_exit
.PROC
.CALLINFO
.ENTRY
;; ldil L%0xf0000004,%r1
;; bl %r1, %r2
ldil L'4026531844,%r19
ldo R'4026531844(%r19),%r19
blr %r19, %r2
nop
;; This just causes a breakpoint exception
;; break 0x0e,0xa5a
;; bv,n (%rp)
nop
.EXIT
.PROCEND
.subspa $UNWIND_START$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=56
.export $UNWIND_START
$UNWIND_START
.subspa $UNWIND$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=64
.subspa $UNWIND_END$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=72
.export $UNWIND_END
$UNWIND_END
.subspa $RECOVER_START$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=73
.export $RECOVER_START
$RECOVER_START
.subspa $RECOVER$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=80
.subspa $RECOVER_END$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=88
.export $RECOVER_END
$RECOVER_END
; The following declarations are, by default in the data space ($PRIVATE$)
;; .space $PRIVATE$,1
/*
* Here we set up the standard date sub spaces.
* _dp is for the WinBond board.
*
* Set up some room for a stack. We just grab a chunk of memory.
* We also setup some space for the global variable space, which
* must be done using the reserved name "$global$" so "C" code
* can find it. The stack grows towards the higher addresses.
*/
.subspa $DATA$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=16
.subspa $SHORTDATA$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=24
.subspa $GLOBAL$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=40
.export $global$
.export _dp
$global$
_dp
.subspa $SHORTBSS$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=80,ZERO
.subspa $BSS$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82,ZERO
.subspa $STACK$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=88,ZERO
.export _stack
_stack
.BLOCK 0x2000
/*
* The heap follows the stack. To use dynamic memory routines in an
* application, some space MUST be assigned to the stack.
*/
.subspa $HEAP$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=96,ZERO
.export _heap
_heap
.end
|
32bitmicro/newlib-nano-1.0
| 11,133
|
libgloss/hp74x/debugger.s
|
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
.space $TEXT$
.subspa $CODE$,access=0x2c
#if 1
#include "diagnose.h"
#endif
i13BREAK .equ 0xa5a ; im13 field for specified functions
i5REG .equ 0x06 ; Init registers
i5BP .equ 0x09 ; GDB breakpoin
i5PSW .equ 0x0b ; Get PSW
i5INLINE .equ 0x0e ; Get INLINE
R_gr0 .equ 0
R_gr1 .equ 4
R_gr2 .equ 8
R_gr3 .equ 12
R_gr4 .equ 16
R_gr5 .equ 20
R_gr6 .equ 24
R_gr7 .equ 28
R_gr8 .equ 32
R_gr9 .equ 36
R_gr10 .equ 40
R_gr11 .equ 44
R_gr12 .equ 48
R_gr13 .equ 52
R_gr14 .equ 56
R_gr15 .equ 60
R_gr16 .equ 64
R_gr17 .equ 68
R_gr18 .equ 72
R_gr19 .equ 76
R_gr20 .equ 80
R_gr21 .equ 84
R_gr22 .equ 88
R_gr23 .equ 92
R_gr24 .equ 96
R_gr25 .equ 100
R_gr26 .equ 104
R_gr27 .equ 108
R_gr28 .equ 112
R_gr29 .equ 116
R_gr30 .equ 120
R_gr31 .equ 124
R_sr0 .equ 128
R_sr1 .equ 132
R_sr2 .equ 136
R_sr3 .equ 140
R_sr4 .equ 144
R_sr5 .equ 148
R_sr6 .equ 152
R_sr7 .equ 156
R_cr0 .equ 160
R_cr1 .equ 164
R_cr2 .equ 168
R_cr3 .equ 172
R_cr4 .equ 176
R_cr5 .equ 180
R_cr6 .equ 184
R_cr7 .equ 188
R_cr8 .equ 192
R_cr9 .equ 196
R_cr10 .equ 200
R_cr11 .equ 204
R_cr12 .equ 208
R_cr13 .equ 212
R_cr14 .equ 216
R_cr15 .equ 220
R_cr16 .equ 224
R_cr17H .equ 228
R_cr18H .equ 232
R_cr19 .equ 236
R_cr20 .equ 240
R_cr21 .equ 244
R_cr22 .equ 248
R_cr23 .equ 252
R_cr24 .equ 256
R_cr25 .equ 260
R_cr26 .equ 264
R_cr27 .equ 268
R_cr28 .equ 272
R_cr29 .equ 276
R_cr30 .equ 280
R_cr31 .equ 284
R_cr17T .equ 288
R_cr18T .equ 292
R_cpu0 .equ 296
R_SIZE .equ 300
min_stack .equ 64
.import handle_exception
.import $global$, data
.IMPORT putnum, code
.IMPORT led_putnum, code
.IMPORT delay, code
.export FICE
.export DEBUG_GO
.export DEBUG_SS
.export STUB_RESTORE
.export save_regs
.export RegBlk
.export Exception_index
;-------------------------------------------------------------------------------
.EXPORT breakpoint,ENTRY,ARGW0=GR,RTNVAL=GR
breakpoint
.PROC
.CALLINFO CALLER,FRAME=128,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30) ; stash the return pointer
ldo 128(%r30),%r30 ; push up the stack pointer
;;; debug
ldi 6, %r26
bl,n led_putnum,%r2
nop
ldil L'900000,%r26
ldo R'900000(%r26),%r26
bl,n delay,%r2
nop
;;;
break i5INLINE,i13BREAK
;;; more debug
ldi 7, %r26
bl,n led_putnum,%r2
nop
ldil L'900000,%r26
ldo R'900000(%r26),%r26
bl,n delay,%r2
nop
;;;
FICE fice 0(0,%r26) ; Flush the i cache entry
sync
ldw -148(0,%r30),%r2 ; retrieve the return pointer
ldo -128(%r30),%r30 ; reset the stack pointer
bv,n 0(%r2) ; return to caller
nop
.EXIT
.PROCEND
;-------------------------------------------------------------------------------
DEBUG_GO
or,tr %r0,%r0,%r10 ; if go, do not set R-bit to 1
DEBUG_SS
ldi 1,%r10 ; else set R-bit to 1
DEBUG_EXEC
bl DGO_0,%r8 ; r8 points to register block
addil L%RegBlk-DGO_0,%r8
DGO_0
ldo R%RegBlk-DGO_0(%r1),%r8
; load space registers
ldw R_sr0(%r8),%r1
mtsp %r1,%sr0
ldw R_sr1(%r8),%r1
mtsp %r1,%sr1
ldw R_sr2(%r8),%r1
mtsp %r1,%sr2
ldw R_sr3(%r8),%r1
mtsp %r1,%sr3
ldw R_sr4(%r8),%r1
mtsp %r1,%sr4
ldw R_sr5(%r8),%r1
mtsp %r1,%sr5
ldw R_sr6(%r8),%r1
mtsp %r1,%sr6
ldw R_sr7(%r8),%r1
mtsp %r1,%sr7
; clear Q-bit for rfi
rsm 0x08,%r0
; load control registers
ldw R_cr0(%r8),%r1
or,= %r10,%r0,%r0 ; if single step
copy %r0,%r1 ; set %cr0 to 0
mtctl %r1,%cr0
ldw R_cr8(%r8),%r1
mtctl %r1,%cr8
ldw R_cr9(%r8),%r1
mtctl %r1,%cr9
ldw R_cr10(%r8),%r1
mtctl %r1,%cr10
ldw R_cr11(%r8),%r1
mtctl %r1,%cr11
ldw R_cr12(%r8),%r1
mtctl %r1,%cr12
ldw R_cr13(%r8),%r1
mtctl %r1,%cr13
ldw R_cr14(%r8),%r1
mtctl %r1,%cr14
ldw R_cr15(%r8),%r1
mtctl %r1,%cr15
ldw R_cr16(%r8),%r1
mtctl %r1,%cr16
ldw R_cr17H(%r8),%r1 ; load iiasq.head
mtctl %r1,%cr17
ldw R_cr18H(%r8),%r1 ; load iiaoq.head
mtctl %r1,%cr18
ldw R_cr17T(%r8),%r1 ; load iiasq.tail
mtctl %r1,%cr17
ldw R_cr18T(%r8),%r1 ; load iiaoq.tail
mtctl %r1,%cr18
ldw R_cr19(%r8),%r1
mtctl %r1,%cr19
ldw R_cr20(%r8),%r1
mtctl %r1,%cr20
ldw R_cr21(%r8),%r1
mtctl %r1,%cr21
ldw R_cr22(%r8),%r1
dep %r10,27,1,%r1 ; set R-bit if applicable
mtctl %r1,%cr22
ldw R_cr23(%r8),%r1
mtctl %r1,%cr23
ldw R_cr24(%r8),%r1
mtctl %r1,%cr24
ldw R_cr25(%r8),%r1
mtctl %r1,%cr25
ldw R_cr26(%r8),%r1
mtctl %r1,%cr26
ldw R_cr27(%r8),%r1
mtctl %r1,%cr27
ldw R_cr28(%r8),%r1
mtctl %r1,%cr28
ldw R_cr29(%r8),%r1
mtctl %r1,%cr29
ldw R_cr30(%r8),%r1
mtctl %r1,%cr30
ldw R_cr31(%r8),%r1
mtctl %r1,%cr31
; load diagnose registers
ldw R_cpu0(%r8),%r1
ldil L%CPU0_MASK,%r2
ldo R%CPU0_MASK(%r2),%r2
xor %r1,%r2,%r1 ; xor the read/clear bits
nop
mtcpu %r1,0
mtcpu %r1,0
; load general registers
ldw R_gr1(%r8),%r1
ldw R_gr2(%r8),%r2
ldw R_gr3(%r8),%r3
ldw R_gr4(%r8),%r4
ldw R_gr5(%r8),%r5
ldw R_gr6(%r8),%r6
ldw R_gr7(%r8),%r7
ldw R_gr9(%r8),%r9
ldw R_gr10(%r8),%r10
ldw R_gr11(%r8),%r11
ldw R_gr12(%r8),%r12
ldw R_gr13(%r8),%r13
ldw R_gr14(%r8),%r14
ldw R_gr15(%r8),%r15
ldw R_gr16(%r8),%r16
ldw R_gr17(%r8),%r17
ldw R_gr18(%r8),%r18
ldw R_gr19(%r8),%r19
ldw R_gr20(%r8),%r20
ldw R_gr21(%r8),%r21
ldw R_gr22(%r8),%r22
ldw R_gr23(%r8),%r23
ldw R_gr24(%r8),%r24
ldw R_gr25(%r8),%r25
ldw R_gr26(%r8),%r26
ldw R_gr27(%r8),%r27
ldw R_gr28(%r8),%r28
ldw R_gr29(%r8),%r29
ldw R_gr30(%r8),%r30
ldw R_gr31(%r8),%r31
ldw R_gr8(%r8),%r8
; execute user program
nop
rfi ; switch to user code
nop
;-------------------------------------------------------------------------------
STUB_RESTORE
copy %r1,%r9 ; save exception index
bl SR_00,%r8
addil L%Exception_index-SR_00,%r8
SR_00
ldo R%Exception_index-SR_00(%r1),%r8
stw %r9,(%r8)
bl save_regs,%r25
nop
#ifdef DEBUG_DEBUGGER1
stwm %r1,8(%sp)
bl putc,%rp
ldi CR,%arg0
bl putc,%rp
ldi LF,%arg0
bl printit,%mrp
mfctl %pcoq,%arg0
mfctl %pcoq,%r1
mtctl %r1,%pcoq
mfctl %pcoq,%arg0
bl printit,%mrp
mtctl %arg0,%pcoq
bl printit,%mrp
ldw -8(%sp),%arg0
ldwm -8(%sp),%r1
#endif
#ifdef DEBUG_DEBUGGER2
stwm %r1,8(%sp)
bl putc,%rp
ldi LF,%arg0
ldwm -8(%sp),%r1
#endif
#ifdef DEBUG_DEBUGGER3
bl printit,%mrp
copy iptr,%arg0
bl printit,%mrp
copy rstack,%arg0
bl printit,%mrp
copy gspace,%arg0
bl printit,%mrp
copy dstack,%arg0
bl printit,%mrp
copy nextptr,%arg0
bl printit,%mrp
copy %dp,%arg0
bl printit,%mrp
copy %sp,%arg0
bl printit,%mrp
mfctl %rctr,%arg0
bl printit,%mrp
mfctl %iva,%arg0
bl printit,%mrp
mfctl %eiem,%arg0
bl printit,%mrp
mfctl %ipsw,%arg0
bl printit,%mrp
copy %r0,%arg0
#endif
bl SR_1,%sp
addil L%Stub_stack-SR_1,%sp
SR_1
ldo R%Stub_stack-SR_1(%r1),%sp ; set the stack pointer
bl SR_2,%arg0
addil L%RegBlk-SR_2,%arg0
SR_2
ldo R%RegBlk-SR_2(%r1),%arg0 ; set arg0 (save register area)
bl SR_3,%arg1
addil L%Exception_index-SR_3,%arg1 ; set arg1 address
SR_3
ldo R%Exception_index-SR_3(%r1),%arg1 ; set arg1 address
addi min_stack,%sp,%sp ; allocate min stack frame
bl handle_exception,%r2
ldw 0(%arg1),%arg1 ; load arg1
addi -min_stack,%sp,%sp ; de allocate min stack frame
b DEBUG_EXEC ;
copy %r28,%r10
;-------------------------------------------------------------------------------
save_regs ; return address is in %r25
bl SR_0,%r1 ; r1 points to Register block
addil L%RegBlk-SR_0,%r1
SR_0
ldo R%RegBlk-SR_0(%r1),%r1
; save general registers
stw %r0,R_gr0(%r1)
; don't store %r1 yet
stw %r2,R_gr2(%r1)
stw %r3,R_gr3(%r1)
stw %r4,R_gr4(%r1)
stw %r5,R_gr5(%r1)
stw %r6,R_gr6(%r1)
stw %r7,R_gr7(%r1)
; don't store %r8 yet
; don't store %r9 yet
stw %r10,R_gr10(%r1)
stw %r11,R_gr11(%r1)
stw %r12,R_gr12(%r1)
stw %r13,R_gr13(%r1)
stw %r14,R_gr14(%r1)
stw %r15,R_gr15(%r1)
; don't store %r16 yet
; don't store %r17 yet
stw %r18,R_gr18(%r1)
stw %r19,R_gr19(%r1)
stw %r20,R_gr20(%r1)
stw %r21,R_gr21(%r1)
stw %r22,R_gr22(%r1)
stw %r23,R_gr23(%r1)
; don't store %r24 yet
; don't store %r25 yet
stw %r26,R_gr26(%r1)
stw %r27,R_gr27(%r1)
stw %r28,R_gr28(%r1)
stw %r29,R_gr29(%r1)
stw %r30,R_gr30(%r1)
stw %r31,R_gr31(%r1)
; restore general registers from shadow registers and save them
copy %r1,%r10 ; hold Register block pointer
copy %r25,%rp ; hold return pointer
shdw_gr
shdw_gr
stw %r1,R_gr1(%r10)
stw %r8,R_gr8(%r10)
stw %r9,R_gr9(%r10)
stw %r16,R_gr16(%r10)
stw %r17,R_gr17(%r10)
stw %r24,R_gr24(%r10)
stw %r25,R_gr25(%r10)
; save control registers
mfctl %cr0,%r1
stw %r1,R_cr0(%r10)
stw %r0,R_cr1(%r10)
stw %r0,R_cr2(%r10)
stw %r0,R_cr3(%r10)
stw %r0,R_cr4(%r10)
stw %r0,R_cr5(%r10)
stw %r0,R_cr6(%r10)
stw %r0,R_cr7(%r10)
mfctl %cr8,%r1
stw %r1,R_cr8(%r10)
mfctl %cr9,%r1
stw %r1,R_cr9(%r10)
mfctl %cr10,%r1
stw %r1,R_cr10(%r10)
mfctl %cr11,%r1
stw %r1,R_cr11(%r10)
mfctl %cr12,%r1
stw %r1,R_cr12(%r10)
mfctl %cr13,%r1
stw %r1,R_cr13(%r10)
mfctl %cr14,%r1
stw %r1,R_cr14(%r10)
mfctl %cr15,%r1
stw %r1,R_cr15(%r10)
mfctl %cr16,%r1
stw %r1,R_cr16(%r10)
mfctl %cr17,%r1
stw %r1,R_cr17H(%r10)
mtctl %r1,%cr17
mfctl %cr17,%r1
stw %r1,R_cr17T(%r10)
mtctl %r1,%cr17
mfctl %cr18,%r1
stw %r1,R_cr18H(%r10)
mtctl %r1,%cr18
mfctl %cr18,%r1
stw %r1,R_cr18T(%r10)
mtctl %r1,%cr18
mfctl %cr19,%r1
stw %r1,R_cr19(%r10)
mfctl %cr20,%r1
stw %r1,R_cr20(%r10)
mfctl %cr21,%r1
stw %r1,R_cr21(%r10)
mfctl %cr22,%r1
stw %r1,R_cr22(%r10)
mfctl %cr23,%r1
stw %r1,R_cr23(%r10)
mfctl %cr24,%r1
stw %r1,R_cr24(%r10)
mfctl %cr25,%r1
stw %r1,R_cr25(%r10)
mfctl %cr26,%r1
stw %r1,R_cr26(%r10)
mfctl %cr27,%r1
stw %r1,R_cr27(%r10)
mfctl %cr28,%r1
stw %r1,R_cr28(%r10)
mfctl %cr29,%r1
stw %r1,R_cr29(%r10)
mfctl %cr30,%r1
stw %r1,R_cr30(%r10)
mfctl %cr31,%r1
stw %r1,R_cr31(%r10)
; save diagnose registers
mfcpu_c 0,%r1
mfcpu_c 0,%r1
stw %r1,R_cpu0(%r10)
; save space registers
mfsp %sr0,%r1
stw %r1,R_sr0(%r10)
mfsp %sr1,%r1
stw %r1,R_sr1(%r10)
mfsp %sr2,%r1
stw %r1,R_sr2(%r10)
mfsp %sr3,%r1
stw %r1,R_sr3(%r10)
mfsp %sr4,%r1
stw %r1,R_sr4(%r10)
mfsp %sr5,%r1
stw %r1,R_sr5(%r10)
mfsp %sr6,%r1
stw %r1,R_sr6(%r10)
mfsp %sr7,%r1
bv (%rp)
stw %r1,R_sr7(%r10)
#ifdef DEBUG_DEBUGGER
;-------------------------------------------------------------------------------
printit
mtctl %rp,%tr0
mtctl %r1,%tr1
bl putnum,%rp
copy %rp,%arg0
mtctl %mrp,%tr2
bl putc,%rp
ldi CR,%arg0
bl putc,%rp
ldi LF,%arg0
mfctl %tr2,%mrp
mfctl %tr1,%r1
bv (%mrp)
mfctl %tr0,%rp
#endif
.space $PRIVATE$
.subspa $DATA$,align=4,access=0x1f
Exception_index
.word 0
RegBlk
.block R_SIZE ; register block
Stub_stack
.block 1024
.end
|
32bitmicro/newlib-nano-1.0
| 19,211
|
libgloss/hp74x/iva_table.s
|
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
.space $TEXT$
.subspa $CODE$,access=0x2c
#include "diagnose.h"
#if 0
#include "iva_table.h"
#endif
R_gr0 .equ 0
R_gr1 .equ 4
R_gr2 .equ 8
R_gr3 .equ 12
R_gr4 .equ 16
R_gr5 .equ 20
R_gr6 .equ 24
R_gr7 .equ 28
R_gr8 .equ 32
R_gr9 .equ 36
R_gr10 .equ 40
R_gr11 .equ 44
R_gr12 .equ 48
R_gr13 .equ 52
R_gr14 .equ 56
R_gr15 .equ 60
R_gr16 .equ 64
R_gr17 .equ 68
R_gr18 .equ 72
R_gr19 .equ 76
R_gr20 .equ 80
R_gr21 .equ 84
R_gr22 .equ 88
R_gr23 .equ 92
R_gr24 .equ 96
R_gr25 .equ 100
R_gr26 .equ 104
R_gr27 .equ 108
R_gr28 .equ 112
R_gr29 .equ 116
R_gr30 .equ 120
R_gr31 .equ 124
R_rctr .equ 160
R_cpu0 .equ 164
R_pidr1 .equ 168
R_pidr2 .equ 172
R_ccr .equ 176
R_sar .equ 180
R_pidr3 .equ 184
R_pidr4 .equ 188
R_iva .equ 192
R_eiem .equ 196
R_itmr .equ 200
R_pcsqH .equ 204
R_pcoqH .equ 208
R_iir .equ 212
R_pcsqT .equ 216
R_pcoqT .equ 220
R_isr .equ 224
R_ior .equ 228
R_ipsw .equ 232
R_eirr .equ 236
R_tr0 .equ 240
R_tr1 .equ 244
R_tr2 .equ 248
R_tr3 .equ 252
R_tr4 .equ 256
R_tr5 .equ 260
R_tr6 .equ 264
R_tr7 .equ 268
R_SIZE .equ 300
.import putc,code
.import puts,code
.import putnum,code
.import put_led,code
.import save_regs,code
.import STUB_RESTORE,code
.import RegBlk,data
.export iva_table,data
.IMPORT led_putnum,code
.IMPORT delay,code
.IMPORT putnum,code
.IMPORT outbyte,code
.IMPORT print,code
.align 2048
iva_table
.blockz 32 ; entry 0 is reserved
.align 32
hpmc
nop
b,n hpmc_handler
nop
.word 0
.word 0
.word 0
.word hpmc_handler
.word 0
.align 32
power_fail
; PrintString Str02,0x2
ldi 1,%r26
bl,n putnum,%r2
nop
.align 32
recovery
;; PrintString Str03,0x3
ldi 2,%r26
bl,n putnum,%r2
nop
ldi 3,%r1
b,n handle_rcc
nop
.align 32
external
; PrintString Str04,0x4
ldi 3,%r26
bl,n putnum,%r2
nop
.align 32
lpmc
; PrintString Str05,0x5
ldi 4,%r26
bl,n putnum,%r2
nop
.align 32
itlb_miss
; PrintString Str06,0x6
ldi 5,%r26
bl,n putnum,%r2
nop
.align 32
imem_protection
; PrintString Str07,0x7
ldi 6,%r26
bl,n putnum,%r2
nop
.align 32
illegal_inst
; PrintString Str08,0x8
ldi 7,%r26
bl,n putnum,%r2
nop
.align 32
break
b,n break_handler
nop
.align 32
privileged_op
; PrintString Str0a,0xa
ldi 8,%r26
bl,n putnum,%r2
nop
.align 32
privileged_reg
; PrintString Str0b,0xb
ldi 9,%r26
bl,n putnum,%r2
nop
.align 32
overflow
; PrintString Str0c,0xc
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
conditional
; PrintString Str0d,0xd
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
assist_excep
; PrintString Str0e,0xe
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
dtlb_miss
; PrintString Str0f,0xf
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
na_itlb
; PrintString Str10,0x10
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
na_dtlb
; PrintString Str11,0x11
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
dmem_protection
; PrintString Str12,0x12
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
dmem_break
; PrintString Str13,0x13
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
tlb_dirty
; PrintString Str14,0x14
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
page_ref
; PrintString Str15,0x15
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
assist_emul
; PrintString Str16,0x16
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
high_priv
; PrintString Str17,0x17
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
low_priv
; PrintString Str18,0x18
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
branch_taken
; PrintString Str19,0x19
ldi 32,%r26
bl,n putnum,%r2
nop
/*
* foobar -- debug procedure calling between C and assembler
*/
.EXPORT foobar,ENTRY,ARGW0=GR,RTNVAL=GR
foobar
.PROC
.CALLINFO CALLER,FRAME=128,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30) ; stash the return pointer
ldo 128(%r30),%r30 ; push up the stack pointer
ldi 8, %r26
bl,n led_putnum,%r2
nop
ldil L'900000,%r26
ldo R'900000(%r26),%r26
bl,n delay,%r2
nop
ldi 8, %r26
bl,n led_putnum,%r2
nop
ldil L'900000,%r26
ldo R'900000(%r26),%r26
bl,n delay,%r2
nop
;; copy %r26,%r26
;; bl,n putnum,%r2
nop
ldw -148(0,%r30),%r2 ; retrieve the return pointer
ldo -128(%r30),%r30 ; reset the stack pointer
bv,n 0(%r2)
nop
.EXIT
.PROCEND
/*
* setup_vectors -- add vectors for GDB to the vector table.
* %r3 - current vector table
* %r4 - new vector table
*/
.EXPORT setup_vectors,ENTRY,ARGW0=GR,RTNVAL=GR
setup_vectors
.PROC
.CALLINFO CALLER,FRAME=128,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30) ; stash the return pointer
ldo 128(%r30),%r30 ; push up the stack pointer
mfctl %iva,%r3
ldil L%iva_table,%r4 ; Get the new vector table
ldo R%iva_table(%r4),%r4 ; address
ldil L%break_handler,%r5 ; Get the breakpoint
ldo R%break_handler(%r5),%r5 ; handler vector
ldil L%break_default,%r6 ; Get the default handler
ldo R%break_default(%r6),%r6 ; vector
stw %r6,4(%r4) ; ad the default vector
stw %r5,36(%r4) ; add the break vector
mtctl %r4,%iva
ldw -148(0,%r30),%r2 ; retrieve the return pointer
ldo -128(%r30),%r30 ; reset the stack pointer
bv,n 0(%r2)
nop
.EXIT
.PROCEND
;-------------------------------------------------------------------------------
hpmc_handler
bl,n save_state,%r25
nop
bl print_intr,%rp
ldi Str01-Str01,%arg0
bl print_state,%rp
nop
ldil L%0xf0000000,%r1
ldw (%r1),%r1 ; read from ROM to reset HPMC
mfcpu_c 0,%r1
mfcpu_c 0,%r1
depi 0,CPU_DIAG_0_PREV_HPMC_PREP_BIT,1,%r1 ; clear Prev HPMC bit
#ifdef PCXL
depi 0,CPU_DIAG_0_L2DHPMC_BIT,1,%r1
depi 0,CPU_DIAG_0_L2IHPMC_BIT,1,%r1
depi 0,CPU_DIAG_0_L1IHPMC_BIT,1,%r1
depi 0,CPU_DIAG_0_L2PARERR_BIT,4,%r1
#else /* PCXT */
depi 0,CPU_DIAG_0_DHPMC_BIT,1,%r1 ; don't clear DHPMC
depi 0,CPU_DIAG_0_ILPMC_BIT,1,%r1 ; don't clear ILPMC
depi 0,CPU_DIAG_0_HTOC_BIT,1,%r1 ; don't clear HTOC
#endif
mtcpu %r1,0
mtcpu %r1,0
b,n restore_to_STUB
ldi 0x1,%r1
/*
* break_handler -- this is the main entry point for an exception
*/
.ALIGN 2048
break_handler
mfctl %iir,%r1 ; r1 = break instruction
extru %r1,18,13,%r8
ldo -i13BREAK(%r8),%r8 ; if im13 field doesn't match
comb,<>,n %r8,%r0,break_default ; go to default operation
extru %r1,31,5,%r8
ldi 0x9,%r1 ; set exception index
comib,=,n i5BP,%r8,break_breakpoint
comib,=,n i5PSW,%r8,break_psw
comib,=,n i5REG,%r8,break_reg_init
comib,=,n i5INLINE,%r8,break_breakpoint
; fall through to break_default
break_default
; PrintString Str09,0x9
ldi 32,%r26
bl,n putnum,%r2
nop
break_reg_init
bl setup_vectors,%r25
nop
bl save_regs,%r25
nop
; fall through to advance past break instruction
break_psw
b,n recover
break_breakpoint
b,n STUB_RESTORE
;-------------------------------------------------------------------------------
handle_rcc
mfctl %ipsw,%r1
bb,>=,n %r1,10,do_restore ; check nullify bit
dep %r0,10,1,%r1
mtctl %r1,%ipsw ; clear nullify bit
;; was the AdvancePCOQ .macro
mtctl %r0,%pcoq ; throw away iiaoq head pointer, tail->head
mfctl %pcoq,%r1 ; get tail pointer
mtctl %r1,%pcoq ; insert tail pointer
ldo 4(%r1),%r1 ; advance tail pointer
mtctl %r1,%pcoq ; insert new tail pointer, former tail->head
do_restore
b,n STUB_RESTORE
nop
;-------------------------------------------------------------------------------
print_intr
; %dp may be messed up, so do self-relocating to reach Save_area
blr %r0,%r1
addil L%Str01-pr_intr_0,%r1
pr_intr_0
ldo R%Str01-pr_intr_0(%r1),%r1 ; r1 points to Save_area
b puts ; print string--return through rp
add %r1,%arg0,%arg0
;-------------------------------------------------------------------------------
halt
; %dp may be messed up, so do self-relocating to reach Save_area
blr %r0,%r1
addil L%HaltStr-halt_0,%r1
halt_0
bl puts,%rp ; print halt message
ldo R%HaltStr-halt_0(%r1),%arg0
nop
b,n . ; loop forever
nop
;-------------------------------------------------------------------------------
recover
;; was the AdvancePCOQ .macro
mtctl %r0,%pcoq ; throw away iiaoq head pointer, tail->head
mfctl %pcoq,%r1 ; get tail pointer
mtctl %r1,%pcoq ; insert tail pointer
ldo 4(%r1),%r1 ; advance tail pointer
mtctl %r1,%pcoq ; insert new tail pointer, former tail->head
rfir
;-------------------------------------------------------------------------------
save_state ; %r25 is return pointer
; %dp may be messed up, so do self-relocating to reach Save_area
blr %r0,%r1
addil L%Save_area-sa_st_0,%r1
sa_st_0
ldo R%Save_area-sa_st_0(%r1),%r1 ; r1 points to Save_area
; save general registers
stw %r0,R_gr0(%r1)
; don't save %r1 until restored
stw %r2,R_gr2(%r1)
stw %r3,R_gr3(%r1)
stw %r4,R_gr4(%r1)
stw %r5,R_gr5(%r1)
stw %r6,R_gr6(%r1)
stw %r7,R_gr7(%r1)
; don't save %r8, %r9 until restored
stw %r10,R_gr10(%r1)
stw %r11,R_gr11(%r1)
stw %r12,R_gr12(%r1)
stw %r13,R_gr13(%r1)
stw %r14,R_gr14(%r1)
stw %r15,R_gr15(%r1)
; don't save %r16, %r17 until restored
stw %r18,R_gr18(%r1)
stw %r19,R_gr19(%r1)
stw %r20,R_gr20(%r1)
stw %r21,R_gr21(%r1)
stw %r22,R_gr22(%r1)
stw %r23,R_gr23(%r1)
; don't save %r24, %r25 until restored
stw %r26,R_gr26(%r1)
stw %r27,R_gr27(%r1)
stw %r28,R_gr28(%r1)
stw %r29,R_gr29(%r1)
copy %r25,%rp ; copy return pointer to %rp
stw %r30,R_gr30(%r1)
copy %r1,%r19 ; save Save_area pointer in %r19
stw %r31,R_gr31(%r1)
shdw_gr ; restore %r1 and %r25 (et al.) from shadow regs
shdw_gr
stw %r1,R_gr1(%r19) ; save %r1
stw %r8,R_gr8(%r19)
stw %r9,R_gr9(%r19)
stw %r16,R_gr16(%r19)
stw %r17,R_gr17(%r19)
stw %r24,R_gr24(%r19)
; save control registers
mfctl %rctr,%r1
stw %r1,R_rctr(%r19)
mfctl %pidr1,%r1
stw %r1,R_pidr1(%r19)
mfctl %pidr2,%r1
stw %r1,R_pidr2(%r19)
mfctl %ccr,%r1
stw %r1,R_ccr(%r19)
mfctl %sar,%r1
stw %r1,R_sar(%r19)
mfctl %pidr3,%r1
stw %r1,R_pidr3(%r19)
mfctl %pidr4,%r1
stw %r1,R_pidr4(%r19)
mfctl %iva,%r1
stw %r1,R_iva(%r19)
mfctl %eiem,%r1
stw %r1,R_eiem(%r19)
mfctl %itmr,%r1
stw %r1,R_itmr(%r19)
mfctl %pcsq,%r1
mtctl %r1,%pcsq
stw %r1,R_pcsqH(%r19)
mfctl %pcsq,%r1
mtctl %r1,%pcsq
stw %r1,R_pcsqT(%r19)
mfctl %pcoq,%r1
mtctl %r1,%pcoq
stw %r1,R_pcoqH(%r19)
mfctl %pcoq,%r1
mtctl %r1,%pcoq
stw %r1,R_pcoqT(%r19)
mfctl %iir,%r1
stw %r1,R_iir(%r19)
mfctl %isr,%r1
stw %r1,R_isr(%r19)
mfctl %ior,%r1
stw %r1,R_ior(%r19)
mfctl %ipsw,%r1
stw %r1,R_ipsw(%r19)
mfctl %eirr,%r1
stw %r1,R_eirr(%r19)
mfctl %tr0,%r1
stw %r1,R_tr0(%r19)
mfctl %tr1,%r1
stw %r1,R_tr1(%r19)
mfctl %tr2,%r1
stw %r1,R_tr2(%r19)
mfctl %tr3,%r1
stw %r1,R_tr3(%r19)
mfctl %tr4,%r1
stw %r1,R_tr4(%r19)
mfctl %tr5,%r1
stw %r1,R_tr5(%r19)
mfctl %tr6,%r1
stw %r1,R_tr6(%r19)
mfctl %tr7,%r1
stw %r1,R_tr7(%r19)
; save diagnose registers
mfcpu_c 0,%r1
mfcpu_c 0,%r1
stw %r1,R_cpu0(%r19)
#ifdef PRINT_SPACE
stw %r25,R_gr25(%r19)
; save space registers
mfsp %sr0,%r1
stw %r1,R_sr0(%r19)
mfsp %sr1,%r1
stw %r1,R_sr1(%r19)
mfsp %sr2,%r1
stw %r1,R_sr2(%r19)
mfsp %sr3,%r1
stw %r1,R_sr3(%r19)
mfsp %sr4,%r1
stw %r1,R_sr4(%r19)
mfsp %sr5,%r1
stw %r1,R_sr5(%r19)
mfsp %sr6,%r1
stw %r1,R_sr6(%r19)
mfsp %sr7,%r1
bv (%rp)
stw %r1,R_sr7(%r19)
#else
bv (%rp)
stw %r25,R_gr25(%r19)
#endif
;-------------------------------------------------------------------------------
restore_to_STUB ; doesn't return--goes to STUB_RESTORE
; Note--STUB_RESTORE executes rfir,
; so we don't need to
copy %r1,%r8 ; save exception index
; %dp may be messed up, so do self-relocating to reach Save_area
bl re_st_0,%r1
addil L%Save_area-re_st_0,%r1
re_st_0
ldo R%Save_area-re_st_0(%r1),%r1 ; r1 points to Save_area
; restore general registers
ldw R_gr2(%r1),%r2
ldw R_gr3(%r1),%r3
ldw R_gr4(%r1),%r4
ldw R_gr5(%r1),%r5
ldw R_gr6(%r1),%r6
ldw R_gr7(%r1),%r7
; ldw R_gr8(%r1),%r8 don't smash the exception index
ldw R_gr9(%r1),%r9
ldw R_gr10(%r1),%r10
ldw R_gr11(%r1),%r11
ldw R_gr12(%r1),%r12
ldw R_gr13(%r1),%r13
ldw R_gr14(%r1),%r14
ldw R_gr15(%r1),%r15
ldw R_gr16(%r1),%r16
ldw R_gr17(%r1),%r17
ldw R_gr18(%r1),%r18
ldw R_gr19(%r1),%r19
ldw R_gr20(%r1),%r20
ldw R_gr21(%r1),%r21
ldw R_gr22(%r1),%r22
ldw R_gr23(%r1),%r23
ldw R_gr24(%r1),%r24
ldw R_gr25(%r1),%r25
ldw R_gr26(%r1),%r26
ldw R_gr27(%r1),%r27
ldw R_gr28(%r1),%r28
ldw R_gr29(%r1),%r29
ldw R_gr30(%r1),%r30
ldw R_gr31(%r1),%r31
ldw R_gr1(%r1),%r1
b STUB_RESTORE
copy %r8,%r1 ; restore the exception index
;-------------------------------------------------------------------------------
#define HoldPtr %r10
#define SavePtr %r11
#define StrPtr %r12
#define Count %r13
#define Hold_Hold 0*4 /* First word of hold area */
#define Hold_Save 1*4 /* Second word of hold area */
#define Hold_Str 2*4 /* Third word of hold area */
#define Hold_Count 3*4 /* Fourth word of hold area */
#define Hold_rp 4*4 /* Fifth word of hold area */
print_state
; %dp may be messed up, so do self-relocating to reach Save_area
blr %r0,%mrp
addil L%Hold_area-pr_st_0,%mrp
pr_st_0
ldo R%Hold_area-pr_st_0(%r1),%r1 ; r1 points to Hold_area
; save working registers
stw HoldPtr,Hold_Hold(%r1)
copy %r1,HoldPtr ; HoldPtr = &Hold_area
stw SavePtr,Hold_Save(HoldPtr)
ldo Save_area-Hold_area(HoldPtr),SavePtr ; SavePtr = &Save_area
stw StrPtr,Hold_Str(HoldPtr)
addil L%PrintLabels-pr_st_0,%mrp
stw Count,Hold_Count(HoldPtr)
ldo R%PrintLabels-pr_st_0(%r1),StrPtr
stw %rp,Hold_rp(HoldPtr)
#ifdef PRINT_SPACE
ldi 68,Count
#else
ldo R_gr0(SavePtr),SavePtr
ldi 60,Count
#endif
; print register values
print_loop
bl puts,%rp ; print label
ldo 1(StrPtr),%arg0 ; advance past length byte
bl putnum,%rp ; print register value
ldwm 4(SavePtr),%arg0
ldbs,ma 1(StrPtr),%r1
addib,> -1,Count,print_loop
add %r1,StrPtr,StrPtr
; skip to next line
bl puts,%rp ; print label
ldo 1(StrPtr),%arg0 ; advance past length byte
; restore working registers
ldw Hold_rp(HoldPtr),%rp
ldw Hold_Count(HoldPtr),Count
ldw Hold_Str(HoldPtr),StrPtr
ldw Hold_Save(HoldPtr),SavePtr
bv (%rp)
ldw Hold_Hold(HoldPtr),HoldPtr
#undef SavePtr
#undef HoldPtr
#undef StrPtr
#undef Count
#undef Hold_Save
#undef Hold_Scr
#undef Hold_Str
#undef Hold_Count
#undef Hold_rp
;-------------------------------------------------------------------------------
.space $PRIVATE$
.subspa $DATA$,align=4,access=0x1f
/* Used to save machine registers before printing */
Save_area
.block R_SIZE ; Used to store registers
/* Used to hold callee-save registers */
Hold_area
.block 8*4 ; 8 words to store temp. registers
HaltStr
.stringz "\r\nHalted\r\n"
RebootStr
.stringz "\r\nRebooting . . .\r\n"
Str01
.stringz "\r\nHPMC\r\n"
Str02
.stringz "\r\nPower Fail\r\n"
Str03
.stringz "\r\nRecovery Counter Trap\r\n"
Str04
.stringz "\r\nExternal Interrupt\r\n"
Str05
.stringz "\r\nLPMC\r\n"
Str06
.stringz "\r\nITLB Miss\r\n"
Str07
.stringz "\r\nInstruction Memory Protection Trap\r\n"
Str08
.stringz "\r\nIllegal Instruction\r\n"
Str09
.stringz "\r\nBreak Trap\r\n"
Str0a
.stringz "\r\nPrivileged Operation\r\n"
Str0b
.stringz "\r\nPrivileged Register\r\n"
Str0c
.stringz "\r\nOverflow Trap\r\n"
Str0d
.stringz "\r\nConditional Trap\r\n"
Str0e
.stringz "\r\nAssist Exception\r\n"
Str0f
.stringz "\r\nData TLB Miss\r\n"
Str10
.stringz "\r\nNon-access ITLB Miss\r\n"
Str11
.stringz "\r\nNon-access DTLB Miss\r\n"
Str12
.stringz "\r\nData Memory Protection Trap\r\n"
Str13
.stringz "\r\nData Memory Break\r\n"
Str14
.stringz "\r\nTLB Dirty Bit Trap\r\n"
Str15
.stringz "\r\nPage Reference Trap\r\n"
Str16
.stringz "\r\nAssist Emulation Trap\r\n"
Str17
.stringz "\r\nHigher-privilege Trap\r\n"
Str18
.stringz "\r\nLower-privilege Trap\r\n"
Str19
.stringz "\r\nTaken Branch Trap\r\n"
Str20
.stringz "\r\nHere I am!\r\n"
PrintLabels
#ifdef PRINT_SPACE
.byte 10
.stringz "sr 0 = 0x"
.byte 13
.stringz "sr 1 = 0x"
.byte 13
.stringz "sr 2 = 0x"
.byte 13
.stringz " sr 3 = 0x"
.byte 12
.stringz "\r\nsr 4 = 0x"
.byte 13
.stringz " sr 5 = 0x"
.byte 13
.stringz " sr 6 = 0x"
.byte 13
.stringz " sr 7 = 0x"
.byte 13
.stringz "\r\n\ngr 0 = 0x"
#else
.byte 10
.stringz "gr 0 = 0x"
#endif
.byte 13
.stringz " gr 1 = 0x"
.byte 13
.stringz " gr 2 = 0x"
.byte 13
.stringz " gr 3 = 0x"
.byte 12
.stringz "\r\ngr 4 = 0x"
.byte 13
.stringz " gr 5 = 0x"
.byte 13
.stringz " gr 6 = 0x"
.byte 13
.stringz " gr 7 = 0x"
.byte 12
.stringz "\r\ngr 8 = 0x"
.byte 13
.stringz " gr 9 = 0x"
.byte 13
.stringz " gr10 = 0x"
.byte 13
.stringz " gr11 = 0x"
.byte 12
.stringz "\r\ngr12 = 0x"
.byte 13
.stringz " gr13 = 0x"
.byte 13
.stringz " gr14 = 0x"
.byte 13
.stringz " gr15 = 0x"
.byte 12
.stringz "\r\ngr16 = 0x"
.byte 13
.stringz " gr17 = 0x"
.byte 13
.stringz " gr18 = 0x"
.byte 13
.stringz " gr19 = 0x"
.byte 12
.stringz "\r\ngr20 = 0x"
.byte 13
.stringz " gr21 = 0x"
.byte 13
.stringz " gr22 = 0x"
.byte 13
.stringz " gr23 = 0x"
.byte 12
.stringz "\r\ngr24 = 0x"
.byte 13
.stringz " gr25 = 0x"
.byte 13
.stringz " gr26 = 0x"
.byte 13
.stringz " gr27 = 0x"
.byte 12
.stringz "\r\ngr28 = 0x"
.byte 13
.stringz " gr29 = 0x"
.byte 13
.stringz " gr30 = 0x"
.byte 13
.stringz " gr31 = 0x"
.byte 13
.stringz "\r\n\nrctr = 0x"
.byte 53
.stringz " cpu0 = 0x"
.byte 12
.stringz "\r\npid1 = 0x"
.byte 13
.stringz " pid2 = 0x"
.byte 13
.stringz " ccr = 0x"
.byte 13
.stringz " sar = 0x"
.byte 12
.stringz "\r\npid3 = 0x"
.byte 13
.stringz " pid4 = 0x"
.byte 13
.stringz " iva = 0x"
.byte 13
.stringz " eiem = 0x"
.byte 12
.stringz "\r\nitmr = 0x"
.byte 13
.stringz " iasq = 0x"
.byte 13
.stringz " iaoq = 0x"
.byte 13
.stringz " iir = 0x"
.byte 32
.stringz "\r\n iasq = 0x"
.byte 13
.stringz " iaoq = 0x"
.byte 12
.stringz "\r\n isr = 0x"
.byte 13
.stringz " ior = 0x"
.byte 13
.stringz " ipsw = 0x"
.byte 13
.stringz " eirr = 0x"
.byte 12
.stringz "\r\ncr24 = 0x"
.byte 13
.stringz " cr25 = 0x"
.byte 13
.stringz " cr26 = 0x"
.byte 13
.stringz " cr27 = 0x"
.byte 12
.stringz "\r\ncr28 = 0x"
.byte 13
.stringz " cr29 = 0x"
.byte 13
.stringz " cr30 = 0x"
.byte 13
.stringz " cr31 = 0x"
.byte 4
.stringz "\r\n\n"
.end
|
33cn/chain33
| 14,509
|
common/crypto/sha3/keccakf_amd64.s
|
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build amd64,!appengine,!gccgo
// This code was translated into a form compatible with 6a from the public
// domain sources at https://github.com/gvanas/KeccakCodePackage
// Offsets in state
#define _ba (0*8)
#define _be (1*8)
#define _bi (2*8)
#define _bo (3*8)
#define _bu (4*8)
#define _ga (5*8)
#define _ge (6*8)
#define _gi (7*8)
#define _go (8*8)
#define _gu (9*8)
#define _ka (10*8)
#define _ke (11*8)
#define _ki (12*8)
#define _ko (13*8)
#define _ku (14*8)
#define _ma (15*8)
#define _me (16*8)
#define _mi (17*8)
#define _mo (18*8)
#define _mu (19*8)
#define _sa (20*8)
#define _se (21*8)
#define _si (22*8)
#define _so (23*8)
#define _su (24*8)
// Temporary registers
#define rT1 AX
// Round vars
#define rpState DI
#define rpStack SP
#define rDa BX
#define rDe CX
#define rDi DX
#define rDo R8
#define rDu R9
#define rBa R10
#define rBe R11
#define rBi R12
#define rBo R13
#define rBu R14
#define rCa SI
#define rCe BP
#define rCi rBi
#define rCo rBo
#define rCu R15
#define MOVQ_RBI_RCE MOVQ rBi, rCe
#define XORQ_RT1_RCA XORQ rT1, rCa
#define XORQ_RT1_RCE XORQ rT1, rCe
#define XORQ_RBA_RCU XORQ rBa, rCu
#define XORQ_RBE_RCU XORQ rBe, rCu
#define XORQ_RDU_RCU XORQ rDu, rCu
#define XORQ_RDA_RCA XORQ rDa, rCa
#define XORQ_RDE_RCE XORQ rDe, rCe
#define mKeccakRound(iState, oState, rc, B_RBI_RCE, G_RT1_RCA, G_RT1_RCE, G_RBA_RCU, K_RT1_RCA, K_RT1_RCE, K_RBA_RCU, M_RT1_RCA, M_RT1_RCE, M_RBE_RCU, S_RDU_RCU, S_RDA_RCA, S_RDE_RCE) \
/* Prepare round */ \
MOVQ rCe, rDa; \
ROLQ $1, rDa; \
\
MOVQ _bi(iState), rCi; \
XORQ _gi(iState), rDi; \
XORQ rCu, rDa; \
XORQ _ki(iState), rCi; \
XORQ _mi(iState), rDi; \
XORQ rDi, rCi; \
\
MOVQ rCi, rDe; \
ROLQ $1, rDe; \
\
MOVQ _bo(iState), rCo; \
XORQ _go(iState), rDo; \
XORQ rCa, rDe; \
XORQ _ko(iState), rCo; \
XORQ _mo(iState), rDo; \
XORQ rDo, rCo; \
\
MOVQ rCo, rDi; \
ROLQ $1, rDi; \
\
MOVQ rCu, rDo; \
XORQ rCe, rDi; \
ROLQ $1, rDo; \
\
MOVQ rCa, rDu; \
XORQ rCi, rDo; \
ROLQ $1, rDu; \
\
/* Result b */ \
MOVQ _ba(iState), rBa; \
MOVQ _ge(iState), rBe; \
XORQ rCo, rDu; \
MOVQ _ki(iState), rBi; \
MOVQ _mo(iState), rBo; \
MOVQ _su(iState), rBu; \
XORQ rDe, rBe; \
ROLQ $44, rBe; \
XORQ rDi, rBi; \
XORQ rDa, rBa; \
ROLQ $43, rBi; \
\
MOVQ rBe, rCa; \
MOVQ rc, rT1; \
ORQ rBi, rCa; \
XORQ rBa, rT1; \
XORQ rT1, rCa; \
MOVQ rCa, _ba(oState); \
\
XORQ rDu, rBu; \
ROLQ $14, rBu; \
MOVQ rBa, rCu; \
ANDQ rBe, rCu; \
XORQ rBu, rCu; \
MOVQ rCu, _bu(oState); \
\
XORQ rDo, rBo; \
ROLQ $21, rBo; \
MOVQ rBo, rT1; \
ANDQ rBu, rT1; \
XORQ rBi, rT1; \
MOVQ rT1, _bi(oState); \
\
NOTQ rBi; \
ORQ rBa, rBu; \
ORQ rBo, rBi; \
XORQ rBo, rBu; \
XORQ rBe, rBi; \
MOVQ rBu, _bo(oState); \
MOVQ rBi, _be(oState); \
B_RBI_RCE; \
\
/* Result g */ \
MOVQ _gu(iState), rBe; \
XORQ rDu, rBe; \
MOVQ _ka(iState), rBi; \
ROLQ $20, rBe; \
XORQ rDa, rBi; \
ROLQ $3, rBi; \
MOVQ _bo(iState), rBa; \
MOVQ rBe, rT1; \
ORQ rBi, rT1; \
XORQ rDo, rBa; \
MOVQ _me(iState), rBo; \
MOVQ _si(iState), rBu; \
ROLQ $28, rBa; \
XORQ rBa, rT1; \
MOVQ rT1, _ga(oState); \
G_RT1_RCA; \
\
XORQ rDe, rBo; \
ROLQ $45, rBo; \
MOVQ rBi, rT1; \
ANDQ rBo, rT1; \
XORQ rBe, rT1; \
MOVQ rT1, _ge(oState); \
G_RT1_RCE; \
\
XORQ rDi, rBu; \
ROLQ $61, rBu; \
MOVQ rBu, rT1; \
ORQ rBa, rT1; \
XORQ rBo, rT1; \
MOVQ rT1, _go(oState); \
\
ANDQ rBe, rBa; \
XORQ rBu, rBa; \
MOVQ rBa, _gu(oState); \
NOTQ rBu; \
G_RBA_RCU; \
\
ORQ rBu, rBo; \
XORQ rBi, rBo; \
MOVQ rBo, _gi(oState); \
\
/* Result k */ \
MOVQ _be(iState), rBa; \
MOVQ _gi(iState), rBe; \
MOVQ _ko(iState), rBi; \
MOVQ _mu(iState), rBo; \
MOVQ _sa(iState), rBu; \
XORQ rDi, rBe; \
ROLQ $6, rBe; \
XORQ rDo, rBi; \
ROLQ $25, rBi; \
MOVQ rBe, rT1; \
ORQ rBi, rT1; \
XORQ rDe, rBa; \
ROLQ $1, rBa; \
XORQ rBa, rT1; \
MOVQ rT1, _ka(oState); \
K_RT1_RCA; \
\
XORQ rDu, rBo; \
ROLQ $8, rBo; \
MOVQ rBi, rT1; \
ANDQ rBo, rT1; \
XORQ rBe, rT1; \
MOVQ rT1, _ke(oState); \
K_RT1_RCE; \
\
XORQ rDa, rBu; \
ROLQ $18, rBu; \
NOTQ rBo; \
MOVQ rBo, rT1; \
ANDQ rBu, rT1; \
XORQ rBi, rT1; \
MOVQ rT1, _ki(oState); \
\
MOVQ rBu, rT1; \
ORQ rBa, rT1; \
XORQ rBo, rT1; \
MOVQ rT1, _ko(oState); \
\
ANDQ rBe, rBa; \
XORQ rBu, rBa; \
MOVQ rBa, _ku(oState); \
K_RBA_RCU; \
\
/* Result m */ \
MOVQ _ga(iState), rBe; \
XORQ rDa, rBe; \
MOVQ _ke(iState), rBi; \
ROLQ $36, rBe; \
XORQ rDe, rBi; \
MOVQ _bu(iState), rBa; \
ROLQ $10, rBi; \
MOVQ rBe, rT1; \
MOVQ _mi(iState), rBo; \
ANDQ rBi, rT1; \
XORQ rDu, rBa; \
MOVQ _so(iState), rBu; \
ROLQ $27, rBa; \
XORQ rBa, rT1; \
MOVQ rT1, _ma(oState); \
M_RT1_RCA; \
\
XORQ rDi, rBo; \
ROLQ $15, rBo; \
MOVQ rBi, rT1; \
ORQ rBo, rT1; \
XORQ rBe, rT1; \
MOVQ rT1, _me(oState); \
M_RT1_RCE; \
\
XORQ rDo, rBu; \
ROLQ $56, rBu; \
NOTQ rBo; \
MOVQ rBo, rT1; \
ORQ rBu, rT1; \
XORQ rBi, rT1; \
MOVQ rT1, _mi(oState); \
\
ORQ rBa, rBe; \
XORQ rBu, rBe; \
MOVQ rBe, _mu(oState); \
\
ANDQ rBa, rBu; \
XORQ rBo, rBu; \
MOVQ rBu, _mo(oState); \
M_RBE_RCU; \
\
/* Result s */ \
MOVQ _bi(iState), rBa; \
MOVQ _go(iState), rBe; \
MOVQ _ku(iState), rBi; \
XORQ rDi, rBa; \
MOVQ _ma(iState), rBo; \
ROLQ $62, rBa; \
XORQ rDo, rBe; \
MOVQ _se(iState), rBu; \
ROLQ $55, rBe; \
\
XORQ rDu, rBi; \
MOVQ rBa, rDu; \
XORQ rDe, rBu; \
ROLQ $2, rBu; \
ANDQ rBe, rDu; \
XORQ rBu, rDu; \
MOVQ rDu, _su(oState); \
\
ROLQ $39, rBi; \
S_RDU_RCU; \
NOTQ rBe; \
XORQ rDa, rBo; \
MOVQ rBe, rDa; \
ANDQ rBi, rDa; \
XORQ rBa, rDa; \
MOVQ rDa, _sa(oState); \
S_RDA_RCA; \
\
ROLQ $41, rBo; \
MOVQ rBi, rDe; \
ORQ rBo, rDe; \
XORQ rBe, rDe; \
MOVQ rDe, _se(oState); \
S_RDE_RCE; \
\
MOVQ rBo, rDi; \
MOVQ rBu, rDo; \
ANDQ rBu, rDi; \
ORQ rBa, rDo; \
XORQ rBi, rDi; \
XORQ rBo, rDo; \
MOVQ rDi, _si(oState); \
MOVQ rDo, _so(oState) \
// func keccakF1600(state *[25]uint64)
TEXT ·keccakF1600(SB), 0, $200-8
MOVQ state+0(FP), rpState
// Convert the user state into an internal state
NOTQ _be(rpState)
NOTQ _bi(rpState)
NOTQ _go(rpState)
NOTQ _ki(rpState)
NOTQ _mi(rpState)
NOTQ _sa(rpState)
// Execute the KeccakF permutation
MOVQ _ba(rpState), rCa
MOVQ _be(rpState), rCe
MOVQ _bu(rpState), rCu
XORQ _ga(rpState), rCa
XORQ _ge(rpState), rCe
XORQ _gu(rpState), rCu
XORQ _ka(rpState), rCa
XORQ _ke(rpState), rCe
XORQ _ku(rpState), rCu
XORQ _ma(rpState), rCa
XORQ _me(rpState), rCe
XORQ _mu(rpState), rCu
XORQ _sa(rpState), rCa
XORQ _se(rpState), rCe
MOVQ _si(rpState), rDi
MOVQ _so(rpState), rDo
XORQ _su(rpState), rCu
mKeccakRound(rpState, rpStack, $0x0000000000000001, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x0000000000008082, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x800000000000808a, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x8000000080008000, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x000000000000808b, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x0000000080000001, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x8000000080008081, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x8000000000008009, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x000000000000008a, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x0000000000000088, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x0000000080008009, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x000000008000000a, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x000000008000808b, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x800000000000008b, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x8000000000008089, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x8000000000008003, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x8000000000008002, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x8000000000000080, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x000000000000800a, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x800000008000000a, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x8000000080008081, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x8000000000008080, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpState, rpStack, $0x0000000080000001, MOVQ_RBI_RCE, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBA_RCU, XORQ_RT1_RCA, XORQ_RT1_RCE, XORQ_RBE_RCU, XORQ_RDU_RCU, XORQ_RDA_RCA, XORQ_RDE_RCE)
mKeccakRound(rpStack, rpState, $0x8000000080008008, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP)
// Revert the internal state to the user state
NOTQ _be(rpState)
NOTQ _bi(rpState)
NOTQ _go(rpState)
NOTQ _ki(rpState)
NOTQ _mi(rpState)
NOTQ _sa(rpState)
RET
|
32bitmicro/newlib-nano-1.0
| 2,338
|
libgloss/cris/crt0.S
|
/* Generic simplistic start-up-stub for CRIS/CRISv32.
Copyright (C) 1993-2005, 2007 Axis Communications.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Neither the name of Axis Communications nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
#undef cris
#undef L
#ifdef __NO_UNDERSCORES__
#define L(x) x
#else
#define L(x) _ ## x
#endif
; Rudimentary v0..v32-compatible startup stub.
#ifdef __ELF__
.section .startup,"ax"
#endif
.global __start
nop
__start:
move.d 0f,$r9
jump $r9
setf
#ifndef __ELF__
; For a.out, everything read-only and code-wise goes into a
; single section, so we can't separate the interrupt table from
; the startup code if we want to have files in-between.
#define IN_CRT0
#include "irqtable.S"
#else
; The interrupt table (at offset 12, irq #3) is expected here.
; The simplest way to make sure we link it in, is to sacrifice
; some memory and refer to it with a relocation.
.text
.dword __irqtable_at_irq3
#endif /* __ELF__ */
0:
move.d __setup,$r9
jsr $r9
nop
#ifdef __ELF__
jsr L(_init)
nop
move.d L(_fini),$r10
jsr L(atexit)
nop
#endif
jsr L(main)
nop
jsr L(exit)
nop
0:
nop
ba 0b
nop
|
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