repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
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| content
stringlengths 590
5.01M
|
|---|---|---|---|
4ms/metamodule-plugin-sdk
| 1,313
|
plugin-libc/libgcc/config/ft32/crti.S
|
# crti.S for FT32
#
# Copyright (C) 2009-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file just make a stack frame for the contents of the .fini and
# .init sections. Users may put any desired instructions in those
# sections.
.file "crti.S"
.section ".init"
.global _init
.type _init, @function
.p2align 2
_init:
.section ".fini"
.global _fini
.type _fini,@function
.p2align 2
_fini:
|
4ms/metamodule-plugin-sdk
| 4,023
|
plugin-libc/libgcc/config/ft32/prolog.S
|
.global __prolog_$r13
__prolog_$r13:
exi $r13,$sp,0
jmpi $r13
.global __prolog_$r14
__prolog_$r14:
exi $r13,$sp,0
push $r14
jmpi $r13
.global __prolog_$r15
__prolog_$r15:
exi $r13,$sp,0
push $r14
push $r15
jmpi $r13
.global __prolog_$r16
__prolog_$r16:
exi $r13,$sp,0
push $r14
push $r15
push $r16
jmpi $r13
.global __prolog_$r17
__prolog_$r17:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
jmpi $r13
.global __prolog_$r18
__prolog_$r18:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
jmpi $r13
.global __prolog_$r19
__prolog_$r19:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
jmpi $r13
.global __prolog_$r20
__prolog_$r20:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
jmpi $r13
.global __prolog_$r21
__prolog_$r21:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
jmpi $r13
.global __prolog_$r22
__prolog_$r22:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
jmpi $r13
.global __prolog_$r23
__prolog_$r23:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
jmpi $r13
.global __prolog_$r24
__prolog_$r24:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
jmpi $r13
.global __prolog_$r25
__prolog_$r25:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
push $r25
jmpi $r13
.global __prolog_$r26
__prolog_$r26:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
push $r25
push $r26
jmpi $r13
.global __prolog_$r27
__prolog_$r27:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
push $r25
push $r26
push $r27
jmpi $r13
.global __prolog_$r28
__prolog_$r28:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
push $r25
push $r26
push $r27
push $r28
jmpi $r13
|
4ms/metamodule-plugin-sdk
| 25,241
|
plugin-libc/libgcc/config/ft32/lib1funcs.S
|
# ieee754 sf routines for FT32
/* Copyright (C) 1995-2022 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
# See http://www.ens-lyon.fr/LIP/Pub/Rapports/PhD/PhD2006/PhD2006-02.pdf
# for implementation details of all except division which is detailed below
#
#ifdef L_fp_tools
// .global __cmpsf2_
nan: .long 0x7FFFFFFF # also abs mask
inf: .long 0x7F800000
sign_mask: .long 0x80000000
m_mask: .long 0x007FFFFF
exp_bias: .long 127
edge_case: .long 0x00FFFFFF
smallest_norm: .long 0x00800000 # implicit bit
high_FF: .long 0xFF000000
high_uint: .long 0xFFFFFFFF
ntz_table:
.byte 32,0,1,12,2,6,0,13,3,0,7,0,0,0,0,14
.byte 10,4,0,0,8,0,0,25,0,0,0,0,0,21,27,15
.byte 31,11,5,0,0,0,0,0,9,0,0,24,0,0,20,26
.byte 30,0,0,0,0,23,0,19,29,0,22,18,28,17,16,0
#endif
# Supply a few 'missing' instructions
# not
.macro not rd,r1
xor \rd,\r1,-1
.endm
# negate
.macro neg x
not \x, \x
add \x, \x, 1
.endm
# set $cc from the result of "ashl reg,dist"
.macro ashlcc reg,dist
.long 0x5de04008 | (\reg << 15) | (\dist << 4)
.endm
# converts an unsigned number x to a signed rep based on the bits in sign
# sign should be 0x00000000 or 0xffffffff.
.macro to_signed x, sign
add \x,\x,\sign # conditionally decrement x
xor \x,\x,\sign # conditionally complement x
.endm
.macro ld32 r,v
ldk \r,(\v>>10)
ldl \r,\r,(\v & 1023)
.endm
# calculate trailing zero count in x, also uses scr.
# Using Seal's algorithm
.macro ntz x, scr
not \scr, \x
add \scr, \scr, 1
and \x, \x, \scr
ashl \scr, \x, 4
add \x, \scr, \x
ashl \scr, \x, 6
add \x, \scr, \x
ashl \scr, \x, 16
sub \x, \scr, \x
lshr \x, \x, 26
ldk \scr, ntz_table
add \x, \x, \scr
lpmi.b \x, \x, 0
.endm
# calculate leading zero count
.macro nlz x, scr
flip \x, \x, 31
ntz \x, \scr
.endm
# Round 26 bit mantissa to nearest
# | 23 bits frac | G | R | S |
.macro round m, s1, s2
ldk \s1,0xc8
and \s2,\m,7
lshr \s1,\s1,\s2
and \s1,\s1,1
lshr \m,\m,2
add \m,\m,\s1
.endm
# If NZ, set the LSB of reg
.macro sticky reg
jmpc z,1f
or \reg,\reg,1 # set the sticky bit to 1
1:
.endm
##########################################################################
##########################################################################
## addition & subtraction
#if defined(L_subsf3) || defined(L_addsub_sf)
.global __subsf3
__subsf3:
# this is subtraction, so we just change the sign of r1
lpm $r2,sign_mask
xor $r1,$r1,$r2
jmp __addsf3
#endif
#if defined(L_addsf3) || defined(L_addsub_sf)
.global __addsf3
__addsf3:
# x in $r0, y in $r1, result z in $r0 --||| 100 instructions +/- |||--
# unpack e, calc d
bextu $r2,$r0,(8<<5)|23 # ex in r2
bextu $r3,$r1,(8<<5)|23 # ey in r3
sub $r5,$r2,$r3 # d = ex - ey
# Special values are 0x00 and 0xff in ex and ey.
# If (ex&ey) != 0 or (xy|ey)=255 then there may be
# a special value.
tst $r2,$r3
jmpc nz,1f
jmp slow
1: or $r4,$r2,$r3
cmp $r4,255
jmpc nz,no_special_vals
slow:
# Check for early exit
cmp $r2,0
jmpc z,test_if_not_255
cmp $r3,0
jmpc nz,no_early_exit
test_if_not_255:
cmp $r2,255
jmpc z,no_early_exit
cmp $r3,255
jmpc z,no_early_exit
or $r6,$r2,$r3
cmp $r6,0
jmpc nz,was_not_zero
and $r0,$r0,$r1
lpm $r1,sign_mask
and $r0,$r0,$r1
return
was_not_zero:
cmp $r2,0
jmpc nz,ret_x
move $r0,$r1
return
ret_x:
return
no_early_exit:
# setup to test for special values
sub $r6,$r2,1
and $r6,$r6,0xFE
sub $r7,$r3,1
and $r7,$r7,0xFE
# test for special values
cmp $r6,$r7
jmpc gte,ex_spec_is_gte
move $r6,$r7
ex_spec_is_gte:
cmp $r6,0xFE
jmpc nz,no_special_vals
cmp $r5,0
jmpc ns,d_gte_0
cmp $r3,0xFF
jmpc z,ret_y
cmp $r2,0
jmpc z,ret_y
ret_y:
move $r0,$r1
return
d_gte_0:
cmp $r5,0
jmpc z,d_is_0
cmp $r2,0xFF
jmpc z,ret_x
cmp $r3,0
jmpc z,ret_x
d_is_0:
cmp $r2,0xFF
jmpc nz,no_special_vals
ashl $r6,$r0,9 # clear all except x frac
ashl $r7,$r1,9 # clear all except y frac
or $r6,$r6,$r7
cmp $r6,0
jmpc nz,ret_nan
lshr $r4,$r0,31 # sx in r4
lshr $r5,$r1,31 # sy in r4
cmp $r4,$r5
jmpc nz,ret_nan
return
ret_nan:
lpm $r0,nan
return
no_special_vals:
ldk $r8,(1<<10)|(9<<5)|26 # setup implicit bit and mask for e
#----------------------
ashr $r4,$r0,31 # sx in r4
ashl $r0,$r0,3 # shift mx 3 for GRS bits
bins $r0,$r0,$r8 # clear sx, ex and add implicit bit mx
# change mx to signed mantissa
to_signed $r0,$r4
#----------------------
ashr $r4,$r1,31 # sy in r4
ashl $r1,$r1,3 # shift my 3 for GRS bits
bins $r1,$r1,$r8 # clear sy, ey and add implicit bit my
# change my to signed mantissa
to_signed $r1,$r4
#----------------------
# test if we swap ms based on d sign
cmp $r5,0
jmpc gte,noswap
# swap mx & my
xor $r0,$r0,$r1
xor $r1,$r0,$r1
xor $r0,$r0,$r1
# d positive means that ex>=ey, so ez = ex
# d negative means that ey>ex, so ez = ey
move $r2,$r3
# |d|
neg $r5
noswap:
# now $r2 = ez = max(ex,ey)
cmp $r5,26 # max necessary alignment shift is 26
jmpc lt,under_26
ldk $r5,26
under_26:
ldk $r7,-1
ashl $r7,$r7,$r5 # create inverse of mask for test of S bit value in discarded my
not $r7,$r7
tst $r1,$r7 # determine value of sticky bit
# shift my >> |d|
ashr $r1,$r1,$r5
sticky $r1
# add ms
add $r0,$r0,$r1
# $r4 = sign(mx), mx = |mx|
ashr $r4,$r0,31
xor $r0,$r0,$r4
sub $r0,$r0,$r4
# realign mantissa using leading zero count
flip $r7,$r0,31
ntz $r7,$r8
ashl $r0,$r0,$r7
btst $r0,(6<<5)|0 # test low bits for sticky again
lshr $r0,$r0,6
sticky $r0
# update exponent
add $r2,$r2,5
sub $r2,$r2,$r7
# Round to nearest
round $r0,$r7,$r6
# detect_exp_update
lshr $r6,$r0,24
add $r2,$r2,$r6
# final tests
# mz == 0? if so, we just bail with a +0
cmp $r0,0
jmpc nz,msum_not_zero
ldk $r0,0
return
msum_not_zero:
# Combined check that (1 <= ez <= 254)
sub $r3,$r2,1
cmp $r3,254
jmpc b,no_special_ret
# underflow?
cmp $r2,0
jmpc gt,no_under
ldk $r0,0
jmp pack_sz
no_under:
# overflow?
cmp $r2,255
jmpc lt,no_special_ret
ldk $r0,0x7F8
ashl $r0,$r0,20
jmp pack_sz
no_special_ret:
# Pack ez
ldl $r2,$r2,(8<<5)|23
bins $r0,$r0,$r2 # width = 8, pos = 23 pack ez
# Pack sz
pack_sz:
ldl $r4,$r4,(1<<5)|31
bins $r0,$r0,$r4 # width = 1, pos = 31 set sz to sy
return
#endif
##########################################################################
##########################################################################
## multiplication
#ifdef L_mulsf3
.global __mulsf3
__mulsf3:
# x in $r0, y in $r1, result z in $r0 --||| 61 instructions +/- |||--
# unpack e
bextu $r2,$r0,(8<<5)|23 # ex in r2
bextu $r3,$r1,(8<<5)|23 # ey in r3
# calc result sign
xor $r4,$r0,$r1
lpm $r5,sign_mask
and $r4,$r4,$r5 # sz in r4
# unpack m add implicit bit
ldk $r5,(1<<10)|(9<<5)|23 # setup implicit bit and mask for e
#----------------------
bins $r0,$r0,$r5 # clear sx, ex and add implicit bit mx
sub $r6,$r2,1
cmp $r6,254
jmpc b,1f
jmp slow_mul
1: sub $r6,$r3,1
cmp $r6,254
jmpc b,no_special_vals_mul
slow_mul:
# Check for early exit
cmp $r2,0
jmpc z,op_is_zero
cmp $r3,0
jmpc nz,no_early_exit_mul
op_is_zero:
cmp $r2,255
jmpc z,no_early_exit_mul
cmp $r3,255
jmpc z,no_early_exit_mul
move $r0,$r4
return
no_early_exit_mul:
# setup to test for special values
sub $r6,$r2,1
and $r6,$r6,0xFE
sub $r7,$r3,1
and $r7,$r7,0xFE
# test for special values
cmp $r6,$r7
jmpc gte,ex_spec_is_gte_ey_mul
move $r6,$r7
ex_spec_is_gte_ey_mul:
cmp $r6,0xFE
jmpc nz,no_special_vals_mul
cmp $r2,0xFF
jmpc nz,ex_not_FF_mul
ashl $r6,$r0,9
cmp $r6,0
jmpc nz,ret_nan
cmp $r3,0
jmpc z,ret_nan
ashl $r6,$r1,1
lpm $r7,high_FF
cmp $r6,$r7
jmpc a,ret_nan
cmp $r6,0
jmpc z,ret_nan
# infinity
lpm $r0,inf
or $r0,$r0,$r4
return
ex_not_FF_mul:
cmp $r2,0
jmpc nz,no_nan_mul
cmp $r3,0xFF
jmpc nz,no_nan_mul
jmp ret_nan
no_nan_mul:
lpm $r0,nan
and $r0,$r0,$r1
or $r0,$r0,$r4
return
ret_nan:
lpm $r0,nan
return
no_special_vals_mul:
bins $r1,$r1,$r5 # clear sy, ey and add implicit bit my
# calc ez
add $r3,$r2,$r3
sub $r3,$r3,127 # ez in r3
# (r1,r2) = R0 * R1
mul $r2,$r0,$r1
muluh $r1,$r0,$r1
btst $r1,(1<<5)|15 # XXX use jmpx
jmpc z,mul_z0
# mz is 1X.XX...X
# 48-bit product is in (r1,r2). The low 22 bits of r2
# are discarded.
lshr $r0,$r2,22
ashl $r1,$r1,10
or $r0,$r0,$r1 # r0 = (r1,r2) >> 22
ashlcc 2,10
sticky $r0
add $r3,$r3,1 # bump exponent
# Round to nearest
round $r0, $r1, $r2
lshr $r6,$r0,24
add $r3,$r3,$r6
sub $r6,$r3,1
cmp $r6,254
jmpc b,no_special_ret_mul
special_ret_mul:
# When the final exponent <= 0, result is flushed to 0 except
# for the border case 0x00FFFFFF which is promoted to next higher
# FP no., that is, the smallest "normalized" number.
cmp $r3,0
jmpc gt,exp_normal
# Pack ez
ldl $r3,$r3,(8<<5)|23
bins $r0,$r0,$r3 # width = 8, pos = 23 pack ez
lpm $r2,edge_case
cmp $r0,$r2
jmpc nz,no_edge_case
lpm $r0,smallest_norm
jmp pack_sz_mul
no_edge_case:
ldk $r0,0
jmp pack_sz_mul
exp_normal:
# overflow?
cmp $r3,255
jmpc lt,no_special_ret_mul
ldk $r0,0x7F8
ashl $r0,$r0,20
jmp pack_sz_mul
no_special_ret_mul:
# Pack ez
ldl $r3,$r3,(8<<5)|23
bins $r0,$r0,$r3 # width = 8, pos = 23 pack ez
# Pack sz
pack_sz_mul:
or $r0,$r0,$r4
return
mul_z0:
# mz is 0X.XX...X
# 48-bit product is in (r1,r2). The low 21 bits of r2
# are discarded.
lshr $r0,$r2,21
ashl $r1,$r1,11
or $r0,$r0,$r1 # r0 = (r1,r2) >> 22
ashlcc 2,11
sticky $r0
# Round to nearest
round $r0, $r1, $r2
lshr $r6,$r0,24
add $r3,$r3,$r6
sub $r6,$r3,1
cmp $r6,254
jmpc b,no_special_ret_mul
jmp special_ret_mul
#endif
##########################################################################
##########################################################################
## division
## See http://perso.ens-lyon.fr/gilles.villard/BIBLIOGRAPHIE/PDF/arith19.pdf
## for implementation details
#ifdef L_divsf3
dc_1: .long 0xffffe7d7
dc_2: .long 0xffffffe8
dc_3: .long 0xffbad86f
dc_4: .long 0xfffbece7
dc_5: .long 0xf3672b51
dc_6: .long 0xfd9d3a3e
dc_7: .long 0x9a3c4390
dc_8: .long 0xd4d2ce9b
dc_9: .long 0x1bba92b3
dc_10: .long 0x525a1a8b
dc_11: .long 0x0452b1bf
dc_12: .long 0xFFFFFFC0
spec_val_test: .long 0x7F7FFFFF
.global __divsf3
__divsf3:
push $r13
# x in $r0, y in $r1, result z in $r0 --||| 73 instructions +/- |||-
bextu $r10,$r0,(8<<5)|23 # ex in r2
bextu $r11,$r1,(8<<5)|23 # ey in r3
lpm $r6, m_mask
and $r2, $r0, $r6 # mx
and $r3, $r1, $r6 # my
cmp $r2,$r3
bextu $r2,$r30,(1<<5)|4 # c = Tx >= T;
ashl $r3,$r3,9 # T = X << 9;
lpm $r13, sign_mask
ashl $r4,$r0,8 # X8 = X << 8;
or $r4,$r4,$r13 # Mx = X8 | 0x80000000;
lshr $r5,$r4,$r2 # S = Mx >> c;
# calc D
sub $r2, $r11, $r2
add $r12, $r10, 125
sub $r2, $r12, $r2 # int D = (Ex + 125) - (Ey - c);
# calc result sign
xor $r12,$r0,$r1
and $r12,$r12,$r13 # Sr = ( X ˆ Y ) & 0x80000000;
# check early exit
cmp $r10, 0
jmpc nz, no_early_ret_dev
cmp $r11, 0
jmpc z, no_early_ret_dev
cmp $r11, 255
jmpc z, no_early_ret_dev
move $r0, $r12
pop $r13
return
no_early_ret_dev:
# setup to test for special values
sub $r8,$r10,1
and $r8,$r8,0xFE
sub $r9,$r11,1
and $r9,$r9,0xFE
# test for special values
cmp $r8, $r9
jmpc gte, absXm1_gte_absYm1
move $r8, $r9
absXm1_gte_absYm1:
cmp $r8, 0xFE
jmpc nz, no_spec_ret_div
cmp $r10, 0xFF
jmpc nz, ex_not_FF_div
lpm $r6, m_mask
and $r2, $r0, $r6 # mx
cmp $r2, 0
jmpc nz, ret_nan_div
cmp $r11, 0xFF
jmpc z, ret_nan_div
jmp ret_inf_div
ex_not_FF_div:
cmp $r11, 0xFF
jmpc nz, ey_not_FF_div
ashl $r13, $r1, 9
cmp $r13, 0
jmpc nz, ret_nan_div
move $r0, $r12
pop $r13
return
ey_not_FF_div:
or $r10, $r10, $r11
cmp $r10, 0
jmpc z, ret_nan_div
ret_inf_div:
lpm $r6, inf
move $r0, $r6
or $r0, $r0, $r12
pop $r13
return
ret_nan_div:
lpm $r0, nan
pop $r13
return
no_spec_ret_div:
# check for overflow
ldk $r6, 0xFE
cmp $r2, $r6
jmpc lt, no_overflow_div
lpm $r6, inf
or $r0, $r12, $r6
pop $r13
return
no_overflow_div:
# check for underflow
cmp $r2, 0
jmpc ns, no_underflow_div
xnor $r6, $r6, $r6 # -1
cmp $r2, $r6
jmpc nz, ret_sr_div
ldk $r7, 0xFF
xor $r6, $r6, $r7 # 0xFF ^ -1 = 0xFFFFFF00
cmp $r4, $r6
jmpc nz, ret_sr_div
lpm $r6, sign_mask
cmp $r4, $r6
jmpc nz, ret_sr_div
lshr $r0, $r6, 8
or $r0, $r0, $r12
pop $r13
return
ret_sr_div:
move $r0, $r12
pop $r13
return
no_underflow_div:
lpm $r6, dc_1
muluh $r7, $r3, $r6 # i0 = mul( T , 0xffffe7d7 );
lpm $r6, dc_2
sub $r7, $r6, $r7 # i1 = 0xffffffe8 - i0;
muluh $r7, $r5, $r7 # i2 = mul( S , i1 );
add $r7, $r7, 0x20 # i3 = 0x00000020 + i2;
muluh $r8, $r3, $r3 # i4 = mul( T , T );
muluh $r9, $r5, $r8 # i5 = mul( S , i4 );
lpm $r6, dc_3
muluh $r10, $r3, $r6 # i6 = mul( T , 0xffbad86f );
lpm $r6, dc_4
sub $r10, $r6, $r10 # i7 = 0xfffbece7 - i6;
muluh $r10, $r9, $r10 # i8 = mul( i5 , i7 );
add $r7, $r7, $r10 # i9 = i3 + i8;
muluh $r9, $r8, $r9 # i10 = mul( i4 , i5 );
lpm $r6, dc_5
muluh $r10, $r3, $r6 # i11 = mul( T , 0xf3672b51 );
lpm $r6, dc_6
sub $r10, $r6, $r10 # i12 = 0xfd9d3a3e - i11;
lpm $r6, dc_7
muluh $r11, $r3, $r6 # i13 = mul( T , 0x9a3c4390 );
lpm $r6, dc_8
sub $r11, $r6, $r11 # i14 = 0xd4d2ce9b - i13
muluh $r11, $r8, $r11 # i15 = mul( i4 , i14 );
add $r10, $r10, $r11 # i16 = i12 + i15;
muluh $r10, $r9, $r10 # i17 = mul( i10 , i16 )
add $r7, $r7, $r10 # i18 = i9 + i17;
muluh $r10, $r8, $r8 # i19 = mul( i4 , i4 );
lpm $r6, dc_9
muluh $r11, $r3, $r6 # i20 = mul( T , 0x1bba92b3 );
lpm $r6, dc_10
sub $r11, $r6, $r11 # i21 = 0x525a1a8b - i20;
lpm $r6, dc_11
muluh $r8, $r8, $r6 # i22 = mul( i4 , 0x0452b1bf );
add $r8, $r11, $r8 # i23 = i21 + i22;
muluh $r8, $r10, $r8 # i24 = mul( i19 , i23 );
muluh $r8, $r9, $r8 # i25 = mul( i10 , i24 );
add $r3, $r7, $r8 # V = i18 + i25;
# W = V & 0xFFFFFFC0;
lpm $r6, dc_12
and $r3, $r3, $r6 # W
# round and pack final values
ashl $r0, $r2, 23 # pack D
or $r0, $r0, $r12 # pack Sr
ashl $r12, $r1, 8
or $r12, $r12, $r13 # My
muluh $r10, $r3, $r12
lshr $r11, $r5, 1
cmp $r10, $r11
jmpc gte, div_ret_1
add $r3, $r3, 0x40
div_ret_1:
lshr $r3, $r3, 7
add $r0, $r0, $r3
pop $r13
return
#endif
##########################################################################
##########################################################################
## Negate
#ifdef L_negsf
.global __negsf
__negsf:
lpm $r1, sign_mask
xor $r0, $r0, $r1
return
#endif
##########################################################################
##########################################################################
## float to int & unsigned int
#ifdef L_fixsfsi
.global __fixsfsi
__fixsfsi: # 20 instructions
bextu $r1,$r0,(8<<5)|23 # e in r1
lshr $r2,$r0,31 # s in r2
lpm $r3, m_mask
and $r0,$r0,$r3 # m in r0
# test nan
cmp $r1,0xFF
jmpc nz, int_not_nan
cmp $r0,0
jmpc z, int_not_nan
ldk $r0,0
return
int_not_nan:
# test edges
cmp $r1, 127
jmpc gte, int_not_zero # lower limit
ldk $r0,0
return
int_not_zero:
cmp $r1, 158
jmpc lt, int_not_max # upper limit
lpm $r0, nan
cmp $r2, 0
jmpc z, int_positive
xnor $r0, $r0, 0
return
int_not_max:
lpm $r3, smallest_norm
or $r0, $r0, $r3 # set implicit bit
sub $r1, $r1, 150
cmp $r1, 0
jmpc s, shift_right
ashl $r0, $r0, $r1
jmp set_int_sign
shift_right:
xnor $r1, $r1, 0
add $r1, $r1, 1
lshr $r0, $r0, $r1
set_int_sign:
cmp $r2, 0
jmpc z, int_positive
xnor $r0, $r0, 0
add $r0, $r0, 1
int_positive:
return
#endif
#ifdef L_fixunssfsi
.global __fixunssfsi
__fixunssfsi: # 19 instructions
lshr $r2, $r0, 31 # s in r2
cmp $r2, 0
jmpc z, uint_not_neg
ldk $r0, 0
return
uint_not_neg:
bextu $r1, $r0, (8<<5)|23 # e in r1
sub $r1, $r1, 127
lpm $r3, m_mask
and $r0, $r0, $r3 # m in r0
# test nan
cmp $r1, 0xFF
jmpc nz, uint_not_nan
cmp $r0, 0
jmpc z, uint_not_nan
ldk $r0, 0
return
uint_not_nan:
# test edges
cmp $r1, 0
jmpc ns, uint_not_zero # lower limit
ldk $r0, 0
return
uint_not_zero:
lpm $r3, smallest_norm
or $r0, $r0, $r3 # set implicit bit
cmp $r1, 23
jmpc lt, shift_uint_right
sub $r1, $r1, 23
ashl $r0, $r0, $r1
return
shift_uint_right:
ldk $r3, 23
sub $r1, $r3, $r1
lshr $r0, $r0, $r1
return
#endif
##########################################################################
##########################################################################
## int & unsigned int to float
.macro i2f x, s1, s2, s3, lbl
move \s1, \x
nlz \s1, \s2
cmp \s1, 8
jmpc s, float_round\lbl
sub \s2, \s1, 8
ashl \x, \x, \s2
jmp float_no_round\lbl
float_round\lbl:
cmp \s1, 6
jmpc s, float_shift_right\lbl
sub \s2, \s1, 6
ashl \x, \x, \s2
jmp float_round_and_pack\lbl
float_shift_right\lbl:
ldk \s2, 6
sub \s2, \s2, \s1
xnor \s3, \s3 ,\s3 # 0xFFFFFFFF
ashl \s3, \s3 ,\s2 # create inverse of mask for test of S bit value in discarded my
xnor \s3, \s3 ,0 # NOT
tst \x, \s3 # determine value of sticky bit
lshr \x, \x, \s2
jmpc z,float_round_and_pack\lbl
or \x, \x, 1 # set the sticky bit to 1
float_round_and_pack\lbl:
bextu \s2, \x, (1<<5)|2 # extract low bit of m
or \x, \x, \s2 # or p into r
add \x, \x, 1
lshr \x, \x, 2
btst \x, (1<<5)|24 # test for carry from round
jmpc z, float_no_round\lbl
sub \s1, \s1, 1 # inc e for carry (actually dec nlz)
lshr \x, \x, 1
float_no_round\lbl:
ldk \s2, 158
sub \s1, \s2, \s1
# Pack e
ldl \s1, \s1, (8<<5)|23
bins \x, \x, \s1
.endm
#ifdef L_floatsisf
.global __floatsisf
__floatsisf: # 32 instructions
cmp $r0, 0
jmpc nz, float_not_zero
return
float_not_zero:
ashr $r1, $r0, 31 # s in r1
xor $r0, $r0, $r1 # cond neg
sub $r0, $r0, $r1
i2f $r0, $r2, $r3, $r4, 1
ldl $r1, $r1, (1<<5)|31
bins $r0, $r0, $r1
return
#endif
#ifdef L_floatunsisf
.global __floatunsisf
__floatunsisf: # 26 instructions
cmp $r0, 0
jmpc nz, float_not_zero2
return
float_not_zero2:
i2f $r0, $r1, $r2, $r3, 2
return
#endif
#if 0
##########################################################################
##########################################################################
## float compare
__cmpsf2_:
# calc abs vals
lpm $r3, nan # also abs mask
and $r2, $r0, $r3
and $r3, $r1, $r3
# test if either abs is nan
lpm $r4, inf
cmp $r2, $r4
jmpc gt, cmp_is_gt
cmp $r3, $r4
jmpc gt, cmp_is_gt
# test if both are 0
or $r2, $r2, $r3
cmp $r2, 0
jmpc z, cmp_is_eq
# test if eq
cmp $r0, $r1
jmpc z, cmp_is_eq
# -- if either is pos
and $r2, $r0, $r1
cmp $r2, 0
jmpc s, cmp_both_neg
cmp $r0, $r1
jmpc gt, cmp_is_gt
# r0 < r1
lpm $r0, high_uint
return
cmp_both_neg:
cmp $r0, $r1
jmpc lt, cmp_is_gt
# r0 < r1
lpm $r0, high_uint
return
cmp_is_gt:
ldk $r0, 1
return
cmp_is_eq:
ldk $r0, 0
return
#endif
#ifdef L_udivsi3
.global __udivsi3
__udivsi3:
# $r0 is dividend
# $r1 is divisor
ldk $r2,0
push $r28
ldk $r28,-32
0:
lshr $r3,$r0,31 # Shift $r2:$r0 left one
ashl $r0,$r0,1
ashl $r2,$r2,1
or $r2,$r2,$r3
cmp $r2,$r1
jmpc b,1f
2:
sub $r2,$r2,$r1
add $r0,$r0,1
1:
add $r28,$r28,1
jmpx 31,$r28,1,0b
pop $r28
# $r0: quotient
# $r2: remainder
return
#endif
#ifdef L_umodsi3
.global __umodsi3
__umodsi3:
call __udivsi3
move $r0,$r2
return
#endif
#ifdef L_divsi3
.global __divsi3
__divsi3:
xor $r5,$r0,$r1 # $r5 is sign of result
ashr $r2,$r0,31 # $r0 = abs($r0)
xor $r0,$r0,$r2
sub $r0,$r0,$r2
ashr $r2,$r1,31 # $r1 = abs($r1)
xor $r1,$r1,$r2
sub $r1,$r1,$r2
call __udivsi3
ashr $r5,$r5,31
xor $r0,$r0,$r5
sub $r0,$r0,$r5
return
#endif
#ifdef L_modsi3
.global __modsi3
__modsi3:
move $r5,$r0 # $r5 is sign of result
ashr $r2,$r0,31 # $r0 = abs($r0)
xor $r0,$r0,$r2
sub $r0,$r0,$r2
ashr $r2,$r1,31 # $r1 = abs($r1)
xor $r1,$r1,$r2
sub $r1,$r1,$r2
call __umodsi3
ashr $r5,$r5,31
xor $r0,$r0,$r5
sub $r0,$r0,$r5
return
#endif
|
4ms/metamodule-plugin-sdk
| 1,525
|
plugin-libc/libgcc/config/mips/crtn.S
|
/* Copyright (C) 2001-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#include "gnustack.h"
/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */
#ifdef __mips16
#define RA $7
#else
#define RA $31
#endif
.section .init,"ax",@progbits
init:
#ifdef __mips64
ld RA,40($sp)
daddu $sp,$sp,48
#else
lw RA,20($sp)
addu $sp,$sp,32
#endif
j RA
.section .fini,"ax",@progbits
fini:
#ifdef __mips64
ld RA,40($sp)
daddu $sp,$sp,48
#else
lw RA,20($sp)
addu $sp,$sp,32
#endif
j RA
|
4ms/metamodule-plugin-sdk
| 21,069
|
plugin-libc/libgcc/config/mips/mips16.S
|
/* mips16 floating point support code
Copyright (C) 1996-2022 Free Software Foundation, Inc.
Contributed by Cygnus Support
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#include "gnustack.h"
#include "auto-host.h"
#if defined(__mips_micromips) || defined(__mips_soft_float) \
|| __mips_isa_rev >= 6
/* Do nothing because this code is only needed when linking
against mips16 hard-float objects. Neither micromips code
nor soft-float nor MIPS R6 code can be linked against mips16
hard-float objects so we do not need these routines when
building libgcc for those cases. */
#else
#if defined(HAVE_AS_MODULE)
#if __mips_fpr == 32
.module fp=32
#elif __mips_fpr == 0
.module fp=xx
#elif __mips_fpr == 64
.module fp=64
#endif
#endif
/* This file contains mips16 floating point support functions. These
functions are called by mips16 code to handle floating point when
-msoft-float is not used. They accept the arguments and return
values using the soft-float calling convention, but do the actual
operation using the hard floating point instructions. */
#if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64)
/* This file contains 32-bit assembly code. */
.set nomips16
/* Start a function. */
#define STARTFN(NAME) .globl NAME; .ent NAME; NAME:
/* Finish a function. */
#define ENDFN(NAME) .end NAME
/* ARG1
The FPR that holds the first floating-point argument.
ARG2
The FPR that holds the second floating-point argument.
RET
The FPR that holds a floating-point return value. */
#define RET $f0
#define ARG1 $f12
#ifdef __mips64
#define ARG2 $f13
#else
#define ARG2 $f14
#endif
/* Set 64-bit register GPR so that its high 32 bits contain HIGH_FPR
and so that its low 32 bits contain LOW_FPR. */
#define MERGE_GPRf(GPR, HIGH_FPR, LOW_FPR) \
.set noat; \
mfc1 $1, LOW_FPR; \
mfc1 GPR, HIGH_FPR; \
dsll $1, $1, 32; \
dsll GPR, GPR, 32; \
dsrl $1, $1, 32; \
or GPR, GPR, $1; \
.set at
/* Move the high 32 bits of GPR to HIGH_FPR and the low 32 bits of
GPR to LOW_FPR. */
#define MERGE_GPRt(GPR, HIGH_FPR, LOW_FPR) \
.set noat; \
dsrl $1, GPR, 32; \
mtc1 GPR, LOW_FPR; \
mtc1 $1, HIGH_FPR; \
.set at
/* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */
#define DELAYt(T, OPCODE, OP2) \
.set noreorder; \
jr T; \
OPCODE, OP2; \
.set reorder
#if __mips >= 4
/* Coprocessor moves are interlocked from the MIPS IV ISA up. */
#define DELAYf(T, OPCODE, OP2) DELAYt (T, OPCODE, OP2)
#else
/* Use "OPCODE. OP2" and jump to T. */
#define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
#endif
/* MOVE_SF_BYTE0(D)
Move the first single-precision floating-point argument between
GPRs and FPRs.
MOVE_SI_BYTE0(D)
Likewise the first single-precision integer argument.
MOVE_SF_BYTE4(D)
Move the second single-precision floating-point argument between
GPRs and FPRs, given that the first argument occupies 4 bytes.
MOVE_SF_BYTE8(D)
Move the second single-precision floating-point argument between
GPRs and FPRs, given that the first argument occupies 8 bytes.
MOVE_DF_BYTE0(D)
Move the first double-precision floating-point argument between
GPRs and FPRs.
MOVE_DF_BYTE8(D)
Likewise the second double-precision floating-point argument.
MOVE_SF_RET(D, T)
Likewise a single-precision floating-point return value,
then jump to T.
MOVE_SC_RET(D, T)
Likewise a complex single-precision floating-point return value.
MOVE_DF_RET(D, T)
Likewise a double-precision floating-point return value.
MOVE_DC_RET(D, T)
Likewise a complex double-precision floating-point return value.
MOVE_SI_RET(D, T)
Likewise a single-precision integer return value.
The D argument is "t" to move to FPRs and "f" to move from FPRs.
The return macros may assume that the target of the jump does not
use a floating-point register. */
#define MOVE_SF_RET(D, T) DELAY##D (T, m##D##c1 $2,$f0)
#define MOVE_SI_RET(D, T) DELAY##D (T, m##D##c1 $2,$f0)
#if defined(__mips64) && defined(__MIPSEB__)
#define MOVE_SC_RET(D, T) MERGE_GPR##D ($2, $f0, $f1); jr T
#elif defined(__mips64)
/* The high 32 bits of $2 correspond to the second word in memory;
i.e. the imaginary part. */
#define MOVE_SC_RET(D, T) MERGE_GPR##D ($2, $f1, $f0); jr T
#else
#define MOVE_SC_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##c1 $3,$f2)
#endif
#if defined(__mips64)
#define MOVE_SF_BYTE0(D) m##D##c1 $4,$f12
#define MOVE_SF_BYTE4(D) m##D##c1 $5,$f13
#define MOVE_SF_BYTE8(D) m##D##c1 $5,$f13
#else
#define MOVE_SF_BYTE0(D) m##D##c1 $4,$f12
#define MOVE_SF_BYTE4(D) m##D##c1 $5,$f14
#define MOVE_SF_BYTE8(D) m##D##c1 $6,$f14
#endif
#define MOVE_SI_BYTE0(D) MOVE_SF_BYTE0(D)
#if defined(__mips64)
#define MOVE_DF_BYTE0(D) dm##D##c1 $4,$f12
#define MOVE_DF_BYTE8(D) dm##D##c1 $5,$f13
#define MOVE_DF_RET(D, T) DELAY##D (T, dm##D##c1 $2,$f0)
#define MOVE_DC_RET(D, T) dm##D##c1 $3,$f1; MOVE_DF_RET (D, T)
#elif __mips_fpr != 32 && __mips_isa_rev >= 2 && defined(__MIPSEB__)
#define MOVE_DF_BYTE0(D) m##D##c1 $5,$f12; m##D##hc1 $4,$f12
#define MOVE_DF_BYTE8(D) m##D##c1 $7,$f14; m##D##hc1 $6,$f14
#define MOVE_DF_RET(D, T) m##D##c1 $3,$f0; DELAY##D (T, m##D##hc1 $2,$f0)
#define MOVE_DC_RET(D, T) m##D##c1 $5,$f2; m##D##hc1 $4,$f2; MOVE_DF_RET (D, T)
#elif __mips_fpr != 32 && __mips_isa_rev >= 2
#define MOVE_DF_BYTE0(D) m##D##c1 $4,$f12; m##D##hc1 $5,$f12
#define MOVE_DF_BYTE8(D) m##D##c1 $6,$f14; m##D##hc1 $7,$f14
#define MOVE_DF_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##hc1 $3,$f0)
#define MOVE_DC_RET(D, T) m##D##c1 $4,$f2; m##D##hc1 $5,$f2; MOVE_DF_RET (D, T)
#elif __mips_fpr == 0
#define MOVE_DF_BYTE0t sw $4, 0($29); sw $5, 4($29); ldc1 $f12, 0($29)
#define MOVE_DF_BYTE0f sdc1 $f12, 0($29); lw $4, 0($29); lw $5, 4($29)
#define MOVE_DF_BYTE0(D) MOVE_DF_BYTE0##D
#define MOVE_DF_BYTE8t sw $6, 8($29); sw $7, 12($29); ldc1 $f14, 8($29)
#define MOVE_DF_BYTE8f sdc1 $f14, 8($29); lw $6, 8($29); lw $7, 12($29)
#define MOVE_DF_BYTE8(D) MOVE_DF_BYTE8##D
#define MOVE_DF_RETt(T) sw $2, 0($29); sw $3, 4($29); DELAYt (T, ldc1 $f0, 0($29))
#define MOVE_DF_RETf(T) sdc1 $f0, 0($29); lw $2, 0($29); DELAYf (T, lw $3, 4($29))
#define MOVE_DF_RET(D, T) MOVE_DF_RET##D(T)
#define MOVE_DC_RETt(T) sw $4, 8($29); sw $5, 12($29); ldc1 $f2, 8($29); MOVE_DF_RETt(T)
#define MOVE_DC_RETf(T) sdc1 $f2, 8($29); lw $4, 8($29); lw $5, 12($29); MOVE_DF_RETf(T)
#define MOVE_DC_RET(D, T) MOVE_DF_RET##D(T)
#elif defined(__MIPSEB__)
/* FPRs are little-endian. */
#define MOVE_DF_BYTE0(D) m##D##c1 $4,$f13; m##D##c1 $5,$f12
#define MOVE_DF_BYTE8(D) m##D##c1 $6,$f15; m##D##c1 $7,$f14
#define MOVE_DF_RET(D, T) m##D##c1 $2,$f1; DELAY##D (T, m##D##c1 $3,$f0)
#define MOVE_DC_RET(D, T) m##D##c1 $4,$f3; m##D##c1 $5,$f2; MOVE_DF_RET (D, T)
#else
#define MOVE_DF_BYTE0(D) m##D##c1 $4,$f12; m##D##c1 $5,$f13
#define MOVE_DF_BYTE8(D) m##D##c1 $6,$f14; m##D##c1 $7,$f15
#define MOVE_DF_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##c1 $3,$f1)
#define MOVE_DC_RET(D, T) m##D##c1 $4,$f2; m##D##c1 $5,$f3; MOVE_DF_RET (D, T)
#endif
/* Single-precision math. */
/* Define a function NAME that loads two single-precision values,
performs FPU operation OPCODE on them, and returns the single-
precision result. */
#define OPSF3(NAME, OPCODE) \
STARTFN (NAME); \
MOVE_SF_BYTE0 (t); \
MOVE_SF_BYTE4 (t); \
OPCODE RET,ARG1,ARG2; \
MOVE_SF_RET (f, $31); \
ENDFN (NAME)
#ifdef L_m16addsf3
OPSF3 (__mips16_addsf3, add.s)
#endif
#ifdef L_m16subsf3
OPSF3 (__mips16_subsf3, sub.s)
#endif
#ifdef L_m16mulsf3
OPSF3 (__mips16_mulsf3, mul.s)
#endif
#ifdef L_m16divsf3
OPSF3 (__mips16_divsf3, div.s)
#endif
/* Define a function NAME that loads a single-precision value,
performs FPU operation OPCODE on it, and returns the single-
precision result. */
#define OPSF2(NAME, OPCODE) \
STARTFN (NAME); \
MOVE_SF_BYTE0 (t); \
OPCODE RET,ARG1; \
MOVE_SF_RET (f, $31); \
ENDFN (NAME)
#ifdef L_m16negsf2
OPSF2 (__mips16_negsf2, neg.s)
#endif
#ifdef L_m16abssf2
OPSF2 (__mips16_abssf2, abs.s)
#endif
/* Single-precision comparisons. */
/* Define a function NAME that loads two single-precision values,
performs floating point comparison OPCODE, and returns TRUE or
FALSE depending on the result. */
#define CMPSF(NAME, OPCODE, TRUE, FALSE) \
STARTFN (NAME); \
MOVE_SF_BYTE0 (t); \
MOVE_SF_BYTE4 (t); \
OPCODE ARG1,ARG2; \
li $2,TRUE; \
bc1t 1f; \
li $2,FALSE; \
1:; \
j $31; \
ENDFN (NAME)
/* Like CMPSF, but reverse the comparison operands. */
#define REVCMPSF(NAME, OPCODE, TRUE, FALSE) \
STARTFN (NAME); \
MOVE_SF_BYTE0 (t); \
MOVE_SF_BYTE4 (t); \
OPCODE ARG2,ARG1; \
li $2,TRUE; \
bc1t 1f; \
li $2,FALSE; \
1:; \
j $31; \
ENDFN (NAME)
#ifdef L_m16eqsf2
CMPSF (__mips16_eqsf2, c.eq.s, 0, 1)
#endif
#ifdef L_m16nesf2
CMPSF (__mips16_nesf2, c.eq.s, 0, 1)
#endif
#ifdef L_m16gtsf2
REVCMPSF (__mips16_gtsf2, c.lt.s, 1, 0)
#endif
#ifdef L_m16gesf2
REVCMPSF (__mips16_gesf2, c.le.s, 0, -1)
#endif
#ifdef L_m16lesf2
CMPSF (__mips16_lesf2, c.le.s, 0, 1)
#endif
#ifdef L_m16ltsf2
CMPSF (__mips16_ltsf2, c.lt.s, -1, 0)
#endif
#ifdef L_m16unordsf2
CMPSF(__mips16_unordsf2, c.un.s, 1, 0)
#endif
/* Single-precision conversions. */
#ifdef L_m16fltsisf
STARTFN (__mips16_floatsisf)
MOVE_SF_BYTE0 (t)
cvt.s.w RET,ARG1
MOVE_SF_RET (f, $31)
ENDFN (__mips16_floatsisf)
#endif
#ifdef L_m16fltunsisf
STARTFN (__mips16_floatunsisf)
.set noreorder
bltz $4,1f
MOVE_SF_BYTE0 (t)
.set reorder
cvt.s.w RET,ARG1
MOVE_SF_RET (f, $31)
1:
and $2,$4,1
srl $3,$4,1
or $2,$2,$3
mtc1 $2,RET
cvt.s.w RET,RET
add.s RET,RET,RET
MOVE_SF_RET (f, $31)
ENDFN (__mips16_floatunsisf)
#endif
#ifdef L_m16fix_truncsfsi
STARTFN (__mips16_fix_truncsfsi)
MOVE_SF_BYTE0 (t)
trunc.w.s RET,ARG1,$4
MOVE_SI_RET (f, $31)
ENDFN (__mips16_fix_truncsfsi)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
/* Double-precision math. */
/* Define a function NAME that loads two double-precision values,
performs FPU operation OPCODE on them, and returns the double-
precision result. */
#define OPDF3(NAME, OPCODE) \
STARTFN (NAME); \
MOVE_DF_BYTE0 (t); \
MOVE_DF_BYTE8 (t); \
OPCODE RET,ARG1,ARG2; \
MOVE_DF_RET (f, $31); \
ENDFN (NAME)
#ifdef L_m16adddf3
OPDF3 (__mips16_adddf3, add.d)
#endif
#ifdef L_m16subdf3
OPDF3 (__mips16_subdf3, sub.d)
#endif
#ifdef L_m16muldf3
OPDF3 (__mips16_muldf3, mul.d)
#endif
#ifdef L_m16divdf3
OPDF3 (__mips16_divdf3, div.d)
#endif
/* Define a function NAME that loads a double-precision value,
performs FPU operation OPCODE on it, and returns the double-
precision result. */
#define OPDF2(NAME, OPCODE) \
STARTFN (NAME); \
MOVE_DF_BYTE0 (t); \
OPCODE RET,ARG1; \
MOVE_DF_RET (f, $31); \
ENDFN (NAME)
#ifdef L_m16negdf2
OPDF2 (__mips16_negdf2, neg.d)
#endif
#ifdef L_m16absdf2
OPDF2 (__mips16_absdf2, abs.d)
#endif
/* Conversions between single and double precision. */
#ifdef L_m16extsfdf2
STARTFN (__mips16_extendsfdf2)
MOVE_SF_BYTE0 (t)
cvt.d.s RET,ARG1
MOVE_DF_RET (f, $31)
ENDFN (__mips16_extendsfdf2)
#endif
#ifdef L_m16trdfsf2
STARTFN (__mips16_truncdfsf2)
MOVE_DF_BYTE0 (t)
cvt.s.d RET,ARG1
MOVE_SF_RET (f, $31)
ENDFN (__mips16_truncdfsf2)
#endif
/* Double-precision comparisons. */
/* Define a function NAME that loads two double-precision values,
performs floating point comparison OPCODE, and returns TRUE or
FALSE depending on the result. */
#define CMPDF(NAME, OPCODE, TRUE, FALSE) \
STARTFN (NAME); \
MOVE_DF_BYTE0 (t); \
MOVE_DF_BYTE8 (t); \
OPCODE ARG1,ARG2; \
li $2,TRUE; \
bc1t 1f; \
li $2,FALSE; \
1:; \
j $31; \
ENDFN (NAME)
/* Like CMPDF, but reverse the comparison operands. */
#define REVCMPDF(NAME, OPCODE, TRUE, FALSE) \
STARTFN (NAME); \
MOVE_DF_BYTE0 (t); \
MOVE_DF_BYTE8 (t); \
OPCODE ARG2,ARG1; \
li $2,TRUE; \
bc1t 1f; \
li $2,FALSE; \
1:; \
j $31; \
ENDFN (NAME)
#ifdef L_m16eqdf2
CMPDF (__mips16_eqdf2, c.eq.d, 0, 1)
#endif
#ifdef L_m16nedf2
CMPDF (__mips16_nedf2, c.eq.d, 0, 1)
#endif
#ifdef L_m16gtdf2
REVCMPDF (__mips16_gtdf2, c.lt.d, 1, 0)
#endif
#ifdef L_m16gedf2
REVCMPDF (__mips16_gedf2, c.le.d, 0, -1)
#endif
#ifdef L_m16ledf2
CMPDF (__mips16_ledf2, c.le.d, 0, 1)
#endif
#ifdef L_m16ltdf2
CMPDF (__mips16_ltdf2, c.lt.d, -1, 0)
#endif
#ifdef L_m16unorddf2
CMPDF(__mips16_unorddf2, c.un.d, 1, 0)
#endif
/* Double-precision conversions. */
#ifdef L_m16fltsidf
STARTFN (__mips16_floatsidf)
MOVE_SI_BYTE0 (t)
cvt.d.w RET,ARG1
MOVE_DF_RET (f, $31)
ENDFN (__mips16_floatsidf)
#endif
#ifdef L_m16fltunsidf
STARTFN (__mips16_floatunsidf)
MOVE_SI_BYTE0 (t)
cvt.d.w RET,ARG1
bgez $4,1f
li.d ARG1, 4.294967296e+9
add.d RET, RET, ARG1
1: MOVE_DF_RET (f, $31)
ENDFN (__mips16_floatunsidf)
#endif
#ifdef L_m16fix_truncdfsi
STARTFN (__mips16_fix_truncdfsi)
MOVE_DF_BYTE0 (t)
trunc.w.d RET,ARG1,$4
MOVE_SI_RET (f, $31)
ENDFN (__mips16_fix_truncdfsi)
#endif
#endif /* !__mips_single_float */
/* We don't export stubs from libgcc_s.so and always require static
versions to be pulled from libgcc.a as needed because they use $2
and possibly $3 as arguments, diverging from the standard SysV ABI,
and as such would require severe pessimisation of MIPS16 PLT entries
just for this single special case.
For compatibility with old binaries that used safe standard MIPS PLT
entries and referred to these functions we still export them at
version GCC_4.4.0 for run-time loading only. */
#ifdef SHARED
#define CE_STARTFN(NAME) \
STARTFN (NAME##_compat); \
.symver NAME##_compat, NAME@GCC_4.4.0
#define CE_ENDFN(NAME) ENDFN (NAME##_compat)
#else
#define CE_STARTFN(NAME) \
STARTFN (NAME); \
.hidden NAME
#define CE_ENDFN(NAME) ENDFN (NAME)
#endif
/* Define a function NAME that moves a return value of mode MODE from
FPRs to GPRs. */
#define RET_FUNCTION(NAME, MODE) \
CE_STARTFN (NAME); \
MOVE_##MODE##_RET (t, $31); \
CE_ENDFN (NAME)
#ifdef L_m16retsf
RET_FUNCTION (__mips16_ret_sf, SF)
#endif
#ifdef L_m16retsc
RET_FUNCTION (__mips16_ret_sc, SC)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16retdf
RET_FUNCTION (__mips16_ret_df, DF)
#endif
#ifdef L_m16retdc
RET_FUNCTION (__mips16_ret_dc, DC)
#endif
#endif /* !__mips_single_float */
/* STUB_ARGS_X copies the arguments from GPRs to FPRs for argument
code X. X is calculated as ARG1 + ARG2 * 4, where ARG1 and ARG2
classify the first and second arguments as follows:
1: a single-precision argument
2: a double-precision argument
0: no argument, or not one of the above. */
#define STUB_ARGS_0 /* () */
#define STUB_ARGS_1 MOVE_SF_BYTE0 (t) /* (sf) */
#define STUB_ARGS_5 MOVE_SF_BYTE0 (t); MOVE_SF_BYTE4 (t) /* (sf, sf) */
#define STUB_ARGS_9 MOVE_SF_BYTE0 (t); MOVE_DF_BYTE8 (t) /* (sf, df) */
#define STUB_ARGS_2 MOVE_DF_BYTE0 (t) /* (df) */
#define STUB_ARGS_6 MOVE_DF_BYTE0 (t); MOVE_SF_BYTE8 (t) /* (df, sf) */
#define STUB_ARGS_10 MOVE_DF_BYTE0 (t); MOVE_DF_BYTE8 (t) /* (df, df) */
/* These functions are used by 16-bit code when calling via a function
pointer. They must copy the floating point arguments from the GPRs
to FPRs and then call function $2. */
#define CALL_STUB_NO_RET(NAME, CODE) \
CE_STARTFN (NAME); \
STUB_ARGS_##CODE; \
.set noreorder; \
jr $2; \
move $25,$2; \
.set reorder; \
CE_ENDFN (NAME)
#ifdef L_m16stub1
CALL_STUB_NO_RET (__mips16_call_stub_1, 1)
#endif
#ifdef L_m16stub5
CALL_STUB_NO_RET (__mips16_call_stub_5, 5)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stub2
CALL_STUB_NO_RET (__mips16_call_stub_2, 2)
#endif
#ifdef L_m16stub6
CALL_STUB_NO_RET (__mips16_call_stub_6, 6)
#endif
#ifdef L_m16stub9
CALL_STUB_NO_RET (__mips16_call_stub_9, 9)
#endif
#ifdef L_m16stub10
CALL_STUB_NO_RET (__mips16_call_stub_10, 10)
#endif
#endif /* !__mips_single_float */
/* Now we have the same set of functions, except that this time the
function being called returns an SFmode, SCmode, DFmode or DCmode
value; we need to instantiate a set for each case. The calling
function will arrange to preserve $18, so these functions are free
to use it to hold the return address.
Note that we do not know whether the function we are calling is 16
bit or 32 bit. However, it does not matter, because 16-bit
functions always return floating point values in both the gp and
the fp regs. It would be possible to check whether the function
being called is 16 bits, in which case the copy is unnecessary;
however, it's faster to always do the copy. */
#define CALL_STUB_RET(NAME, CODE, MODE) \
CE_STARTFN (NAME); \
.cfi_startproc; \
/* Create a fake CFA 4 bytes below the stack pointer. */ \
.cfi_def_cfa 29,-4; \
/* "Save" $sp in itself so we don't use the fake CFA. \
This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */ \
.cfi_escape 0x16,29,1,0x6d; \
move $18,$31; \
.cfi_register 31,18; \
STUB_ARGS_##CODE; \
.set noreorder; \
jalr $2; \
move $25,$2; \
.set reorder; \
MOVE_##MODE##_RET (f, $18); \
.cfi_endproc; \
CE_ENDFN (NAME)
/* First, instantiate the single-float set. */
#ifdef L_m16stubsf0
CALL_STUB_RET (__mips16_call_stub_sf_0, 0, SF)
#endif
#ifdef L_m16stubsf1
CALL_STUB_RET (__mips16_call_stub_sf_1, 1, SF)
#endif
#ifdef L_m16stubsf5
CALL_STUB_RET (__mips16_call_stub_sf_5, 5, SF)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stubsf2
CALL_STUB_RET (__mips16_call_stub_sf_2, 2, SF)
#endif
#ifdef L_m16stubsf6
CALL_STUB_RET (__mips16_call_stub_sf_6, 6, SF)
#endif
#ifdef L_m16stubsf9
CALL_STUB_RET (__mips16_call_stub_sf_9, 9, SF)
#endif
#ifdef L_m16stubsf10
CALL_STUB_RET (__mips16_call_stub_sf_10, 10, SF)
#endif
#endif /* !__mips_single_float */
/* Now we have the same set of functions again, except that this time
the function being called returns an DFmode value. */
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stubdf0
CALL_STUB_RET (__mips16_call_stub_df_0, 0, DF)
#endif
#ifdef L_m16stubdf1
CALL_STUB_RET (__mips16_call_stub_df_1, 1, DF)
#endif
#ifdef L_m16stubdf5
CALL_STUB_RET (__mips16_call_stub_df_5, 5, DF)
#endif
#ifdef L_m16stubdf2
CALL_STUB_RET (__mips16_call_stub_df_2, 2, DF)
#endif
#ifdef L_m16stubdf6
CALL_STUB_RET (__mips16_call_stub_df_6, 6, DF)
#endif
#ifdef L_m16stubdf9
CALL_STUB_RET (__mips16_call_stub_df_9, 9, DF)
#endif
#ifdef L_m16stubdf10
CALL_STUB_RET (__mips16_call_stub_df_10, 10, DF)
#endif
#endif /* !__mips_single_float */
/* Ho hum. Here we have the same set of functions again, this time
for when the function being called returns an SCmode value. */
#ifdef L_m16stubsc0
CALL_STUB_RET (__mips16_call_stub_sc_0, 0, SC)
#endif
#ifdef L_m16stubsc1
CALL_STUB_RET (__mips16_call_stub_sc_1, 1, SC)
#endif
#ifdef L_m16stubsc5
CALL_STUB_RET (__mips16_call_stub_sc_5, 5, SC)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stubsc2
CALL_STUB_RET (__mips16_call_stub_sc_2, 2, SC)
#endif
#ifdef L_m16stubsc6
CALL_STUB_RET (__mips16_call_stub_sc_6, 6, SC)
#endif
#ifdef L_m16stubsc9
CALL_STUB_RET (__mips16_call_stub_sc_9, 9, SC)
#endif
#ifdef L_m16stubsc10
CALL_STUB_RET (__mips16_call_stub_sc_10, 10, SC)
#endif
#endif /* !__mips_single_float */
/* Finally, another set of functions for DCmode. */
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stubdc0
CALL_STUB_RET (__mips16_call_stub_dc_0, 0, DC)
#endif
#ifdef L_m16stubdc1
CALL_STUB_RET (__mips16_call_stub_dc_1, 1, DC)
#endif
#ifdef L_m16stubdc5
CALL_STUB_RET (__mips16_call_stub_dc_5, 5, DC)
#endif
#ifdef L_m16stubdc2
CALL_STUB_RET (__mips16_call_stub_dc_2, 2, DC)
#endif
#ifdef L_m16stubdc6
CALL_STUB_RET (__mips16_call_stub_dc_6, 6, DC)
#endif
#ifdef L_m16stubdc9
CALL_STUB_RET (__mips16_call_stub_dc_9, 9, DC)
#endif
#ifdef L_m16stubdc10
CALL_STUB_RET (__mips16_call_stub_dc_10, 10, DC)
#endif
#endif /* !__mips_single_float */
#endif
#endif /* defined(__mips_micromips) || defined(__mips_soft_float) */
|
4ms/metamodule-plugin-sdk
| 2,381
|
plugin-libc/libgcc/config/mips/vr4120-div.S
|
/* Support file for -mfix-vr4120.
Copyright (C) 2002-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#include "gnustack.h"
/* This file contains functions which implement divsi3 and modsi3 for
-mfix-vr4120. div and ddiv do not give the correct result when one
of the operands is negative. */
.set nomips16
#define DIV \
xor $3,$4,$5 /* t = x ^ y */ ; \
li $2,0x80000000; \
.set noreorder; \
bgez $4,1f /* x >= 0 */; \
and $3,$3,$2 /* t = (x ^ y) & 0x80000000 in delay slot */ ;\
.set reorder; \
subu $4,$0,$4 /* x = -x */ ; \
1:; \
.set noreorder; \
bgez $5,2f /* y >= 0 */ ; \
nop; \
subu $5,$0,$5 /* y = -y */ ; \
.set reorder; \
2:; \
divu $0,$4,$5; /* we use divu because of INT_MIN */ \
.set noreorder; \
bne $5,$0,3f; \
nop; \
break 7 /* division on zero y */ ; \
3:; \
.set reorder; \
mflo $2 /* r = x / y */ ; \
.set noreorder; \
beq $3,$0,4f /* t == 0 */ ; \
nop; \
subu $2,$0,$2 /* r = -r */ ; \
.set reorder; \
4:
.globl __vr4120_divsi3
.ent __vr4120_divsi3
__vr4120_divsi3:
DIV
j $31
.end __vr4120_divsi3
.globl __vr4120_modsi3
.ent __vr4120_modsi3
__vr4120_modsi3:
move $6,$4 # x1 = x
move $7,$5 # y1 = y
DIV
mult $2,$7 # r = r * y1
mflo $2
.set noreorder
j $31
subu $2,$6,$2 # r = x1 - r in delay slot
.end __vr4120_modsi3
|
4ms/metamodule-plugin-sdk
| 1,544
|
plugin-libc/libgcc/config/mips/crti.S
|
/* Copyright (C) 2001-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#include "gnustack.h"
/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */
.section .init,"ax",@progbits
.globl _init
.type _init,@function
_init:
#ifdef __mips64
daddu $sp,$sp,-48
sd $31,40($sp)
#else
addu $sp,$sp,-32
sw $31,20($sp)
#endif
.section .fini,"ax",@progbits
.globl _fini
.type _fini,@function
_fini:
#ifdef __mips64
daddu $sp,$sp,-48
sd $31,40($sp)
#else
addu $sp,$sp,-32
sw $31,20($sp)
#endif
|
4ms/metamodule-plugin-sdk
| 5,358
|
plugin-libc/libgcc/config/or1k/lib1funcs.S
|
/* Copyright (C) 2018-2022 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifdef L__mulsi3
.balign 4
.globl __mulsi3
.type __mulsi3, @function
__mulsi3:
l.movhi r11, 0 /* initial r */
/* Given R = X * Y ... */
1: l.sfeq r4, r0 /* while (y != 0) */
l.bf 2f
l.andi r5, r4, 1 /* if (y & 1) ... */
l.add r12, r11, r3
l.sfne r5, r0
#if defined(__or1k_cmov__)
l.cmov r11, r12, r11 /* ... r += x. */
l.srli r4, r4, 1 /* y >>= 1 */
#else
l.bnf 3f
l.srli r4, r4, 1 /* y >>= 1 */
l.ori r11, r12, 0
3:
#endif
l.j 1b
l.add r3, r3, r3 /* x <<= 1 */
2: l.jr r9
l.nop
.size __mulsi3, . - __mulsi3
#endif
#if defined(L__udivsi3) || defined(L__umodsi3) \
|| defined(L__divsi3) || defined(L__modsi3)
.global __udivmodsi3_internal
.hidden __udivmodsi3_internal
.type __udivmodsi3_internal, @function
#endif
#ifdef L__udivsi3
.balign 4
.global __udivsi3
.type __udivsi3, @function
__udivsi3:
__udivmodsi3_internal:
/* Note that the other division routines assume that r13
is not clobbered by this routine, and use that as to
save a return address without creating a stack frame. */
l.sfeq r4, r0 /* division by zero; return 0. */
l.ori r11, r0, 0 /* initial quotient */
l.bf 9f
l.ori r12, r3, 0 /* initial remainder */
/* Given X/Y, shift Y left until Y >= X. */
l.ori r6, r0, 1 /* mask = 1 */
1: l.sflts r4, r0 /* y has msb set */
l.bf 2f
l.sfltu r4, r12 /* y < x */
l.add r4, r4, r4 /* y <<= 1 */
l.bf 1b
l.add r6, r6, r6 /* mask <<= 1 */
/* Shift Y back to the right again, subtracting from X. */
2: l.add r7, r11, r6 /* tmp1 = quot + mask */
3: l.srli r6, r6, 1 /* mask >>= 1 */
l.sub r8, r12, r4 /* tmp2 = x - y */
l.sfleu r4, r12 /* y <= x */
l.srli r4, r4, 1 /* y >>= 1 */
#if defined(__or1k_cmov__)
l.cmov r11, r7, r11 /* if (y <= x) quot = tmp1 */
l.cmov r12, r8, r12 /* if (y <= x) x = tmp2 */
#else
l.bnf 4f
l.nop
l.ori r11, r7, 0
l.ori r12, r8, 0
4:
#endif
l.sfne r6, r0 /* loop until mask == 0 */
l.bf 3b
l.add r7, r11, r6 /* delay fill from loop start */
9: l.jr r9
l.nop
.size __udivsi3, . - __udivsi3
.size __udivmodsi3_internal, . - __udivmodsi3_internal
#endif
#ifdef L__umodsi3
.balign 4
.global __umodsi3
.type __umodsi3, @function
.cfi_startproc
__umodsi3:
/* Know that __udivmodsi3_internal does not clobber r13. */
l.ori r13, r9, 0
.cfi_register 9, 13
l.jal __udivmodsi3_internal
l.nop
l.jr r13 /* return to saved lr */
l.ori r11, r12, 0 /* move remainder to rv */
.cfi_endproc
.size __umodsi3, . - __umodsi3
#endif
/* For signed division we do:
-x / y = x / -y = -(x / y)
-x % y = -(x % y)
x % -y = x % y
which has the property that (x/y)*y + (x%y) = x. */
#ifdef L__divsi3
.balign 4
.global __divsi3
.type __divsi3, @function
.cfi_startproc
__divsi3:
l.xor r6, r3, r4 /* need result negate? */
l.sflts r3, r0 /* abs(x) */
#if defined(__or1k_cmov__)
l.sub r5, r0, r3
l.cmov r3, r5, r3
#else
l.bnf 1f
l.sub r5, r0, r3
l.ori r3, r5, 0
1:
#endif
l.sflts r4, r0 /* abs(y) */
#if defined(__or1k_cmov__)
l.sub r5, r0, r4
l.cmov r4, r5, r4
#else
l.bnf 2f
l.sub r5, r0, r4
l.ori r4, r5, 0
2:
#endif
/* If the result will not require sign flip, tail call. */
l.sflts r6, r0
l.bnf __udivmodsi3_internal
l.ori r13, r9, 0 /* save lr */
/* Otherwise, know that __udivmodsi3_internal does not clobber r13.
Perform a normal call, then negate and return via saved lr. */
.cfi_register 9, 13
l.jal __udivmodsi3_internal
l.nop
l.jr r13
l.sub r11, r0, r11
.cfi_endproc
.size __divsi3, . - __divsi3
#endif
#ifdef L__modsi3
.balign 4
.global __modsi3
.type __modsi3, @function
.cfi_startproc
__modsi3:
l.sflts r4, r0 /* abs(y) */
#if defined(__or1k_cmov__)
l.sub r5, r0, r4
l.cmov r4, r5, r4
#else
l.bnf 2f
l.sub r5, r0, r4
l.ori r4, r5, 0
2:
#endif
l.sflts r3, r0 /* x negative? */
l.bf 1f
l.ori r13, r9, 0 /* save lr */
/* Know that __udivmodsi3_internal does not clobber r13. */
.cfi_register 9, 13
/* X positive; no negate of the result required. */
l.jal __udivmodsi3_internal
l.nop
l.jr r13 /* return to saved lr */
l.ori r11, r12, 0 /* move remainder to rv */
/* X negative; negate both X and the result. */
1: l.jal __udivmodsi3_internal
l.sub r3, r0, r3
l.jr r13 /* return to saved lr */
l.sub r11, r0, r12 /* negate remainder to rv */
.cfi_endproc
.size __modsi3, .- __modsi3
#endif
|
4ms/metamodule-plugin-sdk
| 1,564
|
plugin-libc/libgcc/config/score/crtn.S
|
# crtn.S for Sunplus S+CORE
# Copyright (C) 2005-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file makes sure that the .init and .fini sections do in
# fact return.
#ifndef __pic__
.section .init, "ax", @progbits
lw r3, [r0, 20]
addi r0, 32
br r3
.section .fini, "ax", @progbits
lw r3, [r0, 20]
addi r0, 32
br r3
#else
.set pic
.section .init, "ax", @progbits
lw r3, [r0, 20]
addi r0, 32
br r3
.set pic
.section .fini, "ax", @progbits
lw r3, [r0, 20]
addi r0, 32
br r3
#endif
|
4ms/metamodule-plugin-sdk
| 3,342
|
plugin-libc/libgcc/config/score/crti.S
|
# crti.S for Sunplus S+CORE
#
# Copyright (C) 2005-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file makes a stack frame for the contents of the .init and
# .fini sections.
.extern _stack
#ifndef __pic__
.section .init, "ax", @progbits
.weak _start
.ent _start
.frame r0, 0, r3, 0
.mask 0x00000000, 0
_start:
la r28, _gp
la r8, __bss_start
la r9, __bss_end__
sub! r9, r8
srli! r9, 2
addi r9, -1
mtsr r9, sr0
li r9, 0
1:
sw r9, [r8]+, 4
bcnz 1b
la r0, _stack
jl _init
la r4, _end
jl _init_argv
jl exit
.end _start
.weak _init_argv
.ent
.frame r0, 0, r3, 0
.mask 0x00000000, 0
_init_argv:
ldiu! r4, 0
ldiu! r5, 0
j main
.end _init_argv
.globl _init
.type _init, %function
_init:
addi r0, -32
sw r3, [r0, 20]
.section .fini, "ax", @progbits
.globl _fini
.type _fini, %function
_fini:
addi r0, -32
sw r3, [r0, 20]
#else
.section .init, "ax", @progbits
.set pic
.weak _start
.ent _start
.frame r0, 0, r3, 0
.mask 0x00000000, 0
_start:
mv r29, r3
bl 0f
0:
.cpload r3
mv r3, r29
la r8, __bss_start
la r9, __bss_end__
sub! r9, r8
srli! r9, 2
addi r9, -1
mtsr r9, sr0
li r9, 0
1:
sw r9, [r8]+, 4
bcnz 1b
la r0, _stack
bl _init
la r4, _end
la r29, _init_argv
brl r29
la r29, exit
brl r29
.end _start
.weak _init_argv
.ent _init_argv
.frame r0, 0, r3, 0
.mask 0x00000000, 0
_init_argv:
ldiu! r4, 0
ldiu! r5, 0
la r29, main
brl r29
.end _init_argv
.globl _init
.type _init, %function
_init:
addi r0, -32
sw r3, [r0, 20]
.section .fini, "ax", @progbits
.globl _fini
.type _fini, %function
_fini:
addi r0, -32
sw r3, [r0, 20]
#endif
|
4ms/metamodule-plugin-sdk
| 1,778
|
plugin-libc/libgcc/config/epiphany/ieee-754/gtesf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
/* Assumptions: NaNs have all bits 10..30 and one of bit 0..9 set.
after sub: AC = ~Borrow.
clobber: TMP0
output: gt / gte indicates greater / greater or equal. */
FSTAB (__gtesf2,T_INT)
.global SYM(__gtesf2)
.balign 4
HIDDEN_FUNC(__gtesf2)
SYM(__gtesf2):
#ifndef FLOAT_FORMAT_MOTOROLA
mov TMP0,0xffff
movt TMP0,0x7f
add TMP0,TMP0,r0
eor TMP0,TMP0,r0
blt .Lret
mov TMP0,0xffff
movt TMP0,0x7f
add TMP0,TMP0,r1
#else
add TMP0,r0,0x3ff; check for r0 NaN
eor TMP0,TMP0,r0
blt .Lret
add TMP0,r1,0x3ff; check for r1 NaN
#endif
eor TMP0,TMP0,r1
blt .Lret
and TMP0,r0,r1
blt .Lneg
orr TMP0,r0,r1
lsl TMP0,TMP0,1
beq .Lret
sub TMP0,r0,r1
.Lret:
rts
.balign 4
.Lneg:
sub TMP0,r1,r0
rts
ENDFUNC(__gtesf2)
|
4ms/metamodule-plugin-sdk
| 3,976
|
plugin-libc/libgcc/config/epiphany/ieee-754/fast_div.S
|
/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
.section _fast_div_text,"a",@progbits;
.balign 8;
_fast_div_table:
.word 0x007fffff// mantissa mask
.word 0x40257ebb// hold constant a = 2.58586
.word 0x3f000000// hold constant 126 shifted to bits [30:23]
.word 0xc0ba2e88// hold constant b = -5.81818
.word 0x4087c1e8// hold constant c = 4.24242
.word 0x40000000// to hold constant 2 for Newton-Raphson iterations
.global SYM(__fast_recipsf2)
FUNC(__fast_recipsf2)
SYM(__fast_recipsf2):
//###################
//# input operands:
//###################
// Divisor
//R0
// Function address (used with negative offsets to read _fast_div_table)
//R1
/* Scratch registers: two single (TMP0/TMP5) and two pairs. */
#define P0L TMP1
#define P0H TMP2
#define P1L TMP3
#define P1H TMP4
//#########################################
//# Constants to be used in the algorithm
//#########################################
ldrd P0L , [ R1 , -3 ]
ldrd P1L , [ R1 , -2 ]
//#############################################################################
//# The Algorithm
//#
//# Operation: C=A/B
//# stage 1 - find the reciprocal 1/B according to the following scheme:
//# B = (2^E)*m (1<m<2, E=e-127)
//# 1/B = 1/((2^E)*m) = 1/((2^(E+1))*m1) (0.5<m1<1)
//# = (2^-(E+1))*(1/m1) = (2^E1)*(1/m1)
//#
//# Now we can find the new exponent:
//# e1 = E1+127 = -E-1+127 = -e+127-1+127 = 253-e **
//# 1/m1 alreadt has the exponent 127, so we have to add 126-e.
//# the exponent might underflow, which we can detect as a sign change.
//# Since the architeture uses flush-to-zero for subnormals, we can
//# give the result 0. then.
//#
//# The 1/m1 term with 0.5<m1<1 is approximated with the Chebyshev polynomial
//# 1/m1 = 2.58586*(m1^2) - 5.81818*m1 + 4.24242
//#
//# Next step is to use two iterations of Newton-Raphson algorithm to complete
//# the reciprocal calculation.
//#
//# Final result is achieved by multiplying A with 1/B
//#############################################################################
// R0 exponent and sign "replacement" into TMP0
AND TMP0,R0,P0L ;
ORR TMP0,TMP0,P1L
SUB TMP5,R0,TMP0 // R0 sign/exponent extraction into TMP5
// Calculate new mantissa
FMADD P1H,TMP0,P0H ;
// Calculate new exponent offset 126 - "old exponent"
SUB P1L,P1L,TMP5
ldrd P0L , [ R1 , -1 ]
FMADD P0L,TMP0,P1H ;
eor P1H,r0,P1L // check for overflow (N-BIT).
blt .Lret_0
// P0L exponent and sign "replacement"
sub P0L,P0L,TMP5
// Newton-Raphson iteration #1
MOV TMP0,P0H ;
FMSUB P0H,R0,P0L ;
FMUL P0L,P0H,P0L ;
// Newton-Raphson iteration #2
FMSUB TMP0,R0,P0L ;
FMUL R0,TMP0,P0L ;
jr lr
.Lret_0:ldrd P0L , [ R1 , -3 ]
lsr TMP0,r0,31 ; extract sign
lsl TMP0,TMP0,31
add P0L,P0L,r0 ; check for NaN input
eor P0L,P0L,r0
movgte r0,TMP0
jr lr
// Quotient calculation is expected by the caller: FMUL quotient,divident,R0
;
ENDFUNC(__fast_recipsf2)
|
4ms/metamodule-plugin-sdk
| 1,434
|
plugin-libc/libgcc/config/epiphany/ieee-754/uneqsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
FSTAB (__uneqsf2,T_INT)
.global SYM(__uneqsf2)
.balign 8,,2
HIDDEN_FUNC(__uneqsf2)
SYM(__uneqsf2):
sub TMP0,r0,r1
beq .Lret
orr TMP0,r0,r1
add TMP0,TMP0,TMP0
beq .Lret
mov TMP0,1
movt TMP0,0xff00
lsl TMP1,r0,1
sub TMP1,TMP0,TMP1
blteu .Lret
lsl TMP1,r1,1
sub TMP1,TMP0,TMP1
.Lret: rts /* uneq: lteu */
ENDFUNC(__uneqsf2)
|
4ms/metamodule-plugin-sdk
| 1,462
|
plugin-libc/libgcc/config/epiphany/ieee-754/eqsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
/* Assumption: NaNs have all bits 10..30 and one of bit 0..9 set. */
FSTAB (__eqsf2,T_INT)
.global SYM(__eqsf2)
.balign 4
HIDDEN_FUNC(__eqsf2)
SYM(__eqsf2):
sub TMP0,r0,r1
beq .Lno_bdiff
orr TMP0,r0,r1
add TMP0,TMP0,TMP0
rts
.Lno_bdiff:
#ifndef FLOAT_FORMAT_MOTOROLA
mov TMP0,0xffff
movt TMP0,0x7f
add TMP0,TMP0,r0
#else
add TMP0,r0,0x3ff
#endif
eor TMP0,TMP0,r0
lsr TMP0,TMP0,31
rts
ENDFUNC(__eqsf2)
|
4ms/metamodule-plugin-sdk
| 1,530
|
plugin-libc/libgcc/config/epiphany/ieee-754/ordsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
FSTAB (__ordsf2,T_INT)
.global SYM(__ordsf2)
.balign 8,,2
HIDDEN_FUNC(__ordsf2)
SYM(__ordsf2):
#ifndef FLOAT_FORMAT_MOTOROLA
mov TMP0,0
movt TMP0,0xff00
lsl TMP1,r0,1
sub TMP1,TMP1,TMP0
bgtu .Lret
lsl TMP1,r1,1
sub TMP1,TMP1,TMP0
.Lret: rts /* ordered: lteu */
#else
/* Assumption: NaNs have all bits 9..30 and one of bit 0..8 set. */
lsl TMP0,r0,1
add TMP0,TMP0,0x3fe
bgteu .Lret
lsl TMP0,r1,1
add TMP0,TMP0,0x3fe
.Lret: rts /* ordered: ltu */
#endif
ENDFUNC(__ordsf2)
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid45_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.45, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_45_4b
.type _nds32_vector_45_4b, @function
_nds32_vector_45_4b:
1:
j 1b
.size _nds32_vector_45_4b, .-_nds32_vector_45_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid40_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.40, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_40_4b
.type _nds32_vector_40_4b, @function
_nds32_vector_40_4b:
1:
j 1b
.size _nds32_vector_40_4b, .-_nds32_vector_40_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid15.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.15, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_15
.type _nds32_vector_15, @function
_nds32_vector_15:
1:
j 1b
.size _nds32_vector_15, .-_nds32_vector_15
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid18.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.18, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_18
.type _nds32_vector_18, @function
_nds32_vector_18:
1:
j 1b
.size _nds32_vector_18, .-_nds32_vector_18
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid32.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.32, "a"
.align 2
.weak _nds32_jmptbl_32
.type _nds32_jmptbl_32, @object
_nds32_jmptbl_32:
.word 0
.size _nds32_jmptbl_32, .-_nds32_jmptbl_32
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid01.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.01, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_01
.type _nds32_vector_01, @function
_nds32_vector_01:
1:
j 1b
.size _nds32_vector_01, .-_nds32_vector_01
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid32.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.32, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_32
.type _nds32_vector_32, @function
_nds32_vector_32:
1:
j 1b
.size _nds32_vector_32, .-_nds32_vector_32
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid00.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.00, "a"
.align 2
.weak _nds32_jmptbl_00
.type _nds32_jmptbl_00, @object
_nds32_jmptbl_00:
.word 0
.size _nds32_jmptbl_00, .-_nds32_jmptbl_00
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid12.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.12, "a"
.align 2
.weak _nds32_jmptbl_12
.type _nds32_jmptbl_12, @object
_nds32_jmptbl_12:
.word 0
.size _nds32_jmptbl_12, .-_nds32_jmptbl_12
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid53.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.53, "a"
.align 2
.weak _nds32_jmptbl_53
.type _nds32_jmptbl_53, @object
_nds32_jmptbl_53:
.word 0
.size _nds32_jmptbl_53, .-_nds32_jmptbl_53
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid12.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.12, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_12
.type _nds32_vector_12, @function
_nds32_vector_12:
1:
j 1b
.size _nds32_vector_12, .-_nds32_vector_12
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid27.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.27, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_27
.type _nds32_vector_27, @function
_nds32_vector_27:
1:
j 1b
.size _nds32_vector_27, .-_nds32_vector_27
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid44.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.44, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_44
.type _nds32_vector_44, @function
_nds32_vector_44:
1:
j 1b
.size _nds32_vector_44, .-_nds32_vector_44
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid56.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.56, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_56
.type _nds32_vector_56, @function
_nds32_vector_56:
1:
j 1b
.size _nds32_vector_56, .-_nds32_vector_56
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid58.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.58, "a"
.align 2
.weak _nds32_jmptbl_58
.type _nds32_jmptbl_58, @object
_nds32_jmptbl_58:
.word 0
.size _nds32_jmptbl_58, .-_nds32_jmptbl_58
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid40.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.40, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_40
.type _nds32_vector_40, @function
_nds32_vector_40:
1:
j 1b
.size _nds32_vector_40, .-_nds32_vector_40
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid40.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.40, "a"
.align 2
.weak _nds32_jmptbl_40
.type _nds32_jmptbl_40, @object
_nds32_jmptbl_40:
.word 0
.size _nds32_jmptbl_40, .-_nds32_jmptbl_40
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid49.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.49, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_49
.type _nds32_vector_49, @function
_nds32_vector_49:
1:
j 1b
.size _nds32_vector_49, .-_nds32_vector_49
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid53_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.53, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_53_4b
.type _nds32_vector_53_4b, @function
_nds32_vector_53_4b:
1:
j 1b
.size _nds32_vector_53_4b, .-_nds32_vector_53_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid29_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.29, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_29_4b
.type _nds32_vector_29_4b, @function
_nds32_vector_29_4b:
1:
j 1b
.size _nds32_vector_29_4b, .-_nds32_vector_29_4b
|
4ms/metamodule-plugin-sdk
| 4,285
|
plugin-libc/libgcc/config/nds32/isr-library/excp_isr_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
#include "save_fpu_regs_01.inc"
#include "save_fpu_regs_02.inc"
#include "save_fpu_regs_03.inc"
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_mac_regs.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/*
First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR: Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT: Nested Type
ns: nested
nn: not nested
nr: nested ready
*/
/*
This is 4-byte vector size version.
The "_4b" postfix was added for 4-byte version symbol.
*/
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_e_sa_ns_4b
.type _nds32_e_sa_ns_4b, @function
_nds32_e_sa_ns_4b:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_e_sa_nr_4b
.type _nds32_e_sa_nr_4b, @function
_nds32_e_sa_nr_4b:
#else /* Not nested handler. */
.globl _nds32_e_sa_nn_4b
.type _nds32_e_sa_nn_4b, @function
_nds32_e_sa_nn_4b:
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.globl _nds32_e_ps_ns_4b
.type _nds32_e_ps_ns_4b, @function
_nds32_e_ps_ns_4b:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_e_ps_nr_4b
.type _nds32_e_ps_nr_4b, @function
_nds32_e_ps_nr_4b:
#else /* Not nested handler. */
.globl _nds32_e_ps_nn_4b
.type _nds32_e_ps_nn_4b, @function
_nds32_e_ps_nn_4b:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/*
This is 4-byte vector size version.
The vector id was restored into $lp in vector by compiler.
*/
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL_4B
#else
SAVE_PARTIAL_4B
#endif
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_00
lw $r2, [$r2 + $r0 << #2]
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
RESTORE_PARTIAL
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_e_sa_ns_4b, .-_nds32_e_sa_ns_4b
#elif defined(NDS32_NESTED_READY)
.size _nds32_e_sa_nr_4b, .-_nds32_e_sa_nr_4b
#else /* Not nested handler. */
.size _nds32_e_sa_nn_4b, .-_nds32_e_sa_nn_4b
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.size _nds32_e_ps_ns_4b, .-_nds32_e_ps_ns_4b
#elif defined(NDS32_NESTED_READY)
.size _nds32_e_ps_nr_4b, .-_nds32_e_ps_nr_4b
#else /* Not nested handler. */
.size _nds32_e_ps_nn_4b, .-_nds32_e_ps_nn_4b
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid62.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.62, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_62
.type _nds32_vector_62, @function
_nds32_vector_62:
1:
j 1b
.size _nds32_vector_62, .-_nds32_vector_62
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid71_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.71, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_71_4b
.type _nds32_vector_71_4b, @function
_nds32_vector_71_4b:
1:
j 1b
.size _nds32_vector_71_4b, .-_nds32_vector_71_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid57.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.57, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_57
.type _nds32_vector_57, @function
_nds32_vector_57:
1:
j 1b
.size _nds32_vector_57, .-_nds32_vector_57
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid72_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.72, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_72_4b
.type _nds32_vector_72_4b, @function
_nds32_vector_72_4b:
1:
j 1b
.size _nds32_vector_72_4b, .-_nds32_vector_72_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid65.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.65, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_65
.type _nds32_vector_65, @function
_nds32_vector_65:
1:
j 1b
.size _nds32_vector_65, .-_nds32_vector_65
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid57.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.57, "a"
.align 2
.weak _nds32_jmptbl_57
.type _nds32_jmptbl_57, @object
_nds32_jmptbl_57:
.word 0
.size _nds32_jmptbl_57, .-_nds32_jmptbl_57
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid14.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.14, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_14
.type _nds32_vector_14, @function
_nds32_vector_14:
1:
j 1b
.size _nds32_vector_14, .-_nds32_vector_14
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid15.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.15, "a"
.align 2
.weak _nds32_jmptbl_15
.type _nds32_jmptbl_15, @object
_nds32_jmptbl_15:
.word 0
.size _nds32_jmptbl_15, .-_nds32_jmptbl_15
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid26.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.26, "a"
.align 2
.weak _nds32_jmptbl_26
.type _nds32_jmptbl_26, @object
_nds32_jmptbl_26:
.word 0
.size _nds32_jmptbl_26, .-_nds32_jmptbl_26
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid55.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.55, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_55
.type _nds32_vector_55, @function
_nds32_vector_55:
1:
j 1b
.size _nds32_vector_55, .-_nds32_vector_55
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid52.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.52, "a"
.align 2
.weak _nds32_jmptbl_52
.type _nds32_jmptbl_52, @object
_nds32_jmptbl_52:
.word 0
.size _nds32_jmptbl_52, .-_nds32_jmptbl_52
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid07.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.07, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_07
.type _nds32_vector_07, @function
_nds32_vector_07:
1:
j 1b
.size _nds32_vector_07, .-_nds32_vector_07
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid00_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.00, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_00_4b
.type _nds32_vector_00_4b, @function
_nds32_vector_00_4b:
1:
j 1b
.size _nds32_vector_00_4b, .-_nds32_vector_00_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid56_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.56, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_56_4b
.type _nds32_vector_56_4b, @function
_nds32_vector_56_4b:
1:
j 1b
.size _nds32_vector_56_4b, .-_nds32_vector_56_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid31.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.31, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_31
.type _nds32_vector_31, @function
_nds32_vector_31:
1:
j 1b
.size _nds32_vector_31, .-_nds32_vector_31
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid20_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.20, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_20_4b
.type _nds32_vector_20_4b, @function
_nds32_vector_20_4b:
1:
j 1b
.size _nds32_vector_20_4b, .-_nds32_vector_20_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid70.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.70, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_70
.type _nds32_vector_70, @function
_nds32_vector_70:
1:
j 1b
.size _nds32_vector_70, .-_nds32_vector_70
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid47.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.47, "a"
.align 2
.weak _nds32_jmptbl_47
.type _nds32_jmptbl_47, @object
_nds32_jmptbl_47:
.word 0
.size _nds32_jmptbl_47, .-_nds32_jmptbl_47
|
4ms/metamodule-plugin-sdk
| 4,824
|
plugin-libc/libgcc/config/nds32/isr-library/intr_isr.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_usr_regs.inc"
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
#include "save_fpu_regs_01.inc"
#include "save_fpu_regs_02.inc"
#include "save_fpu_regs_03.inc"
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_mac_regs.inc"
#include "restore_usr_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/* First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR -- Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT -- Nested Type
ns: nested
nn: not nested
nr: nested ready */
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_i_sa_ns
.type _nds32_i_sa_ns, @function
_nds32_i_sa_ns:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_i_sa_nr
.type _nds32_i_sa_nr, @function
_nds32_i_sa_nr:
#else /* Not nested handler. */
.globl _nds32_i_sa_nn
.type _nds32_i_sa_nn, @function
_nds32_i_sa_nn:
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.globl _nds32_i_ps_ns
.type _nds32_i_ps_ns, @function
_nds32_i_ps_ns:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_i_ps_nr
.type _nds32_i_ps_nr, @function
_nds32_i_ps_nr:
#else /* Not nested handler. */
.globl _nds32_i_ps_nn
.type _nds32_i_ps_nn, @function
_nds32_i_ps_nn:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/* For 4-byte vector size version, the vector id is
extracted from $ITYPE and is set into $r0 by library.
For 16-byte vector size version, the vector id
is set into $r0 in vector section by compiler. */
/* Save used registers first. */
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL
#else
SAVE_PARTIAL
#endif
/* According to vector size, we need to have different implementation. */
#if __NDS32_ISR_VECTOR_SIZE_4__
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_00
lw $r2, [$r2 + $r0 << #2]
addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */
lw $r2, [$r2 + $r0 << #2]
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
RESTORE_PARTIAL
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_i_sa_ns, .-_nds32_i_sa_ns
#elif defined(NDS32_NESTED_READY)
.size _nds32_i_sa_nr, .-_nds32_i_sa_nr
#else /* Not nested handler. */
.size _nds32_i_sa_nn, .-_nds32_i_sa_nn
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.size _nds32_i_ps_ns, .-_nds32_i_ps_ns
#elif defined(NDS32_NESTED_READY)
.size _nds32_i_ps_nr, .-_nds32_i_ps_nr
#else /* Not nested handler. */
.size _nds32_i_ps_nn, .-_nds32_i_ps_nn
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid01.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.01, "a"
.align 2
.weak _nds32_jmptbl_01
.type _nds32_jmptbl_01, @object
_nds32_jmptbl_01:
.word 0
.size _nds32_jmptbl_01, .-_nds32_jmptbl_01
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid68.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.68, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_68
.type _nds32_vector_68, @function
_nds32_vector_68:
1:
j 1b
.size _nds32_vector_68, .-_nds32_vector_68
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid38.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.38, "a"
.align 2
.weak _nds32_jmptbl_38
.type _nds32_jmptbl_38, @object
_nds32_jmptbl_38:
.word 0
.size _nds32_jmptbl_38, .-_nds32_jmptbl_38
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid27.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.27, "a"
.align 2
.weak _nds32_jmptbl_27
.type _nds32_jmptbl_27, @object
_nds32_jmptbl_27:
.word 0
.size _nds32_jmptbl_27, .-_nds32_jmptbl_27
|
4ms/stm32mp1-baremetal
| 27,747
|
third-party/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/startup_stm32mp15xx.s
|
;******************************************************************************
;* File Name : startup_stm32mp15xx.s
;* Author : MCD Application Team
;* Description : STM32MP15xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
//#define __DATA_IN_ExtSRAM /* When External SRAM is used */
#ifdef __DATA_IN_ExtSRAM
__initial_spTop EQU 0x20000400 ; stack used for SystemInit & SystemInit_ExtMemCtl
#endif /*__DATA_IN_ExtSRAM*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
#ifdef __DATA_IN_ExtSRAM
DCD __initial_spTop ; Use internal RAM for stack for calling SystemInit
#else
DCD sfe(CSTACK)
#endif /*__DATA_IN_ExtSRAM*/
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG1_IRQHandler ;
DCD PVD_AVD_IRQHandler ;
DCD TAMP_IRQHandler ;
DCD RTC_WKUP_ALARM_IRQHandler ;
DCD 0 ;
DCD RCC_IRQHandler ;
DCD EXTI0_IRQHandler ;
DCD EXTI1_IRQHandler ;
DCD EXTI2_IRQHandler ;
DCD EXTI3_IRQHandler ;
DCD EXTI4_IRQHandler ;
DCD DMA1_Stream0_IRQHandler ;
DCD DMA1_Stream1_IRQHandler ;
DCD DMA1_Stream2_IRQHandler ;
DCD DMA1_Stream3_IRQHandler ;
DCD DMA1_Stream4_IRQHandler ;
DCD DMA1_Stream5_IRQHandler ;
DCD DMA1_Stream6_IRQHandler ;
DCD ADC1_IRQHandler ;
DCD FDCAN1_IT0_IRQHandler ;
DCD FDCAN2_IT0_IRQHandler ;
DCD FDCAN1_IT1_IRQHandler ;
DCD FDCAN2_IT1_IRQHandler ;
DCD EXTI5_IRQHandler ;
DCD TIM1_BRK_IRQHandler ;
DCD TIM1_UP_IRQHandler ;
DCD TIM1_TRG_COM_IRQHandler ;
DCD TIM1_CC_IRQHandler ;
DCD TIM2_IRQHandler ;
DCD TIM3_IRQHandler ;
DCD TIM4_IRQHandler ;
DCD I2C1_EV_IRQHandler ;
DCD I2C1_ER_IRQHandler ;
DCD I2C2_EV_IRQHandler ;
DCD I2C2_ER_IRQHandler ;
DCD SPI1_IRQHandler ;
DCD SPI2_IRQHandler ;
DCD USART1_IRQHandler ;
DCD USART2_IRQHandler ;
DCD USART3_IRQHandler ;
DCD EXTI10_IRQHandler ;
DCD RTC_TIMESTAMP_IRQHandler ;
DCD EXTI11_IRQHandler ;
DCD TIM8_BRK_IRQHandler ;
DCD TIM8_UP_IRQHandler ;
DCD TIM8_TRG_COM_IRQHandler ;
DCD TIM8_CC_IRQHandler ;
DCD DMA1_Stream7_IRQHandler ;
DCD FMC_IRQHandler ;
DCD SDMMC1_IRQHandler ;
DCD TIM5_IRQHandler ;
DCD SPI3_IRQHandler ;
DCD UART4_IRQHandler ;
DCD UART5_IRQHandler ;
DCD TIM6_IRQHandler ;
DCD TIM7_IRQHandler ;
DCD DMA2_Stream0_IRQHandler ;
DCD DMA2_Stream1_IRQHandler ;
DCD DMA2_Stream2_IRQHandler ;
DCD DMA2_Stream3_IRQHandler ;
DCD DMA2_Stream4_IRQHandler ;
DCD ETH1_IRQHandler ;
DCD ETH1_WKUP_IRQHandler ;
DCD FDCAN_CAL_IRQHandler ;
DCD EXTI6_IRQHandler ;
DCD EXTI7_IRQHandler ;
DCD EXTI8_IRQHandler ;
DCD EXTI9_IRQHandler ;
DCD DMA2_Stream5_IRQHandler ;
DCD DMA2_Stream6_IRQHandler ;
DCD DMA2_Stream7_IRQHandler ;
DCD USART6_IRQHandler ;
DCD I2C3_EV_IRQHandler ;
DCD I2C3_ER_IRQHandler ;
DCD USBH_OHCI_IRQHandler ;
DCD USBH_EHCI_IRQHandler ;
DCD EXTI12_IRQHandler ;
DCD EXTI13_IRQHandler ;
DCD DCMI_IRQHandler ;
DCD CRYP1_IRQHandler ;
DCD HASH1_IRQHandler ;
DCD FPU_IRQHandler ;
DCD UART7_IRQHandler ;
DCD UART8_IRQHandler ;
DCD SPI4_IRQHandler ;
DCD SPI5_IRQHandler ;
DCD SPI6_IRQHandler ;
DCD SAI1_IRQHandler ;
DCD LTDC_IRQHandler ;
DCD LTDC_ER_IRQHandler ;
DCD ADC2_IRQHandler ;
DCD SAI2_IRQHandler ;
DCD QUADSPI_IRQHandler ;
DCD LPTIM1_IRQHandler ;
DCD CEC_IRQHandler ;
DCD I2C4_EV_IRQHandler ;
DCD I2C4_ER_IRQHandler ;
DCD SPDIF_RX_IRQHandler ;
DCD OTG_IRQHandler ;
DCD 0 ;
DCD IPCC_RX0_IRQHandler ;
DCD IPCC_TX0_IRQHandler ;
DCD DMAMUX1_OVR_IRQHandler ;
DCD IPCC_RX1_IRQHandler ;
DCD IPCC_TX1_IRQHandler ;
DCD CRYP2_IRQHandler ;
DCD HASH2_IRQHandler ;
DCD I2C5_EV_IRQHandler ;
DCD I2C5_ER_IRQHandler ;
DCD GPU_IRQHandler ;
DCD DFSDM1_FLT0_IRQHandler ;
DCD DFSDM1_FLT1_IRQHandler ;
DCD DFSDM1_FLT2_IRQHandler ;
DCD DFSDM1_FLT3_IRQHandler ;
DCD SAI3_IRQHandler ;
DCD DFSDM1_FLT4_IRQHandler ;
DCD TIM15_IRQHandler ;
DCD TIM16_IRQHandler ;
DCD TIM17_IRQHandler ;
DCD TIM12_IRQHandler ;
DCD MDIOS_IRQHandler ;
DCD EXTI14_IRQHandler ;
DCD MDMA_IRQHandler ;
DCD DSI_IRQHandler ;
DCD SDMMC2_IRQHandler ;
DCD HSEM_IT2_IRQHandler ;
DCD DFSDM1_FLT5_IRQHandler ;
DCD EXTI15_IRQHandler ;
DCD nCTIIRQ1_IRQHandler ;
DCD nCTIIRQ2_IRQHandler ;
DCD TIM13_IRQHandler ;
DCD TIM14_IRQHandler ;
DCD DAC_IRQHandler ;
DCD RNG1_IRQHandler ;
DCD RNG2_IRQHandler ;
DCD I2C6_EV_IRQHandler ;
DCD I2C6_ER_IRQHandler ;
DCD SDMMC3_IRQHandler ;
DCD LPTIM2_IRQHandler ;
DCD LPTIM3_IRQHandler ;
DCD LPTIM4_IRQHandler ;
DCD LPTIM5_IRQHandler ;
DCD ETH1_LPI_IRQHandler ;
DCD 0 ;
DCD MPU_SEV_IRQHandler ;
DCD RCC_WAKEUP_IRQHandler ;
DCD SAI4_IRQHandler ;
DCD DTS_IRQHandler ;
DCD 0 ;
DCD WAKEUP_PIN_IRQHandler ;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BLX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG1_IRQHandler
B WWDG1_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_IRQHandler
B TAMP_IRQHandler
PUBWEAK RTC_WKUP_ALARM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_ALARM_IRQHandler
B RTC_WKUP_ALARM_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI5_IRQHandler
B EXTI5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI10_IRQHandler
B EXTI10_IRQHandler
PUBWEAK RTC_TIMESTAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TIMESTAMP_IRQHandler
B RTC_TIMESTAMP_IRQHandler
PUBWEAK EXTI11_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI11_IRQHandler
B EXTI11_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH1_IRQHandler
B ETH1_IRQHandler
PUBWEAK ETH1_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH1_WKUP_IRQHandler
B ETH1_WKUP_IRQHandler
PUBWEAK ETH1_LPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH1_LPI_IRQHandler
B ETH1_LPI_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK EXTI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI6_IRQHandler
B EXTI6_IRQHandler
PUBWEAK EXTI7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI7_IRQHandler
B EXTI7_IRQHandler
PUBWEAK EXTI8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI8_IRQHandler
B EXTI8_IRQHandler
PUBWEAK EXTI9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_IRQHandler
B EXTI9_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK USBH_OHCI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBH_OHCI_IRQHandler
B USBH_OHCI_IRQHandler
PUBWEAK USBH_EHCI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBH_EHCI_IRQHandler
B USBH_EHCI_IRQHandler
PUBWEAK EXTI12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI12_IRQHandler
B EXTI12_IRQHandler
PUBWEAK EXTI13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI13_IRQHandler
B EXTI13_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CRYP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRYP1_IRQHandler
B CRYP1_IRQHandler
PUBWEAK HASH1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HASH1_IRQHandler
B HASH1_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_IRQHandler
B OTG_IRQHandler
PUBWEAK IPCC_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_RX0_IRQHandler
B IPCC_RX0_IRQHandler
PUBWEAK IPCC_TX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_TX0_IRQHandler
B IPCC_TX0_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK IPCC_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_RX1_IRQHandler
B IPCC_RX1_IRQHandler
PUBWEAK IPCC_TX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_TX1_IRQHandler
B IPCC_TX1_IRQHandler
PUBWEAK CRYP2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRYP2_IRQHandler
B CRYP2_IRQHandler
PUBWEAK HASH2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HASH2_IRQHandler
B HASH2_IRQHandler
PUBWEAK I2C5_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C5_EV_IRQHandler
B I2C5_EV_IRQHandler
PUBWEAK I2C5_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C5_ER_IRQHandler
B I2C5_ER_IRQHandler
PUBWEAK GPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPU_IRQHandler
B GPU_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK DFSDM1_FLT4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT4_IRQHandler
B DFSDM1_FLT4_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM12_IRQHandler
B TIM12_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK EXTI14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI14_IRQHandler
B EXTI14_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK DSI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DSI_IRQHandler
B DSI_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM_IT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IT2_IRQHandler
B HSEM_IT2_IRQHandler
PUBWEAK DFSDM1_FLT5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT5_IRQHandler
B DFSDM1_FLT5_IRQHandler
PUBWEAK nCTIIRQ1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
nCTIIRQ1_IRQHandler
B nCTIIRQ1_IRQHandler
PUBWEAK nCTIIRQ2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
nCTIIRQ2_IRQHandler
B nCTIIRQ2_IRQHandler
PUBWEAK EXTI15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_IRQHandler
B EXTI15_IRQHandler
PUBWEAK TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM13_IRQHandler
B TIM13_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK RNG1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG1_IRQHandler
B RNG1_IRQHandler
PUBWEAK RNG2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG2_IRQHandler
B RNG2_IRQHandler
PUBWEAK I2C6_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C6_EV_IRQHandler
B I2C6_EV_IRQHandler
PUBWEAK I2C6_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C6_ER_IRQHandler
B I2C6_ER_IRQHandler
PUBWEAK SDMMC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC3_IRQHandler
B SDMMC3_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK MPU_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MPU_SEV_IRQHandler
B MPU_SEV_IRQHandler
PUBWEAK RCC_WAKEUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_WAKEUP_IRQHandler
B RCC_WAKEUP_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK DTS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DTS_IRQHandler
B DTS_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid09_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.09, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_09_4b
.type _nds32_vector_09_4b, @function
_nds32_vector_09_4b:
1:
j 1b
.size _nds32_vector_09_4b, .-_nds32_vector_09_4b
|
4ms/stm32mp1-baremetal
| 34,186
|
third-party/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s
|
/**
******************************************************************************
* @file startup_stm32mp15xx.s
* @author MCD Application Team
* @brief STM32MP15xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .startup_copro_fw.Reset_Handler,"ax"
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _sidata: End of code section, i.e., begin of data sections to copy from.
* _sdata/_edata: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
// ldr r0, =SystemInit
// blx r0
/* Call static constructors */
bl __libc_init_array
// ldr r0, =__libc_init_array
// blx r0
/* Call the application's entry point.*/
bl main
//ldr r0, =main
//blx r0
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
// External Interrupts
.word WWDG1_IRQHandler // Window WatchDog 1
.word PVD_AVD_IRQHandler // PVD and AVD through EXTI Line detection
.word TAMP_IRQHandler // Tamper and TimeStamps through the EXTI line
.word RTC_WKUP_ALARM_IRQHandler // RTC Wakeup and Alarm through the EXTI line
.word RESERVED4_IRQHandler // Reserved
.word RCC_IRQHandler // RCC
.word EXTI0_IRQHandler // EXTI Line0
.word EXTI1_IRQHandler // EXTI Line1
.word EXTI2_IRQHandler // EXTI Line2
.word EXTI3_IRQHandler // EXTI Line3
.word EXTI4_IRQHandler // EXTI Line4
.word DMA1_Stream0_IRQHandler // DMA1 Stream 0
.word DMA1_Stream1_IRQHandler // DMA1 Stream 1
.word DMA1_Stream2_IRQHandler // DMA1 Stream 2
.word DMA1_Stream3_IRQHandler // DMA1 Stream 3
.word DMA1_Stream4_IRQHandler // DMA1 Stream 4
.word DMA1_Stream5_IRQHandler // DMA1 Stream 5
.word DMA1_Stream6_IRQHandler // DMA1 Stream 6
.word ADC1_IRQHandler // ADC1
.word FDCAN1_IT0_IRQHandler // FDCAN1 Interrupt line 0
.word FDCAN2_IT0_IRQHandler // FDCAN2 Interrupt line 0
.word FDCAN1_IT1_IRQHandler // FDCAN1 Interrupt line 1
.word FDCAN2_IT1_IRQHandler // FDCAN2 Interrupt line 1
.word EXTI5_IRQHandler // External Line5 interrupts through AIEC
.word TIM1_BRK_IRQHandler // TIM1 Break interrupt
.word TIM1_UP_IRQHandler // TIM1 Update Interrupt
.word TIM1_TRG_COM_IRQHandler // TIM1 Trigger and Commutation Interrupt
.word TIM1_CC_IRQHandler // TIM1 Capture Compare
.word TIM2_IRQHandler // TIM2
.word TIM3_IRQHandler // TIM3
.word TIM4_IRQHandler // TIM4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EXTI10_IRQHandler // External Line10 interrupts through AIEC
.word RTC_TIMESTAMP_IRQHandler // RTC TimeStamp through EXTI Line
.word EXTI11_IRQHandler // External Line11 interrupts through AIEC
.word TIM8_BRK_IRQHandler // TIM8 Break Interrupt
.word TIM8_UP_IRQHandler // TIM8 Update Interrupt
.word TIM8_TRG_COM_IRQHandler // TIM8 Trigger and Commutation Interrupt
.word TIM8_CC_IRQHandler // TIM8 Capture Compare Interrupt
.word DMA1_Stream7_IRQHandler // DMA1 Stream7
.word FMC_IRQHandler // FMC
.word SDMMC1_IRQHandler // SDMMC1
.word TIM5_IRQHandler // TIM5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word TIM6_IRQHandler // TIM6
.word TIM7_IRQHandler // TIM7
.word DMA2_Stream0_IRQHandler // DMA2 Stream 0
.word DMA2_Stream1_IRQHandler // DMA2 Stream 1
.word DMA2_Stream2_IRQHandler // DMA2 Stream 2
.word DMA2_Stream3_IRQHandler // DMA2 Stream 3
.word DMA2_Stream4_IRQHandler // DMA2 Stream 4
.word ETH1_IRQHandler // Ethernet
.word ETH1_WKUP_IRQHandler // Ethernet Wakeup through EXTI line
.word FDCAN_CAL_IRQHandler // FDCAN Calibration
.word EXTI6_IRQHandler // EXTI Line6 interrupts through AIEC
.word EXTI7_IRQHandler // EXTI Line7 interrupts through AIEC
.word EXTI8_IRQHandler // EXTI Line8 interrupts through AIEC
.word EXTI9_IRQHandler // EXTI Line9 interrupts through AIEC
.word DMA2_Stream5_IRQHandler // DMA2 Stream 5
.word DMA2_Stream6_IRQHandler // DMA2 Stream 6
.word DMA2_Stream7_IRQHandler // DMA2 Stream 7
.word USART6_IRQHandler // USART6
.word I2C3_EV_IRQHandler // I2C3 event
.word I2C3_ER_IRQHandler // I2C3 error
.word USBH_OHCI_IRQHandler // USB Host OHCI
.word USBH_EHCI_IRQHandler // USB Host EHCI
.word EXTI12_IRQHandler // EXTI Line12 interrupts through AIEC
.word EXTI13_IRQHandler // EXTI Line13 interrupts through AIEC
.word DCMI_IRQHandler // DCMI
.word CRYP1_IRQHandler // Crypto1 global interrupt
.word HASH1_IRQHandler // Crypto Hash1 interrupt
.word FPU_IRQHandler // FPU
.word UART7_IRQHandler // UART7
.word UART8_IRQHandler // UART8
.word SPI4_IRQHandler // SPI4
.word SPI5_IRQHandler // SPI5
.word SPI6_IRQHandler // SPI6
.word SAI1_IRQHandler // SAI1
.word LTDC_IRQHandler // LTDC
.word LTDC_ER_IRQHandler // LTDC error
.word ADC2_IRQHandler // ADC2
.word SAI2_IRQHandler // SAI2
.word QUADSPI_IRQHandler // QUADSPI
.word LPTIM1_IRQHandler // LPTIM1 global interrupt
.word CEC_IRQHandler // HDMI_CEC
.word I2C4_EV_IRQHandler // I2C4 Event
.word I2C4_ER_IRQHandler // I2C4 Error
.word SPDIF_RX_IRQHandler // SPDIF_RX
.word OTG_IRQHandler // USB On The Go HS global interrupt
.word RESERVED99_IRQHandler // Reserved
.word IPCC_RX0_IRQHandler // Mailbox RX0 Free interrupt
.word IPCC_TX0_IRQHandler // Mailbox TX0 Free interrupt
.word DMAMUX1_OVR_IRQHandler // DMAMUX1 Overrun interrupt
.word IPCC_RX1_IRQHandler // Mailbox RX1 Free interrupt
.word IPCC_TX1_IRQHandler // Mailbox TX1 Free interrupt
.word CRYP2_IRQHandler // Crypto2 global interrupt
.word HASH2_IRQHandler // Crypto Hash2 interrupt
.word I2C5_EV_IRQHandler // I2C5 Event Interrupt
.word I2C5_ER_IRQHandler // I2C5 Error Interrupt
.word GPU_IRQHandler // GPU Global Interrupt
.word DFSDM1_FLT0_IRQHandler // DFSDM Filter0 Interrupt
.word DFSDM1_FLT1_IRQHandler // DFSDM Filter1 Interrupt
.word DFSDM1_FLT2_IRQHandler // DFSDM Filter2 Interrupt
.word DFSDM1_FLT3_IRQHandler // DFSDM Filter3 Interrupt
.word SAI3_IRQHandler // SAI3 global Interrupt
.word DFSDM1_FLT4_IRQHandler // DFSDM Filter4 Interrupt
.word TIM15_IRQHandler // TIM15 global Interrupt
.word TIM16_IRQHandler // TIM16 global Interrupt
.word TIM17_IRQHandler // TIM17 global Interrupt
.word TIM12_IRQHandler // TIM12 global Interrupt
.word MDIOS_IRQHandler // MDIOS global Interrupt
.word EXTI14_IRQHandler // EXTI Line14 interrupts through AIEC
.word MDMA_IRQHandler // MDMA global Interrupt
.word DSI_IRQHandler // DSI global Interrupt
.word SDMMC2_IRQHandler // SDMMC2 global Interrupt
.word HSEM_IT2_IRQHandler // HSEM global Interrupt
.word DFSDM1_FLT5_IRQHandler // DFSDM Filter5 Interrupt
.word EXTI15_IRQHandler // EXTI Line15 interrupts through AIEC
.word nCTIIRQ1_IRQHandler // Cortex-M4 CTI interrupt 1
.word nCTIIRQ2_IRQHandler // Cortex-M4 CTI interrupt 2
.word TIM13_IRQHandler // TIM13 global interrupt
.word TIM14_IRQHandler // TIM14 global interrupt
.word DAC_IRQHandler // DAC1 and DAC2 underrun error interrupts
.word RNG1_IRQHandler // RNG1 interrupt
.word RNG2_IRQHandler // RNG2 interrupt
.word I2C6_EV_IRQHandler // I2C6 Event Interrupt
.word I2C6_ER_IRQHandler // I2C6 Error Interrupt
.word SDMMC3_IRQHandler // SDMMC3 global Interrupt
.word LPTIM2_IRQHandler // LPTIM2 global interrupt
.word LPTIM3_IRQHandler // LPTIM3 global interrupt
.word LPTIM4_IRQHandler // LPTIM4 global interrupt
.word LPTIM5_IRQHandler // LPTIM5 global interrupt
.word ETH1_LPI_IRQHandler // ETH1_LPI interrupt
.word RESERVED143_IRQHandler // Reserved
.word MPU_SEV_IRQHandler // MPU Send Event through AIEC
.word RCC_WAKEUP_IRQHandler // RCC Wake up interrupt
.word SAI4_IRQHandler // SAI4 global interrupt
.word DTS_IRQHandler // Temperature sensor interrupt
.word RESERVED148_IRQHandler // Reserved
.word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak RESERVED4_IRQHandler
.thumb_set RESERVED4_IRQHandler,Default_Handler
.weak RESERVED99_IRQHandler
.thumb_set RESERVED99_IRQHandler,Default_Handler
.weak ETH1_LPI_IRQHandler
.thumb_set ETH1_LPI_IRQHandler,Default_Handler
.weak RESERVED143_IRQHandler
.thumb_set RESERVED143_IRQHandler,Default_Handler
.weak WWDG1_IRQHandler
.thumb_set WWDG1_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_IRQHandler
.thumb_set TAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_ALARM_IRQHandler
.thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak ADC2_IRQHandler
.thumb_set ADC2_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak EXTI5_IRQHandler
.thumb_set EXTI5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI10_IRQHandler
.thumb_set EXTI10_IRQHandler,Default_Handler
.weak RTC_TIMESTAMP_IRQHandler
.thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
.weak EXTI11_IRQHandler
.thumb_set EXTI11_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH1_IRQHandler
.thumb_set ETH1_IRQHandler,Default_Handler
.weak ETH1_WKUP_IRQHandler
.thumb_set ETH1_WKUP_IRQHandler,Default_Handler
.weak ETH1_LPI_IRQHandler
.thumb_set ETH1_LPI_IRQHandler,Default_Handler
.weak EXTI6_IRQHandler
.thumb_set EXTI6_IRQHandler,Default_Handler
.weak EXTI7_IRQHandler
.thumb_set EXTI7_IRQHandler,Default_Handler
.weak EXTI8_IRQHandler
.thumb_set EXTI8_IRQHandler,Default_Handler
.weak EXTI9_IRQHandler
.thumb_set EXTI9_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak USBH_OHCI_IRQHandler
.thumb_set USBH_OHCI_IRQHandler,Default_Handler
.weak USBH_EHCI_IRQHandler
.thumb_set USBH_EHCI_IRQHandler,Default_Handler
.weak EXTI12_IRQHandler
.thumb_set EXTI12_IRQHandler,Default_Handler
.weak EXTI13_IRQHandler
.thumb_set EXTI13_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP1_IRQHandler
.thumb_set CRYP1_IRQHandler,Default_Handler
.weak HASH1_IRQHandler
.thumb_set HASH1_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_IRQHandler
.thumb_set OTG_IRQHandler,Default_Handler
.weak IPCC_RX0_IRQHandler
.thumb_set IPCC_RX0_IRQHandler,Default_Handler
.weak IPCC_TX0_IRQHandler
.thumb_set IPCC_TX0_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak IPCC_RX1_IRQHandler
.thumb_set IPCC_RX1_IRQHandler,Default_Handler
.weak IPCC_TX1_IRQHandler
.thumb_set IPCC_TX1_IRQHandler,Default_Handler
.weak CRYP2_IRQHandler
.thumb_set CRYP2_IRQHandler,Default_Handler
.weak HASH2_IRQHandler
.thumb_set HASH2_IRQHandler,Default_Handler
.weak I2C5_EV_IRQHandler
.thumb_set I2C5_EV_IRQHandler,Default_Handler
.weak I2C5_ER_IRQHandler
.thumb_set I2C5_ER_IRQHandler,Default_Handler
.weak GPU_IRQHandler
.thumb_set GPU_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak DFSDM1_FLT4_IRQHandler
.thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak TIM12_IRQHandler
.thumb_set TIM12_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak EXTI14_IRQHandler
.thumb_set EXTI14_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak DSI_IRQHandler
.thumb_set DSI_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM_IT2_IRQHandler
.thumb_set HSEM_IT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT5_IRQHandler
.thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
.weak EXTI15_IRQHandler
.thumb_set EXTI15_IRQHandler,Default_Handler
.weak nCTIIRQ1_IRQHandler
.thumb_set nCTIIRQ1_IRQHandler,Default_Handler
.weak nCTIIRQ2_IRQHandler
.thumb_set nCTIIRQ2_IRQHandler,Default_Handler
.weak TIM13_IRQHandler
.thumb_set TIM13_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak RNG1_IRQHandler
.thumb_set RNG1_IRQHandler,Default_Handler
.weak RNG2_IRQHandler
.thumb_set RNG2_IRQHandler,Default_Handler
.weak I2C6_EV_IRQHandler
.thumb_set I2C6_EV_IRQHandler,Default_Handler
.weak I2C6_ER_IRQHandler
.thumb_set I2C6_ER_IRQHandler,Default_Handler
.weak SDMMC3_IRQHandler
.thumb_set SDMMC3_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak MPU_SEV_IRQHandler
.thumb_set MPU_SEV_IRQHandler,Default_Handler
.weak RCC_WAKEUP_IRQHandler
.thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak DTS_IRQHandler
.thumb_set DTS_IRQHandler,Default_Handler
.weak RESERVED148_IRQHandler
.thumb_set RESERVED148_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
4ms/stm32mp1-baremetal
| 30,103
|
third-party/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s
|
;******************************************************************************
;* File Name : startup_stm32mp15xx.s
;* Author : MCD Application Team
;* Description : STM32MP15xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD WWDG1_IRQHandler ;
DCD PVD_AVD_IRQHandler ;
DCD TAMP_IRQHandler ;
DCD RTC_WKUP_ALARM_IRQHandler ;
DCD RESERVED4_IRQHandler ;
DCD RCC_IRQHandler ;
DCD EXTI0_IRQHandler ;
DCD EXTI1_IRQHandler ;
DCD EXTI2_IRQHandler ;
DCD EXTI3_IRQHandler ;
DCD EXTI4_IRQHandler ;
DCD DMA1_Stream0_IRQHandler ;
DCD DMA1_Stream1_IRQHandler ;
DCD DMA1_Stream2_IRQHandler ;
DCD DMA1_Stream3_IRQHandler ;
DCD DMA1_Stream4_IRQHandler ;
DCD DMA1_Stream5_IRQHandler ;
DCD DMA1_Stream6_IRQHandler ;
DCD ADC1_IRQHandler ;
DCD FDCAN1_IT0_IRQHandler ;
DCD FDCAN2_IT0_IRQHandler ;
DCD FDCAN1_IT1_IRQHandler ;
DCD FDCAN2_IT1_IRQHandler ;
DCD EXTI5_IRQHandler ;
DCD TIM1_BRK_IRQHandler ;
DCD TIM1_UP_IRQHandler ;
DCD TIM1_TRG_COM_IRQHandler ;
DCD TIM1_CC_IRQHandler ;
DCD TIM2_IRQHandler ;
DCD TIM3_IRQHandler ;
DCD TIM4_IRQHandler ;
DCD I2C1_EV_IRQHandler ;
DCD I2C1_ER_IRQHandler ;
DCD I2C2_EV_IRQHandler ;
DCD I2C2_ER_IRQHandler ;
DCD SPI1_IRQHandler ;
DCD SPI2_IRQHandler ;
DCD USART1_IRQHandler ;
DCD USART2_IRQHandler ;
DCD USART3_IRQHandler ;
DCD EXTI10_IRQHandler ;
DCD RTC_TIMESTAMP_IRQHandler ;
DCD EXTI11_IRQHandler ;
DCD TIM8_BRK_IRQHandler ;
DCD TIM8_UP_IRQHandler ;
DCD TIM8_TRG_COM_IRQHandler ;
DCD TIM8_CC_IRQHandler ;
DCD DMA1_Stream7_IRQHandler ;
DCD FMC_IRQHandler ;
DCD SDMMC1_IRQHandler ;
DCD TIM5_IRQHandler ;
DCD SPI3_IRQHandler ;
DCD UART4_IRQHandler ;
DCD UART5_IRQHandler ;
DCD TIM6_IRQHandler ;
DCD TIM7_IRQHandler ;
DCD DMA2_Stream0_IRQHandler ;
DCD DMA2_Stream1_IRQHandler ;
DCD DMA2_Stream2_IRQHandler ;
DCD DMA2_Stream3_IRQHandler ;
DCD DMA2_Stream4_IRQHandler ;
DCD ETH1_IRQHandler ;
DCD ETH1_WKUP_IRQHandler ;
DCD FDCAN_CAL_IRQHandler ;
DCD EXTI6_IRQHandler ;
DCD EXTI7_IRQHandler ;
DCD EXTI8_IRQHandler ;
DCD EXTI9_IRQHandler ;
DCD DMA2_Stream5_IRQHandler ;
DCD DMA2_Stream6_IRQHandler ;
DCD DMA2_Stream7_IRQHandler ;
DCD USART6_IRQHandler ;
DCD I2C3_EV_IRQHandler ;
DCD I2C3_ER_IRQHandler ;
DCD USBH_OHCI_IRQHandler ;
DCD USBH_EHCI_IRQHandler ;
DCD EXTI12_IRQHandler ;
DCD EXTI13_IRQHandler ;
DCD DCMI_IRQHandler ;
DCD CRYP1_IRQHandler ;
DCD HASH1_IRQHandler ;
DCD FPU_IRQHandler ;
DCD UART7_IRQHandler ;
DCD UART8_IRQHandler ;
DCD SPI4_IRQHandler ;
DCD SPI5_IRQHandler ;
DCD SPI6_IRQHandler ;
DCD SAI1_IRQHandler ;
DCD LTDC_IRQHandler ;
DCD LTDC_ER_IRQHandler ;
DCD ADC2_IRQHandler ;
DCD SAI2_IRQHandler ;
DCD QUADSPI_IRQHandler ;
DCD LPTIM1_IRQHandler ;
DCD CEC_IRQHandler ;
DCD I2C4_EV_IRQHandler ;
DCD I2C4_ER_IRQHandler ;
DCD SPDIF_RX_IRQHandler ;
DCD OTG_IRQHandler ;
DCD RESERVED99_IRQHandler ;
DCD IPCC_RX0_IRQHandler ;
DCD IPCC_TX0_IRQHandler ;
DCD DMAMUX1_OVR_IRQHandler ;
DCD IPCC_RX1_IRQHandler ;
DCD IPCC_TX1_IRQHandler ;
DCD CRYP2_IRQHandler ;
DCD HASH2_IRQHandler ;
DCD I2C5_EV_IRQHandler ;
DCD I2C5_ER_IRQHandler ;
DCD GPU_IRQHandler ;
DCD DFSDM1_FLT0_IRQHandler ;
DCD DFSDM1_FLT1_IRQHandler ;
DCD DFSDM1_FLT2_IRQHandler ;
DCD DFSDM1_FLT3_IRQHandler ;
DCD SAI3_IRQHandler ;
DCD DFSDM1_FLT4_IRQHandler ;
DCD TIM15_IRQHandler ;
DCD TIM16_IRQHandler ;
DCD TIM17_IRQHandler ;
DCD TIM12_IRQHandler ;
DCD MDIOS_IRQHandler ;
DCD EXTI14_IRQHandler ;
DCD MDMA_IRQHandler ;
DCD DSI_IRQHandler ;
DCD SDMMC2_IRQHandler ;
DCD HSEM_IT2_IRQHandler ;
DCD DFSDM1_FLT5_IRQHandler ;
DCD EXTI15_IRQHandler ;
DCD nCTIIRQ1_IRQHandler ;
DCD nCTIIRQ2_IRQHandler ;
DCD TIM13_IRQHandler ;
DCD TIM14_IRQHandler ;
DCD DAC_IRQHandler ;
DCD RNG1_IRQHandler ;
DCD RNG2_IRQHandler ;
DCD I2C6_EV_IRQHandler ;
DCD I2C6_ER_IRQHandler ;
DCD SDMMC3_IRQHandler ;
DCD LPTIM2_IRQHandler ;
DCD LPTIM3_IRQHandler ;
DCD LPTIM4_IRQHandler ;
DCD LPTIM5_IRQHandler ;
DCD ETH1_LPI_IRQHandler ;
DCD RESERVED143_IRQHandler ;
DCD MPU_SEV_IRQHandler ;
DCD RCC_WAKEUP_IRQHandler ;
DCD SAI4_IRQHandler ;
DCD DTS_IRQHandler ;
DCD RESERVED148_IRQHandler ;
DCD WAKEUP_PIN_IRQHandler ;
SPACE (73 * 4) ; Interrupts 151 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler WWDG1_IRQHandler ; Window WatchDog 1
Set_Default_Handler PVD_AVD_IRQHandler ; PVD and AVD through EXTI Line detection
Set_Default_Handler TAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
Set_Default_Handler RTC_WKUP_ALARM_IRQHandler ; RTC Wakeup and Alarm through the EXTI line
Set_Default_Handler RESERVED4_IRQHandler ; Reserved
Set_Default_Handler RCC_IRQHandler ; RCC
Set_Default_Handler EXTI0_IRQHandler ; EXTI Line0
Set_Default_Handler EXTI1_IRQHandler ; EXTI Line1
Set_Default_Handler EXTI2_IRQHandler ; EXTI Line2
Set_Default_Handler EXTI3_IRQHandler ; EXTI Line3
Set_Default_Handler EXTI4_IRQHandler ; EXTI Line4
Set_Default_Handler DMA1_Stream0_IRQHandler ; DMA1 Stream 0
Set_Default_Handler DMA1_Stream1_IRQHandler ; DMA1 Stream 1
Set_Default_Handler DMA1_Stream2_IRQHandler ; DMA1 Stream 2
Set_Default_Handler DMA1_Stream3_IRQHandler ; DMA1 Stream 3
Set_Default_Handler DMA1_Stream4_IRQHandler ; DMA1 Stream 4
Set_Default_Handler DMA1_Stream5_IRQHandler ; DMA1 Stream 5
Set_Default_Handler DMA1_Stream6_IRQHandler ; DMA1 Stream 6
Set_Default_Handler ADC1_IRQHandler ; ADC1
Set_Default_Handler FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt line 0
Set_Default_Handler FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt line 0
Set_Default_Handler FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt line 1
Set_Default_Handler FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt line 1
Set_Default_Handler EXTI5_IRQHandler ; External Line5 interrupts through AIEC
Set_Default_Handler TIM1_BRK_IRQHandler ; TIM1 Break interrupt
Set_Default_Handler TIM1_UP_IRQHandler ; TIM1 Update Interrupt
Set_Default_Handler TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
Set_Default_Handler TIM1_CC_IRQHandler ; TIM1 Capture Compare
Set_Default_Handler TIM2_IRQHandler ; TIM2
Set_Default_Handler TIM3_IRQHandler ; TIM3
Set_Default_Handler TIM4_IRQHandler ; TIM4
Set_Default_Handler I2C1_EV_IRQHandler ; I2C1 Event
Set_Default_Handler I2C1_ER_IRQHandler ; I2C1 Error
Set_Default_Handler I2C2_EV_IRQHandler ; I2C2 Event
Set_Default_Handler I2C2_ER_IRQHandler ; I2C2 Error
Set_Default_Handler SPI1_IRQHandler ; SPI1
Set_Default_Handler SPI2_IRQHandler ; SPI2
Set_Default_Handler USART1_IRQHandler ; USART1
Set_Default_Handler USART2_IRQHandler ; USART2
Set_Default_Handler USART3_IRQHandler ; USART3
Set_Default_Handler EXTI10_IRQHandler ; External Line10 interrupts through AIEC
Set_Default_Handler RTC_TIMESTAMP_IRQHandler ; RTC TimeStamp through EXTI Line
Set_Default_Handler EXTI11_IRQHandler ; External Line11 interrupts through AIEC
Set_Default_Handler TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
Set_Default_Handler TIM8_UP_IRQHandler ; TIM8 Update Interrupt
Set_Default_Handler TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
Set_Default_Handler TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
Set_Default_Handler DMA1_Stream7_IRQHandler ; DMA1 Stream7
Set_Default_Handler FMC_IRQHandler ; FMC
Set_Default_Handler SDMMC1_IRQHandler ; SDMMC1
Set_Default_Handler TIM5_IRQHandler ; TIM5
Set_Default_Handler SPI3_IRQHandler ; SPI3
Set_Default_Handler UART4_IRQHandler ; UART4
Set_Default_Handler UART5_IRQHandler ; UART5
Set_Default_Handler TIM6_IRQHandler ; TIM6
Set_Default_Handler TIM7_IRQHandler ; TIM7
Set_Default_Handler DMA2_Stream0_IRQHandler ; DMA2 Stream 0
Set_Default_Handler DMA2_Stream1_IRQHandler ; DMA2 Stream 1
Set_Default_Handler DMA2_Stream2_IRQHandler ; DMA2 Stream 2
Set_Default_Handler DMA2_Stream3_IRQHandler ; DMA2 Stream 3
Set_Default_Handler DMA2_Stream4_IRQHandler ; DMA2 Stream 4
Set_Default_Handler ETH1_IRQHandler ; Ethernet
Set_Default_Handler ETH1_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
Set_Default_Handler FDCAN_CAL_IRQHandler ; FDCAN Calibration
Set_Default_Handler EXTI6_IRQHandler ; EXTI Line6 interrupts through AIEC
Set_Default_Handler EXTI7_IRQHandler ; EXTI Line7 interrupts through AIEC
Set_Default_Handler EXTI8_IRQHandler ; EXTI Line8 interrupts through AIEC
Set_Default_Handler EXTI9_IRQHandler ; EXTI Line9 interrupts through AIEC
Set_Default_Handler DMA2_Stream5_IRQHandler ; DMA2 Stream 5
Set_Default_Handler DMA2_Stream6_IRQHandler ; DMA2 Stream 6
Set_Default_Handler DMA2_Stream7_IRQHandler ; DMA2 Stream 7
Set_Default_Handler USART6_IRQHandler ; USART6
Set_Default_Handler I2C3_EV_IRQHandler ; I2C3 event
Set_Default_Handler I2C3_ER_IRQHandler ; I2C3 error
Set_Default_Handler USBH_OHCI_IRQHandler ; USB Host OHCI
Set_Default_Handler USBH_EHCI_IRQHandler ; USB Host EHCI
Set_Default_Handler EXTI12_IRQHandler ; EXTI Line12 interrupts through AIEC
Set_Default_Handler EXTI13_IRQHandler ; EXTI Line13 interrupts through AIEC
Set_Default_Handler DCMI_IRQHandler ; DCMI
Set_Default_Handler CRYP1_IRQHandler ; Crypto1 global interrupt
Set_Default_Handler HASH1_IRQHandler ; Crypto Hash1 interrupt
Set_Default_Handler FPU_IRQHandler ; FPU
Set_Default_Handler UART7_IRQHandler ; UART7
Set_Default_Handler UART8_IRQHandler ; UART8
Set_Default_Handler SPI4_IRQHandler ; SPI4
Set_Default_Handler SPI5_IRQHandler ; SPI5
Set_Default_Handler SPI6_IRQHandler ; SPI6
Set_Default_Handler SAI1_IRQHandler ; SAI1
Set_Default_Handler LTDC_IRQHandler ; LTDC
Set_Default_Handler LTDC_ER_IRQHandler ; LTDC error
Set_Default_Handler ADC2_IRQHandler ; ADC2
Set_Default_Handler SAI2_IRQHandler ; SAI2
Set_Default_Handler QUADSPI_IRQHandler ; QUADSPI
Set_Default_Handler LPTIM1_IRQHandler ; LPTIM1 global interrupt
Set_Default_Handler CEC_IRQHandler ; HDMI_CEC
Set_Default_Handler I2C4_EV_IRQHandler ; I2C4 Event
Set_Default_Handler I2C4_ER_IRQHandler ; I2C4 Error
Set_Default_Handler SPDIF_RX_IRQHandler ; SPDIF_RX
Set_Default_Handler OTG_IRQHandler ; USB On The Go HS global interrupt
Set_Default_Handler RESERVED99_IRQHandler ; Reserved
Set_Default_Handler IPCC_RX0_IRQHandler ; Mailbox RX0 Free interrupt
Set_Default_Handler IPCC_TX0_IRQHandler ; Mailbox TX0 Free interrupt
Set_Default_Handler DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
Set_Default_Handler IPCC_RX1_IRQHandler ; Mailbox RX1 Free interrupt
Set_Default_Handler IPCC_TX1_IRQHandler ; Mailbox TX1 Free interrupt
Set_Default_Handler CRYP2_IRQHandler ; Crypto2 global interrupt
Set_Default_Handler HASH2_IRQHandler ; Crypto Hash2 interrupt
Set_Default_Handler I2C5_EV_IRQHandler ; I2C5 Event Interrupt
Set_Default_Handler I2C5_ER_IRQHandler ; I2C5 Error Interrupt
Set_Default_Handler GPU_IRQHandler ; GPU Global Interrupt
Set_Default_Handler DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
Set_Default_Handler DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
Set_Default_Handler DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
Set_Default_Handler DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
Set_Default_Handler SAI3_IRQHandler ; SAI3 global Interrupt
Set_Default_Handler DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
Set_Default_Handler TIM15_IRQHandler ; TIM15 global Interrupt
Set_Default_Handler TIM16_IRQHandler ; TIM16 global Interrupt
Set_Default_Handler TIM17_IRQHandler ; TIM17 global Interrupt
Set_Default_Handler TIM12_IRQHandler ; TIM12 global Interrupt
Set_Default_Handler MDIOS_IRQHandler ; MDIOS global Interrupt
Set_Default_Handler EXTI14_IRQHandler ; EXTI Line14 interrupts through AIEC
Set_Default_Handler MDMA_IRQHandler ; MDMA global Interrupt
Set_Default_Handler DSI_IRQHandler ; DSI global Interrupt
Set_Default_Handler SDMMC2_IRQHandler ; SDMMC2 global Interrupt
Set_Default_Handler HSEM_IT2_IRQHandler ; HSEM global Interrupt
Set_Default_Handler DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
Set_Default_Handler EXTI15_IRQHandler ; EXTI Line15 interrupts through AIEC
Set_Default_Handler nCTIIRQ1_IRQHandler ; Cortex-M4 CTI interrupt 1
Set_Default_Handler nCTIIRQ2_IRQHandler ; Cortex-M4 CTI interrupt 2
Set_Default_Handler TIM13_IRQHandler ; TIM13 global interrupt
Set_Default_Handler TIM14_IRQHandler ; TIM14 global interrupt
Set_Default_Handler DAC_IRQHandler ; DAC1 and DAC2 underrun error interrupts
Set_Default_Handler RNG1_IRQHandler ; RNG1 interrupt
Set_Default_Handler RNG2_IRQHandler ; RNG2 interrupt
Set_Default_Handler I2C6_EV_IRQHandler ; I2C6 Event Interrupt
Set_Default_Handler I2C6_ER_IRQHandler ; I2C6 Error Interrupt
Set_Default_Handler SDMMC3_IRQHandler ; SDMMC3 global Interrupt
Set_Default_Handler LPTIM2_IRQHandler ; LPTIM2 global interrupt
Set_Default_Handler LPTIM3_IRQHandler ; LPTIM3 global interrupt
Set_Default_Handler LPTIM4_IRQHandler ; LPTIM4 global interrupt
Set_Default_Handler LPTIM5_IRQHandler ; LPTIM5 global interrupt
Set_Default_Handler ETH1_LPI_IRQHandler ; Reserved
Set_Default_Handler RESERVED143_IRQHandler ; Reserved
Set_Default_Handler MPU_SEV_IRQHandler ; MPU Send Event through AIEC
Set_Default_Handler RCC_WAKEUP_IRQHandler ; RCC Wake up interrupt
Set_Default_Handler SAI4_IRQHandler ; SAI4 global interrupt
Set_Default_Handler DTS_IRQHandler ; Temperature sensor interrupt
Set_Default_Handler RESERVED148_IRQHandler ; Reserved
Set_Default_Handler WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid35.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.35, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_35
.type _nds32_vector_35, @function
_nds32_vector_35:
1:
j 1b
.size _nds32_vector_35, .-_nds32_vector_35
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid21.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.21, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_21
.type _nds32_vector_21, @function
_nds32_vector_21:
1:
j 1b
.size _nds32_vector_21, .-_nds32_vector_21
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid66_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.66, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_66_4b
.type _nds32_vector_66_4b, @function
_nds32_vector_66_4b:
1:
j 1b
.size _nds32_vector_66_4b, .-_nds32_vector_66_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid58.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.58, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_58
.type _nds32_vector_58, @function
_nds32_vector_58:
1:
j 1b
.size _nds32_vector_58, .-_nds32_vector_58
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid00.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.00, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_00
.type _nds32_vector_00, @function
_nds32_vector_00:
1:
j 1b
.size _nds32_vector_00, .-_nds32_vector_00
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid63_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.63, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_63_4b
.type _nds32_vector_63_4b, @function
_nds32_vector_63_4b:
1:
j 1b
.size _nds32_vector_63_4b, .-_nds32_vector_63_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid72.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.72, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_72
.type _nds32_vector_72, @function
_nds32_vector_72:
1:
j 1b
.size _nds32_vector_72, .-_nds32_vector_72
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid62_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.62, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_62_4b
.type _nds32_vector_62_4b, @function
_nds32_vector_62_4b:
1:
j 1b
.size _nds32_vector_62_4b, .-_nds32_vector_62_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid52_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.52, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_52_4b
.type _nds32_vector_52_4b, @function
_nds32_vector_52_4b:
1:
j 1b
.size _nds32_vector_52_4b, .-_nds32_vector_52_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid33.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.33, "a"
.align 2
.weak _nds32_jmptbl_33
.type _nds32_jmptbl_33, @object
_nds32_jmptbl_33:
.word 0
.size _nds32_jmptbl_33, .-_nds32_jmptbl_33
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid28.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.28, "a"
.align 2
.weak _nds32_jmptbl_28
.type _nds32_jmptbl_28, @object
_nds32_jmptbl_28:
.word 0
.size _nds32_jmptbl_28, .-_nds32_jmptbl_28
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid64.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.64, "a"
.align 2
.weak _nds32_jmptbl_64
.type _nds32_jmptbl_64, @object
_nds32_jmptbl_64:
.word 0
.size _nds32_jmptbl_64, .-_nds32_jmptbl_64
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid64_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.64, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_64_4b
.type _nds32_vector_64_4b, @function
_nds32_vector_64_4b:
1:
j 1b
.size _nds32_vector_64_4b, .-_nds32_vector_64_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid22.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.22, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_22
.type _nds32_vector_22, @function
_nds32_vector_22:
1:
j 1b
.size _nds32_vector_22, .-_nds32_vector_22
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid37_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.37, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_37_4b
.type _nds32_vector_37_4b, @function
_nds32_vector_37_4b:
1:
j 1b
.size _nds32_vector_37_4b, .-_nds32_vector_37_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid48.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.48, "a"
.align 2
.weak _nds32_jmptbl_48
.type _nds32_jmptbl_48, @object
_nds32_jmptbl_48:
.word 0
.size _nds32_jmptbl_48, .-_nds32_jmptbl_48
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid23.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.23, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_23
.type _nds32_vector_23, @function
_nds32_vector_23:
1:
j 1b
.size _nds32_vector_23, .-_nds32_vector_23
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid24_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.24, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_24_4b
.type _nds32_vector_24_4b, @function
_nds32_vector_24_4b:
1:
j 1b
.size _nds32_vector_24_4b, .-_nds32_vector_24_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid05_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.05, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_05_4b
.type _nds32_vector_05_4b, @function
_nds32_vector_05_4b:
1:
j 1b
.size _nds32_vector_05_4b, .-_nds32_vector_05_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid52.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.52, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_52
.type _nds32_vector_52, @function
_nds32_vector_52:
1:
j 1b
.size _nds32_vector_52, .-_nds32_vector_52
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid43.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.43, "a"
.align 2
.weak _nds32_jmptbl_43
.type _nds32_jmptbl_43, @object
_nds32_jmptbl_43:
.word 0
.size _nds32_jmptbl_43, .-_nds32_jmptbl_43
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid72.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.72, "a"
.align 2
.weak _nds32_jmptbl_72
.type _nds32_jmptbl_72, @object
_nds32_jmptbl_72:
.word 0
.size _nds32_jmptbl_72, .-_nds32_jmptbl_72
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid31_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.31, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_31_4b
.type _nds32_vector_31_4b, @function
_nds32_vector_31_4b:
1:
j 1b
.size _nds32_vector_31_4b, .-_nds32_vector_31_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid59.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.59, "a"
.align 2
.weak _nds32_jmptbl_59
.type _nds32_jmptbl_59, @object
_nds32_jmptbl_59:
.word 0
.size _nds32_jmptbl_59, .-_nds32_jmptbl_59
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid68_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.68, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_68_4b
.type _nds32_vector_68_4b, @function
_nds32_vector_68_4b:
1:
j 1b
.size _nds32_vector_68_4b, .-_nds32_vector_68_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid70.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.70, "a"
.align 2
.weak _nds32_jmptbl_70
.type _nds32_jmptbl_70, @object
_nds32_jmptbl_70:
.word 0
.size _nds32_jmptbl_70, .-_nds32_jmptbl_70
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid14.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.14, "a"
.align 2
.weak _nds32_jmptbl_14
.type _nds32_jmptbl_14, @object
_nds32_jmptbl_14:
.word 0
.size _nds32_jmptbl_14, .-_nds32_jmptbl_14
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid10_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.10, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_10_4b
.type _nds32_vector_10_4b, @function
_nds32_vector_10_4b:
1:
j 1b
.size _nds32_vector_10_4b, .-_nds32_vector_10_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid02.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.02, "a"
.align 2
.weak _nds32_jmptbl_02
.type _nds32_jmptbl_02, @object
_nds32_jmptbl_02:
.word 0
.size _nds32_jmptbl_02, .-_nds32_jmptbl_02
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid61.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.61, "a"
.align 2
.weak _nds32_jmptbl_61
.type _nds32_jmptbl_61, @object
_nds32_jmptbl_61:
.word 0
.size _nds32_jmptbl_61, .-_nds32_jmptbl_61
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid37.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.37, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_37
.type _nds32_vector_37, @function
_nds32_vector_37:
1:
j 1b
.size _nds32_vector_37, .-_nds32_vector_37
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid07_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.07, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_07_4b
.type _nds32_vector_07_4b, @function
_nds32_vector_07_4b:
1:
j 1b
.size _nds32_vector_07_4b, .-_nds32_vector_07_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid36_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.36, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_36_4b
.type _nds32_vector_36_4b, @function
_nds32_vector_36_4b:
1:
j 1b
.size _nds32_vector_36_4b, .-_nds32_vector_36_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid71.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.71, "a"
.align 2
.weak _nds32_jmptbl_71
.type _nds32_jmptbl_71, @object
_nds32_jmptbl_71:
.word 0
.size _nds32_jmptbl_71, .-_nds32_jmptbl_71
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid55.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.55, "a"
.align 2
.weak _nds32_jmptbl_55
.type _nds32_jmptbl_55, @object
_nds32_jmptbl_55:
.word 0
.size _nds32_jmptbl_55, .-_nds32_jmptbl_55
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid07.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.07, "a"
.align 2
.weak _nds32_jmptbl_07
.type _nds32_jmptbl_07, @object
_nds32_jmptbl_07:
.word 0
.size _nds32_jmptbl_07, .-_nds32_jmptbl_07
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid02_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.02, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_02_4b
.type _nds32_vector_02_4b, @function
_nds32_vector_02_4b:
1:
j 1b
.size _nds32_vector_02_4b, .-_nds32_vector_02_4b
|
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