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4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid33_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.33, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_33_4b
.type _nds32_vector_33_4b, @function
_nds32_vector_33_4b:
1:
j 1b
.size _nds32_vector_33_4b, .-_nds32_vector_33_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid49_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.49, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_49_4b
.type _nds32_vector_49_4b, @function
_nds32_vector_49_4b:
1:
j 1b
.size _nds32_vector_49_4b, .-_nds32_vector_49_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid32_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.32, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_32_4b
.type _nds32_vector_32_4b, @function
_nds32_vector_32_4b:
1:
j 1b
.size _nds32_vector_32_4b, .-_nds32_vector_32_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid03.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.03, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_03
.type _nds32_vector_03, @function
_nds32_vector_03:
1:
j 1b
.size _nds32_vector_03, .-_nds32_vector_03
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid29.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.29, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_29
.type _nds32_vector_29, @function
_nds32_vector_29:
1:
j 1b
.size _nds32_vector_29, .-_nds32_vector_29
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid04.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.04, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_04
.type _nds32_vector_04, @function
_nds32_vector_04:
1:
j 1b
.size _nds32_vector_04, .-_nds32_vector_04
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid09.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.09, "a"
.align 2
.weak _nds32_jmptbl_09
.type _nds32_jmptbl_09, @object
_nds32_jmptbl_09:
.word 0
.size _nds32_jmptbl_09, .-_nds32_jmptbl_09
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid45.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.45, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_45
.type _nds32_vector_45, @function
_nds32_vector_45:
1:
j 1b
.size _nds32_vector_45, .-_nds32_vector_45
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid30.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.30, "a"
.align 2
.weak _nds32_jmptbl_30
.type _nds32_jmptbl_30, @object
_nds32_jmptbl_30:
.word 0
.size _nds32_jmptbl_30, .-_nds32_jmptbl_30
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid26.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.26, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_26
.type _nds32_vector_26, @function
_nds32_vector_26:
1:
j 1b
.size _nds32_vector_26, .-_nds32_vector_26
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid34.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.34, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_34
.type _nds32_vector_34, @function
_nds32_vector_34:
1:
j 1b
.size _nds32_vector_34, .-_nds32_vector_34
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid42.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.42, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_42
.type _nds32_vector_42, @function
_nds32_vector_42:
1:
j 1b
.size _nds32_vector_42, .-_nds32_vector_42
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid54.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.54, "a"
.align 2
.weak _nds32_jmptbl_54
.type _nds32_jmptbl_54, @object
_nds32_jmptbl_54:
.word 0
.size _nds32_jmptbl_54, .-_nds32_jmptbl_54
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid49.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.49, "a"
.align 2
.weak _nds32_jmptbl_49
.type _nds32_jmptbl_49, @object
_nds32_jmptbl_49:
.word 0
.size _nds32_jmptbl_49, .-_nds32_jmptbl_49
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid51_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.51, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_51_4b
.type _nds32_vector_51_4b, @function
_nds32_vector_51_4b:
1:
j 1b
.size _nds32_vector_51_4b, .-_nds32_vector_51_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid64.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.64, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_64
.type _nds32_vector_64, @function
_nds32_vector_64:
1:
j 1b
.size _nds32_vector_64, .-_nds32_vector_64
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid12_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.12, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_12_4b
.type _nds32_vector_12_4b, @function
_nds32_vector_12_4b:
1:
j 1b
.size _nds32_vector_12_4b, .-_nds32_vector_12_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid13_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.13, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_13_4b
.type _nds32_vector_13_4b, @function
_nds32_vector_13_4b:
1:
j 1b
.size _nds32_vector_13_4b, .-_nds32_vector_13_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid42.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.42, "a"
.align 2
.weak _nds32_jmptbl_42
.type _nds32_jmptbl_42, @object
_nds32_jmptbl_42:
.word 0
.size _nds32_jmptbl_42, .-_nds32_jmptbl_42
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid31.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.31, "a"
.align 2
.weak _nds32_jmptbl_31
.type _nds32_jmptbl_31, @object
_nds32_jmptbl_31:
.word 0
.size _nds32_jmptbl_31, .-_nds32_jmptbl_31
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid28.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.28, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_28
.type _nds32_vector_28, @function
_nds32_vector_28:
1:
j 1b
.size _nds32_vector_28, .-_nds32_vector_28
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid16.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.16, "a"
.align 2
.weak _nds32_jmptbl_16
.type _nds32_jmptbl_16, @object
_nds32_jmptbl_16:
.word 0
.size _nds32_jmptbl_16, .-_nds32_jmptbl_16
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid50.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.50, "a"
.align 2
.weak _nds32_jmptbl_50
.type _nds32_jmptbl_50, @object
_nds32_jmptbl_50:
.word 0
.size _nds32_jmptbl_50, .-_nds32_jmptbl_50
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid08.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.08, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_08
.type _nds32_vector_08, @function
_nds32_vector_08:
1:
j 1b
.size _nds32_vector_08, .-_nds32_vector_08
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid41.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.41, "a"
.align 2
.weak _nds32_jmptbl_41
.type _nds32_jmptbl_41, @object
_nds32_jmptbl_41:
.word 0
.size _nds32_jmptbl_41, .-_nds32_jmptbl_41
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid69.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.69, "a"
.align 2
.weak _nds32_jmptbl_69
.type _nds32_jmptbl_69, @object
_nds32_jmptbl_69:
.word 0
.size _nds32_jmptbl_69, .-_nds32_jmptbl_69
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid71.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.71, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_71
.type _nds32_vector_71, @function
_nds32_vector_71:
1:
j 1b
.size _nds32_vector_71, .-_nds32_vector_71
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid46_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.46, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_46_4b
.type _nds32_vector_46_4b, @function
_nds32_vector_46_4b:
1:
j 1b
.size _nds32_vector_46_4b, .-_nds32_vector_46_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid29.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.29, "a"
.align 2
.weak _nds32_jmptbl_29
.type _nds32_jmptbl_29, @object
_nds32_jmptbl_29:
.word 0
.size _nds32_jmptbl_29, .-_nds32_jmptbl_29
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid27_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.27, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_27_4b
.type _nds32_vector_27_4b, @function
_nds32_vector_27_4b:
1:
j 1b
.size _nds32_vector_27_4b, .-_nds32_vector_27_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid50.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.50, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_50
.type _nds32_vector_50, @function
_nds32_vector_50:
1:
j 1b
.size _nds32_vector_50, .-_nds32_vector_50
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid34_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.34, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_34_4b
.type _nds32_vector_34_4b, @function
_nds32_vector_34_4b:
1:
j 1b
.size _nds32_vector_34_4b, .-_nds32_vector_34_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid39.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.39, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_39
.type _nds32_vector_39, @function
_nds32_vector_39:
1:
j 1b
.size _nds32_vector_39, .-_nds32_vector_39
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid02.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.02, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_02
.type _nds32_vector_02, @function
_nds32_vector_02:
1:
j 1b
.size _nds32_vector_02, .-_nds32_vector_02
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid67_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.67, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_67_4b
.type _nds32_vector_67_4b, @function
_nds32_vector_67_4b:
1:
j 1b
.size _nds32_vector_67_4b, .-_nds32_vector_67_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid28_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.28, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_28_4b
.type _nds32_vector_28_4b, @function
_nds32_vector_28_4b:
1:
j 1b
.size _nds32_vector_28_4b, .-_nds32_vector_28_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid19.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.19, "a"
.align 2
.weak _nds32_jmptbl_19
.type _nds32_jmptbl_19, @object
_nds32_jmptbl_19:
.word 0
.size _nds32_jmptbl_19, .-_nds32_jmptbl_19
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid09.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.09, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_09
.type _nds32_vector_09, @function
_nds32_vector_09:
1:
j 1b
.size _nds32_vector_09, .-_nds32_vector_09
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid63.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.63, "a"
.align 2
.weak _nds32_jmptbl_63
.type _nds32_jmptbl_63, @object
_nds32_jmptbl_63:
.word 0
.size _nds32_jmptbl_63, .-_nds32_jmptbl_63
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid22_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.22, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_22_4b
.type _nds32_vector_22_4b, @function
_nds32_vector_22_4b:
1:
j 1b
.size _nds32_vector_22_4b, .-_nds32_vector_22_4b
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid23.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.23, "a"
.align 2
.weak _nds32_jmptbl_23
.type _nds32_jmptbl_23, @object
_nds32_jmptbl_23:
.word 0
.size _nds32_jmptbl_23, .-_nds32_jmptbl_23
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid65_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.65, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_65_4b
.type _nds32_vector_65_4b, @function
_nds32_vector_65_4b:
1:
j 1b
.size _nds32_vector_65_4b, .-_nds32_vector_65_4b
|
4ms/metamodule-plugin-sdk
| 1,251
|
plugin-libc/libgcc/config/nds32/isr-library/nmih.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_nmih, "a"
.align 2
.weak _nds32_nmih
.type _nds32_nmih, @object
_nds32_nmih:
.word 0
.size _nds32_nmih, .-_nds32_nmih
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid03_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.03, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_03_4b
.type _nds32_vector_03_4b, @function
_nds32_vector_03_4b:
1:
j 1b
.size _nds32_vector_03_4b, .-_nds32_vector_03_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid19_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.19, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_19_4b
.type _nds32_vector_19_4b, @function
_nds32_vector_19_4b:
1:
j 1b
.size _nds32_vector_19_4b, .-_nds32_vector_19_4b
|
4ms/metamodule-plugin-sdk
| 11,344
|
plugin-libc/libgcc/config/arc/ieee-754/divdf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
to calculate a := b/x as b*y, with y := 1/x:
- x is in the range [1..2)
- calculate 15..18 bit inverse y0 using a table of approximating polynoms.
Precision is higher for polynoms used to evaluate input with larger
value.
- Do one newton-raphson iteration step to double the precision,
then multiply this with the divisor
-> more time to decide if dividend is subnormal
- the worst error propagation is on the side of the value range
with the least initial defect, thus giving us about 30 bits precision.
The truncation error for the either is less than 1 + x/2 ulp.
A 31 bit inverse can be simply calculated by using x with implicit 1
and chaining the multiplies. For a 32 bit inverse, we multiply y0^2
with the bare fraction part of x, then add in y0^2 for the implicit
1 of x.
- If calculating a 31 bit inverse, the systematic error is less than
-1 ulp; likewise, for 32 bit, it is less than -2 ulp.
- If we calculate our seed with a 32 bit fraction, we can archive a
tentative result strictly better than -2 / +2.5 (1) ulp/128, i.e. we
only need to take the step to calculate the 2nd stage rest and
rounding adjust 1/32th of the time. However, if we use a 20 bit
fraction for the seed, the negative error can exceed -2 ulp/128, (2)
thus for a simple add / tst check, we need to do the 2nd stage
rest calculation/ rounding adjust 1/16th of the time.
(1): The inexactness of the 32 bit inverse contributes an error in the
range of (-1 .. +(1+x/2) ) ulp/128. Leaving out the low word of the
rest contributes an error < +1/x ulp/128 . In the interval [1,2),
x/2 + 1/x <= 1.5 .
(2): Unless proven otherwise. I have not actually looked for an
example where -2 ulp/128 is exceeded, and my calculations indicate
that the excess, if existent, is less than -1/512 ulp.
*/
#include "arc-ieee-754.h"
/* N.B. fp-bit.c does double rounding on denormal numbers. */
#if 0 /* DEBUG */
.global __divdf3
FUNC(__divdf3)
.balign 4
__divdf3:
push_s blink
push_s r2
push_s r3
push_s r0
bl.d __divdf3_c
push_s r1
ld_s r2,[sp,12]
ld_s r3,[sp,8]
st_s r0,[sp,12]
st_s r1,[sp,8]
pop_s r1
bl.d __divdf3_asm
pop_s r0
pop_s r3
pop_s r2
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
and r12,DBL0H,DBL1H
bic.f 0,0x7ff80000,r12 ; both NaN -> OK
jeq_s [blink]
bl abort
ENDFUNC(__divdf3)
#define __divdf3 __divdf3_asm
#endif /* DEBUG */
FUNC(__divdf3)
__divdf3_support: /* This label makes debugger output saner. */
.balign 4
.Ldenorm_dbl1:
brge r6, \
0x43500000,.Linf_NaN ; large number / denorm -> Inf
bmsk.f r12,DBL1H,19
mov.eq r12,DBL1L
mov.eq DBL1L,0
sub.eq r7,r7,32
norm.f r11,r12 ; flag for x/0 -> Inf check
beq_s .Linf_NaN
mov.mi r11,0
add.pl r11,r11,1
add_s r12,r12,r12
asl r8,r12,r11
rsub r12,r11,31
lsr r12,DBL1L,r12
tst_s DBL1H,DBL1H
or r8,r8,r12
lsr r4,r8,26
lsr DBL1H,r8,12
ld.as r4,[r10,r4]
bxor.mi DBL1H,DBL1H,31
sub r11,r11,11
asl DBL1L,DBL1L,r11
sub r11,r11,1
MPYHU r5,r4,r8
sub r7,r7,r11
asl r4,r4,12
b.d .Lpast_denorm_dbl1
asl r7,r7,20
; wb stall
.balign 4
.Ldenorm_dbl0:
bmsk.f r12,DBL0H,19
; wb stall
mov.eq r12,DBL0L
sub.eq r6,r6,32
norm.f r11,r12 ; flag for 0/x -> 0 check
brge r7, \
0x43500000, .Lret0_NaN ; denorm/large number -> 0
beq_s .Lret0_NaN
mov.mi r11,0
add.pl r11,r11,1
asl r12,r12,r11
sub r6,r6,r11
add.f 0,r6,31
lsr r10,DBL0L,r6
mov.mi r10,0
add r6,r6,11+32
neg.f r11,r6
asl DBL0L,DBL0L,r11
mov.pl DBL0L,0
sub r6,r6,32-1
b.d .Lpast_denorm_dbl0
asl r6,r6,20
.Linf_NaN:
tst_s DBL0L,DBL0L ; 0/0 -> NaN
xor_s DBL1H,DBL1H,DBL0H
bclr.eq.f DBL0H,DBL0H,31
bmsk DBL0H,DBL1H,30
xor_s DBL0H,DBL0H,DBL1H
sub.eq DBL0H,DBL0H,1
mov_s DBL0L,0
j_s.d [blink]
or DBL0H,DBL0H,r9
.balign 4
.Lret0_NaN:
xor_s DBL1H,DBL1H,DBL0H
cmp_s r12,r9
mov_s DBL0L,0
bmsk DBL0H,DBL1H,30
xor_s DBL0H,DBL0H,DBL1H
j_s.d [blink]
sub.hi DBL0H,DBL0H,1
.Linf_nan_dbl1: ; Inf/Inf -> NaN x/Inf-> 0 x/NaN -> NaN
not_s DBL0L,DBL1H
cmp r6,r9
sub_s.ne DBL0L,DBL0L,DBL0L
tst_s DBL0H,DBL0H
add_s DBL0H,DBL1H,DBL0L
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
.Linf_nan_dbl0:
tst_s DBL1H,DBL1H
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
.balign 4
.global __divdf3
/* N.B. the spacing between divtab and the add3 to get its address must
be a multiple of 8. */
__divdf3:
asl r8,DBL1H,12
lsr r12,DBL1L,20
lsr r4,r8,26
#if defined (__ARCHS__) || defined (__ARCEM__)
add3 r10,pcl,60 ; (.Ldivtab-.) >> 3
#else
add3 r10,pcl,59 ; (.Ldivtab-.) >> 3
#endif
ld.as r4,[r10,r4]
#if defined (__ARCHS__) || defined (__ARCEM__)
ld.as r9,[pcl,182]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000
#else
ld.as r9,[pcl,180]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000
#endif
or r8,r8,r12
MPYHU r5,r4,r8
and.f r7,DBL1H,r9
asl r4,r4,12 ; having the asl here is a concession to the XMAC pipeline.
beq.d .Ldenorm_dbl1
and r6,DBL0H,r9
.Lpast_denorm_dbl1: ; wb stall
sub r4,r4,r5
MPYHU r5,r4,r4
breq.d r6,0,.Ldenorm_dbl0
lsr r8,r8,1
asl r12,DBL0H,11
lsr r10,DBL0L,21
.Lpast_denorm_dbl0: ; wb stall
bset r8,r8,31
MPYHU r11,r5,r8
add_s r12,r12,r10
bset r5,r12,31
cmp r5,r8
cmp.eq DBL0L,DBL1L
; wb stall
lsr.cc r5,r5,1
sub r4,r4,r11 ; u1.31 inverse, about 30 bit
MPYHU r11,r5,r4 ; result fraction highpart
breq r7,r9,.Linf_nan_dbl1
lsr r8,r8,2 ; u3.29
add r5,r6, /* wait for immediate / XMAC wb stall */ \
0x3fe00000
; wb stall (not for XMAC)
breq r6,r9,.Linf_nan_dbl0
mpyu r12,r11,r8 ; u-28.31
asl_s DBL1L,DBL1L,9 ; u-29.23:9
sbc r6,r5,r7
; resource conflict (not for XMAC)
MPYHU r5,r11,DBL1L ; u-28.23:9
add.cs DBL0L,DBL0L,DBL0L
asl_s DBL0L,DBL0L,6 ; u-26.25:7
asl r10,r11,23
sub_l DBL0L,DBL0L,r12
; wb stall (before 'and' for XMAC)
lsr r7,r11,9
sub r5,DBL0L,r5 ; rest msw ; u-26.31:0
MPYH r12,r5,r4 ; result fraction lowpart
xor.f 0,DBL0H,DBL1H
and DBL0H,r6,r9
add_s DBL0H,DBL0H,r7 ; (XMAC wb stall)
bxor.mi DBL0H,DBL0H,31
brhs r6, /* wb stall / wait for immediate */ \
0x7fe00000,.Linf_denorm
add.f r12,r12,0x11
asr r9,r12,5
sub.mi DBL0H,DBL0H,1
add.f DBL0L,r9,r10
tst r12,0x1c
jne.d [blink]
add.cs DBL0H,DBL0H,1
/* work out exact rounding if we fall through here. */
/* We know that the exact result cannot be represented in double
precision. Find the mid-point between the two nearest
representable values, multiply with the divisor, and check if
the result is larger than the dividend. Since we want to know
only the sign bit, it is sufficient to calculate only the
highpart of the lower 64 bits. */
sub.f DBL0L,DBL0L,1
asl r12,r9,2 ; u-22.30:2
mpyu r10,r11,DBL1L ; rest before considering r12 in r5 : -r10
sub.cs DBL0H,DBL0H,1
sub.f r12,r12,2
; resource conflict (not for XMAC)
MPYHU r7,r12,DBL1L ; u-51.32
asl r5,r5,25 ; s-51.7:25
lsr r10,r10,7 ; u-51.30:2
; resource conflict (not for XMAC)
; resource conflict (not for XMAC)
mpyu r9,r12,r8 ; u-51.31:1
sub r5,r5,r10
add.mi r5,r5,DBL1L ; signed multiply adjust for r12*DBL1L
bset r7,r7,0 ; make sure that the result is not zero, and that
; wb stall (one earlier for XMAC)
sub r5,r5,r7 ; a highpart zero appears negative
sub.f r5,r5,r9 ; rest msw
add.pl.f DBL0L,DBL0L,1
j_s.d [blink]
add.eq DBL0H,DBL0H,1
.balign 4
.Linf_denorm:
brlo r6,0xc0000000,.Linf
.Ldenorm:
asr r6,r6,20
neg r9,r6
mov_s DBL0H,0
brhs.d r9,54,.Lret0
bxor.mi DBL0H,DBL0H,31
add_l r12,r12,1
and r12,r12,-4
rsub r7,r6,5
asr r10,r12,28
bmsk r4,r12,27
#if defined (__ARCHS__) || defined (__ARCEM__)
min r7, r7, 31
asr DBL0L, r4, r7
#else
asrs DBL0L,r4,r7
#endif
add DBL1H,r11,r10
#if defined (__ARCHS__) || defined (__ARCEM__)
abs.f r10, r4
sub.mi r10, r10, 1
#endif
add.f r7,r6,32-5
#ifdef __ARC700__
abss r10,r4
#endif
asl r4,r4,r7
mov.mi r4,r10
add.f r10,r6,23
rsub r7,r6,9
lsr r7,DBL1H,r7
asl r10,DBL1H,r10
or.pnz DBL0H,DBL0H,r7
or.mi r4,r4,r10
mov.mi r10,r7
add.f DBL0L,r10,DBL0L
add.cs.f DBL0H,DBL0H,1 ; carry clear after this point
bxor.f 0,r4,31
add.pnz.f DBL0L,DBL0L,1
add.cs.f DBL0H,DBL0H,1
jne_l [blink]
/* Calculation so far was not conclusive; calculate further rest. */
mpyu r11,r11,DBL1L ; rest before considering r12 in r5 : -r11
asr.f r12,r12,3
asl r5,r5,25 ; s-51.7:25
; resource conflict (not for XMAC)
mpyu DBL1H,r12,r8 ; u-51.31:1
and r9,DBL0L,1 ; tie-breaker: round to even
lsr r11,r11,7 ; u-51.30:2
; resource conflict (not for XMAC)
MPYHU r8,r12,DBL1L ; u-51.32
sub.mi r11,r11,DBL1L ; signed multiply adjust for r12*DBL1L
add_s DBL1H,DBL1H,r11
; resource conflict (not for XMAC)
; resource conflict (not for XMAC)
mpyu r12,r12,DBL1L ; u-83.30:2
sub DBL1H,DBL1H,r5 ; -rest msw
add_s DBL1H,DBL1H,r8 ; -rest msw
add.f 0,DBL1H,DBL1H ; can't ror.f by 32 :-(
; wb stall (XMAC: Before add.f)
tst_s DBL1H,DBL1H
cmp.eq r12,r9
add.cs.f DBL0L,DBL0L,1
j_s.d [blink]
add.cs DBL0H,DBL0H,1
.Lret0:
/* return +- 0 */
j_s.d [blink]
mov_s DBL0L,0
.Linf:
mov_s DBL0H,r9
mov_s DBL0L,0
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
.balign 4
.Ldivtab:
.long 0xfc0fffe1
.long 0xf46ffdfb
.long 0xed1ffa54
.long 0xe61ff515
.long 0xdf7fee75
.long 0xd91fe680
.long 0xd2ffdd52
.long 0xcd1fd30c
.long 0xc77fc7cd
.long 0xc21fbbb6
.long 0xbcefaec0
.long 0xb7efa100
.long 0xb32f92bf
.long 0xae8f83b7
.long 0xaa2f7467
.long 0xa5ef6479
.long 0xa1cf53fa
.long 0x9ddf433e
.long 0x9a0f3216
.long 0x965f2091
.long 0x92df0f11
.long 0x8f6efd05
.long 0x8c1eeacc
.long 0x88eed876
.long 0x85dec615
.long 0x82eeb3b9
.long 0x800ea10b
.long 0x7d3e8e0f
.long 0x7a8e7b3f
.long 0x77ee6836
.long 0x756e5576
.long 0x72fe4293
.long 0x709e2f93
.long 0x6e4e1c7f
.long 0x6c0e095e
.long 0x69edf6c5
.long 0x67cde3a5
.long 0x65cdd125
.long 0x63cdbe25
.long 0x61ddab3f
.long 0x600d991f
.long 0x5e3d868c
.long 0x5c6d7384
.long 0x5abd615f
.long 0x590d4ecd
.long 0x576d3c83
.long 0x55dd2a89
.long 0x545d18e9
.long 0x52dd06e9
.long 0x516cf54e
.long 0x4ffce356
.long 0x4e9cd1ce
.long 0x4d3cbfec
.long 0x4becae86
.long 0x4aac9da4
.long 0x496c8c73
.long 0x483c7bd3
.long 0x470c6ae8
.long 0x45dc59af
.long 0x44bc4915
.long 0x43ac3924
.long 0x428c27fb
.long 0x418c187a
.long 0x407c07bd
.L7ff00000:
.long 0x7ff00000
ENDFUNC(__divdf3)
|
4ms/metamodule-plugin-sdk
| 2,584
|
plugin-libc/libgcc/config/arc/ieee-754/gtdf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: DBL0, DBL1
output: c,z flags to be used for 'hi' condition
clobber: r12, flags */
/* For NaNs, bit 19.. bit 30 of the high word must be set. */
#if 0 /* DEBUG */
.global __gtdf2
.balign 4
FUNC(__gtdf2)
__gtdf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __gtdf2_c` push_s r0
mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __gtdf2_asm` ld.ab r10,[sp,4]
pop_s blink
brgt.d r11,0,0f
ld.ab r11,[sp,4]
jls [blink]
bl abort
0: jhi [blink]
bl abort
ENDFUNC(__gtdf2)
#define __gtdf2 __gtdf2_asm
#endif /* DEBUG */
.global __gtdf2
.balign 4
HIDDEN_FUNC(__gtdf2)
__gtdf2:
or.f r12,DBL0H,DBL1H
bmi.d .Lneg
bmsk_s r12,r12,20
add1.f 0,r12,DBL0H ; clear z; set c iff NaN
add1.cc.f r12,r12,DBL1H ; clear z; set c iff NaN
; don't care: z may or may not be cleared if there is no NaN event
cmp.cc DBL0H,DBL1H
j_s.d [blink]
cmp.eq DBL0L,DBL1L
.balign 4
.Lneg: breq.d DBL0H,0,.L0
add1.f 0,r12,DBL1H
add1.cc.f r12,r12,DBL0H
cmp.cc DBL1H,DBL0H
j_s.d [blink]
cmp.eq DBL1L,DBL0L
.balign 4
.L0:
bxor.f 0,DBL1H,31
beq_s .Lcheck_0
cmp.cc DBL1H,DBL0H
j_s.d [blink]
cmp.eq DBL1L,DBL0L
.balign 4
.Lcheck_0:
; high words suggest DBL0 may be +0, DBL1 -0; check low words.
j_s.d [blink]
or.f 0,DBL0L,DBL1L
ENDFUNC(__gtdf2)
|
4ms/metamodule-plugin-sdk
| 3,738
|
plugin-libc/libgcc/config/arc/ieee-754/mulsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* XMAC schedule: directly back-to-back multiplies stall; the third
instruction after a multiply stalls unless it is also a multiply. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __mulsf3
FUNC(__mulsf3)
.balign 4
__mulsf3:
push_s blink
push_s r1
bl.d __mulsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __mulsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
and r12,r0,r1
bic.f 0,0x7f800000,r12
bne 0f
bmsk.f 0,r0,22
bmsk.ne.f r1,r1,22
jne_s [blink] ; both NaN -> OK
0: bl abort
ENDFUNC(__mulsf3)
#define __mulsf3 __mulsf3_asm
#endif /* DEBUG */
.balign 4
.global __mulsf3
FUNC(__mulsf3)
__mulsf3:
ld.as r9,[pcl,79]; [pcl,((.L7f800000-.+2)/4)]
bmsk r4,r1,22
bset r2,r0,23
asl_s r2,r2,8
bset r3,r4,23
MPYHU r6,r2,r3
and r11,r0,r9
breq r11,0,.Ldenorm_dbl0
mpyu r7,r2,r3
breq r11,r9,.Linf_nan_dbl0
and r12,r1,r9
asl.f 0,r6,8
breq r12,0,.Ldenorm_dbl1
.Lpast_denorm:
xor_s r0,r0,r1
.Lpast_denorm_dbl1:
add.pl r6,r6,r6
bclr.pl r6,r6,23
add.pl.f r7,r7,r7
ld.as r4,[pcl,64]; [pcl,((.L7fffffff-.+2)/4)]
add.cs r6,r6,1
lsr.f 0,r6,1
breq r12,r9,.Linf_nan_dbl1
add_s r12,r12,r11
adc.f 0,r7,r4
add_s r12,r12, \
-0x3f800000
adc.f r8,r6,r12
bic r0,r0,r4
tst.pl r8,r9
min r3,r8,r9
jpnz.d [blink]
add.pnz r0,r0,r3
; infinity or denormal number
add.ne.f r3,r3,r3
bpnz .Linfinity
asr_s r3,r3,23+1
bset r6,r6,23
sub_s r3,r3,1
neg_s r2,r3
brhi r2,24,.Lret_r0 ; right shift shift > 24 -> return +-0
lsr r2,r6,r2
asl r9,r6,r3
lsr.f 0,r2,1
tst r7,r7
add_s r0,r0,r2
bset.ne r9,r9,0
adc.f 0,r9,r4
j_s.d [blink]
add.cs r0,r0,1
.Linfinity:
j_s.d [blink]
add_s r0,r0,r9
.Lret_r0: j_s [blink]
.balign 4
.Linf_nan_dbl0:
sub_s r2,r1,1 ; inf/nan * 0 -> nan; inf * nan -> nan (use |r2| >= inf)
bic.f 0,r9,r2
xor_s r0,r0,r1
bclr_s r1,r1,31
xor_s r0,r0,r1
jne_s [blink]
.Lretnan:
j_s.d [blink]
mov r0,-1
.Ldenorm_dbl0_inf_nan_dbl1:
bmsk.f 0,r0,30
beq_s .Lretnan
xor_s r0,r0,r1
.Linf_nan_dbl1:
xor_s r1,r1,r0
bclr_s r1,r1,31
j_s.d [blink]
xor_s r0,r0,r1
.balign 4
.Ldenorm_dbl0:
bclr_s r2,r2,31
norm.f r4,r2
and r12,r1,r9
add_s r2,r2,r2
asl r2,r2,r4
asl r4,r4,23
MPYHU r6,r2,r3
breq r12,r9,.Ldenorm_dbl0_inf_nan_dbl1
sub.ne.f r12,r12,r4
mpyu r7,r2,r3
bhi.d .Lpast_denorm
asl.f 0,r6,8
xor_s r0,r0,r1
bmsk r1,r0,30
j_s.d [blink]
bic_l r0,r0,r1
.balign 4
.Ldenorm_dbl1:
norm.f r3,r4
xor_s r0,r0,r1
sub_s r3,r3,7
asl r4,r4,r3
sub_s r3,r3,1
asl_s r3,r3,23
MPYHU r6,r2,r4
sub.ne.f r11,r11,r3
bmsk r8,r0,30
mpyu r7,r2,r4
bhi.d .Lpast_denorm_dbl1
asl.f 0,r6,8
j_s.d [blink]
bic r0,r0,r8
.balign 4
.L7f800000:
.long 0x7f800000
.L7fffffff:
.long 0x7fffffff
ENDFUNC(__mulsf3)
|
4ms/metamodule-plugin-sdk
| 2,621
|
plugin-libc/libgcc/config/arc/ieee-754/extendsfdf2.S
|
/* Copyright (C) 2006-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __extendsfdf2
.balign 4
FUNC(__extendsfdf2)
__extendsfdf2:
push_s blink
bl.d __extendsfdf2_c
push_s r0
ld_s r2,[sp]
st_s r1,[sp]
push_s r0
bl.d __extendsfdf2_asm
mov_s r0,r2
pop_s r2
pop_s r3
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
bl abort
ENDFUNC(__extendsfdf2)
#define __extendsfdf2 __extendsfdf2_asm
#endif /* DEBUG */
#if 0 /* ARC600 */
__extendsfdf2:
lsr r2,r0,23
tst r2,0xff
bic.ne.f r2,0xff
beq_s .Linf_nan_denorm_0
..
.Linf_nan_denorm:
bbit1 r0,30,.Linf_nan
#endif
.global __extendsfdf2
.balign 4
FUNC(__extendsfdf2)
__extendsfdf2:
add.f r1,r0,r0
norm r3,r1
#ifdef __LITTLE_ENDIAN__
lsr_s DBL0H,r1,4
brhs r3,7,.Linf_nan_denorm_0
asl_s DBL0L,r0,29
add_s DBL0H,DBL0H, \
0x38000000
#else
lsr r2,r1,4
brhs r3,7,.Linf_nan_denorm_0
asl_s DBL0L,r1,28
add DBL0H,r2, \
0x38000000
#endif
j_s.d [blink]
bxor.cs DBL0H,DBL0H,31
.balign 4
.Linf_nan_denorm_0:
#ifdef __LITTLE_ENDIAN__
mov_s DBL0H,r0
jeq.d [blink]
mov.eq DBL0L,0
#else
jeq_s [blink]
#endif
bmi .Linf_nan
asl_s r0,r0,r3
rsub r3,r3,0x380+6
#ifdef __LITTLE_ENDIAN__
asl_s r3,r3,20
lsr DBL0H,r0,9
asl_s DBL0L,r0,23
add_s DBL0H,DBL0H,r3
j_s.d [blink]
bxor.cs DBL0H,DBL0H,31
#else
asl DBL0L,r0,23
lsr_s DBL0H,r0,9
asl_s r3,r3,20
bxor.cs DBL0H,DBL0H,31
j_s.d [blink]
add_l DBL0H,DBL0H,r3
#endif
.Linf_nan:
#ifdef __LITTLE_ENDIAN__
lsr DBL0H,r0,3
or_s DBL0H,DBL0H,r0
j_s.d [blink]
mov_l DBL0L,0
#else
lsr r3,r0,3
mov_s DBL0L,0
j_s.d [blink]
or_l DBL0H,r0,r3
#endif
ENDFUNC(__extendsfdf2)
|
4ms/metamodule-plugin-sdk
| 1,877
|
plugin-libc/libgcc/config/arc/ieee-754/floatsidf.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __floatsidf
.balign 4
FUNC(__floatsidf)
__floatsidf:
push_s blink
bl.d __floatsidf_c
push_s r0
ld_s r2,[sp]
st_s r1,[sp]
push_s r0
bl.d __floatsidf_asm
mov_s r0,r2
pop_s r2
pop_s r3
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
bl abort
ENDFUNC(__floatsidf)
#define __floatsidf __floatsidf_asm
#endif /* DEBUG */
.global __floatsidf
.balign 4
FUNC(__floatsidf)
__floatsidf:
abs.f r1,r0
jeq_s [blink]
lsr r2,r1
mov r12,-0x41d ; -(0x3ff+31-1)
norm r2,r2
bclr.cs r12,r12,11
rsub.f r3,r2,11
add_s r12,r2,r12
add_s r2,r2,21
#ifdef __LITTLE_ENDIAN__
asl DBL0L,r1,r2
lsr_s DBL0H,r1,r3
#else
lsr DBL0H,r1,r3
asl_s DBL0L,r1,r2
#endif
asl_s r12,r12,20
mov.lo DBL0H,DBL0L
sub_s DBL0H,DBL0H,r12
j_s.d [blink]
mov.ls DBL0L,0
ENDFUNC(__floatsidf)
|
4ms/metamodule-plugin-sdk
| 5,611
|
plugin-libc/libgcc/config/arc/ieee-754/muldf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* XMAC schedule: directly back-to-back multiplies stall; the third
instruction after a multiply stalls unless it is also a multiply. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __muldf3
.balign 4
__muldf3:
push_s blink
push_s r2
push_s r3
push_s r0
bl.d __muldf3_c
push_s r1
ld_s r2,[sp,12]
ld_s r3,[sp,8]
st_s r0,[sp,12]
st_s r1,[sp,8]
pop_s r1
bl.d __muldf3_asm
pop_s r0
pop_s r3
pop_s r2
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
b abort
#define __muldf3 __muldf3_asm
#endif /* DEBUG */
/* N.B. This is optimized for ARC700.
ARC600 has very different scheduling / instruction selection criteria. */
/* For the standard multiplier, instead of mpyu rx,DBL0L,DBL1L; tst rx,rx ,
we can do:
sub rx,DBL0L,1; bic rx,DBL0L,rx; lsr rx,rx; norm rx,rx; asl.f 0,DBL1L,rx */
__muldf3_support: /* This label makes debugger output saner. */
/* If one number is denormal, subtract some from the exponent of the other
one (if the other exponent is too small, return 0), and normalize the
denormal. Then re-run the computation. */
.balign 4
FUNC(__muldf3)
.Ldenorm_dbl0:
mov_s r12,DBL0L
mov_s DBL0L,DBL1L
mov_s DBL1L,r12
mov_s r12,DBL0H
mov_s DBL0H,DBL1H
mov_s DBL1H,r12
and r11,DBL0H,r9
.Ldenorm_dbl1:
brhs r11,r9,.Linf_nan
brhs 0x3ca00001,r11,.Lret0
sub_s DBL0H,DBL0H,DBL1H
bmsk_s DBL1H,DBL1H,30
add_s DBL0H,DBL0H,DBL1H
breq_s DBL1H,0,.Ldenorm_2
norm r12,DBL1H
sub_s r12,r12,10
asl r5,r12,20
asl_s DBL1H,DBL1H,r12
sub DBL0H,DBL0H,r5
neg r5,r12
lsr r6,DBL1L,r5
asl_s DBL1L,DBL1L,r12
b.d __muldf3
add_s DBL1H,DBL1H,r6
.balign 4
.Linf_nan:
bclr r12,DBL1H,31
xor_s DBL1H,DBL1H,DBL0H
bclr_s DBL0H,DBL0H,31
max r8,DBL0H,r12 ; either NaN -> NaN ; otherwise inf
or.f 0,DBL0H,DBL0L
mov_s DBL0L,0
or.ne.f DBL1L,DBL1L,r12
not_s DBL0H,DBL0L ; inf * 0 -> NaN
mov.ne DBL0H,r8
tst_s DBL1H,DBL1H
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
.Lret0: xor_s DBL0H,DBL0H,DBL1H
bclr DBL1H,DBL0H,31
xor_s DBL0H,DBL0H,DBL1H
j_s.d [blink]
mov_l DBL0L,0
.balign 4
.Ldenorm_2:
breq_s DBL1L,0,.Lret0 ; 0 input -> 0 output
norm.f r12,DBL1L
mov.mi r12,21
add.pl r12,r12,22
neg r11,r12
asl_s r12,r12,20
lsr.f DBL1H,DBL1L,r11
ror DBL1L,DBL1L,r11
sub_s DBL0H,DBL0H,r12
mov.eq DBL1H,DBL1L
sub_s DBL1L,DBL1L,DBL1H
/* Fall through. */
.global __muldf3
.balign 4
__muldf3:
ld.as r9,[pcl,0x4b] ; ((.L7ff00000-.+2)/4)]
MPYHU r4,DBL0L,DBL1L
bmsk r6,DBL0H,19
bset r6,r6,20
mpyu r7,r6,DBL1L
and r11,DBL0H,r9
breq r11,0,.Ldenorm_dbl0
MPYHU r8,r6,DBL1L
bmsk r10,DBL1H,19
bset r10,r10,20
MPYHU r5,r10,DBL0L
add.f r4,r4,r7
and r12,DBL1H,r9
MPYHU r7,r6,r10
breq r12,0,.Ldenorm_dbl1
adc.f r5,r5,r8
mpyu r8,r10,DBL0L
breq r11,r9,.Linf_nan
breq r12,r9,.Linf_nan
mpyu r6,r6,r10
add.cs r7,r7,1
add.f r4,r4,r8
mpyu r10,DBL1L,DBL0L
bclr r8,r9,30 ; 0x3ff00000
adc.f r5,r5,r6
; XMAC write-back stall / std. mult stall is one cycle later
bclr r6,r9,20 ; 0x7fe00000
add.cs r7,r7,1 ; fraction product in r7:r5:r4
tst r10,r10
bset.ne r4,r4,0 ; put least significant word into sticky bit
lsr.f r10,r7,9
add_l r12,r12,r11 ; add exponents
rsub.eq r8,r8,r9 ; 0x40000000
sub r12,r12,r8 ; subtract bias + implicit 1
brhs.d r12,r6,.Linf_denorm
rsub r10,r10,12
.Lshift_frac:
neg r8,r10
asl r6,r4,r10
lsr DBL0L,r4,r8
add.f 0,r6,r6
btst.eq DBL0L,0
cmp.eq r4,r4 ; round to nearest / round to even
asl r4,r5,r10
lsr r5,r5,r8
adc.f DBL0L,DBL0L,r4
xor.f 0,DBL0H,DBL1H
asl r7,r7,r10
add_s r12,r12,r5
adc DBL0H,r12,r7
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
/* We have checked for infinity / NaN input before, and transformed
denormalized inputs into normalized inputs. Thus, the worst case
exponent overflows are:
1 + 1 - 0x400 == 0xc02 : maximum underflow
0x7fe + 0x7fe - 0x3ff == 0xbfd ; maximum overflow
N.B. 0x7e and 0x7f are also values for overflow.
If (r12 <= -54), we have an underflow to zero. */
.balign 4
.Linf_denorm:
brlo r12,0xc0000000,.Linf
asr r6,r12,20
mov_s r12,0
add.f r10,r10,r6
brgt r10,0,.Lshift_frac
beq_s .Lround_frac
add.f r10,r10,32
.Lshift32_frac:
tst r4,r4
mov r4,r5
bset.ne r4,r4,1
mov r5,r7
mov r7,0
brge r10,1,.Lshift_frac
breq r10,0,.Lround_frac
add.f r10,r10,32
brgt r10,21,.Lshift32_frac
b_s .Lret0
.Lround_frac:
add.f 0,r4,r4
btst.eq r5,0
mov_s DBL0L,r5
mov_s DBL0H,r7
adc.eq.f DBL0L,DBL0L,0
j_s.d [blink]
adc.eq DBL0H,DBL0H,0
.Linf: xor.f DBL1H,DBL1H,DBL0H
mov_s DBL0L,0
mov_s DBL0H,r9
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
ENDFUNC(__muldf3)
.balign 4
.L7ff00000:
.long 0x7ff00000
|
4ms/metamodule-plugin-sdk
| 8,061
|
plugin-libc/libgcc/config/arc/ieee-754/addsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __addsf3
FUNC(__addsf3)
.balign 4
__addsf3:
push_s blink
push_s r1
bl.d __addsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __addsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
bl abort
ENDFUNC(__addsf3)
.global __subsf3
FUNC(__subsf3)
.balign 4
__subsf3:
push_s blink
push_s r1
bl.d __subsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __subsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
bl abort
ENDFUNC(__subsf3)
#define __addsf3 __addsf3_asm
#define __subsf3 __subsf3_asm
#endif /* DEBUG */
/* N.B. This is optimized for ARC700.
ARC600 has very different scheduling / instruction selection criteria. */
/* inputs: r0, r1
output: r0
clobber: r1-r10, r12, flags */
.balign 4
.global __addsf3
.global __subsf3
FUNC(__addsf3)
FUNC(__subsf3)
.long 0x7f800000 ; exponent mask
__subsf3:
bxor_l r1,r1,31
__addsf3:
ld r9,[pcl,-8]
bmsk r4,r0,30
xor r10,r0,r1
and r6,r1,r9
sub.f r12,r4,r6
asr_s r12,r12,23
blo .Ldbl1_gt
brhs r4,r9,.Linf_nan
brne r12,0,.Lsmall_shift
brge r10,0,.Ladd_same_exp ; r12 == 0
/* After subtracting, we need to normalize; when shifting to place the
leading 1 into position for the implicit 1 and adding that to DBL0,
we increment the exponent. Thus, we have to subtract one more than
the shift count from the exponent beforehand. Iff the exponent drops thus
below zero (before adding in the fraction with the leading one), we have
generated a denormal number. Denormal handling is basicallly reducing the
shift count so that we produce a zero exponent instead; FWIW, this way
the shift count can become zero (if we started out with exponent 1).
On the plus side, we don't need to check for denorm input, the result
of subtracing these looks just the same as denormals generated during
subtraction. */
bmsk r7,r1,30
breq r4,r7,.Lret0
sub.f r5,r4,r7
lsr r12,r4,23
neg.cs r5,r5
norm r3,r5
bmsk r2,r0,22
sub_s r3,r3,6
min r12,r12,r3
bic r1,r0,r2
sub_s r3,r12,1
asl_s r12,r12,23
asl r2,r5,r3
sub_s r1,r1,r12
add_s r0,r1,r2
j_s.d [blink]
bxor.cs r0,r0,31
.balign 4
.Linf_nan:
; If both inputs are inf, but with different signs, the result is NaN.
asr r12,r10,31
or_s r1,r1,r12
j_s.d [blink]
or.eq r0,r0,r1
.balign 4
.Ladd_same_exp:
/* This is a special case because we can't test for need to shift
down by checking if bit 23 of DBL0 changes. OTOH, here we know
that we always need to shift down. */
; adding the two floating point numbers together makes the sign
; cancel out and apear as carry; the exponent is doubled, and the
; fraction also in need of shifting left by one. The two implicit
; ones of the sources make an implicit 1 of the result, again
; non-existent in a place shifted by one.
add.f r0,r0,r1
btst_s r0,1
breq r6,0,.Ldenorm_add
add.ne r0,r0,1 ; round to even.
rrc r0,r0
bmsk r1,r9,23
add r0,r0,r1 ; increment exponent
bic.f 0,r9,r0; check for overflow -> infinity.
jne_l [blink]
mov_s r0,r9
j_s.d [blink]
bset.cs r0,r0,31
.Ldenorm_add:
j_s.d [blink]
add r0,r4,r1
.Lret_dbl0:
j_s [blink]
.balign 4
.Lsmall_shift:
brhi r12,25,.Lret_dbl0
breq.d r6,0,.Ldenorm_small_shift
bmsk_s r1,r1,22
bset_s r1,r1,23
.Lfixed_denorm_small_shift:
neg r8,r12
asl r5,r1,r8
brge.d r10,0,.Ladd
lsr_l r1,r1,r12
/* subtract, abs(DBL0) > abs(DBL1) */
/* DBL0: original values
DBL1: fraction with explicit leading 1, shifted into place
r4: orig. DBL0 & 0x7fffffff
r6: orig. DBL1 & 0x7f800000
r9: 0x7f800000
r10: orig. DBL0H ^ DBL1H
r5 : guard bits */
.balign 4
.Lsub:
neg.f r12,r5
bmsk r3,r0,22
bset r5,r3,23
sbc.f r4,r5,r1
beq.d .Large_cancel_sub
bic r7,r0,r3
norm r3,r4
bmsk r6,r7,30
.Lsub_done:
sub_s r3,r3,6
breq r3,1,.Lsub_done_noshift
asl r5,r3,23
sub_l r3,r3,1
brlo r6,r5,.Ldenorm_sub
sub r0,r7,r5
neg_s r1,r3
lsr.f r2,r12,r1
asl_s r12,r12,r3
btst_s r2,0
bmsk.eq.f r12,r12,30
asl r5,r4,r3
add_s r0,r0,r2
adc.ne r0,r0,0
j_s.d [blink]
add_l r0,r0,r5
.Lret0:
j_s.d [blink]
mov_l r0,0
.balign 4
.Ldenorm_small_shift:
brne.d r12,1,.Lfixed_denorm_small_shift
sub_s r12,r12,1
brlt.d r10,0,.Lsub
mov_s r5,r12 ; zero r5, and align following code
.Ladd: ; Both bit 23 of DBL1 and bit 0 of r5 are clear.
bmsk r2,r0,22
add_s r2,r2,r1
bbit0.d r2,23,.Lno_shiftdown
add_s r0,r0,r1
bic.f 0,r9,r0; check for overflow -> infinity; eq : infinity
bmsk r1,r2,22
lsr.ne.f r2,r2,2; cc: even ; hi: might round down
lsr.ne r1,r1,1
rcmp.hi r5,1; hi : round down
bclr.hi r0,r0,0
j_l.d [blink]
sub_s r0,r0,r1
/* r4: DBL0H & 0x7fffffff
r6: DBL1H & 0x7f800000
r9: 0x7f800000
r10: sign difference
r12: shift count (negative) */
.balign 4
.Ldbl1_gt:
brhs r6,r9,.Lret_dbl1 ; inf or NaN
neg r8,r12
brhi r8,25,.Lret_dbl1
.Lsmall_shift_dbl0:
breq.d r6,0,.Ldenorm_small_shift_dbl0
bmsk_s r0,r0,22
bset_s r0,r0,23
.Lfixed_denorm_small_shift_dbl0:
asl r5,r0,r12
brge.d r10,0,.Ladd_dbl1_gt
lsr r0,r0,r8
/* subtract, abs(DBL0) < abs(DBL1) */
/* DBL0: fraction with explicit leading 1, shifted into place
DBL1: original value
r6: orig. DBL1 & 0x7f800000
r9: 0x7f800000
r5: guard bits */
.balign 4
.Lrsub:
neg.f r12,r5
bmsk r5,r1,22
bic r7,r1,r5
bset r5,r5,23
sbc.f r4,r5,r0
bne.d .Lsub_done ; note: r6 is already set up.
norm r3,r4
/* Fall through */
/* r4:r12 : unnormalized result fraction
r7: result sign and exponent */
/* When seeing large cancellation, only the topmost guard bit might be set. */
.balign 4
.Large_cancel_sub:
breq_s r12,0,.Lret0
sub r0,r7,24<<23
xor.f 0,r0,r7 ; test if exponent is negative
tst.pl r9,r0 ; test if exponent is zero
jpnz [blink] ; return if non-denormal result
bmsk r6,r7,30
lsr r3,r6,23
xor r0,r6,r7
sub_s r3,r3,24-22
j_s.d [blink]
bset r0,r0,r3
; If a denorm is produced, we have an exact result -
; no need for rounding.
.balign 4
.Ldenorm_sub:
sub r3,r6,1
lsr.f r3,r3,23
xor r0,r6,r7
neg_s r1,r3
asl.ne r4,r4,r3
lsr_s r12,r12,r1
add_s r0,r0,r4
j_s.d [blink]
add.ne r0,r0,r12
.balign 4
.Lsub_done_noshift:
add.f 0,r12,r12
btst.eq r4,0
bclr r4,r4,23
add r0,r7,r4
j_s.d [blink]
adc.ne r0,r0,0
.balign 4
.Lno_shiftdown:
add.f 0,r5,r5
btst.eq r0,0
cmp.eq r5,r5
j_s.d [blink]
add.cs r0,r0,1
.Lret_dbl1:
j_s.d [blink]
mov_l r0,r1
.balign 4
.Ldenorm_small_shift_dbl0:
sub.f r8,r8,1
bne.d .Lfixed_denorm_small_shift_dbl0
add_s r12,r12,1
brlt.d r10,0,.Lrsub
mov r5,0
.Ladd_dbl1_gt: ; both bit 23 of DBL0 and bit 0 of r5 are clear.
bmsk r2,r1,22
add_s r2,r2,r0
bbit0.d r2,23,.Lno_shiftdown_dbl1_gt
add_s r0,r1,r0
bic.f 0,r9,r0; check for overflow -> infinity; eq : infinity
bmsk r1,r2,22
lsr.ne.f r2,r2,2; cc: even ; hi: might round down
lsr.ne r1,r1,1
rcmp.hi r5,1; hi : round down
bclr.hi r0,r0,0
j_l.d [blink]
sub_s r0,r0,r1
.balign 4
.Lno_shiftdown_dbl1_gt:
add.f 0,r5,r5
btst.eq r0,0
cmp.eq r5,r5
j_s.d [blink]
add.cs r0,r0,1
ENDFUNC(__addsf3)
ENDFUNC(__subsf3)
|
4ms/metamodule-plugin-sdk
| 2,251
|
plugin-libc/libgcc/config/arc/ieee-754/gtsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: r0, r1
output: c, z flags to be used for 'hi' condition
clobber: r12,flags */
/* For NaNs, bit 22.. bit 30 must be set. */
#if 0 /* DEBUG */
.global __gtsf2
.balign 4
FUNC(__gtsf2)
__gtsf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __gtsf2_c` push_s r0
mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __gtsf2_asm` ld.ab r10,[sp,4]
pop_s blink
brgt.d r11,0,0f
ld.ab r11,[sp,4]
jls [blink]
bl abort
0: jhi [blink]
bl abort
ENDFUNC(__gtsf2)
#define __gtsf2 __gtsf2_asm
#endif /* DEBUG */
.global __gtsf2
.balign 4
HIDDEN_FUNC(__gtsf2)
__gtsf2:
or.f r12,r0,r1
bmi.d .Lneg
bmsk_s r12,r12,23
add1.f 0,r12,r0 ; check for NaN
add1.cc.f r12,r12,r1
j_s.d [blink]
cmp.cc r0,r1
.balign 4
.Lneg: breq.d r0,0,.L0
add1.f 0,r12,r0 ; check for NaN
add1.cc.f r12,r12,r1
j_s.d [blink]
cmp.cc r1,r0
.balign 4
.L0: bxor.f 0,r1,31 ; check for -0
j_s.d [blink]
cmp.hi r1,r0
ENDFUNC(__gtsf2)
|
4ms/metamodule-plugin-sdk
| 3,558
|
plugin-libc/libgcc/config/arc/ieee-754/truncdfsf2.S
|
/* Copyright (C) 2006-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
FUNC(__truncdfsf2)
.global __truncdfsf2
.balign 4
__truncdfsf2:
push_s blink
push_s r0
bl.d __truncdfsf2_c
push_s r1
mov_s r2,r0
pop_s r1
ld r0,[sp]
bl.d __truncdfsf2_asm
st r2,[sp]
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
and r12,r0,r1
bic.f 0,0x7f800000,r12
bne 0f
bmsk.f 0,r0,22
bmsk.ne.f r1,r1,22
jne_s [blink] ; both NaN -> OK
0: bl abort
ENDFUNC(__truncdfsf2)
#define __truncdfsf2 __truncdfsf2_asm
#endif /* DEBUG */
.global __truncdfsf2
.balign 4
FUNC(__truncdfsf2)
__truncdfsf2:
lsr r2,DBL0H,20
asl_s DBL0H,DBL0H,12
sub r12,r2,0x380
bclr.f r3,r12,11
brhs r3,0xff,.Lill_exp
beq_l .Ldenorm0
asl_s r12,r12,23
tst DBL0L, \
0x2fffffff /* Check if msb guard bit wants rounding up. */
lsr_s DBL0L,DBL0L,28
lsr_s DBL0H,DBL0H,8
add.ne DBL0L,DBL0L,1
add_s DBL0H,DBL0H,DBL0L
lsr_s DBL0H,DBL0H
btst_s r2,11
add_s r0,DBL0H,r12
j_s.d [blink]
bxor.ne r0,r0,31
.balign 4
.Lill_exp:
bbit1 r2,10,.Linf_nan
bmsk_s r12,r12,9
rsub.f r12,r12,8+0x400-32 ; Go from 9 to 1 guard bit in MSW. */
bhs_s .Lzero
lsr r3,DBL0L,21
rrc DBL0H,DBL0H ; insert leading 1
asl.f 0,DBL0L,8 ; check lower 24 guard bits
add_s r3,DBL0H,r3
add.pnz r3,r3,1 ; assemble fraction with compressed guard bits.
lsr r0,r3,r12
neg_s r12,r12
btst_s r0,1
asl.eq.f r3,r3,r12
add.ne r0,r0,1
btst_s r2,11
lsr_s r0,r0
j_s.d [blink]
bxor.ne r0,r0,31
.Lzero:
lsr_s r2,r2,11
j_s.d [blink]
asl r0,r2,31
.Ldenorm0:
asl_s r12,r12,20
tst DBL0L, \
0x5fffffff /* Check if msb guard bit wants rounding up. */
lsr_s DBL0L,DBL0L,29
lsr_s DBL0H,DBL0H,9
add.ne DBL0L,DBL0L,1
bset_s DBL0H,DBL0H,23
add_s DBL0H,DBL0H,DBL0L
lsr_s DBL0H,DBL0H
j_s.d [blink]
add_l r0,DBL0H,r12
/* We would generally say that NaNs must have a non-zero high fraction part,
but to allow hardware double precision floating point to interoperate
with single precision software floating point, we make an exception here.
The cost is to replace a tst_s DBL0H with an or.f DBL0L,DBL0L,DBL0H .
As we start out unaligned, and there is an odd number of other short insns,
we have a choice of letting this cost us a misalign penalty or
4 more bytes (if we align the code). We choose the former here because
infinity / NaN is not expected to be prevalent in time-critical code. */
.Linf_nan:
or.f DBL0L,DBL0L,DBL0H
mov_s r0,1
add.ne r2,r2,1
tst r2,0x7ff
asl.ne r0,r0,23
btst_s r12,11
neg r0,r0
j_s.d [blink]
bxor.eq r0,r0,31
ENDFUNC(__truncdfsf2)
|
4ms/metamodule-plugin-sdk
| 1,969
|
plugin-libc/libgcc/config/arc/ieee-754/fixunsdfsi.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
FUNC(__fixunsdfsi)
.global __fixunsdfsi
.balign 4
__fixunsdfsi:
push_s blink
push_s r0
bl.d __fixunsdfsi_c
push_s r1
mov_s r2,r0
pop_s r1
ld r0,[sp]
bl.d __fixunsdfsi_asm
st r2,[sp]
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
bl abort
ENDFUNC(__fixunsdfsi)
#define __fixunsdfsi __fixunsdfsi_asm
#endif /* DEBUG */
.global __fixunsdfsi
FUNC(__fixunsdfsi)
.balign 4
__fixunsdfsi:
bbit0 DBL0H,30,.Lret0or1
lsr r2,DBL0H,20
bmsk_s DBL0H,DBL0H,19
sub_s r2,r2,19; 0x3ff+20-0x400
neg_s r3,r2
btst_s r3,10
bset_s DBL0H,DBL0H,20
#ifdef __LITTLE_ENDIAN__
mov.ne DBL0L,DBL0H
asl DBL0H,DBL0H,r2
#else
asl.eq DBL0H,DBL0H,r2
lsr.ne DBL0H,DBL0H,r3
#endif
lsr DBL0L,DBL0L,r3
j_s.d [blink]
add.eq r0,r0,r1
.Lret0:
j_s.d [blink]
mov_l r0,0
.Lret0or1:
add_s DBL0H,DBL0H,0x100000
lsr_s DBL0H,DBL0H,30
j_s.d [blink]
bmsk_l r0,DBL0H,0
ENDFUNC(__fixunsdfsi)
|
4ms/metamodule-plugin-sdk
| 4,862
|
plugin-libc/libgcc/config/arc/ieee-754/divsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __divsf3
FUNC(__divsf3)
.balign 4
__divsf3:
push_s blink
push_s r1
bl.d __divsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __divsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
#if 1
bne abort
jeq_s [blink]
b abort
#else
bne abort
j_s [blink]
#endif
ENDFUNC(__divsf3)
#define __divsf3 __divsf3_asm
#endif /* DEBUG */
.balign 4
__divdf3_support: /* This label makes debugger output saner. */
FUNC(__divsf3)
.Ldenorm_fp0:
norm.f r12,r2 ; flag for 0/x -> 0 check
bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0
beq_s .Lret0_NaN
tst r1,r9
add_s r2,r2,r2
sub_s r12,r12,8
asl_s r2,r2,r12
asl_l r12,r12,23
bne.d .Lpast_denorm_fp0
add r5,r5,r12
/* r0 is subnormal, r1 is subnormal or 0. */
.balign 4
.Ldenorm_fp1:
norm.f r12,r3 ; flag for x/0 -> Inf check
bic.ne.f 0,0x60000000,r0 ; large number/denorm -> Inf
beq_s .Linf
add_s r3,r3,r3
sub_s r12,r12,8
asl_s r3,r3,r12
asl_s r12,r12,23
b.d .Lpast_denorm_fp1
add r4,r4,r12
.Lret0_NaN:
bclr.f 0,r1,31 ; 0/0 -> NaN
bic r0,r10,r9
j_s.d [blink]
sub.eq r0,r0,1
.global __divsf3
.balign 4
.long 0x7f800000 ; exponent mask
__divsf3:
ld r9,[pcl,-4]
bmsk r2,r0,22
xor r4,r0,r2
bmsk r3,r1,22
xor r5,r1,r3
and r11,r0,r9
breq.d r11,0,.Ldenorm_fp0
xor r10,r4,r5
breq r11,r9,.Linf_nan_fp0
bset_s r2,r2,23
and r11,r1,r9
breq r11,0,.Ldenorm_fp1
breq r11,r9,.Linf_nan_fp1
.Lpast_denorm_fp0:
bset_s r3,r3,23
.Lpast_denorm_fp1:
cmp r2,r3
asl_s r2,r2,6+1
asl_s r3,r3,7
add.lo r2,r2,r2
bclr r8,r9,30 ; exponent bias
bclr.lo r8,r8,23 ; reduce exp by one if fraction is shifted
sub r4,r4,r5
add r4,r4,r8
xor.f 0,r10,r4
bmi .Linf_denorm
and r12,r4,r9
breq r12,0,.Ldenorm
sub_s r2,r2,r3 ; discard implicit 1
.Ldiv_23bit:
.rep 6
divaw r2,r2,r3
.endr
breq r12,r9,.Linf
bmsk r0,r2,6
xor_s r2,r2,r0
.Ldiv_17bit:
.rep 7
divaw r2,r2,r3
.endr
asl_s r0,r0,7
bmsk r1,r2,6
xor_s r2,r2,r1
or_s r0,r0,r1
.Ldiv_10bit:
.rep 7
divaw r2,r2,r3
.endr
asl_s r0,r0,7
bmsk r1,r2,6
xor_s r2,r2,r1
or_s r0,r0,r1
.Ldiv_3bit:
.rep 3
divaw r2,r2,r3
.endr
asl_s r0,r0,3
.Ldiv_0bit:
divaw r1,r2,r3
bmsk_s r2,r2,2
tst r1,-0x7e ; 0xffffff82, test for rest or odd
bmsk_s r1,r1,0
add_s r0,r0,r2 ; assemble fraction
add_s r0,r0,r4 ; add in sign & exponent
j_s.d [blink]
add.ne r0,r0,r1 ; round to nearest / even
.balign 4
.Linf_nan_fp0:
bic.f 0,r9,r1 ; fp1 Inf -> result NaN
bic r1,r5,r9 ; fp1 sign
sub.eq r1,r1,1
j_s.d [blink]
xor_s r0,r0,r1
.Linf_nan_fp1:
bic r0,r4,r9 ; fp0 sign
bmsk.f 0,r1,22 ; x/inf -> 0, x/nan -> nan
xor.eq r1,r1,r9
j_s.d [blink]
xor_s r0,r0,r1
.Linf:
j_s.d [blink]
or r0,r10,r9
.Lret_r4:
j_s.d [blink]
mov_s r0,r4
.balign 4
.Linf_denorm:
add.f r12,r4,r4
asr_l r12,r12,24
bpl .Linf
max r12,r12,-24
.Ldenorm:
add r1,pcl,42; .Ldenorm_tab-.
ldb_s r12,[r12,r1]
mov_s r0,0
lsr_s r2,r2
sub_s r1,r1,r12
j_s.d [r1]
bic r4,r10,r9
.byte .Ldenorm_tab-.Lret_r4
.byte .Ldenorm_tab-.Ldiv_0bit
.byte .Ldenorm_tab-.Ldiv_3bit-8
.byte .Ldenorm_tab-.Ldiv_3bit-4
.byte .Ldenorm_tab-.Ldiv_3bit
.byte .Ldenorm_tab-.Ldiv_10bit-24
.byte .Ldenorm_tab-.Ldiv_10bit-20
.byte .Ldenorm_tab-.Ldiv_10bit-16
.byte .Ldenorm_tab-.Ldiv_10bit-12
.byte .Ldenorm_tab-.Ldiv_10bit-8
.byte .Ldenorm_tab-.Ldiv_10bit-4
.byte .Ldenorm_tab-.Ldiv_10bit
.byte .Ldenorm_tab-.Ldiv_17bit-24
.byte .Ldenorm_tab-.Ldiv_17bit-20
.byte .Ldenorm_tab-.Ldiv_17bit-16
.byte .Ldenorm_tab-.Ldiv_17bit-12
.byte .Ldenorm_tab-.Ldiv_17bit-8
.byte .Ldenorm_tab-.Ldiv_17bit-4
.byte .Ldenorm_tab-.Ldiv_17bit
.byte .Ldenorm_tab-.Ldiv_23bit-20
.byte .Ldenorm_tab-.Ldiv_23bit-16
.byte .Ldenorm_tab-.Ldiv_23bit-12
.byte .Ldenorm_tab-.Ldiv_23bit-8
.byte .Ldenorm_tab-.Ldiv_23bit-4
.Ldenorm_tab:
.byte .Ldenorm_tab-.Ldiv_23bit
ENDFUNC(__divsf3)
|
4ms/metamodule-plugin-sdk
| 2,281
|
plugin-libc/libgcc/config/arc/ieee-754/uneqdf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: DBL0, DBL1
output: z flag
clobber: r12, flags
For NaNs, bit 19.. bit 30 of the high word must be set. */
#if 0 /* DEBUG */
.global __uneqdf2
.balign 4
FUNC(__uneqdf2)
__uneqdf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __eqdf2_c` push_s r0
push_s r0` ld_s r0, [sp,4]` ld_s r1, [sp,8]` ld_s r2,[sp,12]
bl.d __unorddf2_c` ld_s r3,[sp,16]
ld.ab r11,[sp,4]` tst r0,r0` mov.ne r11,0
pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __uneqdf2_asm` ld.ab r10,[sp,4]
pop_s blink
breq.d r11,0,0f
ld.ab r11,[sp,4]
jne_s [blink]
bl abort
0: jeq_s [blink]
bl abort
ENDFUNC(__uneqdf2)
#define __uneqdf2 __uneqdf2_asm
#endif /* DEBUG */
.global __uneqdf2
.balign 4
HIDDEN_FUNC(__uneqdf2)
__uneqdf2:
cmp_s DBL0H,DBL1H
cmp.eq DBL0L,DBL1L
jeq_s [blink]
or r12,DBL0H,DBL1H
or.f 0,DBL0L,DBL1L
bclr.eq.f r12,r12,31
jeq_s [blink]
mov_s r12, \
0x7ff80000
bic.f 0,r12,DBL0H
j_s.d [blink]
bic.ne.f r12,r12,DBL1H
ENDFUNC(__uneqdf2)
|
4ms/metamodule-plugin-sdk
| 2,139
|
plugin-libc/libgcc/config/arc/ieee-754/uneqsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: r0, r1
output: z flag
clobber: r12, flags
For NaNs, bit 22 .. bit 30 must be set. */
#if 0 /* DEBUG */
.global __uneqsf2
.balign 4
FUNC(__uneqsf2)
__uneqsf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __eqsf2_c` push_s r0
push_s r0` ld_s r0, [sp,4]
bl.d __unordsf2_c` ld_s r1,[sp,8]
ld.ab r11,[sp,4]` tst r0,r0` mov.ne r11,0
pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __uneqsf2_asm` ld.ab r10,[sp,4]
pop_s blink
breq.d r11,0,0f
ld.ab r11,[sp,4]
jne_s [blink]
bl abort
0: jeq_s [blink]
bl abort
ENDFUNC(__uneqsf2)
#define __uneqsf2 __uneqsf2_asm
#endif /* DEBUG */
.global __uneqsf2
.balign 4
HIDDEN_FUNC(__uneqsf2)
__uneqsf2:
mov_s r12, \
0x7fc00000
bic.f 0,r12,r0
bic.ne.f r12,r12,r1
or r12,r0,r1
bmsk.ne.f r12,r12,30
j_s.d [blink]
cmp.ne r0,r1
ENDFUNC(__uneqsf2)
|
4ms/metamodule-plugin-sdk
| 1,746
|
plugin-libc/libgcc/config/arc/ieee-754/fixsfsi.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __fixsfsi
FUNC(__fixsfsi)
.balign 4
__fixsfsi:
push_s blink
bl.d __fixsfsi_c
push_s r0
ld_s r1,[sp]
st_s r0,[sp]
bl.d __fixsfsi_asm
mov_s r0,r1
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
bl abort
ENDFUNC(__fixsfsi)
#define __fixsfsi __fixsfsi_asm
#endif /* DEBUG */
.global __fixsfsi
FUNC(__fixsfsi)
.balign 4
__fixsfsi:
bbit0 r0,30,.Lret0or1
lsr r2,r0,23
bmsk_s r0,r0,22
bset_s r0,r0,23
sub_s r2,r2,22;0x7f+23-0x80
asl.f 0,r2,24
neg r3,r2
asl.mi r0,r0,r2
lsr.pl r0,r0,r3
j_s.d [blink]
neg.cs r0,r0
.Lret0or1:
add.f r0,r0,0x800000
lsr_s r0,r0,30
bmsk_s r0,r0,0
j_s.d [blink]
neg.mi r0,r0
ENDFUNC(__fixsfsi)
|
4ms/metamodule-plugin-sdk
| 2,274
|
plugin-libc/libgcc/config/arc/ieee-754/floatsisf.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __floatsisf
FUNC(__floatsisf)
.balign 4
__floatsisf:
push_s blink
bl.d __floatsisf_c
push_s r0
ld_s r1,[sp]
st_s r0,[sp]
bl.d __floatsisf_asm
mov_s r0,r1
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
bl abort
ENDFUNC(__floatsisf)
.global __floatunsisf
FUNC(__floatunsisf)
.balign 4
__floatunsisf:
push_s blink
bl.d __floatunsisf_c
push_s r0
ld_s r1,[sp]
st_s r0,[sp]
bl.d __floatunsisf_asm
mov_s r0,r1
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
bl abort
ENDFUNC(__floatunsisf)
#define __floatsisf __floatsisf_asm
#define __floatunsisf __floatunsisf_asm
#endif /* DEBUG */
.global __floatunsisf
.global __floatsisf
FUNC(__floatsisf)
FUNC(__floatunsisf)
.balign 4
__floatunsisf:
lsr_s r2,r0
mov_l r12,0x9d ; 0x7f + 31 - 1
norm r2,r2
brne_l r0,0,0f
j_s [blink]
.balign 4
__floatsisf:
abs.f r0,r0
jeq_s [blink]
lsr_s r2,r0
mov_s r12,0x9d ; 0x7f + 31 - 1
norm r2,r2
bset.cs r12,r12,8
0: rsub.f r3,r2,8
bmsk r1,r0,r3
ror r1,r1,r3
lsr.pl r0,r0,r3
neg_s r3,r3
asl.mi r0,r0,r3
sub_s r12,r12,r2
asl_s r12,r12,23
bxor.pl.f r1,r1,31
add_s r0,r0,r12
j_s.d [blink]
add.pnz r0,r0,1
ENDFUNC(__floatunsisf)
ENDFUNC(__floatsisf)
|
4ms/metamodule-plugin-sdk
| 2,203
|
plugin-libc/libgcc/config/arc/ieee-754/eqsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: r0, r1
output: z flag
clobber: r12, flags
For NaNs, bit 22 .. bit 30 must be set. */
#if 0 /* DEBUG */
.global __eqsf2
.balign 4
FUNC(__eqsf2)
__eqsf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __eqsf2_c` push_s r0
mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __eqsf2_asm` ld.ab r10,[sp,4]
pop_s blink
breq.d r11,0,0f
ld.ab r11,[sp,4]
jne_s [blink]
bl abort
0: jeq_s [blink]
bl abort
ENDFUNC(__eqsf2)
#define __eqsf2 __eqsf2_asm
#endif /* DEBUG */
/* Good performance as long as the binary difference is
well predictable (as seen from the branch predictor). */
.global __eqsf2
.balign 4
HIDDEN_FUNC(__eqsf2)
__eqsf2:
breq r0, r1,.Lno_bdiff
or r12,r0,r1
j_s.d [blink]
bmsk.f 0,r12,30
.Lno_bdiff:
bmsk r12,r0,23
add1.f r12,r12,r0 /* set c iff NaN; also, clear z if NaN. */
j_s.d [blink]
cmp.cc r0,r1
ENDFUNC(__eqsf2)
|
4ms/metamodule-plugin-sdk
| 2,064
|
plugin-libc/libgcc/config/arc/ieee-754/orddf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: r0, r1
output: c flag
clobber: r12, flags
For NaNs, bit 19 .. bit 30 must be set. */
#if 0 /* DEBUG */
.global __orddf2
.balign 4
FUNC(__orddf2)
__orddf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __unorddf2_c` push_s r0
mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __orddf2_asm` ld.ab r10,[sp,4]
pop_s blink
brne.d r11,0,0f
ld.ab r11,[sp,4]
jcc [blink]
bl abort
0: jcs [blink]
bl abort
ENDFUNC(__orddf2)
#define __orddf2 __orddf2_asm
#endif /* DEBUG */
.global __orddf2
.balign 4
HIDDEN_FUNC(__orddf2)
__orddf2:
bmsk r12,DBL0H,20
add1.f r12,r12,DBL0H /* clear z; set c if NaN. */
bmsk r12,DBL1H,20
j_s.d [blink]
add1.cc.f r12,r12,DBL1H /* clear z; set c if NaN. */
ENDFUNC(__orddf2)
|
4ms/metamodule-plugin-sdk
| 2,643
|
plugin-libc/libgcc/config/arc/ieee-754/eqdf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: DBL0, DBL1
output: z flag
clobber: r12, flags
For NaNs, bit 19.. bit 30 of the high word must be set. */
#if 0 /* DEBUG */
.global __eqdf2
.balign 4
FUNC(__eqdf2)
__eqdf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __eqdf2_c` push_s r0
mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __eqdf2_asm` ld.ab r10,[sp,4]
pop_s blink
breq.d r11,0,0f
ld.ab r11,[sp,4]
jne_s [blink]
bl abort
0: jeq_s [blink]
bl abort
ENDFUNC(__eqdf2)
#define __eqdf2 __eqdf2_asm
#endif /* DEBUG */
.global __eqdf2
.balign 4
HIDDEN_FUNC(__eqdf2)
/* Good performance as long as the difference in high word is
well predictable (as seen from the branch predictor). */
__eqdf2:
brne.d DBL0H,DBL1H,.Lhighdiff
#ifndef __HS__
/* The next two instructions are required to recognize the FPX
NaN, which has a pattern like this: 0x7ff0_0000_8000_0000, as
oposite to 0x7ff8_0000_0000_0000. */
or.f 0,DBL0L,DBL1L
mov_s r12,0x00200000
bset.ne r12,r12,0
#else
bmsk r12,DBL0H,20
#endif /* __HS__ */
add1.f r12,r12,DBL0H /* set c iff NaN; also, clear z if NaN. */
j_s.d [blink]
cmp.cc DBL0L,DBL1L
.balign 4
.Lhighdiff:
or r12,DBL0H,DBL1H
or.f 0,DBL0L,DBL1L
j_s.d [blink]
bmsk.eq.f r12,r12,30
ENDFUNC(__eqdf2)
/* ??? could we do better by speeding up some 'common' case of inequality? */
|
4ms/metamodule-plugin-sdk
| 2,052
|
plugin-libc/libgcc/config/arc/ieee-754/ordsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: r0, r1
output: c flag
clobber: r12, flags
For NaNs, bit 22 .. bit 30 must be set. */
#if 0 /* DEBUG */
.global __ordsf2
.balign 4
FUNC(__ordsf2)
__ordsf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __unordsf2_c` push_s r0
mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __ordsf2_asm` ld.ab r10,[sp,4]
pop_s blink
brne.d r11,0,0f
ld.ab r11,[sp,4]
jcc [blink]
bl abort
0: jcs [blink]
bl abort
ENDFUNC(__ordsf2)
#define __ordsf2 __ordsf2_asm
#endif /* DEBUG */
.global __ordsf2
.balign 4
HIDDEN_FUNC(__ordsf2)
__ordsf2:
bmsk r12,r0,23
add1.f r12,r12,r0 /* clear z; set c if NaN. */
bmsk r12,r1,23
j_s.d [blink]
add1.cc.f r12,r12,r1 /* clear z; set c if NaN. */
ENDFUNC(__ordsf2)
|
4ms/metamodule-plugin-sdk
| 2,247
|
plugin-libc/libgcc/config/arc/ieee-754/gesf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: r0, r1
output: c flag to be used for 'hs' condition
clobber: r12,flags */
/* For NaNs, bit 22.. bit 30 must be set. */
#if 0 /* DEBUG */
.global __gesf2
.balign 4
FUNC(__gesf2)
__gesf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __gesf2_c` push_s r0
mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __gesf2_asm` ld.ab r10,[sp,4]
pop_s blink
brge.d r11,0,0f
ld.ab r11,[sp,4]
jlo [blink]
bl abort
0: jhs [blink]
bl abort
ENDFUNC(__gesf2)
#define __gesf2 __gesf2_asm
#endif /* DEBUG */
.global __gesf2
.balign 4
HIDDEN_FUNC(__gesf2)
__gesf2:
or.f r12,r0,r1
bmi.d .Lneg
bmsk_s r12,r12,23
add1.f 0,r12,r0 ; check for NaN
add1.cc.f r12,r12,r1
j_s.d [blink]
cmp.cc r0,r1
.balign 4
.Lneg: breq.d r1,0,.L0
add1.f 0,r12,r0 ; check for NaN
add1.cc.f r12,r12,r1
j_s.d [blink]
cmp.cc r1,r0
.balign 4
.L0: bxor.f 0,r0,31 ; check for -0
j_s.d [blink]
cmp.hi r1,r0
ENDFUNC(__gesf2)
|
4ms/metamodule-plugin-sdk
| 2,573
|
plugin-libc/libgcc/config/arc/ieee-754/gedf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
/* inputs: DBL0, DBL1
output: c flags to be used for 'hs' condition
clobber: r12, flags */
/* For NaNs, bit 19.. bit 30 of the high word must be set. */
#if 0 /* DEBUG */
.global __gedf2
.balign 4
FUNC(__gedf2)
__gedf2:
st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4]
st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4]
st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1`
bl.d __gedf2_c` push_s r0
mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3
ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]`
ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4]
bl.d __gedf2_asm` ld.ab r10,[sp,4]
pop_s blink
brge.d r11,0,0f
ld.ab r11,[sp,4]
jlo [blink]
bl abort
0: jhs [blink]
bl abort
ENDFUNC(__gedf2)
#define __gedf2 __gedf2_asm
#endif /* DEBUG */
.global __gedf2
.balign 4
HIDDEN_FUNC(__gedf2)
__gedf2:
or.f r12,DBL0H,DBL1H
bmi.d .Lneg
bmsk_s r12,r12,20
add1.f 0,r12,DBL0H ; clear z; set c iff NaN
add1.cc.f r12,r12,DBL1H ; clear z; set c iff NaN
bbit1 DBL0H,31,.Lneg
cmp.cc DBL0H,DBL1H
j_s.d [blink]
cmp.eq DBL0L,DBL1L
.balign 4
.Lneg: breq.d DBL1H,0,.L0
add1.f 0,r12,DBL0H
add1.cc.f r12,r12,DBL1H
cmp.cc DBL1H,DBL0H
j_s.d [blink]
cmp.eq DBL1L,DBL0L
.balign 4
.L0:
bxor.f 0,DBL0H,31 ; check for high word of -0.
beq_s .Lcheck_0
cmp.cc DBL1H,DBL0H
j_s.d [blink]
cmp.eq DBL1L,DBL0L
.Lcheck_0:
; high words suggest DBL0 may be -0, DBL1 +0; check low words.
cmp_s DBL1H,DBL0L
j_s.d [blink]
cmp.cc DBL1H,DBL1L
ENDFUNC(__gedf2)
|
4ms/metamodule-plugin-sdk
| 1,882
|
plugin-libc/libgcc/config/arc/ieee-754/floatunsidf.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __floatunsidf
.balign 4
FUNC(__floatunsidf)
__floatunsidf:
push_s blink
bl.d __floatunsidf_c
push_s r0
ld_s r2,[sp]
st_s r1,[sp]
push_s r0
bl.d __floatunsidf_asm
mov_s r0,r2
pop_s r2
pop_s r3
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
bl abort
ENDFUNC(__floatunsidf)
#define __floatunsidf __floatunsidf_asm
#endif /* DEBUG */
.global __floatunsidf
.balign 4
FUNC(__floatunsidf)
__floatunsidf:
lsr_s r1,r0
breq_s r0,0,.Lret0
norm r2,r1
mov r12,-0x41d ; -(0x3ff+31-1)
rsub.f r3,r2,11
add_s r12,r2,r12
add_s r2,r2,21
#ifdef __LITTLE_ENDIAN__
lsr DBL0H,r0,r3
asl_s DBL0L,r0,r2
#else
asl DBL0L,r0,r2
lsr_s DBL0H,r0,r3
#endif
asl_s r12,r12,20
mov.lo DBL0H,DBL0L
sub_s DBL0H,DBL0H,r12
.Lret0: j_s.d [blink]
mov.ls DBL0L,0
ENDFUNC(__floatunsidf)
|
4ms/metamodule-plugin-sdk
| 2,150
|
plugin-libc/libgcc/config/arc/ieee-754/fixdfsi.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
FUNC(__fixdfsi)
.global __fixdfsi
.balign 4
__fixdfsi:
push_s blink
push_s r0
bl.d __fixdfsi_c
push_s r1
mov_s r2,r0
pop_s r1
ld r0,[sp]
bl.d __fixdfsi_asm
st r2,[sp]
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
bl abort
ENDFUNC(__fixdfsi)
#define __fixdfsi __fixdfsi_asm
#endif /* DEBUG */
/* If the fraction has to be shifted left by a positive non-zero amount,
we have to combine bits from DBL0L and DBL0H. If we shift right,
or shift by zero, we only want to have the bits from DBL0H in r0. */
.global __fixdfsi
FUNC(__fixdfsi)
.balign 4
__fixdfsi:
bbit0 DBL0H,30,.Lret0or1
asr r2,DBL0H,20
bmsk_s DBL0H,DBL0H,19
sub_s r2,r2,19; 0x3ff+20-0x400
neg_s r3,r2
asr.f 0,r3,11
bset_s DBL0H,DBL0H,20
#ifdef __LITTLE_ENDIAN__
mov.cs DBL0L,DBL0H
asl DBL0H,DBL0H,r2
#else
asl.cc DBL0H,DBL0H,r2
lsr.cs DBL0H,DBL0H,r3
#endif
lsr_s DBL0L,DBL0L,r3
add.cc r0,r0,r1
j_s.d [blink]
neg.pl r0,r0
.Lret0or1:
add.f r0,DBL0H,0x100000
lsr_s r0,r0,30
bmsk_s r0,r0,0
j_s.d [blink]
neg.mi r0,r0
ENDFUNC(__fixdfsi)
|
4ms/metamodule-plugin-sdk
| 6,432
|
plugin-libc/libgcc/config/arc/ieee-754/divsf3-stdmul.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
- calculate 15..18 bit inverse using a table of approximating polynoms.
precision is higher for polynoms used to evaluate input with larger
value.
- do one newton-raphson iteration step to double the precision,
then multiply this with the divisor
-> more time to decide if dividend is subnormal
- the worst error propagation is on the side of the value range
with the least initial defect, thus giving us about 30 bits precision.
*/
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __divsf3
FUNC(__divsf3)
.balign 4
__divsf3:
push_s blink
push_s r1
bl.d __divsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __divsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
#if 1
bne abort
jeq_s [blink]
b abort
#else
bne abort
j_s [blink]
#endif
ENDFUNC(__divsf3)
#define __divsf3 __divsf3_asm
#endif /* DEBUG */
FUNC(__divsf3)
.balign 4
.L7f800000:
.long 0x7f800000
.Ldivtab:
.long 0xfc0ffff0
.long 0xf46ffefd
.long 0xed1ffd2a
.long 0xe627fa8e
.long 0xdf7ff73b
.long 0xd917f33b
.long 0xd2f7eea3
.long 0xcd1fe986
.long 0xc77fe3e7
.long 0xc21fdddb
.long 0xbcefd760
.long 0xb7f7d08c
.long 0xb32fc960
.long 0xae97c1ea
.long 0xaa27ba26
.long 0xa5e7b22e
.long 0xa1cfa9fe
.long 0x9ddfa1a0
.long 0x9a0f990c
.long 0x9667905d
.long 0x92df878a
.long 0x8f6f7e84
.long 0x8c27757e
.long 0x88f76c54
.long 0x85df630c
.long 0x82e759c5
.long 0x8007506d
.long 0x7d3f470a
.long 0x7a8f3da2
.long 0x77ef341e
.long 0x756f2abe
.long 0x72f7212d
.long 0x709717ad
.long 0x6e4f0e44
.long 0x6c1704d6
.long 0x69e6fb44
.long 0x67cef1d7
.long 0x65c6e872
.long 0x63cedf18
.long 0x61e6d5cd
.long 0x6006cc6d
.long 0x5e36c323
.long 0x5c76b9f3
.long 0x5abeb0b7
.long 0x5916a79b
.long 0x57769e77
.long 0x55de954d
.long 0x54568c4e
.long 0x52d6834d
.long 0x51667a7f
.long 0x4ffe71b5
.long 0x4e9e68f1
.long 0x4d466035
.long 0x4bf65784
.long 0x4aae4ede
.long 0x496e4646
.long 0x48363dbd
.long 0x47063547
.long 0x45de2ce5
.long 0x44be2498
.long 0x43a61c64
.long 0x4296144a
.long 0x41860c0e
.long 0x407e03ee
__divsf3_support: /* This label makes debugger output saner. */
.Ldenorm_fp1:
bclr r6,r6,31
norm.f r12,r6 ; flag for x/0 -> Inf check
add r6,r6,r6
rsub r5,r12,16
ror r5,r1,r5
asl r6,r6,r12
bmsk r5,r5,5
ld.as r5,[r3,r5]
add r4,r6,r6
; load latency
MPYHU r7,r5,r4
bic.ne.f 0, \
0x60000000,r0 ; large number / denorm -> Inf
beq_s .Linf_NaN
asl r5,r5,13
; wb stall
; slow track
sub r7,r5,r7
MPYHU r8,r7,r6
asl_s r12,r12,23
and.f r2,r0,r9
add r2,r2,r12
asl r12,r0,8
; wb stall
bne.d .Lpast_denorm_fp1
.Ldenorm_fp0:
MPYHU r8,r8,r7
bclr r12,r12,31
norm.f r3,r12 ; flag for 0/x -> 0 check
bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0
beq_s .Lret0
asl_s r12,r12,r3
asl_s r3,r3,23
add_s r12,r12,r12
add r11,r11,r3
b.d .Lpast_denorm_fp0
mov_s r3,r12
.balign 4
.Linf_NaN:
bclr.f 0,r0,31 ; 0/0 -> NaN
xor_s r0,r0,r1
bmsk r1,r0,30
bic_s r0,r0,r1
sub.eq r0,r0,1
j_s.d [blink]
or r0,r0,r9
.Lret0:
xor_s r0,r0,r1
bmsk r1,r0,30
j_s.d [blink]
bic_s r0,r0,r1
.Linf_nan_fp1:
lsr_s r0,r0,31
bmsk.f 0,r1,22
asl_s r0,r0,31
bne_s 0f ; inf/inf -> nan
brne r2,r9,.Lsigned0 ; x/inf -> 0, but x/nan -> nan
0: j_s.d [blink]
mov r0,-1
.Lsigned0:
.Linf_nan_fp0:
tst_s r1,r1
j_s.d [blink]
bxor.mi r0,r0,31
.balign 4
.global __divsf3
/* N.B. the spacing between divtab and the sub3 to get its address must
be a multiple of 8. */
__divsf3:
lsr r2,r1,17
sub3 r3,pcl,55;(.-.Ldivtab) >> 3
bmsk_s r2,r2,5
ld.as r5,[r3,r2]
asl r4,r1,9
ld.as r9,[pcl,-114]; [pcl,(-((.-.L7f800000) >> 2))] ; 0x7f800000
MPYHU r7,r5,r4
asl r6,r1,8
and.f r11,r1,r9
bset r6,r6,31
asl r5,r5,13
; wb stall
beq .Ldenorm_fp1
sub r7,r5,r7
MPYHU r8,r7,r6
breq.d r11,r9,.Linf_nan_fp1
and.f r2,r0,r9
beq.d .Ldenorm_fp0
asl r12,r0,8
; wb stall
breq r2,r9,.Linf_nan_fp0
MPYHU r8,r8,r7
.Lpast_denorm_fp1:
bset r3,r12,31
.Lpast_denorm_fp0:
cmp_s r3,r6
lsr.cc r3,r3,1
add_s r2,r2, /* wait for immediate */ \
/* wb stall */ \
0x3f000000
sub r7,r7,r8 ; u1.31 inverse, about 30 bit
MPYHU r3,r3,r7
sbc r2,r2,r11
xor.f 0,r0,r1
and r0,r2,r9
bxor.mi r0,r0,31
brhs r2, /* wb stall / wait for immediate */ \
0x7f000000,.Linf_denorm
.Lpast_denorm:
add_s r3,r3,0x22 ; round to nearest or higher
tst r3,0x3c ; check if rounding was unsafe
lsr r3,r3,6
jne.d [blink] ; return if rounding was safe.
add_s r0,r0,r3
/* work out exact rounding if we fall through here. */
/* We know that the exact result cannot be represented in single
precision. Find the mid-point between the two nearest
representable values, multiply with the divisor, and check if
the result is larger than the dividend. */
add_s r3,r3,r3
sub_s r3,r3,1
mpyu r3,r3,r6
asr.f 0,r0,1 ; for round-to-even in case this is a denorm
rsub r2,r9,25
asl_s r12,r12,r2
; wb stall
; slow track
sub.f 0,r12,r3
j_s.d [blink]
sub.mi r0,r0,1
/* For denormal results, it is possible that an exact result needs
rounding, and thus the round-to-even rule has to come into play. */
.Linf_denorm:
brlo r2,0xc0000000,.Linf
.Ldenorm:
asr_s r2,r2,23
bic r0,r0,r9
neg r9,r2
brlo.d r9,25,.Lpast_denorm
lsr r3,r3,r9
/* Fall through: return +- 0 */
j_s [blink]
.Linf:
j_s.d [blink]
or r0,r0,r9
ENDFUNC(__divsf3)
|
4ms/metamodule-plugin-sdk
| 12,161
|
plugin-libc/libgcc/config/arc/ieee-754/adddf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "arc-ieee-754.h"
#if 0 /* DEBUG */
.global __adddf3
.balign 4
__adddf3:
push_s blink
push_s r2
push_s r3
push_s r0
bl.d __adddf3_c
push_s r1
ld_s r2,[sp,12]
ld_s r3,[sp,8]
st_s r0,[sp,12]
st_s r1,[sp,8]
pop_s r1
bl.d __adddf3_asm
pop_s r0
pop_s r3
pop_s r2
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
bl abort
.global __subdf3
.balign 4
__subdf3:
push_s blink
push_s r2
push_s r3
push_s r0
bl.d __subdf3_c
push_s r1
ld_s r2,[sp,12]
ld_s r3,[sp,8]
st_s r0,[sp,12]
st_s r1,[sp,8]
pop_s r1
bl.d __subdf3_asm
pop_s r0
pop_s r3
pop_s r2
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
bl abort
#define __adddf3 __adddf3_asm
#define __subdf3 __subdf3_asm
#endif /* DEBUG */
/* N.B. This is optimized for ARC700.
ARC600 has very different scheduling / instruction selection criteria. */
/* inputs: DBL0, DBL1 (r0-r3)
output: DBL0 (r0, r1)
clobber: r2-r10, r12, flags
All NaN highword bits must be 1. NaN low word is random. */
.balign 4
.global __adddf3
.global __subdf3
.long 0x7ff00000 ; exponent mask
FUNC(__adddf3)
FUNC(__subdf3)
__subdf3:
bxor_l DBL1H,DBL1H,31
__adddf3:
ld r9,[pcl,-8]
bmsk r4,DBL0H,30
xor r10,DBL0H,DBL1H
and r6,DBL1H,r9
sub.f r12,r4,r6
asr_s r12,r12,20
blo .Ldbl1_gt
brhs r4,r9,.Linf_nan
brhs r12,32,.Large_shift
brne r12,0,.Lsmall_shift
brge r10,0,.Ladd_same_exp ; r12 == 0
/* After subtracting, we need to normalize; when shifting to place the
leading 1 into position for the implicit 1 and adding that to DBL0H,
we increment the exponent. Thus, we have to subtract one more than
the shift count from the exponent beforehand. Iff the exponent drops thus
below zero (before adding in the fraction with the leading one), we have
generated a denormal number. Denormal handling is basicallly reducing the
shift count so that we produce a zero exponent instead; however, this way
the shift count can become zero (if we started out with exponent 1).
Therefore, a simple min operation is not good enough, since we don't
want to handle a zero normalizing shift in the main path.
On the plus side, we don't need to check for denorm input, the result
of subtracing these looks just the same as denormals generated during
subtraction. */
bmsk r7,DBL1H,30
cmp r4,r7
cmp.eq DBL0L,DBL1L
blo .L_rsub_same_exp
sub.f DBL0L,DBL0L,DBL1L
bmsk r12,DBL0H,19
bic DBL1H,DBL0H,r12
sbc.f r4,r4,r7
beq_l .Large_cancel
norm DBL1L,r4
b.d .Lsub_done_same_exp
sub r12,DBL1L,9
.balign 4
.Linf_nan:
; If both inputs are inf, but with different signs, the result is NaN.
asr r12,r10,31
or_s DBL1H,DBL1H,r12
j_s.d [blink]
or.eq DBL0H,DBL0H,DBL1H
.balign 4
.L_rsub_same_exp:
rsub.f DBL0L,DBL0L,DBL1L
bmsk r12,DBL1H,19
bic_s DBL1H,DBL1H,r12
sbc.f r4,r7,r4
beq_l .Large_cancel
norm DBL1L,r4
sub r12,DBL1L,9
.Lsub_done_same_exp:
asl_s r12,r12,20
sub_s DBL1L,DBL1L,10
sub DBL0H,DBL1H,r12
xor.f 0,DBL0H,DBL1H
bmi .Ldenorm
.Lpast_denorm:
neg_s r12,DBL1L
lsr r7,DBL0L,r12
asl r12,r4,DBL1L
asl_s DBL0L,DBL0L,DBL1L
add_s r12,r12,r7
j_s.d [blink]
add_l DBL0H,DBL0H,r12
.balign 4
.Ladd_same_exp:
/* This is a special case because we can't test for need to shift
down by checking if bit 20 of DBL0H changes. OTOH, here we know
that we always need to shift down. */
; The implicit 1 of DBL0 is not shifted together with the
; fraction, thus effectively doubled, compensating for not setting
; implicit1 for DBL1
add_s r12,DBL0L,DBL1L
lsr.f 0,r12,2 ; round to even
breq r6,0,.Ldenorm_add
adc.f DBL0L,DBL0L,DBL1L
sub r7,DBL1H,DBL0H
sub1 r7,r7,r9 ; boost exponent by 2/2
rrc DBL0L,DBL0L
asr.f r7,r7 ; DBL1.fraction/2 - DBL0.fraction/2 ; exp++
add.cs.f DBL0L,DBL0L,0x80000000
add_l DBL0H,DBL0H,r7 ; DBL0.implicit1 not shifted for DBL1.implicit1
add.cs DBL0H,DBL0H,1
bic.f 0,r9,DBL0H ; check for overflow -> infinity.
jne_l [blink]
and DBL0H,DBL0H,0xfff00000
j_s.d [blink]
mov_s DBL0L,0
.balign 4
.Large_shift:
brhs r12,55,.Lret_dbl0
bmsk_s DBL1H,DBL1H,19
brne r6,0,.Lno_denorm_large_shift
brhi.d r12,33,.Lfixed_denorm_large_shift
sub_s r12,r12,1
breq r12,31, .Lfixed_denorm_small_shift
.Lshift32:
mov_s r12,DBL1L
mov_s DBL1L,DBL1H
brlt.d r10,0,.Lsub
mov_s DBL1H,0
b_s .Ladd
.Ldenorm_add:
cmp_s r12,DBL1L
mov_s DBL0L,r12
j_s.d [blink]
adc DBL0H,r4,DBL1H
.Lret_dbl0:
j_s [blink]
.balign 4
.Lsmall_shift:
breq.d r6,0,.Ldenorm_small_shift
bmsk_s DBL1H,DBL1H,19
bset_s DBL1H,DBL1H,20
.Lfixed_denorm_small_shift:
neg r8,r12
asl r4,DBL1H,r8
lsr_l DBL1H,DBL1H,r12
lsr r5,DBL1L,r12
asl r12,DBL1L,r8
brge.d r10,0,.Ladd
or DBL1L,r4,r5
/* subtract, abs(DBL0) > abs(DBL1) */
/* DBL0H, DBL0L: original values
DBL1H, DBL1L: fraction with explicit leading 1, shifted into place
r4: orig. DBL0H & 0x7fffffff
r6: orig. DBL1H & 0x7ff00000
r9: 0x7ff00000
r10: orig. DBL0H ^ DBL1H
r12: guard bits */
.balign 4
.Lsub:
neg.f r12,r12
mov_s r7,DBL1H
bmsk r5,DBL0H,19
sbc.f DBL0L,DBL0L,DBL1L
bic DBL1H,DBL0H,r5
bset r5,r5,20
sbc.f r4,r5,r7
beq_l .Large_cancel_sub
norm DBL1L,r4
bmsk r6,DBL1H,30
.Lsub_done:
sub_s DBL1L,DBL1L,9
breq DBL1L,1,.Lsub_done_noshift
asl r5,DBL1L,20
sub_s DBL1L,DBL1L,1
brlo r6,r5,.Ldenorm_sub
sub DBL0H,DBL1H,r5
.Lpast_denorm_sub:
neg_s DBL1H,DBL1L
lsr r6,r12,DBL1H
asl_s r12,r12,DBL1L
and r8,r6,1
add1.f 0,r8,r12
add.ne.f r12,r12,r12
asl r8,DBL0L,DBL1L
lsr r12,DBL0L,DBL1H
adc.f DBL0L,r8,r6
asl r5,r4,DBL1L
add_s DBL0H,DBL0H,r12
j_s.d [blink]
adc DBL0H,DBL0H,r5
.balign 4
.Lno_denorm_large_shift:
breq.d r12,32,.Lshift32
bset_l DBL1H,DBL1H,20
.Lfixed_denorm_large_shift:
neg r8,r12
asl r4,DBL1H,r8
lsr r5,DBL1L,r12
asl.f 0,DBL1L,r8
lsr DBL1L,DBL1H,r12
or r12,r4,r5
tst.eq r12,1
or.ne r12,r12,2
brlt.d r10,0,.Lsub
mov_s DBL1H,0
b_l .Ladd
; If a denorm is produced without shifting, we have an exact result -
; no need for rounding.
.balign 4
.Ldenorm_sub:
lsr DBL1L,r6,20
xor DBL0H,r6,DBL1H
brne.d DBL1L,1,.Lpast_denorm_sub
sub_s DBL1L,DBL1L,1
.Lsub_done_noshift:
add.f 0,r12,r12
btst.eq DBL0L,0
cmp.eq r12,r12
add.cs.f DBL0L,DBL0L,1
bclr r4,r4,20
j_s.d [blink]
adc DBL0H,DBL1H,r4
.balign 4
.Ldenorm_small_shift:
brne.d r12,1,.Lfixed_denorm_small_shift
sub_l r12,r12,1
brlt r10,0,.Lsub
.Ladd: ; bit 20 of DBL1H is clear and bit 0 of r12 does not matter
add.f DBL0L,DBL0L,DBL1L
add_s DBL1H,DBL1H,DBL0H
add.cs DBL1H,DBL1H,1
xor_l DBL0H,DBL0H,DBL1H
bbit0 DBL0H,20,.Lno_shiftdown
lsr.f DBL0H,DBL1H
and r4,DBL0L,2
bmsk DBL0H,DBL0H,18
sbc DBL0H,DBL1H,DBL0H
rrc.f DBL0L,DBL0L
or.f r12,r12,r4
cmp.eq r12,r12
add.cs.f DBL0L,DBL0L,1
bic.f 0,r9,DBL0H ; check for generating infinity with possible ...
jne.d [blink] ; ... non-zero fraction
add.cs DBL0H,DBL0H,1
mov_s DBL0L,0
bmsk DBL1H,DBL0H,19
j_s.d [blink]
bic_s DBL0H,DBL0H,DBL1H
.Lno_shiftdown:
mov_s DBL0H,DBL1H
add.f 0,r12,r12
btst.eq DBL0L,0
cmp.eq r12,r12
add.cs.f DBL0L,DBL0L,1
j_s.d [blink]
add.cs DBL0H,DBL0H,1
.balign 4
.Ldenorm:
bmsk DBL0H,DBL1H,30
lsr r12,DBL0H,20
xor_s DBL0H,DBL0H,DBL1H
sub_l DBL1L,r12,1
bgt .Lpast_denorm
j_s.d [blink]
add_l DBL0H,DBL0H,r4
.balign 4
.Large_cancel:
;DBL0L: mantissa DBL1H: sign & exponent
norm.f DBL1L,DBL0L
bmsk DBL0H,DBL1H,30
add_s DBL1L,DBL1L,22
mov.mi DBL1L,21
add_s r12,DBL1L,1
asl_s r12,r12,20
beq_s .Lret0
brhs.d DBL0H,r12,.Lpast_denorm_large_cancel
sub DBL0H,DBL1H,r12
bmsk DBL0H,DBL1H,30
lsr r12,DBL0H,20
xor_s DBL0H,DBL0H,DBL1H
sub.f DBL1L,r12,1
jle [blink]
.Lpast_denorm_large_cancel:
rsub.f r7,DBL1L,32
lsr r7,DBL0L,r7
asl_s DBL0L,DBL0L,DBL1L
mov.ls r7,DBL0L
add_s DBL0H,DBL0H,r7
j_s.d [blink]
mov.ls DBL0L,0
.Lret0:
j_s.d [blink]
mov_l DBL0H,0
/* r4:DBL0L:r12 : unnormalized result fraction
DBL1H: result sign and exponent */
/* When seeing large cancellation, only the topmost guard bit might be set. */
.balign 4
.Large_cancel_sub:
norm.f DBL1L,DBL0L
bpnz.d 0f
bmsk DBL0H,DBL1H,30
mov r5,22<<20
bne.d 1f
mov_s DBL1L,21
bset r5,r5,5+20
add_s DBL1L,DBL1L,32
brne r12,0,1f
j_s.d [blink]
mov_l DBL0H,0
.balign 4
0: add r5,DBL1L,23
asl r5,r5,20
add_s DBL1L,DBL1L,22
1: brlo DBL0H,r5,.Ldenorm_large_cancel_sub
sub DBL0H,DBL1H,r5
.Lpast_denorm_large_cancel_sub:
rsub.f r7,DBL1L,32
lsr r12,r12,r7
lsr r7,DBL0L,r7
asl_s DBL0L,DBL0L,DBL1L
add.ge DBL0H,DBL0H,r7
add_s DBL0L,DBL0L,r12
add.lt DBL0H,DBL0H,DBL0L
mov.eq DBL0L,r12
j_s.d [blink]
mov.lt DBL0L,0
.balign 4
.Ldenorm_large_cancel_sub:
lsr r5,DBL0H,20
xor_s DBL0H,DBL0H,DBL1H
brgt.d r5,1,.Lpast_denorm_large_cancel_sub
sub DBL1L,r5,1
j_l [blink] ; denorm, no shift -> no rounding needed.
/* r4: DBL0H & 0x7fffffff
r6: DBL1H & 0x7ff00000
r9: 0x7ff00000
r10: sign difference
r12: shift count (negative) */
.balign 4
.Ldbl1_gt:
brhs r6,r9,.Lret_dbl1 ; inf or NaN
neg r8,r12
brhs r8,32,.Large_shift_dbl0
.Lsmall_shift_dbl0:
breq.d r6,0,.Ldenorm_small_shift_dbl0
bmsk_s DBL0H,DBL0H,19
bset_s DBL0H,DBL0H,20
.Lfixed_denorm_small_shift_dbl0:
asl r4,DBL0H,r12
lsr DBL0H,DBL0H,r8
lsr r5,DBL0L,r8
asl r12,DBL0L,r12
brge.d r10,0,.Ladd_dbl1_gt
or DBL0L,r4,r5
/* subtract, abs(DBL0) < abs(DBL1) */
/* DBL0H, DBL0L: fraction with explicit leading 1, shifted into place
DBL1H, DBL1L: original values
r6: orig. DBL1H & 0x7ff00000
r9: 0x7ff00000
r12: guard bits */
.balign 4
.Lrsub:
neg.f r12,r12
bmsk r7,DBL1H,19
mov_s r5,DBL0H
sbc.f DBL0L,DBL1L,DBL0L
bic DBL1H,DBL1H,r7
bset r7,r7,20
sbc.f r4,r7,r5
beq_l .Large_cancel_sub
norm DBL1L,r4
b_l .Lsub_done ; note: r6 is already set up.
.Lret_dbl1:
mov_s DBL0H,DBL1H
j_s.d [blink]
mov_l DBL0L,DBL1L
.balign 4
.Ldenorm_small_shift_dbl0:
sub.f r8,r8,1
bne.d .Lfixed_denorm_small_shift_dbl0
add_s r12,r12,1
brlt r10,0,.Lrsub
.Ladd_dbl1_gt: ; bit 20 of DBL0H is clear and bit 0 of r12 does not matter
add.f DBL0L,DBL0L,DBL1L
add_s DBL0H,DBL0H,DBL1H
add.cs DBL0H,DBL0H,1
xor DBL1H,DBL0H,DBL1H
bbit0 DBL1H,20,.Lno_shiftdown_dbl1_gt
lsr.f DBL1H,DBL0H
and r4,DBL0L,2
bmsk DBL1H,DBL1H,18
sbc DBL0H,DBL0H,DBL1H
rrc.f DBL0L,DBL0L
or.f r12,r12,r4
cmp.eq r12,r12
add.cs.f DBL0L,DBL0L,1
bic.f 0,r9,DBL0H ; check for generating infinity with possible ...
jne.d [blink] ; ... non-zero fraction
add.cs DBL0H,DBL0H,1
mov_s DBL0L,0
bmsk DBL1H,DBL0H,19
j_s.d [blink]
bic_s DBL0H,DBL0H,DBL1H
.Lno_shiftdown_dbl1_gt:
add.f 0,r12,r12
btst.eq DBL0L,0
cmp.eq r12,r12
add.cs.f DBL0L,DBL0L,1
j_s.d [blink]
add.cs DBL0H,DBL0H,1
.balign 4
.Large_shift_dbl0:
brhs r8,55,.Lret_dbl1
bmsk_s DBL0H,DBL0H,19
brne r6,0,.Lno_denorm_large_shift_dbl0
add_s r12,r12,1
brne.d r8,33,.Lfixed_denorm_large_shift_dbl0
sub r8,r8,1
bset_s DBL0H,DBL0H,20
.Lshift32_dbl0:
mov_s r12,DBL0L
mov_s DBL0L,DBL0H
brlt.d r10,0,.Lrsub
mov_s DBL0H,0
b_s .Ladd_dbl1_gt
.balign 4
.Lno_denorm_large_shift_dbl0:
breq.d r8,32,.Lshift32_dbl0
bset_l DBL0H,DBL0H,20
.Lfixed_denorm_large_shift_dbl0:
asl r4,DBL0H,r12
lsr r5,DBL0L,r8
asl.f 0,DBL0L,r12
lsr DBL0L,DBL0H,r8
or r12,r4,r5
tst.eq r12,1
or.ne r12,r12,2
brlt.d r10,0,.Lrsub
mov_s DBL0H,0
b_l .Ladd_dbl1_gt
ENDFUNC(__adddf3)
ENDFUNC(__subdf3)
|
4ms/metamodule-plugin-sdk
| 10,887
|
plugin-libc/libgcc/config/arc/ieee-754/arc600-dsp/divdf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
to calculate a := b/x as b*y, with y := 1/x:
- x is in the range [1..2)
- calculate 15..18 bit inverse y0 using a table of approximating polynoms.
Precision is higher for polynoms used to evaluate input with larger
value.
- Do one newton-raphson iteration step to double the precision,
then multiply this with the divisor
-> more time to decide if dividend is subnormal
- the worst error propagation is on the side of the value range
with the least initial defect, thus giving us about 30 bits precision.
The truncation error for the either is less than 1 + x/2 ulp.
A 31 bit inverse can be simply calculated by using x with implicit 1
and chaining the multiplies. For a 32 bit inverse, we multiply y0^2
with the bare fraction part of x, then add in y0^2 for the implicit
1 of x.
- If calculating a 31 bit inverse, the systematic error is less than
-1 ulp; likewise, for 32 bit, it is less than -2 ulp.
- If we calculate our seed with a 32 bit fraction, we can archive a
tentative result strictly better than -2 / +2.5 (1) ulp/128, i.e. we
only need to take the step to calculate the 2nd stage rest and
rounding adjust 1/32th of the time. However, if we use a 20 bit
fraction for the seed, the negative error can exceed -2 ulp/128, (2)
thus for a simple add / tst check, we need to do the 2nd stage
rest calculation/ rounding adjust 1/16th of the time.
(1): The inexactness of the 32 bit inverse contributes an error in the
range of (-1 .. +(1+x/2) ) ulp/128. Leaving out the low word of the
rest contributes an error < +1/x ulp/128 . In the interval [1,2),
x/2 + 1/x <= 1.5 .
(2): Unless proven otherwise. I have not actually looked for an
example where -2 ulp/128 is exceeded, and my calculations indicate
that the excess, if existent, is less than -1/512 ulp.
??? The algorithm is still based on the ARC700 optimized code.
Maybe we could make better use of 32x16 bit multiply, or 64 bit multiply
results.
*/
#include "../arc-ieee-754.h"
#define mlo acc2
#define mhi acc1
#define mul64(b,c) mullw 0,b,c` machlw 0,b,c
#define mulu64(b,c) mululw 0,b,c` machulw 0,b,c
/* N.B. fp-bit.c does double rounding on denormal numbers. */
#if 0 /* DEBUG */
.global __divdf3
FUNC(__divdf3)
.balign 4
__divdf3:
push_s blink
push_s r2
push_s r3
push_s r0
bl.d __divdf3_c
push_s r1
ld_s r2,[sp,12]
ld_s r3,[sp,8]
st_s r0,[sp,12]
st_s r1,[sp,8]
pop_s r1
bl.d __divdf3_asm
pop_s r0
pop_s r3
pop_s r2
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
and r12,DBL0H,DBL1H
bic.f 0,0x7ff80000,r12 ; both NaN -> OK
jeq_s [blink]
bl abort
ENDFUNC(__divdf3)
#define __divdf3 __divdf3_asm
#endif /* DEBUG */
FUNC(__divdf3)
.balign 4
.L7ff00000:
.long 0x7ff00000
.Ldivtab:
.long 0xfc0fffe1
.long 0xf46ffdfb
.long 0xed1ffa54
.long 0xe61ff515
.long 0xdf7fee75
.long 0xd91fe680
.long 0xd2ffdd52
.long 0xcd1fd30c
.long 0xc77fc7cd
.long 0xc21fbbb6
.long 0xbcefaec0
.long 0xb7efa100
.long 0xb32f92bf
.long 0xae8f83b7
.long 0xaa2f7467
.long 0xa5ef6479
.long 0xa1cf53fa
.long 0x9ddf433e
.long 0x9a0f3216
.long 0x965f2091
.long 0x92df0f11
.long 0x8f6efd05
.long 0x8c1eeacc
.long 0x88eed876
.long 0x85dec615
.long 0x82eeb3b9
.long 0x800ea10b
.long 0x7d3e8e0f
.long 0x7a8e7b3f
.long 0x77ee6836
.long 0x756e5576
.long 0x72fe4293
.long 0x709e2f93
.long 0x6e4e1c7f
.long 0x6c0e095e
.long 0x69edf6c5
.long 0x67cde3a5
.long 0x65cdd125
.long 0x63cdbe25
.long 0x61ddab3f
.long 0x600d991f
.long 0x5e3d868c
.long 0x5c6d7384
.long 0x5abd615f
.long 0x590d4ecd
.long 0x576d3c83
.long 0x55dd2a89
.long 0x545d18e9
.long 0x52dd06e9
.long 0x516cf54e
.long 0x4ffce356
.long 0x4e9cd1ce
.long 0x4d3cbfec
.long 0x4becae86
.long 0x4aac9da4
.long 0x496c8c73
.long 0x483c7bd3
.long 0x470c6ae8
.long 0x45dc59af
.long 0x44bc4915
.long 0x43ac3924
.long 0x428c27fb
.long 0x418c187a
.long 0x407c07bd
__divdf3_support: /* This label makes debugger output saner. */
.balign 4
.Ldenorm_dbl1:
brge r6, \
0x43500000,.Linf_NaN ; large number / denorm -> Inf
bmsk.f r12,DBL1H,19
mov.eq r12,DBL1L
mov.eq DBL1L,0
sub.eq r7,r7,32
norm.f r11,r12 ; flag for x/0 -> Inf check
beq_s .Linf_NaN
mov.mi r11,0
add.pl r11,r11,1
add_s r12,r12,r12
asl r8,r12,r11
rsub r12,r11,31
lsr r12,DBL1L,r12
tst_s DBL1H,DBL1H
or r8,r8,r12
lsr r4,r8,26
lsr DBL1H,r8,12
ld.as r4,[r10,r4]
bxor.mi DBL1H,DBL1H,31
sub r11,r11,11
asl DBL1L,DBL1L,r11
sub r11,r11,1
mulu64 (r4,r8)
sub r7,r7,r11
b.d .Lpast_denorm_dbl1
asl r7,r7,20
.Linf_NaN:
tst_s DBL0L,DBL0L ; 0/0 -> NaN
xor_s DBL1H,DBL1H,DBL0H
bclr.eq.f DBL0H,DBL0H,31
bmsk DBL0H,DBL1H,30
xor_s DBL0H,DBL0H,DBL1H
sub.eq DBL0H,DBL0H,1
mov_s DBL0L,0
j_s.d [blink]
or DBL0H,DBL0H,r9
.balign 4
.Lret0_2:
xor_s DBL1H,DBL1H,DBL0H
mov_s DBL0L,0
bmsk DBL0H,DBL1H,30
j_s.d [blink]
xor_s DBL0H,DBL0H,DBL1H
.balign 4
.global __divdf3
/* N.B. the spacing between divtab and the sub3 to get its address must
be a multiple of 8. */
__divdf3:
asl r8,DBL1H,12
lsr r4,r8,26
sub3 r10,pcl,51;(.-.Ldivtab) >> 3
ld.as r9,[pcl,-104]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000
ld.as r4,[r10,r4]
lsr r12,DBL1L,20
and.f r7,DBL1H,r9
or r8,r8,r12
mulu64 (r4,r8)
beq.d .Ldenorm_dbl1
.Lpast_denorm_dbl1:
and.f r6,DBL0H,r9
breq.d r7,r9,.Linf_nan_dbl1
asl r4,r4,12
sub r4,r4,mhi
mululw 0,r4,r4
machulw r5,r4,r4
bne.d .Lnormal_dbl0
lsr r8,r8,1
.balign 4
.Ldenorm_dbl0:
bmsk.f r12,DBL0H,19
; wb stall
mov.eq r12,DBL0L
sub.eq r6,r6,32
norm.f r11,r12 ; flag for 0/x -> 0 check
brge r7, \
0x43500000, .Lret0_2 ; denorm/large number -> 0
beq_s .Lret0_2
mov.mi r11,0
add.pl r11,r11,1
asl r12,r12,r11
sub r6,r6,r11
add.f 0,r6,31
lsr r10,DBL0L,r6
mov.mi r10,0
add r6,r6,11+32
neg.f r11,r6
asl DBL0L,DBL0L,r11
mov.pl DBL0L,0
sub r6,r6,32-1
b.d .Lpast_denorm_dbl0
asl r6,r6,20
.balign 4
.Linf_nan_dbl1: ; 0/Inf -> NaN Inf/Inf -> NaN x/Inf-> 0 x/NaN -> NaN
or.f 0,r6,DBL0L
cmp.ne r6,r9
not_s DBL0L,DBL1H
sub_s.ne DBL0L,DBL0L,DBL0L
tst_s DBL0H,DBL0H
add_s DBL0H,DBL1H,DBL0L
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
.balign 4
.Lnormal_dbl0:
breq.d r6,r9,.Linf_nan_dbl0
asl r12,DBL0H,11
lsr r10,DBL0L,21
.Lpast_denorm_dbl0:
bset r8,r8,31
mulu64 (r5,r8)
add_s r12,r12,r10
bset r5,r12,31
cmp r5,r8
cmp.eq DBL0L,DBL1L
lsr.cc r5,r5,1
sub r4,r4,mhi ; u1.31 inverse, about 30 bit
mululw 0,r5,r4
machulw r11,r5,r4 ; result fraction highpart
lsr r8,r8,2 ; u3.29
add r5,r6, /* wait for immediate */ \
0x3fe00000
mulu64 (r11,r8) ; u-28.31
asl_s DBL1L,DBL1L,9 ; u-29.23:9
sbc r6,r5,r7
mov r12,mlo ; u-28.31
mulu64 (r11,DBL1L) ; mhi: u-28.23:9
add.cs DBL0L,DBL0L,DBL0L
asl_s DBL0L,DBL0L,6 ; u-26.25:7
asl r10,r11,23
sub_l DBL0L,DBL0L,r12
lsr r7,r11,9
sub r5,DBL0L,mhi ; rest msw ; u-26.31:0
mul64 (r5,r4) ; mhi: result fraction lowpart
xor.f 0,DBL0H,DBL1H
and DBL0H,r6,r9
add_s DBL0H,DBL0H,r7
bclr r12,r9,20 ; 0x7fe00000
brhs.d r6,r12,.Linf_denorm
bxor.mi DBL0H,DBL0H,31
add.f r12,mhi,0x11
asr r9,r12,5
sub.mi DBL0H,DBL0H,1
add.f DBL0L,r9,r10
tst r12,0x1c
jne.d [blink]
add.cs DBL0H,DBL0H,1
/* work out exact rounding if we fall through here. */
/* We know that the exact result cannot be represented in double
precision. Find the mid-point between the two nearest
representable values, multiply with the divisor, and check if
the result is larger than the dividend. Since we want to know
only the sign bit, it is sufficient to calculate only the
highpart of the lower 64 bits. */
mulu64 (r11,DBL1L) ; rest before considering r12 in r5 : -mlo
sub.f DBL0L,DBL0L,1
asl r12,r9,2 ; u-22.30:2
sub.cs DBL0H,DBL0H,1
sub.f r12,r12,2
mov r10,mlo ; rest before considering r12 in r5 : -r10
mululw 0,r12,DBL1L
machulw r7,r12,DBL1L ; mhi: u-51.32
asl r5,r5,25 ; s-51.7:25
lsr r10,r10,7 ; u-51.30:2
mulu64 (r12,r8) ; mlo: u-51.31:1
sub r5,r5,r10
add.mi r5,r5,DBL1L ; signed multiply adjust for r12*DBL1L
bset r7,r7,0 ; make sure that the result is not zero, and that
sub r5,r5,r7 ; a highpart zero appears negative
sub.f r5,r5,mlo ; rest msw
add.pl.f DBL0L,DBL0L,1
j_s.d [blink]
add.eq DBL0H,DBL0H,1
.Linf_nan_dbl0:
tst_s DBL1H,DBL1H
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
.balign 4
.Linf_denorm:
lsr r12,r6,28
brlo.d r12,0xc,.Linf
.Ldenorm:
asr r6,r6,20
neg r9,r6
mov_s DBL0H,0
brhs.d r9,54,.Lret0
bxor.mi DBL0H,DBL0H,31
add r12,mhi,1
and r12,r12,-4
rsub r7,r6,5
asr r10,r12,28
bmsk r4,r12,27
min r7,r7,31
asr DBL0L,r4,r7
add DBL1H,r11,r10
abs.f r10,r4
sub.mi r10,r10,1
add.f r7,r6,32-5
asl r4,r4,r7
mov.mi r4,r10
add.f r10,r6,23
rsub r7,r6,9
lsr r7,DBL1H,r7
asl r10,DBL1H,r10
or.pnz DBL0H,DBL0H,r7
or.mi r4,r4,r10
mov.mi r10,r7
add.f DBL0L,r10,DBL0L
add.cs.f DBL0H,DBL0H,1 ; carry clear after this point
bxor.f 0,r4,31
add.pnz.f DBL0L,DBL0L,1
add.cs.f DBL0H,DBL0H,1
jne_s [blink]
/* Calculation so far was not conclusive; calculate further rest. */
mulu64 (r11,DBL1L) ; rest before considering r12 in r5 : -mlo
asr.f r12,r12,3
asl r5,r5,25 ; s-51.7:25
mov r11,mlo ; rest before considering r12 in r5 : -r11
mulu64 (r12,r8) ; u-51.31:1
and r9,DBL0L,1 ; tie-breaker: round to even
lsr r11,r11,7 ; u-51.30:2
mov DBL1H,mlo ; u-51.31:1
mulu64 (r12,DBL1L) ; u-51.62:2
sub.mi r11,r11,DBL1L ; signed multiply adjust for r12*DBL1L
add_s DBL1H,DBL1H,r11
sub DBL1H,DBL1H,r5 ; -rest msw
add_s DBL1H,DBL1H,mhi ; -rest msw
add.f 0,DBL1H,DBL1H ; can't ror.f by 32 :-(
tst_s DBL1H,DBL1H
cmp.eq mlo,r9
add.cs.f DBL0L,DBL0L,1
j_s.d [blink]
add.cs DBL0H,DBL0H,1
.Lret0:
/* return +- 0 */
j_s.d [blink]
mov_s DBL0L,0
.Linf:
mov_s DBL0H,r9
mov_s DBL0L,0
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
ENDFUNC(__divdf3)
|
4ms/metamodule-plugin-sdk
| 3,642
|
plugin-libc/libgcc/config/arc/ieee-754/arc600-dsp/mulsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../arc-ieee-754.h"
#if 0 /* DEBUG */
.global __mulsf3
FUNC(__mulsf3)
.balign 4
__mulsf3:
push_s blink
push_s r1
bl.d __mulsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __mulsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
and r12,r0,r1
bic.f 0,0x7f800000,r12
bne 0f
bmsk.f 0,r0,22
bmsk.ne.f r1,r1,22
jne_s [blink] ; both NaN -> OK
0: bl abort
ENDFUNC(__mulsf3)
#define __mulsf3 __mulsf3_asm
#endif /* DEBUG */
.balign 4
.global __mulsf3
FUNC(__mulsf3)
__mulsf3:
ld.as r9,[pcl,80]; [pcl,((.L7f800000-.+2)/4)]
bmsk r4,r1,22
bset r2,r0,23
asl_s r2,r2,8
bset r3,r4,23
and r11,r0,r9
breq.d r11,0,.Ldenorm_dbl0
and r12,r1,r9
breq.d r12,0,.Ldenorm_dbl1
xor_s r0,r0,r1
mululw 0,r2,r3
machulw r6,r2,r3
breq.d r11,r9,.Linf_nan_dbl0
ld.as r4,[pcl,69]; [pcl,((.L7fffffff-.+2)/4)]
breq.d r12,r9,.Linf_nan_dbl1
.Lpast_denorm:
asl.f 0,r6,8
mov r7,acc2
add.pl r6,r6,r6
bclr.pl r6,r6,23
add.pl.f r7,r7,r7
add.cs r6,r6,1
lsr.f 0,r6,1
add_s r12,r12,r11
adc.f 0,r7,r4
add_s r12,r12, \
-0x3f800000
adc.f r8,r6,r12
tst.pl r8,r9
bic r0,r0,r4
min r3,r8,r9
jpnz.d [blink]
add.pnz r0,r0,r3
; infinity or denormal number
add.ne.f r3,r3,r3
asr_s r3,r3,23+1
bset r6,r6,23
bpnz.d .Linfinity
sub_s r3,r3,1
neg_s r2,r3
brhi.d r2,24,.Lret_r0 ; right shift shift > 24 -> return +-0
lsr r2,r6,r2
asl r9,r6,r3
lsr.f 0,r2,1
tst r7,r7
add_s r0,r0,r2
bset.ne r9,r9,0
adc.f 0,r9,r4
j_s.d [blink]
add.cs r0,r0,1
.Linfinity:
j_s.d [blink]
add_s r0,r0,r9
.Lret_r0: j_s [blink]
.balign 4
.Ldenorm_dbl0:
bclr_s r2,r2,31
norm.f r4,r2
add_s r2,r2,r2
asl r2,r2,r4
breq.d r12,r9,.Ldenorm_dbl0_inf_nan_dbl1
asl r4,r4,23
mululw 0,r2,r3
machulw r6,r2,r3
sub.ne.f r12,r12,r4
ld.as r4,[pcl,28]; [pcl,((.L7fffffff-.+2)/4)]
bhi.d .Lpast_denorm
xor_s r0,r0,r1
bmsk r1,r0,30
j_s.d [blink]
bic_s r0,r0,r1
.balign 4
.Ldenorm_dbl0_inf_nan_dbl1:
bmsk.f 0,r0,30
mov.eq r1,-1
.Linf_nan_dbl1:
xor_s r1,r1,r0
.Linf_nan_dbl0:
bclr_s r1,r1,31
j_s.d [blink]
xor_s r0,r0,r1
.balign 4
.Ldenorm_dbl1:
breq.d r11,r9,.Linf_nan_dbl0_2
norm.f r3,r4
sub_s r3,r3,7
asl r4,r4,r3
mululw 0,r2,r4
machulw r6,r2,r4
sub_s r3,r3,1
asl_s r3,r3,23
sub.ne.f r11,r11,r3
ld.as r4,[pcl,11]; [pcl,((.L7fffffff-.+2)/4)]
bhi.d .Lpast_denorm
bmsk r8,r0,30
j_s.d [blink]
bic r0,r0,r8
.balign 4
.Linf_nan_dbl0_2:
bclr_s r1,r1,31
xor_s r0,r0,r1
sub.eq r1,r1,1 ; inf/nan * 0 -> nan
bic.f 0,r9,r1
j_s.d [blink]
or.eq r0,r0,r1 ; r1 nan -> result nan
.balign 4
.L7f800000:
.long 0x7f800000
.L7fffffff:
.long 0x7fffffff
ENDFUNC(__mulsf3)
|
4ms/metamodule-plugin-sdk
| 5,318
|
plugin-libc/libgcc/config/arc/ieee-754/arc600-dsp/muldf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../arc-ieee-754.h"
#if 0 /* DEBUG */
.global __muldf3
.balign 4
__muldf3:
push_s blink
push_s r2
push_s r3
push_s r0
bl.d __muldf3_c
push_s r1
ld_s r2,[sp,12]
ld_s r3,[sp,8]
st_s r0,[sp,12]
st_s r1,[sp,8]
pop_s r1
bl.d __muldf3_asm
pop_s r0
pop_s r3
pop_s r2
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
b abort
#define __muldf3 __muldf3_asm
#endif /* DEBUG */
__muldf3_support: /* This label makes debugger output saner. */
.balign 4
FUNC(__muldf3)
.Ldenorm_2:
breq.d DBL1L,0,.Lret0_2 ; 0 input -> 0 output
norm.f r12,DBL1L
mov.mi r12,21
add.pl r12,r12,22
neg r11,r12
asl_s r12,r12,20
lsr.f DBL1H,DBL1L,r11
ror DBL1L,DBL1L,r11
sub_s DBL0H,DBL0H,r12
mov.eq DBL1H,DBL1L
sub_l DBL1L,DBL1L,DBL1H
/* Fall through. */
.global __muldf3
.balign 4
__muldf3:
mululw 0,DBL0L,DBL1L
machulw r4,DBL0L,DBL1L
ld.as r9,[pcl,0x67] ; ((.L7ff00000-.+2)/4)]
bmsk r6,DBL0H,19
bset r6,r6,20
mov r8,acc2
mululw 0,r4,1
and r11,DBL0H,r9
breq.d r11,0,.Ldenorm_dbl0
and r12,DBL1H,r9
breq.d r12,0,.Ldenorm_dbl1
maclw 0,r6,DBL1L
machulw 0,r6,DBL1L
breq.d r11,r9,.Linf_nan
bmsk r10,DBL1H,19
breq.d r12,r9,.Linf_nan
bset r10,r10,20
maclw 0,r10,DBL0L
machulw r5,r10,DBL0L
add_s r12,r12,r11 ; add exponents
mov r4,acc2
mululw 0,r5,1
maclw 0,r6,r10
machulw r7,r6,r10 ; fraction product in r7:acc2:r4:r8
tst r8,r8
bclr r8,r9,30 ; 0x3ff00000
bset.ne r4,r4,0 ; put least significant word into sticky bit
bclr r6,r9,20 ; 0x7fe00000
lsr.f r10,r7,9
rsub.eq r8,r8,r9 ; 0x40000000
sub r12,r12,r8 ; subtract bias + implicit 1
brhs.d r12,r6,.Linf_denorm
rsub r10,r10,12
.Lshift_frac:
neg r8,r10
asl r6,r4,r10
lsr DBL0L,r4,r8
add.f 0,r6,r6
btst.eq DBL0L,0
cmp.eq r4,r4 ; round to nearest / round to even
asl r4,acc2,r10
lsr r5,acc2,r8
adc.f DBL0L,DBL0L,r4
xor.f 0,DBL0H,DBL1H
asl r7,r7,r10
add_s r12,r12,r5
adc DBL0H,r12,r7
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
/* N.B. This is optimized for ARC700.
ARC600 has very different scheduling / instruction selection criteria. */
/* If one number is denormal, subtract some from the exponent of the other
one (if the other exponent is too small, return 0), and normalize the
denormal. Then re-run the computation. */
.Lret0_2:
lsr_s DBL0H,DBL0H,31
asl_s DBL0H,DBL0H,31
j_s.d [blink]
mov_s DBL0L,0
.balign 4
.Ldenorm_dbl0:
mov_s r12,DBL0L
mov_s DBL0L,DBL1L
mov_s DBL1L,r12
mov_s r12,DBL0H
mov_s DBL0H,DBL1H
mov_s DBL1H,r12
and r11,DBL0H,r9
.Ldenorm_dbl1:
brhs r11,r9,.Linf_nan
brhs 0x3ca00001,r11,.Lret0
sub_s DBL0H,DBL0H,DBL1H
bmsk.f DBL1H,DBL1H,30
add_s DBL0H,DBL0H,DBL1H
beq.d .Ldenorm_2
norm r12,DBL1H
sub_s r12,r12,10
asl r5,r12,20
asl_s DBL1H,DBL1H,r12
sub DBL0H,DBL0H,r5
neg r5,r12
lsr r6,DBL1L,r5
asl_s DBL1L,DBL1L,r12
b.d __muldf3
add_s DBL1H,DBL1H,r6
.Lret0: xor_s DBL0H,DBL0H,DBL1H
bclr DBL1H,DBL0H,31
xor_s DBL0H,DBL0H,DBL1H
j_s.d [blink]
mov_s DBL0L,0
.balign 4
.Linf_nan:
bclr r12,DBL1H,31
xor_s DBL1H,DBL1H,DBL0H
bclr_s DBL0H,DBL0H,31
max r8,DBL0H,r12 ; either NaN -> NaN ; otherwise inf
or.f 0,DBL0H,DBL0L
mov_s DBL0L,0
or.ne.f DBL1L,DBL1L,r12
not_s DBL0H,DBL0L ; inf * 0 -> NaN
mov.ne DBL0H,r8
tst_s DBL1H,DBL1H
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
/* We have checked for infinity / NaN input before, and transformed
denormalized inputs into normalized inputs. Thus, the worst case
exponent overflows are:
1 + 1 - 0x400 == 0xc02 : maximum underflow
0x7fe + 0x7fe - 0x3ff == 0xbfd ; maximum overflow
N.B. 0x7e and 0x7f are also values for overflow.
If (r12 <= -54), we have an underflow to zero. */
.balign 4
.Linf_denorm:
lsr r6,r12,28
brlo.d r6,0xc,.Linf
asr r6,r12,20
add.f r10,r10,r6
brgt.d r10,0,.Lshift_frac
mov_s r12,0
beq.d .Lround_frac
add r10,r10,32
.Lshift32_frac:
tst r4,r4
mov r4,acc2
bset.ne r4,r4,1
mululw 0,r7,1
brge.d r10,1,.Lshift_frac
mov r7,0
breq.d r10,0,.Lround_frac
add r10,r10,32
brgt r10,21,.Lshift32_frac
b_s .Lret0
.Lround_frac:
add.f 0,r4,r4
btst.eq acc2,0
mov_s DBL0L,acc2
mov_s DBL0H,r7
adc.eq.f DBL0L,DBL0L,0
j_s.d [blink]
adc.eq DBL0H,DBL0H,0
.Linf: mov_s DBL0L,0
xor.f DBL1H,DBL1H,DBL0H
mov_s DBL0H,r9
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
ENDFUNC(__muldf3)
.balign 4
.L7ff00000:
.long 0x7ff00000
|
4ms/metamodule-plugin-sdk
| 6,363
|
plugin-libc/libgcc/config/arc/ieee-754/arc600-dsp/divsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
- calculate 15..18 bit inverse using a table of approximating polynoms.
precision is higher for polynoms used to evaluate input with larger
value.
- do one newton-raphson iteration step to double the precision,
then multiply this with the divisor
-> more time to decide if dividend is subnormal
- the worst error propagation is on the side of the value range
with the least initial defect, thus giving us about 30 bits precision.
*/
#include "../arc-ieee-754.h"
#define mlo acc2
#define mhi acc1
#define mul64(b,c) mullw 0,b,c` machlw 0,b,c
#define mulu64(b,c) mululw 0,b,c` machulw 0,b,c
#if 0 /* DEBUG */
.global __divsf3
FUNC(__divsf3)
.balign 4
__divsf3:
push_s blink
push_s r1
bl.d __divsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __divsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
#if 1
bne abort
jeq_s [blink]
b abort
#else
bne abort
j_s [blink]
#endif
ENDFUNC(__divsf3)
#define __divsf3 __divsf3_asm
#endif /* DEBUG */
FUNC(__divsf3)
.balign 4
.Ldivtab:
.long 0xfc0ffff0
.long 0xf46ffefd
.long 0xed1ffd2a
.long 0xe627fa8e
.long 0xdf7ff73b
.long 0xd917f33b
.long 0xd2f7eea3
.long 0xcd1fe986
.long 0xc77fe3e7
.long 0xc21fdddb
.long 0xbcefd760
.long 0xb7f7d08c
.long 0xb32fc960
.long 0xae97c1ea
.long 0xaa27ba26
.long 0xa5e7b22e
.long 0xa1cfa9fe
.long 0x9ddfa1a0
.long 0x9a0f990c
.long 0x9667905d
.long 0x92df878a
.long 0x8f6f7e84
.long 0x8c27757e
.long 0x88f76c54
.long 0x85df630c
.long 0x82e759c5
.long 0x8007506d
.long 0x7d3f470a
.long 0x7a8f3da2
.long 0x77ef341e
.long 0x756f2abe
.long 0x72f7212d
.long 0x709717ad
.long 0x6e4f0e44
.long 0x6c1704d6
.long 0x69e6fb44
.long 0x67cef1d7
.long 0x65c6e872
.long 0x63cedf18
.long 0x61e6d5cd
.long 0x6006cc6d
.long 0x5e36c323
.long 0x5c76b9f3
.long 0x5abeb0b7
.long 0x5916a79b
.long 0x57769e77
.long 0x55de954d
.long 0x54568c4e
.long 0x52d6834d
.long 0x51667a7f
.long 0x4ffe71b5
.long 0x4e9e68f1
.long 0x4d466035
.long 0x4bf65784
.long 0x4aae4ede
.long 0x496e4646
.long 0x48363dbd
.long 0x47063547
.long 0x45de2ce5
.long 0x44be2498
.long 0x43a61c64
.long 0x4296144a
.long 0x41860c0e
.long 0x407e03ee
.L7f800000:
.long 0x7f800000
.balign 4
.global __divsf3_support
__divsf3_support:
.Linf_NaN:
bclr.f 0,r0,31 ; 0/0 -> NaN
xor_s r0,r0,r1
bmsk r1,r0,30
bic_s r0,r0,r1
sub.eq r0,r0,1
j_s.d [blink]
or r0,r0,r9
.Lret0:
xor_s r0,r0,r1
bmsk r1,r0,30
j_s.d [blink]
bic_s r0,r0,r1
/* N.B. the spacing between divtab and the sub3 to get its address must
be a multiple of 8. */
__divsf3:
ld.as r9,[pcl,-9]; [pcl,(-((.-.L7f800000) >> 2))] ; 0x7f800000
sub3 r3,pcl,37;(.-.Ldivtab) >> 3
lsr r2,r1,17
and.f r11,r1,r9
bmsk r5,r2,5
beq.d .Ldenorm_fp1
asl r6,r1,8
and.f r2,r0,r9
ld.as r5,[r3,r5]
asl r4,r1,9
bset r6,r6,31
breq.d r11,r9,.Linf_nan_fp1
.Lpast_denorm_fp1:
mululw 0,r5,r4
machulw r8,r5,r4
breq.d r2,r9,.Linf_nan_fp0
asl r5,r5,13
sub r7,r5,r8
mululw 0,r7,r6
machulw r8,r7,r6
beq.d .Ldenorm_fp0
asl r12,r0,8
mulu64 (r8,r7)
bset r3,r12,31
.Lpast_denorm_fp0:
cmp_s r3,r6
lsr.cc r3,r3,1
add_s r2,r2, /* wait for immediate */ \
0x3f000000
sub r7,r7,mhi ; u1.31 inverse, about 30 bit
mulu64 (r3,r7)
sbc r2,r2,r11
xor.f 0,r0,r1
and r0,r2,r9
bclr r3,r9,23 ; 0x7f000000
brhs.d r2,r3,.Linf_denorm
bxor.mi r0,r0,31
.Lpast_denorm:
add r3,mhi,0x22 ; round to nearest or higher
tst r3,0x3c ; check if rounding was unsafe
lsr r3,r3,6
jne.d [blink] ; return if rounding was safe.
add_s r0,r0,r3
/* work out exact rounding if we fall through here. */
/* We know that the exact result cannot be represented in single
precision. Find the mid-point between the two nearest
representable values, multiply with the divisor, and check if
the result is larger than the dividend. */
add_s r3,r3,r3
sub_s r3,r3,1
mulu64 (r3,r6)
asr.f 0,r0,1 ; for round-to-even in case this is a denorm
rsub r2,r9,25
asl_s r12,r12,r2
sub.f 0,r12,mlo
j_s.d [blink]
sub.mi r0,r0,1
.Linf_nan_fp1:
lsr_s r0,r0,31
bmsk.f 0,r1,22
asl_s r0,r0,31
bne_s 0f ; inf/inf -> nan
brne r2,r9,.Lsigned0 ; x/inf -> 0, but x/nan -> nan
0: j_s.d [blink]
mov r0,-1
.Lsigned0:
.Linf_nan_fp0:
tst_s r1,r1
j_s.d [blink]
bxor.mi r0,r0,31
.balign 4
.global __divsf3
/* For denormal results, it is possible that an exact result needs
rounding, and thus the round-to-even rule has to come into play. */
.Linf_denorm:
brlo r2,0xc0000000,.Linf
.Ldenorm:
asr_s r2,r2,23
bic r0,r0,r9
neg r9,r2
brlo.d r9,25,.Lpast_denorm
lsr r3,mlo,r9
/* Fall through: return +- 0 */
j_s [blink]
.Linf:
j_s.d [blink]
or r0,r0,r9
.balign 4
.Ldenorm_fp1:
norm.f r12,r6 ; flag for x/0 -> Inf check
add r6,r6,r6
rsub r5,r12,16
ror r5,r1,r5
bmsk r5,r5,5
bic.ne.f 0, \
0x60000000,r0 ; large number / denorm -> Inf
ld.as r5,[r3,r5]
asl r6,r6,r12
beq.d .Linf_NaN
and.f r2,r0,r9
add r4,r6,r6
asl_s r12,r12,23
bne.d .Lpast_denorm_fp1
add_s r2,r2,r12
.Ldenorm_fp0:
mulu64 (r8,r7)
bclr r12,r12,31
norm.f r3,r12 ; flag for 0/x -> 0 check
bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0
beq_s .Lret0
asl_s r12,r12,r3
asl_s r3,r3,23
add_s r12,r12,r12
add r11,r11,r3
b.d .Lpast_denorm_fp0
mov_s r3,r12
ENDFUNC(__divsf3)
|
4ms/metamodule-plugin-sdk
| 3,744
|
plugin-libc/libgcc/config/arc/ieee-754/arc600/mulsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../arc-ieee-754.h"
#if 0 /* DEBUG */
.global __mulsf3
FUNC(__mulsf3)
.balign 4
__mulsf3:
push_s blink
push_s r1
bl.d __mulsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __mulsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
and r12,r0,r1
bic.f 0,0x7f800000,r12
bne 0f
bmsk.f 0,r0,22
bmsk.ne.f r1,r1,22
jne_s [blink] ; both NaN -> OK
0: bl abort
ENDFUNC(__mulsf3)
#define __mulsf3 __mulsf3_asm
#endif /* DEBUG */
.balign 4
.global __mulsf3
FUNC(__mulsf3)
__mulsf3:
ld.as r9,[pcl,76]; [pcl,((.L7f800000-.+2)/4)]
bmsk r4,r1,22
bset r3,r4,23
bmsk r2,r0,22
and r11,r0,r9
breq.d r11,0,.Ldenorm_dbl0
and r12,r1,r9
xor_s r0,r0,r1
breq.d r11,r9,.Linf_nan_dbl0
bset_s r2,r2,23
breq r12,0,.Ldenorm_dbl1
breq r12,r9,.Linf_nan_dbl1
.Lpast_denorm:
mov r6,0
lsr.f r7,r2
; We could so this a bit faster here with a 32 bit shift register and
; inserting the r2 factor / retrieving the low result a byte at a time,
; but that'd increase code size.
mov lp_count,24
.balign 4
lp 0f
add.cs r6,r6,r3
lsr.f r6,r6
rrc.f r7,r7
0:
ld.as r4,[pcl,59]; [pcl,((.L7fffffff-.+2)/4)]
asl.f 0,r6,8
add.pl r6,r6,r6
bclr.pl r6,r6,23
add.pl.f r7,r7,r7
add.cs r6,r6,1
lsr.f 0,r6,1
add_s r12,r12,r11
adc.f 0,r7,r4
add_s r12,r12, \
-0x3f800000
adc.f r8,r6,r12
tst.pl r8,r9
bic r0,r0,r4
min r3,r8,r9
jpnz.d [blink]
add.pnz r0,r0,r3
; infinity or denormal number
add.ne.f r3,r3,r3
asr_s r3,r3,23+1
bset r6,r6,23
bpnz.d .Linfinity
sub_s r3,r3,1
neg_s r2,r3
brhi.d r2,24,.Lret_r0 ; right shift shift > 24 -> return +-0
lsr r2,r6,r2
asl r9,r6,r3
lsr.f 0,r2,1
tst r7,r7
add_s r0,r0,r2
bset.ne r9,r9,0
adc.f 0,r9,r4
j_s.d [blink]
add.cs r0,r0,1
.Linfinity:
j_s.d [blink]
add_s r0,r0,r9
.Lret_r0: j_s [blink]
.balign 4
.Ldenorm_dbl0:
asl_s r2,r2,8
norm.f r4,r2
lsr_s r2,r2,7
asl r2,r2,r4
breq.d r12,r9,.Ldenorm_dbl0_inf_nan_dbl1
asl r4,r4,23
sub.ne.f r12,r12,r4
bhi.d .Lpast_denorm
xor_s r0,r0,r1
bmsk r1,r0,30
j_s.d [blink]
bic_s r0,r0,r1
.balign 4
.Ldenorm_dbl0_inf_nan_dbl1:
bmsk.f 0,r0,30
beq_s .Lretnan
xor_s r0,r0,r1
.Linf_nan_dbl1:
xor_s r1,r1,r0
bclr_s r1,r1,31
j_s.d [blink]
xor_s r0,r0,r1
.Linf_nan_dbl0:
sub_s r2,r1,1 ; inf/nan * 0 -> nan; inf * nan -> nan (use |r2| >= inf)
bic.f 0,r9,r2
xor_s r0,r0,r1
bclr_s r1,r1,31
xor_s r0,r0,r1
jne_s [blink]
.Lretnan:
j_s.d [blink]
mov r0,-1
.balign 4
.Ldenorm_dbl1:
norm.f r3,r4
sub_s r3,r3,7
asl r4,r4,r3
sub_s r3,r3,1
asl_s r3,r3,23
sub.ne.f r11,r11,r3
bhi.d .Lpast_denorm
mov_s r3,r4
bmsk r3,r0,30
j_s.d [blink]
bic_s r0,r0,r3
.balign 4
.L7f800000:
.long 0x7f800000
.L7fffffff:
.long 0x7fffffff
ENDFUNC(__mulsf3)
|
4ms/metamodule-plugin-sdk
| 5,136
|
plugin-libc/libgcc/config/arc/ieee-754/arc600/divsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../arc-ieee-754.h"
#if 0 /* DEBUG */
.global __divsf3
FUNC(__divsf3)
.balign 4
__divsf3:
push_s blink
push_s r1
bl.d __divsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __divsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
and r12,r0,r1
bic.f 0,0x7f800000,r12 ; both NaN -> OK
jeq_s [blink]
bl abort
ENDFUNC(__divsf3)
#define __divsf3 __divsf3_asm
#endif /* DEBUG */
.balign 4
__divdf3_support: /* This label makes debugger output saner. */
FUNC(__divsf3)
.Ldenorm_fp0:
norm.f r12,r2 ; flag for 0/x -> 0 check
bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0
beq_s .Lret0_NaN
tst r1,r9
add_s r2,r2,r2
sub_s r12,r12,8
asl_s r2,r2,r12
asl_l r12,r12,23
bne.d .Lpast_denorm_fp0
add r5,r5,r12
/* r0 is subnormal, r1 is subnormal or 0. */
.balign 4
.Ldenorm_fp1:
norm.f r12,r3 ; flag for x/0 -> Inf check
bic.ne.f 0,0x60000000,r0 ; large number/denorm -> Inf
beq_s .Linf
add_s r3,r3,r3
sub_s r12,r12,8
asl_s r3,r3,r12
asl_s r12,r12,23
b.d .Lpast_denorm_fp1
add r4,r4,r12
.Lret0_NaN:
bclr.f 0,r1,31 ; 0/0 -> NaN
bic r0,r10,r9
j_s.d [blink]
sub.eq r0,r0,1
.balign 4
.Linf_nan_fp0:
bic.f 0,r9,r1 ; fp1 Inf -> result NaN
bic r1,r5,r9 ; fp1 sign
sub.eq r1,r1,1
j_s.d [blink]
xor_s r0,r0,r1
.Linf_nan_fp1:
bic r0,r4,r9 ; fp0 sign
bmsk.f 0,r1,22 ; x/inf -> 0, x/nan -> nan
xor.eq r1,r1,r9
j_s.d [blink]
xor_s r0,r0,r1
.global __divsf3
.balign 4
.long 0x7f800000 ; exponent mask
__divsf3:
ld r9,[pcl,-4]
bmsk r2,r0,22
xor r4,r0,r2
bmsk r3,r1,22
xor r5,r1,r3
and r11,r0,r9
breq.d r11,0,.Ldenorm_fp0
xor r10,r4,r5
breq r11,r9,.Linf_nan_fp0
bset_s r2,r2,23
and r11,r1,r9
breq r11,0,.Ldenorm_fp1
breq r11,r9,.Linf_nan_fp1
.Lpast_denorm_fp0:
bset_s r3,r3,23
.Lpast_denorm_fp1:
cmp r2,r3
asl_s r2,r2,6+1
asl_s r3,r3,7
add.lo r2,r2,r2
bclr r8,r9,30 ; exponent bias
bclr.lo r8,r8,23 ; reduce exp by one if fraction is shifted
sub r4,r4,r5
add r4,r4,r8
xor.f 0,r10,r4
bmi .Linf_denorm
and.f r12,r4,r9
beq .Ldenorm
sub_s r2,r2,r3 ; discard implicit 1
rsub r3,r3,1 ; prime r3 for two-insn divide-step use
.Ldiv_23bit:
.rep 6
add1.f r2,r3,r2
sub.cc r2,r2,r3
.endr
breq r12,r9,.Linf
bmsk r0,r2,6
xor_s r2,r2,r0
.Ldiv_17bit:
.rep 7
add1.f r2,r3,r2
sub.cc r2,r2,r3
.endr
asl_s r0,r0,7
bmsk r1,r2,6
xor_s r2,r2,r1
or_s r0,r0,r1
.Ldiv_10bit:
.rep 7
add1.f r2,r3,r2
sub.cc r2,r2,r3
.endr
asl_s r0,r0,7
bmsk r1,r2,6
xor_s r2,r2,r1
or_s r0,r0,r1
.Ldiv_3bit:
.rep 3
add1.f r2,r3,r2
sub.cc r2,r2,r3
.endr
asl_s r0,r0,3
.Ldiv_0bit:
add1.f r1,r3,r2
sub.cc r1,r1,r3
bmsk_s r2,r2,2
tst r1,-0x7e ; 0xffffff82, test for rest or odd
bmsk_s r1,r1,0
add_s r0,r0,r2 ; assemble fraction
add_s r0,r0,r4 ; add in sign & exponent
j_s.d [blink]
add.ne r0,r0,r1 ; round to nearest / even
.balign 4
.Linf:
j_s.d [blink]
or r0,r10,r9
.Lret_r4:
j_s.d [blink]
mov_s r0,r4
.balign 4
.Linf_denorm:
add.f r12,r4,r4
asr_l r12,r12,24
bpl .Linf
max r12,r12,-24
.Ldenorm:
rsub r3,r3,1
add r1,pcl,68; .Ldenorm_tab-.
ldw.as r12,[r1,r12]
mov_s r0,0
lsr_s r2,r2
sub_s r1,r1,r12
j_s.d [r1]
bic r4,r10,r9
.short .Ldenorm_tab-.Lret_r4
.short .Ldenorm_tab-.Ldiv_0bit
.short .Ldenorm_tab-.Ldiv_3bit-2*8
.short .Ldenorm_tab-.Ldiv_3bit-1*8
.short .Ldenorm_tab-.Ldiv_3bit
.short .Ldenorm_tab-.Ldiv_10bit-6*8
.short .Ldenorm_tab-.Ldiv_10bit-5*8
.short .Ldenorm_tab-.Ldiv_10bit-3*8
.short .Ldenorm_tab-.Ldiv_10bit-3*8
.short .Ldenorm_tab-.Ldiv_10bit-2*8
.short .Ldenorm_tab-.Ldiv_10bit-1*8
.short .Ldenorm_tab-.Ldiv_10bit
.short .Ldenorm_tab-.Ldiv_17bit-6*8
.short .Ldenorm_tab-.Ldiv_17bit-5*8
.short .Ldenorm_tab-.Ldiv_17bit-4*8
.short .Ldenorm_tab-.Ldiv_17bit-3*8
.short .Ldenorm_tab-.Ldiv_17bit-2*8
.short .Ldenorm_tab-.Ldiv_17bit-1*8
.short .Ldenorm_tab-.Ldiv_17bit
.short .Ldenorm_tab-.Ldiv_23bit-5*8
.short .Ldenorm_tab-.Ldiv_23bit-4*8
.short .Ldenorm_tab-.Ldiv_23bit-3*8
.short .Ldenorm_tab-.Ldiv_23bit-2*8
.short .Ldenorm_tab-.Ldiv_23bit-1*8
.Ldenorm_tab:
.short .Ldenorm_tab-.Ldiv_23bit
ENDFUNC(__divsf3)
|
4ms/metamodule-plugin-sdk
| 10,684
|
plugin-libc/libgcc/config/arc/ieee-754/arc600-mul64/divdf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
to calculate a := b/x as b*y, with y := 1/x:
- x is in the range [1..2)
- calculate 15..18 bit inverse y0 using a table of approximating polynoms.
Precision is higher for polynoms used to evaluate input with larger
value.
- Do one newton-raphson iteration step to double the precision,
then multiply this with the divisor
-> more time to decide if dividend is subnormal
- the worst error propagation is on the side of the value range
with the least initial defect, thus giving us about 30 bits precision.
The truncation error for the either is less than 1 + x/2 ulp.
A 31 bit inverse can be simply calculated by using x with implicit 1
and chaining the multiplies. For a 32 bit inverse, we multiply y0^2
with the bare fraction part of x, then add in y0^2 for the implicit
1 of x.
- If calculating a 31 bit inverse, the systematic error is less than
-1 ulp; likewise, for 32 bit, it is less than -2 ulp.
- If we calculate our seed with a 32 bit fraction, we can archive a
tentative result strictly better than -2 / +2.5 (1) ulp/128, i.e. we
only need to take the step to calculate the 2nd stage rest and
rounding adjust 1/32th of the time. However, if we use a 20 bit
fraction for the seed, the negative error can exceed -2 ulp/128, (2)
thus for a simple add / tst check, we need to do the 2nd stage
rest calculation/ rounding adjust 1/16th of the time.
(1): The inexactness of the 32 bit inverse contributes an error in the
range of (-1 .. +(1+x/2) ) ulp/128. Leaving out the low word of the
rest contributes an error < +1/x ulp/128 . In the interval [1,2),
x/2 + 1/x <= 1.5 .
(2): Unless proven otherwise. I have not actually looked for an
example where -2 ulp/128 is exceeded, and my calculations indicate
that the excess, if existent, is less than -1/512 ulp.
??? The algorithm is still based on the ARC700 optimized code.
Maybe we could make better use of 64 bit multiply results and/or mmed .
*/
#include "../arc-ieee-754.h"
/* N.B. fp-bit.c does double rounding on denormal numbers. */
#if 0 /* DEBUG */
.global __divdf3
FUNC(__divdf3)
.balign 4
__divdf3:
push_s blink
push_s r2
push_s r3
push_s r0
bl.d __divdf3_c
push_s r1
ld_s r2,[sp,12]
ld_s r3,[sp,8]
st_s r0,[sp,12]
st_s r1,[sp,8]
pop_s r1
bl.d __divdf3_asm
pop_s r0
pop_s r3
pop_s r2
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
and r12,DBL0H,DBL1H
bic.f 0,0x7ff80000,r12 ; both NaN -> OK
jeq_s [blink]
bl abort
ENDFUNC(__divdf3)
#define __divdf3 __divdf3_asm
#endif /* DEBUG */
FUNC(__divdf3)
.balign 4
.L7ff00000:
.long 0x7ff00000
.Ldivtab:
.long 0xfc0fffe1
.long 0xf46ffdfb
.long 0xed1ffa54
.long 0xe61ff515
.long 0xdf7fee75
.long 0xd91fe680
.long 0xd2ffdd52
.long 0xcd1fd30c
.long 0xc77fc7cd
.long 0xc21fbbb6
.long 0xbcefaec0
.long 0xb7efa100
.long 0xb32f92bf
.long 0xae8f83b7
.long 0xaa2f7467
.long 0xa5ef6479
.long 0xa1cf53fa
.long 0x9ddf433e
.long 0x9a0f3216
.long 0x965f2091
.long 0x92df0f11
.long 0x8f6efd05
.long 0x8c1eeacc
.long 0x88eed876
.long 0x85dec615
.long 0x82eeb3b9
.long 0x800ea10b
.long 0x7d3e8e0f
.long 0x7a8e7b3f
.long 0x77ee6836
.long 0x756e5576
.long 0x72fe4293
.long 0x709e2f93
.long 0x6e4e1c7f
.long 0x6c0e095e
.long 0x69edf6c5
.long 0x67cde3a5
.long 0x65cdd125
.long 0x63cdbe25
.long 0x61ddab3f
.long 0x600d991f
.long 0x5e3d868c
.long 0x5c6d7384
.long 0x5abd615f
.long 0x590d4ecd
.long 0x576d3c83
.long 0x55dd2a89
.long 0x545d18e9
.long 0x52dd06e9
.long 0x516cf54e
.long 0x4ffce356
.long 0x4e9cd1ce
.long 0x4d3cbfec
.long 0x4becae86
.long 0x4aac9da4
.long 0x496c8c73
.long 0x483c7bd3
.long 0x470c6ae8
.long 0x45dc59af
.long 0x44bc4915
.long 0x43ac3924
.long 0x428c27fb
.long 0x418c187a
.long 0x407c07bd
__divdf3_support: /* This label makes debugger output saner. */
.balign 4
.Ldenorm_dbl1:
brge r6, \
0x43500000,.Linf_NaN ; large number / denorm -> Inf
bmsk.f r12,DBL1H,19
mov.eq r12,DBL1L
mov.eq DBL1L,0
sub.eq r7,r7,32
norm.f r11,r12 ; flag for x/0 -> Inf check
beq_s .Linf_NaN
mov.mi r11,0
add.pl r11,r11,1
add_s r12,r12,r12
asl r8,r12,r11
rsub r12,r11,31
lsr r12,DBL1L,r12
tst_s DBL1H,DBL1H
or r8,r8,r12
lsr r4,r8,26
lsr DBL1H,r8,12
ld.as r4,[r10,r4]
bxor.mi DBL1H,DBL1H,31
sub r11,r11,11
asl DBL1L,DBL1L,r11
sub r11,r11,1
mulu64 r4,r8
sub r7,r7,r11
b.d .Lpast_denorm_dbl1
asl r7,r7,20
.balign 4
.Ldenorm_dbl0:
bmsk.f r12,DBL0H,19
; wb stall
mov.eq r12,DBL0L
sub.eq r6,r6,32
norm.f r11,r12 ; flag for 0/x -> 0 check
brge r7, \
0x43500000, .Lret0_2 ; denorm/large number -> 0
beq_s .Lret0_2
mov.mi r11,0
add.pl r11,r11,1
asl r12,r12,r11
sub r6,r6,r11
add.f 0,r6,31
lsr r10,DBL0L,r6
mov.mi r10,0
add r6,r6,11+32
neg.f r11,r6
asl DBL0L,DBL0L,r11
mov.pl DBL0L,0
sub r6,r6,32-1
b.d .Lpast_denorm_dbl0
asl r6,r6,20
.Linf_NaN:
tst_s DBL0L,DBL0L ; 0/0 -> NaN
xor_s DBL1H,DBL1H,DBL0H
bclr.eq.f DBL0H,DBL0H,31
bmsk DBL0H,DBL1H,30
xor_s DBL0H,DBL0H,DBL1H
sub.eq DBL0H,DBL0H,1
mov_s DBL0L,0
j_s.d [blink]
or DBL0H,DBL0H,r9
.balign 4
.Lret0_2:
xor_s DBL1H,DBL1H,DBL0H
mov_s DBL0L,0
bmsk DBL0H,DBL1H,30
j_s.d [blink]
xor_s DBL0H,DBL0H,DBL1H
.balign 4
.global __divdf3
/* N.B. the spacing between divtab and the sub3 to get its address must
be a multiple of 8. */
__divdf3:
asl r8,DBL1H,12
lsr r4,r8,26
sub3 r10,pcl,61; (.-.Ldivtab) >> 3
ld.as r9,[pcl,-124]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000
ld.as r4,[r10,r4]
lsr r12,DBL1L,20
and.f r7,DBL1H,r9
or r8,r8,r12
mulu64 r4,r8
beq.d .Ldenorm_dbl1
.Lpast_denorm_dbl1:
and.f r6,DBL0H,r9
breq.d r7,r9,.Linf_nan_dbl1
asl r4,r4,12
sub r4,r4,mhi
mulu64 r4,r4
beq.d .Ldenorm_dbl0
lsr r8,r8,1
breq.d r6,r9,.Linf_nan_dbl0
asl r12,DBL0H,11
lsr r10,DBL0L,21
.Lpast_denorm_dbl0:
bset r8,r8,31
mulu64 mhi,r8
add_s r12,r12,r10
bset r5,r12,31
cmp r5,r8
cmp.eq DBL0L,DBL1L
lsr.cc r5,r5,1
sub r4,r4,mhi ; u1.31 inverse, about 30 bit
mulu64 r5,r4 ; result fraction highpart
lsr r8,r8,2 ; u3.29
add r5,r6, /* wait for immediate */ \
0x3fe00000
mov r11,mhi ; result fraction highpart
mulu64 r11,r8 ; u-28.31
asl_s DBL1L,DBL1L,9 ; u-29.23:9
sbc r6,r5,r7
mov r12,mlo ; u-28.31
mulu64 r11,DBL1L ; mhi: u-28.23:9
add.cs DBL0L,DBL0L,DBL0L
asl_s DBL0L,DBL0L,6 ; u-26.25:7
asl r10,r11,23
sub_l DBL0L,DBL0L,r12
lsr r7,r11,9
sub r5,DBL0L,mhi ; rest msw ; u-26.31:0
mul64 r5,r4 ; mhi: result fraction lowpart
xor.f 0,DBL0H,DBL1H
and DBL0H,r6,r9
add_s DBL0H,DBL0H,r7
bclr r12,r9,20 ; 0x7fe00000
brhs.d r6,r12,.Linf_denorm
bxor.mi DBL0H,DBL0H,31
add.f r12,mhi,0x11
asr r9,r12,5
sub.mi DBL0H,DBL0H,1
add.f DBL0L,r9,r10
tst r12,0x1c
jne.d [blink]
add.cs DBL0H,DBL0H,1
/* work out exact rounding if we fall through here. */
/* We know that the exact result cannot be represented in double
precision. Find the mid-point between the two nearest
representable values, multiply with the divisor, and check if
the result is larger than the dividend. Since we want to know
only the sign bit, it is sufficient to calculate only the
highpart of the lower 64 bits. */
mulu64 r11,DBL1L ; rest before considering r12 in r5 : -mlo
sub.f DBL0L,DBL0L,1
asl r12,r9,2 ; u-22.30:2
sub.cs DBL0H,DBL0H,1
sub.f r12,r12,2
mov r10,mlo ; rest before considering r12 in r5 : -r10
mulu64 r12,DBL1L ; mhi: u-51.32
asl r5,r5,25 ; s-51.7:25
lsr r10,r10,7 ; u-51.30:2
mov r7,mhi ; u-51.32
mulu64 r12,r8 ; mlo: u-51.31:1
sub r5,r5,r10
add.mi r5,r5,DBL1L ; signed multiply adjust for r12*DBL1L
bset r7,r7,0 ; make sure that the result is not zero, and that
sub r5,r5,r7 ; a highpart zero appears negative
sub.f r5,r5,mlo ; rest msw
add.pl.f DBL0L,DBL0L,1
j_s.d [blink]
add.eq DBL0H,DBL0H,1
.Linf_nan_dbl1: ; 0/Inf -> NaN Inf/Inf -> NaN x/Inf-> 0 x/NaN -> NaN
or.f 0,r6,DBL0L
cmp.ne r6,r9
not_s DBL0L,DBL1H
sub_s.ne DBL0L,DBL0L,DBL0L
tst_s DBL0H,DBL0H
add_s DBL0H,DBL1H,DBL0L
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
.Linf_nan_dbl0:
tst_s DBL1H,DBL1H
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
.balign 4
.Linf_denorm:
lsr r12,r6,28
brlo.d r12,0xc,.Linf
.Ldenorm:
asr r6,r6,20
neg r9,r6
mov_s DBL0H,0
brhs.d r9,54,.Lret0
bxor.mi DBL0H,DBL0H,31
add r12,mhi,1
and r12,r12,-4
rsub r7,r6,5
asr r10,r12,28
bmsk r4,r12,27
min r7,r7,31
asr DBL0L,r4,r7
add DBL1H,r11,r10
abs.f r10,r4
sub.mi r10,r10,1
add.f r7,r6,32-5
asl r4,r4,r7
mov.mi r4,r10
add.f r10,r6,23
rsub r7,r6,9
lsr r7,DBL1H,r7
asl r10,DBL1H,r10
or.pnz DBL0H,DBL0H,r7
or.mi r4,r4,r10
mov.mi r10,r7
add.f DBL0L,r10,DBL0L
add.cs.f DBL0H,DBL0H,1 ; carry clear after this point
bxor.f 0,r4,31
add.pnz.f DBL0L,DBL0L,1
add.cs.f DBL0H,DBL0H,1
jne_s [blink]
/* Calculation so far was not conclusive; calculate further rest. */
mulu64 r11,DBL1L ; rest before considering r12 in r5 : -mlo
asr.f r12,r12,3
asl r5,r5,25 ; s-51.7:25
mov r11,mlo ; rest before considering r12 in r5 : -r11
mulu64 r12,r8 ; u-51.31:1
and r9,DBL0L,1 ; tie-breaker: round to even
lsr r11,r11,7 ; u-51.30:2
mov DBL1H,mlo ; u-51.31:1
mulu64 r12,DBL1L ; u-51.62:2
sub.mi r11,r11,DBL1L ; signed multiply adjust for r12*DBL1L
add_s DBL1H,DBL1H,r11
sub DBL1H,DBL1H,r5 ; -rest msw
add_s DBL1H,DBL1H,mhi ; -rest msw
add.f 0,DBL1H,DBL1H ; can't ror.f by 32 :-(
tst_s DBL1H,DBL1H
cmp.eq mlo,r9
add.cs.f DBL0L,DBL0L,1
j_s.d [blink]
add.cs DBL0H,DBL0H,1
.Lret0:
/* return +- 0 */
j_s.d [blink]
mov_s DBL0L,0
.Linf:
mov_s DBL0H,r9
mov_s DBL0L,0
j_s.d [blink]
bxor.mi DBL0H,DBL0H,31
ENDFUNC(__divdf3)
|
4ms/metamodule-plugin-sdk
| 3,684
|
plugin-libc/libgcc/config/arc/ieee-754/arc600-mul64/mulsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../arc-ieee-754.h"
#if 0 /* DEBUG */
.global __mulsf3
FUNC(__mulsf3)
.balign 4
__mulsf3:
push_s blink
push_s r1
bl.d __mulsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __mulsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
jeq_s [blink]
and r12,r0,r1
bic.f 0,0x7f800000,r12
bne 0f
bmsk.f 0,r0,22
bmsk.ne.f r1,r1,22
jne_s [blink] ; both NaN -> OK
0: bl abort
ENDFUNC(__mulsf3)
#define __mulsf3 __mulsf3_asm
#endif /* DEBUG */
.balign 4
.global __mulsf3
FUNC(__mulsf3)
__mulsf3:
ld.as r9,[pcl,80]; [pcl,((.L7f800000-.+2)/4)]
bmsk r4,r1,22
bset r2,r0,23
asl_s r2,r2,8
bset r3,r4,23
mulu64 r2,r3
and r11,r0,r9
breq.d r11,0,.Ldenorm_dbl0
and r12,r1,r9
breq.d r12,0,.Ldenorm_dbl1
xor_s r0,r0,r1
breq.d r11,r9,.Linf_nan_dbl0
ld.as r4,[pcl,70]; [pcl,((.L7fffffff-.+2)/4)]
breq.d r12,r9,.Linf_nan_dbl1
.Lpast_denorm:
asl.f 0,mhi,8
mov r6,mhi
mov r7,mlo
add.pl r6,r6,r6
bclr.pl r6,r6,23
add.pl.f r7,r7,r7
add.cs r6,r6,1
lsr.f 0,r6,1
add_s r12,r12,r11
adc.f 0,r7,r4
add_s r12,r12, \
-0x3f800000
adc.f r8,r6,r12
tst.pl r8,r9
bic r0,r0,r4
min r3,r8,r9
jpnz.d [blink]
add.pnz r0,r0,r3
; infinity or denormal number
add.ne.f r3,r3,r3
asr_s r3,r3,23+1
bset r6,r6,23
bpnz.d .Linfinity
sub_s r3,r3,1
neg_s r2,r3
brhi.d r2,24,.Lret_r0 ; right shift shift > 24 -> return +-0
lsr r2,r6,r2
asl r9,r6,r3
lsr.f 0,r2,1
tst r7,r7
add_s r0,r0,r2
bset.ne r9,r9,0
adc.f 0,r9,r4
j_s.d [blink]
add.cs r0,r0,1
.Linfinity:
j_s.d [blink]
add_s r0,r0,r9
.Lret_r0: j_s [blink]
.balign 4
.Ldenorm_dbl0:
bclr_s r2,r2,31
norm.f r4,r2
add_s r2,r2,r2
asl r2,r2,r4
mulu64 r2,r3
breq.d r12,r9,.Ldenorm_dbl0_inf_nan_dbl1
asl r4,r4,23
sub.ne.f r12,r12,r4
ld.as r4,[pcl,29]; [pcl,((.L7fffffff-.+2)/4)]
bhi.d .Lpast_denorm
xor_s r0,r0,r1
bmsk r1,r0,30
j_s.d [blink]
bic_s r0,r0,r1
.balign 4
.Ldenorm_dbl0_inf_nan_dbl1:
bmsk.f 0,r0,30
beq_s .Lretnan
xor_s r0,r0,r1
.Linf_nan_dbl1:
xor_s r1,r1,r0
.Linf_nan_dbl0:
bclr_s r1,r1,31
cmp_s r1,r9
jls.d [blink]
xor_s r0,r0,r1
; r1 NaN -> result NaN
.Lretnan:
j_s.d [blink]
mov r0,-1
.balign 4
.Ldenorm_dbl1:
breq.d r11,r9,.Linf_nan_dbl0_2
norm.f r3,r4
sub_s r3,r3,7
asl r4,r4,r3
mulu64 r2,r4
sub_s r3,r3,1
asl_s r3,r3,23
sub.ne.f r11,r11,r3
ld.as r4,[pcl,11]; [pcl,((.L7fffffff-.+2)/4)]
bhi.d .Lpast_denorm
bmsk r8,r0,30
j_s.d [blink]
bic r0,r0,r8
.balign 4
.Linf_nan_dbl0_2:
bclr_s r1,r1,31
xor_s r0,r0,r1
sub.eq r1,r1,1 ; inf/nan * 0 -> nan
bic.f 0,r9,r1
j_s.d [blink]
or.eq r0,r0,r1 ; r1 nan -> result nan
.balign 4
.L7f800000:
.long 0x7f800000
.L7fffffff:
.long 0x7fffffff
ENDFUNC(__mulsf3)
|
4ms/metamodule-plugin-sdk
| 5,348
|
plugin-libc/libgcc/config/arc/ieee-754/arc600-mul64/muldf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../arc-ieee-754.h"
#if 0 /* DEBUG */
.global __muldf3
.balign 4
__muldf3:
push_s blink
push_s r2
push_s r3
push_s r0
bl.d __muldf3_c
push_s r1
ld_s r2,[sp,12]
ld_s r3,[sp,8]
st_s r0,[sp,12]
st_s r1,[sp,8]
pop_s r1
bl.d __muldf3_asm
pop_s r0
pop_s r3
pop_s r2
pop_s blink
cmp r0,r2
cmp.eq r1,r3
jeq_s [blink]
and r12,DBL0H,DBL1H
bic.f 0,0x7ff80000,r12 ; both NaN -> OK
jeq_s [blink]
b abort
#define __muldf3 __muldf3_asm
#endif /* DEBUG */
__muldf3_support: /* This label makes debugger output saner. */
.balign 4
FUNC(__muldf3)
.Ldenorm_2:
breq.d DBL1L,0,.Lret0_2 ; 0 input -> 0 output
norm.f r12,DBL1L
mov.mi r12,21
add.pl r12,r12,22
neg r11,r12
asl_s r12,r12,20
lsr.f DBL1H,DBL1L,r11
ror DBL1L,DBL1L,r11
sub_s DBL0H,DBL0H,r12
mov.eq DBL1H,DBL1L
sub_l DBL1L,DBL1L,DBL1H
/* Fall through. */
.global __muldf3
.balign 4
__muldf3:
mulu64 DBL0L,DBL1L
ld.as r9,[pcl,0x68] ; ((.L7ff00000-.+2)/4)]
bmsk r6,DBL0H,19
bset r6,r6,20
and r11,DBL0H,r9
breq.d r11,0,.Ldenorm_dbl0
and r12,DBL1H,r9
breq.d r12,0,.Ldenorm_dbl1
mov r8,mlo
mov r4,mhi
mulu64 r6,DBL1L
breq.d r11,r9,.Linf_nan
bmsk r10,DBL1H,19
breq.d r12,r9,.Linf_nan
bset r10,r10,20
add.f r4,r4,mlo
adc r5,mhi,0
mulu64 r10,DBL0L
add_s r12,r12,r11 ; add exponents
add.f r4,r4,mlo
adc r5,r5,mhi
mulu64 r6,r10
tst r8,r8
bclr r8,r9,30 ; 0x3ff00000
bset.ne r4,r4,0 ; put least significant word into sticky bit
bclr r6,r9,20 ; 0x7fe00000
add.f r5,r5,mlo
adc r7,mhi,0 ; fraction product in r7:r5:r4
lsr.f r10,r7,9
rsub.eq r8,r8,r9 ; 0x40000000
sub r12,r12,r8 ; subtract bias + implicit 1
brhs.d r12,r6,.Linf_denorm
rsub r10,r10,12
.Lshift_frac:
neg r8,r10
asl r6,r4,r10
lsr DBL0L,r4,r8
add.f 0,r6,r6
btst.eq DBL0L,0
cmp.eq r4,r4 ; round to nearest / round to even
asl r4,r5,r10
lsr r5,r5,r8
adc.f DBL0L,DBL0L,r4
xor.f 0,DBL0H,DBL1H
asl r7,r7,r10
add_s r12,r12,r5
adc DBL0H,r12,r7
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
/* N.B. This is optimized for ARC700.
ARC600 has very different scheduling / instruction selection criteria. */
/* If one number is denormal, subtract some from the exponent of the other
one (if the other exponent is too small, return 0), and normalize the
denormal. Then re-run the computation. */
.Lret0_2:
lsr_s DBL0H,DBL0H,31
asl_s DBL0H,DBL0H,31
j_s.d [blink]
mov_s DBL0L,0
.balign 4
.Ldenorm_dbl0:
mov_s r12,DBL0L
mov_s DBL0L,DBL1L
mov_s DBL1L,r12
mov_s r12,DBL0H
mov_s DBL0H,DBL1H
mov_s DBL1H,r12
and r11,DBL0H,r9
.Ldenorm_dbl1:
brhs r11,r9,.Linf_nan
brhs 0x3ca00001,r11,.Lret0
sub_s DBL0H,DBL0H,DBL1H
bmsk.f DBL1H,DBL1H,30
add_s DBL0H,DBL0H,DBL1H
beq.d .Ldenorm_2
norm r12,DBL1H
sub_s r12,r12,10
asl r5,r12,20
asl_s DBL1H,DBL1H,r12
sub DBL0H,DBL0H,r5
neg r5,r12
lsr r6,DBL1L,r5
asl_s DBL1L,DBL1L,r12
b.d __muldf3
add_s DBL1H,DBL1H,r6
.Lret0: xor_s DBL0H,DBL0H,DBL1H
bclr DBL1H,DBL0H,31
xor_s DBL0H,DBL0H,DBL1H
j_s.d [blink]
mov_s DBL0L,0
.balign 4
.Linf_nan:
bclr r12,DBL1H,31
xor_s DBL1H,DBL1H,DBL0H
bclr_s DBL0H,DBL0H,31
max r8,DBL0H,r12 ; either NaN -> NaN ; otherwise inf
or.f 0,DBL0H,DBL0L
mov_s DBL0L,0
or.ne.f DBL1L,DBL1L,r12
not_s DBL0H,DBL0L ; inf * 0 -> NaN
mov.ne DBL0H,r8
tst_s DBL1H,DBL1H
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
/* We have checked for infinity / NaN input before, and transformed
denormalized inputs into normalized inputs. Thus, the worst case
exponent overflows are:
1 + 1 - 0x400 == 0xc02 : maximum underflow
0x7fe + 0x7fe - 0x3ff == 0xbfd ; maximum overflow
N.B. 0x7e and 0x7f are also values for overflow.
If (r12 <= -54), we have an underflow to zero. */
.balign 4
.Linf_denorm:
lsr r6,r12,28
brlo.d r6,0xc,.Linf
asr r6,r12,20
add.f r10,r10,r6
brgt.d r10,0,.Lshift_frac
mov_s r12,0
beq.d .Lround_frac
add r10,r10,32
.Lshift32_frac:
tst r4,r4
mov r4,r5
bset.ne r4,r4,1
mov r5,r7
brge.d r10,1,.Lshift_frac
mov r7,0
breq.d r10,0,.Lround_frac
add r10,r10,32
brgt r10,21,.Lshift32_frac
b_s .Lret0
.Lround_frac:
add.f 0,r4,r4
btst.eq r5,0
mov_s DBL0L,r5
mov_s DBL0H,r7
adc.eq.f DBL0L,DBL0L,0
j_s.d [blink]
adc.eq DBL0H,DBL0H,0
.Linf: mov_s DBL0L,0
xor.f DBL1H,DBL1H,DBL0H
mov_s DBL0H,r9
j_s.d [blink]
bset.mi DBL0H,DBL0H,31
ENDFUNC(__muldf3)
.balign 4
.L7ff00000:
.long 0x7ff00000
|
4ms/metamodule-plugin-sdk
| 6,297
|
plugin-libc/libgcc/config/arc/ieee-754/arc600-mul64/divsf3.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
- calculate 15..18 bit inverse using a table of approximating polynoms.
precision is higher for polynoms used to evaluate input with larger
value.
- do one newton-raphson iteration step to double the precision,
then multiply this with the divisor
-> more time to decide if dividend is subnormal
- the worst error propagation is on the side of the value range
with the least initial defect, thus giving us about 30 bits precision.
*/
#include "../arc-ieee-754.h"
#if 0 /* DEBUG */
.global __divsf3
FUNC(__divsf3)
.balign 4
__divsf3:
push_s blink
push_s r1
bl.d __divsf3_c
push_s r0
ld_s r1,[sp,4]
st_s r0,[sp,4]
bl.d __divsf3_asm
pop_s r0
pop_s r1
pop_s blink
cmp r0,r1
#if 1
bne abort
jeq_s [blink]
b abort
#else
bne abort
j_s [blink]
#endif
ENDFUNC(__divsf3)
#define __divsf3 __divsf3_asm
#endif /* DEBUG */
FUNC(__divsf3)
.balign 4
.Ldivtab:
.long 0xfc0ffff0
.long 0xf46ffefd
.long 0xed1ffd2a
.long 0xe627fa8e
.long 0xdf7ff73b
.long 0xd917f33b
.long 0xd2f7eea3
.long 0xcd1fe986
.long 0xc77fe3e7
.long 0xc21fdddb
.long 0xbcefd760
.long 0xb7f7d08c
.long 0xb32fc960
.long 0xae97c1ea
.long 0xaa27ba26
.long 0xa5e7b22e
.long 0xa1cfa9fe
.long 0x9ddfa1a0
.long 0x9a0f990c
.long 0x9667905d
.long 0x92df878a
.long 0x8f6f7e84
.long 0x8c27757e
.long 0x88f76c54
.long 0x85df630c
.long 0x82e759c5
.long 0x8007506d
.long 0x7d3f470a
.long 0x7a8f3da2
.long 0x77ef341e
.long 0x756f2abe
.long 0x72f7212d
.long 0x709717ad
.long 0x6e4f0e44
.long 0x6c1704d6
.long 0x69e6fb44
.long 0x67cef1d7
.long 0x65c6e872
.long 0x63cedf18
.long 0x61e6d5cd
.long 0x6006cc6d
.long 0x5e36c323
.long 0x5c76b9f3
.long 0x5abeb0b7
.long 0x5916a79b
.long 0x57769e77
.long 0x55de954d
.long 0x54568c4e
.long 0x52d6834d
.long 0x51667a7f
.long 0x4ffe71b5
.long 0x4e9e68f1
.long 0x4d466035
.long 0x4bf65784
.long 0x4aae4ede
.long 0x496e4646
.long 0x48363dbd
.long 0x47063547
.long 0x45de2ce5
.long 0x44be2498
.long 0x43a61c64
.long 0x4296144a
.long 0x41860c0e
.long 0x407e03ee
.L7f800000:
.long 0x7f800000
.balign 4
.global __divsf3_support
__divsf3_support:
.Linf_NaN:
bclr.f 0,r0,31 ; 0/0 -> NaN
xor_s r0,r0,r1
bmsk r1,r0,30
bic_s r0,r0,r1
sub.eq r0,r0,1
j_s.d [blink]
or r0,r0,r9
.Lret0:
xor_s r0,r0,r1
bmsk r1,r0,30
j_s.d [blink]
bic_s r0,r0,r1
/* N.B. the spacing between divtab and the sub3 to get its address must
be a multiple of 8. */
__divsf3:
lsr r2,r1,17
sub3 r3,pcl,37 ; (.-.Ldivtab) >> 3
bmsk_s r2,r2,5
ld.as r5,[r3,r2]
asl r4,r1,9
ld.as r9,[pcl,-13]; [pcl,(-((.-.L7f800000) >> 2))] ; 0x7f800000
mulu64 r5,r4
and.f r11,r1,r9
asl r6,r1,8
bset r6,r6,31
beq.d .Ldenorm_fp1
asl r5,r5,13
breq.d r11,r9,.Linf_nan_fp1
and.f r2,r0,r9
sub r7,r5,mhi
mulu64 r7,r6
beq.d .Ldenorm_fp0
asl r12,r0,8
breq.d r2,r9,.Linf_nan_fp0
mulu64 mhi,r7
.Lpast_denorm_fp1:
bset r3,r12,31
.Lpast_denorm_fp0:
cmp_s r3,r6
lsr.cc r3,r3,1
add_s r2,r2, /* wait for immediate */ \
0x3f000000
sub r7,r7,mhi ; u1.31 inverse, about 30 bit
mulu64 r3,r7
sbc r2,r2,r11
xor.f 0,r0,r1
and r0,r2,r9
bclr r3,r9,23 ; 0x7f000000
brhs.d r2,r3,.Linf_denorm
bxor.mi r0,r0,31
.Lpast_denorm:
add r3,mhi,0x22 ; round to nearest or higher
tst r3,0x3c ; check if rounding was unsafe
lsr r3,r3,6
jne.d [blink] ; return if rounding was safe.
add_s r0,r0,r3
/* work out exact rounding if we fall through here. */
/* We know that the exact result cannot be represented in single
precision. Find the mid-point between the two nearest
representable values, multiply with the divisor, and check if
the result is larger than the dividend. */
add_s r3,r3,r3
sub_s r3,r3,1
mulu64 r3,r6
asr.f 0,r0,1 ; for round-to-even in case this is a denorm
rsub r2,r9,25
asl_s r12,r12,r2
sub.f 0,r12,mlo
j_s.d [blink]
sub.mi r0,r0,1
.Linf_nan_fp1:
lsr_s r0,r0,31
bmsk.f 0,r1,22
asl_s r0,r0,31
bne_s 0f ; inf/inf -> nan
brne r2,r9,.Lsigned0 ; x/inf -> 0, but x/nan -> nan
0: j_s.d [blink]
mov r0,-1
.Lsigned0:
.Linf_nan_fp0:
tst_s r1,r1
j_s.d [blink]
bxor.mi r0,r0,31
.balign 4
.global __divsf3
/* For denormal results, it is possible that an exact result needs
rounding, and thus the round-to-even rule has to come into play. */
.Linf_denorm:
brlo r2,0xc0000000,.Linf
.Ldenorm:
asr_s r2,r2,23
bic r0,r0,r9
neg r9,r2
brlo.d r9,25,.Lpast_denorm
lsr r3,mlo,r9
/* Fall through: return +- 0 */
j_s [blink]
.Linf:
j_s.d [blink]
or r0,r0,r9
.balign 4
.Ldenorm_fp1:
bclr r6,r6,31
norm.f r12,r6 ; flag for x/0 -> Inf check
add r6,r6,r6
rsub r5,r12,16
ror r5,r1,r5
asl r6,r6,r12
bmsk r5,r5,5
ld.as r5,[r3,r5]
add r4,r6,r6
; load latency
mulu64 r5,r4
bic.ne.f 0, \
0x60000000,r0 ; large number / denorm -> Inf
asl r5,r5,13
sub r7,r5,mhi
beq.d .Linf_NaN
mulu64 r7,r6
asl_s r12,r12,23
and.f r2,r0,r9
add_s r2,r2,r12
asl r12,r0,8
bne.d .Lpast_denorm_fp1
.Ldenorm_fp0: mulu64 mhi,r7
bclr r12,r12,31
norm.f r3,r12 ; flag for 0/x -> 0 check
bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0
beq_s .Lret0
asl_s r12,r12,r3
asl_s r3,r3,23
add_s r12,r12,r12
add r11,r11,r3
b.d .Lpast_denorm_fp0
mov_s r3,r12
ENDFUNC(__divsf3)
|
4ms/metamodule-plugin-sdk
| 2,465
|
plugin-libc/newlib/libm/machine/nds32/wf_sqrt.S
|
/*
Copyright (c) 2013-2014 Andes Technology Corporation.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.text
.align 1
.global sqrtf
.type sqrtf, @function
sqrtf:
/* The input argument is supposed to be stored in $fs0.
The return value is supposed to be stored in $fs0 either. */
/* Clear the IEEE cumulative exceptions flags. ($fpcsr.b[6:2]) */
FMFCSR $r0
bitci $r0, $r0, #0b1111100
FMTCSR $r0
fsqrts $fs0, $fs0
/* Check the IEEE cumulative exceptions flags. */
FMFCSR $r5
bmski33 $r5, #2 /* Is $fpcsr.IVO('b2) set ? */
bnez $r5, .L_EDOM /* Set errno as EDOM. */
bmski33 $r5, #4 /* Is $fpcsr.OVF('b4) set ? */
bnez $r5, .L_ERANGE /* Set errno as ERANGE. */
bmski33 $r5, #5 /* Is $fpcsr.UDF('b5) set ? */
bnez $r5, .L_ERANGE /* Set errno as ERANGE. */
/* No error at all. Just ret. */
ret
.L_EDOM:
movi $r0, #33 /* EDOM: Math arg out of domain of func. */
j .L_Set_errno
.L_ERANGE:
movi $r0, #34 /* ERANGE: Math result not representable. */
.L_Set_errno:
l.w $r15, _impure_ptr
swi $r0, [$r15] /* Set errno. */
ret
.size sqrtf, .-sqrtf
|
4ms/metamodule-plugin-sdk
| 2,461
|
plugin-libc/newlib/libm/machine/nds32/w_sqrt.S
|
/*
Copyright (c) 2013-2014 Andes Technology Corporation.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.text
.align 1
.global sqrt
.type sqrt, @function
sqrt:
/* The input argument is supposed to be stored in $fd0.
The return value is supposed to be stored in $fd0 either. */
/* Clear the IEEE cumulative exceptions flags. ($fpcsr.b[6:2]) */
FMFCSR $r0
bitci $r0, $r0, #0b1111100
FMTCSR $r0
fsqrtd $fd0, $fd0
/* Check the IEEE cumulative exceptions flags. */
FMFCSR $r0
bmski33 $r0, #2 /* Is $fpcsr.IVO('b2) set ? */
bnez $r0, .L_EDOM /* Set errno as EDOM. */
bmski33 $r0, #4 /* Is $fpcsr.OVF('b4) set ? */
bnez $r0, .L_ERANGE /* Set errno as ERANGE. */
bmski33 $r0, #5 /* Is $fpcsr.UDF('b5) set ? */
bnez $r0, .L_ERANGE /* Set errno as ERANGE. */
/* No error at all. Just ret. */
ret
.L_EDOM:
movi $r0, #33 /* EDOM: Math arg out of domain of func. */
j .L_Set_errno
.L_ERANGE:
movi $r0, #34 /* ERANGE: Math result not representable. */
.L_Set_errno:
l.w $r15, _impure_ptr
swi $r0, [$r15] /* Set errno. */
ret
.size sqrt, .-sqrt
|
4ms/metamodule-plugin-sdk
| 2,487
|
plugin-libc/newlib/libc/machine/nios2/setjmp.s
|
;/*
; * C library -- _setjmp, _longjmp
; *
; * _longjmp(a,v)
; * will generate a "return(v?v:1)" from
; * the last call to
; * _setjmp(a)
; * by unwinding the call stack.
; * The previous signal state is NOT restored.
; *
; *
; * Copyright (c) 2003 Altera Corporation
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted provided that the following conditions
; * are met:
; *
; * o Redistributions of source code must retain the above copyright
; * notice, this list of conditions and the following disclaimer.
; * o Redistributions in binary form must reproduce the above copyright
; * notice, this list of conditions and the following disclaimer in the
; * documentation and/or other materials provided with the distribution.
; * o Neither the name of Altera Corporation nor the names of its
; * contributors may be used to endorse or promote products derived from
; * this software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY ALTERA CORPORATION, THE COPYRIGHT HOLDER,
; * AND ITS CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
; * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
; * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
; * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
; * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
; * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
; * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; */
.section .text
.align 3
.globl setjmp
.type setjmp,@function
.globl longjmp
.type longjmp,@function
setjmp:
stw r16, 0(r4)
stw r17, 4(r4)
stw r18, 8(r4)
stw r19, 12(r4)
stw r20, 16(r4)
stw r21, 20(r4)
stw r22, 24(r4)
stw r23, 28(r4)
stw gp, 32(r4)
stw sp, 36(r4)
stw fp, 40(r4)
stw ra, 44(r4)
mov r2, zero
ret
longjmp:
ldw r16, 0(r4)
ldw r17, 4(r4)
ldw r18, 8(r4)
ldw r19, 12(r4)
ldw r20, 16(r4)
ldw r21, 20(r4)
ldw r22, 24(r4)
ldw r23, 28(r4)
ldw gp, 32(r4)
ldw sp, 36(r4)
ldw fp, 40(r4)
ldw ra, 44(r4)
mov r2, r5
bne r2, zero, 1f
movi r2, 1
1:
ret
|
4ms/metamodule-plugin-sdk
| 1,855
|
plugin-libc/newlib/libc/machine/rx/strncat.S
|
.file "strncat.S"
.section .text
.global _strncat
.type _strncat,@function
_strncat:
;; On entry: r1 => Destination
;; r2 => Source
;; r3 => Max number of bytes to copy
#ifdef __RX_DISALLOW_STRING_INSNS__
cmp #0, r3 ; If max is zero we have nothing to do.
beq 2f
mov r1, r4 ; Leave the desintation pointer intact for the return value.
1: mov.b [r4+], r5 ; Find the NUL byte at the end of the destination.
cmp #0, r5
bne 1b
sub #1, r4
3: mov.b [r2+], r5 ; Copy bytes from the source into the destination ...
mov.b r5, [r4+]
cmp #0, r5 ; ... until we reach a NUL byte ...
beq 2f
sub #1, r3
bne 3b ; ... or we have copied N bytes.
2: rts
#else
mov r1, r4 ; Save a copy of the dest pointer.
mov r2, r5 ; Save a copy of the source pointer.
mov r3, r14 ; Save a copy of the byte count.
mov #0, r2 ; Search for the NUL byte.
mov #-1, r3 ; Search until we run out of memory.
suntil.b ; Find the end of the destination string.
sub #1, r1 ; suntil.b leaves r1 pointing to the byte beyond the NUL.
mov r14, r3 ; Restore the limit on the number of bytes copied.
mov r5, r2 ; Restore the source pointer.
mov r1, r5 ; Save a copy of the dest pointer.
smovu ; Copy source to destination.
add #0, r14, r3 ; Restore the number of bytes to copy (again), but this time set the Z flag as well.
beq 1f ; If we copied 0 bytes then we already know that the dest string is NUL terminated, so we do not have to do anything.
mov #0, r2 ; Otherwise we must check to see if a NUL byte
mov r5, r1 ; was included in the bytes that were copied.
suntil.b
beq 1f ; Z flag is set if a match was found.
add r14, r5 ; Point at byte after end of copied bytes.
mov.b #0, [r5] ; Store a NUL there.
1:
mov r4, r1 ; Return the original dest pointer.
rts
#endif
.size _strncat, . - _strncat
|
4ms/metamodule-plugin-sdk
| 1,937
|
plugin-libc/newlib/libc/machine/rx/setjmp.S
|
# setjmp/longjmp for Renesas RX.
#
# The jmpbuf looks like this:
#
# Register jmpbuf offset
# R0 0x0
# R1 0x4
# R2 0x8
# R3 0xc
# R4 0x10
# R5 0x14
# R6 0x18
# R7 0x1c
# R8 0x20
# R9 0x24
# R10 0x28
# R11 0x2c
# R12 0x30
# R13 0x34
# R14 0x38
# R15 0x3c
# PC 0x40
#
# R1 contains the pointer to jmpbuf:
#
# int R1 = setjmp (jmp_buf R1)
# void longjmp (jmp_buf R1, int R2)
#
# The ABI allows for R1-R5 to be clobbered by functions. We must be
# careful to always leave the stack in a usable state in case an
# interrupt happens.
.text
.global _setjmp
.type _setjmp, @function
_setjmp:
mov.l r0, [r1] ; save all the general registers
mov.l r1, 0x4[r1] ; longjmp won't use this, but someone else might.
mov.l r2, 0x8[r1]
mov.l r3, 0xc[r1]
mov.l r4, 0x10[r1]
mov.l r5, 0x14[r1]
mov.l r6, 0x18[r1]
mov.l r7, 0x1c[r1]
mov.l r8, 0x20[r1]
mov.l r9, 0x24[r1]
mov.l r10, 0x28[r1]
mov.l r11, 0x2c[r1]
mov.l r12, 0x30[r1]
mov.l r13, 0x34[r1]
mov.l r14, 0x38[r1]
mov.l r15, 0x3c[r1]
mov.l [r0], r2 ; get return address off the stack
mov.l r2, 0x40[r1] ; PC
mov #0, r1 ; Return 0.
rts
.Lend1:
.size _setjmp, .Lend1 - _setjmp
.global _longjmp
.type _longjmp, @function
_longjmp:
tst r2, r2 ; Set the Z flag if r2 is 0.
stz #1, r2 ; If the Z flag was set put 1 into the return register.
mov r2, 4[r1] ; Put r2 (our return value) into the setjmp buffer as r1.
mov.l [r1], r0 ; Restore the stack - there's a slot for PC
mov.l 0x40[r1], r2 ; Get the saved PC
mov.l r2, [r0] ; Overwrite the old return address
mov.l 0x3c[r1], r15
mov.l 0x38[r1], r14
mov.l 0x34[r1], r13
mov.l 0x30[r1], r12
mov.l 0x2c[r1], r11
mov.l 0x28[r1], r10
mov.l 0x24[r1], r9
mov.l 0x20[r1], r8
mov.l 0x1c[r1], r7
mov.l 0x18[r1], r6
mov.l 0x14[r1], r5
mov.l 0x10[r1], r4
mov.l 0xc[r1], r3
mov.l 0x8[r1], r2
mov.l 0x4[r1], r1 ; This sets up the new return value
rts
.Lend2:
.size _longjmp, .Lend2 - _longjmp
|
4ms/metamodule-plugin-sdk
| 1,142
|
plugin-libc/newlib/libc/machine/rx/memmove.S
|
.file "memmove.S"
.section .text
.global _memmove
.type _memmove,@function
_memmove:
;; R1: DEST
;; R2: SRC
;; R3: COUNT
#ifdef __RX_DISALLOW_STRING_INSNS__
/* Do not use the string instructions - they might prefetch
bytes from outside of valid memory. This is particularly
dangerous in I/O space. */
cmp #0, r3 ; If the count is zero, do nothing
beq 4f
cmp r1, r2
blt 3f ; If SRC < DEST copy backwards
mov r1, r14 ; Save a copy of DEST
5: mov.b [r2+], r5
mov.b r5, [r14+]
sub #1, r3
bne 5b
4: rts
3: add r3, r1
add r3, r2
6: mov.b [-r2], r5
mov.b r5, [-r1]
sub #1, r3
bne 6b
rts
#else
mov r1, r4 ; Save a copy of DEST
cmp r1, r2
blt 2f ; If SRC (r2) is less than DEST (r1) then copy backwards
smovf
1:
mov r4, r1 ; Return DEST
rts
2:
add r3, r1 ; The SMOVB instructions requires the DEST in r1 and the
add r3, r2 ; SRC in r2 but it needs them to point the last bytes of
sub #1, r2 ; the regions involved not the first bytes, hence these
sub #1, r1 ; additions and subtractions.
smovb
bra 1b
#endif /* SMOVF allowed. */
.size _memmove, . - _memmove
|
4ms/metamodule-plugin-sdk
| 1,050
|
plugin-libc/newlib/libc/machine/rx/strcat.S
|
.file "strcat.S"
.section .text
.global _strcat
.type _strcat,@function
_strcat:
;; On entry: r1 => Destination
;; r2 => Source
#ifdef __RX_DISALLOW_STRING_INSNS__
mov r1, r4 ; Save a copy of the dest pointer.
1: mov.b [r4+], r5 ; Find the NUL byte at the end of R4.
cmp #0, r5
bne 1b
sub #1, r4 ; Move R4 back to point at the NUL byte.
2: mov.b [r2+], r5 ; Copy bytes from R2 to R4 until we reach a NUL byte.
mov.b r5, [r4+]
cmp #0, r5
bne 2b
rts
#else
mov r1, r4 ; Save a copy of the dest pointer.
mov r2, r5 ; Save a copy of the source pointer.
mov #0, r2 ; Search for the NUL byte.
mov #-1, r3 ; Limit on the number of bytes examined.
suntil.b ; Find the end of the destination string.
sub #1, r1 ; suntil.b leaves r1 pointing to the byte beyond the match.
mov #-1, r3 ; Set a limit on the number of bytes copied.
mov r5, r2 ; Restore the source pointer.
smovu ; Copy source to destination
mov r4, r1 ; Return the original dest pointer.
rts
#endif
.size _strcat, . - _strcat
|
4ms/metamodule-plugin-sdk
| 2,777
|
plugin-libc/newlib/libc/machine/m68k/memcpy.S
|
/* a-memcpy.s -- memcpy, optimised for m68k asm
*
* Copyright (c) 2007 mocom software GmbH & Co KG)
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "m68kasm.h"
#if defined (__mcoldfire__) || defined (__mc68030__) || defined (__mc68040__) || defined (__mc68060__)
# define MISALIGNED_OK 1
#else
# define MISALIGNED_OK 0
#endif
.text
.align 4
.globl SYM(memcpy)
.type SYM(memcpy), @function
/* memcpy, optimised
*
* strategy:
* - no argument testing (the original memcpy from the GNU lib does
* no checking either)
* - make sure the destination pointer (the write pointer) is long word
* aligned. This is the best you can do, because writing to unaligned
* addresses can be the most costfull thing you could do.
* - Once you have figured that out, we do a little loop unrolling
* to further improve speed.
*/
SYM(memcpy):
move.l 4(sp),a0 | dest ptr
move.l 8(sp),a1 | src ptr
move.l 12(sp),d1 | len
cmp.l #8,d1 | if fewer than 8 bytes to transfer,
blo .Lresidue | do not optimise
#if !MISALIGNED_OK
/* Goto .Lresidue if either dest or src is not 4-byte aligned */
move.l a0,d0
and.l #3,d0
bne .Lresidue
move.l a1,d0
and.l #3,d0
bne .Lresidue
#else /* MISALIGNED_OK */
/* align dest */
move.l a0,d0 | copy of dest
neg.l d0
and.l #3,d0 | look for the lower two only
beq 2f | is aligned?
sub.l d0,d1
lsr.l #1,d0 | word align needed?
bcc 1f
move.b (a1)+,(a0)+
1:
lsr.l #1,d0 | long align needed?
bcc 2f
move.w (a1)+,(a0)+
2:
#endif /* !MISALIGNED_OK */
/* long word transfers */
move.l d1,d0
and.l #3,d1 | byte residue
lsr.l #3,d0
bcc 1f | carry set for 4-byte residue
move.l (a1)+,(a0)+
1:
lsr.l #1,d0 | number of 16-byte transfers
bcc .Lcopy | carry set for 8-byte residue
bra .Lcopy8
1:
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
.Lcopy8:
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
.Lcopy:
#if !defined (__mcoldfire__)
dbra d0,1b
sub.l #0x10000,d0
#else
subq.l #1,d0
#endif
bpl 1b
bra .Lresidue
1:
move.b (a1)+,(a0)+ | move residue bytes
.Lresidue:
#if !defined (__mcoldfire__)
dbra d1,1b | loop until done
#else
subq.l #1,d1
bpl 1b
#endif
move.l 4(sp),d0 | return value
rts
|
4ms/metamodule-plugin-sdk
| 2,494
|
plugin-libc/newlib/libc/machine/m68k/memset.S
|
/* a-memset.s -- memset, optimised for fido asm
*
* Copyright (c) 2007 mocom software GmbH & Co KG)
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "m68kasm.h"
.text
.align 4
.globl SYM(memset)
.type SYM(memset), @function
| memset, optimised
|
| strategy:
| - no argument testing (the original memcpy from the GNU lib does
| no checking either)
| - make sure the destination pointer (the write pointer) is long word
| aligned. This is the best you can do, because writing to unaligned
| addresses can be the most costfull thing one could do.
| - we fill long word wise if possible
|
| VG, 2006
|
| bugfixes:
| - distribution of byte value improved - in cases someone gives
| non-byte value
| - residue byte transfer was not working
|
| VG, April 2007
|
SYM(memset):
move.l 4(sp),a0 | dest ptr
move.l 8(sp),d0 | value
move.l 12(sp),d1 | len
cmp.l #16,d1
blo .Lbset | below, byte fills
|
move.l d2,-(sp) | need a register
move.b d0,d2 | distribute low byte to all byte in word
lsl.l #8,d0
move.b d2,d0
move.w d0,d2
swap d0 | rotate 16
move.w d2,d0
|
move.l a0,d2 | copy of src
neg.l d2 | 1 2 3 ==> 3 2 1
and.l #3,d2
beq 2f | is aligned
|
sub.l d2,d1 | fix length
lsr.l #1,d2 | word align needed?
bcc 1f
move.b d0,(a0)+ | fill byte
1:
lsr.l #1,d2 | long align needed?
bcc 2f
move.w d0,(a0)+ | fill word
2:
move.l d1,d2 | number of long transfers (at least 3)
lsr.l #2,d2
subq.l #1,d2
1:
move.l d0,(a0)+ | fill long words
.Llset:
#if !defined (__mcoldfire__)
dbra d2,1b | loop until done
sub.l #0x10000,d2
#else
subq.l #1,d2
#endif
bpl 1b
and.l #3,d1 | residue byte transfers, fixed
move.l (sp)+,d2 | restore d2
bra .Lbset
1:
move.b d0,(a0)+ | fill residue bytes
.Lbset:
#if !defined (__mcoldfire__)
dbra d1,1b | loop until done
#else
subq.l #1,d1
bpl 1b
#endif
move.l 4(sp),d0 | return value
rts
|
4ms/metamodule-plugin-sdk
| 3,629
|
plugin-libc/newlib/libc/machine/rl78/setjmp.S
|
/*
Copyright (c) 2011 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef __RL78_G10__
; clobberable
r8 = 0xffec8
r9 = 0xffec9
r10 = 0xffeca
r11 = 0xffecb
r12 = 0xffecc
r13 = 0xffecd
r14 = 0xffece
r15 = 0xffecf
; preserved
r16 = 0xffed0
r17 = 0xffed1
r18 = 0xffed2
r19 = 0xffed3
r20 = 0xffed4
r21 = 0xffed5
r22 = 0xffed6
r23 = 0xffed7
#else
; clobberable
r8 = 0xffef0
r9 = 0xffef1
r10 = 0xffef2
r11 = 0xffef3
r12 = 0xffef4
r13 = 0xffef5
r14 = 0xffef6
r15 = 0xffef7
; preserved
r16 = 0xffee8
r17 = 0xffee9
r18 = 0xffeea
r19 = 0xffeeb
r20 = 0xffeec
r21 = 0xffeed
r22 = 0xffeee
r23 = 0xffeef
#endif
/* The jump buffer has the following structure:
R0 .. R23 3*8 bytes
SP 2 bytes
ES 1 byte
CS 1 byte
PC 4 bytes
*/
.macro _saveb ofs,reg
mov a,\reg
mov [hl+\ofs],a
.endm
.macro _save ofs,reg
movw ax,\reg
movw [hl+\ofs],ax
.endm
.global _setjmp
.type _setjmp, @function
_setjmp:
;; R8 = setjmp (jmp_buf *[sp+4].w)
;; must return zero !!
push ax
push hl
push ax
movw ax, [sp+10]
movw hl, ax
pop ax
movw [hl], ax
_save 2, bc
_save 4, de
pop ax
movw [hl+6], ax
_save 8, r8
_save 10, r10
_save 12, r12
_save 14, r14
_save 16, r16
_save 18, r18
_save 20, r20
_save 22, r22
;; The sp we have now includes one more pushed reg, plus $PC
movw ax, sp
addw ax, #6
movw [hl+24], ax
_saveb 26, es
_saveb 27, cs
_save 28, [sp+2]
_save 30, [sp+4]
clrw ax
movw r8, ax
pop ax
ret
.size _setjmp, . - _setjmp
.macro _loadb ofs,reg
mov a,[hl+\ofs]
mov \reg,a
.endm
.macro _load ofs,reg
movw ax,[hl+\ofs]
movw \reg,ax
.endm
.macro _push ofs
movw ax,[hl+\ofs]
push ax
.endm
.global _longjmp
.type _longjmp, @function
_longjmp:
;; noreturn longjmp (jmp_buf *[sp+4].w, int [sp+6].w)
movw ax, [sp+6]
cmpw ax,#0
sknz
onew ax
movw r8, ax
movw ax, [sp+4]
movw hl, ax
movw ax, [hl+24]
movw sp, ax ; this is the *new* stack
_push 30 ; high half of PC
_push 28 ; low half of PC
_push 6 ; HL
_push 0 ; AX
_load 2, bc
_load 4, de
_load 10, r10
_load 12, r12
_load 14, r14
_load 16, r16
_load 18, r18
_load 20, r20
_load 22, r22
_loadb 26, es
_loadb 27, cs
pop ax
pop hl
ret ; pops PC (4 bytes)
.size _longjmp, . - _longjmp
|
4ms/metamodule-plugin-sdk
| 1,479
|
plugin-libc/newlib/libc/machine/mt/setjmp.S
|
# setjmp/longjmp for mt.
#
# The jmpbuf looks like this:
#
# Register jmpbuf offset
# R0 --- --
# R1 0x4 4
# R2 0x8 8
# R3 0xc 12
# R4 0x10 16
# R5 0x14 20
# R6 0x18 24
# R7 0x1c 28
# R8 0x20 32
# R9 ---- --
# R10 ---- --
# R11 0x2c 44
# R12 0x30 48
# R13 0x34 52
# R14 0x38 56
# R15 0x3c 60
#
# R1 contains the pointer to jmpbuf
.text
.global setjmp
.type setjmp ,@function
setjmp:
stw r1, r1, #4
or r0, r0, r0
stw r2, r1, #8
or r0, r0, r0
stw r3, r1, #12
or r0, r0, r0
stw r4, r1, #16
or r0, r0, r0
stw r5, r1, #20
or r0, r0, r0
stw r6, r1, #24
or r0, r0, r0
stw r7, r1, #28
or r0, r0, r0
stw r8, r1, #32
or r0, r0, r0
stw r11, r1, #44
or r0, r0, r0
stw r12, r1, #48
or r0, r0, r0
stw r13, r1, #52
or r0, r0, r0
stw r14, r1, #56
or r0, r0, r0
stw r15, r1, #60
jal r0, r14
addi r11, r0, #0
.Lend1:
.size setjmp,.Lend1-setjmp
.global longjmp
.type longjmp,@function
longjmp:
or r9, r1, r1
or r11, r2, r2
ldw r1, r1, #4
or r0, r0, r0
ldw r2, r1, #8
or r0, r0, r0
ldw r3, r1, #12
or r0, r0, r0
ldw r4, r1, #16
or r0, r0, r0
ldw r5, r1, #20
or r0, r0, r0
ldw r6, r1, #24
or r0, r0, r0
ldw r7, r1, #28
or r0, r0, r0
ldw r8, r1, #32
or r0, r0, r0
ldw r12, r1, #48
or r0, r0, r0
ldw r13, r1, #52
or r0, r0, r0
ldw r14, r1, #56
or r0, r0, r0
ldw r15, r1, #60
brne r0, r11, .L01
or r0, r0, r0
addi r11, r0, #1
.L01:
jal r0, r14
or r0, r0, r0
.Lend2:
.size longjmp,.Lend2-longjmp2
|
4ms/metamodule-plugin-sdk
| 2,426
|
plugin-libc/newlib/libc/machine/crx/setjmp.S
|
##############################################################################
# setjmp.S -- CRX setjmp routine #
# #
# Copyright (c) 2004 National Semiconductor Corporation #
# #
# The authors hereby grant permission to use, copy, modify, distribute, #
# and license this software and its documentation for any purpose, provided #
# that existing copyright notices are retained in all copies and that this #
# notice is included verbatim in any distributions. No written agreement, #
# license, or royalty fee is required for any of the authorized uses. #
# Modifications to this software may be copyrighted by their authors #
# and need not follow the licensing terms described here, provided that #
# the new terms are clearly indicated on the first page of each file where #
# they apply. #
# #
# C library -- setjmp, longjmp #
# longjmp(a,v) #
# will generate a "return(v)" #
# from the last call to #
# setjmp(a) #
# by restoring r7-ra, sp, #
# and pc from 'a' #
# and doing a return. (Makes sure that longjmp never returns 0). #
##############################################################################
.text
.file "setjmp.s"
.align 4
.globl _setjmp
.align 4
_setjmp:
#r2: .blkw
storm r2,{r7,r8,r9,r10,r11,r12,r13,r14}
stord sp,0(r2)
movd $0,r0
jump ra
.globl _longjmp
_longjmp:
#r2: .blkw # pointer save area
#r3: .blkw # ret vlaue
loadm r2, {r7,r8,r9,r10,r11,r12,r13,ra}
loadd 0(r2), sp
movd r3, r0
cmpd $0, r3
bne end1
movd $1, r0
end1:
jump ra
.align 4
|
4ms/metamodule-plugin-sdk
| 2,394
|
plugin-libc/newlib/libc/machine/msp430/setjmp.S
|
/* Copyright (c) 2013 Red Hat, Inc. All rights reserved.
This copyrighted material is made available to anyone wishing to use,
modify, copy, or redistribute it subject to the terms and conditions
of the BSD License. This program is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
including the implied warranties of MERCHANTABILITY or FITNESS FOR
A PARTICULAR PURPOSE. A copy of this license is available at
http://www.opensource.org/licenses. Any Red Hat trademarks that are
incorporated in the source code or documentation are not subject to
the BSD License and may only be used or replicated with the express
permission of Red Hat, Inc.
*/
# setjmp/longjmp for msp430. The jmpbuf looks like this:
#
# Register Jmpbuf offset
# small large
# r0 (pc) 0x00 0x00
# r1 (sp) 0x02 0x04
# r4 0x04 0x08
# r5 0x06 0x0c
# r6 0x08 0x10
# r7 0x0a 0x14
# r8 0x0c 0x18
# r9 0x0e 0x1c
# r10 0x10 0x20
.text
.global setjmp
setjmp:
; Upon entry r12 points to the jump buffer.
; Returns 0 to caller.
#if defined __MSP430X_LARGE__
mova @r1, r13
mova r13, 0(r12)
mova r1, 4(r12)
mova r4, 8(r12)
mova r5, 12(r12)
mova r6, 16(r12)
mova r7, 20(r12)
mova r8, 24(r12)
mova r9, 28(r12)
mova r10, 32(r12)
clr r12
reta
#else
;; Get the return address off the stack
mov.w @r1, r13
mov.w r13, 0(r12)
mov.w r1, 2(r12)
mov.w r4, 4(r12)
mov.w r5, 6(r12)
mov.w r6, 8(r12)
mov.w r7, 10(r12)
mov.w r8, 12(r12)
mov.w r9, 14(r12)
mov.w r10, 16(r12)
clr r12
ret
#endif
.size setjmp , . - setjmp
.global longjmp
longjmp:
; Upon entry r12 points to the jump buffer and
; r13 contains the value to be returned by setjmp.
#if defined __MSP430X_LARGE__
mova @r12+, r14
mova @r12+, r1
mova @r12+, r4
mova @r12+, r5
mova @r12+, r6
mova @r12+, r7
mova @r12+, r8
mova @r12+, r9
mova @r12+, r10
#else
mov.w @r12+, r14
mov.w @r12+, r1
mov.w @r12+, r4
mov.w @r12+, r5
mov.w @r12+, r6
mov.w @r12+, r7
mov.w @r12+, r8
mov.w @r12+, r9
mov.w @r12+, r10
#endif
; If caller attempts to return 0, return 1 instead.
cmp.w #0, r13
jne .Lnot_zero
mov.w #1, r13
.Lnot_zero:
mov.w r13, r12
#if defined __MSP430X_LARGE__
adda #4, r1
mova r14, r0
#else
add.w #2, r1
mov.w r14, r0
#endif
.size longjmp , . - longjmp
|
4ms/metamodule-plugin-sdk
| 1,089
|
plugin-libc/newlib/libc/machine/d10v/setjmp.S
|
; setjmp/longjmp for D10V. The jmpbuf looks like this:
;
; Register jmpbuf offset
; R6 0x00
; R7 0x02
; R8 0x04
; R9 0x06
; R10 0x08
; R11 0x0a
; R13 (return address) 0x0c
; R15 (SP) 0x0E
.text
.globl setjmp
.type setjmp,@function
.stabs "setjmp.S",100,0,0,setjmp
.stabs "int:t(0,1)=r(0,1);-65536;65535;",128,0,0,0
.stabs "setjmp:F(0,1)",36,0,1,setjmp
setjmp:
; Address of jmpbuf is passed in R0. Save the appropriate registers.
st2w r6, @r0+
st2w r8, @r0+
st2w r10, @r0+
st r13, @r0+
st r15, @r0+
; Return 0 to caller
ldi r0, 0
jmp r13
.Lsetjmp:
.size setjmp,.Lsetjmp-setjmp
.stabs "",36,0,0,.Lsetjmp-setjmp
.globl longjmp
.type longjmp,@function
.stabs "longjmp:F(0,1)",36,0,1,longjmp
longjmp:
; Address of jmpbuf is in R0. Restore the registers.
ld2w r6, @r0+
ld2w r8, @r0+
ld2w r10, @r0+
ld r13, @r0+
ld r15, @r0+
; Value to return to caller is in R1. If caller attemped to return 0,
; return 1 instead.
mv r0, r1
cmpeqi r0, 0
exef0t || ldi r0,1
jmp r13
.Llongjmp:
.size longjmp,.Llongjmp-longjmp
.stabs "",36,0,0,.Llongjmp-longjmp
|
4ms/metamodule-plugin-sdk
| 1,200
|
plugin-libc/newlib/libc/machine/i386/memcpy.S
|
/*
* ====================================================
* Copyright (C) 1998, 2002 by Red Hat Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this
* software is freely granted, provided that this notice
* is preserved.
* ====================================================
*/
#include "i386mach.h"
.global SYM (memcpy)
SOTYPE_FUNCTION(memcpy)
SYM (memcpy):
#ifdef __iamcu__
pushl esi
pushl edi
movl eax,edi
movl edx,esi
rep movsb
popl edi
popl esi
#else
pushl ebp
movl esp,ebp
pushl esi
pushl edi
pushl ebx
movl 8(ebp),edi
movl 16(ebp),ecx
movl 12(ebp),esi
cld
#ifndef __OPTIMIZE_SIZE__
cmpl $8,ecx
jbe .L3
/* move any preceding bytes until destination address is long word aligned */
movl edi,edx
movl ecx,ebx
andl $3,edx
jz .L11
movl $4,ecx
subl edx,ecx
andl $3,ecx
subl ecx,ebx
rep
movsb
mov ebx,ecx
/* move bytes a long word at a time */
.L11:
shrl $2,ecx
.p2align 2
rep
movsl
movl ebx,ecx
andl $3,ecx
#endif /* !__OPTIMIZE_SIZE__ */
/* handle any remaining bytes */
.L3:
rep
movsb
.L5:
movl 8(ebp),eax
leal -12(ebp),esp
popl ebx
popl edi
popl esi
leave
#endif
ret
|
4ms/metamodule-plugin-sdk
| 2,351
|
plugin-libc/newlib/libc/machine/i386/setjmp.S
|
/* This is file is a merger of SETJMP.S and LONGJMP.S */
/*
* This file was modified to use the __USER_LABEL_PREFIX__ and
* __REGISTER_PREFIX__ macros defined by later versions of GNU cpp by
* Joel Sherrill (joel@OARcorp.com)
* Slight change: now includes i386mach.h for this (Werner Almesberger)
*
* Copyright (C) 1991 DJ Delorie
* All rights reserved.
*
* Redistribution, modification, and use in source and binary forms is permitted
* provided that the above copyright notice and following paragraph are
* duplicated in all such forms.
*
* This file is distributed WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
/*
** jmp_buf:
** eax ebx ecx edx esi edi ebp esp eip
** 0 4 8 12 16 20 24 28 32
**
** Intel MCU jmp_buf:
** ebx esi edi ebp esp eip
** 0 4 8 12 16 20
*/
#include "i386mach.h"
.global SYM (setjmp)
.global SYM (longjmp)
SOTYPE_FUNCTION(setjmp)
SOTYPE_FUNCTION(longjmp)
SYM (setjmp):
#ifdef __iamcu__
/* Store EIP. */
movl 0(esp),ecx
movl ecx,20(eax)
movl ebx,0 (eax)
movl esi,4 (eax)
movl edi,8 (eax)
movl ebp,12(eax)
/* Skip return address, which will be pushed onto stack in
longjmp, and store SP. */
leal 4(esp),ecx
movl ecx,16(eax)
xorl eax,eax
#else
pushl ebp
movl esp,ebp
pushl edi
movl 8 (ebp),edi
movl eax,0 (edi)
movl ebx,4 (edi)
movl ecx,8 (edi)
movl edx,12 (edi)
movl esi,16 (edi)
movl -4 (ebp),eax
movl eax,20 (edi)
movl 0 (ebp),eax
movl eax,24 (edi)
movl esp,eax
addl $12,eax
movl eax,28 (edi)
movl 4 (ebp),eax
movl eax,32 (edi)
popl edi
movl $0,eax
leave
#endif
ret
SYM (longjmp):
#ifdef __iamcu__
/* Check retval. */
testl edx,edx
jne 0f
incl edx
0:
/* Restore stack first. */
movl 16(eax),esp
/* Put return address on stack. */
pushl 20(eax)
movl 0(eax),ebx
movl 4(eax),esi
movl 8(eax),edi
movl 12(eax),ebp
movl edx,eax
#else
pushl ebp
movl esp,ebp
movl 8(ebp),edi /* get jmp_buf */
movl 12(ebp),eax /* store retval in j->eax */
testl eax,eax
jne 0f
incl eax
0:
movl eax,0(edi)
movl 24(edi),ebp
__CLI
movl 28(edi),esp
pushl 32(edi)
movl 0(edi),eax
movl 4(edi),ebx
movl 8(edi),ecx
movl 12(edi),edx
movl 16(edi),esi
movl 20(edi),edi
__STI
#endif
ret
|
4ms/metamodule-plugin-sdk
| 2,318
|
plugin-libc/newlib/libc/machine/i386/memmove.S
|
/*
* ====================================================
* Copyright (C) 1998, 2002 by Red Hat Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this
* software is freely granted, provided that this notice
* is preserved.
* ====================================================
*/
#include "i386mach.h"
.global SYM (memmove)
SOTYPE_FUNCTION(memmove)
SYM (memmove):
#ifdef __iamcu__
pushl esi
pushl edi
movl eax,edi
movl edx,esi
cmp esi,edi
ja .Lcopy_backward
je .Lbwd_write_0bytes
rep movsb
popl edi
popl esi
ret
.Lcopy_backward:
lea -1(edi,ecx),edi
lea -1(esi,ecx),esi
std
rep movsb
cld
.Lbwd_write_0bytes:
popl edi
popl esi
#else
pushl ebp
movl esp,ebp
pushl esi
pushl edi
pushl ebx
movl 8(ebp),edi
movl 16(ebp),ecx
movl 12(ebp),esi
/* check for destructive overlap (src < dst && dst < src + length) */
cld
cmpl edi,esi
jae .L2
leal -1(ecx,esi),ebx
cmpl ebx,edi
ja .L2
/* IF: destructive overlap, must copy backwards */
addl ecx,esi
addl ecx,edi
std
#ifndef __OPTIMIZE_SIZE__
cmpl $8,ecx
jbe .L13
.L18:
/* move trailing bytes in reverse until destination address is long word aligned */
movl edi,edx
movl ecx,ebx
andl $3,edx
jz .L21
movl edx,ecx
decl esi
decl edi
subl ecx,ebx
rep
movsb
mov ebx,ecx
incl esi
incl edi
.L21:
/* move bytes in reverse, a long word at a time */
shrl $2,ecx
subl $4,esi
subl $4,edi
rep
movsl
addl $4,esi
addl $4,edi
movl ebx,ecx
andl $3,ecx
#endif /* !__OPTIMIZE_SIZE__ */
/* handle any remaining bytes not on a long word boundary */
.L13:
decl esi
decl edi
.L15:
rep
movsb
jmp .L5
.p2align 4,,7
/* ELSE: no destructive overlap so we copy forwards */
.L2:
#ifndef __OPTIMIZE_SIZE__
cmpl $8,ecx
jbe .L3
/* move any preceding bytes until destination address is long word aligned */
movl edi,edx
movl ecx,ebx
andl $3,edx
jz .L11
movl $4,ecx
subl edx,ecx
andl $3,ecx
subl ecx,ebx
rep
movsb
mov ebx,ecx
/* move bytes a long word at a time */
.L11:
shrl $2,ecx
.p2align 2
rep
movsl
movl ebx,ecx
andl $3,ecx
#endif /* !__OPTIMIZE_SIZE__ */
/* handle any remaining bytes */
.L3:
rep
movsb
.L5:
movl 8(ebp),eax
cld
leal -12(ebp),esp
popl ebx
popl edi
popl esi
leave
#endif
ret
|
4ms/metamodule-plugin-sdk
| 1,548
|
plugin-libc/newlib/libc/machine/i386/memset.S
|
/*
* ====================================================
* Copyright (C) 1998, 2002, 2008 by Red Hat Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this
* software is freely granted, provided that this notice
* is preserved.
* ====================================================
*/
#include "i386mach.h"
.global SYM (memset)
SOTYPE_FUNCTION(memset)
SYM (memset):
#ifdef __iamcu__
pushl edi
movl eax,edi
movzbl dl,eax
mov edi,edx
rep stosb
mov edx,eax
popl edi
#else
pushl ebp
movl esp,ebp
pushl edi
movl 8(ebp),edi
movzbl 12(ebp),eax
movl 16(ebp),ecx
cld
#ifndef __OPTIMIZE_SIZE__
/* Less than 16 bytes won't benefit from the 'rep stosl' loop. */
cmpl $16,ecx
jbe .L19
testl $7,edi
je .L10
/* It turns out that 8-byte aligned 'rep stosl' outperforms
4-byte aligned on some x86 platforms. */
movb al,(edi)
incl edi
decl ecx
testl $7,edi
je .L10
movb al,(edi)
incl edi
decl ecx
testl $7,edi
je .L10
movb al,(edi)
incl edi
decl ecx
testl $7,edi
je .L10
movb al,(edi)
incl edi
decl ecx
testl $7,edi
je .L10
movb al,(edi)
incl edi
decl ecx
testl $7,edi
je .L10
movb al,(edi)
incl edi
decl ecx
testl $7,edi
je .L10
movb al,(edi)
incl edi
decl ecx
/* At this point, ecx>8 and edi%8==0. */
.L10:
movb al,ah
movl eax,edx
sall $16,edx
orl edx,eax
movl ecx,edx
shrl $2,ecx
andl $3,edx
rep
stosl
movl edx,ecx
#endif /* not __OPTIMIZE_SIZE__ */
.L19:
rep
stosb
movl 8(ebp),eax
leal -4(ebp),esp
popl edi
leave
#endif
ret
|
4ms/metamodule-plugin-sdk
| 1,699
|
plugin-libc/newlib/libc/machine/i386/memchr.S
|
/*
* ====================================================
* Copyright (C) 1998, 2002, 2008 by Red Hat Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this
* software is freely granted, provided that this notice
* is preserved.
* ====================================================
*/
#include "i386mach.h"
.global SYM (memchr)
SOTYPE_FUNCTION(memchr)
SYM (memchr):
#ifdef __iamcu__
pushl edi
movl eax,edi
movl edx,eax
xorl edx,edx
testl ecx,ecx
jz L20
repnz
scasb
setnz dl
decl edi
decl edx
andl edi,edx
L20:
movl edx,eax
popl edi
#else
pushl ebp
movl esp,ebp
pushl edi
movzbl 12(ebp),eax
movl 16(ebp),ecx
movl 8(ebp),edi
xorl edx,edx
testl ecx,ecx
jz L20
#ifdef __OPTIMIZE_SIZE__
cld
repnz
scasb
setnz dl
decl edi
#else /* !__OPTIMIZE_SIZE__ */
/* Do byte-wise checks until string is aligned. */
testl $3,edi
je L5
cmpb (edi),al
je L15
incl edi
decl ecx
je L20
testl $3,edi
je L5
cmpb (edi),al
je L15
incl edi
decl ecx
je L20
testl $3,edi
je L5
cmpb (edi),al
je L15
incl edi
decl ecx
je L20
/* Create a mask, then check a word at a time. */
L5:
movb al,ah
movl eax,edx
sall $16,edx
orl edx,eax
pushl ebx
.p2align 4,,7
L8:
subl $4,ecx
jc L9
movl (edi),edx
addl $4,edi
xorl eax,edx
leal -16843009(edx),ebx
notl edx
andl edx,ebx
testl $-2139062144,ebx
je L8
subl $4,edi
L9:
popl ebx
xorl edx,edx
addl $4,ecx
je L20
/* Final byte-wise checks. */
.p2align 4,,7
L10:
cmpb (edi),al
je L15
incl edi
decl ecx
jne L10
xorl edi,edi
#endif /* !__OPTIMIZE_SIZE__ */
L15:
decl edx
andl edi,edx
L20:
movl edx,eax
leal -4(ebp),esp
popl edi
leave
#endif
ret
|
4ms/metamodule-plugin-sdk
| 1,759
|
plugin-libc/newlib/libc/machine/i386/memcmp.S
|
/*
* ====================================================
* Copyright (C) 1998, 2002 by Red Hat Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this
* software is freely granted, provided that this notice
* is preserved.
* ====================================================
*/
#include "i386mach.h"
.global SYM (memcmp)
SOTYPE_FUNCTION(memcmp)
SYM (memcmp):
#ifdef __iamcu__
pushl edi
pushl esi
movl eax,edi
movl edx,esi
cld
/* check if length is zero in which case just return 0 */
xorl eax,eax
testl ecx,ecx
jz L4
/* compare any unaligned bytes or remainder bytes */
repz
cmpsb
/* set output to be < 0 if less than, 0 if equal, or > 0 if greater than */
xorl edx,edx
movb -1(esi),dl
movb -1(edi),al
subl edx,eax
L4:
popl esi
popl edi
#else
pushl ebp
movl esp,ebp
subl $16,esp
pushl ebx
pushl edi
pushl esi
movl 8(ebp),edi
movl 12(ebp),esi
movl 16(ebp),ecx
cld
/* check if length is zero in which case just return 0 */
xorl eax,eax
testl ecx,ecx
jz L4
#ifndef __OPTIMIZE_SIZE__
/* if aligned on long boundary, compare doublewords at a time first */
movl edi,eax
orl esi,eax
testb $3,al
jne BYTECMP
movl ecx,ebx
shrl $2,ecx /* calculate number of long words to compare */
repz
cmpsl
jz L5
subl $4,esi
subl $4,edi
movl $4,ecx
jmp BYTECMP
L5:
andl $3,ebx /* calculate number of remaining bytes */
movl ebx,ecx
#endif /* not __OPTIMIZE_SIZE__ */
BYTECMP: /* compare any unaligned bytes or remainder bytes */
repz
cmpsb
/* set output to be < 0 if less than, 0 if equal, or > 0 if greater than */
L3:
xorl edx,edx
movb -1(esi),dl
xorl eax,eax
movb -1(edi),al
subl edx,eax
L4:
leal -28(ebp),esp
popl esi
popl edi
popl ebx
leave
#endif
ret
|
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