repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
4ms/metamodule-plugin-sdk
| 1,491
|
plugin-libc/newlib/libc/machine/i386/strlen.S
|
/*
* ====================================================
* Copyright (C) 1998, 2002, 2008 by Red Hat Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this
* software is freely granted, provided that this notice
* is preserved.
* ====================================================
*/
#include "i386mach.h"
.global SYM (strlen)
SOTYPE_FUNCTION(strlen)
SYM (strlen):
pushl ebp
movl esp,ebp
pushl edi
#ifdef __iamcu__
movl eax,edx
#else
movl 8(ebp),edx
#endif
#if defined __OPTIMIZE_SIZE__ || defined __iamcu__
cld
movl edx,edi
movl $4294967295,ecx
xor eax,eax
repnz
scasb
#else
/* Modern x86 hardware is much faster at double-word
manipulation than with bytewise repnz scasb. */
/* Do byte-wise checks until string is aligned. */
movl edx,edi
test $3,edi
je L5
movb (edi),cl
incl edi
testb cl,cl
je L15
test $3,edi
je L5
movb (edi),cl
incl edi
testb cl,cl
je L15
test $3,edi
je L5
movb (edi),cl
incl edi
testb cl,cl
je L15
L5:
subl $4,edi
/* loop performing 4 byte mask checking for desired 0 byte */
.p2align 4,,7
L10:
addl $4,edi
movl (edi),ecx
leal -16843009(ecx),eax
notl ecx
andl ecx,eax
testl $-2139062144,eax
je L10
/* Find which of four bytes is 0. */
notl ecx
incl edi
testb cl,cl
je L15
incl edi
shrl $8,ecx
testb cl,cl
je L15
incl edi
shrl $8,ecx
testb cl,cl
je L15
incl edi
#endif
L15:
subl edx,edi
leal -1(edi),eax
leal -4(ebp),esp
popl edi
leave
ret
|
4ms/metamodule-plugin-sdk
| 2,833
|
plugin-libc/newlib/libc/machine/i386/strchr.S
|
/*
* ====================================================
* Copyright (C) 1998, 2002, 2008 by Red Hat Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this
* software is freely granted, provided that this notice
* is preserved.
* ====================================================
*/
#include "i386mach.h"
.global SYM (strchr)
SOTYPE_FUNCTION(strchr)
SYM (strchr):
#ifdef __iamcu__
xorl ecx,ecx
movb dl,cl
/* loop while (*s && *s++ != c) */
leal -1(eax),eax
L15:
incl eax
movb (eax),dl
testb dl,dl
je L14
cmpb cl,dl
jne L15
L14:
/* if (*s == c) return address otherwise return NULL */
cmpb cl,(eax)
je L19
xorl eax,eax
L19:
ret
#else
pushl ebp
movl esp,ebp
pushl edi
pushl ebx
xorl ebx,ebx
movl 8(ebp),edi
addb 12(ebp),bl
#ifndef __OPTIMIZE_SIZE__
/* Special case strchr(p,0). */
je L25
/* Do byte-wise checks until string is aligned. */
test $3,edi
je L5
movl edi,eax
movb (eax),cl
testb cl,cl
je L14
cmpb bl,cl
je L19
incl edi
test $3,edi
je L5
movl edi,eax
movb (eax),cl
testb cl,cl
je L14
cmpb bl,cl
je L19
incl edi
test $3,edi
je L5
movl edi,eax
movb (eax),cl
testb cl,cl
je L14
cmpb bl,cl
je L19
incl edi
/* create 4 byte mask which is just the desired byte repeated 4 times */
L5:
movl ebx,ecx
sall $8,ebx
subl $4,edi
orl ecx,ebx
movl ebx,edx
sall $16,ebx
orl edx,ebx
/* loop performing 4 byte mask checking for 0 byte or desired byte */
.p2align 4,,7
L10:
addl $4,edi
movl (edi),ecx
leal -16843009(ecx),edx
movl ecx,eax
notl eax
andl eax,edx
testl $-2139062144,edx
jne L9
xorl ebx,ecx
leal -16843009(ecx),edx
notl ecx
andl ecx,edx
testl $-2139062144,edx
je L10
#endif /* not __OPTIMIZE_SIZE__ */
/* loop while (*s && *s++ != c) */
L9:
leal -1(edi),eax
.p2align 4,,7
L15:
incl eax
movb (eax),dl
testb dl,dl
je L14
cmpb bl,dl
jne L15
L14:
/* if (*s == c) return address otherwise return NULL */
cmpb bl,(eax)
je L19
xorl eax,eax
L19:
leal -8(ebp),esp
popl ebx
popl edi
leave
ret
#ifndef __OPTIMIZE_SIZE__
/* Special case strchr(p,0). */
#if 0
/* Hideous performance on modern machines. */
L25:
cld
movl $-1,ecx
xor eax,eax
repnz
scasb
leal -1(edi),eax
jmp L19
#endif
L25:
/* Do byte-wise checks until string is aligned. */
test $3,edi
je L26
movl edi,eax
movb (eax),cl
testb cl,cl
je L19
incl edi
test $3,edi
je L26
movl edi,eax
movb (eax),cl
testb cl,cl
je L19
incl edi
test $3,edi
je L26
movl edi,eax
movb (eax),cl
testb cl,cl
je L19
incl edi
L26:
subl $4,edi
/* loop performing 4 byte mask checking for desired 0 byte */
.p2align 4,,7
L27:
addl $4,edi
movl (edi),ecx
leal -16843009(ecx),edx
movl ecx,eax
notl eax
andl eax,edx
testl $-2139062144,edx
je L27
jmp L9
#endif /* !__OPTIMIZE_SIZE__ */
#endif /* __iamcu__ */
|
4ms/metamodule-plugin-sdk
| 2,194
|
plugin-libc/newlib/libc/machine/d30v/setjmp.S
|
; setjmp/longjmp for D30V.
.text
.globl setjmp
.type setjmp,@function
.stabs "setjmp.S",100,0,0,setjmp
.stabs "int:t(0,1)=r(0,1);-2147483648;2147483647;",128,0,0,0
.stabs "setjmp:F(0,1)",36,0,1,setjmp
setjmp:
; Address of jmpbuf is passed in R2. Save the appropriate registers.
st2w r26, @(r2+,r0)
st2w r28, @(r2+,r0)
st2w r30, @(r2+,r0)
st2w r32, @(r2+,r0)
st2w r34, @(r2+,r0)
st2w r36, @(r2+,r0)
st2w r38, @(r2+,r0)
st2w r40, @(r2+,r0)
st2w r42, @(r2+,r0)
st2w r44, @(r2+,r0)
st2w r46, @(r2+,r0)
st2w r48, @(r2+,r0)
st2w r50, @(r2+,r0)
st2w r52, @(r2+,r0)
st2w r54, @(r2+,r0)
st2w r56, @(r2+,r0)
st2w r58, @(r2+,r0)
st2w r60, @(r2+,r0)
st2w r62, @(r2+,r0)
mvfacc r4, a1, 16
mvfacc r5, a1, 0
st2w r4, @(r2+,r0)
mvfsys r4, psw
mvfsys r5, rpt_c
st2w r4, @(r2+,r0)
mvfsys r4, rpt_s
mvfsys r5, rpt_e
st2w r4, @(r2+,r0)
mvfsys r4, mod_s
mvfsys r5, mod_e
st2w r4, @(r2+,r0)
; Return 0 to caller
add r2, r0, r0
jmp link
.Lsetjmp:
.size setjmp,.Lsetjmp-setjmp
.stabs "",36,0,0,.Lsetjmp-setjmp
.globl longjmp
.type longjmp,@function
.stabs "longjmp:F(0,1)",36,0,1,longjmp
longjmp:
; Address of jmpbuf is in R2. Restore the registers.
ld2w r26, @(r2+,r0)
ld2w r28, @(r2+,r0)
ld2w r30, @(r2+,r0)
ld2w r32, @(r2+,r0)
ld2w r34, @(r2+,r0)
ld2w r36, @(r2+,r0)
ld2w r38, @(r2+,r0)
ld2w r40, @(r2+,r0)
ld2w r42, @(r2+,r0)
ld2w r44, @(r2+,r0)
ld2w r46, @(r2+,r0)
ld2w r48, @(r2+,r0)
ld2w r50, @(r2+,r0)
ld2w r52, @(r2+,r0)
ld2w r54, @(r2+,r0)
ld2w r56, @(r2+,r0)
ld2w r58, @(r2+,r0)
ld2w r60, @(r2+,r0)
ld2w r62, @(r2+,r0)
ld2w r4, @(r2+,r0)
mvtacc a1, r4, r5
mvfsys r6, psw
ld2w r4, @(r2+,r0) /* psw, rpt_c */
and r6, r6, 0xfcff /* set rp, md bits from setjmp, leave */
and r4, r4, 0x0300 /* all other psw bits the same */
or r4, r4, r6
mvtsys psw, r4
mvtsys rpt_c, r5
ld2w r4, @(r2+,r0)
mvtsys rpt_s, r4
mvtsys rpt_e, r5
ld2w r4, @(r2+,r0)
mvtsys mod_s, r4
mvtsys mod_e, r5
; Value to return to caller is in R3. If caller attemped to return 0,
; return 1 instead.
cmpeq f0, r3, 0 || add r2, r3, r0
jmp link || add/tx r2, r2, 1
.Llongjmp:
.size longjmp,.Llongjmp-longjmp
.stabs "",36,0,0,.Llongjmp-longjmp
|
4ms/metamodule-plugin-sdk
| 1,762
|
plugin-libc/newlib/libc/machine/aarch64/stpcpy.S
|
/*
stpcpy - copy a string returning pointer to end.
Copyright (c) 2015 ARM Ltd.
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the company nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* This is just a wrapper that uses strcpy code with appropriate
pre-defines. */
#define BUILD_STPCPY
#include "strcpy.S"
|
4ms/metamodule-plugin-sdk
| 7,064
|
plugin-libc/newlib/libc/machine/aarch64/memcpy.S
|
/* Copyright (c) 2012-2013, Linaro Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Linaro nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*
* Copyright (c) 2015 ARM Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Assumptions:
*
* ARMv8-a, AArch64, unaligned accesses.
*
*/
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See memcpy-stub.c */
#else
#define dstin x0
#define src x1
#define count x2
#define dst x3
#define srcend x4
#define dstend x5
#define A_l x6
#define A_lw w6
#define A_h x7
#define A_hw w7
#define B_l x8
#define B_lw w8
#define B_h x9
#define C_l x10
#define C_h x11
#define D_l x12
#define D_h x13
#define E_l src
#define E_h count
#define F_l srcend
#define F_h dst
#define tmp1 x9
#define L(l) .L ## l
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
/* Copies are split into 3 main cases: small copies of up to 16 bytes,
medium copies of 17..96 bytes which are fully unrolled. Large copies
of more than 96 bytes align the destination and use an unrolled loop
processing 64 bytes per iteration.
Small and medium copies read all data before writing, allowing any
kind of overlap, and memmove tailcalls memcpy for these cases as
well as non-overlapping copies.
*/
def_fn memcpy p2align=6
prfm PLDL1KEEP, [src]
add srcend, src, count
add dstend, dstin, count
cmp count, 16
b.ls L(copy16)
cmp count, 96
b.hi L(copy_long)
/* Medium copies: 17..96 bytes. */
sub tmp1, count, 1
ldp A_l, A_h, [src]
tbnz tmp1, 6, L(copy96)
ldp D_l, D_h, [srcend, -16]
tbz tmp1, 5, 1f
ldp B_l, B_h, [src, 16]
ldp C_l, C_h, [srcend, -32]
stp B_l, B_h, [dstin, 16]
stp C_l, C_h, [dstend, -32]
1:
stp A_l, A_h, [dstin]
stp D_l, D_h, [dstend, -16]
ret
.p2align 4
/* Small copies: 0..16 bytes. */
L(copy16):
cmp count, 8
b.lo 1f
ldr A_l, [src]
ldr A_h, [srcend, -8]
str A_l, [dstin]
str A_h, [dstend, -8]
ret
.p2align 4
1:
tbz count, 2, 1f
ldr A_lw, [src]
ldr A_hw, [srcend, -4]
str A_lw, [dstin]
str A_hw, [dstend, -4]
ret
/* Copy 0..3 bytes. Use a branchless sequence that copies the same
byte 3 times if count==1, or the 2nd byte twice if count==2. */
1:
cbz count, 2f
lsr tmp1, count, 1
ldrb A_lw, [src]
ldrb A_hw, [srcend, -1]
ldrb B_lw, [src, tmp1]
strb A_lw, [dstin]
strb B_lw, [dstin, tmp1]
strb A_hw, [dstend, -1]
2: ret
.p2align 4
/* Copy 64..96 bytes. Copy 64 bytes from the start and
32 bytes from the end. */
L(copy96):
ldp B_l, B_h, [src, 16]
ldp C_l, C_h, [src, 32]
ldp D_l, D_h, [src, 48]
ldp E_l, E_h, [srcend, -32]
ldp F_l, F_h, [srcend, -16]
stp A_l, A_h, [dstin]
stp B_l, B_h, [dstin, 16]
stp C_l, C_h, [dstin, 32]
stp D_l, D_h, [dstin, 48]
stp E_l, E_h, [dstend, -32]
stp F_l, F_h, [dstend, -16]
ret
/* Align DST to 16 byte alignment so that we don't cross cache line
boundaries on both loads and stores. There are at least 96 bytes
to copy, so copy 16 bytes unaligned and then align. The loop
copies 64 bytes per iteration and prefetches one iteration ahead. */
.p2align 4
L(copy_long):
and tmp1, dstin, 15
bic dst, dstin, 15
ldp D_l, D_h, [src]
sub src, src, tmp1
add count, count, tmp1 /* Count is now 16 too large. */
ldp A_l, A_h, [src, 16]
stp D_l, D_h, [dstin]
ldp B_l, B_h, [src, 32]
ldp C_l, C_h, [src, 48]
ldp D_l, D_h, [src, 64]!
subs count, count, 128 + 16 /* Test and readjust count. */
b.ls 2f
1:
stp A_l, A_h, [dst, 16]
ldp A_l, A_h, [src, 16]
stp B_l, B_h, [dst, 32]
ldp B_l, B_h, [src, 32]
stp C_l, C_h, [dst, 48]
ldp C_l, C_h, [src, 48]
stp D_l, D_h, [dst, 64]!
ldp D_l, D_h, [src, 64]!
subs count, count, 64
b.hi 1b
/* Write the last full set of 64 bytes. The remainder is at most 64
bytes, so it is safe to always copy 64 bytes from the end even if
there is just 1 byte left. */
2:
ldp E_l, E_h, [srcend, -64]
stp A_l, A_h, [dst, 16]
ldp A_l, A_h, [srcend, -48]
stp B_l, B_h, [dst, 32]
ldp B_l, B_h, [srcend, -32]
stp C_l, C_h, [dst, 48]
ldp C_l, C_h, [srcend, -16]
stp D_l, D_h, [dst, 64]
stp E_l, E_h, [dstend, -64]
stp A_l, A_h, [dstend, -48]
stp B_l, B_h, [dstend, -32]
stp C_l, C_h, [dstend, -16]
ret
.size memcpy, . - memcpy
#endif
|
4ms/metamodule-plugin-sdk
| 2,274
|
plugin-libc/newlib/libc/machine/aarch64/rawmemchr.S
|
/* Copyright (c) 2015-2016, ARM Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the company nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* Assumptions:
*
* ARMv8-a, AArch64, unaligned accesses
*
*/
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See rawmemchr-stub.c. */
#else
#define L(l) .L ## l
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
/* Special case rawmemchr (s, 0) as strlen, otherwise tailcall memchr.
Call strlen without setting up a full frame - it preserves x14/x15.
*/
def_fn rawmemchr p2align=5
.cfi_startproc
cbz w1, L(do_strlen)
mov x2, -1
b memchr
L(do_strlen):
mov x15, x30
.cfi_return_column x15
mov x14, x0
bl strlen
add x0, x14, x0
ret x15
.cfi_endproc
.size rawmemchr, . - rawmemchr
#endif
|
4ms/metamodule-plugin-sdk
| 2,524
|
plugin-libc/newlib/libc/machine/aarch64/setjmp.S
|
/*
Copyright (c) 2011, 2012 ARM Ltd
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define GPR_LAYOUT \
REG_PAIR (x19, x20, 0); \
REG_PAIR (x21, x22, 16); \
REG_PAIR (x23, x24, 32); \
REG_PAIR (x25, x26, 48); \
REG_PAIR (x27, x28, 64); \
REG_PAIR (x29, x30, 80); \
REG_ONE (x16, 96)
#define FPR_LAYOUT \
REG_PAIR ( d8, d9, 112); \
REG_PAIR (d10, d11, 128); \
REG_PAIR (d12, d13, 144); \
REG_PAIR (d14, d15, 160);
// int setjmp (jmp_buf)
.global setjmp
.type setjmp, %function
setjmp:
mov x16, sp
#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
GPR_LAYOUT
FPR_LAYOUT
#undef REG_PAIR
#undef REG_ONE
mov w0, #0
ret
.size setjmp, .-setjmp
// void longjmp (jmp_buf, int) __attribute__ ((noreturn))
.global longjmp
.type longjmp, %function
longjmp:
#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
GPR_LAYOUT
FPR_LAYOUT
#undef REG_PAIR
#undef REG_ONE
mov sp, x16
cmp w1, #0
cinc w0, w1, eq
// use br not ret, as ret is guaranteed to mispredict
br x30
.size longjmp, .-longjmp
|
4ms/metamodule-plugin-sdk
| 10,507
|
plugin-libc/newlib/libc/machine/aarch64/strcpy.S
|
/*
strcpy/stpcpy - copy a string returning pointer to start/end.
Copyright (c) 2013, 2014, 2015 ARM Ltd.
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the company nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See strchr-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64, unaligned accesses, min page size 4k.
*/
/* To build as stpcpy, define BUILD_STPCPY before compiling this file.
To test the page crossing code path more thoroughly, compile with
-DSTRCPY_TEST_PAGE_CROSS - this will force all copies through the slower
entry path. This option is not intended for production use. */
/* Arguments and results. */
#define dstin x0
#define srcin x1
/* Locals and temporaries. */
#define src x2
#define dst x3
#define data1 x4
#define data1w w4
#define data2 x5
#define data2w w5
#define has_nul1 x6
#define has_nul2 x7
#define tmp1 x8
#define tmp2 x9
#define tmp3 x10
#define tmp4 x11
#define zeroones x12
#define data1a x13
#define data2a x14
#define pos x15
#define len x16
#define to_align x17
#ifdef BUILD_STPCPY
#define STRCPY stpcpy
#else
#define STRCPY strcpy
#endif
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
can be done in parallel across the entire word. */
#define REP8_01 0x0101010101010101
#define REP8_7f 0x7f7f7f7f7f7f7f7f
#define REP8_80 0x8080808080808080
/* AArch64 systems have a minimum page size of 4k. We can do a quick
page size check for crossing this boundary on entry and if we
do not, then we can short-circuit much of the entry code. We
expect early page-crossing strings to be rare (probability of
16/MIN_PAGE_SIZE ~= 0.4%), so the branch should be quite
predictable, even with random strings.
We don't bother checking for larger page sizes, the cost of setting
up the correct page size is just not worth the extra gain from
a small reduction in the cases taking the slow path. Note that
we only care about whether the first fetch, which may be
misaligned, crosses a page boundary - after that we move to aligned
fetches for the remainder of the string. */
#ifdef STRCPY_TEST_PAGE_CROSS
/* Make everything that isn't Qword aligned look like a page cross. */
#define MIN_PAGE_P2 4
#else
#define MIN_PAGE_P2 12
#endif
#define MIN_PAGE_SIZE (1 << MIN_PAGE_P2)
def_fn STRCPY p2align=6
/* For moderately short strings, the fastest way to do the copy is to
calculate the length of the string in the same way as strlen, then
essentially do a memcpy of the result. This avoids the need for
multiple byte copies and further means that by the time we
reach the bulk copy loop we know we can always use DWord
accesses. We expect strcpy to rarely be called repeatedly
with the same source string, so branch prediction is likely to
always be difficult - we mitigate against this by preferring
conditional select operations over branches whenever this is
feasible. */
and tmp2, srcin, #(MIN_PAGE_SIZE - 1)
mov zeroones, #REP8_01
and to_align, srcin, #15
cmp tmp2, #(MIN_PAGE_SIZE - 16)
neg tmp1, to_align
/* The first fetch will straddle a (possible) page boundary iff
srcin + 15 causes bit[MIN_PAGE_P2] to change value. A 16-byte
aligned string will never fail the page align check, so will
always take the fast path. */
b.gt .Lpage_cross
.Lpage_cross_ok:
ldp data1, data2, [srcin]
#ifdef __AARCH64EB__
/* Because we expect the end to be found within 16 characters
(profiling shows this is the most common case), it's worth
swapping the bytes now to save having to recalculate the
termination syndrome later. We preserve data1 and data2
so that we can re-use the values later on. */
rev tmp2, data1
sub tmp1, tmp2, zeroones
orr tmp2, tmp2, #REP8_7f
bics has_nul1, tmp1, tmp2
b.ne .Lfp_le8
rev tmp4, data2
sub tmp3, tmp4, zeroones
orr tmp4, tmp4, #REP8_7f
#else
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
bics has_nul1, tmp1, tmp2
b.ne .Lfp_le8
sub tmp3, data2, zeroones
orr tmp4, data2, #REP8_7f
#endif
bics has_nul2, tmp3, tmp4
b.eq .Lbulk_entry
/* The string is short (<=16 bytes). We don't know exactly how
short though, yet. Work out the exact length so that we can
quickly select the optimal copy strategy. */
.Lfp_gt8:
rev has_nul2, has_nul2
clz pos, has_nul2
mov tmp2, #56
add dst, dstin, pos, lsr #3 /* Bits to bytes. */
sub pos, tmp2, pos
#ifdef __AARCH64EB__
lsr data2, data2, pos
#else
lsl data2, data2, pos
#endif
str data2, [dst, #1]
str data1, [dstin]
#ifdef BUILD_STPCPY
add dstin, dst, #8
#endif
ret
.Lfp_le8:
rev has_nul1, has_nul1
clz pos, has_nul1
add dst, dstin, pos, lsr #3 /* Bits to bytes. */
subs tmp2, pos, #24 /* Pos in bits. */
b.lt .Lfp_lt4
#ifdef __AARCH64EB__
mov tmp2, #56
sub pos, tmp2, pos
lsr data2, data1, pos
lsr data1, data1, #32
#else
lsr data2, data1, tmp2
#endif
/* 4->7 bytes to copy. */
str data2w, [dst, #-3]
str data1w, [dstin]
#ifdef BUILD_STPCPY
mov dstin, dst
#endif
ret
.Lfp_lt4:
cbz pos, .Lfp_lt2
/* 2->3 bytes to copy. */
#ifdef __AARCH64EB__
lsr data1, data1, #48
#endif
strh data1w, [dstin]
/* Fall-through, one byte (max) to go. */
.Lfp_lt2:
/* Null-terminated string. Last character must be zero! */
strb wzr, [dst]
#ifdef BUILD_STPCPY
mov dstin, dst
#endif
ret
.p2align 6
/* Aligning here ensures that the entry code and main loop all lies
within one 64-byte cache line. */
.Lbulk_entry:
sub to_align, to_align, #16
stp data1, data2, [dstin]
sub src, srcin, to_align
sub dst, dstin, to_align
b .Lentry_no_page_cross
/* The inner loop deals with two Dwords at a time. This has a
slightly higher start-up cost, but we should win quite quickly,
especially on cores with a high number of issue slots per
cycle, as we get much better parallelism out of the operations. */
.Lmain_loop:
stp data1, data2, [dst], #16
.Lentry_no_page_cross:
ldp data1, data2, [src], #16
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
sub tmp3, data2, zeroones
orr tmp4, data2, #REP8_7f
bic has_nul1, tmp1, tmp2
bics has_nul2, tmp3, tmp4
ccmp has_nul1, #0, #0, eq /* NZCV = 0000 */
b.eq .Lmain_loop
/* Since we know we are copying at least 16 bytes, the fastest way
to deal with the tail is to determine the location of the
trailing NUL, then (re)copy the 16 bytes leading up to that. */
cmp has_nul1, #0
#ifdef __AARCH64EB__
/* For big-endian, carry propagation (if the final byte in the
string is 0x01) means we cannot use has_nul directly. The
easiest way to get the correct byte is to byte-swap the data
and calculate the syndrome a second time. */
csel data1, data1, data2, ne
rev data1, data1
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
bic has_nul1, tmp1, tmp2
#else
csel has_nul1, has_nul1, has_nul2, ne
#endif
rev has_nul1, has_nul1
clz pos, has_nul1
add tmp1, pos, #72
add pos, pos, #8
csel pos, pos, tmp1, ne
add src, src, pos, lsr #3
add dst, dst, pos, lsr #3
ldp data1, data2, [src, #-32]
stp data1, data2, [dst, #-16]
#ifdef BUILD_STPCPY
sub dstin, dst, #1
#endif
ret
.Lpage_cross:
bic src, srcin, #15
/* Start by loading two words at [srcin & ~15], then forcing the
bytes that precede srcin to 0xff. This means they never look
like termination bytes. */
ldp data1, data2, [src]
lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
tst to_align, #7
csetm tmp2, ne
#ifdef __AARCH64EB__
lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
#else
lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
#endif
orr data1, data1, tmp2
orr data2a, data2, tmp2
cmp to_align, #8
csinv data1, data1, xzr, lt
csel data2, data2, data2a, lt
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
sub tmp3, data2, zeroones
orr tmp4, data2, #REP8_7f
bic has_nul1, tmp1, tmp2
bics has_nul2, tmp3, tmp4
ccmp has_nul1, #0, #0, eq /* NZCV = 0000 */
b.eq .Lpage_cross_ok
/* We now need to make data1 and data2 look like they've been
loaded directly from srcin. Do a rotate on the 128-bit value. */
lsl tmp1, to_align, #3 /* Bytes->bits. */
neg tmp2, to_align, lsl #3
#ifdef __AARCH64EB__
lsl data1a, data1, tmp1
lsr tmp4, data2, tmp2
lsl data2, data2, tmp1
orr tmp4, tmp4, data1a
cmp to_align, #8
csel data1, tmp4, data2, lt
rev tmp2, data1
rev tmp4, data2
sub tmp1, tmp2, zeroones
orr tmp2, tmp2, #REP8_7f
sub tmp3, tmp4, zeroones
orr tmp4, tmp4, #REP8_7f
#else
lsr data1a, data1, tmp1
lsl tmp4, data2, tmp2
lsr data2, data2, tmp1
orr tmp4, tmp4, data1a
cmp to_align, #8
csel data1, tmp4, data2, lt
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
sub tmp3, data2, zeroones
orr tmp4, data2, #REP8_7f
#endif
bic has_nul1, tmp1, tmp2
cbnz has_nul1, .Lfp_le8
bic has_nul2, tmp3, tmp4
b .Lfp_gt8
.size STRCPY, . - STRCPY
#endif
|
4ms/metamodule-plugin-sdk
| 5,439
|
plugin-libc/newlib/libc/machine/aarch64/memmove.S
|
/* Copyright (c) 2013, Linaro Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Linaro nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*
* Copyright (c) 2015 ARM Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Assumptions:
*
* ARMv8-a, AArch64, unaligned accesses
*/
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See memmove-stub.c */
#else
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
/* Parameters and result. */
#define dstin x0
#define src x1
#define count x2
#define srcend x3
#define dstend x4
#define tmp1 x5
#define A_l x6
#define A_h x7
#define B_l x8
#define B_h x9
#define C_l x10
#define C_h x11
#define D_l x12
#define D_h x13
#define E_l count
#define E_h tmp1
/* All memmoves up to 96 bytes are done by memcpy as it supports overlaps.
Larger backwards copies are also handled by memcpy. The only remaining
case is forward large copies. The destination is aligned, and an
unrolled loop processes 64 bytes per iteration.
*/
def_fn memmove, 6
sub tmp1, dstin, src
cmp count, 96
ccmp tmp1, count, 2, hi
b.hs memcpy
cbz tmp1, 3f
add dstend, dstin, count
add srcend, src, count
/* Align dstend to 16 byte alignment so that we don't cross cache line
boundaries on both loads and stores. There are at least 96 bytes
to copy, so copy 16 bytes unaligned and then align. The loop
copies 64 bytes per iteration and prefetches one iteration ahead. */
and tmp1, dstend, 15
ldp D_l, D_h, [srcend, -16]
sub srcend, srcend, tmp1
sub count, count, tmp1
ldp A_l, A_h, [srcend, -16]
stp D_l, D_h, [dstend, -16]
ldp B_l, B_h, [srcend, -32]
ldp C_l, C_h, [srcend, -48]
ldp D_l, D_h, [srcend, -64]!
sub dstend, dstend, tmp1
subs count, count, 128
b.ls 2f
nop
1:
stp A_l, A_h, [dstend, -16]
ldp A_l, A_h, [srcend, -16]
stp B_l, B_h, [dstend, -32]
ldp B_l, B_h, [srcend, -32]
stp C_l, C_h, [dstend, -48]
ldp C_l, C_h, [srcend, -48]
stp D_l, D_h, [dstend, -64]!
ldp D_l, D_h, [srcend, -64]!
subs count, count, 64
b.hi 1b
/* Write the last full set of 64 bytes. The remainder is at most 64
bytes, so it is safe to always copy 64 bytes from the start even if
there is just 1 byte left. */
2:
ldp E_l, E_h, [src, 48]
stp A_l, A_h, [dstend, -16]
ldp A_l, A_h, [src, 32]
stp B_l, B_h, [dstend, -32]
ldp B_l, B_h, [src, 16]
stp C_l, C_h, [dstend, -48]
ldp C_l, C_h, [src]
stp D_l, D_h, [dstend, -64]
stp E_l, E_h, [dstin, 48]
stp A_l, A_h, [dstin, 32]
stp B_l, B_h, [dstin, 16]
stp C_l, C_h, [dstin]
3: ret
.size memmove, . - memmove
#endif
|
4ms/metamodule-plugin-sdk
| 5,109
|
plugin-libc/newlib/libc/machine/aarch64/strchrnul.S
|
/*
strchrnul - find a character or nul in a string
Copyright (c) 2014, ARM Limited
All rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the company nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See strchrnul-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64
* Neon Available.
*/
/* Arguments and results. */
#define srcin x0
#define chrin w1
#define result x0
#define src x2
#define tmp1 x3
#define wtmp2 w4
#define tmp3 x5
#define vrepchr v0
#define vdata1 v1
#define vdata2 v2
#define vhas_nul1 v3
#define vhas_nul2 v4
#define vhas_chr1 v5
#define vhas_chr2 v6
#define vrepmask v7
#define vend1 v16
/* Core algorithm.
For each 32-byte hunk we calculate a 64-bit syndrome value, with
two bits per byte (LSB is always in bits 0 and 1, for both big
and little-endian systems). For each tuple, bit 0 is set iff
the relevant byte matched the requested character or nul. Since the
bits in the syndrome reflect exactly the order in which things occur
in the original string a count_trailing_zeros() operation will
identify exactly which byte is causing the termination. */
/* Locals and temporaries. */
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
def_fn strchrnul
/* Magic constant 0x40100401 to allow us to identify which lane
matches the termination condition. */
mov wtmp2, #0x0401
movk wtmp2, #0x4010, lsl #16
dup vrepchr.16b, chrin
bic src, srcin, #31 /* Work with aligned 32-byte hunks. */
dup vrepmask.4s, wtmp2
ands tmp1, srcin, #31
b.eq .Lloop
/* Input string is not 32-byte aligned. Rather than forcing
the padding bytes to a safe value, we calculate the syndrome
for all the bytes, but then mask off those bits of the
syndrome that are related to the padding. */
ld1 {vdata1.16b, vdata2.16b}, [src], #32
neg tmp1, tmp1
cmeq vhas_nul1.16b, vdata1.16b, #0
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
cmeq vhas_nul2.16b, vdata2.16b, #0
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
orr vhas_chr1.16b, vhas_chr1.16b, vhas_nul1.16b
orr vhas_chr2.16b, vhas_chr2.16b, vhas_nul2.16b
and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
lsl tmp1, tmp1, #1
addp vend1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
mov tmp3, #~0
addp vend1.16b, vend1.16b, vend1.16b // 128->64
lsr tmp1, tmp3, tmp1
mov tmp3, vend1.2d[0]
bic tmp1, tmp3, tmp1 // Mask padding bits.
cbnz tmp1, .Ltail
.Lloop:
ld1 {vdata1.16b, vdata2.16b}, [src], #32
cmeq vhas_nul1.16b, vdata1.16b, #0
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
cmeq vhas_nul2.16b, vdata2.16b, #0
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
/* Use a fast check for the termination condition. */
orr vhas_chr1.16b, vhas_nul1.16b, vhas_chr1.16b
orr vhas_chr2.16b, vhas_nul2.16b, vhas_chr2.16b
orr vend1.16b, vhas_chr1.16b, vhas_chr2.16b
addp vend1.2d, vend1.2d, vend1.2d
mov tmp1, vend1.2d[0]
cbz tmp1, .Lloop
/* Termination condition found. Now need to establish exactly why
we terminated. */
and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
addp vend1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
addp vend1.16b, vend1.16b, vend1.16b // 128->64
mov tmp1, vend1.2d[0]
.Ltail:
/* Count the trailing zeros, by bit reversing... */
rbit tmp1, tmp1
/* Re-bias source. */
sub src, src, #32
clz tmp1, tmp1 /* ... and counting the leading zeros. */
/* tmp1 is twice the offset into the fragment. */
add result, src, tmp1, lsr #1
ret
.size strchrnul, . - strchrnul
#endif
|
4ms/metamodule-plugin-sdk
| 8,771
|
plugin-libc/newlib/libc/machine/aarch64/strncmp.S
|
/* Copyright (c) 2013, 2018, Linaro Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Linaro nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See strcmp-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64
*/
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
#define REP8_01 0x0101010101010101
#define REP8_7f 0x7f7f7f7f7f7f7f7f
#define REP8_80 0x8080808080808080
/* Parameters and result. */
#define src1 x0
#define src2 x1
#define limit x2
#define result x0
/* Internal variables. */
#define data1 x3
#define data1w w3
#define data2 x4
#define data2w w4
#define has_nul x5
#define diff x6
#define syndrome x7
#define tmp1 x8
#define tmp2 x9
#define tmp3 x10
#define zeroones x11
#define pos x12
#define limit_wd x13
#define mask x14
#define endloop x15
#define count mask
.text
.p2align 6
.rep 7
nop /* Pad so that the loop below fits a cache line. */
.endr
def_fn strncmp
cbz limit, .Lret0
eor tmp1, src1, src2
mov zeroones, #REP8_01
tst tmp1, #7
and count, src1, #7
b.ne .Lmisaligned8
cbnz count, .Lmutual_align
/* Calculate the number of full and partial words -1. */
sub limit_wd, limit, #1 /* limit != 0, so no underflow. */
lsr limit_wd, limit_wd, #3 /* Convert to Dwords. */
/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
can be done in parallel across the entire word. */
/* Start of performance-critical section -- one 64B cache line. */
.Lloop_aligned:
ldr data1, [src1], #8
ldr data2, [src2], #8
.Lstart_realigned:
subs limit_wd, limit_wd, #1
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
eor diff, data1, data2 /* Non-zero if differences found. */
csinv endloop, diff, xzr, pl /* Last Dword or differences. */
bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
ccmp endloop, #0, #0, eq
b.eq .Lloop_aligned
/* End of performance-critical section -- one 64B cache line. */
/* Not reached the limit, must have found the end or a diff. */
tbz limit_wd, #63, .Lnot_limit
/* Limit % 8 == 0 => all bytes significant. */
ands limit, limit, #7
b.eq .Lnot_limit
lsl limit, limit, #3 /* Bits -> bytes. */
mov mask, #~0
#ifdef __AARCH64EB__
lsr mask, mask, limit
#else
lsl mask, mask, limit
#endif
bic data1, data1, mask
bic data2, data2, mask
/* Make sure that the NUL byte is marked in the syndrome. */
orr has_nul, has_nul, mask
.Lnot_limit:
orr syndrome, diff, has_nul
#ifndef __AARCH64EB__
rev syndrome, syndrome
rev data1, data1
/* The MS-non-zero bit of the syndrome marks either the first bit
that is different, or the top bit of the first zero byte.
Shifting left now will bring the critical information into the
top bits. */
clz pos, syndrome
rev data2, data2
lsl data1, data1, pos
lsl data2, data2, pos
/* But we need to zero-extend (char is unsigned) the value and then
perform a signed 32-bit subtraction. */
lsr data1, data1, #56
sub result, data1, data2, lsr #56
ret
#else
/* For big-endian we cannot use the trick with the syndrome value
as carry-propagation can corrupt the upper bits if the trailing
bytes in the string contain 0x01. */
/* However, if there is no NUL byte in the dword, we can generate
the result directly. We can't just subtract the bytes as the
MSB might be significant. */
cbnz has_nul, 1f
cmp data1, data2
cset result, ne
cneg result, result, lo
ret
1:
/* Re-compute the NUL-byte detection, using a byte-reversed value. */
rev tmp3, data1
sub tmp1, tmp3, zeroones
orr tmp2, tmp3, #REP8_7f
bic has_nul, tmp1, tmp2
rev has_nul, has_nul
orr syndrome, diff, has_nul
clz pos, syndrome
/* The MS-non-zero bit of the syndrome marks either the first bit
that is different, or the top bit of the first zero byte.
Shifting left now will bring the critical information into the
top bits. */
lsl data1, data1, pos
lsl data2, data2, pos
/* But we need to zero-extend (char is unsigned) the value and then
perform a signed 32-bit subtraction. */
lsr data1, data1, #56
sub result, data1, data2, lsr #56
ret
#endif
.Lmutual_align:
/* Sources are mutually aligned, but are not currently at an
alignment boundary. Round down the addresses and then mask off
the bytes that precede the start point.
We also need to adjust the limit calculations, but without
overflowing if the limit is near ULONG_MAX. */
bic src1, src1, #7
bic src2, src2, #7
ldr data1, [src1], #8
neg tmp3, count, lsl #3 /* 64 - bits(bytes beyond align). */
ldr data2, [src2], #8
mov tmp2, #~0
sub limit_wd, limit, #1 /* limit != 0, so no underflow. */
#ifdef __AARCH64EB__
/* Big-endian. Early bytes are at MSB. */
lsl tmp2, tmp2, tmp3 /* Shift (count & 63). */
#else
/* Little-endian. Early bytes are at LSB. */
lsr tmp2, tmp2, tmp3 /* Shift (count & 63). */
#endif
and tmp3, limit_wd, #7
lsr limit_wd, limit_wd, #3
/* Adjust the limit. Only low 3 bits used, so overflow irrelevant. */
add limit, limit, count
add tmp3, tmp3, count
orr data1, data1, tmp2
orr data2, data2, tmp2
add limit_wd, limit_wd, tmp3, lsr #3
b .Lstart_realigned
.p2align 6
/* Don't bother with dwords for up to 16 bytes. */
.Lmisaligned8:
cmp limit, #16
b.hs .Ltry_misaligned_words
.Lbyte_loop:
/* Perhaps we can do better than this. */
ldrb data1w, [src1], #1
ldrb data2w, [src2], #1
subs limit, limit, #1
ccmp data1w, #1, #0, hi /* NZCV = 0b0000. */
ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */
b.eq .Lbyte_loop
.Ldone:
sub result, data1, data2
ret
/* Align the SRC1 to a dword by doing a bytewise compare and then do
the dword loop. */
.Ltry_misaligned_words:
lsr limit_wd, limit, #3
cbz count, .Ldo_misaligned
neg count, count
and count, count, #7
sub limit, limit, count
lsr limit_wd, limit, #3
.Lpage_end_loop:
ldrb data1w, [src1], #1
ldrb data2w, [src2], #1
cmp data1w, #1
ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */
b.ne .Ldone
subs count, count, #1
b.hi .Lpage_end_loop
.Ldo_misaligned:
/* Prepare ourselves for the next page crossing. Unlike the aligned
loop, we fetch 1 less dword because we risk crossing bounds on
SRC2. */
mov count, #8
subs limit_wd, limit_wd, #1
b.lo .Ldone_loop
.Lloop_misaligned:
and tmp2, src2, #0xff8
eor tmp2, tmp2, #0xff8
cbz tmp2, .Lpage_end_loop
ldr data1, [src1], #8
ldr data2, [src2], #8
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
eor diff, data1, data2 /* Non-zero if differences found. */
bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
ccmp diff, #0, #0, eq
b.ne .Lnot_limit
subs limit_wd, limit_wd, #1
b.pl .Lloop_misaligned
.Ldone_loop:
/* We found a difference or a NULL before the limit was reached. */
and limit, limit, #7
cbz limit, .Lnot_limit
/* Read the last word. */
sub src1, src1, 8
sub src2, src2, 8
ldr data1, [src1, limit]
ldr data2, [src2, limit]
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
eor diff, data1, data2 /* Non-zero if differences found. */
bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
ccmp diff, #0, #0, eq
b.ne .Lnot_limit
.Lret0:
mov result, #0
ret
.size strncmp, . - strncmp
#endif
|
4ms/metamodule-plugin-sdk
| 6,769
|
plugin-libc/newlib/libc/machine/aarch64/memset.S
|
/* Copyright (c) 2012-2013, Linaro Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Linaro nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*
* Copyright (c) 2015 ARM Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Assumptions:
*
* ARMv8-a, AArch64, unaligned accesses
*
*/
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See memset-stub.c */
#else
#define dstin x0
#define val x1
#define valw w1
#define count x2
#define dst x3
#define dstend x4
#define tmp1 x5
#define tmp1w w5
#define tmp2 x6
#define tmp2w w6
#define zva_len x7
#define zva_lenw w7
#define L(l) .L ## l
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
def_fn memset p2align=6
dup v0.16B, valw
add dstend, dstin, count
cmp count, 96
b.hi L(set_long)
cmp count, 16
b.hs L(set_medium)
mov val, v0.D[0]
/* Set 0..15 bytes. */
tbz count, 3, 1f
str val, [dstin]
str val, [dstend, -8]
ret
nop
1: tbz count, 2, 2f
str valw, [dstin]
str valw, [dstend, -4]
ret
2: cbz count, 3f
strb valw, [dstin]
tbz count, 1, 3f
strh valw, [dstend, -2]
3: ret
/* Set 17..96 bytes. */
L(set_medium):
str q0, [dstin]
tbnz count, 6, L(set96)
str q0, [dstend, -16]
tbz count, 5, 1f
str q0, [dstin, 16]
str q0, [dstend, -32]
1: ret
.p2align 4
/* Set 64..96 bytes. Write 64 bytes from the start and
32 bytes from the end. */
L(set96):
str q0, [dstin, 16]
stp q0, q0, [dstin, 32]
stp q0, q0, [dstend, -32]
ret
.p2align 3
nop
L(set_long):
and valw, valw, 255
bic dst, dstin, 15
str q0, [dstin]
cmp count, 256
ccmp valw, 0, 0, cs
b.eq L(try_zva)
L(no_zva):
sub count, dstend, dst /* Count is 16 too large. */
sub dst, dst, 16 /* Dst is biased by -32. */
sub count, count, 64 + 16 /* Adjust count and bias for loop. */
1: stp q0, q0, [dst, 32]
stp q0, q0, [dst, 64]!
L(tail64):
subs count, count, 64
b.hi 1b
2: stp q0, q0, [dstend, -64]
stp q0, q0, [dstend, -32]
ret
.p2align 3
L(try_zva):
mrs tmp1, dczid_el0
tbnz tmp1w, 4, L(no_zva)
and tmp1w, tmp1w, 15
cmp tmp1w, 4 /* ZVA size is 64 bytes. */
b.ne L(zva_128)
/* Write the first and last 64 byte aligned block using stp rather
than using DC ZVA. This is faster on some cores.
*/
L(zva_64):
str q0, [dst, 16]
stp q0, q0, [dst, 32]
bic dst, dst, 63
stp q0, q0, [dst, 64]
stp q0, q0, [dst, 96]
sub count, dstend, dst /* Count is now 128 too large. */
sub count, count, 128+64+64 /* Adjust count and bias for loop. */
add dst, dst, 128
nop
1: dc zva, dst
add dst, dst, 64
subs count, count, 64
b.hi 1b
stp q0, q0, [dst, 0]
stp q0, q0, [dst, 32]
stp q0, q0, [dstend, -64]
stp q0, q0, [dstend, -32]
ret
.p2align 3
L(zva_128):
cmp tmp1w, 5 /* ZVA size is 128 bytes. */
b.ne L(zva_other)
str q0, [dst, 16]
stp q0, q0, [dst, 32]
stp q0, q0, [dst, 64]
stp q0, q0, [dst, 96]
bic dst, dst, 127
sub count, dstend, dst /* Count is now 128 too large. */
sub count, count, 128+128 /* Adjust count and bias for loop. */
add dst, dst, 128
1: dc zva, dst
add dst, dst, 128
subs count, count, 128
b.hi 1b
stp q0, q0, [dstend, -128]
stp q0, q0, [dstend, -96]
stp q0, q0, [dstend, -64]
stp q0, q0, [dstend, -32]
ret
L(zva_other):
mov tmp2w, 4
lsl zva_lenw, tmp2w, tmp1w
add tmp1, zva_len, 64 /* Max alignment bytes written. */
cmp count, tmp1
blo L(no_zva)
sub tmp2, zva_len, 1
add tmp1, dst, zva_len
add dst, dst, 16
subs count, tmp1, dst /* Actual alignment bytes to write. */
bic tmp1, tmp1, tmp2 /* Aligned dc zva start address. */
beq 2f
1: stp q0, q0, [dst], 64
stp q0, q0, [dst, -32]
subs count, count, 64
b.hi 1b
2: mov dst, tmp1
sub count, dstend, tmp1 /* Remaining bytes to write. */
subs count, count, zva_len
b.lo 4f
3: dc zva, dst
add dst, dst, zva_len
subs count, count, zva_len
b.hs 3b
4: add count, count, zva_len
sub dst, dst, 32 /* Bias dst for tail loop. */
b L(tail64)
.size memset, . - memset
#endif
|
4ms/metamodule-plugin-sdk
| 6,488
|
plugin-libc/newlib/libc/machine/aarch64/strrchr.S
|
/*
strrchr - find last instance of a character in a string
Copyright (c) 2014, ARM Limited
All rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the company nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See strchr-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64
* Neon Available.
*/
/* Arguments and results. */
#define srcin x0
#define chrin w1
#define result x0
#define src x2
#define tmp1 x3
#define wtmp2 w4
#define tmp3 x5
#define src_match x6
#define src_offset x7
#define const_m1 x8
#define tmp4 x9
#define nul_match x10
#define chr_match x11
#define vrepchr v0
#define vdata1 v1
#define vdata2 v2
#define vhas_nul1 v3
#define vhas_nul2 v4
#define vhas_chr1 v5
#define vhas_chr2 v6
#define vrepmask_0 v7
#define vrepmask_c v16
#define vend1 v17
#define vend2 v18
/* Core algorithm.
For each 32-byte hunk we calculate a 64-bit syndrome value, with
two bits per byte (LSB is always in bits 0 and 1, for both big
and little-endian systems). For each tuple, bit 0 is set iff
the relevant byte matched the requested character; bit 1 is set
iff the relevant byte matched the NUL end of string (we trigger
off bit0 for the special case of looking for NUL). Since the bits
in the syndrome reflect exactly the order in which things occur
in the original string a count_trailing_zeros() operation will
identify exactly which byte is causing the termination, and why. */
/* Locals and temporaries. */
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
def_fn strrchr
/* Magic constant 0x40100401 to allow us to identify which lane
matches the requested byte. Magic constant 0x80200802 used
similarly for NUL termination. */
mov wtmp2, #0x0401
movk wtmp2, #0x4010, lsl #16
dup vrepchr.16b, chrin
bic src, srcin, #31 /* Work with aligned 32-byte hunks. */
dup vrepmask_c.4s, wtmp2
mov src_offset, #0
ands tmp1, srcin, #31
add vrepmask_0.4s, vrepmask_c.4s, vrepmask_c.4s /* equiv: lsl #1 */
b.eq .Laligned
/* Input string is not 32-byte aligned. Rather than forcing
the padding bytes to a safe value, we calculate the syndrome
for all the bytes, but then mask off those bits of the
syndrome that are related to the padding. */
ld1 {vdata1.16b, vdata2.16b}, [src], #32
neg tmp1, tmp1
cmeq vhas_nul1.16b, vdata1.16b, #0
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
cmeq vhas_nul2.16b, vdata2.16b, #0
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
and vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
and vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
and vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
and vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
addp vhas_nul1.16b, vhas_nul1.16b, vhas_nul2.16b // 256->128
addp vhas_chr1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
addp vhas_nul1.16b, vhas_nul1.16b, vhas_nul1.16b // 128->64
addp vhas_chr1.16b, vhas_chr1.16b, vhas_chr1.16b // 128->64
mov nul_match, vhas_nul1.2d[0]
lsl tmp1, tmp1, #1
mov const_m1, #~0
mov chr_match, vhas_chr1.2d[0]
lsr tmp3, const_m1, tmp1
bic nul_match, nul_match, tmp3 // Mask padding bits.
bic chr_match, chr_match, tmp3 // Mask padding bits.
cbnz nul_match, .Ltail
.Lloop:
cmp chr_match, #0
csel src_match, src, src_match, ne
csel src_offset, chr_match, src_offset, ne
.Laligned:
ld1 {vdata1.16b, vdata2.16b}, [src], #32
cmeq vhas_nul1.16b, vdata1.16b, #0
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
cmeq vhas_nul2.16b, vdata2.16b, #0
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
addp vend1.16b, vhas_nul1.16b, vhas_nul2.16b // 256->128
and vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
and vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
addp vhas_chr1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
addp vend1.16b, vend1.16b, vend1.16b // 128->64
addp vhas_chr1.16b, vhas_chr1.16b, vhas_chr1.16b // 128->64
mov nul_match, vend1.2d[0]
mov chr_match, vhas_chr1.2d[0]
cbz nul_match, .Lloop
and vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
and vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
addp vhas_nul1.16b, vhas_nul1.16b, vhas_nul2.16b
addp vhas_nul1.16b, vhas_nul1.16b, vhas_nul1.16b
mov nul_match, vhas_nul1.2d[0]
.Ltail:
/* Work out exactly where the string ends. */
sub tmp4, nul_match, #1
eor tmp4, tmp4, nul_match
ands chr_match, chr_match, tmp4
/* And pick the values corresponding to the last match. */
csel src_match, src, src_match, ne
csel src_offset, chr_match, src_offset, ne
/* Count down from the top of the syndrome to find the last match. */
clz tmp3, src_offset
/* Src_match points beyond the word containing the match, so we can
simply subtract half the bit-offset into the syndrome. Because
we are counting down, we need to go back one more character. */
add tmp3, tmp3, #2
sub result, src_match, tmp3, lsr #1
/* But if the syndrome shows no match was found, then return NULL. */
cmp src_offset, #0
csel result, result, xzr, ne
ret
.size strrchr, . - strrchr
#endif
|
4ms/metamodule-plugin-sdk
| 5,428
|
plugin-libc/newlib/libc/machine/aarch64/memchr.S
|
/*
* memchr - find a character in a memory zone
*
* Copyright (c) 2014, ARM Limited
* All rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the company nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See memchr-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64
* Neon Available.
*/
/* Arguments and results. */
#define srcin x0
#define chrin w1
#define cntin x2
#define result x0
#define src x3
#define tmp x4
#define wtmp2 w5
#define synd x6
#define soff x9
#define cntrem x10
#define vrepchr v0
#define vdata1 v1
#define vdata2 v2
#define vhas_chr1 v3
#define vhas_chr2 v4
#define vrepmask v5
#define vend v6
/*
* Core algorithm:
*
* For each 32-byte chunk we calculate a 64-bit syndrome value, with two bits
* per byte. For each tuple, bit 0 is set if the relevant byte matched the
* requested character and bit 1 is not used (faster than using a 32bit
* syndrome). Since the bits in the syndrome reflect exactly the order in which
* things occur in the original string, counting trailing zeros allows to
* identify exactly which byte has matched.
*/
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
def_fn memchr
/* Do not dereference srcin if no bytes to compare. */
cbz cntin, .Lzero_length
/*
* Magic constant 0x40100401 allows us to identify which lane matches
* the requested byte.
*/
mov wtmp2, #0x0401
movk wtmp2, #0x4010, lsl #16
dup vrepchr.16b, chrin
/* Work with aligned 32-byte chunks */
bic src, srcin, #31
dup vrepmask.4s, wtmp2
ands soff, srcin, #31
and cntrem, cntin, #31
b.eq .Lloop
/*
* Input string is not 32-byte aligned. We calculate the syndrome
* value for the aligned 32 bytes block containing the first bytes
* and mask the irrelevant part.
*/
ld1 {vdata1.16b, vdata2.16b}, [src], #32
sub tmp, soff, #32
adds cntin, cntin, tmp
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
addp vend.16b, vhas_chr1.16b, vhas_chr2.16b /* 256->128 */
addp vend.16b, vend.16b, vend.16b /* 128->64 */
mov synd, vend.2d[0]
/* Clear the soff*2 lower bits */
lsl tmp, soff, #1
lsr synd, synd, tmp
lsl synd, synd, tmp
/* The first block can also be the last */
b.ls .Lmasklast
/* Have we found something already? */
cbnz synd, .Ltail
.Lloop:
ld1 {vdata1.16b, vdata2.16b}, [src], #32
subs cntin, cntin, #32
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
/* If we're out of data we finish regardless of the result */
b.ls .Lend
/* Use a fast check for the termination condition */
orr vend.16b, vhas_chr1.16b, vhas_chr2.16b
addp vend.2d, vend.2d, vend.2d
mov synd, vend.2d[0]
/* We're not out of data, loop if we haven't found the character */
cbz synd, .Lloop
.Lend:
/* Termination condition found, let's calculate the syndrome value */
and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
addp vend.16b, vhas_chr1.16b, vhas_chr2.16b /* 256->128 */
addp vend.16b, vend.16b, vend.16b /* 128->64 */
mov synd, vend.2d[0]
/* Only do the clear for the last possible block */
b.hi .Ltail
.Lmasklast:
/* Clear the (32 - ((cntrem + soff) % 32)) * 2 upper bits */
add tmp, cntrem, soff
and tmp, tmp, #31
sub tmp, tmp, #32
neg tmp, tmp, lsl #1
lsl synd, synd, tmp
lsr synd, synd, tmp
.Ltail:
/* Count the trailing zeros using bit reversing */
rbit synd, synd
/* Compensate the last post-increment */
sub src, src, #32
/* Check that we have found a character */
cmp synd, #0
/* And count the leading zeros */
clz synd, synd
/* Compute the potential result */
add result, src, synd, lsr #1
/* Select result or NULL */
csel result, xzr, result, eq
ret
.Lzero_length:
mov result, #0
ret
.size memchr, . - memchr
#endif
|
4ms/metamodule-plugin-sdk
| 5,918
|
plugin-libc/newlib/libc/machine/aarch64/memcmp.S
|
/* memcmp - compare memory
Copyright (c) 2018 Linaro Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Linaro nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*
* Copyright (c) 2017 ARM Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See memcmp-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64, unaligned accesses.
*/
#define L(l) .L ## l
/* Parameters and result. */
#define src1 x0
#define src2 x1
#define limit x2
#define result w0
/* Internal variables. */
#define data1 x3
#define data1w w3
#define data1h x4
#define data2 x5
#define data2w w5
#define data2h x6
#define tmp1 x7
#define tmp2 x8
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
def_fn memcmp p2align=6
subs limit, limit, 8
b.lo L(less8)
ldr data1, [src1], 8
ldr data2, [src2], 8
cmp data1, data2
b.ne L(return)
subs limit, limit, 8
b.gt L(more16)
ldr data1, [src1, limit]
ldr data2, [src2, limit]
b L(return)
L(more16):
ldr data1, [src1], 8
ldr data2, [src2], 8
cmp data1, data2
bne L(return)
/* Jump directly to comparing the last 16 bytes for 32 byte (or less)
strings. */
subs limit, limit, 16
b.ls L(last_bytes)
/* We overlap loads between 0-32 bytes at either side of SRC1 when we
try to align, so limit it only to strings larger than 128 bytes. */
cmp limit, 96
b.ls L(loop16)
/* Align src1 and adjust src2 with bytes not yet done. */
and tmp1, src1, 15
add limit, limit, tmp1
sub src1, src1, tmp1
sub src2, src2, tmp1
/* Loop performing 16 bytes per iteration using aligned src1.
Limit is pre-decremented by 16 and must be larger than zero.
Exit if <= 16 bytes left to do or if the data is not equal. */
.p2align 4
L(loop16):
ldp data1, data1h, [src1], 16
ldp data2, data2h, [src2], 16
subs limit, limit, 16
ccmp data1, data2, 0, hi
ccmp data1h, data2h, 0, eq
b.eq L(loop16)
cmp data1, data2
bne L(return)
mov data1, data1h
mov data2, data2h
cmp data1, data2
bne L(return)
/* Compare last 1-16 bytes using unaligned access. */
L(last_bytes):
add src1, src1, limit
add src2, src2, limit
ldp data1, data1h, [src1]
ldp data2, data2h, [src2]
cmp data1, data2
bne L(return)
mov data1, data1h
mov data2, data2h
cmp data1, data2
/* Compare data bytes and set return value to 0, -1 or 1. */
L(return):
#ifndef __AARCH64EB__
rev data1, data1
rev data2, data2
#endif
cmp data1, data2
L(ret_eq):
cset result, ne
cneg result, result, lo
ret
.p2align 4
/* Compare up to 8 bytes. Limit is [-8..-1]. */
L(less8):
adds limit, limit, 4
b.lo L(less4)
ldr data1w, [src1], 4
ldr data2w, [src2], 4
cmp data1w, data2w
b.ne L(return)
sub limit, limit, 4
L(less4):
adds limit, limit, 4
beq L(ret_eq)
L(byte_loop):
ldrb data1w, [src1], 1
ldrb data2w, [src2], 1
subs limit, limit, 1
ccmp data1w, data2w, 0, ne /* NZCV = 0b0000. */
b.eq L(byte_loop)
sub result, data1w, data2w
ret
.size memcmp, . - memcmp
#endif
|
4ms/metamodule-plugin-sdk
| 7,735
|
plugin-libc/newlib/libc/machine/aarch64/strlen.S
|
/* Copyright (c) 2013-2015, Linaro Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Linaro nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See strlen-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64, unaligned accesses, min page size 4k.
*/
/* To test the page crossing code path more thoroughly, compile with
-DTEST_PAGE_CROSS - this will force all calls through the slower
entry path. This option is not intended for production use. */
/* Arguments and results. */
#define srcin x0
#define len x0
/* Locals and temporaries. */
#define src x1
#define data1 x2
#define data2 x3
#define has_nul1 x4
#define has_nul2 x5
#define tmp1 x4
#define tmp2 x5
#define tmp3 x6
#define tmp4 x7
#define zeroones x8
#define L(l) .L ## l
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
can be done in parallel across the entire word. A faster check
(X - 1) & 0x80 is zero for non-NUL ASCII characters, but gives
false hits for characters 129..255. */
#define REP8_01 0x0101010101010101
#define REP8_7f 0x7f7f7f7f7f7f7f7f
#define REP8_80 0x8080808080808080
#ifdef TEST_PAGE_CROSS
# define MIN_PAGE_SIZE 15
#else
# define MIN_PAGE_SIZE 4096
#endif
/* Since strings are short on average, we check the first 16 bytes
of the string for a NUL character. In order to do an unaligned ldp
safely we have to do a page cross check first. If there is a NUL
byte we calculate the length from the 2 8-byte words using
conditional select to reduce branch mispredictions (it is unlikely
strlen will be repeatedly called on strings with the same length).
If the string is longer than 16 bytes, we align src so don't need
further page cross checks, and process 32 bytes per iteration
using the fast NUL check. If we encounter non-ASCII characters,
fallback to a second loop using the full NUL check.
If the page cross check fails, we read 16 bytes from an aligned
address, remove any characters before the string, and continue
in the main loop using aligned loads. Since strings crossing a
page in the first 16 bytes are rare (probability of
16/MIN_PAGE_SIZE ~= 0.4%), this case does not need to be optimized.
AArch64 systems have a minimum page size of 4k. We don't bother
checking for larger page sizes - the cost of setting up the correct
page size is just not worth the extra gain from a small reduction in
the cases taking the slow path. Note that we only care about
whether the first fetch, which may be misaligned, crosses a page
boundary. */
def_fn strlen p2align=6
and tmp1, srcin, MIN_PAGE_SIZE - 1
mov zeroones, REP8_01
cmp tmp1, MIN_PAGE_SIZE - 16
b.gt L(page_cross)
ldp data1, data2, [srcin]
#ifdef __AARCH64EB__
/* For big-endian, carry propagation (if the final byte in the
string is 0x01) means we cannot use has_nul1/2 directly.
Since we expect strings to be small and early-exit,
byte-swap the data now so has_null1/2 will be correct. */
rev data1, data1
rev data2, data2
#endif
sub tmp1, data1, zeroones
orr tmp2, data1, REP8_7f
sub tmp3, data2, zeroones
orr tmp4, data2, REP8_7f
bics has_nul1, tmp1, tmp2
bic has_nul2, tmp3, tmp4
ccmp has_nul2, 0, 0, eq
beq L(main_loop_entry)
/* Enter with C = has_nul1 == 0. */
csel has_nul1, has_nul1, has_nul2, cc
mov len, 8
rev has_nul1, has_nul1
clz tmp1, has_nul1
csel len, xzr, len, cc
add len, len, tmp1, lsr 3
ret
/* The inner loop processes 32 bytes per iteration and uses the fast
NUL check. If we encounter non-ASCII characters, use a second
loop with the accurate NUL check. */
.p2align 4
L(main_loop_entry):
bic src, srcin, 15
sub src, src, 16
L(main_loop):
ldp data1, data2, [src, 32]!
.Lpage_cross_entry:
sub tmp1, data1, zeroones
sub tmp3, data2, zeroones
orr tmp2, tmp1, tmp3
tst tmp2, zeroones, lsl 7
bne 1f
ldp data1, data2, [src, 16]
sub tmp1, data1, zeroones
sub tmp3, data2, zeroones
orr tmp2, tmp1, tmp3
tst tmp2, zeroones, lsl 7
beq L(main_loop)
add src, src, 16
1:
/* The fast check failed, so do the slower, accurate NUL check. */
orr tmp2, data1, REP8_7f
orr tmp4, data2, REP8_7f
bics has_nul1, tmp1, tmp2
bic has_nul2, tmp3, tmp4
ccmp has_nul2, 0, 0, eq
beq L(nonascii_loop)
/* Enter with C = has_nul1 == 0. */
L(tail):
#ifdef __AARCH64EB__
/* For big-endian, carry propagation (if the final byte in the
string is 0x01) means we cannot use has_nul1/2 directly. The
easiest way to get the correct byte is to byte-swap the data
and calculate the syndrome a second time. */
csel data1, data1, data2, cc
rev data1, data1
sub tmp1, data1, zeroones
orr tmp2, data1, REP8_7f
bic has_nul1, tmp1, tmp2
#else
csel has_nul1, has_nul1, has_nul2, cc
#endif
sub len, src, srcin
rev has_nul1, has_nul1
add tmp2, len, 8
clz tmp1, has_nul1
csel len, len, tmp2, cc
add len, len, tmp1, lsr 3
ret
L(nonascii_loop):
ldp data1, data2, [src, 16]!
sub tmp1, data1, zeroones
orr tmp2, data1, REP8_7f
sub tmp3, data2, zeroones
orr tmp4, data2, REP8_7f
bics has_nul1, tmp1, tmp2
bic has_nul2, tmp3, tmp4
ccmp has_nul2, 0, 0, eq
bne L(tail)
ldp data1, data2, [src, 16]!
sub tmp1, data1, zeroones
orr tmp2, data1, REP8_7f
sub tmp3, data2, zeroones
orr tmp4, data2, REP8_7f
bics has_nul1, tmp1, tmp2
bic has_nul2, tmp3, tmp4
ccmp has_nul2, 0, 0, eq
beq L(nonascii_loop)
b L(tail)
/* Load 16 bytes from [srcin & ~15] and force the bytes that precede
srcin to 0x7f, so we ignore any NUL bytes before the string.
Then continue in the aligned loop. */
L(page_cross):
bic src, srcin, 15
ldp data1, data2, [src]
lsl tmp1, srcin, 3
mov tmp4, -1
#ifdef __AARCH64EB__
/* Big-endian. Early bytes are at MSB. */
lsr tmp1, tmp4, tmp1 /* Shift (tmp1 & 63). */
#else
/* Little-endian. Early bytes are at LSB. */
lsl tmp1, tmp4, tmp1 /* Shift (tmp1 & 63). */
#endif
orr tmp1, tmp1, REP8_80
orn data1, data1, tmp1
orn tmp2, data2, tmp1
tst srcin, 8
csel data1, data1, tmp4, eq
csel data2, data2, tmp2, eq
b L(page_cross_entry)
.size strlen, . - strlen
#endif
|
4ms/metamodule-plugin-sdk
| 5,909
|
plugin-libc/newlib/libc/machine/aarch64/strnlen.S
|
/* strnlen - calculate the length of a string with limit.
Copyright (c) 2013, Linaro Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Linaro nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See strlen-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64
*/
/* Arguments and results. */
#define srcin x0
#define len x0
#define limit x1
/* Locals and temporaries. */
#define src x2
#define data1 x3
#define data2 x4
#define data2a x5
#define has_nul1 x6
#define has_nul2 x7
#define tmp1 x8
#define tmp2 x9
#define tmp3 x10
#define tmp4 x11
#define zeroones x12
#define pos x13
#define limit_wd x14
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
#define REP8_01 0x0101010101010101
#define REP8_7f 0x7f7f7f7f7f7f7f7f
#define REP8_80 0x8080808080808080
.text
.p2align 6
.Lstart:
/* Pre-pad to ensure critical loop begins an icache line. */
.rep 7
nop
.endr
/* Put this code here to avoid wasting more space with pre-padding. */
.Lhit_limit:
mov len, limit
ret
def_fn strnlen
cbz limit, .Lhit_limit
mov zeroones, #REP8_01
bic src, srcin, #15
ands tmp1, srcin, #15
b.ne .Lmisaligned
/* Calculate the number of full and partial words -1. */
sub limit_wd, limit, #1 /* Limit != 0, so no underflow. */
lsr limit_wd, limit_wd, #4 /* Convert to Qwords. */
/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
can be done in parallel across the entire word. */
/* The inner loop deals with two Dwords at a time. This has a
slightly higher start-up cost, but we should win quite quickly,
especially on cores with a high number of issue slots per
cycle, as we get much better parallelism out of the operations. */
/* Start of critial section -- keep to one 64Byte cache line. */
.Lloop:
ldp data1, data2, [src], #16
.Lrealigned:
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
sub tmp3, data2, zeroones
orr tmp4, data2, #REP8_7f
bic has_nul1, tmp1, tmp2
bic has_nul2, tmp3, tmp4
subs limit_wd, limit_wd, #1
orr tmp1, has_nul1, has_nul2
ccmp tmp1, #0, #0, pl /* NZCV = 0000 */
b.eq .Lloop
/* End of critical section -- keep to one 64Byte cache line. */
orr tmp1, has_nul1, has_nul2
cbz tmp1, .Lhit_limit /* No null in final Qword. */
/* We know there's a null in the final Qword. The easiest thing
to do now is work out the length of the string and return
MIN (len, limit). */
sub len, src, srcin
cbz has_nul1, .Lnul_in_data2
#ifdef __AARCH64EB__
mov data2, data1
#endif
sub len, len, #8
mov has_nul2, has_nul1
.Lnul_in_data2:
#ifdef __AARCH64EB__
/* For big-endian, carry propagation (if the final byte in the
string is 0x01) means we cannot use has_nul directly. The
easiest way to get the correct byte is to byte-swap the data
and calculate the syndrome a second time. */
rev data2, data2
sub tmp1, data2, zeroones
orr tmp2, data2, #REP8_7f
bic has_nul2, tmp1, tmp2
#endif
sub len, len, #8
rev has_nul2, has_nul2
clz pos, has_nul2
add len, len, pos, lsr #3 /* Bits to bytes. */
cmp len, limit
csel len, len, limit, ls /* Return the lower value. */
ret
.Lmisaligned:
/* Deal with a partial first word.
We're doing two things in parallel here;
1) Calculate the number of words (but avoiding overflow if
limit is near ULONG_MAX) - to do this we need to work out
limit + tmp1 - 1 as a 65-bit value before shifting it;
2) Load and mask the initial data words - we force the bytes
before the ones we are interested in to 0xff - this ensures
early bytes will not hit any zero detection. */
sub limit_wd, limit, #1
neg tmp4, tmp1
cmp tmp1, #8
and tmp3, limit_wd, #15
lsr limit_wd, limit_wd, #4
mov tmp2, #~0
ldp data1, data2, [src], #16
lsl tmp4, tmp4, #3 /* Bytes beyond alignment -> bits. */
add tmp3, tmp3, tmp1
#ifdef __AARCH64EB__
/* Big-endian. Early bytes are at MSB. */
lsl tmp2, tmp2, tmp4 /* Shift (tmp1 & 63). */
#else
/* Little-endian. Early bytes are at LSB. */
lsr tmp2, tmp2, tmp4 /* Shift (tmp1 & 63). */
#endif
add limit_wd, limit_wd, tmp3, lsr #4
orr data1, data1, tmp2
orr data2a, data2, tmp2
csinv data1, data1, xzr, le
csel data2, data2, data2a, le
b .Lrealigned
.size strnlen, . - .Lstart /* Include pre-padding in size. */
#endif
|
4ms/metamodule-plugin-sdk
| 5,783
|
plugin-libc/newlib/libc/machine/aarch64/strchr.S
|
/*
strchr - find a character in a string
Copyright (c) 2014, ARM Limited
All rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the company nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See strchr-stub.c */
#else
/* Assumptions:
*
* ARMv8-a, AArch64
* Neon Available.
*/
/* Arguments and results. */
#define srcin x0
#define chrin w1
#define result x0
#define src x2
#define tmp1 x3
#define wtmp2 w4
#define tmp3 x5
#define vrepchr v0
#define vdata1 v1
#define vdata2 v2
#define vhas_nul1 v3
#define vhas_nul2 v4
#define vhas_chr1 v5
#define vhas_chr2 v6
#define vrepmask_0 v7
#define vrepmask_c v16
#define vend1 v17
#define vend2 v18
/* Core algorithm.
For each 32-byte hunk we calculate a 64-bit syndrome value, with
two bits per byte (LSB is always in bits 0 and 1, for both big
and little-endian systems). For each tuple, bit 0 is set iff
the relevant byte matched the requested character; bit 1 is set
iff the relevant byte matched the NUL end of string (we trigger
off bit0 for the special case of looking for NUL). Since the bits
in the syndrome reflect exactly the order in which things occur
in the original string a count_trailing_zeros() operation will
identify exactly which byte is causing the termination, and why. */
/* Locals and temporaries. */
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
def_fn strchr
/* Magic constant 0x40100401 to allow us to identify which lane
matches the requested byte. Magic constant 0x80200802 used
similarly for NUL termination. */
mov wtmp2, #0x0401
movk wtmp2, #0x4010, lsl #16
dup vrepchr.16b, chrin
bic src, srcin, #31 /* Work with aligned 32-byte hunks. */
dup vrepmask_c.4s, wtmp2
ands tmp1, srcin, #31
add vrepmask_0.4s, vrepmask_c.4s, vrepmask_c.4s /* equiv: lsl #1 */
b.eq .Lloop
/* Input string is not 32-byte aligned. Rather than forcing
the padding bytes to a safe value, we calculate the syndrome
for all the bytes, but then mask off those bits of the
syndrome that are related to the padding. */
ld1 {vdata1.16b, vdata2.16b}, [src], #32
neg tmp1, tmp1
cmeq vhas_nul1.16b, vdata1.16b, #0
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
cmeq vhas_nul2.16b, vdata2.16b, #0
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
and vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
and vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
and vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
and vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b
orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b
lsl tmp1, tmp1, #1
addp vend1.16b, vend1.16b, vend2.16b // 256->128
mov tmp3, #~0
addp vend1.16b, vend1.16b, vend2.16b // 128->64
lsr tmp1, tmp3, tmp1
mov tmp3, vend1.2d[0]
bic tmp1, tmp3, tmp1 // Mask padding bits.
cbnz tmp1, .Ltail
.Lloop:
ld1 {vdata1.16b, vdata2.16b}, [src], #32
cmeq vhas_nul1.16b, vdata1.16b, #0
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
cmeq vhas_nul2.16b, vdata2.16b, #0
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
/* Use a fast check for the termination condition. */
orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b
orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b
orr vend1.16b, vend1.16b, vend2.16b
addp vend1.2d, vend1.2d, vend1.2d
mov tmp1, vend1.2d[0]
cbz tmp1, .Lloop
/* Termination condition found. Now need to establish exactly why
we terminated. */
and vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
and vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
and vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
and vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b
orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b
addp vend1.16b, vend1.16b, vend2.16b // 256->128
addp vend1.16b, vend1.16b, vend2.16b // 128->64
mov tmp1, vend1.2d[0]
.Ltail:
/* Count the trailing zeros, by bit reversing... */
rbit tmp1, tmp1
/* Re-bias source. */
sub src, src, #32
clz tmp1, tmp1 /* And counting the leading zeros. */
/* Tmp1 is even if the target charager was found first. Otherwise
we've found the end of string and we weren't looking for NUL. */
tst tmp1, #1
add result, src, tmp1, lsr #1
csel result, result, xzr, eq
ret
.size strchr, . - strchr
#endif
|
4ms/metamodule-plugin-sdk
| 6,465
|
plugin-libc/newlib/libc/machine/aarch64/strcmp.S
|
/* Copyright (c) 2012-2018, Linaro Limited
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Linaro nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* Assumptions:
*
* ARMv8-a, AArch64
*/
#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
/* See strcmp-stub.c */
#else
.macro def_fn f p2align=0
.text
.p2align \p2align
.global \f
.type \f, %function
\f:
.endm
#define L(label) .L ## label
#define REP8_01 0x0101010101010101
#define REP8_7f 0x7f7f7f7f7f7f7f7f
#define REP8_80 0x8080808080808080
/* Parameters and result. */
#define src1 x0
#define src2 x1
#define result x0
/* Internal variables. */
#define data1 x2
#define data1w w2
#define data2 x3
#define data2w w3
#define has_nul x4
#define diff x5
#define syndrome x6
#define tmp1 x7
#define tmp2 x8
#define tmp3 x9
#define zeroones x10
#define pos x11
/* Start of performance-critical section -- one 64B cache line. */
def_fn strcmp p2align=6
eor tmp1, src1, src2
mov zeroones, #REP8_01
tst tmp1, #7
b.ne L(misaligned8)
ands tmp1, src1, #7
b.ne L(mutual_align)
/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
can be done in parallel across the entire word. */
L(loop_aligned):
ldr data1, [src1], #8
ldr data2, [src2], #8
L(start_realigned):
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
eor diff, data1, data2 /* Non-zero if differences found. */
bic has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
orr syndrome, diff, has_nul
cbz syndrome, L(loop_aligned)
/* End of performance-critical section -- one 64B cache line. */
L(end):
#ifndef __AARCH64EB__
rev syndrome, syndrome
rev data1, data1
/* The MS-non-zero bit of the syndrome marks either the first bit
that is different, or the top bit of the first zero byte.
Shifting left now will bring the critical information into the
top bits. */
clz pos, syndrome
rev data2, data2
lsl data1, data1, pos
lsl data2, data2, pos
/* But we need to zero-extend (char is unsigned) the value and then
perform a signed 32-bit subtraction. */
lsr data1, data1, #56
sub result, data1, data2, lsr #56
ret
#else
/* For big-endian we cannot use the trick with the syndrome value
as carry-propagation can corrupt the upper bits if the trailing
bytes in the string contain 0x01. */
/* However, if there is no NUL byte in the dword, we can generate
the result directly. We can't just subtract the bytes as the
MSB might be significant. */
cbnz has_nul, 1f
cmp data1, data2
cset result, ne
cneg result, result, lo
ret
1:
/* Re-compute the NUL-byte detection, using a byte-reversed value. */
rev tmp3, data1
sub tmp1, tmp3, zeroones
orr tmp2, tmp3, #REP8_7f
bic has_nul, tmp1, tmp2
rev has_nul, has_nul
orr syndrome, diff, has_nul
clz pos, syndrome
/* The MS-non-zero bit of the syndrome marks either the first bit
that is different, or the top bit of the first zero byte.
Shifting left now will bring the critical information into the
top bits. */
lsl data1, data1, pos
lsl data2, data2, pos
/* But we need to zero-extend (char is unsigned) the value and then
perform a signed 32-bit subtraction. */
lsr data1, data1, #56
sub result, data1, data2, lsr #56
ret
#endif
L(mutual_align):
/* Sources are mutually aligned, but are not currently at an
alignment boundary. Round down the addresses and then mask off
the bytes that preceed the start point. */
bic src1, src1, #7
bic src2, src2, #7
lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
ldr data1, [src1], #8
neg tmp1, tmp1 /* Bits to alignment -64. */
ldr data2, [src2], #8
mov tmp2, #~0
#ifdef __AARCH64EB__
/* Big-endian. Early bytes are at MSB. */
lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
#else
/* Little-endian. Early bytes are at LSB. */
lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
#endif
orr data1, data1, tmp2
orr data2, data2, tmp2
b L(start_realigned)
L(misaligned8):
/* Align SRC1 to 8 bytes and then compare 8 bytes at a time, always
checking to make sure that we don't access beyond page boundary in
SRC2. */
tst src1, #7
b.eq L(loop_misaligned)
L(do_misaligned):
ldrb data1w, [src1], #1
ldrb data2w, [src2], #1
cmp data1w, #1
ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */
b.ne L(done)
tst src1, #7
b.ne L(do_misaligned)
L(loop_misaligned):
/* Test if we are within the last dword of the end of a 4K page. If
yes then jump back to the misaligned loop to copy a byte at a time. */
and tmp1, src2, #0xff8
eor tmp1, tmp1, #0xff8
cbz tmp1, L(do_misaligned)
ldr data1, [src1], #8
ldr data2, [src2], #8
sub tmp1, data1, zeroones
orr tmp2, data1, #REP8_7f
eor diff, data1, data2 /* Non-zero if differences found. */
bic has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
orr syndrome, diff, has_nul
cbz syndrome, L(loop_misaligned)
b L(end)
L(done):
sub result, data1, data2
ret
.size strcmp, .-strcmp
#endif
|
4ms/metamodule-plugin-sdk
| 2,546
|
plugin-libc/newlib/libc/machine/frv/setjmp.S
|
# setjmp/longjmp for Frv. The jmpbuf looks like this:
#
# Register jmpbuf offset
# R16-R31 0x0-0x03c
# R48-R63 0x40-0x7c
# FR16-FR31 0x80-0xbc
# FR48-FR63 0xc0-0xfc
# LR 0x100
# SP 0x104
# FP 0x108
#
# R8 contains the pointer to jmpbuf
#include <frv-asm.h>
.text
.global EXT(setjmp)
.type EXT(setjmp),@function
EXT(setjmp):
stdi gr16, @(gr8,0)
stdi gr18, @(gr8,8)
stdi gr20, @(gr8,16)
stdi gr22, @(gr8,24)
stdi gr24, @(gr8,32)
stdi gr26, @(gr8,40)
stdi gr28, @(gr8,48)
stdi gr30, @(gr8,56)
#if __FRV_GPR__ != 32
stdi gr48, @(gr8,64)
stdi gr50, @(gr8,72)
stdi gr52, @(gr8,80)
stdi gr54, @(gr8,88)
stdi gr56, @(gr8,96)
stdi gr58, @(gr8,104)
stdi gr60, @(gr8,112)
stdi gr62, @(gr8,120)
#endif
#if __FRV_FPR__ != 0
stdfi fr16, @(gr8,128)
stdfi fr18, @(gr8,136)
stdfi fr20, @(gr8,144)
stdfi fr22, @(gr8,152)
stdfi fr24, @(gr8,160)
stdfi fr26, @(gr8,168)
stdfi fr28, @(gr8,176)
stdfi fr30, @(gr8,184)
#if __FRV_FPR__ != 32
stdfi fr48, @(gr8,192)
stdfi fr50, @(gr8,200)
stdfi fr52, @(gr8,208)
stdfi fr54, @(gr8,216)
stdfi fr56, @(gr8,224)
stdfi fr58, @(gr8,232)
stdfi fr60, @(gr8,240)
stdfi fr62, @(gr8,248)
#endif
#endif
movsg lr, gr4
sti gr4, @(gr8,256)
sti sp, @(gr8,260)
sti fp, @(gr8,264)
mov gr0,gr8
ret
.Lend1:
.size EXT(setjmp),.Lend1-EXT(setjmp)
.global EXT(longjmp)
.type EXT(longjmp),@function
EXT(longjmp):
lddi @(gr8,0), gr16
lddi @(gr8,8), gr18
lddi @(gr8,16), gr20
lddi @(gr8,24), gr22
lddi @(gr8,32), gr24
lddi @(gr8,40), gr26
lddi @(gr8,48), gr28
lddi @(gr8,56), gr30
#if __FRV_GPR__ != 32
lddi @(gr8,64), gr48
lddi @(gr8,72), gr50
lddi @(gr8,80), gr52
lddi @(gr8,88), gr54
lddi @(gr8,96), gr56
lddi @(gr8,104), gr58
lddi @(gr8,112), gr60
lddi @(gr8,120), gr62
#endif
#if __FRV_FPR__ != 0
lddfi @(gr8,128), fr16
lddfi @(gr8,136), fr18
lddfi @(gr8,144), fr20
lddfi @(gr8,152), fr22
lddfi @(gr8,160), fr24
lddfi @(gr8,168), fr26
lddfi @(gr8,176), fr28
lddfi @(gr8,184), fr30
#if __FRV_FPR__ != 32
lddfi @(gr8,192), fr48
lddfi @(gr8,200), fr50
lddfi @(gr8,208), fr52
lddfi @(gr8,216), fr54
lddfi @(gr8,224), fr56
lddfi @(gr8,232), fr58
lddfi @(gr8,240), fr60
lddfi @(gr8,248), fr62
#endif
#endif
ldi @(gr8,256), gr4
movgs gr4,lr
ldi @(gr8,260), sp
ldi @(gr8,264), fp
# Value to return is in r9. If zero, return 1
cmp gr9, gr0, icc0
setlos #1, gr8
ckne icc0, cc4
cmov gr9, gr8, cc4, 1
ret
.Lend2:
.size EXT(longjmp),.Lend2-EXT(longjmp)
|
4ms/metamodule-plugin-sdk
| 2,325
|
plugin-libc/newlib/libc/machine/epiphany/setjmp.S
|
/* setjmp and longjmp
Copyright (c) 2011, Adapteva, Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Adapteva nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
.file "setjmp.S"
.section .text
.align 4
.global _setjmp
.type _setjmp, %function
_setjmp:
strd lr,[r0]
strd r4,[r0,1]
strd r6,[r0,2]
strd r8,[r0,3]
strd r10,[r0,4]
strd r32,[r0,5]
strd r34,[r0,6]
strd r36,[r0,7]
strd r38,[r0,8]
str sp,[r0,18]
mov r0,#0
rts
.size _setjmp, .-_setjmp
.global setjmp
.set setjmp, _setjmp
.global _longjmp
_longjmp:
ldrd lr,[r0] ; return address / r15
ldrd r4,[r0,1]
ldrd r6,[r0,2]
ldrd r8,[r0,3]
ldrd r10,[r0,4]
ldrd r32,[r0,5]
ldrd r34,[r0,6]
ldrd r36,[r0,7]
ldrd r38,[r0,8]
ldr sp,[r0,18]
sub r1,r1,0
mov r0,#1
movne r0,r1
jr lr
.size _longjmp, .-_longjmp
.global longjmp
.set longjmp, _longjmp
|
4ms/metamodule-plugin-sdk
| 2,935
|
plugin-libc/newlib/libc/machine/lm32/setjmp.S
|
/*
* setjmp/longjmp for LatticeMico32.
* Contributed by Jon Beniston <jon@beniston.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
.section .text
.align 4
.globl setjmp
.type setjmp,@function
.globl longjmp
.type longjmp,@function
/* setjmp: save all callee saves into jmp_buf
r1 - Address of jmp_buf
*/
setjmp:
sw (r1+0), r11
sw (r1+4), r12
sw (r1+8), r13
sw (r1+12), r14
sw (r1+16), r15
sw (r1+20), r16
sw (r1+24), r17
sw (r1+28), r18
sw (r1+32), r19
sw (r1+36), r20
sw (r1+40), r21
sw (r1+44), r22
sw (r1+48), r23
sw (r1+52), r24
sw (r1+56), r25
sw (r1+60), gp
sw (r1+64), fp
sw (r1+68), sp
sw (r1+72), ra
mvi r1, 0
ret
/* longjmp: restore all callee saves from jmp_buf
r1 - Address of jmb_buf
r2 - Value to return with
*/
.global longjmp
.type longjmp,@function
.align 4
longjmp:
lw r11, (r1+0)
lw r12, (r1+4)
lw r13, (r1+8)
lw r14, (r1+12)
lw r15, (r1+16)
lw r16, (r1+20)
lw r17, (r1+24)
lw r18, (r1+28)
lw r19, (r1+32)
lw r20, (r1+36)
lw r21, (r1+40)
lw r22, (r1+44)
lw r23, (r1+48)
lw r24, (r1+52)
lw r25, (r1+56)
lw gp, (r1+60)
lw fp, (r1+64)
lw sp, (r1+68)
lw ra, (r1+72)
mv r1, r2
ret
|
4ms/metamodule-plugin-sdk
| 1,979
|
plugin-libc/newlib/libc/machine/moxie/setjmp.S
|
/* A setjmp.c for Moxie
Copyright (C) 2009, 2019 Anthony Green
The authors hereby grant permission to use, copy, modify, distribute,
and license this software and its documentation for any purpose, provided
that existing copyright notices are retained in all copies and that this
notice is included verbatim in any distributions. No written agreement,
license, or royalty fee is required for any of the authorized uses.
Modifications to this software may be copyrighted by their authors
and need not follow the licensing terms described here, provided that
the new terms are clearly indicated on the first page of each file where
they apply. */
# setjmp/longjmp for moxie. The jmpbuf looks like this:
#
# Register jmpbuf offset
# $r6 0x00
# $r7 0x04
# $r8 0x08
# $r9 0x0c
# $r10 0x10
# $fp 0x14
# $sp 0x18
# stack frame fp 0x1c
# stack frame ra 0x20
# stack frame sc 0x25
.text
.global setjmp
.type setjmp,@function
setjmp:
st.l ($r0), $r6
sto.l 0x04($r0), $r7
sto.l 0x08($r0), $r8
sto.l 0x0c($r0), $r9
sto.l 0x10($r0), $r10
sto.l 0x14($r0), $sp
sto.l 0x18($r0), $fp
ldo.l $r1, 0x00($fp)
sto.l 0x1c($r0), $r1
ldo.l $r1, 0x04($fp)
sto.l 0x20($r0), $r1
ldo.l $r1, 0x08($fp)
sto.l 0x24($r0), $r1
xor $r0, $r0
ret
.Lend1:
.size setjmp,.Lend1-setjmp
.global longjmp
.type longjmp,@function
longjmp:
ldo.l $r6, 0x00($r0)
ldo.l $r7, 0x04($r0)
ldo.l $r8, 0x08($r0)
ldo.l $r9, 0x0c($r0)
ldo.l $r10, 0x10($r0)
ldo.l $sp, 0x14($r0)
ldo.l $fp, 0x18($r0)
ldo.l $r2, 0x1c($r0)
sto.l 0x0($fp), $r2
ldo.l $r2, 0x20($r0)
sto.l 0x4($fp), $r2
ldo.l $r2, 0x24($r0)
sto.l 0x8($fp), $r2
ldo.l $r2, 0x08($r0)
mov $r0, $r1
xor $r2, $r2
cmp $r0, $r2
beq .Lreturn1
ret
.Lreturn1:
inc $r0, 1
ret
.Lend2:
.size longjmp,.Lend2-longjmp
|
4ms/metamodule-plugin-sdk
| 2,776
|
plugin-libc/newlib/libc/machine/microblaze/setjmp.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* setjmp - save stack context for non-local goto
* args - r5 - jmp_buf
*
* jmpbuf frame structure
* ---------------------
*
* +-------------+ + 0
* | r1 |
* +-------------+ + 4
* | r13 |
* | . |
* | . |
* | . |
* | r31 |
* +-------------+ + 80
* | . |
* | . |
*/
.globl setjmp
.section .text
.align 2
.ent setjmp
setjmp:
swi r1, r5, 0
swi r13, r5, 4
swi r14, r5, 8
swi r15, r5, 12
swi r16, r5, 16
swi r17, r5, 20
swi r18, r5, 24
swi r19, r5, 28
swi r20, r5, 32
swi r21, r5, 36
swi r22, r5, 40
swi r23, r5, 44
swi r24, r5, 48
swi r25, r5, 52
swi r26, r5, 56
swi r27, r5, 60
swi r28, r5, 64
swi r29, r5, 68
swi r30, r5, 72
swi r31, r5, 76
rtsd r15, 8
or r3, r0, r0
.end setjmp
|
4ms/metamodule-plugin-sdk
| 2,800
|
plugin-libc/newlib/libc/machine/microblaze/longjmp.S
|
/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Xilinx nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* longjmp - non-local jump to a saved stack context
* args - r5 - jmp_buf
* r6 - val
*
* jmpbuf frame structure
* ---------------------
*
* +-------------+ + 0
* | r1 |
* +-------------+ + 4
* | r13 |
* | . |
* | . |
* | . |
* | r31 |
* +-------------+ + 80
* | . |
* | . |
*/
.globl longjmp
.section .text
.align 2
.ent longjmp
longjmp:
lwi r1, r5, 0
lwi r13, r5, 4
lwi r14, r5, 8
lwi r15, r5, 12
lwi r16, r5, 16
lwi r17, r5, 20
lwi r18, r5, 24
lwi r19, r5, 28
lwi r20, r5, 32
lwi r21, r5, 36
lwi r22, r5, 40
lwi r23, r5, 44
lwi r24, r5, 48
lwi r25, r5, 52
lwi r26, r5, 56
lwi r27, r5, 60
lwi r28, r5, 64
lwi r29, r5, 68
lwi r30, r5, 72
lwi r31, r5, 76
rtsd r15, 8
or r3, r0, r6
.end longjmp
|
4ms/metamodule-plugin-sdk
| 6,575
|
plugin-libc/newlib/libc/machine/hppa/memcpy.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/* HPUX_ID: @(#) $Revision$ */
/*
* memcpy(s1, s2, n)
*
* Copy n characters from s2 to s1; returns s1.
*/
#define d_addr arg0
#define s_addr arg1
#define count arg2
#define tmp5 arg3
#define tmp1 r19
#define tmp2 r20
#define tmp3 r21
#define tmp4 r22
#define tmp6 r31
#include "DEFS.h"
ENTRY(memcpy)
comib,>= 5,count,byteloop /* If count is <= 6 don't get fancy.*/
movb,=,n d_addr,ret0,done /* The return value is defined to be the value of d_addr. DELAY SLOT */
/* if d_addr is null then exit */
extru s_addr,31,2,tmp1 /* Extract the low two bits of the source address. */
extru d_addr,31,2,tmp2 /* Extract the low two bits of the destination address. */
add count,tmp2,count /* pre increment the count to adjust for alignment of s1 */
comb,<> tmp2,tmp1,not_aligned /* see if s1 is aligned w.r.t. s2. */
dep 0,31,2,s_addr /* Compute the word address of the source. DELAY SLOT. */
/* aligned */
/* We will now begin the 16 byte at a time word move if count >= 16 ! */
/* Else we will branch to the 4 byte-at-a time word move ! */
addibt,<,n -16,count,chekchunk /* If count < 16 then we can't move 16 byte chunks ! */
/* actually we can legally move 13 or more bytes on the first loop. */
/* These loads and stores are done so as to prevent processor interlock. */
chunks:
ldwm 16(0,s_addr),tmp1 /* tmp1 = *s_addr s_addr += 16 */
ldw -12(0,s_addr),tmp2 /* tmp2 = 2nd word */
ldw -8(0,s_addr),tmp3 /* tmp3 = 3rd word */
ldw -4(0,s_addr),tmp4 /* tmp4 = 4th word */
/* Now store the results ! */
stbys,b,m tmp1,4(0,d_addr) /* tmp1 = 1st word stored d_addr += 16 also take care of front porch. */
stwm tmp2,4(0,d_addr) /* tmp2 = 2nd word stored. */
stwm tmp3,4(0,d_addr) /* tmp3 = 3rd word stored. */
addibf,< -16,count,chunks /* If count is still >= 16 do another loop. */
stwm tmp4,4(0,d_addr) /* tmp4 = 4th word stored. DELAY SLOT */
chekchunk:
addibt,<,n 12,count,back_porch /* since the count is already decremented by -16 we're testing */
/* to see if there are at least 4 bytes left ? */
subchunk:
ldws,ma 4(s_addr),tmp1 /* tmp1 = *s_addr++ */
addibf,< -4,count,subchunk /* count -= 4 */
stbys,b,m tmp1,4(d_addr) /* *d_addr++ = tmp1 */
back_porch:
addibt,=,n 4,count,done /* if count = 0 we're, of course, done ! */
ldws 0(s_addr),tmp1 /* load up the back_porch */
add d_addr,count,d_addr/* final store address is +1 too high ! */
bv 0(r2) /* return--were done. */
stbys,e tmp1,0(d_addr) /* kerplunk! whew ! */
/* Begin non_aligned code. (no refrence to politics) */
not_aligned:
sub,>= tmp2,tmp1,tmp3 /* compute the shift quantity again and skip the load if tmp2 > tmp1. */
ldwm 4(0,s_addr),tmp1 /* load up the first word from the source. tmp1 = *s_addr++ */
zdep tmp3,28,29,tmp4 /* compute the number of bits to shift based on the number of bytes above. */
mtctl tmp4,11 /* load the shift count into cr11 = shift count register. */
addibt,<,n -16,count,chkchnk2 /* first step in pre adjustment of count for looping. */
chunk2:
ldwm 16(0,s_addr),tmp2 /* get either first or second word . tmp2 = *s_addr++ */
ldw -12(s_addr),tmp3
ldw -8(s_addr),tmp4
ldw -4(s_addr),tmp5
vshd tmp1,tmp2,tmp6 /* position data ! */
stbys,b,m tmp6,4(0,d_addr) /* store ! */
vshd tmp2,tmp3,tmp6 /* position data ! */
stwm tmp6,4(0,d_addr) /* store ! */
vshd tmp3,tmp4,tmp6 /* position data ! */
stwm tmp6,4(0,d_addr) /* store ! */
vshd tmp4,tmp5,tmp6 /* position data ! */
stwm tmp6,4(0,d_addr) /* store the data ! */
addibf,< -16,count,chunk2 /* If count is still >= 16 do another loop. */
copy tmp5,tmp1
chkchnk2:
addibt,<,n 12,count,bp_0 /* if we don't have 4 bytes left then do the back porch (bp_0) */
subchnk2:
ldwm 4(0,s_addr),tmp2 /* get next word ! */
vshd tmp1,tmp2,tmp3 /* position data ! */
addibt,< -4,count,bp_1 /* decrement count and when count < 4 goto back_porch (bp_1) */
stbys,b,m tmp3,4(0,d_addr) /* store ! */
ldwm 4(0,s_addr),tmp1 /* get 4th word ! */
vshd tmp2,tmp1,tmp3 /* position data ! */
addib,>= -4,count,subchnk2 /* decrement count and when count <= 4 go to back porch (bp_2) */
stbys,b,m tmp3,4(0,d_addr) /* store the data ! */
bp_0: copy tmp1,tmp2 /* switch registers used in the shift process. */
bp_1: addibt,<=,n 4,count,done /* if count = -4 this implies that count = 0 -> done */
add d_addr,count,d_addr /* bump destination address to be +1 too high ! */
mfctl sar,tmp3 /* suppress final ldwm unless result used */
extru tmp3,28,2,tmp3 /* convert bitshift to byteshift */
sub,<= count,tmp3,r0 /* bytes unused if (count-byteshift <= 0*/
ldwm 4(0,s_addr),tmp1 /* get final word ! */
vshd tmp2,tmp1,tmp3 /* position data ! */
bv 0(r2) /* return */
stbys,e tmp3,0(0,d_addr) /* store the data ! */
/* here we do ye old byte-at-a-time moves. */
byteloop:
comb,>=,n 0,count,done
encore:
ldbs,ma 1(s_addr),tmp1
addibf,= -1,count,encore
stbs,ma tmp1,1(d_addr)
done:
EXIT(memcpy)
|
4ms/metamodule-plugin-sdk
| 8,424
|
plugin-libc/newlib/libc/machine/hppa/strncat.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/*HPUX_ID: @(#) $Revision$ */
/* strncat(s1,s2,n) : concatonate at most n characters from s2 onto s1 */
#include "DEFS.h"
#define d_addr r26
#define s_addr r25
#define count r24
#define tmp1 r19
#define tmp2 r20
#define tmp3 r21
#define tmp4 r22
#define tmp5 arg3
#define tmp6 r31
#define save r1
#define tmp7 ret1 /* source offset-- reset to orig source addr if not aligned */
ENTRY(strncat)
comb,= r0,s_addr,quit /* quit if s2=NULL */
copy d_addr,ret0 /* The return value is the value of d_addr. DELAY SLOT*/
/* First look for end of s1 (d_addr) */
extru d_addr,31,2,tmp1 /* Extract the low two bits of the dest address. */
combt,= tmp1,r0,dont_mask
dep 0,31,2,d_addr /*set word alignment */
ldwm 4(d_addr),tmp2
sh3add tmp1,r0,save /* build mask based on tmp1 */
mtctl save,11
zvdepi -2,32,save
or save,tmp2,tmp2
uxor,nbz tmp2,r0,save
search:
b,n found_end /* nullified under uxor conditions above and below */
dont_mask:
ldwm 4(d_addr),tmp2
comib,tr r0,r0,search
uxor,nbz tmp2,r0,save
found_end: /* at this point d_addr points to word */
extru,<> save,7,8,r0 /* following word with null */
addib,tr,n -4,d_addr,begin_copy /*set d_addr to end of s1 */
extru,<> save,15,8,r0
addib,tr,n -3,d_addr,begin_copy
extru,<> save,23,8,r0
addi -1,d_addr,d_addr
addi -1,d_addr,d_addr
begin_copy:
addibt,<,n -4,count,byteloop /* If count is <= 4 don't get fancy.*/
extru s_addr,31,2,tmp4 /* Extract the low two bits of the source address.*/
extru d_addr,31,2,tmp5 /* Extract the low two bits of the destination address.*/
add count,tmp5,count /* pre increment the count by the byte address so that the count is*/
copy s_addr,tmp6 /* save original s_addr in case we find null in first word */
copy s_addr, tmp7 /* save s_addr in case we find null before first store */
comb,<> tmp5,tmp4,not_aligned /* branch if tmp5<>tmp4. */
dep 0,31,2,s_addr /* Compute the word address of the source. DELAY SLOT.*/
/* aligned*/
combt,= tmp5,r0,skip_mask
ldwm 4(0,s_addr),tmp1 /* tmp1 = *s_addr s_addr += 4 (DELAY SLOT)*/
sh3add tmp5,r0,save /* compute mask in save*/
mtctl save,11
zvdepi -2,32,save
or save,tmp1,tmp1 /* or mask with data*/
uxor,nbz tmp1,r0,save /* check for null*/
b,n null1
addibt,< -4,count,back_porch
stbys,b,m tmp1,4(0,d_addr) /* store word (delay slot)*/
chunks:
ldwm 4(0,s_addr),tmp1 /* get a word*/
skip_mask:
uxor,nbz tmp1,r0,save /* check for null*/
b,n align_null1
addibf,< -4,count,chunks
stbys,b,m tmp1,4(0,d_addr) /* store word (delay slot)*/
back_porch: /* last word to store*/
addibt,=,n 4,count,done /* if count = 0 we're, of course, done !*/
ldws 0(s_addr),tmp1 /* load up the back_porch*/
sh3add count,r0, save /* setup right mask based on count*/
mtctl save,r11
zvdepi -2,32,save /*save now has left-hand mask*/
uaddcm r0,save,save /*form right hand mask */
or tmp1,save,tmp1 /*and insert data*/
uxor,nbz tmp1,r0,save /* check for null*/
b,n null2
add d_addr,count,d_addr/* final store address is +1 too high !*/
b done
stbys,e tmp1,0(d_addr) /* done */
/* Begin non_aligned code. */
not_aligned:
sub,>= tmp5,tmp4,tmp6 /* compute the shift amt.and skip load if tmp5 > tmp4.*/
ldwm 4(0,s_addr),tmp1 /* load up the first word from the source. tmp1 = *s_addr++*/
zdep tmp6,28,29,tmp4 /* compute the number of bits to shift */
mtctl tmp4,11 /* load the shift count into cr11 = shift count register.*/
addibt,<,n -4,count,chkchnk2 /* first step in pre adjustment of count for looping.*/
ldwm 4(0,s_addr),tmp2 /* get either first or second word from source. */
combt,= tmp5,r0,skip_mask4 /* don't mask if whole word is valid*/
vshd tmp1,tmp2,tmp3 /* position data ! (delay slot)*/
sh3add tmp5,r0,save /* setup r1*/
mtctl save,r11 /* setup mask in save*/
zvdepi -2,32,save
or save, tmp3, tmp3
mtctl tmp4,11 /* re-load the shift count into cr11 */
skip_mask4:
uxor,nbz tmp3, r0, save
b,n null4 /* special case for first word */
copy r0, tmp5 /* zero out tmp5 so we don't try to mask again*/
copy r0, tmp7 /* zero out tmp7 so we don't try to use original s_addr anymore */
b continue
stbys,b,m tmp3,4(0,d_addr) /* store ! */
chunk2:
ldwm 4(0,s_addr),tmp2
vshd tmp1,tmp2,tmp3
skip_mask2:
uxor,nbz tmp3, r0, save
b,n null3
stbys,b,m tmp3,4(0,d_addr) /* store ! */
continue:
ldwm 4(0,s_addr),tmp1 /* get 2nd word ! */
vshd tmp2,tmp1,tmp3 /* position data ! */
uxor,nbz tmp3, r0, save
b,n null3
addibf,< -8,count,chunk2 /* If count is still >= 8 do another loop.*/
stbys,b,m tmp3,4(0,d_addr) /* store !*/
chkchnk2:
addibt,<,n 4,count,bp_0 /* if we don't have 4 bytes left then do the back porch (bp_0)*/
subchnk2: /* we have less than 8 chars to copy*/
ldwm 4(0,s_addr),tmp2 /* get next word !*/
combt,= tmp5,r0,skip_mask3
vshd tmp1,tmp2,tmp3 /* position data !*/
sh3add tmp5,r0,save /* setup r1*/
mtctl save,r11 /* setup mask in save*/
zvdepi -2,32,save
or save, tmp3, tmp3
mtctl tmp4,11 /* restore shift value again */
skip_mask3:
uxor,nbz tmp3,r0,save
b,n null3
copy r0,tmp5 /* zero out tmp5 so null3 does correct alignment */
copy r0,tmp7 /* zero out tmp7 so we don't use orignal s_addr since no longer valid */
b bp_1 /* we now have less than 4 bytes to move*/
stbys,b,m tmp3,4(0,d_addr) /* store !*/
bp_0:
copy tmp1,tmp2 /* switch registers for shift process */
addibt,<=,n 4,count,done /* if count = -4 this implies that count = 0 -> done */
bp_1:
ldwm 4(0,s_addr),tmp1 /* get final word ! */
vshd tmp2,tmp1,tmp3 /* position data !*/
uxor,nbz tmp3,r0,save /* if no-byte-zero */
b,n bp_null /* don't goto no_null-find which null instead */
no_null:
add d_addr,count,d_addr /* set up d_addr for stbys,e */
b done /* were done*/
stbys,e tmp3,0(0,d_addr) /* store the data !*/
/* here we do ye old byte-at-a-time moves.*/
align_null1:
b byteloop
addi -4,s_addr,s_addr
null1:
copy tmp6,s_addr /* restore orig s_addr (aligned only) */
byteloop:
addibt,= 4,count,done
null2:
ldbs,ma 1(s_addr),tmp1
encore:
combt,=,n tmp1,r0, done
stbs,ma tmp1,1(d_addr)
addibf,=,n -1,count,encore
ldbs,ma 1(s_addr),tmp1
b,n done
bp_null:
addi -4,count,count /* fudge count 'cause byteloop will re-increment */
null3: /* not_aligned case reset s_addr and finish byte-wise */
combt,=,n r0,tmp7,null3a /* if tmp7 is not valid address then branch below */
b byteloop /* otherwise reset s_addr to tmp7 and finish */
copy tmp7, s_addr
null3a: /* right shift target */
addibt,<,n 0,tmp6,null3b /* if left shifting */
sub r0,tmp6,tmp6 /* do null3b code */
addi -4,tmp6,tmp6
b byteloop
add tmp6,s_addr,s_addr /* reset s_addr by 4 + shift_amt */
null3b:
subi -8,tmp6,tmp6
add tmp5,tmp6,tmp6 /* adjust by the dest offset if this is our first store */
b byteloop
add tmp6,s_addr,s_addr /* adjust s_addr by (8-shift_amt-dest_off) */
null4:
add,> tmp6,r0,tmp6 /* if left shift */
b,n null3 /* then do null3 */
b byteloop
addi -4,s_addr,s_addr /* adj source only by 4 */
done:
bv 0(r2)
stbs r0,0(d_addr)
quit:
EXIT(strncat)
|
4ms/metamodule-plugin-sdk
| 4,191
|
plugin-libc/newlib/libc/machine/hppa/setjmp.S
|
/* Copyright (c) 1995, 2002 Red Hat Incorporated.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* The name of Red Hat Incorporated may not be used to endorse
* or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Note I don't know an easy way to get the FP version into the
traditional C library and the non-FP version into the soft-float
library. Maybe we'll have to have -msoft-float trigger something
like -DSOFT_FLOAT if this issue ever arises. */
#include "DEFS.h"
#if 0
.SPACE $PRIVATE$
.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
.SPACE $TEXT$
.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY
.IMPORT $global$,DATA
.IMPORT $$dyncall,MILLICODE
; gcc_compiled.:
#endif
TEXT_SEGMENT
.align 4
.EXPORT setjmp,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
setjmp
.PROC
.CALLINFO FRAME=64,NO_CALLS,SAVE_SP,ENTRY_GR=3
.ENTRY
stwm %r30,4(%r26)
stwm %r2,4(%r26)
stwm %r3,4(%r26)
stwm %r4,4(%r26)
stwm %r5,4(%r26)
stwm %r6,4(%r26)
stwm %r7,4(%r26)
stwm %r8,4(%r26)
stwm %r9,4(%r26)
stwm %r10,4(%r26)
stwm %r11,4(%r26)
stwm %r12,4(%r26)
stwm %r13,4(%r26)
stwm %r14,4(%r26)
stwm %r15,4(%r26)
stwm %r16,4(%r26)
stwm %r17,4(%r26)
stwm %r18,4(%r26)
stwm %r27,4(%r26)
#ifdef FP
; jmp_buf may only have a 4 byte alignment, so handle FP stores
; very carefully.
fstds %fr12,-16(%r30)
ldw -16(%r30),%r28
stwm %r28,4(%r26)
ldw -12(%r30),%r28
stwm %r28,4(%r26)
fstds %fr13,-16(%r30)
ldw -16(%r30),%r28
stwm %r28,4(%r26)
ldw -12(%r30),%r28
stwm %r28,4(%r26)
fstds %fr14,-16(%r30)
ldw -16(%r30),%r28
stwm %r28,4(%r26)
ldw -12(%r30),%r28
stwm %r28,4(%r26)
fstds %fr15,-16(%r30)
ldw -16(%r30),%r28
stwm %r28,4(%r26)
ldw -12(%r30),%r28
stwm %r28,4(%r26)
#endif
bv 0(%r2)
copy %r0,%r28
.EXIT
.PROCEND
.align 4
.EXPORT longjmp,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
longjmp
.PROC
.CALLINFO FRAME=64,NO_CALLS,SAVE_SP,ENTRY_GR=3
.ENTRY
ldwm 4(%r26),%r30
ldwm 4(%r26),%r2
ldwm 4(%r26),%r3
ldwm 4(%r26),%r4
ldwm 4(%r26),%r5
ldwm 4(%r26),%r6
ldwm 4(%r26),%r7
ldwm 4(%r26),%r8
ldwm 4(%r26),%r9
ldwm 4(%r26),%r10
ldwm 4(%r26),%r11
ldwm 4(%r26),%r12
ldwm 4(%r26),%r13
ldwm 4(%r26),%r14
ldwm 4(%r26),%r15
ldwm 4(%r26),%r16
ldwm 4(%r26),%r17
ldwm 4(%r26),%r18
ldwm 4(%r26),%r27
#ifdef FP
ldwm 4(%r26),%r28
stw %r28,-16(%r30)
ldwm 4(%r26),%r28
stw %r28,-12(%r30)
fldds -16(%r30),%fr12
ldwm 4(%r26),%r28
stw %r28,-16(%r30)
ldwm 4(%r26),%r28
stw %r28,-12(%r30)
fldds -16(%r30),%fr13
ldwm 4(%r26),%r28
stw %r28,-16(%r30)
ldwm 4(%r26),%r28
stw %r28,-12(%r30)
fldds -16(%r30),%fr14
ldwm 4(%r26),%r28
stw %r28,-16(%r30)
ldwm 4(%r26),%r28
stw %r28,-12(%r30)
fldds -16(%r30),%fr15
#endif
comclr,<> %r0,%r25,%r0
ldi 1,%r25
bv 0(%r2)
copy %r25,%r28
.EXIT
.PROCEND
|
4ms/metamodule-plugin-sdk
| 10,201
|
plugin-libc/newlib/libc/machine/hppa/strcpy.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/*
A faster strcpy.
by
Jerry Huck (aligned case)
Daryl Odnert (equal-alignment case)
Edgar Circenis (non-aligned case)
*/
/*
* strcpy(s1, s2)
*
* Copy string s2 to s1. s1 must be large enough.
* return s1
*/
#include "DEFS.h"
#define d_addr r26
#define s_addr r25
#define tmp6 r24
#define tmp1 r19
#define evenside r19
#define tmp2 r20
#define oddside r20
#define tmp3 r21
#define tmp4 r22
#define tmp5 arg3
#define save r1
ENTRY(strcpy)
/* Do some quick alignment checking on and fast path both word aligned */
extru,<> s_addr,31,2,tmp6 /*Is source word aligned? */
ldwm 4(0,s_addr),oddside /*Assume yes and guess that it
is double-word aligned. */
dep,= d_addr,29,2,tmp6 /*Is target word aligned? */
b case_analysis
copy d_addr,ret0
/* Both are aligned. First source word already loaded assuming that
source was oddword aligned. Fall through (therefore fastest) code
shuffles the registers to join the main loop */
bothaligned:
bb,>= s_addr,29,twoatatime /*Branch if source was odd aligned*/
uxor,nbz oddside,r0,save
/* Even aligned source. save holds that operand.
Do one iteration of the main copy loop juggling the registers to avoid
one copy. */
b,n nullfound
ldwm 4(s_addr),oddside
stwm save,4(d_addr)
uxor,nbz oddside,r0,save
b,n nullfound
ldwm 4(s_addr),evenside
stwm oddside,4(d_addr)
uxor,nbz evenside,r0,save
b,n nullfound
ldwm 4(s_addr),oddside
/* Main loop body. Entry expects evenside still to be stored, oddside
just loaded. */
loop:
stwm evenside,4(d_addr)
uxor,nbz oddside,r0,save
/* mid loop entry */
twoatatime:
b,n nullfound
ldwm 4(s_addr),evenside
stwm oddside,4(d_addr)
uxor,sbz evenside,r0,save
b loop
ldwm 4(s_addr),oddside
/* fall through when null found in evenside. oddside actually loaded */
nullfound: /* adjust d_addr and store final word */
extru,<> save,7,8,r0 /* pick up leftmost byte */
addib,tr,n 1,d_addr,store_final
extru,<> save,15,8,r0
addib,tr,n 2,d_addr,store_final
extru,<> save,23,8,r0
addib,tr 3,d_addr,store_final2
bv 0(rp)
stw save,0(d_addr)
store_final:
bv 0(rp)
store_final2:
stbys,e save,0(d_addr) /* delay slot */
case_analysis:
blr tmp6,r0
nop
/* NOTE: the delay slots for the non-aligned cases load a */
/* shift quantity which is TGT-SRC into tmp3. */
/* Note also, the case for both strings being word aligned */
/* is already checked before the BLR is executed, so that */
/* case can never occur. */
/* TGT SRC */
nop /* 00 00 can't happen */
nop
b neg_aligned_copy /* 00 01 */
ldi -1,tmp3 /* load shift quantity. delay slot */
b neg_aligned_copy /* 00 10 */
ldi -2,tmp3 /* load shift quantity. delay slot */
b neg_aligned_copy /* 00 11 */
ldi -3,tmp3 /* load shift quantity. delay slot */
b pos_aligned_copy0 /* 01 00 */
ldi 1,tmp3 /* load shift quantity. delay slot */
b equal_alignment_1 /* 01 01 */
ldbs,ma 1(s_addr),tmp1
b neg_aligned_copy /* 01 10 */
ldi -1,tmp3 /* load shift quantity. delay slot */
b neg_aligned_copy /* 01 11 */
ldi -2,tmp3 /* load shift quantity. delay slot */
b pos_aligned_copy0 /* 10 00 */
ldi 2,tmp3 /* load shift quantity. delay slot */
b pos_aligned_copy /* 10 01 */
ldi 1,tmp3 /* load shift quantity. delay slot */
b equal_alignment_2 /* 10 10 */
ldhs,ma 2(s_addr),tmp1
b neg_aligned_copy /* 10 11 */
ldi -1,tmp3 /* load shift quantity. delay slot */
b pos_aligned_copy0 /* 11 00 */
ldi 3,tmp3 /* load shift quantity. delay slot */
b pos_aligned_copy /* 11 01 */
ldi 2,tmp3 /* load shift quantity. delay slot */
b pos_aligned_copy /* 11 10 */
ldi 1,tmp3 /* load shift quantity. delay slot */
ldbs,ma 1(s_addr),tmp1 /* 11 11 */
comiclr,<> r0,tmp1,r0
bv 0(rp) /* return if 1st byte was null */
stbs,ma tmp1,1(d_addr) /* store a byte to dst string */
b bothaligned /* can now goto word_aligned */
ldwm 4(s_addr),oddside /* load next word of source */
equal_alignment_1:
comiclr,<> r0,tmp1,r0 /* nullify next if tmp1 <> 0 */
bv 0(rp) /* return if null byte found */
stbs,ma tmp1,1(d_addr) /* store a byte to dst string */
ldhs,ma 2(s_addr),tmp1 /* load next halfword */
equal_alignment_2:
extru,<> tmp1,23,8,tmp6 /* look at left byte of halfword */
bv 0(rp) /* return if 1st byte was null */
stbs,ma tmp6,1(d_addr)
extru,<> tmp1,31,8,r0
bv 0(rp) /* return if 2nd byte was null */
stbs,ma tmp1,1(d_addr)
b bothaligned
ldwm 4(s_addr),oddside /* load next word */
/* source and destination are not aligned, so we do it the hard way. */
/* target alignment is greater than source alignment */
pos_aligned_copy0:
addi -4,s_addr,s_addr
pos_aligned_copy:
extru d_addr,31,2,tmp6 /* Extract low 2 bits of the dest addr */
extru s_addr,31,2,tmp1 /* Extract low 2 bits of the src addr */
dep r0,31,2,s_addr /* Compute word address of the source. */
sh3add tmp3,r0,tmp4 /* compute shift amt */
ldwm 4(0,s_addr),tmp2 /* get 1st source word */
sh3add tmp1,r0,save /* setup mask shift amount */
mtctl save,r11 /* set-up cr11 for mask */
zvdepi -2,32,save /* create mask */
or save,tmp2,tmp2 /* mask unused bytes in src */
ldi -1,tmp1 /* load tmp1 with 0xffffffff */
mtctl tmp4,r11 /* shift count -> shift count reg */
vshd tmp1,tmp2,tmp3 /* position data ! */
uxor,nbz tmp3,r0,save
b,n first_null
uxor,nbz tmp2,r0,save
b nullfound1
mtctl tmp4,r11 /* re-load shift cnt (delay slot) */
b loop_entry
ldwm 4(0,s_addr),tmp1 /* get next word. delay slot */
neg_aligned_copy:
extru d_addr,31,2,tmp6 /* Extract low 2 bits of the dest addr */
extru s_addr,31,2,tmp2 /* Extract low 2 bits of the src addr */
dep r0,31,2,s_addr /* Compute word address of the source. */
sh3add tmp3,r0,tmp4 /* compute shift amt */
ldwm 4(0,s_addr),tmp1 /* load first word from source. */
/* check to see if next word can be read safely */
sh3add tmp2,r0,save
mtctl save,r11 /* shift count -> shift count reg */
zvdepi -2,32,save
or save, tmp1, tmp1
uxor,nbz tmp1,r0,save /* any nulls in first word? */
b first_null0
mtctl tmp4,r11
ldwm 4(0,s_addr),tmp2 /* load second word from source */
combt,= tmp6,r0,chunk1 /* don't mask if whole word valid */
vshd tmp1,tmp2,tmp3 /* position data ! */
sh3add tmp6,r0,save /* setup r1 */
mtctl save,r11 /* set-up cr11 for mask */
zvdepi -2,32,save
or save, tmp3, tmp3
uxor,nbz tmp3,r0,save
b,n first_null
uxor,nbz tmp2,r0,save
b nullfound1
mtctl tmp4,r11 /* re-load shift cnt (delay slot) */
b loop_entry
ldwm 4(0,s_addr),tmp1 /* get next word. delay slot */
chunk1:
uxor,nbz tmp2,r0,save
b nullfound0
vshd tmp1,tmp2,tmp3
did_mask:
ldwm 4(0,s_addr),tmp1 /* get next word ! */
loop_entry:
stbys,b,m tmp3,4(0,d_addr) /* store ! */
uxor,nbz tmp1, r0, save
b nullfound2
vshd tmp2,tmp1,tmp3 /* position data ! */
ldwm 4(s_addr),tmp2
stwm tmp3,4(d_addr)
uxor,sbz tmp2,r0,save
b did_mask
nullfound0:
vshd tmp1,tmp2,tmp3 /* delay slot */
uxor,nbz tmp3,r0,save
b,n nullfound
nullfound1:
stbys,b,m tmp3,4(0,d_addr)
b nullfound
vshd tmp2,r0,save /* delay slot */
nullfound2:
uxor,nbz tmp3,r0,save
b,n nullfound
stwm tmp3,4(d_addr)
b nullfound
/* notice that delay slot is in next routine */
first_null0: /* null found in first word of non-aligned (wrt d_addr) */
vshd tmp1,r0,save /* delay slot */
combt,= tmp6,r0,check4
extru save,7,8,tmp4
first_null:
addibt,= -1,tmp6,check3 /* check last 3 bytes of word */
extru save,15,8,tmp4
addibt,=,n -1,tmp6,check2 /* check last 2 bytes */
bv 0(rp) /* null in last byte--store and exit */
stbys,b save, 0(d_addr)
check4:
combt,= tmp4,r0,done
stbs,ma tmp4,1(d_addr)
extru,<> save,15,8,tmp4
check3:
combt,= tmp4,r0,done
stbs,ma tmp4,1(d_addr)
check2:
extru,<> save,23,8,tmp4
bv 0(rp)
stbs,ma tmp4,1(d_addr)
bv 0(rp)
stbs r0,0(d_addr)
done:
EXIT(strcpy)
|
4ms/metamodule-plugin-sdk
| 7,404
|
plugin-libc/newlib/libc/machine/hppa/strncmp.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/* strcmp(s1, s2) */
/* returns integer: < 0 iff s1 lexicographically less than s2 */
/* > 0 iff s1 lexicographically greater than s2 */
/* = 0 iff s1 lexicographically equal to s2 */
/* = 0 iff s1 lexicographically equal to s2 */
/* quit after n charachters */
#include "DEFS.h"
#define s1 26
#define s2 25
#define tmp1 19
#define s2word 20
#define tmp3 21
#define tmp7 22
#define s1word 29
#define save 1
#define tmp6 23
#define tmp5 28
#define count 24
ENTRY(strncmp)
combt,<,n r0,count,search /* N <= 0 yields equality */
bv r0(rp) /* */
copy 0,ret0 /* return 0 (DELAY SLOT) */
search: combf,=,n s1,s2,findout /* s1 != s2? */
bv r0(rp) /* */
copy 0,ret0 /* return 0 (delay slot) */
findout:
comibf,=,n 0,s1,checks1 /* s1 == NULL? */
ldbs 0(0,s2),ret0 /* */
bv r0(rp) /* */
subi 0,ret0,ret0 /* ret0 <- -*s2 */
checks1:
comibf,=,n 0,s2,checkitout /* s2 == NULL? */
bv r0(rp) /* */
ldbs 0(0,s1),28 /* return *s1 */
checkitout:
extru s2,31,2,tmp1 /* Extract the low two bits of the s2. */
extru s1,31,2,tmp5 /* Extract the low two bits of the s1 */
sub,= tmp5,tmp1,tmp3 /* Are s1 & s2 aligned with each other? */
b not_aligned /* It's more complicated (not_aligned) */
dep 0,31,2,s1 /* Compute word address of s1 (DELAY SLOT) */
dep 0,31,2,s2 /* Compute word address of s2 */
ldwm 4(0,s1),s1word /* get next s1 word s1+=4 */
combt,= tmp5,r0,skipmask /* skip masking, if we can */
ldwm 4(0,s2),s2word /* get next s2 word s2+=4 (DELAY SLOT) */
add tmp5,count,count /* bump count by the number of bytes */
/* we are going to mask */
sh3add tmp5,r0,save /* save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /* load save with proper mask */
or save,s1word,s1word /* mask s1word (s1) */
or save,s2word,s2word /* mask s2word (s2) */
skipmask:
combt,=,n s1word,s2word,chknulls /* are these words equal? */
checkbyte:
extru s1word,7,8,tmp3 /* get first byte (character) */
ckbyte2: extru s2word,7,8,tmp7 /* get first byte (character) */
combf,= tmp3,tmp7,done /* quit if first byte is not equal */
sub tmp3,tmp7,ret0 /* return difference (delay slot) */
comibt,=,n 0,tmp3,done /* have we reached the end of string */
/* if so done ret0 already has zero */
addibt,<=,n -1,count,done /* have we checked N chars? ret0 == 0 */
extru s1word,15,8,tmp3 /* get second byte (character) */
extru s2word,15,8,tmp7 /* get second byte (character) */
combf,= tmp3,tmp7,done /* quit if second byte is not equal */
sub tmp3,tmp7,ret0 /* return difference (delay slot) */
comibt,=,n 0,tmp3,done /* have we reached the end of string */
/* if so done ret0 already has zero */
addibt,<=,n -1,count,done /* have we checked N chars? */
extru s1word,23,8,tmp3 /* get third byte (character) */
extru s2word,23,8,tmp7 /* get third byte (character) */
combf,= tmp3,tmp7,done /* done if third byte is not equal */
sub tmp3,tmp7,ret0 /* return difference (delay slot) */
comibt,=,n 0,tmp3,done /* have we reached the end of string */
/* if so done ret0 already has zero */
addibt,<=,n -1,count,done /* have we checked N chars? */
extru s1word,31,8,tmp3 /* get last byte (character) */
extru s2word,31,8,tmp7 /* get last byte (character) */
bv r0(rp) /* */
sub tmp3,tmp7,ret0 /* the last characters in the word is */
/* where the difference is, so return */
/* the difference and we're outta here */
chknulls:
addibt,<=,n -4,count,zero /* have we checked N chars? */
uxor,nbz s1word,0,0 /* don't have to check s2 Just quit */
bv r0(rp) /* */
copy 0,28 /* return 0 */
ldwm 4(0,s2),s2word /* get next s2 word s2+=4 */
b skipmask /* keep checking */
ldwm 4(0,s1),s1word /* get next s1 word s1+=4 */
not_aligned:
dep r0,31,2,s2 /* Compute word address of s2 */
combt,<,n r0,tmp3,shifts1 /* Do we shift s1 or s2 */
sh3add tmp3,r0,tmp3 /* eight bits per byte so mul by 8 */
ldwm 4(0,s1),s1word /* get first word of s1 */
ldwm 4(0,s2),s2word /* get first word or s2 */
combt,=,n r0,tmp5,masks2 /* Do we need to mask beginning of s1 */
add tmp5,count,count /* bump count by the number of bytes */
/* we are going to mask */
sh3add tmp5,r0,save /* save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /* load save with proper mask */
or save,s1word,s1word /* */
masks2: sh3add tmp1,r0,save /* save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /* load save with proper mask */
or save,s2word,s2word /* */
mtctl tmp3,11 /* Move shift amount to CR11 */
more: uxor,nbz s2word,r0,r0 /* Is there a null in first word */
b,n chunk1 /* */
ldwm 4(0,s2),tmp7 /* load second word to enable us to shift */
vshd s2word,tmp7,s2word /* */
combf,=,n s1word,s2word,ckbyte2 /* */
extru s1word,7,8,tmp3 /* get first byte (DELAY SLOT) */
addibt,<=,n -4,count,zero /* have we checked N chars? */
uxor,nbz s1word,0,0 /* even though they're equal we could be done */
b,n zero
copy tmp7,s2word /* */
b more /* keep checking */
ldwm 4(0,s1),s1word /* get next s1 (DELAY SLOT) */
chunk1:
vshd s2word,r0,s2word /* */
b ckbyte2 /* */
extru s1word,7,8,tmp3 /* */
shifts1:
sh3add tmp3,r0,tmp3 /* eight bits per byte so mul by 4 */
sub r0,tmp3,tmp3 /* Get negative value for left shift */
ldwm 4(0,s2),s2word /* get first word of s2 */
ldwm 4(0,s1),s1word /* get first word or s1 */
combt,=,n r0,tmp1,masks1 /* Do we need to mask beginning of s2 */
add tmp1,count,count /* bump count by the number of bytes */
/* we are going to mask */
sh3add tmp1,r0,save /* save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /* load save with proper mask */
or save,s2word,s2word /* */
masks1: sh3add tmp5,r0,save /* save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /* load save with proper mask */
or save,s1word,s1word /* */
mtctl tmp3,11 /* Move shift amount to CR11 */
more1: uxor,nbz s1word,r0,r0 /* Is there a null in first byte */
b,n chunk2 /* */
ldwm 4(0,s1),tmp7 /* load second word to enable us to shift */
vshd s1word,tmp7,s1word /* */
combf,=,n s2word,s1word,ckbyte2 /* */
extru s1word,7,8,tmp3 /* get first byte (DELAY SLOT) */
addibt,<=,n -4,count,zero /* have we checked N chars? */
uxor,nbz s2word,0,0 /* even though they're equal we could be done */
b,n zero /* zero ret0 and quit */
copy tmp7,s1word /* */
b more1 /* keep checking */
ldwm 4(0,s2),s2word /* get next s2 (DELAY SLOT) */
chunk2:
vshd s1word,r0,s1word /* */
b ckbyte2 /* */
extru s1word,7,8,tmp3 /* */
zero: copy r0,ret0
done:
EXIT(strncmp)
|
4ms/metamodule-plugin-sdk
| 2,480
|
plugin-libc/newlib/libc/machine/hppa/memset.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/* SPECTRUM_ID: @(#)memset.s 37.4 86/08/25 */
/*
* memset(s, c, n)
*
* Sets first n chars in memory area s to value of character c.
* Returns s.
*/
#ifndef _NAMESPACE_CLEAN
#define NOSECDEF /* prevent _memset from being defined as entry */
#endif
#include "DEFS.h"
#define TO arg0
#define FILLCHAR arg1
#define COUNT arg2
#define TMP r31
ENTRY(memset)
comb,<= COUNT,r0,msexit /* return if count not positive */
copy TO,ret0 /* return value is start of copy */
comibf,<,n 5,COUNT,msbyteloop /* be straightforward */
dep FILLCHAR,23,8,FILLCHAR /* dup low byte */
dep FILLCHAR,15,16,FILLCHAR /* into high bytes */
add TO,COUNT,TMP /* TMP points just past fill area */
stbys,m FILLCHAR,0(TO) /* fill out first word */
/*
* If we're pointing to high-order byte, no fill will happen,
* but permissions will be checked. We don't want this (we
* might be pointing at the beginning of a protected region),
* so we branch around stbys if neither low bits are set.
*/
bb,<,n TMP,31,filend /* if low bit is set, stbys */
bb,>=,n TMP,30,endfil /* if next lowest bit isn't set */
/* (and lowest isn't, either) */
/* do not stbys */
filend:
stbys,m,e FILLCHAR,0(TMP) /* fill out the last */
endfil:
addi 4, TO, TO
sub TMP,TO,COUNT /* will now divide by 4 */
comb,=,n COUNT,r0,msexit /* If count is zero ret. */
extru,<> COUNT,31,4,r1
b msquadloop
depi 0,31,4,COUNT /* will now divide by 16 */
mswordloop:
addib,<> -4,r1,mswordloop
stws,ma FILLCHAR,4(TO)
comb,=,n COUNT,r0,msexit /* If count is zero ret. */
msquadloop:
stws,ma FILLCHAR,4(TO)
stws,ma FILLCHAR,4(TO)
stws,ma FILLCHAR,4(TO)
addib,<> -16,COUNT,msquadloop
stws,ma FILLCHAR,4(TO)
b,n msexit
msbyteloop:
addib,<> -1,COUNT,msbyteloop
stbs,ma FILLCHAR,1(TO)
msexit:
EXIT(memset)
|
4ms/metamodule-plugin-sdk
| 1,332
|
plugin-libc/newlib/libc/machine/hppa/memchr.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/* SPECTRUM_ID: @(#)memchr.s 37.4 86/04/23 */
/*
* memchr(s, c, n)
*
* returns pointer to first occurrence of char c
* in first n characters of memory area s,
* or null if c does not occur.
*/
#include "DEFS.h"
#define FROM arg0
#define CHAR arg1
#define COUNT arg2
#define TEMP1 r19
ENTRY(memchr)
comb,<= COUNT,r0,memchrexit /* return if count is zero */
copy r0,ret0 /* null if c not found in n chars */
depi 0,23,24,CHAR /* make char unsigned */
ldbs,ma 1(FROM),TEMP1
memchrloop:
comb,=,n TEMP1,CHAR,memchrequal
addib,<> -1,COUNT,memchrloop
ldbs,ma 1(FROM),TEMP1
b,n memchrexit
memchrequal:
ldo -1(FROM),ret0
memchrexit:
EXIT(memchr)
|
4ms/metamodule-plugin-sdk
| 7,108
|
plugin-libc/newlib/libc/machine/hppa/memcmp.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/* memcmp(s1, s2, n) */
/* returns integer: < 0 iff s1 lexicographically less than s2 */
/* > 0 iff s1 lexicographically greater than s2 */
/* = 0 iff s1 lexicographically equal to s2 */
/* = 0 iff s1 lexicographically equal to s2 */
/* quit after n charachters */
#ifndef _NAMESPACE_CLEAN
#define NOSECDEF /* prevents _memcmp from becoming primary entry */
#endif
#include "DEFS.h"
#define s1 26
#define s2 25
#define tmp1 19
#define s2word 20
#define tmp3 21
#define tmp7 22
#define s1word 29
#define save 1
#define tmp6 23
#define tmp5 28
#define count 24
ENTRY(memcmp)
combt,<,n r0,count,search /*N <= 0 yields equality */
b done /**/
copy 0,ret0 /*return 0 (DELAY SLOT) */
search: combf,=,n s1,s2,findout /*s1 != s2? */
b done
copy 0,ret0 /*return 0 (delay slot) */
findout:
comibf,=,n 0,s1,checks1 /*s1 == NULL? */
ldbs 0(0,s2),ret0 /**/
b done /*quit */
sub 0,ret0,ret0 /*ret0 <- -*s2 */
checks1:
comibf,=,n 0,s2,checkitout /*s2 == NULL? */
b done /* quit */
ldbs 0(0,s1),28 /* return *s1 */
checkitout:
extru s2,31,2,tmp1 /* Extract the low two bits of the s2. */
extru s1,31,2,tmp5 /* Extract the low two bits of the s1 */
sub,= tmp5,tmp1,tmp3 /* Are s1 & s2 aligned with each other? */
b not_aligned /* It's more complicated (not_aligned) */
dep 0,31,2,s1 /* Compute word address of s1 (DELAY SLOT) */
dep 0,31,2,s2 /* Compute word address of s2 */
ldwm 4(0,s1),s1word /* get next s1 word s1+=4 */
combt,= tmp5,r0,skipmask /* skip masking, if we can */
ldwm 4(0,s2),s2word /* get next s2 word s2+=4 (DELAY SLOT) */
add tmp5,count,count /* bump count by the number of bytes */
/* we are going to mask */
sh3add tmp5,r0,save /* save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /* load save with proper mask */
or save,s1word,s1word /* mask s1word (s1) */
or save,s2word,s2word /* mask s2word (s2) */
skipmask:
combt,=,n s1word,s2word,checkN /* We may be done */
checkbyte:
extru s1word,7,8,tmp3 /* get first byte (character) */
ckbyte2: extru s2word,7,8,tmp7 /* get first byte (character) */
combf,= tmp3,tmp7,done /* quit if first byte is not equal */
sub tmp3,tmp7,ret0 /* return difference (delay slot) */
addibt,<=,n -1,count,done /* have we checked N chars? ret0 == 0 */
extru s1word,15,8,tmp3 /* get second byte (character) */
extru s2word,15,8,tmp7 /* get second byte (character) */
combf,= tmp3,tmp7,done /* quit if second byte is not equal */
sub tmp3,tmp7,ret0 /* return difference (delay slot) */
addibt,<=,n -1,count,done /* have we checked N chars? */
extru s1word,23,8,tmp3 /* get third byte (character) */
extru s2word,23,8,tmp7 /* get third byte (character) */
combf,= tmp3,tmp7,done /* done if third byte is not equal */
sub tmp3,tmp7,ret0 /* return difference (delay slot) */
addibt,<=,n -1,count,done /* have we checked N chars? */
extru s1word,31,8,tmp3 /* get last byte (character) */
extru s2word,31,8,tmp7 /* get last byte (character) */
b done /* if we reach this point we know that */
sub tmp3,tmp7,ret0 /* the last character in the word is */
/* where the difference is, so return */
/* the difference and we're outta here */
checkN:
addibt,<=,n -4,count,zero /* have we checked N chars? */
ldwm 4(0,s2),s2word /* get next s2 word s2+=4 */
b skipmask /* keep checking */
ldwm 4(0,s1),s1word /* get next s1 word s1+=4 */
not_aligned:
dep r0,31,2,s2 /* Compute word address of s2 */
combt,<,n r0,tmp3,shifts1 /* Do we shift s1 or s2 */
sh3add tmp3,r0,tmp3 /* eight bits per byte so mul by 8 */
ldwm 4(0,s1),s1word /* get first word of s1 */
ldwm 4(0,s2),s2word /* get first word or s2 */
combt,=,n r0,tmp5,masks2 /* Do we need to mask beginning of s1 */
add tmp5,count,count /* bump count by the number of bytes */
/* we are going to mask */
sh3add tmp5,r0,save /* save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /* load save with proper mask */
or save,s1word,s1word /**/
masks2: sh3add tmp1,r0,save /* save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /* load save with proper mask */
or save,s2word,s2word /**/
subi 4,tmp1,tmp1 /* tmp1 now has the number of byte that */
/* are valid in s2word before the vshd */
mtctl tmp3,11 /* Move shift amount to CR11 */
more: combt,<=,n count,tmp1,chunk1 /* Can we do the vshd? */
ldwm 4(0,s2),tmp7 /* load second word to enable us to shift */
vshd s2word,tmp7,s2word /**/
combf,=,n s1word,s2word,ckbyte2 /**/
extru s1word,7,8,tmp3 /* get first byte (DELAY SLOT) */
addibt,<=,n -4,count,zero /* have we checked N chars? */
copy tmp7,s2word /**/
b more /* keep checking */
ldwm 4(0,s1),s1word /* get next s1 (DELAY SLOT) */
chunk1:
vshd s2word,r0,s2word /* do an arithmetic shift left to position data */
b ckbyte2 /**/
extru s1word,7,8,tmp3 /**/
shifts1:
sh3add tmp3,r0,tmp3 /* eight bits per byte so mul by 8 */
sub r0,tmp3,tmp3 /* Get negative value for left shift */
dep r0,31,2,s2 /* Compute word address of s2 */
ldwm 4(0,s2),s2word /* get first word of s2 */
ldwm 4(0,s1),s1word /* get first word or s1 */
combt,=,n r0,tmp1,masks1 /*Do we need to mask beginning of s2 */
add tmp1,count,count /*bump count by the number of bytes */
/* we are going to mask */
sh3add tmp1,r0,save /*save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /*load save with proper mask */
or save,s2word,s2word /**/
masks1: sh3add tmp5,r0,save /*save now has number of bits to mask */
mtctl save,11
zvdepi -2,32,save /*load save with proper mask */
or save,s1word,s1word /**/
subi 4,tmp5,tmp5 /*tmp5 now has the number of byte that */
/*are valid in s1word before the vshd */
mtctl tmp3,11 /*Move shift amount to CR11 */
more1: combt,<=,n count,tmp5,chunk2 /*Can we do the vshd? */
ldwm 4(0,s1),tmp7 /*load second word to enable us to shift */
vshd s1word,tmp7,s1word /**/
combf,=,n s2word,s1word,ckbyte2 /**/
extru s1word,7,8,tmp3 /*get first byte (DELAY SLOT) */
addibt,<=,n -4,count,zero /*have we checked N chars? */
copy tmp7,s1word /**/
b more1 /*keep checking */
ldwm 4(0,s2),s2word /*get next s2 (DELAY SLOT) */
chunk2:
vshd s1word,r0,s1word /**/
b ckbyte2 /**/
extru s1word,7,8,tmp3 /**/
zero: copy r0,ret0
done:
EXIT(memcmp)
|
4ms/metamodule-plugin-sdk
| 3,370
|
plugin-libc/newlib/libc/machine/hppa/strlen.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/* HPUX_ID = "@(#) $Revision$" */
/* strlen(s): Return length of string s */
#define start arg0
#define end ret0
#define tmp1 arg1
#define tmp2 arg2
#include "DEFS.h"
ENTRY(strlen)
movb,=,n start,end,$null_ptr
depi 0,31,2,end
comb,<> start,end,$not_aligned
ldws,ma 4(end),tmp1
comib,tr 0,0,$loop /* avoid INDIGO two register interlock */
uxor,nbz 0,tmp1,0
$not_aligned:
/*
; Tricky code. The problem is that the value of of the word
; including the start of the string has some garbage bytes that
; may be 0. We don't want them to stop the string scan. So
; we make those bytes non-zero (and any old non-zero value
; will do). Notice that the end pointer has been rounded
; down to a word boundary, and then incremented to the next
; word by the time we get here. Therefore, (start-end) has
; one of the values (-3, -2, or -1). Use uaddcm to do the
; subtraction (instead of sub), and the result will be
; (-4, -3, or -2). Multiply this by 8, and put into the
; shift register (which truncates to the last 5 bits) and
; the value will be (0, 8, or 16). Use this as a bit position,
; and drop a mask down into tmp1. All the garbage bytes will
; have at least 1 bit affected by the vdepi, so all the garbage
; in this first word will be non-zero garbage.
*/
uaddcm start,end,tmp2 /* tmp2 <- { -4, -3, -2 } */
sh3add tmp2,0,tmp2 /* tmp2 <- { -32, -24, -16 } */
mtsar tmp2 /* sar <- { 0, 8, 16 } */
vdepi -1,32,tmp1
uxor,nbz 0,tmp1,0
$loop:
b,n $end_loop
ldws,ma 4(end),tmp1
comib,tr 0,0,$loop /* avoid INDIGO two register interlock */
uxor,nbz 0,tmp1,0
$end_loop:
/* adjust the end pointer to one past the end of the string */
extru,<> tmp1,7,8,0
addib,tr,n -3,end,$out
extru,<> tmp1,15,8,0
addib,tr,n -2,end,$out
extru,<> tmp1,23,8,0
addi -1,end,end
$out:
bv 0(rp)
/*
; tricky code. the end pointer is just beyond the terminating
; null byte, so the length is (end-start-1). use uaddcm
; to do this in 1 instruction
*/
uaddcm end,start,ret0
$null_ptr:
EXIT(strlen)
|
4ms/metamodule-plugin-sdk
| 5,257
|
plugin-libc/newlib/libc/machine/hppa/strcat.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/* HPUX_ID: @(#) $Revision$ */
/*
* strcat(s1, s2)
*
* Concatenate s2 on the end of s1. S1's space must be large enough.
* Return s1.
*/
#include "DEFS.h"
#define d_addr r26
#define s_addr r25
#define tmp6 r24
#define tmp1 r19
#define tmp2 r20
#define tmp3 r21
#define tmp4 r22
#define tmp5 arg3
#define save r1
ENTRY(strcat)
comb,= r0,s_addr,done /* quit if s2=NULL */
copy d_addr,ret0 /* The return value is the value of d_addr. DELAY SLOT*/
/* First look for end of s1 (d_addr) */
extru d_addr,31,2,tmp1 /* Extract the low two bits of the dest address. */
combt,= tmp1,r0,dont_mask
dep 0,31,2,d_addr /*set word alignment */
ldwm 4(d_addr),tmp2
sh3add tmp1,r0,save /* build mask based on tmp1 */
mtctl save,11
zvdepi -2,32,save
or save,tmp2,tmp2
uxor,nbz tmp2,r0,save
search:
b,n found_end /* nullified under uxor conditions above and below */
dont_mask:
ldwm 4(d_addr),tmp2
comib,tr r0,r0,search
uxor,nbz tmp2,r0,save
found_end: /* at this point d_addr points to word */
extru,<> save,7,8,r0 /* following word with null */
addib,tr,n -4,d_addr,begin_copy /*set d_addr to end of s1 */
extru,<> save,15,8,r0
addib,tr,n -3,d_addr,begin_copy
extru,<> save,23,8,r0
addi -1,d_addr,d_addr
addi -1,d_addr,d_addr
begin_copy:
extru s_addr,31,2,tmp1 /* Extract the low two bits of the source address. */
extru d_addr,31,2,tmp6 /* Extract the low two bits of the destination address. */
sub,= tmp6,tmp1,tmp3 /* Compute the shift quantity and don't branch if tmp6=tmp1. */
b not_aligned /* Not_aligned says that shifts Will be needed. */
dep 0,31,2,s_addr /* Compute the word address of the source. DELAY SLOT. */
/* aligned */
combt,= tmp6,r0,skip_mask
ldwm 4(0,s_addr),tmp1 /* tmp1 = *s_addr s_addr += 4 (DELAY SLOT) */
sh3add tmp6,r0,save
mtctl save,r11
zvdepi -2,32,save
or save,tmp1,tmp1
uxor,nbz tmp1,r0,save
b,n first_null /* special case: null in first word */
b,n skip_mask2
chunks:
b,n null_found /* delay slot for uxor below */
skip_mask2:
stbys,b,m tmp1,4(d_addr)
ldwm 4(s_addr),tmp1
skip_mask:
comib,tr 0,0,chunks
uxor,nbz tmp1,r0,save
/* Begin non_aligned code. */
not_aligned:
sh3add,>= tmp3,r0,tmp4 /* compute the shift amt.and skip load if tmp6 > tmp1. */
ldwm 4(0,s_addr),tmp1 /* load up the first word from the source. tmp1 = *s_addr++ */
ldwm 4(0,s_addr),tmp2 /* get either first or second word from source. */
combt,= tmp6,r0,chunk2 /* don't mask if whole word is valid */
mtctl tmp4,11 /* load the shift count into cr11 = shift count register. */
vshd tmp1,tmp2,tmp3 /* position data ! (delay slot) */
sh3add tmp6,r0,save /* setup r1 */
mtctl save,r11 /* set-up cr11 for mask */
zvdepi -2,32,save
or save, tmp3, tmp3
uxor,nbz tmp3,r0,save
b,n first_null2
b did_mask
mtctl tmp4,11 /* re-load the shift count into cr11 */
chunk2:
vshd tmp1,tmp2,tmp3
uxor,nbz tmp3, r0, save
b,n null_found
did_mask:
stbys,b,m tmp3,4(0,d_addr) /* store ! */
ldwm 4(0,s_addr),tmp1 /* get next word ! */
vshd tmp2,tmp1,tmp3 /* position data ! */
uxor,nbz tmp3, r0, save
b,n null_found
stwm tmp3,4(d_addr)
comib,tr 0,0,chunk2
ldwm 4(s_addr),tmp2
null_found: /* adjust d_addr and store final word */
extru,<> save,7,8,r0
addib,tr,n 1,d_addr,store_final
extru,<> save,15,8,r0
addib,tr,n 2,d_addr,store_final
extru,<> save,23,8,r0
addib,tr 3,d_addr,store_final2
bv 0(r2)
stw save,0(d_addr)
store_final:
bv 0(r2)
store_final2:
stbys,e save,0(d_addr) /* delay slot */
first_null: /* null found in first word of aligned (wrt d_addr) */
addi -4,s_addr,s_addr
ldbx tmp6(s_addr),tmp4
add tmp6,s_addr,s_addr
comib,= 0,tmp4,done
stbs,ma tmp4,1(d_addr)
ldbs 1(s_addr),tmp4
comib,= 0,tmp4,done
stbs,ma tmp4,1(d_addr)
bv 0(r2) /* done */
stbs 0,0(d_addr)
first_null2: /* null found in first word of non-aligned (wrt d_addr) */
addibt,= -1,tmp6,check3 /* check last 3 bytes of word */
extru save,15,8,tmp4
addibt,=,n -1,tmp6,check2 /* check last 2 bytes */
bv 0(r2)
stbys,b save, 0(d_addr)
check3:
combt,= tmp4,r0,done
stbs,ma tmp4,1(d_addr)
check2:
extru,<> save,23,8,tmp4
bv 0(r2)
stbs,ma tmp4,1(d_addr)
bv 0(r2)
stbs r0,0(d_addr)
done:
EXIT(strcat)
|
4ms/metamodule-plugin-sdk
| 7,312
|
plugin-libc/newlib/libc/machine/hppa/pcc_prefix.s
|
;
; (c) Copyright 1986 HEWLETT-PACKARD COMPANY
;
; To anyone who acknowledges that this file is provided "AS IS"
; without any express or implied warranty:
; permission to use, copy, modify, and distribute this file
; for any purpose is hereby granted without fee, provided that
; the above copyright notice and this notice appears in all
; copies, and that the name of Hewlett-Packard Company not be
; used in advertising or publicity pertaining to distribution
; of the software without specific, written prior permission.
; Hewlett-Packard Company makes no representations about the
; suitability of this software for any purpose.
;
; Standard Hardware Register Definitions for Use with Assembler
; version A.08.06
; - fr16-31 added at Utah
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; Hardware General Registers
r0: .equ 0
r1: .equ 1
r2: .equ 2
r3: .equ 3
r4: .equ 4
r5: .equ 5
r6: .equ 6
r7: .equ 7
r8: .equ 8
r9: .equ 9
r10: .equ 10
r11: .equ 11
r12: .equ 12
r13: .equ 13
r14: .equ 14
r15: .equ 15
r16: .equ 16
r17: .equ 17
r18: .equ 18
r19: .equ 19
r20: .equ 20
r21: .equ 21
r22: .equ 22
r23: .equ 23
r24: .equ 24
r25: .equ 25
r26: .equ 26
r27: .equ 27
r28: .equ 28
r29: .equ 29
r30: .equ 30
r31: .equ 31
; Hardware Space Registers
sr0: .equ 0
sr1: .equ 1
sr2: .equ 2
sr3: .equ 3
sr4: .equ 4
sr5: .equ 5
sr6: .equ 6
sr7: .equ 7
; Hardware Floating Point Registers
fr0: .equ 0
fr1: .equ 1
fr2: .equ 2
fr3: .equ 3
fr4: .equ 4
fr5: .equ 5
fr6: .equ 6
fr7: .equ 7
fr8: .equ 8
fr9: .equ 9
fr10: .equ 10
fr11: .equ 11
fr12: .equ 12
fr13: .equ 13
fr14: .equ 14
fr15: .equ 15
fr16: .equ 16
fr17: .equ 17
fr18: .equ 18
fr19: .equ 19
fr20: .equ 20
fr21: .equ 21
fr22: .equ 22
fr23: .equ 23
fr24: .equ 24
fr25: .equ 25
fr26: .equ 26
fr27: .equ 27
fr28: .equ 28
fr29: .equ 29
fr30: .equ 30
fr31: .equ 31
; Hardware Control Registers
cr0: .equ 0
rctr: .equ 0 ; Recovery Counter Register
cr8: .equ 8 ; Protection ID 1
pidr1: .equ 8
cr9: .equ 9 ; Protection ID 2
pidr2: .equ 9
cr10: .equ 10
ccr: .equ 10 ; Coprocessor Confiquration Register
cr11: .equ 11
sar: .equ 11 ; Shift Amount Register
cr12: .equ 12
pidr3: .equ 12 ; Protection ID 3
cr13: .equ 13
pidr4: .equ 13 ; Protection ID 4
cr14: .equ 14
iva: .equ 14 ; Interrupt Vector Address
cr15: .equ 15
eiem: .equ 15 ; External Interrupt Enable Mask
cr16: .equ 16
itmr: .equ 16 ; Interval Timer
cr17: .equ 17
pcsq: .equ 17 ; Program Counter Space queue
cr18: .equ 18
pcoq: .equ 18 ; Program Counter Offset queue
cr19: .equ 19
iir: .equ 19 ; Interruption Instruction Register
cr20: .equ 20
isr: .equ 20 ; Interruption Space Register
cr21: .equ 21
ior: .equ 21 ; Interruption Offset Register
cr22: .equ 22
ipsw: .equ 22 ; Interrpution Processor Status Word
cr23: .equ 23
eirr: .equ 23 ; External Interrupt Request
cr24: .equ 24
ppda: .equ 24 ; Physcial Page Directory Address
tr0: .equ 24 ; Temporary register 0
cr25: .equ 25
hta: .equ 25 ; Hash Table Address
tr1: .equ 25 ; Temporary register 1
cr26: .equ 26
tr2: .equ 26 ; Temporary register 2
cr27: .equ 27
tr3: .equ 27 ; Temporary register 3
cr28: .equ 28
tr4: .equ 28 ; Temporary register 4
cr29: .equ 29
tr5: .equ 29 ; Temporary register 5
cr30: .equ 30
tr6: .equ 30 ; Temporary register 6
cr31: .equ 31
tr7: .equ 31 ; Temporary register 7
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; Procedure Call Convention ~
; Register Definitions for Use with Assembler ~
; version A.08.06
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; Software Architecture General Registers
rp: .equ r2 ; return pointer
mrp: .equ r31 ; millicode return pointer
ret0: .equ r28 ; return value
ret1: .equ r29 ; return value (high part of double)
sl: .equ r29 ; static link
sp: .equ r30 ; stack pointer
dp: .equ r27 ; data pointer
arg0: .equ r26 ; argument
arg1: .equ r25 ; argument or high part of double argument
arg2: .equ r24 ; argument
arg3: .equ r23 ; argument or high part of double argument
;_____________________________________________________________________________
; Software Architecture Space Registers
; sr0 ; return link form BLE
sret: .equ sr1 ; return value
sarg: .equ sr1 ; argument
; sr4 ; PC SPACE tracker
; sr5 ; process private data
;_____________________________________________________________________________
; Software Architecture Pseudo Registers
previous_sp: .equ 64 ; old stack pointer (locates previous frame)
#if 0
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; Standard space and subspace definitions. version A.08.06
; These are generally suitable for programs on HP_UX and HPE.
; Statements commented out are used when building such things as operating
; system kernels.
;;;;;;;;;;;;;;;;
.SPACE $TEXT$, SPNUM=0,SORT=8
; .subspa $FIRST$, QUAD=0,ALIGN=2048,ACCESS=0x2c,SORT=4,FIRST
; .subspa $REAL$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=4,FIRST,LOCK
.subspa $MILLICODE$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=8
.subspa $LIT$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=16
.subspa $CODE$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=24
; .subspa $UNWIND$, QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=64
; .subspa $RECOVER$, QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=80
; .subspa $RESERVED$, QUAD=0,ALIGN=8,ACCESS=0x73,SORT=82
; .subspa $GATE$, QUAD=0,ALIGN=8,ACCESS=0x4c,SORT=84,CODE_ONLY
; Additional code subspaces should have ALIGN=8 for an interspace BV
; and should have SORT=24.
;
; For an incomplete executable (program bound to shared libraries),
; sort keys $GLOBAL$ -1 and $GLOBAL$ -2 are reserved for the $DLT$
; and $PLT$ subspaces respectively.
;;;;;;;;;;;;;;;
.SPACE $PRIVATE$, SPNUM=1,PRIVATE,SORT=16
.subspa $GLOBAL$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=40
.import $global$
.subspa $SHORTDATA$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=24
.subspa $DATA$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=16
.subspa $PFA_COUNTER$, QUAD=1,ALIGN=4,ACCESS=0x1f,SORT=8
.subspa $SHORTBSS$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=80,ZERO
.subspa $BSS$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82,ZERO
; .subspa $PCB$, QUAD=1,ALIGN=8,ACCESS=0x10,SORT=82
; .subspa $STACK$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82
; .subspa $HEAP$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82
;;;;;;;;;;;;;;;;
; .SPACE $PFA$, SPNUM=0,PRIVATE,UNLOADABLE,SORT=64
; .subspa $PFA_ADDRESS$, ALIGN=4,ACCESS=0x2c,UNLOADABLE
;;;;;;;;;;;;;;;;
; .SPACE $DEBUG$, SPNUM=2,PRIVATE,UNLOADABLE,SORT=80
; .subspa $HEADER$, ALIGN=4,ACCESS=0,UNLOADABLE,FIRST
; .subspa $GNTT$, ALIGN=4,ACCESS=0,UNLOADABLE
; .subspa $LNTT$, ALIGN=4,ACCESS=0,UNLOADABLE
; .subspa $SLT$, ALIGN=4,ACCESS=0,UNLOADABLE
; .subspa $VT$, ALIGN=4,ACCESS=0,UNLOADABLE
; To satisfy the copyright terms each .o will have a reference
; the the actual copyright. This will force the actual copyright
; message to be brought in from libgloss/hp-milli.s
.space $PRIVATE$
.subspa $DATA$
#else
.data
#endif
.import ___hp_free_copyright,data
L$copyright .word ___hp_free_copyright
|
4ms/metamodule-plugin-sdk
| 9,050
|
plugin-libc/newlib/libc/machine/hppa/strcmp.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/*
strcmp
Jerry Huck
Edgar Circenis
*/
/*
* strcmp(s1, s2)
*
* returns integer: < 0 iff s1 lexicographically less than s2
* > 0 iff s1 lexicographically greater than s2
* = 0 iff s1 lexicographically equal to s2
*/
#include "DEFS.h"
#define s1 26
#define s2 25
#define tmp1 19
#define s2word 20
#define tmp3 21
#define tmp7 22
#define s1word 23
#define save 1
#define tmp6 24
#define tmp5 28
ENTRY(strcmp)
comb,=,n s1,s2,samestring
comib,=,n 0,s1,s1isnull
comib,=,n 0,s2,s2isnull
/* Hope for word alignment. Pick up low two bits of each adress */
extru,<> s1,31,2,tmp1
ldwm 4(s1),s1word
dep,= s2,29,2,tmp1
b,n case_analysis
/* Start looping until null is found in s1 or they mis-compare */
loop:
ldwm 4(s2),s2word
loop_plus:
uxor,nbz s1word,r0,r0 /* Null in this? */
b,n nullins1
comb,=,n s1word,s2word,loop
ldwm 4(s1),s1word
/* The words do not compare equal and s1 does not have a null.
Need to treat words as unsigned and generate either a positive
or negative return value */
wordcomparereturn:
comclr,>> s1word,s2word,ret0 /*Set ret0 to 0 and skip if greater*/
ldi -2,ret0 /*Set ret0 to -2 when less */
bv r0(rp)
addi 1,ret0,ret0 /*Fix return value to be -1 or +1 */
/* s1 has a null. s2 has not been checked. */
nullins1:
/*If s2 has no nulls this is simple, but assume that it might
and fix up s1 to allow the word comparision to work by
scanning s1 and duplicating all the bytes in s2 below that byte into
the remainder of s1. A remainder only exists if the zero byte
is found in the upper three bytes */
extru,<> s1word,7,8,r0 /*in the first byte? */
dep,tr s2word,31,24,s1word /*copy low 3 bytes of *s2 into *s1 */
extru,<> s1word,15,8,r0 /*in the second byte? */
dep,tr s2word,31,16,s1word /*copy low 2 bytes of *s2 into *s1 */
extru,<> s1word,23,8,r0 /*in the third byte? */
dep s2word,31,8,s1word /*copy low 1 byte of *s2 into *s1 */
/* Do the normal unsigned compare and return */
comclr,<> s1word,s2word,ret0 /*Set ret0 to 0 and skip if not equal */
bv,n r0(rp)
comclr,>> s1word,s2word,ret0 /*Set ret0 to 0 and skip if greater*/
ldi -2,ret0 /*Set ret0 to -2 when less */
bv r0(rp)
addi 1,ret0,ret0 /*Fix return value to be -1 or +1 */
/* s1 and s2 are the same string and therefore equal */
samestring:
bv r0(rp)
copy r0,ret0
/* s1 is null. Treat as string of nulls. Therefore return
the negative of s2's first byte. s2 cannot be zero. */
s1isnull:
ldbs 0(0,s2),ret0
bv r0(rp)
sub 0,ret0,ret0
/* s2 is null. Treat as string of nulls. Therefore return
s1's first byte. s1 cannot be zero. */
s2isnull:
bv r0(rp)
ldbs 0(0,s1),ret0
case_analysis:
blr tmp1,r0
nop
/*
Case statement for non-aligned cases (we've already
checked the aligned case.
NOTE: for non-aligned cases, the absolute shift value
gets loaded into tmp3.
*/
/* S2 S1 */
nop /* 00 00 can't happen */
nop
b shifts2 /* 00 01 */
ldi 8,tmp3 /* load shift count (delay slot) */
b shifts2 /* 00 10 */
ldi 16,tmp3 /* load shift count (delay slot) */
b shifts2 /* 00 11 */
ldi 24,tmp3 /* load shift count (delay slot) */
b shifts1_0 /* 01 00 */
ldi 8,tmp3 /* load shift count (delay slot) */
b eq_align1 /* 01 01 */
ldbs,ma 1(s1),s1word
b shifts2 /* 01 10 */
ldi 8,tmp3 /* load shift count (delay slot) */
b shifts2 /* 01 11 */
ldi 16,tmp3 /* load shift count (delay slot) */
b shifts1_0 /* 10 00 */
ldi 16,tmp3 /* load shift count (delay slot) */
b shifts1 /* 10 01 */
ldi 8,tmp3 /* load shift count (delay slot) */
b eq_align2 /* 10 10 */
ldhs,ma 2(s1),s1word
b shifts2 /* 10 11 */
ldi 8,tmp3 /* load shift count (delay slot) */
b shifts1_0 /* 11 00 */
ldi 24,tmp3 /* load shift count (delay slot) */
b shifts1 /* 11 01 */
ldi 16,tmp3 /* load shift count (delay slot) */
b shifts1 /* 11 10 */
ldi 8,tmp3 /* load shift count (delay slot) */
ldbs,ma 1(s1),s1word /* 11 11 */
ldbs,ma 1(s2),s2word
sub,= s1word,s2word,ret0 /* if not equal, we can return now */
bv,n r0(rp)
comclr,<> s1word,r0,ret0
bv,n r0(rp)
b loop /* fall into main loop */
ldwm 4(s1),s1word
eq_align1:
ldbs,ma 1(s2),s2word
sub,= s1word,s2word,ret0 /* if not equal, we can return now */
bv,n r0(rp)
comclr,<> s1word,r0,ret0
bv,n r0(rp)
/* fall through to half-word aligned case */
ldhs,ma 2(s1),s1word /* load next halfword */
eq_align2:
ldhs,ma 2(s2),s2word /* load next halfword */
/* form the mask: 0xffff0000 and mask leading nulls in s1word and s2word
so that we can fall into the main loop with word aligned data */
ldi 16,save
mtctl save,r11
zvdepi -2,32,save
or save,s1word,s1word
b loop_plus /* fall into main loop */
or save,s2word,s2word
/* s2's alignment is greater than s1's alignment, so we will shift s1 */
shifts1_0:
addi -4,s1,s1 /* fix up s1 due to earlier read */
shifts1:
extru s1,31,2,tmp1
extru s2,31,2,tmp5
dep r0,31,2,s1 /* Compute word address of s1 */
dep r0,31,2,s2 /* Compute word address of s2 */
ldwm 4(s1),s1word /* get first word of s1 */
ldwm 4(s2),s2word /* get first word of s2 */
combt,=,n r0,tmp1,masks2 /* Do we need to mask beginning of s1 */
sh3add tmp1,r0,save /* save now has number of bits to mask */
mtctl save,r11
zvdepi -2,32,save /* load save with proper mask */
or save,s1word,s1word
masks2:
sh3add tmp5,r0,save /* save now has number of bits to mask */
mtctl save,r11
zvdepi -2,32,save /* load save with proper mask */
or save,s2word,s2word
ldi -1,tmp7 /* load tmp7 with 0xffffffff */
mtctl tmp3,r11 /* Move shift amount to CR11 */
more: uxor,nbz s1word,r0,r0 /* Is there a null in s1? */
b ends1
vshd tmp7,s1word,save
combf,=,n save,s2word,cmps1
ldwm 4(s1),tmp7
ldwm 4(s2),s2word
uxor,nbz tmp7,r0,r0 /* is there a null in s1? */
b ends1_0
vshd s1word,tmp7,save
combf,=,n save,s2word,cmps1
ldwm 4(s1),s1word
b more
ldwm 4(s2),s2word
cmps1: movb,tr save,s1word,wordcomparereturn
nop
ends1_0:
copy tmp7,s1word /* move tmp7 to s1word */
ends1:
combf,=,n save,s2word,nullins1 /* branch if no match */
copy save,s1word /* delay slot */
/* At this point, we know that we've read a null */
/* from s1, so we can't read more from s1 */
uxor,nbz save,r0,r0 /* are the strings equal? */
b,n samestring
vshd s1word,r0,s1word
b nullins1
ldwm 4(s2),s2word
/* s1's alignment is greater than s2's alignment, so we will shift s2 */
shifts2:
extru s1,31,2,tmp1
extru s2,31,2,tmp5
dep r0,31,2,s1 /* Compute word address of s1 */
dep r0,31,2,s2 /* Compute word address of s2 */
ldwm 4(s2),s2word /* get first word of s2 */
ldwm 4(s1),s1word /* get first word of s1 */
combt,=,n r0,tmp5,masks1 /* Do we need to mask beginning of s2 */
sh3add tmp5,r0,save /* save now has number of bits to mask */
mtctl save,r11
zvdepi -2,32,save /* load save with proper mask */
or save,s2word,s2word
masks1:
sh3add tmp1,r0,save /* save now has number of bits to mask */
mtctl save,r11
zvdepi -2,32,save /* load save with proper mask */
or save,s1word,s1word
ldi -1,tmp7 /* load tmp7 with 0xffffffff */
mtctl tmp3,r11 /* Move shift amount to CR11 */
more1: uxor,nbz s2word,r0,r0 /* is there a null in s2? */
b ends2
vshd tmp7,s2word,save
combf,=,n s1word,save,cmps2
ldwm 4(s2),tmp7
ldwm 4(s1),s1word
uxor,nbz tmp7,r0,r0 /* is there a null in s2? */
b ends2_0
vshd s2word,tmp7,save
combf,=,n s1word,save,cmps2
ldwm 4(s2),s2word
b more1
ldwm 4(s1),s1word
cmps2: movb,tr save,s2word,wordcomparereturn
nop
ends2_0:
copy tmp7,s2word /* move tmp7 to s2word */
ends2:
combf,=,n s1word,save,nullins1 /* branch if no match */
copy save,s2word /* delay slot */
/* At this point, we know that we've read a null */
/* from s2, so we can't read more from s2 */
uxor,nbz save,r0,r0 /* are the strings equal? */
b,n samestring
vshd s2word,r0,s2word
b nullins1
ldwm 4(s1),s1word
EXIT(strcmp)
|
4ms/metamodule-plugin-sdk
| 8,847
|
plugin-libc/newlib/libc/machine/hppa/strncpy.S
|
/*
* (c) Copyright 1986 HEWLETT-PACKARD COMPANY
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Hewlett-Packard Company not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Hewlett-Packard Company makes no representations about the
* suitability of this software for any purpose.
*/
/* HPUX_ID: @(#) $Revision$ */
/*
* strncpy(s1, s2, n)
*
* Copy s2 to s1, truncating or null-padding to always copy n bytes
* return s1
*/
#include "DEFS.h"
#define d_addr r26
#define s_addr r25
#define count r24
#define tmp1 r19
#define tmp2 r20
#define tmp3 r21
#define tmp4 r22
#define tmp5 arg3
#define save r1
ENTRY(strncpy)
combt,= s_addr,r0,pad_null_bytes1 /* if s2==NULL then pad nulls and exit */
copy d_addr,ret0 /* The return value is defined to be the value of d_addr. DELAY SLOT*/
addibt,<,n -4,count,byteloop /* If count is <= 4 don't get fancy.*/
extru s_addr,31,2,tmp1 /* Extract the low two bits of the source address.*/
extru d_addr,31,2,tmp5 /* Extract the low two bits of the destination address.*/
add count,tmp5,count /* pre increment the count by the byte address so that the count is*/
comb,<> tmp5,tmp1,not_aligned /* branch if tmp5<>tmp1. */
dep 0,31,2,s_addr /* Compute the word address of the source. DELAY SLOT.*/
/* aligned*/
combt,= tmp5,r0,skip_mask
ldwm 4(0,s_addr),tmp1 /* tmp1 = *s_addr s_addr += 4 (DELAY SLOT)*/
sh3add tmp5,r0,save /* compute mask in save*/
mtctl save,11
zvdepi -2,32,save
b skip_mask /* don't reload tmp1*/
or save,tmp1,tmp1 /* or mask with data*/
chunks:
ldwm 4(0,s_addr),tmp1 /* get a word*/
skip_mask:
uxor,nbz tmp1,r0,save /* check for null*/
b,n null1
addibf,< -4,count,chunks
stbys,b,m tmp1,4(0,d_addr) /* store word (delay slot)*/
/* back_porch last word to store*/
addibt,=,n 4,count,done /* if count = 0 we're, of course, done !*/
ldws 0(s_addr),tmp1 /* load up the back_porch*/
add d_addr,count,d_addr/* final store address is +1 too high !*/
sh3add count,r0, save /* setup right mask based on count*/
mtctl save,r11
zvdepi -2,32,save /*save now has left-hand mask*/
uaddcm r0,save,save /*form right hand mask */
or tmp1,save,tmp1 /*and insert data*/
uxor,nbz tmp1,r0,save /* check for null*/
b,n null2
bv 0(r2)
stbys,e tmp1,0(d_addr) /* done */
/* Begin non_aligned code. */
not_aligned:
sub,>= tmp5,tmp1,tmp3 /* compute the shift amt.and skip load if tmp5 > tmp1.*/
ldwm 4(0,s_addr),tmp1 /* load up the first word from the source. tmp1 = *s_addr++*/
zdep tmp3,28,29,tmp4 /* compute the number of bits to shift */
mtctl tmp4,11 /* load the shift count into cr11 = shift count register.*/
addibt,<,n -4,count,chkchnk2 /* first step in pre adjustment of count for looping.*/
ldwm 4(0,s_addr),tmp2 /* get either first or second word from source. */
combt,= tmp5,r0,skip_mask2 /* don't mask if whole word is valid*/
vshd tmp1,tmp2,tmp3 /* position data ! (delay slot)*/
sh3add tmp5,r0,save /* setup r1*/
mtctl save,r11 /* setup mask in save*/
zvdepi -2,32,save
or save, tmp3, tmp3
mtctl tmp4,11 /* re-load the shift count into cr11 */
b skip_mask2
copy r0, tmp5 /* zero out tmp5 so we don't try to mask again*/
chunk2:
ldwm 4(0,s_addr),tmp2
vshd tmp1,tmp2,tmp3
skip_mask2:
uxor,nbz tmp3, r0, save
b,n null3
stbys,b,m tmp3,4(0,d_addr) /* store ! */
ldwm 4(0,s_addr),tmp1 /* get 2nd word ! */
vshd tmp2,tmp1,tmp3 /* position data ! */
uxor,nbz tmp3, r0, save
b,n null4
addibf,< -8,count,chunk2 /* If count is still >= 8 do another loop.*/
stbys,b,m tmp3,4(0,d_addr) /* store !*/
chkchnk2:
addibt,<,n 4,count,bp_0 /* if we don't have 4 bytes left then do the back porch (bp_0)*/
subchnk2: /* we have less than 8 chars to copy*/
ldwm 4(0,s_addr),tmp2 /* get next word !*/
combt,= tmp5,r0,skip_mask3
vshd tmp1,tmp2,tmp3 /* position data !*/
sh3add tmp5,r0,save /* setup r1*/
mtctl save,r11 /* setup mask in save*/
zvdepi -2,32,save
or save, tmp3, tmp3
mtctl tmp4,11 /* restore shift value again */
copy r0, tmp5 /* zero out tmp5 so we don't try to mask again*/
skip_mask3:
uxor,nbz tmp3,r0,save
b,n null4
b bp_1 /* we now have less than 4 bytes to move*/
stbys,b,m tmp3,4(0,d_addr) /* store !*/
bp_0:
copy tmp1,tmp2 /* switch registers used in the shift process.*/
addibt,<=,n 4,count,done /* if count = -4 this implies that count = 0 -> done */
bp_1:
ldwm 4(0,s_addr),tmp1 /* get final word ! */
vshd tmp2,tmp1,tmp3 /* position data !*/
uxor,sbz tmp3,r0,save /* if some-byte-zero */
b no_null /* don't goto no_null-find which null instead */
add d_addr,count,d_addr /* get d_addr ready for stbys,e */
extru,<> save,7,8,r0
b found_null5
copy r0, tmp5
extru,<> save,15,8,r0
b found_null5
ldil 0x1FE000,tmp5 /* setup mask (FF000000)*/
extru,<> save,23,8,r0
b found_null5
ldil 0x1FFFE0,tmp5 /* setup mask (FFFF0000)*/
ldo -1(r0),tmp5 /* setup mask (FFFFFFFF)*/
found_null5:
and tmp3,tmp5,tmp3 /* zero out tmp5 based on mask in tmp5*/
no_null:
bv 0(r2) /* were done*/
stbys,e tmp3,0(0,d_addr) /* store the data !*/
/* here we do ye old byte-at-a-time moves.*/
byteloop:
addibt,=,n 4,count,done
comb,= 0,s_addr,done
stbs r0,0(d_addr) /* store null in case s_addr == NULL */
ldbs,ma 1(s_addr),tmp1
encore:
combt,=,n tmp1,r0, pad_null_bytes1
stbs,ma tmp1,1(d_addr)
addibf,=,n -1,count,encore
ldbs,ma 1(s_addr),tmp1
b,n done
pnb_1:
addibt,=,n 4,count,done /* if count was already 0 then we're done*/
pad_null_bytes1:
combt,=,n count,r0,done /* if count==0 then exit */
pad_null_bytes2:
addibf,= -1,count,pad_null_bytes2
stbs,ma r0,1(d_addr)
b,n done
pad_nulls:
addibf,<=,n -4,count,pad_nulls
stwm r0,4(d_addr)
b,n pnb_1
null1:
extru,<> save,7,8,r0
b found_null1
copy r0, tmp5
extru,<> save,15,8,r0
b found_null1
ldil 0x1FE000,tmp5 /* setup mask (FF000000)*/
extru,<> save,23,8,r0
b found_null1
ldil 0x1FFFE0,tmp5 /* setup mask (FFFF0000)*/
ldo -1(r0),tmp5 /* setup mask (FFFFFFFF)*/
found_null1:
and tmp1,tmp5,tmp1 /*zero out tmp1 according to mask*/
b pad_nulls /* nullify remaining count bytes*/
stbys,b,m tmp1,4(0,d_addr) /* first word (account for alignment)*/
null2: /* back porch case. We have less than 4 bytes to go.*/
extru,<> save,7,8,r0 /* is null in 1st byte? */
b found_null2
copy r0, tmp5
extru,<> save,15,8,r0 /* is null in 2nd byte? */
b found_null2
ldil 0x1FE000,tmp5 /* setup mask (FF000000)*/
b found_null2 /* null must be in 3rd byte */
ldil 0x1FFFE0,tmp5 /* setup mask (FFFF0000)*/
found_null2:
and tmp1,tmp5,tmp1 /*zero out tmp1 according to mask*/
bv 0(r2) /* we're done*/
stbys,e tmp1,0(0,d_addr) /* last word (back porch)*/
null3: /* not_aligned case where null is found in first of two words--adjust count*/
extru,<> save,7,8,r0
b found_null3
copy r0, tmp5
extru,<> save,15,8,r0
b found_null3
ldil 0x1FE000,tmp5 /* setup mask (FF000000)*/
extru,<> save,23,8,r0
b found_null3
ldil 0x1FFFE0,tmp5 /* setup mask (FFFF0000)*/
ldo -1(r0),tmp5 /* setup mask (FFFFFFFF)*/
found_null3:
addi 4,count,count /* fix count since null is in first of two words*/
and tmp3,tmp5,tmp3 /*zero out tmp3 according to mask*/
b pad_nulls /* nullify remaining count bytes*/
stbys,b,m tmp3,4(d_addr)
null4: /* not_aligned case where null is found in second of two words*/
extru,<> save,7,8,r0
b found_null4
copy r0, tmp5
extru,<> save,15,8,r0
b found_null4
ldil 0x1FE000,tmp5 /* setup mask (FF000000)*/
extru,<> save,23,8,r0
b found_null4
ldil 0x1FFFE0,tmp5 /* setup mask (FFFF0000)*/
ldo -1(r0),tmp5 /* setup mask (FFFFFFFF)*/
found_null4:
and tmp3,tmp5,tmp3 /*zero out tmp4 according to mask*/
b pad_nulls /* nullify remaining count bytes*/
stbys,b,m tmp3,4(d_addr)
done:
EXIT(strncpy)
|
4ms/metamodule-plugin-sdk
| 3,913
|
plugin-libc/newlib/libc/machine/m32c/setjmp.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
#define A16 1
#endif
/* We implement setjmp/longjmp much like the way gcc implements
exceptions - we create new stack frames, then switch to them and
return. Thus, the two setjmp's below each push all the relevent
registers, then copy the whole frame into the buffer (first $sp is
moved, then smovf copies the frame itself), and the two longjmps
restore $sp, copy the frame back into place, and issue the same
return as the setjmp would have used.
Since the sizes of registers differs between the 16 and 24 bit
models, we provide separate implementations for each rather than
trying to parameterize them.
Jump buffer sizes: 21 bytes for 16 bit, 34 bytes for 24 bit.
*/
.text
#ifdef A16 /* 16 bit versions */
.global _setjmp
_setjmp:
enter #0
pushm r1,r2,r3,a0,a1,sb,fb
; At this point, the stack looks like this:
; ... [pc:3] [oldfb:2] <fb> [r1:2] [r2:2] [r3:2] [a0:2] [a1:2] [sb:2] [fb:2] <sp> */
mov.w r1,a1 ; a1 is the destination of smovf
mov.b #0,r1h
stc sp,a0 ; r1h:a0 is the source of smovf
mov.w a0,[a1]
add.w #2,a1
mov.w #19,r3 ; plus two for sp later
smovf.b
; Return 0 to caller.
mov.w #0,r0
popm r1,r2,r3,a0,a1,sb,fb
exitd
.global _longjmp
_longjmp:
enter #0
mov.w r1,a0 ; pointer to jump buf
mov.w r2,r0 ; setjmp's "new" return value
mov.b #0,r1h ; r1h: a0 is the source, now jmpbuf
mov.w [a0],a1 ; dest is new stack
ldc a1,sp
add.w #2,a0
mov.w #19,r3
smovf.b
;; now return to our caller with this newly restored frame
popm r1,r2,r3,a0,a1,sb,fb
exitd
#else /* 24 bit versions */
.global _setjmp
_setjmp:
enter #0
pushm r1,r2,r3,a0,a1,sb,fb
; At this point, the stack looks like this:
; ... [jbuf:4] [pc:4] [oldfb:4] <fb> [r1:2] [r2:2] [r3:2] [a0:4] [a1:4] [sb:4] [fb:4] <sp> */
mov.l 8[fb],a1 ; a1 is the destination of smovf
stc sp,a0 ; r1h:a0 is the source of smovf
mov.l a0,[a1]
add.l #4,a1
mov.w #30,r3 ; plus two for sp later
smovf.b
; Return 0 to caller.
mov.w #0,r0
popm r1,r2,r3,a0,a1,sb,fb
exitd
.global _longjmp
_longjmp:
enter #0
; ... [rv:2] [jbuf:4] [pc:4] [oldfb:4] <fb>
mov.l 8[fb],a0 ; pointer to jump buf
mov.w 12[fb],r0 ; setjmp's "new" return value
mov.l [a0],a1 ; dest is new stack
ldc a1,sp
add.l #4,a0
mov.w #30,r3
smovf.b
;; now return to our caller with this newly restored frame
popm r1,r2,r3,a0,a1,sb,fb
exitd
#endif
|
4ms/metamodule-plugin-sdk
| 2,426
|
plugin-libc/newlib/libc/machine/z8k/memcpy.S
|
/*
* memcpy routine for Z8000
* Copyright (C) 2004 Christian Groessler <chris@groessler.org>
*
* Permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies.
*
* This file is distributed WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
/* void *memcpy(void *dest, const void *src, size_t length);
*/
name "memcpy.S"
.text
even
global _memcpy
global memmove_entry
_memcpy:
#ifdef __Z8001__
segm
#ifdef __STD_CALL__
ldl rr6,rr14(#4)
ldl rr4,rr14(#8)
ldl rr2,rr14(#12)
#else
pushl @rr14,rr6
#endif
/* rr2 - length (high word ignored)
* rr4 - src
* rr6 - dest
*/
testl rr2
jr z,finish
memmove_entry: /* external entry point from memmove */
bitb rl7,#0 /* odd destination address? */
jr nz,testsrc
bitb rl5,#0 /* odd source address? */
jr nz,odd_copy
jr t,even_copy /* dest even, src odd */
testsrc:
bitb rl5,#0
jr z,odd_copy /* src even, dest odd */
ldib @rr6,@rr4,r3
jr ov,finish /* jump if r3 is zero now */
/* copy words */
even_copy:
ld r2,r3 /* remember length */
srl r3,#1
jr z,no_words
ldir @rr6,@rr4,r3
no_words:
bitb rl2,#0 /* odd length? */
jr z,finish
ldib @rr6,@rr4,r2 /* yes, copy last byte */
jr finish
/* copy bytes */
odd_copy:
ldirb @rr6,@rr4,r3
finish:
#ifdef __STD_CALL__
ldl rr6,rr14(#4)
#else
popl rr2,@rr14
#endif
#else /* above Z8001, below Z8002 */
unsegm
#ifdef __STD_CALL__
ld r7,r15(#2)
ld r6,r15(#4)
ld r5,r15(#6)
#else
ld r2,r7 /* buffer pointer return value */
#endif
/* r5 - length
* r6 - src
* r7 - dest
*/
test r5
jr z,finish
memmove_entry: /* external entry point from memmove */
bitb rl7,#0 /* odd destination address? */
jr nz,testsrc
bitb rl6,#0 /* odd source address? */
jr nz,odd_copy
jr t,even_copy /* dest even, src odd */
testsrc:
bitb rl6,#0
jr z,odd_copy /* src even, dest odd */
ldib @r7,@r6,r5
jr ov,finish /* jump if r5 is zero now */
/* copy words */
even_copy:
ld r4,r5 /* remember length */
srl r5,#1
jr z,no_words
ldir @r7,@r6,r5
no_words:
bitb rl4,#0 /* odd length? */
jr z,finish
ldib @r7,@r6,r4 /* yes, copy last byte */
jr finish
/* copy bytes */
odd_copy:
ldirb @r7,@r6,r5
finish:
#ifdef __STD_CALL__
ld r7,r15(#2)
#endif
#endif /* Z8002 */
ret
.end
|
4ms/metamodule-plugin-sdk
| 1,905
|
plugin-libc/newlib/libc/machine/z8k/setjmp.S
|
.global _setjmp
.global _longjmp
#ifdef __Z8001__
segm
#ifdef __STD_CALL__
_setjmp:
ldl rr6,rr14(#4) ! get argument
ldl rr2,@rr14 ! fetch pc
ldl @rr6,rr2 ! save it
ldl rr6(#16),rr8
ldl rr6(#4),rr10
ldl rr6(#8),rr12 ! remember frame pointer
ldl rr6(#12),rr14 ! remember stack pointer
ldk r7,#0
ret t
_longjmp:
ldl rr4,rr14(#4) ! get first argument
ld r7,rr14(#8) ! get return value
ldl rr8,rr4(#16)
ldl rr10,rr4(#4)
ldl rr12,rr4(#8) ! restore old frame pointer
ldl rr14,rr4(#12) ! restore old stack pointer
ldl rr4,@rr4 ! return address
inc r15,#4
jp @rr4
#else /* above __STD_CALL_, below not */
_setjmp:
ldl rr2,@rr14 ! fetch pc
ldl @rr6,rr2 ! save it
ldl rr6(16),rr8
ldl rr6(4),rr10
ldl rr6(8),rr12 ! and the other special regs
ldl rr6(12),rr14
ldk r2,#0
ret t
_longjmp:
ld r2,r5 ! get return value
ldl rr4,rr6(0)
ldl rr8,rr6(16)
ldl rr10,rr6(4)
ldl rr12,rr6(8)
ldl rr14,rr6(12)
inc r15,#4
jp @rr4
#endif /* not __STD_CALL__ */
#else /* above Z8001, below Z8002 */
unseg
#ifdef __STD_CALL__
_setjmp:
ld r7,r15(#2) ! get argument
ld r2,@r15 ! fetch pc
ld @r7,r2 ! save it
ldl r7(#14),rr8
ldl r7(#2),rr10
ldl r7(#6),rr12 ! remember frame pointer
ldl r7(#10),rr14 ! remember stack pointer
ldk r7,#0
ret t
_longjmp:
ld r4,r15(#2) ! get first argument (jmp_buf)
ld r7,r15(#4) ! get return value
ldl rr8,r4(#14)
ldl rr10,r4(#2)
ldl rr12,r4(#6) ! restore old frame pointer
ldl rr14,r4(#10) ! restore old stack pointer
ld r4,@r4 ! return address
inc r15,#2
jp @r4
#else /* above __STD_CALL_, below not */
_setjmp:
ld r2,@r15 ! fetch pc
ld @r7,r2 ! save it
ldl r7(4),rr10
ldl r7(8),rr12 ! and the other special regs
ldl r7(12),rr14
ldk r2,#0
ret t
_longjmp:
ld r2,r6 ! get return value
ld r4,@r7
ldl rr10,r7(4)
ldl rr12,r7(8)
ldl rr14,r7(12)
inc r15,#2
jp @r4
#endif /* not __STD_CALL__ */
#endif /* Z8002 version */
|
4ms/metamodule-plugin-sdk
| 3,306
|
plugin-libc/newlib/libc/machine/z8k/memmove.S
|
/*
* memmove routine for Z8000
* Copyright (C) 2004 Christian Groessler <chris@groessler.org>
*
* Permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies.
*
* This file is distributed WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
/* void *memmove(void *dest, const void *src, size_t length);
*/
name "memmove.S"
.text
even
global _memmove
_memmove:
#ifdef __Z8001__
segm
#ifdef __STD_CALL__
ldl rr6,rr14(#4)
ldl rr4,rr14(#8)
ldl rr2,rr14(#12)
#else
pushl @rr14,rr6
#endif
/* rr2 - length (high word ignored)
* rr4 - src
* rr6 - dest
*/
testl rr2
jr z,finish
/* check for destructive overlap (src < dest && dest < src + length) */
cpl rr6,rr4
jp ule,memmove_entry /* non-destructive, let memcpy do the work */
ldl rr0,rr2
addl rr0,rr4 /* rr0 = src + length */
cpl rr0,rr6
jp ult,memmove_entry /* non-destructive, let memcpy do the work */
/* set-up pointers to copy backwards, add (length - 1) */
addl rr4,rr2 /* src + length */
addl rr6,rr2 /* dest + length */
subl rr4,#1
subl rr6,#1
/* check alignment */
bitb rl7,#0 /* odd destination address? */
jr z,testsrc
bitb rl5,#0 /* odd source address? */
jr z,odd_copy
jr even_copy
testsrc:
bitb rl5,#0
jr nz,odd_copy /* src even, dest odd */
lddb @rr6,@rr4,r3
jr ov,finish /* jump if r5 is zero now */
/* copy words */
even_copy:
ld r2,r3 /* remember length */
srl r3,#1
/* jr z,no_words it cannot be zero here */
dec r5,#1
dec r7,#1
lddr @rr6,@rr4,r3
no_words:
bitb rl2,#0 /* odd length? */
jr z,finish
inc r5,#1
inc r7,#1
lddb @rr6,@rr4,r2 /* yes, copy last byte */
jr finish
/* copy bytes */
odd_copy:
lddrb @rr6,@rr4,r3
finish:
#ifdef __STD_CALL__
ldl rr6,rr14(#4)
#else
popl rr2,@rr14
#endif
#else /* above Z8001, below Z8002 */
unsegm
#ifdef __STD_CALL__
ld r7,r15(#2)
ld r6,r15(#4)
ld r5,r15(#6)
#else
ld r2,r7 /* buffer pointer return value */
#endif
/* r5 - length
* r6 - src
* r7 - dest
*/
test r5
jr z,finish
/* check for destructive overlap (src < dest && dest < src + length) */
cp r7,r6
jp ule,memmove_entry /* non-destructive, let memcpy do the work */
ld r0,r5
add r0,r6 /* r0 = src + length */
cp r0,r7
jp ult,memmove_entry /* non-destructive, let memcpy do the work */
/* set-up pointers to copy backwards, add (length - 1) */
add r6,r5 /* src + length */
add r7,r5 /* dest + length */
dec r6,#1
dec r7,#1
/* check alignment */
bitb rl7,#0 /* odd destination address? */
jr z,testsrc
bitb rl6,#0 /* odd source address? */
jr z,odd_copy
jr even_copy
testsrc:
bitb rl6,#0
jr nz,odd_copy /* src even, dest odd */
lddb @r7,@r6,r5
jr ov,finish /* jump if r5 is zero now */
/* copy words */
even_copy:
ld r4,r5 /* remember length */
srl r5,#1
/* jr z,no_words it cannot be zero here */
dec r6,#1
dec r7,#1
lddr @r7,@r6,r5
no_words:
bitb rl4,#0 /* odd length? */
jr z,finish
inc r6,#1
inc r7,#1
lddb @r7,@r6,r4 /* yes, copy last byte */
jr finish
/* copy bytes */
odd_copy:
lddrb @r7,@r6,r5
finish:
#ifdef __STD_CALL__
ld r7,r15(#2)
#endif
#endif /* Z8002 */
ret
.end
|
4ms/metamodule-plugin-sdk
| 1,908
|
plugin-libc/newlib/libc/machine/z8k/memset.S
|
/*
* memset routine for Z8000
* Copyright (C) 2004 Christian Groessler <chris@groessler.org>
*
* Permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies.
*
* This file is distributed WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
/* void *memset(void *buffer, int value, size_t length);
*/
name "memset.S"
.text
even
global _memset
_memset:
#ifdef __Z8001__
segm
#ifdef __STD_CALL__
ldl rr6,rr14(#4)
ld r5,rr14(#8)
ldl rr2,rr14(#10)
#else
pushl @rr14,rr6
#endif
/* rr2 - length
* rl5 - value
* rr6 - buffer
*/
testl rr2
jr z,finish
ldb rh5,rl5
ld r1,r5 /* r1 contains value */
bit r7,#0
jr z,not_odd
ldb @rr6,rl1
inc r7,#1
subl rr2,#1
jr z,finish
not_odd:ld r0,r3 /* remember length */
srl r3,#1
jr z,no_words
ldl rr4,rr6
ld @rr6,r1
inc r7,#2
dec r3,#1
jr z,no_words
ldir @rr6,@rr4,r3 /* fill words */
no_words:
bit r0,#0 /* one byte remaining? */
jr z,finish
ldb @rr6,rl1
finish:
#ifdef __STD_CALL__
ldl rr6,rr14(#4)
#else
popl rr2,@rr14
#endif
#else /* above Z8001, below Z8002 */
unsegm
#ifdef __STD_CALL__
ld r7,r15(#2)
ld r6,r15(#4)
ld r5,r15(#6)
#else
ld r2,r7 /* buffer pointer return value */
#endif
/* r5 - length
* r6 - value
* r7 - buffer
*/
test r5
jr z,finish
ldb rh6,rl6
ld r1,r6 /* r1 contains value */
bit r7,#0
jr z,not_odd
ldb @r7,rl1
inc r7,#1
dec r5,#1
jr z,finish
not_odd:ld r0,r5 /* remember length */
srl r5,#1
jr z,no_words
ld r4,r7
ld @r7,r1
inc r7,#2
dec r5,#1
jr z,no_words
ldir @r7,@r4,r5 /* fill words */
no_words:
bit r0,#0 /* one byte remaining? */
jr z,finish
ldb @r7,rl1
finish:
#ifdef __STD_CALL__
ld r7,r15(#2)
#endif
#endif /* Z8002 */
ret
.end
|
4ms/metamodule-plugin-sdk
| 2,911
|
plugin-libc/newlib/libc/machine/z8k/memcmp.S
|
/*
* memcmp routine for Z8000
* Copyright (C) 2004 Christian Groessler <chris@groessler.org>
*
* Permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies.
*
* This file is distributed WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
/* int memcmp(const void *b1, const void *b2, size_t length);
*/
name "memcmp.S"
.text
even
global _memcmp
_memcmp:
#ifdef __Z8001__
segm
#ifdef __STD_CALL__
ldl rr6,rr14(#4)
ldl rr4,rr14(#8)
ldl rr2,rr14(#12)
#endif
/* rr2 - length (high word ignored)
* rr4 - b2
* rr6 - b1
*/
clr r1 /* initialize return value */
testl rr2
jr z,finish
bitb rl7,#0 /* odd b1? */
jr nz,testb2
bitb rl5,#0 /* odd b2? */
jr nz,odd_cmp /* b1 even, b2 odd */
jr t,even_cmp
testb2:
bitb rl5,#0
jr z,odd_cmp /* b2 even, b1 odd */
cpsib @rr6,@rr4,r3,eq
jr z,beq /* bytes are the same */
jr t,byte_diff
beq: jr ov,finish /* jump if r3 is zero now */
/* compare words */
even_cmp:
ld r2,r3 /* remember length */
srl r3,#1
jr z,no_words
cpsir @rr6,@rr4,r3,ne
jr nz,no_words
dec r7,#2
dec r5,#2 /* point to different bytes */
ldk r3,#2
jr t,odd_cmp
no_words:
bitb rl2,#0 /* odd length? */
jr z,finish
cpsib @rr6,@rr4,r3,eq
jr z,finish /* last bytes are the same */
jr t,byte_diff
/* compare bytes */
odd_cmp:
cpsirb @rr6,@rr4,r3,ne
jr nz,finish
byte_diff:
dec r7,#1
dec r5,#1 /* point to different bytes */
ldb rl1,@rr6
clr r0
ldb rl0,@rr4
sub r1,r0
finish: /* set return value */
#ifdef __STD_CALL__
ld r7,r1
#else
ld r2,r1
#endif
#else /* above Z8001, below Z8002 */
unsegm
#ifdef __STD_CALL__
ld r7,r15(#2)
ld r6,r15(#4)
ld r5,r15(#6)
#endif
/* r5 - length
* r6 - b2
* r7 - b1
*/
clr r1 /* initialize return value */
test r5
jr z,finish
bitb rl7,#0 /* odd destination address? */
jr nz,testb2
bitb rl6,#0 /* odd source address? */
jr nz,odd_cmp /* b1 even, b2 odd */
jr t,even_cmp
testb2:
bitb rl6,#0
jr z,odd_cmp /* b2 even, b1 odd */
cpsib @r7,@r6,r5,eq
jr z,beq /* bytes are the same */
jr t,byte_diff
beq: jr ov,finish /* jump if r3 is zero now */
/* compare words */
even_cmp:
ld r4,r5 /* remember length */
srl r5,#1
jr z,no_words
cpsir @r7,@r6,r5,ne
jr nz,no_words
dec r7,#2
dec r6,#2 /* point to different bytes */
ldk r5,#2
jr t,odd_cmp
no_words:
bitb rl4,#0 /* odd length? */
jr z,finish
cpsib @r7,@r6,r4,eq
jr z,finish /* last bytes are the same */
jr t,byte_diff
/* compare bytes */
odd_cmp:
cpsirb @r7,@r6,r5,ne
jr nz,finish
byte_diff:
dec r7,#1
dec r6,#1 /* point to different bytes */
ldb rl1,@r7
clr r0
ldb rl0,@r6
sub r1,r0
finish:
#ifdef __STD_CALL__
ld r7,r1
#else
ld r2,r1
#endif
#endif /* Z8002 */
ret
.end
|
4ms/metamodule-plugin-sdk
| 6,260
|
plugin-libc/newlib/libc/machine/spu/spu_timer_flih.S
|
/*
(C) Copyright IBM Corp. 2008
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of IBM nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* First-level interrupt handler. */
/* The following two convenience macros assist in the coding of the
saving and restoring the volatile register starting from register
2 up to register 79.
saveregs first, last Saves registers from first to the last.
restoreregs first, last Restores registers from last down to first.
Note: first must be less than or equal to last. */
.macro saveregs first, last
stqd $\first, -(STACK_SKIP+\first)*16($SP)
.if \last-\first
saveregs "(\first+1)",\last
.endif
.endm
.macro restoreregs first, last
lqd $\last, (82-\last)*16($SP)
.if \last-\first
restoreregs \first,"(\last-1)"
.endif
.endm
.section .interrupt,"ax"
.align 3
.type spu_flih, @function
spu_flih:
/* Adjust the stack pointer to skip the maximum register save area
(STACK_SKIP quadword registers) in case an interrupt occurred while
executing a leaf function that used the stack area without actually
allocating its own stack frame. */
.set STACK_SKIP, 125
/* Save the current link register on a new stack frame for the
normal spu_flih() version of this file. */
stqd $0, -(STACK_SKIP+80)*16($SP)
stqd $SP, -(STACK_SKIP+82)*16($SP) /* Save back chain pointer. */
saveregs 2, 39
il $2, -(STACK_SKIP+82)*16 /* Stack frame size. */
rdch $3, $SPU_RdEventStat /* Read event status. */
rdch $6, $SPU_RdEventMask /* Read event mask. */
hbrp /* Open a slot for instruction prefetch. */
saveregs 40,59
clz $4, $3 /* Get first slih index. */
stqd $6, -(STACK_SKIP+1)*16($SP) /* Save event mask on stack. */
saveregs 60, 67
/* Do not disable/ack the decrementer event here.
The timer library manages this and expects it
to be enabled upon entry to the SLIH. */
il $7, 0x20
andc $5, $3, $7
andc $7, $6, $5 /* Clear event bits. */
saveregs 68, 69
wrch $SPU_WrEventAck, $3 /* Ack events(s) - include decrementer event. */
wrch $SPU_WrEventMask, $7 /* Disable event(s) - exclude decrementer event. */
saveregs 70, 79
a $SP, $SP, $2 /* Instantiate flih stack frame. */
next_event:
/* Fetch and dispatch the event handler for the first non-zero event. The
dispatch handler is indexed into the __spu_slih_handlers array using the
count of zero off the event status as an index. */
ila $5, __spu_slih_handlers /* Slih array offset. */
shli $4, $4, 2 /* Slih entry offset. */
lqx $5, $4, $5 /* Load slih address. */
rotqby $5, $5, $4 /* Rotate to word 0. */
bisl $0, $5 /* Branch to slih. */
clz $4, $3 /* Get next slih index. */
brnz $3, next_event
lqd $2, 81*16($SP) /* Read event mask from stack. */
restoreregs 40, 79
wrch $SPU_WrEventMask, $2 /* Restore event mask. */
hbrp /* Open a slot for instruction pre-fetch. */
restoreregs 2, 39
/* Restore the link register from the new stack frame for the
normal spu_flih() version of this file. */
lqd $0, 2*16($SP)
lqd $SP, 0*16($SP) /* restore stack pointer from back chain ptr. */
irete /* Return from interrupt and re-enable interrupts. */
.size spu_flih, .-spu_flih
/* spu_slih_handlers[]
Here we initialize 33 default event handlers. The first entry in this array
corresponds to the event handler for the event associated with bit 0 of
Channel 0 (External Event Status). The 32nd entry in this array corresponds
to bit 31 of Channel 0 (DMA Tag Status Update Event). The 33rd entry in
this array is a special case entry to handle "phantom events" which occur
when the channel count for Channel 0 is 1, causing an asynchronous SPU
interrupt, but the value returned for a read of Channel 0 is 0. The index
calculated into this array by spu_flih() for this case is 32, hence the
33rd entry. */
.data
.align 4
.extern __spu_default_slih
.global __spu_slih_handlers
.type __spu_slih_handlers, @object
__spu_slih_handlers:
.rept 33
.long __spu_default_slih
.endr
.size __spu_slih_handlers, .-__spu_slih_handlers
|
4ms/metamodule-plugin-sdk
| 1,585
|
plugin-libc/newlib/libc/machine/spu/sniprintf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#define snprintf sniprintf
#include "snprintf.S"
|
4ms/metamodule-plugin-sdk
| 2,250
|
plugin-libc/newlib/libc/machine/spu/fprintf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#include "c99ppe.h"
.text
.align 4
GLOBL fprintf
.type fprintf, @function
fprintf:
stqd $0, 16($sp) /* save caller address */
il $2, 2 /* number of fixed arguments */
brsl $0, __stack_reg_va /* save register to the stack frame */
brsl $0, __check_init
lqd $3, 16*2($sp) /* $3 <- saved FP on the stack frame */
lqd $2, 0($3) /* FP = fp->_fp */
rotqby $2, $2, $3
stqd $2, 16*2($sp) /* replace FP on the stack frame */
il $3, SPE_C99_SIGNALCODE
il $4, SPE_C99_VFPRINTF
ai $5, $sp, 16*2 /* data ($3 save address) */
brsl $0, __send_to_ppe
il $2, 16*(SPE_STACK_REGS+2+2)
a $sp, $sp, $2
lqd $0, 16($sp) /* load caller address */
bi $0 /* return to caller */
.size fprintf, .-fprintf
|
4ms/metamodule-plugin-sdk
| 5,817
|
plugin-libc/newlib/libc/machine/spu/stack_reg_va.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file contains code use to construct a PIC, spu side, syscall
* function with variable parameters in accordance with the CBE ABI.
*
* This function is equivalent to constructing a va_list structure and
* calling the va_list form of the function. Therefore, for example,
* a printf function stack frame will look like this:
*
* | Stack | high memory
* | Parms |
* | |
* |------------|
* | Link Reg |
* |------------|
* | Back Chain |<-----. <---- input SP
* |------------| |
* | Reg 74 | |
* |------------| |
* | Reg 73 | |
* |------------| |
* // ... // |
* |------------| |
* | Reg 5 | |
* |------------| |
* | Reg 4 |<--. |
* |------------| | |
* va_list.| call_stack |------'
* |------------| |
* va_list.| next_arg |---'
* |------------|
* | format (r3)| <---- start of parameters
* |------------| |------------|
* | stack | | |
* | code | |(Back Chain)| <---- output SP
* | 1-3 qwords | <---- code_ptr `------------'
* `------------'
* low memory
*
* This was written in assembly so that it is smaller than what would
* be produced by using va_start.
*/
#include "c99ppe.h"
#define parms $2 /* Number of fixed arguments */
#define offset $67
#define flag $68
#define regdec $69
#define link $70
#define code_ptr $71
#define ptr $72
#define inst $73
#define tmp $74
.text
.global __stack_reg_va
.type __stack_reg_va, @function
__stack_reg_va:
/* Save registers 69-74 explicitly so that we have some
* working registers.
*/
stqd $74, 16*(-1)($sp)
stqd $73, 16*(-2)($sp)
stqd $72, 16*(-3)($sp)
stqd $71, 16*(-4)($sp)
stqd $70, 16*(-5)($sp)
stqd $69, 16*(-6)($sp)
/* Construct self-modifying stack code that saves the remaining
* volatile registers onto the stack.
*/
il regdec, -1 /* for decrement register value in save instruction */
shlqbyi regdec, regdec, 12
il tmp, -(SPE_STACK_REGS+2+3)*16
a code_ptr, $sp, tmp
lqr tmp, save_regs_1 /* store stack code */
stqd tmp, 0(code_ptr)
lqr inst, save_regs_2
ai ptr, $sp, 16*(-6)
sync
bisl link, code_ptr /* branch to the constructed stack code */
/* Adjust pointer so that it points to the first variable
* argument on the stack.
*/
ai offset, parms, -1 /* offset = parms - 1 */
mpyi offset, offset, 16 /* offset = offset * 16 */
a ptr, ptr, offset /* ptr = ptr + offset */
/* Store the va_list to the parameter list.
*/
stqd $sp, 16*(-1)(ptr)
stqd ptr, 16*(-2)(ptr)
/* Make $3 store address.
*/
ai offset, parms, 2 /* offset = parms + 2 */
mpyi offset, offset, -16 /* offset = offset * -16 */
a ptr, ptr, offset /* ptr = ptr + offset */
/* Save all the fixed (non-variable arguments on the stack)
*/
ceqi flag, parms, 0x01 /* if(parms==1) flag=0xFFFFFFFF */
brnz flag, reg_3 /* if(flag!=0) jump */
ceqi flag, parms, 0x02 /* if(parms==2) flag=0xFFFFFFFF */
brnz flag, reg_4 /* if(flag!=0) jump */
stqd $5, 16*2(ptr)
reg_4:
stqd $4, 16*1(ptr)
reg_3:
stqd $3, 0(ptr)
il $3, -16*(SPE_STACK_REGS+2+2)
stqx $sp, $3, $sp /* save back chain */
a $sp, $sp, $3
bi $0 /* return to caller */
/***************************** stack code *********************************************/
/* The following code is copied into the stack for re-entract,
* self-modified, code execution. This code copies the volatile
* registers into a va_list parameter array.
*/
.balignl 16, 0
save_regs_1:
stqd inst, 16(code_ptr) /* store instruction */
sync
a inst, inst, regdec /* decrement register number in the instruction */
ceqbi tmp, inst, 3 /* if (reg-num == 3) tmp = 0x000000FF 000..0 */
save_regs_2:
stqd $68, -16(ptr)
ai ptr, ptr, -16
brz tmp, save_regs_1 /* if (tmp == 0) jump */
bi link /* finish to make va_list */
.size __stack_reg_va, .-__stack_reg_va
|
4ms/metamodule-plugin-sdk
| 4,238
|
plugin-libc/newlib/libc/machine/spu/setjmp.S
|
/*
(C) Copyright IBM Corp. 2005, 2006
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of IBM nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
Author: Andreas Neukoetter (ti95neuk@de.ibm.com)
*/
/*
int setjmp( jmp_buf env );
*/
.text
.align 2
.global setjmp
.type setjmp, @function
setjmp:
stqd $80, 2*16($3)
stqd $81, 3*16($3)
stqd $82, 4*16($3)
stqd $83, 5*16($3)
stqd $84, 6*16($3)
stqd $85, 7*16($3)
stqd $86, 8*16($3)
stqd $87, 9*16($3)
stqd $88, 10*16($3)
stqd $89, 11*16($3)
stqd $90, 12*16($3)
stqd $91, 13*16($3)
stqd $92, 14*16($3)
stqd $93, 15*16($3)
stqd $94, 16*16($3)
stqd $95, 17*16($3)
stqd $96, 18*16($3)
stqd $97, 19*16($3)
stqd $98, 20*16($3)
stqd $99, 21*16($3)
stqd $100, 22*16($3)
stqd $101, 23*16($3)
stqd $102, 24*16($3)
stqd $103, 25*16($3)
stqd $104, 26*16($3)
stqd $105, 27*16($3)
stqd $106, 28*16($3)
stqd $107, 29*16($3)
stqd $108, 30*16($3)
stqd $109, 31*16($3)
stqd $110, 32*16($3)
stqd $111, 33*16($3)
stqd $112, 34*16($3)
stqd $113, 35*16($3)
stqd $114, 36*16($3)
stqd $115, 37*16($3)
stqd $116, 38*16($3)
stqd $117, 39*16($3)
stqd $118, 40*16($3)
stqd $119, 41*16($3)
hbr setjmp_ret, $0
lnop # pipe1 bubble added for instruction fetch
stqd $120, 42*16($3)
stqd $121, 43*16($3)
stqd $122, 44*16($3)
stqd $123, 45*16($3)
stqd $124, 46*16($3)
stqd $125, 47*16($3)
stqd $126, 48*16($3)
stqd $127, 49*16($3)
stqd $0, 0*16($3)
stqd $1, 1*16($3)
il $3, 0
setjmp_ret:
bi $0
.size setjmp, .-setjmp
/*
int longjmp( jmp_buf env, int val );
*/
.text
.align 2
.global longjmp
.type longjmp, @function
longjmp:
lr $127, $1
lqd $0, 0*16($3)
lqd $1, 1*16($3)
sf $126, $127, $1
rotqbyi $126, $126, 12
fsmbi $127, 0x0F00
and $126, $126, $127
a $1, $1, $126
# restore all the non-volatile registers
lqd $80, 2*16($3)
lqd $81, 3*16($3)
lqd $82, 4*16($3)
lqd $83, 5*16($3)
lqd $84, 6*16($3)
lqd $85, 7*16($3)
lqd $86, 8*16($3)
lqd $87, 9*16($3)
lqd $88, 10*16($3)
lqd $89, 11*16($3)
lqd $90, 12*16($3)
lqd $91, 13*16($3)
lqd $92, 14*16($3)
lqd $93, 15*16($3)
lqd $94, 16*16($3)
lqd $95, 17*16($3)
lqd $96, 18*16($3)
lqd $97, 19*16($3)
lqd $98, 20*16($3)
lqd $99, 21*16($3)
lqd $100, 22*16($3)
lqd $101, 23*16($3)
lqd $102, 24*16($3)
lqd $103, 25*16($3)
lqd $104, 26*16($3)
lqd $105, 27*16($3)
lqd $106, 28*16($3)
lqd $107, 29*16($3)
lqd $108, 30*16($3)
lqd $109, 31*16($3)
hbr longjmp_ret, $0
lqd $110, 32*16($3)
lqd $111, 33*16($3)
lqd $112, 34*16($3)
lqd $113, 35*16($3)
lqd $114, 36*16($3)
lqd $115, 37*16($3)
lqd $116, 38*16($3)
lqd $117, 39*16($3)
lqd $118, 40*16($3)
lqd $119, 41*16($3)
lqd $120, 42*16($3)
lqd $121, 43*16($3)
lqd $122, 44*16($3)
lqd $123, 45*16($3)
lqd $124, 46*16($3)
lqd $125, 47*16($3)
ceqi $5, $4, 0
lqd $126, 48*16($3)
lqd $127, 49*16($3)
sf $3, $5, $4
longjmp_ret:
bi $0
.size longjmp, .-longjmp
|
4ms/metamodule-plugin-sdk
| 1,576
|
plugin-libc/newlib/libc/machine/spu/iscanf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#define scanf iscanf
#include "scanf.S"
|
4ms/metamodule-plugin-sdk
| 2,244
|
plugin-libc/newlib/libc/machine/spu/fscanf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#include "c99ppe.h"
.text
.align 4
GLOBL fscanf
.type fscanf, @function
fscanf:
stqd $0, 16($sp) /* save caller address */
il $2, 2 /* number of fixed arguments */
brsl $0, __stack_reg_va /* save register to the stack frame */
brsl $0, __check_init
lqd $3, 16*2($sp) /* $3 <- saved FP on the stack frame */
lqd $2, 0($3) /* FP = fp->_fp */
rotqby $2, $2, $3
stqd $2, 16*2($sp) /* replace FP on the stack frame */
il $3, SPE_C99_SIGNALCODE
il $4, SPE_C99_VFSCANF
ai $5, $sp, 16*2 /* data ($3 save address) */
brsl $0, __send_to_ppe
il $2, 16*(SPE_STACK_REGS+2+2)
a $sp, $sp, $2
lqd $0, 16($sp) /* load caller address */
bi $0 /* return to caller */
.size fscanf, .-fscanf
|
4ms/metamodule-plugin-sdk
| 1,582
|
plugin-libc/newlib/libc/machine/spu/siprintf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#define sprintf siprintf
#include "sprintf.S"
|
4ms/metamodule-plugin-sdk
| 2,055
|
plugin-libc/newlib/libc/machine/spu/sprintf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#include "c99ppe.h"
.text
.align 4
GLOBL sprintf
.type sprintf, @function
sprintf:
stqd $0, 16($sp) /* save caller address */
il $2, 2 /* number of fixed arguments */
brsl $0, __stack_reg_va /* save register to the stack frame */
il $3, SPE_C99_SIGNALCODE
il $4, SPE_C99_VSPRINTF
ai $5, $sp, 16*2 /* data ($3 save address) */
brsl $0, __send_to_ppe
il $2, 16*(SPE_STACK_REGS+2+2)
a $sp, $sp, $2
lqd $0, 16($sp) /* load caller address */
bi $0 /* return to caller */
.size sprintf, .-sprintf
|
4ms/metamodule-plugin-sdk
| 1,579
|
plugin-libc/newlib/libc/machine/spu/iprintf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#define printf iprintf
#include "printf.S"
|
4ms/metamodule-plugin-sdk
| 1,579
|
plugin-libc/newlib/libc/machine/spu/fiscanf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#define fscanf fiscanf
#include "fscanf.S"
|
4ms/metamodule-plugin-sdk
| 1,579
|
plugin-libc/newlib/libc/machine/spu/siscanf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#define sscanf siscanf
#include "sscanf.S"
|
4ms/metamodule-plugin-sdk
| 2,049
|
plugin-libc/newlib/libc/machine/spu/printf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#include "c99ppe.h"
.text
.align 4
GLOBL printf
.type printf, @function
printf:
stqd $0, 16($sp) /* save caller address */
il $2, 1 /* number of fixed arguments */
brsl $0, __stack_reg_va /* save register to the stack frame */
il $3, SPE_C99_SIGNALCODE
il $4, SPE_C99_VPRINTF
ai $5, $sp, 16*2 /* data ($3 save address) */
brsl $0, __send_to_ppe
il $2, 16*(SPE_STACK_REGS+2+2)
a $sp, $sp, $2
lqd $0, 16($sp) /* load caller address */
bi $0 /* return to caller */
.size printf, .-printf
|
4ms/metamodule-plugin-sdk
| 1,582
|
plugin-libc/newlib/libc/machine/spu/fiprintf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#define fprintf fiprintf
#include "fprintf.S"
|
4ms/metamodule-plugin-sdk
| 2,043
|
plugin-libc/newlib/libc/machine/spu/scanf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#include "c99ppe.h"
.text
.align 4
GLOBL scanf
.type scanf, @function
scanf:
stqd $0, 16($sp) /* save caller address */
il $2, 1 /* number of fixed arguments */
brsl $0, __stack_reg_va /* save register to the stack frame */
il $3, SPE_C99_SIGNALCODE
il $4, SPE_C99_VSCANF
ai $5, $sp, 16*2 /* data ($3 save address) */
brsl $0, __send_to_ppe
il $2, 16*(SPE_STACK_REGS+2+2)
a $sp, $sp, $2
lqd $0, 16($sp) /* load caller address */
bi $0 /* return to caller */
.size scanf, .-scanf
|
4ms/metamodule-plugin-sdk
| 2,061
|
plugin-libc/newlib/libc/machine/spu/snprintf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#include "c99ppe.h"
.text
.align 4
GLOBL snprintf
.type snprintf, @function
snprintf:
stqd $0, 16($sp) /* save caller address */
il $2, 3 /* number of fixed arguments */
brsl $0, __stack_reg_va /* save register to the stack frame */
il $3, SPE_C99_SIGNALCODE
il $4, SPE_C99_VSNPRINTF
ai $5, $sp, 16*2 /* data ($3 save address) */
brsl $0, __send_to_ppe
il $2, 16*(SPE_STACK_REGS+2+2)
a $sp, $sp, $2
lqd $0, 16($sp) /* load caller address */
bi $0 /* return to caller */
.size snprintf, .-snprintf
|
4ms/metamodule-plugin-sdk
| 2,049
|
plugin-libc/newlib/libc/machine/spu/sscanf.S
|
/*
Copyright (c) 2007, Toshiba Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the names of Toshiba nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#include "c99ppe.h"
.text
.align 4
GLOBL sscanf
.type sscanf, @function
sscanf:
stqd $0, 16($sp) /* save caller address */
il $2, 2 /* number of fixed arguments */
brsl $0, __stack_reg_va /* save register to the stack frame */
il $3, SPE_C99_SIGNALCODE
il $4, SPE_C99_VSSCANF
ai $5, $sp, 16*2 /* data ($3 save address) */
brsl $0, __send_to_ppe
il $2, 16*(SPE_STACK_REGS+2+2)
a $sp, $sp, $2
lqd $0, 16($sp) /* load caller address */
bi $0 /* return to caller */
.size sscanf, .-sscanf
|
4ms/metamodule-plugin-sdk
| 3,694
|
plugin-libc/newlib/libc/machine/spu/spu-mcount.S
|
/*
(C) Copyright IBM Corp. 2008
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of IBM nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
Author: Ken Werner <ken.werner@de.ibm.com>
*/
/* _mcount extracts the address of the function just entered and the address
of the caller of that function and then calls __mcount_internal. The
prologue calls mcount without saving any registers. The return address is
stored in $75. The _mcount function has to:
- create a new stack frame
- save registers $2 to $75 on the stack
- copy the two addresses ($0 and $75) into the argument registers $3 and $4
- call __mcount_internal
- restore registers
- return to $75 */
/* The following two convenience macros assist in the coding of the
saving and restoring the register.
saveregs first, last Saves registers from first to the last.
restoreregs first, last Restores registers from last down to first.
Note: first must be less than or equal to last. */
.macro saveregs first, last
stqd $\first, \first*16($SP)
.if \last-\first
saveregs "(\first+1)",\last
.endif
.endm
.macro restoreregs first, last
lqd $\last, \last*16($SP)
.if \last-\first
restoreregs \first,"(\last-1)"
.endif
.endm
/* _mcount needs to be resident since the overlay manager uses the scratch
registers too. */
.text
.align 3 /* 8 byte alignment. */
.global _mcount
.type _mcount, @function
_mcount:
stqd $lr, 16($sp) /* Save link register in the callers stack frame. */
stqd $lr, -1216($sp) /* Store back pointer. */
il $lr, -1216 /* Push a new stack frame. */
a $sp, $sp, $lr /* Frame size: 16 * (74 + 2) = 1216. */
/* Save registers $2 to $75 on the stack. */
saveregs 2, 75
/* Bring the __mcount_internal arguments in place. */
lqd $3, 1232($sp) /* frompc (the link register). */
ori $4, $75, 0 /* selfpc (the gcc prologue puts "brsl $75, _mcount" in
front of every function). */
brsl $lr, __mcount_internal
/* Restore register $2 to $75 from the stack. */
restoreregs 2, 75
il $lr, 1216
a $sp, $sp, $lr /* Pop the stack frame. */
lqd $lr, 16($sp) /* Restore link register. */
bi $75 /* Branch to the called function. */
|
4ms/metamodule-plugin-sdk
| 5,119
|
plugin-libc/newlib/libc/machine/sparc/setjmp.S
|
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* Modified for incorporation into newlib by Joel Sherrill
* (joel@OARcorp.com), On-Line Applications Research, 1995.
* Did the following:
* + merged in DEFS.h
* + removed error check since it prevented using this setjmp
* to "context switch"
* + added the support for the "user label" and "register" prefix
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: $Header$
*/
#if defined(LIBC_SCCS) && !defined(lint)
.asciz "@(#)_setjmp.s 8.1 (Berkeley) 6/4/93"
#endif /* LIBC_SCCS and not lint */
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/*********************************************************************
*********************************************************************
* Contents of DEFS.h *
*********************************************************************
*********************************************************************/
#ifdef PROF
#define ENTRY(x) \
.align 4; .globl SYM(x); .proc 1; SYM(x):; .data; .align 4; 1: .long 0; \
.text; save %sp,-96,%sp; sethi %hi(1b),%o0; call mcount; \
or %lo(1b),%o0,%o0; restore
#else
#define ENTRY(x) \
.align 4; .globl SYM(x); .proc 1; SYM(x):
#endif
/*********************************************************************
*********************************************************************
* END of DEFS.h *
*********************************************************************
*********************************************************************/
/*
* C library -- _setjmp, _longjmp
*
* _longjmp(a,v)
* will generate a "return(v?v:1)" from
* the last call to
* _setjmp(a)
* by unwinding the call stack.
* The previous signal state is NOT restored.
*/
/* #include "DEFS.h" */
ENTRY(setjmp)
ENTRY(_setjmp)
st %sp, [%o0] /* caller's stack pointer */
st %i7, [%o0+4] /* caller's return pc */
st %fp, [%o0+8] /* store caller's frame pointer */
st %o7, [%o0+12]
retl
clr %o0 ! return 0
ENTRY(longjmp)
ENTRY(_longjmp)
ta 0x03 /* flush registers */
addcc %o1, %g0, %g1 ! compute v ? v : 1 in a global register
be,a 0f
mov 1, %g1
0:
ld [%o0], %sp /* caller's stack pointer */
ldd [%sp], %l0
ldd [%sp+8], %l2
ldd [%sp+16], %l4
ldd [%sp+24], %l6
ldd [%sp+32], %i0
ldd [%sp+40], %i2
ldd [%sp+48], %i4
ld [%o0+4], %i7 /* caller's return pc */
ld [%o0+8], %fp /* caller's frame pointer */
ld [%o0+12], %o7
jmp %o7 + 8 ! success, return %g1
mov %g1, %o0
|
4ms/metamodule-plugin-sdk
| 1,462
|
plugin-libc/newlib/libc/machine/tic4x/setjmp.S
|
/* setjmp/longjmp routines.
*
* Written by Michael Hayes <m.hayes@elec.canterbury.ac.nz>.
*
* The author hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
.sect .text
.global setjmp
.global longjmp
setjmp:
pop r1
ldi sp, ar0
#ifndef _REGPARM
ldi *ar0, ar2
#endif
sti r4, *ar2++
sti r5, *ar2++
stf r6, *ar2++
stf r7, *ar2++
#ifdef _TMS320C4x
sti r8, *ar2++
#endif
sti ar3, *ar2++
sti ar4, *ar2++
sti ar5, *ar2++
sti ar6, *ar2++
sti ar7, *ar2++
bd r1
sti r1, *ar2++
sti ar0, *ar2
ldi 0, r0
longjmp:
#ifndef _REGPARM
ldi sp, ar0
ldi *-ar0(1), ar2
ldi *-ar0(2), r0
ldiz 1, r0
#else
ldi r2, r0
ldiz 1, r0
#endif
ldi *ar2++, r4
ldi *ar2++, r5
ldf *ar2++, r6
ldf *ar2++, r7
#ifdef _TMS320C4x
ldi *ar2++, r8
#endif
ldi *ar2++, ar3
ldi *ar2++, ar4
ldi *ar2++, ar5
ldi *ar2++, ar6
ldi *ar2++, ar7
ldi *ar2++, r1
ldi *ar2, sp
b r1
.end
|
4ms/metamodule-plugin-sdk
| 2,731
|
plugin-libc/newlib/libc/machine/necv70/fastmath.S
|
.globl _fast_sin
_fast_sin:
fsin.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_sinf
_fast_sinf:
fsin.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_cos
_fast_cos:
fcos.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_cosf
_fast_cosf:
fcos.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_tan
_fast_tan:
ftan.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_tanf
_fast_tanf:
ftan.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_fabs
_fast_fabs:
fabs.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_fabsf
_fast_fabsf:
fabs.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_sqrt
_fast_sqrt:
fsqrt.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_sqrtf
_fast_sqrtf:
fsqrt.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_acos
_fast_acos:
facos.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_acosf
_fast_acosf:
facos.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_asin
_fast_asin:
fasin.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_asinf
_fast_asinf:
fasin.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_atan
_fast_atan:
fatan.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_atanf
_fast_atanf:
fatan.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_cosh
_fast_cosh:
fcosh.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_coshf
_fast_coshf:
fcosh.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_sinh
_fast_sinh:
fsin.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_sinhf
_fast_sinhf:
fsin.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_tanh
_fast_tanh:
ftanh.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_tanhf
_fast_tanhf:
ftanh.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_atanh
_fast_atanh:
fatanh.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_atanhf
_fast_atanhf:
fatanh.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_exp2
_fast_exp2:
fexp2.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_exp2f
_fast_exp2f:
fexp2.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_exp10
_fast_exp10:
fexp10.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_exp10f
_fast_exp10f:
fexp10.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_expe
_fast_expe:
fexpe.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_expef
_fast_expef:
fexpe.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_log2
_fast_log2:
flog2.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_log2f
_fast_log2f:
flog2.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_log10
_fast_log10:
flog10.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_log10f
_fast_log10f:
flog10.s [ap],[ap]
mov.w [ap],r0
ret #0
.globl _fast_loge
_fast_loge:
floge.l [ap],[ap]
mov.d [ap],r0
ret #0
.globl _fast_logef
_fast_logef:
floge.s [ap],[ap]
mov.w [ap],r0
ret #0
|
4ms/metamodule-plugin-sdk
| 1,098
|
plugin-libc/newlib/libc/machine/m88k/setjmp.S
|
/* This is a simple version of setjmp and longjmp.
Ian Lance Taylor, Cygnus Support, 15 July 1993. */
/* We need to save the address of the return instruction, which is in
r1, as well as general register r14 through r25. If we are
compiling for the 88110 with the extended register file, we also
need to save registers x22 through x29. The jmp_buf should be 52
bytes long in the one case, 84 bytes in the other. */
/* int setjmp (jmp_buf); */
globl _setjmp
_setjmp:
st r1,r2,0
st.d r14,r2,4
st.d r16,r2,12
st.d r18,r2,20
st.d r20,r2,28
st.d r22,r2,36
st.d r24,r2,44
#ifdef __m88110__
/* These instructions are just a guess, and gas doesn't
support them anyhow. */
st.d x22,r2,52
st.d x24,r2,60
st.d x26,r2,68
st.d x28,r2,76
#endif
jmp r1
global _longjmp
_longjmp:
ld r1,r2,0
ld.d r14,r2,4
ld.d r16,r2,12
ld.d r18,r2,20
ld.d r20,r2,28
ld.d r22,r2,36
ld.d r24,r2,44
#ifdef __m88110__
/* These instructions are just a guess, and gas doesn't
support them anyhow. */
ld.d x22,r2,52
ld.d x24,r2,60
ld.d x26,r2,68
ld.d x28,r2,76
#endif
jmp r1
|
4ms/metamodule-plugin-sdk
| 1,790
|
plugin-libc/newlib/libc/machine/mn10300/memcpy.S
|
.file "memcpy.S"
.section .text
.global _memcpy
.type _memcpy,@function
_memcpy:
movm [d2,d3,a2,a3],(sp)
.Lend_of_prologue:
mov d0,d2
mov d1,a0
mov d2,a1
mov (28,sp),d1
#ifndef __OPTIMIZE_SIZE__
mov a0,d0
or d2,d0
btst 3,d0
bne .L37
cmp 15,d1
bls .L34
setlb
mov (a0),d0
mov d0,(a1)
inc4 a0
inc4 a1
mov (a0),d0
mov d0,(a1)
inc4 a0
inc4 a1
mov (a0),d0
mov d0,(a1)
inc4 a0
inc4 a1
mov (a0),d0
mov d0,(a1)
inc4 a0
inc4 a1
add -16,d1
cmp 15,d1
lhi
.L34:
cmp 3,d1
bls .L37
setlb
mov (a0),d0
mov d0,(a1)
inc4 a0
inc4 a1
add -4,d1
cmp 3,d1
lhi
.L37:
#endif
cmp 0,d1
beq .L36
setlb
movbu (a0),d0
movbu d0,(a1)
inc a0
inc a1
sub 1,d1
lne
.L36:
mov d2,a0
.Lepilogue:
ret [d2,d3,a2,a3],16
.Lend_of_memcpy:
.size _memcpy, .Lend_of_memcpy - _memcpy
.section .debug_frame,"",@progbits
.Lstart_of_debug_frame:
# Common Information Entry (CIE)
.4byte .Lend_of_CIE - .Lstart_of_CIE # CIE Length
.Lstart_of_CIE:
.4byte 0xffffffff # CIE Identifier Tag
.byte 0x1 # CIE Version
.ascii "\0" # CIE Augmentation
.uleb128 0x1 # CIE Code Alignment Factor
.sleb128 -4 # CIE Data Alignment Factor
.byte 0x32 # CIE RA Column
.byte 0xc # DW_CFA_def_cfa
.uleb128 0x9
.uleb128 0x0
.byte 0xb2 # DW_CFA_offset, column 0x32
.uleb128 0x0
.align 2
.Lend_of_CIE:
# Frame Description Entry (FDE)
.4byte .Lend_of_FDE - .Lstart_of_FDE # FDE Length
.Lstart_of_FDE:
.4byte .Lstart_of_debug_frame # FDE CIE offset
.4byte _memcpy # FDE initial location
.4byte .Lend_of_memcpy - _memcpy # FDE address range
.byte 0x4 # DW_CFA_advance_loc4
.4byte .Lend_of_prologue - _memcpy
.byte 0xe # DW_CFA_def_cfa_offset
.uleb128 0x4
.byte 0x87 # DW_CFA_offset, column 0x7
.uleb128 0x1
.align 2
.Lend_of_FDE:
|
4ms/metamodule-plugin-sdk
| 1,328
|
plugin-libc/newlib/libc/machine/mn10300/setjmp.S
|
.file "setjmp.S"
.section .text
.align 1
.global _setjmp
#ifdef __AM33__
#ifdef __AM33_2__
.am33_2
#else
.am33
#endif
#endif
_setjmp:
mov d0,a0
mov d2,(0,a0)
mov d3,(4,a0)
mov mdr,d1
mov d1,(8,a0)
mov a2,(12,a0)
mov a3,(16,a0)
mov sp,a1
mov a1,(20,a0)
#ifdef __AM33__
add 24,a0
mov r4,(a0+)
mov r5,(a0+)
mov r6,(a0+)
mov r7,(a0+)
#ifdef __AM33_2__
fmov fs4,(a0+)
fmov fs5,(a0+)
fmov fs6,(a0+)
fmov fs7,(a0+)
fmov fs8,(a0+)
fmov fs9,(a0+)
fmov fs10,(a0+)
fmov fs11,(a0+)
fmov fs12,(a0+)
fmov fs13,(a0+)
fmov fs14,(a0+)
fmov fs15,(a0+)
fmov fs16,(a0+)
fmov fs17,(a0+)
fmov fs18,(a0+)
fmov fs19,(a0+)
#endif
#endif
sub d0,d0
rets
.global _longjmp
_longjmp:
mov d0,a0
mov (8,a0),d2
mov d2,mdr
mov (0,a0),d2
mov (4,a0),d3
mov (12,a0),a2
mov (16,a0),a3
mov (20,a0),a1
mov a1,sp
#ifdef __AM33__
add 24,a0
mov (a0+),r4
mov (a0+),r5
mov (a0+),r6
mov (a0+),r7
#ifdef __AM33_2__
fmov (a0+),fs4
fmov (a0+),fs5
fmov (a0+),fs6
fmov (a0+),fs7
fmov (a0+),fs8
fmov (a0+),fs9
fmov (a0+),fs10
fmov (a0+),fs11
fmov (a0+),fs12
fmov (a0+),fs13
fmov (a0+),fs14
fmov (a0+),fs15
fmov (a0+),fs16
fmov (a0+),fs17
fmov (a0+),fs18
fmov (a0+),fs19
#endif
#endif
cmp 0,d1
bne L1
mov 1,d1
L1:
mov d1,d0
retf [],0
|
4ms/metamodule-plugin-sdk
| 1,655
|
plugin-libc/newlib/libc/machine/mn10300/strcpy.S
|
.file "strcpy.S"
.section .text
.global _strcpy
.type _strcpy,@function
_strcpy:
movm [d2,d3,a2,a3],(sp)
.Lend_of_prologue:
mov d0,d3
mov d1,a0
mov d3,a1
mov a0,d0
#ifndef __OPTIMIZE_SIZE__
or d3,d0
btst 3,d0
bne .L2
mov (a0),d0
mov -16843009,a2
mov a2,d1
add d0,d1
not d0
and d0,d1
mov -2139062144,d2
btst -2139062144,d1
bne .L2
setlb
mov (a0),d0
mov d0,(a1)
inc4 a0
inc4 a1
mov (a0),d0
mov a2,d1
add d0,d1
not d0
and d0,d1
and d2,d1
leq
.L2:
#endif
setlb
movbu (a0),d0
movbu d0,(a1)
inc a0
inc a1
cmp 0,d0
lne
mov d3,a0
.Lepilogue:
ret [d2,d3,a2,a3],16
.Lend_of_strcpy:
.size _strcpy, .Lend_of_strcpy - _strcpy
.section .debug_frame,"",@progbits
.Lstart_of_debug_frame:
# Common Information Entry (CIE)
.4byte .Lend_of_CIE - .Lstart_of_CIE # CIE Length
.Lstart_of_CIE:
.4byte 0xffffffff # CIE Identifier Tag
.byte 0x1 # CIE Version
.ascii "\0" # CIE Augmentation
.uleb128 0x1 # CIE Code Alignment Factor
.sleb128 -4 # CIE Data Alignment Factor
.byte 0x32 # CIE RA Column
.byte 0xc # DW_CFA_def_cfa
.uleb128 0x9
.uleb128 0x0
.byte 0xb2 # DW_CFA_offset, column 0x32
.uleb128 0x0
.align 2
.Lend_of_CIE:
# Frame Description Entry (FDE)
.4byte .Lend_of_FDE - .Lstart_of_FDE # FDE Length
.Lstart_of_FDE:
.4byte .Lstart_of_debug_frame # FDE CIE offset
.4byte _strcpy # FDE initial location
.4byte .Lend_of_strcpy - _strcpy # FDE address range
.byte 0x4 # DW_CFA_advance_loc4
.4byte .Lend_of_prologue - _strcpy
.byte 0xe # DW_CFA_def_cfa_offset
.uleb128 0x4
.byte 0x87 # DW_CFA_offset, column 0x7
.uleb128 0x1
.align 2
.Lend_of_FDE:
|
4ms/metamodule-plugin-sdk
| 1,826
|
plugin-libc/newlib/libc/machine/mn10300/memset.S
|
.file "memset.S"
.section .text
.global _memset
.type _memset,@function
_memset:
movm [d2,d3,a2,a3], (sp)
.Lend_of_prologue:
mov d0, d3
mov d1, d2
mov (28, sp),a1
mov d3, a0
#ifndef __OPTIMIZE_SIZE__
cmp 3, a1
bls .L41
btst 3, d3
bne .L41
extbu d2
mov d2, d1
asl 8, d1
or d2, d1
mov d1, d0
asl 16, d0
or d0, d1
cmp 15, a1
bls .L36
setlb
mov d1, (a0)
inc4 a0
mov d1, (a0)
inc4 a0
mov d1, (a0)
inc4 a0
mov d1, (a0)
inc4 a0
add -16, a1
cmp 15, a1
lhi
.L36:
cmp 3, a1
bls .L41
setlb
mov d1, (a0)
inc4 a0
add -4, a1
cmp 3, a1
lhi
.L41:
#endif
cmp 0, a1
beq .Lepilogue
setlb
movbu d2, (a0)
inc a0
sub 1, a1
lne
.Lepilogue:
mov d3,a0
ret [d2,d3,a2,a3], 16
.Lend_of_memset:
.size _memset, .Lend_of_memset - _memset
.section .debug_frame,"",@progbits
.Lstart_of_debug_frame:
# Common Information Entry (CIE)
.4byte .Lend_of_CIE - .Lstart_of_CIE # CIE Length
.Lstart_of_CIE:
.4byte 0xffffffff # CIE Identifier Tag
.byte 0x1 # CIE Version
.ascii "\0" # CIE Augmentation
.uleb128 0x1 # CIE Code Alignment Factor
.sleb128 -4 # CIE Data Alignment Factor
.byte 0x32 # CIE RA Column
.byte 0xc # DW_CFA_def_cfa
.uleb128 0x9
.uleb128 0x0
.byte 0xb2 # DW_CFA_offset, column 0x32
.uleb128 0x0
.align 2
.Lend_of_CIE:
# Frame Description Entry (FDE)
.4byte .Lend_of_FDE - .Lstart_of_FDE # FDE Length
.Lstart_of_FDE:
.4byte .Lstart_of_debug_frame # FDE CIE offset
.4byte _memset # FDE initial location
.4byte .Lend_of_memset - _memset # FDE address range
.byte 0x4 # DW_CFA_advance_loc4
.4byte .Lend_of_prologue - _memset
.byte 0xe # DW_CFA_def_cfa_offset
.uleb128 0x4
.byte 0x87 # DW_CFA_offset, column 0x7
.uleb128 0x1
.align 2
.Lend_of_FDE:
|
4ms/metamodule-plugin-sdk
| 1,863
|
plugin-libc/newlib/libc/machine/mn10300/memchr.S
|
.file "memchr.S"
.section .text
.global _memchr
.type _memchr,@function
_memchr:
movm [d2,d3,a2,a3],(sp)
.Lend_of_prologue:
mov d0,a0
mov d1,d2
mov (28,sp),a1
#ifndef __OPTIMIZE_SIZE__
cmp 3,a1
bls .L44
mov a0,d3
btst 3,d3
bne .L44
mov a0,a2
mov 0,a3
clr d1
setlb
mov a3,d0
asl 8,d0
mov d2,a3
add d0,a3
inc d1
cmp 3,d1
lls
cmp 3,a1
bls .L48
.L33:
mov (a2),d0
mov a3,d3
xor d3,d0
mov d0,d1
not d1
add -16843009,d0
and d1,d0
btst -2139062144,d0
beq .L34
mov a2,a0
clr d1
setlb
movbu (a0),d0
cmp d2,d0
beq .Lepilogue
inc a0
inc d1
cmp 3,d1
lls
.L34:
add -4,a1
inc4 a2
cmp 3,a1
bhi .L33
.L48:
mov a2,a0
.L44:
#endif
cmp 0,a1
beq .L50
setlb
movbu (a0),d0
cmp d2,d0
beq .Lepilogue
inc a0
sub 1,a1
lne
.L50:
mov 0,a0
.Lepilogue:
ret [d2,d3,a2,a3],16
.Lend_of_memchr:
.size _memchr, .Lend_of_memchr - _memchr
.section .debug_frame,"",@progbits
.Lstart_of_debug_frame:
# Common Information Entry (CIE)
.4byte .Lend_of_CIE - .Lstart_of_CIE # CIE Length
.Lstart_of_CIE:
.4byte 0xffffffff # CIE Identifier Tag
.byte 0x1 # CIE Version
.ascii "\0" # CIE Augmentation
.uleb128 0x1 # CIE Code Alignment Factor
.sleb128 -4 # CIE Data Alignment Factor
.byte 0x32 # CIE RA Column
.byte 0xc # DW_CFA_def_cfa
.uleb128 0x9
.uleb128 0x0
.byte 0xb2 # DW_CFA_offset, column 0x32
.uleb128 0x0
.align 2
.Lend_of_CIE:
# Frame Description Entry (FDE)
.4byte .Lend_of_FDE - .Lstart_of_FDE # FDE Length
.Lstart_of_FDE:
.4byte .Lstart_of_debug_frame # FDE CIE offset
.4byte _memchr # FDE initial location
.4byte .Lend_of_memchr - _memchr # FDE address range
.byte 0x4 # DW_CFA_advance_loc4
.4byte .Lend_of_prologue - _memchr
.byte 0xe # DW_CFA_def_cfa_offset
.uleb128 0x4
.byte 0x87 # DW_CFA_offset, column 0x7
.uleb128 0x1
.align 2
.Lend_of_FDE:
|
4ms/metamodule-plugin-sdk
| 1,618
|
plugin-libc/newlib/libc/machine/mn10300/memcmp.S
|
.file "memcmp.S"
.section .text
.global _memcmp
.type _memcmp,@function
_memcmp:
movm [d2,d3,a2,a3],(sp)
.Lend_of_prologue:
mov d0,a0
mov d1,a1
mov (28,sp),a2
#ifndef __OPTIMIZE_SIZE__
cmp 3,a2
bls .L22
mov a1,d2
or d2,d0
btst 3,d0
bne .L22
setlb
mov (a0),d1
mov (a1),d0
cmp d0,d1
bne .L22
inc4 a0
inc4 a1
add -4,a2
cmp 3,a2
lhi
.L22:
#endif
cmp 0,a2
beq .L24
setlb
movbu (a0),d3
movbu (a1),d2
cmp d2,d3
beq .L23
mov d3,d0
sub d2,d0
jmp .Lepilogue
.L23:
inc a0
inc a1
sub 1,a2
lne
.L24:
clr d0
.Lepilogue:
ret [d2,d3,a2,a3],16
.Lend_of_func:
.size _memcmp, .Lend_of_func - _memcmp
.section .debug_frame,"",@progbits
.Lstart_of_debug_frame:
# Common Information Entry (CIE)
.4byte .Lend_of_CIE - .Lstart_of_CIE # CIE Length
.Lstart_of_CIE:
.4byte 0xffffffff # CIE Identifier Tag
.byte 0x1 # CIE Version
.ascii "\0" # CIE Augmentation
.uleb128 0x1 # CIE Code Alignment Factor
.sleb128 -4 # CIE Data Alignment Factor
.byte 0x32 # CIE RA Column
.byte 0xc # DW_CFA_def_cfa
.uleb128 0x9
.uleb128 0x0
.byte 0xb2 # DW_CFA_offset, column 0x32
.uleb128 0x0
.align 2
.Lend_of_CIE:
# Frame Description Entry (FDE)
.4byte .Lend_of_FDE - .Lstart_of_FDE # FDE Length
.Lstart_of_FDE:
.4byte .Lstart_of_debug_frame # FDE CIE offset
.4byte _memcmp # FDE initial location
.4byte .Lend_of_func - _memcmp # FDE address range
.byte 0x4 # DW_CFA_advance_loc4
.4byte .Lend_of_prologue - _memcmp
.byte 0xe # DW_CFA_def_cfa_offset
.uleb128 0x4
.byte 0x87 # DW_CFA_offset, column 0x7
.uleb128 0x1
.align 2
.Lend_of_FDE:
|
4ms/metamodule-plugin-sdk
| 1,592
|
plugin-libc/newlib/libc/machine/mn10300/strlen.S
|
.file "strlen.S"
.section .text
.global _strlen
.type _strlen,@function
_strlen:
movm [d2,d3,a2,a3],(sp)
.Lend_of_prologue:
mov d0,a0
mov a0,a2
#ifndef __OPTIMIZE_SIZE__
btst 3,d0
bne .L21
mov (a0),d0
mov -16843009,a1
mov a1,d1
add d0,d1
not d0
and d0,d1
mov -2139062144,d2
btst -2139062144,d1
bne .L21
setlb
inc4 a0
mov (a0),d0
mov a1,d1
add d0,d1
not d0
and d0,d1
and d2,d1
leq
jmp .L21
#endif
.L19:
inc a0
.L21:
movbu (a0),d3
cmp 0,d3
bne .L19
sub a2,a0
mov a0,d0
.Lepilogue:
ret [d2,d3,a2,a3],16
.Lend_of_strlen:
.size _strlen, .Lend_of_strlen - _strlen
.section .debug_frame,"",@progbits
.Lstart_of_debug_frame:
# Common Information Entry (CIE)
.4byte .Lend_of_CIE - .Lstart_of_CIE # CIE Length
.Lstart_of_CIE:
.4byte 0xffffffff # CIE Identifier Tag
.byte 0x1 # CIE Version
.ascii "\0" # CIE Augmentation
.uleb128 0x1 # CIE Code Alignment Factor
.sleb128 -4 # CIE Data Alignment Factor
.byte 0x32 # CIE RA Column
.byte 0xc # DW_CFA_def_cfa
.uleb128 0x9
.uleb128 0x0
.byte 0xb2 # DW_CFA_offset, column 0x32
.uleb128 0x0
.align 2
.Lend_of_CIE:
# Frame Description Entry (FDE)
.4byte .Lend_of_FDE - .Lstart_of_FDE # FDE Length
.Lstart_of_FDE:
.4byte .Lstart_of_debug_frame # FDE CIE offset
.4byte _strlen # FDE initial location
.4byte .Lend_of_strlen - _strlen # FDE address range
.byte 0x4 # DW_CFA_advance_loc4
.4byte .Lend_of_prologue - _strlen
.byte 0xe # DW_CFA_def_cfa_offset
.uleb128 0x4
.byte 0x87 # DW_CFA_offset, column 0x7
.uleb128 0x1
.align 2
.Lend_of_FDE:
|
4ms/metamodule-plugin-sdk
| 2,065
|
plugin-libc/newlib/libc/machine/mn10300/strchr.S
|
.file "strchr.S"
.section .text
.global _strchr
.type _strchr,@function
_strchr:
movm [d2,d3,a2,a3],(sp)
add -12,sp
.Lend_of_prologue:
mov d0,a1
movbu d1,(7,sp)
#ifndef __OPTIMIZE_SIZE__
btst 3,d0
bne .L20
clr d0
setlb
mov sp,a2
mov d0,d3
add d3,a2
mov a2,a0
add 12,a0
movbu (7,sp),d3
movbu d3,(-4,a0)
inc d0
cmp 3,d0
lls
mov a1,a0
mov -16843009,a1
mov (a0),d2
mov a1,d1
add d2,d1
mov d2,d0
not d0
and d0,d1
mov -2139062144,d3
mov d3,(0,sp)
btst -2139062144,d1
bne .L27
jmp .L38
.L28:
inc4 a0
mov (a0),d2
mov a1,d1
add d2,d1
mov d2,d0
not d0
and d0,d1
mov (0,sp),d3
and d3,d1
bne .L27
.L38:
mov (8,sp),d0
xor d2,d0
mov a1,d1
add d0,d1
not d0
and d0,d1
and d3,d1
beq .L28
.L27:
mov a0,a1
.L20:
#endif
movbu (a1),d0
cmp 0,d0
beq .L32
movbu (7,sp),d1
setlb
cmp d1,d0
beq .L36
inc a1
movbu (a1),d0
cmp 0,d0
lne
.L32:
movbu (7,sp),d0
movbu (a1),d3
cmp d0,d3
beq .L36
mov 0,a0
jmp .Lepilogue
.L36:
mov a1,a0
.Lepilogue:
ret [d2,d3,a2,a3],28
.Lend_of_strchr:
.size _strchr, .Lend_of_strchr - _strchr
.section .debug_frame,"",@progbits
.Lstart_of_debug_frame:
# Common Information Entry (CIE)
.4byte .Lend_of_CIE - .Lstart_of_CIE # CIE Length
.Lstart_of_CIE:
.4byte 0xffffffff # CIE Identifier Tag
.byte 0x1 # CIE Version
.ascii "\0" # CIE Augmentation
.uleb128 0x1 # CIE Code Alignment Factor
.sleb128 -4 # CIE Data Alignment Factor
.byte 0x32 # CIE RA Column
.byte 0xc # DW_CFA_def_cfa
.uleb128 0x9
.uleb128 0x0
.byte 0xb2 # DW_CFA_offset, column 0x32
.uleb128 0x0
.align 2
.Lend_of_CIE:
# Frame Description Entry (FDE)
.4byte .Lend_of_FDE - .Lstart_of_FDE # FDE Length
.Lstart_of_FDE:
.4byte .Lstart_of_debug_frame # FDE CIE offset
.4byte _strchr # FDE initial location
.4byte .Lend_of_strchr - _strchr # FDE address range
.byte 0x4 # DW_CFA_advance_loc4
.4byte .Lend_of_prologue - _strchr
.byte 0xe # DW_CFA_def_cfa_offset
.uleb128 0x4
.byte 0x87 # DW_CFA_offset, column 0x7
.uleb128 0x1
.align 2
.Lend_of_FDE:
|
4ms/metamodule-plugin-sdk
| 1,669
|
plugin-libc/newlib/libc/machine/mn10300/strcmp.S
|
.file "strcmp.S"
.section .text
.global _strcmp
.type _strcmp,@function
_strcmp:
movm [d2,d3,a2,a3],(sp)
.Lend_of_prologue:
mov d0,a0
mov d1,a1
#ifndef __OPTIMIZE_SIZE__
or d1,d0
btst 3,d0
bne .L11
mov (a0),d1
mov (a1),d0
cmp d0,d1
bne .L11
mov -16843009,d3
setlb
mov (a0),d0
mov d3,d1
add d0,d1
not d0
and d0,d1
and -2139062144,d1
beq .L6
clr d0
jmp .Lepilogue
.L6:
inc4 a0
inc4 a1
mov (a0),d1
mov (a1),d0
cmp d0,d1
leq
.L11:
#endif
setlb
movbu (a1),d2
movbu (a0),d0
cmp 0,d0
beq .L9
cmp d2,d0
bne .L9
inc a0
inc a1
lra
.L9:
sub d2,d0
.Lepilogue:
ret [d2,d3,a2,a3],16
.Lend_of_strcmp:
.size _strcmp, .Lend_of_strcmp - _strcmp
.section .debug_frame,"",@progbits
.Lstart_of_debug_frame:
# Common Information Entry (CIE)
.4byte .Lend_of_CIE - .Lstart_of_CIE # CIE Length
.Lstart_of_CIE:
.4byte 0xffffffff # CIE Identifier Tag
.byte 0x1 # CIE Version
.ascii "\0" # CIE Augmentation
.uleb128 0x1 # CIE Code Alignment Factor
.sleb128 -4 # CIE Data Alignment Factor
.byte 0x32 # CIE RA Column
.byte 0xc # DW_CFA_def_cfa
.uleb128 0x9
.uleb128 0x0
.byte 0xb2 # DW_CFA_offset, column 0x32
.uleb128 0x0
.align 2
.Lend_of_CIE:
# Frame Description Entry (FDE)
.4byte .Lend_of_FDE - .Lstart_of_FDE # FDE Length
.Lstart_of_FDE:
.4byte .Lstart_of_debug_frame # FDE CIE offset
.4byte _strcmp # FDE initial location
.4byte .Lend_of_strcmp - _strcmp # FDE address range
.byte 0x4 # DW_CFA_advance_loc4
.4byte .Lend_of_prologue - _strcmp
.byte 0xe # DW_CFA_def_cfa_offset
.uleb128 0x4
.byte 0x87 # DW_CFA_offset, column 0x7
.uleb128 0x1
.align 2
.Lend_of_FDE:
|
4ms/metamodule-plugin-sdk
| 3,291
|
plugin-libc/newlib/libc/machine/h8300/memcpy.S
|
#include "setarch.h"
#include "defines.h"
#ifdef __H8300SX__
.global _memcpy
_memcpy:
stm.l er4-er6,@-er7
; Set up source and destination pointers for movmd.
mov.l er0,er6
mov.l er1,er5
; See whether the copy is long enough to use the movmd.l code.
; Although the code can handle anything longer than 6 bytes,
; it can be more expensive than movmd.b for small moves.
; It's better to use a higher threshold to account for this.
;
; Note that the exact overhead of the movmd.l checks depends on
; the alignments of the length and pointers. They are faster when
; er0 & 3 == er1 & 3 == er2 & 3, faster still when these values
; are 0. This threshold is a compromise between the various cases.
cmp #16,LEN(r2)
blo simple
; movmd.l only works for even addresses. If one of the addresses
; is odd and the other is not, fall back on a simple move.
bld #0,r5l
bxor #0,r6l
bcs simple
; Make the addresses even.
bld #0,r5l
bcc word_aligned
mov.b @er5+,@er6+
sub #1,LEN(r2)
word_aligned:
; See if copying one word would make the first operand longword
; aligned. Although this is only really worthwhile if it aligns
; the second operand as well, it's no worse if doesn't, so it
; hardly seems worth the overhead of a "band" check.
bld #1,r6l
bcc fast_copy
mov.w @er5+,@er6+
sub #2,LEN(r2)
fast_copy:
; Set (e)r4 to the number of longwords to copy.
mov LEN(r2),LEN(r4)
shlr #2,LEN(r4)
#ifdef __NORMAL_MODE__
; 16-bit pointers and size_ts: one movmd.l is enough. This code
; is never reached with r4 == 0.
movmd.l
and.w #3,r2
simple:
mov.w r2,r4
beq quit
movmd.b
quit:
rts/l er4-er6
#else
; Skip the first iteration if the number of longwords is divisible
; by 0x10000.
mov.w r4,r4
beq fast_loop_next
; This loop copies r4 (!= 0) longwords the first time round and 65536
; longwords on each iteration after that.
fast_loop:
movmd.l
fast_loop_next:
sub.w #1,e4
bhs fast_loop
; Mop up any left-over bytes. We could just fall through to the
; simple code after the "and" but the version below is quicker
; and only takes 10 more bytes.
and.w #3,r2
beq quit
mov.w r2,r4
movmd.b
quit:
rts/l er4-er6
simple:
; Simple bytewise copy. We need to handle all lengths, including zero.
mov.w r2,r4
beq simple_loop_next
simple_loop:
movmd.b
simple_loop_next:
sub.w #1,e2
bhs simple_loop
rts/l er4-er6
#endif
#else
.global _memcpy
_memcpy:
; MOVP @(2/4,r7),A0P ; dst
; MOVP @(4/8,r7),A1P ; src
; MOVP @(6/12,r7),A2P ; len
MOVP A0P,A3P ; keep copy of final dst
ADDP A2P,A0P ; point to end of dst
CMPP A0P,A3P ; see if anything to do
beq quit
ADDP A2P,A1P ; point to end of src
; lets see if we can do this in words
or A0L,A2L ; or in the dst address
or A3L,A2L ; or the length
or A1L,A2L ; or the src address
btst #0,A2L ; see if the lsb is zero
bne byteloop
wordloop:
#ifdef __NORMAL_MODE__
sub #2,A1P
#else
subs #2,A1P ; point to word
#endif
mov.w @A1P,A2 ; get word
mov.w A2,@-A0P ; save word
CMPP A0P,A3P ; at the front again ?
bne wordloop
rts
byteloop:
#ifdef __NORMAL_MODE__
sub #1,A1P
#else
subs #1,A1P ; point to byte
#endif
mov.b @A1P,A2L ; get byte
mov.b A2L,@-A0P ; save byte
CMPP A0P,A3P ; at the front again ?
bne byteloop
; return with A0 pointing to dst
quit: rts
#endif
|
4ms/metamodule-plugin-sdk
| 1,037
|
plugin-libc/newlib/libc/machine/h8300/setjmp.S
|
#include "setarch.h"
.file "setjmp.S"
.section .text
.align 2
.global _setjmp
_setjmp:
#if defined(__H8300SX__)
mov.l er7,@er0+
mov.l er6,@er0+
mov.l er5,@er0+
mov.l er4,@er0+
mov.l @sp,@er0
sub.l er0,er0
#elif defined(__H8300H__) || defined(__H8300S__)
mov.l er7,@er0
mov.l er6,@(4,er0)
mov.l er5,@(8,er0)
mov.l er4,@(12,er0)
mov.l @sp,er1
mov.l er1,@(16,er0)
sub.l er0,er0
#else
mov.w r7,@r0
mov.w r6,@(2,r0)
mov.w r5,@(4,r0)
mov.w r4,@(6,r0)
mov.w @sp,r1
mov.w r1,@(8,r0)
sub.w r0,r0
#endif
rts
.global _longjmp
_longjmp:
#if defined(__H8300H__) || defined (__H8300S__) || defined (__H8300SX__)
mov.l @er0+,er7
mov.l @er0+,er6
mov.l @er0+,er5
mov.l @er0+,er4
#if defined(__H8300SX__)
mov.l @er0,@sp
#else
mov.l @er0,er2
mov.l er2,@sp
#endif
#if (__INT_MAX__ <= 32767)
mov.w r1,r0
#else
mov.l er1,er0
#endif
bne .L1
sub er0,er0
adds #1,er0
#else
mov.w @r0+,r7
mov.w @r0+,r6
mov.w @r0+,r5
mov.w @r0+,r4
mov.w @r0,r2
mov.w r2,@sp
mov.w r1,r0
bne .L1
mov.w #1,r0
#endif
.L1:
rts
|
4ms/metamodule-plugin-sdk
| 1,640
|
plugin-libc/newlib/libc/machine/h8300/memset.S
|
#include "setarch.h"
#include "defines.h"
#if defined (__H8300SX__)
.global _memset
_memset:
; Use er3 is a temporary since er0 must remain unchanged on exit.
mov.l er0,er3
; Fill er1 with the byte to copy.
mov.b r1l,r1h
mov.w r1,e1
; Account for any excess bytes and words that will be copied after
; the main loop. r2 >= 0 if there is a longword to copy.
sub #4,LEN(r2)
blo longs_done
; Copy one byte if doing so will make er3 word-aligned.
; This isn't needed for correctness but it makes the main loop
; slightly faster.
bld #0,r3l
bcc word_aligned
mov.b r1l,@er3+
sub #1,LEN(r2)
blo longs_done
word_aligned:
; Likewise one word for longword alignment.
bld #1,r3l
bcc long_copy
mov.w r1,@er3+
sub #2,LEN(r2)
blo longs_done
long_copy:
; Copy longwords.
mov.l er1,@er3+
sub #4,LEN(r2)
bhs long_copy
longs_done:
; At this point, we need to copy r2 & 3 bytes. Copy a word
; if necessary.
bld #1,r2l
bcc words_done
mov.w r1,@er3+
words_done:
; Copy a byte.
bld #0,r2l
bcc bytes_done
mov.b r1l,@er3+
bytes_done:
rts
#else
; A0P pointer to cursor
; A1P thing to copy
.global _memset
_memset:
; MOVP @(2/4,r7),A2P ; dst
; MOVP @(4/8,r7),A1 ; src thing
; MOVP @(6/12,r7),A3P ; len
MOVP A2P,A2P
beq quit
; A3 points to the end of the area
MOVP A0P,A3P
ADDP A2P,A3P
; see if we can do it in words
; by oring in the start of the buffer to the end address
or A0L,A2L
btst #0,A2L
bne byteloop
; we can do it a word at a time
mov.b A1L,A1H
wordloop:
mov.w A1,@-A3P
CMPP A3P,A0P
bne wordloop
quit: rts
byteloop:
mov.b A1L,@-A3P
CMPP A3P,A0P
bne byteloop
rts
#endif
|
4ms/metamodule-plugin-sdk
| 2,731
|
plugin-libc/newlib/libc/machine/nds32/memcpy.S
|
/*
Copyright (c) 2013 Andes Technology Corporation.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Function:
memcpy - copy memory regions
Syntax:
void *memcpy(void *s1, const void *s2, size_t n);
Description:
The memcpy function copies n characters from the object pointed to
by s2 into the object pointed to by s1. If copying takes place
between objects that overlap, the behavior is undefined.
Return value:
The memcpy function returns the value of s1.
*/
.text
.align 2
.globl memcpy
.type memcpy, @function
memcpy:
/* Corner cases. If *s1 equals *s2
or size_t is zero, just go return. */
beq $r0, $r1, .Lend_memcpy
beqz $r2, .Lend_memcpy
/* Keep *s1 as return value.
Set $r3 as how many words to copy.
Set $r2 as how many bytes are less than a word. */
move $r5, $r0
srli $r3, $r2, 2
andi $r2, $r2, 3
beqz $r3, .Lbyte_copy
.Lword_copy:
/* Do the word copy $r3 times. Then, do the byte copy $r2 times. */
lmw.bim $r4, [$r1], $r4, 0
addi $r3, $r3, -1
smw.bim $r4, [$r5], $r4, 0
bnez $r3, .Lword_copy /* Loop again ? */
beqz $r2, .Lend_memcpy /* Fall THRU or go return ? */
.Lbyte_copy:
/* Do the byte copy $r2 times. */
lbi.bi $r4, [$r1], 1
addi $r2, $r2, -1
sbi.bi $r4, [$r5], 1
bnez $r2, .Lbyte_copy /* Loop again ? */
.Lend_memcpy:
ret
.size memcpy, .-memcpy
|
4ms/metamodule-plugin-sdk
| 4,974
|
plugin-libc/newlib/libc/machine/nds32/setjmp.S
|
/*
Copyright (c) 2013 Andes Technology Corporation.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
The setjmp/longjmp for nds32.
The usage of thirty-two 32-bit General Purpose Registers (GPR):
$r28 : $fp
$r29 : $gp
$r30 : $lp
$r31 : $sp
caller-save registers: $r0 ~ $r5, $r16 ~ $r23
callee-save registers: $r6 ~ $r10, $r11 ~ $r14
reserved for assembler : $r15
reserved for other use : $r24, $r25, $r26, $r27
Save all callee-save registers and $fp, $gp, $lp and $sp is enough in theory.
For debugging issue, the layout of jum_buf in here should be in sync with GDB.
The $r16 ~ $r19 are used to store D0/D1, keep them for backward-compatible.
*/
/* int setjmp(jmp_buf env); */
.text
.align 2
.global setjmp
.type setjmp, @function
setjmp:
#if __NDS32_REDUCED_REGS__
smw.bim $r6, [$r0], $r10, #0b0000
addi $r0, $r0, #32 /* Leave room to keep jum_buf all the same. */
smw.bim $r31, [$r0], $r31, #0b1111
#else
smw.bim $r6, [$r0], $r14, #0b0000
smw.bim $r16, [$r0], $r19, #0b1111
#endif
#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__
/* Extract $fpcfg.freg (b[3:2]), then save into jmp_buf. */
fmfcfg $r2
slli $r2, $r2, #28
srli $r2, $r2, #30
swi.bi $r2, [$r0], #4
/* Make sure $r0 is double-word-aligned. */
addi $r0, $r0, #7
bitci $r0, $r0, #7
/* Case switch according to $fpcfg.freg */
beqz $r2, .LCFG0_save /* Branch if $fpcfg.freg = 0b00. */
xori $r15, $r2, #0b10
beqz $r15, .LCFG2_save /* Branch $fpcfg.freg = 0b10. */
srli $r2, $r2, #0b01
beqz $r2, .LCFG1_save /* Branch if $fpcfg.freg = 0b01. */
/* Fall-through if $fpcfg.freg = 0b11. */
.LCFG3_save:
fsdi.bi $fd31, [$r0], #8
fsdi.bi $fd29, [$r0], #8
fsdi.bi $fd27, [$r0], #8
fsdi.bi $fd25, [$r0], #8
fsdi.bi $fd23, [$r0], #8
fsdi.bi $fd21, [$r0], #8
fsdi.bi $fd19, [$r0], #8
fsdi.bi $fd17, [$r0], #8
.LCFG2_save:
fsdi.bi $fd15, [$r0], #8
fsdi.bi $fd13, [$r0], #8
fsdi.bi $fd11, [$r0], #8
fsdi.bi $fd9, [$r0], #8
.LCFG1_save:
fsdi.bi $fd7, [$r0], #8
fsdi.bi $fd5, [$r0], #8
.LCFG0_save:
fsdi.bi $fd3, [$r0], #8
#endif
/* Set return value to zero. */
movi $r0, 0
ret
.size setjmp, .-setjmp
/* void longjmp(jmp_buf env, int val); */
.text
.align 2
.global longjmp
.type longjmp, @function
longjmp:
#if __NDS32_REDUCED_REGS__
lmw.bim $r6, [$r0], $r10, #0b0000
addi $r0, $r0, #32
lmw.bim $r31, [$r0], $r31, #0b1111
#else
lmw.bim $r6, [$r0], $r14, #0b0000
lmw.bim $r16, [$r0], $r19, #0b1111
#endif
#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__
/* Restore value of $fpcfg.freg (b[3:2]). */
lwi.bi $r2, [$r0], #4
/* Make sure $r0 is double-word-aligned. */
addi $r0, $r0, #7
bitci $r0, $r0, #7
/* Case switch according to $fpcfg.freg */
beqz $r2, .LCFG0_restore /* Branch if $fpcfg.freg = 0b00. */
xori $r15, $r2, #0b10
beqz $r15, .LCFG2_restore /* Branch $fpcfg.freg = 0b10. */
srli $r2, $r2, #0b01
beqz $r2, .LCFG1_restore /* Branch if $fpcfg.freg = 0b01. */
/* Fall-through if $fpcfg.freg = 0b11. */
.LCFG3_restore:
fldi.bi $fd31, [$r0], #8
fldi.bi $fd29, [$r0], #8
fldi.bi $fd27, [$r0], #8
fldi.bi $fd25, [$r0], #8
fldi.bi $fd23, [$r0], #8
fldi.bi $fd21, [$r0], #8
fldi.bi $fd19, [$r0], #8
fldi.bi $fd17, [$r0], #8
.LCFG2_restore:
fldi.bi $fd15, [$r0], #8
fldi.bi $fd13, [$r0], #8
fldi.bi $fd11, [$r0], #8
fldi.bi $fd9, [$r0], #8
.LCFG1_restore:
fldi.bi $fd7, [$r0], #8
fldi.bi $fd5, [$r0], #8
.LCFG0_restore:
fldi.bi $fd3, [$r0], #8
#endif
/* Set val as return value. If the value val is 0, 1 will be returned
instead. */
movi $r0, 1
cmovn $r0, $r1, $r1 /* r0=(r1!=0)? r1: r0 */
ret
.size longjmp, .-longjmp
|
4ms/metamodule-plugin-sdk
| 2,863
|
plugin-libc/newlib/libc/machine/nds32/strcpy.S
|
/*
Copyright (c) 2013 Andes Technology Corporation.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Function:
strcpy - copy a string.
Syntax:
char *strcpy(char *dest, const char *src);
Description:
This function copies the string pointed to by src into the array
point to by dest (include the teminating null character).
Return value:
strcpy returns the dest as given.
*/
.text
.align 2
.globl strcpy
.type strcpy, @function
strcpy:
move $r3, $r0 /* Keep r0 as reture value. */
/* If SRC or DEST is unaligned, then copy bytes. */
or $r2, $r1, $r0
andi $r2, $r2, #3
bnez $r2, .Lbyte_mode
.Lword_mode:
/* SRC and DEST are both "long int" aligned, try to do "long int"
sized copies. */
/* #define DETECTNULL(X) (((X) - 0x01010101) & ~(X) & 0x80808080)
DETECTNULL returns nonzero if (long)X contains a NULL byte. */
lwi $r2, [$r1+(0)] /* r2 is X */
sethi $r4, hi20(0xFEFEFEFF)
ori $r4, $r4, lo12(0xFEFEFEFF)
add $r4, $r2, $r4 /* r4 = ((X) - 0x01010101) */
nor $r5, $r2, $r2 /* r5 = ~(X) */
and $r4, $r5, $r4 /* r4 = ~(X) & ((X) - 0x01010101) */
sethi $r5, hi20(0x80808080)
ori $r5, $r5, lo12(0x80808080)
and $r4, $r4, $r5 /* r4 = r4 & 0x80808080 */
bnez $r4, .Lbyte_mode /* Contains a NULL byte. */
swi.bi $r2, [$r3], #4
addi $r1, $r1, #4
b .Lword_mode
.Lbyte_mode:
lbi.bi $r4, [$r1], #1 /* r4 <- *src++ */
sbi.bi $r4, [$r3], #1 /* r4 -> *dest++ */
bnez $r4, .Lbyte_mode
ret
.size strcpy, .-strcpy
|
4ms/metamodule-plugin-sdk
| 3,027
|
plugin-libc/newlib/libc/machine/nds32/memset.S
|
/*
Copyright (c) 2013 Andes Technology Corporation.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Function:
memset - fill memory with a constant byte
Syntax:
void *memset(void *s, int c, size_t n);
Description:
The memset function copies the value of c (converted to an unsigned char)
into each of the first n characters of the object pointed to by s.
Return value:
The memset function returns the value of s.
*/
.text
.align 2
.globl memset
.type memset, @function
memset:
/* Corner case. If n is zero, just go return. */
beqz $r2, .Lend_memset
/* Keep $r0 as return value.
Set $r4 as how many words to copy.
Set $r2 as how many bytes are less than a word. */
move $r5, $r0
srli $r4, $r2, 2
andi $r2, $r2, 3
beqz $r4, .Lbyte_set
/* Set $r1 a word-size pattern composed of the value of c
(converted to an unsigned char). Convert ??????ab to abababab. */
andi $r1, $r1, 0xff /* Set $r1 = 000000ab. */
slli $r3, $r1, 8 /* Set $r3 = 0000ab00. */
or $r1, $r1, $r3 /* Set $r1 = 0000abab. */
slli $r3, $r1, 16 /* Set $r3 = abab0000. */
or $r1, $r1, $r3 /* Set $r1 = abababab. */
.Lword_set:
/* Do the word set $r4 times. Then, do the byte set $r2 times. */
addi $r4, $r4, -1
smw.bim $r1, [$r5], $r1 /* Set a word-size. */
bnez $r4, .Lword_set /* Loop again ? */
beqz $r2, .Lend_memset /* Fall THRU or go return ? */
.Lbyte_set:
/* Do the byte set $r2 times. */
addi $r2, $r2, -1
sbi.p $r1, [$r5], 1 /* Set a byte-size. */
bnez $r2, .Lbyte_set /* Loop again ? */
.Lend_memset:
ret
.size memset, .-memset
|
4ms/metamodule-plugin-sdk
| 3,494
|
plugin-libc/newlib/libc/machine/nds32/strcmp.S
|
/*
Copyright (c) 2013 Andes Technology Corporation.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Function:
strcmp - compare two strings.
Syntax:
int strcmp(const char *s1, const char *s2);
Description:
This function compares the two strings s1 and s2. It returns an
integer less than, equal to, or greater than zero if s1 is found,
respectively, to be less than, to match, or be greater than s2.
Return value:
strcmp returns an integer less than, equal to, or greater than
zero if s1 (or the first n bytes thereof) is found, respectively,
to be less than, to match, or be greater than s2.
*/
.text
.align 2
.globl strcmp
.type strcmp, @function
strcmp:
/* If s1 or s2 are unaligned, then compare bytes. */
or $r5, $r1, $r0
andi $r5, $r5, #3
bnez $r5, .Lbyte_mode
/* If s1 and s2 are word-aligned, compare them a word at a time. */
lwi $r5, [$r0+(0)]
lwi $r3, [$r1+(0)]
bne $r5, $r3, .Lbyte_mode /* A difference was detected, so
search bytewise. */
/* It's more efficient to set bit mask outside the word_mode loop. */
sethi $r4, hi20(0xFEFEFEFF) /* Set $r4 as -0x01010101. */
ori $r4, $r4, lo12(0xFEFEFEFF)
sethi $r2, hi20(0x80808080)
ori $r2, $r2, lo12(0x80808080)
b .Ldetect_null
.align 2
.Lword_mode:
lmw.aim $r5, [$r0], $r5
lmw.aim $r3, [$r1], $r3
bne $r5, $r3, .Lbyte_mode
.Ldetect_null:
/* #define DETECTNULL(X) (((X) - 0x01010101) & ~(X) & 0x80808080)
DETECTNULL returns nonzero if (long)X contains a NULL byte. */
nor $r3, $r5, $r5 /* r3 = ~(X) */
add $r5, $r5, $r4 /* r2 = ((X) - 0x01010101) */
and $r5, $r5, $r3 /* r2 = ~(X) & ((X) - 0x01010101) */
and $r5, $r5, $r2 /* r2= r2 & 0x80808080 */
beqz $r5, .Lword_mode /* No NULL byte, compare next word. */
/* To get here, *a1 == *a2, thus if we find a null in *a1,
then the strings must be equal, so return zero. */
movi $r0, #0
ret
.Lbyte_mode:
/* Byte-mode compare. */
lbi.bi $r5, [$r0], #1
lbi.bi $r3, [$r1], #1
bne $r5, $r3, 1f /* Mismatch, done. */
bnez $r5, .Lbyte_mode
1:
sub $r0, $r5, $r3
ret
.size strcmp, .-strcmp
|
4ms/metamodule-plugin-sdk
| 8,107
|
plugin-libc/newlib/libc/machine/i960/memccpy_ca.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "mccpy_ca.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1989,1993 Intel Corp., all rights reserved
*/
/*
procedure memccpy (optimized assembler version for the 80960CA)
dest_addr = memccpy (dest_addr, src_addr, char, len)
copy len bytes pointed to by src_addr to the space pointed to by
dest_addr, stopping if char is copied. If char is copied,
return address of byte after char in dest string; else null.
Undefined behavior will occur if the end of the source array is in
the last two words of the program's allocated memory space. This
is so because the routine fetches ahead. Disallowing the fetch
ahead would impose a severe performance penalty.
Undefined behavior will also occur if the source and destination
strings overlap.
This program handles five cases:
1) both arguments start on a word boundary
2) neither are word aligned, but they are offset by the same amount
3) source is word aligned, destination is not
4) destination is word aligned, source is not
5) neither is word aligned, and they are offset by differing amounts
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine.
*/
#if __i960_BIG_ENDIAN__
#define MSW g6
#define LSW g7
#else
#define LSW g6
#define MSW g7
#endif
.globl _memccpy
.leafproc _memccpy, __memccpy
.align 2
_memccpy:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__memccpy:
notand g1,3,g5 # extract word addr of start of src
lda (g14),g13 # preserve return address
cmpibge.f 0,g3,Lexit_char_not_found # Lexit if # of bytes to move is <= 0
cmpo g5,g1 # check alignment of src
ld (g5),LSW # fetch word containing at least first byte
notand g0,3,g4 # extract word addr of start of dest
lda 4(g5),g5 # advance src word addr
shlo 24,g2,g2 # reduce char to single byte
bne.f Lcase_245 # branch if src is NOT word aligned
Lcase_13:
cmpobe.t g0,g4,Lcase_1_setup # branch if dest word aligned
Lcase_3: # src is word aligned; dest is not
mov LSW,MSW # make copy of first word of src
addo 4,g4,g1 # move dest word ptr to first word boundary
lda 32,g14 # initialize shift count to zero
Lcase_25:
Lcase_3_cloop_at_start: # character copying loop for start of dest str
cmpdeci 0,g3,g3 # is max_bytes exhausted?
#if __i960_BIG_ENDIAN__
lda -8(g14),g14 # augment the shift counter
#else
lda 8(g14),g14 # augment the shift counter
#endif
be.f Lexit_char_not_found # Lexit if max_bytes is exhausted
#if __i960_BIG_ENDIAN__
rotate 8,MSW,MSW # move next byte into position for extraction
#endif
shlo 24,MSW,g4
stob MSW,(g0) # store the byte in dest
cmpo g4,g2
lda 1(g0),g0 # post-increment dest ptr
#if ! __i960_BIG_ENDIAN__
shro 8,MSW,MSW # move next byte into position for extraction
#endif
be.f Lexit_char_found # Lexit if char found
cmpobne.t g1,g0,Lcase_3_cloop_at_start # branch if reached word boundary
ld (g5),MSW # fetch msw of operand for double shift
Lcase_4:
shro 8,g2,g4
or g4,g2,g1
shro 16,g1,g4
or g4,g1,g4
#if __i960_BIG_ENDIAN__
cmpobne 0,g14,Lcase_3_wloop
Lcase_3_wloop2:
cmpi g3,4 # less than four bytes to move?
lda 4(g5),g5 # post-increment src word addr
mov LSW,g1 # extract 4 bytes of src
bl.f Lcase_13_cloop_setup # branch if < four bytes left to move
scanbyte g4,g1 # branch if word has char in it
bo.f Lcase_13_cloop_setup
mov MSW,LSW # move msw to lsw
ld (g5),MSW # pre-fetch msw of operand for double shift
subi 4,g3,g3 # decrease max_byte count by the 4 bytes moved
st g1,(g0) # store 4 bytes to dest
addo 4,g0,g0 # post-increment dest ptr
b Lcase_3_wloop2
#endif
Lcase_3_wloop:
cmpi g3,4 # less than four bytes to move?
lda 4(g5),g5 # post-increment src word addr
eshro g14,g6,g1 # extract 4 bytes of src
bl.f Lcase_13_cloop_setup # branch if < four bytes left to move
scanbyte g4,g1 # branch if word has char in it
bo.f Lcase_13_cloop_setup
mov MSW,LSW # move msw to lsw
ld (g5),MSW # pre-fetch msw of operand for double shift
subi 4,g3,g3 # decrease max_byte count by the 4 bytes moved
st g1,(g0) # store 4 bytes to dest
addo 4,g0,g0 # post-increment dest ptr
b Lcase_3_wloop
Lcase_1_setup:
subo 4,g0,g0 # store is pre-incrementing; back up dest addr
shro 8,g2,g4
or g4,g2,MSW
shro 16,MSW,g4
or g4,MSW,g4
b Lcase_1
Lcase_1_wloop: # word copying loop
subi 4,g3,g3 # decrease max_byte count by the 4 bytes moved
ld (g5),LSW # pre-fetch next word of src
addo 4,g5,g5 # post-increment src addr
st g1,(g0) # store word in dest string
Lcase_1: # src and dest are word aligned
cmpi g3,4 # check for fewer than four bytes to move
addo 4,g0,g0 # pre-increment dest addr
lda (LSW),g1 # keep a copy of the src word
bl.f Lcase_13_cloop_setup # branch if less than four bytes to copy
scanbyte LSW,g4 # branch if char is not in foursome
bno.t Lcase_1_wloop
Lcase_13_cloop_setup:
cmpibe.f 0,g3,Lexit_char_not_found # Lexit if max_bytes is exhausted
Lcase_1_cloop:
#if __i960_BIG_ENDIAN__
rotate 8,g1,g1 # move next byte into position for extraction
#endif
shlo 24,g1,g4
stob g1,(g0) # store the byte in dest
cmpo g4,g2
lda 1(g0),g0 # post-increment dest byte addr
subi 1,g3,g3
be.f Lexit_char_found # Lexit if char reached
cmpi 0,g3
#if ! __i960_BIG_ENDIAN__
shro 8,g1,g1 # move next byte into position for extraction
#endif
bne.t Lcase_1_cloop # continue if len not exhausted
Lexit_char_not_found:
mov 0,g0
Lexit_char_found:
lda 0,g14
bx (g13) # g0 = dest array address; g14 = 0
Lrett:
ret
Lcase_245:
cmpo g0,g4 # check alignment of dest
ld (g5),MSW # pre-fetch second half
and 3,g1,g1 # compute shift count
shlo 3,g1,g14
#if __i960_BIG_ENDIAN__
subo g14,0,g14 # adjust shift count for big endian
#endif
be.t Lcase_4 # branch if dest is word aligned
or g4,g1,g1 # is src earlier in word, later, or sync w/ dst
cmpo g0,g1 # < indicates first word of dest has more bytes
/* than first word of source. */
eshro g14,g6,g4 # extract four bytes
lda 4(g0),g1 # move dest word addr to first word boundary
#if __i960_BIG_ENDIAN__
bge.f 1f
#else
bg.f 1f
#endif
mov MSW,LSW
lda 4(g5),g5 # move src word addr to second word boundary
1:
notand g1,3,g1
mov g4,MSW
b Lcase_25
/* end of memccpy */
|
4ms/metamodule-plugin-sdk
| 5,853
|
plugin-libc/newlib/libc/machine/i960/memcpy.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "memcpy.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1993 Intel Corp., all rights reserved
*/
/*
procedure memmove (optimized assembler version for the 80960K series)
procedure memcpy (optimized assembler version for the 80960K series)
dest_addr = memmove (dest_addr, src_addr, len)
dest_addr = memcpy (dest_addr, src_addr, len)
copy len bytes pointed to by src_addr to the space pointed to by
dest_addr. Return the original dest_addr.
These routines will work even if the arrays overlap. The standard
requires this of memmove, but memcpy is allowed to fail if overlap
is present. Nevertheless, it is implemented the same as memmove
because the overhead is trifling.
Undefined behavior will occur if the end of the source array is in
the last two words of the program's allocated memory space. This
is so because the routine fetches ahead. Disallowing the fetch
ahead would impose a severe performance penalty.
Strategy:
Fetch the source array by words and store them by words to the
destination array, until there are fewer than three bytes left
to copy. Then, using the last word of the source (the one that
contains the remaining 0, 1, 2, or 3 bytes to be copied), store
a byte at a time until Ldone.
Tactics:
1) Do NOT try to fetch and store the words in a word aligned manner
because, in my judgement, the performance degradation experienced due
to non-aligned accesses does NOT outweigh the time and complexity added
by the preamble and convoluted body that would be necessary to assure
alignment. This is supported by the intuition that most source and
destination arrays (even more true of most big source arrays) will
be word aligned to begin with.
2) For non-overlapping arrays, rather than decrementing len to zero,
I calculate the address of the byte after the last byte of the
destination array, and quit when the destination byte pointer passes
that.
3) For overlapping arrays where the source starts at a lower address
than the destination the move is performed in reverse order.
4) Overlapping arrays where the source starts at a higher address
are treated like non-overlapping case. Where the two arrays exactly
coincide, the routine is short-circuited; no move is Ldone at all.
This costs only one cycle.
*/
.globl _memcpy, _memmove
.globl __memcpy, __memmove
.leafproc _memmove, __memmove
.leafproc _memcpy, __memcpy
.align 2
_memmove:
_memcpy:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__memmove:
__memcpy:
mov g14, g13 # preserve return address
cmpibge 0,g2,Lexit # exit if number of bytes to move is <= zero.
cmpo g0,g1 # does start of dest overlap end of src?
addo g2,g1,g3
be Lexit # no move necessary if src and dest are same
concmpo g3,g0
addo g2, g0, g6
bg Lbackwards # if overlap, then do move backwards
ld (g1), g7 # fetch first word of source
mov g0, g5
b Lwloop_b
Lwloop_a:
ld (g1), g7 # fetch ahead next word of source
st g4, (g5) # store word to dest
addo 4, g5, g5 # post-increment dest pointer
Lwloop_b: # word copying loop
addo 4, g1, g1 # pre-increment src pointer
cmpo g3, g1 # is len <= 3 ?
mov g7, g4 # keep a copy of the current word
bge Lwloop_a # loop if more than 3 bytes to move
cmpobe g6, g5, Lexit # quit if no more bytes to move
Lcloop_a: # character copying loop (len < 3)
stob g4, (g5) # store a byte
shro 8, g4, g4 # position next byte for storing
addo 1, g5, g5
cmpobne g6, g5, Lcloop_a # quit if no more bytes to move
Lexit:
mov 0, g14
bx (g13) # g0 = dest array address; g14 = 0
Lrett:
ret
Lwloop.a:
subo 4, g6, g6 # pre-decrement dest pointer
st g7, (g6) # store word to dest
Lbackwards: # word copying loop
subo 4, g3, g3 # pre-decrement src pointer
cmpo g1, g3 # is len <= 3?
ld (g3), g7 # fetch ahead next word of source
ble Lwloop.a # loop if more than 3 bytes to move
cmpobe g6, g0, Lexit # quit if no more bytes to move
Lcloop.a:
subo 1, g6, g6
rotate 8, g7, g7 # position byte for storing
stob g7, (g6) # store byte
cmpobne g6, g0, Lcloop.a # quit if no more bytes to move
b Lexit
/* end of memmove */
|
4ms/metamodule-plugin-sdk
| 12,226
|
plugin-libc/newlib/libc/machine/i960/memcpy_ca.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "memcp_ca.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1992,1993 Intel Corp., all rights reserved
*/
/*
procedure memmove (optimized assembler version for the CA)
procedure memcpy (optimized assembler version for the CA)
dest_addr = memmove (dest_addr, src_addr, len)
dest_addr = memcpy (dest_addr, src_addr, len)
copy len bytes pointed to by src_addr to the space pointed to by
dest_addr. Return the original dest_addr.
Memcpy will fail if the source and destination string overlap
(in particular, if the end of the source is overlapped by the
beginning of the destination). The behavior is undefined.
This is acceptable according to the draft C standard.
Memmove will not fail if overlap exists.
Undefined behavior will also occur if the end of the source string
(i.e. the terminating null byte) is in the last word of the program's
allocated memory space. This is so because, in several cases, the
routine will fetch ahead one word. Disallowing the fetch ahead would
impose a severe performance penalty.
This program handles five cases:
1) both arguments start on a word boundary
2) neither are word aligned, but they are offset by the same amount
3) source is word aligned, destination is not
4) destination is word aligned, source is not
5) neither is word aligned, and they are offset by differing amounts
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine. The registers are used as follows:
g0 dest ptr; not modified, so that it may be returned
g1 src ptr; shift count
g2 len
g3 src ptr (word aligned)
g4 dest ptr (word aligned)
g5 -4 for Lbackwards move
Little endian
g6 lsw of double word for extraction of 4 bytes
g7 msw of double word for extraction of 4 bytes
Big endian
g6 msw of double word for extraction of 4 bytes
g7 lsw of double word for extraction of 4 bytes
g13 return address
g14 byte extracted.
*/
#if __i960_BIG_ENDIAN__
#define MSW g6
#define LSW g7
#else
#define LSW g6
#define MSW g7
#endif
.globl _memmove, _memcpy
.globl __memmove, __memcpy
.leafproc _memmove, __memmove
.leafproc _memcpy, __memcpy
.align 2
_memcpy:
_memmove:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__memcpy:
__memmove:
cmpibge.f 0,g2,Lquick_exit # Lexit if number of bytes to move is <= zero.
cmpo g0,g1 # if dest starts earlier than src ...
lda (g14),g13 # preserve return address
addo g2,g1,g5 # compute addr of byte after last byte of src
be.f Lexit_code # no move necessary if src and dest are same
concmpo g5,g0 # ... or if dest starts after end of src ...
notand g1,3,g3 # extract word addr of start of src
bg.f Lbackwards # ... then drop thru, else do move backwards
cmpo g3,g1 # check alignment of src
ld (g3),LSW # fetch word containing at least first byte
notand g0,3,g4 # extract word addr of start of dest
lda 4(g3),g3 # advance src word addr
bne.f Lcase_245 # branch if src is NOT word aligned
Lcase_13:
cmpo g0,g4 # check alignment of dest
subo 4,g4,g4 # store is pre-incrementing; back up dest addr
be.t Lcase_1 # branch if dest word aligned
Lcase_3: # src is word aligned; dest is not
addo 8,g4,g4 # move dest word ptr to first word boundary
lda (g0),g1 # copy dest byte ptr
mov LSW,MSW # make copy of first word of src
lda 32,g14 # initialize shift count to zero (mod 32)
Lcase_25:
Lcase_3_cloop_at_start: # character copying loop for start of dest str
cmpdeci 0,g2,g2 # is max_bytes exhausted?
be.f Lexit_code # Lexit if max_bytes is exhausted
#if __i960_BIG_ENDIAN__
rotate 8,MSW,MSW # move next byte into position for extraction
subo 8,g14,g14 # augment the shift counter
stob MSW,(g1) # store the byte in dest
#else
addo 8,g14,g14 # augment the shift counter
stob MSW,(g1) # store the byte in dest
shro 8,MSW,MSW # move next byte into position for extraction
#endif
lda 1(g1),g1 # post-increment dest ptr
cmpobne.t g1,g4,Lcase_3_cloop_at_start # branch if reached word boundary
ld (g3),MSW # fetch msw of operand for double shift
Lcase_4:
Lcase_3_wloop:
cmpi g2,4 # less than four bytes to move?
lda 4(g3),g3 # post-increment src word addr
eshro g14,g6,g1 # extract 4 bytes of src
bl.f Lcase_3_cloop # branch if < four bytes left to move
mov MSW,LSW # move msw to lsw
ld (g3),MSW # pre-fetch msw of operand for double shift
subi 4,g2,g2 # decrease max_byte count by the 4 bytes moved
st g1,(g4) # store 4 bytes to dest
addo 4,g4,g4 # post-increment dest ptr
b Lcase_3_wloop
Lcase_1_wloop: # word copying loop
subi 4,g2,g2 # decrease max_byte count by the 4 bytes moved
ld (g3),LSW # pre-fetch next word of src
addo 4,g3,g3 # post-increment src addr
st g1,(g4) # store word in dest string
Lcase_1: # src and dest are word aligned
cmpi g2,4 # check for fewer than four bytes to move
addo 4,g4,g4 # pre-increment dest addr
lda (LSW),g1 # keep a copy of the src word
bge.t Lcase_1_wloop # branch if at least four bytes to copy
Lcase_3_cloop:
cmpibe.f 0,g2,Lexit_code # Lexit if max_bytes is exhausted
Lcase_1_cloop:
#if __i960_BIG_ENDIAN__
rotate 8,g1,g1 # move next byte into position for extraction
#endif
subi 1,g2,g2
stob g1,(g4) # store the byte in dest
cmpi 0,g2
lda 1(g4),g4 # post-increment dest byte addr
#if ! __i960_BIG_ENDIAN__
shro 8,g1,g1 # move next byte into position for extraction
#endif
bne.t Lcase_1_cloop # Lexit if max_bytes is exhausted
Lexit_code:
mov 0,g14 # conform to register conventions
bx (g13) # g0 = addr of dest; g14 = 0
Lrett:
ret
Lcase_245:
cmpo g0,g4 # check alignment of dest
ld (g3),MSW # pre-fetch second half
and 3,g1,g1 # compute shift count
shlo 3,g1,g14
#if __i960_BIG_ENDIAN__
subo g14,0,g14 # adjust shift count for big endian
#endif
be.t Lcase_4 # branch if dest is word aligned
or g4,g1,g1 # is src earlier in word, later, or sync w/ dst
cmpo g0,g1 # < indicates first word of dest has more bytes
lda 4(g4),g4 # move dest word addr to first word boundary
eshro g14,g6,g5 # extract four bytes
lda (g0),g1
#if __i960_BIG_ENDIAN__
bge.f 1f
#else
bg.f 1f
#endif
mov MSW,LSW
lda 4(g3),g3 # move src word addr to second word boundary
1:
mov g5,MSW
b Lcase_25
Lbackwards:
notand g5,3,MSW # extract word addr of byte after end of src
cmpo MSW,g5 # check alignment of end of src
subo 4,MSW,g3 # retreat src word addr
addo g2,g0,g1 # compute addr of byte after end of dest
notand g1,3,g4 # extract word addr of start of dest
bne.f Lcase.245 # branch if src is NOT word aligned
Lcase.13:
cmpo g1,g4 # check alignment of dest
ld (g3),MSW # fetch last word of src
subo 4,g3,g3 # retreat src word addr
be.t Lcase.1 # branch if dest word aligned
Lcase.3: # src is word aligned; dest is not
mov MSW,LSW # make copy of first word of src
lda 32,g14 # initialize shift count to zero (mod 32)
Lcase.25:
Lcase.3_cloop_at_start: # character copying loop for start of dest str
cmpdeci 0,g2,g2 # is max.bytes exhausted?
be.f Lexit_code # Lexit if max_bytes is exhausted
#if ! __i960_BIG_ENDIAN__
rotate 8,LSW,LSW # move next byte into position for storing
#endif
lda -1(g1),g1 # pre-decrement dest ptr
cmpo g1,g4 # have we reached word boundary in dest yet?
stob LSW,(g1) # store the byte in dest
#if __i960_BIG_ENDIAN__
shro 8,LSW,LSW # move next byte into position for storing
addo 8,g14,g14 # augment the shift counter
#else
subo 8,g14,g14 # augment the shift counter
#endif
bne.t Lcase.3_cloop_at_start # branch if reached word boundary?
ld (g3),LSW # fetch lsw of operand for double shift
#if __i960_BIG_ENDIAN__
cmpobne 0,g14,Lcase.3_wloop
Lcase.3_wloop2:
cmpi g2,4 # less than four bytes to move?
lda -4(g3),g3 # post-decrement src word addr
mov MSW,g1 # extract 4 bytes of src
lda (LSW),MSW # move lsw to msw
subo 4,g4,g4 # pre-decrement dest ptr
bl.f Lcase.3_cloop # branch if < four bytes left to move
ld (g3),LSW # pre-fetch lsw of operand for double shift
subi 4,g2,g2 # decrease max.byte count by the 4 bytes moved
st g1,(g4) # store 4 bytes to dest
b Lcase.3_wloop2
#endif
Lcase.4:
Lcase.3_wloop:
cmpi g2,4 # less than four bytes to move?
lda -4(g3),g3 # post-decrement src word addr
eshro g14,g6,g1 # extract 4 bytes of src
lda (LSW),MSW # move lsw to msw
subo 4,g4,g4 # pre-decrement dest ptr
bl.f Lcase.3_cloop # branch if < four bytes left to move
ld (g3),LSW # pre-fetch lsw of operand for double shift
subi 4,g2,g2 # decrease max.byte count by the 4 bytes moved
st g1,(g4) # store 4 bytes to dest
b Lcase.3_wloop
Lcase.1_wloop: # word copying loop
subi 4,g2,g2 # decrease max.byte count by the 4 bytes moved
ld (g3),MSW # pre-fetch next word of src
subo 4,g3,g3 # post-decrement src addr
st g1,(g4) # store word in dest string
Lcase.1: # src and dest are word aligned
cmpi g2,4 # check for fewer than four bytes to move
subo 4,g4,g4 # pre-decrement dest addr
lda (MSW),g1 # keep a copy of the src word
bge.t Lcase.1_wloop # branch if at least four bytes to copy
Lcase.3_cloop:
cmpibe.f 0,g2,Lexit_code # Lexit if max_bytes is exhausted
#if ! __i960_BIG_ENDIAN__
rotate 8,g1,g1 # move next byte into position for storing
#endif
lda 4(g4),g4 # pre-decremented dest addr 4 too much
Lcase.1_cloop:
subi 1,g4,g4 # pre-decrement dest byte addr
cmpi g4,g0 # has dest ptr reached beginning of dest?
stob g1,(g4) # store the byte in dest
#if __i960_BIG_ENDIAN__
shro 8,g1,g1 # move next byte into position for storing
#else
rotate 8,g1,g1 # move next byte into position for storing
#endif
bne.t Lcase.1_cloop # Lexit if move is completed
b Lexit_code
Lcase.245:
cmpo g1,g4 # check alignment of dest
ld (MSW),MSW # pre-fetch word with at least last byte
and 3,g5,g5 # compute shift count
ld (g3),LSW # pre-fetch second to last word
shlo 3,g5,g14
#if __i960_BIG_ENDIAN__
subo g14,0,g14 # adjust shift count for big endian
#endif
be.t Lcase.4 # branch if dest is word aligned
or g4,g5,g5 # is src earlier in word, later, or sync w/ dst
cmpo g1,g5 # < indicates last word of dest has less bytes
eshro g14,g6,g5 # extract four bytes
bl.t 1f
mov LSW,MSW
#if ! __i960_BIG_ENDIAN__
be.t 1f
#endif
subo 4,g3,g3 # move src word addr to second word boundary
1:
mov g5,LSW
b Lcase.25
Lquick_exit:
mov g14,g13
b Lexit_code
/* end of memmove */
|
4ms/metamodule-plugin-sdk
| 3,435
|
plugin-libc/newlib/libc/machine/i960/strpbrk.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
/*
* (c) copyright 1989,1993 Intel Corp., all rights reserved
*/
/*
procedure strpbrk (optimized assembler version: 80960K series, 80960CA)
char_addr = strpbrk (string, brkset_string)
Return the address of the first character in string that is NOT
in the brkset_string. Return NULL if none exists.
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine.
This routine stays out of g3 and g4 altogether. They may be used by
the strtok routine, which calls this routine in an incestuous way.
*/
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
.file "strprk.s"
.globl _strpbrk
.globl __strpbrk
.leafproc _strpbrk, __strpbrk
.align 2
_strpbrk:
#ifdef __PIC
lda Lrett-(.+8)(ip),g14
b __strpbrk
#else
lda Lrett,g14
b __strpbrk
#endif
Lrett: ret
__strpbrk:
Lnext_char_strpbrk:
addo 1,g1,g2 # g2 will be the brkset ptr
ldob (g0),g7 # fetch next character of string
ldob (g1),g6 # fetch first character of brkset
cmpobe.f 0,g7,Lexit_char_not_found # quit if at end of string
Lscan_set_strpbrk:
cmpo g6,g7 # is brkset char equal to string char?
ldob (g2),g5 # fetch next brkset char
addo 1,g2,g2 # bump brkset ptr
be.f Lexit_char_found
cmpo g6,0 # is brkset_string exhausted?
lda (g5),g6
bne.t Lscan_set_strpbrk # check next character of brkset
addo 1,g0,g0 # check next character of string
b Lnext_char_strpbrk
Lexit_char_not_found:
mov 0,g0 # return null if brkset char not found in string
Lexit_char_found:
mov g14,g13 # save return address
lda 0,g14 # conform to register conventions
bx (g13)
/* end of strpbrk */
|
4ms/metamodule-plugin-sdk
| 6,881
|
plugin-libc/newlib/libc/machine/i960/memcmp_ca.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "memcm_ca.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1992,1993 Intel Corp., all rights reserved
*/
/*
procedure memcmp (optimized assembler version for the CA)
result = memcmp (src1_addr, src2_addr, max_bytes)
compare the byte array pointed to by src1_addr to the byte array
pointed to by src2_addr. Return 0 iff the arrays are equal, -1 if
src1_addr is lexicly less than src2_addr, and 1 if it is lexicly
greater. Do not compare more than max_bytes bytes.
Undefined behavior will occur if the end of either source array
is in the last word of the program's allocated memory space. This
is so because, in several cases, memcmp will fetch ahead one word.
Disallowing the fetch ahead would impose a severe performance penalty.
This program handles five cases:
1) both arguments start on a word boundary
2) neither are word aligned, but they are offset by the same amount
3) source1 is word aligned, source2 is not
4) source2 is word aligned, source1 is not
5) neither is word aligned, and they are offset by differing amounts
At the time of this writing, only g0 thru g7 and g14 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers are sufficient to implement the routine.
The registers are used as follows:
g0 original src1 ptr; extracted word; return result
g1 src2 ptr; byt extraction mask
g2 maximum number of bytes to compare
g3 src2 word ptr
Little endian
g4 lsw of src1
g5 msw of src1
g6 src2 word
g7 src1 word ptr
Big endian
g4 msw of src1
g5 lsw of src1
g6 src1 word ptr
g7 src2 word
g13 return address
g14 shift count
*/
#if __i960_BIG_ENDIAN__
#define MSW g4
#define LSW g5
#define SRC1 g6
#define SRC2 g7
#else
#define LSW g4
#define MSW g5
#define SRC2 g6
#define SRC1 g7
#endif
.globl _memcmp
.globl __memcmp
.leafproc _memcmp, __memcmp
.align 2
_memcmp:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__memcmp:
Lrestart:
#if __i960_BIG_ENDIAN__
subo 1,g0,SRC1
notand SRC1,3,SRC1 # extract word addr of start of src1
#else
notand g0,3,SRC1 # extract word addr of start of src1
#endif
lda (g14),g13 # preserve return address
cmpibge.f 0,g2,Lequal_exit # return equality if number bytes 0
notand g1,3,g3 # extract word addr of start of src2
ld (SRC1),LSW # fetch word with at least first byte of src1
cmpo g3,g1 # check alignment of src2
ld 4(SRC1),MSW # fetch second word of src1
shlo 3,g0,g14 # compute shift count for src1
#if __i960_BIG_ENDIAN__
subo g14,0,g14 # adjust shift count for big endian.
#endif
ld (g3),SRC2 # fetch word with at least first byte of src2
eshro g14,g4,LSW # extract word of src1
lda 8(SRC1),SRC1 # advance src1 word addr
bne.f Lsrc2_unaligned # branch if src2 is NOT word aligned
mov LSW,g0 # at least src2 is word aligned
lda 0xff,g1
Lwloop: # word comparing loop
cmpo SRC2,g0 # compare src1 and src2 words
lda 4(g3),g3 # pre-increment src2 addr
mov MSW,LSW # move msw of src1 to lsw
ld (SRC1),MSW # pre-fetch next msw of src1
subi 4,g2,g2 # decrement maximum byte count
bne.f Lcloop # branch if src1 and src2 unequal
cmpi 0,g2
ld (g3),SRC2 # pre-fetch next word of src2
eshro g14,g4,g0 # extract word of src1
lda 4(SRC1),SRC1 # post-increment src1 addr
bl.t Lwloop # branch if max_bytes not reached yet
b Lequal_exit # strings were equal up through max_bytes
Lcloop_setup: # setup for coming from Lsrc2_unaligned
mov LSW,g0 # restore extracted src1 word
subo 4,g2,g2 # make up for later re-incrementing
lda 0xff,g1 # byte extraction mask
Lcloop: # character comparing loop
#if __i960_BIG_ENDIAN__
rotate 24,g1,g1 # shift mask for next byte
#endif
and SRC2,g1,g3 # extract next char of src2
and g0,g1,LSW # extract next char of src1
cmpobne.f LSW,g3,.diff # check for equality
#if ! __i960_BIG_ENDIAN__
shlo 8,g1,g1 # shift mask for next byte
#endif
subi 1,g2,g2 # decrement character counter
b Lcloop # branch if null not reached
Lequal_exit: # words are equal up thru null byte
mov 0,g14 # conform to register conventions
lda 0,g0 # return zero, indicating equality
bx (g13) # return
Lrett:
ret
.diff:
addo 4,g2,g2 # to make up for extra decrement in loop
lda 0,g14
bl Lless_than_exit
Lgreater_than_exit:
cmpibge.f 0,g2,Lequal_exit # branch if difference is beyond max_bytes
mov 1,g0
bx (g13) # g0 = 1 (src1 > src2)
Lless_than_exit:
cmpibge.f 0,g2,Lequal_exit # branch if difference is beyond max_bytes
subi 1,0,g0
bx (g13) # g0 = -1 (src1 < src2)
Lsrc2_unaligned:
notor g1,3,g14 # first step in computing new src1 ptr
ld 4(g3),SRC1 # fetch second word of src2
shlo 3,g1,MSW # compute shift count for src2
#if __i960_BIG_ENDIAN__
subo MSW,0,MSW
#endif
eshro MSW,g6,SRC2 # extract word of src2
cmpo LSW,SRC2 # compare src1 and src2 words
lda 4(g3),g1 # set new src2 ptr
bne.f Lcloop_setup # first four bytes differ
subo g14,g0,g0 # second (final) step in computing new src1 ptr
addi g14,g2,g2 # compute new max_bytes too
lda (g13),g14 # prepare return pointer for Lrestart
b Lrestart # continue with both string fetches shifted
|
4ms/metamodule-plugin-sdk
| 5,781
|
plugin-libc/newlib/libc/machine/i960/strncat.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "strncat.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1993 Intel Corp., all rights reserved
*/
/*
procedure strncat (optimized assembler version for the 80960K Series)
dest_addr = strncat (dest_addr, src_addr, max_bytes)
append the null terminated string pointed to by src_addr to the null
terminated string pointed to by dest_addr. Return the original
dest_addr. If the source string is longer than max_bytes, then
append only max_bytes bytes, and tack on a null byte on the end.
This routine will fail if the source and destination string
overlap (in particular, if the end of the source is overlapped
by the beginning of the destination). The behavior is undefined.
This is acceptable according to the draft C standard.
Undefined behavior will also occur if the end of the source string
(i.e. the terminating null byte) is in the last two words of the
program's allocated memory space. This is so because strncat fetches
ahead. Disallowing the fetch ahead would impose a severe performance
penalty.
Strategy:
First, skip to the null byte in the destination string. Then
fetch the source string by words and store them by words to the
destination string, until there are fewer than three bytes left
to copy. Then, using the last word of the source (the one that
contains the remaining 0, 1, 2, or 3 bytes to be copied), store
a byte at a time until Ldone.
If, before exhausting the max_byte count, the null byte is encountered
in the source string, then just copy up thru the null byte.
Tactics:
1) Do NOT try to fetch and store the words in a word aligned manner
because, in my judgement, the performance degradation experienced due
to non-aligned accesses does NOT outweigh the time and complexity added
by the preamble and convoluted body that would be necessary to assure
alignment.
*/
.globl _strncat
.globl __strncat
.leafproc _strncat,__strncat
.align 2
_strncat:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__strncat:
mov g14,g6
cmpibge 0, g2, Lno_operation # Lexit early if max_bytes <= 0
mov g0, g5
Lskip_word_loop:
ld (g5), g7 # fetch word of dest string
addo 4, g5, g5 # post-increment dest ptr
scanbyte 0, g7 # does it contain null byte?
bno Lskip_word_loop # if not, loop
subo 5, g5, g5 # adjust dest ptr
lda 0xff, g3 # byte extraction mask = 0xff;
Lskip_byte_loop:
and g7, g3, g14 # extract byte of last word of dest string
cmpo 0, g14 # is it null?
addo 1, g5, g5 # adjust dest ptr
shro 8, g7, g7 # position next byte for extraction
bne Lskip_byte_loop # loop if null not found yet
ld (g1), g7 # fetch first word of source string
Lwloop: # word copying loop
cmpo 4, g2 # max_bytes < 4 ?
addo 4, g1, g1 # post-increment source ptr
bge Lcloop.a # branch if less than 4 bytes to move
scanbyte 0, g7 # is null byte reached yet?
mov g7, g4 # keep a copy of the source word
be Lcloop # branch if null byte reached
ld (g1), g7 # pre-fetch next word of source
subo 4, g2, g2 # reduce max_byte counter
st g4, (g5) # store current word
addo 4, g5, g5 # post-increment destination ptr
b Lwloop
Lcloop.b:
addo 1, g5, g5 # post-increment destination ptr
shro 8, g7, g7 # position next byte for extraction
Lcloop: # character copying loop (max_byte > 3)
and g3, g7, g4 # extract character
cmpo 0, g4 # is it null?
stob g4, (g5) # store it
bne Lcloop.b # loop if null not encountered yet
bx (g6) # g0 = dest string address; g14 = 0
Lrett:
ret
Lcloop.c:
addo 1, g5, g5 # post-increment destination ptr
shro 8, g7, g7 # position next byte for extraction
Lcloop.a: # character copying loop (max_byte <= 3)
cmpdeco 0,g2,g2 # max_byte == 0?
and g3, g7, g4 # extract character
be Ldone # store null and Lexit if max_byte exhausted
cmpo 0, g4 # is it null?
stob g4, (g5) # store it
bne Lcloop.c # loop if null not encountered yet
Ldone: stob g14, (g5) # store trailing null
bx (g6) # g0 = dest string address; g14 = 0
Lno_operation: mov 0, g14 # conform to register conventions
bx (g6)
/* end of strncat */
|
4ms/metamodule-plugin-sdk
| 3,917
|
plugin-libc/newlib/libc/machine/i960/setjmp.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
/******************************************************************************/
/* */
/* setjmp(), longjmp() */
/* */
/******************************************************************************/
.file "setjmp.as"
.text
/* .link_pix */
.align 4
.globl _setjmp
_setjmp:
flushreg
andnot 0xf,pfp,g1 /* get pfp, mask out return status bits */
st g1, 0x58(g0) /* save fp of caller*/
/* save globals not killed by the calling convention */
stq g8, 0x40(g0) /* save g8-g11*/
st g12, 0x50(g0) /* save g12*/
st g14, 0x54(g0) /* save g14*/
/* save previous frame local registers */
ldq (g1), g4 /* get previous frame pfp, sp, rip, r3 */
stq g4, (g0) /* save pfp, sp, rip, r3 */
ldq 0x10(g1), g4 /* get previous frame r4-r7 */
stq g4, 0x10(g0) /* save r4-r7 */
ldq 0x20(g1), g4 /* get previous frame r8-r11 */
stq g4, 0x20(g0) /* save r8-r11 */
ldq 0x30(g1), g4 /* get previous frame r12-r15 */
stq g4, 0x30(g0) /* save r12-r15 */
mov 0, g0 /* return 0 */
ret
/*
* fake a return to the place that called the corresponding _setjmp
*/
.align 4
.globl _longjmp
_longjmp:
call 0f /* ensure there is at least one stack frame */
0:
flushreg /* do this before swapping stack */
ld 0x58(g0), pfp /* get fp of caller of setjmp */
/* restore local registers
* the following code modifies the frame of the function which originally
* called setjmp.
*/
ldq (g0), g4 /* get pfp, sp, rip, r3 */
stq g4, (pfp) /* restore pfp, sp, rip, r3 */
ldq 0x10(g0), g4 /* get r4-r7 */
stq g4, 0x10(pfp) /* restore r4-r7 */
ldq 0x20(g0), g4 /* get r8-r11 */
stq g4, 0x20(pfp) /* restore r8-r11 */
ldq 0x30(g0), g4 /* get r12-r15 */
stq g4, 0x30(pfp) /* restore r12-r15 */
/* restore global registers */
ldq 0x40(g0), g8 /* get old g8-g11 values */
ld 0x50(g0), g12 /* get old g12 value */
ld 0x54(g0), g14 /* get old g14 value */
mov g1, g0 /* get return value */
cmpo g0, 0 /* make sure it is not zero */
bne 0f
mov 1, g0 /* return 1 by default */
0:
ret /* return to caller of _setjmp */
|
4ms/metamodule-plugin-sdk
| 6,476
|
plugin-libc/newlib/libc/machine/i960/strcpy.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "strcpy.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1993 Intel Corp., all rights reserved
*/
/*
procedure strcpy (optimized assembler version for the 80960K series)
procedure strcat (optimized assembler version for the 80960K series)
dest_addr = strcpy (dest_addr, src_addr)
copy the null terminated string pointed to by src_addr to
the string space pointed to by dest_addr. Return the original
dest_addr.
This routine will fail if the source and destination string
overlap (in particular, if the end of the source is overlapped
by the beginning of the destination). The behavior is undefined.
This is acceptable according to the draft C standard.
Undefined behavior will also occur if the end of the source string
(i.e. the terminating null byte) is in the last two words of the
program's allocated memory space. This is so because strcpy fetches
ahead. Disallowing the fetch ahead would impose a severe performance
penalty.
Strategy:
Fetch the source string and store the destination string by words
until the null byte is encountered. When the word with the null
byte is reached, store it by bytes up through the null byte only.
Tactics:
1) Do NOT try to fetch and store the words in a word aligned manner
because, in my judgement, the performance degradation experienced due
to non-aligned accesses does NOT outweigh the time and complexity added
by the preamble and convoluted body that would be necessary to assure
alignment. This is supported by the intuition that most source and
destination strings will be word aligned to begin with.
procedure strcat
dest_addr = strcat (dest_addr, src_addr)
Appends the string pointed to by src_addr to the string pointed
to by dest_addr. The first character of the source string is
copied to the location initially occupied by the trailing null
byte of the destination string. Thereafter, characters are copied
from the source to the destination up thru the null byte that
trails the source string.
See the strcpy routine, above, for its caveats, as they apply here too.
Strategy:
Skip to the end (null byte) of the destination string, and then drop
into the strcpy code.
Tactics:
Skipping to the null byte is Ldone by reading the destination string
in long-words and scanbyte'ing them, then examining the bytes of the
word that contains the null byte, until the address of the null byte is
known. Then we drop into the strcpy routine. It is probable (approx.
three out of four times) that the destination string as strcpy sees
it will NOT be word aligned (i.e. that the null byte won't be the
last byte of a word). But it is not worth the complication to that
routine to force word aligned memory accesses to be gaurenteed.
*/
.globl _strcpy, _strcat
.globl __strcpy, __strcat
.leafproc _strcpy,__strcpy
.leafproc _strcat,__strcat
.align 2
_strcat:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__strcat:
mov g14,g13 # preserve return address
ldl (g0),g4 # fetch first two words
addo 8,g0,g2 # post-increment src word pointer
lda 0xff,g3 # byte extraction mask
Lsearch_for_word_with_null_byte:
scanbyte 0,g4 # check for null byte
mov g5,g7 # copy second word
bo.f Lsearch_for_null # branch if null found
scanbyte 0,g7 # check for null byte
ldl (g2),g4 # fetch next pair of word of src
addo 8,g2,g2 # post-increment src word pointer
bno Lsearch_for_word_with_null_byte # branch if null not found yet
subo 4,g2,g2 # back up the byte pointer
mov g7,g4 # move word with null to search word
Lsearch_for_null:
subo 9,g2,g5 # back up the byte pointer
Lsearch_for_null.a:
and g4,g3,g6 # extract byte
cmpo 0,g6 # is it null?
addo 1,g5,g5 # bump src byte ptr
shro 8,g4,g4 # shift word to position next byte
bne Lsearch_for_null.a
b Lend_of_dest_found
_strcpy:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__strcpy:
mov g0, g5
Lend_of_dest_found:
ld (g1), g2 # fetch first word of source
mov g14,g6 # preserve return address
lda 0xff, g3 # byte extraction mask = 0xff;
Lwloop: # word copying loop
addo 4, g1, g1 # post-increment source ptr
scanbyte 0, g2 # does source word contain null byte?
mov g2, g4 # save a copy of the source word
be Lcloop # branch if null present
ld (g1), g2 # pre-fetch next word of source
st g4, (g5) # store current word
addo 4, g5, g5 # post-increment dest ptr
b Lwloop
Lcloop: # character copying loop
and g3, g4, g14 # extract next char
shro 8, g4, g4 # position word for next byte extraction
cmpo 0, g14 # is it null?
stob g14, (g5) # store the byte
addo 1, g5, g5 # post-increment dest ptr
bne Lcloop # quit if null encountered
bx (g6) # g0 = dest string address; g14 = 0
Lrett:
ret
|
4ms/metamodule-plugin-sdk
| 3,179
|
plugin-libc/newlib/libc/machine/i960/strcspn.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "strcspn.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1989,1993 Intel Corp., all rights reserved
*/
/*
procedure strcspn (optimized assembler version: 80960K series, 80960CA)
len = strcspn (string, charset)
Return the number of characters in the maximum leading segment
of string which consists solely of characters NOT from charset.
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine.
*/
.globl _strcspn
.globl __strcspn
.leafproc _strcspn, __strcspn
.align 2
_strcspn:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__strcspn:
mov g14,g13 # save return address
lda (g0),g3 # copy string pointer
mov 0,g14 # conform to register conventions
Lnext_char:
ldob (g3),g7 # fetch next character of string
addo 1,g1,g2 # g2 will be the charset ptr
ldob (g1),g6 # fetch first character of charset
cmpobe.f 0,g7,Lexit # quit if at end of string
Lscan_set:
cmpo g6,g7 # is charset char same as string char?
ldob (g2),g5 # fetch next charset char
addo 1,g2,g2 # bump charset ptr
be.f Lexit
cmpo g6,0 # is charset exhausted?
lda (g5),g6
bne.t Lscan_set # check next character of charset
addo 1,g3,g3 # check next character of string
b Lnext_char
Lexit:
subo g0,g3,g0 # compute string length
bx (g13)
Lrett:
ret
/* end of strcspn */
|
4ms/metamodule-plugin-sdk
| 9,947
|
plugin-libc/newlib/libc/machine/i960/strcpy_ca.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "strcp_ca.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1993 Intel Corp., all rights reserved
*/
/*
procedure strcpy (optimized assembler version for the CA)
dest_addr = strcpy (dest_addr, src_addr)
copy the null terminated string pointed to by src_addr to
the string space pointed to by dest_addr. Return the original
dest_addr.
This routine will fail if the source and destination string
overlap (in particular, if the end of the source is overlapped
by the beginning of the destination). The behavior is undefined.
This is acceptable according to the draft C standard.
Undefined behavior will also occur if the end of the source string
(i.e. the terminating null byte) is in the last word of the program's
allocated memory space. This is so because, in several cases, strcpy
will fetch ahead one word. Disallowing the fetch ahead would impose
a severe performance penalty.
This program handles five cases:
1) both arguments start on a word boundary
2) neither are word aligned, but they are offset by the same amount
3) source is word aligned, destination is not
4) destination is word aligned, source is not
5) neither is word aligned, and they are offset by differing amounts
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine. The registers are used as follows:
g0 original dest ptr; not modified, so that it may be returned.
g1 src ptr; shift count
g2 dest ptr; 4 bytes of src
g3 src ptr (word aligned)
g4 dest ptr (word aligned)
g5 0xff -- byte extraction mask
g6 lsw of double word for extraction of 4 bytes (little endian)
msw of double word for extraction of 4 bytes (big endian)
g7 msw of double word for extraction of 4 bytes (little endian)
lsw of double word for extraction of 4 bytes (big endian)
g13 return address
g14 byte extracted. When reaches null byte, which is zero, we will
be in conformance with register conventions, and can return to
the caller with a clear conscience.
procedure strcat
dest_addr = strcat (dest_addr, src_addr)
Appends the string pointed to by src_addr to the string pointed
to by dest_addr. The first character of the source string is
copied to the location initially occupied by the trailing null
byte of the destination string. Thereafter, characters are copied
from the source to the destination up thru the null byte that
trails the source string.
*/
#if __i960_BIG_ENDIAN__
#define MSW g6
#define LSW g7
#else
#define LSW g6
#define MSW g7
#endif
.globl _strcpy, _strcat
.globl __strcpy, __strcat
.leafproc _strcpy, __strcpy
.leafproc _strcat, __strcat
.align 2
_strcat:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__strcat:
notand g0,3,g4 # extract word addr of start of dest
lda (g14),g13 # preserve return address
and g0,3,LSW # extract byte offset of dest
ld (g4),MSW # fetch word containing at least first byte
shlo 3,LSW,g14 # get shift count for making mask for first word
subi 1,0,LSW # mask initially all ones
#if __i960_BIG_ENDIAN__
shro g14,LSW,LSW # get mask for bytes needed from first word
lda 0xff000000,g5 # byte extraction mask
#else
shlo g14,LSW,LSW # get mask for bytes needed from first word
lda 0xff,g5 # byte extraction mask
#endif
notor MSW,LSW,MSW # set unneeded bytes to all ones
Lsearch_for_word_with_null:
scanbyte 0,MSW # check for null byte
lda 4(g4),g4 # post-increment dest word pointer
mov MSW,LSW # keep a copy of current word
ld (g4),MSW # fetch next word of dest
bno.t Lsearch_for_word_with_null # branch if null not found yet
and g5,LSW,g14 # extract byte
cmpo 0,g14 # branch if null is first byte of word
subo 4,g4,g4 # move dest word ptr back to word with null
notand g1,3,g3 # extract word addr of start of src
lda (g4),g2 # set dest byte ptr to 1st byte of word w/ null
be.f Lcase_14
Lsearch_for_null:
#if __i960_BIG_ENDIAN__
shro 8,g5,g5 # move mask down to next byte
#else
shlo 8,g5,g5 # move mask up to next byte
#endif
lda 1(g2),g2 # move dest byte ptr to next byte
and g5,LSW,g14 # extract byte
cmpobne.t 0,g14,Lsearch_for_null # branch if null is not yet found
lda 0xff,g5 # byte extraction mask
b Lcase_235.a
_strcpy:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__strcpy:
notand g0,3,g4 # extract word addr of start of dest
lda (g14),g13 # preserve return address
cmpo g0,g4 # check alignment of dest
lda 0xff,g5 # load mask for byte extraction
notand g1,3,g3 # extract word addr of start of src
bne.f Lcase_235 # branch if dest is NOT word aligned
Lcase_14:
cmpo g3,g1 # check alignment of src
ld (g3),LSW # fetch word containing at least first byte
shlo 3,g1,g1 # compute shift count
lda 4(g3),g3 # advance src word addr
#if __i960_BIG_ENDIAN__
lda 0xff,g5 # byte extraction mask
#endif
bne.f Lcase_4 # branch if src is NOT word aligned
Lcase_1: # src and dest are word aligned
subo 4,g4,g4 # store is pre-incrementing; back up dest addr
Lcase_1_wloop: # word copying loop
scanbyte 0,LSW # check for null byte in src word
lda (LSW),g2 # keep a copy of the src word
addo 4,g4,g4 # pre-increment dest addr
ld (g3),LSW # pre-fetch next word of src
addo 4,g3,g3 # post-increment src addr
bo.f Lcase_1_cloop # branch if word contains null byte
st g2,(g4) # store word in dest string
b Lcase_1_wloop
Lcase_3_cloop:
Lcase_1_cloop: # character copying loop
#if __i960_BIG_ENDIAN__
rotate 8,g2,g2 # move next byte into position for extraction
and g5,g2,g14 # extract next char
#else
and g5,g2,g14 # extract next char
shro 8,g2,g2 # move next byte into position for extraction
#endif
cmpo 0,g14 # check for null byte
stob g14,(g4) # store the byte in dest
lda 1(g4),g4 # post-increment dest byte addr
bne.t Lcase_1_cloop # branch if null not reached
Lexit_code:
bx (g13) # g0 = addr of dest; g14 = 0
Lrett:
ret
Lcase_3: # src is word aligned; dest is not
addo 4,g4,g4 # move dest word ptr to first word boundary
mov LSW,MSW # make copy of first word of src
lda 0,g1 # initialize shift count to zero
Lcase_25:
Lcase_3_cloop_at_start: # character copying loop for start of dest str
#if __i960_BIG_ENDIAN__
rotate 8,MSW,MSW # move next byte into position for extraction
and g5,MSW,g14 # extract next char
#else
and g5,MSW,g14 # extract next char
shro 8,MSW,MSW # move next byte into position for extraction
#endif
cmpo 0,g14 # check for null byte
stob g14,(g2) # store the byte in dest
lda 1(g2),g2 # post-increment dest ptr
be.f Lexit_code # branch if null byte reached
cmpo g2,g4 # have we reached word boundary in dest?
lda 8(g1),g1 # augment the shift counter
bne.t Lcase_3_cloop_at_start
Lcase_4:
ld (g3),MSW # fetch msw of operand for double shift
#if __i960_BIG_ENDIAN__
subo g1,0,g1 # Adjust shift count for big endian.
#endif
Lcase_3_wloop:
eshro g1,g6,g2 # extract 4 bytes of src
lda 4(g3),g3 # post-increment src word addr
scanbyte 0,g2 # check for null byte
lda (MSW),LSW # move msw to lsw
ld (g3),MSW # pre-fetch msw of operand for double shift
bo.f Lcase_3_cloop # branch if word contains null byte
st g2,(g4) # store 4 bytes to dest
addo 4,g4,g4 # post-increment dest ptr
b Lcase_3_wloop
Lcase_235:
lda (g0),g2 # copy dest ptr
Lcase_235.a:
cmpo g3,g1 # check alignment of src
ld (g3),LSW # fetch word containing at least first byte
and 3,g1,g14 # compute shift count
lda 4(g3),g3 # advance src word addr
shlo 3,g14,g1
be.t Lcase_3 # branch if dest is word aligned
or g4,g14,g14 # is src earlier in word, later, or sync w/ dst
ld (g3),MSW # pre-fetch second half
cmpo g2,g14 # < indicates first word of dest has more bytes
lda 4(g4),g4 # move dest word addr to first word boundary
/* than first word of source. */
#if __i960_BIG_ENDIAN__
subo g1,0,g14 # Adjust shift count for big endian.
eshro g14,g6,g14 # extract four bytes
bge.f 1f
#else
eshro g1,g6,g14 # extract four bytes
bg.f 1f
#endif
mov MSW,LSW
lda 4(g3),g3 # move src word addr to second word boundary
1:
mov g14,MSW
b Lcase_25
/* end of strcpy */
|
4ms/metamodule-plugin-sdk
| 5,074
|
plugin-libc/newlib/libc/machine/i960/strlen_ca.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "strle_ca.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1993 Intel Corp., all rights reserved
*/
/*
procedure strlen (optimized assembler version for the CA)
src_addr = strlen (src_addr)
return the number of bytes that precede the null byte in the
string pointed to by src_addr.
Undefined behavior will occur if the end of the source string (i.e.
the terminating null byte) is in the last four words of the program's
allocated memory space. This is so because, in several cases, strlen
will fetch ahead several words. Disallowing the fetch ahead would
impose a severe performance penalty.
This program handles two cases:
1) the argument starts on a word boundary
2) the argument doesn't start on a word boundary
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine. The registers are used as follows:
g0 original src ptr; upon return it is the byte count.
g1
g2 src ptr
g3 mask
g4 even word of the source string
g5 odd word of the source string
g6 copy of even word, shift count
g7 copy of odd word
g13 return address
g14 byte extracted.
*/
.globl _strlen
.globl __strlen
.leafproc _strlen, __strlen
.align 2
_strlen:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__strlen:
notand g0,3,g2 # extract word addr of start of src
lda (g14),g13 # preserve return address
and g0,3,g7 # extract byte offset of src
ld (g2),g5 # fetch word containing at least first byte
shlo 3,g7,g7 # get shift count for making mask for first word
lda 4(g2),g2 # post-increment src word pointer
subi 1,0,g3 # mask initially all ones
chkbit 2,g2 # are we on an even word boundary or an odd one?
#if __i960_BIG_ENDIAN__
shro g7,g3,g3 # get mask for bytes needed from first word
notor g5,g3,g7 # set unneeded bytes to all ones
lda 0xff000000,g3 # byte extraction mask
#else
shlo g7,g3,g3 # get mask for bytes needed from first word
notor g5,g3,g7 # set unneeded bytes to all ones
lda 0xff,g3 # byte extraction mask
#endif
bno.f Lodd_word # branch if first word is odd
mov g7,g4 # move first word to copy thereof
ld (g2),g5 # load odd word
lda 4(g2),g2 # post-increment src word pointer
Leven_word:
scanbyte 0,g4 # check for null byte
movl g4,g6 # copy both words
Lodd_word: # trickery! if we branch here, following branch
/* instruction will fall thru, as we want, */
/* effecting the load of g4 and g5 only. */
ldl (g2),g4 # fetch next pair of word of src
bo.f Lsearch_for_null # branch if null found
scanbyte 0,g7 # check for null byte
lda 8(g2),g2 # post-increment src word pointer
bno.t Leven_word # branch if null not found yet
subo 4,g2,g2 # back up the byte pointer
lda (g7),g6 # move odd word to search word
Lsearch_for_null:
subo 9,g2,g2 # back up the byte pointer
Lsearch_for_null.a:
and g6,g3,g14 # extract byte
cmpo 0,g14 # is it null?
lda 1(g2),g2 # bump src byte ptr
#if __i960_BIG_ENDIAN__
shlo 8,g6,g6 # shift word to position next byte
#else
shro 8,g6,g6 # shift word to position next byte
#endif
bne.t Lsearch_for_null.a
Lexit_code:
subo g0,g2,g0 # calculate string length
bx (g13) # g0 = addr of src; g14 = 0
Lrett:
ret
/* end of strlen */
|
4ms/metamodule-plugin-sdk
| 2,480
|
plugin-libc/newlib/libc/machine/i960/strdup.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "strdup.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1989,1993 Intel Corp., all rights reserved
*/
/*
procedure strdup (optimized assembler version: 80960K series, 80960CA)
dest_addr = strdup (src_addr)
Allocate memory and copy thereto the string pointed to by src_addr.
Return the address of the copy, or null if unable to perform the
operation.
*/
.text
.align 2
.globl _strdup
_strdup:
mov g0,r3 # Keep a copy of the original string addr
callj _strlen # Determine how much to allocate
addo 1,g0,g0 # Add one byte for the null byte at end
callj _malloc # Allocate the storage
cmpo 0,g0
mov r3,g1 # Original string addr is now src for copy
bne.t _strcpy # Jump if allocation was successful
ret # Return the null ptr otherwise
/* end of strdup */
|
4ms/metamodule-plugin-sdk
| 4,835
|
plugin-libc/newlib/libc/machine/i960/memccpy.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "memccpy.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1989,1993 Intel Corp., all rights reserved
*/
/*
procedure memccpy (optimized assembler version for the 80960K series)
dest_addr = memccpy (dest_addr, src_addr, char, len)
copy len bytes pointed to by src_addr to the space pointed to by
dest_addr, stopping if char is copied. If char is copied,
return address of byte after char in dest string; else null.
Undefined behavior will occur if the end of the source array is in
the last two words of the program's allocated memory space. This
is so because the routine fetches ahead. Disallowing the fetch
ahead would impose a severe performance penalty.
Undefined behavior will also occur if the source and destination
strings overlap.
Strategy:
Fetch the source array by words and store them by words to the
destination array, until there are fewer than three bytes left
to copy. Then, using the last word of the source (the one that
contains the remaining 0, 1, 2, or 3 bytes to be copied), store
a byte at a time until Ldone.
Tactics:
1) Do NOT try to fetch and store the words in a word aligned manner
because, in my judgement, the performance degradation experienced due
to non-aligned accesses does NOT outweigh the time and complexity added
by the preamble and convoluted body that would be necessary to assure
alignment. This is supported by the intuition that most source and
destination arrays (even more true of most big source arrays) will
be word aligned to begin with.
2) Rather than decrementing len to zero,
I calculate the address of the byte after the last byte of the
destination array, and quit when the destination byte pointer passes
that.
*/
.globl _memccpy
.leafproc _memccpy, __memccpy
.align 2
_memccpy:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__memccpy:
mov g14, g13 # preserve return address
cmpibge 0,g3,Lexit_char_not_found
addo g3,g1,g3 # compute beyond end of src
ld (g1), g7 # fetch first word of source
lda 0xff,g5 # mask for char
and g5,g2,g2 # extract only char
shlo 8,g2,g6
or g2,g6,g6
shlo 16,g6,g4
or g6,g4,g6 # word of char
b Lwloop_b
Lwloop_a:
ld (g1), g7 # fetch ahead next word of source
st g4, (g0) # store word to dest
addo 4, g0, g0 # post-increment dest pointer
Lwloop_b: # word copying loop
addo 4, g1, g1 # pre-increment src pointer
cmpo g3, g1 # is len <= 3 ?
mov g7, g4 # keep a copy of the current word
bl Lcloop_setup # quit word loop if less than 4 bytes
scanbyte g6, g7 # check for char
bno Lwloop_a # continue word loop if char not found.
Lcloop_setup:
subo 4, g1, g1 # back down src pointer
cmpobe g1, g3, Lexit_char_not_found
Lcloop_a: # character copying loop (len < 3)
and g5,g4,g7 # check the byte against char
cmpo g7,g2
stob g7,(g0) # store the byte
addo 1, g0, g0
be Lexit_char_found
addo 1,g1,g1
cmpo g1,g3
shro 8,g4,g4 # position next byte
bne Lcloop_a
Lexit_char_not_found:
mov 0, g0
Lexit_char_found:
lda 0,g14
bx (g13) # g0 = dest array address; g14 = 0
Lrett:
ret
/* end of memccpy */
|
4ms/metamodule-plugin-sdk
| 5,373
|
plugin-libc/newlib/libc/machine/i960/memchr_ca.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "memchr_ca.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1993 Intel Corp., all rights reserved
*/
/*
procedure memchr (optimized assembler version for the CA)
src_addr = memchr (src_addr, char, max_bytes)
searching from src_addr for max_bytes bytes, return a pointer to the
first byte that contains the indicated byte in the source string.
Return null if the byte is not found.
Undefined behavior will occur if the end of the source string (i.e.
the terminating null byte) is in the last two words of the program's
allocated memory space. This is so because, in several cases, memchr
will fetch ahead. Disallowing the fetch ahead would impose a severe
performance penalty.
This program handles two cases:
1) the argument starts on a word boundary
2) the argument doesn't start on a word boundary
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine. The registers are used as follows:
g0 src ptr; upon return it is a pointer to the matching byte, or null
g1 char to seek
g2 maximum number of bytes to check
g3 char to seek, broadcast to all four bytes
g4 word of the source string
g5 copy of the word
g6 mask to avoid unimportant bytes in first word
g7 byte extraction mask
g13 return address
g14
*/
.globl _memchr
.globl __memchr
.leafproc _memchr, __memchr
.align 2
_memchr:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__memchr:
mov g14,g13 # preserve return address
lda 0xff,g7 # byte extraction mask
and g1,g7,g1 # make char an 8-bit ordinal
lda 0,g14 # conform to register linkage standard
cmpibge.f 0,g2,Lnot_found # do nothing if max_bytes <= 0
addo g0,g2,g2 # compute ending address from start and len
and g0,3,g6 # extract byte offset of src
notand g0,3,g0 # extract word addr of start of src
shlo 8,g1,g3 # broadcast the char to four bytes
ld (g0),g4 # fetch word containing at least first byte
or g1,g3,g3
shlo 16,g3,g5
cmpo g1,g7 # is char being sought 0xff?
or g5,g3,g3
shlo 3,g6,g6 # get shift count for making mask for first word
subi 1,0,g5 # mask initially all ones
#if __i960_BIG_ENDIAN__
shro g6,g5,g5 # get mask for bytes needed from first word
#else
shlo g6,g5,g5 # get mask for bytes needed from first word
#endif
notor g4,g5,g4 # set unneeded bytes to all ones
be.f Lsearch_for_0xff # branch if seeking 0xff
Lsearch_for_word_with_char:
scanbyte g3,g4 # check for byte with char
lda 4(g0),g0 # pre-increment src word pointer
mov g4,g5 # keep a copy of word
ld (g0),g4 # fetch next word of src
bo.f Lsearch_for_char # branch if null found
cmpoble.t g0,g2,Lsearch_for_word_with_char # branch if not null
Lnot_found:
mov 0,g0 # char not found. Return null
Lexit_code:
bx (g13) # g0 = addr of char in src (or null); g14 = 0
Lrett:
ret
Lsearch_for_char:
subo 4,g0,g0 # back up the byte pointer
Lsearch_for_char.a:
cmpobe.f g0,g2,Lnot_found # quit if max_bytes exhausted
#if __i960_BIG_ENDIAN__
rotate 8,g5,g5 # shift word to position next byte
#endif
and g5,g7,g6 # extract byte
cmpo g1,g6 # is it char?
lda 1(g0),g0 # bump src byte ptr
#if ! __i960_BIG_ENDIAN__
shro 8,g5,g5 # shift word to position next byte
#endif
bne.t Lsearch_for_char.a
subo 1,g0,g0 # back up the byte pointer
b Lexit_code
Lsearch_for_0xff:
lda 0xf0f0f0f0,g6 # make first comparison mask for char=-1 case.
or g6,g5,g6
and g4,g6,g4 # make unimportant bytes of first word 0x0f
b Lsearch_for_word_with_char
/* end of memchr */
|
4ms/metamodule-plugin-sdk
| 4,578
|
plugin-libc/newlib/libc/machine/i960/strncmp.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "strncmp.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1993 Intel Corp., all rights reserved
*/
/*
procedure strncmp (optimized assembler version for the 80960K Series)
result = strncmp (src1_addr, src2_addr, max_bytes)
compare the null terminated string pointed to by src1_addr to
the string pointed to by src2_addr. Return 0 iff the strings
are equal, -1 if src1_addr is lexicographically less than src2_addr,
and 1 if it is lexicographically greater. Do not compare more than
max_bytes bytes.
Undefined behavior will occur if the end of either source string
(i.e. the terminating null byte) is in the last two words of the
program's allocated memory space. This is so because strncmp
will fetch ahead. Disallowing the fetch ahead would impose
a severe performance penalty.
Strategy:
Fetch and compare the strings by words and go to a character
comparison loop as soon as a pair of words differ. If the
words are equal up through either the exhaustion of max_bytes
or the presence of the null byte, return 0 (equality). Otherwise,
the character comparator will return -1 or 1 for inequality, or
0 if the differing byte is after the null byte or after the
exhaustion of max_bytes.
Tactics:
1) Do NOT try to fetch the words in a word aligned manner because,
in my judgement, the performance degradation experienced due to
non-aligned accesses does NOT outweigh the time and complexity added
by the preamble and convoluted body that would be necessary to assure
alignment.
*/
.globl _strncmp
.globl __strncmp
.leafproc _strncmp,__strncmp
.align 2
_strncmp:
#ifndef __PIC
lda .Lrett,g14
#else
lda .Lrett-(.+8)(ip),g14
#endif
__strncmp:
mov g14,g13
ldconst 0,g14
cmpibge 0,g2,Lequal_exit # Lexit early if max_bytes <= 0
addo g2,g0,g2
.Lwloop:
cmpo g0,g2 # are max_bytes exhausted?
ld (g0), g5 # fetch word of source_1
bge Lequal_exit # Lexit (equality) if max_bytes exhausted
ld (g1), g3 # fetch word of source_2
addo 4,g0,g0 # post-increment source_1 ptr
scanbyte 0,g5 # is a null byte present?
addo 4,g1,g1 # post-increment source_1 ptr
be .Lcloop.a # perform char comparator if null byte found
cmpobe g5,g3,.Lwloop # perform char comparator if words are unequal
.Lcloop.a: subo 4,g0,g0 # adjust max_byte counter
ldconst 0xff,g4 # byte extraction mask
.Lcloop: and g4,g5,g7 # compare individual bytes
and g4,g3,g6
cmpobne g7,g6,.diff # if different, return -1 or 1
cmpo 0,g6 # they are equal. are they null?
shlo 8,g4,g4 # position mask to extract next byte
be Lequal_exit # if they are null, Lexit (equality)
addo 1,g0,g0 # is max_bytes exhausted?
cmpobl g0,g2,.Lcloop # if not, loop. if so, Lexit (equality)
Lequal_exit:
mov 0,g0
bx (g13)
.Lrett:
ret
.diff: bl .neg
mov 1,g0
bx (g13)
.neg: subi 1,0,g0
.Lexit:
bx (g13)
/* end of strncmp */
|
4ms/metamodule-plugin-sdk
| 3,969
|
plugin-libc/newlib/libc/machine/i960/memset.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "memset.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1989,1993 Intel Corp., all rights reserved
*/
/*
procedure memset (optimized assembler version: 80960K series, 80960CA)
dest_addr = memset (dest_addr, char, len)
Fill len bytes pointed to by dest_addr with the value of char.
Return the original address of dest_addr.
This program avoids performing unaligned accesses. It stores
from zero to seven bytes, and then stores aligned longwords,
and then stores from zero to seven bytes, as necessary to
store len bytes starting at dest_addr.
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine.
*/
.globl _memset
.globl __memset
.leafproc _memset, __memset
.align 2
_memset:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__memset:
cmpo 7,g2 # are there fewer than seven characters to move?
lda (g14),g13 # save return address
notand g0,7,g3 # test for non-aligned dest_ptr
lda 0,g14 # conform to register conventions
shlo 24,g1,g4 # prepare word of char
lda (g0),g6 # preserve dest_ptr for return
shro 8,g4,g5
bge.f Lcloop_setup
cmpo g3,g0 # is dest longword aligned
lda 7(g3),g3 # bump dest_ptr to next longword boundary
or g4,g5,g4
be.t Lwloop_setup
Lbgn_cloop:
cmpo g6,g3 # Have we reached longword boundary?
stob g1,(g6) # store one byte of char
subo 1,g2,g2 # decrement len
lda 1(g6),g6 # increment dest_ptr
bne.t Lbgn_cloop # loop if more bytes to store before longword
cmpobge.f 7,g2,Lcloop
Lwloop_setup:
shro 16,g4,g5
or g4,g5,g4
mov g4,g5 # now have a longword of char
Lwloop:
cmpo 15,g2 # Do we have to store more longwords?
stl g4,(g6) # Store longword of char
subo 8,g2,g2 # Decrement len
lda 8(g6),g6 # Increment dest_ptr
bl.t Lwloop # loop if more longwords to store
Lcloop_setup:
cmpobge.t 0,g2,Lexit
Lcloop:
cmpo 1,g2 # Is len exhausted?
stob g1,(g6) # Store byte
subo 1,g2,g2 # Decrement len
lda 1(g6),g6 # Increment dest_ptr
bne.t Lcloop # loop if more bytes to store
Lexit:
bx (g13)
Lrett:
ret
/* end of memset */
|
4ms/metamodule-plugin-sdk
| 10,423
|
plugin-libc/newlib/libc/machine/i960/strncat_ca.S
|
/*******************************************************************************
*
* Copyright (c) 1993 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and distribute this
* software and its documentation. Intel grants this permission provided
* that the above copyright notice appears in all copies and that both the
* copyright notice and this permission notice appear in supporting
* documentation. In addition, Intel grants this permission provided that
* you prominently mark as "not part of the original" any modifications
* made to this software or documentation, and that the name of Intel
* Corporation not be used in advertising or publicity pertaining to
* distribution of the software or the documentation without specific,
* written prior permission.
*
* Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
* IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
* representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
.file "sncat_ca.s"
#ifdef __PIC
.pic
#endif
#ifdef __PID
.pid
#endif
/*
* (c) copyright 1988,1993 Intel Corp., all rights reserved
*/
/*
procedure strncat (optimized assembler version for the CA)
dest_addr = strncat (dest_addr, src_addr, max_bytes)
append the null terminated string pointed to by src_addr to the null
terminated string pointed to by dest_addr. Return the original
dest_addr. If the source string is longer than max_bytes, then
append only max_bytes bytes, and tack on a null byte on the end
This routine will fail if the source and destination string
overlap (in particular, if the end of the source is overlapped
by the beginning of the destination). The behavior is undefined.
This is acceptable according to the draft C standard.
Undefined behavior will also occur if the end of the source string
(i.e. the terminating null byte) is in the last word of the program's
allocated memory space. This is so because, in several cases, strncat
will fetch ahead one word. Disallowing the fetch ahead would impose
a severe performance penalty.
This program handles five cases:
1) both arguments start on a word boundary
2) neither are word aligned, but they are offset by the same amount
3) source is word aligned, destination is not
4) destination is word aligned, source is not
5) neither is word aligned, and they are offset by differing amounts
At the time of this writing, only g0 thru g7 and g13 are available
for use in this leafproc; other registers would have to be saved and
restored. These nine registers, plus tricky use of g14 are sufficient
to implement the routine. The registers are used as follows:
g0 original dest ptr; not modified, so that it may be returned.
g1 src ptr; shift count
g2 max_bytes
g3 src ptr (word aligned)
g4 dest ptr (word aligned)
g5 0xff -- byte extraction mask
Little endian:
g6 lsw of double word for extraction of 4 bytes
g7 msw of double word for extraction of 4 bytes
Big endian:
g6 msw of double word for extraction of 4 bytes
g7 lsw of double word for extraction of 4 bytes
g13 return address
g14 byte extracted.
*/
#if __i960_BIG_ENDIAN__
#define MSW g6
#define LSW g7
#else
#define LSW g6
#define MSW g7
#endif
.globl _strncat
.globl __strncat
.leafproc _strncat, __strncat
.align 2
_strncat:
#ifndef __PIC
lda Lrett,g14
#else
lda Lrett-(.+8)(ip),g14
#endif
__strncat:
notand g0,3,g4 # extract word addr of start of dest
lda (g14),g13 # preserve return address
cmpibge.f 0,g2,Lexit_code # Lexit if number of bytes to move is <= zero.
and g0,3,LSW # extract byte offset of dest
ld (g4),MSW # fetch word containing at least first byte
shlo 3,LSW,g14 # get shift count for making mask for first word
subi 1,0,LSW # mask initially all ones
#if __i960_BIG_ENDIAN__
shro g14,LSW,LSW # get mask for bytes needed from first word
#else
shlo g14,LSW,LSW # get mask for bytes needed from first word
#endif
notor MSW,LSW,MSW # set unneeded bytes to all ones
lda 0xff,g5 # byte extraction mask
Lsearch_for_word_with_null:
scanbyte 0,MSW # check for null byte
lda 4(g4),g4 # post-increment dest word pointer
mov MSW,LSW # keep a copy of current word
ld (g4),MSW # fetch next word of dest
bno.t Lsearch_for_word_with_null # branch if null not found yet
#if __i960_BIG_ENDIAN__
shro 24,LSW,g14 # extract byte
#else
and g5,LSW,g14 # extract byte
#endif
cmpo 0,g14 # branch if null is first byte of word
subo 4,g4,g4 # move dest word ptr to word with null
notand g1,3,g3 # extract word addr of start of src
bne.t Lsearch_for_null
Lcase_14:
cmpo g1,g3 # check alignment of source
ld (g3),LSW # fetch first word of source
shlo 3,g1,g14 # compute shift count
lda 4(g3),g3 # post-increment src addr
bne.f Lcase_4 # branch if source is unaligned
Lcase_1:
Lcase_1_wloop: # word copying loop
cmpi g2,4 # check for fewer than four bytes to move
lda (LSW),g1 # keep a copy of the src word
bl.f Lcase_1_cloop # branch if fewer than four bytes to copy
scanbyte 0,g1 # check for null byte in src word
ld (g3),LSW # pre-fetch next word of src
addo 4,g3,g3 # post-increment src addr
bo.f Lcase_1_cloop # branch if word contains null byte
subi 4,g2,g2 # decrease max_byte count by the 4 bytes moved
st g1,(g4) # store word in dest string
addo 4,g4,g4 # post-increment dest addr
b Lcase_1_wloop
Lcase_3_cloop:
Lcase_1_cloop: # character copying loop (max_bytes <= 3)
cmpdeci 0,g2,g2 # is max_bytes exhausted?
#if __i960_BIG_ENDIAN__
rotate 8,g1,g1 # move next byte into position for extraction
#endif
and g5,g1,g14 # extract next char
be.f Lstore_null # if max_bytes is exhausted, store null and quit
cmpo 0,g14 # check for null byte
stob g14,(g4) # store the byte in dest
#if ! __i960_BIG_ENDIAN__
shro 8,g1,g1 # move next byte into position for extraction
#endif
lda 1(g4),g4 # post-increment dest byte addr
bne.t Lcase_1_cloop # branch if null not reached
bx (g13) # Lexit (g14 == 0)
Lstore_null:
mov 0,g14 # store null, and set g14 to zero
stob g14,(g4)
bx (g13)
Lsearch_for_null:
#if __i960_BIG_ENDIAN__
shlo 8,LSW,LSW # check next byte
shro 24,LSW,g14
#else
shlo 8,g5,g5 # move mask up to next byte
and g5,LSW,g14 # extract byte
#endif
lda 1(g4),g4 # move dest byte ptr to next byte
cmpobne.t 0,g14,Lsearch_for_null # branch if null is not yet found
Lcase_235:
cmpo g1,g3 # check alignment of src
ld (g3),LSW # pre-fetch word with start of src
and 3,g1,g1 # compute shift count
lda 0xff,g5 # load mask for byte extraction
shlo 3,g1,g14
lda 4(g3),g3 # post-increment src word counter
be.t Lcase_3 # branch if src is word aligned
and g4,3,MSW # extract byte offset for dest string
cmpo MSW,g1 # < indicates first word of dest has more bytes
/* than first word of source. */
ld (g3),MSW # fetch second word of src
#if __i960_BIG_ENDIAN__
subo g14,0,g14 # adjust shift count for big endian
#endif
eshro g14,g6,g5 # extract four bytes
#if __i960_BIG_ENDIAN__
bge.f 1f
#else
bg.f 1f
#endif
mov MSW,LSW
lda 4(g3),g3 # move src word addr to second word boundary
1:
mov g5,MSW
lda 0xff,g5
b Lcase_25
Lcase_3: # src is word aligned; dest is not
mov LSW,MSW # make copy of first word of src
lda 32,g14 # initialize shift count to zero (mod 32)
Lcase_25:
Lcase_3_cloop_at_start: # character copying loop for start of dest str
cmpdeci 0,g2,g2 # is max_bytes exhausted?
#if __i960_BIG_ENDIAN__
shro 24,MSW,g5 # extract next char
#else
and g5,MSW,g5 # extract next char
#endif
be.f Lstore_null # Lexit if max_bytes is exhausted
cmpo 0,g5 # check for null byte
stob g5,(g4) # store the byte in dest
addo 1,g4,g4 # post-increment dest ptr
lda 0xff,g5 # re-initialize byte extraction mask
notand g4,3,g1 # extract word address
be.t Lexit_code # Lexit if null byte reached
cmpo g1,g4 # have we reached word boundary in dest yet?
#if __i960_BIG_ENDIAN__
lda -8(g14),g14 # augment the shift counter
rotate 8,MSW,MSW # move next byte into position for extraction
#else
lda 8(g14),g14 # augment the shift counter
shro 8,MSW,MSW # move next byte into position for extraction
#endif
bne.t Lcase_3_cloop_at_start # branch if reached word boundary?
#if __i960_BIG_ENDIAN__
cmpo 0,g14
ld (g3),MSW # fetch msw of operand for double shift
bne Lcase_3_wloop # branch if src is still unaligned.
Lcase_3_wloop2:
cmpi g2,4 # less than four bytes to move?
mov LSW,g1 # extract 4 bytes of src
lda 4(g3),g3 # post-increment src word addr
bl.f Lcase_3_cloop # branch if < four bytes left to move
scanbyte 0,g1 # check for null byte
mov MSW,LSW # move msw to lsw
ld (g3),MSW # pre-fetch msw of operand for double shift
bo.f Lcase_3_cloop # branch if word contains null byte
subi 4,g2,g2 # decrease max_byte count by the 4 bytes moved
st g1,(g4) # store 4 bytes to dest
addo 4,g4,g4 # post-increment dest ptr
b Lcase_3_wloop2
Lcase_4:
subo g14,0,g14 # adjust shift count for big endian
#else
Lcase_4:
#endif
ld (g3),MSW # fetch msw of operand for double shift
Lcase_3_wloop:
cmpi g2,4 # less than four bytes to move?
eshro g14,g6,g1 # extract 4 bytes of src
lda 4(g3),g3 # post-increment src word addr
bl.f Lcase_3_cloop # branch if < four bytes left to move
scanbyte 0,g1 # check for null byte
mov MSW,LSW # move msw to lsw
ld (g3),MSW # pre-fetch msw of operand for double shift
bo.f Lcase_3_cloop # branch if word contains null byte
subi 4,g2,g2 # decrease max_byte count by the 4 bytes moved
st g1,(g4) # store 4 bytes to dest
addo 4,g4,g4 # post-increment dest ptr
b Lcase_3_wloop
Lexit_code:
mov 0,g14 # conform to register conventions
bx (g13) # g0 = addr of dest; g14 = 0
Lrett:
ret
/* end of strncat */
|
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